1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "integrate.h"
54 #include "langhooks.h"
55 #include "cfglayout.h"
56 #include "sched-int.h"
59 #include "diagnostic.h"
60 #include "target-globals.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type {
185 /* Macros to create an enumeration identifier for a function prototype. */
186 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
187 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
188 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
189 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
191 /* Classifies the prototype of a built-in function. */
192 enum mips_function_type {
193 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
194 #include "config/mips/mips-ftypes.def"
195 #undef DEF_MIPS_FTYPE
199 /* Specifies how a built-in function should be converted into rtl. */
200 enum mips_builtin_type {
201 /* The function corresponds directly to an .md pattern. The return
202 value is mapped to operand 0 and the arguments are mapped to
203 operands 1 and above. */
206 /* The function corresponds directly to an .md pattern. There is no return
207 value and the arguments are mapped to operands 0 and above. */
208 MIPS_BUILTIN_DIRECT_NO_TARGET,
210 /* The function corresponds to a comparison instruction followed by
211 a mips_cond_move_tf_ps pattern. The first two arguments are the
212 values to compare and the second two arguments are the vector
213 operands for the movt.ps or movf.ps instruction (in assembly order). */
217 /* The function corresponds to a V2SF comparison instruction. Operand 0
218 of this instruction is the result of the comparison, which has mode
219 CCV2 or CCV4. The function arguments are mapped to operands 1 and
220 above. The function's return value is an SImode boolean that is
221 true under the following conditions:
223 MIPS_BUILTIN_CMP_ANY: one of the registers is true
224 MIPS_BUILTIN_CMP_ALL: all of the registers are true
225 MIPS_BUILTIN_CMP_LOWER: the first register is true
226 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
227 MIPS_BUILTIN_CMP_ANY,
228 MIPS_BUILTIN_CMP_ALL,
229 MIPS_BUILTIN_CMP_UPPER,
230 MIPS_BUILTIN_CMP_LOWER,
232 /* As above, but the instruction only sets a single $fcc register. */
233 MIPS_BUILTIN_CMP_SINGLE,
235 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
236 MIPS_BUILTIN_BPOSGE32
239 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
240 #define MIPS_FP_CONDITIONS(MACRO) \
258 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
259 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
260 enum mips_fp_condition {
261 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
264 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
265 #define STRINGIFY(X) #X
266 static const char *const mips_fp_conditions[] = {
267 MIPS_FP_CONDITIONS (STRINGIFY)
270 /* Information about a function's frame layout. */
271 struct GTY(()) mips_frame_info {
272 /* The size of the frame in bytes. */
273 HOST_WIDE_INT total_size;
275 /* The number of bytes allocated to variables. */
276 HOST_WIDE_INT var_size;
278 /* The number of bytes allocated to outgoing function arguments. */
279 HOST_WIDE_INT args_size;
281 /* The number of bytes allocated to the .cprestore slot, or 0 if there
283 HOST_WIDE_INT cprestore_size;
285 /* Bit X is set if the function saves or restores GPR X. */
288 /* Likewise FPR X. */
291 /* Likewise doubleword accumulator X ($acX). */
292 unsigned int acc_mask;
294 /* The number of GPRs, FPRs, doubleword accumulators and COP0
298 unsigned int num_acc;
299 unsigned int num_cop0_regs;
301 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
302 save slots from the top of the frame, or zero if no such slots are
304 HOST_WIDE_INT gp_save_offset;
305 HOST_WIDE_INT fp_save_offset;
306 HOST_WIDE_INT acc_save_offset;
307 HOST_WIDE_INT cop0_save_offset;
309 /* Likewise, but giving offsets from the bottom of the frame. */
310 HOST_WIDE_INT gp_sp_offset;
311 HOST_WIDE_INT fp_sp_offset;
312 HOST_WIDE_INT acc_sp_offset;
313 HOST_WIDE_INT cop0_sp_offset;
315 /* Similar, but the value passed to _mcount. */
316 HOST_WIDE_INT ra_fp_offset;
318 /* The offset of arg_pointer_rtx from the bottom of the frame. */
319 HOST_WIDE_INT arg_pointer_offset;
321 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
322 HOST_WIDE_INT hard_frame_pointer_offset;
325 struct GTY(()) machine_function {
326 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
327 rtx mips16_gp_pseudo_rtx;
329 /* The number of extra stack bytes taken up by register varargs.
330 This area is allocated by the callee at the very top of the frame. */
333 /* The current frame information, calculated by mips_compute_frame_info. */
334 struct mips_frame_info frame;
336 /* The register to use as the function's global pointer, or INVALID_REGNUM
337 if the function doesn't need one. */
338 unsigned int global_pointer;
340 /* How many instructions it takes to load a label into $AT, or 0 if
341 this property hasn't yet been calculated. */
342 unsigned int load_label_num_insns;
344 /* True if mips_adjust_insn_length should ignore an instruction's
346 bool ignore_hazard_length_p;
348 /* True if the whole function is suitable for .set noreorder and
350 bool all_noreorder_p;
352 /* True if the function has "inflexible" and "flexible" references
353 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
354 and mips_cfun_has_flexible_gp_ref_p for details. */
355 bool has_inflexible_gp_insn_p;
356 bool has_flexible_gp_insn_p;
358 /* True if the function's prologue must load the global pointer
359 value into pic_offset_table_rtx and store the same value in
360 the function's cprestore slot (if any). Even if this value
361 is currently false, we may decide to set it to true later;
362 see mips_must_initialize_gp_p () for details. */
363 bool must_initialize_gp_p;
365 /* True if the current function must restore $gp after any potential
366 clobber. This value is only meaningful during the first post-epilogue
367 split_insns pass; see mips_must_initialize_gp_p () for details. */
368 bool must_restore_gp_when_clobbered_p;
370 /* True if this is an interrupt handler. */
371 bool interrupt_handler_p;
373 /* True if this is an interrupt handler that uses shadow registers. */
374 bool use_shadow_register_set_p;
376 /* True if this is an interrupt handler that should keep interrupts
378 bool keep_interrupts_masked_p;
380 /* True if this is an interrupt handler that should use DERET
382 bool use_debug_exception_return_p;
385 /* Information about a single argument. */
386 struct mips_arg_info {
387 /* True if the argument is passed in a floating-point register, or
388 would have been if we hadn't run out of registers. */
391 /* The number of words passed in registers, rounded up. */
392 unsigned int reg_words;
394 /* For EABI, the offset of the first register from GP_ARG_FIRST or
395 FP_ARG_FIRST. For other ABIs, the offset of the first register from
396 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
397 comment for details).
399 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
401 unsigned int reg_offset;
403 /* The number of words that must be passed on the stack, rounded up. */
404 unsigned int stack_words;
406 /* The offset from the start of the stack overflow area of the argument's
407 first stack word. Only meaningful when STACK_WORDS is nonzero. */
408 unsigned int stack_offset;
411 /* Information about an address described by mips_address_type.
417 REG is the base register and OFFSET is the constant offset.
420 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
421 is the type of symbol it references.
424 SYMBOL_TYPE is the type of symbol that the address references. */
425 struct mips_address_info {
426 enum mips_address_type type;
429 enum mips_symbol_type symbol_type;
432 /* One stage in a constant building sequence. These sequences have
436 A = A CODE[1] VALUE[1]
437 A = A CODE[2] VALUE[2]
440 where A is an accumulator, each CODE[i] is a binary rtl operation
441 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
442 struct mips_integer_op {
444 unsigned HOST_WIDE_INT value;
447 /* The largest number of operations needed to load an integer constant.
448 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
449 When the lowest bit is clear, we can try, but reject a sequence with
450 an extra SLL at the end. */
451 #define MIPS_MAX_INTEGER_OPS 7
453 /* Information about a MIPS16e SAVE or RESTORE instruction. */
454 struct mips16e_save_restore_info {
455 /* The number of argument registers saved by a SAVE instruction.
456 0 for RESTORE instructions. */
459 /* Bit X is set if the instruction saves or restores GPR X. */
462 /* The total number of bytes to allocate. */
466 /* Costs of various operations on the different architectures. */
468 struct mips_rtx_cost_data
470 unsigned short fp_add;
471 unsigned short fp_mult_sf;
472 unsigned short fp_mult_df;
473 unsigned short fp_div_sf;
474 unsigned short fp_div_df;
475 unsigned short int_mult_si;
476 unsigned short int_mult_di;
477 unsigned short int_div_si;
478 unsigned short int_div_di;
479 unsigned short branch_cost;
480 unsigned short memory_latency;
483 /* Global variables for machine-dependent things. */
485 /* The -G setting, or the configuration's default small-data limit if
486 no -G option is given. */
487 static unsigned int mips_small_data_threshold;
489 /* The number of file directives written by mips_output_filename. */
490 int num_source_filenames;
492 /* The name that appeared in the last .file directive written by
493 mips_output_filename, or "" if mips_output_filename hasn't
494 written anything yet. */
495 const char *current_function_file = "";
497 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
500 /* Arrays that map GCC register numbers to debugger register numbers. */
501 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
502 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
504 /* Information about the current function's epilogue, used only while
507 /* A list of queued REG_CFA_RESTORE notes. */
510 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
512 HOST_WIDE_INT cfa_offset;
514 /* The offset of the CFA from the stack pointer while restoring
516 HOST_WIDE_INT cfa_restore_sp_offset;
519 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
520 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
521 struct mips_asm_switch mips_nomacro = { "macro", 0 };
522 struct mips_asm_switch mips_noat = { "at", 0 };
524 /* True if we're writing out a branch-likely instruction rather than a
526 static bool mips_branch_likely;
528 /* The current instruction-set architecture. */
529 enum processor mips_arch;
530 const struct mips_cpu_info *mips_arch_info;
532 /* The processor that we should tune the code for. */
533 enum processor mips_tune;
534 const struct mips_cpu_info *mips_tune_info;
536 /* The ISA level associated with mips_arch. */
539 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
540 static const struct mips_cpu_info *mips_isa_option_info;
542 /* Which cost information to use. */
543 static const struct mips_rtx_cost_data *mips_cost;
545 /* The ambient target flags, excluding MASK_MIPS16. */
546 static int mips_base_target_flags;
548 /* True if MIPS16 is the default mode. */
549 bool mips_base_mips16;
551 /* The ambient values of other global variables. */
552 static int mips_base_schedule_insns; /* flag_schedule_insns */
553 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
554 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
555 static int mips_base_align_loops; /* align_loops */
556 static int mips_base_align_jumps; /* align_jumps */
557 static int mips_base_align_functions; /* align_functions */
559 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
560 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
562 /* Index C is true if character C is a valid PRINT_OPERAND punctation
564 static bool mips_print_operand_punct[256];
566 static GTY (()) int mips_output_filename_first_time = 1;
568 /* mips_split_p[X] is true if symbols of type X can be split by
569 mips_split_symbol. */
570 bool mips_split_p[NUM_SYMBOL_TYPES];
572 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
573 can be split by mips_split_symbol. */
574 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
576 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
577 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
578 if they are matched by a special .md file pattern. */
579 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
581 /* Likewise for HIGHs. */
582 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
584 /* Target state for MIPS16. */
585 struct target_globals *mips16_globals;
587 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
588 and returned from mips_sched_reorder2. */
589 static int cached_can_issue_more;
591 /* Index R is the smallest register class that contains register R. */
592 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
593 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
594 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
595 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
596 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
597 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
598 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
599 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
600 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
601 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
602 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
603 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
604 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
610 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
611 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
612 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
613 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
614 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
615 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
616 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
622 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
623 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
624 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
630 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
631 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
632 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
638 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
639 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
642 /* The value of TARGET_ATTRIBUTE_TABLE. */
643 static const struct attribute_spec mips_attribute_table[] = {
644 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
646 { "long_call", 0, 0, false, true, true, NULL, false },
647 { "far", 0, 0, false, true, true, NULL, false },
648 { "near", 0, 0, false, true, true, NULL, false },
649 /* We would really like to treat "mips16" and "nomips16" as type
650 attributes, but GCC doesn't provide the hooks we need to support
651 the right conversion rules. As declaration attributes, they affect
652 code generation but don't carry other semantics. */
653 { "mips16", 0, 0, true, false, false, NULL, false },
654 { "nomips16", 0, 0, true, false, false, NULL, false },
655 /* Allow functions to be specified as interrupt handlers */
656 { "interrupt", 0, 0, false, true, true, NULL, false },
657 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
658 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
659 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
660 { NULL, 0, 0, false, false, false, NULL, false }
663 /* A table describing all the processors GCC knows about; see
664 mips-cpus.def for details. */
665 static const struct mips_cpu_info mips_cpu_info_table[] = {
666 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
667 { NAME, CPU, ISA, FLAGS },
668 #include "mips-cpus.def"
672 /* Default costs. If these are used for a processor we should look
673 up the actual costs. */
674 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
675 COSTS_N_INSNS (7), /* fp_mult_sf */ \
676 COSTS_N_INSNS (8), /* fp_mult_df */ \
677 COSTS_N_INSNS (23), /* fp_div_sf */ \
678 COSTS_N_INSNS (36), /* fp_div_df */ \
679 COSTS_N_INSNS (10), /* int_mult_si */ \
680 COSTS_N_INSNS (10), /* int_mult_di */ \
681 COSTS_N_INSNS (69), /* int_div_si */ \
682 COSTS_N_INSNS (69), /* int_div_di */ \
683 2, /* branch_cost */ \
684 4 /* memory_latency */
686 /* Floating-point costs for processors without an FPU. Just assume that
687 all floating-point libcalls are very expensive. */
688 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
689 COSTS_N_INSNS (256), /* fp_mult_sf */ \
690 COSTS_N_INSNS (256), /* fp_mult_df */ \
691 COSTS_N_INSNS (256), /* fp_div_sf */ \
692 COSTS_N_INSNS (256) /* fp_div_df */
694 /* Costs to use when optimizing for size. */
695 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
696 COSTS_N_INSNS (1), /* fp_add */
697 COSTS_N_INSNS (1), /* fp_mult_sf */
698 COSTS_N_INSNS (1), /* fp_mult_df */
699 COSTS_N_INSNS (1), /* fp_div_sf */
700 COSTS_N_INSNS (1), /* fp_div_df */
701 COSTS_N_INSNS (1), /* int_mult_si */
702 COSTS_N_INSNS (1), /* int_mult_di */
703 COSTS_N_INSNS (1), /* int_div_si */
704 COSTS_N_INSNS (1), /* int_div_di */
706 4 /* memory_latency */
709 /* Costs to use when optimizing for speed, indexed by processor. */
710 static const struct mips_rtx_cost_data
711 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
713 COSTS_N_INSNS (2), /* fp_add */
714 COSTS_N_INSNS (4), /* fp_mult_sf */
715 COSTS_N_INSNS (5), /* fp_mult_df */
716 COSTS_N_INSNS (12), /* fp_div_sf */
717 COSTS_N_INSNS (19), /* fp_div_df */
718 COSTS_N_INSNS (12), /* int_mult_si */
719 COSTS_N_INSNS (12), /* int_mult_di */
720 COSTS_N_INSNS (35), /* int_div_si */
721 COSTS_N_INSNS (35), /* int_div_di */
723 4 /* memory_latency */
727 COSTS_N_INSNS (6), /* int_mult_si */
728 COSTS_N_INSNS (6), /* int_mult_di */
729 COSTS_N_INSNS (36), /* int_div_si */
730 COSTS_N_INSNS (36), /* int_div_di */
732 4 /* memory_latency */
736 COSTS_N_INSNS (36), /* int_mult_si */
737 COSTS_N_INSNS (36), /* int_mult_di */
738 COSTS_N_INSNS (37), /* int_div_si */
739 COSTS_N_INSNS (37), /* int_div_di */
741 4 /* memory_latency */
745 COSTS_N_INSNS (4), /* int_mult_si */
746 COSTS_N_INSNS (11), /* int_mult_di */
747 COSTS_N_INSNS (36), /* int_div_si */
748 COSTS_N_INSNS (68), /* int_div_di */
750 4 /* memory_latency */
753 COSTS_N_INSNS (4), /* fp_add */
754 COSTS_N_INSNS (4), /* fp_mult_sf */
755 COSTS_N_INSNS (5), /* fp_mult_df */
756 COSTS_N_INSNS (17), /* fp_div_sf */
757 COSTS_N_INSNS (32), /* fp_div_df */
758 COSTS_N_INSNS (4), /* int_mult_si */
759 COSTS_N_INSNS (11), /* int_mult_di */
760 COSTS_N_INSNS (36), /* int_div_si */
761 COSTS_N_INSNS (68), /* int_div_di */
763 4 /* memory_latency */
766 COSTS_N_INSNS (4), /* fp_add */
767 COSTS_N_INSNS (4), /* fp_mult_sf */
768 COSTS_N_INSNS (5), /* fp_mult_df */
769 COSTS_N_INSNS (17), /* fp_div_sf */
770 COSTS_N_INSNS (32), /* fp_div_df */
771 COSTS_N_INSNS (4), /* int_mult_si */
772 COSTS_N_INSNS (7), /* int_mult_di */
773 COSTS_N_INSNS (42), /* int_div_si */
774 COSTS_N_INSNS (72), /* int_div_di */
776 4 /* memory_latency */
780 COSTS_N_INSNS (5), /* int_mult_si */
781 COSTS_N_INSNS (5), /* int_mult_di */
782 COSTS_N_INSNS (41), /* int_div_si */
783 COSTS_N_INSNS (41), /* int_div_di */
785 4 /* memory_latency */
788 COSTS_N_INSNS (8), /* fp_add */
789 COSTS_N_INSNS (8), /* fp_mult_sf */
790 COSTS_N_INSNS (10), /* fp_mult_df */
791 COSTS_N_INSNS (34), /* fp_div_sf */
792 COSTS_N_INSNS (64), /* fp_div_df */
793 COSTS_N_INSNS (5), /* int_mult_si */
794 COSTS_N_INSNS (5), /* int_mult_di */
795 COSTS_N_INSNS (41), /* int_div_si */
796 COSTS_N_INSNS (41), /* int_div_di */
798 4 /* memory_latency */
801 COSTS_N_INSNS (4), /* fp_add */
802 COSTS_N_INSNS (4), /* fp_mult_sf */
803 COSTS_N_INSNS (5), /* fp_mult_df */
804 COSTS_N_INSNS (17), /* fp_div_sf */
805 COSTS_N_INSNS (32), /* fp_div_df */
806 COSTS_N_INSNS (5), /* int_mult_si */
807 COSTS_N_INSNS (5), /* int_mult_di */
808 COSTS_N_INSNS (41), /* int_div_si */
809 COSTS_N_INSNS (41), /* int_div_di */
811 4 /* memory_latency */
815 COSTS_N_INSNS (5), /* int_mult_si */
816 COSTS_N_INSNS (5), /* int_mult_di */
817 COSTS_N_INSNS (41), /* int_div_si */
818 COSTS_N_INSNS (41), /* int_div_di */
820 4 /* memory_latency */
823 COSTS_N_INSNS (8), /* fp_add */
824 COSTS_N_INSNS (8), /* fp_mult_sf */
825 COSTS_N_INSNS (10), /* fp_mult_df */
826 COSTS_N_INSNS (34), /* fp_div_sf */
827 COSTS_N_INSNS (64), /* fp_div_df */
828 COSTS_N_INSNS (5), /* int_mult_si */
829 COSTS_N_INSNS (5), /* int_mult_di */
830 COSTS_N_INSNS (41), /* int_div_si */
831 COSTS_N_INSNS (41), /* int_div_di */
833 4 /* memory_latency */
836 COSTS_N_INSNS (4), /* fp_add */
837 COSTS_N_INSNS (4), /* fp_mult_sf */
838 COSTS_N_INSNS (5), /* fp_mult_df */
839 COSTS_N_INSNS (17), /* fp_div_sf */
840 COSTS_N_INSNS (32), /* fp_div_df */
841 COSTS_N_INSNS (5), /* int_mult_si */
842 COSTS_N_INSNS (5), /* int_mult_di */
843 COSTS_N_INSNS (41), /* int_div_si */
844 COSTS_N_INSNS (41), /* int_div_di */
846 4 /* memory_latency */
849 COSTS_N_INSNS (6), /* fp_add */
850 COSTS_N_INSNS (6), /* fp_mult_sf */
851 COSTS_N_INSNS (7), /* fp_mult_df */
852 COSTS_N_INSNS (25), /* fp_div_sf */
853 COSTS_N_INSNS (48), /* fp_div_df */
854 COSTS_N_INSNS (5), /* int_mult_si */
855 COSTS_N_INSNS (5), /* int_mult_di */
856 COSTS_N_INSNS (41), /* int_div_si */
857 COSTS_N_INSNS (41), /* int_div_di */
859 4 /* memory_latency */
876 COSTS_N_INSNS (5), /* int_mult_si */
877 COSTS_N_INSNS (5), /* int_mult_di */
878 COSTS_N_INSNS (72), /* int_div_si */
879 COSTS_N_INSNS (72), /* int_div_di */
881 4 /* memory_latency */
884 COSTS_N_INSNS (2), /* fp_add */
885 COSTS_N_INSNS (4), /* fp_mult_sf */
886 COSTS_N_INSNS (5), /* fp_mult_df */
887 COSTS_N_INSNS (12), /* fp_div_sf */
888 COSTS_N_INSNS (19), /* fp_div_df */
889 COSTS_N_INSNS (2), /* int_mult_si */
890 COSTS_N_INSNS (2), /* int_mult_di */
891 COSTS_N_INSNS (35), /* int_div_si */
892 COSTS_N_INSNS (35), /* int_div_di */
894 4 /* memory_latency */
897 COSTS_N_INSNS (3), /* fp_add */
898 COSTS_N_INSNS (5), /* fp_mult_sf */
899 COSTS_N_INSNS (6), /* fp_mult_df */
900 COSTS_N_INSNS (15), /* fp_div_sf */
901 COSTS_N_INSNS (16), /* fp_div_df */
902 COSTS_N_INSNS (17), /* int_mult_si */
903 COSTS_N_INSNS (17), /* int_mult_di */
904 COSTS_N_INSNS (38), /* int_div_si */
905 COSTS_N_INSNS (38), /* int_div_di */
907 6 /* memory_latency */
910 COSTS_N_INSNS (6), /* fp_add */
911 COSTS_N_INSNS (7), /* fp_mult_sf */
912 COSTS_N_INSNS (8), /* fp_mult_df */
913 COSTS_N_INSNS (23), /* fp_div_sf */
914 COSTS_N_INSNS (36), /* fp_div_df */
915 COSTS_N_INSNS (10), /* int_mult_si */
916 COSTS_N_INSNS (10), /* int_mult_di */
917 COSTS_N_INSNS (69), /* int_div_si */
918 COSTS_N_INSNS (69), /* int_div_di */
920 6 /* memory_latency */
932 /* The only costs that appear to be updated here are
933 integer multiplication. */
935 COSTS_N_INSNS (4), /* int_mult_si */
936 COSTS_N_INSNS (6), /* int_mult_di */
937 COSTS_N_INSNS (69), /* int_div_si */
938 COSTS_N_INSNS (69), /* int_div_di */
940 4 /* memory_latency */
952 COSTS_N_INSNS (6), /* fp_add */
953 COSTS_N_INSNS (4), /* fp_mult_sf */
954 COSTS_N_INSNS (5), /* fp_mult_df */
955 COSTS_N_INSNS (23), /* fp_div_sf */
956 COSTS_N_INSNS (36), /* fp_div_df */
957 COSTS_N_INSNS (5), /* int_mult_si */
958 COSTS_N_INSNS (5), /* int_mult_di */
959 COSTS_N_INSNS (36), /* int_div_si */
960 COSTS_N_INSNS (36), /* int_div_di */
962 4 /* memory_latency */
965 COSTS_N_INSNS (6), /* fp_add */
966 COSTS_N_INSNS (5), /* fp_mult_sf */
967 COSTS_N_INSNS (6), /* fp_mult_df */
968 COSTS_N_INSNS (30), /* fp_div_sf */
969 COSTS_N_INSNS (59), /* fp_div_df */
970 COSTS_N_INSNS (3), /* int_mult_si */
971 COSTS_N_INSNS (4), /* int_mult_di */
972 COSTS_N_INSNS (42), /* int_div_si */
973 COSTS_N_INSNS (74), /* int_div_di */
975 4 /* memory_latency */
978 COSTS_N_INSNS (6), /* fp_add */
979 COSTS_N_INSNS (5), /* fp_mult_sf */
980 COSTS_N_INSNS (6), /* fp_mult_df */
981 COSTS_N_INSNS (30), /* fp_div_sf */
982 COSTS_N_INSNS (59), /* fp_div_df */
983 COSTS_N_INSNS (5), /* int_mult_si */
984 COSTS_N_INSNS (9), /* int_mult_di */
985 COSTS_N_INSNS (42), /* int_div_si */
986 COSTS_N_INSNS (74), /* int_div_di */
988 4 /* memory_latency */
991 /* The only costs that are changed here are
992 integer multiplication. */
993 COSTS_N_INSNS (6), /* fp_add */
994 COSTS_N_INSNS (7), /* fp_mult_sf */
995 COSTS_N_INSNS (8), /* fp_mult_df */
996 COSTS_N_INSNS (23), /* fp_div_sf */
997 COSTS_N_INSNS (36), /* fp_div_df */
998 COSTS_N_INSNS (5), /* int_mult_si */
999 COSTS_N_INSNS (9), /* int_mult_di */
1000 COSTS_N_INSNS (69), /* int_div_si */
1001 COSTS_N_INSNS (69), /* int_div_di */
1002 1, /* branch_cost */
1003 4 /* memory_latency */
1009 /* The only costs that are changed here are
1010 integer multiplication. */
1011 COSTS_N_INSNS (6), /* fp_add */
1012 COSTS_N_INSNS (7), /* fp_mult_sf */
1013 COSTS_N_INSNS (8), /* fp_mult_df */
1014 COSTS_N_INSNS (23), /* fp_div_sf */
1015 COSTS_N_INSNS (36), /* fp_div_df */
1016 COSTS_N_INSNS (3), /* int_mult_si */
1017 COSTS_N_INSNS (8), /* int_mult_di */
1018 COSTS_N_INSNS (69), /* int_div_si */
1019 COSTS_N_INSNS (69), /* int_div_di */
1020 1, /* branch_cost */
1021 4 /* memory_latency */
1024 COSTS_N_INSNS (2), /* fp_add */
1025 COSTS_N_INSNS (2), /* fp_mult_sf */
1026 COSTS_N_INSNS (2), /* fp_mult_df */
1027 COSTS_N_INSNS (12), /* fp_div_sf */
1028 COSTS_N_INSNS (19), /* fp_div_df */
1029 COSTS_N_INSNS (5), /* int_mult_si */
1030 COSTS_N_INSNS (9), /* int_mult_di */
1031 COSTS_N_INSNS (34), /* int_div_si */
1032 COSTS_N_INSNS (66), /* int_div_di */
1033 1, /* branch_cost */
1034 4 /* memory_latency */
1037 /* These costs are the same as the SB-1A below. */
1038 COSTS_N_INSNS (4), /* fp_add */
1039 COSTS_N_INSNS (4), /* fp_mult_sf */
1040 COSTS_N_INSNS (4), /* fp_mult_df */
1041 COSTS_N_INSNS (24), /* fp_div_sf */
1042 COSTS_N_INSNS (32), /* fp_div_df */
1043 COSTS_N_INSNS (3), /* int_mult_si */
1044 COSTS_N_INSNS (4), /* int_mult_di */
1045 COSTS_N_INSNS (36), /* int_div_si */
1046 COSTS_N_INSNS (68), /* int_div_di */
1047 1, /* branch_cost */
1048 4 /* memory_latency */
1051 /* These costs are the same as the SB-1 above. */
1052 COSTS_N_INSNS (4), /* fp_add */
1053 COSTS_N_INSNS (4), /* fp_mult_sf */
1054 COSTS_N_INSNS (4), /* fp_mult_df */
1055 COSTS_N_INSNS (24), /* fp_div_sf */
1056 COSTS_N_INSNS (32), /* fp_div_df */
1057 COSTS_N_INSNS (3), /* int_mult_si */
1058 COSTS_N_INSNS (4), /* int_mult_di */
1059 COSTS_N_INSNS (36), /* int_div_si */
1060 COSTS_N_INSNS (68), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1069 COSTS_N_INSNS (8), /* int_mult_si */
1070 COSTS_N_INSNS (8), /* int_mult_di */
1071 COSTS_N_INSNS (72), /* int_div_si */
1072 COSTS_N_INSNS (72), /* int_div_di */
1073 1, /* branch_cost */
1074 4 /* memory_latency */
1078 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1079 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1081 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1083 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1084 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1085 struct GTY (()) mflip_mips16_entry {
1089 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1091 /* Hash table callbacks for mflip_mips16_htab. */
1094 mflip_mips16_htab_hash (const void *entry)
1096 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1100 mflip_mips16_htab_eq (const void *entry, const void *name)
1102 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1103 (const char *) name) == 0;
1106 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1107 mode, false if it should next add an attribute for the opposite mode. */
1108 static GTY(()) bool mips16_flipper;
1110 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1111 for -mflip-mips16. Return true if it should use "mips16" and false if
1112 it should use "nomips16". */
1115 mflip_mips16_use_mips16_p (tree decl)
1117 struct mflip_mips16_entry *entry;
1122 /* Use the opposite of the command-line setting for anonymous decls. */
1123 if (!DECL_NAME (decl))
1124 return !mips_base_mips16;
1126 if (!mflip_mips16_htab)
1127 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1128 mflip_mips16_htab_eq, NULL);
1130 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1131 hash = htab_hash_string (name);
1132 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1133 entry = (struct mflip_mips16_entry *) *slot;
1136 mips16_flipper = !mips16_flipper;
1137 entry = ggc_alloc_mflip_mips16_entry ();
1139 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1142 return entry->mips16_p;
1145 /* Predicates to test for presence of "near" and "far"/"long_call"
1146 attributes on the given TYPE. */
1149 mips_near_type_p (const_tree type)
1151 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1155 mips_far_type_p (const_tree type)
1157 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1158 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1161 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1164 mips_mips16_decl_p (const_tree decl)
1166 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1170 mips_nomips16_decl_p (const_tree decl)
1172 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1175 /* Check if the interrupt attribute is set for a function. */
1178 mips_interrupt_type_p (tree type)
1180 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1183 /* Check if the attribute to use shadow register set is set for a function. */
1186 mips_use_shadow_register_set_p (tree type)
1188 return lookup_attribute ("use_shadow_register_set",
1189 TYPE_ATTRIBUTES (type)) != NULL;
1192 /* Check if the attribute to keep interrupts masked is set for a function. */
1195 mips_keep_interrupts_masked_p (tree type)
1197 return lookup_attribute ("keep_interrupts_masked",
1198 TYPE_ATTRIBUTES (type)) != NULL;
1201 /* Check if the attribute to use debug exception return is set for
1205 mips_use_debug_exception_return_p (tree type)
1207 return lookup_attribute ("use_debug_exception_return",
1208 TYPE_ATTRIBUTES (type)) != NULL;
1211 /* Return true if function DECL is a MIPS16 function. Return the ambient
1212 setting if DECL is null. */
1215 mips_use_mips16_mode_p (tree decl)
1219 /* Nested functions must use the same frame pointer as their
1220 parent and must therefore use the same ISA mode. */
1221 tree parent = decl_function_context (decl);
1224 if (mips_mips16_decl_p (decl))
1226 if (mips_nomips16_decl_p (decl))
1229 return mips_base_mips16;
1232 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1235 mips_comp_type_attributes (const_tree type1, const_tree type2)
1237 /* Disallow mixed near/far attributes. */
1238 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1240 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1245 /* Implement TARGET_INSERT_ATTRIBUTES. */
1248 mips_insert_attributes (tree decl, tree *attributes)
1251 bool mips16_p, nomips16_p;
1253 /* Check for "mips16" and "nomips16" attributes. */
1254 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1255 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1256 if (TREE_CODE (decl) != FUNCTION_DECL)
1259 error ("%qs attribute only applies to functions", "mips16");
1261 error ("%qs attribute only applies to functions", "nomips16");
1265 mips16_p |= mips_mips16_decl_p (decl);
1266 nomips16_p |= mips_nomips16_decl_p (decl);
1267 if (mips16_p || nomips16_p)
1269 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1270 if (mips16_p && nomips16_p)
1271 error ("%qE cannot have both %<mips16%> and "
1272 "%<nomips16%> attributes",
1275 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1277 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1278 "mips16" attribute, arbitrarily pick one. We must pick the same
1279 setting for duplicate declarations of a function. */
1280 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1281 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1286 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1289 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1291 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1292 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1293 error ("%qE redeclared with conflicting %qs attributes",
1294 DECL_NAME (newdecl), "mips16");
1295 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1296 error ("%qE redeclared with conflicting %qs attributes",
1297 DECL_NAME (newdecl), "nomips16");
1299 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1300 DECL_ATTRIBUTES (newdecl));
1303 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1304 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1307 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1309 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1311 *base_ptr = XEXP (x, 0);
1312 *offset_ptr = INTVAL (XEXP (x, 1));
1321 static unsigned int mips_build_integer (struct mips_integer_op *,
1322 unsigned HOST_WIDE_INT);
1324 /* A subroutine of mips_build_integer, with the same interface.
1325 Assume that the final action in the sequence should be a left shift. */
1328 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1330 unsigned int i, shift;
1332 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1333 since signed numbers are easier to load than unsigned ones. */
1335 while ((value & 1) == 0)
1336 value /= 2, shift++;
1338 i = mips_build_integer (codes, value);
1339 codes[i].code = ASHIFT;
1340 codes[i].value = shift;
1344 /* As for mips_build_shift, but assume that the final action will be
1345 an IOR or PLUS operation. */
1348 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1350 unsigned HOST_WIDE_INT high;
1353 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1354 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1356 /* The constant is too complex to load with a simple LUI/ORI pair,
1357 so we want to give the recursive call as many trailing zeros as
1358 possible. In this case, we know bit 16 is set and that the
1359 low 16 bits form a negative number. If we subtract that number
1360 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1361 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1362 codes[i].code = PLUS;
1363 codes[i].value = CONST_LOW_PART (value);
1367 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1368 bits gives a value with at least 17 trailing zeros. */
1369 i = mips_build_integer (codes, high);
1370 codes[i].code = IOR;
1371 codes[i].value = value & 0xffff;
1376 /* Fill CODES with a sequence of rtl operations to load VALUE.
1377 Return the number of operations needed. */
1380 mips_build_integer (struct mips_integer_op *codes,
1381 unsigned HOST_WIDE_INT value)
1383 if (SMALL_OPERAND (value)
1384 || SMALL_OPERAND_UNSIGNED (value)
1385 || LUI_OPERAND (value))
1387 /* The value can be loaded with a single instruction. */
1388 codes[0].code = UNKNOWN;
1389 codes[0].value = value;
1392 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1394 /* Either the constant is a simple LUI/ORI combination or its
1395 lowest bit is set. We don't want to shift in this case. */
1396 return mips_build_lower (codes, value);
1398 else if ((value & 0xffff) == 0)
1400 /* The constant will need at least three actions. The lowest
1401 16 bits are clear, so the final action will be a shift. */
1402 return mips_build_shift (codes, value);
1406 /* The final action could be a shift, add or inclusive OR.
1407 Rather than use a complex condition to select the best
1408 approach, try both mips_build_shift and mips_build_lower
1409 and pick the one that gives the shortest sequence.
1410 Note that this case is only used once per constant. */
1411 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1412 unsigned int cost, alt_cost;
1414 cost = mips_build_shift (codes, value);
1415 alt_cost = mips_build_lower (alt_codes, value);
1416 if (alt_cost < cost)
1418 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1425 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1428 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1430 return mips_const_insns (x) > 0;
1433 /* Return true if symbols of type TYPE require a GOT access. */
1436 mips_got_symbol_type_p (enum mips_symbol_type type)
1440 case SYMBOL_GOT_PAGE_OFST:
1441 case SYMBOL_GOT_DISP:
1449 /* Return true if X is a thread-local symbol. */
1452 mips_tls_symbol_p (rtx x)
1454 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1457 /* Return true if SYMBOL_REF X is associated with a global symbol
1458 (in the STB_GLOBAL sense). */
1461 mips_global_symbol_p (const_rtx x)
1463 const_tree decl = SYMBOL_REF_DECL (x);
1466 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1468 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1469 or weak symbols. Relocations in the object file will be against
1470 the target symbol, so it's that symbol's binding that matters here. */
1471 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1474 /* Return true if function X is a libgcc MIPS16 stub function. */
1477 mips16_stub_function_p (const_rtx x)
1479 return (GET_CODE (x) == SYMBOL_REF
1480 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1483 /* Return true if function X is a locally-defined and locally-binding
1487 mips16_local_function_p (const_rtx x)
1489 return (GET_CODE (x) == SYMBOL_REF
1490 && SYMBOL_REF_LOCAL_P (x)
1491 && !SYMBOL_REF_EXTERNAL_P (x)
1492 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1495 /* Return true if SYMBOL_REF X binds locally. */
1498 mips_symbol_binds_local_p (const_rtx x)
1500 return (SYMBOL_REF_DECL (x)
1501 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1502 : SYMBOL_REF_LOCAL_P (x));
1505 /* Return true if rtx constants of mode MODE should be put into a small
1509 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1511 return (!TARGET_EMBEDDED_DATA
1512 && TARGET_LOCAL_SDATA
1513 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1516 /* Return true if X should not be moved directly into register $25.
1517 We need this because many versions of GAS will treat "la $25,foo" as
1518 part of a call sequence and so allow a global "foo" to be lazily bound. */
1521 mips_dangerous_for_la25_p (rtx x)
1523 return (!TARGET_EXPLICIT_RELOCS
1525 && GET_CODE (x) == SYMBOL_REF
1526 && mips_global_symbol_p (x));
1529 /* Return true if calls to X might need $25 to be valid on entry. */
1532 mips_use_pic_fn_addr_reg_p (const_rtx x)
1534 if (!TARGET_USE_PIC_FN_ADDR_REG)
1537 /* MIPS16 stub functions are guaranteed not to use $25. */
1538 if (mips16_stub_function_p (x))
1541 if (GET_CODE (x) == SYMBOL_REF)
1543 /* If PLTs and copy relocations are available, the static linker
1544 will make sure that $25 is valid on entry to the target function. */
1545 if (TARGET_ABICALLS_PIC0)
1548 /* Locally-defined functions use absolute accesses to set up
1549 the global pointer. */
1550 if (TARGET_ABSOLUTE_ABICALLS
1551 && mips_symbol_binds_local_p (x)
1552 && !SYMBOL_REF_EXTERNAL_P (x))
1559 /* Return the method that should be used to access SYMBOL_REF or
1560 LABEL_REF X in context CONTEXT. */
1562 static enum mips_symbol_type
1563 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1566 return SYMBOL_GOT_DISP;
1568 if (GET_CODE (x) == LABEL_REF)
1570 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1571 code and if we know that the label is in the current function's
1572 text section. LABEL_REFs are used for jump tables as well as
1573 text labels, so we must check whether jump tables live in the
1575 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1576 && !LABEL_REF_NONLOCAL_P (x))
1577 return SYMBOL_PC_RELATIVE;
1579 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1580 return SYMBOL_GOT_PAGE_OFST;
1582 return SYMBOL_ABSOLUTE;
1585 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1587 if (SYMBOL_REF_TLS_MODEL (x))
1590 if (CONSTANT_POOL_ADDRESS_P (x))
1592 if (TARGET_MIPS16_TEXT_LOADS)
1593 return SYMBOL_PC_RELATIVE;
1595 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1596 return SYMBOL_PC_RELATIVE;
1598 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1599 return SYMBOL_GP_RELATIVE;
1602 /* Do not use small-data accesses for weak symbols; they may end up
1604 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1605 return SYMBOL_GP_RELATIVE;
1607 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1609 if (TARGET_ABICALLS_PIC2
1610 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1612 /* There are three cases to consider:
1614 - o32 PIC (either with or without explicit relocs)
1615 - n32/n64 PIC without explicit relocs
1616 - n32/n64 PIC with explicit relocs
1618 In the first case, both local and global accesses will use an
1619 R_MIPS_GOT16 relocation. We must correctly predict which of
1620 the two semantics (local or global) the assembler and linker
1621 will apply. The choice depends on the symbol's binding rather
1622 than its visibility.
1624 In the second case, the assembler will not use R_MIPS_GOT16
1625 relocations, but it chooses between local and global accesses
1626 in the same way as for o32 PIC.
1628 In the third case we have more freedom since both forms of
1629 access will work for any kind of symbol. However, there seems
1630 little point in doing things differently. */
1631 if (mips_global_symbol_p (x))
1632 return SYMBOL_GOT_DISP;
1634 return SYMBOL_GOT_PAGE_OFST;
1637 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1638 return SYMBOL_FORCE_TO_MEM;
1640 return SYMBOL_ABSOLUTE;
1643 /* Classify the base of symbolic expression X, given that X appears in
1646 static enum mips_symbol_type
1647 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1651 split_const (x, &x, &offset);
1652 if (UNSPEC_ADDRESS_P (x))
1653 return UNSPEC_ADDRESS_TYPE (x);
1655 return mips_classify_symbol (x, context);
1658 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1659 is the alignment in bytes of SYMBOL_REF X. */
1662 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1664 HOST_WIDE_INT align;
1666 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1667 return IN_RANGE (offset, 0, align - 1);
1670 /* Return true if X is a symbolic constant that can be used in context
1671 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1674 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1675 enum mips_symbol_type *symbol_type)
1679 split_const (x, &x, &offset);
1680 if (UNSPEC_ADDRESS_P (x))
1682 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1683 x = UNSPEC_ADDRESS (x);
1685 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1687 *symbol_type = mips_classify_symbol (x, context);
1688 if (*symbol_type == SYMBOL_TLS)
1694 if (offset == const0_rtx)
1697 /* Check whether a nonzero offset is valid for the underlying
1699 switch (*symbol_type)
1701 case SYMBOL_ABSOLUTE:
1702 case SYMBOL_FORCE_TO_MEM:
1703 case SYMBOL_32_HIGH:
1704 case SYMBOL_64_HIGH:
1707 /* If the target has 64-bit pointers and the object file only
1708 supports 32-bit symbols, the values of those symbols will be
1709 sign-extended. In this case we can't allow an arbitrary offset
1710 in case the 32-bit value X + OFFSET has a different sign from X. */
1711 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1712 return offset_within_block_p (x, INTVAL (offset));
1714 /* In other cases the relocations can handle any offset. */
1717 case SYMBOL_PC_RELATIVE:
1718 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1719 In this case, we no longer have access to the underlying constant,
1720 but the original symbol-based access was known to be valid. */
1721 if (GET_CODE (x) == LABEL_REF)
1726 case SYMBOL_GP_RELATIVE:
1727 /* Make sure that the offset refers to something within the
1728 same object block. This should guarantee that the final
1729 PC- or GP-relative offset is within the 16-bit limit. */
1730 return offset_within_block_p (x, INTVAL (offset));
1732 case SYMBOL_GOT_PAGE_OFST:
1733 case SYMBOL_GOTOFF_PAGE:
1734 /* If the symbol is global, the GOT entry will contain the symbol's
1735 address, and we will apply a 16-bit offset after loading it.
1736 If the symbol is local, the linker should provide enough local
1737 GOT entries for a 16-bit offset, but larger offsets may lead
1739 return SMALL_INT (offset);
1743 /* There is no carry between the HI and LO REL relocations, so the
1744 offset is only valid if we know it won't lead to such a carry. */
1745 return mips_offset_within_alignment_p (x, INTVAL (offset));
1747 case SYMBOL_GOT_DISP:
1748 case SYMBOL_GOTOFF_DISP:
1749 case SYMBOL_GOTOFF_CALL:
1750 case SYMBOL_GOTOFF_LOADGP:
1753 case SYMBOL_GOTTPREL:
1761 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1762 single instruction. We rely on the fact that, in the worst case,
1763 all instructions involved in a MIPS16 address calculation are usually
1767 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1771 case SYMBOL_ABSOLUTE:
1772 /* When using 64-bit symbols, we need 5 preparatory instructions,
1775 lui $at,%highest(symbol)
1776 daddiu $at,$at,%higher(symbol)
1778 daddiu $at,$at,%hi(symbol)
1781 The final address is then $at + %lo(symbol). With 32-bit
1782 symbols we just need a preparatory LUI for normal mode and
1783 a preparatory LI and SLL for MIPS16. */
1784 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1786 case SYMBOL_GP_RELATIVE:
1787 /* Treat GP-relative accesses as taking a single instruction on
1788 MIPS16 too; the copy of $gp can often be shared. */
1791 case SYMBOL_PC_RELATIVE:
1792 /* PC-relative constants can be only be used with ADDIUPC,
1793 DADDIUPC, LWPC and LDPC. */
1794 if (mode == MAX_MACHINE_MODE
1795 || GET_MODE_SIZE (mode) == 4
1796 || GET_MODE_SIZE (mode) == 8)
1799 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1802 case SYMBOL_FORCE_TO_MEM:
1803 /* LEAs will be converted into constant-pool references by
1805 if (mode == MAX_MACHINE_MODE)
1808 /* The constant must be loaded and then dereferenced. */
1811 case SYMBOL_GOT_DISP:
1812 /* The constant will have to be loaded from the GOT before it
1813 is used in an address. */
1814 if (mode != MAX_MACHINE_MODE)
1819 case SYMBOL_GOT_PAGE_OFST:
1820 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1821 local/global classification is accurate. The worst cases are:
1823 (1) For local symbols when generating o32 or o64 code. The assembler
1829 ...and the final address will be $at + %lo(symbol).
1831 (2) For global symbols when -mxgot. The assembler will use:
1833 lui $at,%got_hi(symbol)
1836 ...and the final address will be $at + %got_lo(symbol). */
1839 case SYMBOL_GOTOFF_PAGE:
1840 case SYMBOL_GOTOFF_DISP:
1841 case SYMBOL_GOTOFF_CALL:
1842 case SYMBOL_GOTOFF_LOADGP:
1843 case SYMBOL_32_HIGH:
1844 case SYMBOL_64_HIGH:
1850 case SYMBOL_GOTTPREL:
1853 /* A 16-bit constant formed by a single relocation, or a 32-bit
1854 constant formed from a high 16-bit relocation and a low 16-bit
1855 relocation. Use mips_split_p to determine which. 32-bit
1856 constants need an "lui; addiu" sequence for normal mode and
1857 an "li; sll; addiu" sequence for MIPS16 mode. */
1858 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1861 /* We don't treat a bare TLS symbol as a constant. */
1867 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1868 to load symbols of type TYPE into a register. Return 0 if the given
1869 type of symbol cannot be used as an immediate operand.
1871 Otherwise, return the number of instructions needed to load or store
1872 values of mode MODE to or from addresses of type TYPE. Return 0 if
1873 the given type of symbol is not valid in addresses.
1875 In both cases, treat extended MIPS16 instructions as two instructions. */
1878 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1880 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1883 /* A for_each_rtx callback. Stop the search if *X references a
1884 thread-local symbol. */
1887 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1889 return mips_tls_symbol_p (*x);
1892 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1895 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
1897 enum mips_symbol_type type;
1900 /* There is no assembler syntax for expressing an address-sized
1902 if (GET_CODE (x) == HIGH)
1905 /* As an optimization, reject constants that mips_legitimize_move
1908 Suppose we have a multi-instruction sequence that loads constant C
1909 into register R. If R does not get allocated a hard register, and
1910 R is used in an operand that allows both registers and memory
1911 references, reload will consider forcing C into memory and using
1912 one of the instruction's memory alternatives. Returning false
1913 here will force it to use an input reload instead. */
1914 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
1917 split_const (x, &base, &offset);
1918 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1919 && type != SYMBOL_FORCE_TO_MEM)
1921 /* The same optimization as for CONST_INT. */
1922 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1925 /* If MIPS16 constant pools live in the text section, they should
1926 not refer to anything that might need run-time relocation. */
1927 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1931 /* TLS symbols must be computed by mips_legitimize_move. */
1932 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1938 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1939 constants when we're using a per-function constant pool. */
1942 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1943 const_rtx x ATTRIBUTE_UNUSED)
1945 return !TARGET_MIPS16_PCREL_LOADS;
1948 /* Return true if register REGNO is a valid base register for mode MODE.
1949 STRICT_P is true if REG_OK_STRICT is in effect. */
1952 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1955 if (!HARD_REGISTER_NUM_P (regno))
1959 regno = reg_renumber[regno];
1962 /* These fake registers will be eliminated to either the stack or
1963 hard frame pointer, both of which are usually valid base registers.
1964 Reload deals with the cases where the eliminated form isn't valid. */
1965 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1968 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1969 values, nothing smaller. There are two problems here:
1971 (a) Instantiating virtual registers can introduce new uses of the
1972 stack pointer. If these virtual registers are valid addresses,
1973 the stack pointer should be too.
1975 (b) Most uses of the stack pointer are not made explicit until
1976 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1977 We don't know until that stage whether we'll be eliminating to the
1978 stack pointer (which needs the restriction) or the hard frame
1979 pointer (which doesn't).
1981 All in all, it seems more consistent to only enforce this restriction
1982 during and after reload. */
1983 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1984 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1986 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1989 /* Return true if X is a valid base register for mode MODE.
1990 STRICT_P is true if REG_OK_STRICT is in effect. */
1993 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1995 if (!strict_p && GET_CODE (x) == SUBREG)
1999 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2002 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2003 can address a value of mode MODE. */
2006 mips_valid_offset_p (rtx x, enum machine_mode mode)
2008 /* Check that X is a signed 16-bit number. */
2009 if (!const_arith_operand (x, Pmode))
2012 /* We may need to split multiword moves, so make sure that every word
2014 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2015 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2021 /* Return true if a LO_SUM can address a value of mode MODE when the
2022 LO_SUM symbol has type SYMBOL_TYPE. */
2025 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2027 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2029 if (mips_symbol_insns (symbol_type, mode) == 0)
2032 /* Check that there is a known low-part relocation. */
2033 if (mips_lo_relocs[symbol_type] == NULL)
2036 /* We may need to split multiword moves, so make sure that each word
2037 can be accessed without inducing a carry. This is mainly needed
2038 for o64, which has historically only guaranteed 64-bit alignment
2039 for 128-bit types. */
2040 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2041 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2047 /* Return true if X is a valid address for machine mode MODE. If it is,
2048 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2052 mips_classify_address (struct mips_address_info *info, rtx x,
2053 enum machine_mode mode, bool strict_p)
2055 switch (GET_CODE (x))
2059 info->type = ADDRESS_REG;
2061 info->offset = const0_rtx;
2062 return mips_valid_base_register_p (info->reg, mode, strict_p);
2065 info->type = ADDRESS_REG;
2066 info->reg = XEXP (x, 0);
2067 info->offset = XEXP (x, 1);
2068 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2069 && mips_valid_offset_p (info->offset, mode));
2072 info->type = ADDRESS_LO_SUM;
2073 info->reg = XEXP (x, 0);
2074 info->offset = XEXP (x, 1);
2075 /* We have to trust the creator of the LO_SUM to do something vaguely
2076 sane. Target-independent code that creates a LO_SUM should also
2077 create and verify the matching HIGH. Target-independent code that
2078 adds an offset to a LO_SUM must prove that the offset will not
2079 induce a carry. Failure to do either of these things would be
2080 a bug, and we are not required to check for it here. The MIPS
2081 backend itself should only create LO_SUMs for valid symbolic
2082 constants, with the high part being either a HIGH or a copy
2085 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2086 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2087 && mips_valid_lo_sum_p (info->symbol_type, mode));
2090 /* Small-integer addresses don't occur very often, but they
2091 are legitimate if $0 is a valid base register. */
2092 info->type = ADDRESS_CONST_INT;
2093 return !TARGET_MIPS16 && SMALL_INT (x);
2098 info->type = ADDRESS_SYMBOLIC;
2099 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2101 && mips_symbol_insns (info->symbol_type, mode) > 0
2102 && !mips_split_p[info->symbol_type]);
2109 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2112 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2114 struct mips_address_info addr;
2116 return mips_classify_address (&addr, x, mode, strict_p);
2119 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2122 mips_stack_address_p (rtx x, enum machine_mode mode)
2124 struct mips_address_info addr;
2126 return (mips_classify_address (&addr, x, mode, false)
2127 && addr.type == ADDRESS_REG
2128 && addr.reg == stack_pointer_rtx);
2131 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2132 address instruction. Note that such addresses are not considered
2133 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2134 is so restricted. */
2137 mips_lwxs_address_p (rtx addr)
2140 && GET_CODE (addr) == PLUS
2141 && REG_P (XEXP (addr, 1)))
2143 rtx offset = XEXP (addr, 0);
2144 if (GET_CODE (offset) == MULT
2145 && REG_P (XEXP (offset, 0))
2146 && CONST_INT_P (XEXP (offset, 1))
2147 && INTVAL (XEXP (offset, 1)) == 4)
2153 /* Return true if a value at OFFSET bytes from base register BASE can be
2154 accessed using an unextended MIPS16 instruction. MODE is the mode of
2157 Usually the offset in an unextended instruction is a 5-bit field.
2158 The offset is unsigned and shifted left once for LH and SH, twice
2159 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2160 an 8-bit immediate field that's shifted left twice. */
2163 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2164 unsigned HOST_WIDE_INT offset)
2166 if (offset % GET_MODE_SIZE (mode) == 0)
2168 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2169 return offset < 256U * GET_MODE_SIZE (mode);
2170 return offset < 32U * GET_MODE_SIZE (mode);
2175 /* Return the number of instructions needed to load or store a value
2176 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2177 Assume that multiword moves may need to be split into word moves
2178 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2181 For MIPS16 code, count extended instructions as two instructions. */
2184 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2186 struct mips_address_info addr;
2189 /* BLKmode is used for single unaligned loads and stores and should
2190 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2191 meaningless, so we have to single it out as a special case one way
2193 if (mode != BLKmode && might_split_p)
2194 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2198 if (mips_classify_address (&addr, x, mode, false))
2203 && !mips16_unextended_reference_p (mode, addr.reg,
2204 UINTVAL (addr.offset)))
2208 case ADDRESS_LO_SUM:
2209 return TARGET_MIPS16 ? factor * 2 : factor;
2211 case ADDRESS_CONST_INT:
2214 case ADDRESS_SYMBOLIC:
2215 return factor * mips_symbol_insns (addr.symbol_type, mode);
2220 /* Return the number of instructions needed to load constant X.
2221 Return 0 if X isn't a valid constant. */
2224 mips_const_insns (rtx x)
2226 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2227 enum mips_symbol_type symbol_type;
2230 switch (GET_CODE (x))
2233 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2235 || !mips_split_p[symbol_type])
2238 /* This is simply an LUI for normal mode. It is an extended
2239 LI followed by an extended SLL for MIPS16. */
2240 return TARGET_MIPS16 ? 4 : 1;
2244 /* Unsigned 8-bit constants can be loaded using an unextended
2245 LI instruction. Unsigned 16-bit constants can be loaded
2246 using an extended LI. Negative constants must be loaded
2247 using LI and then negated. */
2248 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2249 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2250 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2251 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2254 return mips_build_integer (codes, INTVAL (x));
2258 /* Allow zeros for normal mode, where we can use $0. */
2259 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2265 /* See if we can refer to X directly. */
2266 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2267 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2269 /* Otherwise try splitting the constant into a base and offset.
2270 If the offset is a 16-bit value, we can load the base address
2271 into a register and then use (D)ADDIU to add in the offset.
2272 If the offset is larger, we can load the base and offset
2273 into separate registers and add them together with (D)ADDU.
2274 However, the latter is only possible before reload; during
2275 and after reload, we must have the option of forcing the
2276 constant into the pool instead. */
2277 split_const (x, &x, &offset);
2280 int n = mips_const_insns (x);
2283 if (SMALL_INT (offset))
2285 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2286 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2293 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2301 /* X is a doubleword constant that can be handled by splitting it into
2302 two words and loading each word separately. Return the number of
2303 instructions required to do this. */
2306 mips_split_const_insns (rtx x)
2308 unsigned int low, high;
2310 low = mips_const_insns (mips_subword (x, false));
2311 high = mips_const_insns (mips_subword (x, true));
2312 gcc_assert (low > 0 && high > 0);
2316 /* Return the number of instructions needed to implement INSN,
2317 given that it loads from or stores to MEM. Count extended
2318 MIPS16 instructions as two instructions. */
2321 mips_load_store_insns (rtx mem, rtx insn)
2323 enum machine_mode mode;
2327 gcc_assert (MEM_P (mem));
2328 mode = GET_MODE (mem);
2330 /* Try to prove that INSN does not need to be split. */
2331 might_split_p = true;
2332 if (GET_MODE_BITSIZE (mode) == 64)
2334 set = single_set (insn);
2335 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2336 might_split_p = false;
2339 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2342 /* Return the number of instructions needed for an integer division. */
2345 mips_idiv_insns (void)
2350 if (TARGET_CHECK_ZERO_DIV)
2352 if (GENERATE_DIVIDE_TRAPS)
2358 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2363 /* Emit a move from SRC to DEST. Assume that the move expanders can
2364 handle all moves if !can_create_pseudo_p (). The distinction is
2365 important because, unlike emit_move_insn, the move expanders know
2366 how to force Pmode objects into the constant pool even when the
2367 constant pool address is not itself legitimate. */
2370 mips_emit_move (rtx dest, rtx src)
2372 return (can_create_pseudo_p ()
2373 ? emit_move_insn (dest, src)
2374 : emit_move_insn_1 (dest, src));
2377 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2380 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2382 emit_insn (gen_rtx_SET (VOIDmode, target,
2383 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2386 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2387 Return that new register. */
2390 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2394 reg = gen_reg_rtx (mode);
2395 mips_emit_unary (code, reg, op0);
2399 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2402 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2404 emit_insn (gen_rtx_SET (VOIDmode, target,
2405 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2408 /* Compute (CODE OP0 OP1) and store the result in a new register
2409 of mode MODE. Return that new register. */
2412 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2416 reg = gen_reg_rtx (mode);
2417 mips_emit_binary (code, reg, op0, op1);
2421 /* Copy VALUE to a register and return that register. If new pseudos
2422 are allowed, copy it into a new register, otherwise use DEST. */
2425 mips_force_temporary (rtx dest, rtx value)
2427 if (can_create_pseudo_p ())
2428 return force_reg (Pmode, value);
2431 mips_emit_move (dest, value);
2436 /* Emit a call sequence with call pattern PATTERN and return the call
2437 instruction itself (which is not necessarily the last instruction
2438 emitted). ORIG_ADDR is the original, unlegitimized address,
2439 ADDR is the legitimized form, and LAZY_P is true if the call
2440 address is lazily-bound. */
2443 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2447 insn = emit_call_insn (pattern);
2449 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2451 /* MIPS16 JALRs only take MIPS16 registers. If the target
2452 function requires $25 to be valid on entry, we must copy it
2453 there separately. The move instruction can be put in the
2454 call's delay slot. */
2455 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2456 emit_insn_before (gen_move_insn (reg, addr), insn);
2457 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2461 /* Lazy-binding stubs require $gp to be valid on entry. */
2462 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2466 /* See the comment above load_call<mode> for details. */
2467 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2468 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2469 emit_insn (gen_update_got_version ());
2474 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2475 then add CONST_INT OFFSET to the result. */
2478 mips_unspec_address_offset (rtx base, rtx offset,
2479 enum mips_symbol_type symbol_type)
2481 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2482 UNSPEC_ADDRESS_FIRST + symbol_type);
2483 if (offset != const0_rtx)
2484 base = gen_rtx_PLUS (Pmode, base, offset);
2485 return gen_rtx_CONST (Pmode, base);
2488 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2489 type SYMBOL_TYPE. */
2492 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2496 split_const (address, &base, &offset);
2497 return mips_unspec_address_offset (base, offset, symbol_type);
2500 /* If OP is an UNSPEC address, return the address to which it refers,
2501 otherwise return OP itself. */
2504 mips_strip_unspec_address (rtx op)
2508 split_const (op, &base, &offset);
2509 if (UNSPEC_ADDRESS_P (base))
2510 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2514 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2515 high part to BASE and return the result. Just return BASE otherwise.
2516 TEMP is as for mips_force_temporary.
2518 The returned expression can be used as the first operand to a LO_SUM. */
2521 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2522 enum mips_symbol_type symbol_type)
2524 if (mips_split_p[symbol_type])
2526 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2527 addr = mips_force_temporary (temp, addr);
2528 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2533 /* Return an instruction that copies $gp into register REG. We want
2534 GCC to treat the register's value as constant, so that its value
2535 can be rematerialized on demand. */
2538 gen_load_const_gp (rtx reg)
2540 return PMODE_INSN (gen_load_const_gp, (reg));
2543 /* Return a pseudo register that contains the value of $gp throughout
2544 the current function. Such registers are needed by MIPS16 functions,
2545 for which $gp itself is not a valid base register or addition operand. */
2548 mips16_gp_pseudo_reg (void)
2550 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2554 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2556 push_topmost_sequence ();
2558 scan = get_insns ();
2559 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2560 scan = NEXT_INSN (scan);
2562 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2563 emit_insn_after (insn, scan);
2565 pop_topmost_sequence ();
2568 return cfun->machine->mips16_gp_pseudo_rtx;
2571 /* Return a base register that holds pic_offset_table_rtx.
2572 TEMP, if nonnull, is a scratch Pmode base register. */
2575 mips_pic_base_register (rtx temp)
2578 return pic_offset_table_rtx;
2580 if (currently_expanding_to_rtl)
2581 return mips16_gp_pseudo_reg ();
2583 if (can_create_pseudo_p ())
2584 temp = gen_reg_rtx (Pmode);
2587 /* The first post-reload split exposes all references to $gp
2588 (both uses and definitions). All references must remain
2589 explicit after that point.
2591 It is safe to introduce uses of $gp at any time, so for
2592 simplicity, we do that before the split too. */
2593 mips_emit_move (temp, pic_offset_table_rtx);
2595 emit_insn (gen_load_const_gp (temp));
2599 /* Return the RHS of a load_call<mode> insn. */
2602 mips_unspec_call (rtx reg, rtx symbol)
2606 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2607 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2610 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2611 reference. Return NULL_RTX otherwise. */
2614 mips_strip_unspec_call (rtx src)
2616 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2617 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2621 /* Create and return a GOT reference of type TYPE for address ADDR.
2622 TEMP, if nonnull, is a scratch Pmode base register. */
2625 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2627 rtx base, high, lo_sum_symbol;
2629 base = mips_pic_base_register (temp);
2631 /* If we used the temporary register to load $gp, we can't use
2632 it for the high part as well. */
2633 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2636 high = mips_unspec_offset_high (temp, base, addr, type);
2637 lo_sum_symbol = mips_unspec_address (addr, type);
2639 if (type == SYMBOL_GOTOFF_CALL)
2640 return mips_unspec_call (high, lo_sum_symbol);
2642 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2645 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2646 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2647 constant in that context and can be split into high and low parts.
2648 If so, and if LOW_OUT is nonnull, emit the high part and store the
2649 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2651 TEMP is as for mips_force_temporary and is used to load the high
2652 part into a register.
2654 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2655 a legitimize SET_SRC for an .md pattern, otherwise the low part
2656 is guaranteed to be a legitimate address for mode MODE. */
2659 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2661 enum mips_symbol_context context;
2662 enum mips_symbol_type symbol_type;
2665 context = (mode == MAX_MACHINE_MODE
2666 ? SYMBOL_CONTEXT_LEA
2667 : SYMBOL_CONTEXT_MEM);
2668 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2670 addr = XEXP (addr, 0);
2671 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2672 && mips_symbol_insns (symbol_type, mode) > 0
2673 && mips_split_hi_p[symbol_type])
2676 switch (symbol_type)
2678 case SYMBOL_GOT_PAGE_OFST:
2679 /* The high part of a page/ofst pair is loaded from the GOT. */
2680 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2691 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2692 && mips_symbol_insns (symbol_type, mode) > 0
2693 && mips_split_p[symbol_type])
2696 switch (symbol_type)
2698 case SYMBOL_GOT_DISP:
2699 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2700 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2703 case SYMBOL_GP_RELATIVE:
2704 high = mips_pic_base_register (temp);
2705 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2709 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2710 high = mips_force_temporary (temp, high);
2711 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2720 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2721 mips_force_temporary; it is only needed when OFFSET is not a
2725 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2727 if (!SMALL_OPERAND (offset))
2733 /* Load the full offset into a register so that we can use
2734 an unextended instruction for the address itself. */
2735 high = GEN_INT (offset);
2740 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2741 The addition inside the macro CONST_HIGH_PART may cause an
2742 overflow, so we need to force a sign-extension check. */
2743 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2744 offset = CONST_LOW_PART (offset);
2746 high = mips_force_temporary (temp, high);
2747 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2749 return plus_constant (reg, offset);
2752 /* The __tls_get_attr symbol. */
2753 static GTY(()) rtx mips_tls_symbol;
2755 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2756 the TLS symbol we are referencing and TYPE is the symbol type to use
2757 (either global dynamic or local dynamic). V0 is an RTX for the
2758 return value location. */
2761 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2765 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2767 if (!mips_tls_symbol)
2768 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2770 loc = mips_unspec_address (sym, type);
2774 emit_insn (gen_rtx_SET (Pmode, a0,
2775 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2776 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2777 const0_rtx, NULL_RTX, false);
2778 RTL_CONST_CALL_P (insn) = 1;
2779 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2780 insn = get_insns ();
2787 /* Return a pseudo register that contains the current thread pointer. */
2794 tp = gen_reg_rtx (Pmode);
2795 if (Pmode == DImode)
2796 emit_insn (gen_tls_get_tp_di (tp));
2798 emit_insn (gen_tls_get_tp_si (tp));
2802 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2803 its address. The return value will be both a valid address and a valid
2804 SET_SRC (either a REG or a LO_SUM). */
2807 mips_legitimize_tls_address (rtx loc)
2809 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2810 enum tls_model model;
2814 sorry ("MIPS16 TLS");
2815 return gen_reg_rtx (Pmode);
2818 model = SYMBOL_REF_TLS_MODEL (loc);
2819 /* Only TARGET_ABICALLS code can have more than one module; other
2820 code must be be static and should not use a GOT. All TLS models
2821 reduce to local exec in this situation. */
2822 if (!TARGET_ABICALLS)
2823 model = TLS_MODEL_LOCAL_EXEC;
2827 case TLS_MODEL_GLOBAL_DYNAMIC:
2828 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2829 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2830 dest = gen_reg_rtx (Pmode);
2831 emit_libcall_block (insn, dest, v0, loc);
2834 case TLS_MODEL_LOCAL_DYNAMIC:
2835 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2836 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2837 tmp1 = gen_reg_rtx (Pmode);
2839 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2840 share the LDM result with other LD model accesses. */
2841 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2843 emit_libcall_block (insn, tmp1, v0, eqv);
2845 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2846 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2847 mips_unspec_address (loc, SYMBOL_DTPREL));
2850 case TLS_MODEL_INITIAL_EXEC:
2851 tp = mips_get_tp ();
2852 tmp1 = gen_reg_rtx (Pmode);
2853 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2854 if (Pmode == DImode)
2855 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2857 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2858 dest = gen_reg_rtx (Pmode);
2859 emit_insn (gen_add3_insn (dest, tmp1, tp));
2862 case TLS_MODEL_LOCAL_EXEC:
2863 tp = mips_get_tp ();
2864 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2865 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2866 mips_unspec_address (loc, SYMBOL_TPREL));
2875 /* If X is not a valid address for mode MODE, force it into a register. */
2878 mips_force_address (rtx x, enum machine_mode mode)
2880 if (!mips_legitimate_address_p (mode, x, false))
2881 x = force_reg (Pmode, x);
2885 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2886 be legitimized in a way that the generic machinery might not expect,
2887 return a new address, otherwise return NULL. MODE is the mode of
2888 the memory being accessed. */
2891 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2892 enum machine_mode mode)
2895 HOST_WIDE_INT offset;
2897 if (mips_tls_symbol_p (x))
2898 return mips_legitimize_tls_address (x);
2900 /* See if the address can split into a high part and a LO_SUM. */
2901 if (mips_split_symbol (NULL, x, mode, &addr))
2902 return mips_force_address (addr, mode);
2904 /* Handle BASE + OFFSET using mips_add_offset. */
2905 mips_split_plus (x, &base, &offset);
2908 if (!mips_valid_base_register_p (base, mode, false))
2909 base = copy_to_mode_reg (Pmode, base);
2910 addr = mips_add_offset (NULL, base, offset);
2911 return mips_force_address (addr, mode);
2917 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2920 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2922 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2923 enum machine_mode mode;
2924 unsigned int i, num_ops;
2927 mode = GET_MODE (dest);
2928 num_ops = mips_build_integer (codes, value);
2930 /* Apply each binary operation to X. Invariant: X is a legitimate
2931 source operand for a SET pattern. */
2932 x = GEN_INT (codes[0].value);
2933 for (i = 1; i < num_ops; i++)
2935 if (!can_create_pseudo_p ())
2937 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2941 x = force_reg (mode, x);
2942 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2945 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2948 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2949 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2953 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2957 /* Split moves of big integers into smaller pieces. */
2958 if (splittable_const_int_operand (src, mode))
2960 mips_move_integer (dest, dest, INTVAL (src));
2964 /* Split moves of symbolic constants into high/low pairs. */
2965 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2967 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2971 /* Generate the appropriate access sequences for TLS symbols. */
2972 if (mips_tls_symbol_p (src))
2974 mips_emit_move (dest, mips_legitimize_tls_address (src));
2978 /* If we have (const (plus symbol offset)), and that expression cannot
2979 be forced into memory, load the symbol first and add in the offset.
2980 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2981 forced into memory, as it usually produces better code. */
2982 split_const (src, &base, &offset);
2983 if (offset != const0_rtx
2984 && (targetm.cannot_force_const_mem (mode, src)
2985 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2987 base = mips_force_temporary (dest, base);
2988 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2992 src = force_const_mem (mode, src);
2994 /* When using explicit relocs, constant pool references are sometimes
2995 not legitimate addresses. */
2996 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2997 mips_emit_move (dest, src);
3000 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3001 sequence that is valid. */
3004 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3006 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3008 mips_emit_move (dest, force_reg (mode, src));
3012 /* We need to deal with constants that would be legitimate
3013 immediate_operands but aren't legitimate move_operands. */
3014 if (CONSTANT_P (src) && !move_operand (src, mode))
3016 mips_legitimize_const_move (mode, dest, src);
3017 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3023 /* Return true if value X in context CONTEXT is a small-data address
3024 that can be rewritten as a LO_SUM. */
3027 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3029 enum mips_symbol_type symbol_type;
3031 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3032 && !mips_split_p[SYMBOL_GP_RELATIVE]
3033 && mips_symbolic_constant_p (x, context, &symbol_type)
3034 && symbol_type == SYMBOL_GP_RELATIVE);
3037 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3038 containing MEM, or null if none. */
3041 mips_small_data_pattern_1 (rtx *loc, void *data)
3043 enum mips_symbol_context context;
3045 if (GET_CODE (*loc) == LO_SUM)
3050 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3055 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3056 return mips_rewrite_small_data_p (*loc, context);
3059 /* Return true if OP refers to small data symbols directly, not through
3063 mips_small_data_pattern_p (rtx op)
3065 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3068 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3069 DATA is the containing MEM, or null if none. */
3072 mips_rewrite_small_data_1 (rtx *loc, void *data)
3074 enum mips_symbol_context context;
3078 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3082 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3083 if (mips_rewrite_small_data_p (*loc, context))
3084 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3086 if (GET_CODE (*loc) == LO_SUM)
3092 /* Rewrite instruction pattern PATTERN so that it refers to small data
3093 using explicit relocations. */
3096 mips_rewrite_small_data (rtx pattern)
3098 pattern = copy_insn (pattern);
3099 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3103 /* We need a lot of little routines to check the range of MIPS16 immediate
3107 m16_check_op (rtx op, int low, int high, int mask)
3109 return (CONST_INT_P (op)
3110 && IN_RANGE (INTVAL (op), low, high)
3111 && (INTVAL (op) & mask) == 0);
3115 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3117 return m16_check_op (op, 0x1, 0x8, 0);
3121 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3123 return m16_check_op (op, -0x8, 0x7, 0);
3127 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3129 return m16_check_op (op, -0x7, 0x8, 0);
3133 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3135 return m16_check_op (op, -0x10, 0xf, 0);
3139 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3141 return m16_check_op (op, -0xf, 0x10, 0);
3145 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3147 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3151 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3153 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3157 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3159 return m16_check_op (op, -0x80, 0x7f, 0);
3163 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3165 return m16_check_op (op, -0x7f, 0x80, 0);
3169 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3171 return m16_check_op (op, 0x0, 0xff, 0);
3175 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3177 return m16_check_op (op, -0xff, 0x0, 0);
3181 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3183 return m16_check_op (op, -0x1, 0xfe, 0);
3187 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3189 return m16_check_op (op, 0x0, 0xff << 2, 3);
3193 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3195 return m16_check_op (op, -0xff << 2, 0x0, 3);
3199 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3201 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3205 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3207 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3210 /* The cost of loading values from the constant pool. It should be
3211 larger than the cost of any constant we want to synthesize inline. */
3212 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3214 /* Return the cost of X when used as an operand to the MIPS16 instruction
3215 that implements CODE. Return -1 if there is no such instruction, or if
3216 X is not a valid immediate operand for it. */
3219 mips16_constant_cost (int code, HOST_WIDE_INT x)
3226 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3227 other shifts are extended. The shift patterns truncate the shift
3228 count to the right size, so there are no out-of-range values. */
3229 if (IN_RANGE (x, 1, 8))
3231 return COSTS_N_INSNS (1);
3234 if (IN_RANGE (x, -128, 127))
3236 if (SMALL_OPERAND (x))
3237 return COSTS_N_INSNS (1);
3241 /* Like LE, but reject the always-true case. */
3245 /* We add 1 to the immediate and use SLT. */
3248 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3251 if (IN_RANGE (x, 0, 255))
3253 if (SMALL_OPERAND_UNSIGNED (x))
3254 return COSTS_N_INSNS (1);
3259 /* Equality comparisons with 0 are cheap. */
3269 /* Return true if there is a non-MIPS16 instruction that implements CODE
3270 and if that instruction accepts X as an immediate operand. */
3273 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3280 /* All shift counts are truncated to a valid constant. */
3285 /* Likewise rotates, if the target supports rotates at all. */
3291 /* These instructions take 16-bit unsigned immediates. */
3292 return SMALL_OPERAND_UNSIGNED (x);
3297 /* These instructions take 16-bit signed immediates. */
3298 return SMALL_OPERAND (x);
3304 /* The "immediate" forms of these instructions are really
3305 implemented as comparisons with register 0. */
3310 /* Likewise, meaning that the only valid immediate operand is 1. */
3314 /* We add 1 to the immediate and use SLT. */
3315 return SMALL_OPERAND (x + 1);
3318 /* Likewise SLTU, but reject the always-true case. */
3319 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3323 /* The bit position and size are immediate operands. */
3324 return ISA_HAS_EXT_INS;
3327 /* By default assume that $0 can be used for 0. */
3332 /* Return the cost of binary operation X, given that the instruction
3333 sequence for a word-sized or smaller operation has cost SINGLE_COST
3334 and that the sequence of a double-word operation has cost DOUBLE_COST.
3335 If SPEED is true, optimize for speed otherwise optimize for size. */
3338 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3342 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3347 + set_src_cost (XEXP (x, 0), speed)
3348 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3351 /* Return the cost of floating-point multiplications of mode MODE. */
3354 mips_fp_mult_cost (enum machine_mode mode)
3356 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3359 /* Return the cost of floating-point divisions of mode MODE. */
3362 mips_fp_div_cost (enum machine_mode mode)
3364 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3367 /* Return the cost of sign-extending OP to mode MODE, not including the
3368 cost of OP itself. */
3371 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3374 /* Extended loads are as cheap as unextended ones. */
3377 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3378 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3381 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3382 /* We can use SEB or SEH. */
3383 return COSTS_N_INSNS (1);
3385 /* We need to use a shift left and a shift right. */
3386 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3389 /* Return the cost of zero-extending OP to mode MODE, not including the
3390 cost of OP itself. */
3393 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3396 /* Extended loads are as cheap as unextended ones. */
3399 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3400 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3401 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3403 if (GENERATE_MIPS16E)
3404 /* We can use ZEB or ZEH. */
3405 return COSTS_N_INSNS (1);
3408 /* We need to load 0xff or 0xffff into a register and use AND. */
3409 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3411 /* We can use ANDI. */
3412 return COSTS_N_INSNS (1);
3415 /* Implement TARGET_RTX_COSTS. */
3418 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3419 int *total, bool speed)
3421 enum machine_mode mode = GET_MODE (x);
3422 bool float_mode_p = FLOAT_MODE_P (mode);
3426 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3427 appear in the instruction stream, and the cost of a comparison is
3428 really the cost of the branch or scc condition. At the time of
3429 writing, GCC only uses an explicit outer COMPARE code when optabs
3430 is testing whether a constant is expensive enough to force into a
3431 register. We want optabs to pass such constants through the MIPS
3432 expanders instead, so make all constants very cheap here. */
3433 if (outer_code == COMPARE)
3435 gcc_assert (CONSTANT_P (x));
3443 /* Treat *clear_upper32-style ANDs as having zero cost in the
3444 second operand. The cost is entirely in the first operand.
3446 ??? This is needed because we would otherwise try to CSE
3447 the constant operand. Although that's the right thing for
3448 instructions that continue to be a register operation throughout
3449 compilation, it is disastrous for instructions that could
3450 later be converted into a memory operation. */
3452 && outer_code == AND
3453 && UINTVAL (x) == 0xffffffff)
3461 cost = mips16_constant_cost (outer_code, INTVAL (x));
3470 /* When not optimizing for size, we care more about the cost
3471 of hot code, and hot code is often in a loop. If a constant
3472 operand needs to be forced into a register, we will often be
3473 able to hoist the constant load out of the loop, so the load
3474 should not contribute to the cost. */
3475 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3487 if (force_to_mem_operand (x, VOIDmode))
3489 *total = COSTS_N_INSNS (1);
3492 cost = mips_const_insns (x);
3495 /* If the constant is likely to be stored in a GPR, SETs of
3496 single-insn constants are as cheap as register sets; we
3497 never want to CSE them.
3499 Don't reduce the cost of storing a floating-point zero in
3500 FPRs. If we have a zero in an FPR for other reasons, we
3501 can get better cfg-cleanup and delayed-branch results by
3502 using it consistently, rather than using $0 sometimes and
3503 an FPR at other times. Also, moves between floating-point
3504 registers are sometimes cheaper than (D)MTC1 $0. */
3506 && outer_code == SET
3507 && !(float_mode_p && TARGET_HARD_FLOAT))
3509 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3510 want to CSE the constant itself. It is usually better to
3511 have N copies of the last operation in the sequence and one
3512 shared copy of the other operations. (Note that this is
3513 not true for MIPS16 code, where the final operation in the
3514 sequence is often an extended instruction.)
3516 Also, if we have a CONST_INT, we don't know whether it is
3517 for a word or doubleword operation, so we cannot rely on
3518 the result of mips_build_integer. */
3519 else if (!TARGET_MIPS16
3520 && (outer_code == SET || mode == VOIDmode))
3522 *total = COSTS_N_INSNS (cost);
3525 /* The value will need to be fetched from the constant pool. */
3526 *total = CONSTANT_POOL_COST;
3530 /* If the address is legitimate, return the number of
3531 instructions it needs. */
3533 cost = mips_address_insns (addr, mode, true);
3536 *total = COSTS_N_INSNS (cost + 1);
3539 /* Check for a scaled indexed address. */
3540 if (mips_lwxs_address_p (addr))
3542 *total = COSTS_N_INSNS (2);
3545 /* Otherwise use the default handling. */
3549 *total = COSTS_N_INSNS (6);
3553 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3557 /* Check for a *clear_upper32 pattern and treat it like a zero
3558 extension. See the pattern's comment for details. */
3561 && CONST_INT_P (XEXP (x, 1))
3562 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3564 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3565 + set_src_cost (XEXP (x, 0), speed));
3572 /* Double-word operations use two single-word operations. */
3573 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3582 if (CONSTANT_P (XEXP (x, 1)))
3583 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3586 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3592 *total = mips_cost->fp_add;
3594 *total = COSTS_N_INSNS (4);
3598 /* Low-part immediates need an extended MIPS16 instruction. */
3599 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3600 + set_src_cost (XEXP (x, 0), speed));
3615 /* Branch comparisons have VOIDmode, so use the first operand's
3617 mode = GET_MODE (XEXP (x, 0));
3618 if (FLOAT_MODE_P (mode))
3620 *total = mips_cost->fp_add;
3623 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3629 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3630 && TARGET_FUSED_MADD
3631 && !HONOR_NANS (mode)
3632 && !HONOR_SIGNED_ZEROS (mode))
3634 /* See if we can use NMADD or NMSUB. See mips.md for the
3635 associated patterns. */
3636 rtx op0 = XEXP (x, 0);
3637 rtx op1 = XEXP (x, 1);
3638 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3640 *total = (mips_fp_mult_cost (mode)
3641 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3642 + set_src_cost (XEXP (op0, 1), speed)
3643 + set_src_cost (op1, speed));
3646 if (GET_CODE (op1) == MULT)
3648 *total = (mips_fp_mult_cost (mode)
3649 + set_src_cost (op0, speed)
3650 + set_src_cost (XEXP (op1, 0), speed)
3651 + set_src_cost (XEXP (op1, 1), speed));
3660 /* If this is part of a MADD or MSUB, treat the PLUS as
3663 && TARGET_FUSED_MADD
3664 && GET_CODE (XEXP (x, 0)) == MULT)
3667 *total = mips_cost->fp_add;
3671 /* Double-word operations require three single-word operations and
3672 an SLTU. The MIPS16 version then needs to move the result of
3673 the SLTU from $24 to a MIPS16 register. */
3674 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3675 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3681 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3682 && TARGET_FUSED_MADD
3683 && !HONOR_NANS (mode)
3684 && HONOR_SIGNED_ZEROS (mode))
3686 /* See if we can use NMADD or NMSUB. See mips.md for the
3687 associated patterns. */
3688 rtx op = XEXP (x, 0);
3689 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3690 && GET_CODE (XEXP (op, 0)) == MULT)
3692 *total = (mips_fp_mult_cost (mode)
3693 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3694 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3695 + set_src_cost (XEXP (op, 1), speed));
3701 *total = mips_cost->fp_add;
3703 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3708 *total = mips_fp_mult_cost (mode);
3709 else if (mode == DImode && !TARGET_64BIT)
3710 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3711 where the mulsidi3 always includes an MFHI and an MFLO. */
3713 ? mips_cost->int_mult_si * 3 + 6
3714 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3716 *total = (ISA_HAS_MUL3 ? 1 : 2);
3717 else if (mode == DImode)
3718 *total = mips_cost->int_mult_di;
3720 *total = mips_cost->int_mult_si;
3724 /* Check for a reciprocal. */
3727 && flag_unsafe_math_optimizations
3728 && XEXP (x, 0) == CONST1_RTX (mode))
3730 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3731 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3732 division as being free. */
3733 *total = set_src_cost (XEXP (x, 1), speed);
3735 *total = (mips_fp_div_cost (mode)
3736 + set_src_cost (XEXP (x, 1), speed));
3745 *total = mips_fp_div_cost (mode);
3754 /* It is our responsibility to make division by a power of 2
3755 as cheap as 2 register additions if we want the division
3756 expanders to be used for such operations; see the setting
3757 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3758 should always produce shorter code than using
3759 expand_sdiv2_pow2. */
3761 && CONST_INT_P (XEXP (x, 1))
3762 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3764 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
3767 *total = COSTS_N_INSNS (mips_idiv_insns ());
3769 else if (mode == DImode)
3770 *total = mips_cost->int_div_di;
3772 *total = mips_cost->int_div_si;
3776 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3780 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3784 case UNSIGNED_FLOAT:
3787 case FLOAT_TRUNCATE:
3788 *total = mips_cost->fp_add;
3796 /* Implement TARGET_ADDRESS_COST. */
3799 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3801 return mips_address_insns (addr, SImode, false);
3804 /* Information about a single instruction in a multi-instruction
3806 struct mips_multi_member {
3807 /* True if this is a label, false if it is code. */
3810 /* The output_asm_insn format of the instruction. */
3813 /* The operands to the instruction. */
3814 rtx operands[MAX_RECOG_OPERANDS];
3816 typedef struct mips_multi_member mips_multi_member;
3818 /* Vector definitions for the above. */
3819 DEF_VEC_O(mips_multi_member);
3820 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3822 /* The instructions that make up the current multi-insn sequence. */
3823 static VEC (mips_multi_member, heap) *mips_multi_members;
3825 /* How many instructions (as opposed to labels) are in the current
3826 multi-insn sequence. */
3827 static unsigned int mips_multi_num_insns;
3829 /* Start a new multi-insn sequence. */
3832 mips_multi_start (void)
3834 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3835 mips_multi_num_insns = 0;
3838 /* Add a new, uninitialized member to the current multi-insn sequence. */
3840 static struct mips_multi_member *
3841 mips_multi_add (void)
3843 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3846 /* Add a normal insn with the given asm format to the current multi-insn
3847 sequence. The other arguments are a null-terminated list of operands. */
3850 mips_multi_add_insn (const char *format, ...)
3852 struct mips_multi_member *member;
3857 member = mips_multi_add ();
3858 member->is_label_p = false;
3859 member->format = format;
3860 va_start (ap, format);
3862 while ((op = va_arg (ap, rtx)))
3863 member->operands[i++] = op;
3865 mips_multi_num_insns++;
3868 /* Add the given label definition to the current multi-insn sequence.
3869 The definition should include the colon. */
3872 mips_multi_add_label (const char *label)
3874 struct mips_multi_member *member;
3876 member = mips_multi_add ();
3877 member->is_label_p = true;
3878 member->format = label;
3881 /* Return the index of the last member of the current multi-insn sequence. */
3884 mips_multi_last_index (void)
3886 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3889 /* Add a copy of an existing instruction to the current multi-insn
3890 sequence. I is the index of the instruction that should be copied. */
3893 mips_multi_copy_insn (unsigned int i)
3895 struct mips_multi_member *member;
3897 member = mips_multi_add ();
3898 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
3900 gcc_assert (!member->is_label_p);
3903 /* Change the operand of an existing instruction in the current
3904 multi-insn sequence. I is the index of the instruction,
3905 OP is the index of the operand, and X is the new value. */
3908 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
3910 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
3913 /* Write out the asm code for the current multi-insn sequence. */
3916 mips_multi_write (void)
3918 struct mips_multi_member *member;
3921 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
3922 if (member->is_label_p)
3923 fprintf (asm_out_file, "%s\n", member->format);
3925 output_asm_insn (member->format, member->operands);
3928 /* Return one word of double-word value OP, taking into account the fixed
3929 endianness of certain registers. HIGH_P is true to select the high part,
3930 false to select the low part. */
3933 mips_subword (rtx op, bool high_p)
3935 unsigned int byte, offset;
3936 enum machine_mode mode;
3938 mode = GET_MODE (op);
3939 if (mode == VOIDmode)
3940 mode = TARGET_64BIT ? TImode : DImode;
3942 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3943 byte = UNITS_PER_WORD;
3947 if (FP_REG_RTX_P (op))
3949 /* Paired FPRs are always ordered little-endian. */
3950 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3951 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3955 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3957 return simplify_gen_subreg (word_mode, op, mode, byte);
3960 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3963 mips_split_64bit_move_p (rtx dest, rtx src)
3968 /* FPR-to-FPR moves can be done in a single instruction, if they're
3970 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3973 /* Check for floating-point loads and stores. */
3974 if (ISA_HAS_LDC1_SDC1)
3976 if (FP_REG_RTX_P (dest) && MEM_P (src))
3978 if (FP_REG_RTX_P (src) && MEM_P (dest))
3984 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3985 this function handles 64-bit moves for which mips_split_64bit_move_p
3986 holds. For 64-bit targets, this function handles 128-bit moves. */
3989 mips_split_doubleword_move (rtx dest, rtx src)
3993 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3995 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3996 emit_insn (gen_move_doubleword_fprdi (dest, src));
3997 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3998 emit_insn (gen_move_doubleword_fprdf (dest, src));
3999 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4000 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4001 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4002 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4003 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4004 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4005 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4006 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4007 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4008 emit_insn (gen_move_doubleword_fprtf (dest, src));
4012 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4014 low_dest = mips_subword (dest, false);
4015 mips_emit_move (low_dest, mips_subword (src, false));
4017 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4019 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4021 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4023 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4025 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4027 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4031 /* The operation can be split into two normal moves. Decide in
4032 which order to do them. */
4033 low_dest = mips_subword (dest, false);
4034 if (REG_P (low_dest)
4035 && reg_overlap_mentioned_p (low_dest, src))
4037 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4038 mips_emit_move (low_dest, mips_subword (src, false));
4042 mips_emit_move (low_dest, mips_subword (src, false));
4043 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4048 /* Return the appropriate instructions to move SRC into DEST. Assume
4049 that SRC is operand 1 and DEST is operand 0. */
4052 mips_output_move (rtx dest, rtx src)
4054 enum rtx_code dest_code, src_code;
4055 enum machine_mode mode;
4056 enum mips_symbol_type symbol_type;
4059 dest_code = GET_CODE (dest);
4060 src_code = GET_CODE (src);
4061 mode = GET_MODE (dest);
4062 dbl_p = (GET_MODE_SIZE (mode) == 8);
4064 if (dbl_p && mips_split_64bit_move_p (dest, src))
4067 if ((src_code == REG && GP_REG_P (REGNO (src)))
4068 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4070 if (dest_code == REG)
4072 if (GP_REG_P (REGNO (dest)))
4073 return "move\t%0,%z1";
4075 /* Moves to HI are handled by special .md insns. */
4076 if (REGNO (dest) == LO_REGNUM)
4079 if (DSP_ACC_REG_P (REGNO (dest)))
4081 static char retval[] = "mt__\t%z1,%q0";
4083 retval[2] = reg_names[REGNO (dest)][4];
4084 retval[3] = reg_names[REGNO (dest)][5];
4088 if (FP_REG_P (REGNO (dest)))
4089 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4091 if (ALL_COP_REG_P (REGNO (dest)))
4093 static char retval[] = "dmtc_\t%z1,%0";
4095 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4096 return dbl_p ? retval : retval + 1;
4099 if (dest_code == MEM)
4100 switch (GET_MODE_SIZE (mode))
4102 case 1: return "sb\t%z1,%0";
4103 case 2: return "sh\t%z1,%0";
4104 case 4: return "sw\t%z1,%0";
4105 case 8: return "sd\t%z1,%0";
4108 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4110 if (src_code == REG)
4112 /* Moves from HI are handled by special .md insns. */
4113 if (REGNO (src) == LO_REGNUM)
4115 /* When generating VR4120 or VR4130 code, we use MACC and
4116 DMACC instead of MFLO. This avoids both the normal
4117 MIPS III HI/LO hazards and the errata related to
4120 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4124 if (DSP_ACC_REG_P (REGNO (src)))
4126 static char retval[] = "mf__\t%0,%q1";
4128 retval[2] = reg_names[REGNO (src)][4];
4129 retval[3] = reg_names[REGNO (src)][5];
4133 if (FP_REG_P (REGNO (src)))
4134 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4136 if (ALL_COP_REG_P (REGNO (src)))
4138 static char retval[] = "dmfc_\t%0,%1";
4140 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4141 return dbl_p ? retval : retval + 1;
4144 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4145 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4148 if (src_code == MEM)
4149 switch (GET_MODE_SIZE (mode))
4151 case 1: return "lbu\t%0,%1";
4152 case 2: return "lhu\t%0,%1";
4153 case 4: return "lw\t%0,%1";
4154 case 8: return "ld\t%0,%1";
4157 if (src_code == CONST_INT)
4159 /* Don't use the X format for the operand itself, because that
4160 will give out-of-range numbers for 64-bit hosts and 32-bit
4163 return "li\t%0,%1\t\t\t# %X1";
4165 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4168 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4172 if (src_code == HIGH)
4173 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4175 if (CONST_GP_P (src))
4176 return "move\t%0,%1";
4178 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4179 && mips_lo_relocs[symbol_type] != 0)
4181 /* A signed 16-bit constant formed by applying a relocation
4182 operator to a symbolic address. */
4183 gcc_assert (!mips_split_p[symbol_type]);
4184 return "li\t%0,%R1";
4187 if (symbolic_operand (src, VOIDmode))
4189 gcc_assert (TARGET_MIPS16
4190 ? TARGET_MIPS16_TEXT_LOADS
4191 : !TARGET_EXPLICIT_RELOCS);
4192 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4195 if (src_code == REG && FP_REG_P (REGNO (src)))
4197 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4199 if (GET_MODE (dest) == V2SFmode)
4200 return "mov.ps\t%0,%1";
4202 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4205 if (dest_code == MEM)
4206 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4208 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4210 if (src_code == MEM)
4211 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4213 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4215 static char retval[] = "l_c_\t%0,%1";
4217 retval[1] = (dbl_p ? 'd' : 'w');
4218 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4221 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4223 static char retval[] = "s_c_\t%1,%0";
4225 retval[1] = (dbl_p ? 'd' : 'w');
4226 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4232 /* Return true if CMP1 is a suitable second operand for integer ordering
4233 test CODE. See also the *sCC patterns in mips.md. */
4236 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4242 return reg_or_0_operand (cmp1, VOIDmode);
4246 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4250 return arith_operand (cmp1, VOIDmode);
4253 return sle_operand (cmp1, VOIDmode);
4256 return sleu_operand (cmp1, VOIDmode);
4263 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4264 integer ordering test *CODE, or if an equivalent combination can
4265 be formed by adjusting *CODE and *CMP1. When returning true, update
4266 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4270 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4271 enum machine_mode mode)
4273 HOST_WIDE_INT plus_one;
4275 if (mips_int_order_operand_ok_p (*code, *cmp1))
4278 if (CONST_INT_P (*cmp1))
4282 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4283 if (INTVAL (*cmp1) < plus_one)
4286 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4292 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4296 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4307 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4308 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4309 is nonnull, it's OK to set TARGET to the inverse of the result and
4310 flip *INVERT_PTR instead. */
4313 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4314 rtx target, rtx cmp0, rtx cmp1)
4316 enum machine_mode mode;
4318 /* First see if there is a MIPS instruction that can do this operation.
4319 If not, try doing the same for the inverse operation. If that also
4320 fails, force CMP1 into a register and try again. */
4321 mode = GET_MODE (cmp0);
4322 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4323 mips_emit_binary (code, target, cmp0, cmp1);
4326 enum rtx_code inv_code = reverse_condition (code);
4327 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4329 cmp1 = force_reg (mode, cmp1);
4330 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4332 else if (invert_ptr == 0)
4336 inv_target = mips_force_binary (GET_MODE (target),
4337 inv_code, cmp0, cmp1);
4338 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4342 *invert_ptr = !*invert_ptr;
4343 mips_emit_binary (inv_code, target, cmp0, cmp1);
4348 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4349 The register will have the same mode as CMP0. */
4352 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4354 if (cmp1 == const0_rtx)
4357 if (uns_arith_operand (cmp1, VOIDmode))
4358 return expand_binop (GET_MODE (cmp0), xor_optab,
4359 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4361 return expand_binop (GET_MODE (cmp0), sub_optab,
4362 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4365 /* Convert *CODE into a code that can be used in a floating-point
4366 scc instruction (C.cond.fmt). Return true if the values of
4367 the condition code registers will be inverted, with 0 indicating
4368 that the condition holds. */
4371 mips_reversed_fp_cond (enum rtx_code *code)
4378 *code = reverse_condition_maybe_unordered (*code);
4386 /* Convert a comparison into something that can be used in a branch or
4387 conditional move. On entry, *OP0 and *OP1 are the values being
4388 compared and *CODE is the code used to compare them.
4390 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4391 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4392 otherwise any standard branch condition can be used. The standard branch
4395 - EQ or NE between two registers.
4396 - any comparison between a register and zero. */
4399 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4404 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4406 if (!need_eq_ne_p && *op1 == const0_rtx)
4408 else if (*code == EQ || *code == NE)
4412 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4416 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4420 /* The comparison needs a separate scc instruction. Store the
4421 result of the scc in *OP0 and compare it against zero. */
4422 bool invert = false;
4423 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4424 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4425 *code = (invert ? EQ : NE);
4429 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4431 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4432 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4438 enum rtx_code cmp_code;
4440 /* Floating-point tests use a separate C.cond.fmt comparison to
4441 set a condition code register. The branch or conditional move
4442 will then compare that register against zero.
4444 Set CMP_CODE to the code of the comparison instruction and
4445 *CODE to the code that the branch or move should use. */
4447 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4449 ? gen_reg_rtx (CCmode)
4450 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4452 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4456 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4457 and OPERAND[3]. Store the result in OPERANDS[0].
4459 On 64-bit targets, the mode of the comparison and target will always be
4460 SImode, thus possibly narrower than that of the comparison's operands. */
4463 mips_expand_scc (rtx operands[])
4465 rtx target = operands[0];
4466 enum rtx_code code = GET_CODE (operands[1]);
4467 rtx op0 = operands[2];
4468 rtx op1 = operands[3];
4470 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4472 if (code == EQ || code == NE)
4475 && reg_imm10_operand (op1, GET_MODE (op1)))
4476 mips_emit_binary (code, target, op0, op1);
4479 rtx zie = mips_zero_if_equal (op0, op1);
4480 mips_emit_binary (code, target, zie, const0_rtx);
4484 mips_emit_int_order_test (code, 0, target, op0, op1);
4487 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4488 CODE and jump to OPERANDS[3] if the condition holds. */
4491 mips_expand_conditional_branch (rtx *operands)
4493 enum rtx_code code = GET_CODE (operands[0]);
4494 rtx op0 = operands[1];
4495 rtx op1 = operands[2];
4498 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4499 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4500 emit_jump_insn (gen_condjump (condition, operands[3]));
4505 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4506 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4509 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4510 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4515 reversed_p = mips_reversed_fp_cond (&cond);
4516 cmp_result = gen_reg_rtx (CCV2mode);
4517 emit_insn (gen_scc_ps (cmp_result,
4518 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4520 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4523 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4527 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4528 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4531 mips_expand_conditional_move (rtx *operands)
4534 enum rtx_code code = GET_CODE (operands[1]);
4535 rtx op0 = XEXP (operands[1], 0);
4536 rtx op1 = XEXP (operands[1], 1);
4538 mips_emit_compare (&code, &op0, &op1, true);
4539 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4540 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4541 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4542 operands[2], operands[3])));
4545 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4548 mips_expand_conditional_trap (rtx comparison)
4551 enum machine_mode mode;
4554 /* MIPS conditional trap instructions don't have GT or LE flavors,
4555 so we must swap the operands and convert to LT and GE respectively. */
4556 code = GET_CODE (comparison);
4563 code = swap_condition (code);
4564 op0 = XEXP (comparison, 1);
4565 op1 = XEXP (comparison, 0);
4569 op0 = XEXP (comparison, 0);
4570 op1 = XEXP (comparison, 1);
4574 mode = GET_MODE (XEXP (comparison, 0));
4575 op0 = force_reg (mode, op0);
4576 if (!arith_operand (op1, mode))
4577 op1 = force_reg (mode, op1);
4579 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4580 gen_rtx_fmt_ee (code, mode, op0, op1),
4584 /* Initialize *CUM for a call to a function of type FNTYPE. */
4587 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4589 memset (cum, 0, sizeof (*cum));
4590 cum->prototype = (fntype && prototype_p (fntype));
4591 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4594 /* Fill INFO with information about a single argument. CUM is the
4595 cumulative state for earlier arguments. MODE is the mode of this
4596 argument and TYPE is its type (if known). NAMED is true if this
4597 is a named (fixed) argument rather than a variable one. */
4600 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4601 enum machine_mode mode, const_tree type, bool named)
4603 bool doubleword_aligned_p;
4604 unsigned int num_bytes, num_words, max_regs;
4606 /* Work out the size of the argument. */
4607 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4608 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4610 /* Decide whether it should go in a floating-point register, assuming
4611 one is free. Later code checks for availability.
4613 The checks against UNITS_PER_FPVALUE handle the soft-float and
4614 single-float cases. */
4618 /* The EABI conventions have traditionally been defined in terms
4619 of TYPE_MODE, regardless of the actual type. */
4620 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4621 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4622 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4627 /* Only leading floating-point scalars are passed in
4628 floating-point registers. We also handle vector floats the same
4629 say, which is OK because they are not covered by the standard ABI. */
4630 info->fpr_p = (!cum->gp_reg_found
4631 && cum->arg_number < 2
4633 || SCALAR_FLOAT_TYPE_P (type)
4634 || VECTOR_FLOAT_TYPE_P (type))
4635 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4636 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4637 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4642 /* Scalar, complex and vector floating-point types are passed in
4643 floating-point registers, as long as this is a named rather
4644 than a variable argument. */
4645 info->fpr_p = (named
4646 && (type == 0 || FLOAT_TYPE_P (type))
4647 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4648 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4649 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4650 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4652 /* ??? According to the ABI documentation, the real and imaginary
4653 parts of complex floats should be passed in individual registers.
4654 The real and imaginary parts of stack arguments are supposed
4655 to be contiguous and there should be an extra word of padding
4658 This has two problems. First, it makes it impossible to use a
4659 single "void *" va_list type, since register and stack arguments
4660 are passed differently. (At the time of writing, MIPSpro cannot
4661 handle complex float varargs correctly.) Second, it's unclear
4662 what should happen when there is only one register free.
4664 For now, we assume that named complex floats should go into FPRs
4665 if there are two FPRs free, otherwise they should be passed in the
4666 same way as a struct containing two floats. */
4668 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4669 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4671 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4672 info->fpr_p = false;
4682 /* See whether the argument has doubleword alignment. */
4683 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4686 /* Set REG_OFFSET to the register count we're interested in.
4687 The EABI allocates the floating-point registers separately,
4688 but the other ABIs allocate them like integer registers. */
4689 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4693 /* Advance to an even register if the argument is doubleword-aligned. */
4694 if (doubleword_aligned_p)
4695 info->reg_offset += info->reg_offset & 1;
4697 /* Work out the offset of a stack argument. */
4698 info->stack_offset = cum->stack_words;
4699 if (doubleword_aligned_p)
4700 info->stack_offset += info->stack_offset & 1;
4702 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4704 /* Partition the argument between registers and stack. */
4705 info->reg_words = MIN (num_words, max_regs);
4706 info->stack_words = num_words - info->reg_words;
4709 /* INFO describes a register argument that has the normal format for the
4710 argument's mode. Return the register it uses, assuming that FPRs are
4711 available if HARD_FLOAT_P. */
4714 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4716 if (!info->fpr_p || !hard_float_p)
4717 return GP_ARG_FIRST + info->reg_offset;
4718 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4719 /* In o32, the second argument is always passed in $f14
4720 for TARGET_DOUBLE_FLOAT, regardless of whether the
4721 first argument was a word or doubleword. */
4722 return FP_ARG_FIRST + 2;
4724 return FP_ARG_FIRST + info->reg_offset;
4727 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4730 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
4732 return !TARGET_OLDABI;
4735 /* Implement TARGET_FUNCTION_ARG. */
4738 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
4739 const_tree type, bool named)
4741 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4742 struct mips_arg_info info;
4744 /* We will be called with a mode of VOIDmode after the last argument
4745 has been seen. Whatever we return will be passed to the call expander.
4746 If we need a MIPS16 fp_code, return a REG with the code stored as
4748 if (mode == VOIDmode)
4750 if (TARGET_MIPS16 && cum->fp_code != 0)
4751 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4756 mips_get_arg_info (&info, cum, mode, type, named);
4758 /* Return straight away if the whole argument is passed on the stack. */
4759 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4762 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4763 contains a double in its entirety, then that 64-bit chunk is passed
4764 in a floating-point register. */
4766 && TARGET_HARD_FLOAT
4769 && TREE_CODE (type) == RECORD_TYPE
4770 && TYPE_SIZE_UNIT (type)
4771 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4775 /* First check to see if there is any such field. */
4776 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4777 if (TREE_CODE (field) == FIELD_DECL
4778 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4779 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4780 && host_integerp (bit_position (field), 0)
4781 && int_bit_position (field) % BITS_PER_WORD == 0)
4786 /* Now handle the special case by returning a PARALLEL
4787 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4788 chunks are passed in registers. */
4790 HOST_WIDE_INT bitpos;
4793 /* assign_parms checks the mode of ENTRY_PARM, so we must
4794 use the actual mode here. */
4795 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4798 field = TYPE_FIELDS (type);
4799 for (i = 0; i < info.reg_words; i++)
4803 for (; field; field = DECL_CHAIN (field))
4804 if (TREE_CODE (field) == FIELD_DECL
4805 && int_bit_position (field) >= bitpos)
4809 && int_bit_position (field) == bitpos
4810 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4811 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4812 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4814 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4817 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4818 GEN_INT (bitpos / BITS_PER_UNIT));
4820 bitpos += BITS_PER_WORD;
4826 /* Handle the n32/n64 conventions for passing complex floating-point
4827 arguments in FPR pairs. The real part goes in the lower register
4828 and the imaginary part goes in the upper register. */
4831 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4834 enum machine_mode inner;
4837 inner = GET_MODE_INNER (mode);
4838 regno = FP_ARG_FIRST + info.reg_offset;
4839 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4841 /* Real part in registers, imaginary part on stack. */
4842 gcc_assert (info.stack_words == info.reg_words);
4843 return gen_rtx_REG (inner, regno);
4847 gcc_assert (info.stack_words == 0);
4848 real = gen_rtx_EXPR_LIST (VOIDmode,
4849 gen_rtx_REG (inner, regno),
4851 imag = gen_rtx_EXPR_LIST (VOIDmode,
4853 regno + info.reg_words / 2),
4854 GEN_INT (GET_MODE_SIZE (inner)));
4855 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4859 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4862 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4865 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
4866 const_tree type, bool named)
4868 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4869 struct mips_arg_info info;
4871 mips_get_arg_info (&info, cum, mode, type, named);
4874 cum->gp_reg_found = true;
4876 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4877 an explanation of what this code does. It assumes that we're using
4878 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4880 if (cum->arg_number < 2 && info.fpr_p)
4881 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4883 /* Advance the register count. This has the effect of setting
4884 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4885 argument required us to skip the final GPR and pass the whole
4886 argument on the stack. */
4887 if (mips_abi != ABI_EABI || !info.fpr_p)
4888 cum->num_gprs = info.reg_offset + info.reg_words;
4889 else if (info.reg_words > 0)
4890 cum->num_fprs += MAX_FPRS_PER_FMT;
4892 /* Advance the stack word count. */
4893 if (info.stack_words > 0)
4894 cum->stack_words = info.stack_offset + info.stack_words;
4899 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4902 mips_arg_partial_bytes (cumulative_args_t cum,
4903 enum machine_mode mode, tree type, bool named)
4905 struct mips_arg_info info;
4907 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
4908 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4911 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
4912 least PARM_BOUNDARY bits of alignment, but will be given anything up
4913 to STACK_BOUNDARY bits if the type requires it. */
4916 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
4918 unsigned int alignment;
4920 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4921 if (alignment < PARM_BOUNDARY)
4922 alignment = PARM_BOUNDARY;
4923 if (alignment > STACK_BOUNDARY)
4924 alignment = STACK_BOUNDARY;
4928 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4929 upward rather than downward. In other words, return true if the
4930 first byte of the stack slot has useful data, false if the last
4934 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4936 /* On little-endian targets, the first byte of every stack argument
4937 is passed in the first byte of the stack slot. */
4938 if (!BYTES_BIG_ENDIAN)
4941 /* Otherwise, integral types are padded downward: the last byte of a
4942 stack argument is passed in the last byte of the stack slot. */
4944 ? (INTEGRAL_TYPE_P (type)
4945 || POINTER_TYPE_P (type)
4946 || FIXED_POINT_TYPE_P (type))
4947 : (SCALAR_INT_MODE_P (mode)
4948 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4951 /* Big-endian o64 pads floating-point arguments downward. */
4952 if (mips_abi == ABI_O64)
4953 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4956 /* Other types are padded upward for o32, o64, n32 and n64. */
4957 if (mips_abi != ABI_EABI)
4960 /* Arguments smaller than a stack slot are padded downward. */
4961 if (mode != BLKmode)
4962 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4964 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4967 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4968 if the least significant byte of the register has useful data. Return
4969 the opposite if the most significant byte does. */
4972 mips_pad_reg_upward (enum machine_mode mode, tree type)
4974 /* No shifting is required for floating-point arguments. */
4975 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4976 return !BYTES_BIG_ENDIAN;
4978 /* Otherwise, apply the same padding to register arguments as we do
4979 to stack arguments. */
4980 return mips_pad_arg_upward (mode, type);
4983 /* Return nonzero when an argument must be passed by reference. */
4986 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
4987 enum machine_mode mode, const_tree type,
4988 bool named ATTRIBUTE_UNUSED)
4990 if (mips_abi == ABI_EABI)
4994 /* ??? How should SCmode be handled? */
4995 if (mode == DImode || mode == DFmode
4996 || mode == DQmode || mode == UDQmode
4997 || mode == DAmode || mode == UDAmode)
5000 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5001 return size == -1 || size > UNITS_PER_WORD;
5005 /* If we have a variable-sized parameter, we have no choice. */
5006 return targetm.calls.must_pass_in_stack (mode, type);
5010 /* Implement TARGET_CALLEE_COPIES. */
5013 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5014 enum machine_mode mode ATTRIBUTE_UNUSED,
5015 const_tree type ATTRIBUTE_UNUSED, bool named)
5017 return mips_abi == ABI_EABI && named;
5020 /* See whether VALTYPE is a record whose fields should be returned in
5021 floating-point registers. If so, return the number of fields and
5022 list them in FIELDS (which should have two elements). Return 0
5025 For n32 & n64, a structure with one or two fields is returned in
5026 floating-point registers as long as every field has a floating-point
5030 mips_fpr_return_fields (const_tree valtype, tree *fields)
5038 if (TREE_CODE (valtype) != RECORD_TYPE)
5042 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5044 if (TREE_CODE (field) != FIELD_DECL)
5047 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5053 fields[i++] = field;
5058 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5059 a value in the most significant part of $2/$3 if:
5061 - the target is big-endian;
5063 - the value has a structure or union type (we generalize this to
5064 cover aggregates from other languages too); and
5066 - the structure is not returned in floating-point registers. */
5069 mips_return_in_msb (const_tree valtype)
5073 return (TARGET_NEWABI
5074 && TARGET_BIG_ENDIAN
5075 && AGGREGATE_TYPE_P (valtype)
5076 && mips_fpr_return_fields (valtype, fields) == 0);
5079 /* Return true if the function return value MODE will get returned in a
5080 floating-point register. */
5083 mips_return_mode_in_fpr_p (enum machine_mode mode)
5085 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5086 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5087 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5088 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5091 /* Return the representation of an FPR return register when the
5092 value being returned in FP_RETURN has mode VALUE_MODE and the
5093 return type itself has mode TYPE_MODE. On NewABI targets,
5094 the two modes may be different for structures like:
5096 struct __attribute__((packed)) foo { float f; }
5098 where we return the SFmode value of "f" in FP_RETURN, but where
5099 the structure itself has mode BLKmode. */
5102 mips_return_fpr_single (enum machine_mode type_mode,
5103 enum machine_mode value_mode)
5107 x = gen_rtx_REG (value_mode, FP_RETURN);
5108 if (type_mode != value_mode)
5110 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5111 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5116 /* Return a composite value in a pair of floating-point registers.
5117 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5118 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5121 For n32 & n64, $f0 always holds the first value and $f2 the second.
5122 Otherwise the values are packed together as closely as possible. */
5125 mips_return_fpr_pair (enum machine_mode mode,
5126 enum machine_mode mode1, HOST_WIDE_INT offset1,
5127 enum machine_mode mode2, HOST_WIDE_INT offset2)
5131 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5132 return gen_rtx_PARALLEL
5135 gen_rtx_EXPR_LIST (VOIDmode,
5136 gen_rtx_REG (mode1, FP_RETURN),
5138 gen_rtx_EXPR_LIST (VOIDmode,
5139 gen_rtx_REG (mode2, FP_RETURN + inc),
5140 GEN_INT (offset2))));
5144 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5145 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5146 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5149 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5150 enum machine_mode mode)
5158 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5159 func = fn_decl_or_type;
5163 mode = TYPE_MODE (valtype);
5164 unsigned_p = TYPE_UNSIGNED (valtype);
5166 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5167 return values, promote the mode here too. */
5168 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5170 /* Handle structures whose fields are returned in $f0/$f2. */
5171 switch (mips_fpr_return_fields (valtype, fields))
5174 return mips_return_fpr_single (mode,
5175 TYPE_MODE (TREE_TYPE (fields[0])));
5178 return mips_return_fpr_pair (mode,
5179 TYPE_MODE (TREE_TYPE (fields[0])),
5180 int_byte_position (fields[0]),
5181 TYPE_MODE (TREE_TYPE (fields[1])),
5182 int_byte_position (fields[1]));
5185 /* If a value is passed in the most significant part of a register, see
5186 whether we have to round the mode up to a whole number of words. */
5187 if (mips_return_in_msb (valtype))
5189 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5190 if (size % UNITS_PER_WORD != 0)
5192 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5193 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5197 /* For EABI, the class of return register depends entirely on MODE.
5198 For example, "struct { some_type x; }" and "union { some_type x; }"
5199 are returned in the same way as a bare "some_type" would be.
5200 Other ABIs only use FPRs for scalar, complex or vector types. */
5201 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5202 return gen_rtx_REG (mode, GP_RETURN);
5207 /* Handle long doubles for n32 & n64. */
5209 return mips_return_fpr_pair (mode,
5211 DImode, GET_MODE_SIZE (mode) / 2);
5213 if (mips_return_mode_in_fpr_p (mode))
5215 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5216 return mips_return_fpr_pair (mode,
5217 GET_MODE_INNER (mode), 0,
5218 GET_MODE_INNER (mode),
5219 GET_MODE_SIZE (mode) / 2);
5221 return gen_rtx_REG (mode, FP_RETURN);
5225 return gen_rtx_REG (mode, GP_RETURN);
5228 /* Implement TARGET_FUNCTION_VALUE. */
5231 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5232 bool outgoing ATTRIBUTE_UNUSED)
5234 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5237 /* Implement TARGET_LIBCALL_VALUE. */
5240 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5242 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5245 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5247 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5248 Currently, R2 and F0 are only implemented here (C has no complex type). */
5251 mips_function_value_regno_p (const unsigned int regno)
5253 if (regno == GP_RETURN
5254 || regno == FP_RETURN
5255 || (LONG_DOUBLE_TYPE_SIZE == 128
5256 && FP_RETURN != GP_RETURN
5257 && regno == FP_RETURN + 2))
5263 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5264 all BLKmode objects are returned in memory. Under the n32, n64
5265 and embedded ABIs, small structures are returned in a register.
5266 Objects with varying size must still be returned in memory, of
5270 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5272 return (TARGET_OLDABI
5273 ? TYPE_MODE (type) == BLKmode
5274 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5277 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5280 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5281 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5284 CUMULATIVE_ARGS local_cum;
5285 int gp_saved, fp_saved;
5287 /* The caller has advanced CUM up to, but not beyond, the last named
5288 argument. Advance a local copy of CUM past the last "real" named
5289 argument, to find out how many registers are left over. */
5290 local_cum = *get_cumulative_args (cum);
5291 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5294 /* Found out how many registers we need to save. */
5295 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5296 fp_saved = (EABI_FLOAT_VARARGS_P
5297 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5306 ptr = plus_constant (virtual_incoming_args_rtx,
5307 REG_PARM_STACK_SPACE (cfun->decl)
5308 - gp_saved * UNITS_PER_WORD);
5309 mem = gen_frame_mem (BLKmode, ptr);
5310 set_mem_alias_set (mem, get_varargs_alias_set ());
5312 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5317 /* We can't use move_block_from_reg, because it will use
5319 enum machine_mode mode;
5322 /* Set OFF to the offset from virtual_incoming_args_rtx of
5323 the first float register. The FP save area lies below
5324 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5325 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5326 off -= fp_saved * UNITS_PER_FPREG;
5328 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5330 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5331 i += MAX_FPRS_PER_FMT)
5335 ptr = plus_constant (virtual_incoming_args_rtx, off);
5336 mem = gen_frame_mem (mode, ptr);
5337 set_mem_alias_set (mem, get_varargs_alias_set ());
5338 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5339 off += UNITS_PER_HWFPVALUE;
5343 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5344 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5345 + fp_saved * UNITS_PER_FPREG);
5348 /* Implement TARGET_BUILTIN_VA_LIST. */
5351 mips_build_builtin_va_list (void)
5353 if (EABI_FLOAT_VARARGS_P)
5355 /* We keep 3 pointers, and two offsets.
5357 Two pointers are to the overflow area, which starts at the CFA.
5358 One of these is constant, for addressing into the GPR save area
5359 below it. The other is advanced up the stack through the
5362 The third pointer is to the bottom of the GPR save area.
5363 Since the FPR save area is just below it, we can address
5364 FPR slots off this pointer.
5366 We also keep two one-byte offsets, which are to be subtracted
5367 from the constant pointers to yield addresses in the GPR and
5368 FPR save areas. These are downcounted as float or non-float
5369 arguments are used, and when they get to zero, the argument
5370 must be obtained from the overflow region. */
5371 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5374 record = lang_hooks.types.make_type (RECORD_TYPE);
5376 f_ovfl = build_decl (BUILTINS_LOCATION,
5377 FIELD_DECL, get_identifier ("__overflow_argptr"),
5379 f_gtop = build_decl (BUILTINS_LOCATION,
5380 FIELD_DECL, get_identifier ("__gpr_top"),
5382 f_ftop = build_decl (BUILTINS_LOCATION,
5383 FIELD_DECL, get_identifier ("__fpr_top"),
5385 f_goff = build_decl (BUILTINS_LOCATION,
5386 FIELD_DECL, get_identifier ("__gpr_offset"),
5387 unsigned_char_type_node);
5388 f_foff = build_decl (BUILTINS_LOCATION,
5389 FIELD_DECL, get_identifier ("__fpr_offset"),
5390 unsigned_char_type_node);
5391 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5392 warn on every user file. */
5393 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5394 array = build_array_type (unsigned_char_type_node,
5395 build_index_type (index));
5396 f_res = build_decl (BUILTINS_LOCATION,
5397 FIELD_DECL, get_identifier ("__reserved"), array);
5399 DECL_FIELD_CONTEXT (f_ovfl) = record;
5400 DECL_FIELD_CONTEXT (f_gtop) = record;
5401 DECL_FIELD_CONTEXT (f_ftop) = record;
5402 DECL_FIELD_CONTEXT (f_goff) = record;
5403 DECL_FIELD_CONTEXT (f_foff) = record;
5404 DECL_FIELD_CONTEXT (f_res) = record;
5406 TYPE_FIELDS (record) = f_ovfl;
5407 DECL_CHAIN (f_ovfl) = f_gtop;
5408 DECL_CHAIN (f_gtop) = f_ftop;
5409 DECL_CHAIN (f_ftop) = f_goff;
5410 DECL_CHAIN (f_goff) = f_foff;
5411 DECL_CHAIN (f_foff) = f_res;
5413 layout_type (record);
5416 else if (TARGET_IRIX6)
5417 /* On IRIX 6, this type is 'char *'. */
5418 return build_pointer_type (char_type_node);
5420 /* Otherwise, we use 'void *'. */
5421 return ptr_type_node;
5424 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5427 mips_va_start (tree valist, rtx nextarg)
5429 if (EABI_FLOAT_VARARGS_P)
5431 const CUMULATIVE_ARGS *cum;
5432 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5433 tree ovfl, gtop, ftop, goff, foff;
5435 int gpr_save_area_size;
5436 int fpr_save_area_size;
5439 cum = &crtl->args.info;
5441 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5443 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5445 f_ovfl = TYPE_FIELDS (va_list_type_node);
5446 f_gtop = DECL_CHAIN (f_ovfl);
5447 f_ftop = DECL_CHAIN (f_gtop);
5448 f_goff = DECL_CHAIN (f_ftop);
5449 f_foff = DECL_CHAIN (f_goff);
5451 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5453 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5455 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5457 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5459 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5462 /* Emit code to initialize OVFL, which points to the next varargs
5463 stack argument. CUM->STACK_WORDS gives the number of stack
5464 words used by named arguments. */
5465 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5466 if (cum->stack_words > 0)
5467 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5468 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5469 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5471 /* Emit code to initialize GTOP, the top of the GPR save area. */
5472 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5473 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5474 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5476 /* Emit code to initialize FTOP, the top of the FPR save area.
5477 This address is gpr_save_area_bytes below GTOP, rounded
5478 down to the next fp-aligned boundary. */
5479 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5480 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5481 fpr_offset &= -UNITS_PER_FPVALUE;
5483 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5484 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5485 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5487 /* Emit code to initialize GOFF, the offset from GTOP of the
5488 next GPR argument. */
5489 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5490 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5491 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5493 /* Likewise emit code to initialize FOFF, the offset from FTOP
5494 of the next FPR argument. */
5495 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5496 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5497 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5501 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5502 std_expand_builtin_va_start (valist, nextarg);
5506 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5509 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5515 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5517 type = build_pointer_type (type);
5519 if (!EABI_FLOAT_VARARGS_P)
5520 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5523 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5524 tree ovfl, top, off, align;
5525 HOST_WIDE_INT size, rsize, osize;
5528 f_ovfl = TYPE_FIELDS (va_list_type_node);
5529 f_gtop = DECL_CHAIN (f_ovfl);
5530 f_ftop = DECL_CHAIN (f_gtop);
5531 f_goff = DECL_CHAIN (f_ftop);
5532 f_foff = DECL_CHAIN (f_goff);
5536 TOP be the top of the GPR or FPR save area;
5537 OFF be the offset from TOP of the next register;
5538 ADDR_RTX be the address of the argument;
5539 SIZE be the number of bytes in the argument type;
5540 RSIZE be the number of bytes used to store the argument
5541 when it's in the register save area; and
5542 OSIZE be the number of bytes used to store it when it's
5543 in the stack overflow area.
5545 The code we want is:
5547 1: off &= -rsize; // round down
5550 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5555 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5556 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5560 [1] and [9] can sometimes be optimized away. */
5562 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5564 size = int_size_in_bytes (type);
5566 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5567 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5569 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5570 unshare_expr (valist), f_ftop, NULL_TREE);
5571 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5572 unshare_expr (valist), f_foff, NULL_TREE);
5574 /* When va_start saves FPR arguments to the stack, each slot
5575 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5576 argument's precision. */
5577 rsize = UNITS_PER_HWFPVALUE;
5579 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5580 (= PARM_BOUNDARY bits). This can be different from RSIZE
5583 (1) On 32-bit targets when TYPE is a structure such as:
5585 struct s { float f; };
5587 Such structures are passed in paired FPRs, so RSIZE
5588 will be 8 bytes. However, the structure only takes
5589 up 4 bytes of memory, so OSIZE will only be 4.
5591 (2) In combinations such as -mgp64 -msingle-float
5592 -fshort-double. Doubles passed in registers will then take
5593 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5594 stack take up UNITS_PER_WORD bytes. */
5595 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5599 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5600 unshare_expr (valist), f_gtop, NULL_TREE);
5601 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5602 unshare_expr (valist), f_goff, NULL_TREE);
5603 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5604 if (rsize > UNITS_PER_WORD)
5606 /* [1] Emit code for: off &= -rsize. */
5607 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5608 build_int_cst (TREE_TYPE (off), -rsize));
5609 gimplify_assign (unshare_expr (off), t, pre_p);
5614 /* [2] Emit code to branch if off == 0. */
5615 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
5616 build_int_cst (TREE_TYPE (off), 0));
5617 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5619 /* [5] Emit code for: off -= rsize. We do this as a form of
5620 post-decrement not available to C. */
5621 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5622 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5624 /* [4] Emit code for:
5625 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5626 t = fold_convert (sizetype, t);
5627 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5628 t = fold_build_pointer_plus (top, t);
5629 if (BYTES_BIG_ENDIAN && rsize > size)
5630 t = fold_build_pointer_plus_hwi (t, rsize - size);
5631 COND_EXPR_THEN (addr) = t;
5633 if (osize > UNITS_PER_WORD)
5635 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5636 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
5637 u = build_int_cst (TREE_TYPE (t), -osize);
5638 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
5639 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5640 unshare_expr (ovfl), t);
5645 /* [10, 11] Emit code for:
5646 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5648 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5649 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5650 if (BYTES_BIG_ENDIAN && osize > size)
5651 t = fold_build_pointer_plus_hwi (t, osize - size);
5653 /* String [9] and [10, 11] together. */
5655 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5656 COND_EXPR_ELSE (addr) = t;
5658 addr = fold_convert (build_pointer_type (type), addr);
5659 addr = build_va_arg_indirect_ref (addr);
5663 addr = build_va_arg_indirect_ref (addr);
5668 /* Start a definition of function NAME. MIPS16_P indicates whether the
5669 function contains MIPS16 code. */
5672 mips_start_function_definition (const char *name, bool mips16_p)
5675 fprintf (asm_out_file, "\t.set\tmips16\n");
5677 fprintf (asm_out_file, "\t.set\tnomips16\n");
5679 if (!flag_inhibit_size_directive)
5681 fputs ("\t.ent\t", asm_out_file);
5682 assemble_name (asm_out_file, name);
5683 fputs ("\n", asm_out_file);
5686 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5688 /* Start the definition proper. */
5689 assemble_name (asm_out_file, name);
5690 fputs (":\n", asm_out_file);
5693 /* End a function definition started by mips_start_function_definition. */
5696 mips_end_function_definition (const char *name)
5698 if (!flag_inhibit_size_directive)
5700 fputs ("\t.end\t", asm_out_file);
5701 assemble_name (asm_out_file, name);
5702 fputs ("\n", asm_out_file);
5706 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5709 mips_ok_for_lazy_binding_p (rtx x)
5711 return (TARGET_USE_GOT
5712 && GET_CODE (x) == SYMBOL_REF
5713 && !SYMBOL_REF_BIND_NOW_P (x)
5714 && !mips_symbol_binds_local_p (x));
5717 /* Load function address ADDR into register DEST. TYPE is as for
5718 mips_expand_call. Return true if we used an explicit lazy-binding
5722 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5724 /* If we're generating PIC, and this call is to a global function,
5725 try to allow its address to be resolved lazily. This isn't
5726 possible for sibcalls when $gp is call-saved because the value
5727 of $gp on entry to the stub would be our caller's gp, not ours. */
5728 if (TARGET_EXPLICIT_RELOCS
5729 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5730 && mips_ok_for_lazy_binding_p (addr))
5732 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5733 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5738 mips_emit_move (dest, addr);
5743 /* Each locally-defined hard-float MIPS16 function has a local symbol
5744 associated with it. This hash table maps the function symbol (FUNC)
5745 to the local symbol (LOCAL). */
5746 struct GTY(()) mips16_local_alias {
5750 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5752 /* Hash table callbacks for mips16_local_aliases. */
5755 mips16_local_aliases_hash (const void *entry)
5757 const struct mips16_local_alias *alias;
5759 alias = (const struct mips16_local_alias *) entry;
5760 return htab_hash_string (XSTR (alias->func, 0));
5764 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5766 const struct mips16_local_alias *alias1, *alias2;
5768 alias1 = (const struct mips16_local_alias *) entry1;
5769 alias2 = (const struct mips16_local_alias *) entry2;
5770 return rtx_equal_p (alias1->func, alias2->func);
5773 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5774 Return a local alias for it, creating a new one if necessary. */
5777 mips16_local_alias (rtx func)
5779 struct mips16_local_alias *alias, tmp_alias;
5782 /* Create the hash table if this is the first call. */
5783 if (mips16_local_aliases == NULL)
5784 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5785 mips16_local_aliases_eq, NULL);
5787 /* Look up the function symbol, creating a new entry if need be. */
5788 tmp_alias.func = func;
5789 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5790 gcc_assert (slot != NULL);
5792 alias = (struct mips16_local_alias *) *slot;
5795 const char *func_name, *local_name;
5798 /* Create a new SYMBOL_REF for the local symbol. The choice of
5799 __fn_local_* is based on the __fn_stub_* names that we've
5800 traditionally used for the non-MIPS16 stub. */
5801 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5802 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5803 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5804 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5806 /* Create a new structure to represent the mapping. */
5807 alias = ggc_alloc_mips16_local_alias ();
5809 alias->local = local;
5812 return alias->local;
5815 /* A chained list of functions for which mips16_build_call_stub has already
5816 generated a stub. NAME is the name of the function and FP_RET_P is true
5817 if the function returns a value in floating-point registers. */
5818 struct mips16_stub {
5819 struct mips16_stub *next;
5823 static struct mips16_stub *mips16_stubs;
5825 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5828 mips16_stub_function (const char *name)
5832 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5833 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5837 /* Return the two-character string that identifies floating-point
5838 return mode MODE in the name of a MIPS16 function stub. */
5841 mips16_call_stub_mode_suffix (enum machine_mode mode)
5845 else if (mode == DFmode)
5847 else if (mode == SCmode)
5849 else if (mode == DCmode)
5851 else if (mode == V2SFmode)
5857 /* Write instructions to move a 32-bit value between general register
5858 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5859 from GPREG to FPREG and 'f' to move in the opposite direction. */
5862 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5864 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5865 reg_names[gpreg], reg_names[fpreg]);
5868 /* Likewise for 64-bit values. */
5871 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5874 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5875 reg_names[gpreg], reg_names[fpreg]);
5876 else if (TARGET_FLOAT64)
5878 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5879 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5880 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5881 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5885 /* Move the least-significant word. */
5886 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5887 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5888 /* ...then the most significant word. */
5889 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5890 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5894 /* Write out code to move floating-point arguments into or out of
5895 general registers. FP_CODE is the code describing which arguments
5896 are present (see the comment above the definition of CUMULATIVE_ARGS
5897 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5900 mips_output_args_xfer (int fp_code, char direction)
5902 unsigned int gparg, fparg, f;
5903 CUMULATIVE_ARGS cum;
5905 /* This code only works for o32 and o64. */
5906 gcc_assert (TARGET_OLDABI);
5908 mips_init_cumulative_args (&cum, NULL);
5910 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5912 enum machine_mode mode;
5913 struct mips_arg_info info;
5917 else if ((f & 3) == 2)
5922 mips_get_arg_info (&info, &cum, mode, NULL, true);
5923 gparg = mips_arg_regno (&info, false);
5924 fparg = mips_arg_regno (&info, true);
5927 mips_output_32bit_xfer (direction, gparg, fparg);
5929 mips_output_64bit_xfer (direction, gparg, fparg);
5931 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
5935 /* Write a MIPS16 stub for the current function. This stub is used
5936 for functions which take arguments in the floating-point registers.
5937 It is normal-mode code that moves the floating-point arguments
5938 into the general registers and then jumps to the MIPS16 code. */
5941 mips16_build_function_stub (void)
5943 const char *fnname, *alias_name, *separator;
5944 char *secname, *stubname;
5949 /* Create the name of the stub, and its unique section. */
5950 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5951 alias = mips16_local_alias (symbol);
5953 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5954 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5955 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5956 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5958 /* Build a decl for the stub. */
5959 stubdecl = build_decl (BUILTINS_LOCATION,
5960 FUNCTION_DECL, get_identifier (stubname),
5961 build_function_type_list (void_type_node, NULL_TREE));
5962 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5963 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
5964 RESULT_DECL, NULL_TREE, void_type_node);
5966 /* Output a comment. */
5967 fprintf (asm_out_file, "\t# Stub function for %s (",
5968 current_function_name ());
5970 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5972 fprintf (asm_out_file, "%s%s", separator,
5973 (f & 3) == 1 ? "float" : "double");
5976 fprintf (asm_out_file, ")\n");
5978 /* Start the function definition. */
5979 assemble_start_function (stubdecl, stubname);
5980 mips_start_function_definition (stubname, false);
5982 /* If generating pic2 code, either set up the global pointer or
5984 if (TARGET_ABICALLS_PIC2)
5986 if (TARGET_ABSOLUTE_ABICALLS)
5987 fprintf (asm_out_file, "\t.option\tpic0\n");
5990 output_asm_insn ("%(.cpload\t%^%)", NULL);
5991 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5992 target function is. Use a local GOT access when loading the
5993 symbol, to cut down on the number of unnecessary GOT entries
5994 for stubs that aren't needed. */
5995 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6000 /* Load the address of the MIPS16 function into $25. Do this first so
6001 that targets with coprocessor interlocks can use an MFC1 to fill the
6003 output_asm_insn ("la\t%^,%0", &symbol);
6005 /* Move the arguments from floating-point registers to general registers. */
6006 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6008 /* Jump to the MIPS16 function. */
6009 output_asm_insn ("jr\t%^", NULL);
6011 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6012 fprintf (asm_out_file, "\t.option\tpic2\n");
6014 mips_end_function_definition (stubname);
6016 /* If the linker needs to create a dynamic symbol for the target
6017 function, it will associate the symbol with the stub (which,
6018 unlike the target function, follows the proper calling conventions).
6019 It is therefore useful to have a local alias for the target function,
6020 so that it can still be identified as MIPS16 code. As an optimization,
6021 this symbol can also be used for indirect MIPS16 references from
6022 within this file. */
6023 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6025 switch_to_section (function_section (current_function_decl));
6028 /* The current function is a MIPS16 function that returns a value in an FPR.
6029 Copy the return value from its soft-float to its hard-float location.
6030 libgcc2 has special non-MIPS16 helper functions for each case. */
6033 mips16_copy_fpr_return_value (void)
6035 rtx fn, insn, retval;
6037 enum machine_mode return_mode;
6040 return_type = DECL_RESULT (current_function_decl);
6041 return_mode = DECL_MODE (return_type);
6043 name = ACONCAT (("__mips16_ret_",
6044 mips16_call_stub_mode_suffix (return_mode),
6046 fn = mips16_stub_function (name);
6048 /* The function takes arguments in $2 (and possibly $3), so calls
6049 to it cannot be lazily bound. */
6050 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6052 /* Model the call as something that takes the GPR return value as
6053 argument and returns an "updated" value. */
6054 retval = gen_rtx_REG (return_mode, GP_RETURN);
6055 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6056 const0_rtx, NULL_RTX, false);
6057 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6060 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6061 RETVAL is the location of the return value, or null if this is
6062 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6063 arguments and FP_CODE is the code built by mips_function_arg;
6064 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6066 There are three alternatives:
6068 - If a stub was needed, emit the call and return the call insn itself.
6070 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6071 to the new target and return null.
6073 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6076 A stub is needed for calls to functions that, in normal mode,
6077 receive arguments in FPRs or return values in FPRs. The stub
6078 copies the arguments from their soft-float positions to their
6079 hard-float positions, calls the real function, then copies the
6080 return value from its hard-float position to its soft-float
6083 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6084 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6085 automatically redirects the JAL to the stub, otherwise the JAL
6086 continues to call FN directly. */
6089 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6093 struct mips16_stub *l;
6096 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6097 we were invoked with the -msoft-float option. */
6098 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6101 /* Figure out whether the value might come back in a floating-point
6103 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6105 /* We don't need to do anything if there were no floating-point
6106 arguments and the value will not be returned in a floating-point
6108 if (fp_code == 0 && !fp_ret_p)
6111 /* We don't need to do anything if this is a call to a special
6112 MIPS16 support function. */
6114 if (mips16_stub_function_p (fn))
6117 /* This code will only work for o32 and o64 abis. The other ABI's
6118 require more sophisticated support. */
6119 gcc_assert (TARGET_OLDABI);
6121 /* If we're calling via a function pointer, use one of the magic
6122 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6123 Each stub expects the function address to arrive in register $2. */
6124 if (GET_CODE (fn) != SYMBOL_REF
6125 || !call_insn_operand (fn, VOIDmode))
6128 rtx stub_fn, insn, addr;
6131 /* If this is a locally-defined and locally-binding function,
6132 avoid the stub by calling the local alias directly. */
6133 if (mips16_local_function_p (fn))
6135 *fn_ptr = mips16_local_alias (fn);
6139 /* Create a SYMBOL_REF for the libgcc.a function. */
6141 sprintf (buf, "__mips16_call_stub_%s_%d",
6142 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6145 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6146 stub_fn = mips16_stub_function (buf);
6148 /* The function uses $2 as an argument, so calls to it
6149 cannot be lazily bound. */
6150 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6152 /* Load the target function into $2. */
6153 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6154 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6156 /* Emit the call. */
6157 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6158 args_size, NULL_RTX, lazy_p);
6160 /* Tell GCC that this call does indeed use the value of $2. */
6161 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6163 /* If we are handling a floating-point return value, we need to
6164 save $18 in the function prologue. Putting a note on the
6165 call will mean that df_regs_ever_live_p ($18) will be true if the
6166 call is not eliminated, and we can check that in the prologue
6169 CALL_INSN_FUNCTION_USAGE (insn) =
6170 gen_rtx_EXPR_LIST (VOIDmode,
6171 gen_rtx_CLOBBER (VOIDmode,
6172 gen_rtx_REG (word_mode, 18)),
6173 CALL_INSN_FUNCTION_USAGE (insn));
6178 /* We know the function we are going to call. If we have already
6179 built a stub, we don't need to do anything further. */
6180 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6181 for (l = mips16_stubs; l != NULL; l = l->next)
6182 if (strcmp (l->name, fnname) == 0)
6187 const char *separator;
6188 char *secname, *stubname;
6189 tree stubid, stubdecl;
6192 /* If the function does not return in FPRs, the special stub
6196 If the function does return in FPRs, the stub section is named
6197 .mips16.call.fp.FNNAME
6199 Build a decl for the stub. */
6200 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6202 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6204 stubid = get_identifier (stubname);
6205 stubdecl = build_decl (BUILTINS_LOCATION,
6206 FUNCTION_DECL, stubid,
6207 build_function_type_list (void_type_node,
6209 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6210 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6211 RESULT_DECL, NULL_TREE,
6214 /* Output a comment. */
6215 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6217 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6221 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6223 fprintf (asm_out_file, "%s%s", separator,
6224 (f & 3) == 1 ? "float" : "double");
6227 fprintf (asm_out_file, ")\n");
6229 /* Start the function definition. */
6230 assemble_start_function (stubdecl, stubname);
6231 mips_start_function_definition (stubname, false);
6235 /* Load the address of the MIPS16 function into $25. Do this
6236 first so that targets with coprocessor interlocks can use
6237 an MFC1 to fill the delay slot. */
6238 if (TARGET_EXPLICIT_RELOCS)
6240 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6241 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6244 output_asm_insn ("la\t%^,%0", &fn);
6247 /* Move the arguments from general registers to floating-point
6249 mips_output_args_xfer (fp_code, 't');
6253 /* Jump to the previously-loaded address. */
6254 output_asm_insn ("jr\t%^", NULL);
6258 /* Save the return address in $18 and call the non-MIPS16 function.
6259 The stub's caller knows that $18 might be clobbered, even though
6260 $18 is usually a call-saved register. */
6261 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6262 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6263 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6265 /* Move the result from floating-point registers to
6266 general registers. */
6267 switch (GET_MODE (retval))
6270 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6272 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6274 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6275 TARGET_LITTLE_ENDIAN
6276 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6278 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6280 /* On 64-bit targets, complex floats are returned in
6281 a single GPR, such that "sd" on a suitably-aligned
6282 target would store the value correctly. */
6283 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6284 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6285 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6286 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6287 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6288 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6289 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6290 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6291 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6292 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6293 reg_names[GP_RETURN],
6294 reg_names[GP_RETURN],
6295 reg_names[GP_RETURN + 1]);
6300 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6304 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6305 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6309 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6315 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6318 #ifdef ASM_DECLARE_FUNCTION_SIZE
6319 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6322 mips_end_function_definition (stubname);
6324 /* Record this stub. */
6325 l = XNEW (struct mips16_stub);
6326 l->name = xstrdup (fnname);
6327 l->fp_ret_p = fp_ret_p;
6328 l->next = mips16_stubs;
6332 /* If we expect a floating-point return value, but we've built a
6333 stub which does not expect one, then we're in trouble. We can't
6334 use the existing stub, because it won't handle the floating-point
6335 value. We can't build a new stub, because the linker won't know
6336 which stub to use for the various calls in this object file.
6337 Fortunately, this case is illegal, since it means that a function
6338 was declared in two different ways in a single compilation. */
6339 if (fp_ret_p && !l->fp_ret_p)
6340 error ("cannot handle inconsistent calls to %qs", fnname);
6342 if (retval == NULL_RTX)
6343 insn = gen_call_internal_direct (fn, args_size);
6345 insn = gen_call_value_internal_direct (retval, fn, args_size);
6346 insn = mips_emit_call_insn (insn, fn, fn, false);
6348 /* If we are calling a stub which handles a floating-point return
6349 value, we need to arrange to save $18 in the prologue. We do this
6350 by marking the function call as using the register. The prologue
6351 will later see that it is used, and emit code to save it. */
6353 CALL_INSN_FUNCTION_USAGE (insn) =
6354 gen_rtx_EXPR_LIST (VOIDmode,
6355 gen_rtx_CLOBBER (VOIDmode,
6356 gen_rtx_REG (word_mode, 18)),
6357 CALL_INSN_FUNCTION_USAGE (insn));
6362 /* Expand a call of type TYPE. RESULT is where the result will go (null
6363 for "call"s and "sibcall"s), ADDR is the address of the function,
6364 ARGS_SIZE is the size of the arguments and AUX is the value passed
6365 to us by mips_function_arg. LAZY_P is true if this call already
6366 involves a lazily-bound function address (such as when calling
6367 functions through a MIPS16 hard-float stub).
6369 Return the call itself. */
6372 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6373 rtx args_size, rtx aux, bool lazy_p)
6375 rtx orig_addr, pattern, insn;
6378 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6379 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6382 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6387 if (!call_insn_operand (addr, VOIDmode))
6389 if (type == MIPS_CALL_EPILOGUE)
6390 addr = MIPS_EPILOGUE_TEMP (Pmode);
6392 addr = gen_reg_rtx (Pmode);
6393 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6398 rtx (*fn) (rtx, rtx);
6400 if (type == MIPS_CALL_SIBCALL)
6401 fn = gen_sibcall_internal;
6403 fn = gen_call_internal;
6405 pattern = fn (addr, args_size);
6407 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6409 /* Handle return values created by mips_return_fpr_pair. */
6410 rtx (*fn) (rtx, rtx, rtx, rtx);
6413 if (type == MIPS_CALL_SIBCALL)
6414 fn = gen_sibcall_value_multiple_internal;
6416 fn = gen_call_value_multiple_internal;
6418 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6419 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6420 pattern = fn (reg1, addr, args_size, reg2);
6424 rtx (*fn) (rtx, rtx, rtx);
6426 if (type == MIPS_CALL_SIBCALL)
6427 fn = gen_sibcall_value_internal;
6429 fn = gen_call_value_internal;
6431 /* Handle return values created by mips_return_fpr_single. */
6432 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6433 result = XEXP (XVECEXP (result, 0, 0), 0);
6434 pattern = fn (result, addr, args_size);
6437 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6440 /* Split call instruction INSN into a $gp-clobbering call and
6441 (where necessary) an instruction to restore $gp from its save slot.
6442 CALL_PATTERN is the pattern of the new call. */
6445 mips_split_call (rtx insn, rtx call_pattern)
6447 emit_call_insn (call_pattern);
6448 if (!find_reg_note (insn, REG_NORETURN, 0))
6449 /* Pick a temporary register that is suitable for both MIPS16 and
6450 non-MIPS16 code. $4 and $5 are used for returning complex double
6451 values in soft-float code, so $6 is the first suitable candidate. */
6452 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6455 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6458 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6460 if (!TARGET_SIBCALLS)
6463 /* Interrupt handlers need special epilogue code and therefore can't
6465 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6468 /* We can't do a sibcall if the called function is a MIPS16 function
6469 because there is no direct "jx" instruction equivalent to "jalx" to
6470 switch the ISA mode. We only care about cases where the sibling
6471 and normal calls would both be direct. */
6473 && mips_use_mips16_mode_p (decl)
6474 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6477 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6478 functions could be MIPS16 ones unless an attribute explicitly tells
6480 if (TARGET_INTERLINK_MIPS16
6482 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6483 && !mips_nomips16_decl_p (decl)
6484 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6491 /* Emit code to move general operand SRC into condition-code
6492 register DEST given that SCRATCH is a scratch TFmode FPR.
6499 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6502 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6506 /* Change the source to SFmode. */
6508 src = adjust_address (src, SFmode, 0);
6509 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6510 src = gen_rtx_REG (SFmode, true_regnum (src));
6512 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6513 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6515 mips_emit_move (copy_rtx (fp1), src);
6516 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6517 emit_insn (gen_slt_sf (dest, fp2, fp1));
6520 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6521 Assume that the areas do not overlap. */
6524 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6526 HOST_WIDE_INT offset, delta;
6527 unsigned HOST_WIDE_INT bits;
6529 enum machine_mode mode;
6532 /* Work out how many bits to move at a time. If both operands have
6533 half-word alignment, it is usually better to move in half words.
6534 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6535 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6536 Otherwise move word-sized chunks. */
6537 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6538 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6539 bits = BITS_PER_WORD / 2;
6541 bits = BITS_PER_WORD;
6543 mode = mode_for_size (bits, MODE_INT, 0);
6544 delta = bits / BITS_PER_UNIT;
6546 /* Allocate a buffer for the temporary registers. */
6547 regs = XALLOCAVEC (rtx, length / delta);
6549 /* Load as many BITS-sized chunks as possible. Use a normal load if
6550 the source has enough alignment, otherwise use left/right pairs. */
6551 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6553 regs[i] = gen_reg_rtx (mode);
6554 if (MEM_ALIGN (src) >= bits)
6555 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6558 rtx part = adjust_address (src, BLKmode, offset);
6559 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6564 /* Copy the chunks to the destination. */
6565 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6566 if (MEM_ALIGN (dest) >= bits)
6567 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6570 rtx part = adjust_address (dest, BLKmode, offset);
6571 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6575 /* Mop up any left-over bytes. */
6576 if (offset < length)
6578 src = adjust_address (src, BLKmode, offset);
6579 dest = adjust_address (dest, BLKmode, offset);
6580 move_by_pieces (dest, src, length - offset,
6581 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6585 /* Helper function for doing a loop-based block operation on memory
6586 reference MEM. Each iteration of the loop will operate on LENGTH
6589 Create a new base register for use within the loop and point it to
6590 the start of MEM. Create a new memory reference that uses this
6591 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6594 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6595 rtx *loop_reg, rtx *loop_mem)
6597 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6599 /* Although the new mem does not refer to a known location,
6600 it does keep up to LENGTH bytes of alignment. */
6601 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6602 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6605 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6606 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6607 the memory regions do not overlap. */
6610 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6611 HOST_WIDE_INT bytes_per_iter)
6613 rtx label, src_reg, dest_reg, final_src, test;
6614 HOST_WIDE_INT leftover;
6616 leftover = length % bytes_per_iter;
6619 /* Create registers and memory references for use within the loop. */
6620 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6621 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6623 /* Calculate the value that SRC_REG should have after the last iteration
6625 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6628 /* Emit the start of the loop. */
6629 label = gen_label_rtx ();
6632 /* Emit the loop body. */
6633 mips_block_move_straight (dest, src, bytes_per_iter);
6635 /* Move on to the next block. */
6636 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6637 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6639 /* Emit the loop condition. */
6640 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6641 if (Pmode == DImode)
6642 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6644 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6646 /* Mop up any left-over bytes. */
6648 mips_block_move_straight (dest, src, leftover);
6651 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6652 memory reference SRC to memory reference DEST. */
6655 mips_expand_block_move (rtx dest, rtx src, rtx length)
6657 if (CONST_INT_P (length))
6659 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6661 mips_block_move_straight (dest, src, INTVAL (length));
6666 mips_block_move_loop (dest, src, INTVAL (length),
6667 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6674 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6677 mips_expand_synci_loop (rtx begin, rtx end)
6679 rtx inc, label, end_label, cmp_result, mask, length;
6681 /* Create end_label. */
6682 end_label = gen_label_rtx ();
6684 /* Check if begin equals end. */
6685 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6686 emit_jump_insn (gen_condjump (cmp_result, end_label));
6688 /* Load INC with the cache line size (rdhwr INC,$1). */
6689 inc = gen_reg_rtx (Pmode);
6690 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
6692 /* Check if inc is 0. */
6693 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
6694 emit_jump_insn (gen_condjump (cmp_result, end_label));
6696 /* Calculate mask. */
6697 mask = mips_force_unary (Pmode, NEG, inc);
6699 /* Mask out begin by mask. */
6700 begin = mips_force_binary (Pmode, AND, begin, mask);
6702 /* Calculate length. */
6703 length = mips_force_binary (Pmode, MINUS, end, begin);
6705 /* Loop back to here. */
6706 label = gen_label_rtx ();
6709 emit_insn (gen_synci (begin));
6711 /* Update length. */
6712 mips_emit_binary (MINUS, length, length, inc);
6715 mips_emit_binary (PLUS, begin, begin, inc);
6717 /* Check if length is greater than 0. */
6718 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
6719 emit_jump_insn (gen_condjump (cmp_result, label));
6721 emit_label (end_label);
6724 /* Expand a QI or HI mode atomic memory operation.
6726 GENERATOR contains a pointer to the gen_* function that generates
6727 the SI mode underlying atomic operation using masks that we
6730 RESULT is the return register for the operation. Its value is NULL
6733 MEM is the location of the atomic access.
6735 OLDVAL is the first operand for the operation.
6737 NEWVAL is the optional second operand for the operation. Its value
6738 is NULL if unused. */
6741 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6742 rtx result, rtx mem, rtx oldval, rtx newval)
6744 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6745 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6747 enum machine_mode mode;
6749 mode = GET_MODE (mem);
6751 /* Compute the address of the containing SImode value. */
6752 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6753 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6754 force_reg (Pmode, GEN_INT (-4)));
6756 /* Create a memory reference for it. */
6757 memsi = gen_rtx_MEM (SImode, memsi_addr);
6758 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6759 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6761 /* Work out the byte offset of the QImode or HImode value,
6762 counting from the least significant byte. */
6763 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6764 if (TARGET_BIG_ENDIAN)
6765 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6767 /* Multiply by eight to convert the shift value from bytes to bits. */
6768 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6770 /* Make the final shift an SImode value, so that it can be used in
6771 SImode operations. */
6772 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6774 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6775 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6776 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6777 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6779 /* Compute the equivalent exclusive mask. */
6780 inverted_mask = gen_reg_rtx (SImode);
6781 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6782 gen_rtx_NOT (SImode, mask)));
6784 /* Shift the old value into place. */
6785 if (oldval != const0_rtx)
6787 oldval = convert_modes (SImode, mode, oldval, true);
6788 oldval = force_reg (SImode, oldval);
6789 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6792 /* Do the same for the new value. */
6793 if (newval && newval != const0_rtx)
6795 newval = convert_modes (SImode, mode, newval, true);
6796 newval = force_reg (SImode, newval);
6797 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6800 /* Do the SImode atomic access. */
6802 res = gen_reg_rtx (SImode);
6804 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6806 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6808 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6814 /* Shift and convert the result. */
6815 mips_emit_binary (AND, res, res, mask);
6816 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6817 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6821 /* Return true if it is possible to use left/right accesses for a
6822 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6823 returning true, update *OP, *LEFT and *RIGHT as follows:
6825 *OP is a BLKmode reference to the whole field.
6827 *LEFT is a QImode reference to the first byte if big endian or
6828 the last byte if little endian. This address can be used in the
6829 left-side instructions (LWL, SWL, LDL, SDL).
6831 *RIGHT is a QImode reference to the opposite end of the field and
6832 can be used in the patterning right-side instruction. */
6835 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6836 rtx *left, rtx *right)
6840 /* Check that the operand really is a MEM. Not all the extv and
6841 extzv predicates are checked. */
6845 /* Check that the size is valid. */
6846 if (width != 32 && (!TARGET_64BIT || width != 64))
6849 /* We can only access byte-aligned values. Since we are always passed
6850 a reference to the first byte of the field, it is not necessary to
6851 do anything with BITPOS after this check. */
6852 if (bitpos % BITS_PER_UNIT != 0)
6855 /* Reject aligned bitfields: we want to use a normal load or store
6856 instead of a left/right pair. */
6857 if (MEM_ALIGN (*op) >= width)
6860 /* Adjust *OP to refer to the whole field. This also has the effect
6861 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6862 *op = adjust_address (*op, BLKmode, 0);
6863 set_mem_size (*op, width / BITS_PER_UNIT);
6865 /* Get references to both ends of the field. We deliberately don't
6866 use the original QImode *OP for FIRST since the new BLKmode one
6867 might have a simpler address. */
6868 first = adjust_address (*op, QImode, 0);
6869 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6871 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6872 correspond to the MSB and RIGHT to the LSB. */
6873 if (TARGET_BIG_ENDIAN)
6874 *left = first, *right = last;
6876 *left = last, *right = first;
6881 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6882 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6883 the operation is the equivalent of:
6885 (set DEST (*_extract SRC WIDTH BITPOS))
6887 Return true on success. */
6890 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6891 HOST_WIDE_INT bitpos)
6893 rtx left, right, temp;
6895 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6896 be a paradoxical word_mode subreg. This is the only case in which
6897 we allow the destination to be larger than the source. */
6898 if (GET_CODE (dest) == SUBREG
6899 && GET_MODE (dest) == DImode
6900 && GET_MODE (SUBREG_REG (dest)) == SImode)
6901 dest = SUBREG_REG (dest);
6903 /* After the above adjustment, the destination must be the same
6904 width as the source. */
6905 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6908 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6911 temp = gen_reg_rtx (GET_MODE (dest));
6912 if (GET_MODE (dest) == DImode)
6914 emit_insn (gen_mov_ldl (temp, src, left));
6915 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6919 emit_insn (gen_mov_lwl (temp, src, left));
6920 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6925 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6926 BITPOS and SRC are the operands passed to the expander; the operation
6927 is the equivalent of:
6929 (set (zero_extract DEST WIDTH BITPOS) SRC)
6931 Return true on success. */
6934 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6935 HOST_WIDE_INT bitpos)
6938 enum machine_mode mode;
6940 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6943 mode = mode_for_size (width, MODE_INT, 0);
6944 src = gen_lowpart (mode, src);
6947 emit_insn (gen_mov_sdl (dest, src, left));
6948 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6952 emit_insn (gen_mov_swl (dest, src, left));
6953 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6958 /* Return true if X is a MEM with the same size as MODE. */
6961 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6964 && MEM_SIZE_KNOWN_P (x)
6965 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
6968 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6969 source of an "ext" instruction or the destination of an "ins"
6970 instruction. OP must be a register operand and the following
6971 conditions must hold:
6973 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6974 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6975 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6977 Also reject lengths equal to a word as they are better handled
6978 by the move patterns. */
6981 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6983 if (!ISA_HAS_EXT_INS
6984 || !register_operand (op, VOIDmode)
6985 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6988 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6991 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6997 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6998 operation if MAXLEN is the maxium length of consecutive bits that
6999 can make up MASK. MODE is the mode of the operation. See
7000 mask_low_and_shift_len for the actual definition. */
7003 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7005 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7008 /* Return true iff OP1 and OP2 are valid operands together for the
7009 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7010 see the table in the comment before the pattern. */
7013 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7015 return (memory_operand (op1, mode)
7016 ? and_load_operand (op2, mode)
7017 : and_reg_operand (op2, mode));
7020 /* The canonical form of a mask-low-and-shift-left operation is
7021 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7022 cleared. Thus we need to shift MASK to the right before checking if it
7023 is a valid mask value. MODE is the mode of the operation. If true
7024 return the length of the mask, otherwise return -1. */
7027 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7029 HOST_WIDE_INT shval;
7031 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7032 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7035 /* Return true if -msplit-addresses is selected and should be honored.
7037 -msplit-addresses is a half-way house between explicit relocations
7038 and the traditional assembler macros. It can split absolute 32-bit
7039 symbolic constants into a high/lo_sum pair but uses macros for other
7042 Like explicit relocation support for REL targets, it relies
7043 on GNU extensions in the assembler and the linker.
7045 Although this code should work for -O0, it has traditionally
7046 been treated as an optimization. */
7049 mips_split_addresses_p (void)
7051 return (TARGET_SPLIT_ADDRESSES
7055 && !ABI_HAS_64BIT_SYMBOLS);
7058 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7061 mips_init_relocs (void)
7063 memset (mips_split_p, '\0', sizeof (mips_split_p));
7064 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7065 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7066 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7068 if (ABI_HAS_64BIT_SYMBOLS)
7070 if (TARGET_EXPLICIT_RELOCS)
7072 mips_split_p[SYMBOL_64_HIGH] = true;
7073 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7074 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7076 mips_split_p[SYMBOL_64_MID] = true;
7077 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7078 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7080 mips_split_p[SYMBOL_64_LOW] = true;
7081 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7082 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7084 mips_split_p[SYMBOL_ABSOLUTE] = true;
7085 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7090 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7092 mips_split_p[SYMBOL_ABSOLUTE] = true;
7093 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7094 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7096 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7102 /* The high part is provided by a pseudo copy of $gp. */
7103 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7104 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7106 else if (TARGET_EXPLICIT_RELOCS)
7107 /* Small data constants are kept whole until after reload,
7108 then lowered by mips_rewrite_small_data. */
7109 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7111 if (TARGET_EXPLICIT_RELOCS)
7113 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7116 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7117 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7121 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7122 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7125 /* Expose the use of $28 as soon as possible. */
7126 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7130 /* The HIGH and LO_SUM are matched by special .md patterns. */
7131 mips_split_p[SYMBOL_GOT_DISP] = true;
7133 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7134 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7135 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7137 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7138 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7139 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7144 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7146 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7147 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7149 /* Expose the use of $28 as soon as possible. */
7150 mips_split_p[SYMBOL_GOT_DISP] = true;
7156 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7157 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7158 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7161 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7162 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7164 mips_split_p[SYMBOL_DTPREL] = true;
7165 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7166 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7168 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7170 mips_split_p[SYMBOL_TPREL] = true;
7171 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7172 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7174 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7177 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7178 in context CONTEXT. RELOCS is the array of relocations to use. */
7181 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7182 const char **relocs)
7184 enum mips_symbol_type symbol_type;
7187 symbol_type = mips_classify_symbolic_expression (op, context);
7188 gcc_assert (relocs[symbol_type]);
7190 fputs (relocs[symbol_type], file);
7191 output_addr_const (file, mips_strip_unspec_address (op));
7192 for (p = relocs[symbol_type]; *p != 0; p++)
7197 /* Start a new block with the given asm switch enabled. If we need
7198 to print a directive, emit PREFIX before it and SUFFIX after it. */
7201 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7202 const char *prefix, const char *suffix)
7204 if (asm_switch->nesting_level == 0)
7205 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7206 asm_switch->nesting_level++;
7209 /* Likewise, but end a block. */
7212 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7213 const char *prefix, const char *suffix)
7215 gcc_assert (asm_switch->nesting_level);
7216 asm_switch->nesting_level--;
7217 if (asm_switch->nesting_level == 0)
7218 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7221 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7222 that either print a complete line or print nothing. */
7225 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7227 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7231 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7233 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7236 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7237 The punctuation characters are:
7239 '(' Start a nested ".set noreorder" block.
7240 ')' End a nested ".set noreorder" block.
7241 '[' Start a nested ".set noat" block.
7242 ']' End a nested ".set noat" block.
7243 '<' Start a nested ".set nomacro" block.
7244 '>' End a nested ".set nomacro" block.
7245 '*' Behave like %(%< if generating a delayed-branch sequence.
7246 '#' Print a nop if in a ".set noreorder" block.
7247 '/' Like '#', but do nothing within a delayed-branch sequence.
7248 '?' Print "l" if mips_branch_likely is true
7249 '~' Print a nop if mips_branch_likely is true
7250 '.' Print the name of the register with a hard-wired zero (zero or $0).
7251 '@' Print the name of the assembler temporary register (at or $1).
7252 '^' Print the name of the pic call-through register (t9 or $25).
7253 '+' Print the name of the gp register (usually gp or $28).
7254 '$' Print the name of the stack pointer register (sp or $29).
7256 See also mips_init_print_operand_pucnt. */
7259 mips_print_operand_punctuation (FILE *file, int ch)
7264 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7268 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7272 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7276 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7280 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7284 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7288 if (final_sequence != 0)
7290 mips_print_operand_punctuation (file, '(');
7291 mips_print_operand_punctuation (file, '<');
7296 if (mips_noreorder.nesting_level > 0)
7297 fputs ("\n\tnop", file);
7301 /* Print an extra newline so that the delayed insn is separated
7302 from the following ones. This looks neater and is consistent
7303 with non-nop delayed sequences. */
7304 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7305 fputs ("\n\tnop\n", file);
7309 if (mips_branch_likely)
7314 if (mips_branch_likely)
7315 fputs ("\n\tnop", file);
7319 fputs (reg_names[GP_REG_FIRST + 0], file);
7323 fputs (reg_names[AT_REGNUM], file);
7327 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7331 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7335 fputs (reg_names[STACK_POINTER_REGNUM], file);
7344 /* Initialize mips_print_operand_punct. */
7347 mips_init_print_operand_punct (void)
7351 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7352 mips_print_operand_punct[(unsigned char) *p] = true;
7355 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7356 associated with condition CODE. Print the condition part of the
7360 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7374 /* Conveniently, the MIPS names for these conditions are the same
7375 as their RTL equivalents. */
7376 fputs (GET_RTX_NAME (code), file);
7380 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7385 /* Likewise floating-point branches. */
7388 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7393 fputs ("c1f", file);
7397 fputs ("c1t", file);
7401 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7406 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7409 mips_print_operand_punct_valid_p (unsigned char code)
7411 return mips_print_operand_punct[code];
7414 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7416 'X' Print CONST_INT OP in hexadecimal format.
7417 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7418 'd' Print CONST_INT OP in decimal.
7419 'm' Print one less than CONST_INT OP in decimal.
7420 'h' Print the high-part relocation associated with OP, after stripping
7422 'R' Print the low-part relocation associated with OP.
7423 'C' Print the integer branch condition for comparison OP.
7424 'N' Print the inverse of the integer branch condition for comparison OP.
7425 'F' Print the FPU branch condition for comparison OP.
7426 'W' Print the inverse of the FPU branch condition for comparison OP.
7427 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7428 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7429 't' Like 'T', but with the EQ/NE cases reversed
7430 'Y' Print mips_fp_conditions[INTVAL (OP)]
7431 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7432 'q' Print a DSP accumulator register.
7433 'D' Print the second part of a double-word register or memory operand.
7434 'L' Print the low-order register in a double-word register operand.
7435 'M' Print high-order register in a double-word register operand.
7436 'z' Print $0 if OP is zero, otherwise print OP normally. */
7439 mips_print_operand (FILE *file, rtx op, int letter)
7443 if (mips_print_operand_punct_valid_p (letter))
7445 mips_print_operand_punctuation (file, letter);
7450 code = GET_CODE (op);
7455 if (CONST_INT_P (op))
7456 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7458 output_operand_lossage ("invalid use of '%%%c'", letter);
7462 if (CONST_INT_P (op))
7463 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7465 output_operand_lossage ("invalid use of '%%%c'", letter);
7469 if (CONST_INT_P (op))
7470 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7472 output_operand_lossage ("invalid use of '%%%c'", letter);
7476 if (CONST_INT_P (op))
7477 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7479 output_operand_lossage ("invalid use of '%%%c'", letter);
7485 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7489 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7493 mips_print_int_branch_condition (file, code, letter);
7497 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7501 mips_print_float_branch_condition (file, code, letter);
7505 mips_print_float_branch_condition (file, reverse_condition (code),
7512 int truth = (code == NE) == (letter == 'T');
7513 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7518 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7519 fputs (mips_fp_conditions[UINTVAL (op)], file);
7521 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7528 mips_print_operand (file, op, 0);
7534 if (code == REG && MD_REG_P (REGNO (op)))
7535 fprintf (file, "$ac0");
7536 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7537 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7539 output_operand_lossage ("invalid use of '%%%c'", letter);
7547 unsigned int regno = REGNO (op);
7548 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7549 || (letter == 'L' && TARGET_BIG_ENDIAN)
7552 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7553 output_operand_lossage ("invalid use of '%%%c'", letter);
7554 /* We need to print $0 .. $31 for COP0 registers. */
7555 if (COP0_REG_P (regno))
7556 fprintf (file, "$%s", ®_names[regno][4]);
7558 fprintf (file, "%s", reg_names[regno]);
7564 output_address (plus_constant (XEXP (op, 0), 4));
7565 else if (letter && letter != 'z')
7566 output_operand_lossage ("invalid use of '%%%c'", letter);
7568 output_address (XEXP (op, 0));
7572 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7573 fputs (reg_names[GP_REG_FIRST], file);
7574 else if (letter && letter != 'z')
7575 output_operand_lossage ("invalid use of '%%%c'", letter);
7576 else if (CONST_GP_P (op))
7577 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7579 output_addr_const (file, mips_strip_unspec_address (op));
7585 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7588 mips_print_operand_address (FILE *file, rtx x)
7590 struct mips_address_info addr;
7592 if (mips_classify_address (&addr, x, word_mode, true))
7596 mips_print_operand (file, addr.offset, 0);
7597 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7600 case ADDRESS_LO_SUM:
7601 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7603 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7606 case ADDRESS_CONST_INT:
7607 output_addr_const (file, x);
7608 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7611 case ADDRESS_SYMBOLIC:
7612 output_addr_const (file, mips_strip_unspec_address (x));
7618 /* Implement TARGET_ENCODE_SECTION_INFO. */
7621 mips_encode_section_info (tree decl, rtx rtl, int first)
7623 default_encode_section_info (decl, rtl, first);
7625 if (TREE_CODE (decl) == FUNCTION_DECL)
7627 rtx symbol = XEXP (rtl, 0);
7628 tree type = TREE_TYPE (decl);
7630 /* Encode whether the symbol is short or long. */
7631 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7632 || mips_far_type_p (type))
7633 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7637 /* Implement TARGET_SELECT_RTX_SECTION. */
7640 mips_select_rtx_section (enum machine_mode mode, rtx x,
7641 unsigned HOST_WIDE_INT align)
7643 /* ??? Consider using mergeable small data sections. */
7644 if (mips_rtx_constant_in_small_data_p (mode))
7645 return get_named_section (NULL, ".sdata", 0);
7647 return default_elf_select_rtx_section (mode, x, align);
7650 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7652 The complication here is that, with the combination TARGET_ABICALLS
7653 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7654 absolute addresses, and should therefore not be included in the
7655 read-only part of a DSO. Handle such cases by selecting a normal
7656 data section instead of a read-only one. The logic apes that in
7657 default_function_rodata_section. */
7660 mips_function_rodata_section (tree decl)
7662 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7663 return default_function_rodata_section (decl);
7665 if (decl && DECL_SECTION_NAME (decl))
7667 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7668 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7670 char *rname = ASTRDUP (name);
7672 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7674 else if (flag_function_sections
7675 && flag_data_sections
7676 && strncmp (name, ".text.", 6) == 0)
7678 char *rname = ASTRDUP (name);
7679 memcpy (rname + 1, "data", 4);
7680 return get_section (rname, SECTION_WRITE, decl);
7683 return data_section;
7686 /* Implement TARGET_IN_SMALL_DATA_P. */
7689 mips_in_small_data_p (const_tree decl)
7691 unsigned HOST_WIDE_INT size;
7693 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7696 /* We don't yet generate small-data references for -mabicalls
7697 or VxWorks RTP code. See the related -G handling in
7698 mips_option_override. */
7699 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7702 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7706 /* Reject anything that isn't in a known small-data section. */
7707 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7708 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7711 /* If a symbol is defined externally, the assembler will use the
7712 usual -G rules when deciding how to implement macros. */
7713 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7716 else if (TARGET_EMBEDDED_DATA)
7718 /* Don't put constants into the small data section: we want them
7719 to be in ROM rather than RAM. */
7720 if (TREE_CODE (decl) != VAR_DECL)
7723 if (TREE_READONLY (decl)
7724 && !TREE_SIDE_EFFECTS (decl)
7725 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7729 /* Enforce -mlocal-sdata. */
7730 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7733 /* Enforce -mextern-sdata. */
7734 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7736 if (DECL_EXTERNAL (decl))
7738 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7742 /* We have traditionally not treated zero-sized objects as small data,
7743 so this is now effectively part of the ABI. */
7744 size = int_size_in_bytes (TREE_TYPE (decl));
7745 return size > 0 && size <= mips_small_data_threshold;
7748 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7749 anchors for small data: the GP register acts as an anchor in that
7750 case. We also don't want to use them for PC-relative accesses,
7751 where the PC acts as an anchor. */
7754 mips_use_anchors_for_symbol_p (const_rtx symbol)
7756 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7758 case SYMBOL_PC_RELATIVE:
7759 case SYMBOL_GP_RELATIVE:
7763 return default_use_anchors_for_symbol_p (symbol);
7767 /* The MIPS debug format wants all automatic variables and arguments
7768 to be in terms of the virtual frame pointer (stack pointer before
7769 any adjustment in the function), while the MIPS 3.0 linker wants
7770 the frame pointer to be the stack pointer after the initial
7771 adjustment. So, we do the adjustment here. The arg pointer (which
7772 is eliminated) points to the virtual frame pointer, while the frame
7773 pointer (which may be eliminated) points to the stack pointer after
7774 the initial adjustments. */
7777 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7779 rtx offset2 = const0_rtx;
7780 rtx reg = eliminate_constant_term (addr, &offset2);
7783 offset = INTVAL (offset2);
7785 if (reg == stack_pointer_rtx
7786 || reg == frame_pointer_rtx
7787 || reg == hard_frame_pointer_rtx)
7789 offset -= cfun->machine->frame.total_size;
7790 if (reg == hard_frame_pointer_rtx)
7791 offset += cfun->machine->frame.hard_frame_pointer_offset;
7794 /* sdbout_parms does not want this to crash for unrecognized cases. */
7796 else if (reg != arg_pointer_rtx)
7797 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7804 /* Implement ASM_OUTPUT_EXTERNAL. */
7807 mips_output_external (FILE *file, tree decl, const char *name)
7809 default_elf_asm_output_external (file, decl, name);
7811 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7812 set in order to avoid putting out names that are never really
7814 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7816 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7818 /* When using assembler macros, emit .extern directives for
7819 all small-data externs so that the assembler knows how
7822 In most cases it would be safe (though pointless) to emit
7823 .externs for other symbols too. One exception is when an
7824 object is within the -G limit but declared by the user to
7825 be in a section other than .sbss or .sdata. */
7826 fputs ("\t.extern\t", file);
7827 assemble_name (file, name);
7828 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7829 int_size_in_bytes (TREE_TYPE (decl)));
7834 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7837 mips_output_filename (FILE *stream, const char *name)
7839 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7841 if (write_symbols == DWARF2_DEBUG)
7843 else if (mips_output_filename_first_time)
7845 mips_output_filename_first_time = 0;
7846 num_source_filenames += 1;
7847 current_function_file = name;
7848 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7849 output_quoted_string (stream, name);
7850 putc ('\n', stream);
7852 /* If we are emitting stabs, let dbxout.c handle this (except for
7853 the mips_output_filename_first_time case). */
7854 else if (write_symbols == DBX_DEBUG)
7856 else if (name != current_function_file
7857 && strcmp (name, current_function_file) != 0)
7859 num_source_filenames += 1;
7860 current_function_file = name;
7861 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7862 output_quoted_string (stream, name);
7863 putc ('\n', stream);
7867 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7869 static void ATTRIBUTE_UNUSED
7870 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7875 fputs ("\t.dtprelword\t", file);
7879 fputs ("\t.dtpreldword\t", file);
7885 output_addr_const (file, x);
7886 fputs ("+0x8000", file);
7889 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7892 mips_dwarf_register_span (rtx reg)
7895 enum machine_mode mode;
7897 /* By default, GCC maps increasing register numbers to increasing
7898 memory locations, but paired FPRs are always little-endian,
7899 regardless of the prevailing endianness. */
7900 mode = GET_MODE (reg);
7901 if (FP_REG_P (REGNO (reg))
7902 && TARGET_BIG_ENDIAN
7903 && MAX_FPRS_PER_FMT > 1
7904 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7906 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7907 high = mips_subword (reg, true);
7908 low = mips_subword (reg, false);
7909 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7915 /* Implement ASM_OUTPUT_ASCII. */
7918 mips_output_ascii (FILE *stream, const char *string, size_t len)
7924 fprintf (stream, "\t.ascii\t\"");
7925 for (i = 0; i < len; i++)
7929 c = (unsigned char) string[i];
7932 if (c == '\\' || c == '\"')
7934 putc ('\\', stream);
7942 fprintf (stream, "\\%03o", c);
7946 if (cur_pos > 72 && i+1 < len)
7949 fprintf (stream, "\"\n\t.ascii\t\"");
7952 fprintf (stream, "\"\n");
7955 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7956 macros, mark the symbol as written so that mips_asm_output_external
7957 won't emit an .extern for it. STREAM is the output file, NAME is the
7958 name of the symbol, INIT_STRING is the string that should be written
7959 before the symbol and FINAL_STRING is the string that should be
7960 written after it. FINAL_STRING is a printf format that consumes the
7961 remaining arguments. */
7964 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7965 const char *final_string, ...)
7969 fputs (init_string, stream);
7970 assemble_name (stream, name);
7971 va_start (ap, final_string);
7972 vfprintf (stream, final_string, ap);
7975 if (!TARGET_EXPLICIT_RELOCS)
7977 tree name_tree = get_identifier (name);
7978 TREE_ASM_WRITTEN (name_tree) = 1;
7982 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7983 NAME is the name of the object and ALIGN is the required alignment
7984 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7985 alignment argument. */
7988 mips_declare_common_object (FILE *stream, const char *name,
7989 const char *init_string,
7990 unsigned HOST_WIDE_INT size,
7991 unsigned int align, bool takes_alignment_p)
7993 if (!takes_alignment_p)
7995 size += (align / BITS_PER_UNIT) - 1;
7996 size -= size % (align / BITS_PER_UNIT);
7997 mips_declare_object (stream, name, init_string,
7998 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8001 mips_declare_object (stream, name, init_string,
8002 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8003 size, align / BITS_PER_UNIT);
8006 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8007 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8010 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8011 unsigned HOST_WIDE_INT size,
8014 /* If the target wants uninitialized const declarations in
8015 .rdata then don't put them in .comm. */
8016 if (TARGET_EMBEDDED_DATA
8017 && TARGET_UNINIT_CONST_IN_RODATA
8018 && TREE_CODE (decl) == VAR_DECL
8019 && TREE_READONLY (decl)
8020 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8022 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8023 targetm.asm_out.globalize_label (stream, name);
8025 switch_to_section (readonly_data_section);
8026 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8027 mips_declare_object (stream, name, "",
8028 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8032 mips_declare_common_object (stream, name, "\n\t.comm\t",
8036 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8037 extern int size_directive_output;
8039 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8040 definitions except that it uses mips_declare_object to emit the label. */
8043 mips_declare_object_name (FILE *stream, const char *name,
8044 tree decl ATTRIBUTE_UNUSED)
8046 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8047 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8050 size_directive_output = 0;
8051 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8055 size_directive_output = 1;
8056 size = int_size_in_bytes (TREE_TYPE (decl));
8057 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8060 mips_declare_object (stream, name, "", ":\n");
8063 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8066 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8070 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8071 if (!flag_inhibit_size_directive
8072 && DECL_SIZE (decl) != 0
8075 && DECL_INITIAL (decl) == error_mark_node
8076 && !size_directive_output)
8080 size_directive_output = 1;
8081 size = int_size_in_bytes (TREE_TYPE (decl));
8082 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8087 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8088 with the current ABI. */
8091 mips_mdebug_abi_name (void)
8104 return TARGET_64BIT ? "eabi64" : "eabi32";
8110 /* Implement TARGET_ASM_FILE_START. */
8113 mips_file_start (void)
8115 default_file_start ();
8117 /* Generate a special section to describe the ABI switches used to
8118 produce the resultant binary. This is unnecessary on IRIX and
8119 causes unwanted warnings from the native linker. */
8122 /* Record the ABI itself. Modern versions of binutils encode
8123 this information in the ELF header flags, but GDB needs the
8124 information in order to correctly debug binaries produced by
8125 older binutils. See the function mips_gdbarch_init in
8127 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8128 mips_mdebug_abi_name ());
8130 /* There is no ELF header flag to distinguish long32 forms of the
8131 EABI from long64 forms. Emit a special section to help tools
8132 such as GDB. Do the same for o64, which is sometimes used with
8134 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8135 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8136 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8138 #ifdef HAVE_AS_GNU_ATTRIBUTE
8142 /* No floating-point operations, -mno-float. */
8143 if (TARGET_NO_FLOAT)
8145 /* Soft-float code, -msoft-float. */
8146 else if (!TARGET_HARD_FLOAT_ABI)
8148 /* Single-float code, -msingle-float. */
8149 else if (!TARGET_DOUBLE_FLOAT)
8151 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8152 else if (!TARGET_64BIT && TARGET_FLOAT64)
8154 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8158 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8163 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8164 if (TARGET_ABICALLS)
8166 fprintf (asm_out_file, "\t.abicalls\n");
8167 if (TARGET_ABICALLS_PIC0)
8168 fprintf (asm_out_file, "\t.option\tpic0\n");
8171 if (flag_verbose_asm)
8172 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8174 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8177 /* Make the last instruction frame-related and note that it performs
8178 the operation described by FRAME_PATTERN. */
8181 mips_set_frame_expr (rtx frame_pattern)
8185 insn = get_last_insn ();
8186 RTX_FRAME_RELATED_P (insn) = 1;
8187 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8192 /* Return a frame-related rtx that stores REG at MEM.
8193 REG must be a single register. */
8196 mips_frame_set (rtx mem, rtx reg)
8200 set = gen_rtx_SET (VOIDmode, mem, reg);
8201 RTX_FRAME_RELATED_P (set) = 1;
8206 /* Record that the epilogue has restored call-saved register REG. */
8209 mips_add_cfa_restore (rtx reg)
8211 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8212 mips_epilogue.cfa_restores);
8215 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8216 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8217 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8218 static const unsigned char mips16e_s2_s8_regs[] = {
8219 30, 23, 22, 21, 20, 19, 18
8221 static const unsigned char mips16e_a0_a3_regs[] = {
8225 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8226 ordered from the uppermost in memory to the lowest in memory. */
8227 static const unsigned char mips16e_save_restore_regs[] = {
8228 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8231 /* Return the index of the lowest X in the range [0, SIZE) for which
8232 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8235 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8240 for (i = 0; i < size; i++)
8241 if (BITSET_P (mask, regs[i]))
8247 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8248 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8249 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8250 is true for all indexes (X, SIZE). */
8253 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8254 unsigned int size, unsigned int *num_regs_ptr)
8258 i = mips16e_find_first_register (*mask_ptr, regs, size);
8259 for (i++; i < size; i++)
8260 if (!BITSET_P (*mask_ptr, regs[i]))
8263 *mask_ptr |= 1 << regs[i];
8267 /* Return a simplified form of X using the register values in REG_VALUES.
8268 REG_VALUES[R] is the last value assigned to hard register R, or null
8269 if R has not been modified.
8271 This function is rather limited, but is good enough for our purposes. */
8274 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8276 x = avoid_constant_pool_reference (x);
8280 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8281 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8282 x0, GET_MODE (XEXP (x, 0)));
8285 if (ARITHMETIC_P (x))
8287 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8288 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8289 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8293 && reg_values[REGNO (x)]
8294 && !rtx_unstable_p (reg_values[REGNO (x)]))
8295 return reg_values[REGNO (x)];
8300 /* Return true if (set DEST SRC) stores an argument register into its
8301 caller-allocated save slot, storing the number of that argument
8302 register in *REGNO_PTR if so. REG_VALUES is as for
8303 mips16e_collect_propagate_value. */
8306 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8307 unsigned int *regno_ptr)
8309 unsigned int argno, regno;
8310 HOST_WIDE_INT offset, required_offset;
8313 /* Check that this is a word-mode store. */
8314 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8317 /* Check that the register being saved is an unmodified argument
8319 regno = REGNO (src);
8320 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8322 argno = regno - GP_ARG_FIRST;
8324 /* Check whether the address is an appropriate stack-pointer or
8325 frame-pointer access. */
8326 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8327 mips_split_plus (addr, &base, &offset);
8328 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8329 if (base == hard_frame_pointer_rtx)
8330 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8331 else if (base != stack_pointer_rtx)
8333 if (offset != required_offset)
8340 /* A subroutine of mips_expand_prologue, called only when generating
8341 MIPS16e SAVE instructions. Search the start of the function for any
8342 instructions that save argument registers into their caller-allocated
8343 save slots. Delete such instructions and return a value N such that
8344 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8345 instructions redundant. */
8348 mips16e_collect_argument_saves (void)
8350 rtx reg_values[FIRST_PSEUDO_REGISTER];
8351 rtx insn, next, set, dest, src;
8352 unsigned int nargs, regno;
8354 push_topmost_sequence ();
8356 memset (reg_values, 0, sizeof (reg_values));
8357 for (insn = get_insns (); insn; insn = next)
8359 next = NEXT_INSN (insn);
8360 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8366 set = PATTERN (insn);
8367 if (GET_CODE (set) != SET)
8370 dest = SET_DEST (set);
8371 src = SET_SRC (set);
8372 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8374 if (!BITSET_P (cfun->machine->frame.mask, regno))
8377 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8380 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8381 reg_values[REGNO (dest)]
8382 = mips16e_collect_propagate_value (src, reg_values);
8386 pop_topmost_sequence ();
8391 /* Return a move between register REGNO and memory location SP + OFFSET.
8392 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
8393 Make the move a load if RESTORE_P, otherwise make it a store. */
8396 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
8397 HOST_WIDE_INT offset, unsigned int regno)
8401 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8402 reg = gen_rtx_REG (SImode, regno);
8405 mips_add_cfa_restore (reg);
8406 return gen_rtx_SET (VOIDmode, reg, mem);
8409 return gen_rtx_SET (VOIDmode, mem, reg);
8410 return mips_frame_set (mem, reg);
8413 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8414 The instruction must:
8416 - Allocate or deallocate SIZE bytes in total; SIZE is known
8419 - Save or restore as many registers in *MASK_PTR as possible.
8420 The instruction saves the first registers at the top of the
8421 allocated area, with the other registers below it.
8423 - Save NARGS argument registers above the allocated area.
8425 (NARGS is always zero if RESTORE_P.)
8427 The SAVE and RESTORE instructions cannot save and restore all general
8428 registers, so there may be some registers left over for the caller to
8429 handle. Destructively modify *MASK_PTR so that it contains the registers
8430 that still need to be saved or restored. The caller can save these
8431 registers in the memory immediately below *OFFSET_PTR, which is a
8432 byte offset from the bottom of the allocated stack area. */
8435 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8436 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8440 HOST_WIDE_INT offset, top_offset;
8441 unsigned int i, regno;
8444 gcc_assert (cfun->machine->frame.num_fp == 0);
8446 /* Calculate the number of elements in the PARALLEL. We need one element
8447 for the stack adjustment, one for each argument register save, and one
8448 for each additional register move. */
8450 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8451 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8454 /* Create the final PARALLEL. */
8455 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8458 /* Add the stack pointer adjustment. */
8459 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8460 plus_constant (stack_pointer_rtx,
8461 restore_p ? size : -size));
8462 RTX_FRAME_RELATED_P (set) = 1;
8463 XVECEXP (pattern, 0, n++) = set;
8465 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8466 top_offset = restore_p ? size : 0;
8468 /* Save the arguments. */
8469 for (i = 0; i < nargs; i++)
8471 offset = top_offset + i * UNITS_PER_WORD;
8472 set = mips16e_save_restore_reg (restore_p, true, offset,
8474 XVECEXP (pattern, 0, n++) = set;
8477 /* Then fill in the other register moves. */
8478 offset = top_offset;
8479 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8481 regno = mips16e_save_restore_regs[i];
8482 if (BITSET_P (*mask_ptr, regno))
8484 offset -= UNITS_PER_WORD;
8485 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
8486 XVECEXP (pattern, 0, n++) = set;
8487 *mask_ptr &= ~(1 << regno);
8491 /* Tell the caller what offset it should use for the remaining registers. */
8492 *offset_ptr = size + (offset - top_offset);
8494 gcc_assert (n == XVECLEN (pattern, 0));
8499 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8500 pointer. Return true if PATTERN matches the kind of instruction
8501 generated by mips16e_build_save_restore. If INFO is nonnull,
8502 initialize it when returning true. */
8505 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8506 struct mips16e_save_restore_info *info)
8508 unsigned int i, nargs, mask, extra;
8509 HOST_WIDE_INT top_offset, save_offset, offset;
8510 rtx set, reg, mem, base;
8513 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8516 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8517 top_offset = adjust > 0 ? adjust : 0;
8519 /* Interpret all other members of the PARALLEL. */
8520 save_offset = top_offset - UNITS_PER_WORD;
8524 for (n = 1; n < XVECLEN (pattern, 0); n++)
8526 /* Check that we have a SET. */
8527 set = XVECEXP (pattern, 0, n);
8528 if (GET_CODE (set) != SET)
8531 /* Check that the SET is a load (if restoring) or a store
8533 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8537 /* Check that the address is the sum of the stack pointer and a
8538 possibly-zero constant offset. */
8539 mips_split_plus (XEXP (mem, 0), &base, &offset);
8540 if (base != stack_pointer_rtx)
8543 /* Check that SET's other operand is a register. */
8544 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8548 /* Check for argument saves. */
8549 if (offset == top_offset + nargs * UNITS_PER_WORD
8550 && REGNO (reg) == GP_ARG_FIRST + nargs)
8552 else if (offset == save_offset)
8554 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8555 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8558 mask |= 1 << REGNO (reg);
8559 save_offset -= UNITS_PER_WORD;
8565 /* Check that the restrictions on register ranges are met. */
8567 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8568 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8569 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8570 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8574 /* Make sure that the topmost argument register is not saved twice.
8575 The checks above ensure that the same is then true for the other
8576 argument registers. */
8577 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8580 /* Pass back information, if requested. */
8583 info->nargs = nargs;
8585 info->size = (adjust > 0 ? adjust : -adjust);
8591 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8592 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8593 the null terminator. */
8596 mips16e_add_register_range (char *s, unsigned int min_reg,
8597 unsigned int max_reg)
8599 if (min_reg != max_reg)
8600 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8602 s += sprintf (s, ",%s", reg_names[min_reg]);
8606 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8607 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8610 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8612 static char buffer[300];
8614 struct mips16e_save_restore_info info;
8615 unsigned int i, end;
8618 /* Parse the pattern. */
8619 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8622 /* Add the mnemonic. */
8623 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8626 /* Save the arguments. */
8628 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8629 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8630 else if (info.nargs == 1)
8631 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8633 /* Emit the amount of stack space to allocate or deallocate. */
8634 s += sprintf (s, "%d", (int) info.size);
8636 /* Save or restore $16. */
8637 if (BITSET_P (info.mask, 16))
8638 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8640 /* Save or restore $17. */
8641 if (BITSET_P (info.mask, 17))
8642 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8644 /* Save or restore registers in the range $s2...$s8, which
8645 mips16e_s2_s8_regs lists in decreasing order. Note that this
8646 is a software register range; the hardware registers are not
8647 numbered consecutively. */
8648 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8649 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8651 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8652 mips16e_s2_s8_regs[i]);
8654 /* Save or restore registers in the range $a0...$a3. */
8655 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8656 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8658 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8659 mips16e_a0_a3_regs[end - 1]);
8661 /* Save or restore $31. */
8662 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8663 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8668 /* Return true if the current function returns its value in a floating-point
8669 register in MIPS16 mode. */
8672 mips16_cfun_returns_in_fpr_p (void)
8674 tree return_type = DECL_RESULT (current_function_decl);
8675 return (TARGET_MIPS16
8676 && TARGET_HARD_FLOAT_ABI
8677 && !aggregate_value_p (return_type, current_function_decl)
8678 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8681 /* Return true if predicate PRED is true for at least one instruction.
8682 Cache the result in *CACHE, and assume that the result is true
8683 if *CACHE is already true. */
8686 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8692 push_topmost_sequence ();
8693 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8694 if (USEFUL_INSN_P (insn) && pred (insn))
8699 pop_topmost_sequence ();
8704 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8705 See mips_cfun_has_inflexible_gp_ref_p for details. */
8708 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8710 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8711 indicate that the target could be a traditional MIPS
8712 lazily-binding stub. */
8713 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8716 /* Return true if the current function refers to the global pointer
8717 in a way that forces $28 to be valid. This means that we can't
8718 change the choice of global pointer, even for NewABI code.
8720 One example of this (and one which needs several checks) is that
8721 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8722 (This restriction does not apply to PLTs.) */
8725 mips_cfun_has_inflexible_gp_ref_p (void)
8727 /* If the function has a nonlocal goto, $28 must hold the correct
8728 global pointer for the target function. That is, the target
8729 of the goto implicitly uses $28. */
8730 if (crtl->has_nonlocal_goto)
8733 if (TARGET_ABICALLS_PIC2)
8735 /* Symbolic accesses implicitly use the global pointer unless
8736 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8737 might go to traditional MIPS lazy-binding stubs. */
8738 if (!TARGET_EXPLICIT_RELOCS)
8741 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8742 can be lazily-bound. */
8746 /* MIPS16 functions that return in FPRs need to call an
8747 external libgcc routine. This call is only made explict
8748 during mips_expand_epilogue, and it too might be lazily bound. */
8749 if (mips16_cfun_returns_in_fpr_p ())
8753 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8754 mips_insn_has_inflexible_gp_ref_p);
8757 /* Return true if INSN refers to the global pointer in a "flexible" way.
8758 See mips_cfun_has_flexible_gp_ref_p for details. */
8761 mips_insn_has_flexible_gp_ref_p (rtx insn)
8763 return (get_attr_got (insn) != GOT_UNSET
8764 || mips_small_data_pattern_p (PATTERN (insn))
8765 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8768 /* Return true if the current function references the global pointer,
8769 but if those references do not inherently require the global pointer
8770 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8773 mips_cfun_has_flexible_gp_ref_p (void)
8775 /* Reload can sometimes introduce constant pool references
8776 into a function that otherwise didn't need them. For example,
8777 suppose we have an instruction like:
8779 (set (reg:DF R1) (float:DF (reg:SI R2)))
8781 If R2 turns out to be a constant such as 1, the instruction may
8782 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8783 the option of using this constant if R2 doesn't get allocated
8786 In cases like these, reload will have added the constant to the
8787 pool but no instruction will yet refer to it. */
8788 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8791 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8792 mips_insn_has_flexible_gp_ref_p);
8795 /* Return the register that should be used as the global pointer
8796 within this function. Return INVALID_REGNUM if the function
8797 doesn't need a global pointer. */
8800 mips_global_pointer (void)
8804 /* $gp is always available unless we're using a GOT. */
8805 if (!TARGET_USE_GOT)
8806 return GLOBAL_POINTER_REGNUM;
8808 /* If there are inflexible references to $gp, we must use the
8809 standard register. */
8810 if (mips_cfun_has_inflexible_gp_ref_p ())
8811 return GLOBAL_POINTER_REGNUM;
8813 /* If there are no current references to $gp, then the only uses
8814 we can introduce later are those involved in long branches. */
8815 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8816 return INVALID_REGNUM;
8818 /* If the global pointer is call-saved, try to use a call-clobbered
8820 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8821 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8822 if (!df_regs_ever_live_p (regno)
8823 && call_really_used_regs[regno]
8824 && !fixed_regs[regno]
8825 && regno != PIC_FUNCTION_ADDR_REGNUM)
8828 return GLOBAL_POINTER_REGNUM;
8831 /* Return true if the current function's prologue must load the global
8832 pointer value into pic_offset_table_rtx and store the same value in
8833 the function's cprestore slot (if any).
8835 One problem we have to deal with is that, when emitting GOT-based
8836 position independent code, long-branch sequences will need to load
8837 the address of the branch target from the GOT. We don't know until
8838 the very end of compilation whether (and where) the function needs
8839 long branches, so we must ensure that _any_ branch can access the
8840 global pointer in some form. However, we do not want to pessimize
8841 the usual case in which all branches are short.
8843 We handle this as follows:
8845 (1) During reload, we set cfun->machine->global_pointer to
8846 INVALID_REGNUM if we _know_ that the current function
8847 doesn't need a global pointer. This is only valid if
8848 long branches don't need the GOT.
8850 Otherwise, we assume that we might need a global pointer
8851 and pick an appropriate register.
8853 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8854 we ensure that the global pointer is available at every
8855 block boundary bar entry and exit. We do this in one of two ways:
8857 - If the function has a cprestore slot, we ensure that this
8858 slot is valid at every branch. However, as explained in
8859 point (6) below, there is no guarantee that pic_offset_table_rtx
8860 itself is valid if new uses of the global pointer are introduced
8861 after the first post-epilogue split.
8863 We guarantee that the cprestore slot is valid by loading it
8864 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8865 this register live at every block boundary bar function entry
8866 and exit. It is then invalid to move the load (and thus the
8867 preceding store) across a block boundary.
8869 - If the function has no cprestore slot, we guarantee that
8870 pic_offset_table_rtx itself is valid at every branch.
8872 See mips_eh_uses for the handling of the register liveness.
8874 (3) During prologue and epilogue generation, we emit "ghost"
8875 placeholder instructions to manipulate the global pointer.
8877 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8878 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8879 that the function needs a global pointer. (There is no need to set
8880 them earlier than this, and doing it as late as possible leads to
8881 fewer false positives.)
8883 (5) If cfun->machine->must_initialize_gp_p is true during a
8884 split_insns pass, we split the ghost instructions into real
8885 instructions. These split instructions can then be optimized in
8886 the usual way. Otherwise, we keep the ghost instructions intact,
8887 and optimize for the case where they aren't needed. We still
8888 have the option of splitting them later, if we need to introduce
8889 new uses of the global pointer.
8891 For example, the scheduler ignores a ghost instruction that
8892 stores $28 to the stack, but it handles the split form of
8893 the ghost instruction as an ordinary store.
8895 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8896 is true during the first post-epilogue split_insns pass, we split
8897 calls and restore_gp patterns into instructions that explicitly
8898 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8899 we split these patterns into instructions that _don't_ load from
8902 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8903 time of the split, then any instructions that exist at that time
8904 can make free use of pic_offset_table_rtx. However, if we want
8905 to introduce new uses of the global pointer after the split,
8906 we must explicitly load the value from the cprestore slot, since
8907 pic_offset_table_rtx itself might not be valid at a given point
8910 The idea is that we want to be able to delete redundant
8911 loads from the cprestore slot in the usual case where no
8912 long branches are needed.
8914 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8915 of md_reorg, we decide whether the global pointer is needed for
8916 long branches. If so, we set cfun->machine->must_initialize_gp_p
8917 to true and split the ghost instructions into real instructions
8920 Note that the ghost instructions must have a zero length for three reasons:
8922 - Giving the length of the underlying $gp sequence might cause
8923 us to use long branches in cases where they aren't really needed.
8925 - They would perturb things like alignment calculations.
8927 - More importantly, the hazard detection in md_reorg relies on
8928 empty instructions having a zero length.
8930 If we find a long branch and split the ghost instructions at the
8931 end of md_reorg, the split could introduce more long branches.
8932 That isn't a problem though, because we still do the split before
8933 the final shorten_branches pass.
8935 This is extremely ugly, but it seems like the best compromise between
8936 correctness and efficiency. */
8939 mips_must_initialize_gp_p (void)
8941 return cfun->machine->must_initialize_gp_p;
8944 /* Return true if REGNO is a register that is ordinarily call-clobbered
8945 but must nevertheless be preserved by an interrupt handler. */
8948 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8950 if (MD_REG_P (regno))
8953 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8956 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8958 /* $0 is hard-wired. */
8959 if (regno == GP_REG_FIRST)
8962 /* The interrupt handler can treat kernel registers as
8963 scratch registers. */
8964 if (KERNEL_REG_P (regno))
8967 /* The function will return the stack pointer to its original value
8969 if (regno == STACK_POINTER_REGNUM)
8972 /* Otherwise, return true for registers that aren't ordinarily
8974 return call_really_used_regs[regno];
8980 /* Return true if the current function should treat register REGNO
8984 mips_cfun_call_saved_reg_p (unsigned int regno)
8986 /* If the user makes an ordinarily-call-saved register global,
8987 that register is no longer call-saved. */
8988 if (global_regs[regno])
8991 /* Interrupt handlers need to save extra registers. */
8992 if (cfun->machine->interrupt_handler_p
8993 && mips_interrupt_extra_call_saved_reg_p (regno))
8996 /* call_insns preserve $28 unless they explicitly say otherwise,
8997 so call_really_used_regs[] treats $28 as call-saved. However,
8998 we want the ABI property rather than the default call_insn
9000 return (regno == GLOBAL_POINTER_REGNUM
9001 ? TARGET_CALL_SAVED_GP
9002 : !call_really_used_regs[regno]);
9005 /* Return true if the function body might clobber register REGNO.
9006 We know that REGNO is call-saved. */
9009 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9011 /* Some functions should be treated as clobbering all call-saved
9013 if (crtl->saves_all_registers)
9016 /* DF handles cases where a register is explicitly referenced in
9017 the rtl. Incoming values are passed in call-clobbered registers,
9018 so we can assume that any live call-saved register is set within
9020 if (df_regs_ever_live_p (regno))
9023 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9024 These clobbers are not explicit in the rtl. */
9025 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9028 /* If we're using a call-saved global pointer, the function's
9029 prologue will need to set it up. */
9030 if (cfun->machine->global_pointer == regno)
9033 /* The function's prologue will need to set the frame pointer if
9034 frame_pointer_needed. */
9035 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9038 /* If a MIPS16 function returns a value in FPRs, its epilogue
9039 will need to call an external libgcc routine. This yet-to-be
9040 generated call_insn will clobber $31. */
9041 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9044 /* If REGNO is ordinarily call-clobbered, we must assume that any
9045 called function could modify it. */
9046 if (cfun->machine->interrupt_handler_p
9047 && !current_function_is_leaf
9048 && mips_interrupt_extra_call_saved_reg_p (regno))
9054 /* Return true if the current function must save register REGNO. */
9057 mips_save_reg_p (unsigned int regno)
9059 if (mips_cfun_call_saved_reg_p (regno))
9061 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9064 /* Save both registers in an FPR pair if either one is used. This is
9065 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9066 register to be used without the even register. */
9067 if (FP_REG_P (regno)
9068 && MAX_FPRS_PER_FMT == 2
9069 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9073 /* We need to save the incoming return address if __builtin_eh_return
9074 is being used to set a different return address. */
9075 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9081 /* Populate the current function's mips_frame_info structure.
9083 MIPS stack frames look like:
9085 +-------------------------------+
9087 | incoming stack arguments |
9089 +-------------------------------+
9091 | caller-allocated save area |
9092 A | for register arguments |
9094 +-------------------------------+ <-- incoming stack pointer
9096 | callee-allocated save area |
9097 B | for arguments that are |
9098 | split between registers and |
9101 +-------------------------------+ <-- arg_pointer_rtx
9103 C | callee-allocated save area |
9104 | for register varargs |
9106 +-------------------------------+ <-- frame_pointer_rtx
9107 | | + cop0_sp_offset
9108 | COP0 reg save area | + UNITS_PER_WORD
9110 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9111 | | + UNITS_PER_WORD
9112 | accumulator save area |
9114 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9115 | | + UNITS_PER_HWFPVALUE
9118 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9119 | | + UNITS_PER_WORD
9122 +-------------------------------+ <-- frame_pointer_rtx with
9123 | | \ -fstack-protector
9124 | local variables | | var_size
9126 +-------------------------------+
9128 | $gp save area | | cprestore_size
9130 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9132 | outgoing stack arguments | |
9134 +-------------------------------+ | args_size
9136 | caller-allocated save area | |
9137 | for register arguments | |
9139 +-------------------------------+ <-- stack_pointer_rtx
9140 frame_pointer_rtx without
9142 hard_frame_pointer_rtx for
9145 At least two of A, B and C will be empty.
9147 Dynamic stack allocations such as alloca insert data at point P.
9148 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9149 hard_frame_pointer_rtx unchanged. */
9152 mips_compute_frame_info (void)
9154 struct mips_frame_info *frame;
9155 HOST_WIDE_INT offset, size;
9156 unsigned int regno, i;
9158 /* Set this function's interrupt properties. */
9159 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9162 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9163 else if (TARGET_HARD_FLOAT)
9164 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9165 else if (TARGET_MIPS16)
9166 error ("interrupt handlers cannot be MIPS16 functions");
9169 cfun->machine->interrupt_handler_p = true;
9170 cfun->machine->use_shadow_register_set_p =
9171 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9172 cfun->machine->keep_interrupts_masked_p =
9173 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9174 cfun->machine->use_debug_exception_return_p =
9175 mips_use_debug_exception_return_p (TREE_TYPE
9176 (current_function_decl));
9180 frame = &cfun->machine->frame;
9181 memset (frame, 0, sizeof (*frame));
9182 size = get_frame_size ();
9184 cfun->machine->global_pointer = mips_global_pointer ();
9186 /* The first two blocks contain the outgoing argument area and the $gp save
9187 slot. This area isn't needed in leaf functions, but if the
9188 target-independent frame size is nonzero, we have already committed to
9189 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9190 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9192 /* The MIPS 3.0 linker does not like functions that dynamically
9193 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9194 looks like we are trying to create a second frame pointer to the
9195 function, so allocate some stack space to make it happy. */
9196 if (cfun->calls_alloca)
9197 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9199 frame->args_size = 0;
9200 frame->cprestore_size = 0;
9204 frame->args_size = crtl->outgoing_args_size;
9205 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9207 offset = frame->args_size + frame->cprestore_size;
9209 /* Move above the local variables. */
9210 frame->var_size = MIPS_STACK_ALIGN (size);
9211 offset += frame->var_size;
9213 /* Find out which GPRs we need to save. */
9214 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9215 if (mips_save_reg_p (regno))
9218 frame->mask |= 1 << (regno - GP_REG_FIRST);
9221 /* If this function calls eh_return, we must also save and restore the
9222 EH data registers. */
9223 if (crtl->calls_eh_return)
9224 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9227 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9230 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9231 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9232 save all later registers too. */
9233 if (GENERATE_MIPS16E_SAVE_RESTORE)
9235 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9236 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9237 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9238 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9241 /* Move above the GPR save area. */
9242 if (frame->num_gp > 0)
9244 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9245 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9248 /* Find out which FPRs we need to save. This loop must iterate over
9249 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9250 if (TARGET_HARD_FLOAT)
9251 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9252 if (mips_save_reg_p (regno))
9254 frame->num_fp += MAX_FPRS_PER_FMT;
9255 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9258 /* Move above the FPR save area. */
9259 if (frame->num_fp > 0)
9261 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9262 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9265 /* Add in space for the interrupt context information. */
9266 if (cfun->machine->interrupt_handler_p)
9269 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9272 frame->acc_mask |= (1 << 0);
9275 /* Check accumulators 1, 2, 3. */
9276 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9277 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9280 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9283 /* All interrupt context functions need space to preserve STATUS. */
9284 frame->num_cop0_regs++;
9286 /* If we don't keep interrupts masked, we need to save EPC. */
9287 if (!cfun->machine->keep_interrupts_masked_p)
9288 frame->num_cop0_regs++;
9291 /* Move above the accumulator save area. */
9292 if (frame->num_acc > 0)
9294 /* Each accumulator needs 2 words. */
9295 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9296 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9299 /* Move above the COP0 register save area. */
9300 if (frame->num_cop0_regs > 0)
9302 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9303 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9306 /* Move above the callee-allocated varargs save area. */
9307 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9308 frame->arg_pointer_offset = offset;
9310 /* Move above the callee-allocated area for pretend stack arguments. */
9311 offset += crtl->args.pretend_args_size;
9312 frame->total_size = offset;
9314 /* Work out the offsets of the save areas from the top of the frame. */
9315 if (frame->gp_sp_offset > 0)
9316 frame->gp_save_offset = frame->gp_sp_offset - offset;
9317 if (frame->fp_sp_offset > 0)
9318 frame->fp_save_offset = frame->fp_sp_offset - offset;
9319 if (frame->acc_sp_offset > 0)
9320 frame->acc_save_offset = frame->acc_sp_offset - offset;
9321 if (frame->num_cop0_regs > 0)
9322 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9324 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9325 arguments. This tends to increase the chances of using unextended
9326 instructions for local variables and incoming arguments. */
9328 frame->hard_frame_pointer_offset = frame->args_size;
9331 /* Return the style of GP load sequence that is being used for the
9332 current function. */
9334 enum mips_loadgp_style
9335 mips_current_loadgp_style (void)
9337 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9343 if (TARGET_ABSOLUTE_ABICALLS)
9344 return LOADGP_ABSOLUTE;
9346 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9349 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9352 mips_frame_pointer_required (void)
9354 /* If the function contains dynamic stack allocations, we need to
9355 use the frame pointer to access the static parts of the frame. */
9356 if (cfun->calls_alloca)
9359 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9360 reload may be unable to compute the address of a local variable,
9361 since there is no way to add a large constant to the stack pointer
9362 without using a second temporary register. */
9365 mips_compute_frame_info ();
9366 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9373 /* Make sure that we're not trying to eliminate to the wrong hard frame
9377 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9379 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9382 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9383 or argument pointer. TO is either the stack pointer or hard frame
9387 mips_initial_elimination_offset (int from, int to)
9389 HOST_WIDE_INT offset;
9391 mips_compute_frame_info ();
9393 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9396 case FRAME_POINTER_REGNUM:
9397 if (FRAME_GROWS_DOWNWARD)
9398 offset = (cfun->machine->frame.args_size
9399 + cfun->machine->frame.cprestore_size
9400 + cfun->machine->frame.var_size);
9405 case ARG_POINTER_REGNUM:
9406 offset = cfun->machine->frame.arg_pointer_offset;
9413 if (to == HARD_FRAME_POINTER_REGNUM)
9414 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9419 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9422 mips_extra_live_on_entry (bitmap regs)
9426 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9427 the global pointer. */
9428 if (!TARGET_ABSOLUTE_ABICALLS)
9429 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9431 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9432 the global pointer. */
9434 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9436 /* See the comment above load_call<mode> for details. */
9437 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9441 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9445 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9450 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9453 /* Emit code to change the current function's return address to
9454 ADDRESS. SCRATCH is available as a scratch register, if needed.
9455 ADDRESS and SCRATCH are both word-mode GPRs. */
9458 mips_set_return_address (rtx address, rtx scratch)
9462 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9463 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9464 cfun->machine->frame.gp_sp_offset);
9465 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9468 /* Return true if the current function has a cprestore slot. */
9471 mips_cfun_has_cprestore_slot_p (void)
9473 return (cfun->machine->global_pointer != INVALID_REGNUM
9474 && cfun->machine->frame.cprestore_size > 0);
9477 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9478 cprestore slot. LOAD_P is true if the caller wants to load from
9479 the cprestore slot; it is false if the caller wants to store to
9483 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9486 const struct mips_frame_info *frame;
9488 frame = &cfun->machine->frame;
9489 /* .cprestore always uses the stack pointer instead of the frame pointer.
9490 We have a free choice for direct stores for non-MIPS16 functions,
9491 and for MIPS16 functions whose cprestore slot is in range of the
9492 stack pointer. Using the stack pointer would sometimes give more
9493 (early) scheduling freedom, but using the frame pointer would
9494 sometimes give more (late) scheduling freedom. It's hard to
9495 predict which applies to a given function, so let's keep things
9498 Loads must always use the frame pointer in functions that call
9499 alloca, and there's little benefit to using the stack pointer
9501 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9503 *base = hard_frame_pointer_rtx;
9504 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9508 *base = stack_pointer_rtx;
9509 *offset = frame->args_size;
9513 /* Return true if X is the load or store address of the cprestore slot;
9514 LOAD_P says which. */
9517 mips_cprestore_address_p (rtx x, bool load_p)
9519 rtx given_base, required_base;
9520 HOST_WIDE_INT given_offset, required_offset;
9522 mips_split_plus (x, &given_base, &given_offset);
9523 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9524 return given_base == required_base && given_offset == required_offset;
9527 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9528 going to load from it, false if we are going to store to it.
9529 Use TEMP as a temporary register if need be. */
9532 mips_cprestore_slot (rtx temp, bool load_p)
9535 HOST_WIDE_INT offset;
9537 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9538 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9541 /* Emit instructions to save global pointer value GP into cprestore
9542 slot MEM. OFFSET is the offset that MEM applies to the base register.
9544 MEM may not be a legitimate address. If it isn't, TEMP is a
9545 temporary register that can be used, otherwise it is a SCRATCH. */
9548 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9550 if (TARGET_CPRESTORE_DIRECTIVE)
9552 gcc_assert (gp == pic_offset_table_rtx);
9553 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
9556 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9559 /* Restore $gp from its save slot, using TEMP as a temporary base register
9560 if need be. This function is for o32 and o64 abicalls only.
9562 See mips_must_initialize_gp_p for details about how we manage the
9566 mips_restore_gp_from_cprestore_slot (rtx temp)
9568 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9570 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9572 emit_note (NOTE_INSN_DELETED);
9578 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9579 mips_emit_move (pic_offset_table_rtx, temp);
9582 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9583 if (!TARGET_EXPLICIT_RELOCS)
9584 emit_insn (gen_blockage ());
9587 /* A function to save or store a register. The first argument is the
9588 register and the second is the stack slot. */
9589 typedef void (*mips_save_restore_fn) (rtx, rtx);
9591 /* Use FN to save or restore register REGNO. MODE is the register's
9592 mode and OFFSET is the offset of its save slot from the current
9596 mips_save_restore_reg (enum machine_mode mode, int regno,
9597 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9601 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9602 fn (gen_rtx_REG (mode, regno), mem);
9605 /* Call FN for each accumlator that is saved by the current function.
9606 SP_OFFSET is the offset of the current stack pointer from the start
9610 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9612 HOST_WIDE_INT offset;
9615 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9616 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9618 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9619 offset -= UNITS_PER_WORD;
9620 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9621 offset -= UNITS_PER_WORD;
9624 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9625 if (BITSET_P (cfun->machine->frame.acc_mask,
9626 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9628 mips_save_restore_reg (word_mode, regno, offset, fn);
9629 offset -= UNITS_PER_WORD;
9633 /* Call FN for each register that is saved by the current function.
9634 SP_OFFSET is the offset of the current stack pointer from the start
9638 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9639 mips_save_restore_fn fn)
9641 enum machine_mode fpr_mode;
9642 HOST_WIDE_INT offset;
9645 /* Save registers starting from high to low. The debuggers prefer at least
9646 the return register be stored at func+4, and also it allows us not to
9647 need a nop in the epilogue if at least one register is reloaded in
9648 addition to return address. */
9649 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9650 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9651 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9653 /* Record the ra offset for use by mips_function_profiler. */
9654 if (regno == RETURN_ADDR_REGNUM)
9655 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
9656 mips_save_restore_reg (word_mode, regno, offset, fn);
9657 offset -= UNITS_PER_WORD;
9660 /* This loop must iterate over the same space as its companion in
9661 mips_compute_frame_info. */
9662 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9663 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9664 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9665 regno >= FP_REG_FIRST;
9666 regno -= MAX_FPRS_PER_FMT)
9667 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9669 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9670 offset -= GET_MODE_SIZE (fpr_mode);
9674 /* Return true if a move between register REGNO and its save slot (MEM)
9675 can be done in a single move. LOAD_P is true if we are loading
9676 from the slot, false if we are storing to it. */
9679 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9681 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9682 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9685 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9686 GET_MODE (mem), mem, load_p) == NO_REGS;
9689 /* Emit a move from SRC to DEST, given that one of them is a register
9690 save slot and that the other is a register. TEMP is a temporary
9691 GPR of the same mode that is available if need be. */
9694 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9701 regno = REGNO (src);
9706 regno = REGNO (dest);
9710 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9712 /* We don't yet know whether we'll need this instruction or not.
9713 Postpone the decision by emitting a ghost move. This move
9714 is specifically not frame-related; only the split version is. */
9716 emit_insn (gen_move_gpdi (dest, src));
9718 emit_insn (gen_move_gpsi (dest, src));
9722 if (regno == HI_REGNUM)
9726 mips_emit_move (temp, src);
9728 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9729 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9731 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9732 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9737 emit_insn (gen_mfhidi_ti (temp,
9738 gen_rtx_REG (TImode, MD_REG_FIRST)));
9740 emit_insn (gen_mfhisi_di (temp,
9741 gen_rtx_REG (DImode, MD_REG_FIRST)));
9742 mips_emit_move (dest, temp);
9745 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9746 mips_emit_move (dest, src);
9749 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9750 mips_emit_move (temp, src);
9751 mips_emit_move (dest, temp);
9754 mips_set_frame_expr (mips_frame_set (dest, src));
9757 /* If we're generating n32 or n64 abicalls, and the current function
9758 does not use $28 as its global pointer, emit a cplocal directive.
9759 Use pic_offset_table_rtx as the argument to the directive. */
9762 mips_output_cplocal (void)
9764 if (!TARGET_EXPLICIT_RELOCS
9765 && mips_must_initialize_gp_p ()
9766 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9767 output_asm_insn (".cplocal %+", 0);
9770 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9773 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9777 #ifdef SDB_DEBUGGING_INFO
9778 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9779 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9782 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9783 floating-point arguments. */
9785 && TARGET_HARD_FLOAT_ABI
9786 && crtl->args.info.fp_code != 0)
9787 mips16_build_function_stub ();
9789 /* Get the function name the same way that toplev.c does before calling
9790 assemble_start_function. This is needed so that the name used here
9791 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9792 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9793 mips_start_function_definition (fnname, TARGET_MIPS16);
9795 /* Output MIPS-specific frame information. */
9796 if (!flag_inhibit_size_directive)
9798 const struct mips_frame_info *frame;
9800 frame = &cfun->machine->frame;
9802 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9804 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9805 "# vars= " HOST_WIDE_INT_PRINT_DEC
9807 ", args= " HOST_WIDE_INT_PRINT_DEC
9808 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9809 reg_names[frame_pointer_needed
9810 ? HARD_FRAME_POINTER_REGNUM
9811 : STACK_POINTER_REGNUM],
9812 (frame_pointer_needed
9813 ? frame->total_size - frame->hard_frame_pointer_offset
9814 : frame->total_size),
9815 reg_names[RETURN_ADDR_REGNUM],
9817 frame->num_gp, frame->num_fp,
9819 frame->cprestore_size);
9821 /* .mask MASK, OFFSET. */
9822 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9823 frame->mask, frame->gp_save_offset);
9825 /* .fmask MASK, OFFSET. */
9826 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9827 frame->fmask, frame->fp_save_offset);
9830 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9831 Also emit the ".set noreorder; .set nomacro" sequence for functions
9833 if (mips_must_initialize_gp_p ()
9834 && mips_current_loadgp_style () == LOADGP_OLDABI)
9838 /* This is a fixed-form sequence. The position of the
9839 first two instructions is important because of the
9840 way _gp_disp is defined. */
9841 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9842 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9843 output_asm_insn ("sll\t$2,16", 0);
9844 output_asm_insn ("addu\t$2,$3", 0);
9848 /* .cpload must be in a .set noreorder but not a
9849 .set nomacro block. */
9850 mips_push_asm_switch (&mips_noreorder);
9851 output_asm_insn (".cpload\t%^", 0);
9852 if (!cfun->machine->all_noreorder_p)
9853 mips_pop_asm_switch (&mips_noreorder);
9855 mips_push_asm_switch (&mips_nomacro);
9858 else if (cfun->machine->all_noreorder_p)
9860 mips_push_asm_switch (&mips_noreorder);
9861 mips_push_asm_switch (&mips_nomacro);
9864 /* Tell the assembler which register we're using as the global
9865 pointer. This is needed for thunks, since they can use either
9866 explicit relocs or assembler macros. */
9867 mips_output_cplocal ();
9870 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9873 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9874 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9878 /* Reinstate the normal $gp. */
9879 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9880 mips_output_cplocal ();
9882 if (cfun->machine->all_noreorder_p)
9884 mips_pop_asm_switch (&mips_nomacro);
9885 mips_pop_asm_switch (&mips_noreorder);
9888 /* Get the function name the same way that toplev.c does before calling
9889 assemble_start_function. This is needed so that the name used here
9890 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9891 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9892 mips_end_function_definition (fnname);
9895 /* Emit an optimisation barrier for accesses to the current frame. */
9898 mips_frame_barrier (void)
9900 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
9903 /* Save register REG to MEM. Make the instruction frame-related. */
9906 mips_save_reg (rtx reg, rtx mem)
9908 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9912 if (mips_split_64bit_move_p (mem, reg))
9913 mips_split_doubleword_move (mem, reg);
9915 mips_emit_move (mem, reg);
9917 x1 = mips_frame_set (mips_subword (mem, false),
9918 mips_subword (reg, false));
9919 x2 = mips_frame_set (mips_subword (mem, true),
9920 mips_subword (reg, true));
9921 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9924 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9927 /* The __gnu_local_gp symbol. */
9929 static GTY(()) rtx mips_gnu_local_gp;
9931 /* If we're generating n32 or n64 abicalls, emit instructions
9932 to set up the global pointer. */
9935 mips_emit_loadgp (void)
9937 rtx addr, offset, incoming_address, base, index, pic_reg;
9939 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9940 switch (mips_current_loadgp_style ())
9942 case LOADGP_ABSOLUTE:
9943 if (mips_gnu_local_gp == NULL)
9945 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9946 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9948 emit_insn (PMODE_INSN (gen_loadgp_absolute,
9949 (pic_reg, mips_gnu_local_gp)));
9953 /* Added by mips_output_function_prologue. */
9957 addr = XEXP (DECL_RTL (current_function_decl), 0);
9958 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9959 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9960 emit_insn (PMODE_INSN (gen_loadgp_newabi,
9961 (pic_reg, offset, incoming_address)));
9965 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9966 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9967 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
9975 emit_insn (PMODE_INSN (gen_copygp_mips16,
9976 (pic_offset_table_rtx, pic_reg)));
9978 /* Emit a blockage if there are implicit uses of the GP register.
9979 This includes profiled functions, because FUNCTION_PROFILE uses
9981 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9982 emit_insn (gen_loadgp_blockage ());
9985 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9988 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
9990 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
9993 /* Expand the "prologue" pattern. */
9996 mips_expand_prologue (void)
9998 const struct mips_frame_info *frame;
10000 unsigned int nargs;
10003 if (cfun->machine->global_pointer != INVALID_REGNUM)
10005 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10006 or implicitly. If so, we can commit to using a global pointer
10007 straight away, otherwise we need to defer the decision. */
10008 if (mips_cfun_has_inflexible_gp_ref_p ()
10009 || mips_cfun_has_flexible_gp_ref_p ())
10011 cfun->machine->must_initialize_gp_p = true;
10012 cfun->machine->must_restore_gp_when_clobbered_p = true;
10015 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10018 frame = &cfun->machine->frame;
10019 size = frame->total_size;
10021 if (flag_stack_usage_info)
10022 current_function_static_stack_size = size;
10024 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10025 bytes beforehand; this is enough to cover the register save area
10026 without going out of range. */
10027 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10028 || frame->num_cop0_regs > 0)
10030 HOST_WIDE_INT step1;
10032 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10033 if (GENERATE_MIPS16E_SAVE_RESTORE)
10035 HOST_WIDE_INT offset;
10036 unsigned int mask, regno;
10038 /* Try to merge argument stores into the save instruction. */
10039 nargs = mips16e_collect_argument_saves ();
10041 /* Build the save instruction. */
10042 mask = frame->mask;
10043 insn = mips16e_build_save_restore (false, &mask, &offset,
10045 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10046 mips_frame_barrier ();
10049 /* Check if we need to save other registers. */
10050 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10051 if (BITSET_P (mask, regno - GP_REG_FIRST))
10053 offset -= UNITS_PER_WORD;
10054 mips_save_restore_reg (word_mode, regno,
10055 offset, mips_save_reg);
10060 if (cfun->machine->interrupt_handler_p)
10062 HOST_WIDE_INT offset;
10065 /* If this interrupt is using a shadow register set, we need to
10066 get the stack pointer from the previous register set. */
10067 if (cfun->machine->use_shadow_register_set_p)
10068 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10069 stack_pointer_rtx));
10071 if (!cfun->machine->keep_interrupts_masked_p)
10073 /* Move from COP0 Cause to K0. */
10074 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10075 gen_rtx_REG (SImode,
10076 COP0_CAUSE_REG_NUM)));
10077 /* Move from COP0 EPC to K1. */
10078 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10079 gen_rtx_REG (SImode,
10080 COP0_EPC_REG_NUM)));
10083 /* Allocate the first part of the frame. */
10084 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10086 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10087 mips_frame_barrier ();
10090 /* Start at the uppermost location for saving. */
10091 offset = frame->cop0_sp_offset - size;
10092 if (!cfun->machine->keep_interrupts_masked_p)
10094 /* Push EPC into its stack slot. */
10095 mem = gen_frame_mem (word_mode,
10096 plus_constant (stack_pointer_rtx,
10098 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10099 offset -= UNITS_PER_WORD;
10102 /* Move from COP0 Status to K1. */
10103 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10104 gen_rtx_REG (SImode,
10105 COP0_STATUS_REG_NUM)));
10107 /* Right justify the RIPL in k0. */
10108 if (!cfun->machine->keep_interrupts_masked_p)
10109 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10110 gen_rtx_REG (SImode, K0_REG_NUM),
10111 GEN_INT (CAUSE_IPL)));
10113 /* Push Status into its stack slot. */
10114 mem = gen_frame_mem (word_mode,
10115 plus_constant (stack_pointer_rtx, offset));
10116 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10117 offset -= UNITS_PER_WORD;
10119 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10120 if (!cfun->machine->keep_interrupts_masked_p)
10121 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10124 gen_rtx_REG (SImode, K0_REG_NUM)));
10126 if (!cfun->machine->keep_interrupts_masked_p)
10127 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10128 IE is already the correct value, so we don't have to do
10129 anything explicit. */
10130 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10133 gen_rtx_REG (SImode, GP_REG_FIRST)));
10135 /* Disable interrupts by clearing the KSU, ERL, EXL,
10137 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10140 gen_rtx_REG (SImode, GP_REG_FIRST)));
10144 insn = gen_add3_insn (stack_pointer_rtx,
10147 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10148 mips_frame_barrier ();
10151 mips_for_each_saved_acc (size, mips_save_reg);
10152 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10156 /* Allocate the rest of the frame. */
10159 if (SMALL_OPERAND (-size))
10160 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10162 GEN_INT (-size)))) = 1;
10165 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10168 /* There are no instructions to add or subtract registers
10169 from the stack pointer, so use the frame pointer as a
10170 temporary. We should always be using a frame pointer
10171 in this case anyway. */
10172 gcc_assert (frame_pointer_needed);
10173 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10174 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10175 hard_frame_pointer_rtx,
10176 MIPS_PROLOGUE_TEMP (Pmode)));
10177 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10180 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10182 MIPS_PROLOGUE_TEMP (Pmode)));
10184 /* Describe the combined effect of the previous instructions. */
10185 mips_set_frame_expr
10186 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10187 plus_constant (stack_pointer_rtx, -size)));
10189 mips_frame_barrier ();
10192 /* Set up the frame pointer, if we're using one. */
10193 if (frame_pointer_needed)
10195 HOST_WIDE_INT offset;
10197 offset = frame->hard_frame_pointer_offset;
10200 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10201 RTX_FRAME_RELATED_P (insn) = 1;
10203 else if (SMALL_OPERAND (offset))
10205 insn = gen_add3_insn (hard_frame_pointer_rtx,
10206 stack_pointer_rtx, GEN_INT (offset));
10207 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10211 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10212 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10213 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10214 hard_frame_pointer_rtx,
10215 MIPS_PROLOGUE_TEMP (Pmode)));
10216 mips_set_frame_expr
10217 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10218 plus_constant (stack_pointer_rtx, offset)));
10222 mips_emit_loadgp ();
10224 /* Initialize the $gp save slot. */
10225 if (mips_cfun_has_cprestore_slot_p ())
10227 rtx base, mem, gp, temp;
10228 HOST_WIDE_INT offset;
10230 mips_get_cprestore_base_and_offset (&base, &offset, false);
10231 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10232 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10233 temp = (SMALL_OPERAND (offset)
10234 ? gen_rtx_SCRATCH (Pmode)
10235 : MIPS_PROLOGUE_TEMP (Pmode));
10236 emit_insn (PMODE_INSN (gen_potential_cprestore,
10237 (mem, GEN_INT (offset), gp, temp)));
10239 mips_get_cprestore_base_and_offset (&base, &offset, true);
10240 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10241 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
10244 /* We need to search back to the last use of K0 or K1. */
10245 if (cfun->machine->interrupt_handler_p)
10247 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10249 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10251 /* Emit a move from K1 to COP0 Status after insn. */
10252 gcc_assert (insn != NULL_RTX);
10253 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10254 gen_rtx_REG (SImode, K1_REG_NUM)),
10258 /* If we are profiling, make sure no instructions are scheduled before
10259 the call to mcount. */
10261 emit_insn (gen_blockage ());
10264 /* Attach all pending register saves to the previous instruction.
10265 Return that instruction. */
10268 mips_epilogue_emit_cfa_restores (void)
10272 insn = get_last_insn ();
10273 gcc_assert (insn && !REG_NOTES (insn));
10274 if (mips_epilogue.cfa_restores)
10276 RTX_FRAME_RELATED_P (insn) = 1;
10277 REG_NOTES (insn) = mips_epilogue.cfa_restores;
10278 mips_epilogue.cfa_restores = 0;
10283 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
10284 now at REG + OFFSET. */
10287 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
10291 insn = mips_epilogue_emit_cfa_restores ();
10292 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
10294 RTX_FRAME_RELATED_P (insn) = 1;
10295 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
10296 plus_constant (reg, offset),
10298 mips_epilogue.cfa_reg = reg;
10299 mips_epilogue.cfa_offset = offset;
10303 /* Emit instructions to restore register REG from slot MEM. Also update
10304 the cfa_restores list. */
10307 mips_restore_reg (rtx reg, rtx mem)
10309 /* There's no MIPS16 instruction to load $31 directly. Load into
10310 $7 instead and adjust the return insn appropriately. */
10311 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10312 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10313 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10315 mips_add_cfa_restore (mips_subword (reg, true));
10316 mips_add_cfa_restore (mips_subword (reg, false));
10319 mips_add_cfa_restore (reg);
10321 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10322 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
10323 /* The CFA is currently defined in terms of the register whose
10324 value we have just restored. Redefine the CFA in terms of
10325 the stack pointer. */
10326 mips_epilogue_set_cfa (stack_pointer_rtx,
10327 mips_epilogue.cfa_restore_sp_offset);
10330 /* Emit code to set the stack pointer to BASE + OFFSET, given that
10331 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
10332 BASE, if not the stack pointer, is available as a temporary. */
10335 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
10337 if (base == stack_pointer_rtx && offset == const0_rtx)
10340 mips_frame_barrier ();
10341 if (offset == const0_rtx)
10343 emit_move_insn (stack_pointer_rtx, base);
10344 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10346 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
10348 emit_insn (gen_add3_insn (base, base, offset));
10349 mips_epilogue_set_cfa (base, new_frame_size);
10350 emit_move_insn (stack_pointer_rtx, base);
10354 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
10355 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10359 /* Emit any instructions needed before a return. */
10362 mips_expand_before_return (void)
10364 /* When using a call-clobbered gp, we start out with unified call
10365 insns that include instructions to restore the gp. We then split
10366 these unified calls after reload. These split calls explicitly
10367 clobber gp, so there is no need to define
10368 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10370 For consistency, we should also insert an explicit clobber of $28
10371 before return insns, so that the post-reload optimizers know that
10372 the register is not live on exit. */
10373 if (TARGET_CALL_CLOBBERED_GP)
10374 emit_clobber (pic_offset_table_rtx);
10377 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10381 mips_expand_epilogue (bool sibcall_p)
10383 const struct mips_frame_info *frame;
10384 HOST_WIDE_INT step1, step2;
10385 rtx base, adjust, insn;
10387 if (!sibcall_p && mips_can_use_return_insn ())
10389 emit_jump_insn (gen_return ());
10393 /* In MIPS16 mode, if the return value should go into a floating-point
10394 register, we need to call a helper routine to copy it over. */
10395 if (mips16_cfun_returns_in_fpr_p ())
10396 mips16_copy_fpr_return_value ();
10398 /* Split the frame into two. STEP1 is the amount of stack we should
10399 deallocate before restoring the registers. STEP2 is the amount we
10400 should deallocate afterwards.
10402 Start off by assuming that no registers need to be restored. */
10403 frame = &cfun->machine->frame;
10404 step1 = frame->total_size;
10407 /* Work out which register holds the frame address. */
10408 if (!frame_pointer_needed)
10409 base = stack_pointer_rtx;
10412 base = hard_frame_pointer_rtx;
10413 step1 -= frame->hard_frame_pointer_offset;
10415 mips_epilogue.cfa_reg = base;
10416 mips_epilogue.cfa_offset = step1;
10417 mips_epilogue.cfa_restores = NULL_RTX;
10419 /* If we need to restore registers, deallocate as much stack as
10420 possible in the second step without going out of range. */
10421 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10422 || frame->num_cop0_regs > 0)
10424 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10428 /* Get an rtx for STEP1 that we can add to BASE. */
10429 adjust = GEN_INT (step1);
10430 if (!SMALL_OPERAND (step1))
10432 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10433 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10435 mips_deallocate_stack (base, adjust, step2);
10437 /* If we're using addressing macros, $gp is implicitly used by all
10438 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10440 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10441 emit_insn (gen_blockage ());
10443 mips_epilogue.cfa_restore_sp_offset = step2;
10444 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10446 unsigned int regno, mask;
10447 HOST_WIDE_INT offset;
10450 /* Generate the restore instruction. */
10451 mask = frame->mask;
10452 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10454 /* Restore any other registers manually. */
10455 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10456 if (BITSET_P (mask, regno - GP_REG_FIRST))
10458 offset -= UNITS_PER_WORD;
10459 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10462 /* Restore the remaining registers and deallocate the final bit
10464 mips_frame_barrier ();
10465 emit_insn (restore);
10466 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
10470 /* Restore the registers. */
10471 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10472 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10475 if (cfun->machine->interrupt_handler_p)
10477 HOST_WIDE_INT offset;
10480 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10481 if (!cfun->machine->keep_interrupts_masked_p)
10483 /* Restore the original EPC. */
10484 mem = gen_frame_mem (word_mode,
10485 plus_constant (stack_pointer_rtx, offset));
10486 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10487 offset -= UNITS_PER_WORD;
10489 /* Move to COP0 EPC. */
10490 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10491 gen_rtx_REG (SImode, K0_REG_NUM)));
10494 /* Restore the original Status. */
10495 mem = gen_frame_mem (word_mode,
10496 plus_constant (stack_pointer_rtx, offset));
10497 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10498 offset -= UNITS_PER_WORD;
10500 /* If we don't use shoadow register set, we need to update SP. */
10501 if (!cfun->machine->use_shadow_register_set_p)
10502 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
10504 /* The choice of position is somewhat arbitrary in this case. */
10505 mips_epilogue_emit_cfa_restores ();
10507 /* Move to COP0 Status. */
10508 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10509 gen_rtx_REG (SImode, K0_REG_NUM)));
10512 /* Deallocate the final bit of the frame. */
10513 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
10515 gcc_assert (!mips_epilogue.cfa_restores);
10517 /* Add in the __builtin_eh_return stack adjustment. We need to
10518 use a temporary in MIPS16 code. */
10519 if (crtl->calls_eh_return)
10523 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10524 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10525 MIPS_EPILOGUE_TEMP (Pmode),
10526 EH_RETURN_STACKADJ_RTX));
10527 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10530 emit_insn (gen_add3_insn (stack_pointer_rtx,
10532 EH_RETURN_STACKADJ_RTX));
10537 mips_expand_before_return ();
10538 if (cfun->machine->interrupt_handler_p)
10540 /* Interrupt handlers generate eret or deret. */
10541 if (cfun->machine->use_debug_exception_return_p)
10542 emit_jump_insn (gen_mips_deret ());
10544 emit_jump_insn (gen_mips_eret ());
10550 /* When generating MIPS16 code, the normal
10551 mips_for_each_saved_gpr_and_fpr path will restore the return
10552 address into $7 rather than $31. */
10554 && !GENERATE_MIPS16E_SAVE_RESTORE
10555 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10557 /* simple_returns cannot rely on values that are only available
10558 on paths through the epilogue (because return paths that do
10559 not pass through the epilogue may nevertheless reuse a
10560 simple_return that occurs at the end of the epilogue).
10561 Use a normal return here instead. */
10562 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
10563 pat = gen_return_internal (reg);
10567 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
10568 pat = gen_simple_return_internal (reg);
10570 emit_jump_insn (pat);
10574 /* Search from the beginning to the first use of K0 or K1. */
10575 if (cfun->machine->interrupt_handler_p
10576 && !cfun->machine->keep_interrupts_masked_p)
10578 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10580 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10582 gcc_assert (insn != NULL_RTX);
10583 /* Insert disable interrupts before the first use of K0 or K1. */
10584 emit_insn_before (gen_mips_di (), insn);
10585 emit_insn_before (gen_mips_ehb (), insn);
10589 /* Return nonzero if this function is known to have a null epilogue.
10590 This allows the optimizer to omit jumps to jumps if no stack
10594 mips_can_use_return_insn (void)
10596 /* Interrupt handlers need to go through the epilogue. */
10597 if (cfun->machine->interrupt_handler_p)
10600 if (!reload_completed)
10606 /* In MIPS16 mode, a function that returns a floating-point value
10607 needs to arrange to copy the return value into the floating-point
10609 if (mips16_cfun_returns_in_fpr_p ())
10612 return cfun->machine->frame.total_size == 0;
10615 /* Return true if register REGNO can store a value of mode MODE.
10616 The result of this function is cached in mips_hard_regno_mode_ok. */
10619 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10622 enum mode_class mclass;
10624 if (mode == CCV2mode)
10625 return (ISA_HAS_8CC
10626 && ST_REG_P (regno)
10627 && (regno - ST_REG_FIRST) % 2 == 0);
10629 if (mode == CCV4mode)
10630 return (ISA_HAS_8CC
10631 && ST_REG_P (regno)
10632 && (regno - ST_REG_FIRST) % 4 == 0);
10634 if (mode == CCmode)
10637 return regno == FPSW_REGNUM;
10639 return (ST_REG_P (regno)
10640 || GP_REG_P (regno)
10641 || FP_REG_P (regno));
10644 size = GET_MODE_SIZE (mode);
10645 mclass = GET_MODE_CLASS (mode);
10647 if (GP_REG_P (regno))
10648 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10650 if (FP_REG_P (regno)
10651 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10652 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10654 /* Allow TFmode for CCmode reloads. */
10655 if (mode == TFmode && ISA_HAS_8CC)
10658 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10659 if (TARGET_LOONGSON_VECTORS
10660 && (mode == V2SImode
10661 || mode == V4HImode
10662 || mode == V8QImode
10663 || mode == DImode))
10666 if (mclass == MODE_FLOAT
10667 || mclass == MODE_COMPLEX_FLOAT
10668 || mclass == MODE_VECTOR_FLOAT)
10669 return size <= UNITS_PER_FPVALUE;
10671 /* Allow integer modes that fit into a single register. We need
10672 to put integers into FPRs when using instructions like CVT
10673 and TRUNC. There's no point allowing sizes smaller than a word,
10674 because the FPU has no appropriate load/store instructions. */
10675 if (mclass == MODE_INT)
10676 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10679 if (ACC_REG_P (regno)
10680 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10682 if (MD_REG_P (regno))
10684 /* After a multiplication or division, clobbering HI makes
10685 the value of LO unpredictable, and vice versa. This means
10686 that, for all interesting cases, HI and LO are effectively
10689 We model this by requiring that any value that uses HI
10691 if (size <= UNITS_PER_WORD * 2)
10692 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10696 /* DSP accumulators do not have the same restrictions as
10697 HI and LO, so we can treat them as normal doubleword
10699 if (size <= UNITS_PER_WORD)
10702 if (size <= UNITS_PER_WORD * 2
10703 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10708 if (ALL_COP_REG_P (regno))
10709 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10711 if (regno == GOT_VERSION_REGNUM)
10712 return mode == SImode;
10717 /* Implement HARD_REGNO_NREGS. */
10720 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10722 if (ST_REG_P (regno))
10723 /* The size of FP status registers is always 4, because they only hold
10724 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10725 return (GET_MODE_SIZE (mode) + 3) / 4;
10727 if (FP_REG_P (regno))
10728 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10730 /* All other registers are word-sized. */
10731 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10734 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10735 in mips_hard_regno_nregs. */
10738 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10744 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10745 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10747 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
10748 size = MIN (size, 4);
10749 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10751 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10753 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
10754 size = MIN (size, UNITS_PER_FPREG);
10755 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10757 if (!hard_reg_set_empty_p (left))
10758 size = MIN (size, UNITS_PER_WORD);
10759 return (GET_MODE_SIZE (mode) + size - 1) / size;
10762 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10765 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10766 enum machine_mode to ATTRIBUTE_UNUSED,
10767 enum reg_class rclass)
10769 /* There are several problems with changing the modes of values in
10770 floating-point registers:
10772 - When a multi-word value is stored in paired floating-point
10773 registers, the first register always holds the low word. We
10774 therefore can't allow FPRs to change between single-word and
10775 multi-word modes on big-endian targets.
10777 - GCC assumes that each word of a multiword register can be
10778 accessed individually using SUBREGs. This is not true for
10779 floating-point registers if they are bigger than a word.
10781 - Loading a 32-bit value into a 64-bit floating-point register
10782 will not sign-extend the value, despite what LOAD_EXTEND_OP
10783 says. We can't allow FPRs to change from SImode to a wider
10784 mode on 64-bit targets.
10786 - If the FPU has already interpreted a value in one format, we
10787 must not ask it to treat the value as having a different
10790 We therefore disallow all mode changes involving FPRs. */
10791 return reg_classes_intersect_p (FP_REGS, rclass);
10794 /* Implement target hook small_register_classes_for_mode_p. */
10797 mips_small_register_classes_for_mode_p (enum machine_mode mode
10800 return TARGET_MIPS16;
10803 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10806 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10811 return TARGET_HARD_FLOAT;
10814 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10817 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10824 /* Implement MODES_TIEABLE_P. */
10827 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10829 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10830 prefer to put one of them in FPRs. */
10831 return (mode1 == mode2
10832 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10833 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10836 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
10839 mips_preferred_reload_class (rtx x, reg_class_t rclass)
10841 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10844 if (reg_class_subset_p (FP_REGS, rclass)
10845 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10848 if (reg_class_subset_p (GR_REGS, rclass))
10851 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10857 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10858 Return a "canonical" class to represent it in later calculations. */
10861 mips_canonicalize_move_class (reg_class_t rclass)
10863 /* All moves involving accumulator registers have the same cost. */
10864 if (reg_class_subset_p (rclass, ACC_REGS))
10867 /* Likewise promote subclasses of general registers to the most
10868 interesting containing class. */
10869 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10871 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10872 rclass = GENERAL_REGS;
10877 /* Return the cost of moving a value of mode MODE from a register of
10878 class FROM to a GPR. Return 0 for classes that are unions of other
10879 classes handled by this function. */
10882 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10888 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10892 /* MFLO and MFHI. */
10900 /* LUI followed by MOVF. */
10906 /* This choice of value is historical. */
10914 /* Return the cost of moving a value of mode MODE from a GPR to a
10915 register of class TO. Return 0 for classes that are unions of
10916 other classes handled by this function. */
10919 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
10924 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10928 /* MTLO and MTHI. */
10936 /* A secondary reload through an FPR scratch. */
10937 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10938 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10943 /* This choice of value is historical. */
10951 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10952 maximum of the move costs for subclasses; regclass will work out
10953 the maximum for us. */
10956 mips_register_move_cost (enum machine_mode mode,
10957 reg_class_t from, reg_class_t to)
10962 from = mips_canonicalize_move_class (from);
10963 to = mips_canonicalize_move_class (to);
10965 /* Handle moves that can be done without using general-purpose registers. */
10966 if (from == FP_REGS)
10968 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10972 /* The sequence generated by mips_expand_fcc_reload. */
10976 /* Handle cases in which only one class deviates from the ideal. */
10977 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10979 return mips_move_from_gpr_cost (mode, to);
10981 return mips_move_to_gpr_cost (mode, from);
10983 /* Handles cases that require a GPR temporary. */
10984 cost1 = mips_move_to_gpr_cost (mode, from);
10987 cost2 = mips_move_from_gpr_cost (mode, to);
10989 return cost1 + cost2;
10995 /* Implement TARGET_MEMORY_MOVE_COST. */
10998 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11000 return (mips_cost->memory_latency
11001 + memory_move_secondary_cost (mode, rclass, in));
11004 /* Return the register class required for a secondary register when
11005 copying between one of the registers in RCLASS and value X, which
11006 has mode MODE. X is the source of the move if IN_P, otherwise it
11007 is the destination. Return NO_REGS if no secondary register is
11011 mips_secondary_reload_class (enum reg_class rclass,
11012 enum machine_mode mode, rtx x, bool in_p)
11016 /* If X is a constant that cannot be loaded into $25, it must be loaded
11017 into some other GPR. No other register class allows a direct move. */
11018 if (mips_dangerous_for_la25_p (x))
11019 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11021 regno = true_regnum (x);
11024 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11025 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11031 /* Copying from accumulator registers to anywhere other than a general
11032 register requires a temporary general register. */
11033 if (reg_class_subset_p (rclass, ACC_REGS))
11034 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11035 if (ACC_REG_P (regno))
11036 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11038 /* We can only copy a value to a condition code register from a
11039 floating-point register, and even then we require a scratch
11040 floating-point register. We can only copy a value out of a
11041 condition-code register into a general register. */
11042 if (reg_class_subset_p (rclass, ST_REGS))
11046 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11048 if (ST_REG_P (regno))
11052 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11055 if (reg_class_subset_p (rclass, FP_REGS))
11058 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11059 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11060 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11063 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11064 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11067 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
11068 /* We can force the constant to memory and use lwc1
11069 and ldc1. As above, we will use pairs of lwc1s if
11070 ldc1 is not supported. */
11073 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11074 /* In this case we can use mov.fmt. */
11077 /* Otherwise, we need to reload through an integer register. */
11080 if (FP_REG_P (regno))
11081 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11086 /* Implement TARGET_MODE_REP_EXTENDED. */
11089 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11091 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11092 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11093 return SIGN_EXTEND;
11098 /* Implement TARGET_VALID_POINTER_MODE. */
11101 mips_valid_pointer_mode (enum machine_mode mode)
11103 return mode == SImode || (TARGET_64BIT && mode == DImode);
11106 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11109 mips_vector_mode_supported_p (enum machine_mode mode)
11114 return TARGET_PAIRED_SINGLE_FLOAT;
11129 return TARGET_LOONGSON_VECTORS;
11136 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11139 mips_scalar_mode_supported_p (enum machine_mode mode)
11141 if (ALL_FIXED_POINT_MODE_P (mode)
11142 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11145 return default_scalar_mode_supported_p (mode);
11148 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11150 static enum machine_mode
11151 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11153 if (TARGET_PAIRED_SINGLE_FLOAT
11159 /* Implement TARGET_INIT_LIBFUNCS. */
11162 mips_init_libfuncs (void)
11164 if (TARGET_FIX_VR4120)
11166 /* Register the special divsi3 and modsi3 functions needed to work
11167 around VR4120 division errata. */
11168 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11169 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11172 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11174 /* Register the MIPS16 -mhard-float stubs. */
11175 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11176 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11177 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11178 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11180 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11181 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11182 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11183 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11184 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11185 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11186 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11188 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11189 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11190 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11192 if (TARGET_DOUBLE_FLOAT)
11194 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11195 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11196 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11197 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11199 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11200 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11201 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11202 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11203 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11204 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11205 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11207 set_conv_libfunc (sext_optab, DFmode, SFmode,
11208 "__mips16_extendsfdf2");
11209 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11210 "__mips16_truncdfsf2");
11211 set_conv_libfunc (sfix_optab, SImode, DFmode,
11212 "__mips16_fix_truncdfsi");
11213 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11214 "__mips16_floatsidf");
11215 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11216 "__mips16_floatunsidf");
11220 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11221 on an external non-MIPS16 routine to implement __sync_synchronize.
11222 Similarly for the rest of the ll/sc libfuncs. */
11225 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11226 init_sync_libfuncs (UNITS_PER_WORD);
11230 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11233 mips_process_load_label (rtx target)
11235 rtx base, gp, intop;
11236 HOST_WIDE_INT offset;
11238 mips_multi_start ();
11242 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11243 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11247 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11248 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11252 gp = pic_offset_table_rtx;
11253 if (mips_cfun_has_cprestore_slot_p ())
11255 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11256 mips_get_cprestore_base_and_offset (&base, &offset, true);
11257 if (!SMALL_OPERAND (offset))
11259 intop = GEN_INT (CONST_HIGH_PART (offset));
11260 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11261 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11264 offset = CONST_LOW_PART (offset);
11266 intop = GEN_INT (offset);
11267 if (ISA_HAS_LOAD_DELAY)
11268 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11270 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11272 if (ISA_HAS_LOAD_DELAY)
11273 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11275 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11276 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11281 /* Return the number of instructions needed to load a label into $AT. */
11283 static unsigned int
11284 mips_load_label_num_insns (void)
11286 if (cfun->machine->load_label_num_insns == 0)
11288 mips_process_load_label (pc_rtx);
11289 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11291 return cfun->machine->load_label_num_insns;
11294 /* Emit an asm sequence to start a noat block and load the address
11295 of a label into $1. */
11298 mips_output_load_label (rtx target)
11300 mips_push_asm_switch (&mips_noat);
11301 if (TARGET_EXPLICIT_RELOCS)
11303 mips_process_load_label (target);
11304 mips_multi_write ();
11308 if (Pmode == DImode)
11309 output_asm_insn ("dla\t%@,%0", &target);
11311 output_asm_insn ("la\t%@,%0", &target);
11315 /* Return the length of INSN. LENGTH is the initial length computed by
11316 attributes in the machine-description file. */
11319 mips_adjust_insn_length (rtx insn, int length)
11321 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11322 of a PIC long-branch sequence. Substitute the correct value. */
11323 if (length == MAX_PIC_BRANCH_LENGTH
11324 && INSN_CODE (insn) >= 0
11325 && get_attr_type (insn) == TYPE_BRANCH)
11327 /* Add the branch-over instruction and its delay slot, if this
11328 is a conditional branch. */
11329 length = simplejump_p (insn) ? 0 : 8;
11331 /* Load the label into $AT and jump to it. Ignore the delay
11332 slot of the jump. */
11333 length += 4 * mips_load_label_num_insns() + 4;
11336 /* A unconditional jump has an unfilled delay slot if it is not part
11337 of a sequence. A conditional jump normally has a delay slot, but
11338 does not on MIPS16. */
11339 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11342 /* See how many nops might be needed to avoid hardware hazards. */
11343 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11344 switch (get_attr_hazard (insn))
11358 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11359 the .md file length attributes are 4-based for both modes.
11360 Adjust the MIPS16 ones here. */
11367 /* Return the assembly code for INSN, which has the operands given by
11368 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11369 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11370 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11371 version of BRANCH_IF_TRUE. */
11374 mips_output_conditional_branch (rtx insn, rtx *operands,
11375 const char *branch_if_true,
11376 const char *branch_if_false)
11378 unsigned int length;
11379 rtx taken, not_taken;
11381 gcc_assert (LABEL_P (operands[0]));
11383 length = get_attr_length (insn);
11386 /* Just a simple conditional branch. */
11387 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11388 return branch_if_true;
11391 /* Generate a reversed branch around a direct jump. This fallback does
11392 not use branch-likely instructions. */
11393 mips_branch_likely = false;
11394 not_taken = gen_label_rtx ();
11395 taken = operands[0];
11397 /* Generate the reversed branch to NOT_TAKEN. */
11398 operands[0] = not_taken;
11399 output_asm_insn (branch_if_false, operands);
11401 /* If INSN has a delay slot, we must provide delay slots for both the
11402 branch to NOT_TAKEN and the conditional jump. We must also ensure
11403 that INSN's delay slot is executed in the appropriate cases. */
11404 if (final_sequence)
11406 /* This first delay slot will always be executed, so use INSN's
11407 delay slot if is not annulled. */
11408 if (!INSN_ANNULLED_BRANCH_P (insn))
11410 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11411 asm_out_file, optimize, 1, NULL);
11412 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11415 output_asm_insn ("nop", 0);
11416 fprintf (asm_out_file, "\n");
11419 /* Output the unconditional branch to TAKEN. */
11420 if (TARGET_ABSOLUTE_JUMPS)
11421 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11424 mips_output_load_label (taken);
11425 output_asm_insn ("jr\t%@%]%/", 0);
11428 /* Now deal with its delay slot; see above. */
11429 if (final_sequence)
11431 /* This delay slot will only be executed if the branch is taken.
11432 Use INSN's delay slot if is annulled. */
11433 if (INSN_ANNULLED_BRANCH_P (insn))
11435 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11436 asm_out_file, optimize, 1, NULL);
11437 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11440 output_asm_insn ("nop", 0);
11441 fprintf (asm_out_file, "\n");
11444 /* Output NOT_TAKEN. */
11445 targetm.asm_out.internal_label (asm_out_file, "L",
11446 CODE_LABEL_NUMBER (not_taken));
11450 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11451 if some ordering condition is true. The condition is given by
11452 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11453 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11454 its second is always zero. */
11457 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11459 const char *branch[2];
11461 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11462 Make BRANCH[0] branch on the inverse condition. */
11463 switch (GET_CODE (operands[1]))
11465 /* These cases are equivalent to comparisons against zero. */
11467 inverted_p = !inverted_p;
11468 /* Fall through. */
11470 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11471 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11474 /* These cases are always true or always false. */
11476 inverted_p = !inverted_p;
11477 /* Fall through. */
11479 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11480 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11484 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11485 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11488 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11491 /* Start a block of code that needs access to the LL, SC and SYNC
11495 mips_start_ll_sc_sync_block (void)
11497 if (!ISA_HAS_LL_SC)
11499 output_asm_insn (".set\tpush", 0);
11500 output_asm_insn (".set\tmips2", 0);
11504 /* End a block started by mips_start_ll_sc_sync_block. */
11507 mips_end_ll_sc_sync_block (void)
11509 if (!ISA_HAS_LL_SC)
11510 output_asm_insn (".set\tpop", 0);
11513 /* Output and/or return the asm template for a sync instruction. */
11516 mips_output_sync (void)
11518 mips_start_ll_sc_sync_block ();
11519 output_asm_insn ("sync", 0);
11520 mips_end_ll_sc_sync_block ();
11524 /* Return the asm template associated with sync_insn1 value TYPE.
11525 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11527 static const char *
11528 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11532 case SYNC_INSN1_MOVE:
11533 return "move\t%0,%z2";
11534 case SYNC_INSN1_LI:
11535 return "li\t%0,%2";
11536 case SYNC_INSN1_ADDU:
11537 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11538 case SYNC_INSN1_ADDIU:
11539 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11540 case SYNC_INSN1_SUBU:
11541 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11542 case SYNC_INSN1_AND:
11543 return "and\t%0,%1,%z2";
11544 case SYNC_INSN1_ANDI:
11545 return "andi\t%0,%1,%2";
11546 case SYNC_INSN1_OR:
11547 return "or\t%0,%1,%z2";
11548 case SYNC_INSN1_ORI:
11549 return "ori\t%0,%1,%2";
11550 case SYNC_INSN1_XOR:
11551 return "xor\t%0,%1,%z2";
11552 case SYNC_INSN1_XORI:
11553 return "xori\t%0,%1,%2";
11555 gcc_unreachable ();
11558 /* Return the asm template associated with sync_insn2 value TYPE. */
11560 static const char *
11561 mips_sync_insn2_template (enum attr_sync_insn2 type)
11565 case SYNC_INSN2_NOP:
11566 gcc_unreachable ();
11567 case SYNC_INSN2_AND:
11568 return "and\t%0,%1,%z2";
11569 case SYNC_INSN2_XOR:
11570 return "xor\t%0,%1,%z2";
11571 case SYNC_INSN2_NOT:
11572 return "nor\t%0,%1,%.";
11574 gcc_unreachable ();
11577 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11578 the value of the one of the sync_* attributes. Return the operand
11579 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11580 have the associated attribute. */
11583 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11586 default_value = operands[index - 1];
11587 return default_value;
11590 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11591 sequence for it. */
11594 mips_process_sync_loop (rtx insn, rtx *operands)
11596 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11597 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11598 unsigned int tmp3_insn;
11599 enum attr_sync_insn1 insn1;
11600 enum attr_sync_insn2 insn2;
11603 /* Read an operand from the sync_WHAT attribute and store it in
11604 variable WHAT. DEFAULT is the default value if no attribute
11606 #define READ_OPERAND(WHAT, DEFAULT) \
11607 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11610 /* Read the memory. */
11611 READ_OPERAND (mem, 0);
11613 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11615 /* Read the other attributes. */
11616 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11617 READ_OPERAND (oldval, at);
11618 READ_OPERAND (newval, at);
11619 READ_OPERAND (inclusive_mask, 0);
11620 READ_OPERAND (exclusive_mask, 0);
11621 READ_OPERAND (required_oldval, 0);
11622 READ_OPERAND (insn1_op2, 0);
11623 insn1 = get_attr_sync_insn1 (insn);
11624 insn2 = get_attr_sync_insn2 (insn);
11626 mips_multi_start ();
11628 /* Output the release side of the memory barrier. */
11629 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11631 if (required_oldval == 0 && TARGET_OCTEON)
11633 /* Octeon doesn't reorder reads, so a full barrier can be
11634 created by using SYNCW to order writes combined with the
11635 write from the following SC. When the SC successfully
11636 completes, we know that all preceding writes are also
11637 committed to the coherent memory system. It is possible
11638 for a single SYNCW to fail, but a pair of them will never
11639 fail, so we use two. */
11640 mips_multi_add_insn ("syncw", NULL);
11641 mips_multi_add_insn ("syncw", NULL);
11644 mips_multi_add_insn ("sync", NULL);
11647 /* Output the branch-back label. */
11648 mips_multi_add_label ("1:");
11650 /* OLDVAL = *MEM. */
11651 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11652 oldval, mem, NULL);
11654 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11655 if (required_oldval)
11657 if (inclusive_mask == 0)
11661 gcc_assert (oldval != at);
11662 mips_multi_add_insn ("and\t%0,%1,%2",
11663 at, oldval, inclusive_mask, NULL);
11666 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11669 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11670 if (exclusive_mask == 0)
11674 gcc_assert (oldval != at);
11675 mips_multi_add_insn ("and\t%0,%1,%z2",
11676 at, oldval, exclusive_mask, NULL);
11680 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11682 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11683 at least one instruction in that case. */
11684 if (insn1 == SYNC_INSN1_MOVE
11685 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11689 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11690 newval, oldval, insn1_op2, NULL);
11694 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11695 if (insn2 == SYNC_INSN2_NOP)
11699 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11700 newval, tmp2, inclusive_mask, NULL);
11703 tmp3_insn = mips_multi_last_index ();
11705 /* $AT = $TMP1 | $TMP3. */
11706 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11708 mips_multi_set_operand (tmp3_insn, 0, at);
11713 gcc_assert (tmp1 != tmp3);
11714 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11717 /* if (!commit (*MEM = $AT)) goto 1.
11719 This will sometimes be a delayed branch; see the write code below
11721 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11722 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11724 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11725 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11727 mips_multi_copy_insn (tmp3_insn);
11728 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11731 mips_multi_add_insn ("nop", NULL);
11733 /* Output the acquire side of the memory barrier. */
11734 if (TARGET_SYNC_AFTER_SC)
11735 mips_multi_add_insn ("sync", NULL);
11737 /* Output the exit label, if needed. */
11738 if (required_oldval)
11739 mips_multi_add_label ("2:");
11741 #undef READ_OPERAND
11744 /* Output and/or return the asm template for sync loop INSN, which has
11745 the operands given by OPERANDS. */
11748 mips_output_sync_loop (rtx insn, rtx *operands)
11750 mips_process_sync_loop (insn, operands);
11752 /* Use branch-likely instructions to work around the LL/SC R10000
11754 mips_branch_likely = TARGET_FIX_R10000;
11756 mips_push_asm_switch (&mips_noreorder);
11757 mips_push_asm_switch (&mips_nomacro);
11758 mips_push_asm_switch (&mips_noat);
11759 mips_start_ll_sc_sync_block ();
11761 mips_multi_write ();
11763 mips_end_ll_sc_sync_block ();
11764 mips_pop_asm_switch (&mips_noat);
11765 mips_pop_asm_switch (&mips_nomacro);
11766 mips_pop_asm_switch (&mips_noreorder);
11771 /* Return the number of individual instructions in sync loop INSN,
11772 which has the operands given by OPERANDS. */
11775 mips_sync_loop_insns (rtx insn, rtx *operands)
11777 mips_process_sync_loop (insn, operands);
11778 return mips_multi_num_insns;
11781 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11782 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11784 When working around R4000 and R4400 errata, we need to make sure that
11785 the division is not immediately followed by a shift[1][2]. We also
11786 need to stop the division from being put into a branch delay slot[3].
11787 The easiest way to avoid both problems is to add a nop after the
11788 division. When a divide-by-zero check is needed, this nop can be
11789 used to fill the branch delay slot.
11791 [1] If a double-word or a variable shift executes immediately
11792 after starting an integer division, the shift may give an
11793 incorrect result. See quotations of errata #16 and #28 from
11794 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11795 in mips.md for details.
11797 [2] A similar bug to [1] exists for all revisions of the
11798 R4000 and the R4400 when run in an MC configuration.
11799 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11801 "19. In this following sequence:
11803 ddiv (or ddivu or div or divu)
11804 dsll32 (or dsrl32, dsra32)
11806 if an MPT stall occurs, while the divide is slipping the cpu
11807 pipeline, then the following double shift would end up with an
11810 Workaround: The compiler needs to avoid generating any
11811 sequence with divide followed by extended double shift."
11813 This erratum is also present in "MIPS R4400MC Errata, Processor
11814 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11815 & 3.0" as errata #10 and #4, respectively.
11817 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11818 (also valid for MIPS R4000MC processors):
11820 "52. R4000SC: This bug does not apply for the R4000PC.
11822 There are two flavors of this bug:
11824 1) If the instruction just after divide takes an RF exception
11825 (tlb-refill, tlb-invalid) and gets an instruction cache
11826 miss (both primary and secondary) and the line which is
11827 currently in secondary cache at this index had the first
11828 data word, where the bits 5..2 are set, then R4000 would
11829 get a wrong result for the div.
11834 ------------------- # end-of page. -tlb-refill
11839 ------------------- # end-of page. -tlb-invalid
11842 2) If the divide is in the taken branch delay slot, where the
11843 target takes RF exception and gets an I-cache miss for the
11844 exception vector or where I-cache miss occurs for the
11845 target address, under the above mentioned scenarios, the
11846 div would get wrong results.
11849 j r2 # to next page mapped or unmapped
11850 div r8,r9 # this bug would be there as long
11851 # as there is an ICache miss and
11852 nop # the "data pattern" is present
11855 beq r0, r0, NextPage # to Next page
11859 This bug is present for div, divu, ddiv, and ddivu
11862 Workaround: For item 1), OS could make sure that the next page
11863 after the divide instruction is also mapped. For item 2), the
11864 compiler could make sure that the divide instruction is not in
11865 the branch delay slot."
11867 These processors have PRId values of 0x00004220 and 0x00004300 for
11868 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11871 mips_output_division (const char *division, rtx *operands)
11876 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11878 output_asm_insn (s, operands);
11881 if (TARGET_CHECK_ZERO_DIV)
11885 output_asm_insn (s, operands);
11886 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11888 else if (GENERATE_DIVIDE_TRAPS)
11890 /* Avoid long replay penalty on load miss by putting the trap before
11893 output_asm_insn ("teq\t%2,%.,7", operands);
11896 output_asm_insn (s, operands);
11897 s = "teq\t%2,%.,7";
11902 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11903 output_asm_insn (s, operands);
11904 s = "break\t7%)\n1:";
11910 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11911 instruction and if OUT_INSN assigns to the accumulator operand. */
11914 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11918 x = single_set (in_insn);
11924 if (GET_CODE (x) == PLUS
11925 && GET_CODE (XEXP (x, 0)) == MULT
11926 && reg_set_p (XEXP (x, 1), out_insn))
11929 if (GET_CODE (x) == MINUS
11930 && GET_CODE (XEXP (x, 1)) == MULT
11931 && reg_set_p (XEXP (x, 0), out_insn))
11937 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11938 data rather than the address. We need this because the cprestore
11939 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11940 which causes the default routine to abort. We just return false
11944 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11946 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11949 return !store_data_bypass_p (out_insn, in_insn);
11953 /* Variables and flags used in scheduler hooks when tuning for
11957 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11960 /* If true, then next ALU1/2 instruction will go to ALU1. */
11963 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11966 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11967 int alu1_core_unit_code;
11968 int alu2_core_unit_code;
11969 int falu1_core_unit_code;
11970 int falu2_core_unit_code;
11972 /* True if current cycle has a multi instruction.
11973 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11974 bool cycle_has_multi_p;
11976 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11977 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11979 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11980 instruction to go ALU1. */
11981 rtx alu1_turn_enabled_insn;
11982 rtx alu2_turn_enabled_insn;
11983 rtx falu1_turn_enabled_insn;
11984 rtx falu2_turn_enabled_insn;
11987 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11988 dependencies have no cost, except on the 20Kc where output-dependence
11989 is treated like input-dependence. */
11992 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11993 rtx dep ATTRIBUTE_UNUSED, int cost)
11995 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11998 if (REG_NOTE_KIND (link) != 0)
12003 /* Return the number of instructions that can be issued per cycle. */
12006 mips_issue_rate (void)
12010 case PROCESSOR_74KC:
12011 case PROCESSOR_74KF2_1:
12012 case PROCESSOR_74KF1_1:
12013 case PROCESSOR_74KF3_2:
12014 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12015 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12016 but in reality only a maximum of 3 insns can be issued as
12017 floating-point loads and stores also require a slot in the
12019 case PROCESSOR_R10000:
12020 /* All R10K Processors are quad-issue (being the first MIPS
12021 processors to support this feature). */
12024 case PROCESSOR_20KC:
12025 case PROCESSOR_R4130:
12026 case PROCESSOR_R5400:
12027 case PROCESSOR_R5500:
12028 case PROCESSOR_R7000:
12029 case PROCESSOR_R9000:
12030 case PROCESSOR_OCTEON:
12033 case PROCESSOR_SB1:
12034 case PROCESSOR_SB1A:
12035 /* This is actually 4, but we get better performance if we claim 3.
12036 This is partly because of unwanted speculative code motion with the
12037 larger number, and partly because in most common cases we can't
12038 reach the theoretical max of 4. */
12041 case PROCESSOR_LOONGSON_2E:
12042 case PROCESSOR_LOONGSON_2F:
12043 case PROCESSOR_LOONGSON_3A:
12051 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12054 mips_ls2_init_dfa_post_cycle_insn (void)
12057 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12058 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12062 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12063 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12067 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12068 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12072 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12073 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12076 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12077 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12078 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12079 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12082 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12083 Init data used in mips_dfa_post_advance_cycle. */
12086 mips_init_dfa_post_cycle_insn (void)
12088 if (TUNE_LOONGSON_2EF)
12089 mips_ls2_init_dfa_post_cycle_insn ();
12092 /* Initialize STATE when scheduling for Loongson 2E/2F.
12093 Support round-robin dispatch scheme by enabling only one of
12094 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12098 mips_ls2_dfa_post_advance_cycle (state_t state)
12100 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12102 /* Though there are no non-pipelined ALU1 insns,
12103 we can get an instruction of type 'multi' before reload. */
12104 gcc_assert (mips_ls2.cycle_has_multi_p);
12105 mips_ls2.alu1_turn_p = false;
12108 mips_ls2.cycle_has_multi_p = false;
12110 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12111 /* We have a non-pipelined alu instruction in the core,
12112 adjust round-robin counter. */
12113 mips_ls2.alu1_turn_p = true;
12115 if (mips_ls2.alu1_turn_p)
12117 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12118 gcc_unreachable ();
12122 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12123 gcc_unreachable ();
12126 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12128 /* There are no non-pipelined FALU1 insns. */
12129 gcc_unreachable ();
12130 mips_ls2.falu1_turn_p = false;
12133 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12134 /* We have a non-pipelined falu instruction in the core,
12135 adjust round-robin counter. */
12136 mips_ls2.falu1_turn_p = true;
12138 if (mips_ls2.falu1_turn_p)
12140 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12141 gcc_unreachable ();
12145 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12146 gcc_unreachable ();
12150 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12151 This hook is being called at the start of each cycle. */
12154 mips_dfa_post_advance_cycle (void)
12156 if (TUNE_LOONGSON_2EF)
12157 mips_ls2_dfa_post_advance_cycle (curr_state);
12160 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12161 be as wide as the scheduling freedom in the DFA. */
12164 mips_multipass_dfa_lookahead (void)
12166 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12170 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12179 /* Remove the instruction at index LOWER from ready queue READY and
12180 reinsert it in front of the instruction at index HIGHER. LOWER must
12184 mips_promote_ready (rtx *ready, int lower, int higher)
12189 new_head = ready[lower];
12190 for (i = lower; i < higher; i++)
12191 ready[i] = ready[i + 1];
12192 ready[i] = new_head;
12195 /* If the priority of the instruction at POS2 in the ready queue READY
12196 is within LIMIT units of that of the instruction at POS1, swap the
12197 instructions if POS2 is not already less than POS1. */
12200 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12203 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12207 temp = ready[pos1];
12208 ready[pos1] = ready[pos2];
12209 ready[pos2] = temp;
12213 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12214 that may clobber hi or lo. */
12215 static rtx mips_macc_chains_last_hilo;
12217 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12218 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12221 mips_macc_chains_record (rtx insn)
12223 if (get_attr_may_clobber_hilo (insn))
12224 mips_macc_chains_last_hilo = insn;
12227 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12228 has NREADY elements, looking for a multiply-add or multiply-subtract
12229 instruction that is cumulative with mips_macc_chains_last_hilo.
12230 If there is one, promote it ahead of anything else that might
12231 clobber hi or lo. */
12234 mips_macc_chains_reorder (rtx *ready, int nready)
12238 if (mips_macc_chains_last_hilo != 0)
12239 for (i = nready - 1; i >= 0; i--)
12240 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12242 for (j = nready - 1; j > i; j--)
12243 if (recog_memoized (ready[j]) >= 0
12244 && get_attr_may_clobber_hilo (ready[j]))
12246 mips_promote_ready (ready, i, j);
12253 /* The last instruction to be scheduled. */
12254 static rtx vr4130_last_insn;
12256 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12257 points to an rtx that is initially an instruction. Nullify the rtx
12258 if the instruction uses the value of register X. */
12261 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12266 insn_ptr = (rtx *) data;
12269 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12273 /* Return true if there is true register dependence between vr4130_last_insn
12277 vr4130_true_reg_dependence_p (rtx insn)
12279 note_stores (PATTERN (vr4130_last_insn),
12280 vr4130_true_reg_dependence_p_1, &insn);
12284 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12285 the ready queue and that INSN2 is the instruction after it, return
12286 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12287 in which INSN1 and INSN2 can probably issue in parallel, but for
12288 which (INSN2, INSN1) should be less sensitive to instruction
12289 alignment than (INSN1, INSN2). See 4130.md for more details. */
12292 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12294 sd_iterator_def sd_it;
12297 /* Check for the following case:
12299 1) there is some other instruction X with an anti dependence on INSN1;
12300 2) X has a higher priority than INSN2; and
12301 3) X is an arithmetic instruction (and thus has no unit restrictions).
12303 If INSN1 is the last instruction blocking X, it would better to
12304 choose (INSN1, X) over (INSN2, INSN1). */
12305 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12306 if (DEP_TYPE (dep) == REG_DEP_ANTI
12307 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12308 && recog_memoized (DEP_CON (dep)) >= 0
12309 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12312 if (vr4130_last_insn != 0
12313 && recog_memoized (insn1) >= 0
12314 && recog_memoized (insn2) >= 0)
12316 /* See whether INSN1 and INSN2 use different execution units,
12317 or if they are both ALU-type instructions. If so, they can
12318 probably execute in parallel. */
12319 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12320 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12321 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12323 /* If only one of the instructions has a dependence on
12324 vr4130_last_insn, prefer to schedule the other one first. */
12325 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12326 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12327 if (dep1_p != dep2_p)
12330 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12331 is not an ALU-type instruction and if INSN1 uses the same
12332 execution unit. (Note that if this condition holds, we already
12333 know that INSN2 uses a different execution unit.) */
12334 if (class1 != VR4130_CLASS_ALU
12335 && recog_memoized (vr4130_last_insn) >= 0
12336 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12343 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12344 queue with at least two instructions. Swap the first two if
12345 vr4130_swap_insns_p says that it could be worthwhile. */
12348 vr4130_reorder (rtx *ready, int nready)
12350 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12351 mips_promote_ready (ready, nready - 2, nready - 1);
12354 /* Record whether last 74k AGEN instruction was a load or store. */
12355 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12357 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12358 resets to TYPE_UNKNOWN state. */
12361 mips_74k_agen_init (rtx insn)
12363 if (!insn || CALL_P (insn) || JUMP_P (insn))
12364 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12367 enum attr_type type = get_attr_type (insn);
12368 if (type == TYPE_LOAD || type == TYPE_STORE)
12369 mips_last_74k_agen_insn = type;
12373 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12374 loads to be grouped together, and multiple stores to be grouped
12375 together. Swap things around in the ready queue to make this happen. */
12378 mips_74k_agen_reorder (rtx *ready, int nready)
12381 int store_pos, load_pos;
12386 for (i = nready - 1; i >= 0; i--)
12388 rtx insn = ready[i];
12389 if (USEFUL_INSN_P (insn))
12390 switch (get_attr_type (insn))
12393 if (store_pos == -1)
12398 if (load_pos == -1)
12407 if (load_pos == -1 || store_pos == -1)
12410 switch (mips_last_74k_agen_insn)
12413 /* Prefer to schedule loads since they have a higher latency. */
12415 /* Swap loads to the front of the queue. */
12416 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12419 /* Swap stores to the front of the queue. */
12420 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12427 /* Implement TARGET_SCHED_INIT. */
12430 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12431 int max_ready ATTRIBUTE_UNUSED)
12433 mips_macc_chains_last_hilo = 0;
12434 vr4130_last_insn = 0;
12435 mips_74k_agen_init (NULL_RTX);
12437 /* When scheduling for Loongson2, branch instructions go to ALU1,
12438 therefore basic block is most likely to start with round-robin counter
12439 pointed to ALU2. */
12440 mips_ls2.alu1_turn_p = false;
12441 mips_ls2.falu1_turn_p = true;
12444 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12447 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12448 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12450 if (!reload_completed
12451 && TUNE_MACC_CHAINS
12453 mips_macc_chains_reorder (ready, *nreadyp);
12455 if (reload_completed
12457 && !TARGET_VR4130_ALIGN
12459 vr4130_reorder (ready, *nreadyp);
12462 mips_74k_agen_reorder (ready, *nreadyp);
12465 /* Implement TARGET_SCHED_REORDER. */
12468 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12469 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12471 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12472 return mips_issue_rate ();
12475 /* Implement TARGET_SCHED_REORDER2. */
12478 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12479 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12481 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12482 return cached_can_issue_more;
12485 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12488 mips_ls2_variable_issue (rtx insn)
12490 if (mips_ls2.alu1_turn_p)
12492 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12493 mips_ls2.alu1_turn_p = false;
12497 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12498 mips_ls2.alu1_turn_p = true;
12501 if (mips_ls2.falu1_turn_p)
12503 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12504 mips_ls2.falu1_turn_p = false;
12508 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12509 mips_ls2.falu1_turn_p = true;
12512 if (recog_memoized (insn) >= 0)
12513 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12516 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12519 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12520 rtx insn, int more)
12522 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12523 if (USEFUL_INSN_P (insn))
12525 if (get_attr_type (insn) != TYPE_GHOST)
12527 if (!reload_completed && TUNE_MACC_CHAINS)
12528 mips_macc_chains_record (insn);
12529 vr4130_last_insn = insn;
12531 mips_74k_agen_init (insn);
12532 else if (TUNE_LOONGSON_2EF)
12533 mips_ls2_variable_issue (insn);
12536 /* Instructions of type 'multi' should all be split before
12537 the second scheduling pass. */
12538 gcc_assert (!reload_completed
12539 || recog_memoized (insn) < 0
12540 || get_attr_type (insn) != TYPE_MULTI);
12542 cached_can_issue_more = more;
12546 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12547 return the first operand of the associated PREF or PREFX insn. */
12550 mips_prefetch_cookie (rtx write, rtx locality)
12552 /* store_streamed / load_streamed. */
12553 if (INTVAL (locality) <= 0)
12554 return GEN_INT (INTVAL (write) + 4);
12556 /* store / load. */
12557 if (INTVAL (locality) <= 2)
12560 /* store_retained / load_retained. */
12561 return GEN_INT (INTVAL (write) + 6);
12564 /* Flags that indicate when a built-in function is available.
12566 BUILTIN_AVAIL_NON_MIPS16
12567 The function is available on the current target, but only
12568 in non-MIPS16 mode. */
12569 #define BUILTIN_AVAIL_NON_MIPS16 1
12571 /* Declare an availability predicate for built-in functions that
12572 require non-MIPS16 mode and also require COND to be true.
12573 NAME is the main part of the predicate's name. */
12574 #define AVAIL_NON_MIPS16(NAME, COND) \
12575 static unsigned int \
12576 mips_builtin_avail_##NAME (void) \
12578 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12581 /* This structure describes a single built-in function. */
12582 struct mips_builtin_description {
12583 /* The code of the main .md file instruction. See mips_builtin_type
12584 for more information. */
12585 enum insn_code icode;
12587 /* The floating-point comparison code to use with ICODE, if any. */
12588 enum mips_fp_condition cond;
12590 /* The name of the built-in function. */
12593 /* Specifies how the function should be expanded. */
12594 enum mips_builtin_type builtin_type;
12596 /* The function's prototype. */
12597 enum mips_function_type function_type;
12599 /* Whether the function is available. */
12600 unsigned int (*avail) (void);
12603 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12604 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12605 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12606 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12607 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12608 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12609 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12610 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12611 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12613 /* Construct a mips_builtin_description from the given arguments.
12615 INSN is the name of the associated instruction pattern, without the
12616 leading CODE_FOR_mips_.
12618 CODE is the floating-point condition code associated with the
12619 function. It can be 'f' if the field is not applicable.
12621 NAME is the name of the function itself, without the leading
12624 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12626 AVAIL is the name of the availability predicate, without the leading
12627 mips_builtin_avail_. */
12628 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12629 FUNCTION_TYPE, AVAIL) \
12630 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12631 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12632 mips_builtin_avail_ ## AVAIL }
12634 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12635 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12636 are as for MIPS_BUILTIN. */
12637 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12638 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12640 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12641 are subject to mips_builtin_avail_<AVAIL>. */
12642 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12643 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12644 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12645 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12646 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12648 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12649 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12650 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12651 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12652 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12653 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12655 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12656 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12658 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12659 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12661 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12662 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12665 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12666 are subject to mips_builtin_avail_mips3d. */
12667 #define CMP_4S_BUILTINS(INSN, COND) \
12668 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12669 MIPS_BUILTIN_CMP_ANY, \
12670 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12671 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12672 MIPS_BUILTIN_CMP_ALL, \
12673 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12675 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12676 instruction requires mips_builtin_avail_<AVAIL>. */
12677 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12678 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12679 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12681 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12682 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12685 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12686 #define CMP_BUILTINS(COND) \
12687 MOVTF_BUILTINS (c, COND, paired_single), \
12688 MOVTF_BUILTINS (cabs, COND, mips3d), \
12689 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12690 CMP_PS_BUILTINS (c, COND, paired_single), \
12691 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12692 CMP_4S_BUILTINS (c, COND), \
12693 CMP_4S_BUILTINS (cabs, COND)
12695 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12696 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12697 and AVAIL are as for MIPS_BUILTIN. */
12698 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12699 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12700 FUNCTION_TYPE, AVAIL)
12702 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12703 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12704 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12705 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12706 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12708 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12709 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12710 builtin_description field. */
12711 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12712 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12713 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12714 FUNCTION_TYPE, mips_builtin_avail_loongson }
12716 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12717 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12718 builtin_description field. */
12719 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12720 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12722 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12723 We use functions of this form when the same insn can be usefully applied
12724 to more than one datatype. */
12725 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12726 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12728 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12729 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12730 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12731 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12732 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12733 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12734 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
12735 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
12737 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12738 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12739 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12740 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12741 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12742 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12743 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12744 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12745 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12746 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12747 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12748 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12749 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12750 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12751 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12752 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12753 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12754 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
12755 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
12756 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
12757 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
12758 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
12759 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
12760 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12761 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12762 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12763 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12764 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12765 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12766 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12767 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12768 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12769 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12770 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12771 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12772 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12774 static const struct mips_builtin_description mips_builtins[] = {
12775 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12776 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12777 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12778 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12779 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12780 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12781 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12782 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12784 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12785 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12786 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12787 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12788 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12790 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12791 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12792 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12793 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12794 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12795 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12797 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12798 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12799 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12800 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12801 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12802 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12804 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12806 /* Built-in functions for the SB-1 processor. */
12807 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12809 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12810 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12811 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12812 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12813 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12814 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12815 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12816 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12817 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12818 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12819 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12820 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12821 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12822 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12823 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12824 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12825 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12826 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12827 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12828 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12829 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12830 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12831 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12832 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12833 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12834 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12835 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12836 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12837 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12838 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12839 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12840 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12841 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12842 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12843 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12844 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12845 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12846 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12847 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12848 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12849 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12850 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12851 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12852 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12853 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12854 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12855 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12856 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12857 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12858 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12859 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12860 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12861 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12862 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12863 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12864 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12865 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12866 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12867 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12868 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12869 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12870 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12871 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12872 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12873 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12874 BPOSGE_BUILTIN (32, dsp),
12876 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12877 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12878 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12879 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12880 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12881 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12882 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12883 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12884 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12885 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12886 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12887 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12888 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12889 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12890 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12891 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12892 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12893 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12894 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12895 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12896 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12897 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12898 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12899 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12900 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12901 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12902 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12903 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12904 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12905 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12906 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12907 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12908 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12909 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12910 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12912 /* Built-in functions for the DSP ASE (32-bit only). */
12913 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12914 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12915 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12916 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12917 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12918 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12919 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12920 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12921 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12922 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12923 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12924 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12925 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12926 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12927 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12928 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12929 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12930 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12931 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12932 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12933 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12934 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12935 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12936 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12937 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12938 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
12939 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
12941 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12942 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12943 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12944 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12945 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12946 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12947 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12948 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12949 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12950 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12952 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12953 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12954 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12955 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12956 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12957 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12958 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12959 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12960 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12961 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12962 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12963 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12964 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12965 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12966 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12967 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12968 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12969 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12970 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12971 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12972 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12973 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12974 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12975 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12976 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12977 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12978 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12979 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12980 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12981 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12982 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12983 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12984 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12985 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12986 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12987 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12988 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12989 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12990 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12991 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12992 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12993 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12994 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12995 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12996 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12997 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12998 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12999 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13000 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13001 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13002 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13003 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13004 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13005 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13006 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13007 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13008 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13009 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13010 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13011 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13012 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13013 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13014 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
13015 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
13016 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13017 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13018 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13019 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13020 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13021 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13022 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13023 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13024 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13025 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13026 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13027 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13028 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13029 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13030 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13031 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13032 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13033 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13034 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13035 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13036 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13037 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13038 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13039 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13040 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13041 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13042 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13043 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13044 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13045 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13046 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13047 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13048 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13049 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13050 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13051 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13053 /* Sundry other built-in functions. */
13054 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13057 /* Index I is the function declaration for mips_builtins[I], or null if the
13058 function isn't defined on this target. */
13059 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13061 /* MODE is a vector mode whose elements have type TYPE. Return the type
13062 of the vector itself. */
13065 mips_builtin_vector_type (tree type, enum machine_mode mode)
13067 static tree types[2 * (int) MAX_MACHINE_MODE];
13070 mode_index = (int) mode;
13072 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13073 mode_index += MAX_MACHINE_MODE;
13075 if (types[mode_index] == NULL_TREE)
13076 types[mode_index] = build_vector_type_for_mode (type, mode);
13077 return types[mode_index];
13080 /* Return a type for 'const volatile void *'. */
13083 mips_build_cvpointer_type (void)
13087 if (cache == NULL_TREE)
13088 cache = build_pointer_type (build_qualified_type
13090 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13094 /* Source-level argument types. */
13095 #define MIPS_ATYPE_VOID void_type_node
13096 #define MIPS_ATYPE_INT integer_type_node
13097 #define MIPS_ATYPE_POINTER ptr_type_node
13098 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13100 /* Standard mode-based argument types. */
13101 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13102 #define MIPS_ATYPE_SI intSI_type_node
13103 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13104 #define MIPS_ATYPE_DI intDI_type_node
13105 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13106 #define MIPS_ATYPE_SF float_type_node
13107 #define MIPS_ATYPE_DF double_type_node
13109 /* Vector argument types. */
13110 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13111 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13112 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13113 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13114 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13115 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13116 #define MIPS_ATYPE_UV2SI \
13117 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13118 #define MIPS_ATYPE_UV4HI \
13119 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13120 #define MIPS_ATYPE_UV8QI \
13121 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13123 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13124 their associated MIPS_ATYPEs. */
13125 #define MIPS_FTYPE_ATYPES1(A, B) \
13126 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13128 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13129 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13131 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13132 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13134 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13135 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13138 /* Return the function type associated with function prototype TYPE. */
13141 mips_build_function_type (enum mips_function_type type)
13143 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13145 if (types[(int) type] == NULL_TREE)
13148 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13149 case MIPS_FTYPE_NAME##NUM ARGS: \
13150 types[(int) type] \
13151 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13154 #include "config/mips/mips-ftypes.def"
13155 #undef DEF_MIPS_FTYPE
13157 gcc_unreachable ();
13160 return types[(int) type];
13163 /* Implement TARGET_INIT_BUILTINS. */
13166 mips_init_builtins (void)
13168 const struct mips_builtin_description *d;
13171 /* Iterate through all of the bdesc arrays, initializing all of the
13172 builtin functions. */
13173 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13175 d = &mips_builtins[i];
13177 mips_builtin_decls[i]
13178 = add_builtin_function (d->name,
13179 mips_build_function_type (d->function_type),
13180 i, BUILT_IN_MD, NULL, NULL);
13184 /* Implement TARGET_BUILTIN_DECL. */
13187 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13189 if (code >= ARRAY_SIZE (mips_builtins))
13190 return error_mark_node;
13191 return mips_builtin_decls[code];
13194 /* Take argument ARGNO from EXP's argument list and convert it into
13195 an expand operand. Store the operand in *OP. */
13198 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13199 unsigned int argno)
13204 arg = CALL_EXPR_ARG (exp, argno);
13205 value = expand_normal (arg);
13206 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13209 /* Expand instruction ICODE as part of a built-in function sequence.
13210 Use the first NOPS elements of OPS as the instruction's operands.
13211 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13212 instruction has no target.
13214 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13217 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13218 struct expand_operand *ops, bool has_target_p)
13220 if (!maybe_expand_insn (icode, nops, ops))
13222 error ("invalid argument to built-in function");
13223 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13225 return has_target_p ? ops[0].value : const0_rtx;
13228 /* Expand a floating-point comparison for built-in function call EXP.
13229 The first NARGS arguments are the values to be compared. ICODE is
13230 the .md pattern that does the comparison and COND is the condition
13231 that is being tested. Return an rtx for the result. */
13234 mips_expand_builtin_compare_1 (enum insn_code icode,
13235 enum mips_fp_condition cond,
13236 tree exp, int nargs)
13238 struct expand_operand ops[MAX_RECOG_OPERANDS];
13241 /* The instruction should have a target operand, an operand for each
13242 argument, and an operand for COND. */
13243 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13246 create_output_operand (&ops[opno++], NULL_RTX,
13247 insn_data[(int) icode].operand[0].mode);
13248 for (argno = 0; argno < nargs; argno++)
13249 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13250 create_integer_operand (&ops[opno++], (int) cond);
13251 return mips_expand_builtin_insn (icode, opno, ops, true);
13254 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13255 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13256 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13257 suggests a good place to put the result. */
13260 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13263 struct expand_operand ops[MAX_RECOG_OPERANDS];
13266 /* Map any target to operand 0. */
13269 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13271 /* Map the arguments to the other operands. */
13272 gcc_assert (opno + call_expr_nargs (exp)
13273 == insn_data[icode].n_generator_args);
13274 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13275 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13277 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13280 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13281 function; TYPE says which. EXP is the CALL_EXPR that calls the
13282 function, ICODE is the instruction that should be used to compare
13283 the first two arguments, and COND is the condition it should test.
13284 TARGET, if nonnull, suggests a good place to put the result. */
13287 mips_expand_builtin_movtf (enum mips_builtin_type type,
13288 enum insn_code icode, enum mips_fp_condition cond,
13289 rtx target, tree exp)
13291 struct expand_operand ops[4];
13294 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13295 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13296 if (type == MIPS_BUILTIN_MOVT)
13298 mips_prepare_builtin_arg (&ops[2], exp, 2);
13299 mips_prepare_builtin_arg (&ops[1], exp, 3);
13303 mips_prepare_builtin_arg (&ops[1], exp, 2);
13304 mips_prepare_builtin_arg (&ops[2], exp, 3);
13306 create_fixed_operand (&ops[3], cmp_result);
13307 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13311 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13312 into TARGET otherwise. Return TARGET. */
13315 mips_builtin_branch_and_move (rtx condition, rtx target,
13316 rtx value_if_true, rtx value_if_false)
13318 rtx true_label, done_label;
13320 true_label = gen_label_rtx ();
13321 done_label = gen_label_rtx ();
13323 /* First assume that CONDITION is false. */
13324 mips_emit_move (target, value_if_false);
13326 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13327 emit_jump_insn (gen_condjump (condition, true_label));
13328 emit_jump_insn (gen_jump (done_label));
13331 /* Fix TARGET if CONDITION is true. */
13332 emit_label (true_label);
13333 mips_emit_move (target, value_if_true);
13335 emit_label (done_label);
13339 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13340 the CALL_EXPR that calls the function, ICODE is the code of the
13341 comparison instruction, and COND is the condition it should test.
13342 TARGET, if nonnull, suggests a good place to put the boolean result. */
13345 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13346 enum insn_code icode, enum mips_fp_condition cond,
13347 rtx target, tree exp)
13349 rtx offset, condition, cmp_result;
13351 if (target == 0 || GET_MODE (target) != SImode)
13352 target = gen_reg_rtx (SImode);
13353 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
13354 call_expr_nargs (exp));
13356 /* If the comparison sets more than one register, we define the result
13357 to be 0 if all registers are false and -1 if all registers are true.
13358 The value of the complete result is indeterminate otherwise. */
13359 switch (builtin_type)
13361 case MIPS_BUILTIN_CMP_ALL:
13362 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13363 return mips_builtin_branch_and_move (condition, target,
13364 const0_rtx, const1_rtx);
13366 case MIPS_BUILTIN_CMP_UPPER:
13367 case MIPS_BUILTIN_CMP_LOWER:
13368 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13369 condition = gen_single_cc (cmp_result, offset);
13370 return mips_builtin_branch_and_move (condition, target,
13371 const1_rtx, const0_rtx);
13374 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13375 return mips_builtin_branch_and_move (condition, target,
13376 const1_rtx, const0_rtx);
13380 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13381 if nonnull, suggests a good place to put the boolean result. */
13384 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13386 rtx condition, cmp_result;
13389 if (target == 0 || GET_MODE (target) != SImode)
13390 target = gen_reg_rtx (SImode);
13392 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13394 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13399 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13400 return mips_builtin_branch_and_move (condition, target,
13401 const1_rtx, const0_rtx);
13404 /* Implement TARGET_EXPAND_BUILTIN. */
13407 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13408 enum machine_mode mode, int ignore)
13411 unsigned int fcode, avail;
13412 const struct mips_builtin_description *d;
13414 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13415 fcode = DECL_FUNCTION_CODE (fndecl);
13416 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13417 d = &mips_builtins[fcode];
13418 avail = d->avail ();
13419 gcc_assert (avail != 0);
13422 error ("built-in function %qE not supported for MIPS16",
13423 DECL_NAME (fndecl));
13424 return ignore ? const0_rtx : CONST0_RTX (mode);
13426 switch (d->builtin_type)
13428 case MIPS_BUILTIN_DIRECT:
13429 return mips_expand_builtin_direct (d->icode, target, exp, true);
13431 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13432 return mips_expand_builtin_direct (d->icode, target, exp, false);
13434 case MIPS_BUILTIN_MOVT:
13435 case MIPS_BUILTIN_MOVF:
13436 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13437 d->cond, target, exp);
13439 case MIPS_BUILTIN_CMP_ANY:
13440 case MIPS_BUILTIN_CMP_ALL:
13441 case MIPS_BUILTIN_CMP_UPPER:
13442 case MIPS_BUILTIN_CMP_LOWER:
13443 case MIPS_BUILTIN_CMP_SINGLE:
13444 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13445 d->cond, target, exp);
13447 case MIPS_BUILTIN_BPOSGE32:
13448 return mips_expand_builtin_bposge (d->builtin_type, target);
13450 gcc_unreachable ();
13453 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13454 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13455 struct mips16_constant {
13456 struct mips16_constant *next;
13459 enum machine_mode mode;
13462 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13463 first constant, HIGHEST_ADDRESS is the highest address that the first
13464 byte of the pool can have, and INSN_ADDRESS is the current instruction
13466 struct mips16_constant_pool {
13467 struct mips16_constant *first;
13468 int highest_address;
13472 /* Add constant VALUE to POOL and return its label. MODE is the
13473 value's mode (used for CONST_INTs, etc.). */
13476 mips16_add_constant (struct mips16_constant_pool *pool,
13477 rtx value, enum machine_mode mode)
13479 struct mips16_constant **p, *c;
13480 bool first_of_size_p;
13482 /* See whether the constant is already in the pool. If so, return the
13483 existing label, otherwise leave P pointing to the place where the
13484 constant should be added.
13486 Keep the pool sorted in increasing order of mode size so that we can
13487 reduce the number of alignments needed. */
13488 first_of_size_p = true;
13489 for (p = &pool->first; *p != 0; p = &(*p)->next)
13491 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13492 return (*p)->label;
13493 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13495 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13496 first_of_size_p = false;
13499 /* In the worst case, the constant needed by the earliest instruction
13500 will end up at the end of the pool. The entire pool must then be
13501 accessible from that instruction.
13503 When adding the first constant, set the pool's highest address to
13504 the address of the first out-of-range byte. Adjust this address
13505 downwards each time a new constant is added. */
13506 if (pool->first == 0)
13507 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13508 of the instruction with the lowest two bits clear. The base PC
13509 value for LDPC has the lowest three bits clear. Assume the worst
13510 case here; namely that the PC-relative instruction occupies the
13511 last 2 bytes in an aligned word. */
13512 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13513 pool->highest_address -= GET_MODE_SIZE (mode);
13514 if (first_of_size_p)
13515 /* Take into account the worst possible padding due to alignment. */
13516 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13518 /* Create a new entry. */
13519 c = XNEW (struct mips16_constant);
13522 c->label = gen_label_rtx ();
13529 /* Output constant VALUE after instruction INSN and return the last
13530 instruction emitted. MODE is the mode of the constant. */
13533 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13535 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13537 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13538 return emit_insn_after (gen_consttable_int (value, size), insn);
13541 if (SCALAR_FLOAT_MODE_P (mode))
13542 return emit_insn_after (gen_consttable_float (value), insn);
13544 if (VECTOR_MODE_P (mode))
13548 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13549 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13550 CONST_VECTOR_ELT (value, i), insn);
13554 gcc_unreachable ();
13557 /* Dump out the constants in CONSTANTS after INSN. */
13560 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13562 struct mips16_constant *c, *next;
13566 for (c = constants; c != NULL; c = next)
13568 /* If necessary, increase the alignment of PC. */
13569 if (align < GET_MODE_SIZE (c->mode))
13571 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13572 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13574 align = GET_MODE_SIZE (c->mode);
13576 insn = emit_label_after (c->label, insn);
13577 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13583 emit_barrier_after (insn);
13586 /* Return the length of instruction INSN. */
13589 mips16_insn_length (rtx insn)
13593 rtx body = PATTERN (insn);
13594 if (GET_CODE (body) == ADDR_VEC)
13595 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13596 if (GET_CODE (body) == ADDR_DIFF_VEC)
13597 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13599 return get_attr_length (insn);
13602 /* If *X is a symbolic constant that refers to the constant pool, add
13603 the constant to POOL and rewrite *X to use the constant's label. */
13606 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13608 rtx base, offset, label;
13610 split_const (*x, &base, &offset);
13611 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13613 label = mips16_add_constant (pool, get_pool_constant (base),
13614 get_pool_mode (base));
13615 base = gen_rtx_LABEL_REF (Pmode, label);
13616 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13620 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13621 INSN is the instruction we're rewriting and POOL points to the current
13623 struct mips16_rewrite_pool_refs_info {
13625 struct mips16_constant_pool *pool;
13628 /* Rewrite *X so that constant pool references refer to the constant's
13629 label instead. DATA points to a mips16_rewrite_pool_refs_info
13633 mips16_rewrite_pool_refs (rtx *x, void *data)
13635 struct mips16_rewrite_pool_refs_info *info =
13636 (struct mips16_rewrite_pool_refs_info *) data;
13638 if (force_to_mem_operand (*x, Pmode))
13640 rtx mem = force_const_mem (GET_MODE (*x), *x);
13641 validate_change (info->insn, x, mem, false);
13646 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13650 if (TARGET_MIPS16_TEXT_LOADS)
13651 mips16_rewrite_pool_constant (info->pool, x);
13653 return GET_CODE (*x) == CONST ? -1 : 0;
13656 /* Return whether CFG is used in mips_reorg. */
13659 mips_cfg_in_reorg (void)
13661 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13662 || TARGET_RELAX_PIC_CALLS);
13665 /* Build MIPS16 constant pools. */
13668 mips16_lay_out_constants (void)
13670 struct mips16_constant_pool pool;
13671 struct mips16_rewrite_pool_refs_info info;
13674 if (!TARGET_MIPS16_PCREL_LOADS)
13677 if (mips_cfg_in_reorg ())
13678 split_all_insns ();
13680 split_all_insns_noflow ();
13682 memset (&pool, 0, sizeof (pool));
13683 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13685 /* Rewrite constant pool references in INSN. */
13686 if (USEFUL_INSN_P (insn))
13690 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13693 pool.insn_address += mips16_insn_length (insn);
13695 if (pool.first != NULL)
13697 /* If there are no natural barriers between the first user of
13698 the pool and the highest acceptable address, we'll need to
13699 create a new instruction to jump around the constant pool.
13700 In the worst case, this instruction will be 4 bytes long.
13702 If it's too late to do this transformation after INSN,
13703 do it immediately before INSN. */
13704 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13708 label = gen_label_rtx ();
13710 jump = emit_jump_insn_before (gen_jump (label), insn);
13711 JUMP_LABEL (jump) = label;
13712 LABEL_NUSES (label) = 1;
13713 barrier = emit_barrier_after (jump);
13715 emit_label_after (label, barrier);
13716 pool.insn_address += 4;
13719 /* See whether the constant pool is now out of range of the first
13720 user. If so, output the constants after the previous barrier.
13721 Note that any instructions between BARRIER and INSN (inclusive)
13722 will use negative offsets to refer to the pool. */
13723 if (pool.insn_address > pool.highest_address)
13725 mips16_emit_constants (pool.first, barrier);
13729 else if (BARRIER_P (insn))
13733 mips16_emit_constants (pool.first, get_last_insn ());
13736 /* Return true if it is worth r10k_simplify_address's while replacing
13737 an address with X. We are looking for constants, and for addresses
13738 at a known offset from the incoming stack pointer. */
13741 r10k_simplified_address_p (rtx x)
13743 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13745 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13748 /* X is an expression that appears in INSN. Try to use the UD chains
13749 to simplify it, returning the simplified form on success and the
13750 original form otherwise. Replace the incoming value of $sp with
13751 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13754 r10k_simplify_address (rtx x, rtx insn)
13756 rtx newx, op0, op1, set, def_insn, note;
13758 struct df_link *defs;
13763 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13764 if (op0 != XEXP (x, 0))
13765 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13766 op0, GET_MODE (XEXP (x, 0)));
13768 else if (BINARY_P (x))
13770 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13771 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13772 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13773 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13775 else if (GET_CODE (x) == LO_SUM)
13777 /* LO_SUMs can be offset from HIGHs, if we know they won't
13778 overflow. See mips_classify_address for the rationale behind
13780 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13781 if (GET_CODE (op0) == HIGH)
13782 newx = XEXP (x, 1);
13784 else if (REG_P (x))
13786 /* Uses are recorded by regno_reg_rtx, not X itself. */
13787 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13789 defs = DF_REF_CHAIN (use);
13791 /* Require a single definition. */
13792 if (defs && defs->next == NULL)
13795 if (DF_REF_IS_ARTIFICIAL (def))
13797 /* Replace the incoming value of $sp with
13798 virtual_incoming_args_rtx. */
13799 if (x == stack_pointer_rtx
13800 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13801 newx = virtual_incoming_args_rtx;
13803 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13806 /* Make sure that DEF_INSN is a single set of REG. */
13807 def_insn = DF_REF_INSN (def);
13808 if (NONJUMP_INSN_P (def_insn))
13810 set = single_set (def_insn);
13811 if (set && rtx_equal_p (SET_DEST (set), x))
13813 /* Prefer to use notes, since the def-use chains
13814 are often shorter. */
13815 note = find_reg_equal_equiv_note (def_insn);
13817 newx = XEXP (note, 0);
13819 newx = SET_SRC (set);
13820 newx = r10k_simplify_address (newx, def_insn);
13826 if (newx && r10k_simplified_address_p (newx))
13831 /* Return true if ADDRESS is known to be an uncached address
13832 on R10K systems. */
13835 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13837 unsigned HOST_WIDE_INT upper;
13839 /* Check for KSEG1. */
13840 if (address + 0x60000000 < 0x20000000)
13843 /* Check for uncached XKPHYS addresses. */
13844 if (Pmode == DImode)
13846 upper = (address >> 40) & 0xf9ffff;
13847 if (upper == 0x900000 || upper == 0xb80000)
13853 /* Return true if we can prove that an access to address X in instruction
13854 INSN would be safe from R10K speculation. This X is a general
13855 expression; it might not be a legitimate address. */
13858 r10k_safe_address_p (rtx x, rtx insn)
13861 HOST_WIDE_INT offset_val;
13863 x = r10k_simplify_address (x, insn);
13865 /* Check for references to the stack frame. It doesn't really matter
13866 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13867 allows us to assume that accesses to any part of the eventual frame
13868 is safe from speculation at any point in the function. */
13869 mips_split_plus (x, &base, &offset_val);
13870 if (base == virtual_incoming_args_rtx
13871 && offset_val >= -cfun->machine->frame.total_size
13872 && offset_val < cfun->machine->frame.args_size)
13875 /* Check for uncached addresses. */
13876 if (CONST_INT_P (x))
13877 return r10k_uncached_address_p (INTVAL (x));
13879 /* Check for accesses to a static object. */
13880 split_const (x, &base, &offset);
13881 return offset_within_block_p (base, INTVAL (offset));
13884 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13885 an in-range access to an automatic variable, or to an object with
13886 a link-time-constant address. */
13889 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
13891 if (offset < 0 || offset >= int_size_in_bytes (TREE_TYPE (expr)))
13894 while (TREE_CODE (expr) == COMPONENT_REF)
13896 expr = TREE_OPERAND (expr, 0);
13897 if (expr == NULL_TREE)
13901 return DECL_P (expr);
13904 /* A for_each_rtx callback for which DATA points to the instruction
13905 containing *X. Stop the search if we find a MEM that is not safe
13906 from R10K speculation. */
13909 r10k_needs_protection_p_1 (rtx *loc, void *data)
13918 && MEM_OFFSET_KNOWN_P (mem)
13919 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13922 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13928 /* A note_stores callback for which DATA points to an instruction pointer.
13929 If *DATA is nonnull, make it null if it X contains a MEM that is not
13930 safe from R10K speculation. */
13933 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13938 insn_ptr = (rtx *) data;
13939 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13940 *insn_ptr = NULL_RTX;
13943 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13944 Return nonzero if the call is not to a declared function. */
13947 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13956 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13962 /* Return true if instruction INSN needs to be protected by an R10K
13966 r10k_needs_protection_p (rtx insn)
13969 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13971 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13973 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13974 return insn == NULL_RTX;
13977 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
13980 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13981 edge is unconditional. */
13984 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
13989 FOR_EACH_EDGE (e, ei, bb->preds)
13990 if (!single_succ_p (e->src)
13991 || !TEST_BIT (protected_bbs, e->src->index)
13992 || (e->flags & EDGE_COMPLEX) != 0)
13997 /* Implement -mr10k-cache-barrier= for the current function. */
14000 r10k_insert_cache_barriers (void)
14002 int *rev_post_order;
14005 sbitmap protected_bbs;
14006 rtx insn, end, unprotected_region;
14010 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14014 /* Calculate dominators. */
14015 calculate_dominance_info (CDI_DOMINATORS);
14017 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14018 X is protected by a cache barrier. */
14019 protected_bbs = sbitmap_alloc (last_basic_block);
14020 sbitmap_zero (protected_bbs);
14022 /* Iterate over the basic blocks in reverse post-order. */
14023 rev_post_order = XNEWVEC (int, last_basic_block);
14024 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14025 for (i = 0; i < n; i++)
14027 bb = BASIC_BLOCK (rev_post_order[i]);
14029 /* If this block is only reached by unconditional edges, and if the
14030 source of every edge is protected, the beginning of the block is
14032 if (r10k_protected_bb_p (bb, protected_bbs))
14033 unprotected_region = NULL_RTX;
14035 unprotected_region = pc_rtx;
14036 end = NEXT_INSN (BB_END (bb));
14038 /* UNPROTECTED_REGION is:
14040 - null if we are processing a protected region,
14041 - pc_rtx if we are processing an unprotected region but have
14042 not yet found the first instruction in it
14043 - the first instruction in an unprotected region otherwise. */
14044 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14046 if (unprotected_region && USEFUL_INSN_P (insn))
14048 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14049 /* This CACHE instruction protects the following code. */
14050 unprotected_region = NULL_RTX;
14053 /* See if INSN is the first instruction in this
14054 unprotected region. */
14055 if (unprotected_region == pc_rtx)
14056 unprotected_region = insn;
14058 /* See if INSN needs to be protected. If so,
14059 we must insert a cache barrier somewhere between
14060 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14061 clear which position is better performance-wise,
14062 but as a tie-breaker, we assume that it is better
14063 to allow delay slots to be back-filled where
14064 possible, and that it is better not to insert
14065 barriers in the middle of already-scheduled code.
14066 We therefore insert the barrier at the beginning
14068 if (r10k_needs_protection_p (insn))
14070 emit_insn_before (gen_r10k_cache_barrier (),
14071 unprotected_region);
14072 unprotected_region = NULL_RTX;
14078 /* The called function is not required to protect the exit path.
14079 The code that follows a call is therefore unprotected. */
14080 unprotected_region = pc_rtx;
14083 /* Record whether the end of this block is protected. */
14084 if (unprotected_region == NULL_RTX)
14085 SET_BIT (protected_bbs, bb->index);
14087 XDELETEVEC (rev_post_order);
14089 sbitmap_free (protected_bbs);
14091 free_dominance_info (CDI_DOMINATORS);
14094 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14095 otherwise. If INSN has two call rtx, then store the second one in
14099 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14104 if (!CALL_P (insn))
14107 x = PATTERN (insn);
14108 if (GET_CODE (x) == PARALLEL)
14110 /* Calls returning complex values have two CALL rtx. Look for the second
14111 one here, and return it via the SECOND_CALL arg. */
14112 x2 = XVECEXP (x, 0, 1);
14113 if (GET_CODE (x2) == SET)
14115 if (GET_CODE (x2) == CALL)
14118 x = XVECEXP (x, 0, 0);
14120 if (GET_CODE (x) == SET)
14122 gcc_assert (GET_CODE (x) == CALL);
14127 /* REG is set in DEF. See if the definition is one of the ways we load a
14128 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14129 If it is, return the symbol reference of the function, otherwise return
14132 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14133 the values of source registers, otherwise treat such registers as
14134 having an unknown value. */
14137 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
14141 if (DF_REF_IS_ARTIFICIAL (def))
14144 def_insn = DF_REF_INSN (def);
14145 set = single_set (def_insn);
14146 if (set && rtx_equal_p (SET_DEST (set), reg))
14148 rtx note, src, symbol;
14150 /* First, look at REG_EQUAL/EQUIV notes. */
14151 note = find_reg_equal_equiv_note (def_insn);
14152 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14153 return XEXP (note, 0);
14155 /* For %call16 references we don't have REG_EQUAL. */
14156 src = SET_SRC (set);
14157 symbol = mips_strip_unspec_call (src);
14160 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14164 /* Follow at most one simple register copy. Such copies are
14165 interesting in cases like:
14169 locally_binding_fn (...);
14174 locally_binding_fn (...);
14176 locally_binding_fn (...);
14178 where the load of locally_binding_fn can legitimately be
14179 hoisted or shared. However, we do not expect to see complex
14180 chains of copies, so a full worklist solution to the problem
14181 would probably be overkill. */
14182 if (recurse_p && REG_P (src))
14183 return mips_find_pic_call_symbol (def_insn, src, false);
14189 /* Find the definition of the use of REG in INSN. See if the definition
14190 is one of the ways we load a register with a symbol address for a
14191 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14192 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14193 mips_pic_call_symbol_from_set. */
14196 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
14199 struct df_link *defs;
14202 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14205 defs = DF_REF_CHAIN (use);
14208 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14212 /* If we have more than one definition, they need to be identical. */
14213 for (defs = defs->next; defs; defs = defs->next)
14217 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14218 if (!rtx_equal_p (symbol, other))
14225 /* Replace the args_size operand of the call expression CALL with the
14226 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14229 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14233 args_size = XEXP (call, 1);
14234 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14235 gen_rtvec (2, args_size, symbol),
14239 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14240 if instead of the arg_size argument it contains the call attributes. If
14241 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14242 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14246 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14248 rtx args_size, symbol;
14250 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14253 args_size = operands[args_size_opno];
14254 if (GET_CODE (args_size) != UNSPEC)
14256 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14258 symbol = XVECEXP (args_size, 0, 1);
14259 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14261 operands[args_size_opno] = symbol;
14265 /* Use DF to annotate PIC indirect calls with the function symbol they
14269 mips_annotate_pic_calls (void)
14275 FOR_BB_INSNS (bb, insn)
14277 rtx call, reg, symbol, second_call;
14280 call = mips_call_expr_from_insn (insn, &second_call);
14283 gcc_assert (MEM_P (XEXP (call, 0)));
14284 reg = XEXP (XEXP (call, 0), 0);
14288 symbol = mips_find_pic_call_symbol (insn, reg, true);
14291 mips_annotate_pic_call_expr (call, symbol);
14293 mips_annotate_pic_call_expr (second_call, symbol);
14298 /* A temporary variable used by for_each_rtx callbacks, etc. */
14299 static rtx mips_sim_insn;
14301 /* A structure representing the state of the processor pipeline.
14302 Used by the mips_sim_* family of functions. */
14304 /* The maximum number of instructions that can be issued in a cycle.
14305 (Caches mips_issue_rate.) */
14306 unsigned int issue_rate;
14308 /* The current simulation time. */
14311 /* How many more instructions can be issued in the current cycle. */
14312 unsigned int insns_left;
14314 /* LAST_SET[X].INSN is the last instruction to set register X.
14315 LAST_SET[X].TIME is the time at which that instruction was issued.
14316 INSN is null if no instruction has yet set register X. */
14320 } last_set[FIRST_PSEUDO_REGISTER];
14322 /* The pipeline's current DFA state. */
14326 /* Reset STATE to the initial simulation state. */
14329 mips_sim_reset (struct mips_sim *state)
14332 state->insns_left = state->issue_rate;
14333 memset (&state->last_set, 0, sizeof (state->last_set));
14334 state_reset (state->dfa_state);
14337 /* Initialize STATE before its first use. DFA_STATE points to an
14338 allocated but uninitialized DFA state. */
14341 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14343 state->issue_rate = mips_issue_rate ();
14344 state->dfa_state = dfa_state;
14345 mips_sim_reset (state);
14348 /* Advance STATE by one clock cycle. */
14351 mips_sim_next_cycle (struct mips_sim *state)
14354 state->insns_left = state->issue_rate;
14355 state_transition (state->dfa_state, 0);
14358 /* Advance simulation state STATE until instruction INSN can read
14362 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14364 unsigned int regno, end_regno;
14366 end_regno = END_REGNO (reg);
14367 for (regno = REGNO (reg); regno < end_regno; regno++)
14368 if (state->last_set[regno].insn != 0)
14372 t = (state->last_set[regno].time
14373 + insn_latency (state->last_set[regno].insn, insn));
14374 while (state->time < t)
14375 mips_sim_next_cycle (state);
14379 /* A for_each_rtx callback. If *X is a register, advance simulation state
14380 DATA until mips_sim_insn can read the register's value. */
14383 mips_sim_wait_regs_2 (rtx *x, void *data)
14386 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14390 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14393 mips_sim_wait_regs_1 (rtx *x, void *data)
14395 for_each_rtx (x, mips_sim_wait_regs_2, data);
14398 /* Advance simulation state STATE until all of INSN's register
14399 dependencies are satisfied. */
14402 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14404 mips_sim_insn = insn;
14405 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14408 /* Advance simulation state STATE until the units required by
14409 instruction INSN are available. */
14412 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14416 tmp_state = alloca (state_size ());
14417 while (state->insns_left == 0
14418 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14419 state_transition (tmp_state, insn) >= 0))
14420 mips_sim_next_cycle (state);
14423 /* Advance simulation state STATE until INSN is ready to issue. */
14426 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14428 mips_sim_wait_regs (state, insn);
14429 mips_sim_wait_units (state, insn);
14432 /* mips_sim_insn has just set X. Update the LAST_SET array
14433 in simulation state DATA. */
14436 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14438 struct mips_sim *state;
14440 state = (struct mips_sim *) data;
14443 unsigned int regno, end_regno;
14445 end_regno = END_REGNO (x);
14446 for (regno = REGNO (x); regno < end_regno; regno++)
14448 state->last_set[regno].insn = mips_sim_insn;
14449 state->last_set[regno].time = state->time;
14454 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14455 can issue immediately (i.e., that mips_sim_wait_insn has already
14459 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14461 state_transition (state->dfa_state, insn);
14462 state->insns_left--;
14464 mips_sim_insn = insn;
14465 note_stores (PATTERN (insn), mips_sim_record_set, state);
14468 /* Simulate issuing a NOP in state STATE. */
14471 mips_sim_issue_nop (struct mips_sim *state)
14473 if (state->insns_left == 0)
14474 mips_sim_next_cycle (state);
14475 state->insns_left--;
14478 /* Update simulation state STATE so that it's ready to accept the instruction
14479 after INSN. INSN should be part of the main rtl chain, not a member of a
14483 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14485 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14487 mips_sim_issue_nop (state);
14489 switch (GET_CODE (SEQ_BEGIN (insn)))
14493 /* We can't predict the processor state after a call or label. */
14494 mips_sim_reset (state);
14498 /* The delay slots of branch likely instructions are only executed
14499 when the branch is taken. Therefore, if the caller has simulated
14500 the delay slot instruction, STATE does not really reflect the state
14501 of the pipeline for the instruction after the delay slot. Also,
14502 branch likely instructions tend to incur a penalty when not taken,
14503 so there will probably be an extra delay between the branch and
14504 the instruction after the delay slot. */
14505 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14506 mips_sim_reset (state);
14514 /* The VR4130 pipeline issues aligned pairs of instructions together,
14515 but it stalls the second instruction if it depends on the first.
14516 In order to cut down the amount of logic required, this dependence
14517 check is not based on a full instruction decode. Instead, any non-SPECIAL
14518 instruction is assumed to modify the register specified by bits 20-16
14519 (which is usually the "rt" field).
14521 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14522 input, so we can end up with a false dependence between the branch
14523 and its delay slot. If this situation occurs in instruction INSN,
14524 try to avoid it by swapping rs and rt. */
14527 vr4130_avoid_branch_rt_conflict (rtx insn)
14531 first = SEQ_BEGIN (insn);
14532 second = SEQ_END (insn);
14534 && NONJUMP_INSN_P (second)
14535 && GET_CODE (PATTERN (first)) == SET
14536 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14537 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14539 /* Check for the right kind of condition. */
14540 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14541 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14542 && REG_P (XEXP (cond, 0))
14543 && REG_P (XEXP (cond, 1))
14544 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14545 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14547 /* SECOND mentions the rt register but not the rs register. */
14548 rtx tmp = XEXP (cond, 0);
14549 XEXP (cond, 0) = XEXP (cond, 1);
14550 XEXP (cond, 1) = tmp;
14555 /* Implement -mvr4130-align. Go through each basic block and simulate the
14556 processor pipeline. If we find that a pair of instructions could execute
14557 in parallel, and the first of those instructions is not 8-byte aligned,
14558 insert a nop to make it aligned. */
14561 vr4130_align_insns (void)
14563 struct mips_sim state;
14564 rtx insn, subinsn, last, last2, next;
14569 /* LAST is the last instruction before INSN to have a nonzero length.
14570 LAST2 is the last such instruction before LAST. */
14574 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14577 mips_sim_init (&state, alloca (state_size ()));
14578 for (insn = get_insns (); insn != 0; insn = next)
14580 unsigned int length;
14582 next = NEXT_INSN (insn);
14584 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14585 This isn't really related to the alignment pass, but we do it on
14586 the fly to avoid a separate instruction walk. */
14587 vr4130_avoid_branch_rt_conflict (insn);
14589 if (USEFUL_INSN_P (insn))
14590 FOR_EACH_SUBINSN (subinsn, insn)
14592 mips_sim_wait_insn (&state, subinsn);
14594 /* If we want this instruction to issue in parallel with the
14595 previous one, make sure that the previous instruction is
14596 aligned. There are several reasons why this isn't worthwhile
14597 when the second instruction is a call:
14599 - Calls are less likely to be performance critical,
14600 - There's a good chance that the delay slot can execute
14601 in parallel with the call.
14602 - The return address would then be unaligned.
14604 In general, if we're going to insert a nop between instructions
14605 X and Y, it's better to insert it immediately after X. That
14606 way, if the nop makes Y aligned, it will also align any labels
14607 between X and Y. */
14608 if (state.insns_left != state.issue_rate
14609 && !CALL_P (subinsn))
14611 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14613 /* SUBINSN is the first instruction in INSN and INSN is
14614 aligned. We want to align the previous instruction
14615 instead, so insert a nop between LAST2 and LAST.
14617 Note that LAST could be either a single instruction
14618 or a branch with a delay slot. In the latter case,
14619 LAST, like INSN, is already aligned, but the delay
14620 slot must have some extra delay that stops it from
14621 issuing at the same time as the branch. We therefore
14622 insert a nop before the branch in order to align its
14624 emit_insn_after (gen_nop (), last2);
14627 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14629 /* SUBINSN is the delay slot of INSN, but INSN is
14630 currently unaligned. Insert a nop between
14631 LAST and INSN to align it. */
14632 emit_insn_after (gen_nop (), last);
14636 mips_sim_issue_insn (&state, subinsn);
14638 mips_sim_finish_insn (&state, insn);
14640 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14641 length = get_attr_length (insn);
14644 /* If the instruction is an asm statement or multi-instruction
14645 mips.md patern, the length is only an estimate. Insert an
14646 8 byte alignment after it so that the following instructions
14647 can be handled correctly. */
14648 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14649 && (recog_memoized (insn) < 0 || length >= 8))
14651 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14652 next = NEXT_INSN (next);
14653 mips_sim_next_cycle (&state);
14656 else if (length & 4)
14657 aligned_p = !aligned_p;
14662 /* See whether INSN is an aligned label. */
14663 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14669 /* This structure records that the current function has a LO_SUM
14670 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14671 the largest offset applied to BASE by all such LO_SUMs. */
14672 struct mips_lo_sum_offset {
14674 HOST_WIDE_INT offset;
14677 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14680 mips_hash_base (rtx base)
14682 int do_not_record_p;
14684 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14687 /* Hash-table callbacks for mips_lo_sum_offsets. */
14690 mips_lo_sum_offset_hash (const void *entry)
14692 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14696 mips_lo_sum_offset_eq (const void *entry, const void *value)
14698 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14699 (const_rtx) value);
14702 /* Look up symbolic constant X in HTAB, which is a hash table of
14703 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14704 paired with a recorded LO_SUM, otherwise record X in the table. */
14707 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14711 struct mips_lo_sum_offset *entry;
14713 /* Split X into a base and offset. */
14714 split_const (x, &base, &offset);
14715 if (UNSPEC_ADDRESS_P (base))
14716 base = UNSPEC_ADDRESS (base);
14718 /* Look up the base in the hash table. */
14719 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14723 entry = (struct mips_lo_sum_offset *) *slot;
14724 if (option == INSERT)
14728 entry = XNEW (struct mips_lo_sum_offset);
14729 entry->base = base;
14730 entry->offset = INTVAL (offset);
14735 if (INTVAL (offset) > entry->offset)
14736 entry->offset = INTVAL (offset);
14739 return INTVAL (offset) <= entry->offset;
14742 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14743 Record every LO_SUM in *LOC. */
14746 mips_record_lo_sum (rtx *loc, void *data)
14748 if (GET_CODE (*loc) == LO_SUM)
14749 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14753 /* Return true if INSN is a SET of an orphaned high-part relocation.
14754 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14755 LO_SUMs in the current function. */
14758 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14760 enum mips_symbol_type type;
14763 set = single_set (insn);
14766 /* Check for %his. */
14768 if (GET_CODE (x) == HIGH
14769 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14770 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14772 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14773 if (GET_CODE (x) == UNSPEC
14774 && XINT (x, 1) == UNSPEC_LOAD_GOT
14775 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14776 SYMBOL_CONTEXT_LEA, &type)
14777 && type == SYMBOL_GOTOFF_PAGE)
14778 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14783 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14784 INSN and a previous instruction, avoid it by inserting nops after
14787 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14788 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14789 before using the value of that register. *HILO_DELAY counts the
14790 number of instructions since the last hilo hazard (that is,
14791 the number of instructions since the last MFLO or MFHI).
14793 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14794 for the next instruction.
14796 LO_REG is an rtx for the LO register, used in dependence checking. */
14799 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14800 rtx *delayed_reg, rtx lo_reg)
14805 pattern = PATTERN (insn);
14807 /* Do not put the whole function in .set noreorder if it contains
14808 an asm statement. We don't know whether there will be hazards
14809 between the asm statement and the gcc-generated code. */
14810 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14811 cfun->machine->all_noreorder_p = false;
14813 /* Ignore zero-length instructions (barriers and the like). */
14814 ninsns = get_attr_length (insn) / 4;
14818 /* Work out how many nops are needed. Note that we only care about
14819 registers that are explicitly mentioned in the instruction's pattern.
14820 It doesn't matter that calls use the argument registers or that they
14821 clobber hi and lo. */
14822 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14823 nops = 2 - *hilo_delay;
14824 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14829 /* Insert the nops between this instruction and the previous one.
14830 Each new nop takes us further from the last hilo hazard. */
14831 *hilo_delay += nops;
14833 emit_insn_after (gen_hazard_nop (), after);
14835 /* Set up the state for the next instruction. */
14836 *hilo_delay += ninsns;
14838 if (INSN_CODE (insn) >= 0)
14839 switch (get_attr_hazard (insn))
14849 set = single_set (insn);
14851 *delayed_reg = SET_DEST (set);
14856 /* Go through the instruction stream and insert nops where necessary.
14857 Also delete any high-part relocations whose partnering low parts
14858 are now all dead. See if the whole function can then be put into
14859 .set noreorder and .set nomacro. */
14862 mips_reorg_process_insns (void)
14864 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14868 /* Force all instructions to be split into their final form. */
14869 split_all_insns_noflow ();
14871 /* Recalculate instruction lengths without taking nops into account. */
14872 cfun->machine->ignore_hazard_length_p = true;
14873 shorten_branches (get_insns ());
14875 cfun->machine->all_noreorder_p = true;
14877 /* We don't track MIPS16 PC-relative offsets closely enough to make
14878 a good job of "set .noreorder" code in MIPS16 mode. */
14880 cfun->machine->all_noreorder_p = false;
14882 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14883 if (!TARGET_EXPLICIT_RELOCS)
14884 cfun->machine->all_noreorder_p = false;
14886 /* Profiled functions can't be all noreorder because the profiler
14887 support uses assembler macros. */
14889 cfun->machine->all_noreorder_p = false;
14891 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
14892 because we rely on the assembler to work around some errata. */
14893 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
14894 cfun->machine->all_noreorder_p = false;
14896 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14897 MFHI instructions. Note that we avoid using MFLO and MFHI if
14898 the VR4130 MACC and DMACC instructions are available instead;
14899 see the *mfhilo_{si,di}_macc patterns. */
14900 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14901 cfun->machine->all_noreorder_p = false;
14903 htab = htab_create (37, mips_lo_sum_offset_hash,
14904 mips_lo_sum_offset_eq, free);
14906 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14907 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14908 FOR_EACH_SUBINSN (subinsn, insn)
14909 if (USEFUL_INSN_P (subinsn))
14910 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14915 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14917 /* Make a second pass over the instructions. Delete orphaned
14918 high-part relocations or turn them into NOPs. Avoid hazards
14919 by inserting NOPs. */
14920 for (insn = get_insns (); insn != 0; insn = next_insn)
14922 next_insn = NEXT_INSN (insn);
14923 if (USEFUL_INSN_P (insn))
14925 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14927 /* If we find an orphaned high-part relocation in a delay
14928 slot, it's easier to turn that instruction into a NOP than
14929 to delete it. The delay slot will be a NOP either way. */
14930 FOR_EACH_SUBINSN (subinsn, insn)
14931 if (INSN_P (subinsn))
14933 if (mips_orphaned_high_part_p (htab, subinsn))
14935 PATTERN (subinsn) = gen_nop ();
14936 INSN_CODE (subinsn) = CODE_FOR_nop;
14938 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14939 &delayed_reg, lo_reg);
14945 /* INSN is a single instruction. Delete it if it's an
14946 orphaned high-part relocation. */
14947 if (mips_orphaned_high_part_p (htab, insn))
14948 delete_insn (insn);
14949 /* Also delete cache barriers if the last instruction
14950 was an annulled branch. INSN will not be speculatively
14952 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14954 && JUMP_P (SEQ_BEGIN (last_insn))
14955 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14956 delete_insn (insn);
14959 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14960 &delayed_reg, lo_reg);
14967 htab_delete (htab);
14970 /* If we are using a GOT, but have not decided to use a global pointer yet,
14971 see whether we need one to implement long branches. Convert the ghost
14972 global-pointer instructions into real ones if so. */
14975 mips_expand_ghost_gp_insns (void)
14980 /* Quick exit if we already know that we will or won't need a
14982 if (!TARGET_USE_GOT
14983 || cfun->machine->global_pointer == INVALID_REGNUM
14984 || mips_must_initialize_gp_p ())
14987 shorten_branches (get_insns ());
14989 /* Look for a branch that is longer than normal. The normal length for
14990 non-MIPS16 branches is 8, because the length includes the delay slot.
14991 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14992 but they have no delay slot. */
14993 normal_length = (TARGET_MIPS16 ? 4 : 8);
14994 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14996 && USEFUL_INSN_P (insn)
14997 && get_attr_length (insn) > normal_length)
15000 if (insn == NULL_RTX)
15003 /* We've now established that we need $gp. */
15004 cfun->machine->must_initialize_gp_p = true;
15005 split_all_insns_noflow ();
15010 /* Subroutine of mips_reorg to manage passes that require DF. */
15013 mips_df_reorg (void)
15015 /* Create def-use chains. */
15016 df_set_flags (DF_EQ_NOTES);
15017 df_chain_add_problem (DF_UD_CHAIN);
15020 if (TARGET_RELAX_PIC_CALLS)
15021 mips_annotate_pic_calls ();
15023 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15024 r10k_insert_cache_barriers ();
15026 df_finish_pass (false);
15029 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15034 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15035 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15036 to date if the CFG is available. */
15037 if (mips_cfg_in_reorg ())
15038 compute_bb_for_insn ();
15039 mips16_lay_out_constants ();
15040 if (mips_cfg_in_reorg ())
15043 free_bb_for_insn ();
15046 if (optimize > 0 && flag_delayed_branch)
15047 dbr_schedule (get_insns ());
15048 mips_reorg_process_insns ();
15050 && TARGET_EXPLICIT_RELOCS
15052 && TARGET_VR4130_ALIGN)
15053 vr4130_align_insns ();
15054 if (mips_expand_ghost_gp_insns ())
15055 /* The expansion could invalidate some of the VR4130 alignment
15056 optimizations, but this should be an extremely rare case anyhow. */
15057 mips_reorg_process_insns ();
15060 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15061 in order to avoid duplicating too much logic from elsewhere. */
15064 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15065 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15068 rtx this_rtx, temp1, temp2, insn, fnaddr;
15069 bool use_sibcall_p;
15071 /* Pretend to be a post-reload pass while generating rtl. */
15072 reload_completed = 1;
15074 /* Mark the end of the (empty) prologue. */
15075 emit_note (NOTE_INSN_PROLOGUE_END);
15077 /* Determine if we can use a sibcall to call FUNCTION directly. */
15078 fnaddr = XEXP (DECL_RTL (function), 0);
15079 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15080 && const_call_insn_operand (fnaddr, Pmode));
15082 /* Determine if we need to load FNADDR from the GOT. */
15084 && (mips_got_symbol_type_p
15085 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15087 /* Pick a global pointer. Use a call-clobbered register if
15088 TARGET_CALL_SAVED_GP. */
15089 cfun->machine->global_pointer
15090 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15091 cfun->machine->must_initialize_gp_p = true;
15092 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15094 /* Set up the global pointer for n32 or n64 abicalls. */
15095 mips_emit_loadgp ();
15098 /* We need two temporary registers in some cases. */
15099 temp1 = gen_rtx_REG (Pmode, 2);
15100 temp2 = gen_rtx_REG (Pmode, 3);
15102 /* Find out which register contains the "this" pointer. */
15103 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15104 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15106 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15108 /* Add DELTA to THIS_RTX. */
15111 rtx offset = GEN_INT (delta);
15112 if (!SMALL_OPERAND (delta))
15114 mips_emit_move (temp1, offset);
15117 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15120 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15121 if (vcall_offset != 0)
15125 /* Set TEMP1 to *THIS_RTX. */
15126 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15128 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15129 addr = mips_add_offset (temp2, temp1, vcall_offset);
15131 /* Load the offset and add it to THIS_RTX. */
15132 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15133 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15136 /* Jump to the target function. Use a sibcall if direct jumps are
15137 allowed, otherwise load the address into a register first. */
15140 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15141 SIBLING_CALL_P (insn) = 1;
15145 /* This is messy. GAS treats "la $25,foo" as part of a call
15146 sequence and may allow a global "foo" to be lazily bound.
15147 The general move patterns therefore reject this combination.
15149 In this context, lazy binding would actually be OK
15150 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15151 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15152 We must therefore load the address via a temporary
15153 register if mips_dangerous_for_la25_p.
15155 If we jump to the temporary register rather than $25,
15156 the assembler can use the move insn to fill the jump's
15159 We can use the same technique for MIPS16 code, where $25
15160 is not a valid JR register. */
15161 if (TARGET_USE_PIC_FN_ADDR_REG
15163 && !mips_dangerous_for_la25_p (fnaddr))
15164 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15165 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15167 if (TARGET_USE_PIC_FN_ADDR_REG
15168 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15169 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15170 emit_jump_insn (gen_indirect_jump (temp1));
15173 /* Run just enough of rest_of_compilation. This sequence was
15174 "borrowed" from alpha.c. */
15175 insn = get_insns ();
15176 insn_locators_alloc ();
15177 split_all_insns_noflow ();
15178 mips16_lay_out_constants ();
15179 shorten_branches (insn);
15180 final_start_function (insn, file, 1);
15181 final (insn, file, 1);
15182 final_end_function ();
15184 /* Clean up the vars set above. Note that final_end_function resets
15185 the global pointer for us. */
15186 reload_completed = 0;
15189 /* The last argument passed to mips_set_mips16_mode, or negative if the
15190 function hasn't been called yet.
15192 There are two copies of this information. One is saved and restored
15193 by the PCH process while the other is specific to this compiler
15194 invocation. The information calculated by mips_set_mips16_mode
15195 is invalid unless the two variables are the same. */
15196 static int was_mips16_p = -1;
15197 static GTY(()) int was_mips16_pch_p = -1;
15199 /* Set up the target-dependent global state so that it matches the
15200 current function's ISA mode. */
15203 mips_set_mips16_mode (int mips16_p)
15205 if (mips16_p == was_mips16_p
15206 && mips16_p == was_mips16_pch_p)
15209 /* Restore base settings of various flags. */
15210 target_flags = mips_base_target_flags;
15211 flag_schedule_insns = mips_base_schedule_insns;
15212 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15213 flag_move_loop_invariants = mips_base_move_loop_invariants;
15214 align_loops = mips_base_align_loops;
15215 align_jumps = mips_base_align_jumps;
15216 align_functions = mips_base_align_functions;
15220 /* Switch to MIPS16 mode. */
15221 target_flags |= MASK_MIPS16;
15223 /* Don't run the scheduler before reload, since it tends to
15224 increase register pressure. */
15225 flag_schedule_insns = 0;
15227 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15228 the whole function to be in a single section. */
15229 flag_reorder_blocks_and_partition = 0;
15231 /* Don't move loop invariants, because it tends to increase
15232 register pressure. It also introduces an extra move in cases
15233 where the constant is the first operand in a two-operand binary
15234 instruction, or when it forms a register argument to a functon
15236 flag_move_loop_invariants = 0;
15238 target_flags |= MASK_EXPLICIT_RELOCS;
15240 /* Experiments suggest we get the best overall section-anchor
15241 results from using the range of an unextended LW or SW. Code
15242 that makes heavy use of byte or short accesses can do better
15243 with ranges of 0...31 and 0...63 respectively, but most code is
15244 sensitive to the range of LW and SW instead. */
15245 targetm.min_anchor_offset = 0;
15246 targetm.max_anchor_offset = 127;
15248 targetm.const_anchor = 0;
15250 /* MIPS16 has no BAL instruction. */
15251 target_flags &= ~MASK_RELAX_PIC_CALLS;
15253 /* The R4000 errata don't apply to any known MIPS16 cores.
15254 It's simpler to make the R4000 fixes and MIPS16 mode
15255 mutually exclusive. */
15256 target_flags &= ~MASK_FIX_R4000;
15258 if (flag_pic && !TARGET_OLDABI)
15259 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15262 sorry ("MIPS16 -mxgot code");
15264 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15265 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15269 /* Switch to normal (non-MIPS16) mode. */
15270 target_flags &= ~MASK_MIPS16;
15272 /* Provide default values for align_* for 64-bit targets. */
15275 if (align_loops == 0)
15277 if (align_jumps == 0)
15279 if (align_functions == 0)
15280 align_functions = 8;
15283 targetm.min_anchor_offset = -32768;
15284 targetm.max_anchor_offset = 32767;
15286 targetm.const_anchor = 0x8000;
15289 /* (Re)initialize MIPS target internals for new ISA. */
15290 mips_init_relocs ();
15294 if (!mips16_globals)
15295 mips16_globals = save_target_globals ();
15297 restore_target_globals (mips16_globals);
15300 restore_target_globals (&default_target_globals);
15302 was_mips16_p = mips16_p;
15303 was_mips16_pch_p = mips16_p;
15306 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15307 function should use the MIPS16 ISA and switch modes accordingly. */
15310 mips_set_current_function (tree fndecl)
15312 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15315 /* Allocate a chunk of memory for per-function machine-dependent data. */
15317 static struct machine_function *
15318 mips_init_machine_status (void)
15320 return ggc_alloc_cleared_machine_function ();
15323 /* Return the processor associated with the given ISA level, or null
15324 if the ISA isn't valid. */
15326 static const struct mips_cpu_info *
15327 mips_cpu_info_from_isa (int isa)
15331 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15332 if (mips_cpu_info_table[i].isa == isa)
15333 return mips_cpu_info_table + i;
15338 /* Return a mips_cpu_info entry determined by an option valued
15341 static const struct mips_cpu_info *
15342 mips_cpu_info_from_opt (int opt)
15346 case MIPS_ARCH_OPTION_FROM_ABI:
15347 /* 'from-abi' selects the most compatible architecture for the
15348 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
15349 ABIs. For the EABIs, we have to decide whether we're using
15350 the 32-bit or 64-bit version. */
15351 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15352 : ABI_NEEDS_64BIT_REGS ? 3
15353 : (TARGET_64BIT ? 3 : 1));
15355 case MIPS_ARCH_OPTION_NATIVE:
15356 gcc_unreachable ();
15359 return &mips_cpu_info_table[opt];
15363 /* Return a default mips_cpu_info entry, given that no -march= option
15364 was explicitly specified. */
15366 static const struct mips_cpu_info *
15367 mips_default_arch (void)
15369 #if defined (MIPS_CPU_STRING_DEFAULT)
15371 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15372 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
15373 return mips_cpu_info_table + i;
15374 gcc_unreachable ();
15375 #elif defined (MIPS_ISA_DEFAULT)
15376 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
15378 /* 'from-abi' makes a good default: you get whatever the ABI
15380 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
15384 /* Set up globals to generate code for the ISA or processor
15385 described by INFO. */
15388 mips_set_architecture (const struct mips_cpu_info *info)
15392 mips_arch_info = info;
15393 mips_arch = info->cpu;
15394 mips_isa = info->isa;
15398 /* Likewise for tuning. */
15401 mips_set_tune (const struct mips_cpu_info *info)
15405 mips_tune_info = info;
15406 mips_tune = info->cpu;
15410 /* Implement TARGET_OPTION_OVERRIDE. */
15413 mips_option_override (void)
15415 int i, start, regno, mode;
15417 if (global_options_set.x_mips_isa_option)
15418 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
15420 /* Process flags as though we were generating non-MIPS16 code. */
15421 mips_base_mips16 = TARGET_MIPS16;
15422 target_flags &= ~MASK_MIPS16;
15424 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15425 SUBTARGET_OVERRIDE_OPTIONS;
15428 /* -mno-float overrides -mhard-float and -msoft-float. */
15429 if (TARGET_NO_FLOAT)
15431 target_flags |= MASK_SOFT_FLOAT_ABI;
15432 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15435 if (TARGET_FLIP_MIPS16)
15436 TARGET_INTERLINK_MIPS16 = 1;
15438 /* Set the small data limit. */
15439 mips_small_data_threshold = (global_options_set.x_g_switch_value
15441 : MIPS_DEFAULT_GVALUE);
15443 /* The following code determines the architecture and register size.
15444 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15445 The GAS and GCC code should be kept in sync as much as possible. */
15447 if (global_options_set.x_mips_arch_option)
15448 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
15450 if (mips_isa_option_info != 0)
15452 if (mips_arch_info == 0)
15453 mips_set_architecture (mips_isa_option_info);
15454 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15455 error ("%<-%s%> conflicts with the other architecture options, "
15456 "which specify a %s processor",
15457 mips_isa_option_info->name,
15458 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15461 if (mips_arch_info == 0)
15462 mips_set_architecture (mips_default_arch ());
15464 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15465 error ("%<-march=%s%> is not compatible with the selected ABI",
15466 mips_arch_info->name);
15468 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15469 if (global_options_set.x_mips_tune_option)
15470 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
15472 if (mips_tune_info == 0)
15473 mips_set_tune (mips_arch_info);
15475 if ((target_flags_explicit & MASK_64BIT) != 0)
15477 /* The user specified the size of the integer registers. Make sure
15478 it agrees with the ABI and ISA. */
15479 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15480 error ("%<-mgp64%> used with a 32-bit processor");
15481 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15482 error ("%<-mgp32%> used with a 64-bit ABI");
15483 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15484 error ("%<-mgp64%> used with a 32-bit ABI");
15488 /* Infer the integer register size from the ABI and processor.
15489 Restrict ourselves to 32-bit registers if that's all the
15490 processor has, or if the ABI cannot handle 64-bit registers. */
15491 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15492 target_flags &= ~MASK_64BIT;
15494 target_flags |= MASK_64BIT;
15497 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15499 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15500 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15501 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15502 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15503 else if (!TARGET_64BIT && TARGET_FLOAT64)
15505 if (!ISA_HAS_MXHC1)
15506 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15507 " the target supports the mfhc1 and mthc1 instructions");
15508 else if (mips_abi != ABI_32)
15509 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15515 /* -msingle-float selects 32-bit float registers. Otherwise the
15516 float registers should be the same size as the integer ones. */
15517 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15518 target_flags |= MASK_FLOAT64;
15520 target_flags &= ~MASK_FLOAT64;
15523 /* End of code shared with GAS. */
15525 /* If a -mlong* option was given, check that it matches the ABI,
15526 otherwise infer the -mlong* setting from the other options. */
15527 if ((target_flags_explicit & MASK_LONG64) != 0)
15531 if (mips_abi == ABI_N32)
15532 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
15533 else if (mips_abi == ABI_32)
15534 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
15535 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
15536 /* We have traditionally allowed non-abicalls code to use
15537 an LP64 form of o64. However, it would take a bit more
15538 effort to support the combination of 32-bit GOT entries
15539 and 64-bit pointers, so we treat the abicalls case as
15541 error ("the combination of %qs and %qs is incompatible with %qs",
15542 "-mabi=o64", "-mabicalls", "-mlong64");
15546 if (mips_abi == ABI_64)
15547 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
15552 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15553 target_flags |= MASK_LONG64;
15555 target_flags &= ~MASK_LONG64;
15558 if (!TARGET_OLDABI)
15559 flag_pcc_struct_return = 0;
15561 /* Decide which rtx_costs structure to use. */
15563 mips_cost = &mips_rtx_cost_optimize_size;
15565 mips_cost = &mips_rtx_cost_data[mips_tune];
15567 /* If the user hasn't specified a branch cost, use the processor's
15569 if (mips_branch_cost == 0)
15570 mips_branch_cost = mips_cost->branch_cost;
15572 /* If neither -mbranch-likely nor -mno-branch-likely was given
15573 on the command line, set MASK_BRANCHLIKELY based on the target
15574 architecture and tuning flags. Annulled delay slots are a
15575 size win, so we only consider the processor-specific tuning
15576 for !optimize_size. */
15577 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15579 if (ISA_HAS_BRANCHLIKELY
15581 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15582 target_flags |= MASK_BRANCHLIKELY;
15584 target_flags &= ~MASK_BRANCHLIKELY;
15586 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15587 warning (0, "the %qs architecture does not support branch-likely"
15588 " instructions", mips_arch_info->name);
15590 /* The effect of -mabicalls isn't defined for the EABI. */
15591 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15593 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15594 target_flags &= ~MASK_ABICALLS;
15597 if (TARGET_ABICALLS_PIC2)
15598 /* We need to set flag_pic for executables as well as DSOs
15599 because we may reference symbols that are not defined in
15600 the final executable. (MIPS does not use things like
15601 copy relocs, for example.)
15603 There is a body of code that uses __PIC__ to distinguish
15604 between -mabicalls and -mno-abicalls code. The non-__PIC__
15605 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15606 long as any indirect jumps use $25. */
15609 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15610 faster code, but at the expense of more nops. Enable it at -O3 and
15612 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15613 target_flags |= MASK_VR4130_ALIGN;
15615 /* Prefer a call to memcpy over inline code when optimizing for size,
15616 though see MOVE_RATIO in mips.h. */
15617 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15618 target_flags |= MASK_MEMCPY;
15620 /* If we have a nonzero small-data limit, check that the -mgpopt
15621 setting is consistent with the other target flags. */
15622 if (mips_small_data_threshold > 0)
15626 if (!TARGET_EXPLICIT_RELOCS)
15627 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15629 TARGET_LOCAL_SDATA = false;
15630 TARGET_EXTERN_SDATA = false;
15634 if (TARGET_VXWORKS_RTP)
15635 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15637 if (TARGET_ABICALLS)
15638 warning (0, "cannot use small-data accesses for %qs",
15643 #ifdef MIPS_TFMODE_FORMAT
15644 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15647 /* Make sure that the user didn't turn off paired single support when
15648 MIPS-3D support is requested. */
15650 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15651 && !TARGET_PAIRED_SINGLE_FLOAT)
15652 error ("%<-mips3d%> requires %<-mpaired-single%>");
15654 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15656 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15658 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15659 and TARGET_HARD_FLOAT_ABI are both true. */
15660 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15661 error ("%qs must be used with %qs",
15662 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15663 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15665 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15667 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15668 warning (0, "the %qs architecture does not support paired-single"
15669 " instructions", mips_arch_info->name);
15671 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15672 && !TARGET_CACHE_BUILTIN)
15674 error ("%qs requires a target that provides the %qs instruction",
15675 "-mr10k-cache-barrier", "cache");
15676 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15679 /* If TARGET_DSPR2, enable MASK_DSP. */
15681 target_flags |= MASK_DSP;
15683 /* .eh_frame addresses should be the same width as a C pointer.
15684 Most MIPS ABIs support only one pointer size, so the assembler
15685 will usually know exactly how big an .eh_frame address is.
15687 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15688 originally defined to use 64-bit pointers (i.e. it is LP64), and
15689 this is still the default mode. However, we also support an n32-like
15690 ILP32 mode, which is selected by -mlong32. The problem is that the
15691 assembler has traditionally not had an -mlong option, so it has
15692 traditionally not known whether we're using the ILP32 or LP64 form.
15694 As it happens, gas versions up to and including 2.19 use _32-bit_
15695 addresses for EABI64 .cfi_* directives. This is wrong for the
15696 default LP64 mode, so we can't use the directives by default.
15697 Moreover, since gas's current behavior is at odds with gcc's
15698 default behavior, it seems unwise to rely on future versions
15699 of gas behaving the same way. We therefore avoid using .cfi
15700 directives for -mlong32 as well. */
15701 if (mips_abi == ABI_EABI && TARGET_64BIT)
15702 flag_dwarf2_cfi_asm = 0;
15704 /* .cfi_* directives generate a read-only section, so fall back on
15705 manual .eh_frame creation if we need the section to be writable. */
15706 if (TARGET_WRITABLE_EH_FRAME)
15707 flag_dwarf2_cfi_asm = 0;
15709 mips_init_print_operand_punct ();
15711 /* Set up array to map GCC register number to debug register number.
15712 Ignore the special purpose register numbers. */
15714 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15716 mips_dbx_regno[i] = INVALID_REGNUM;
15717 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15718 mips_dwarf_regno[i] = i;
15720 mips_dwarf_regno[i] = INVALID_REGNUM;
15723 start = GP_DBX_FIRST - GP_REG_FIRST;
15724 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15725 mips_dbx_regno[i] = i + start;
15727 start = FP_DBX_FIRST - FP_REG_FIRST;
15728 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15729 mips_dbx_regno[i] = i + start;
15731 /* Accumulator debug registers use big-endian ordering. */
15732 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15733 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15734 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15735 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15736 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15738 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15739 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15742 /* Set up mips_hard_regno_mode_ok. */
15743 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15744 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15745 mips_hard_regno_mode_ok[mode][regno]
15746 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15748 /* Function to allocate machine-dependent function status. */
15749 init_machine_status = &mips_init_machine_status;
15751 /* Default to working around R4000 errata only if the processor
15752 was selected explicitly. */
15753 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15754 && strcmp (mips_arch_info->name, "r4000") == 0)
15755 target_flags |= MASK_FIX_R4000;
15757 /* Default to working around R4400 errata only if the processor
15758 was selected explicitly. */
15759 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15760 && strcmp (mips_arch_info->name, "r4400") == 0)
15761 target_flags |= MASK_FIX_R4400;
15763 /* Default to working around R10000 errata only if the processor
15764 was selected explicitly. */
15765 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15766 && strcmp (mips_arch_info->name, "r10000") == 0)
15767 target_flags |= MASK_FIX_R10000;
15769 /* Make sure that branch-likely instructions available when using
15770 -mfix-r10000. The instructions are not available if either:
15772 1. -mno-branch-likely was passed.
15773 2. The selected ISA does not support branch-likely and
15774 the command line does not include -mbranch-likely. */
15775 if (TARGET_FIX_R10000
15776 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15777 ? !ISA_HAS_BRANCHLIKELY
15778 : !TARGET_BRANCHLIKELY))
15779 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15781 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15783 warning (0, "the %qs architecture does not support the synci "
15784 "instruction", mips_arch_info->name);
15785 target_flags &= ~MASK_SYNCI;
15788 /* Only optimize PIC indirect calls if they are actually required. */
15789 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15790 target_flags &= ~MASK_RELAX_PIC_CALLS;
15792 /* Save base state of options. */
15793 mips_base_target_flags = target_flags;
15794 mips_base_schedule_insns = flag_schedule_insns;
15795 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15796 mips_base_move_loop_invariants = flag_move_loop_invariants;
15797 mips_base_align_loops = align_loops;
15798 mips_base_align_jumps = align_jumps;
15799 mips_base_align_functions = align_functions;
15801 /* Now select the ISA mode.
15803 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15804 MIPS16 mode afterwards if need be. */
15805 mips_set_mips16_mode (false);
15808 /* Swap the register information for registers I and I + 1, which
15809 currently have the wrong endianness. Note that the registers'
15810 fixedness and call-clobberedness might have been set on the
15814 mips_swap_registers (unsigned int i)
15819 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15820 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15822 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15823 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15824 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15825 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15831 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
15834 mips_conditional_register_usage (void)
15839 /* These DSP control register fields are global. */
15840 global_regs[CCDSP_PO_REGNUM] = 1;
15841 global_regs[CCDSP_SC_REGNUM] = 1;
15844 AND_COMPL_HARD_REG_SET (accessible_reg_set,
15845 reg_class_contents[(int) DSP_ACC_REGS]);
15847 if (!TARGET_HARD_FLOAT)
15849 AND_COMPL_HARD_REG_SET (accessible_reg_set,
15850 reg_class_contents[(int) FP_REGS]);
15851 AND_COMPL_HARD_REG_SET (accessible_reg_set,
15852 reg_class_contents[(int) ST_REGS]);
15854 else if (!ISA_HAS_8CC)
15856 /* We only have a single condition-code register. We implement
15857 this by fixing all the condition-code registers and generating
15858 RTL that refers directly to ST_REG_FIRST. */
15859 AND_COMPL_HARD_REG_SET (accessible_reg_set,
15860 reg_class_contents[(int) ST_REGS]);
15861 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
15862 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
15866 /* In MIPS16 mode, we permit the $t temporary registers to be used
15867 for reload. We prohibit the unused $s registers, since they
15868 are call-saved, and saving them via a MIPS16 register would
15869 probably waste more time than just reloading the value. */
15870 fixed_regs[18] = call_used_regs[18] = 1;
15871 fixed_regs[19] = call_used_regs[19] = 1;
15872 fixed_regs[20] = call_used_regs[20] = 1;
15873 fixed_regs[21] = call_used_regs[21] = 1;
15874 fixed_regs[22] = call_used_regs[22] = 1;
15875 fixed_regs[23] = call_used_regs[23] = 1;
15876 fixed_regs[26] = call_used_regs[26] = 1;
15877 fixed_regs[27] = call_used_regs[27] = 1;
15878 fixed_regs[30] = call_used_regs[30] = 1;
15880 /* Do not allow HI and LO to be treated as register operands.
15881 There are no MTHI or MTLO instructions (or any real need
15882 for them) and one-way registers cannot easily be reloaded. */
15883 AND_COMPL_HARD_REG_SET (operand_reg_set,
15884 reg_class_contents[(int) MD_REGS]);
15886 /* $f20-$f23 are call-clobbered for n64. */
15887 if (mips_abi == ABI_64)
15890 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15891 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15893 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15895 if (mips_abi == ABI_N32)
15898 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15899 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15901 /* Make sure that double-register accumulator values are correctly
15902 ordered for the current endianness. */
15903 if (TARGET_LITTLE_ENDIAN)
15905 unsigned int regno;
15907 mips_swap_registers (MD_REG_FIRST);
15908 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15909 mips_swap_registers (regno);
15913 /* Initialize vector TARGET to VALS. */
15916 mips_expand_vector_init (rtx target, rtx vals)
15918 enum machine_mode mode;
15919 enum machine_mode inner;
15920 unsigned int i, n_elts;
15923 mode = GET_MODE (target);
15924 inner = GET_MODE_INNER (mode);
15925 n_elts = GET_MODE_NUNITS (mode);
15927 gcc_assert (VECTOR_MODE_P (mode));
15929 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
15930 for (i = 0; i < n_elts; i++)
15931 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
15932 XVECEXP (vals, 0, i));
15934 emit_move_insn (target, mem);
15937 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15938 other registers for instructions for which it is possible. This
15939 encourages the compiler to use CMP in cases where an XOR would
15940 require some register shuffling. */
15943 mips_order_regs_for_local_alloc (void)
15947 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15948 reg_alloc_order[i] = i;
15952 /* It really doesn't matter where we put register 0, since it is
15953 a fixed register anyhow. */
15954 reg_alloc_order[0] = 24;
15955 reg_alloc_order[24] = 0;
15959 /* Implement EH_USES. */
15962 mips_eh_uses (unsigned int regno)
15964 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
15966 /* We need to force certain registers to be live in order to handle
15967 PIC long branches correctly. See mips_must_initialize_gp_p for
15969 if (mips_cfun_has_cprestore_slot_p ())
15971 if (regno == CPRESTORE_SLOT_REGNUM)
15976 if (cfun->machine->global_pointer == regno)
15984 /* Implement EPILOGUE_USES. */
15987 mips_epilogue_uses (unsigned int regno)
15989 /* Say that the epilogue uses the return address register. Note that
15990 in the case of sibcalls, the values "used by the epilogue" are
15991 considered live at the start of the called function. */
15992 if (regno == RETURN_ADDR_REGNUM)
15995 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
15996 See the comment above load_call<mode> for details. */
15997 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16000 /* An interrupt handler must preserve some registers that are
16001 ordinarily call-clobbered. */
16002 if (cfun->machine->interrupt_handler_p
16003 && mips_interrupt_extra_call_saved_reg_p (regno))
16009 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16012 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16014 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16017 /* Return true if INSN needs to be wrapped in ".set noat".
16018 INSN has NOPERANDS operands, stored in OPVEC. */
16021 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16025 if (recog_memoized (insn) >= 0)
16026 for (i = 0; i < noperands; i++)
16027 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16032 /* Implement FINAL_PRESCAN_INSN. */
16035 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16037 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16038 mips_push_asm_switch (&mips_noat);
16041 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16044 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16045 rtx *opvec, int noperands)
16047 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16048 mips_pop_asm_switch (&mips_noat);
16051 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16052 EXT_CODE is the code of the extension used. Return NULL if widening
16053 multiplication shouldn't be used. */
16056 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16060 signed_p = ext_code == SIGN_EXTEND;
16063 /* Don't use widening multiplication with MULT when we have DMUL. Even
16064 with the extension of its input operands DMUL is faster. Note that
16065 the extension is not needed for signed multiplication. In order to
16066 ensure that we always remove the redundant sign-extension in this
16067 case we still expand mulsidi3 for DMUL. */
16069 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16072 ? gen_mulsidi3_64bit_mips16
16073 : gen_umulsidi3_64bit_mips16);
16074 if (TARGET_FIX_R4000)
16076 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16082 ? gen_mulsidi3_32bit_mips16
16083 : gen_umulsidi3_32bit_mips16);
16084 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16085 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16086 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16090 /* Return the size in bytes of the trampoline code, padded to
16091 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16092 function address immediately follow. */
16095 mips_trampoline_code_size (void)
16097 if (TARGET_USE_PIC_FN_ADDR_REG)
16099 else if (ptr_mode == DImode)
16101 else if (ISA_HAS_LOAD_DELAY)
16107 /* Implement TARGET_TRAMPOLINE_INIT. */
16110 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16112 rtx addr, end_addr, high, low, opcode, mem;
16115 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16117 /* Work out the offsets of the pointers from the start of the
16118 trampoline code. */
16119 end_addr_offset = mips_trampoline_code_size ();
16120 static_chain_offset = end_addr_offset;
16121 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16123 /* Get pointers to the beginning and end of the code block. */
16124 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16125 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16127 #define OP(X) gen_int_mode (X, SImode)
16129 /* Build up the code in TRAMPOLINE. */
16131 if (TARGET_USE_PIC_FN_ADDR_REG)
16133 /* $25 contains the address of the trampoline. Emit code of the form:
16135 l[wd] $1, target_function_offset($25)
16136 l[wd] $static_chain, static_chain_offset($25)
16139 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16140 target_function_offset,
16141 PIC_FUNCTION_ADDR_REGNUM));
16142 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16143 static_chain_offset,
16144 PIC_FUNCTION_ADDR_REGNUM));
16145 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16146 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16148 else if (ptr_mode == DImode)
16150 /* It's too cumbersome to create the full 64-bit address, so let's
16156 1: l[wd] $25, target_function_offset - 12($31)
16157 l[wd] $static_chain, static_chain_offset - 12($31)
16161 where 12 is the offset of "1:" from the start of the code block. */
16162 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16163 trampoline[i++] = OP (MIPS_BAL (1));
16164 trampoline[i++] = OP (MIPS_NOP);
16165 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16166 target_function_offset - 12,
16167 RETURN_ADDR_REGNUM));
16168 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16169 static_chain_offset - 12,
16170 RETURN_ADDR_REGNUM));
16171 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16172 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16176 /* If the target has load delays, emit:
16178 lui $1, %hi(end_addr)
16179 lw $25, %lo(end_addr + ...)($1)
16180 lw $static_chain, %lo(end_addr + ...)($1)
16186 lui $1, %hi(end_addr)
16187 lw $25, %lo(end_addr + ...)($1)
16189 lw $static_chain, %lo(end_addr + ...)($1). */
16191 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16192 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16193 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16194 NULL, false, OPTAB_WIDEN);
16195 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16196 NULL, false, OPTAB_WIDEN);
16197 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16199 /* Emit the LUI. */
16200 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16201 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16202 NULL, false, OPTAB_WIDEN);
16204 /* Emit the load of the target function. */
16205 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16206 target_function_offset - end_addr_offset,
16208 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16209 NULL, false, OPTAB_WIDEN);
16211 /* Emit the JR here, if we can. */
16212 if (!ISA_HAS_LOAD_DELAY)
16213 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16215 /* Emit the load of the static chain register. */
16216 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16217 static_chain_offset - end_addr_offset,
16219 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16220 NULL, false, OPTAB_WIDEN);
16222 /* Emit the JR, if we couldn't above. */
16223 if (ISA_HAS_LOAD_DELAY)
16225 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16226 trampoline[i++] = OP (MIPS_NOP);
16232 /* Copy the trampoline code. Leave any padding uninitialized. */
16233 for (j = 0; j < i; j++)
16235 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16236 mips_emit_move (mem, trampoline[j]);
16239 /* Set up the static chain pointer field. */
16240 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16241 mips_emit_move (mem, chain_value);
16243 /* Set up the target function field. */
16244 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16245 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16247 /* Flush the code part of the trampoline. */
16248 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16249 emit_insn (gen_clear_cache (addr, end_addr));
16252 /* Implement FUNCTION_PROFILER. */
16254 void mips_function_profiler (FILE *file)
16257 sorry ("mips16 function profiling");
16258 if (TARGET_LONG_CALLS)
16260 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16261 if (Pmode == DImode)
16262 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16264 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16266 mips_push_asm_switch (&mips_noat);
16267 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16268 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16269 /* _mcount treats $2 as the static chain register. */
16270 if (cfun->static_chain_decl != NULL)
16271 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16272 reg_names[STATIC_CHAIN_REGNUM]);
16273 if (TARGET_MCOUNT_RA_ADDRESS)
16275 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16276 ra save location. */
16277 if (cfun->machine->frame.ra_fp_offset == 0)
16278 /* ra not saved, pass zero. */
16279 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16281 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16282 Pmode == DImode ? "dla" : "la", reg_names[12],
16283 cfun->machine->frame.ra_fp_offset,
16284 reg_names[STACK_POINTER_REGNUM]);
16286 if (!TARGET_NEWABI)
16288 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16289 TARGET_64BIT ? "dsubu" : "subu",
16290 reg_names[STACK_POINTER_REGNUM],
16291 reg_names[STACK_POINTER_REGNUM],
16292 Pmode == DImode ? 16 : 8);
16294 if (TARGET_LONG_CALLS)
16295 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16297 fprintf (file, "\tjal\t_mcount\n");
16298 mips_pop_asm_switch (&mips_noat);
16299 /* _mcount treats $2 as the static chain register. */
16300 if (cfun->static_chain_decl != NULL)
16301 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16305 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16306 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16307 when TARGET_LOONGSON_VECTORS is true. */
16309 static unsigned HOST_WIDE_INT
16310 mips_shift_truncation_mask (enum machine_mode mode)
16312 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16315 return GET_MODE_BITSIZE (mode) - 1;
16319 /* Initialize the GCC target structure. */
16320 #undef TARGET_ASM_ALIGNED_HI_OP
16321 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16322 #undef TARGET_ASM_ALIGNED_SI_OP
16323 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16324 #undef TARGET_ASM_ALIGNED_DI_OP
16325 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16327 #undef TARGET_OPTION_OVERRIDE
16328 #define TARGET_OPTION_OVERRIDE mips_option_override
16330 #undef TARGET_LEGITIMIZE_ADDRESS
16331 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16333 #undef TARGET_ASM_FUNCTION_PROLOGUE
16334 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16335 #undef TARGET_ASM_FUNCTION_EPILOGUE
16336 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16337 #undef TARGET_ASM_SELECT_RTX_SECTION
16338 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16339 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16340 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16342 #undef TARGET_SCHED_INIT
16343 #define TARGET_SCHED_INIT mips_sched_init
16344 #undef TARGET_SCHED_REORDER
16345 #define TARGET_SCHED_REORDER mips_sched_reorder
16346 #undef TARGET_SCHED_REORDER2
16347 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
16348 #undef TARGET_SCHED_VARIABLE_ISSUE
16349 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16350 #undef TARGET_SCHED_ADJUST_COST
16351 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16352 #undef TARGET_SCHED_ISSUE_RATE
16353 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16354 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16355 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16356 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16357 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16358 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16359 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16360 mips_multipass_dfa_lookahead
16361 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16362 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16363 mips_small_register_classes_for_mode_p
16365 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16366 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16368 #undef TARGET_INSERT_ATTRIBUTES
16369 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16370 #undef TARGET_MERGE_DECL_ATTRIBUTES
16371 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16372 #undef TARGET_SET_CURRENT_FUNCTION
16373 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16375 #undef TARGET_VALID_POINTER_MODE
16376 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16377 #undef TARGET_REGISTER_MOVE_COST
16378 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16379 #undef TARGET_MEMORY_MOVE_COST
16380 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16381 #undef TARGET_RTX_COSTS
16382 #define TARGET_RTX_COSTS mips_rtx_costs
16383 #undef TARGET_ADDRESS_COST
16384 #define TARGET_ADDRESS_COST mips_address_cost
16386 #undef TARGET_IN_SMALL_DATA_P
16387 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16389 #undef TARGET_MACHINE_DEPENDENT_REORG
16390 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16392 #undef TARGET_PREFERRED_RELOAD_CLASS
16393 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
16395 #undef TARGET_ASM_FILE_START
16396 #define TARGET_ASM_FILE_START mips_file_start
16397 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16398 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16400 #undef TARGET_INIT_LIBFUNCS
16401 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16403 #undef TARGET_BUILD_BUILTIN_VA_LIST
16404 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16405 #undef TARGET_EXPAND_BUILTIN_VA_START
16406 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16407 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16408 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16410 #undef TARGET_PROMOTE_FUNCTION_MODE
16411 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16412 #undef TARGET_PROMOTE_PROTOTYPES
16413 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16415 #undef TARGET_FUNCTION_VALUE
16416 #define TARGET_FUNCTION_VALUE mips_function_value
16417 #undef TARGET_LIBCALL_VALUE
16418 #define TARGET_LIBCALL_VALUE mips_libcall_value
16419 #undef TARGET_FUNCTION_VALUE_REGNO_P
16420 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
16421 #undef TARGET_RETURN_IN_MEMORY
16422 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16423 #undef TARGET_RETURN_IN_MSB
16424 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16426 #undef TARGET_ASM_OUTPUT_MI_THUNK
16427 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16428 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16429 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16431 #undef TARGET_PRINT_OPERAND
16432 #define TARGET_PRINT_OPERAND mips_print_operand
16433 #undef TARGET_PRINT_OPERAND_ADDRESS
16434 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16435 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16436 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16438 #undef TARGET_SETUP_INCOMING_VARARGS
16439 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16440 #undef TARGET_STRICT_ARGUMENT_NAMING
16441 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16442 #undef TARGET_MUST_PASS_IN_STACK
16443 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16444 #undef TARGET_PASS_BY_REFERENCE
16445 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16446 #undef TARGET_CALLEE_COPIES
16447 #define TARGET_CALLEE_COPIES mips_callee_copies
16448 #undef TARGET_ARG_PARTIAL_BYTES
16449 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16450 #undef TARGET_FUNCTION_ARG
16451 #define TARGET_FUNCTION_ARG mips_function_arg
16452 #undef TARGET_FUNCTION_ARG_ADVANCE
16453 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16454 #undef TARGET_FUNCTION_ARG_BOUNDARY
16455 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
16457 #undef TARGET_MODE_REP_EXTENDED
16458 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16460 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16461 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16463 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16464 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16466 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16467 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
16469 #undef TARGET_INIT_BUILTINS
16470 #define TARGET_INIT_BUILTINS mips_init_builtins
16471 #undef TARGET_BUILTIN_DECL
16472 #define TARGET_BUILTIN_DECL mips_builtin_decl
16473 #undef TARGET_EXPAND_BUILTIN
16474 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16476 #undef TARGET_HAVE_TLS
16477 #define TARGET_HAVE_TLS HAVE_AS_TLS
16479 #undef TARGET_CANNOT_FORCE_CONST_MEM
16480 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16482 #undef TARGET_LEGITIMATE_CONSTANT_P
16483 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
16485 #undef TARGET_ENCODE_SECTION_INFO
16486 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16488 #undef TARGET_ATTRIBUTE_TABLE
16489 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16490 /* All our function attributes are related to how out-of-line copies should
16491 be compiled or called. They don't in themselves prevent inlining. */
16492 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16493 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16495 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16496 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16498 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16499 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16500 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16501 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16503 #undef TARGET_COMP_TYPE_ATTRIBUTES
16504 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16506 #ifdef HAVE_AS_DTPRELWORD
16507 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16508 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16510 #undef TARGET_DWARF_REGISTER_SPAN
16511 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16513 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16514 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16516 #undef TARGET_LEGITIMATE_ADDRESS_P
16517 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16519 #undef TARGET_FRAME_POINTER_REQUIRED
16520 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16522 #undef TARGET_CAN_ELIMINATE
16523 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16525 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16526 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
16528 #undef TARGET_TRAMPOLINE_INIT
16529 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16531 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16532 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16534 #undef TARGET_SHIFT_TRUNCATION_MASK
16535 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
16537 struct gcc_target targetm = TARGET_INITIALIZER;
16539 #include "gt-mips.h"