1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
28 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
30 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
31 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
32 #define INT_OP_NO_DOT 2 /* byte, short, long */
33 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
36 #define INT_OP_GROUP INT_OP_DOT_WORD
38 /* Names to predefine in the preprocessor for this target machine. */
40 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
42 /* Print subsidiary information on the compiler version in use. */
44 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
46 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
49 /* Run-time compilation parameters selecting different hardware subsets. */
51 extern int target_flags;
53 /* Macros used in the machine description to test the flags. */
55 /* Compile for a 68020 (not a 68000 or 68010). */
57 #define TARGET_68020 (target_flags & MASK_68020)
59 /* Compile 68881 insns for floating point (not library calls). */
61 #define TARGET_68881 (target_flags & MASK_68881)
63 /* Compile using 68020 bit-field insns. */
64 #define MASK_BITFIELD 4
65 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
67 /* Compile using rtd insn calling sequence.
68 This will not work unless you use prototypes at least
69 for all functions that can take varying numbers of args. */
71 #define TARGET_RTD (target_flags & MASK_RTD)
73 /* Compile passing first two args in regs 0 and 1.
74 This exists only to test compiler features that will
75 be needed for RISC chips. It is not usable
76 and is not intended to be usable on this cpu. */
77 #define MASK_REGPARM 16
78 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
80 /* Compile with 16-bit `int'. */
82 #define TARGET_SHORT (target_flags & MASK_SHORT)
84 /* Optimize for 68040, but still allow execution on 68020
85 (-m68020-40 or -m68040).
86 The 68040 will execute all 68030 and 68881/2 instructions, but some
87 of them must be emulated in software by the OS. When TARGET_68040 is
88 turned on, these instructions won't be used. This code will still
89 run on a 68030 and 68881/2. */
90 #define MASK_68040 256
91 #define TARGET_68040 (target_flags & MASK_68040)
93 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
94 #define MASK_68040_ONLY 512
95 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
97 /* Optimize for 68060, but still allow execution on 68020
98 (-m68020-60 or -m68060).
99 The 68060 will execute all 68030 and 68881/2 instructions, but some
100 of them must be emulated in software by the OS. When TARGET_68060 is
101 turned on, these instructions won't be used. This code will still
102 run on a 68030 and 68881/2. */
103 #define MASK_68060 1024
104 #define TARGET_68060 (target_flags & MASK_68060)
106 /* Compile for mcf5200 */
107 #define MASK_5200 2048
108 #define TARGET_5200 (target_flags & MASK_5200)
110 /* Align ints to a word boundary. This breaks compatibility with the
111 published ABI's for structures containing ints, but produces faster
112 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
113 It's required for coldfire cpus without a misalignment module. */
114 #define MASK_ALIGN_INT 4096
115 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
117 /* Compile for a CPU32 */
118 /* A 68020 without bitfields is a good heuristic for a CPU32 */
119 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
121 /* Use PC-relative addressing modes (without using a global offset table).
122 The m68000 supports 16-bit PC-relative addressing.
123 The m68020 supports 32-bit PC-relative addressing
124 (using outer displacements).
126 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
127 treated as all containing an implicit PC-relative component, and hence
128 cannot be used directly as addresses for memory writes. See the comments
129 in m68k.c for more information. */
130 #define MASK_PCREL 8192
131 #define TARGET_PCREL (target_flags & MASK_PCREL)
133 /* Relax strict alignment. */
134 #define MASK_NO_STRICT_ALIGNMENT 16384
135 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
137 /* Macro to define tables used to set the flags.
138 This is a list in braces of pairs in braces,
139 each pair being { "NAME", VALUE }
140 where VALUE is the bits to set or minus the bits to clear.
141 An empty string NAME is used to identify the default VALUE. */
143 #define TARGET_SWITCHES \
144 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
145 N_("Generate code for a 68020") }, \
146 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
147 N_("Generate code for a 68020") }, \
148 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
149 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
150 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
151 |MASK_68020|MASK_BITFIELD|MASK_68881), \
152 N_("Generate code for a 68000") }, \
153 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
154 |MASK_68020|MASK_BITFIELD|MASK_68881), \
155 N_("Generate code for a 68000") }, \
156 { "bitfield", MASK_BITFIELD, \
157 N_("Use the bit-field instructions") }, \
158 { "nobitfield", - MASK_BITFIELD, \
159 N_("Do not use the bit-field instructions") }, \
161 N_("Use different calling convention using 'rtd'") }, \
162 { "nortd", - MASK_RTD, \
163 N_("Use normal calling convention") }, \
164 { "short", MASK_SHORT, \
165 N_("Consider type `int' to be 16 bits wide") }, \
166 { "noshort", - MASK_SHORT, \
167 N_("Consider type `int' to be 32 bits wide") }, \
168 { "68881", MASK_68881, "" }, \
169 { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
170 N_("Generate code with library calls for floating point") }, \
171 { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \
172 N_("Generate code for a 68040, without any new instructions") }, \
173 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
174 { "68020-60", -(MASK_5200|MASK_68040_ONLY), \
175 N_("Generate code for a 68060, without any new instructions") }, \
176 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
177 |MASK_68060), "" }, \
178 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
179 N_("Generate code for a 68030") }, \
180 { "68030", (MASK_68020|MASK_BITFIELD), "" }, \
181 { "68040", - (MASK_5200|MASK_68060), \
182 N_("Generate code for a 68040") }, \
183 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
184 |MASK_68040_ONLY|MASK_68040), "" }, \
185 { "68060", - (MASK_5200|MASK_68040), \
186 N_("Generate code for a 68060") }, \
187 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
188 |MASK_68040_ONLY|MASK_68060), "" }, \
189 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
190 |MASK_BITFIELD|MASK_68881), \
191 N_("Generate code for a 520X") }, \
192 { "5200", (MASK_5200), "" }, \
194 N_("Generate code for a 68851") }, \
196 N_("Do no generate code for a 68851") }, \
197 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
198 |MASK_68020|MASK_BITFIELD|MASK_68881), \
199 N_("Generate code for a 68302") }, \
200 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
201 |MASK_BITFIELD|MASK_68881), \
202 N_("Generate code for a 68332") }, \
203 { "68332", MASK_68020, "" }, \
204 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
205 |MASK_BITFIELD|MASK_68881), \
206 N_("Generate code for a cpu32") }, \
207 { "cpu32", MASK_68020, "" }, \
208 { "align-int", MASK_ALIGN_INT, \
209 N_("Align variables on a 32-bit boundary") }, \
210 { "no-align-int", -MASK_ALIGN_INT, \
211 N_("Align variables on a 16-bit boundary") }, \
212 { "pcrel", MASK_PCREL, \
213 N_("Generate pc-relative code") }, \
214 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
215 N_("Do not use unaligned memory references") }, \
216 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
217 N_("Use unaligned memory references") }, \
219 { "", TARGET_DEFAULT, "" }}
220 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
222 /* This macro is similar to `TARGET_SWITCHES' but defines names of
223 command options that have values. Its definition is an
224 initializer with a subgrouping for each command option.
226 Each subgrouping contains a string constant, that defines the
227 fixed part of the option name, and the address of a variable. The
228 variable, type `char *', is set to the variable part of the given
229 option if the fixed part matches. The actual option name is made
230 by appending `-m' to the specified name. */
231 #define TARGET_OPTIONS \
232 { { "align-loops=", &m68k_align_loops_string, \
233 N_("Loop code aligned to this power of 2"), 0}, \
234 { "align-jumps=", &m68k_align_jumps_string, \
235 N_("Jump targets are aligned to this power of 2"), 0}, \
236 { "align-functions=", &m68k_align_funcs_string, \
237 N_("Function starts are aligned to this power of 2"), 0}, \
241 /* Sometimes certain combinations of command options do not make
242 sense on a particular target machine. You can define a macro
243 `OVERRIDE_OPTIONS' to take account of this. This macro, if
244 defined, is executed once just after all the command options have
247 Don't use this macro to turn on various extra optimizations for
248 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
250 #define OVERRIDE_OPTIONS override_options()
252 /* These are meant to be redefined in the host dependent files */
253 #define SUBTARGET_SWITCHES
254 #define SUBTARGET_OPTIONS
255 #define SUBTARGET_OVERRIDE_OPTIONS
257 /* target machine storage layout */
259 /* Define for XFmode extended real floating point support. */
260 #define LONG_DOUBLE_TYPE_SIZE 96
262 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
263 instructions, we get proper intermediate rounding, otherwise we
264 get extended precision results. */
265 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
267 /* Define this if most significant bit is lowest numbered
268 in instructions that operate on numbered bit-fields.
269 This is true for 68020 insns such as bfins and bfexts.
270 We make it true always by avoiding using the single-bit insns
271 except in special cases with constant bit numbers. */
272 #define BITS_BIG_ENDIAN 1
274 /* Define this if most significant byte of a word is the lowest numbered. */
275 /* That is true on the 68000. */
276 #define BYTES_BIG_ENDIAN 1
278 /* Define this if most significant word of a multiword number is the lowest
280 /* For 68000 we can decide arbitrarily
281 since there are no machine instructions for them.
282 So let's be consistent. */
283 #define WORDS_BIG_ENDIAN 1
285 /* Width of a word, in units (bytes). */
286 #define UNITS_PER_WORD 4
288 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
289 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
291 /* Boundary (in *bits*) on which stack pointer should be aligned. */
292 #define STACK_BOUNDARY 16
294 /* Allocation boundary (in *bits*) for the code of a function. */
295 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
297 /* Alignment of field after `int : 0' in a structure. */
298 #define EMPTY_FIELD_BOUNDARY 16
300 /* No data type wants to be aligned rounder than this.
301 Most published ABIs say that ints should be aligned on 16 bit
302 boundaries, but cpus with 32 bit busses get better performance
303 aligned on 32 bit boundaries. Coldfires without a misalignment
304 module require 32 bit alignment. */
305 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
307 /* Set this nonzero if move instructions will actually fail to work
308 when given unaligned data. */
309 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
311 /* Maximum power of 2 that code can be aligned to. */
312 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
314 /* Align loop starts for optimal branching. */
315 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
317 /* This is how to align an instruction for optimal branching. */
318 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
320 /* Define number of bits in most basic integer type.
321 (If undefined, default is BITS_PER_WORD). */
323 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
325 /* Define these to avoid dependence on meaning of `int'. */
327 #define WCHAR_TYPE "long int"
328 #define WCHAR_TYPE_SIZE 32
330 /* Standard register usage. */
332 /* Number of actual hardware registers.
333 The hardware registers are assigned numbers for the compiler
334 from 0 to just below FIRST_PSEUDO_REGISTER.
335 All registers that the compiler knows about must be given numbers,
336 even those that are not normally considered general registers.
337 For the 68000, we give the data registers numbers 0-7,
338 the address registers numbers 010-017,
339 and the 68881 floating point registers numbers 020-027. */
340 #define FIRST_PSEUDO_REGISTER 24
342 /* This defines the register which is used to hold the offset table for PIC. */
343 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
345 /* 1 for registers that have pervasive standard uses
346 and are not available for the register allocator.
347 On the 68000, only the stack pointer is such. */
349 #define FIXED_REGISTERS \
350 {/* Data registers. */ \
351 0, 0, 0, 0, 0, 0, 0, 0, \
353 /* Address registers. */ \
354 0, 0, 0, 0, 0, 0, 0, 1, \
356 /* Floating point registers \
358 0, 0, 0, 0, 0, 0, 0, 0 }
360 /* 1 for registers not available across function calls.
361 These must include the FIXED_REGISTERS and also any
362 registers that can be used without being saved.
363 The latter must include the registers where values are returned
364 and the register where structure-value addresses are passed.
365 Aside from that, you can include as many other registers as you like. */
366 #define CALL_USED_REGISTERS \
367 {1, 1, 0, 0, 0, 0, 0, 0, \
368 1, 1, 0, 0, 0, 0, 0, 1, \
369 1, 1, 0, 0, 0, 0, 0, 0 }
372 /* Make sure everything's fine if we *don't* have a given processor.
373 This assumes that putting a register in fixed_regs will keep the
374 compiler's mitts completely off it. We don't bother to zero it out
375 of register classes. */
377 #define CONDITIONAL_REGISTER_USAGE \
381 if (! TARGET_68881) \
383 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
384 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
385 if (TEST_HARD_REG_BIT (x, i)) \
386 fixed_regs[i] = call_used_regs[i] = 1; \
388 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
389 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
390 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
393 /* Return number of consecutive hard regs needed starting at reg REGNO
394 to hold something of mode MODE.
395 This is ordinarily the length in words of a value of mode MODE
396 but can be less for certain modes in special long registers.
398 On the 68000, ordinary registers hold 32 bits worth;
399 for the 68881 registers, a single register is always enough for
400 anything that can be stored in them at all. */
401 #define HARD_REGNO_NREGS(REGNO, MODE) \
402 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
403 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
405 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
406 On the 68000, the cpu registers can hold any mode but the 68881 registers
407 can hold only SFmode or DFmode. */
409 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
411 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
412 || ((REGNO) >= 16 && (REGNO) < 24 \
413 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
414 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
415 && GET_MODE_UNIT_SIZE (MODE) <= 12))
418 /* Value is 1 if it is a good idea to tie two pseudo registers
419 when one has mode MODE1 and one has mode MODE2.
420 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
421 for any hard reg, then this must be 0 for correct output. */
422 #define MODES_TIEABLE_P(MODE1, MODE2) \
424 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
425 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
426 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
427 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
429 /* Specify the registers used for certain standard purposes.
430 The values of these macros are register numbers. */
432 /* m68000 pc isn't overloaded on a register. */
433 /* #define PC_REGNUM */
435 /* Register to use for pushing function arguments. */
436 #define STACK_POINTER_REGNUM 15
438 /* Base register for access to local variables of the function. */
439 #define FRAME_POINTER_REGNUM 14
441 /* Value should be nonzero if functions must have frame pointers.
442 Zero means the frame pointer need not be set up (and parms
443 may be accessed via the stack pointer) in functions that seem suitable.
444 This is computed in `reload', in reload1.c. */
445 #define FRAME_POINTER_REQUIRED 0
447 /* Base register for access to arguments of the function. */
448 #define ARG_POINTER_REGNUM 14
450 /* Register in which static-chain is passed to a function. */
451 #define STATIC_CHAIN_REGNUM 8
453 /* Register in which address to store a structure value
454 is passed to a function. */
455 #define STRUCT_VALUE_REGNUM 9
457 /* Define the classes of registers for register constraints in the
458 machine description. Also define ranges of constants.
460 One of the classes must always be named ALL_REGS and include all hard regs.
461 If there is more than one class, another class must be named NO_REGS
462 and contain no registers.
464 The name GENERAL_REGS must be the name of a class (or an alias for
465 another name such as ALL_REGS). This is the class of registers
466 that is allowed by "g" or "r" in a register constraint.
467 Also, registers outside this class are allocated only when
468 instructions express preferences for them.
470 The classes must be numbered in nondecreasing order; that is,
471 a larger-numbered class must never be contained completely
472 in a smaller-numbered class.
474 For any two classes, it is very desirable that there be another
475 class that represents their union. */
477 /* The 68000 has three kinds of registers, so eight classes would be
478 a complete set. One of them is not needed. */
483 GENERAL_REGS, DATA_OR_FP_REGS,
484 ADDR_OR_FP_REGS, ALL_REGS,
487 #define N_REG_CLASSES (int) LIM_REG_CLASSES
489 /* Give names of register classes as strings for dump file. */
491 #define REG_CLASS_NAMES \
492 { "NO_REGS", "DATA_REGS", \
493 "ADDR_REGS", "FP_REGS", \
494 "GENERAL_REGS", "DATA_OR_FP_REGS", \
495 "ADDR_OR_FP_REGS", "ALL_REGS" }
497 /* Define which registers fit in which classes.
498 This is an initializer for a vector of HARD_REG_SET
499 of length N_REG_CLASSES. */
501 #define REG_CLASS_CONTENTS \
503 {0x00000000}, /* NO_REGS */ \
504 {0x000000ff}, /* DATA_REGS */ \
505 {0x0000ff00}, /* ADDR_REGS */ \
506 {0x00ff0000}, /* FP_REGS */ \
507 {0x0000ffff}, /* GENERAL_REGS */ \
508 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
509 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
510 {0x00ffffff}, /* ALL_REGS */ \
513 /* The same information, inverted:
514 Return the class number of the smallest class containing
515 reg number REGNO. This could be a conditional expression
516 or could index an array. */
518 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
520 /* The class value for index registers, and the one for base regs. */
522 #define INDEX_REG_CLASS GENERAL_REGS
523 #define BASE_REG_CLASS ADDR_REGS
525 /* Get reg_class from a letter such as appears in the machine description.
526 We do a trick here to modify the effective constraints on the
527 machine description; we zorch the constraint letters that aren't
528 appropriate for a specific target. This allows us to guarantee
529 that a specific kind of register will not be used for a given target
530 without fiddling with the register classes above. */
532 #define REG_CLASS_FROM_LETTER(C) \
533 ((C) == 'a' ? ADDR_REGS : \
534 ((C) == 'd' ? DATA_REGS : \
535 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
539 /* The letters I, J, K, L and M in a register constraint string
540 can be used to stand for particular ranges of immediate operands.
541 This macro defines what the ranges are.
542 C is the letter, and VALUE is a constant value.
543 Return 1 if VALUE is in the range specified by C.
545 For the 68000, `I' is used for the range 1 to 8
546 allowed as immediate shift counts and in addq.
547 `J' is used for the range of signed numbers that fit in 16 bits.
548 `K' is for numbers that moveq can't handle.
549 `L' is for range -8 to -1, range of values that can be added with subq.
550 `M' is for numbers that moveq+notb can't handle.
551 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
552 'O' is for 16 (for rotate using swap).
553 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
555 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
556 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
557 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
558 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
559 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
560 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
561 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
562 (C) == 'O' ? (VALUE) == 16 : \
563 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
566 * A small bit of explanation:
567 * "G" defines all of the floating constants that are *NOT* 68881
568 * constants. this is so 68881 constants get reloaded and the
571 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
572 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
574 /* A C expression that defines the optional machine-dependent constraint
575 letters that can be used to segregate specific types of operands,
576 usually memory references, for the target machine. It should return 1 if
577 VALUE corresponds to the operand type represented by the constraint letter
578 C. If C is not defined as an extra constraint, the value returned should
579 be 0 regardless of VALUE. */
581 /* Letters in the range `Q' through `U' may be defined in a
582 machine-dependent fashion to stand for arbitrary operand types.
583 The machine description macro `EXTRA_CONSTRAINT' is passed the
584 operand as its first argument and the constraint letter as its
587 `Q' means address register indirect addressing mode.
588 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
589 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
591 #define EXTRA_CONSTRAINT(OP,CODE) \
594 && GET_CODE (OP) == MEM \
595 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
596 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
597 || GET_CODE (XEXP (OP, 0)) == CONST)) \
601 && (GET_CODE (OP) == SYMBOL_REF \
602 || GET_CODE (OP) == LABEL_REF \
603 || GET_CODE (OP) == CONST)) \
606 ? (GET_CODE (OP) == MEM \
607 && GET_CODE (XEXP (OP, 0)) == REG) \
611 /* Given an rtx X being reloaded into a reg required to be
612 in class CLASS, return the class of reg to actually use.
613 In general this is just CLASS; but on some machines
614 in some cases it is preferable to use a more restrictive class.
615 On the 68000 series, use a data reg if possible when the
616 value is a constant in the range where moveq could be used
617 and we ensure that QImodes are reloaded into data regs. */
619 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
620 ((GET_CODE (X) == CONST_INT \
621 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
622 && (CLASS) != ADDR_REGS) \
624 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
626 : (GET_CODE (X) == CONST_DOUBLE \
627 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
628 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
629 ? FP_REGS : NO_REGS) \
631 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
632 || GET_CODE (X) == LABEL_REF)) \
636 /* Force QImode output reloads from subregs to be allocated to data regs,
637 since QImode stores from address regs are not supported. We make the
638 assumption that if the class is not ADDR_REGS, then it must be a superset
641 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
642 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
646 /* Return the maximum number of consecutive registers
647 needed to represent mode MODE in a register of class CLASS. */
648 /* On the 68000, this is the size of MODE in words,
649 except in the FP regs, where a single reg is always enough. */
650 #define CLASS_MAX_NREGS(CLASS, MODE) \
651 ((CLASS) == FP_REGS ? 1 \
652 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
654 /* Moves between fp regs and other regs are two insns. */
655 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
656 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
657 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
660 /* Stack layout; function entry, exit and calling. */
662 /* Define this if pushing a word on the stack
663 makes the stack pointer a smaller address. */
664 #define STACK_GROWS_DOWNWARD
666 /* Nonzero if we need to generate stack-probe insns.
667 On most systems they are not needed.
668 When they are needed, define this as the stack offset to probe at. */
671 /* Define this if the nominal address of the stack frame
672 is at the high-address end of the local variables;
673 that is, each additional local variable allocated
674 goes at a more negative offset in the frame. */
675 #define FRAME_GROWS_DOWNWARD
677 /* Offset within stack frame to start allocating local variables at.
678 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
679 first local allocated. Otherwise, it is the offset to the BEGINNING
680 of the first local allocated. */
681 #define STARTING_FRAME_OFFSET 0
683 /* If we generate an insn to push BYTES bytes,
684 this says how many the stack pointer really advances by.
685 On the 68000, sp@- in a byte insn really pushes a word.
686 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
687 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
689 /* We want to avoid trying to push bytes. */
690 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
691 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
692 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200)))
694 /* Offset of first parameter from the argument pointer register value. */
695 #define FIRST_PARM_OFFSET(FNDECL) 8
697 /* Value is the number of byte of arguments automatically
698 popped when returning from a subroutine call.
699 FUNDECL is the declaration node of the function (as a tree),
700 FUNTYPE is the data type of the function (as a tree),
701 or for a library call it is an identifier node for the subroutine name.
702 SIZE is the number of bytes of arguments passed on the stack.
704 On the 68000, the RTS insn cannot pop anything.
705 On the 68010, the RTD insn may be used to pop them if the number
706 of args is fixed, but if the number is variable then the caller
707 must pop them all. RTD can't be used for library calls now
708 because the library is compiled with the Unix compiler.
709 Use of RTD is a selectable option, since it is incompatible with
710 standard Unix calling sequences. If the option is not selected,
711 the caller must always pop the args. */
713 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
714 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
715 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
716 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
717 == void_type_node))) \
720 /* Define how to find the value returned by a function.
721 VALTYPE is the data type of the value (as a tree).
722 If the precise function being called is known, FUNC is its FUNCTION_DECL;
723 otherwise, FUNC is 0. */
725 /* On the 68000 the return value is in D0 regardless. */
727 #define FUNCTION_VALUE(VALTYPE, FUNC) \
728 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
730 /* Define how to find the value returned by a library function
731 assuming the value has mode MODE. */
733 /* On the 68000 the return value is in D0 regardless. */
735 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
737 /* 1 if N is a possible register number for a function value.
738 On the 68000, d0 is the only register thus used. */
740 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
742 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
743 more than one register. */
745 #define NEEDS_UNTYPED_CALL 0
747 /* Define this if PCC uses the nonreentrant convention for returning
748 structure and union values. */
750 #define PCC_STATIC_STRUCT_RETURN
752 /* 1 if N is a possible register number for function argument passing.
753 On the 68000, no registers are used in this way. */
755 #define FUNCTION_ARG_REGNO_P(N) 0
757 /* Define a data type for recording info about an argument list
758 during the scan of that argument list. This data type should
759 hold all necessary information about the function itself
760 and about the args processed so far, enough to enable macros
761 such as FUNCTION_ARG to determine where the next arg should go.
763 On the m68k, this is a single integer, which is a number of bytes
764 of arguments scanned so far. */
766 #define CUMULATIVE_ARGS int
768 /* Initialize a variable CUM of type CUMULATIVE_ARGS
769 for a call to a function whose data type is FNTYPE.
770 For a library call, FNTYPE is 0.
772 On the m68k, the offset starts at 0. */
774 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
777 /* Update the data in CUM to advance over an argument
778 of mode MODE and data type TYPE.
779 (TYPE is null for libcalls where that information may not be available.) */
781 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
782 ((CUM) += ((MODE) != BLKmode \
783 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
784 : (int_size_in_bytes (TYPE) + 3) & ~3))
786 /* Define where to put the arguments to a function.
787 Value is zero to push the argument on the stack,
788 or a hard register in which to store the argument.
790 MODE is the argument's machine mode.
791 TYPE is the data type of the argument (as a tree).
792 This is null for libcalls where that information may
794 CUM is a variable of type CUMULATIVE_ARGS which gives info about
795 the preceding args and about the function being called.
796 NAMED is nonzero if this argument is a named parameter
797 (otherwise it is an extra parameter matching an ellipsis). */
799 /* On the 68000 all args are pushed, except if -mregparm is specified
800 then the first two words of arguments are passed in d0, d1.
801 *NOTE* -mregparm does not work.
802 It exists only to test register calling conventions. */
804 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
805 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
807 /* For an arg passed partly in registers and partly in memory,
808 this is the number of registers used.
809 For args passed entirely in registers or entirely in memory, zero. */
811 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
812 ((TARGET_REGPARM && (CUM) < 8 \
813 && 8 < ((CUM) + ((MODE) == BLKmode \
814 ? int_size_in_bytes (TYPE) \
815 : GET_MODE_SIZE (MODE)))) \
818 /* Output assembler code to FILE to increment profiler label # LABELNO
819 for profiling a function entry. */
821 #define FUNCTION_PROFILER(FILE, LABELNO) \
822 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
824 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
825 the stack pointer does not matter. The value is tested only in
826 functions that have frame pointers.
827 No definition is equivalent to always zero. */
829 #define EXIT_IGNORE_STACK 1
831 /* This is a hook for other tm files to change. */
832 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
834 /* Determine if the epilogue should be output as RTL.
835 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
836 #define USE_RETURN_INSN use_return_insn ()
838 /* Store in the variable DEPTH the initial difference between the
839 frame pointer reg contents and the stack pointer reg contents,
840 as of the start of the function body. This depends on the layout
841 of the fixed parts of the stack frame and on how registers are saved.
843 On the 68k, if we have a frame, we must add one word to its length
844 to allow for the place that a6 is stored when we do have a frame pointer.
845 Otherwise, we would need to compute the offset from the frame pointer
846 of a local variable as a function of frame_pointer_needed, which
849 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
852 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
853 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
855 for (regno = 0; regno < 16; regno++) \
856 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
858 if (flag_pic && current_function_uses_pic_offset_table) \
860 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
861 + (get_frame_size () == 0 ? 0 : 4)); \
864 /* Output assembler code for a block containing the constant parts
865 of a trampoline, leaving space for the variable parts. */
867 /* On the 68k, the trampoline looks like this:
871 WARNING: Targets that may run on 68040+ cpus must arrange for
872 the instruction cache to be flushed. Previous incarnations of
873 the m68k trampoline code attempted to get around this by either
874 using an out-of-line transfer function or pc-relative data, but
875 the fact remains that the code to jump to the transfer function
876 or the code to load the pc-relative data needs to be flushed
877 just as much as the "variable" portion of the trampoline.
878 Recognizing that a cache flush is going to be required anyway,
879 dispense with such notions and build a smaller trampoline. */
881 /* Since more instructions are required to move a template into
882 place than to create it on the spot, don't use a template. */
884 /* Length in units of the trampoline for entering a nested function. */
886 #define TRAMPOLINE_SIZE 12
888 /* Alignment required for a trampoline in bits. */
890 #define TRAMPOLINE_ALIGNMENT 16
892 /* Targets redefine this to invoke code to either flush the cache,
893 or enable stack execution (or both). */
895 #ifndef FINALIZE_TRAMPOLINE
896 #define FINALIZE_TRAMPOLINE(TRAMP)
899 /* Emit RTL insns to initialize the variable parts of a trampoline.
900 FNADDR is an RTX for the address of the function's pure code.
901 CXT is an RTX for the static chain value for the function.
903 We generate a two-instructions program at address TRAMP :
907 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
909 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
910 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
911 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
913 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
914 FINALIZE_TRAMPOLINE(TRAMP); \
917 /* This is the library routine that is used
918 to transfer control from the trampoline
919 to the actual nested function.
920 It is defined for backward compatibility,
921 for linking with object code that used the old
922 trampoline definition. */
924 /* A colon is used with no explicit operands
925 to cause the template string to be scanned for %-constructs. */
926 /* The function name __transfer_from_trampoline is not actually used.
927 The function definition just permits use of "asm with operands"
928 (though the operand list is empty). */
929 #define TRANSFER_FROM_TRAMPOLINE \
931 __transfer_from_trampoline () \
933 register char *a0 asm ("%a0"); \
934 asm (GLOBAL_ASM_OP "___trampoline"); \
935 asm ("___trampoline:"); \
936 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
937 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
941 /* Addressing modes, and classification of registers for them. */
943 #define HAVE_POST_INCREMENT 1
945 #define HAVE_PRE_DECREMENT 1
947 /* Macros to check register numbers against specific register classes. */
949 /* These assume that REGNO is a hard or pseudo reg number.
950 They give nonzero only if REGNO is a hard reg of the suitable class
951 or a pseudo reg currently allocated to a suitable hard reg.
952 Since they use reg_renumber, they are safe only once reg_renumber
953 has been allocated, which happens in local-alloc.c. */
955 #define REGNO_OK_FOR_INDEX_P(REGNO) \
956 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
957 #define REGNO_OK_FOR_BASE_P(REGNO) \
958 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
959 #define REGNO_OK_FOR_DATA_P(REGNO) \
960 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
961 #define REGNO_OK_FOR_FP_P(REGNO) \
962 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
964 /* Now macros that check whether X is a register and also,
965 strictly, whether it is in a specified class.
967 These macros are specific to the 68000, and may be used only
968 in code for printing assembler insns and in conditions for
969 define_optimization. */
971 /* 1 if X is a data register. */
973 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
975 /* 1 if X is an fp register. */
977 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
979 /* 1 if X is an address register */
981 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
983 /* Maximum number of registers that can appear in a valid memory address. */
985 #define MAX_REGS_PER_ADDRESS 2
987 /* Recognize any constant value that is a valid address. */
989 #define CONSTANT_ADDRESS_P(X) \
990 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
991 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
992 || GET_CODE (X) == HIGH)
994 /* Nonzero if the constant value X is a legitimate general operand.
995 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
997 #define LEGITIMATE_CONSTANT_P(X) 1
999 /* Nonzero if the constant value X is a legitimate general operand
1000 when generating PIC code. It is given that flag_pic is on and
1001 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1003 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1004 accepted by insn predicates, but which would otherwise fail the
1005 `general_operand' test. */
1007 #ifndef REG_OK_STRICT
1008 #define PCREL_GENERAL_OPERAND_OK 0
1010 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1013 #define LEGITIMATE_PIC_OPERAND_P(X) \
1014 ((! symbolic_operand (X, VOIDmode) \
1015 && ! (GET_CODE (X) == CONST_DOUBLE && mem_for_const_double (X) != 0 \
1016 && GET_CODE (mem_for_const_double (X)) == MEM \
1017 && symbolic_operand (XEXP (mem_for_const_double (X), 0), \
1019 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1020 || PCREL_GENERAL_OPERAND_OK)
1022 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1023 and check its validity for a certain class.
1024 We have two alternate definitions for each of them.
1025 The usual definition accepts all pseudo regs; the other rejects
1026 them unless they have been allocated suitable hard regs.
1027 The symbol REG_OK_STRICT causes the latter definition to be used.
1029 Most source files want to accept pseudo regs in the hope that
1030 they will get allocated to the class that the insn wants them to be in.
1031 Source files for reload pass need to be strict.
1032 After reload, it makes no difference, since pseudo regs have
1033 been eliminated by then. */
1035 #ifndef REG_OK_STRICT
1037 /* Nonzero if X is a hard reg that can be used as an index
1038 or if it is a pseudo reg. */
1039 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1040 /* Nonzero if X is a hard reg that can be used as a base reg
1041 or if it is a pseudo reg. */
1042 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1046 /* Nonzero if X is a hard reg that can be used as an index. */
1047 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1048 /* Nonzero if X is a hard reg that can be used as a base reg. */
1049 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1053 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1054 that is a valid memory address for an instruction.
1055 The MODE argument is the machine mode for the MEM expression
1056 that wants to use this address.
1058 When generating PIC, an address involving a SYMBOL_REF is legitimate
1059 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1060 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1061 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1063 Likewise for a LABEL_REF when generating PIC.
1065 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1067 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1068 also makes function inlining work when inline functions are called with
1069 arguments that are SUBREGs. */
1071 #define LEGITIMATE_BASE_REG_P(X) \
1072 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1073 || (GET_CODE (X) == SUBREG \
1074 && GET_CODE (SUBREG_REG (X)) == REG \
1075 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1077 #define INDIRECTABLE_1_ADDRESS_P(X) \
1078 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1079 || LEGITIMATE_BASE_REG_P (X) \
1080 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1081 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1082 || (GET_CODE (X) == PLUS \
1083 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1084 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1086 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1087 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1088 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1089 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1090 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1092 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1093 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1095 /* Only labels on dispatch tables are valid for indexing from. */
1096 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1098 if (GET_CODE (X) == LABEL_REF \
1099 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1100 && GET_CODE (temp) == JUMP_INSN \
1101 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1102 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1104 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1106 #define GO_IF_INDEXING(X, ADDR) \
1107 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1108 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1109 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1110 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1112 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1113 { GO_IF_INDEXING (X, ADDR); \
1114 if (GET_CODE (X) == PLUS) \
1115 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1116 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1117 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1118 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1119 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1120 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1122 /* coldfire/5200 does not allow HImode index registers. */
1123 #define LEGITIMATE_INDEX_REG_P(X) \
1124 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1126 && GET_CODE (X) == SIGN_EXTEND \
1127 && GET_CODE (XEXP (X, 0)) == REG \
1128 && GET_MODE (XEXP (X, 0)) == HImode \
1129 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1130 || (GET_CODE (X) == SUBREG \
1131 && GET_CODE (SUBREG_REG (X)) == REG \
1132 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1134 #define LEGITIMATE_INDEX_P(X) \
1135 (LEGITIMATE_INDEX_REG_P (X) \
1136 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1137 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1138 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1139 && (INTVAL (XEXP (X, 1)) == 2 \
1140 || INTVAL (XEXP (X, 1)) == 4 \
1141 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1143 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1144 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1145 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1146 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1147 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1148 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1149 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1152 /* Don't call memory_address_noforce for the address to fetch
1153 the switch offset. This address is ok as it stands (see above),
1154 but memory_address_noforce would alter it. */
1155 #define PIC_CASE_VECTOR_ADDRESS(index) index
1157 /* Try machine-dependent ways of modifying an illegitimate address
1158 to be legitimate. If we find one, return the new, valid address.
1159 This macro is used in only one place: `memory_address' in explow.c.
1161 OLDX is the address as it was before break_out_memory_refs was called.
1162 In some cases it is useful to look at this to decide what needs to be done.
1164 MODE and WIN are passed so that this macro can use
1165 GO_IF_LEGITIMATE_ADDRESS.
1167 It is always safe for this macro to do nothing. It exists to recognize
1168 opportunities to optimize the output.
1170 For the 68000, we handle X+REG by loading X into a register R and
1171 using R+REG. R will go in an address reg and indexing will be used.
1172 However, if REG is a broken-out memory address or multiplication,
1173 nothing needs to be done because REG can certainly go in an address reg. */
1175 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1176 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1177 { register int ch = (X) != (OLDX); \
1178 if (GET_CODE (X) == PLUS) \
1180 if (GET_CODE (XEXP (X, 0)) == MULT) \
1181 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1182 if (GET_CODE (XEXP (X, 1)) == MULT) \
1183 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1184 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1185 && GET_CODE (XEXP (X, 0)) == REG) \
1187 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1188 if (GET_CODE (XEXP (X, 0)) == REG \
1189 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1190 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1191 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1192 { register rtx temp = gen_reg_rtx (Pmode); \
1193 register rtx val = force_operand (XEXP (X, 1), 0); \
1194 emit_move_insn (temp, val); \
1196 XEXP (X, 1) = temp; \
1198 else if (GET_CODE (XEXP (X, 1)) == REG \
1199 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1200 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1201 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1202 { register rtx temp = gen_reg_rtx (Pmode); \
1203 register rtx val = force_operand (XEXP (X, 0), 0); \
1204 emit_move_insn (temp, val); \
1206 XEXP (X, 0) = temp; \
1209 /* Go to LABEL if ADDR (a legitimate address expression)
1210 has an effect that depends on the machine mode it is used for.
1211 On the 68000, only predecrement and postincrement address depend thus
1212 (the amount of decrement or increment being the length of the operand). */
1214 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1215 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1217 /* Specify the machine mode that this machine uses
1218 for the index in the tablejump instruction. */
1219 #define CASE_VECTOR_MODE HImode
1221 /* Define as C expression which evaluates to nonzero if the tablejump
1222 instruction expects the table to contain offsets from the address of the
1224 Do not define this if the table should contain absolute addresses. */
1225 #define CASE_VECTOR_PC_RELATIVE 1
1227 /* Define this as 1 if `char' should by default be signed; else as 0. */
1228 #define DEFAULT_SIGNED_CHAR 1
1230 /* Don't cse the address of the function being compiled. */
1231 #define NO_RECURSIVE_FUNCTION_CSE
1233 /* Max number of bytes we can move from memory to memory
1234 in one reasonably fast instruction. */
1237 /* Nonzero if access to memory by bytes is slow and undesirable. */
1238 #define SLOW_BYTE_ACCESS 0
1240 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1241 is done just by pretending it is already truncated. */
1242 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1244 /* We assume that the store-condition-codes instructions store 0 for false
1245 and some other value for true. This is the value stored for true. */
1247 #define STORE_FLAG_VALUE (-1)
1249 /* When a prototype says `char' or `short', really pass an `int'. */
1250 #define PROMOTE_PROTOTYPES 1
1252 /* Specify the machine mode that pointers have.
1253 After generation of rtl, the compiler makes no further distinction
1254 between pointers and any other objects of this machine mode. */
1255 #define Pmode SImode
1257 /* A function address in a call instruction
1258 is a byte address (for indexing purposes)
1259 so give the MEM rtx a byte's mode. */
1260 #define FUNCTION_MODE QImode
1263 /* Tell final.c how to eliminate redundant test instructions. */
1265 /* Here we define machine-dependent flags and fields in cc_status
1266 (see `conditions.h'). */
1268 /* Set if the cc value is actually in the 68881, so a floating point
1269 conditional branch must be output. */
1270 #define CC_IN_68881 04000
1272 /* Store in cc_status the expressions that the condition codes will
1273 describe after execution of an instruction whose pattern is EXP.
1274 Do not alter them if the instruction would not alter the cc's. */
1276 /* On the 68000, all the insns to store in an address register fail to
1277 set the cc's. However, in some cases these instructions can make it
1278 possibly invalid to use the saved cc's. In those cases we clear out
1279 some or all of the saved cc's so they won't be used. */
1281 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1283 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1284 { if (cc_prev_status.flags & CC_IN_68881) \
1286 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1290 /* Control the assembler format that we output. */
1292 /* Output at beginning of assembler file. */
1294 #define ASM_FILE_START(FILE) \
1295 fprintf (FILE, "#NO_APP\n");
1297 /* Output to assembler file text saying following lines
1298 may contain character constants, extra white space, comments, etc. */
1300 #define ASM_APP_ON "#APP\n"
1302 /* Output to assembler file text saying following lines
1303 no longer contain unusual constructs. */
1305 #define ASM_APP_OFF "#NO_APP\n"
1307 /* Output before read-only data. */
1309 #define TEXT_SECTION_ASM_OP "\t.text"
1311 /* Output before writable data. */
1313 #define DATA_SECTION_ASM_OP "\t.data"
1315 #define GLOBAL_ASM_OP "\t.globl\t"
1317 /* Here are four prefixes that are used by asm_fprintf to
1318 facilitate customization for alternate assembler syntaxes.
1319 Machines with no likelihood of an alternate syntax need not
1320 define these and need not use asm_fprintf. */
1322 /* The prefix for register names. Note that REGISTER_NAMES
1323 is supposed to include this prefix. */
1325 #define REGISTER_PREFIX ""
1327 /* The prefix for local labels. You should be able to define this as
1328 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1329 without having to make any other changes to account for the specific
1330 definition. Note it is a string literal, not interpreted by printf
1333 #define LOCAL_LABEL_PREFIX ""
1335 /* The prefix to add to user-visible assembler symbols. */
1337 #define USER_LABEL_PREFIX "_"
1339 /* The prefix for immediate operands. */
1341 #define IMMEDIATE_PREFIX "#"
1343 /* How to refer to registers in assembler output.
1344 This sequence is indexed by compiler's hard-register-number (see above). */
1346 #define REGISTER_NAMES \
1347 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1348 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1349 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1351 /* How to renumber registers for dbx and gdb.
1352 On the Sun-3, the floating point registers have numbers
1353 18 to 25, not 16 to 23 as they do in the compiler. */
1355 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1357 /* Before the prologue, RA is at 0(%sp). */
1358 #define INCOMING_RETURN_ADDR_RTX \
1359 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1361 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1362 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1363 Instead use the identity mapping. */
1364 #define DWARF_FRAME_REGNUM(REG) REG
1366 /* Before the prologue, the top of the frame is at 4(%sp). */
1367 #define INCOMING_FRAME_SP_OFFSET 4
1369 /* Describe how we implement __builtin_eh_return. */
1370 #define EH_RETURN_DATA_REGNO(N) \
1371 ((N) < 2 ? (N) : INVALID_REGNUM)
1372 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1373 #define EH_RETURN_HANDLER_RTX \
1374 gen_rtx_MEM (Pmode, \
1375 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1376 plus_constant (EH_RETURN_STACKADJ_RTX, \
1379 /* Select a format to encode pointers in exception handling data. CODE
1380 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1381 true if the symbol may be affected by dynamic relocations. */
1382 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1384 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1387 /* This is how to output a reference to a user-level label named NAME.
1388 `assemble_name' uses this. */
1390 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1391 asm_fprintf (FILE, "%0U%s", NAME)
1393 /* This is how to store into the string LABEL
1394 the symbol_ref name of an internal numbered label where
1395 PREFIX is the class of label and NUM is the number within the class.
1396 This is suitable for output with `assemble_name'. */
1398 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1399 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1401 /* This is how to output an insn to push a register on the stack.
1402 It need not be very fast code. */
1404 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1405 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1407 /* This is how to output an insn to pop a register from the stack.
1408 It need not be very fast code. */
1410 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1411 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1413 /* This is how to output an element of a case-vector that is absolute.
1414 (The 68000 does not use such vectors,
1415 but we must define this macro anyway.) */
1417 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1418 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1420 /* This is how to output an element of a case-vector that is relative. */
1422 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1423 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1425 /* This is how to output an assembler line
1426 that says to advance the location counter
1427 to a multiple of 2**LOG bytes. */
1429 /* We don't have a way to align to more than a two-byte boundary, so do the
1430 best we can and don't complain. */
1431 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1433 fprintf (FILE, "\t.even\n");
1435 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1436 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1438 /* This says how to output an assembler line
1439 to define a global common symbol. */
1441 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1442 ( fputs (".comm ", (FILE)), \
1443 assemble_name ((FILE), (NAME)), \
1444 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1446 /* This says how to output an assembler line
1447 to define a local common symbol. */
1449 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1450 ( fputs (".lcomm ", (FILE)), \
1451 assemble_name ((FILE), (NAME)), \
1452 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1454 /* Output a float value (represented as a C double) as an immediate operand.
1455 This macro is a 68k-specific macro. */
1457 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1462 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1463 asm_fprintf ((FILE), "%I0r%s", dstr); \
1468 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1469 asm_fprintf ((FILE), "%I0x%lx", l); \
1473 /* Output a double value (represented as a C double) as an immediate operand.
1474 This macro is a 68k-specific macro. */
1475 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1476 do { char dstr[30]; \
1477 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1478 asm_fprintf (FILE, "%I0r%s", dstr); \
1481 /* Note, long double immediate operands are not actually
1482 generated by m68k.md. */
1483 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1484 do { char dstr[30]; \
1485 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1486 asm_fprintf (FILE, "%I0r%s", dstr); \
1489 /* Print operand X (an rtx) in assembler syntax to file FILE.
1490 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1491 For `%' followed by punctuation, CODE is the punctuation and X is null.
1493 On the 68000, we use several CODE characters:
1494 '.' for dot needed in Motorola-style opcode names.
1495 '-' for an operand pushing on the stack:
1496 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1497 '+' for an operand pushing on the stack:
1498 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1499 '@' for a reference to the top word on the stack:
1500 sp@, (sp) or (%sp) depending on the style of syntax.
1501 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1502 but & in SGS syntax).
1503 '!' for the fpcr register (used in some float-to-fixed conversions).
1504 '$' for the letter `s' in an op code, but only on the 68040.
1505 '&' for the letter `d' in an op code, but only on the 68040.
1506 '/' for register prefix needed by longlong.h.
1508 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1509 'd' to force memory addressing to be absolute, not relative.
1510 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1511 'o' for operands to go directly to output_operand_address (bypassing
1512 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1513 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1514 or print pair of registers as rx:ry. */
1516 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1517 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1518 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1519 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1521 /* A C compound statement to output to stdio stream STREAM the
1522 assembler syntax for an instruction operand X. X is an RTL
1525 CODE is a value that can be used to specify one of several ways
1526 of printing the operand. It is used when identical operands
1527 must be printed differently depending on the context. CODE
1528 comes from the `%' specification that was used to request
1529 printing of the operand. If the specification was just `%DIGIT'
1530 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1531 is the ASCII code for LTR.
1533 If X is a register, this macro should print the register's name.
1534 The names can be found in an array `reg_names' whose type is
1535 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1537 When the machine description has a specification `%PUNCT' (a `%'
1538 followed by a punctuation character), this macro is called with
1539 a null pointer for X and the punctuation character for CODE.
1541 See m68k.c for the m68k specific codes. */
1543 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1545 /* A C compound statement to output to stdio stream STREAM the
1546 assembler syntax for an instruction operand that is a memory
1547 reference whose address is ADDR. ADDR is an RTL expression. */
1549 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1551 /* Variables in m68k.c */
1552 extern const char *m68k_align_loops_string;
1553 extern const char *m68k_align_jumps_string;
1554 extern const char *m68k_align_funcs_string;
1555 extern int m68k_align_loops;
1556 extern int m68k_align_jumps;
1557 extern int m68k_align_funcs;
1558 extern int m68k_last_compare_had_fp_operands;
1561 /* Define the codes that are matched by predicates in m68k.c. */
1563 #define PREDICATE_CODES \
1564 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1565 LABEL_REF, SUBREG, REG, MEM}}, \
1566 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1567 {"memory_src_operand", {SUBREG, MEM}}, \
1568 {"not_sp_operand", {SUBREG, REG, MEM}}, \
1569 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \
1570 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \
1571 {"const_sint32_operand", {CONST_INT}}, \
1572 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
1574 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},