1 /* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
2 Copyright (C) 1987, 88, 93-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Note that some other tm.h files include this one and then override
23 many of the definitions that relate to assembler syntax. */
26 /* Names to predefine in the preprocessor for this target machine. */
28 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
30 /* Print subsidiary information on the compiler version in use. */
32 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
34 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
37 /* Define SUPPORT_SUN_FPA to include support for generating code for
38 the Sun Floating Point Accelerator, an optional product for Sun 3
39 machines. By default, it is not defined. Avoid defining it unless
40 you need to output code for the Sun3+FPA architecture, as it has the
41 effect of slowing down the register set operations in hard-reg-set.h
42 (total number of registers will exceed number of bits in a long,
43 if defined, causing the set operations to expand to loops).
44 SUPPORT_SUN_FPA is typically defined in sun3.h. */
46 /* Run-time compilation parameters selecting different hardware subsets. */
48 extern int target_flags;
50 /* Macros used in the machine description to test the flags. */
52 /* Compile for a 68020 (not a 68000 or 68010). */
54 #define TARGET_68020 (target_flags & MASK_68020)
56 /* Compile 68881 insns for floating point (not library calls). */
58 #define TARGET_68881 (target_flags & MASK_68881)
60 /* Compile using 68020 bitfield insns. */
61 #define MASK_BITFIELD 4
62 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
64 /* Compile using rtd insn calling sequence.
65 This will not work unless you use prototypes at least
66 for all functions that can take varying numbers of args. */
68 #define TARGET_RTD (target_flags & MASK_RTD)
70 /* Compile passing first two args in regs 0 and 1.
71 This exists only to test compiler features that will
72 be needed for RISC chips. It is not usable
73 and is not intended to be usable on this cpu. */
74 #define MASK_REGPARM 16
75 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
77 /* Compile with 16-bit `int'. */
79 #define TARGET_SHORT (target_flags & MASK_SHORT)
81 /* Compile with special insns for Sun FPA. */
83 #define TARGET_FPA (target_flags & MASK_FPA)
85 /* Compile (actually, link) for Sun SKY board. */
87 #define TARGET_SKY (target_flags & MASK_SKY)
89 /* Optimize for 68040, but still allow execution on 68020
90 (-m68020-40 or -m68040).
91 The 68040 will execute all 68030 and 68881/2 instructions, but some
92 of them must be emulated in software by the OS. When TARGET_68040 is
93 turned on, these instructions won't be used. This code will still
94 run on a 68030 and 68881/2. */
95 #define MASK_68040 256
96 #define TARGET_68040 (target_flags & MASK_68040)
98 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
99 #define MASK_68040_ONLY 512
100 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
102 /* Optimize for 68060, but still allow execution on 68020
103 (-m68020-60 or -m68060).
104 The 68060 will execute all 68030 and 68881/2 instructions, but some
105 of them must be emulated in software by the OS. When TARGET_68060 is
106 turned on, these instructions won't be used. This code will still
107 run on a 68030 and 68881/2. */
108 #define MASK_68060 1024
109 #define TARGET_68060 (target_flags & MASK_68060)
111 /* Compile for mcf5200 */
112 #define MASK_5200 2048
113 #define TARGET_5200 (target_flags & MASK_5200)
115 /* Align ints to a word boundary. This breaks compatibility with the
116 published ABI's for structures containing ints, but produces faster
117 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
118 It's required for coldfire cpus without a misalignment module. */
119 #define MASK_ALIGN_INT 4096
120 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
122 /* Compile for a CPU32 */
123 /* A 68020 without bitfields is a good heuristic for a CPU32 */
124 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
126 /* Use PC-relative addressing modes (without using a global offset table).
127 The m68000 supports 16-bit PC-relative addressing.
128 The m68020 supports 32-bit PC-relative addressing
129 (using outer displacements).
131 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
132 treated as all containing an implicit PC-relative component, and hence
133 cannot be used directly as addresses for memory writes. See the comments
134 in m68k.c for more information. */
135 #define MASK_PCREL 4096
136 #define TARGET_PCREL (target_flags & MASK_PCREL)
138 /* Macro to define tables used to set the flags.
139 This is a list in braces of pairs in braces,
140 each pair being { "NAME", VALUE }
141 where VALUE is the bits to set or minus the bits to clear.
142 An empty string NAME is used to identify the default VALUE. */
144 #define TARGET_SWITCHES \
145 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
146 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
147 { "68020", (MASK_68020|MASK_BITFIELD)}, \
148 { "c68020", (MASK_68020|MASK_BITFIELD)}, \
149 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
150 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
151 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
152 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
153 { "bitfield", MASK_BITFIELD}, \
154 { "nobitfield", - MASK_BITFIELD}, \
155 { "rtd", MASK_RTD}, \
156 { "nortd", - MASK_RTD}, \
157 { "short", MASK_SHORT}, \
158 { "noshort", - MASK_SHORT}, \
159 { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \
160 { "fpa", MASK_FPA}, \
161 { "nofpa", - MASK_FPA}, \
162 { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881)}, \
163 { "sky", MASK_SKY}, \
164 { "nosky", - MASK_SKY}, \
165 { "68881", - (MASK_FPA|MASK_SKY)}, \
166 { "68881", MASK_68881}, \
167 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \
168 { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY)}, \
169 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040)}, \
170 { "68020-60", -(MASK_5200|MASK_68040_ONLY)}, \
171 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
173 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
174 { "68030", (MASK_68020|MASK_BITFIELD)}, \
175 { "68040", - (MASK_5200|MASK_68060)}, \
176 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
177 |MASK_68040_ONLY|MASK_68040)}, \
178 { "68060", - (MASK_5200|MASK_68040)}, \
179 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
180 |MASK_68040_ONLY|MASK_68060)}, \
181 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
182 |MASK_BITFIELD|MASK_68881)}, \
183 { "5200", (MASK_5200)}, \
186 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
187 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
188 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
189 |MASK_BITFIELD|MASK_68881)}, \
190 { "68332", MASK_68020}, \
191 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
192 |MASK_BITFIELD|MASK_68881)}, \
193 { "cpu32", MASK_68020}, \
194 { "align-int", MASK_ALIGN_INT }, \
195 { "no-align-int", -MASK_ALIGN_INT }, \
196 { "pcrel", MASK_PCREL}, \
198 { "", TARGET_DEFAULT}}
199 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
201 /* This macro is similar to `TARGET_SWITCHES' but defines names of
202 command options that have values. Its definition is an
203 initializer with a subgrouping for each command option.
205 Each subgrouping contains a string constant, that defines the
206 fixed part of the option name, and the address of a variable. The
207 variable, type `char *', is set to the variable part of the given
208 option if the fixed part matches. The actual option name is made
209 by appending `-m' to the specified name. */
210 #define TARGET_OPTIONS \
211 { { "align-loops=", &m68k_align_loops_string }, \
212 { "align-jumps=", &m68k_align_jumps_string }, \
213 { "align-functions=", &m68k_align_funcs_string }, \
217 /* Sometimes certain combinations of command options do not make
218 sense on a particular target machine. You can define a macro
219 `OVERRIDE_OPTIONS' to take account of this. This macro, if
220 defined, is executed once just after all the command options have
223 Don't use this macro to turn on various extra optimizations for
224 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
226 #define OVERRIDE_OPTIONS \
228 override_options(); \
229 if (! TARGET_68020 && flag_pic == 2) \
230 error("-fPIC is not currently supported on the 68000 or 68010\n"); \
231 if (TARGET_PCREL && flag_pic == 0) \
233 SUBTARGET_OVERRIDE_OPTIONS; \
236 /* These are meant to be redefined in the host dependent files */
237 #define SUBTARGET_SWITCHES
238 #define SUBTARGET_OPTIONS
239 #define SUBTARGET_OVERRIDE_OPTIONS
241 /* target machine storage layout */
243 /* Define for XFmode extended real floating point support.
244 This will automatically cause REAL_ARITHMETIC to be defined. */
245 #define LONG_DOUBLE_TYPE_SIZE 96
247 /* Define if you don't want extended real, but do want to use the
248 software floating point emulator for REAL_ARITHMETIC and
249 decimal <-> binary conversion. */
250 /* #define REAL_ARITHMETIC */
252 /* Define this if most significant bit is lowest numbered
253 in instructions that operate on numbered bit-fields.
254 This is true for 68020 insns such as bfins and bfexts.
255 We make it true always by avoiding using the single-bit insns
256 except in special cases with constant bit numbers. */
257 #define BITS_BIG_ENDIAN 1
259 /* Define this if most significant byte of a word is the lowest numbered. */
260 /* That is true on the 68000. */
261 #define BYTES_BIG_ENDIAN 1
263 /* Define this if most significant word of a multiword number is the lowest
265 /* For 68000 we can decide arbitrarily
266 since there are no machine instructions for them.
267 So let's be consistent. */
268 #define WORDS_BIG_ENDIAN 1
270 /* number of bits in an addressable storage unit */
271 #define BITS_PER_UNIT 8
273 /* Width in bits of a "word", which is the contents of a machine register.
274 Note that this is not necessarily the width of data type `int';
275 if using 16-bit ints on a 68000, this would still be 32.
276 But on a machine with 16-bit registers, this would be 16. */
277 #define BITS_PER_WORD 32
279 /* Width of a word, in units (bytes). */
280 #define UNITS_PER_WORD 4
282 /* Width in bits of a pointer.
283 See also the macro `Pmode' defined below. */
284 #define POINTER_SIZE 32
286 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
287 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
289 /* Boundary (in *bits*) on which stack pointer should be aligned. */
290 #define STACK_BOUNDARY 16
292 /* Allocation boundary (in *bits*) for the code of a function. */
293 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
295 /* Alignment of field after `int : 0' in a structure. */
296 #define EMPTY_FIELD_BOUNDARY 16
298 /* No data type wants to be aligned rounder than this.
299 Most published ABIs say that ints should be aligned on 16 bit
300 boundaries, but cpus with 32 bit busses get better performance
301 aligned on 32 bit boundaries. Coldfires without a misalignment
302 module require 32 bit alignment. */
303 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
305 /* Set this nonzero if move instructions will actually fail to work
306 when given unaligned data. */
307 #define STRICT_ALIGNMENT 1
309 /* Maximum power of 2 that code can be aligned to. */
310 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
312 /* Align loop starts for optimal branching. */
313 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
315 /* This is how to align an instruction for optimal branching. */
316 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
318 #define SELECT_RTX_SECTION(MODE, X) \
321 readonly_data_section(); \
322 else if (LEGITIMATE_PIC_OPERAND_P (X)) \
323 readonly_data_section(); \
328 /* Define number of bits in most basic integer type.
329 (If undefined, default is BITS_PER_WORD). */
331 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
333 /* Define these to avoid dependence on meaning of `int'.
334 Note that WCHAR_TYPE_SIZE is used in cexp.y,
335 where TARGET_SHORT is not available. */
337 #define WCHAR_TYPE "long int"
338 #define WCHAR_TYPE_SIZE 32
340 /* Standard register usage. */
342 /* Number of actual hardware registers.
343 The hardware registers are assigned numbers for the compiler
344 from 0 to just below FIRST_PSEUDO_REGISTER.
345 All registers that the compiler knows about must be given numbers,
346 even those that are not normally considered general registers.
347 For the 68000, we give the data registers numbers 0-7,
348 the address registers numbers 010-017,
349 and the 68881 floating point registers numbers 020-027. */
350 #ifndef SUPPORT_SUN_FPA
351 #define FIRST_PSEUDO_REGISTER 24
353 #define FIRST_PSEUDO_REGISTER 56
356 /* This defines the register which is used to hold the offset table for PIC. */
357 #define PIC_OFFSET_TABLE_REGNUM 13
359 #ifndef SUPPORT_SUN_FPA
361 /* 1 for registers that have pervasive standard uses
362 and are not available for the register allocator.
363 On the 68000, only the stack pointer is such. */
365 #define FIXED_REGISTERS \
366 {/* Data registers. */ \
367 0, 0, 0, 0, 0, 0, 0, 0, \
369 /* Address registers. */ \
370 0, 0, 0, 0, 0, 0, 0, 1, \
372 /* Floating point registers \
374 0, 0, 0, 0, 0, 0, 0, 0 }
376 /* 1 for registers not available across function calls.
377 These must include the FIXED_REGISTERS and also any
378 registers that can be used without being saved.
379 The latter must include the registers where values are returned
380 and the register where structure-value addresses are passed.
381 Aside from that, you can include as many other registers as you like. */
382 #define CALL_USED_REGISTERS \
383 {1, 1, 0, 0, 0, 0, 0, 0, \
384 1, 1, 0, 0, 0, 0, 0, 1, \
385 1, 1, 0, 0, 0, 0, 0, 0 }
387 #else /* SUPPORT_SUN_FPA */
389 /* 1 for registers that have pervasive standard uses
390 and are not available for the register allocator.
391 On the 68000, only the stack pointer is such. */
393 /* fpa0 is also reserved so that it can be used to move data back and
394 forth between high fpa regs and everything else. */
396 #define FIXED_REGISTERS \
397 {/* Data registers. */ \
398 0, 0, 0, 0, 0, 0, 0, 0, \
400 /* Address registers. */ \
401 0, 0, 0, 0, 0, 0, 0, 1, \
403 /* Floating point registers \
405 0, 0, 0, 0, 0, 0, 0, 0, \
407 /* Sun3 FPA registers. */ \
408 1, 0, 0, 0, 0, 0, 0, 0, \
409 0, 0, 0, 0, 0, 0, 0, 0, \
410 0, 0, 0, 0, 0, 0, 0, 0, \
411 0, 0, 0, 0, 0, 0, 0, 0 }
413 /* 1 for registers not available across function calls.
414 These must include the FIXED_REGISTERS and also any
415 registers that can be used without being saved.
416 The latter must include the registers where values are returned
417 and the register where structure-value addresses are passed.
418 Aside from that, you can include as many other registers as you like. */
419 #define CALL_USED_REGISTERS \
420 {1, 1, 0, 0, 0, 0, 0, 0, \
421 1, 1, 0, 0, 0, 0, 0, 1, \
422 1, 1, 0, 0, 0, 0, 0, 0, \
423 /* FPA registers. */ \
424 1, 1, 1, 1, 0, 0, 0, 0, \
425 0, 0, 0, 0, 0, 0, 0, 0, \
426 0, 0, 0, 0, 0, 0, 0, 0, \
427 0, 0, 0, 0, 0, 0, 0, 0 }
429 #endif /* defined SUPPORT_SUN_FPA */
432 /* Make sure everything's fine if we *don't* have a given processor.
433 This assumes that putting a register in fixed_regs will keep the
434 compiler's mitts completely off it. We don't bother to zero it out
435 of register classes. If neither TARGET_FPA or TARGET_68881 is set,
436 the compiler won't touch since no instructions that use these
437 registers will be valid. */
439 #ifdef SUPPORT_SUN_FPA
441 #define CONDITIONAL_REGISTER_USAGE \
447 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
448 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
449 if (TEST_HARD_REG_BIT (x, i)) \
450 fixed_regs[i] = call_used_regs[i] = 1; \
454 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
455 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
456 if (TEST_HARD_REG_BIT (x, i)) \
457 fixed_regs[i] = call_used_regs[i] = 1; \
460 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
461 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
464 #define CONDITIONAL_REGISTER_USAGE \
467 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
468 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\
471 #endif /* defined SUPPORT_SUN_FPA */
473 /* Return number of consecutive hard regs needed starting at reg REGNO
474 to hold something of mode MODE.
475 This is ordinarily the length in words of a value of mode MODE
476 but can be less for certain modes in special long registers.
478 On the 68000, ordinary registers hold 32 bits worth;
479 for the 68881 registers, a single register is always enough for
480 anything that can be stored in them at all. */
481 #define HARD_REGNO_NREGS(REGNO, MODE) \
482 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
483 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
485 #ifndef SUPPORT_SUN_FPA
487 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
488 On the 68000, the cpu registers can hold any mode but the 68881 registers
489 can hold only SFmode or DFmode. The 68881 registers can't hold anything
490 if 68881 use is disabled. */
492 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
494 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
495 || ((REGNO) >= 16 && (REGNO) < 24 \
497 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
498 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
499 && GET_MODE_UNIT_SIZE (MODE) <= 12))
501 #else /* defined SUPPORT_SUN_FPA */
503 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
504 On the 68000, the cpu registers can hold any mode but the 68881 registers
505 can hold only SFmode or DFmode. And the 68881 registers can't hold anything
506 if 68881 use is disabled. However, the Sun FPA register can
507 (apparently) hold whatever you feel like putting in them.
508 If using the fpa, don't put a double in d7/a0. */
510 /* ??? This is confused. The check to prohibit d7/a0 overlaps should always
511 be enabled regardless of whether TARGET_FPA is specified. It isn't clear
512 what the other d/a register checks are for. Every check using REGNO
513 actually needs to use a range, e.g. 24>=X<56 not <56. There is probably
514 no one using this code anymore. */
515 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
518 && GET_MODE_CLASS ((MODE)) != MODE_INT \
519 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
520 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
521 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
524 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
525 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
526 && GET_MODE_UNIT_SIZE (MODE) <= 12) \
527 : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0)))
529 #endif /* defined SUPPORT_SUN_FPA */
531 /* Value is 1 if it is a good idea to tie two pseudo registers
532 when one has mode MODE1 and one has mode MODE2.
533 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
534 for any hard reg, then this must be 0 for correct output. */
535 #define MODES_TIEABLE_P(MODE1, MODE2) \
537 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
538 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
539 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
540 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
542 /* Specify the registers used for certain standard purposes.
543 The values of these macros are register numbers. */
545 /* m68000 pc isn't overloaded on a register. */
546 /* #define PC_REGNUM */
548 /* Register to use for pushing function arguments. */
549 #define STACK_POINTER_REGNUM 15
551 /* Base register for access to local variables of the function. */
552 #define FRAME_POINTER_REGNUM 14
554 /* Value should be nonzero if functions must have frame pointers.
555 Zero means the frame pointer need not be set up (and parms
556 may be accessed via the stack pointer) in functions that seem suitable.
557 This is computed in `reload', in reload1.c. */
558 #define FRAME_POINTER_REQUIRED 0
560 /* Base register for access to arguments of the function. */
561 #define ARG_POINTER_REGNUM 14
563 /* Register in which static-chain is passed to a function. */
564 #define STATIC_CHAIN_REGNUM 8
566 /* Register in which address to store a structure value
567 is passed to a function. */
568 #define STRUCT_VALUE_REGNUM 9
570 /* Define the classes of registers for register constraints in the
571 machine description. Also define ranges of constants.
573 One of the classes must always be named ALL_REGS and include all hard regs.
574 If there is more than one class, another class must be named NO_REGS
575 and contain no registers.
577 The name GENERAL_REGS must be the name of a class (or an alias for
578 another name such as ALL_REGS). This is the class of registers
579 that is allowed by "g" or "r" in a register constraint.
580 Also, registers outside this class are allocated only when
581 instructions express preferences for them.
583 The classes must be numbered in nondecreasing order; that is,
584 a larger-numbered class must never be contained completely
585 in a smaller-numbered class.
587 For any two classes, it is very desirable that there be another
588 class that represents their union. */
590 /* The 68000 has three kinds of registers, so eight classes would be
591 a complete set. One of them is not needed. */
593 #ifndef SUPPORT_SUN_FPA
598 GENERAL_REGS, DATA_OR_FP_REGS,
599 ADDR_OR_FP_REGS, ALL_REGS,
602 #define N_REG_CLASSES (int) LIM_REG_CLASSES
604 /* Give names of register classes as strings for dump file. */
606 #define REG_CLASS_NAMES \
607 { "NO_REGS", "DATA_REGS", \
608 "ADDR_REGS", "FP_REGS", \
609 "GENERAL_REGS", "DATA_OR_FP_REGS", \
610 "ADDR_OR_FP_REGS", "ALL_REGS" }
612 /* Define which registers fit in which classes.
613 This is an initializer for a vector of HARD_REG_SET
614 of length N_REG_CLASSES. */
616 #define REG_CLASS_CONTENTS \
618 {0x00000000}, /* NO_REGS */ \
619 {0x000000ff}, /* DATA_REGS */ \
620 {0x0000ff00}, /* ADDR_REGS */ \
621 {0x00ff0000}, /* FP_REGS */ \
622 {0x0000ffff}, /* GENERAL_REGS */ \
623 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
624 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
625 {0x00ffffff}, /* ALL_REGS */ \
628 /* The same information, inverted:
629 Return the class number of the smallest class containing
630 reg number REGNO. This could be a conditional expression
631 or could index an array. */
633 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
635 #else /* defined SUPPORT_SUN_FPA */
638 * Notes on final choices:
640 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
642 * 2) Removed all unions that involve address registers with
643 * floating point registers (left in unions of address and data with
645 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
646 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
647 * 4) Left in everything else.
649 enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
650 FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
651 DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
652 GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
655 #define N_REG_CLASSES (int) LIM_REG_CLASSES
657 /* Give names of register classes as strings for dump file. */
659 #define REG_CLASS_NAMES \
660 { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
661 "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
662 "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
663 "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
665 /* Define which registers fit in which classes.
666 This is an initializer for a vector of HARD_REG_SET
667 of length N_REG_CLASSES. */
669 #define REG_CLASS_CONTENTS \
671 {0, 0}, /* NO_REGS */ \
672 {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
673 {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
674 {0x00ff0000, 0x00000000}, /* FP_REGS */ \
675 {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
676 {0x000000ff, 0x00000000}, /* DATA_REGS */ \
677 {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
678 {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
679 {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
680 {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
681 {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
682 {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
683 {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
684 {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \
687 /* The same information, inverted:
688 Return the class number of the smallest class containing
689 reg number REGNO. This could be a conditional expression
690 or could index an array. */
692 extern enum reg_class regno_reg_class[];
693 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
695 #endif /* SUPPORT_SUN_FPA */
697 /* The class value for index registers, and the one for base regs. */
699 #define INDEX_REG_CLASS GENERAL_REGS
700 #define BASE_REG_CLASS ADDR_REGS
702 /* Get reg_class from a letter such as appears in the machine description.
703 We do a trick here to modify the effective constraints on the
704 machine description; we zorch the constraint letters that aren't
705 appropriate for a specific target. This allows us to guarantee
706 that a specific kind of register will not be used for a given target
707 without fiddling with the register classes above. */
709 #ifndef SUPPORT_SUN_FPA
711 #define REG_CLASS_FROM_LETTER(C) \
712 ((C) == 'a' ? ADDR_REGS : \
713 ((C) == 'd' ? DATA_REGS : \
714 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
718 #else /* defined SUPPORT_SUN_FPA */
720 #define REG_CLASS_FROM_LETTER(C) \
721 ((C) == 'a' ? ADDR_REGS : \
722 ((C) == 'd' ? DATA_REGS : \
723 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
725 ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
727 ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
731 #endif /* defined SUPPORT_SUN_FPA */
733 /* The letters I, J, K, L and M in a register constraint string
734 can be used to stand for particular ranges of immediate operands.
735 This macro defines what the ranges are.
736 C is the letter, and VALUE is a constant value.
737 Return 1 if VALUE is in the range specified by C.
739 For the 68000, `I' is used for the range 1 to 8
740 allowed as immediate shift counts and in addq.
741 `J' is used for the range of signed numbers that fit in 16 bits.
742 `K' is for numbers that moveq can't handle.
743 `L' is for range -8 to -1, range of values that can be added with subq.
744 `M' is for numbers that moveq+notb can't handle.
745 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
746 'O' is for 16 (for rotate using swap).
747 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
749 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
750 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
751 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
752 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
753 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
754 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
755 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
756 (C) == 'O' ? (VALUE) == 16 : \
757 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
760 * A small bit of explanation:
761 * "G" defines all of the floating constants that are *NOT* 68881
762 * constants. this is so 68881 constants get reloaded and the
763 * fpmovecr is used. "H" defines *only* the class of constants that
764 * the fpa can use, because these can be gotten at in any fpa
765 * instruction and there is no need to force reloads.
767 #ifndef SUPPORT_SUN_FPA
768 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
769 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
770 #else /* defined SUPPORT_SUN_FPA */
771 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
772 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
773 (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
774 #endif /* defined SUPPORT_SUN_FPA */
776 /* A C expression that defines the optional machine-dependent constraint
777 letters that can be used to segregate specific types of operands,
778 usually memory references, for the target machine. It should return 1 if
779 VALUE corresponds to the operand type represented by the constraint letter
780 C. If C is not defined as an extra constraint, the value returned should
781 be 0 regardless of VALUE. */
783 /* Letters in the range `Q' through `U' may be defined in a
784 machine-dependent fashion to stand for arbitrary operand types.
785 The machine description macro `EXTRA_CONSTRAINT' is passed the
786 operand as its first argument and the constraint letter as its
789 `Q' means address register indirect addressing mode.
790 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
791 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
793 #define EXTRA_CONSTRAINT(OP,CODE) \
796 && GET_CODE (OP) == MEM \
797 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
798 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
799 || GET_CODE (XEXP (OP, 0)) == CONST)) \
803 && (GET_CODE (OP) == SYMBOL_REF \
804 || GET_CODE (OP) == LABEL_REF \
805 || GET_CODE (OP) == CONST)) \
808 ? (GET_CODE (OP) == MEM \
809 && GET_CODE (XEXP (OP, 0)) == REG) \
813 /* Given an rtx X being reloaded into a reg required to be
814 in class CLASS, return the class of reg to actually use.
815 In general this is just CLASS; but on some machines
816 in some cases it is preferable to use a more restrictive class.
817 On the 68000 series, use a data reg if possible when the
818 value is a constant in the range where moveq could be used
819 and we ensure that QImodes are reloaded into data regs. */
821 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
822 ((GET_CODE (X) == CONST_INT \
823 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
824 && (CLASS) != ADDR_REGS) \
826 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
828 : (GET_CODE (X) == CONST_DOUBLE \
829 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
830 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
831 ? FP_REGS : NO_REGS) \
833 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
834 || GET_CODE (X) == LABEL_REF)) \
838 /* Force QImode output reloads from subregs to be allocated to data regs,
839 since QImode stores from address regs are not supported. We make the
840 assumption that if the class is not ADDR_REGS, then it must be a superset
843 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
844 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
848 /* Return the maximum number of consecutive registers
849 needed to represent mode MODE in a register of class CLASS. */
850 /* On the 68000, this is the size of MODE in words,
851 except in the FP regs, where a single reg is always enough. */
852 #ifndef SUPPORT_SUN_FPA
854 #define CLASS_MAX_NREGS(CLASS, MODE) \
855 ((CLASS) == FP_REGS ? 1 \
856 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
858 /* Moves between fp regs and other regs are two insns. */
859 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
860 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
861 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
864 #else /* defined SUPPORT_SUN_FPA */
866 #define CLASS_MAX_NREGS(CLASS, MODE) \
867 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
868 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
870 /* Moves between fp regs and other regs are two insns. */
871 /* Likewise for high fpa regs and other regs. */
872 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
873 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
874 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
875 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
876 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
879 #endif /* define SUPPORT_SUN_FPA */
881 /* Stack layout; function entry, exit and calling. */
883 /* Define this if pushing a word on the stack
884 makes the stack pointer a smaller address. */
885 #define STACK_GROWS_DOWNWARD
887 /* Nonzero if we need to generate stack-probe insns.
888 On most systems they are not needed.
889 When they are needed, define this as the stack offset to probe at. */
892 /* Define this if the nominal address of the stack frame
893 is at the high-address end of the local variables;
894 that is, each additional local variable allocated
895 goes at a more negative offset in the frame. */
896 #define FRAME_GROWS_DOWNWARD
898 /* Offset within stack frame to start allocating local variables at.
899 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
900 first local allocated. Otherwise, it is the offset to the BEGINNING
901 of the first local allocated. */
902 #define STARTING_FRAME_OFFSET 0
904 /* If we generate an insn to push BYTES bytes,
905 this says how many the stack pointer really advances by.
906 On the 68000, sp@- in a byte insn really pushes a word.
907 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
908 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
910 /* Offset of first parameter from the argument pointer register value. */
911 #define FIRST_PARM_OFFSET(FNDECL) 8
913 /* Offset of the CFA from the argument pointer register value. */
914 #define ARG_POINTER_CFA_OFFSET 8
916 /* Value is the number of byte of arguments automatically
917 popped when returning from a subroutine call.
918 FUNDECL is the declaration node of the function (as a tree),
919 FUNTYPE is the data type of the function (as a tree),
920 or for a library call it is an identifier node for the subroutine name.
921 SIZE is the number of bytes of arguments passed on the stack.
923 On the 68000, the RTS insn cannot pop anything.
924 On the 68010, the RTD insn may be used to pop them if the number
925 of args is fixed, but if the number is variable then the caller
926 must pop them all. RTD can't be used for library calls now
927 because the library is compiled with the Unix compiler.
928 Use of RTD is a selectable option, since it is incompatible with
929 standard Unix calling sequences. If the option is not selected,
930 the caller must always pop the args. */
932 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
933 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
934 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
935 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
936 == void_type_node))) \
939 /* Define how to find the value returned by a function.
940 VALTYPE is the data type of the value (as a tree).
941 If the precise function being called is known, FUNC is its FUNCTION_DECL;
942 otherwise, FUNC is 0. */
944 /* On the 68000 the return value is in D0 regardless. */
946 #define FUNCTION_VALUE(VALTYPE, FUNC) \
947 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
949 /* Define how to find the value returned by a library function
950 assuming the value has mode MODE. */
952 /* On the 68000 the return value is in D0 regardless. */
954 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
956 /* 1 if N is a possible register number for a function value.
957 On the 68000, d0 is the only register thus used. */
959 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
961 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
962 more than one register. */
964 #define NEEDS_UNTYPED_CALL 0
966 /* Define this if PCC uses the nonreentrant convention for returning
967 structure and union values. */
969 #define PCC_STATIC_STRUCT_RETURN
971 /* 1 if N is a possible register number for function argument passing.
972 On the 68000, no registers are used in this way. */
974 #define FUNCTION_ARG_REGNO_P(N) 0
976 /* Define a data type for recording info about an argument list
977 during the scan of that argument list. This data type should
978 hold all necessary information about the function itself
979 and about the args processed so far, enough to enable macros
980 such as FUNCTION_ARG to determine where the next arg should go.
982 On the m68k, this is a single integer, which is a number of bytes
983 of arguments scanned so far. */
985 #define CUMULATIVE_ARGS int
987 /* Initialize a variable CUM of type CUMULATIVE_ARGS
988 for a call to a function whose data type is FNTYPE.
989 For a library call, FNTYPE is 0.
991 On the m68k, the offset starts at 0. */
993 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
996 /* Update the data in CUM to advance over an argument
997 of mode MODE and data type TYPE.
998 (TYPE is null for libcalls where that information may not be available.) */
1000 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1001 ((CUM) += ((MODE) != BLKmode \
1002 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1003 : (int_size_in_bytes (TYPE) + 3) & ~3))
1005 /* Define where to put the arguments to a function.
1006 Value is zero to push the argument on the stack,
1007 or a hard register in which to store the argument.
1009 MODE is the argument's machine mode.
1010 TYPE is the data type of the argument (as a tree).
1011 This is null for libcalls where that information may
1013 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1014 the preceding args and about the function being called.
1015 NAMED is nonzero if this argument is a named parameter
1016 (otherwise it is an extra parameter matching an ellipsis). */
1018 /* On the 68000 all args are pushed, except if -mregparm is specified
1019 then the first two words of arguments are passed in d0, d1.
1020 *NOTE* -mregparm does not work.
1021 It exists only to test register calling conventions. */
1023 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1024 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
1026 /* For an arg passed partly in registers and partly in memory,
1027 this is the number of registers used.
1028 For args passed entirely in registers or entirely in memory, zero. */
1030 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1031 ((TARGET_REGPARM && (CUM) < 8 \
1032 && 8 < ((CUM) + ((MODE) == BLKmode \
1033 ? int_size_in_bytes (TYPE) \
1034 : GET_MODE_SIZE (MODE)))) \
1035 ? 2 - (CUM) / 4 : 0)
1037 /* Generate the assembly code for function entry. */
1038 #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE)
1040 /* Output assembler code to FILE to increment profiler label # LABELNO
1041 for profiling a function entry. */
1043 #define FUNCTION_PROFILER(FILE, LABELNO) \
1044 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
1046 /* Output assembler code to FILE to initialize this source file's
1047 basic block profiling info, if that has not already been done. */
1049 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1052 switch (profile_block_flag) \
1055 asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \
1056 (BLOCK_OR_LABEL)); \
1060 asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \
1061 (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \
1067 /* Output assembler code to FILE to increment the counter for
1068 the BLOCKNO'th basic block in this source file. */
1070 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1073 switch (profile_block_flag) \
1076 asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \
1081 asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO); \
1087 /* Output assembler code to FILE to indicate return from
1088 a function during basic block profiling. */
1090 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1091 asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n");
1093 /* Save all registers which may be clobbered by a function call.
1094 MACHINE_STATE_SAVE and MACHINE_STATE_RESTORE are target-code macros,
1095 used in libgcc2.c. They may not refer to TARGET_* macros !!! */
1096 #if defined (__mc68010__) || defined(mc68010) \
1097 || defined(__mc68020__) || defined(mc68020) \
1098 || defined(__mc68030__) || defined(mc68030) \
1099 || defined(__mc68040__) || defined(mc68040) \
1100 || defined(__mcpu32__) || defined(mcpu32)
1101 #define MACHINE_STATE_m68010_up
1105 #if defined(__mcf5200__)
1106 #define MACHINE_STATE_SAVE(id) \
1108 asm ("sub.l 20,%sp"); \
1109 asm ("movm.l &0x0303,4(%sp)"); \
1110 asm ("move.w %ccr,%d0"); \
1111 asm ("movm.l &0x0001,(%sp)"); \
1113 #else /* !__mcf5200__ */
1114 #if defined(MACHINE_STATE_m68010_up)
1116 /* HPUX assembler does not accept %ccr. */
1117 #define MACHINE_STATE_SAVE(id) \
1119 asm ("move.w %cc,-(%sp)"); \
1120 asm ("movm.l &0xc0c0,-(%sp)"); \
1122 #else /* ! __HPUX_ASM__ */
1123 #define MACHINE_STATE_SAVE(id) \
1125 asm ("move.w %ccr,-(%sp)"); \
1126 asm ("movm.l &0xc0c0,-(%sp)"); \
1128 #endif /* __HPUX_ASM__ */
1129 #else /* !MACHINE_STATE_m68010_up */
1130 #define MACHINE_STATE_SAVE(id) \
1132 asm ("move.w %sr,-(%sp)"); \
1133 asm ("movm.l &0xc0c0,-(%sp)"); \
1135 #endif /* MACHINE_STATE_m68010_up */
1136 #endif /* __mcf5200__ */
1137 #else /* !MOTOROLA */
1138 #if defined(__mcf5200__)
1139 #define MACHINE_STATE_SAVE(id) \
1141 asm ("subl %#20,%/sp" : ); \
1142 asm ("movml %/d0/%/d1/%/a0/%/a1,%/sp@(4)" : ); \
1143 asm ("movew %/cc,%/d0" : ); \
1144 asm ("movml %/d0,%/sp@" : ); \
1146 #else /* !__mcf5200__ */
1147 #if defined(MACHINE_STATE_m68010_up)
1148 #define MACHINE_STATE_SAVE(id) \
1150 asm ("movew %/cc,%/sp@-" : ); \
1151 asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
1153 #else /* !MACHINE_STATE_m68010_up */
1154 #define MACHINE_STATE_SAVE(id) \
1156 asm ("movew %/sr,%/sp@-" : ); \
1157 asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
1159 #endif /* MACHINE_STATE_m68010_up */
1160 #endif /* __mcf5200__ */
1161 #endif /* MOTOROLA */
1163 /* Restore all registers saved by MACHINE_STATE_SAVE. */
1166 #if defined(__mcf5200__)
1167 #define MACHINE_STATE_RESTORE(id) \
1169 asm ("movm.l (%sp),&0x0001"); \
1170 asm ("move.w %d0,%ccr"); \
1171 asm ("movm.l 4(%sp),&0x0303"); \
1172 asm ("add.l 20,%sp"); \
1174 #else /* !__mcf5200__ */
1176 /* HPUX assembler does not accept %ccr. */
1177 #define MACHINE_STATE_RESTORE(id) \
1179 asm ("movm.l (%sp)+,&0x0303"); \
1180 asm ("move.w (%sp)+,%cc"); \
1182 #else /* ! __HPUX_ASM__ */
1183 #define MACHINE_STATE_RESTORE(id) \
1185 asm ("movm.l (%sp)+,&0x0303"); \
1186 asm ("move.w (%sp)+,%ccr"); \
1188 #endif /* __HPUX_ASM__ */
1189 #endif /* __mcf5200__ */
1190 #else /* !MOTOROLA */
1191 #if defined(__mcf5200__)
1192 #define MACHINE_STATE_RESTORE(id) \
1194 asm ("movml %/sp@,%/d0" : ); \
1195 asm ("movew %/d0,%/cc" : ); \
1196 asm ("movml %/sp@(4),%/d0/%/d1/%/a0/%/a1" : ); \
1197 asm ("addl %#20,%/sp" : ); \
1199 #else /* !__mcf5200__ */
1200 #define MACHINE_STATE_RESTORE(id) \
1202 asm ("moveml %/sp@+,%/d0/%/d1/%/a0/%/a1" : ); \
1203 asm ("movew %/sp@+,%/cc" : ); \
1205 #endif /* __mcf5200__ */
1206 #endif /* MOTOROLA */
1208 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1209 the stack pointer does not matter. The value is tested only in
1210 functions that have frame pointers.
1211 No definition is equivalent to always zero. */
1213 #define EXIT_IGNORE_STACK 1
1215 /* Generate the assembly code for function exit. */
1216 #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE)
1218 /* This is a hook for other tm files to change. */
1219 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
1221 /* Determine if the epilogue should be output as RTL.
1222 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1223 #define USE_RETURN_INSN use_return_insn ()
1225 /* Store in the variable DEPTH the initial difference between the
1226 frame pointer reg contents and the stack pointer reg contents,
1227 as of the start of the function body. This depends on the layout
1228 of the fixed parts of the stack frame and on how registers are saved.
1230 On the 68k, if we have a frame, we must add one word to its length
1231 to allow for the place that a6 is stored when we do have a frame pointer.
1232 Otherwise, we would need to compute the offset from the frame pointer
1233 of a local variable as a function of frame_pointer_needed, which
1236 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1239 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1240 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1242 for (regno = 0; regno < 16; regno++) \
1243 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1245 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1246 + (get_frame_size () == 0 ? 0 : 4)); \
1249 /* Output assembler code for a block containing the constant parts
1250 of a trampoline, leaving space for the variable parts. */
1252 /* On the 68k, the trampoline looks like this:
1256 WARNING: Targets that may run on 68040+ cpus must arrange for
1257 the instruction cache to be flushed. Previous incarnations of
1258 the m68k trampoline code attempted to get around this by either
1259 using an out-of-line transfer function or pc-relative data, but
1260 the fact remains that the code to jump to the transfer function
1261 or the code to load the pc-relative data needs to be flushed
1262 just as much as the "variable" portion of the trampoline.
1263 Recognizing that a cache flush is going to be required anyway,
1264 dispense with such notions and build a smaller trampoline. */
1266 /* Since more instructions are required to move a template into
1267 place than to create it on the spot, don't use a template. */
1269 /* Length in units of the trampoline for entering a nested function. */
1271 #define TRAMPOLINE_SIZE 12
1273 /* Alignment required for a trampoline in bits. */
1275 #define TRAMPOLINE_ALIGNMENT 16
1277 /* Targets redefine this to invoke code to either flush the cache,
1278 or enable stack execution (or both). */
1280 #ifndef FINALIZE_TRAMPOLINE
1281 #define FINALIZE_TRAMPOLINE(TRAMP)
1284 /* Emit RTL insns to initialize the variable parts of a trampoline.
1285 FNADDR is an RTX for the address of the function's pure code.
1286 CXT is an RTX for the static chain value for the function.
1288 We generate a two-instructions program at address TRAMP :
1292 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1294 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1295 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1296 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1298 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1299 FINALIZE_TRAMPOLINE(TRAMP); \
1302 /* This is the library routine that is used
1303 to transfer control from the trampoline
1304 to the actual nested function.
1305 It is defined for backward compatibility,
1306 for linking with object code that used the old
1307 trampoline definition. */
1309 /* A colon is used with no explicit operands
1310 to cause the template string to be scanned for %-constructs. */
1311 /* The function name __transfer_from_trampoline is not actually used.
1312 The function definition just permits use of "asm with operands"
1313 (though the operand list is empty). */
1314 #define TRANSFER_FROM_TRAMPOLINE \
1316 __transfer_from_trampoline () \
1318 register char *a0 asm ("%a0"); \
1319 asm (GLOBAL_ASM_OP " ___trampoline"); \
1320 asm ("___trampoline:"); \
1321 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1322 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1326 /* Addressing modes, and classification of registers for them. */
1328 #define HAVE_POST_INCREMENT 1
1329 /* #define HAVE_POST_DECREMENT 0 */
1331 #define HAVE_PRE_DECREMENT 1
1332 /* #define HAVE_PRE_INCREMENT 0 */
1334 /* Macros to check register numbers against specific register classes. */
1336 /* These assume that REGNO is a hard or pseudo reg number.
1337 They give nonzero only if REGNO is a hard reg of the suitable class
1338 or a pseudo reg currently allocated to a suitable hard reg.
1339 Since they use reg_renumber, they are safe only once reg_renumber
1340 has been allocated, which happens in local-alloc.c. */
1342 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1343 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1344 #define REGNO_OK_FOR_BASE_P(REGNO) \
1345 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1346 #define REGNO_OK_FOR_DATA_P(REGNO) \
1347 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1348 #define REGNO_OK_FOR_FP_P(REGNO) \
1349 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1350 #ifdef SUPPORT_SUN_FPA
1351 #define REGNO_OK_FOR_FPA_P(REGNO) \
1352 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1355 /* Now macros that check whether X is a register and also,
1356 strictly, whether it is in a specified class.
1358 These macros are specific to the 68000, and may be used only
1359 in code for printing assembler insns and in conditions for
1360 define_optimization. */
1362 /* 1 if X is a data register. */
1364 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1366 /* 1 if X is an fp register. */
1368 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1370 /* 1 if X is an address register */
1372 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1374 #ifdef SUPPORT_SUN_FPA
1375 /* 1 if X is a register in the Sun FPA. */
1376 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1378 /* Answer must be no if we don't have an FPA. */
1379 #define FPA_REG_P(X) 0
1382 /* Maximum number of registers that can appear in a valid memory address. */
1384 #define MAX_REGS_PER_ADDRESS 2
1386 /* Recognize any constant value that is a valid address. */
1388 #define CONSTANT_ADDRESS_P(X) \
1389 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1390 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1391 || GET_CODE (X) == HIGH)
1393 /* Nonzero if the constant value X is a legitimate general operand.
1394 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1396 #define LEGITIMATE_CONSTANT_P(X) 1
1398 /* Nonzero if the constant value X is a legitimate general operand
1399 when generating PIC code. It is given that flag_pic is on and
1400 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1402 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1403 accepted by insn predicates, but which would otherwise fail the
1404 `general_operand' test. */
1406 #ifndef REG_OK_STRICT
1407 #define PCREL_GENERAL_OPERAND_OK 0
1409 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1412 #define LEGITIMATE_PIC_OPERAND_P(X) \
1413 ((! symbolic_operand (X, VOIDmode) \
1414 && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X) \
1415 && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM \
1416 && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), \
1418 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1419 || PCREL_GENERAL_OPERAND_OK)
1421 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1422 and check its validity for a certain class.
1423 We have two alternate definitions for each of them.
1424 The usual definition accepts all pseudo regs; the other rejects
1425 them unless they have been allocated suitable hard regs.
1426 The symbol REG_OK_STRICT causes the latter definition to be used.
1428 Most source files want to accept pseudo regs in the hope that
1429 they will get allocated to the class that the insn wants them to be in.
1430 Source files for reload pass need to be strict.
1431 After reload, it makes no difference, since pseudo regs have
1432 been eliminated by then. */
1434 #ifndef REG_OK_STRICT
1436 /* Nonzero if X is a hard reg that can be used as an index
1437 or if it is a pseudo reg. */
1438 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1439 /* Nonzero if X is a hard reg that can be used as a base reg
1440 or if it is a pseudo reg. */
1441 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1445 /* Nonzero if X is a hard reg that can be used as an index. */
1446 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1447 /* Nonzero if X is a hard reg that can be used as a base reg. */
1448 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1452 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1453 that is a valid memory address for an instruction.
1454 The MODE argument is the machine mode for the MEM expression
1455 that wants to use this address.
1457 When generating PIC, an address involving a SYMBOL_REF is legitimate
1458 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1459 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1460 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1462 Likewise for a LABEL_REF when generating PIC.
1464 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1466 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1467 also makes function inlining work when inline functions are called with
1468 arguments that are SUBREGs. */
1470 #define LEGITIMATE_BASE_REG_P(X) \
1471 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1472 || (GET_CODE (X) == SUBREG \
1473 && GET_CODE (SUBREG_REG (X)) == REG \
1474 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1476 #define INDIRECTABLE_1_ADDRESS_P(X) \
1477 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1478 || LEGITIMATE_BASE_REG_P (X) \
1479 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1480 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1481 || (GET_CODE (X) == PLUS \
1482 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1483 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1485 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1486 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1487 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1488 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1489 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1491 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1492 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1494 /* Only labels on dispatch tables are valid for indexing from. */
1495 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1497 if (GET_CODE (X) == LABEL_REF \
1498 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1499 && GET_CODE (temp) == JUMP_INSN \
1500 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1501 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1503 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1505 #define GO_IF_INDEXING(X, ADDR) \
1506 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1507 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1508 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1509 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1511 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1512 { GO_IF_INDEXING (X, ADDR); \
1513 if (GET_CODE (X) == PLUS) \
1514 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1515 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1516 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1517 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1518 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1519 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1521 /* coldfire/5200 does not allow HImode index registers. */
1522 #define LEGITIMATE_INDEX_REG_P(X) \
1523 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1525 && GET_CODE (X) == SIGN_EXTEND \
1526 && GET_CODE (XEXP (X, 0)) == REG \
1527 && GET_MODE (XEXP (X, 0)) == HImode \
1528 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1529 || (GET_CODE (X) == SUBREG \
1530 && GET_CODE (SUBREG_REG (X)) == REG \
1531 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1533 #define LEGITIMATE_INDEX_P(X) \
1534 (LEGITIMATE_INDEX_REG_P (X) \
1535 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1536 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1537 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1538 && (INTVAL (XEXP (X, 1)) == 2 \
1539 || INTVAL (XEXP (X, 1)) == 4 \
1540 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1542 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1543 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1544 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1545 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1546 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1547 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1548 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1551 /* Don't call memory_address_noforce for the address to fetch
1552 the switch offset. This address is ok as it stands (see above),
1553 but memory_address_noforce would alter it. */
1554 #define PIC_CASE_VECTOR_ADDRESS(index) index
1556 /* Try machine-dependent ways of modifying an illegitimate address
1557 to be legitimate. If we find one, return the new, valid address.
1558 This macro is used in only one place: `memory_address' in explow.c.
1560 OLDX is the address as it was before break_out_memory_refs was called.
1561 In some cases it is useful to look at this to decide what needs to be done.
1563 MODE and WIN are passed so that this macro can use
1564 GO_IF_LEGITIMATE_ADDRESS.
1566 It is always safe for this macro to do nothing. It exists to recognize
1567 opportunities to optimize the output.
1569 For the 68000, we handle X+REG by loading X into a register R and
1570 using R+REG. R will go in an address reg and indexing will be used.
1571 However, if REG is a broken-out memory address or multiplication,
1572 nothing needs to be done because REG can certainly go in an address reg. */
1574 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1575 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1576 { register int ch = (X) != (OLDX); \
1577 if (GET_CODE (X) == PLUS) \
1579 if (GET_CODE (XEXP (X, 0)) == MULT) \
1580 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1581 if (GET_CODE (XEXP (X, 1)) == MULT) \
1582 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1583 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1584 && GET_CODE (XEXP (X, 0)) == REG) \
1586 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1587 if (GET_CODE (XEXP (X, 0)) == REG \
1588 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1589 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1590 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1591 { register rtx temp = gen_reg_rtx (Pmode); \
1592 register rtx val = force_operand (XEXP (X, 1), 0); \
1593 emit_move_insn (temp, val); \
1595 XEXP (X, 1) = temp; \
1597 else if (GET_CODE (XEXP (X, 1)) == REG \
1598 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1599 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1600 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1601 { register rtx temp = gen_reg_rtx (Pmode); \
1602 register rtx val = force_operand (XEXP (X, 0), 0); \
1603 emit_move_insn (temp, val); \
1605 XEXP (X, 0) = temp; \
1608 /* Go to LABEL if ADDR (a legitimate address expression)
1609 has an effect that depends on the machine mode it is used for.
1610 On the 68000, only predecrement and postincrement address depend thus
1611 (the amount of decrement or increment being the length of the operand). */
1613 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1614 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1616 /* Specify the machine mode that this machine uses
1617 for the index in the tablejump instruction. */
1618 #define CASE_VECTOR_MODE HImode
1620 /* Define as C expression which evaluates to nonzero if the tablejump
1621 instruction expects the table to contain offsets from the address of the
1623 Do not define this if the table should contain absolute addresses. */
1624 #define CASE_VECTOR_PC_RELATIVE 1
1626 /* Specify the tree operation to be used to convert reals to integers. */
1627 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1629 /* This is the kind of divide that is easiest to do in the general case. */
1630 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1632 /* Define this as 1 if `char' should by default be signed; else as 0. */
1633 #define DEFAULT_SIGNED_CHAR 1
1635 /* Don't cse the address of the function being compiled. */
1636 #define NO_RECURSIVE_FUNCTION_CSE
1638 /* Max number of bytes we can move from memory to memory
1639 in one reasonably fast instruction. */
1642 /* Define this if zero-extension is slow (more than one real instruction). */
1643 #define SLOW_ZERO_EXTEND
1645 /* Nonzero if access to memory by bytes is slow and undesirable. */
1646 #define SLOW_BYTE_ACCESS 0
1648 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1649 is done just by pretending it is already truncated. */
1650 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1652 /* We assume that the store-condition-codes instructions store 0 for false
1653 and some other value for true. This is the value stored for true. */
1655 #define STORE_FLAG_VALUE -1
1657 /* When a prototype says `char' or `short', really pass an `int'. */
1658 #define PROMOTE_PROTOTYPES
1660 /* Specify the machine mode that pointers have.
1661 After generation of rtl, the compiler makes no further distinction
1662 between pointers and any other objects of this machine mode. */
1663 #define Pmode SImode
1665 /* A function address in a call instruction
1666 is a byte address (for indexing purposes)
1667 so give the MEM rtx a byte's mode. */
1668 #define FUNCTION_MODE QImode
1670 /* Compute the cost of computing a constant rtl expression RTX
1671 whose rtx-code is CODE. The body of this macro is a portion
1672 of a switch statement. If the code is computed here,
1673 return it with a return statement. Otherwise, break from the switch. */
1675 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1677 /* Constant zero is super cheap due to clr instruction. */ \
1678 if (RTX == const0_rtx) return 0; \
1679 /* if ((OUTER_CODE) == SET) */ \
1680 return const_int_cost(RTX); \
1685 case CONST_DOUBLE: \
1688 /* Compute the cost of various arithmetic operations.
1689 These are vaguely right for a 68020. */
1690 /* The costs for long multiply have been adjusted to
1691 work properly in synth_mult on the 68020,
1692 relative to an average of the time for add and the time for shift,
1693 taking away a little more because sometimes move insns are needed. */
1694 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1695 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1696 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1697 #define DIVW_COST (TARGET_68020 ? 27 : 12)
1699 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1701 /* An lea costs about three times as much as a simple add. */ \
1702 if (GET_MODE (X) == SImode \
1703 && GET_CODE (XEXP (X, 1)) == REG \
1704 && GET_CODE (XEXP (X, 0)) == MULT \
1705 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1706 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1707 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \
1708 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \
1709 || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \
1710 return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1716 return COSTS_N_INSNS(1); \
1717 if (! TARGET_68020) \
1719 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1721 if (INTVAL (XEXP (X, 1)) < 16) \
1722 return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \
1724 /* We're using clrw + swap for these cases. */ \
1725 return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \
1727 return COSTS_N_INSNS (10); /* worst case */ \
1729 /* A shift by a big integer takes an extra instruction. */ \
1730 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1731 && (INTVAL (XEXP (X, 1)) == 16)) \
1732 return COSTS_N_INSNS (2); /* clrw;swap */ \
1733 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1734 && !(INTVAL (XEXP (X, 1)) > 0 \
1735 && INTVAL (XEXP (X, 1)) <= 8)) \
1736 return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1739 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \
1740 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \
1741 && GET_MODE (X) == SImode) \
1742 return COSTS_N_INSNS (MULW_COST); \
1743 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1744 return COSTS_N_INSNS (MULW_COST); \
1746 return COSTS_N_INSNS (MULL_COST); \
1751 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1752 return COSTS_N_INSNS (DIVW_COST); /* div.w */ \
1753 return COSTS_N_INSNS (43); /* div.l */
1755 /* Tell final.c how to eliminate redundant test instructions. */
1757 /* Here we define machine-dependent flags and fields in cc_status
1758 (see `conditions.h'). */
1760 /* Set if the cc value is actually in the 68881, so a floating point
1761 conditional branch must be output. */
1762 #define CC_IN_68881 04000
1764 /* Store in cc_status the expressions that the condition codes will
1765 describe after execution of an instruction whose pattern is EXP.
1766 Do not alter them if the instruction would not alter the cc's. */
1768 /* On the 68000, all the insns to store in an address register fail to
1769 set the cc's. However, in some cases these instructions can make it
1770 possibly invalid to use the saved cc's. In those cases we clear out
1771 some or all of the saved cc's so they won't be used. */
1773 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1775 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1776 { if (cc_prev_status.flags & CC_IN_68881) \
1778 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1782 /* Control the assembler format that we output. */
1784 /* Output at beginning of assembler file. */
1786 #define ASM_FILE_START(FILE) \
1787 fprintf (FILE, "#NO_APP\n");
1789 /* Output to assembler file text saying following lines
1790 may contain character constants, extra white space, comments, etc. */
1792 #define ASM_APP_ON "#APP\n"
1794 /* Output to assembler file text saying following lines
1795 no longer contain unusual constructs. */
1797 #define ASM_APP_OFF "#NO_APP\n"
1799 /* Output before read-only data. */
1801 #define TEXT_SECTION_ASM_OP ".text"
1803 /* Output before writable data. */
1805 #define DATA_SECTION_ASM_OP ".data"
1807 /* Here are four prefixes that are used by asm_fprintf to
1808 facilitate customization for alternate assembler syntaxes.
1809 Machines with no likelihood of an alternate syntax need not
1810 define these and need not use asm_fprintf. */
1812 /* The prefix for register names. Note that REGISTER_NAMES
1813 is supposed to include this prefix. */
1815 #define REGISTER_PREFIX ""
1817 /* The prefix for local labels. You should be able to define this as
1818 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1819 without having to make any other changes to account for the specific
1820 definition. Note it is a string literal, not interpreted by printf
1823 #define LOCAL_LABEL_PREFIX ""
1825 /* The prefix to add to user-visible assembler symbols. */
1827 #define USER_LABEL_PREFIX "_"
1829 /* The prefix for immediate operands. */
1831 #define IMMEDIATE_PREFIX "#"
1833 /* How to refer to registers in assembler output.
1834 This sequence is indexed by compiler's hard-register-number (see above). */
1836 #ifndef SUPPORT_SUN_FPA
1838 #define REGISTER_NAMES \
1839 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1840 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1841 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1843 #else /* SUPPORTED_SUN_FPA */
1845 #define REGISTER_NAMES \
1846 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1847 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1848 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
1849 "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
1850 "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
1851 "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
1852 "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
1854 #endif /* defined SUPPORT_SUN_FPA */
1856 /* How to renumber registers for dbx and gdb.
1857 On the Sun-3, the floating point registers have numbers
1858 18 to 25, not 16 to 23 as they do in the compiler. */
1860 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1862 /* Before the prologue, RA is at 0(%sp). */
1863 #define INCOMING_RETURN_ADDR_RTX \
1864 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1866 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1867 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1868 Instead use the identity mapping. */
1869 #define DWARF_FRAME_REGNUM(REG) REG
1871 /* Before the prologue, the top of the frame is at 4(%sp). */
1872 #define INCOMING_FRAME_SP_OFFSET 4
1874 /* This is how to output the definition of a user-level label named NAME,
1875 such as the label on a static function or variable NAME. */
1877 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1878 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1880 /* This is how to output a command to make the user-level label named NAME
1881 defined for reference from other files. */
1883 #define GLOBAL_ASM_OP ".globl"
1884 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1885 do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \
1886 assemble_name (FILE, NAME); \
1887 fputs ("\n", FILE);} while (0)
1889 /* This is how to output a reference to a user-level label named NAME.
1890 `assemble_name' uses this. */
1892 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1893 asm_fprintf (FILE, "%0U%s", NAME)
1895 /* This is how to output an internal numbered label where
1896 PREFIX is the class of label and NUM is the number within the class. */
1898 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1899 asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
1901 /* This is how to store into the string LABEL
1902 the symbol_ref name of an internal numbered label where
1903 PREFIX is the class of label and NUM is the number within the class.
1904 This is suitable for output with `assemble_name'. */
1906 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1907 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
1909 /* This is how to output a `long double' extended real constant. */
1911 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1913 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1914 fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \
1917 /* This is how to output an assembler line defining a `double' constant. */
1919 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1920 do { char dstr[30]; \
1921 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1922 fprintf (FILE, "\t.double 0r%s\n", dstr); \
1925 /* This is how to output an assembler line defining a `float' constant. */
1927 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1929 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1930 fprintf (FILE, "\t.long 0x%lx\n", l); \
1933 /* This is how to output an assembler line defining an `int' constant. */
1935 #define ASM_OUTPUT_INT(FILE,VALUE) \
1936 ( fprintf (FILE, "\t.long "), \
1937 output_addr_const (FILE, (VALUE)), \
1938 fprintf (FILE, "\n"))
1940 /* Likewise for `char' and `short' constants. */
1942 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1943 ( fprintf (FILE, "\t.word "), \
1944 output_addr_const (FILE, (VALUE)), \
1945 fprintf (FILE, "\n"))
1947 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1948 ( fprintf (FILE, "\t.byte "), \
1949 output_addr_const (FILE, (VALUE)), \
1950 fprintf (FILE, "\n"))
1952 /* This is how to output an assembler line for a numeric constant byte. */
1954 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1955 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1957 /* This is how to output an insn to push a register on the stack.
1958 It need not be very fast code. */
1960 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1961 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1963 /* This is how to output an insn to pop a register from the stack.
1964 It need not be very fast code. */
1966 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1967 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1969 /* This is how to output an element of a case-vector that is absolute.
1970 (The 68000 does not use such vectors,
1971 but we must define this macro anyway.) */
1973 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1974 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1976 /* This is how to output an element of a case-vector that is relative. */
1978 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1979 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1981 /* This is how to output an assembler line
1982 that says to advance the location counter
1983 to a multiple of 2**LOG bytes. */
1985 /* We don't have a way to align to more than a two-byte boundary, so do the
1986 best we can and don't complain. */
1987 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1989 fprintf (FILE, "\t.even\n");
1991 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1992 fprintf (FILE, "\t.skip %u\n", (SIZE))
1994 /* This says how to output an assembler line
1995 to define a global common symbol. */
1997 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1998 ( fputs (".comm ", (FILE)), \
1999 assemble_name ((FILE), (NAME)), \
2000 fprintf ((FILE), ",%u\n", (ROUNDED)))
2002 /* This says how to output an assembler line
2003 to define a local common symbol. */
2005 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2006 ( fputs (".lcomm ", (FILE)), \
2007 assemble_name ((FILE), (NAME)), \
2008 fprintf ((FILE), ",%u\n", (ROUNDED)))
2010 /* Store in OUTPUT a string (made with alloca) containing
2011 an assembler-name for a local static variable named NAME.
2012 LABELNO is an integer which is different for each call. */
2014 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2015 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2016 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2018 /* Define the parentheses used to group arithmetic operations
2019 in assembler code. */
2021 #define ASM_OPEN_PAREN "("
2022 #define ASM_CLOSE_PAREN ")"
2024 /* Define results of standard character escape sequences. */
2025 #define TARGET_BELL 007
2026 #define TARGET_BS 010
2027 #define TARGET_TAB 011
2028 #define TARGET_NEWLINE 012
2029 #define TARGET_VT 013
2030 #define TARGET_FF 014
2031 #define TARGET_CR 015
2033 /* Output a float value (represented as a C double) as an immediate operand.
2034 This macro is a 68k-specific macro. */
2036 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
2041 REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \
2042 asm_fprintf ((FILE), "%I0r%s", dstr); \
2047 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2048 asm_fprintf ((FILE), "%I0x%lx", l); \
2052 /* Output a double value (represented as a C double) as an immediate operand.
2053 This macro is a 68k-specific macro. */
2054 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
2055 do { char dstr[30]; \
2056 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
2057 asm_fprintf (FILE, "%I0r%s", dstr); \
2060 /* Note, long double immediate operands are not actually
2061 generated by m68k.md. */
2062 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
2063 do { char dstr[30]; \
2064 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
2065 asm_fprintf (FILE, "%I0r%s", dstr); \
2068 /* Print operand X (an rtx) in assembler syntax to file FILE.
2069 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2070 For `%' followed by punctuation, CODE is the punctuation and X is null.
2072 On the 68000, we use several CODE characters:
2073 '.' for dot needed in Motorola-style opcode names.
2074 '-' for an operand pushing on the stack:
2075 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2076 '+' for an operand pushing on the stack:
2077 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2078 '@' for a reference to the top word on the stack:
2079 sp@, (sp) or (%sp) depending on the style of syntax.
2080 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2081 but & in SGS syntax).
2082 '!' for the fpcr register (used in some float-to-fixed conversions).
2083 '$' for the letter `s' in an op code, but only on the 68040.
2084 '&' for the letter `d' in an op code, but only on the 68040.
2085 '/' for register prefix needed by longlong.h.
2087 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2088 'd' to force memory addressing to be absolute, not relative.
2089 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2090 'o' for operands to go directly to output_operand_address (bypassing
2091 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2092 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2093 than directly). Second part of 'y' below.
2094 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2095 or print pair of registers as rx:ry.
2096 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2097 CONST_DOUBLE's as SunFPA constant RAM registers if
2098 possible, so it should not be used except for the SunFPA. */
2100 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2101 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
2102 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
2103 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
2105 /* A C compound statement to output to stdio stream STREAM the
2106 assembler syntax for an instruction operand X. X is an RTL
2109 CODE is a value that can be used to specify one of several ways
2110 of printing the operand. It is used when identical operands
2111 must be printed differently depending on the context. CODE
2112 comes from the `%' specification that was used to request
2113 printing of the operand. If the specification was just `%DIGIT'
2114 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2115 is the ASCII code for LTR.
2117 If X is a register, this macro should print the register's name.
2118 The names can be found in an array `reg_names' whose type is
2119 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2121 When the machine description has a specification `%PUNCT' (a `%'
2122 followed by a punctuation character), this macro is called with
2123 a null pointer for X and the punctuation character for CODE.
2125 See m68k.c for the m68k specific codes. */
2127 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2129 /* A C compound statement to output to stdio stream STREAM the
2130 assembler syntax for an instruction operand that is a memory
2131 reference whose address is ADDR. ADDR is an RTL expression.
2133 On some machines, the syntax for a symbolic address depends on
2134 the section that the address refers to. On these machines,
2135 define the macro `ENCODE_SECTION_INFO' to store the information
2136 into the `symbol_ref', and then check for it here. */
2138 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2140 /* Define functions defined in aux-output.c and used in templates. */
2142 extern char *output_move_const_into_data_reg ();
2143 extern char *output_move_simode_const ();
2144 extern char *output_move_simode ();
2145 extern char *output_move_himode ();
2146 extern char *output_move_qimode ();
2147 extern char *output_move_stricthi ();
2148 extern char *output_move_strictqi ();
2149 extern char *output_move_double ();
2150 extern char *output_move_const_single ();
2151 extern char *output_move_const_double ();
2152 extern char *output_btst ();
2153 extern char *output_scc_di ();
2154 extern char *output_addsi3 ();
2155 extern char *output_andsi3 ();
2156 extern char *output_iorsi3 ();
2157 extern char *output_xorsi3 ();
2158 extern void output_dbcc_and_branch ();
2159 extern int const_uint32_operand ();
2160 extern int const_sint32_operand ();
2161 extern int floating_exact_log2 ();
2162 extern int not_sp_operand ();
2163 extern int valid_dbcc_comparison_p ();
2164 extern int extend_operator ();
2165 extern int flags_in_68881 ();
2166 extern int strict_low_part_peephole_ok ();
2168 /* Variables in m68k.c */
2169 extern const char *m68k_align_loops_string;
2170 extern const char *m68k_align_jumps_string;
2171 extern const char *m68k_align_funcs_string;
2172 extern int m68k_align_loops;
2173 extern int m68k_align_jumps;
2174 extern int m68k_align_funcs;
2175 extern int m68k_last_compare_had_fp_operands;
2177 /* Functions from m68k.c used in macros. */
2178 extern int symbolic_operand ();
2179 extern int const_int_cost ();
2180 extern int standard_68881_constant_p ();
2181 extern int standard_sun_fpa_constant_p ();
2182 extern void output_function_prologue ();
2183 extern void output_function_epilogue ();
2184 extern int use_return_insn ();
2185 extern void print_operand_address ();
2186 extern void print_operand ();
2187 extern void notice_update_cc ();
2188 extern void finalize_pic ();
2189 extern void override_options ();
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