1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
46 #include "sched-int.h"
47 #include "insn-codes.h"
50 enum reg_class regno_reg_class[] =
52 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
53 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
54 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
55 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
56 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
57 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
62 /* The minimum number of integer registers that we want to save with the
63 movem instruction. Using two movel instructions instead of a single
64 moveml is about 15% faster for the 68020 and 68030 at no expense in
66 #define MIN_MOVEM_REGS 3
68 /* The minimum number of floating point registers that we want to save
69 with the fmovem instruction. */
70 #define MIN_FMOVEM_REGS 1
72 /* Structure describing stack frame layout. */
75 /* Stack pointer to frame pointer offset. */
78 /* Offset of FPU registers. */
79 HOST_WIDE_INT foffset;
81 /* Frame size in bytes (rounded up). */
84 /* Data and address register. */
86 unsigned int reg_mask;
90 unsigned int fpu_mask;
92 /* Offsets relative to ARG_POINTER. */
93 HOST_WIDE_INT frame_pointer_offset;
94 HOST_WIDE_INT stack_pointer_offset;
96 /* Function which the above information refers to. */
100 /* Current frame information calculated by m68k_compute_frame_layout(). */
101 static struct m68k_frame current_frame;
103 /* Structure describing an m68k address.
105 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
106 with null fields evaluating to 0. Here:
108 - BASE satisfies m68k_legitimate_base_reg_p
109 - INDEX satisfies m68k_legitimate_index_reg_p
110 - OFFSET satisfies m68k_legitimate_constant_address_p
112 INDEX is either HImode or SImode. The other fields are SImode.
114 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
115 the address is (BASE)+. */
116 struct m68k_address {
124 static int m68k_sched_adjust_cost (rtx, rtx, rtx, int);
125 static int m68k_sched_issue_rate (void);
126 static int m68k_sched_variable_issue (FILE *, int, rtx, int);
127 static void m68k_sched_md_init_global (FILE *, int, int);
128 static void m68k_sched_md_finish_global (FILE *, int);
129 static void m68k_sched_md_init (FILE *, int, int);
130 static void m68k_sched_dfa_pre_advance_cycle (void);
131 static void m68k_sched_dfa_post_advance_cycle (void);
132 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
134 static bool m68k_can_eliminate (const int, const int);
135 static void m68k_conditional_register_usage (void);
136 static bool m68k_legitimate_address_p (enum machine_mode, rtx, bool);
137 static bool m68k_handle_option (size_t, const char *, int);
138 static void m68k_option_override (void);
139 static rtx find_addr_reg (rtx);
140 static const char *singlemove_string (rtx *);
141 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
142 HOST_WIDE_INT, tree);
143 static rtx m68k_struct_value_rtx (tree, int);
144 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
145 tree args, int flags,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
149 static bool m68k_ok_for_sibcall_p (tree, tree);
150 static bool m68k_tls_symbol_p (rtx);
151 static rtx m68k_legitimize_address (rtx, rtx, enum machine_mode);
152 static bool m68k_rtx_costs (rtx, int, int, int *, bool);
153 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
154 static bool m68k_return_in_memory (const_tree, const_tree);
156 static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
157 static void m68k_trampoline_init (rtx, tree, rtx);
158 static int m68k_return_pops_args (tree, tree, int);
159 static rtx m68k_delegitimize_address (rtx);
160 static void m68k_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
162 static rtx m68k_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
166 /* Specify the identification number of the library being built */
167 const char *m68k_library_id_string = "_current_shared_library_a5_offset_";
169 /* Initialize the GCC target structure. */
171 #if INT_OP_GROUP == INT_OP_DOT_WORD
172 #undef TARGET_ASM_ALIGNED_HI_OP
173 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
176 #if INT_OP_GROUP == INT_OP_NO_DOT
177 #undef TARGET_ASM_BYTE_OP
178 #define TARGET_ASM_BYTE_OP "\tbyte\t"
179 #undef TARGET_ASM_ALIGNED_HI_OP
180 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
181 #undef TARGET_ASM_ALIGNED_SI_OP
182 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
185 #if INT_OP_GROUP == INT_OP_DC
186 #undef TARGET_ASM_BYTE_OP
187 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
188 #undef TARGET_ASM_ALIGNED_HI_OP
189 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
190 #undef TARGET_ASM_ALIGNED_SI_OP
191 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
194 #undef TARGET_ASM_UNALIGNED_HI_OP
195 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
196 #undef TARGET_ASM_UNALIGNED_SI_OP
197 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
199 #undef TARGET_ASM_OUTPUT_MI_THUNK
200 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
201 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
202 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
204 #undef TARGET_ASM_FILE_START_APP_OFF
205 #define TARGET_ASM_FILE_START_APP_OFF true
207 #undef TARGET_LEGITIMIZE_ADDRESS
208 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
210 #undef TARGET_SCHED_ADJUST_COST
211 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
213 #undef TARGET_SCHED_ISSUE_RATE
214 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
216 #undef TARGET_SCHED_VARIABLE_ISSUE
217 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
219 #undef TARGET_SCHED_INIT_GLOBAL
220 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
222 #undef TARGET_SCHED_FINISH_GLOBAL
223 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
225 #undef TARGET_SCHED_INIT
226 #define TARGET_SCHED_INIT m68k_sched_md_init
228 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
229 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
231 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
232 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
234 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
235 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
236 m68k_sched_first_cycle_multipass_dfa_lookahead
238 #undef TARGET_HANDLE_OPTION
239 #define TARGET_HANDLE_OPTION m68k_handle_option
241 #undef TARGET_OPTION_OVERRIDE
242 #define TARGET_OPTION_OVERRIDE m68k_option_override
244 #undef TARGET_RTX_COSTS
245 #define TARGET_RTX_COSTS m68k_rtx_costs
247 #undef TARGET_ATTRIBUTE_TABLE
248 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
250 #undef TARGET_PROMOTE_PROTOTYPES
251 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
253 #undef TARGET_STRUCT_VALUE_RTX
254 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
256 #undef TARGET_CANNOT_FORCE_CONST_MEM
257 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
259 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
260 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
262 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
263 #undef TARGET_RETURN_IN_MEMORY
264 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
268 #undef TARGET_HAVE_TLS
269 #define TARGET_HAVE_TLS (true)
271 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
272 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
275 #undef TARGET_LEGITIMATE_ADDRESS_P
276 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
278 #undef TARGET_CAN_ELIMINATE
279 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
281 #undef TARGET_CONDITIONAL_REGISTER_USAGE
282 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
284 #undef TARGET_TRAMPOLINE_INIT
285 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
287 #undef TARGET_RETURN_POPS_ARGS
288 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
290 #undef TARGET_DELEGITIMIZE_ADDRESS
291 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
293 #undef TARGET_FUNCTION_ARG
294 #define TARGET_FUNCTION_ARG m68k_function_arg
296 #undef TARGET_FUNCTION_ARG_ADVANCE
297 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
299 static const struct attribute_spec m68k_attribute_table[] =
301 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
302 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
303 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
304 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
305 { NULL, 0, 0, false, false, false, NULL }
308 struct gcc_target targetm = TARGET_INITIALIZER;
310 /* Base flags for 68k ISAs. */
311 #define FL_FOR_isa_00 FL_ISA_68000
312 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
313 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
314 generated 68881 code for 68020 and 68030 targets unless explicitly told
316 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
317 | FL_BITFIELD | FL_68881)
318 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
319 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
321 /* Base flags for ColdFire ISAs. */
322 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
323 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
324 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
325 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
326 /* ISA_C is not upwardly compatible with ISA_B. */
327 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
331 /* Traditional 68000 instruction sets. */
337 /* ColdFire instruction set variants. */
345 /* Information about one of the -march, -mcpu or -mtune arguments. */
346 struct m68k_target_selection
348 /* The argument being described. */
351 /* For -mcpu, this is the device selected by the option.
352 For -mtune and -march, it is a representative device
353 for the microarchitecture or ISA respectively. */
354 enum target_device device;
356 /* The M68K_DEVICE fields associated with DEVICE. See the comment
357 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
359 enum uarch_type microarch;
364 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
365 static const struct m68k_target_selection all_devices[] =
367 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
368 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
369 #include "m68k-devices.def"
371 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
374 /* A list of all ISAs, mapping each one to a representative device.
375 Used for -march selection. */
376 static const struct m68k_target_selection all_isas[] =
378 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
379 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
380 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
381 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
382 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
383 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
384 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
385 { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a
387 { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus
389 { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
390 { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c
392 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
395 /* A list of all microarchitectures, mapping each one to a representative
396 device. Used for -mtune selection. */
397 static const struct m68k_target_selection all_microarchs[] =
399 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
400 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
401 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
402 { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 },
403 { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 },
404 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
405 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
406 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
407 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
408 { "cfv1", mcf51qe, NULL, ucfv1, isa_c, FL_FOR_isa_c },
409 { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a },
410 { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a
412 { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
413 { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b
417 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
420 /* The entries associated with the -mcpu, -march and -mtune settings,
421 or null for options that have not been used. */
422 const struct m68k_target_selection *m68k_cpu_entry;
423 const struct m68k_target_selection *m68k_arch_entry;
424 const struct m68k_target_selection *m68k_tune_entry;
426 /* Which CPU we are generating code for. */
427 enum target_device m68k_cpu;
429 /* Which microarchitecture to tune for. */
430 enum uarch_type m68k_tune;
432 /* Which FPU to use. */
433 enum fpu_type m68k_fpu;
435 /* The set of FL_* flags that apply to the target processor. */
436 unsigned int m68k_cpu_flags;
438 /* The set of FL_* flags that apply to the processor to be tuned for. */
439 unsigned int m68k_tune_flags;
441 /* Asm templates for calling or jumping to an arbitrary symbolic address,
442 or NULL if such calls or jumps are not supported. The address is held
444 const char *m68k_symbolic_call;
445 const char *m68k_symbolic_jump;
447 /* Enum variable that corresponds to m68k_symbolic_call values. */
448 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
451 /* See whether TABLE has an entry with name NAME. Return true and
452 store the entry in *ENTRY if so, otherwise return false and
453 leave *ENTRY alone. */
456 m68k_find_selection (const struct m68k_target_selection **entry,
457 const struct m68k_target_selection *table,
462 for (i = 0; table[i].name; i++)
463 if (strcmp (table[i].name, name) == 0)
471 /* Implement TARGET_HANDLE_OPTION. */
474 m68k_handle_option (size_t code, const char *arg, int value)
479 return m68k_find_selection (&m68k_arch_entry, all_isas, arg);
482 return m68k_find_selection (&m68k_cpu_entry, all_devices, arg);
485 return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg);
488 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206");
491 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e");
494 return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x");
497 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307");
500 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407");
503 return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x");
507 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000");
510 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010");
514 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020");
517 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
519 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
522 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
524 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
527 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030");
530 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040");
533 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060");
536 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302");
540 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332");
542 case OPT_mshared_library_id_:
543 if (value > MAX_LIBRARY_ID)
544 error ("-mshared-library-id=%s is not between 0 and %d",
545 arg, MAX_LIBRARY_ID);
549 asprintf (&tmp, "%d", (value * -4) - 4);
550 m68k_library_id_string = tmp;
559 /* Implement TARGET_OPTION_OVERRIDE. */
562 m68k_option_override (void)
564 const struct m68k_target_selection *entry;
565 unsigned long target_mask;
573 -march=ARCH should generate code that runs any processor
574 implementing architecture ARCH. -mcpu=CPU should override -march
575 and should generate code that runs on processor CPU, making free
576 use of any instructions that CPU understands. -mtune=UARCH applies
577 on top of -mcpu or -march and optimizes the code for UARCH. It does
578 not change the target architecture. */
581 /* Complain if the -march setting is for a different microarchitecture,
582 or includes flags that the -mcpu setting doesn't. */
584 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
585 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
586 warning (0, "-mcpu=%s conflicts with -march=%s",
587 m68k_cpu_entry->name, m68k_arch_entry->name);
589 entry = m68k_cpu_entry;
592 entry = m68k_arch_entry;
595 entry = all_devices + TARGET_CPU_DEFAULT;
597 m68k_cpu_flags = entry->flags;
599 /* Use the architecture setting to derive default values for
603 /* ColdFire is lenient about alignment. */
604 if (!TARGET_COLDFIRE)
605 target_mask |= MASK_STRICT_ALIGNMENT;
607 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
608 target_mask |= MASK_BITFIELD;
609 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
610 target_mask |= MASK_CF_HWDIV;
611 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
612 target_mask |= MASK_HARD_FLOAT;
613 target_flags |= target_mask & ~target_flags_explicit;
615 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
616 m68k_cpu = entry->device;
619 m68k_tune = m68k_tune_entry->microarch;
620 m68k_tune_flags = m68k_tune_entry->flags;
622 #ifdef M68K_DEFAULT_TUNE
623 else if (!m68k_cpu_entry && !m68k_arch_entry)
625 enum target_device dev;
626 dev = all_microarchs[M68K_DEFAULT_TUNE].device;
627 m68k_tune_flags = all_devices[dev]->flags;
632 m68k_tune = entry->microarch;
633 m68k_tune_flags = entry->flags;
636 /* Set the type of FPU. */
637 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
638 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
641 /* Sanity check to ensure that msep-data and mid-sahred-library are not
642 * both specified together. Doing so simply doesn't make sense.
644 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
645 error ("cannot specify both -msep-data and -mid-shared-library");
647 /* If we're generating code for a separate A5 relative data segment,
648 * we've got to enable -fPIC as well. This might be relaxable to
649 * -fpic but it hasn't been tested properly.
651 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
654 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
655 error if the target does not support them. */
656 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
657 error ("-mpcrel -fPIC is not currently supported on selected cpu");
659 /* ??? A historic way of turning on pic, or is this intended to
660 be an embedded thing that doesn't have the same name binding
661 significance that it does on hosted ELF systems? */
662 if (TARGET_PCREL && flag_pic == 0)
667 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
669 m68k_symbolic_jump = "jra %a0";
671 else if (TARGET_ID_SHARED_LIBRARY)
672 /* All addresses must be loaded from the GOT. */
674 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
677 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
679 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
682 /* No unconditional long branch */;
683 else if (TARGET_PCREL)
684 m68k_symbolic_jump = "bra%.l %c0";
686 m68k_symbolic_jump = "bra%.l %p0";
687 /* Turn off function cse if we are doing PIC. We always want
688 function call to be done as `bsr foo@PLTPC'. */
689 /* ??? It's traditional to do this for -mpcrel too, but it isn't
690 clear how intentional that is. */
691 flag_no_function_cse = 1;
694 switch (m68k_symbolic_call_var)
696 case M68K_SYMBOLIC_CALL_JSR:
697 m68k_symbolic_call = "jsr %a0";
700 case M68K_SYMBOLIC_CALL_BSR_C:
701 m68k_symbolic_call = "bsr%.l %c0";
704 case M68K_SYMBOLIC_CALL_BSR_P:
705 m68k_symbolic_call = "bsr%.l %p0";
708 case M68K_SYMBOLIC_CALL_NONE:
709 gcc_assert (m68k_symbolic_call == NULL);
716 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
717 if (align_labels > 2)
719 warning (0, "-falign-labels=%d is not supported", align_labels);
724 warning (0, "-falign-loops=%d is not supported", align_loops);
729 SUBTARGET_OVERRIDE_OPTIONS;
731 /* Setup scheduling options. */
733 m68k_sched_cpu = CPU_CFV1;
735 m68k_sched_cpu = CPU_CFV2;
737 m68k_sched_cpu = CPU_CFV3;
739 m68k_sched_cpu = CPU_CFV4;
742 m68k_sched_cpu = CPU_UNKNOWN;
743 flag_schedule_insns = 0;
744 flag_schedule_insns_after_reload = 0;
745 flag_modulo_sched = 0;
748 if (m68k_sched_cpu != CPU_UNKNOWN)
750 if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0)
751 m68k_sched_mac = MAC_CF_EMAC;
752 else if ((m68k_cpu_flags & FL_CF_MAC) != 0)
753 m68k_sched_mac = MAC_CF_MAC;
755 m68k_sched_mac = MAC_NO;
759 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
760 given argument and NAME is the argument passed to -mcpu. Return NULL
761 if -mcpu was not passed. */
764 m68k_cpp_cpu_ident (const char *prefix)
768 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
771 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
772 given argument and NAME is the name of the representative device for
773 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
776 m68k_cpp_cpu_family (const char *prefix)
780 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
783 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
784 "interrupt_handler" attribute and interrupt_thread if FUNC has an
785 "interrupt_thread" attribute. Otherwise, return
786 m68k_fk_normal_function. */
788 enum m68k_function_kind
789 m68k_get_function_kind (tree func)
793 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
795 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
797 return m68k_fk_interrupt_handler;
799 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
801 return m68k_fk_interrupt_handler;
803 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
805 return m68k_fk_interrupt_thread;
807 return m68k_fk_normal_function;
810 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
811 struct attribute_spec.handler. */
813 m68k_handle_fndecl_attribute (tree *node, tree name,
814 tree args ATTRIBUTE_UNUSED,
815 int flags ATTRIBUTE_UNUSED,
818 if (TREE_CODE (*node) != FUNCTION_DECL)
820 warning (OPT_Wattributes, "%qE attribute only applies to functions",
822 *no_add_attrs = true;
825 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
827 error ("multiple interrupt attributes not allowed");
828 *no_add_attrs = true;
832 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
834 error ("interrupt_thread is available only on fido");
835 *no_add_attrs = true;
842 m68k_compute_frame_layout (void)
846 enum m68k_function_kind func_kind =
847 m68k_get_function_kind (current_function_decl);
848 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
849 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
851 /* Only compute the frame once per function.
852 Don't cache information until reload has been completed. */
853 if (current_frame.funcdef_no == current_function_funcdef_no
857 current_frame.size = (get_frame_size () + 3) & -4;
861 /* Interrupt thread does not need to save any register. */
862 if (!interrupt_thread)
863 for (regno = 0; regno < 16; regno++)
864 if (m68k_save_reg (regno, interrupt_handler))
866 mask |= 1 << (regno - D0_REG);
869 current_frame.offset = saved * 4;
870 current_frame.reg_no = saved;
871 current_frame.reg_mask = mask;
873 current_frame.foffset = 0;
875 if (TARGET_HARD_FLOAT)
877 /* Interrupt thread does not need to save any register. */
878 if (!interrupt_thread)
879 for (regno = 16; regno < 24; regno++)
880 if (m68k_save_reg (regno, interrupt_handler))
882 mask |= 1 << (regno - FP0_REG);
885 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
886 current_frame.offset += current_frame.foffset;
888 current_frame.fpu_no = saved;
889 current_frame.fpu_mask = mask;
891 /* Remember what function this frame refers to. */
892 current_frame.funcdef_no = current_function_funcdef_no;
895 /* Worker function for TARGET_CAN_ELIMINATE. */
898 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
900 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
904 m68k_initial_elimination_offset (int from, int to)
907 /* The arg pointer points 8 bytes before the start of the arguments,
908 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
909 frame pointer in most frames. */
910 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
911 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
912 return argptr_offset;
914 m68k_compute_frame_layout ();
916 gcc_assert (to == STACK_POINTER_REGNUM);
919 case ARG_POINTER_REGNUM:
920 return current_frame.offset + current_frame.size - argptr_offset;
921 case FRAME_POINTER_REGNUM:
922 return current_frame.offset + current_frame.size;
928 /* Refer to the array `regs_ever_live' to determine which registers
929 to save; `regs_ever_live[I]' is nonzero if register number I
930 is ever used in the function. This function is responsible for
931 knowing which registers should not be saved even if used.
932 Return true if we need to save REGNO. */
935 m68k_save_reg (unsigned int regno, bool interrupt_handler)
937 if (flag_pic && regno == PIC_REG)
939 if (crtl->saves_all_registers)
941 if (crtl->uses_pic_offset_table)
943 /* Reload may introduce constant pool references into a function
944 that thitherto didn't need a PIC register. Note that the test
945 above will not catch that case because we will only set
946 crtl->uses_pic_offset_table when emitting
947 the address reloads. */
948 if (crtl->uses_const_pool)
952 if (crtl->calls_eh_return)
957 unsigned int test = EH_RETURN_DATA_REGNO (i);
958 if (test == INVALID_REGNUM)
965 /* Fixed regs we never touch. */
966 if (fixed_regs[regno])
969 /* The frame pointer (if it is such) is handled specially. */
970 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
973 /* Interrupt handlers must also save call_used_regs
974 if they are live or when calling nested functions. */
975 if (interrupt_handler)
977 if (df_regs_ever_live_p (regno))
980 if (!current_function_is_leaf && call_used_regs[regno])
984 /* Never need to save registers that aren't touched. */
985 if (!df_regs_ever_live_p (regno))
988 /* Otherwise save everything that isn't call-clobbered. */
989 return !call_used_regs[regno];
992 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
993 the lowest memory address. COUNT is the number of registers to be
994 moved, with register REGNO + I being moved if bit I of MASK is set.
995 STORE_P specifies the direction of the move and ADJUST_STACK_P says
996 whether or not this is pre-decrement (if STORE_P) or post-increment
997 (if !STORE_P) operation. */
1000 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
1001 unsigned int count, unsigned int regno,
1002 unsigned int mask, bool store_p, bool adjust_stack_p)
1005 rtx body, addr, src, operands[2];
1006 enum machine_mode mode;
1008 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
1009 mode = reg_raw_mode[regno];
1014 src = plus_constant (base, (count
1015 * GET_MODE_SIZE (mode)
1016 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
1017 XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src);
1020 for (; mask != 0; mask >>= 1, regno++)
1023 addr = plus_constant (base, offset);
1024 operands[!store_p] = gen_frame_mem (mode, addr);
1025 operands[store_p] = gen_rtx_REG (mode, regno);
1026 XVECEXP (body, 0, i++)
1027 = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
1028 offset += GET_MODE_SIZE (mode);
1030 gcc_assert (i == XVECLEN (body, 0));
1032 return emit_insn (body);
1035 /* Make INSN a frame-related instruction. */
1038 m68k_set_frame_related (rtx insn)
1043 RTX_FRAME_RELATED_P (insn) = 1;
1044 body = PATTERN (insn);
1045 if (GET_CODE (body) == PARALLEL)
1046 for (i = 0; i < XVECLEN (body, 0); i++)
1047 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
1050 /* Emit RTL for the "prologue" define_expand. */
1053 m68k_expand_prologue (void)
1055 HOST_WIDE_INT fsize_with_regs;
1056 rtx limit, src, dest;
1058 m68k_compute_frame_layout ();
1060 /* If the stack limit is a symbol, we can check it here,
1061 before actually allocating the space. */
1062 if (crtl->limit_stack
1063 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
1065 limit = plus_constant (stack_limit_rtx, current_frame.size + 4);
1066 if (!LEGITIMATE_CONSTANT_P (limit))
1068 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
1069 limit = gen_rtx_REG (Pmode, D0_REG);
1071 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode,
1072 stack_pointer_rtx, limit),
1073 stack_pointer_rtx, limit,
1077 fsize_with_regs = current_frame.size;
1078 if (TARGET_COLDFIRE)
1080 /* ColdFire's move multiple instructions do not allow pre-decrement
1081 addressing. Add the size of movem saves to the initial stack
1082 allocation instead. */
1083 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1084 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1085 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1086 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1089 if (frame_pointer_needed)
1091 if (fsize_with_regs == 0 && TUNE_68040)
1093 /* On the 68040, two separate moves are faster than link.w 0. */
1094 dest = gen_frame_mem (Pmode,
1095 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1096 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
1097 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
1098 stack_pointer_rtx));
1100 else if (fsize_with_regs < 0x8000 || TARGET_68020)
1101 m68k_set_frame_related
1102 (emit_insn (gen_link (frame_pointer_rtx,
1103 GEN_INT (-4 - fsize_with_regs))));
1106 m68k_set_frame_related
1107 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
1108 m68k_set_frame_related
1109 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1111 GEN_INT (-fsize_with_regs))));
1114 /* If the frame pointer is needed, emit a special barrier that
1115 will prevent the scheduler from moving stores to the frame
1116 before the stack adjustment. */
1117 emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx));
1119 else if (fsize_with_regs != 0)
1120 m68k_set_frame_related
1121 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1123 GEN_INT (-fsize_with_regs))));
1125 if (current_frame.fpu_mask)
1127 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
1129 m68k_set_frame_related
1130 (m68k_emit_movem (stack_pointer_rtx,
1131 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
1132 current_frame.fpu_no, FP0_REG,
1133 current_frame.fpu_mask, true, true));
1138 /* If we're using moveml to save the integer registers,
1139 the stack pointer will point to the bottom of the moveml
1140 save area. Find the stack offset of the first FP register. */
1141 if (current_frame.reg_no < MIN_MOVEM_REGS)
1144 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1145 m68k_set_frame_related
1146 (m68k_emit_movem (stack_pointer_rtx, offset,
1147 current_frame.fpu_no, FP0_REG,
1148 current_frame.fpu_mask, true, false));
1152 /* If the stack limit is not a symbol, check it here.
1153 This has the disadvantage that it may be too late... */
1154 if (crtl->limit_stack)
1156 if (REG_P (stack_limit_rtx))
1157 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx,
1159 stack_pointer_rtx, stack_limit_rtx,
1162 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1163 warning (0, "stack limit expression is not supported");
1166 if (current_frame.reg_no < MIN_MOVEM_REGS)
1168 /* Store each register separately in the same order moveml does. */
1171 for (i = 16; i-- > 0; )
1172 if (current_frame.reg_mask & (1 << i))
1174 src = gen_rtx_REG (SImode, D0_REG + i);
1175 dest = gen_frame_mem (SImode,
1176 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1177 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1182 if (TARGET_COLDFIRE)
1183 /* The required register save space has already been allocated.
1184 The first register should be stored at (%sp). */
1185 m68k_set_frame_related
1186 (m68k_emit_movem (stack_pointer_rtx, 0,
1187 current_frame.reg_no, D0_REG,
1188 current_frame.reg_mask, true, false));
1190 m68k_set_frame_related
1191 (m68k_emit_movem (stack_pointer_rtx,
1192 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1193 current_frame.reg_no, D0_REG,
1194 current_frame.reg_mask, true, true));
1197 if (!TARGET_SEP_DATA
1198 && crtl->uses_pic_offset_table)
1199 emit_insn (gen_load_got (pic_offset_table_rtx));
1202 /* Return true if a simple (return) instruction is sufficient for this
1203 instruction (i.e. if no epilogue is needed). */
1206 m68k_use_return_insn (void)
1208 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1211 m68k_compute_frame_layout ();
1212 return current_frame.offset == 0;
1215 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1216 SIBCALL_P says which.
1218 The function epilogue should not depend on the current stack pointer!
1219 It should use the frame pointer only, if there is a frame pointer.
1220 This is mandatory because of alloca; we also take advantage of it to
1221 omit stack adjustments before returning. */
1224 m68k_expand_epilogue (bool sibcall_p)
1226 HOST_WIDE_INT fsize, fsize_with_regs;
1227 bool big, restore_from_sp;
1229 m68k_compute_frame_layout ();
1231 fsize = current_frame.size;
1233 restore_from_sp = false;
1235 /* FIXME : current_function_is_leaf below is too strong.
1236 What we really need to know there is if there could be pending
1237 stack adjustment needed at that point. */
1238 restore_from_sp = (!frame_pointer_needed
1239 || (!cfun->calls_alloca
1240 && current_function_is_leaf));
1242 /* fsize_with_regs is the size we need to adjust the sp when
1243 popping the frame. */
1244 fsize_with_regs = fsize;
1245 if (TARGET_COLDFIRE && restore_from_sp)
1247 /* ColdFire's move multiple instructions do not allow post-increment
1248 addressing. Add the size of movem loads to the final deallocation
1250 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1251 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1252 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1253 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1256 if (current_frame.offset + fsize >= 0x8000
1258 && (current_frame.reg_mask || current_frame.fpu_mask))
1261 && (current_frame.reg_no >= MIN_MOVEM_REGS
1262 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1264 /* ColdFire's move multiple instructions do not support the
1265 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1266 stack-based restore. */
1267 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1268 GEN_INT (-(current_frame.offset + fsize)));
1269 emit_insn (gen_addsi3 (stack_pointer_rtx,
1270 gen_rtx_REG (Pmode, A1_REG),
1271 frame_pointer_rtx));
1272 restore_from_sp = true;
1276 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1282 if (current_frame.reg_no < MIN_MOVEM_REGS)
1284 /* Restore each register separately in the same order moveml does. */
1286 HOST_WIDE_INT offset;
1288 offset = current_frame.offset + fsize;
1289 for (i = 0; i < 16; i++)
1290 if (current_frame.reg_mask & (1 << i))
1296 /* Generate the address -OFFSET(%fp,%a1.l). */
1297 addr = gen_rtx_REG (Pmode, A1_REG);
1298 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1299 addr = plus_constant (addr, -offset);
1301 else if (restore_from_sp)
1302 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1304 addr = plus_constant (frame_pointer_rtx, -offset);
1305 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1306 gen_frame_mem (SImode, addr));
1307 offset -= GET_MODE_SIZE (SImode);
1310 else if (current_frame.reg_mask)
1313 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1314 gen_rtx_REG (Pmode, A1_REG),
1316 -(current_frame.offset + fsize),
1317 current_frame.reg_no, D0_REG,
1318 current_frame.reg_mask, false, false);
1319 else if (restore_from_sp)
1320 m68k_emit_movem (stack_pointer_rtx, 0,
1321 current_frame.reg_no, D0_REG,
1322 current_frame.reg_mask, false,
1325 m68k_emit_movem (frame_pointer_rtx,
1326 -(current_frame.offset + fsize),
1327 current_frame.reg_no, D0_REG,
1328 current_frame.reg_mask, false, false);
1331 if (current_frame.fpu_no > 0)
1334 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1335 gen_rtx_REG (Pmode, A1_REG),
1337 -(current_frame.foffset + fsize),
1338 current_frame.fpu_no, FP0_REG,
1339 current_frame.fpu_mask, false, false);
1340 else if (restore_from_sp)
1342 if (TARGET_COLDFIRE)
1346 /* If we used moveml to restore the integer registers, the
1347 stack pointer will still point to the bottom of the moveml
1348 save area. Find the stack offset of the first FP
1350 if (current_frame.reg_no < MIN_MOVEM_REGS)
1353 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1354 m68k_emit_movem (stack_pointer_rtx, offset,
1355 current_frame.fpu_no, FP0_REG,
1356 current_frame.fpu_mask, false, false);
1359 m68k_emit_movem (stack_pointer_rtx, 0,
1360 current_frame.fpu_no, FP0_REG,
1361 current_frame.fpu_mask, false, true);
1364 m68k_emit_movem (frame_pointer_rtx,
1365 -(current_frame.foffset + fsize),
1366 current_frame.fpu_no, FP0_REG,
1367 current_frame.fpu_mask, false, false);
1370 if (frame_pointer_needed)
1371 emit_insn (gen_unlink (frame_pointer_rtx));
1372 else if (fsize_with_regs)
1373 emit_insn (gen_addsi3 (stack_pointer_rtx,
1375 GEN_INT (fsize_with_regs)));
1377 if (crtl->calls_eh_return)
1378 emit_insn (gen_addsi3 (stack_pointer_rtx,
1380 EH_RETURN_STACKADJ_RTX));
1383 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1386 /* Return true if X is a valid comparison operator for the dbcc
1389 Note it rejects floating point comparison operators.
1390 (In the future we could use Fdbcc).
1392 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1395 valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1397 switch (GET_CODE (x))
1399 case EQ: case NE: case GTU: case LTU:
1403 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1405 case GT: case LT: case GE: case LE:
1406 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1412 /* Return nonzero if flags are currently in the 68881 flag register. */
1414 flags_in_68881 (void)
1416 /* We could add support for these in the future */
1417 return cc_status.flags & CC_IN_68881;
1420 /* Return true if PARALLEL contains register REGNO. */
1422 m68k_reg_present_p (const_rtx parallel, unsigned int regno)
1426 if (REG_P (parallel) && REGNO (parallel) == regno)
1429 if (GET_CODE (parallel) != PARALLEL)
1432 for (i = 0; i < XVECLEN (parallel, 0); ++i)
1436 x = XEXP (XVECEXP (parallel, 0, i), 0);
1437 if (REG_P (x) && REGNO (x) == regno)
1444 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1447 m68k_ok_for_sibcall_p (tree decl, tree exp)
1449 enum m68k_function_kind kind;
1451 /* We cannot use sibcalls for nested functions because we use the
1452 static chain register for indirect calls. */
1453 if (CALL_EXPR_STATIC_CHAIN (exp))
1456 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
1458 /* Check that the return value locations are the same. For
1459 example that we aren't returning a value from the sibling in
1460 a D0 register but then need to transfer it to a A0 register. */
1464 cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)),
1466 call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl);
1468 /* Check that the values are equal or that the result the callee
1469 function returns is superset of what the current function returns. */
1470 if (!(rtx_equal_p (cfun_value, call_value)
1471 || (REG_P (cfun_value)
1472 && m68k_reg_present_p (call_value, REGNO (cfun_value)))))
1476 kind = m68k_get_function_kind (current_function_decl);
1477 if (kind == m68k_fk_normal_function)
1478 /* We can always sibcall from a normal function, because it's
1479 undefined if it is calling an interrupt function. */
1482 /* Otherwise we can only sibcall if the function kind is known to be
1484 if (decl && m68k_get_function_kind (decl) == kind)
1490 /* On the m68k all args are always pushed. */
1493 m68k_function_arg (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1494 enum machine_mode mode ATTRIBUTE_UNUSED,
1495 const_tree type ATTRIBUTE_UNUSED,
1496 bool named ATTRIBUTE_UNUSED)
1502 m68k_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1503 const_tree type, bool named ATTRIBUTE_UNUSED)
1505 *cum += (mode != BLKmode
1506 ? (GET_MODE_SIZE (mode) + 3) & ~3
1507 : (int_size_in_bytes (type) + 3) & ~3);
1510 /* Convert X to a legitimate function call memory reference and return the
1514 m68k_legitimize_call_address (rtx x)
1516 gcc_assert (MEM_P (x));
1517 if (call_operand (XEXP (x, 0), VOIDmode))
1519 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1522 /* Likewise for sibling calls. */
1525 m68k_legitimize_sibcall_address (rtx x)
1527 gcc_assert (MEM_P (x));
1528 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1531 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1532 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1535 /* Convert X to a legitimate address and return it if successful. Otherwise
1538 For the 68000, we handle X+REG by loading X into a register R and
1539 using R+REG. R will go in an address reg and indexing will be used.
1540 However, if REG is a broken-out memory address or multiplication,
1541 nothing needs to be done because REG can certainly go in an address reg. */
1544 m68k_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
1546 if (m68k_tls_symbol_p (x))
1547 return m68k_legitimize_tls_address (x);
1549 if (GET_CODE (x) == PLUS)
1551 int ch = (x) != (oldx);
1554 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1556 if (GET_CODE (XEXP (x, 0)) == MULT)
1559 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
1561 if (GET_CODE (XEXP (x, 1)) == MULT)
1564 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
1568 if (GET_CODE (XEXP (x, 1)) == REG
1569 && GET_CODE (XEXP (x, 0)) == REG)
1571 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1574 x = force_operand (x, 0);
1578 if (memory_address_p (mode, x))
1581 if (GET_CODE (XEXP (x, 0)) == REG
1582 || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
1583 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
1584 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode))
1586 rtx temp = gen_reg_rtx (Pmode);
1587 rtx val = force_operand (XEXP (x, 1), 0);
1588 emit_move_insn (temp, val);
1591 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
1592 && GET_CODE (XEXP (x, 0)) == REG)
1593 x = force_operand (x, 0);
1595 else if (GET_CODE (XEXP (x, 1)) == REG
1596 || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
1597 && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
1598 && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode))
1600 rtx temp = gen_reg_rtx (Pmode);
1601 rtx val = force_operand (XEXP (x, 0), 0);
1602 emit_move_insn (temp, val);
1605 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
1606 && GET_CODE (XEXP (x, 1)) == REG)
1607 x = force_operand (x, 0);
1615 /* Output a dbCC; jCC sequence. Note we do not handle the
1616 floating point version of this sequence (Fdbcc). We also
1617 do not handle alternative conditions when CC_NO_OVERFLOW is
1618 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1619 kick those out before we get here. */
1622 output_dbcc_and_branch (rtx *operands)
1624 switch (GET_CODE (operands[3]))
1627 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1631 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1635 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1639 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1643 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1647 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1651 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1655 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1659 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1663 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1670 /* If the decrement is to be done in SImode, then we have
1671 to compensate for the fact that dbcc decrements in HImode. */
1672 switch (GET_MODE (operands[0]))
1675 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
1687 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1690 enum rtx_code op_code = GET_CODE (op);
1692 /* This does not produce a useful cc. */
1695 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1696 below. Swap the operands and change the op if these requirements
1697 are not fulfilled. */
1698 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1702 operand1 = operand2;
1704 op_code = swap_condition (op_code);
1706 loperands[0] = operand1;
1707 if (GET_CODE (operand1) == REG)
1708 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1710 loperands[1] = adjust_address (operand1, SImode, 4);
1711 if (operand2 != const0_rtx)
1713 loperands[2] = operand2;
1714 if (GET_CODE (operand2) == REG)
1715 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1717 loperands[3] = adjust_address (operand2, SImode, 4);
1719 loperands[4] = gen_label_rtx ();
1720 if (operand2 != const0_rtx)
1721 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1724 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1725 output_asm_insn ("tst%.l %0", loperands);
1727 output_asm_insn ("cmp%.w #0,%0", loperands);
1729 output_asm_insn ("jne %l4", loperands);
1731 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1732 output_asm_insn ("tst%.l %1", loperands);
1734 output_asm_insn ("cmp%.w #0,%1", loperands);
1737 loperands[5] = dest;
1742 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1743 CODE_LABEL_NUMBER (loperands[4]));
1744 output_asm_insn ("seq %5", loperands);
1748 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1749 CODE_LABEL_NUMBER (loperands[4]));
1750 output_asm_insn ("sne %5", loperands);
1754 loperands[6] = gen_label_rtx ();
1755 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1756 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1757 CODE_LABEL_NUMBER (loperands[4]));
1758 output_asm_insn ("sgt %5", loperands);
1759 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1760 CODE_LABEL_NUMBER (loperands[6]));
1764 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1765 CODE_LABEL_NUMBER (loperands[4]));
1766 output_asm_insn ("shi %5", loperands);
1770 loperands[6] = gen_label_rtx ();
1771 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1772 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1773 CODE_LABEL_NUMBER (loperands[4]));
1774 output_asm_insn ("slt %5", loperands);
1775 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1776 CODE_LABEL_NUMBER (loperands[6]));
1780 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1781 CODE_LABEL_NUMBER (loperands[4]));
1782 output_asm_insn ("scs %5", loperands);
1786 loperands[6] = gen_label_rtx ();
1787 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1788 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1789 CODE_LABEL_NUMBER (loperands[4]));
1790 output_asm_insn ("sge %5", loperands);
1791 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1792 CODE_LABEL_NUMBER (loperands[6]));
1796 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1797 CODE_LABEL_NUMBER (loperands[4]));
1798 output_asm_insn ("scc %5", loperands);
1802 loperands[6] = gen_label_rtx ();
1803 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1804 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1805 CODE_LABEL_NUMBER (loperands[4]));
1806 output_asm_insn ("sle %5", loperands);
1807 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1808 CODE_LABEL_NUMBER (loperands[6]));
1812 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1813 CODE_LABEL_NUMBER (loperands[4]));
1814 output_asm_insn ("sls %5", loperands);
1824 output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
1826 operands[0] = countop;
1827 operands[1] = dataop;
1829 if (GET_CODE (countop) == CONST_INT)
1831 register int count = INTVAL (countop);
1832 /* If COUNT is bigger than size of storage unit in use,
1833 advance to the containing unit of same size. */
1834 if (count > signpos)
1836 int offset = (count & ~signpos) / 8;
1837 count = count & signpos;
1838 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1840 if (count == signpos)
1841 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1843 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1845 /* These three statements used to use next_insns_test_no...
1846 but it appears that this should do the same job. */
1848 && next_insn_tests_no_inequality (insn))
1851 && next_insn_tests_no_inequality (insn))
1854 && next_insn_tests_no_inequality (insn))
1856 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1857 On some m68k variants unfortunately that's slower than btst.
1858 On 68000 and higher, that should also work for all HImode operands. */
1859 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1861 if (count == 3 && DATA_REG_P (operands[1])
1862 && next_insn_tests_no_inequality (insn))
1864 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1865 return "move%.w %1,%%ccr";
1867 if (count == 2 && DATA_REG_P (operands[1])
1868 && next_insn_tests_no_inequality (insn))
1870 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1871 return "move%.w %1,%%ccr";
1873 /* count == 1 followed by bvc/bvs and
1874 count == 0 followed by bcc/bcs are also possible, but need
1875 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1878 cc_status.flags = CC_NOT_NEGATIVE;
1880 return "btst %0,%1";
1883 /* Return true if X is a legitimate base register. STRICT_P says
1884 whether we need strict checking. */
1887 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1889 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1890 if (!strict_p && GET_CODE (x) == SUBREG)
1895 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1896 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
1899 /* Return true if X is a legitimate index register. STRICT_P says
1900 whether we need strict checking. */
1903 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1905 if (!strict_p && GET_CODE (x) == SUBREG)
1910 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1911 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
1914 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1915 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1916 ADDRESS if so. STRICT_P says whether we need strict checking. */
1919 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1923 /* Check for a scale factor. */
1925 if ((TARGET_68020 || TARGET_COLDFIRE)
1926 && GET_CODE (x) == MULT
1927 && GET_CODE (XEXP (x, 1)) == CONST_INT
1928 && (INTVAL (XEXP (x, 1)) == 2
1929 || INTVAL (XEXP (x, 1)) == 4
1930 || (INTVAL (XEXP (x, 1)) == 8
1931 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1933 scale = INTVAL (XEXP (x, 1));
1937 /* Check for a word extension. */
1938 if (!TARGET_COLDFIRE
1939 && GET_CODE (x) == SIGN_EXTEND
1940 && GET_MODE (XEXP (x, 0)) == HImode)
1943 if (m68k_legitimate_index_reg_p (x, strict_p))
1945 address->scale = scale;
1953 /* Return true if X is an illegitimate symbolic constant. */
1956 m68k_illegitimate_symbolic_constant_p (rtx x)
1960 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1962 split_const (x, &base, &offset);
1963 if (GET_CODE (base) == SYMBOL_REF
1964 && !offset_within_block_p (base, INTVAL (offset)))
1967 return m68k_tls_reference_p (x, false);
1970 /* Return true if X is a legitimate constant address that can reach
1971 bytes in the range [X, X + REACH). STRICT_P says whether we need
1975 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1979 if (!CONSTANT_ADDRESS_P (x))
1983 && !(strict_p && TARGET_PCREL)
1984 && symbolic_operand (x, VOIDmode))
1987 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1989 split_const (x, &base, &offset);
1990 if (GET_CODE (base) == SYMBOL_REF
1991 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1995 return !m68k_tls_reference_p (x, false);
1998 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1999 labels will become jump tables. */
2002 m68k_jump_table_ref_p (rtx x)
2004 if (GET_CODE (x) != LABEL_REF)
2008 if (!NEXT_INSN (x) && !PREV_INSN (x))
2011 x = next_nonnote_insn (x);
2012 return x && JUMP_TABLE_DATA_P (x);
2015 /* Return true if X is a legitimate address for values of mode MODE.
2016 STRICT_P says whether strict checking is needed. If the address
2017 is valid, describe its components in *ADDRESS. */
2020 m68k_decompose_address (enum machine_mode mode, rtx x,
2021 bool strict_p, struct m68k_address *address)
2025 memset (address, 0, sizeof (*address));
2027 if (mode == BLKmode)
2030 reach = GET_MODE_SIZE (mode);
2032 /* Check for (An) (mode 2). */
2033 if (m68k_legitimate_base_reg_p (x, strict_p))
2039 /* Check for -(An) and (An)+ (modes 3 and 4). */
2040 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
2041 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
2043 address->code = GET_CODE (x);
2044 address->base = XEXP (x, 0);
2048 /* Check for (d16,An) (mode 5). */
2049 if (GET_CODE (x) == PLUS
2050 && GET_CODE (XEXP (x, 1)) == CONST_INT
2051 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
2052 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
2054 address->base = XEXP (x, 0);
2055 address->offset = XEXP (x, 1);
2059 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2060 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2062 if (GET_CODE (x) == PLUS
2063 && XEXP (x, 0) == pic_offset_table_rtx)
2065 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2066 they are invalid in this context. */
2067 if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1))
2069 address->base = XEXP (x, 0);
2070 address->offset = XEXP (x, 1);
2075 /* The ColdFire FPU only accepts addressing modes 2-5. */
2076 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
2079 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2080 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2081 All these modes are variations of mode 7. */
2082 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
2084 address->offset = x;
2088 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2091 ??? do_tablejump creates these addresses before placing the target
2092 label, so we have to assume that unplaced labels are jump table
2093 references. It seems unlikely that we would ever generate indexed
2094 accesses to unplaced labels in other cases. */
2095 if (GET_CODE (x) == PLUS
2096 && m68k_jump_table_ref_p (XEXP (x, 1))
2097 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
2099 address->offset = XEXP (x, 1);
2103 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2104 (bd,An,Xn.SIZE*SCALE) addresses. */
2108 /* Check for a nonzero base displacement. */
2109 if (GET_CODE (x) == PLUS
2110 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
2112 address->offset = XEXP (x, 1);
2116 /* Check for a suppressed index register. */
2117 if (m68k_legitimate_base_reg_p (x, strict_p))
2123 /* Check for a suppressed base register. Do not allow this case
2124 for non-symbolic offsets as it effectively gives gcc freedom
2125 to treat data registers as base registers, which can generate
2128 && symbolic_operand (address->offset, VOIDmode)
2129 && m68k_decompose_index (x, strict_p, address))
2134 /* Check for a nonzero base displacement. */
2135 if (GET_CODE (x) == PLUS
2136 && GET_CODE (XEXP (x, 1)) == CONST_INT
2137 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
2139 address->offset = XEXP (x, 1);
2144 /* We now expect the sum of a base and an index. */
2145 if (GET_CODE (x) == PLUS)
2147 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
2148 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
2150 address->base = XEXP (x, 0);
2154 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
2155 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
2157 address->base = XEXP (x, 1);
2164 /* Return true if X is a legitimate address for values of mode MODE.
2165 STRICT_P says whether strict checking is needed. */
2168 m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2170 struct m68k_address address;
2172 return m68k_decompose_address (mode, x, strict_p, &address);
2175 /* Return true if X is a memory, describing its address in ADDRESS if so.
2176 Apply strict checking if called during or after reload. */
2179 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
2182 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
2183 reload_in_progress || reload_completed,
2187 /* Return true if X matches the 'Q' constraint. It must be a memory
2188 with a base address and no constant offset or index. */
2191 m68k_matches_q_p (rtx x)
2193 struct m68k_address address;
2195 return (m68k_legitimate_mem_p (x, &address)
2196 && address.code == UNKNOWN
2202 /* Return true if X matches the 'U' constraint. It must be a base address
2203 with a constant offset and no index. */
2206 m68k_matches_u_p (rtx x)
2208 struct m68k_address address;
2210 return (m68k_legitimate_mem_p (x, &address)
2211 && address.code == UNKNOWN
2217 /* Return GOT pointer. */
2222 if (pic_offset_table_rtx == NULL_RTX)
2223 pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG);
2225 crtl->uses_pic_offset_table = 1;
2227 return pic_offset_table_rtx;
2230 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2232 enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO,
2233 RELOC_TLSIE, RELOC_TLSLE };
2235 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2237 /* Wrap symbol X into unspec representing relocation RELOC.
2238 BASE_REG - register that should be added to the result.
2239 TEMP_REG - if non-null, temporary register. */
2242 m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg)
2246 use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS;
2248 if (TARGET_COLDFIRE && use_x_p)
2249 /* When compiling with -mx{got, tls} switch the code will look like this:
2251 move.l <X>@<RELOC>,<TEMP_REG>
2252 add.l <BASE_REG>,<TEMP_REG> */
2254 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2255 to put @RELOC after reference. */
2256 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
2258 x = gen_rtx_CONST (Pmode, x);
2260 if (temp_reg == NULL)
2262 gcc_assert (can_create_pseudo_p ());
2263 temp_reg = gen_reg_rtx (Pmode);
2266 emit_move_insn (temp_reg, x);
2267 emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg));
2272 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
2274 x = gen_rtx_CONST (Pmode, x);
2276 x = gen_rtx_PLUS (Pmode, base_reg, x);
2282 /* Helper for m68k_unwrap_symbol.
2283 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2284 sets *RELOC_PTR to relocation type for the symbol. */
2287 m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p,
2288 enum m68k_reloc *reloc_ptr)
2290 if (GET_CODE (orig) == CONST)
2293 enum m68k_reloc dummy;
2297 if (reloc_ptr == NULL)
2300 /* Handle an addend. */
2301 if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS)
2302 && CONST_INT_P (XEXP (x, 1)))
2305 if (GET_CODE (x) == UNSPEC)
2307 switch (XINT (x, 1))
2309 case UNSPEC_RELOC16:
2310 orig = XVECEXP (x, 0, 0);
2311 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
2314 case UNSPEC_RELOC32:
2315 if (unwrap_reloc32_p)
2317 orig = XVECEXP (x, 0, 0);
2318 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
2331 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2332 UNSPEC_RELOC32 wrappers. */
2335 m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p)
2337 return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL);
2340 /* Helper for m68k_final_prescan_insn. */
2343 m68k_final_prescan_insn_1 (rtx *x_ptr, void *data ATTRIBUTE_UNUSED)
2347 if (m68k_unwrap_symbol (x, true) != x)
2348 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2352 gcc_assert (GET_CODE (x) == CONST);
2355 if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS)
2360 unspec = XEXP (plus, 0);
2361 gcc_assert (GET_CODE (unspec) == UNSPEC);
2362 addend = XEXP (plus, 1);
2363 gcc_assert (CONST_INT_P (addend));
2365 /* We now have all the pieces, rearrange them. */
2367 /* Move symbol to plus. */
2368 XEXP (plus, 0) = XVECEXP (unspec, 0, 0);
2370 /* Move plus inside unspec. */
2371 XVECEXP (unspec, 0, 0) = plus;
2373 /* Move unspec to top level of const. */
2374 XEXP (x, 0) = unspec;
2383 /* Prescan insn before outputing assembler for it. */
2386 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED,
2387 rtx *operands, int n_operands)
2391 /* Combine and, possibly, other optimizations may do good job
2393 (const (unspec [(symbol)]))
2395 (const (plus (unspec [(symbol)])
2397 The problem with this is emitting @TLS or @GOT decorations.
2398 The decoration is emitted when processing (unspec), so the
2399 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2401 It seems that the easiest solution to this is to convert such
2403 (const (unspec [(plus (symbol)
2405 Note, that the top level of operand remains intact, so we don't have
2406 to patch up anything outside of the operand. */
2408 for (i = 0; i < n_operands; ++i)
2414 for_each_rtx (&op, m68k_final_prescan_insn_1, NULL);
2418 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2419 If REG is non-null, use it; generate new pseudo otherwise. */
2422 m68k_move_to_reg (rtx x, rtx orig, rtx reg)
2426 if (reg == NULL_RTX)
2428 gcc_assert (can_create_pseudo_p ());
2429 reg = gen_reg_rtx (Pmode);
2432 insn = emit_move_insn (reg, x);
2433 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2435 set_unique_reg_note (insn, REG_EQUAL, orig);
2440 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2444 m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg)
2446 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg);
2448 x = gen_rtx_MEM (Pmode, x);
2449 MEM_READONLY_P (x) = 1;
2454 /* Legitimize PIC addresses. If the address is already
2455 position-independent, we return ORIG. Newly generated
2456 position-independent addresses go to REG. If we need more
2457 than one register, we lose.
2459 An address is legitimized by making an indirect reference
2460 through the Global Offset Table with the name of the symbol
2463 The assembler and linker are responsible for placing the
2464 address of the symbol in the GOT. The function prologue
2465 is responsible for initializing a5 to the starting address
2468 The assembler is also responsible for translating a symbol name
2469 into a constant displacement from the start of the GOT.
2471 A quick example may make things a little clearer:
2473 When not generating PIC code to store the value 12345 into _foo
2474 we would generate the following code:
2478 When generating PIC two transformations are made. First, the compiler
2479 loads the address of foo into a register. So the first transformation makes:
2484 The code in movsi will intercept the lea instruction and call this
2485 routine which will transform the instructions into:
2487 movel a5@(_foo:w), a0
2491 That (in a nutshell) is how *all* symbol and label references are
2495 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
2500 /* First handle a simple SYMBOL_REF or LABEL_REF */
2501 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
2505 pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg);
2506 pic_ref = m68k_move_to_reg (pic_ref, orig, reg);
2508 else if (GET_CODE (orig) == CONST)
2512 /* Make sure this has not already been legitimized. */
2513 if (m68k_unwrap_symbol (orig, true) != orig)
2518 /* legitimize both operands of the PLUS */
2519 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2521 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2522 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2523 base == reg ? 0 : reg);
2525 if (GET_CODE (orig) == CONST_INT)
2526 pic_ref = plus_constant (base, INTVAL (orig));
2528 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2534 /* The __tls_get_addr symbol. */
2535 static GTY(()) rtx m68k_tls_get_addr;
2537 /* Return SYMBOL_REF for __tls_get_addr. */
2540 m68k_get_tls_get_addr (void)
2542 if (m68k_tls_get_addr == NULL_RTX)
2543 m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr");
2545 return m68k_tls_get_addr;
2548 /* Return libcall result in A0 instead of usual D0. */
2549 static bool m68k_libcall_value_in_a0_p = false;
2551 /* Emit instruction sequence that calls __tls_get_addr. X is
2552 the TLS symbol we are referencing and RELOC is the symbol type to use
2553 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2554 emitted. A pseudo register with result of __tls_get_addr call is
2558 m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc)
2564 /* Emit the call sequence. */
2567 /* FIXME: Unfortunately, emit_library_call_value does not
2568 consider (plus (%a5) (const (unspec))) to be a good enough
2569 operand for push, so it forces it into a register. The bad
2570 thing about this is that combiner, due to copy propagation and other
2571 optimizations, sometimes can not later fix this. As a consequence,
2572 additional register may be allocated resulting in a spill.
2573 For reference, see args processing loops in
2574 calls.c:emit_library_call_value_1.
2575 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2576 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX);
2578 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2579 is the simpliest way of generating a call. The difference between
2580 __tls_get_addr() and libcall is that the result is returned in D0
2581 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2582 which temporarily switches returning the result to A0. */
2584 m68k_libcall_value_in_a0_p = true;
2585 a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE,
2586 Pmode, 1, x, Pmode);
2587 m68k_libcall_value_in_a0_p = false;
2589 insns = get_insns ();
2592 gcc_assert (can_create_pseudo_p ());
2593 dest = gen_reg_rtx (Pmode);
2594 emit_libcall_block (insns, dest, a0, eqv);
2599 /* The __tls_get_addr symbol. */
2600 static GTY(()) rtx m68k_read_tp;
2602 /* Return SYMBOL_REF for __m68k_read_tp. */
2605 m68k_get_m68k_read_tp (void)
2607 if (m68k_read_tp == NULL_RTX)
2608 m68k_read_tp = init_one_libfunc ("__m68k_read_tp");
2610 return m68k_read_tp;
2613 /* Emit instruction sequence that calls __m68k_read_tp.
2614 A pseudo register with result of __m68k_read_tp call is returned. */
2617 m68k_call_m68k_read_tp (void)
2626 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2627 is the simpliest way of generating a call. The difference between
2628 __m68k_read_tp() and libcall is that the result is returned in D0
2629 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2630 which temporarily switches returning the result to A0. */
2632 /* Emit the call sequence. */
2633 m68k_libcall_value_in_a0_p = true;
2634 a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE,
2636 m68k_libcall_value_in_a0_p = false;
2637 insns = get_insns ();
2640 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2641 share the m68k_read_tp result with other IE/LE model accesses. */
2642 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32);
2644 gcc_assert (can_create_pseudo_p ());
2645 dest = gen_reg_rtx (Pmode);
2646 emit_libcall_block (insns, dest, a0, eqv);
2651 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2652 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2656 m68k_legitimize_tls_address (rtx orig)
2658 switch (SYMBOL_REF_TLS_MODEL (orig))
2660 case TLS_MODEL_GLOBAL_DYNAMIC:
2661 orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD);
2664 case TLS_MODEL_LOCAL_DYNAMIC:
2670 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2671 share the LDM result with other LD model accesses. */
2672 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2675 a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM);
2677 x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX);
2679 if (can_create_pseudo_p ())
2680 x = m68k_move_to_reg (x, orig, NULL_RTX);
2686 case TLS_MODEL_INITIAL_EXEC:
2691 a0 = m68k_call_m68k_read_tp ();
2693 x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX);
2694 x = gen_rtx_PLUS (Pmode, x, a0);
2696 if (can_create_pseudo_p ())
2697 x = m68k_move_to_reg (x, orig, NULL_RTX);
2703 case TLS_MODEL_LOCAL_EXEC:
2708 a0 = m68k_call_m68k_read_tp ();
2710 x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX);
2712 if (can_create_pseudo_p ())
2713 x = m68k_move_to_reg (x, orig, NULL_RTX);
2726 /* Return true if X is a TLS symbol. */
2729 m68k_tls_symbol_p (rtx x)
2731 if (!TARGET_HAVE_TLS)
2734 if (GET_CODE (x) != SYMBOL_REF)
2737 return SYMBOL_REF_TLS_MODEL (x) != 0;
2740 /* Helper for m68k_tls_referenced_p. */
2743 m68k_tls_reference_p_1 (rtx *x_ptr, void *data ATTRIBUTE_UNUSED)
2745 /* Note: this is not the same as m68k_tls_symbol_p. */
2746 if (GET_CODE (*x_ptr) == SYMBOL_REF)
2747 return SYMBOL_REF_TLS_MODEL (*x_ptr) != 0 ? 1 : 0;
2749 /* Don't recurse into legitimate TLS references. */
2750 if (m68k_tls_reference_p (*x_ptr, true))
2756 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2757 though illegitimate one.
2758 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2761 m68k_tls_reference_p (rtx x, bool legitimate_p)
2763 if (!TARGET_HAVE_TLS)
2767 return for_each_rtx (&x, m68k_tls_reference_p_1, NULL) == 1 ? true : false;
2770 enum m68k_reloc reloc = RELOC_GOT;
2772 return (m68k_unwrap_symbol_1 (x, true, &reloc) != x
2773 && TLS_RELOC_P (reloc));
2779 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2781 /* Return the type of move that should be used for integer I. */
2784 m68k_const_method (HOST_WIDE_INT i)
2791 /* The ColdFire doesn't have byte or word operations. */
2792 /* FIXME: This may not be useful for the m68060 either. */
2793 if (!TARGET_COLDFIRE)
2795 /* if -256 < N < 256 but N is not in range for a moveq
2796 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2797 if (USE_MOVQ (i ^ 0xff))
2799 /* Likewise, try with not.w */
2800 if (USE_MOVQ (i ^ 0xffff))
2802 /* This is the only value where neg.w is useful */
2807 /* Try also with swap. */
2809 if (USE_MOVQ ((u >> 16) | (u << 16)))
2814 /* Try using MVZ/MVS with an immediate value to load constants. */
2815 if (i >= 0 && i <= 65535)
2817 if (i >= -32768 && i <= 32767)
2821 /* Otherwise, use move.l */
2825 /* Return the cost of moving constant I into a data register. */
2828 const_int_cost (HOST_WIDE_INT i)
2830 switch (m68k_const_method (i))
2833 /* Constants between -128 and 127 are cheap due to moveq. */
2841 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2851 m68k_rtx_costs (rtx x, int code, int outer_code, int *total,
2852 bool speed ATTRIBUTE_UNUSED)
2857 /* Constant zero is super cheap due to clr instruction. */
2858 if (x == const0_rtx)
2861 *total = const_int_cost (INTVAL (x));
2871 /* Make 0.0 cheaper than other floating constants to
2872 encourage creating tstsf and tstdf insns. */
2873 if (outer_code == COMPARE
2874 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2880 /* These are vaguely right for a 68020. */
2881 /* The costs for long multiply have been adjusted to work properly
2882 in synth_mult on the 68020, relative to an average of the time
2883 for add and the time for shift, taking away a little more because
2884 sometimes move insns are needed. */
2885 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2890 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2891 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2893 : TARGET_COLDFIRE ? 3 : 13)
2898 : TUNE_68000_10 ? 5 \
2899 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2900 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2902 : TARGET_COLDFIRE ? 2 : 8)
2905 (TARGET_CF_HWDIV ? 11 \
2906 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2909 /* An lea costs about three times as much as a simple add. */
2910 if (GET_MODE (x) == SImode
2911 && GET_CODE (XEXP (x, 1)) == REG
2912 && GET_CODE (XEXP (x, 0)) == MULT
2913 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2914 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2915 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2916 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2917 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2919 /* lea an@(dx:l:i),am */
2920 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2930 *total = COSTS_N_INSNS(1);
2935 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2937 if (INTVAL (XEXP (x, 1)) < 16)
2938 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2940 /* We're using clrw + swap for these cases. */
2941 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2944 *total = COSTS_N_INSNS (10); /* Worst case. */
2947 /* A shift by a big integer takes an extra instruction. */
2948 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2949 && (INTVAL (XEXP (x, 1)) == 16))
2951 *total = COSTS_N_INSNS (2); /* clrw;swap */
2954 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2955 && !(INTVAL (XEXP (x, 1)) > 0
2956 && INTVAL (XEXP (x, 1)) <= 8))
2958 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2964 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2965 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2966 && GET_MODE (x) == SImode)
2967 *total = COSTS_N_INSNS (MULW_COST);
2968 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2969 *total = COSTS_N_INSNS (MULW_COST);
2971 *total = COSTS_N_INSNS (MULL_COST);
2978 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2979 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2980 else if (TARGET_CF_HWDIV)
2981 *total = COSTS_N_INSNS (18);
2983 *total = COSTS_N_INSNS (43); /* div.l */
2987 if (outer_code == COMPARE)
2996 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
3000 output_move_const_into_data_reg (rtx *operands)
3004 i = INTVAL (operands[1]);
3005 switch (m68k_const_method (i))
3008 return "mvzw %1,%0";
3010 return "mvsw %1,%0";
3012 return "moveq %1,%0";
3015 operands[1] = GEN_INT (i ^ 0xff);
3016 return "moveq %1,%0\n\tnot%.b %0";
3019 operands[1] = GEN_INT (i ^ 0xffff);
3020 return "moveq %1,%0\n\tnot%.w %0";
3023 return "moveq #-128,%0\n\tneg%.w %0";
3028 operands[1] = GEN_INT ((u << 16) | (u >> 16));
3029 return "moveq %1,%0\n\tswap %0";
3032 return "move%.l %1,%0";
3038 /* Return true if I can be handled by ISA B's mov3q instruction. */
3041 valid_mov3q_const (HOST_WIDE_INT i)
3043 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
3046 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3047 I is the value of OPERANDS[1]. */
3050 output_move_simode_const (rtx *operands)
3056 src = INTVAL (operands[1]);
3058 && (DATA_REG_P (dest) || MEM_P (dest))
3059 /* clr insns on 68000 read before writing. */
3060 && ((TARGET_68010 || TARGET_COLDFIRE)
3061 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
3063 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
3064 return "mov3q%.l %1,%0";
3065 else if (src == 0 && ADDRESS_REG_P (dest))
3066 return "sub%.l %0,%0";
3067 else if (DATA_REG_P (dest))
3068 return output_move_const_into_data_reg (operands);
3069 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
3071 if (valid_mov3q_const (src))
3072 return "mov3q%.l %1,%0";
3073 return "move%.w %1,%0";
3075 else if (MEM_P (dest)
3076 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
3077 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
3078 && IN_RANGE (src, -0x8000, 0x7fff))
3080 if (valid_mov3q_const (src))
3081 return "mov3q%.l %1,%-";
3084 return "move%.l %1,%0";
3088 output_move_simode (rtx *operands)
3090 if (GET_CODE (operands[1]) == CONST_INT)
3091 return output_move_simode_const (operands);
3092 else if ((GET_CODE (operands[1]) == SYMBOL_REF
3093 || GET_CODE (operands[1]) == CONST)
3094 && push_operand (operands[0], SImode))
3096 else if ((GET_CODE (operands[1]) == SYMBOL_REF
3097 || GET_CODE (operands[1]) == CONST)
3098 && ADDRESS_REG_P (operands[0]))
3099 return "lea %a1,%0";
3100 return "move%.l %1,%0";
3104 output_move_himode (rtx *operands)
3106 if (GET_CODE (operands[1]) == CONST_INT)
3108 if (operands[1] == const0_rtx
3109 && (DATA_REG_P (operands[0])
3110 || GET_CODE (operands[0]) == MEM)
3111 /* clr insns on 68000 read before writing. */
3112 && ((TARGET_68010 || TARGET_COLDFIRE)
3113 || !(GET_CODE (operands[0]) == MEM
3114 && MEM_VOLATILE_P (operands[0]))))
3116 else if (operands[1] == const0_rtx
3117 && ADDRESS_REG_P (operands[0]))
3118 return "sub%.l %0,%0";
3119 else if (DATA_REG_P (operands[0])
3120 && INTVAL (operands[1]) < 128
3121 && INTVAL (operands[1]) >= -128)
3122 return "moveq %1,%0";
3123 else if (INTVAL (operands[1]) < 0x8000
3124 && INTVAL (operands[1]) >= -0x8000)
3125 return "move%.w %1,%0";
3127 else if (CONSTANT_P (operands[1]))
3128 return "move%.l %1,%0";
3129 return "move%.w %1,%0";
3133 output_move_qimode (rtx *operands)
3135 /* 68k family always modifies the stack pointer by at least 2, even for
3136 byte pushes. The 5200 (ColdFire) does not do this. */
3138 /* This case is generated by pushqi1 pattern now. */
3139 gcc_assert (!(GET_CODE (operands[0]) == MEM
3140 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
3141 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
3142 && ! ADDRESS_REG_P (operands[1])
3143 && ! TARGET_COLDFIRE));
3145 /* clr and st insns on 68000 read before writing. */
3146 if (!ADDRESS_REG_P (operands[0])
3147 && ((TARGET_68010 || TARGET_COLDFIRE)
3148 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3150 if (operands[1] == const0_rtx)
3152 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
3153 && GET_CODE (operands[1]) == CONST_INT
3154 && (INTVAL (operands[1]) & 255) == 255)
3160 if (GET_CODE (operands[1]) == CONST_INT
3161 && DATA_REG_P (operands[0])
3162 && INTVAL (operands[1]) < 128
3163 && INTVAL (operands[1]) >= -128)
3164 return "moveq %1,%0";
3165 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
3166 return "sub%.l %0,%0";
3167 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
3168 return "move%.l %1,%0";
3169 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3170 from address registers. */
3171 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
3172 return "move%.w %1,%0";
3173 return "move%.b %1,%0";
3177 output_move_stricthi (rtx *operands)
3179 if (operands[1] == const0_rtx
3180 /* clr insns on 68000 read before writing. */
3181 && ((TARGET_68010 || TARGET_COLDFIRE)
3182 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3184 return "move%.w %1,%0";
3188 output_move_strictqi (rtx *operands)
3190 if (operands[1] == const0_rtx
3191 /* clr insns on 68000 read before writing. */
3192 && ((TARGET_68010 || TARGET_COLDFIRE)
3193 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3195 return "move%.b %1,%0";
3198 /* Return the best assembler insn template
3199 for moving operands[1] into operands[0] as a fullword. */
3202 singlemove_string (rtx *operands)
3204 if (GET_CODE (operands[1]) == CONST_INT)
3205 return output_move_simode_const (operands);
3206 return "move%.l %1,%0";
3210 /* Output assembler or rtl code to perform a doubleword move insn
3211 with operands OPERANDS.
3212 Pointers to 3 helper functions should be specified:
3213 HANDLE_REG_ADJUST to adjust a register by a small value,
3214 HANDLE_COMPADR to compute an address and
3215 HANDLE_MOVSI to move 4 bytes. */
3218 handle_move_double (rtx operands[2],
3219 void (*handle_reg_adjust) (rtx, int),
3220 void (*handle_compadr) (rtx [2]),
3221 void (*handle_movsi) (rtx [2]))
3225 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
3230 rtx addreg0 = 0, addreg1 = 0;
3231 int dest_overlapped_low = 0;
3232 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
3237 /* First classify both operands. */
3239 if (REG_P (operands[0]))
3241 else if (offsettable_memref_p (operands[0]))
3243 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
3245 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3247 else if (GET_CODE (operands[0]) == MEM)
3252 if (REG_P (operands[1]))
3254 else if (CONSTANT_P (operands[1]))
3256 else if (offsettable_memref_p (operands[1]))
3258 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3260 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
3262 else if (GET_CODE (operands[1]) == MEM)
3267 /* Check for the cases that the operand constraints are not supposed
3268 to allow to happen. Generating code for these cases is
3270 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
3272 /* If one operand is decrementing and one is incrementing
3273 decrement the former register explicitly
3274 and change that operand into ordinary indexing. */
3276 if (optype0 == PUSHOP && optype1 == POPOP)
3278 operands[0] = XEXP (XEXP (operands[0], 0), 0);
3280 handle_reg_adjust (operands[0], -size);
3282 if (GET_MODE (operands[1]) == XFmode)
3283 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
3284 else if (GET_MODE (operands[0]) == DFmode)
3285 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
3287 operands[0] = gen_rtx_MEM (DImode, operands[0]);
3290 if (optype0 == POPOP && optype1 == PUSHOP)
3292 operands[1] = XEXP (XEXP (operands[1], 0), 0);
3294 handle_reg_adjust (operands[1], -size);
3296 if (GET_MODE (operands[1]) == XFmode)
3297 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
3298 else if (GET_MODE (operands[1]) == DFmode)
3299 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
3301 operands[1] = gen_rtx_MEM (DImode, operands[1]);
3305 /* If an operand is an unoffsettable memory ref, find a register
3306 we can increment temporarily to make it refer to the second word. */
3308 if (optype0 == MEMOP)
3309 addreg0 = find_addr_reg (XEXP (operands[0], 0));
3311 if (optype1 == MEMOP)
3312 addreg1 = find_addr_reg (XEXP (operands[1], 0));
3314 /* Ok, we can do one word at a time.
3315 Normally we do the low-numbered word first,
3316 but if either operand is autodecrementing then we
3317 do the high-numbered word first.
3319 In either case, set up in LATEHALF the operands to use
3320 for the high-numbered word and in some cases alter the
3321 operands in OPERANDS to be suitable for the low-numbered word. */
3325 if (optype0 == REGOP)
3327 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
3328 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3330 else if (optype0 == OFFSOP)
3332 middlehalf[0] = adjust_address (operands[0], SImode, 4);
3333 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
3337 middlehalf[0] = adjust_address (operands[0], SImode, 0);
3338 latehalf[0] = adjust_address (operands[0], SImode, 0);
3341 if (optype1 == REGOP)
3343 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
3344 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3346 else if (optype1 == OFFSOP)
3348 middlehalf[1] = adjust_address (operands[1], SImode, 4);
3349 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
3351 else if (optype1 == CNSTOP)
3353 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3358 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
3359 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
3360 operands[1] = GEN_INT (l[0]);
3361 middlehalf[1] = GEN_INT (l[1]);
3362 latehalf[1] = GEN_INT (l[2]);
3366 /* No non-CONST_DOUBLE constant should ever appear
3368 gcc_assert (!CONSTANT_P (operands[1]));
3373 middlehalf[1] = adjust_address (operands[1], SImode, 0);
3374 latehalf[1] = adjust_address (operands[1], SImode, 0);
3378 /* size is not 12: */
3380 if (optype0 == REGOP)
3381 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3382 else if (optype0 == OFFSOP)
3383 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
3385 latehalf[0] = adjust_address (operands[0], SImode, 0);
3387 if (optype1 == REGOP)
3388 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3389 else if (optype1 == OFFSOP)
3390 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
3391 else if (optype1 == CNSTOP)
3392 split_double (operands[1], &operands[1], &latehalf[1]);
3394 latehalf[1] = adjust_address (operands[1], SImode, 0);
3397 /* If insn is effectively movd N(sp),-(sp) then we will do the
3398 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3399 for the low word as well, to compensate for the first decrement of sp. */
3400 if (optype0 == PUSHOP
3401 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
3402 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
3403 operands[1] = middlehalf[1] = latehalf[1];
3405 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3406 if the upper part of reg N does not appear in the MEM, arrange to
3407 emit the move late-half first. Otherwise, compute the MEM address
3408 into the upper part of N and use that as a pointer to the memory
3410 if (optype0 == REGOP
3411 && (optype1 == OFFSOP || optype1 == MEMOP))
3413 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
3415 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
3416 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
3418 /* If both halves of dest are used in the src memory address,
3419 compute the address into latehalf of dest.
3420 Note that this can't happen if the dest is two data regs. */
3422 xops[0] = latehalf[0];
3423 xops[1] = XEXP (operands[1], 0);
3425 handle_compadr (xops);
3426 if (GET_MODE (operands[1]) == XFmode)
3428 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
3429 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
3430 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
3434 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
3435 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
3439 && reg_overlap_mentioned_p (middlehalf[0],
3440 XEXP (operands[1], 0)))
3442 /* Check for two regs used by both source and dest.
3443 Note that this can't happen if the dest is all data regs.
3444 It can happen if the dest is d6, d7, a0.
3445 But in that case, latehalf is an addr reg, so
3446 the code at compadr does ok. */
3448 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
3449 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
3452 /* JRV says this can't happen: */
3453 gcc_assert (!addreg0 && !addreg1);
3455 /* Only the middle reg conflicts; simply put it last. */
3456 handle_movsi (operands);
3457 handle_movsi (latehalf);
3458 handle_movsi (middlehalf);
3462 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
3463 /* If the low half of dest is mentioned in the source memory
3464 address, the arrange to emit the move late half first. */
3465 dest_overlapped_low = 1;
3468 /* If one or both operands autodecrementing,
3469 do the two words, high-numbered first. */
3471 /* Likewise, the first move would clobber the source of the second one,
3472 do them in the other order. This happens only for registers;
3473 such overlap can't happen in memory unless the user explicitly
3474 sets it up, and that is an undefined circumstance. */
3476 if (optype0 == PUSHOP || optype1 == PUSHOP
3477 || (optype0 == REGOP && optype1 == REGOP
3478 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
3479 || REGNO (operands[0]) == REGNO (latehalf[1])))
3480 || dest_overlapped_low)
3482 /* Make any unoffsettable addresses point at high-numbered word. */
3484 handle_reg_adjust (addreg0, size - 4);
3486 handle_reg_adjust (addreg1, size - 4);
3489 handle_movsi (latehalf);
3491 /* Undo the adds we just did. */
3493 handle_reg_adjust (addreg0, -4);
3495 handle_reg_adjust (addreg1, -4);
3499 handle_movsi (middlehalf);
3502 handle_reg_adjust (addreg0, -4);
3504 handle_reg_adjust (addreg1, -4);
3507 /* Do low-numbered word. */
3509 handle_movsi (operands);
3513 /* Normal case: do the two words, low-numbered first. */
3515 handle_movsi (operands);
3517 /* Do the middle one of the three words for long double */
3521 handle_reg_adjust (addreg0, 4);
3523 handle_reg_adjust (addreg1, 4);
3525 handle_movsi (middlehalf);
3528 /* Make any unoffsettable addresses point at high-numbered word. */
3530 handle_reg_adjust (addreg0, 4);
3532 handle_reg_adjust (addreg1, 4);
3535 handle_movsi (latehalf);
3537 /* Undo the adds we just did. */
3539 handle_reg_adjust (addreg0, -(size - 4));
3541 handle_reg_adjust (addreg1, -(size - 4));
3546 /* Output assembler code to adjust REG by N. */
3548 output_reg_adjust (rtx reg, int n)
3552 gcc_assert (GET_MODE (reg) == SImode
3553 && -12 <= n && n != 0 && n <= 12);
3558 s = "add%.l #12,%0";
3562 s = "addq%.l #8,%0";
3566 s = "addq%.l #4,%0";
3570 s = "sub%.l #12,%0";
3574 s = "subq%.l #8,%0";
3578 s = "subq%.l #4,%0";
3586 output_asm_insn (s, ®);
3589 /* Emit rtl code to adjust REG by N. */
3591 emit_reg_adjust (rtx reg1, int n)
3595 gcc_assert (GET_MODE (reg1) == SImode
3596 && -12 <= n && n != 0 && n <= 12);
3598 reg1 = copy_rtx (reg1);
3599 reg2 = copy_rtx (reg1);
3602 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
3604 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
3609 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3611 output_compadr (rtx operands[2])
3613 output_asm_insn ("lea %a1,%0", operands);
3616 /* Output the best assembler insn for moving operands[1] into operands[0]
3619 output_movsi (rtx operands[2])
3621 output_asm_insn (singlemove_string (operands), operands);
3624 /* Copy OP and change its mode to MODE. */
3626 copy_operand (rtx op, enum machine_mode mode)
3628 /* ??? This looks really ugly. There must be a better way
3629 to change a mode on the operand. */
3630 if (GET_MODE (op) != VOIDmode)
3633 op = gen_rtx_REG (mode, REGNO (op));
3637 PUT_MODE (op, mode);
3644 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3646 emit_movsi (rtx operands[2])
3648 operands[0] = copy_operand (operands[0], SImode);
3649 operands[1] = copy_operand (operands[1], SImode);
3651 emit_insn (gen_movsi (operands[0], operands[1]));
3654 /* Output assembler code to perform a doubleword move insn
3655 with operands OPERANDS. */
3657 output_move_double (rtx *operands)
3659 handle_move_double (operands,
3660 output_reg_adjust, output_compadr, output_movsi);
3665 /* Output rtl code to perform a doubleword move insn
3666 with operands OPERANDS. */
3668 m68k_emit_move_double (rtx operands[2])
3670 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
3673 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3674 new rtx with the correct mode. */
3677 force_mode (enum machine_mode mode, rtx orig)
3679 if (mode == GET_MODE (orig))
3682 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
3685 return gen_rtx_REG (mode, REGNO (orig));
3689 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3691 return reg_renumber && FP_REG_P (op);
3694 /* Emit insns to move operands[1] into operands[0].
3696 Return 1 if we have written out everything that needs to be done to
3697 do the move. Otherwise, return 0 and the caller will emit the move
3700 Note SCRATCH_REG may not be in the proper mode depending on how it
3701 will be used. This routine is responsible for creating a new copy
3702 of SCRATCH_REG in the proper mode. */
3705 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
3707 register rtx operand0 = operands[0];
3708 register rtx operand1 = operands[1];
3712 && reload_in_progress && GET_CODE (operand0) == REG
3713 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
3714 operand0 = reg_equiv_mem[REGNO (operand0)];
3715 else if (scratch_reg
3716 && reload_in_progress && GET_CODE (operand0) == SUBREG
3717 && GET_CODE (SUBREG_REG (operand0)) == REG
3718 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
3720 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3721 the code which tracks sets/uses for delete_output_reload. */
3722 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
3723 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
3724 SUBREG_BYTE (operand0));
3725 operand0 = alter_subreg (&temp);
3729 && reload_in_progress && GET_CODE (operand1) == REG
3730 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
3731 operand1 = reg_equiv_mem[REGNO (operand1)];
3732 else if (scratch_reg
3733 && reload_in_progress && GET_CODE (operand1) == SUBREG
3734 && GET_CODE (SUBREG_REG (operand1)) == REG
3735 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
3737 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3738 the code which tracks sets/uses for delete_output_reload. */
3739 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
3740 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
3741 SUBREG_BYTE (operand1));
3742 operand1 = alter_subreg (&temp);
3745 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
3746 && ((tem = find_replacement (&XEXP (operand0, 0)))
3747 != XEXP (operand0, 0)))
3748 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
3749 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
3750 && ((tem = find_replacement (&XEXP (operand1, 0)))
3751 != XEXP (operand1, 0)))
3752 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
3754 /* Handle secondary reloads for loads/stores of FP registers where
3755 the address is symbolic by using the scratch register */
3756 if (fp_reg_operand (operand0, mode)
3757 && ((GET_CODE (operand1) == MEM
3758 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
3759 || ((GET_CODE (operand1) == SUBREG
3760 && GET_CODE (XEXP (operand1, 0)) == MEM
3761 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
3764 if (GET_CODE (operand1) == SUBREG)
3765 operand1 = XEXP (operand1, 0);
3767 /* SCRATCH_REG will hold an address. We want
3768 it in SImode regardless of what mode it was originally given
3770 scratch_reg = force_mode (SImode, scratch_reg);
3772 /* D might not fit in 14 bits either; for such cases load D into
3774 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
3776 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
3777 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
3779 XEXP (XEXP (operand1, 0), 0),
3783 emit_move_insn (scratch_reg, XEXP (operand1, 0));
3784 emit_insn (gen_rtx_SET (VOIDmode, operand0,
3785 gen_rtx_MEM (mode, scratch_reg)));
3788 else if (fp_reg_operand (operand1, mode)
3789 && ((GET_CODE (operand0) == MEM
3790 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
3791 || ((GET_CODE (operand0) == SUBREG)
3792 && GET_CODE (XEXP (operand0, 0)) == MEM
3793 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
3796 if (GET_CODE (operand0) == SUBREG)
3797 operand0 = XEXP (operand0, 0);
3799 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3800 it in SIMODE regardless of what mode it was originally given
3802 scratch_reg = force_mode (SImode, scratch_reg);
3804 /* D might not fit in 14 bits either; for such cases load D into
3806 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
3808 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
3809 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
3812 XEXP (XEXP (operand0, 0),
3817 emit_move_insn (scratch_reg, XEXP (operand0, 0));
3818 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
3822 /* Handle secondary reloads for loads of FP registers from constant
3823 expressions by forcing the constant into memory.
3825 use scratch_reg to hold the address of the memory location.
3827 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3828 NO_REGS when presented with a const_int and an register class
3829 containing only FP registers. Doing so unfortunately creates
3830 more problems than it solves. Fix this for 2.5. */
3831 else if (fp_reg_operand (operand0, mode)
3832 && CONSTANT_P (operand1)
3837 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3838 it in SIMODE regardless of what mode it was originally given
3840 scratch_reg = force_mode (SImode, scratch_reg);
3842 /* Force the constant into memory and put the address of the
3843 memory location into scratch_reg. */
3844 xoperands[0] = scratch_reg;
3845 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
3846 emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1]));
3848 /* Now load the destination register. */
3849 emit_insn (gen_rtx_SET (mode, operand0,
3850 gen_rtx_MEM (mode, scratch_reg)));
3854 /* Now have insn-emit do whatever it normally does. */
3858 /* Split one or more DImode RTL references into pairs of SImode
3859 references. The RTL can be REG, offsettable MEM, integer constant, or
3860 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3861 split and "num" is its length. lo_half and hi_half are output arrays
3862 that parallel "operands". */
3865 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3869 rtx op = operands[num];
3871 /* simplify_subreg refuses to split volatile memory addresses,
3872 but we still have to handle it. */
3873 if (GET_CODE (op) == MEM)
3875 lo_half[num] = adjust_address (op, SImode, 4);
3876 hi_half[num] = adjust_address (op, SImode, 0);
3880 lo_half[num] = simplify_gen_subreg (SImode, op,
3881 GET_MODE (op) == VOIDmode
3882 ? DImode : GET_MODE (op), 4);
3883 hi_half[num] = simplify_gen_subreg (SImode, op,
3884 GET_MODE (op) == VOIDmode
3885 ? DImode : GET_MODE (op), 0);
3890 /* Split X into a base and a constant offset, storing them in *BASE
3891 and *OFFSET respectively. */
3894 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3897 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3899 *offset += INTVAL (XEXP (x, 1));
3905 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3906 instruction. STORE_P says whether the move is a load or store.
3908 If the instruction uses post-increment or pre-decrement addressing,
3909 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3910 adjustment. This adjustment will be made by the first element of
3911 PARALLEL, with the loads or stores starting at element 1. If the
3912 instruction does not use post-increment or pre-decrement addressing,
3913 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3914 start at element 0. */
3917 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3918 HOST_WIDE_INT automod_offset, bool store_p)
3920 rtx base, mem_base, set, mem, reg, last_reg;
3921 HOST_WIDE_INT offset, mem_offset;
3923 enum reg_class rclass;
3925 len = XVECLEN (pattern, 0);
3926 first = (automod_base != NULL);
3930 /* Stores must be pre-decrement and loads must be post-increment. */
3931 if (store_p != (automod_offset < 0))
3934 /* Work out the base and offset for lowest memory location. */
3935 base = automod_base;
3936 offset = (automod_offset < 0 ? automod_offset : 0);
3940 /* Allow any valid base and offset in the first access. */
3947 for (i = first; i < len; i++)
3949 /* We need a plain SET. */
3950 set = XVECEXP (pattern, 0, i);
3951 if (GET_CODE (set) != SET)
3954 /* Check that we have a memory location... */
3955 mem = XEXP (set, !store_p);
3956 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3959 /* ...with the right address. */
3962 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3963 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3964 There are no mode restrictions for 680x0 besides the
3965 automodification rules enforced above. */
3967 && !m68k_legitimate_base_reg_p (base, reload_completed))
3972 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3973 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3977 /* Check that we have a register of the required mode and class. */
3978 reg = XEXP (set, store_p);
3980 || !HARD_REGISTER_P (reg)
3981 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3986 /* The register must belong to RCLASS and have a higher number
3987 than the register in the previous SET. */
3988 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3989 || REGNO (last_reg) >= REGNO (reg))
3994 /* Work out which register class we need. */
3995 if (INT_REGNO_P (REGNO (reg)))
3996 rclass = GENERAL_REGS;
3997 else if (FP_REGNO_P (REGNO (reg)))
4004 offset += GET_MODE_SIZE (GET_MODE (reg));
4007 /* If we have an automodification, check whether the final offset is OK. */
4008 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
4011 /* Reject unprofitable cases. */
4012 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
4018 /* Return the assembly code template for a movem or fmovem instruction
4019 whose pattern is given by PATTERN. Store the template's operands
4022 If the instruction uses post-increment or pre-decrement addressing,
4023 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
4024 is true if this is a store instruction. */
4027 m68k_output_movem (rtx *operands, rtx pattern,
4028 HOST_WIDE_INT automod_offset, bool store_p)
4033 gcc_assert (GET_CODE (pattern) == PARALLEL);
4035 first = (automod_offset != 0);
4036 for (i = first; i < XVECLEN (pattern, 0); i++)
4038 /* When using movem with pre-decrement addressing, register X + D0_REG
4039 is controlled by bit 15 - X. For all other addressing modes,
4040 register X + D0_REG is controlled by bit X. Confusingly, the
4041 register mask for fmovem is in the opposite order to that for
4045 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
4046 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
4047 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
4048 if (automod_offset < 0)
4050 if (FP_REGNO_P (regno))
4051 mask |= 1 << (regno - FP0_REG);
4053 mask |= 1 << (15 - (regno - D0_REG));
4057 if (FP_REGNO_P (regno))
4058 mask |= 1 << (7 - (regno - FP0_REG));
4060 mask |= 1 << (regno - D0_REG);
4065 if (automod_offset == 0)
4066 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
4067 else if (automod_offset < 0)
4068 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
4070 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
4071 operands[1] = GEN_INT (mask);
4072 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
4075 return "fmovem %1,%a0";
4077 return "fmovem %a0,%1";
4082 return "movem%.l %1,%a0";
4084 return "movem%.l %a0,%1";
4088 /* Return a REG that occurs in ADDR with coefficient 1.
4089 ADDR can be effectively incremented by incrementing REG. */
4092 find_addr_reg (rtx addr)
4094 while (GET_CODE (addr) == PLUS)
4096 if (GET_CODE (XEXP (addr, 0)) == REG)
4097 addr = XEXP (addr, 0);
4098 else if (GET_CODE (XEXP (addr, 1)) == REG)
4099 addr = XEXP (addr, 1);
4100 else if (CONSTANT_P (XEXP (addr, 0)))
4101 addr = XEXP (addr, 1);
4102 else if (CONSTANT_P (XEXP (addr, 1)))
4103 addr = XEXP (addr, 0);
4107 gcc_assert (GET_CODE (addr) == REG);
4111 /* Output assembler code to perform a 32-bit 3-operand add. */
4114 output_addsi3 (rtx *operands)
4116 if (! operands_match_p (operands[0], operands[1]))
4118 if (!ADDRESS_REG_P (operands[1]))
4120 rtx tmp = operands[1];
4122 operands[1] = operands[2];
4126 /* These insns can result from reloads to access
4127 stack slots over 64k from the frame pointer. */
4128 if (GET_CODE (operands[2]) == CONST_INT
4129 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
4130 return "move%.l %2,%0\n\tadd%.l %1,%0";
4131 if (GET_CODE (operands[2]) == REG)
4132 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4133 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4135 if (GET_CODE (operands[2]) == CONST_INT)
4137 if (INTVAL (operands[2]) > 0
4138 && INTVAL (operands[2]) <= 8)
4139 return "addq%.l %2,%0";
4140 if (INTVAL (operands[2]) < 0
4141 && INTVAL (operands[2]) >= -8)
4143 operands[2] = GEN_INT (- INTVAL (operands[2]));
4144 return "subq%.l %2,%0";
4146 /* On the CPU32 it is faster to use two addql instructions to
4147 add a small integer (8 < N <= 16) to a register.
4148 Likewise for subql. */
4149 if (TUNE_CPU32 && REG_P (operands[0]))
4151 if (INTVAL (operands[2]) > 8
4152 && INTVAL (operands[2]) <= 16)
4154 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
4155 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4157 if (INTVAL (operands[2]) < -8
4158 && INTVAL (operands[2]) >= -16)
4160 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
4161 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4164 if (ADDRESS_REG_P (operands[0])
4165 && INTVAL (operands[2]) >= -0x8000
4166 && INTVAL (operands[2]) < 0x8000)
4169 return "add%.w %2,%0";
4171 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4174 return "add%.l %2,%0";
4177 /* Store in cc_status the expressions that the condition codes will
4178 describe after execution of an instruction whose pattern is EXP.
4179 Do not alter them if the instruction would not alter the cc's. */
4181 /* On the 68000, all the insns to store in an address register fail to
4182 set the cc's. However, in some cases these instructions can make it
4183 possibly invalid to use the saved cc's. In those cases we clear out
4184 some or all of the saved cc's so they won't be used. */
4187 notice_update_cc (rtx exp, rtx insn)
4189 if (GET_CODE (exp) == SET)
4191 if (GET_CODE (SET_SRC (exp)) == CALL)
4193 else if (ADDRESS_REG_P (SET_DEST (exp)))
4195 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
4196 cc_status.value1 = 0;
4197 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
4198 cc_status.value2 = 0;
4200 /* fmoves to memory or data registers do not set the condition
4201 codes. Normal moves _do_ set the condition codes, but not in
4202 a way that is appropriate for comparison with 0, because -0.0
4203 would be treated as a negative nonzero number. Note that it
4204 isn't appropriate to conditionalize this restriction on
4205 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4206 we care about the difference between -0.0 and +0.0. */
4207 else if (!FP_REG_P (SET_DEST (exp))
4208 && SET_DEST (exp) != cc0_rtx
4209 && (FP_REG_P (SET_SRC (exp))
4210 || GET_CODE (SET_SRC (exp)) == FIX
4211 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
4213 /* A pair of move insns doesn't produce a useful overall cc. */
4214 else if (!FP_REG_P (SET_DEST (exp))
4215 && !FP_REG_P (SET_SRC (exp))
4216 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
4217 && (GET_CODE (SET_SRC (exp)) == REG
4218 || GET_CODE (SET_SRC (exp)) == MEM
4219 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
4221 else if (SET_DEST (exp) != pc_rtx)
4223 cc_status.flags = 0;
4224 cc_status.value1 = SET_DEST (exp);
4225 cc_status.value2 = SET_SRC (exp);
4228 else if (GET_CODE (exp) == PARALLEL
4229 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
4231 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
4232 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
4234 if (ADDRESS_REG_P (dest))
4236 else if (dest != pc_rtx)
4238 cc_status.flags = 0;
4239 cc_status.value1 = dest;
4240 cc_status.value2 = src;
4245 if (cc_status.value2 != 0
4246 && ADDRESS_REG_P (cc_status.value2)
4247 && GET_MODE (cc_status.value2) == QImode)
4249 if (cc_status.value2 != 0)
4250 switch (GET_CODE (cc_status.value2))
4252 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
4253 case ROTATE: case ROTATERT:
4254 /* These instructions always clear the overflow bit, and set
4255 the carry to the bit shifted out. */
4256 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
4259 case PLUS: case MINUS: case MULT:
4260 case DIV: case UDIV: case MOD: case UMOD: case NEG:
4261 if (GET_MODE (cc_status.value2) != VOIDmode)
4262 cc_status.flags |= CC_NO_OVERFLOW;
4265 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4266 ends with a move insn moving r2 in r2's mode.
4267 Thus, the cc's are set for r2.
4268 This can set N bit spuriously. */
4269 cc_status.flags |= CC_NOT_NEGATIVE;
4274 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
4276 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
4277 cc_status.value2 = 0;
4278 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
4279 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
4280 cc_status.flags = CC_IN_68881;
4281 if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
4282 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT)
4284 cc_status.flags = CC_IN_68881;
4285 if (!FP_REG_P (XEXP (cc_status.value2, 0)))
4286 cc_status.flags |= CC_REVERSED;
4291 output_move_const_double (rtx *operands)
4293 int code = standard_68881_constant_p (operands[1]);
4297 static char buf[40];
4299 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
4302 return "fmove%.d %1,%0";
4306 output_move_const_single (rtx *operands)
4308 int code = standard_68881_constant_p (operands[1]);
4312 static char buf[40];
4314 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
4317 return "fmove%.s %f1,%0";
4320 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4321 from the "fmovecr" instruction.
4322 The value, anded with 0xff, gives the code to use in fmovecr
4323 to get the desired constant. */
4325 /* This code has been fixed for cross-compilation. */
4327 static int inited_68881_table = 0;
4329 static const char *const strings_68881[7] = {
4339 static const int codes_68881[7] = {
4349 REAL_VALUE_TYPE values_68881[7];
4351 /* Set up values_68881 array by converting the decimal values
4352 strings_68881 to binary. */
4355 init_68881_table (void)
4359 enum machine_mode mode;
4362 for (i = 0; i < 7; i++)
4366 r = REAL_VALUE_ATOF (strings_68881[i], mode);
4367 values_68881[i] = r;
4369 inited_68881_table = 1;
4373 standard_68881_constant_p (rtx x)
4378 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4379 used at all on those chips. */
4383 if (! inited_68881_table)
4384 init_68881_table ();
4386 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4388 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4390 for (i = 0; i < 6; i++)
4392 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
4393 return (codes_68881[i]);
4396 if (GET_MODE (x) == SFmode)
4399 if (REAL_VALUES_EQUAL (r, values_68881[6]))
4400 return (codes_68881[6]);
4402 /* larger powers of ten in the constants ram are not used
4403 because they are not equal to a `double' C constant. */
4407 /* If X is a floating-point constant, return the logarithm of X base 2,
4408 or 0 if X is not a power of 2. */
4411 floating_exact_log2 (rtx x)
4413 REAL_VALUE_TYPE r, r1;
4416 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4418 if (REAL_VALUES_LESS (r, dconst1))
4421 exp = real_exponent (&r);
4422 real_2expN (&r1, exp, DFmode);
4423 if (REAL_VALUES_EQUAL (r1, r))
4429 /* A C compound statement to output to stdio stream STREAM the
4430 assembler syntax for an instruction operand X. X is an RTL
4433 CODE is a value that can be used to specify one of several ways
4434 of printing the operand. It is used when identical operands
4435 must be printed differently depending on the context. CODE
4436 comes from the `%' specification that was used to request
4437 printing of the operand. If the specification was just `%DIGIT'
4438 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4439 is the ASCII code for LTR.
4441 If X is a register, this macro should print the register's name.
4442 The names can be found in an array `reg_names' whose type is
4443 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4445 When the machine description has a specification `%PUNCT' (a `%'
4446 followed by a punctuation character), this macro is called with
4447 a null pointer for X and the punctuation character for CODE.
4449 The m68k specific codes are:
4451 '.' for dot needed in Motorola-style opcode names.
4452 '-' for an operand pushing on the stack:
4453 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4454 '+' for an operand pushing on the stack:
4455 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4456 '@' for a reference to the top word on the stack:
4457 sp@, (sp) or (%sp) depending on the style of syntax.
4458 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4459 but & in SGS syntax).
4460 '!' for the cc register (used in an `and to cc' insn).
4461 '$' for the letter `s' in an op code, but only on the 68040.
4462 '&' for the letter `d' in an op code, but only on the 68040.
4463 '/' for register prefix needed by longlong.h.
4464 '?' for m68k_library_id_string
4466 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4467 'd' to force memory addressing to be absolute, not relative.
4468 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4469 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4470 or print pair of registers as rx:ry.
4471 'p' print an address with @PLTPC attached, but only if the operand
4472 is not locally-bound. */
4475 print_operand (FILE *file, rtx op, int letter)
4480 fprintf (file, ".");
4482 else if (letter == '#')
4483 asm_fprintf (file, "%I");
4484 else if (letter == '-')
4485 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
4486 else if (letter == '+')
4487 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
4488 else if (letter == '@')
4489 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
4490 else if (letter == '!')
4491 asm_fprintf (file, "%Rfpcr");
4492 else if (letter == '$')
4495 fprintf (file, "s");
4497 else if (letter == '&')
4500 fprintf (file, "d");
4502 else if (letter == '/')
4503 asm_fprintf (file, "%R");
4504 else if (letter == '?')
4505 asm_fprintf (file, m68k_library_id_string);
4506 else if (letter == 'p')
4508 output_addr_const (file, op);
4509 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
4510 fprintf (file, "@PLTPC");
4512 else if (GET_CODE (op) == REG)
4515 /* Print out the second register name of a register pair.
4516 I.e., R (6) => 7. */
4517 fputs (M68K_REGNAME(REGNO (op) + 1), file);
4519 fputs (M68K_REGNAME(REGNO (op)), file);
4521 else if (GET_CODE (op) == MEM)
4523 output_address (XEXP (op, 0));
4524 if (letter == 'd' && ! TARGET_68020
4525 && CONSTANT_ADDRESS_P (XEXP (op, 0))
4526 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
4527 && INTVAL (XEXP (op, 0)) < 0x8000
4528 && INTVAL (XEXP (op, 0)) >= -0x8000))
4529 fprintf (file, MOTOROLA ? ".l" : ":l");
4531 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
4535 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
4536 REAL_VALUE_TO_TARGET_SINGLE (r, l);
4537 asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF);
4539 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
4543 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
4544 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
4545 asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF,
4546 l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF);
4548 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
4552 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
4553 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
4554 asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF);
4558 /* Use `print_operand_address' instead of `output_addr_const'
4559 to ensure that we print relevant PIC stuff. */
4560 asm_fprintf (file, "%I");
4562 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
4563 print_operand_address (file, op);
4565 output_addr_const (file, op);
4569 /* Return string for TLS relocation RELOC. */
4572 m68k_get_reloc_decoration (enum m68k_reloc reloc)
4574 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4575 gcc_assert (MOTOROLA || reloc == RELOC_GOT);
4582 if (flag_pic == 1 && TARGET_68020)
4623 /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */
4626 m68k_output_addr_const_extra (FILE *file, rtx x)
4628 if (GET_CODE (x) == UNSPEC)
4630 switch (XINT (x, 1))
4632 case UNSPEC_RELOC16:
4633 case UNSPEC_RELOC32:
4634 output_addr_const (file, XVECEXP (x, 0, 0));
4635 fputs (m68k_get_reloc_decoration
4636 ((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file);
4647 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4650 m68k_output_dwarf_dtprel (FILE *file, int size, rtx x)
4652 gcc_assert (size == 4);
4653 fputs ("\t.long\t", file);
4654 output_addr_const (file, x);
4655 fputs ("@TLSLDO+0x8000", file);
4658 /* In the name of slightly smaller debug output, and to cater to
4659 general assembler lossage, recognize various UNSPEC sequences
4660 and turn them back into a direct symbol reference. */
4663 m68k_delegitimize_address (rtx orig_x)
4666 struct m68k_address addr;
4669 orig_x = delegitimize_mem_from_attrs (orig_x);
4674 if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
4677 if (!m68k_decompose_address (GET_MODE (x), x, false, &addr)
4678 || addr.offset == NULL_RTX
4679 || GET_CODE (addr.offset) != CONST)
4682 unspec = XEXP (addr.offset, 0);
4683 if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1)))
4684 unspec = XEXP (unspec, 0);
4685 if (GET_CODE (unspec) != UNSPEC
4686 || (XINT (unspec, 1) != UNSPEC_RELOC16
4687 && XINT (unspec, 1) != UNSPEC_RELOC32))
4689 x = XVECEXP (unspec, 0, 0);
4690 gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF);
4691 if (unspec != XEXP (addr.offset, 0))
4692 x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1));
4695 rtx idx = addr.index;
4696 if (addr.scale != 1)
4697 idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale));
4698 x = gen_rtx_PLUS (Pmode, idx, x);
4701 x = gen_rtx_PLUS (Pmode, addr.base, x);
4703 x = replace_equiv_address_nv (orig_x, x);
4708 /* A C compound statement to output to stdio stream STREAM the
4709 assembler syntax for an instruction operand that is a memory
4710 reference whose address is ADDR. ADDR is an RTL expression.
4712 Note that this contains a kludge that knows that the only reason
4713 we have an address (plus (label_ref...) (reg...)) when not generating
4714 PIC code is in the insn before a tablejump, and we know that m68k.md
4715 generates a label LInnn: on such an insn.
4717 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4718 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4720 This routine is responsible for distinguishing between -fpic and -fPIC
4721 style relocations in an address. When generating -fpic code the
4722 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4723 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4726 print_operand_address (FILE *file, rtx addr)
4728 struct m68k_address address;
4730 if (!m68k_decompose_address (QImode, addr, true, &address))
4733 if (address.code == PRE_DEC)
4734 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
4735 M68K_REGNAME (REGNO (address.base)));
4736 else if (address.code == POST_INC)
4737 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
4738 M68K_REGNAME (REGNO (address.base)));
4739 else if (!address.base && !address.index)
4741 /* A constant address. */
4742 gcc_assert (address.offset == addr);
4743 if (GET_CODE (addr) == CONST_INT)
4745 /* (xxx).w or (xxx).l. */
4746 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
4747 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
4749 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
4751 else if (TARGET_PCREL)
4753 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4755 output_addr_const (file, addr);
4756 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4760 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4761 name ends in `.<letter>', as the last 2 characters can be
4762 mistaken as a size suffix. Put the name in parentheses. */
4763 if (GET_CODE (addr) == SYMBOL_REF
4764 && strlen (XSTR (addr, 0)) > 2
4765 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
4768 output_addr_const (file, addr);
4772 output_addr_const (file, addr);
4779 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4780 label being accessed, otherwise it is -1. */
4781 labelno = (address.offset
4783 && GET_CODE (address.offset) == LABEL_REF
4784 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
4788 /* Print the "offset(base" component. */
4790 asm_fprintf (file, "%LL%d(%Rpc,", labelno);
4794 output_addr_const (file, address.offset);
4798 fputs (M68K_REGNAME (REGNO (address.base)), file);
4800 /* Print the ",index" component, if any. */
4805 fprintf (file, "%s.%c",
4806 M68K_REGNAME (REGNO (address.index)),
4807 GET_MODE (address.index) == HImode ? 'w' : 'l');
4808 if (address.scale != 1)
4809 fprintf (file, "*%d", address.scale);
4813 else /* !MOTOROLA */
4815 if (!address.offset && !address.index)
4816 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
4819 /* Print the "base@(offset" component. */
4821 asm_fprintf (file, "%Rpc@(%LL%d", labelno);
4825 fputs (M68K_REGNAME (REGNO (address.base)), file);
4826 fprintf (file, "@(");
4828 output_addr_const (file, address.offset);
4830 /* Print the ",index" component, if any. */
4833 fprintf (file, ",%s:%c",
4834 M68K_REGNAME (REGNO (address.index)),
4835 GET_MODE (address.index) == HImode ? 'w' : 'l');
4836 if (address.scale != 1)
4837 fprintf (file, ":%d", address.scale);
4845 /* Check for cases where a clr insns can be omitted from code using
4846 strict_low_part sets. For example, the second clrl here is not needed:
4847 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4849 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4850 insn we are checking for redundancy. TARGET is the register set by the
4854 strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn,
4859 while ((p = PREV_INSN (p)))
4861 if (NOTE_INSN_BASIC_BLOCK_P (p))
4867 /* If it isn't an insn, then give up. */
4871 if (reg_set_p (target, p))
4873 rtx set = single_set (p);
4876 /* If it isn't an easy to recognize insn, then give up. */
4880 dest = SET_DEST (set);
4882 /* If this sets the entire target register to zero, then our
4883 first_insn is redundant. */
4884 if (rtx_equal_p (dest, target)
4885 && SET_SRC (set) == const0_rtx)
4887 else if (GET_CODE (dest) == STRICT_LOW_PART
4888 && GET_CODE (XEXP (dest, 0)) == REG
4889 && REGNO (XEXP (dest, 0)) == REGNO (target)
4890 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
4891 <= GET_MODE_SIZE (mode)))
4892 /* This is a strict low part set which modifies less than
4893 we are using, so it is safe. */
4903 /* Operand predicates for implementing asymmetric pc-relative addressing
4904 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4905 when used as a source operand, but not as a destination operand.
4907 We model this by restricting the meaning of the basic predicates
4908 (general_operand, memory_operand, etc) to forbid the use of this
4909 addressing mode, and then define the following predicates that permit
4910 this addressing mode. These predicates can then be used for the
4911 source operands of the appropriate instructions.
4913 n.b. While it is theoretically possible to change all machine patterns
4914 to use this addressing more where permitted by the architecture,
4915 it has only been implemented for "common" cases: SImode, HImode, and
4916 QImode operands, and only for the principle operations that would
4917 require this addressing mode: data movement and simple integer operations.
4919 In parallel with these new predicates, two new constraint letters
4920 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4921 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4922 In the pcrel case 's' is only valid in combination with 'a' registers.
4923 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4924 of how these constraints are used.
4926 The use of these predicates is strictly optional, though patterns that
4927 don't will cause an extra reload register to be allocated where one
4930 lea (abc:w,%pc),%a0 ; need to reload address
4931 moveq &1,%d1 ; since write to pc-relative space
4932 movel %d1,%a0@ ; is not allowed
4934 lea (abc:w,%pc),%a1 ; no need to reload address here
4935 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4937 For more info, consult tiemann@cygnus.com.
4940 All of the ugliness with predicates and constraints is due to the
4941 simple fact that the m68k does not allow a pc-relative addressing
4942 mode as a destination. gcc does not distinguish between source and
4943 destination addresses. Hence, if we claim that pc-relative address
4944 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4945 end up with invalid code. To get around this problem, we left
4946 pc-relative modes as invalid addresses, and then added special
4947 predicates and constraints to accept them.
4949 A cleaner way to handle this is to modify gcc to distinguish
4950 between source and destination addresses. We can then say that
4951 pc-relative is a valid source address but not a valid destination
4952 address, and hopefully avoid a lot of the predicate and constraint
4953 hackery. Unfortunately, this would be a pretty big change. It would
4954 be a useful change for a number of ports, but there aren't any current
4955 plans to undertake this.
4957 ***************************************************************************/
4961 output_andsi3 (rtx *operands)
4964 if (GET_CODE (operands[2]) == CONST_INT
4965 && (INTVAL (operands[2]) | 0xffff) == -1
4966 && (DATA_REG_P (operands[0])
4967 || offsettable_memref_p (operands[0]))
4968 && !TARGET_COLDFIRE)
4970 if (GET_CODE (operands[0]) != REG)
4971 operands[0] = adjust_address (operands[0], HImode, 2);
4972 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4973 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4975 if (operands[2] == const0_rtx)
4977 return "and%.w %2,%0";
4979 if (GET_CODE (operands[2]) == CONST_INT
4980 && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0
4981 && (DATA_REG_P (operands[0])
4982 || offsettable_memref_p (operands[0])))
4984 if (DATA_REG_P (operands[0]))
4985 operands[1] = GEN_INT (logval);
4988 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4989 operands[1] = GEN_INT (logval % 8);
4991 /* This does not set condition codes in a standard way. */
4993 return "bclr %1,%0";
4995 return "and%.l %2,%0";
4999 output_iorsi3 (rtx *operands)
5001 register int logval;
5002 if (GET_CODE (operands[2]) == CONST_INT
5003 && INTVAL (operands[2]) >> 16 == 0
5004 && (DATA_REG_P (operands[0])
5005 || offsettable_memref_p (operands[0]))
5006 && !TARGET_COLDFIRE)
5008 if (GET_CODE (operands[0]) != REG)
5009 operands[0] = adjust_address (operands[0], HImode, 2);
5010 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5012 if (INTVAL (operands[2]) == 0xffff)
5013 return "mov%.w %2,%0";
5014 return "or%.w %2,%0";
5016 if (GET_CODE (operands[2]) == CONST_INT
5017 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
5018 && (DATA_REG_P (operands[0])
5019 || offsettable_memref_p (operands[0])))
5021 if (DATA_REG_P (operands[0]))
5022 operands[1] = GEN_INT (logval);
5025 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
5026 operands[1] = GEN_INT (logval % 8);
5029 return "bset %1,%0";
5031 return "or%.l %2,%0";
5035 output_xorsi3 (rtx *operands)
5037 register int logval;
5038 if (GET_CODE (operands[2]) == CONST_INT
5039 && INTVAL (operands[2]) >> 16 == 0
5040 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
5041 && !TARGET_COLDFIRE)
5043 if (! DATA_REG_P (operands[0]))
5044 operands[0] = adjust_address (operands[0], HImode, 2);
5045 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5047 if (INTVAL (operands[2]) == 0xffff)
5049 return "eor%.w %2,%0";
5051 if (GET_CODE (operands[2]) == CONST_INT
5052 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
5053 && (DATA_REG_P (operands[0])
5054 || offsettable_memref_p (operands[0])))
5056 if (DATA_REG_P (operands[0]))
5057 operands[1] = GEN_INT (logval);
5060 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
5061 operands[1] = GEN_INT (logval % 8);
5064 return "bchg %1,%0";
5066 return "eor%.l %2,%0";
5069 /* Return the instruction that should be used for a call to address X,
5070 which is known to be in operand 0. */
5075 if (symbolic_operand (x, VOIDmode))
5076 return m68k_symbolic_call;
5081 /* Likewise sibling calls. */
5084 output_sibcall (rtx x)
5086 if (symbolic_operand (x, VOIDmode))
5087 return m68k_symbolic_jump;
5093 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
5094 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
5097 rtx this_slot, offset, addr, mem, insn, tmp;
5099 /* Avoid clobbering the struct value reg by using the
5100 static chain reg as a temporary. */
5101 tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
5103 /* Pretend to be a post-reload pass while generating rtl. */
5104 reload_completed = 1;
5106 /* The "this" pointer is stored at 4(%sp). */
5107 this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4));
5109 /* Add DELTA to THIS. */
5112 /* Make the offset a legitimate operand for memory addition. */
5113 offset = GEN_INT (delta);
5114 if ((delta < -8 || delta > 8)
5115 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
5117 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
5118 offset = gen_rtx_REG (Pmode, D0_REG);
5120 emit_insn (gen_add3_insn (copy_rtx (this_slot),
5121 copy_rtx (this_slot), offset));
5124 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5125 if (vcall_offset != 0)
5127 /* Set the static chain register to *THIS. */
5128 emit_move_insn (tmp, this_slot);
5129 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
5131 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5132 addr = plus_constant (tmp, vcall_offset);
5133 if (!m68k_legitimate_address_p (Pmode, addr, true))
5135 emit_insn (gen_rtx_SET (VOIDmode, tmp, addr));
5139 /* Load the offset into %d0 and add it to THIS. */
5140 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
5141 gen_rtx_MEM (Pmode, addr));
5142 emit_insn (gen_add3_insn (copy_rtx (this_slot),
5143 copy_rtx (this_slot),
5144 gen_rtx_REG (Pmode, D0_REG)));
5147 /* Jump to the target function. Use a sibcall if direct jumps are
5148 allowed, otherwise load the address into a register first. */
5149 mem = DECL_RTL (function);
5150 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
5152 gcc_assert (flag_pic);
5154 if (!TARGET_SEP_DATA)
5156 /* Use the static chain register as a temporary (call-clobbered)
5157 GOT pointer for this function. We can use the static chain
5158 register because it isn't live on entry to the thunk. */
5159 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
5160 emit_insn (gen_load_got (pic_offset_table_rtx));
5162 legitimize_pic_address (XEXP (mem, 0), Pmode, tmp);
5163 mem = replace_equiv_address (mem, tmp);
5165 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
5166 SIBLING_CALL_P (insn) = 1;
5168 /* Run just enough of rest_of_compilation. */
5169 insn = get_insns ();
5170 split_all_insns_noflow ();
5171 final_start_function (insn, file, 1);
5172 final (insn, file, 1);
5173 final_end_function ();
5175 /* Clean up the vars set above. */
5176 reload_completed = 0;
5178 /* Restore the original PIC register. */
5180 SET_REGNO (pic_offset_table_rtx, PIC_REG);
5183 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5186 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
5187 int incoming ATTRIBUTE_UNUSED)
5189 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
5192 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5194 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5195 unsigned int new_reg)
5198 /* Interrupt functions can only use registers that have already been
5199 saved by the prologue, even if they would normally be
5202 if ((m68k_get_function_kind (current_function_decl)
5203 == m68k_fk_interrupt_handler)
5204 && !df_regs_ever_live_p (new_reg))
5210 /* Value is true if hard register REGNO can hold a value of machine-mode
5211 MODE. On the 68000, we let the cpu registers can hold any mode, but
5212 restrict the 68881 registers to floating-point modes. */
5215 m68k_regno_mode_ok (int regno, enum machine_mode mode)
5217 if (DATA_REGNO_P (regno))
5219 /* Data Registers, can hold aggregate if fits in. */
5220 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
5223 else if (ADDRESS_REGNO_P (regno))
5225 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
5228 else if (FP_REGNO_P (regno))
5230 /* FPU registers, hold float or complex float of long double or
5232 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5233 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5234 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
5240 /* Implement SECONDARY_RELOAD_CLASS. */
5243 m68k_secondary_reload_class (enum reg_class rclass,
5244 enum machine_mode mode, rtx x)
5248 regno = true_regnum (x);
5250 /* If one operand of a movqi is an address register, the other
5251 operand must be a general register or constant. Other types
5252 of operand must be reloaded through a data register. */
5253 if (GET_MODE_SIZE (mode) == 1
5254 && reg_classes_intersect_p (rclass, ADDR_REGS)
5255 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
5258 /* PC-relative addresses must be loaded into an address register first. */
5260 && !reg_class_subset_p (rclass, ADDR_REGS)
5261 && symbolic_operand (x, VOIDmode))
5267 /* Implement PREFERRED_RELOAD_CLASS. */
5270 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
5272 enum reg_class secondary_class;
5274 /* If RCLASS might need a secondary reload, try restricting it to
5275 a class that doesn't. */
5276 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
5277 if (secondary_class != NO_REGS
5278 && reg_class_subset_p (secondary_class, rclass))
5279 return secondary_class;
5281 /* Prefer to use moveq for in-range constants. */
5282 if (GET_CODE (x) == CONST_INT
5283 && reg_class_subset_p (DATA_REGS, rclass)
5284 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
5287 /* ??? Do we really need this now? */
5288 if (GET_CODE (x) == CONST_DOUBLE
5289 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5291 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
5300 /* Return floating point values in a 68881 register. This makes 68881 code
5301 a little bit faster. It also makes -msoft-float code incompatible with
5302 hard-float code, so people have to be careful not to mix the two.
5303 For ColdFire it was decided the ABI incompatibility is undesirable.
5304 If there is need for a hard-float ABI it is probably worth doing it
5305 properly and also passing function arguments in FP registers. */
5307 m68k_libcall_value (enum machine_mode mode)
5314 return gen_rtx_REG (mode, FP0_REG);
5320 return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG);
5323 /* Location in which function value is returned.
5324 NOTE: Due to differences in ABIs, don't call this function directly,
5325 use FUNCTION_VALUE instead. */
5327 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
5329 enum machine_mode mode;
5331 mode = TYPE_MODE (valtype);
5337 return gen_rtx_REG (mode, FP0_REG);
5343 /* If the function returns a pointer, push that into %a0. */
5344 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
5345 /* For compatibility with the large body of existing code which
5346 does not always properly declare external functions returning
5347 pointer types, the m68k/SVR4 convention is to copy the value
5348 returned for pointer functions from a0 to d0 in the function
5349 epilogue, so that callers that have neglected to properly
5350 declare the callee can still find the correct return value in
5352 return gen_rtx_PARALLEL
5355 gen_rtx_EXPR_LIST (VOIDmode,
5356 gen_rtx_REG (mode, A0_REG),
5358 gen_rtx_EXPR_LIST (VOIDmode,
5359 gen_rtx_REG (mode, D0_REG),
5361 else if (POINTER_TYPE_P (valtype))
5362 return gen_rtx_REG (mode, A0_REG);
5364 return gen_rtx_REG (mode, D0_REG);
5367 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5368 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5370 m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5372 enum machine_mode mode = TYPE_MODE (type);
5374 if (mode == BLKmode)
5377 /* If TYPE's known alignment is less than the alignment of MODE that
5378 would contain the structure, then return in memory. We need to
5379 do so to maintain the compatibility between code compiled with
5380 -mstrict-align and that compiled with -mno-strict-align. */
5381 if (AGGREGATE_TYPE_P (type)
5382 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
5389 /* CPU to schedule the program for. */
5390 enum attr_cpu m68k_sched_cpu;
5392 /* MAC to schedule the program for. */
5393 enum attr_mac m68k_sched_mac;
5401 /* Integer register. */
5407 /* Implicit mem reference (e.g. stack). */
5410 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5413 /* Memory with offset but without indexing. EA mode 5. */
5416 /* Memory with indexing. EA mode 6. */
5419 /* Memory referenced by absolute address. EA mode 7. */
5422 /* Immediate operand that doesn't require extension word. */
5425 /* Immediate 16 bit operand. */
5428 /* Immediate 32 bit operand. */
5432 /* Return type of memory ADDR_RTX refers to. */
5433 static enum attr_op_type
5434 sched_address_type (enum machine_mode mode, rtx addr_rtx)
5436 struct m68k_address address;
5438 if (symbolic_operand (addr_rtx, VOIDmode))
5439 return OP_TYPE_MEM7;
5441 if (!m68k_decompose_address (mode, addr_rtx,
5442 reload_completed, &address))
5444 gcc_assert (!reload_completed);
5445 /* Reload will likely fix the address to be in the register. */
5446 return OP_TYPE_MEM234;
5449 if (address.scale != 0)
5450 return OP_TYPE_MEM6;
5452 if (address.base != NULL_RTX)
5454 if (address.offset == NULL_RTX)
5455 return OP_TYPE_MEM234;
5457 return OP_TYPE_MEM5;
5460 gcc_assert (address.offset != NULL_RTX);
5462 return OP_TYPE_MEM7;
5465 /* Return X or Y (depending on OPX_P) operand of INSN. */
5467 sched_get_operand (rtx insn, bool opx_p)
5471 if (recog_memoized (insn) < 0)
5474 extract_constrain_insn_cached (insn);
5477 i = get_attr_opx (insn);
5479 i = get_attr_opy (insn);
5481 if (i >= recog_data.n_operands)
5484 return recog_data.operand[i];
5487 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5488 If ADDRESS_P is true, return type of memory location operand refers to. */
5489 static enum attr_op_type
5490 sched_attr_op_type (rtx insn, bool opx_p, bool address_p)
5494 op = sched_get_operand (insn, opx_p);
5498 gcc_assert (!reload_completed);
5503 return sched_address_type (QImode, op);
5505 if (memory_operand (op, VOIDmode))
5506 return sched_address_type (GET_MODE (op), XEXP (op, 0));
5508 if (register_operand (op, VOIDmode))
5510 if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op)))
5511 || (reload_completed && FP_REG_P (op)))
5517 if (GET_CODE (op) == CONST_INT)
5523 /* Check for quick constants. */
5524 switch (get_attr_type (insn))
5527 if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1))
5528 return OP_TYPE_IMM_Q;
5530 gcc_assert (!reload_completed);
5534 if (USE_MOVQ (ival))
5535 return OP_TYPE_IMM_Q;
5537 gcc_assert (!reload_completed);
5541 if (valid_mov3q_const (ival))
5542 return OP_TYPE_IMM_Q;
5544 gcc_assert (!reload_completed);
5551 if (IN_RANGE (ival, -0x8000, 0x7fff))
5552 return OP_TYPE_IMM_W;
5554 return OP_TYPE_IMM_L;
5557 if (GET_CODE (op) == CONST_DOUBLE)
5559 switch (GET_MODE (op))
5562 return OP_TYPE_IMM_W;
5566 return OP_TYPE_IMM_L;
5573 if (GET_CODE (op) == CONST
5574 || symbolic_operand (op, VOIDmode)
5577 switch (GET_MODE (op))
5580 return OP_TYPE_IMM_Q;
5583 return OP_TYPE_IMM_W;
5586 return OP_TYPE_IMM_L;
5589 if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode))
5591 return OP_TYPE_IMM_W;
5593 return OP_TYPE_IMM_L;
5597 gcc_assert (!reload_completed);
5599 if (FLOAT_MODE_P (GET_MODE (op)))
5605 /* Implement opx_type attribute.
5606 Return type of INSN's operand X.
5607 If ADDRESS_P is true, return type of memory location operand refers to. */
5609 m68k_sched_attr_opx_type (rtx insn, int address_p)
5611 switch (sched_attr_op_type (insn, true, address_p != 0))
5617 return OPX_TYPE_FPN;
5620 return OPX_TYPE_MEM1;
5622 case OP_TYPE_MEM234:
5623 return OPX_TYPE_MEM234;
5626 return OPX_TYPE_MEM5;
5629 return OPX_TYPE_MEM6;
5632 return OPX_TYPE_MEM7;
5635 return OPX_TYPE_IMM_Q;
5638 return OPX_TYPE_IMM_W;
5641 return OPX_TYPE_IMM_L;
5648 /* Implement opy_type attribute.
5649 Return type of INSN's operand Y.
5650 If ADDRESS_P is true, return type of memory location operand refers to. */
5652 m68k_sched_attr_opy_type (rtx insn, int address_p)
5654 switch (sched_attr_op_type (insn, false, address_p != 0))
5660 return OPY_TYPE_FPN;
5663 return OPY_TYPE_MEM1;
5665 case OP_TYPE_MEM234:
5666 return OPY_TYPE_MEM234;
5669 return OPY_TYPE_MEM5;
5672 return OPY_TYPE_MEM6;
5675 return OPY_TYPE_MEM7;
5678 return OPY_TYPE_IMM_Q;
5681 return OPY_TYPE_IMM_W;
5684 return OPY_TYPE_IMM_L;
5691 /* Return size of INSN as int. */
5693 sched_get_attr_size_int (rtx insn)
5697 switch (get_attr_type (insn))
5700 /* There should be no references to m68k_sched_attr_size for 'ignore'
5714 switch (get_attr_opx_type (insn))
5720 case OPX_TYPE_MEM234:
5721 case OPY_TYPE_IMM_Q:
5726 /* Here we assume that most absolute references are short. */
5728 case OPY_TYPE_IMM_W:
5732 case OPY_TYPE_IMM_L:
5740 switch (get_attr_opy_type (insn))
5746 case OPY_TYPE_MEM234:
5747 case OPY_TYPE_IMM_Q:
5752 /* Here we assume that most absolute references are short. */
5754 case OPY_TYPE_IMM_W:
5758 case OPY_TYPE_IMM_L:
5768 gcc_assert (!reload_completed);
5776 /* Return size of INSN as attribute enum value. */
5778 m68k_sched_attr_size (rtx insn)
5780 switch (sched_get_attr_size_int (insn))
5796 /* Return operand X or Y (depending on OPX_P) of INSN,
5797 if it is a MEM, or NULL overwise. */
5798 static enum attr_op_type
5799 sched_get_opxy_mem_type (rtx insn, bool opx_p)
5803 switch (get_attr_opx_type (insn))
5808 case OPX_TYPE_IMM_Q:
5809 case OPX_TYPE_IMM_W:
5810 case OPX_TYPE_IMM_L:
5814 case OPX_TYPE_MEM234:
5817 return OP_TYPE_MEM1;
5820 return OP_TYPE_MEM6;
5828 switch (get_attr_opy_type (insn))
5833 case OPY_TYPE_IMM_Q:
5834 case OPY_TYPE_IMM_W:
5835 case OPY_TYPE_IMM_L:
5839 case OPY_TYPE_MEM234:
5842 return OP_TYPE_MEM1;
5845 return OP_TYPE_MEM6;
5853 /* Implement op_mem attribute. */
5855 m68k_sched_attr_op_mem (rtx insn)
5857 enum attr_op_type opx;
5858 enum attr_op_type opy;
5860 opx = sched_get_opxy_mem_type (insn, true);
5861 opy = sched_get_opxy_mem_type (insn, false);
5863 if (opy == OP_TYPE_RN && opx == OP_TYPE_RN)
5866 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1)
5868 switch (get_attr_opx_access (insn))
5884 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6)
5886 switch (get_attr_opx_access (insn))
5902 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN)
5905 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1)
5907 switch (get_attr_opx_access (insn))
5913 gcc_assert (!reload_completed);
5918 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6)
5920 switch (get_attr_opx_access (insn))
5926 gcc_assert (!reload_completed);
5931 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN)
5934 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1)
5936 switch (get_attr_opx_access (insn))
5942 gcc_assert (!reload_completed);
5947 gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6);
5948 gcc_assert (!reload_completed);
5952 /* Jump instructions types. Indexed by INSN_UID.
5953 The same rtl insn can be expanded into different asm instructions
5954 depending on the cc0_status. To properly determine type of jump
5955 instructions we scan instruction stream and map jumps types to this
5957 static enum attr_type *sched_branch_type;
5959 /* Return the type of the jump insn. */
5961 m68k_sched_branch_type (rtx insn)
5963 enum attr_type type;
5965 type = sched_branch_type[INSN_UID (insn)];
5967 gcc_assert (type != 0);
5972 /* Data for ColdFire V4 index bypass.
5973 Producer modifies register that is used as index in consumer with
5977 /* Producer instruction. */
5980 /* Consumer instruction. */
5983 /* Scale of indexed memory access within consumer.
5984 Or zero if bypass should not be effective at the moment. */
5986 } sched_cfv4_bypass_data;
5988 /* An empty state that is used in m68k_sched_adjust_cost. */
5989 static state_t sched_adjust_cost_state;
5991 /* Implement adjust_cost scheduler hook.
5992 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5994 m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn,
5999 if (recog_memoized (def_insn) < 0
6000 || recog_memoized (insn) < 0)
6003 if (sched_cfv4_bypass_data.scale == 1)
6004 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
6006 /* haifa-sched.c: insn_cost () calls bypass_p () just before
6007 targetm.sched.adjust_cost (). Hence, we can be relatively sure
6008 that the data in sched_cfv4_bypass_data is up to date. */
6009 gcc_assert (sched_cfv4_bypass_data.pro == def_insn
6010 && sched_cfv4_bypass_data.con == insn);
6015 sched_cfv4_bypass_data.pro = NULL;
6016 sched_cfv4_bypass_data.con = NULL;
6017 sched_cfv4_bypass_data.scale = 0;
6020 gcc_assert (sched_cfv4_bypass_data.pro == NULL
6021 && sched_cfv4_bypass_data.con == NULL
6022 && sched_cfv4_bypass_data.scale == 0);
6024 /* Don't try to issue INSN earlier than DFA permits.
6025 This is especially useful for instructions that write to memory,
6026 as their true dependence (default) latency is better to be set to 0
6027 to workaround alias analysis limitations.
6028 This is, in fact, a machine independent tweak, so, probably,
6029 it should be moved to haifa-sched.c: insn_cost (). */
6030 delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn);
6037 /* Return maximal number of insns that can be scheduled on a single cycle. */
6039 m68k_sched_issue_rate (void)
6041 switch (m68k_sched_cpu)
6057 /* Maximal length of instruction for current CPU.
6058 E.g. it is 3 for any ColdFire core. */
6059 static int max_insn_size;
6061 /* Data to model instruction buffer of CPU. */
6064 /* True if instruction buffer model is modeled for current CPU. */
6067 /* Size of the instruction buffer in words. */
6070 /* Number of filled words in the instruction buffer. */
6073 /* Additional information about instruction buffer for CPUs that have
6074 a buffer of instruction records, rather then a plain buffer
6075 of instruction words. */
6076 struct _sched_ib_records
6078 /* Size of buffer in records. */
6081 /* Array to hold data on adjustements made to the size of the buffer. */
6084 /* Index of the above array. */
6088 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6092 static struct _sched_ib sched_ib;
6094 /* ID of memory unit. */
6095 static int sched_mem_unit_code;
6097 /* Implementation of the targetm.sched.variable_issue () hook.
6098 It is called after INSN was issued. It returns the number of insns
6099 that can possibly get scheduled on the current cycle.
6100 It is used here to determine the effect of INSN on the instruction
6103 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
6104 int sched_verbose ATTRIBUTE_UNUSED,
6105 rtx insn, int can_issue_more)
6109 if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE)
6111 switch (m68k_sched_cpu)
6115 insn_size = sched_get_attr_size_int (insn);
6119 insn_size = sched_get_attr_size_int (insn);
6121 /* ColdFire V3 and V4 cores have instruction buffers that can
6122 accumulate up to 8 instructions regardless of instructions'
6123 sizes. So we should take care not to "prefetch" 24 one-word
6124 or 12 two-words instructions.
6125 To model this behavior we temporarily decrease size of the
6126 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6130 adjust = max_insn_size - insn_size;
6131 sched_ib.size -= adjust;
6133 if (sched_ib.filled > sched_ib.size)
6134 sched_ib.filled = sched_ib.size;
6136 sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust;
6139 ++sched_ib.records.adjust_index;
6140 if (sched_ib.records.adjust_index == sched_ib.records.n_insns)
6141 sched_ib.records.adjust_index = 0;
6143 /* Undo adjustement we did 7 instructions ago. */
6145 += sched_ib.records.adjust[sched_ib.records.adjust_index];
6150 gcc_assert (!sched_ib.enabled_p);
6158 gcc_assert (insn_size <= sched_ib.filled);
6161 else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6162 || asm_noperands (PATTERN (insn)) >= 0)
6163 insn_size = sched_ib.filled;
6167 sched_ib.filled -= insn_size;
6169 return can_issue_more;
6172 /* Return how many instructions should scheduler lookahead to choose the
6175 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6177 return m68k_sched_issue_rate () - 1;
6180 /* Implementation of targetm.sched.init_global () hook.
6181 It is invoked once per scheduling pass and is used here
6182 to initialize scheduler constants. */
6184 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
6185 int sched_verbose ATTRIBUTE_UNUSED,
6186 int n_insns ATTRIBUTE_UNUSED)
6188 /* Init branch types. */
6192 sched_branch_type = XCNEWVEC (enum attr_type, get_max_uid () + 1);
6194 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6197 /* !!! FIXME: Implement real scan here. */
6198 sched_branch_type[INSN_UID (insn)] = TYPE_BCC;
6202 #ifdef ENABLE_CHECKING
6203 /* Check that all instructions have DFA reservations and
6204 that all instructions can be issued from a clean state. */
6209 state = alloca (state_size ());
6211 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6213 if (INSN_P (insn) && recog_memoized (insn) >= 0)
6215 gcc_assert (insn_has_dfa_reservation_p (insn));
6217 state_reset (state);
6218 if (state_transition (state, insn) >= 0)
6225 /* Setup target cpu. */
6227 /* ColdFire V4 has a set of features to keep its instruction buffer full
6228 (e.g., a separate memory bus for instructions) and, hence, we do not model
6229 buffer for this CPU. */
6230 sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4);
6232 switch (m68k_sched_cpu)
6235 sched_ib.filled = 0;
6242 sched_ib.records.n_insns = 0;
6243 sched_ib.records.adjust = NULL;
6248 sched_ib.records.n_insns = 8;
6249 sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns);
6256 sched_mem_unit_code = get_cpu_unit_code ("cf_mem1");
6258 sched_adjust_cost_state = xmalloc (state_size ());
6259 state_reset (sched_adjust_cost_state);
6262 emit_insn (gen_ib ());
6263 sched_ib.insn = get_insns ();
6267 /* Scheduling pass is now finished. Free/reset static variables. */
6269 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6270 int verbose ATTRIBUTE_UNUSED)
6272 sched_ib.insn = NULL;
6274 free (sched_adjust_cost_state);
6275 sched_adjust_cost_state = NULL;
6277 sched_mem_unit_code = 0;
6279 free (sched_ib.records.adjust);
6280 sched_ib.records.adjust = NULL;
6281 sched_ib.records.n_insns = 0;
6284 free (sched_branch_type);
6285 sched_branch_type = NULL;
6288 /* Implementation of targetm.sched.init () hook.
6289 It is invoked each time scheduler starts on the new block (basic block or
6290 extended basic block). */
6292 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
6293 int sched_verbose ATTRIBUTE_UNUSED,
6294 int n_insns ATTRIBUTE_UNUSED)
6296 switch (m68k_sched_cpu)
6304 sched_ib.size = sched_ib.records.n_insns * max_insn_size;
6306 memset (sched_ib.records.adjust, 0,
6307 sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust));
6308 sched_ib.records.adjust_index = 0;
6312 gcc_assert (!sched_ib.enabled_p);
6320 if (sched_ib.enabled_p)
6321 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6322 the first cycle. Workaround that. */
6323 sched_ib.filled = -2;
6326 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6327 It is invoked just before current cycle finishes and is used here
6328 to track if instruction buffer got its two words this cycle. */
6330 m68k_sched_dfa_pre_advance_cycle (void)
6332 if (!sched_ib.enabled_p)
6335 if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
6337 sched_ib.filled += 2;
6339 if (sched_ib.filled > sched_ib.size)
6340 sched_ib.filled = sched_ib.size;
6344 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6345 It is invoked just after new cycle begins and is used here
6346 to setup number of filled words in the instruction buffer so that
6347 instructions which won't have all their words prefetched would be
6348 stalled for a cycle. */
6350 m68k_sched_dfa_post_advance_cycle (void)
6354 if (!sched_ib.enabled_p)
6357 /* Setup number of prefetched instruction words in the instruction
6359 i = max_insn_size - sched_ib.filled;
6363 if (state_transition (curr_state, sched_ib.insn) >= 0)
6368 /* Return X or Y (depending on OPX_P) operand of INSN,
6369 if it is an integer register, or NULL overwise. */
6371 sched_get_reg_operand (rtx insn, bool opx_p)
6377 if (get_attr_opx_type (insn) == OPX_TYPE_RN)
6379 op = sched_get_operand (insn, true);
6380 gcc_assert (op != NULL);
6382 if (!reload_completed && !REG_P (op))
6388 if (get_attr_opy_type (insn) == OPY_TYPE_RN)
6390 op = sched_get_operand (insn, false);
6391 gcc_assert (op != NULL);
6393 if (!reload_completed && !REG_P (op))
6401 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6404 sched_mem_operand_p (rtx insn, bool opx_p)
6406 switch (sched_get_opxy_mem_type (insn, opx_p))
6417 /* Return X or Y (depending on OPX_P) operand of INSN,
6418 if it is a MEM, or NULL overwise. */
6420 sched_get_mem_operand (rtx insn, bool must_read_p, bool must_write_p)
6440 if (opy_p && sched_mem_operand_p (insn, false))
6441 return sched_get_operand (insn, false);
6443 if (opx_p && sched_mem_operand_p (insn, true))
6444 return sched_get_operand (insn, true);
6450 /* Return non-zero if PRO modifies register used as part of
6453 m68k_sched_address_bypass_p (rtx pro, rtx con)
6458 pro_x = sched_get_reg_operand (pro, true);
6462 con_mem_read = sched_get_mem_operand (con, true, false);
6463 gcc_assert (con_mem_read != NULL);
6465 if (reg_mentioned_p (pro_x, con_mem_read))
6471 /* Helper function for m68k_sched_indexed_address_bypass_p.
6472 if PRO modifies register used as index in CON,
6473 return scale of indexed memory access in CON. Return zero overwise. */
6475 sched_get_indexed_address_scale (rtx pro, rtx con)
6479 struct m68k_address address;
6481 reg = sched_get_reg_operand (pro, true);
6485 mem = sched_get_mem_operand (con, true, false);
6486 gcc_assert (mem != NULL && MEM_P (mem));
6488 if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed,
6492 if (REGNO (reg) == REGNO (address.index))
6494 gcc_assert (address.scale != 0);
6495 return address.scale;
6501 /* Return non-zero if PRO modifies register used
6502 as index with scale 2 or 4 in CON. */
6504 m68k_sched_indexed_address_bypass_p (rtx pro, rtx con)
6506 gcc_assert (sched_cfv4_bypass_data.pro == NULL
6507 && sched_cfv4_bypass_data.con == NULL
6508 && sched_cfv4_bypass_data.scale == 0);
6510 switch (sched_get_indexed_address_scale (pro, con))
6513 /* We can't have a variable latency bypass, so
6514 remember to adjust the insn cost in adjust_cost hook. */
6515 sched_cfv4_bypass_data.pro = pro;
6516 sched_cfv4_bypass_data.con = con;
6517 sched_cfv4_bypass_data.scale = 1;
6529 /* We generate a two-instructions program at M_TRAMP :
6530 movea.l &CHAIN_VALUE,%a0
6532 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6535 m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
6537 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6540 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM));
6542 mem = adjust_address (m_tramp, HImode, 0);
6543 emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9)));
6544 mem = adjust_address (m_tramp, SImode, 2);
6545 emit_move_insn (mem, chain_value);
6547 mem = adjust_address (m_tramp, HImode, 6);
6548 emit_move_insn (mem, GEN_INT(0x4EF9));
6549 mem = adjust_address (m_tramp, SImode, 8);
6550 emit_move_insn (mem, fnaddr);
6552 FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0));
6555 /* On the 68000, the RTS insn cannot pop anything.
6556 On the 68010, the RTD insn may be used to pop them if the number
6557 of args is fixed, but if the number is variable then the caller
6558 must pop them all. RTD can't be used for library calls now
6559 because the library is compiled with the Unix compiler.
6560 Use of RTD is a selectable option, since it is incompatible with
6561 standard Unix calling sequences. If the option is not selected,
6562 the caller must always pop the args. */
6565 m68k_return_pops_args (tree fundecl, tree funtype, int size)
6569 || TREE_CODE (fundecl) != IDENTIFIER_NODE)
6570 && (!stdarg_p (funtype)))
6574 /* Make sure everything's fine if we *don't* have a given processor.
6575 This assumes that putting a register in fixed_regs will keep the
6576 compiler's mitts completely off it. We don't bother to zero it out
6577 of register classes. */
6580 m68k_conditional_register_usage (void)
6584 if (!TARGET_HARD_FLOAT)
6586 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]);
6587 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6588 if (TEST_HARD_REG_BIT (x, i))
6589 fixed_regs[i] = call_used_regs[i] = 1;
6592 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1;
6595 #include "gt-m68k.h"