1 /* Definitions of target machine for GNU compiler, Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 /* ??? Create elf.h and have svr4.h include it. */
29 #undef SWITCH_TAKES_ARG
30 #undef WORD_SWITCH_TAKES_ARG
31 #undef HANDLE_SYSV_PRAGMA
35 #undef WCHAR_TYPE_SIZE
37 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
44 #undef SUBTARGET_SWITCHES
46 /* Print subsidiary information on the compiler version in use. */
47 #ifndef TARGET_VERSION
48 #define TARGET_VERSION fprintf (stderr, " (m32r)")
51 /* Switch Recognition by gcc.c. Add -G xx support */
53 #undef SWITCH_TAKES_ARG
54 #define SWITCH_TAKES_ARG(CHAR) \
55 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
57 /* Names to predefine in the preprocessor for this target machine. */
58 /* __M32R__ is defined by the existing compiler so we use that. */
59 #define CPP_PREDEFINES "-Acpu=m32r -Amachine=m32r -D__M32R__"
61 /* This macro defines names of additional specifications to put in the specs
62 that can be used in various specifications like CC1_SPEC. Its definition
63 is an initializer with a subgrouping for each command option.
65 Each subgrouping contains a string constant, that defines the
66 specification name, and a string constant that used by the GNU CC driver
69 Do not define this macro if it does not need to do anything. */
71 #ifndef SUBTARGET_EXTRA_SPECS
72 #define SUBTARGET_EXTRA_SPECS
76 #define ASM_CPU_SPEC ""
80 #define CPP_CPU_SPEC ""
84 #define CC1_CPU_SPEC ""
88 #define LINK_CPU_SPEC ""
91 #ifndef STARTFILE_CPU_SPEC
92 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
95 #ifndef ENDFILE_CPU_SPEC
96 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
100 #if 0 /* not supported yet */
101 #define RELAX_SPEC "%{mrelax:-relax}"
103 #define RELAX_SPEC ""
107 #define EXTRA_SPECS \
108 { "asm_cpu", ASM_CPU_SPEC }, \
109 { "cpp_cpu", CPP_CPU_SPEC }, \
110 { "cc1_cpu", CC1_CPU_SPEC }, \
111 { "link_cpu", LINK_CPU_SPEC }, \
112 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
113 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
114 { "relax", RELAX_SPEC }, \
115 SUBTARGET_EXTRA_SPECS
117 #define CC1_SPEC "%{G*} %(cc1_cpu)"
119 /* Options to pass on to the assembler. */
121 #define ASM_SPEC "%{v} %(asm_cpu) %(relax)"
123 #undef ASM_FINAL_SPEC
125 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
127 #undef STARTFILE_SPEC
128 #define STARTFILE_SPEC "%(startfile_cpu)"
131 #define ENDFILE_SPEC "%(endfile_cpu)"
135 /* Run-time compilation parameters selecting different hardware subsets. */
137 extern int target_flags;
139 /* If non-zero, tell the linker to do relaxing.
140 We don't do anything with the option, other than recognize it.
141 LINK_SPEC handles passing -relax to the linker.
142 This can cause incorrect debugging information as line numbers may
143 turn out wrong. This shouldn't be specified unless accompanied with -O2
144 [where the user expects debugging information to be less accurate]. */
145 #define TARGET_RELAX_MASK (1 << 0)
147 /* For miscellaneous debugging purposes. */
148 #define TARGET_DEBUG_MASK (1 << 1)
149 #define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
151 /* Align loops to 32 byte boundaries (cache line size). */
152 /* ??? This option is experimental and is not documented. */
153 #define TARGET_ALIGN_LOOPS_MASK (1 << 2)
154 #define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
156 /* Change issue rate. */
157 #define TARGET_ISSUE_RATE_MASK (1 << 3)
158 #define TARGET_ISSUE_RATE (target_flags & TARGET_ISSUE_RATE_MASK)
160 /* Change branch cost */
161 #define TARGET_BRANCH_COST_MASK (1 << 4)
162 #define TARGET_BRANCH_COST (target_flags & TARGET_BRANCH_COST_MASK)
164 /* Target machine to compile for. */
165 #define TARGET_M32R 1
167 /* Macro to define tables used to set the flags.
168 This is a list in braces of pairs in braces,
169 each pair being { "NAME", VALUE }
170 where VALUE is the bits to set or minus the bits to clear.
171 An empty string NAME is used to identify the default VALUE. */
173 #ifndef SUBTARGET_SWITCHES
174 #define SUBTARGET_SWITCHES
177 #ifndef TARGET_DEFAULT
178 #define TARGET_DEFAULT 0
181 #define TARGET_SWITCHES \
183 /* { "relax", TARGET_RELAX_MASK, "" }, \
184 { "no-relax", -TARGET_RELAX_MASK, "" },*/ \
185 { "debug", TARGET_DEBUG_MASK, \
186 N_("Display compile time statistics") }, \
187 { "align-loops", TARGET_ALIGN_LOOPS_MASK, \
188 N_("Align all loops to 32 byte boundary") }, \
189 { "no-align-loops", -TARGET_ALIGN_LOOPS_MASK, "" }, \
190 { "issue-rate=1", TARGET_ISSUE_RATE_MASK, \
191 N_("Only issue one instruction per cycle") }, \
192 { "issue-rate=2", -TARGET_ISSUE_RATE_MASK, "" }, \
193 { "branch-cost=1", TARGET_BRANCH_COST_MASK, \
194 N_("Prefer branches over conditional execution") }, \
195 { "branch-cost=2", -TARGET_BRANCH_COST_MASK, "" }, \
197 { "", TARGET_DEFAULT, "" } \
200 extern const char * m32r_model_string;
201 extern const char * m32r_sdata_string;
203 #ifndef SUBTARGET_OPTIONS
204 #define SUBTARGET_OPTIONS
207 #define TARGET_OPTIONS \
209 { "model=", & m32r_model_string, \
210 N_("Code size: small, medium or large") }, \
211 { "sdata=", & m32r_sdata_string, \
212 N_("Small data area: none, sdata, use") } \
218 Code models are used to select between two choices of two separate
219 possibilities (address space size, call insn to use):
221 small: addresses use 24 bits, use bl to make calls
222 medium: addresses use 32 bits, use bl to make calls (*1)
223 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
225 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
226 using this one doesn't make much sense.
228 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
229 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
231 Internally these are recorded as TARGET_ADDR{24,32} and
234 The __model__ attribute can be used to select the code model to use when
235 accessing particular objects. */
237 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
239 extern enum m32r_model m32r_model;
240 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
241 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
242 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
243 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
244 #define TARGET_ADDR32 (! TARGET_ADDR24)
245 #define TARGET_CALL26 (! TARGET_CALL32)
246 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
248 /* The default is the small model. */
249 #ifndef M32R_MODEL_DEFAULT
250 #define M32R_MODEL_DEFAULT "small"
255 The SDA consists of sections .sdata, .sbss, and .scommon.
256 .scommon isn't a real section, symbols in it have their section index
257 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
259 Two switches control the SDA:
261 -G NNN - specifies the maximum size of variable to go in the SDA
263 -msdata=foo - specifies how such variables are handled
265 -msdata=none - small data area is disabled
267 -msdata=sdata - small data goes in the SDA, special code isn't
268 generated to use it, and special relocs aren't
271 -msdata=use - small data goes in the SDA, special code is generated
272 to use the SDA and special relocs are generated
274 The SDA is not multilib'd, it isn't necessary.
275 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
276 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
277 -msdata=use will successfully link with them (references in header files
278 will cause the compiler to emit code that refers to library objects in
279 .data). ??? There can be a problem if the user passes a -G value greater
280 than the default and a library object in a header file is that size.
281 The default is 8 so this should be rare - if it occurs the user
282 is required to rebuild the libraries or use a smaller value for -G.
285 /* Maximum size of variables that go in .sdata/.sbss.
286 The -msdata=foo switch also controls how small variables are handled. */
287 #ifndef SDATA_DEFAULT_SIZE
288 #define SDATA_DEFAULT_SIZE 8
291 extern int g_switch_value; /* value of the -G xx switch */
292 extern int g_switch_set; /* whether -G xx was passed. */
294 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
296 extern enum m32r_sdata m32r_sdata;
297 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
298 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
299 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
301 /* Default is to disable the SDA
302 [for upward compatibility with previous toolchains]. */
303 #ifndef M32R_SDATA_DEFAULT
304 #define M32R_SDATA_DEFAULT "none"
307 /* Define this macro as a C expression for the initializer of an array of
308 strings to tell the driver program which options are defaults for this
309 target and thus do not need to be handled specially when using
310 `MULTILIB_OPTIONS'. */
311 #ifndef SUBTARGET_MULTILIB_DEFAULTS
312 #define SUBTARGET_MULTILIB_DEFAULTS
315 #ifndef MULTILIB_DEFAULTS
316 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
319 /* Sometimes certain combinations of command options do not make
320 sense on a particular target machine. You can define a macro
321 `OVERRIDE_OPTIONS' to take account of this. This macro, if
322 defined, is executed once just after all the command options have
325 Don't use this macro to turn on various extra optimizations for
326 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
328 #ifndef SUBTARGET_OVERRIDE_OPTIONS
329 #define SUBTARGET_OVERRIDE_OPTIONS
332 #define OVERRIDE_OPTIONS \
335 /* These need to be done at start up. \
336 It's convenient to do them here. */ \
338 SUBTARGET_OVERRIDE_OPTIONS \
342 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
343 #define SUBTARGET_OPTIMIZATION_OPTIONS
346 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
350 flag_regmove = TRUE; \
354 flag_omit_frame_pointer = TRUE; \
355 flag_strength_reduce = FALSE; \
358 SUBTARGET_OPTIMIZATION_OPTIONS \
362 /* Define this macro if debugging can be performed even without a
363 frame pointer. If this macro is defined, GNU CC will turn on the
364 `-fomit-frame-pointer' option whenever `-O' is specified. */
365 #define CAN_DEBUG_WITHOUT_FP
367 /* Target machine storage layout. */
369 /* Define to use software floating point emulator for REAL_ARITHMETIC and
370 decimal <-> binary conversion. */
371 #define REAL_ARITHMETIC
373 /* Define this if most significant bit is lowest numbered
374 in instructions that operate on numbered bit-fields. */
375 #define BITS_BIG_ENDIAN 1
377 /* Define this if most significant byte of a word is the lowest numbered. */
378 #define BYTES_BIG_ENDIAN 1
380 /* Define this if most significant word of a multiword number is the lowest
382 #define WORDS_BIG_ENDIAN 1
384 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
385 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
386 which will be used only when compiling libgcc2.c. Typically the
387 value will be set based on preprocessor defines. */
388 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
390 /* Number of bits in an addressable storage unit. */
391 #define BITS_PER_UNIT 8
393 /* Width in bits of a "word", which is the contents of a machine register.
394 Note that this is not necessarily the width of data type `int';
395 if using 16-bit ints on a 68000, this would still be 32.
396 But on a machine with 16-bit registers, this would be 16. */
397 #define BITS_PER_WORD 32
399 /* Width of a word, in units (bytes). */
400 #define UNITS_PER_WORD 4
402 /* Define this macro if it is advisable to hold scalars in registers
403 in a wider mode than that declared by the program. In such cases,
404 the value is constrained to be within the bounds of the declared
405 type, but kept valid in the wider mode. The signedness of the
406 extension may differ from that of the type. */
407 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
408 if (GET_MODE_CLASS (MODE) == MODE_INT \
409 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
414 /* Define this macro if the promotion described by `PROMOTE_MODE'
415 should also be done for outgoing function arguments. */
416 /*#define PROMOTE_FUNCTION_ARGS*/
418 /* Likewise, if the function return value is promoted.
419 If defined, FUNCTION_VALUE must perform the same promotions done by
421 /*#define PROMOTE_FUNCTION_RETURN*/
423 /* Width in bits of a pointer.
424 See also the macro `Pmode' defined below. */
425 #define POINTER_SIZE 32
427 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
428 #define PARM_BOUNDARY 32
430 /* Boundary (in *bits*) on which stack pointer should be aligned. */
431 #define STACK_BOUNDARY 32
433 /* ALIGN FRAMES on word boundaries */
434 #define M32R_STACK_ALIGN(LOC) (((LOC)+3) & ~3)
436 /* Allocation boundary (in *bits*) for the code of a function. */
437 #define FUNCTION_BOUNDARY 32
439 /* Alignment of field after `int : 0' in a structure. */
440 #define EMPTY_FIELD_BOUNDARY 32
442 /* Every structure's size must be a multiple of this. */
443 #define STRUCTURE_SIZE_BOUNDARY 8
445 /* A bitfield declared as `int' forces `int' alignment for the struct. */
446 #define PCC_BITFIELD_TYPE_MATTERS 1
448 /* No data type wants to be aligned rounder than this. */
449 #define BIGGEST_ALIGNMENT 32
451 /* The best alignment to use in cases where we have a choice. */
452 #define FASTEST_ALIGNMENT 32
454 /* Make strings word-aligned so strcpy from constants will be faster. */
455 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
456 ((TREE_CODE (EXP) == STRING_CST \
457 && (ALIGN) < FASTEST_ALIGNMENT) \
458 ? FASTEST_ALIGNMENT : (ALIGN))
460 /* Make arrays of chars word-aligned for the same reasons. */
461 #define DATA_ALIGNMENT(TYPE, ALIGN) \
462 (TREE_CODE (TYPE) == ARRAY_TYPE \
463 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
464 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
466 /* Set this nonzero if move instructions will actually fail to work
467 when given unaligned data. */
468 #define STRICT_ALIGNMENT 1
470 /* Layout of source language data types. */
472 #define SHORT_TYPE_SIZE 16
473 #define INT_TYPE_SIZE 32
474 #define LONG_TYPE_SIZE 32
475 #define LONG_LONG_TYPE_SIZE 64
476 #define FLOAT_TYPE_SIZE 32
477 #define DOUBLE_TYPE_SIZE 64
478 #define LONG_DOUBLE_TYPE_SIZE 64
480 /* Define this as 1 if `char' should by default be signed; else as 0. */
481 #define DEFAULT_SIGNED_CHAR 1
483 #define SIZE_TYPE "long unsigned int"
484 #define PTRDIFF_TYPE "long int"
485 #define WCHAR_TYPE "short unsigned int"
486 #define WCHAR_TYPE_SIZE 16
488 /* Standard register usage. */
490 /* Number of actual hardware registers.
491 The hardware registers are assigned numbers for the compiler
492 from 0 to just below FIRST_PSEUDO_REGISTER.
493 All registers that the compiler knows about must be given numbers,
494 even those that are not normally considered general registers. */
496 #define M32R_NUM_REGISTERS 19
498 #ifndef SUBTARGET_NUM_REGISTERS
499 #define SUBTARGET_NUM_REGISTERS 0
502 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
504 /* 1 for registers that have pervasive standard uses
505 and are not available for the register allocator.
507 0-3 - arguments/results
508 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
510 7 - call used, static chain pointer
512 12 - call saved [reserved for global pointer]
514 14 - subroutine link register
520 By default, the extension registers are not available. */
522 #ifndef SUBTARGET_FIXED_REGISTERS
523 #define SUBTARGET_FIXED_REGISTERS
526 #define FIXED_REGISTERS \
528 0, 0, 0, 0, 0, 0, 0, 0, \
529 0, 0, 0, 0, 0, 0, 0, 1, \
531 SUBTARGET_FIXED_REGISTERS \
534 /* 1 for registers not available across function calls.
535 These must include the FIXED_REGISTERS and also any
536 registers that can be used without being saved.
537 The latter must include the registers where values are returned
538 and the register where structure-value addresses are passed.
539 Aside from that, you can include as many other registers as you like. */
541 #ifndef SUBTARGET_CALL_USED_REGISTERS
542 #define SUBTARGET_CALL_USED_REGISTERS
545 #define CALL_USED_REGISTERS \
547 1, 1, 1, 1, 1, 1, 1, 1, \
548 0, 0, 0, 0, 0, 0, 1, 1, \
550 SUBTARGET_CALL_USED_REGISTERS \
553 /* Zero or more C statements that may conditionally modify two variables
554 `fixed_regs' and `call_used_regs' (both of type `char []') after they
555 have been initialized from the two preceding macros.
557 This is necessary in case the fixed or call-clobbered registers depend
560 You need not define this macro if it has no work to do. */
562 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
563 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
566 /* If defined, an initializer for a vector of integers, containing the
567 numbers of hard registers in the order in which GNU CC should
568 prefer to use them (from most preferred to least). */
570 #ifndef SUBTARGET_REG_ALLOC_ORDER
571 #define SUBTARGET_REG_ALLOC_ORDER
574 #if 1 /* better for int code */
575 #define REG_ALLOC_ORDER \
577 4, 5, 6, 7, 2, 3, 8, 9, 10, \
578 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
579 SUBTARGET_REG_ALLOC_ORDER \
582 #else /* better for fp code at expense of int code */
583 #define REG_ALLOC_ORDER \
585 0, 1, 2, 3, 4, 5, 6, 7, 8, \
586 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
587 SUBTARGET_REG_ALLOC_ORDER \
591 /* Return number of consecutive hard regs needed starting at reg REGNO
592 to hold something of mode MODE.
593 This is ordinarily the length in words of a value of mode MODE
594 but can be less for certain modes in special long registers. */
595 #define HARD_REGNO_NREGS(REGNO, MODE) \
596 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
598 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
599 extern unsigned int m32r_hard_regno_mode_ok[];
600 extern unsigned int m32r_mode_class[];
601 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
602 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
604 /* A C expression that is nonzero if it is desirable to choose
605 register allocation so as to avoid move instructions between a
606 value of mode MODE1 and a value of mode MODE2.
608 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
609 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
610 MODE2)' must be zero. */
612 /* Tie QI/HI/SI modes together. */
613 #define MODES_TIEABLE_P(MODE1, MODE2) \
614 (GET_MODE_CLASS (MODE1) == MODE_INT \
615 && GET_MODE_CLASS (MODE2) == MODE_INT \
616 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
617 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
619 /* Register classes and constants. */
621 /* Define the classes of registers for register constraints in the
622 machine description. Also define ranges of constants.
624 One of the classes must always be named ALL_REGS and include all hard regs.
625 If there is more than one class, another class must be named NO_REGS
626 and contain no registers.
628 The name GENERAL_REGS must be the name of a class (or an alias for
629 another name such as ALL_REGS). This is the class of registers
630 that is allowed by "g" or "r" in a register constraint.
631 Also, registers outside this class are allocated only when
632 instructions express preferences for them.
634 The classes must be numbered in nondecreasing order; that is,
635 a larger-numbered class must never be contained completely
636 in a smaller-numbered class.
638 For any two classes, it is very desirable that there be another
639 class that represents their union.
641 It is important that any condition codes have class NO_REGS.
642 See `register_operand'. */
646 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
649 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
651 /* Give names of register classes as strings for dump file. */
652 #define REG_CLASS_NAMES \
653 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
655 /* Define which registers fit in which classes.
656 This is an initializer for a vector of HARD_REG_SET
657 of length N_REG_CLASSES. */
659 #ifndef SUBTARGET_REG_CLASS_CARRY
660 #define SUBTARGET_REG_CLASS_CARRY 0
663 #ifndef SUBTARGET_REG_CLASS_ACCUM
664 #define SUBTARGET_REG_CLASS_ACCUM 0
667 #ifndef SUBTARGET_REG_CLASS_GENERAL
668 #define SUBTARGET_REG_CLASS_GENERAL 0
671 #ifndef SUBTARGET_REG_CLASS_ALL
672 #define SUBTARGET_REG_CLASS_ALL 0
675 #define REG_CLASS_CONTENTS \
678 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
679 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
680 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
681 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
684 /* The same information, inverted:
685 Return the class number of the smallest class containing
686 reg number REGNO. This could be a conditional expression
687 or could index an array. */
688 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
689 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
691 /* The class value for index registers, and the one for base regs. */
692 #define INDEX_REG_CLASS GENERAL_REGS
693 #define BASE_REG_CLASS GENERAL_REGS
695 #define REG_CLASS_FROM_LETTER(C) \
696 ((C) == 'c' ? CARRY_REG \
697 : (C) == 'a' ? ACCUM_REGS \
700 /* These assume that REGNO is a hard or pseudo reg number.
701 They give nonzero only if REGNO is a hard reg of the suitable class
702 or a pseudo reg currently allocated to a suitable hard reg.
703 Since they use reg_renumber, they are safe only once reg_renumber
704 has been allocated, which happens in local-alloc.c. */
705 #define REGNO_OK_FOR_BASE_P(REGNO) \
706 ((REGNO) < FIRST_PSEUDO_REGISTER \
707 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
708 : GPR_P (reg_renumber[REGNO]))
709 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
711 /* Given an rtx X being reloaded into a reg required to be
712 in class CLASS, return the class of reg to actually use.
713 In general this is just CLASS; but on some machines
714 in some cases it is preferable to use a more restrictive class. */
715 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
718 /* Return the maximum number of consecutive registers
719 needed to represent mode MODE in a register of class CLASS. */
720 #define CLASS_MAX_NREGS(CLASS, MODE) \
721 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
723 /* The letters I, J, K, L, M, N, O, P in a register constraint string
724 can be used to stand for particular ranges of immediate operands.
725 This macro defines what the ranges are.
726 C is the letter, and VALUE is a constant value.
727 Return 1 if VALUE is in the range specified by C. */
728 /* 'I' is used for 8 bit signed immediates.
729 'J' is used for 16 bit signed immediates.
730 'K' is used for 16 bit unsigned immediates.
731 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
732 'M' is used for 24 bit unsigned immediates.
733 'N' is used for any 32 bit non-symbolic value.
734 'O' is used for 5 bit unsigned immediates (shift count).
735 'P' is used for 16 bit signed immediates for compares
736 (values in the range -32767 to +32768). */
738 /* Return true if a value is inside a range. */
739 #define IN_RANGE_P(VALUE, LOW, HIGH) \
740 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
741 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
743 /* Local to this file. */
744 #define INT8_P(X) ((X) >= -0x80 && (X) <= 0x7f)
745 #define INT16_P(X) ((X) >= -0x8000 && (X) <= 0x7fff)
746 #define CMP_INT16_P(X) ((X) >= -0x7fff && (X) <= 0x8000)
747 #define UPPER16_P(X) (((X) & 0xffff) == 0 \
748 && ((X) >> 16) >= -0x8000 \
749 && ((X) >> 16) <= 0x7fff)
750 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
751 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
752 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
753 #define UINT5_P(X) ((X) >= 0 && (X) < 32)
754 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
756 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
757 ((C) == 'I' ? INT8_P (VALUE) \
758 : (C) == 'J' ? INT16_P (VALUE) \
759 : (C) == 'K' ? UINT16_P (VALUE) \
760 : (C) == 'L' ? UPPER16_P (VALUE) \
761 : (C) == 'M' ? UINT24_P (VALUE) \
762 : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \
763 : (C) == 'O' ? UINT5_P (VALUE) \
764 : (C) == 'P' ? CMP_INT16_P (VALUE) \
767 /* Similar, but for floating constants, and defining letters G and H.
768 Here VALUE is the CONST_DOUBLE rtx itself.
769 For the m32r, handle a few constants inline.
770 ??? We needn't treat DI and DF modes differently, but for now we do. */
771 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
772 ((C) == 'G' ? easy_di_const (VALUE) \
773 : (C) == 'H' ? easy_df_const (VALUE) \
776 /* A C expression that defines the optional machine-dependent constraint
777 letters that can be used to segregate specific types of operands,
778 usually memory references, for the target machine. It should return 1 if
779 VALUE corresponds to the operand type represented by the constraint letter
780 C. If C is not defined as an extra constraint, the value returned should
781 be 0 regardless of VALUE. */
782 /* Q is for symbolic addresses loadable with ld24.
783 R is for symbolic addresses when ld24 can't be used.
784 S is for stores with pre {inc,dec}rement
785 T is for indirect of a pointer.
786 U is for loads with post increment. */
788 #define EXTRA_CONSTRAINT(VALUE, C) \
789 ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
790 || addr24_operand (VALUE, VOIDmode)) \
791 : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
792 || addr32_operand (VALUE, VOIDmode)) \
793 : (C) == 'S' ? (GET_CODE (VALUE) == MEM \
794 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
796 : (C) == 'T' ? (GET_CODE (VALUE) == MEM \
797 && memreg_operand (VALUE, GET_MODE (VALUE))) \
798 : (C) == 'U' ? (GET_CODE (VALUE) == MEM \
799 && LOAD_POSTINC_P (GET_MODE (VALUE), \
803 /* Stack layout and stack pointer usage. */
805 /* Define this macro if pushing a word onto the stack moves the stack
806 pointer to a smaller address. */
807 #define STACK_GROWS_DOWNWARD
809 /* Define this if the nominal address of the stack frame
810 is at the high-address end of the local variables;
811 that is, each additional local variable allocated
812 goes at a more negative offset from the frame pointer. */
813 /*#define FRAME_GROWS_DOWNWARD*/
815 /* Offset from frame pointer to start allocating local variables at.
816 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
817 first local allocated. Otherwise, it is the offset to the BEGINNING
818 of the first local allocated. */
819 /* The frame pointer points at the same place as the stack pointer, except if
820 alloca has been called. */
821 #define STARTING_FRAME_OFFSET \
822 M32R_STACK_ALIGN (current_function_outgoing_args_size)
824 /* Offset from the stack pointer register to the first location at which
825 outgoing arguments are placed. */
826 #define STACK_POINTER_OFFSET 0
828 /* Offset of first parameter from the argument pointer register value. */
829 #define FIRST_PARM_OFFSET(FNDECL) 0
831 /* A C expression whose value is RTL representing the address in a
832 stack frame where the pointer to the caller's frame is stored.
833 Assume that FRAMEADDR is an RTL expression for the address of the
836 If you don't define this macro, the default is to return the value
837 of FRAMEADDR--that is, the stack frame address is also the address
838 of the stack word that points to the previous frame. */
839 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
841 /* A C expression whose value is RTL representing the value of the
842 return address for the frame COUNT steps up from the current frame.
843 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
844 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
846 /* The current return address is in r14. */
847 #if 0 /* The default value should work. */
848 #define RETURN_ADDR_RTX(COUNT, FRAME) \
850 ? gen_rtx_REG (Pmode, 14) \
851 : copy_to_reg (gen_rtx_MEM (Pmode, \
852 memory_address (Pmode, \
853 plus_constant ((FRAME), \
857 /* Register to use for pushing function arguments. */
858 #define STACK_POINTER_REGNUM 15
860 /* Base register for access to local variables of the function. */
861 #define FRAME_POINTER_REGNUM 13
863 /* Base register for access to arguments of the function. */
864 #define ARG_POINTER_REGNUM 16
866 /* The register number of the return address pointer register, which
867 is used to access the current function's return address from the
868 stack. On some machines, the return address is not at a fixed
869 offset from the frame pointer or stack pointer or argument
870 pointer. This register can be defined to point to the return
871 address on the stack, and then be converted by `ELIMINABLE_REGS'
872 into either the frame pointer or stack pointer.
874 Do not define this macro unless there is no other way to get the
875 return address from the stack. */
877 /* #define RETURN_ADDRESS_POINTER_REGNUM */
879 /* Register in which static-chain is passed to a function. This must
880 not be a register used by the prologue. */
881 #define STATIC_CHAIN_REGNUM 7
883 /* These aren't official macros. */
884 #define PROLOGUE_TMP_REGNUM 4
885 #define RETURN_ADDR_REGNUM 14
886 /* #define GP_REGNUM 12 */
887 #define CARRY_REGNUM 17
888 #define ACCUM_REGNUM 18
889 #define M32R_MAX_INT_REGS 16
891 #ifndef SUBTARGET_GPR_P
892 #define SUBTARGET_GPR_P(REGNO) 0
895 #ifndef SUBTARGET_ACCUM_P
896 #define SUBTARGET_ACCUM_P(REGNO) 0
899 #ifndef SUBTARGET_CARRY_P
900 #define SUBTARGET_CARRY_P(REGNO) 0
903 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
904 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
905 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
907 /* Eliminating the frame and arg pointers. */
909 /* A C expression which is nonzero if a function must have and use a
910 frame pointer. This expression is evaluated in the reload pass.
911 If its value is nonzero the function will have a frame pointer. */
912 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
915 /* C statement to store the difference between the frame pointer
916 and the stack pointer values immediately after the function prologue.
917 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
918 need not be defined. */
919 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
920 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
923 /* If defined, this macro specifies a table of register pairs used to
924 eliminate unneeded registers that point into the stack frame. If
925 it is not defined, the only elimination attempted by the compiler
926 is to replace references to the frame pointer with references to
929 Note that the elimination of the argument pointer with the stack
930 pointer is specified first since that is the preferred elimination. */
932 #define ELIMINABLE_REGS \
933 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
934 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
935 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
937 /* A C expression that returns non-zero if the compiler is allowed to
938 try to replace register number FROM-REG with register number
939 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
940 defined, and will usually be the constant 1, since most of the
941 cases preventing register elimination are things that the compiler
942 already knows about. */
944 #define CAN_ELIMINATE(FROM, TO) \
945 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
946 ? ! frame_pointer_needed \
949 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
950 specifies the initial difference between the specified pair of
951 registers. This macro must be defined if `ELIMINABLE_REGS' is
954 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
956 int size = m32r_compute_frame_size (get_frame_size ()); \
958 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
960 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
961 (OFFSET) = size - current_function_pretend_args_size; \
962 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
963 (OFFSET) = size - current_function_pretend_args_size; \
968 /* Function argument passing. */
970 /* When a prototype says `char' or `short', really pass an `int'. */
971 #define PROMOTE_PROTOTYPES 1
973 /* If defined, the maximum amount of space required for outgoing
974 arguments will be computed and placed into the variable
975 `current_function_outgoing_args_size'. No space will be pushed
976 onto the stack for each call; instead, the function prologue should
977 increase the stack frame size by this amount. */
978 #define ACCUMULATE_OUTGOING_ARGS 1
980 /* Define this macro if functions should assume that stack space has
981 been allocated for arguments even when their values are passed in
984 The value of this macro is the size, in bytes, of the area
985 reserved for arguments passed in registers for the function
986 represented by FNDECL.
988 This space can be allocated by the caller, or be a part of the
989 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
992 #define REG_PARM_STACK_SPACE(FNDECL) \
993 (M32R_MAX_PARM_REGS * UNITS_PER_WORD)
996 /* Value is the number of bytes of arguments automatically
997 popped when returning from a subroutine call.
998 FUNDECL is the declaration node of the function (as a tree),
999 FUNTYPE is the data type of the function (as a tree),
1000 or for a library call it is an identifier node for the subroutine name.
1001 SIZE is the number of bytes of arguments passed on the stack. */
1002 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
1004 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1005 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1007 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1008 || TREE_ADDRESSABLE (TYPE)))
1010 /* Define a data type for recording info about an argument list
1011 during the scan of that argument list. This data type should
1012 hold all necessary information about the function itself
1013 and about the args processed so far, enough to enable macros
1014 such as FUNCTION_ARG to determine where the next arg should go. */
1015 #define CUMULATIVE_ARGS int
1017 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1018 for a call to a function whose data type is FNTYPE.
1019 For a library call, FNTYPE is 0. */
1020 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1023 /* The number of registers used for parameter passing. Local to this file. */
1024 #define M32R_MAX_PARM_REGS 4
1026 /* 1 if N is a possible register number for function argument passing. */
1027 #define FUNCTION_ARG_REGNO_P(N) \
1028 ((unsigned) (N) < M32R_MAX_PARM_REGS)
1030 /* The ROUND_ADVANCE* macros are local to this file. */
1031 /* Round SIZE up to a word boundary. */
1032 #define ROUND_ADVANCE(SIZE) \
1033 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1035 /* Round arg MODE/TYPE up to the next word boundary. */
1036 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1037 ((MODE) == BLKmode \
1038 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1039 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
1041 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1042 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1044 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1045 a reg. This includes arguments that have to be passed by reference as the
1046 pointer to them is passed in a reg if one is available (and that is what
1048 This macro is only used in this file. */
1049 #define PASS_IN_REG_P(CUM, MODE, TYPE, NAMED) \
1050 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1052 /* Determine where to put an argument to a function.
1053 Value is zero to push the argument on the stack,
1054 or a hard register in which to store the argument.
1056 MODE is the argument's machine mode.
1057 TYPE is the data type of the argument (as a tree).
1058 This is null for libcalls where that information may
1060 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1061 the preceding args and about the function being called.
1062 NAMED is nonzero if this argument is a named parameter
1063 (otherwise it is an extra parameter matching an ellipsis). */
1064 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1065 and the rest are pushed. */
1066 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1067 (PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED)) \
1068 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1071 /* ??? Quick hack to try to get varargs working the normal way. */
1072 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1073 (((! current_function_varargs || (NAMED)) \
1074 && PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))) \
1075 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1078 /* A C expression for the number of words, at the beginning of an
1079 argument, must be put in registers. The value must be zero for
1080 arguments that are passed entirely in registers or that are entirely
1081 pushed on the stack.
1083 On some machines, certain arguments must be passed partially in
1084 registers and partially in memory. On these machines, typically the
1085 first @var{n} words of arguments are passed in registers, and the rest
1086 on the stack. If a multi-word argument (a @code{double} or a
1087 structure) crosses that boundary, its first few words must be passed
1088 in registers and the rest must be pushed. This macro tells the
1089 compiler when this occurs, and how many of the words should go in
1091 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1092 function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED)
1094 /* A C expression that indicates when an argument must be passed by
1095 reference. If nonzero for an argument, a copy of that argument is
1096 made in memory and a pointer to the argument is passed instead of
1097 the argument itself. The pointer is passed in whatever way is
1098 appropriate for passing a pointer to that type. */
1099 /* All arguments greater than 8 bytes are passed this way. */
1100 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1101 ((TYPE) && int_size_in_bytes (TYPE) > 8)
1103 /* Update the data in CUM to advance over an argument
1104 of mode MODE and data type TYPE.
1105 (TYPE is null for libcalls where that information may not be available.) */
1106 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1107 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
1108 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
1110 /* If defined, a C expression that gives the alignment boundary, in bits,
1111 of an argument with the specified mode and type. If it is not defined,
1112 PARM_BOUNDARY is used for all arguments. */
1114 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
1115 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1116 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
1118 : 2 * PARM_BOUNDARY)
1121 /* This macro offers an alternative
1122 to using `__builtin_saveregs' and defining the macro
1123 `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1124 arguments into the stack so that all the arguments appear to have
1125 been passed consecutively on the stack. Once this is done, you
1126 can use the standard implementation of varargs that works for
1127 machines that pass all their arguments on the stack.
1129 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure,
1130 containing the values that obtain after processing of the named
1131 arguments. The arguments MODE and TYPE describe the last named
1132 argument--its machine mode and its data type as a tree node.
1134 The macro implementation should do two things: first, push onto the
1135 stack all the argument registers *not* used for the named
1136 arguments, and second, store the size of the data thus pushed into
1137 the `int'-valued variable whose name is supplied as the argument
1138 PRETEND_SIZE. The value that you store here will serve as
1139 additional offset for setting up the stack frame.
1141 If the argument NO_RTL is nonzero, it means that the
1142 arguments of the function are being analyzed for the second time.
1143 This happens for an inline function, which is not actually
1144 compiled until the end of the source file. The macro
1145 `SETUP_INCOMING_VARARGS' should not generate any instructions in
1148 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1149 m32r_setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1151 /* Implement `va_arg'. */
1152 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1153 m32r_va_arg (valist, type)
1155 /* Function results. */
1157 /* Define how to find the value returned by a function.
1158 VALTYPE is the data type of the value (as a tree).
1159 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1160 otherwise, FUNC is 0. */
1161 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1163 /* Define how to find the value returned by a library function
1164 assuming the value has mode MODE. */
1165 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1167 /* 1 if N is a possible register number for a function value
1168 as seen by the caller. */
1169 /* ??? What about r1 in DI/DF values. */
1170 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1172 /* A C expression which can inhibit the returning of certain function
1173 values in registers, based on the type of value. A nonzero value says
1174 to return the function value in memory, just as large structures are
1175 always returned. Here TYPE will be a C expression of type `tree',
1176 representing the data type of the value. */
1177 #define RETURN_IN_MEMORY(TYPE) \
1178 (int_size_in_bytes (TYPE) > 8)
1180 /* Tell GCC to use RETURN_IN_MEMORY. */
1181 #define DEFAULT_PCC_STRUCT_RETURN 0
1183 /* Register in which address to store a structure value
1184 is passed to a function, or 0 to use `invisible' first argument. */
1185 #define STRUCT_VALUE 0
1187 /* Function entry and exit. */
1189 /* Initialize data used by insn expanders. This is called from
1190 init_emit, once for each function, before code is generated. */
1191 #define INIT_EXPANDERS m32r_init_expanders ()
1193 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1194 the stack pointer does not matter. The value is tested only in
1195 functions that have frame pointers.
1196 No definition is equivalent to always zero. */
1197 #define EXIT_IGNORE_STACK 1
1199 /* Output assembler code to FILE to increment profiler label # LABELNO
1200 for profiling a function entry. */
1201 #define FUNCTION_PROFILER(FILE, LABELNO) abort ()
1205 /* On the M32R, the trampoline is
1212 ??? Need addr32 support.
1215 /* Length in bytes of the trampoline for entering a nested function. */
1216 #define TRAMPOLINE_SIZE 12
1218 /* Emit RTL insns to initialize the variable parts of a trampoline.
1219 FNADDR is an RTX for the address of the function's pure code.
1220 CXT is an RTX for the static chain value for the function. */
1221 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1223 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1224 plus_constant ((CXT), 0xe7000000)); \
1225 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1226 plus_constant ((FNADDR), 0xe6000000)); \
1227 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1228 GEN_INT (0x1fc67000)); \
1229 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)))); \
1232 /* Library calls. */
1234 /* Generate calls to memcpy, memcmp and memset. */
1235 #define TARGET_MEM_FUNCTIONS
1237 /* Addressing modes, and classification of registers for them. */
1239 /* Maximum number of registers that can appear in a valid memory address. */
1240 #define MAX_REGS_PER_ADDRESS 1
1242 /* We have post-inc load and pre-dec,pre-inc store,
1243 but only for 4 byte vals. */
1244 #define HAVE_PRE_DECREMENT 1
1245 #define HAVE_PRE_INCREMENT 1
1246 #define HAVE_POST_INCREMENT 1
1248 /* Recognize any constant value that is a valid address. */
1249 #define CONSTANT_ADDRESS_P(X) \
1250 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1251 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
1253 /* Nonzero if the constant value X is a legitimate general operand.
1254 We don't allow (plus symbol large-constant) as the relocations can't
1255 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1256 We allow all CONST_DOUBLE's as the md file patterns will force the
1257 constant to memory if they can't handle them. */
1259 #define LEGITIMATE_CONSTANT_P(X) \
1260 (! (GET_CODE (X) == CONST \
1261 && GET_CODE (XEXP (X, 0)) == PLUS \
1262 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1263 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1264 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1266 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1267 and check its validity for a certain class.
1268 We have two alternate definitions for each of them.
1269 The usual definition accepts all pseudo regs; the other rejects
1270 them unless they have been allocated suitable hard regs.
1271 The symbol REG_OK_STRICT causes the latter definition to be used.
1273 Most source files want to accept pseudo regs in the hope that
1274 they will get allocated to the class that the insn wants them to be in.
1275 Source files for reload pass need to be strict.
1276 After reload, it makes no difference, since pseudo regs have
1277 been eliminated by then. */
1279 #ifdef REG_OK_STRICT
1281 /* Nonzero if X is a hard reg that can be used as a base reg. */
1282 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1283 /* Nonzero if X is a hard reg that can be used as an index. */
1284 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1288 /* Nonzero if X is a hard reg that can be used as a base reg
1289 or if it is a pseudo reg. */
1290 #define REG_OK_FOR_BASE_P(X) \
1291 (GPR_P (REGNO (X)) \
1292 || (REGNO (X)) == ARG_POINTER_REGNUM \
1293 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1294 /* Nonzero if X is a hard reg that can be used as an index
1295 or if it is a pseudo reg. */
1296 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1300 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1301 that is a valid memory address for an instruction.
1302 The MODE argument is the machine mode for the MEM expression
1303 that wants to use this address. */
1305 /* Local to this file. */
1306 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1308 /* Local to this file. */
1309 #define RTX_OK_FOR_OFFSET_P(X) \
1310 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1312 /* Local to this file. */
1313 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1314 (GET_CODE (X) == PLUS \
1315 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1316 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1318 /* Local to this file. */
1319 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1320 since more than one instruction will be required. */
1321 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1322 (GET_CODE (X) == LO_SUM \
1323 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
1324 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1325 && CONSTANT_P (XEXP (X, 1)))
1327 /* Local to this file. */
1328 /* Is this a load and increment operation. */
1329 #define LOAD_POSTINC_P(MODE, X) \
1330 (((MODE) == SImode || (MODE) == SFmode) \
1331 && GET_CODE (X) == POST_INC \
1332 && GET_CODE (XEXP (X, 0)) == REG \
1333 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1335 /* Local to this file. */
1336 /* Is this a increment/decrement and store operation. */
1337 #define STORE_PREINC_PREDEC_P(MODE, X) \
1338 (((MODE) == SImode || (MODE) == SFmode) \
1339 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1340 && GET_CODE (XEXP (X, 0)) == REG \
1341 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1343 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1344 { if (RTX_OK_FOR_BASE_P (X)) \
1346 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1348 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1350 if (LOAD_POSTINC_P ((MODE), (X))) \
1352 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1356 /* Try machine-dependent ways of modifying an illegitimate address
1357 to be legitimate. If we find one, return the new, valid address.
1358 This macro is used in only one place: `memory_address' in explow.c.
1360 OLDX is the address as it was before break_out_memory_refs was called.
1361 In some cases it is useful to look at this to decide what needs to be done.
1363 MODE and WIN are passed so that this macro can use
1364 GO_IF_LEGITIMATE_ADDRESS.
1366 It is always safe for this macro to do nothing. It exists to recognize
1367 opportunities to optimize the output.
1369 ??? Is there anything useful we can do here for the M32R? */
1371 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1373 /* Go to LABEL if ADDR (a legitimate address expression)
1374 has an effect that depends on the machine mode it is used for. */
1375 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1377 if (GET_CODE (ADDR) == PRE_DEC \
1378 || GET_CODE (ADDR) == PRE_INC \
1379 || GET_CODE (ADDR) == POST_INC \
1380 || GET_CODE (ADDR) == LO_SUM) \
1384 /* Condition code usage. */
1386 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1387 return the mode to be used for the comparison. */
1388 #define SELECT_CC_MODE(OP, X, Y) \
1389 ((enum machine_mode)m32r_select_cc_mode ((int)OP, X, Y))
1391 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
1392 floating point inequality comparison. */
1393 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1397 /* ??? I'm quite sure I don't understand enough of the subtleties involved
1398 in choosing the right numbers to use here, but there doesn't seem to be
1399 enough documentation on this. What I've done is define an insn to cost
1400 4 "units" and work from there. COSTS_N_INSNS (N) is defined as (N) * 4 - 2
1401 so that seems reasonable. Some values are supposed to be defined relative
1402 to each other and thus aren't necessarily related to COSTS_N_INSNS. */
1404 /* Compute the cost of computing a constant rtl expression RTX
1405 whose rtx-code is CODE. The body of this macro is a portion
1406 of a switch statement. If the code is computed here,
1407 return it with a return statement. Otherwise, break from the switch. */
1408 /* Small integers are as cheap as registers. 4 byte values can be fetched
1409 as immediate constants - let's give that the cost of an extra insn. */
1410 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1412 if (INT16_P (INTVAL (X))) \
1414 /* fall through */ \
1419 case CONST_DOUBLE : \
1422 split_double (X, &high, &low); \
1423 return 4 * (!INT16_P (INTVAL (high)) \
1424 + !INT16_P (INTVAL (low))); \
1427 /* Compute the cost of an address. */
1428 #define ADDRESS_COST(ADDR) m32r_address_cost (ADDR)
1430 /* Compute extra cost of moving data between one register class
1432 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1434 /* Compute the cost of moving data between registers and memory. */
1435 /* Memory is 3 times as expensive as registers.
1436 ??? Is that the right way to look at it? */
1437 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1438 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1440 /* The cost of a branch insn. */
1441 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1442 while (a < N && a). Branches aren't that expensive on the M32R so
1443 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1444 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1446 /* Provide the costs of a rtl expression. This is in the body of a
1447 switch on CODE. The purpose for the cost of MULT is to encourage
1448 `synth_mult' to find a synthetic multiply when reasonable.
1450 If we need more than 12 insns to do a multiply, then go out-of-line,
1451 since the call overhead will be < 10% of the cost of the multiply. */
1452 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1454 return COSTS_N_INSNS (3); \
1459 return COSTS_N_INSNS (10);
1461 /* Nonzero if access to memory by bytes is slow and undesirable.
1462 For RISC chips, it means that access to memory by bytes is no
1463 better than access by words when possible, so grab a whole word
1464 and maybe make use of that. */
1465 #define SLOW_BYTE_ACCESS 1
1467 /* Define this macro if it is as good or better to call a constant
1468 function address than to call an address kept in a register. */
1469 #define NO_FUNCTION_CSE
1471 /* Define this macro if it is as good or better for a function to call
1472 itself with an explicit address than to call an address kept in a
1474 #define NO_RECURSIVE_FUNCTION_CSE
1476 /* A C statement (sans semicolon) to update the integer variable COST based on
1477 the relationship between INSN that is dependent on DEP_INSN through the
1478 dependence LINK. The default is to make no adjustment to COST. This can be
1479 used for example to specify to the scheduler that an output- or
1480 anti-dependence does not incur the same cost as a data-dependence. */
1482 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
1483 (COST) = m32r_adjust_cost (INSN, LINK, DEP_INSN, COST)
1485 /* A C statement (sans semicolon) to update the integer scheduling
1486 priority `INSN_PRIORITY(INSN)'. Reduce the priority to execute
1487 the INSN earlier, increase the priority to execute INSN later.
1488 Do not define this macro if you do not need to adjust the
1489 scheduling priorities of insns. */
1490 #define ADJUST_PRIORITY(INSN) \
1491 INSN_PRIORITY (INSN) = m32r_adjust_priority (INSN, INSN_PRIORITY (INSN))
1493 /* Macro to determine whether the Haifa scheduler is used. */
1500 /* Indicate how many instructions can be issued at the same time.
1501 This is sort of a lie. The m32r can issue only 1 long insn at
1502 once, but it can issue 2 short insns. The default therefore is
1503 set at 2, but this can be overridden by the command line option
1505 #define ISSUE_RATE ((TARGET_ISSUE_RATE) ? 1 : 2)
1507 /* If we have a machine that can issue a variable # of instructions
1508 per cycle, indicate how many more instructions can be issued
1509 after the current one. */
1510 #define MD_SCHED_VARIABLE_ISSUE(STREAM, VERBOSE, INSN, HOW_MANY) \
1511 (HOW_MANY) = m32r_sched_variable_issue (STREAM, VERBOSE, INSN, HOW_MANY)
1513 /* Whether we are on an odd word boundary while scheduling. */
1514 extern int m32r_sched_odd_word_p;
1516 /* Hook to run before scheduling a block of insns. */
1517 #define MD_SCHED_INIT(STREAM, VERBOSE, MAX_READY) \
1518 m32r_sched_init (STREAM, VERBOSE)
1520 /* Hook to reorder the list of ready instructions. */
1521 #define MD_SCHED_REORDER(STREAM, VERBOSE, READY, N_READY, CLOCK, CIM) \
1524 m32r_sched_reorder (STREAM, VERBOSE, READY, N_READY); \
1529 /* When the `length' insn attribute is used, this macro specifies the
1530 value to be assigned to the address of the first insn in a
1531 function. If not specified, 0 is used. */
1532 #define FIRST_INSN_ADDRESS m32r_first_insn_address ()
1535 /* Section selection. */
1537 #define TEXT_SECTION_ASM_OP "\t.section .text"
1538 #define DATA_SECTION_ASM_OP "\t.section .data"
1539 #define RODATA_SECTION_ASM_OP "\t.section .rodata"
1540 #define BSS_SECTION_ASM_OP "\t.section .bss"
1541 #define SDATA_SECTION_ASM_OP "\t.section .sdata"
1542 #define SBSS_SECTION_ASM_OP "\t.section .sbss"
1543 /* This one is for svr4.h. */
1544 #undef CONST_SECTION_ASM_OP
1545 #define CONST_SECTION_ASM_OP "\t.section .rodata"
1547 /* A list of names for sections other than the standard two, which are
1548 `in_text' and `in_data'. You need not define this macro
1549 on a system with no other sections (that GCC needs to use). */
1550 #undef EXTRA_SECTIONS
1551 #define EXTRA_SECTIONS in_sdata, in_sbss, in_const
1553 /* One or more functions to be defined in "varasm.c". These
1554 functions should do jobs analogous to those of `text_section' and
1555 `data_section', for your additional sections. Do not define this
1556 macro if you do not define `EXTRA_SECTIONS'. */
1557 #undef EXTRA_SECTION_FUNCTIONS
1558 #define EXTRA_SECTION_FUNCTIONS \
1559 CONST_SECTION_FUNCTION \
1560 SDATA_SECTION_FUNCTION \
1561 SBSS_SECTION_FUNCTION
1563 #define SDATA_SECTION_FUNCTION \
1567 if (in_section != in_sdata) \
1569 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
1570 in_section = in_sdata; \
1574 #define SBSS_SECTION_FUNCTION \
1578 if (in_section != in_sbss) \
1580 fprintf (asm_out_file, "%s\n", SBSS_SECTION_ASM_OP); \
1581 in_section = in_sbss; \
1585 /* A C statement or statements to switch to the appropriate section for
1586 output of EXP. You can assume that EXP is either a `VAR_DECL' node
1587 or a constant of some sort. RELOC indicates whether the initial value
1588 of EXP requires link-time relocations. */
1589 #undef SELECT_SECTION
1590 #define SELECT_SECTION(EXP, RELOC) m32r_select_section ((EXP), (RELOC))
1592 /* A C statement or statements to switch to the appropriate section for
1593 output of RTX in mode MODE. You can assume that RTX
1594 is some kind of constant in RTL. The argument MODE is redundant
1595 except in the case of a `const_int' rtx. Select the section by
1596 calling `text_section' or one of the alternatives for other
1599 Do not define this macro if you put all constants in the read-only
1602 #undef SELECT_RTX_SECTION
1604 /* Define this macro if jump tables (for tablejump insns) should be
1605 output in the text section, along with the assembler instructions.
1606 Otherwise, the readonly data section is used.
1607 This macro is irrelevant if there is no separate readonly data section. */
1608 /*#define JUMP_TABLES_IN_TEXT_SECTION*/
1610 /* Define this macro if references to a symbol must be treated
1611 differently depending on something about the variable or
1612 function named by the symbol (such as what section it is in).
1614 The macro definition, if any, is executed immediately after the
1615 rtl for DECL or other node is created.
1616 The value of the rtl will be a `mem' whose address is a
1619 The usual thing for this macro to do is to store a flag in the
1620 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1621 name string in the `symbol_ref' (if one bit is not enough
1624 #define SDATA_FLAG_CHAR '@'
1625 /* Small objects are recorded with no prefix for space efficiency since
1626 they'll be the most common. This isn't the case if the user passes
1627 -mmodel={medium|large} and one could choose to not mark symbols that
1628 are the default, but that complicates things. */
1629 /*#define SMALL_FLAG_CHAR '#'*/
1630 #define MEDIUM_FLAG_CHAR '%'
1631 #define LARGE_FLAG_CHAR '&'
1633 #define SDATA_NAME_P(NAME) (*(NAME) == SDATA_FLAG_CHAR)
1634 /*#define SMALL_NAME_P(NAME) (*(NAME) == SMALL_FLAG_CHAR)*/
1635 #define SMALL_NAME_P(NAME) (! ENCODED_NAME_P (NAME) && ! LIT_NAME_P (NAME))
1636 #define MEDIUM_NAME_P(NAME) (*(NAME) == MEDIUM_FLAG_CHAR)
1637 #define LARGE_NAME_P(NAME) (*(NAME) == LARGE_FLAG_CHAR)
1638 /* For string literals, etc. */
1639 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
1641 #define ENCODED_NAME_P(SYMBOL_NAME) \
1642 (SDATA_NAME_P (SYMBOL_NAME) \
1643 /*|| SMALL_NAME_P (SYMBOL_NAME)*/ \
1644 || MEDIUM_NAME_P (SYMBOL_NAME) \
1645 || LARGE_NAME_P (SYMBOL_NAME))
1647 #define ENCODE_SECTION_INFO(DECL) m32r_encode_section_info (DECL)
1649 /* Decode SYM_NAME and store the real name part in VAR, sans
1650 the characters that encode section info. Define this macro if
1651 ENCODE_SECTION_INFO alters the symbol's name string. */
1652 /* Note that we have to handle symbols like "%*start". */
1653 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1655 (VAR) = (SYMBOL_NAME) + ENCODED_NAME_P (SYMBOL_NAME); \
1656 (VAR) += *(VAR) == '*'; \
1661 /* The register number of the register used to address a table of static
1662 data addresses in memory. In some cases this register is defined by a
1663 processor's ``application binary interface'' (ABI). When this macro
1664 is defined, RTL is generated for this register once, as with the stack
1665 pointer and frame pointer registers. If this macro is not defined, it
1666 is up to the machine-dependent files to allocate such a register (if
1668 /*#define PIC_OFFSET_TABLE_REGNUM 12*/
1670 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1671 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1673 /* This register is call-saved on the M32R. */
1674 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1676 /* By generating position-independent code, when two different programs (A
1677 and B) share a common library (libC.a), the text of the library can be
1678 shared whether or not the library is linked at the same address for both
1679 programs. In some of these environments, position-independent code
1680 requires not only the use of different addressing modes, but also
1681 special code to enable the use of these addressing modes.
1683 The FINALIZE_PIC macro serves as a hook to emit these special
1684 codes once the function is being compiled into assembly code, but not
1685 before. (It is not done before, because in the case of compiling an
1686 inline function, it would lead to multiple PIC prologues being
1687 included in functions which used inline functions and were compiled to
1688 assembly language.) */
1690 /*#define FINALIZE_PIC m32r_finalize_pic ()*/
1692 /* A C expression that is nonzero if X is a legitimate immediate
1693 operand on the target machine when generating position independent code.
1694 You can assume that X satisfies CONSTANT_P, so you need not
1695 check this. You can also assume `flag_pic' is true, so you need not
1696 check it either. You need not define this macro if all constants
1697 (including SYMBOL_REF) can be immediate operands when generating
1698 position independent code. */
1699 /*#define LEGITIMATE_PIC_OPERAND_P(X)*/
1701 /* Control the assembler format that we output. */
1703 /* Output at beginning of assembler file. */
1704 #define ASM_FILE_START(FILE) m32r_asm_file_start (FILE)
1706 /* A C string constant describing how to begin a comment in the target
1707 assembler language. The compiler assumes that the comment will
1708 end at the end of the line. */
1709 #define ASM_COMMENT_START ";"
1711 /* Output to assembler file text saying following lines
1712 may contain character constants, extra white space, comments, etc. */
1713 #define ASM_APP_ON ""
1715 /* Output to assembler file text saying following lines
1716 no longer contain unusual constructs. */
1717 #define ASM_APP_OFF ""
1719 /* This is how to output an assembler line defining a `char' constant. */
1720 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
1723 fprintf (FILE, "\t.byte\t"); \
1724 output_addr_const (FILE, (VALUE)); \
1725 fprintf (FILE, "\n"); \
1729 /* This is how to output an assembler line defining a `short' constant. */
1730 #define ASM_OUTPUT_SHORT(FILE, VALUE) \
1733 fprintf (FILE, "\t.hword\t"); \
1734 output_addr_const (FILE, (VALUE)); \
1735 fprintf (FILE, "\n"); \
1739 /* This is how to output an assembler line defining an `int' constant.
1740 We also handle symbol output here. */
1741 #define ASM_OUTPUT_INT(FILE, VALUE) \
1744 fprintf (FILE, "\t.word\t"); \
1745 output_addr_const (FILE, (VALUE)); \
1746 fprintf (FILE, "\n"); \
1750 /* This is how to output an assembler line defining a `float' constant. */
1751 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
1756 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1757 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1758 fprintf (FILE, "\t.word\t0x%lx %s %s\n", \
1759 t, ASM_COMMENT_START, str); \
1763 /* This is how to output an assembler line defining a `double' constant. */
1764 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
1769 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1770 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1771 fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \
1772 t[0], ASM_COMMENT_START, str, t[1]); \
1776 /* This is how to output an assembler line for a numeric constant byte. */
1777 #define ASM_OUTPUT_BYTE(FILE, VALUE) \
1778 fprintf (FILE, "%s0x%x\n", ASM_BYTE_OP, (VALUE))
1780 /* This is how to output the definition of a user-level label named NAME,
1781 such as the label on a static function or variable NAME. */
1782 /* On the M32R we need to ensure the next instruction starts on a 32 bit
1783 boundary [the previous insn must either be 2 16 bit insns or 1 32 bit]. */
1784 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1787 assemble_name (FILE, NAME); \
1788 fputs (":\n", FILE); \
1792 /* This is how to output a command to make the user-level label named NAME
1793 defined for reference from other files. */
1794 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
1797 fputs ("\t.global\t", FILE); \
1798 assemble_name (FILE, NAME); \
1799 fputs ("\n", FILE); \
1803 /* This is how to output a reference to a user-level label named NAME.
1804 `assemble_name' uses this. */
1805 #undef ASM_OUTPUT_LABELREF
1806 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1809 const char * real_name; \
1810 STRIP_NAME_ENCODING (real_name, (NAME)); \
1811 asm_fprintf (FILE, "%U%s", real_name); \
1815 /* If -Os, don't force line number labels to begin at the beginning of
1816 the word; we still want the assembler to try to put things in parallel,
1817 should that be possible.
1818 For m32r/d, instructions are never in parallel (other than with a nop)
1819 and the simulator and stub both handle a breakpoint in the middle of
1820 a word so don't ever force line number labels to begin at the beginning
1823 #undef ASM_OUTPUT_SOURCE_LINE
1824 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1827 static int sym_lineno = 1; \
1828 fprintf (file, ".stabn 68,0,%d,.LM%d-", \
1829 line, sym_lineno); \
1831 (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
1832 fprintf (file, (optimize_size || TARGET_M32R) \
1833 ? "\n\t.debugsym .LM%d\n" \
1840 /* Store in OUTPUT a string (made with alloca) containing
1841 an assembler-name for a local static variable named NAME.
1842 LABELNO is an integer which is different for each call. */
1843 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1846 (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10);\
1847 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)); \
1851 /* How to refer to registers in assembler output.
1852 This sequence is indexed by compiler's hard-register-number (see above). */
1853 #ifndef SUBTARGET_REGISTER_NAMES
1854 #define SUBTARGET_REGISTER_NAMES
1857 #define REGISTER_NAMES \
1859 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1860 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1861 "ap", "cbit", "a0" \
1862 SUBTARGET_REGISTER_NAMES \
1865 /* If defined, a C initializer for an array of structures containing
1866 a name and a register number. This macro defines additional names
1867 for hard registers, thus allowing the `asm' option in declarations
1868 to refer to registers using alternate names. */
1869 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1870 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1873 #define ADDITIONAL_REGISTER_NAMES \
1875 /*{ "gp", GP_REGNUM },*/ \
1876 { "r13", FRAME_POINTER_REGNUM }, \
1877 { "r14", RETURN_ADDR_REGNUM }, \
1878 { "r15", STACK_POINTER_REGNUM }, \
1879 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1882 /* A C expression which evaluates to true if CODE is a valid
1883 punctuation character for use in the `PRINT_OPERAND' macro. */
1884 extern char m32r_punct_chars[];
1885 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1886 m32r_punct_chars[(unsigned char) (CHAR)]
1888 /* Print operand X (an rtx) in assembler syntax to file FILE.
1889 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1890 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1891 #define PRINT_OPERAND(FILE, X, CODE) \
1892 m32r_print_operand (FILE, X, CODE)
1894 /* A C compound statement to output to stdio stream STREAM the
1895 assembler syntax for an instruction operand that is a memory
1896 reference whose address is ADDR. ADDR is an RTL expression.
1898 On some machines, the syntax for a symbolic address depends on
1899 the section that the address refers to. On these machines,
1900 define the macro `ENCODE_SECTION_INFO' to store the information
1901 into the `symbol_ref', and then check for it here. */
1902 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1903 m32r_print_operand_address (FILE, ADDR)
1905 /* If defined, C string expressions to be used for the `%R', `%L',
1906 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1907 are useful when a single `md' file must support multiple assembler
1908 formats. In that case, the various `tm.h' files can define these
1909 macros differently. */
1910 #define REGISTER_PREFIX ""
1911 #define LOCAL_LABEL_PREFIX ".L"
1912 #define USER_LABEL_PREFIX ""
1913 #define IMMEDIATE_PREFIX "#"
1915 /* This is how to output an element of a case-vector that is absolute. */
1916 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1920 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1921 fprintf (FILE, "\t.word\t"); \
1922 assemble_name (FILE, label); \
1923 fprintf (FILE, "\n"); \
1927 /* This is how to output an element of a case-vector that is relative. */
1928 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1932 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1933 fprintf (FILE, "\t.word\t"); \
1934 assemble_name (FILE, label); \
1935 fprintf (FILE, "-"); \
1936 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1937 assemble_name (FILE, label); \
1938 fprintf (FILE, ")\n"); \
1942 /* The desired alignment for the location counter at the beginning
1944 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1945 if -malign-loops. */
1946 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1948 /* Define this to be the maximum number of insns to move around when moving
1949 a loop test from the top of a loop to the bottom
1950 and seeing whether to duplicate it. The default is thirty.
1952 Loop unrolling currently doesn't like this optimization, so
1953 disable doing if we are unrolling loops and saving space. */
1954 #define LOOP_TEST_THRESHOLD (optimize_size \
1955 && !flag_unroll_loops \
1956 && !flag_unroll_all_loops ? 2 : 30)
1958 /* This is how to output an assembler line
1959 that says to advance the location counter
1960 to a multiple of 2**LOG bytes. */
1961 /* .balign is used to avoid confusion. */
1962 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1966 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1970 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1971 separate, explicit argument. If you define this macro, it is used in
1972 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1973 handling the required alignment of the variable. The alignment is
1974 specified as the number of bits. */
1976 #define SCOMMON_ASM_OP "\t.scomm\t"
1978 #undef ASM_OUTPUT_ALIGNED_COMMON
1979 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1982 if (! TARGET_SDATA_NONE \
1983 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1984 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1986 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1987 assemble_name ((FILE), (NAME)); \
1988 fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \
1992 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1993 separate, explicit argument. If you define this macro, it is used in
1994 place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1995 handling the required alignment of the variable. The alignment is
1996 specified as the number of bits.
1998 For the M32R we need sbss support. */
2000 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2003 ASM_GLOBALIZE_LABEL (FILE, NAME); \
2004 ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN); \
2008 /* Debugging information. */
2010 /* Generate DBX and DWARF debugging information. */
2011 #undef DBX_DEBUGGING_INFO
2012 #undef DWARF_DEBUGGING_INFO
2013 #undef DWARF2_DEBUGGING_INFO
2015 #define DBX_DEBUGGING_INFO
2016 #define DWARF_DEBUGGING_INFO
2017 #define DWARF2_DEBUGGING_INFO
2019 /* Prefer STABS (for now). */
2020 #undef PREFERRED_DEBUGGING_TYPE
2021 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
2023 /* How to renumber registers for dbx and gdb. */
2024 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2026 /* Turn off splitting of long stabs. */
2027 #define DBX_CONTIN_LENGTH 0
2029 /* Miscellaneous. */
2031 /* Specify the machine mode that this machine uses
2032 for the index in the tablejump instruction. */
2033 #define CASE_VECTOR_MODE Pmode
2035 /* Define as C expression which evaluates to nonzero if the tablejump
2036 instruction expects the table to contain offsets from the address of the
2038 Do not define this if the table should contain absolute addresses. */
2039 /* It's not clear what PIC will look like or whether we want to use -fpic
2040 for the embedded form currently being talked about. For now require -fpic
2041 to get pc relative switch tables. */
2042 /*#define CASE_VECTOR_PC_RELATIVE 1 */
2044 /* Define if operations between registers always perform the operation
2045 on the full register even if a narrower mode is specified. */
2046 #define WORD_REGISTER_OPERATIONS
2048 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2049 will either zero-extend or sign-extend. The value of this macro should
2050 be the code that says which one of the two operations is implicitly
2051 done, NIL if none. */
2052 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2054 /* Specify the tree operation to be used to convert reals to integers. */
2055 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2057 /* This is the kind of divide that is easiest to do in the general case. */
2058 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2060 /* Max number of bytes we can move from memory to memory
2061 in one reasonably fast instruction. */
2064 /* Define this to be nonzero if shift instructions ignore all but the low-order
2066 #define SHIFT_COUNT_TRUNCATED 1
2068 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2069 is done just by pretending it is already truncated. */
2070 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2072 /* We assume that the store-condition-codes instructions store 0 for false
2073 and some other value for true. This is the value stored for true. */
2074 #define STORE_FLAG_VALUE 1
2076 /* Specify the machine mode that pointers have.
2077 After generation of rtl, the compiler makes no further distinction
2078 between pointers and any other objects of this machine mode. */
2079 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
2080 it's own problems (you have to add extendpsisi2 and truncsipsi2).
2082 #define Pmode SImode
2084 /* A function address in a call instruction. */
2085 #define FUNCTION_MODE SImode
2087 /* Define the information needed to generate branch and scc insns. This is
2088 stored from the compare operation. Note that we can't use "rtx" here
2089 since it hasn't been defined! */
2090 extern struct rtx_def * m32r_compare_op0;
2091 extern struct rtx_def * m32r_compare_op1;
2093 /* M32R function types. */
2094 enum m32r_function_type
2096 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
2099 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
2101 /* Define this if you have defined special-purpose predicates in the
2102 file `MACHINE.c'. This macro is called within an initializer of an
2103 array of structures. The first field in the structure is the name
2104 of a predicate and the second field is an array of rtl codes. For
2105 each predicate, list all rtl codes that can be in expressions
2106 matched by the predicate. The list should have a trailing comma. */
2108 #define PREDICATE_CODES \
2109 { "conditional_move_operand", { REG, SUBREG, CONST_INT }}, \
2110 { "carry_compare_operand", { EQ, NE }}, \
2111 { "eqne_comparison_operator", { EQ, NE }}, \
2112 { "signed_comparison_operator", { EQ, NE, LT, LE, GT, GE }}, \
2113 { "move_dest_operand", { REG, SUBREG, MEM }}, \
2114 { "move_src_operand", { REG, SUBREG, MEM, CONST_INT, \
2115 CONST_DOUBLE, LABEL_REF, CONST, \
2117 { "move_double_src_operand", { REG, SUBREG, MEM, CONST_INT, \
2119 { "two_insn_const_operand", { CONST_INT }}, \
2120 { "symbolic_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2121 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2122 { "int8_operand", { CONST_INT }}, \
2123 { "uint16_operand", { CONST_INT }}, \
2124 { "reg_or_int16_operand", { REG, SUBREG, CONST_INT }}, \
2125 { "reg_or_uint16_operand", { REG, SUBREG, CONST_INT }}, \
2126 { "reg_or_cmp_int16_operand", { REG, SUBREG, CONST_INT }}, \
2127 { "reg_or_eq_int16_operand", { REG, SUBREG, CONST_INT }}, \
2128 { "cmp_int16_operand", { CONST_INT }}, \
2129 { "call_address_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2130 { "extend_operand", { REG, SUBREG, MEM }}, \
2131 { "small_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
2132 { "m32r_block_immediate_operand",{ CONST_INT }}, \
2133 { "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
2134 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }},
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