1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
28 #undef WCHAR_TYPE_SIZE
40 /* M32R/X overrides. */
41 /* Print subsidiary information on the compiler version in use. */
42 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
44 /* Additional flags for the preprocessor. */
45 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
46 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
47 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
50 /* Assembler switches. */
51 #define ASM_CPU_SPEC \
52 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
54 /* Use m32rx specific crt0/crtinit/crtfini files. */
55 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
56 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
58 /* Define this macro as a C expression for the initializer of an array of
59 strings to tell the driver program which options are defaults for this
60 target and thus do not need to be handled specially when using
61 `MULTILIB_OPTIONS'. */
62 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
64 /* Number of additional registers the subtarget defines. */
65 #define SUBTARGET_NUM_REGISTERS 1
67 /* 1 for registers that cannot be allocated. */
68 #define SUBTARGET_FIXED_REGISTERS , 1
70 /* 1 for registers that are not available across function calls. */
71 #define SUBTARGET_CALL_USED_REGISTERS , 1
73 /* Order to allocate model specific registers. */
74 #define SUBTARGET_REG_ALLOC_ORDER , 19
76 /* Registers which are accumulators. */
77 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
79 /* All registers added. */
80 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
82 /* Additional accumulator registers. */
83 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
85 /* Define additional register names. */
86 #define SUBTARGET_REGISTER_NAMES , "a1"
87 /* end M32R/X overrides. */
89 /* Print subsidiary information on the compiler version in use. */
90 #ifndef TARGET_VERSION
91 #define TARGET_VERSION fprintf (stderr, " (m32r)")
94 /* Names to predefine in the preprocessor for this target machine. */
95 /* __M32R__ is defined by the existing compiler so we use that. */
96 #define TARGET_CPU_CPP_BUILTINS() \
99 builtin_define ("__M32R__"); \
100 builtin_define ("__m32r__"); \
101 builtin_assert ("cpu=m32r"); \
102 builtin_assert ("machine=m32r"); \
103 builtin_define (TARGET_BIG_ENDIAN \
104 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
108 /* This macro defines names of additional specifications to put in the specs
109 that can be used in various specifications like CC1_SPEC. Its definition
110 is an initializer with a subgrouping for each command option.
112 Each subgrouping contains a string constant, that defines the
113 specification name, and a string constant that used by the GCC driver
116 Do not define this macro if it does not need to do anything. */
118 #ifndef SUBTARGET_EXTRA_SPECS
119 #define SUBTARGET_EXTRA_SPECS
123 #define ASM_CPU_SPEC ""
127 #define CPP_CPU_SPEC ""
131 #define CC1_CPU_SPEC ""
134 #ifndef LINK_CPU_SPEC
135 #define LINK_CPU_SPEC ""
138 #ifndef STARTFILE_CPU_SPEC
139 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
142 #ifndef ENDFILE_CPU_SPEC
143 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
147 #if 0 /* Not supported yet. */
148 #define RELAX_SPEC "%{mrelax:-relax}"
150 #define RELAX_SPEC ""
154 #define EXTRA_SPECS \
155 { "asm_cpu", ASM_CPU_SPEC }, \
156 { "cpp_cpu", CPP_CPU_SPEC }, \
157 { "cc1_cpu", CC1_CPU_SPEC }, \
158 { "link_cpu", LINK_CPU_SPEC }, \
159 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
160 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
161 { "relax", RELAX_SPEC }, \
162 SUBTARGET_EXTRA_SPECS
164 #define CPP_SPEC "%(cpp_cpu)"
167 #define CC1_SPEC "%{G*} %(cc1_cpu)"
169 /* Options to pass on to the assembler. */
171 #define ASM_SPEC "%(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}"
173 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
175 #undef STARTFILE_SPEC
176 #define STARTFILE_SPEC "%(startfile_cpu)"
179 #define ENDFILE_SPEC "%(endfile_cpu)"
183 /* Run-time compilation parameters selecting different hardware subsets. */
185 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
187 #ifndef TARGET_LITTLE_ENDIAN
188 #define TARGET_LITTLE_ENDIAN 0
190 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
192 /* This defaults us to m32r. */
193 #ifndef TARGET_CPU_DEFAULT
194 #define TARGET_CPU_DEFAULT 0
198 #include "config/m32r/m32r-opts.h"
201 /* Define this macro as a C expression for the initializer of an array of
202 strings to tell the driver program which options are defaults for this
203 target and thus do not need to be handled specially when using
204 `MULTILIB_OPTIONS'. */
205 #ifndef SUBTARGET_MULTILIB_DEFAULTS
206 #define SUBTARGET_MULTILIB_DEFAULTS
209 #ifndef MULTILIB_DEFAULTS
210 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
213 #ifndef SUBTARGET_OVERRIDE_OPTIONS
214 #define SUBTARGET_OVERRIDE_OPTIONS
217 /* Target machine storage layout. */
219 /* Define this if most significant bit is lowest numbered
220 in instructions that operate on numbered bit-fields. */
221 #define BITS_BIG_ENDIAN 1
223 /* Define this if most significant byte of a word is the lowest numbered. */
224 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
226 /* Define this if most significant word of a multiword number is the lowest
228 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
230 /* Width of a word, in units (bytes). */
231 #define UNITS_PER_WORD 4
233 /* Define this macro if it is advisable to hold scalars in registers
234 in a wider mode than that declared by the program. In such cases,
235 the value is constrained to be within the bounds of the declared
236 type, but kept valid in the wider mode. The signedness of the
237 extension may differ from that of the type. */
238 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
239 if (GET_MODE_CLASS (MODE) == MODE_INT \
240 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
245 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
246 #define PARM_BOUNDARY 32
248 /* Boundary (in *bits*) on which stack pointer should be aligned. */
249 #define STACK_BOUNDARY 32
251 /* ALIGN FRAMES on word boundaries */
252 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
254 /* Allocation boundary (in *bits*) for the code of a function. */
255 #define FUNCTION_BOUNDARY 32
257 /* Alignment of field after `int : 0' in a structure. */
258 #define EMPTY_FIELD_BOUNDARY 32
260 /* Every structure's size must be a multiple of this. */
261 #define STRUCTURE_SIZE_BOUNDARY 8
263 /* A bit-field declared as `int' forces `int' alignment for the struct. */
264 #define PCC_BITFIELD_TYPE_MATTERS 1
266 /* No data type wants to be aligned rounder than this. */
267 #define BIGGEST_ALIGNMENT 32
269 /* The best alignment to use in cases where we have a choice. */
270 #define FASTEST_ALIGNMENT 32
272 /* Make strings word-aligned so strcpy from constants will be faster. */
273 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
274 ((TREE_CODE (EXP) == STRING_CST \
275 && (ALIGN) < FASTEST_ALIGNMENT) \
276 ? FASTEST_ALIGNMENT : (ALIGN))
278 /* Make arrays of chars word-aligned for the same reasons. */
279 #define DATA_ALIGNMENT(TYPE, ALIGN) \
280 (TREE_CODE (TYPE) == ARRAY_TYPE \
281 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
282 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
284 /* Set this nonzero if move instructions will actually fail to work
285 when given unaligned data. */
286 #define STRICT_ALIGNMENT 1
288 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
289 #define LABEL_ALIGN(insn) 2
291 /* Layout of source language data types. */
293 #define SHORT_TYPE_SIZE 16
294 #define INT_TYPE_SIZE 32
295 #define LONG_TYPE_SIZE 32
296 #define LONG_LONG_TYPE_SIZE 64
297 #define FLOAT_TYPE_SIZE 32
298 #define DOUBLE_TYPE_SIZE 64
299 #define LONG_DOUBLE_TYPE_SIZE 64
301 /* Define this as 1 if `char' should by default be signed; else as 0. */
302 #define DEFAULT_SIGNED_CHAR 1
304 #define SIZE_TYPE "long unsigned int"
305 #define PTRDIFF_TYPE "long int"
306 #define WCHAR_TYPE "short unsigned int"
307 #define WCHAR_TYPE_SIZE 16
309 /* Standard register usage. */
311 /* Number of actual hardware registers.
312 The hardware registers are assigned numbers for the compiler
313 from 0 to just below FIRST_PSEUDO_REGISTER.
314 All registers that the compiler knows about must be given numbers,
315 even those that are not normally considered general registers. */
317 #define M32R_NUM_REGISTERS 19
319 #ifndef SUBTARGET_NUM_REGISTERS
320 #define SUBTARGET_NUM_REGISTERS 0
323 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
325 /* 1 for registers that have pervasive standard uses
326 and are not available for the register allocator.
328 0-3 - arguments/results
329 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
331 7 - call used, static chain pointer
333 12 - call saved [reserved for global pointer]
335 14 - subroutine link register
340 19 - accumulator 1 in the m32r/x
341 By default, the extension registers are not available. */
343 #ifndef SUBTARGET_FIXED_REGISTERS
344 #define SUBTARGET_FIXED_REGISTERS
347 #define FIXED_REGISTERS \
349 0, 0, 0, 0, 0, 0, 0, 0, \
350 0, 0, 0, 0, 0, 0, 0, 1, \
352 SUBTARGET_FIXED_REGISTERS \
355 /* 1 for registers not available across function calls.
356 These must include the FIXED_REGISTERS and also any
357 registers that can be used without being saved.
358 The latter must include the registers where values are returned
359 and the register where structure-value addresses are passed.
360 Aside from that, you can include as many other registers as you like. */
362 #ifndef SUBTARGET_CALL_USED_REGISTERS
363 #define SUBTARGET_CALL_USED_REGISTERS
366 #define CALL_USED_REGISTERS \
368 1, 1, 1, 1, 1, 1, 1, 1, \
369 0, 0, 0, 0, 0, 0, 1, 1, \
371 SUBTARGET_CALL_USED_REGISTERS \
374 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
376 /* If defined, an initializer for a vector of integers, containing the
377 numbers of hard registers in the order in which GCC should
378 prefer to use them (from most preferred to least). */
380 #ifndef SUBTARGET_REG_ALLOC_ORDER
381 #define SUBTARGET_REG_ALLOC_ORDER
384 #if 1 /* Better for int code. */
385 #define REG_ALLOC_ORDER \
387 4, 5, 6, 7, 2, 3, 8, 9, 10, \
388 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
389 SUBTARGET_REG_ALLOC_ORDER \
392 #else /* Better for fp code at expense of int code. */
393 #define REG_ALLOC_ORDER \
395 0, 1, 2, 3, 4, 5, 6, 7, 8, \
396 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
397 SUBTARGET_REG_ALLOC_ORDER \
401 /* Return number of consecutive hard regs needed starting at reg REGNO
402 to hold something of mode MODE.
403 This is ordinarily the length in words of a value of mode MODE
404 but can be less for certain modes in special long registers. */
405 #define HARD_REGNO_NREGS(REGNO, MODE) \
406 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
408 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
409 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
410 extern unsigned int m32r_mode_class[];
411 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
412 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
414 /* A C expression that is nonzero if it is desirable to choose
415 register allocation so as to avoid move instructions between a
416 value of mode MODE1 and a value of mode MODE2.
418 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
419 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
420 MODE2)' must be zero. */
422 /* Tie QI/HI/SI modes together. */
423 #define MODES_TIEABLE_P(MODE1, MODE2) \
424 ( GET_MODE_CLASS (MODE1) == MODE_INT \
425 && GET_MODE_CLASS (MODE2) == MODE_INT \
426 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
427 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
429 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
430 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
432 /* Register classes and constants. */
434 /* Define the classes of registers for register constraints in the
435 machine description. Also define ranges of constants.
437 One of the classes must always be named ALL_REGS and include all hard regs.
438 If there is more than one class, another class must be named NO_REGS
439 and contain no registers.
441 The name GENERAL_REGS must be the name of a class (or an alias for
442 another name such as ALL_REGS). This is the class of registers
443 that is allowed by "g" or "r" in a register constraint.
444 Also, registers outside this class are allocated only when
445 instructions express preferences for them.
447 The classes must be numbered in nondecreasing order; that is,
448 a larger-numbered class must never be contained completely
449 in a smaller-numbered class.
451 For any two classes, it is very desirable that there be another
452 class that represents their union.
454 It is important that any condition codes have class NO_REGS.
455 See `register_operand'. */
459 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
462 #define IRA_COVER_CLASSES \
464 ACCUM_REGS, GENERAL_REGS, LIM_REG_CLASSES \
467 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
469 /* Give names of register classes as strings for dump file. */
470 #define REG_CLASS_NAMES \
471 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
473 /* Define which registers fit in which classes.
474 This is an initializer for a vector of HARD_REG_SET
475 of length N_REG_CLASSES. */
477 #ifndef SUBTARGET_REG_CLASS_CARRY
478 #define SUBTARGET_REG_CLASS_CARRY 0
481 #ifndef SUBTARGET_REG_CLASS_ACCUM
482 #define SUBTARGET_REG_CLASS_ACCUM 0
485 #ifndef SUBTARGET_REG_CLASS_GENERAL
486 #define SUBTARGET_REG_CLASS_GENERAL 0
489 #ifndef SUBTARGET_REG_CLASS_ALL
490 #define SUBTARGET_REG_CLASS_ALL 0
493 #define REG_CLASS_CONTENTS \
496 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
497 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
498 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
499 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
502 /* The same information, inverted:
503 Return the class number of the smallest class containing
504 reg number REGNO. This could be a conditional expression
505 or could index an array. */
506 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
507 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
509 /* The class value for index registers, and the one for base regs. */
510 #define INDEX_REG_CLASS GENERAL_REGS
511 #define BASE_REG_CLASS GENERAL_REGS
513 /* These assume that REGNO is a hard or pseudo reg number.
514 They give nonzero only if REGNO is a hard reg of the suitable class
515 or a pseudo reg currently allocated to a suitable hard reg.
516 Since they use reg_renumber, they are safe only once reg_renumber
517 has been allocated, which happens in local-alloc.c. */
518 #define REGNO_OK_FOR_BASE_P(REGNO) \
519 ((REGNO) < FIRST_PSEUDO_REGISTER \
520 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
521 : GPR_P (reg_renumber[REGNO]))
523 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
525 /* Return the maximum number of consecutive registers
526 needed to represent mode MODE in a register of class CLASS. */
527 #define CLASS_MAX_NREGS(CLASS, MODE) \
528 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
530 /* Return true if a value is inside a range. */
531 #define IN_RANGE_P(VALUE, LOW, HIGH) \
532 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
533 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
535 /* Some range macros. */
536 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
537 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
538 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
539 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
541 /* Stack layout and stack pointer usage. */
543 /* Define this macro if pushing a word onto the stack moves the stack
544 pointer to a smaller address. */
545 #define STACK_GROWS_DOWNWARD
547 /* Offset from frame pointer to start allocating local variables at.
548 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
549 first local allocated. Otherwise, it is the offset to the BEGINNING
550 of the first local allocated. */
551 /* The frame pointer points at the same place as the stack pointer, except if
552 alloca has been called. */
553 #define STARTING_FRAME_OFFSET \
554 M32R_STACK_ALIGN (crtl->outgoing_args_size)
556 /* Offset from the stack pointer register to the first location at which
557 outgoing arguments are placed. */
558 #define STACK_POINTER_OFFSET 0
560 /* Offset of first parameter from the argument pointer register value. */
561 #define FIRST_PARM_OFFSET(FNDECL) 0
563 /* Register to use for pushing function arguments. */
564 #define STACK_POINTER_REGNUM 15
566 /* Base register for access to local variables of the function. */
567 #define FRAME_POINTER_REGNUM 13
569 /* Base register for access to arguments of the function. */
570 #define ARG_POINTER_REGNUM 16
572 /* Register in which static-chain is passed to a function.
573 This must not be a register used by the prologue. */
574 #define STATIC_CHAIN_REGNUM 7
576 /* These aren't official macros. */
577 #define PROLOGUE_TMP_REGNUM 4
578 #define RETURN_ADDR_REGNUM 14
579 /* #define GP_REGNUM 12 */
580 #define CARRY_REGNUM 17
581 #define ACCUM_REGNUM 18
582 #define M32R_MAX_INT_REGS 16
584 #ifndef SUBTARGET_GPR_P
585 #define SUBTARGET_GPR_P(REGNO) 0
588 #ifndef SUBTARGET_ACCUM_P
589 #define SUBTARGET_ACCUM_P(REGNO) 0
592 #ifndef SUBTARGET_CARRY_P
593 #define SUBTARGET_CARRY_P(REGNO) 0
596 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
597 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
598 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
600 /* Eliminating the frame and arg pointers. */
603 /* C statement to store the difference between the frame pointer
604 and the stack pointer values immediately after the function prologue.
605 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
606 need not be defined. */
607 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
608 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
611 /* If defined, this macro specifies a table of register pairs used to
612 eliminate unneeded registers that point into the stack frame. If
613 it is not defined, the only elimination attempted by the compiler
614 is to replace references to the frame pointer with references to
617 Note that the elimination of the argument pointer with the stack
618 pointer is specified first since that is the preferred elimination. */
620 #define ELIMINABLE_REGS \
621 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
622 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
623 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
625 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
626 specifies the initial difference between the specified pair of
627 registers. This macro must be defined if `ELIMINABLE_REGS' is
630 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
633 int size = m32r_compute_frame_size (get_frame_size ()); \
635 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
637 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
638 (OFFSET) = size - crtl->args.pretend_args_size; \
639 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
640 (OFFSET) = size - crtl->args.pretend_args_size; \
642 gcc_unreachable (); \
646 /* Function argument passing. */
648 /* If defined, the maximum amount of space required for outgoing
649 arguments will be computed and placed into the variable
650 `crtl->outgoing_args_size'. No space will be pushed
651 onto the stack for each call; instead, the function prologue should
652 increase the stack frame size by this amount. */
653 #define ACCUMULATE_OUTGOING_ARGS 1
655 /* Define a data type for recording info about an argument list
656 during the scan of that argument list. This data type should
657 hold all necessary information about the function itself
658 and about the args processed so far, enough to enable macros
659 such as FUNCTION_ARG to determine where the next arg should go. */
660 #define CUMULATIVE_ARGS int
662 /* Initialize a variable CUM of type CUMULATIVE_ARGS
663 for a call to a function whose data type is FNTYPE.
664 For a library call, FNTYPE is 0. */
665 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
668 /* The number of registers used for parameter passing. Local to this file. */
669 #define M32R_MAX_PARM_REGS 4
671 /* 1 if N is a possible register number for function argument passing. */
672 #define FUNCTION_ARG_REGNO_P(N) \
673 ((unsigned) (N) < M32R_MAX_PARM_REGS)
676 /* Function results. */
678 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
679 #define DEFAULT_PCC_STRUCT_RETURN 0
681 /* Function entry and exit. */
683 /* Initialize data used by insn expanders. This is called from
684 init_emit, once for each function, before code is generated. */
685 #define INIT_EXPANDERS m32r_init_expanders ()
687 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
688 the stack pointer does not matter. The value is tested only in
689 functions that have frame pointers.
690 No definition is equivalent to always zero. */
691 #define EXIT_IGNORE_STACK 1
693 /* Output assembler code to FILE to increment profiler label # LABELNO
694 for profiling a function entry. */
695 #undef FUNCTION_PROFILER
696 #define FUNCTION_PROFILER(FILE, LABELNO) \
701 fprintf (FILE, "\tld24 r14,#mcount\n"); \
702 fprintf (FILE, "\tadd r14,r12\n"); \
703 fprintf (FILE, "\tld r14,@r14\n"); \
704 fprintf (FILE, "\tjl r14\n"); \
709 fprintf (FILE, "\tbl mcount\n"); \
712 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \
713 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \
714 fprintf (FILE, "\tjl r14\n"); \
717 fprintf (FILE, "\taddi sp,#4\n"); \
723 /* On the M32R, the trampoline is:
725 mv r7, lr -> bl L1 ; 178e 7e01
726 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
727 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
728 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
732 #ifndef CACHE_FLUSH_FUNC
733 #define CACHE_FLUSH_FUNC "_flush_cache"
735 #ifndef CACHE_FLUSH_TRAP
736 #define CACHE_FLUSH_TRAP 12
739 /* Length in bytes of the trampoline for entering a nested function. */
740 #define TRAMPOLINE_SIZE 24
743 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
745 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
747 /* Addressing modes, and classification of registers for them. */
749 /* Maximum number of registers that can appear in a valid memory address. */
750 #define MAX_REGS_PER_ADDRESS 1
752 /* We have post-inc load and pre-dec,pre-inc store,
753 but only for 4 byte vals. */
754 #define HAVE_PRE_DECREMENT 1
755 #define HAVE_PRE_INCREMENT 1
756 #define HAVE_POST_INCREMENT 1
758 /* Recognize any constant value that is a valid address. */
759 #define CONSTANT_ADDRESS_P(X) \
760 ( GET_CODE (X) == LABEL_REF \
761 || GET_CODE (X) == SYMBOL_REF \
763 || (GET_CODE (X) == CONST \
764 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
766 /* Nonzero if the constant value X is a legitimate general operand.
767 We don't allow (plus symbol large-constant) as the relocations can't
768 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
769 We allow all CONST_DOUBLE's as the md file patterns will force the
770 constant to memory if they can't handle them. */
772 #define LEGITIMATE_CONSTANT_P(X) \
773 (! (GET_CODE (X) == CONST \
774 && GET_CODE (XEXP (X, 0)) == PLUS \
775 && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \
776 && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
777 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
779 /* Condition code usage. */
781 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
782 floating point inequality comparison. */
783 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
787 /* The cost of a branch insn. */
788 /* A value of 2 here causes GCC to avoid using branches in comparisons like
789 while (a < N && a). Branches aren't that expensive on the M32R so
790 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
791 #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1)
793 /* Nonzero if access to memory by bytes is slow and undesirable.
794 For RISC chips, it means that access to memory by bytes is no
795 better than access by words when possible, so grab a whole word
796 and maybe make use of that. */
797 #define SLOW_BYTE_ACCESS 1
799 /* Define this macro if it is as good or better to call a constant
800 function address than to call an address kept in a register. */
801 #define NO_FUNCTION_CSE
803 /* Section selection. */
805 #define TEXT_SECTION_ASM_OP "\t.section .text"
806 #define DATA_SECTION_ASM_OP "\t.section .data"
807 #define BSS_SECTION_ASM_OP "\t.section .bss"
809 /* Define this macro if jump tables (for tablejump insns) should be
810 output in the text section, along with the assembler instructions.
811 Otherwise, the readonly data section is used.
812 This macro is irrelevant if there is no separate readonly data section. */
813 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
815 /* Position Independent Code. */
817 /* The register number of the register used to address a table of static
818 data addresses in memory. In some cases this register is defined by a
819 processor's ``application binary interface'' (ABI). When this macro
820 is defined, RTL is generated for this register once, as with the stack
821 pointer and frame pointer registers. If this macro is not defined, it
822 is up to the machine-dependent files to allocate such a register (if
824 #define PIC_OFFSET_TABLE_REGNUM 12
826 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
827 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
829 /* This register is call-saved on the M32R. */
830 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
832 /* A C expression that is nonzero if X is a legitimate immediate
833 operand on the target machine when generating position independent code.
834 You can assume that X satisfies CONSTANT_P, so you need not
835 check this. You can also assume `flag_pic' is true, so you need not
836 check it either. You need not define this macro if all constants
837 (including SYMBOL_REF) can be immediate operands when generating
838 position independent code. */
839 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
841 /* Control the assembler format that we output. */
843 /* A C string constant describing how to begin a comment in the target
844 assembler language. The compiler assumes that the comment will
845 end at the end of the line. */
846 #define ASM_COMMENT_START ";"
848 /* Output to assembler file text saying following lines
849 may contain character constants, extra white space, comments, etc. */
850 #define ASM_APP_ON ""
852 /* Output to assembler file text saying following lines
853 no longer contain unusual constructs. */
854 #define ASM_APP_OFF ""
856 /* Globalizing directive for a label. */
857 #define GLOBAL_ASM_OP "\t.global\t"
859 /* We do not use DBX_LINES_FUNCTION_RELATIVE or
860 dbxout_stab_value_internal_label_diff here because
861 we need to use .debugsym for the line label. */
863 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \
866 const char * begin_label = \
867 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \
869 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \
871 dbxout_begin_stabn_sline (line); \
872 assemble_name (file, label); \
874 assemble_name (file, begin_label); \
875 fputs ("\n\t.debugsym ", file); \
876 assemble_name (file, label); \
882 /* How to refer to registers in assembler output.
883 This sequence is indexed by compiler's hard-register-number (see above). */
884 #ifndef SUBTARGET_REGISTER_NAMES
885 #define SUBTARGET_REGISTER_NAMES
888 #define REGISTER_NAMES \
890 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
891 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
893 SUBTARGET_REGISTER_NAMES \
896 /* If defined, a C initializer for an array of structures containing
897 a name and a register number. This macro defines additional names
898 for hard registers, thus allowing the `asm' option in declarations
899 to refer to registers using alternate names. */
900 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
901 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
904 #define ADDITIONAL_REGISTER_NAMES \
906 /*{ "gp", GP_REGNUM },*/ \
907 { "r13", FRAME_POINTER_REGNUM }, \
908 { "r14", RETURN_ADDR_REGNUM }, \
909 { "r15", STACK_POINTER_REGNUM }, \
910 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
913 /* If defined, C string expressions to be used for the `%R', `%L',
914 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
915 are useful when a single `md' file must support multiple assembler
916 formats. In that case, the various `tm.h' files can define these
917 macros differently. */
918 #define REGISTER_PREFIX ""
919 #define LOCAL_LABEL_PREFIX ".L"
920 #define USER_LABEL_PREFIX ""
921 #define IMMEDIATE_PREFIX "#"
923 /* This is how to output an element of a case-vector that is absolute. */
924 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
928 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
929 fprintf (FILE, "\t.word\t"); \
930 assemble_name (FILE, label); \
931 fprintf (FILE, "\n"); \
935 /* This is how to output an element of a case-vector that is relative. */
936 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
940 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
941 fprintf (FILE, "\t.word\t"); \
942 assemble_name (FILE, label); \
943 fprintf (FILE, "-"); \
944 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
945 assemble_name (FILE, label); \
946 fprintf (FILE, "\n"); \
950 /* The desired alignment for the location counter at the beginning
952 /* On the M32R, align loops to 32 byte boundaries (cache line size)
954 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
956 /* Define this to be the maximum number of insns to move around when moving
957 a loop test from the top of a loop to the bottom
958 and seeing whether to duplicate it. The default is thirty.
960 Loop unrolling currently doesn't like this optimization, so
961 disable doing if we are unrolling loops and saving space. */
962 #define LOOP_TEST_THRESHOLD (optimize_size \
963 && !flag_unroll_loops \
964 && !flag_unroll_all_loops ? 2 : 30)
966 /* This is how to output an assembler line
967 that says to advance the location counter
968 to a multiple of 2**LOG bytes. */
969 /* .balign is used to avoid confusion. */
970 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
974 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
978 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
979 separate, explicit argument. If you define this macro, it is used in
980 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
981 handling the required alignment of the variable. The alignment is
982 specified as the number of bits. */
984 #define SCOMMON_ASM_OP "\t.scomm\t"
986 #undef ASM_OUTPUT_ALIGNED_COMMON
987 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
990 if (! TARGET_SDATA_NONE \
992 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
993 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
995 fprintf ((FILE), "%s", COMMON_ASM_OP); \
996 assemble_name ((FILE), (NAME)); \
997 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
1001 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1004 if (! TARGET_SDATA_NONE \
1006 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
1007 switch_to_section (get_named_section (NULL, ".sbss", 0)); \
1009 switch_to_section (bss_section); \
1010 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
1011 last_assemble_variable_decl = DECL; \
1012 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
1013 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
1017 /* Debugging information. */
1019 /* Generate DBX and DWARF debugging information. */
1020 #define DBX_DEBUGGING_INFO 1
1021 #define DWARF2_DEBUGGING_INFO 1
1023 /* Use DWARF2 debugging info by default. */
1024 #undef PREFERRED_DEBUGGING_TYPE
1025 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1027 /* Turn off splitting of long stabs. */
1028 #define DBX_CONTIN_LENGTH 0
1030 /* Miscellaneous. */
1032 /* Specify the machine mode that this machine uses
1033 for the index in the tablejump instruction. */
1034 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1036 /* Define if operations between registers always perform the operation
1037 on the full register even if a narrower mode is specified. */
1038 #define WORD_REGISTER_OPERATIONS
1040 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1041 will either zero-extend or sign-extend. The value of this macro should
1042 be the code that says which one of the two operations is implicitly
1043 done, UNKNOWN if none. */
1044 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1046 /* Max number of bytes we can move from memory
1047 to memory in one reasonably fast instruction. */
1050 /* Define this to be nonzero if shift instructions ignore all but the low-order
1052 #define SHIFT_COUNT_TRUNCATED 1
1054 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1055 is done just by pretending it is already truncated. */
1056 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1058 /* Specify the machine mode that pointers have.
1059 After generation of rtl, the compiler makes no further distinction
1060 between pointers and any other objects of this machine mode. */
1061 /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has
1062 its own problems (you have to add extendpsisi2 and truncsipsi2).
1064 #define Pmode SImode
1066 /* A function address in a call instruction. */
1067 #define FUNCTION_MODE SImode
1069 /* M32R function types. */
1070 enum m32r_function_type
1072 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
1075 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1077 /* The maximum number of bytes to copy using pairs of load/store instructions.
1078 If a block is larger than this then a loop will be generated to copy
1079 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
1080 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
1081 string copy in it. */
1082 #define MAX_MOVE_BYTES 32
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