1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
39 #include "m32r-protos.h"
41 #include "target-def.h"
43 /* Save the operands last given to a compare for use when we
44 generate a scc or bcc insn. */
45 rtx m32r_compare_op0, m32r_compare_op1;
47 /* Array of valid operand punctuation characters. */
48 char m32r_punct_chars[256];
50 /* Selected code model. */
51 const char * m32r_model_string = M32R_MODEL_DEFAULT;
52 enum m32r_model m32r_model;
54 /* Selected SDA support. */
55 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
56 enum m32r_sdata m32r_sdata;
58 /* Scheduler support */
59 static int m32r_sched_odd_word_p;
61 /* Forward declaration. */
62 static void init_reg_tables PARAMS ((void));
63 static void block_move_call PARAMS ((rtx, rtx, rtx));
64 static int m32r_is_insn PARAMS ((rtx));
65 const struct attribute_spec m32r_attribute_table[];
66 static tree m32r_handle_model_attribute PARAMS ((tree *, tree, tree, int, bool *));
67 static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
68 static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
70 static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
71 static int m32r_adjust_priority PARAMS ((rtx, int));
72 static void m32r_sched_init PARAMS ((FILE *, int, int));
73 static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
74 static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
75 static int m32r_issue_rate PARAMS ((void));
78 /* Initialize the GCC target structure. */
79 #undef TARGET_ATTRIBUTE_TABLE
80 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
82 #undef TARGET_ASM_ALIGNED_HI_OP
83 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
84 #undef TARGET_ASM_ALIGNED_SI_OP
85 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
87 #undef TARGET_ASM_FUNCTION_PROLOGUE
88 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
89 #undef TARGET_ASM_FUNCTION_EPILOGUE
90 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
92 #undef TARGET_SCHED_ADJUST_COST
93 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
94 #undef TARGET_SCHED_ADJUST_PRIORITY
95 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
96 #undef TARGET_SCHED_ISSUE_RATE
97 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
98 #undef TARGET_SCHED_VARIABLE_ISSUE
99 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
100 #undef TARGET_SCHED_INIT
101 #define TARGET_SCHED_INIT m32r_sched_init
102 #undef TARGET_SCHED_REORDER
103 #define TARGET_SCHED_REORDER m32r_sched_reorder
105 struct gcc_target targetm = TARGET_INITIALIZER;
107 /* Called by OVERRIDE_OPTIONS to initialize various things. */
114 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
115 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
116 m32r_punct_chars['#'] = 1;
117 m32r_punct_chars['@'] = 1; /* ??? no longer used */
119 /* Provide default value if not specified. */
121 g_switch_value = SDATA_DEFAULT_SIZE;
123 if (strcmp (m32r_model_string, "small") == 0)
124 m32r_model = M32R_MODEL_SMALL;
125 else if (strcmp (m32r_model_string, "medium") == 0)
126 m32r_model = M32R_MODEL_MEDIUM;
127 else if (strcmp (m32r_model_string, "large") == 0)
128 m32r_model = M32R_MODEL_LARGE;
130 error ("bad value (%s) for -mmodel switch", m32r_model_string);
132 if (strcmp (m32r_sdata_string, "none") == 0)
133 m32r_sdata = M32R_SDATA_NONE;
134 else if (strcmp (m32r_sdata_string, "sdata") == 0)
135 m32r_sdata = M32R_SDATA_SDATA;
136 else if (strcmp (m32r_sdata_string, "use") == 0)
137 m32r_sdata = M32R_SDATA_USE;
139 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
142 /* Vectors to keep interesting information about registers where it can easily
143 be got. We use to use the actual mode value as the bit number, but there
144 is (or may be) more than 32 modes now. Instead we use two tables: one
145 indexed by hard register number, and one indexed by mode. */
147 /* The purpose of m32r_mode_class is to shrink the range of modes so that
148 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
149 mapped into one m32r_mode_class mode. */
154 S_MODE, D_MODE, T_MODE, O_MODE,
155 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
158 /* Modes for condition codes. */
159 #define C_MODES (1 << (int) C_MODE)
161 /* Modes for single-word and smaller quantities. */
162 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
164 /* Modes for double-word and smaller quantities. */
165 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
167 /* Modes for quad-word and smaller quantities. */
168 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
170 /* Modes for accumulators. */
171 #define A_MODES (1 << (int) A_MODE)
173 /* Value is 1 if register/mode pair is acceptable on arc. */
175 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
177 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
178 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
179 S_MODES, C_MODES, A_MODES, A_MODES
182 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
184 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
191 for (i = 0; i < NUM_MACHINE_MODES; i++)
193 switch (GET_MODE_CLASS (i))
196 case MODE_PARTIAL_INT:
197 case MODE_COMPLEX_INT:
198 if (GET_MODE_SIZE (i) <= 4)
199 m32r_mode_class[i] = 1 << (int) S_MODE;
200 else if (GET_MODE_SIZE (i) == 8)
201 m32r_mode_class[i] = 1 << (int) D_MODE;
202 else if (GET_MODE_SIZE (i) == 16)
203 m32r_mode_class[i] = 1 << (int) T_MODE;
204 else if (GET_MODE_SIZE (i) == 32)
205 m32r_mode_class[i] = 1 << (int) O_MODE;
207 m32r_mode_class[i] = 0;
210 case MODE_COMPLEX_FLOAT:
211 if (GET_MODE_SIZE (i) <= 4)
212 m32r_mode_class[i] = 1 << (int) SF_MODE;
213 else if (GET_MODE_SIZE (i) == 8)
214 m32r_mode_class[i] = 1 << (int) DF_MODE;
215 else if (GET_MODE_SIZE (i) == 16)
216 m32r_mode_class[i] = 1 << (int) TF_MODE;
217 else if (GET_MODE_SIZE (i) == 32)
218 m32r_mode_class[i] = 1 << (int) OF_MODE;
220 m32r_mode_class[i] = 0;
224 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
225 we must explicitly check for them here. */
226 if (i == (int) CCmode)
227 m32r_mode_class[i] = 1 << (int) C_MODE;
229 m32r_mode_class[i] = 0;
234 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
237 m32r_regno_reg_class[i] = GENERAL_REGS;
238 else if (i == ARG_POINTER_REGNUM)
239 m32r_regno_reg_class[i] = GENERAL_REGS;
241 m32r_regno_reg_class[i] = NO_REGS;
245 /* M32R specific attribute support.
247 interrupt - for interrupt functions
249 model - select code model used to access object
251 small: addresses use 24 bits, use bl to make calls
252 medium: addresses use 32 bits, use bl to make calls
253 large: addresses use 32 bits, use seth/add3/jl to make calls
255 Grep for MODEL in m32r.h for more info.
258 static tree small_ident1;
259 static tree small_ident2;
260 static tree medium_ident1;
261 static tree medium_ident2;
262 static tree large_ident1;
263 static tree large_ident2;
266 init_idents PARAMS ((void))
268 if (small_ident1 == 0)
270 small_ident1 = get_identifier ("small");
271 small_ident2 = get_identifier ("__small__");
272 medium_ident1 = get_identifier ("medium");
273 medium_ident2 = get_identifier ("__medium__");
274 large_ident1 = get_identifier ("large");
275 large_ident2 = get_identifier ("__large__");
279 const struct attribute_spec m32r_attribute_table[] =
281 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
282 { "interrupt", 0, 0, true, false, false, NULL },
283 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
284 { NULL, 0, 0, false, false, false, NULL }
288 /* Handle an "model" attribute; arguments as in
289 struct attribute_spec.handler. */
291 m32r_handle_model_attribute (node, name, args, flags, no_add_attrs)
292 tree *node ATTRIBUTE_UNUSED;
295 int flags ATTRIBUTE_UNUSED;
301 arg = TREE_VALUE (args);
303 if (arg != small_ident1
304 && arg != small_ident2
305 && arg != medium_ident1
306 && arg != medium_ident2
307 && arg != large_ident1
308 && arg != large_ident2)
310 warning ("invalid argument of `%s' attribute",
311 IDENTIFIER_POINTER (name));
312 *no_add_attrs = true;
318 /* A C statement or statements to switch to the appropriate
319 section for output of DECL. DECL is either a `VAR_DECL' node
320 or a constant of some sort. RELOC indicates whether forming
321 the initial value of DECL requires link-time relocations. */
324 m32r_select_section (decl, reloc)
328 if (TREE_CODE (decl) == STRING_CST)
330 if (! flag_writable_strings)
335 else if (TREE_CODE (decl) == VAR_DECL)
337 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
339 else if ((flag_pic && reloc)
340 || !TREE_READONLY (decl)
341 || TREE_SIDE_EFFECTS (decl)
342 || !DECL_INITIAL (decl)
343 || (DECL_INITIAL (decl) != error_mark_node
344 && !TREE_CONSTANT (DECL_INITIAL (decl))))
353 /* Encode section information of DECL, which is either a VAR_DECL,
354 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
356 For the M32R we want to record:
358 - whether the object lives in .sdata/.sbss.
359 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
361 - what code model should be used to access the object
362 small: recorded with no flag - for space efficiency since they'll
364 medium: prefixed with MEDIUM_FLAG_CHAR
365 large: prefixed with LARGE_FLAG_CHAR
369 m32r_encode_section_info (decl, first)
379 switch (TREE_CODE (decl))
383 model = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
387 /* ??? document all others that can appear here */
392 /* Only mark the object as being small data area addressable if
393 it hasn't been explicitly marked with a code model.
395 The user can explicitly put an object in the small data area with the
396 section attribute. If the object is in sdata/sbss and marked with a
397 code model do both [put the object in .sdata and mark it as being
398 addressed with a specific code model - don't mark it as being addressed
399 with an SDA reloc though]. This is ok and might be useful at times. If
400 the object doesn't fit the linker will give an error. */
404 if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
405 && DECL_SECTION_NAME (decl) != NULL_TREE)
407 char *name = (char *) TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
408 if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
410 #if 0 /* ??? There's no reason to disallow this, is there? */
411 if (TREE_READONLY (decl))
412 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
414 prefix = SDATA_FLAG_CHAR;
419 if (TREE_CODE (decl) == VAR_DECL
420 && ! TREE_READONLY (decl)
421 && ! TARGET_SDATA_NONE)
423 int size = int_size_in_bytes (TREE_TYPE (decl));
425 if (size > 0 && size <= g_switch_value)
426 prefix = SDATA_FLAG_CHAR;
431 /* If data area not decided yet, check for a code model. */
440 id = TREE_VALUE (TREE_VALUE (model));
442 if (id == small_ident1 || id == small_ident2)
443 ; /* don't mark the symbol specially */
444 else if (id == medium_ident1 || id == medium_ident2)
445 prefix = MEDIUM_FLAG_CHAR;
446 else if (id == large_ident1 || id == large_ident2)
447 prefix = LARGE_FLAG_CHAR;
449 abort (); /* shouldn't happen */
453 if (TARGET_MODEL_SMALL)
454 ; /* don't mark the symbol specially */
455 else if (TARGET_MODEL_MEDIUM)
456 prefix = MEDIUM_FLAG_CHAR;
457 else if (TARGET_MODEL_LARGE)
458 prefix = LARGE_FLAG_CHAR;
460 abort (); /* shouldn't happen */
466 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
467 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
468 const char *str = XSTR (XEXP (rtl, 0), 0);
469 int len = strlen (str);
470 char *newstr = ggc_alloc (len + 2);
472 strcpy (newstr + 1, str);
474 /* Note - we cannot leave the string in the ggc_alloc'ed space.
475 It must reside in the stringtable's domain. */
476 newstr = (char *) ggc_alloc_string (newstr, len + 2);
478 XSTR (XEXP (rtl, 0), 0) = newstr;
482 /* Do anything needed before RTL is emitted for each function. */
485 m32r_init_expanders ()
487 /* ??? At one point there was code here. The function is left in
488 to make it easy to experiment. */
491 /* Acceptable arguments to the call insn. */
494 call_address_operand (op, mode)
496 enum machine_mode mode;
498 return symbolic_operand (op, mode);
500 /* Constants and values in registers are not OK, because
501 the m32r BL instruction can only support PC relative branching. */
505 call_operand (op, mode)
507 enum machine_mode mode;
509 if (GET_CODE (op) != MEM)
512 return call_address_operand (op, mode);
515 /* Returns 1 if OP is a symbol reference. */
518 symbolic_operand (op, mode)
520 enum machine_mode mode ATTRIBUTE_UNUSED;
522 switch (GET_CODE (op))
534 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
537 small_data_operand (op, mode)
539 enum machine_mode mode ATTRIBUTE_UNUSED;
541 if (! TARGET_SDATA_USE)
544 if (GET_CODE (op) == SYMBOL_REF)
545 return SDATA_NAME_P (XSTR (op, 0));
547 if (GET_CODE (op) == CONST
548 && GET_CODE (XEXP (op, 0)) == PLUS
549 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
550 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
551 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
552 return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
557 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
560 addr24_operand (op, mode)
562 enum machine_mode mode ATTRIBUTE_UNUSED;
564 if (GET_CODE (op) == LABEL_REF)
565 return TARGET_ADDR24;
567 if (GET_CODE (op) == SYMBOL_REF)
568 return (SMALL_NAME_P (XSTR (op, 0))
570 && (CONSTANT_POOL_ADDRESS_P (op)
571 || LIT_NAME_P (XSTR (op, 0)))));
573 if (GET_CODE (op) == CONST
574 && GET_CODE (XEXP (op, 0)) == PLUS
575 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
576 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
577 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
579 rtx sym = XEXP (XEXP (op, 0), 0);
580 return (SMALL_NAME_P (XSTR (sym, 0))
582 && (CONSTANT_POOL_ADDRESS_P (op)
583 || LIT_NAME_P (XSTR (op, 0)))));
589 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
592 addr32_operand (op, mode)
594 enum machine_mode mode;
596 if (GET_CODE (op) == LABEL_REF)
597 return TARGET_ADDR32;
599 if (GET_CODE (op) == SYMBOL_REF)
600 return (! addr24_operand (op, mode)
601 && ! small_data_operand (op, mode));
603 if (GET_CODE (op) == CONST
604 && GET_CODE (XEXP (op, 0)) == PLUS
605 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
606 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
608 return (! addr24_operand (op, mode)
609 && ! small_data_operand (op, mode));
615 /* Return 1 if OP is a function that can be called with the `bl' insn. */
618 call26_operand (op, mode)
620 enum machine_mode mode ATTRIBUTE_UNUSED;
622 if (GET_CODE (op) == SYMBOL_REF)
623 return ! LARGE_NAME_P (XSTR (op, 0));
625 return TARGET_CALL26;
628 /* Returns 1 if OP is an acceptable operand for seth/add3. */
631 seth_add3_operand (op, mode)
633 enum machine_mode mode ATTRIBUTE_UNUSED;
635 if (GET_CODE (op) == SYMBOL_REF
636 || GET_CODE (op) == LABEL_REF)
639 if (GET_CODE (op) == CONST
640 && GET_CODE (XEXP (op, 0)) == PLUS
641 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
642 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
643 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
649 /* Return true if OP is a signed 8 bit immediate value. */
652 int8_operand (op, mode)
654 enum machine_mode mode ATTRIBUTE_UNUSED;
656 if (GET_CODE (op) != CONST_INT)
658 return INT8_P (INTVAL (op));
661 /* Return true if OP is a signed 16 bit immediate value
662 useful in comparisons. */
665 cmp_int16_operand (op, mode)
667 enum machine_mode mode ATTRIBUTE_UNUSED;
669 if (GET_CODE (op) != CONST_INT)
671 return CMP_INT16_P (INTVAL (op));
674 /* Return true if OP is an unsigned 16 bit immediate value. */
677 uint16_operand (op, mode)
679 enum machine_mode mode ATTRIBUTE_UNUSED;
681 if (GET_CODE (op) != CONST_INT)
683 return UINT16_P (INTVAL (op));
686 /* Return true if OP is a register or signed 16 bit value. */
689 reg_or_int16_operand (op, mode)
691 enum machine_mode mode;
693 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
694 return register_operand (op, mode);
695 if (GET_CODE (op) != CONST_INT)
697 return INT16_P (INTVAL (op));
700 /* Return true if OP is a register or an unsigned 16 bit value. */
703 reg_or_uint16_operand (op, mode)
705 enum machine_mode mode;
707 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
708 return register_operand (op, mode);
709 if (GET_CODE (op) != CONST_INT)
711 return UINT16_P (INTVAL (op));
714 /* Return true if OP is a register or an integer value that can be
715 used is SEQ/SNE. We can use either XOR of the value or ADD of
716 the negative of the value for the constant. Don't allow 0,
717 because that is special cased. */
720 reg_or_eq_int16_operand (op, mode)
722 enum machine_mode mode;
726 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
727 return register_operand (op, mode);
729 if (GET_CODE (op) != CONST_INT)
733 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
736 /* Return true if OP is a register or signed 16 bit value for compares. */
739 reg_or_cmp_int16_operand (op, mode)
741 enum machine_mode mode;
743 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
744 return register_operand (op, mode);
745 if (GET_CODE (op) != CONST_INT)
747 return CMP_INT16_P (INTVAL (op));
750 /* Return true if OP is a register or the constant 0. */
753 reg_or_zero_operand (op, mode)
755 enum machine_mode mode;
757 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
758 return register_operand (op, mode);
760 if (GET_CODE (op) != CONST_INT)
763 return INTVAL (op) == 0;
766 /* Return true if OP is a const_int requiring two instructions to load. */
769 two_insn_const_operand (op, mode)
771 enum machine_mode mode ATTRIBUTE_UNUSED;
773 if (GET_CODE (op) != CONST_INT)
775 if (INT16_P (INTVAL (op))
776 || UINT24_P (INTVAL (op))
777 || UPPER16_P (INTVAL (op)))
782 /* Return true if OP is an acceptable argument for a single word
786 move_src_operand (op, mode)
788 enum machine_mode mode;
790 switch (GET_CODE (op))
794 return addr24_operand (op, mode);
796 /* ??? We allow more cse opportunities if we only allow constants
797 loadable with one insn, and split the rest into two. The instances
798 where this would help should be rare and the current way is
800 if (HOST_BITS_PER_WIDE_INT > 32)
802 HOST_WIDE_INT rest = INTVAL (op) >> 31;
803 return (rest == 0 || rest == -1);
808 return TARGET_ADDR24;
812 else if (mode == SImode)
814 /* Large unsigned constants are represented as const_double's. */
815 unsigned HOST_WIDE_INT low, high;
817 low = CONST_DOUBLE_LOW (op);
818 high = CONST_DOUBLE_HIGH (op);
819 return high == 0 && low <= 0xffffffff;
824 return register_operand (op, mode);
826 /* (subreg (mem ...) ...) can occur here if the inner part was once a
827 pseudo-reg and is now a stack slot. */
828 if (GET_CODE (SUBREG_REG (op)) == MEM)
829 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
831 return register_operand (op, mode);
833 if (GET_CODE (XEXP (op, 0)) == PRE_INC
834 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
835 return 0; /* loads can't do pre-{inc,dec} */
836 return address_operand (XEXP (op, 0), mode);
842 /* Return true if OP is an acceptable argument for a double word
846 move_double_src_operand (op, mode)
848 enum machine_mode mode;
850 switch (GET_CODE (op))
856 return register_operand (op, mode);
858 /* (subreg (mem ...) ...) can occur here if the inner part was once a
859 pseudo-reg and is now a stack slot. */
860 if (GET_CODE (SUBREG_REG (op)) == MEM)
861 return move_double_src_operand (SUBREG_REG (op), mode);
863 return register_operand (op, mode);
865 /* Disallow auto inc/dec for now. */
866 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
867 || GET_CODE (XEXP (op, 0)) == PRE_INC)
869 return address_operand (XEXP (op, 0), mode);
875 /* Return true if OP is an acceptable argument for a move destination. */
878 move_dest_operand (op, mode)
880 enum machine_mode mode;
882 switch (GET_CODE (op))
885 return register_operand (op, mode);
887 /* (subreg (mem ...) ...) can occur here if the inner part was once a
888 pseudo-reg and is now a stack slot. */
889 if (GET_CODE (SUBREG_REG (op)) == MEM)
890 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
892 return register_operand (op, mode);
894 if (GET_CODE (XEXP (op, 0)) == POST_INC)
895 return 0; /* stores can't do post inc */
896 return address_operand (XEXP (op, 0), mode);
902 /* Return 1 if OP is a DImode const we want to handle inline.
903 This must match the code in the movdi pattern.
904 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
910 rtx high_rtx, low_rtx;
911 HOST_WIDE_INT high, low;
913 split_double (op, &high_rtx, &low_rtx);
914 high = INTVAL (high_rtx);
915 low = INTVAL (low_rtx);
916 /* Pick constants loadable with 2 16 bit `ldi' insns. */
917 if (high >= -128 && high <= 127
918 && low >= -128 && low <= 127)
923 /* Return 1 if OP is a DFmode const we want to handle inline.
924 This must match the code in the movdf pattern.
925 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
934 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
935 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
936 if (l[0] == 0 && l[1] == 0)
938 if ((l[0] & 0xffff) == 0 && l[1] == 0)
943 /* Return 1 if OP is an EQ or NE comparison operator. */
946 eqne_comparison_operator (op, mode)
948 enum machine_mode mode ATTRIBUTE_UNUSED;
950 enum rtx_code code = GET_CODE (op);
952 if (GET_RTX_CLASS (code) != '<')
954 return (code == EQ || code == NE);
957 /* Return 1 if OP is a signed comparison operator. */
960 signed_comparison_operator (op, mode)
962 enum machine_mode mode ATTRIBUTE_UNUSED;
964 enum rtx_code code = GET_CODE (op);
966 if (GET_RTX_CLASS (code) != '<')
968 return (code == EQ || code == NE
969 || code == LT || code == LE || code == GT || code == GE);
972 /* Return 1 if OP is (mem (reg ...)).
973 This is used in insn length calcs. */
976 memreg_operand (op, mode)
978 enum machine_mode mode ATTRIBUTE_UNUSED;
980 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
983 /* Return true if OP is an acceptable input argument for a zero/sign extend
987 extend_operand (op, mode)
989 enum machine_mode mode;
993 switch (GET_CODE (op))
997 return register_operand (op, mode);
1000 addr = XEXP (op, 0);
1001 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1002 return 0; /* loads can't do pre inc/pre dec */
1004 return address_operand (addr, mode);
1011 /* Return non-zero if the operand is an insn that is a small insn.
1012 Allow const_int 0 as well, which is a placeholder for NOP slots. */
1015 small_insn_p (op, mode)
1017 enum machine_mode mode ATTRIBUTE_UNUSED;
1019 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1025 return get_attr_length (op) == 2;
1028 /* Return non-zero if the operand is an insn that is a large insn. */
1031 large_insn_p (op, mode)
1033 enum machine_mode mode ATTRIBUTE_UNUSED;
1038 return get_attr_length (op) != 2;
1044 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1045 return the mode to be used for the comparison. */
1048 m32r_select_cc_mode (op, x, y)
1049 int op ATTRIBUTE_UNUSED;
1050 rtx x ATTRIBUTE_UNUSED;
1051 rtx y ATTRIBUTE_UNUSED;
1053 return (int) CCmode;
1056 /* X and Y are two things to compare using CODE. Emit the compare insn and
1057 return the rtx for compare [arg0 of the if_then_else].
1058 If need_compare is true then the comparison insn must be generated, rather
1059 than being susummed into the following branch instruction. */
1062 gen_compare (code, x, y, need_compare)
1067 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1068 enum rtx_code compare_code, branch_code;
1069 rtx cc_reg = gen_rtx_REG (mode, CARRY_REGNUM);
1074 case EQ: compare_code = EQ; branch_code = NE; break;
1075 case NE: compare_code = EQ; branch_code = EQ; break;
1076 case LT: compare_code = LT; branch_code = NE; break;
1077 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1078 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1079 case GE: compare_code = LT; branch_code = EQ; break;
1080 case LTU: compare_code = LTU; branch_code = NE; break;
1081 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1082 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1083 case GEU: compare_code = LTU; branch_code = EQ; break;
1091 switch (compare_code)
1094 if (GET_CODE (y) == CONST_INT
1095 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1098 rtx tmp = gen_reg_rtx (SImode);
1100 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1104 else if (CONSTANT_P (y)) /* reg equal to const. */
1106 rtx tmp = force_reg (GET_MODE (x), y);
1110 if (register_operand (y, SImode) /* reg equal to reg. */
1111 || y == const0_rtx) /* req equal to zero. */
1113 emit_insn (gen_cmp_eqsi_insn (x, y));
1115 return gen_rtx (code, mode, cc_reg, const0_rtx);
1120 if (register_operand (y, SImode)
1121 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1123 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1128 emit_insn (gen_cmp_ltsi_insn (x, y));
1132 if (y == const0_rtx)
1135 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1136 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1140 if (GET_CODE (y) == CONST_INT)
1141 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1143 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1144 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1148 emit_insn (gen_cmp_ltsi_insn (x, y));
1155 return gen_rtx (code, mode, cc_reg, const0_rtx);
1160 if (register_operand (y, SImode)
1161 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1163 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1168 emit_insn (gen_cmp_ltusi_insn (x, y));
1172 if (y == const0_rtx)
1175 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1176 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1180 if (GET_CODE (y) == CONST_INT)
1181 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1183 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1184 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1188 emit_insn (gen_cmp_ltusi_insn (x, y));
1195 return gen_rtx (code, mode, cc_reg, const0_rtx);
1205 /* reg/reg equal comparison */
1206 if (compare_code == EQ
1207 && register_operand (y, SImode))
1208 return gen_rtx (code, mode, x, y);
1210 /* reg/zero signed comparison */
1211 if ((compare_code == EQ || compare_code == LT)
1213 return gen_rtx (code, mode, x, y);
1215 /* reg/smallconst equal comparison */
1216 if (compare_code == EQ
1217 && GET_CODE (y) == CONST_INT
1218 && CMP_INT16_P (INTVAL (y)))
1220 rtx tmp = gen_reg_rtx (SImode);
1221 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1222 return gen_rtx (code, mode, tmp, const0_rtx);
1225 /* reg/const equal comparison */
1226 if (compare_code == EQ
1229 rtx tmp = force_reg (GET_MODE (x), y);
1230 return gen_rtx (code, mode, x, tmp);
1237 y = force_reg (GET_MODE (x), y);
1241 (code == LTU || code == LEU || code == GTU || code == GEU)
1242 ? uint16_operand (y, GET_MODE (y))
1243 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1246 y = force_reg (GET_MODE (x), y);
1250 switch (compare_code)
1253 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1256 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1259 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1266 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (mode));
1269 /* Split a 2 word move (DI or DF) into component parts. */
1272 gen_split_move_double (operands)
1275 enum machine_mode mode = GET_MODE (operands[0]);
1276 rtx dest = operands[0];
1277 rtx src = operands[1];
1280 /* We might have (SUBREG (MEM)) here, so just get rid of the
1281 subregs to make this code simpler. It is safe to call
1282 alter_subreg any time after reload. */
1283 if (GET_CODE (dest) == SUBREG)
1284 alter_subreg (&dest);
1285 if (GET_CODE (src) == SUBREG)
1286 alter_subreg (&src);
1289 if (GET_CODE (dest) == REG)
1291 int dregno = REGNO (dest);
1294 if (GET_CODE (src) == REG)
1296 int sregno = REGNO (src);
1298 int reverse = (dregno == sregno + 1);
1300 /* We normally copy the low-numbered register first. However, if
1301 the first register operand 0 is the same as the second register of
1302 operand 1, we must copy in the opposite order. */
1303 emit_insn (gen_rtx_SET (VOIDmode,
1304 operand_subword (dest, reverse, TRUE, mode),
1305 operand_subword (src, reverse, TRUE, mode)));
1307 emit_insn (gen_rtx_SET (VOIDmode,
1308 operand_subword (dest, !reverse, TRUE, mode),
1309 operand_subword (src, !reverse, TRUE, mode)));
1312 /* reg = constant */
1313 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1316 split_double (src, &words[0], &words[1]);
1317 emit_insn (gen_rtx_SET (VOIDmode,
1318 operand_subword (dest, 0, TRUE, mode),
1321 emit_insn (gen_rtx_SET (VOIDmode,
1322 operand_subword (dest, 1, TRUE, mode),
1327 else if (GET_CODE (src) == MEM)
1329 /* If the high-address word is used in the address, we must load it
1330 last. Otherwise, load it first. */
1332 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1334 /* We used to optimize loads from single registers as
1338 if r3 were not used subsequently. However, the REG_NOTES aren't
1339 propigated correctly by the reload phase, and it can cause bad
1340 code to be generated. We could still try:
1342 ld r1,r3+; ld r2,r3; addi r3,-4
1344 which saves 2 bytes and doesn't force longword alignment. */
1345 emit_insn (gen_rtx_SET (VOIDmode,
1346 operand_subword (dest, reverse, TRUE, mode),
1347 adjust_address (src, SImode,
1348 reverse * UNITS_PER_WORD)));
1350 emit_insn (gen_rtx_SET (VOIDmode,
1351 operand_subword (dest, !reverse, TRUE, mode),
1352 adjust_address (src, SImode,
1353 !reverse * UNITS_PER_WORD)));
1361 /* We used to optimize loads from single registers as
1365 if r3 were not used subsequently. However, the REG_NOTES aren't
1366 propigated correctly by the reload phase, and it can cause bad
1367 code to be generated. We could still try:
1369 st r1,r3; st r2,+r3; addi r3,-4
1371 which saves 2 bytes and doesn't force longword alignment. */
1372 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1374 emit_insn (gen_rtx_SET (VOIDmode,
1375 adjust_address (dest, SImode, 0),
1376 operand_subword (src, 0, TRUE, mode)));
1378 emit_insn (gen_rtx_SET (VOIDmode,
1379 adjust_address (dest, SImode, UNITS_PER_WORD),
1380 operand_subword (src, 1, TRUE, mode)));
1386 val = gen_sequence ();
1392 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1395 function_arg_partial_nregs (cum, mode, type, named)
1396 CUMULATIVE_ARGS *cum;
1397 enum machine_mode mode;
1399 int named ATTRIBUTE_UNUSED;
1403 (((mode == BLKmode && type)
1404 ? (unsigned int) int_size_in_bytes (type)
1405 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1408 if (*cum >= M32R_MAX_PARM_REGS)
1410 else if (*cum + size > M32R_MAX_PARM_REGS)
1411 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1418 /* Do any needed setup for a variadic function. For the M32R, we must
1419 create a register parameter block, and then copy any anonymous arguments
1420 in registers to memory.
1422 CUM has not been updated for the last named argument which has type TYPE
1423 and mode MODE, and we rely on this fact. */
1426 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1427 CUMULATIVE_ARGS *cum;
1428 enum machine_mode mode;
1438 /* All BLKmode values are passed by reference. */
1439 if (mode == BLKmode)
1442 /* We must treat `__builtin_va_alist' as an anonymous arg. */
1443 if (current_function_varargs)
1444 first_anon_arg = *cum;
1446 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1447 + ROUND_ADVANCE_ARG (mode, type));
1449 if (first_anon_arg < M32R_MAX_PARM_REGS)
1451 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1452 int first_reg_offset = first_anon_arg;
1453 /* Size in words to "pretend" allocate. */
1454 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1457 regblock = gen_rtx_MEM (BLKmode,
1458 plus_constant (arg_pointer_rtx,
1459 FIRST_PARM_OFFSET (0)));
1460 set_mem_alias_set (regblock, get_varargs_alias_set ());
1461 move_block_from_reg (first_reg_offset, regblock,
1462 size, size * UNITS_PER_WORD);
1464 *pretend_size = (size * UNITS_PER_WORD);
1469 /* Implement `va_arg'. */
1472 m32r_va_arg (valist, type)
1475 HOST_WIDE_INT size, rsize;
1479 size = int_size_in_bytes (type);
1480 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1484 tree type_ptr, type_ptr_ptr;
1486 /* Pass by reference. */
1488 type_ptr = build_pointer_type (type);
1489 type_ptr_ptr = build_pointer_type (type_ptr);
1491 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1492 build_int_2 (UNITS_PER_WORD, 0));
1493 TREE_SIDE_EFFECTS (t) = 1;
1494 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1495 TREE_SIDE_EFFECTS (t) = 1;
1496 t = build1 (INDIRECT_REF, type_ptr, t);
1498 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1502 /* Pass by value. */
1504 if (size < UNITS_PER_WORD)
1506 /* Care for bigendian correction on the aligned address. */
1507 t = build (PLUS_EXPR, ptr_type_node, valist,
1508 build_int_2 (rsize - size, 0));
1509 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1510 addr_rtx = copy_to_reg (addr_rtx);
1513 t = build (PLUS_EXPR, va_list_type_node, valist,
1514 build_int_2 (rsize, 0));
1515 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1516 TREE_SIDE_EFFECTS (t) = 1;
1517 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1521 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1522 build_int_2 (rsize, 0));
1523 TREE_SIDE_EFFECTS (t) = 1;
1524 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1532 m32r_adjust_cost (insn, link, dep_insn, cost)
1533 rtx insn ATTRIBUTE_UNUSED;
1534 rtx link ATTRIBUTE_UNUSED;
1535 rtx dep_insn ATTRIBUTE_UNUSED;
1542 /* Return true if INSN is real instruction bearing insn. */
1548 return (INSN_P (insn)
1549 && GET_CODE (PATTERN (insn)) != USE
1550 && GET_CODE (PATTERN (insn)) != CLOBBER
1551 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1554 /* Increase the priority of long instructions so that the
1555 short instructions are scheduled ahead of the long ones. */
1558 m32r_adjust_priority (insn, priority)
1562 if (m32r_is_insn (insn)
1563 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1570 /* Initialize for scheduling a group of instructions. */
1573 m32r_sched_init (stream, verbose, max_ready)
1574 FILE * stream ATTRIBUTE_UNUSED;
1575 int verbose ATTRIBUTE_UNUSED;
1576 int max_ready ATTRIBUTE_UNUSED;
1578 m32r_sched_odd_word_p = FALSE;
1582 /* Reorder the schedulers priority list if needed */
1585 m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
1590 int clock ATTRIBUTE_UNUSED;
1592 int n_ready = *n_readyp;
1595 return m32r_issue_rate ();
1602 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1604 (m32r_sched_odd_word_p) ? "odd" : "even");
1608 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1609 rtx * long_tail = long_head;
1610 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1611 rtx * short_tail = short_head;
1612 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1613 rtx * new_tail = new_head + (n_ready - 1);
1616 /* Loop through the instructions, classifing them as short/long. Try
1617 to keep 2 short together and/or 1 long. Note, the ready list is
1618 actually ordered backwards, so keep it in that manner. */
1619 for (i = n_ready-1; i >= 0; i--)
1621 rtx insn = ready[i];
1623 if (! m32r_is_insn (insn))
1625 /* Dump all current short/long insns just in case. */
1626 while (long_head != long_tail)
1627 *new_tail-- = *long_head++;
1629 while (short_head != short_tail)
1630 *new_tail-- = *short_head++;
1635 ";;\t\t::: Skipping non instruction %d\n",
1642 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1643 *long_tail++ = insn;
1646 *short_tail++ = insn;
1650 /* If we are on an odd word, emit a single short instruction if
1652 if (m32r_sched_odd_word_p && short_head != short_tail)
1653 *new_tail-- = *short_head++;
1655 /* Now dump out all of the long instructions */
1656 while (long_head != long_tail)
1657 *new_tail-- = *long_head++;
1659 /* Now dump out all of the short instructions */
1660 while (short_head != short_tail)
1661 *new_tail-- = *short_head++;
1663 if (new_tail+1 != new_head)
1666 memcpy (ready, new_head, sizeof (rtx) * n_ready);
1670 fprintf (stream, ";;\t\t::: New ready list: ");
1671 for (i = 0; i < n_ready; i++)
1673 rtx insn = ready[i];
1675 fprintf (stream, " %d", INSN_UID (ready[i]));
1677 if (! m32r_is_insn (insn))
1678 fputs ("(?)", stream);
1680 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1681 fputs ("(l)", stream);
1684 fputs ("(s)", stream);
1687 fprintf (stream, "\n");
1690 return m32r_issue_rate ();
1693 /* Indicate how many instructions can be issued at the same time.
1694 This is sort of a lie. The m32r can issue only 1 long insn at
1695 once, but it can issue 2 short insns. The default therefore is
1696 set at 2, but this can be overridden by the command line option
1701 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1704 /* If we have a machine that can issue a variable # of instructions
1705 per cycle, indicate how many more instructions can be issued
1706 after the current one. */
1708 m32r_variable_issue (stream, verbose, insn, how_many)
1714 int orig_odd_word_p = m32r_sched_odd_word_p;
1715 int short_p = FALSE;
1718 if (how_many > 0 && !TARGET_DEBUG)
1720 if (! m32r_is_insn (insn))
1723 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1726 m32r_sched_odd_word_p = 0;
1730 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1735 if (verbose > 7 && stream)
1737 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1738 short_p ? "short" : "long",
1740 orig_odd_word_p ? "odd" : "even",
1746 /* Cost functions. */
1748 /* Provide the costs of an addressing mode that contains ADDR.
1749 If ADDR is not a valid address, its cost is irrelevant.
1751 This function is trivial at the moment. This code doesn't live
1752 in m32r.h so it's easy to experiment. */
1755 m32r_address_cost (addr)
1756 rtx addr ATTRIBUTE_UNUSED;
1761 /* Type of function DECL.
1763 The result is cached. To reset the cache at the end of a function,
1764 call with DECL = NULL_TREE. */
1766 enum m32r_function_type
1767 m32r_compute_function_type (decl)
1771 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1772 /* Last function we were called for. */
1773 static tree last_fn = NULL_TREE;
1775 /* Resetting the cached value? */
1776 if (decl == NULL_TREE)
1778 fn_type = M32R_FUNCTION_UNKNOWN;
1779 last_fn = NULL_TREE;
1783 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1786 /* Compute function type. */
1787 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1788 ? M32R_FUNCTION_INTERRUPT
1789 : M32R_FUNCTION_NORMAL);
1794 \f/* Function prologue/epilogue handlers. */
1796 /* M32R stack frames look like:
1798 Before call After call
1799 +-----------------------+ +-----------------------+
1801 high | local variables, | | local variables, |
1802 mem | reg save area, etc. | | reg save area, etc. |
1804 +-----------------------+ +-----------------------+
1806 | arguments on stack. | | arguments on stack. |
1808 SP+0->+-----------------------+ +-----------------------+
1809 | reg parm save area, |
1810 | only created for |
1811 | variable argument |
1813 +-----------------------+
1814 | previous frame ptr |
1815 +-----------------------+
1817 | register save area |
1819 +-----------------------+
1821 +-----------------------+
1825 +-----------------------+
1827 | alloca allocations |
1829 +-----------------------+
1831 low | arguments on stack |
1833 SP+0->+-----------------------+
1836 1) The "reg parm save area" does not exist for non variable argument fns.
1837 2) The "reg parm save area" can be eliminated completely if we saved regs
1838 containing anonymous args separately but that complicates things too
1839 much (so it's not done).
1840 3) The return address is saved after the register save area so as to have as
1841 many insns as possible between the restoration of `lr' and the `jmp lr'.
1844 /* Structure to be filled in by m32r_compute_frame_size with register
1845 save masks, and offsets for the current function. */
1846 struct m32r_frame_info
1848 unsigned int total_size; /* # bytes that the entire frame takes up */
1849 unsigned int extra_size; /* # bytes of extra stuff */
1850 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1851 unsigned int args_size; /* # bytes that outgoing arguments take up */
1852 unsigned int reg_size; /* # bytes needed to store regs */
1853 unsigned int var_size; /* # bytes that variables take up */
1854 unsigned int gmask; /* mask of saved gp registers */
1855 unsigned int save_fp; /* nonzero if fp must be saved */
1856 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1857 int initialized; /* nonzero if frame size already calculated */
1860 /* Current frame information calculated by m32r_compute_frame_size. */
1861 static struct m32r_frame_info current_frame_info;
1863 /* Zero structure to initialize current_frame_info. */
1864 static struct m32r_frame_info zero_frame_info;
1866 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1867 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1869 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1870 The return address and frame pointer are treated separately.
1871 Don't consider them here. */
1872 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1873 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1874 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1876 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1877 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1879 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1880 #define LONG_INSN_SIZE 4 /* size of long instructions */
1882 /* Return the bytes needed to compute the frame pointer from the current
1885 SIZE is the size needed for local variables. */
1888 m32r_compute_frame_size (size)
1889 int size; /* # of var. bytes allocated. */
1892 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1893 unsigned int reg_size, frame_size;
1895 enum m32r_function_type fn_type;
1898 var_size = M32R_STACK_ALIGN (size);
1899 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1900 pretend_size = current_function_pretend_args_size;
1901 extra_size = FIRST_PARM_OFFSET (0);
1902 total_size = extra_size + pretend_size + args_size + var_size;
1906 /* See if this is an interrupt handler. Call used registers must be saved
1908 fn_type = m32r_compute_function_type (current_function_decl);
1909 interrupt_p = M32R_INTERRUPT_P (fn_type);
1911 /* Calculate space needed for registers. */
1913 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1915 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1917 reg_size += UNITS_PER_WORD;
1918 gmask |= 1 << regno;
1922 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1923 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1925 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1927 total_size += reg_size;
1929 /* ??? Not sure this is necessary, and I don't think the epilogue
1930 handler will do the right thing if this changes total_size. */
1931 total_size = M32R_STACK_ALIGN (total_size);
1933 frame_size = total_size - (pretend_size + reg_size);
1935 /* Save computed information. */
1936 current_frame_info.total_size = total_size;
1937 current_frame_info.extra_size = extra_size;
1938 current_frame_info.pretend_size = pretend_size;
1939 current_frame_info.var_size = var_size;
1940 current_frame_info.args_size = args_size;
1941 current_frame_info.reg_size = reg_size;
1942 current_frame_info.gmask = gmask;
1943 current_frame_info.initialized = reload_completed;
1945 /* Ok, we're done. */
1949 /* When the `length' insn attribute is used, this macro specifies the
1950 value to be assigned to the address of the first insn in a
1951 function. If not specified, 0 is used. */
1954 m32r_first_insn_address ()
1956 if (! current_frame_info.initialized)
1957 m32r_compute_frame_size (get_frame_size ());
1962 /* Expand the m32r prologue as a series of insns. */
1965 m32r_expand_prologue ()
1971 if (! current_frame_info.initialized)
1972 m32r_compute_frame_size (get_frame_size ());
1974 gmask = current_frame_info.gmask;
1976 /* These cases shouldn't happen. Catch them now. */
1977 if (current_frame_info.total_size == 0 && gmask)
1980 /* Allocate space for register arguments if this is a variadic function. */
1981 if (current_frame_info.pretend_size != 0)
1983 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1984 the wrong result on a 64-bit host. */
1985 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1986 emit_insn (gen_addsi3 (stack_pointer_rtx,
1988 GEN_INT (-pretend_size)));
1991 /* Save any registers we need to and set up fp. */
1993 if (current_frame_info.save_fp)
1994 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1996 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1998 /* Save any needed call-saved regs (and call-used if this is an
1999 interrupt handler). */
2000 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
2002 if ((gmask & (1 << regno)) != 0)
2003 emit_insn (gen_movsi_push (stack_pointer_rtx,
2004 gen_rtx_REG (Pmode, regno)));
2007 if (current_frame_info.save_lr)
2008 emit_insn (gen_movsi_push (stack_pointer_rtx,
2009 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
2011 /* Allocate the stack frame. */
2012 frame_size = (current_frame_info.total_size
2013 - (current_frame_info.pretend_size
2014 + current_frame_info.reg_size));
2016 if (frame_size == 0)
2017 ; /* nothing to do */
2018 else if (frame_size <= 32768)
2019 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2020 GEN_INT (-frame_size)));
2023 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
2024 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
2025 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2028 if (frame_pointer_needed)
2029 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2031 if (current_function_profile)
2032 emit_insn (gen_blockage ());
2036 /* Set up the stack and frame pointer (if desired) for the function.
2037 Note, if this is changed, you need to mirror the changes in
2038 m32r_compute_frame_size which calculates the prolog size. */
2041 m32r_output_function_prologue (file, size)
2045 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2047 /* If this is an interrupt handler, mark it as such. */
2048 if (M32R_INTERRUPT_P (fn_type))
2050 fprintf (file, "\t%s interrupt handler\n",
2054 if (! current_frame_info.initialized)
2055 m32r_compute_frame_size (size);
2057 /* This is only for the human reader. */
2059 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2061 current_frame_info.var_size,
2062 current_frame_info.reg_size / 4,
2063 current_frame_info.args_size,
2064 current_frame_info.extra_size);
2067 /* Do any necessary cleanup after a function to restore stack, frame,
2071 m32r_output_function_epilogue (file, size)
2073 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2076 int noepilogue = FALSE;
2078 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2080 /* This is only for the human reader. */
2081 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2083 if (!current_frame_info.initialized)
2085 total_size = current_frame_info.total_size;
2087 if (total_size == 0)
2089 rtx insn = get_last_insn ();
2091 /* If the last insn was a BARRIER, we don't have to write any code
2092 because a jump (aka return) was put there. */
2093 if (GET_CODE (insn) == NOTE)
2094 insn = prev_nonnote_insn (insn);
2095 if (insn && GET_CODE (insn) == BARRIER)
2101 unsigned int var_size = current_frame_info.var_size;
2102 unsigned int args_size = current_frame_info.args_size;
2103 unsigned int gmask = current_frame_info.gmask;
2104 int can_trust_sp_p = !current_function_calls_alloca;
2105 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2106 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2108 /* The first thing to do is point the sp at the bottom of the register
2112 unsigned int reg_offset = var_size + args_size;
2113 if (reg_offset == 0)
2114 ; /* nothing to do */
2115 else if (reg_offset < 128)
2116 fprintf (file, "\taddi %s,%s%d\n",
2117 sp_str, IMMEDIATE_PREFIX, reg_offset);
2118 else if (reg_offset < 32768)
2119 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2120 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2122 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2123 reg_names[PROLOGUE_TMP_REGNUM],
2124 IMMEDIATE_PREFIX, reg_offset,
2125 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2127 else if (frame_pointer_needed)
2129 unsigned int reg_offset = var_size + args_size;
2130 if (reg_offset == 0)
2131 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2132 else if (reg_offset < 32768)
2133 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2134 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2136 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2137 reg_names[PROLOGUE_TMP_REGNUM],
2138 IMMEDIATE_PREFIX, reg_offset,
2139 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2144 if (current_frame_info.save_lr)
2145 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2147 /* Restore any saved registers, in reverse order of course. */
2148 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2149 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2151 if ((gmask & (1L << regno)) != 0)
2152 fprintf (file, "\tpop %s\n", reg_names[regno]);
2155 if (current_frame_info.save_fp)
2156 fprintf (file, "\tpop %s\n", fp_str);
2158 /* Remove varargs area if present. */
2159 if (current_frame_info.pretend_size != 0)
2160 fprintf (file, "\taddi %s,%s%d\n",
2161 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2163 /* Emit the return instruction. */
2164 if (M32R_INTERRUPT_P (fn_type))
2165 fprintf (file, "\trte\n");
2167 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2170 #if 0 /* no longer needed */
2171 /* Ensure the function cleanly ends on a 32 bit boundary. */
2172 fprintf (file, "\t.fillinsn\n");
2175 /* Reset state info for each function. */
2176 current_frame_info = zero_frame_info;
2177 m32r_compute_function_type (NULL_TREE);
2180 /* Return non-zero if this function is known to have a null or 1 instruction
2186 if (!reload_completed)
2189 if (! current_frame_info.initialized)
2190 m32r_compute_frame_size (get_frame_size ());
2192 return current_frame_info.total_size == 0;
2198 /* Emit special PIC prologues and epilogues. */
2201 m32r_finalize_pic ()
2206 /* Nested function support. */
2208 /* Emit RTL insns to initialize the variable parts of a trampoline.
2209 FNADDR is an RTX for the address of the function's pure code.
2210 CXT is an RTX for the static chain value for the function. */
2213 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2214 rtx tramp ATTRIBUTE_UNUSED;
2215 rtx fnaddr ATTRIBUTE_UNUSED;
2216 rtx cxt ATTRIBUTE_UNUSED;
2220 /* Set the cpu type and print out other fancy things,
2221 at the top of the file. */
2224 m32r_asm_file_start (file)
2227 if (flag_verbose_asm)
2228 fprintf (file, "%s M32R/D special options: -G %d\n",
2229 ASM_COMMENT_START, g_switch_value);
2232 /* Print operand X (an rtx) in assembler syntax to file FILE.
2233 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2234 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2237 m32r_print_operand (file, x, code)
2246 /* The 's' and 'p' codes are used by output_block_move() to
2247 indicate post-increment 's'tores and 'p're-increment loads. */
2249 if (GET_CODE (x) == REG)
2250 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2252 output_operand_lossage ("invalid operand to %%s code");
2256 if (GET_CODE (x) == REG)
2257 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2259 output_operand_lossage ("invalid operand to %%p code");
2263 /* Write second word of DImode or DFmode reference,
2264 register or memory. */
2265 if (GET_CODE (x) == REG)
2266 fputs (reg_names[REGNO (x)+1], file);
2267 else if (GET_CODE (x) == MEM)
2269 fprintf (file, "@(");
2270 /* Handle possible auto-increment. Since it is pre-increment and
2271 we have already done it, we can just use an offset of four. */
2272 /* ??? This is taken from rs6000.c I think. I don't think it is
2273 currently necessary, but keep it around. */
2274 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2275 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2276 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2278 output_address (plus_constant (XEXP (x, 0), 4));
2282 output_operand_lossage ("invalid operand to %%R code");
2285 case 'H' : /* High word */
2286 case 'L' : /* Low word */
2287 if (GET_CODE (x) == REG)
2289 /* L = least significant word, H = most significant word */
2290 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2291 fputs (reg_names[REGNO (x)], file);
2293 fputs (reg_names[REGNO (x)+1], file);
2295 else if (GET_CODE (x) == CONST_INT
2296 || GET_CODE (x) == CONST_DOUBLE)
2300 split_double (x, &first, &second);
2301 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2302 code == 'L' ? INTVAL (first) : INTVAL (second));
2305 output_operand_lossage ("invalid operand to %%H/%%L code");
2313 if (GET_CODE (x) != CONST_DOUBLE
2314 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2315 fatal_insn ("bad insn for 'A'", x);
2316 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2317 REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
2318 fprintf (file, "%s", str);
2322 case 'B' : /* Bottom half */
2323 case 'T' : /* Top half */
2324 /* Output the argument to a `seth' insn (sets the Top half-word).
2325 For constants output arguments to a seth/or3 pair to set Top and
2326 Bottom halves. For symbols output arguments to a seth/add3 pair to
2327 set Top and Bottom halves. The difference exists because for
2328 constants seth/or3 is more readable but for symbols we need to use
2329 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2330 switch (GET_CODE (x))
2337 split_double (x, &first, &second);
2338 x = WORDS_BIG_ENDIAN ? second : first;
2340 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2346 ? INTVAL (x) & 0xffff
2347 : (INTVAL (x) >> 16) & 0xffff));
2353 && small_data_operand (x, VOIDmode))
2355 fputs ("sda(", file);
2356 output_addr_const (file, x);
2362 fputs (code == 'T' ? "shigh(" : "low(", file);
2363 output_addr_const (file, x);
2367 output_operand_lossage ("invalid operand to %%T/%%B code");
2374 /* Output a load/store with update indicator if appropriate. */
2375 if (GET_CODE (x) == MEM)
2377 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2378 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2382 output_operand_lossage ("invalid operand to %%U code");
2386 /* Print a constant value negated. */
2387 if (GET_CODE (x) == CONST_INT)
2388 output_addr_const (file, GEN_INT (- INTVAL (x)));
2390 output_operand_lossage ("invalid operand to %%N code");
2394 /* Print a const_int in hex. Used in comments. */
2395 if (GET_CODE (x) == CONST_INT)
2397 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2406 fputs (IMMEDIATE_PREFIX, file);
2409 #if 0 /* ??? no longer used */
2411 fputs (reg_names[SDA_REGNUM], file);
2416 /* Do nothing special. */
2421 output_operand_lossage ("invalid operand output code");
2424 switch (GET_CODE (x))
2427 fputs (reg_names[REGNO (x)], file);
2432 if (GET_CODE (addr) == PRE_INC)
2434 if (GET_CODE (XEXP (addr, 0)) != REG)
2435 fatal_insn ("pre-increment address is not a register", x);
2437 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2439 else if (GET_CODE (addr) == PRE_DEC)
2441 if (GET_CODE (XEXP (addr, 0)) != REG)
2442 fatal_insn ("pre-decrement address is not a register", x);
2444 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2446 else if (GET_CODE (addr) == POST_INC)
2448 if (GET_CODE (XEXP (addr, 0)) != REG)
2449 fatal_insn ("post-increment address is not a register", x);
2451 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2456 output_address (XEXP (x, 0));
2462 /* We handle SFmode constants here as output_addr_const doesn't. */
2463 if (GET_MODE (x) == SFmode)
2468 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2469 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2470 fprintf (file, "0x%08lx", l);
2474 /* Fall through. Let output_addr_const deal with it. */
2477 output_addr_const (file, x);
2482 /* Print a memory address as an operand to reference that memory location. */
2485 m32r_print_operand_address (file, addr)
2490 register rtx index = 0;
2493 switch (GET_CODE (addr))
2496 fputs (reg_names[REGNO (addr)], file);
2500 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2501 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2502 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2503 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2505 base = XEXP (addr, 0), index = XEXP (addr, 1);
2506 if (GET_CODE (base) == REG)
2508 /* Print the offset first (if present) to conform to the manual. */
2512 fprintf (file, "%d,", offset);
2513 fputs (reg_names[REGNO (base)], file);
2515 /* The chip doesn't support this, but left in for generality. */
2516 else if (GET_CODE (index) == REG)
2517 fprintf (file, "%s,%s",
2518 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2519 /* Not sure this can happen, but leave in for now. */
2520 else if (GET_CODE (index) == SYMBOL_REF)
2522 output_addr_const (file, index);
2524 fputs (reg_names[REGNO (base)], file);
2527 fatal_insn ("bad address", addr);
2529 else if (GET_CODE (base) == LO_SUM)
2532 || GET_CODE (XEXP (base, 0)) != REG)
2534 if (small_data_operand (XEXP (base, 1), VOIDmode))
2535 fputs ("sda(", file);
2537 fputs ("low(", file);
2538 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2540 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2543 fatal_insn ("bad address", addr);
2547 if (GET_CODE (XEXP (addr, 0)) != REG)
2548 fatal_insn ("lo_sum not of register", addr);
2549 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2550 fputs ("sda(", file);
2552 fputs ("low(", file);
2553 output_addr_const (file, XEXP (addr, 1));
2555 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2558 case PRE_INC : /* Assume SImode */
2559 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2562 case PRE_DEC : /* Assume SImode */
2563 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2566 case POST_INC : /* Assume SImode */
2567 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2571 output_addr_const (file, addr);
2576 /* Return true if the operands are the constants 0 and 1. */
2578 zero_and_one (operand1, operand2)
2583 GET_CODE (operand1) == CONST_INT
2584 && GET_CODE (operand2) == CONST_INT
2585 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2586 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2589 /* Return non-zero if the operand is suitable for use in a conditional move sequence. */
2591 conditional_move_operand (operand, mode)
2593 enum machine_mode mode;
2595 /* Only defined for simple integers so far... */
2596 if (mode != SImode && mode != HImode && mode != QImode)
2599 /* At the moment we can hanndle moving registers and loading constants. */
2600 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2602 switch (GET_CODE (operand))
2608 return INT8_P (INTVAL (operand));
2612 fprintf (stderr, "Test for cond move op of type: %s\n",
2613 GET_RTX_NAME (GET_CODE (operand)));
2619 /* Return true if the code is a test of the carry bit */
2621 carry_compare_operand (op, mode)
2623 enum machine_mode mode ATTRIBUTE_UNUSED;
2627 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2630 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2634 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2638 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2644 /* Generate the correct assembler code to handle the conditional loading of a
2645 value into a register. It is known that the operands satisfy the
2646 conditional_move_operand() function above. The destination is operand[0].
2647 The condition is operand [1]. The 'true' value is operand [2] and the
2648 'false' value is operand [3]. */
2650 emit_cond_move (operands, insn)
2652 rtx insn ATTRIBUTE_UNUSED;
2654 static char buffer [100];
2655 const char * dest = reg_names [REGNO (operands [0])];
2659 /* Destination must be a register. */
2660 if (GET_CODE (operands [0]) != REG)
2662 if (! conditional_move_operand (operands [2], SImode))
2664 if (! conditional_move_operand (operands [3], SImode))
2667 /* Check to see if the test is reversed. */
2668 if (GET_CODE (operands [1]) == NE)
2670 rtx tmp = operands [2];
2671 operands [2] = operands [3];
2675 sprintf (buffer, "mvfc %s, cbr", dest);
2677 /* If the true value was '0' then we need to invert the results of the move. */
2678 if (INTVAL (operands [2]) == 0)
2679 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2685 /* Returns true if the registers contained in the two
2686 rtl expressions are different. */
2688 m32r_not_same_reg (a, b)
2695 while (GET_CODE (a) == SUBREG)
2698 if (GET_CODE (a) == REG)
2701 while (GET_CODE (b) == SUBREG)
2704 if (GET_CODE (b) == REG)
2707 return reg_a != reg_b;
2711 /* Use a library function to move some bytes. */
2713 block_move_call (dest_reg, src_reg, bytes_rtx)
2718 /* We want to pass the size as Pmode, which will normally be SImode
2719 but will be DImode if we are using 64 bit longs and pointers. */
2720 if (GET_MODE (bytes_rtx) != VOIDmode
2721 && GET_MODE (bytes_rtx) != Pmode)
2722 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2724 #ifdef TARGET_MEM_FUNCTIONS
2725 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2726 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2727 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2728 TREE_UNSIGNED (sizetype)),
2729 TYPE_MODE (sizetype));
2731 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2732 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2733 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2734 TREE_UNSIGNED (integer_type_node)),
2735 TYPE_MODE (integer_type_node));
2739 /* The maximum number of bytes to copy using pairs of load/store instructions.
2740 If a block is larger than this then a loop will be generated to copy
2741 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2742 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2743 string copy in it. */
2744 #define MAX_MOVE_BYTES 32
2746 /* Expand string/block move operations.
2748 operands[0] is the pointer to the destination.
2749 operands[1] is the pointer to the source.
2750 operands[2] is the number of bytes to move.
2751 operands[3] is the alignment. */
2754 m32r_expand_block_move (operands)
2757 rtx orig_dst = operands[0];
2758 rtx orig_src = operands[1];
2759 rtx bytes_rtx = operands[2];
2760 rtx align_rtx = operands[3];
2761 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2762 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2763 int align = INTVAL (align_rtx);
2768 if (constp && bytes <= 0)
2771 /* Move the address into scratch registers. */
2772 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2773 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2775 if (align > UNITS_PER_WORD)
2776 align = UNITS_PER_WORD;
2778 /* If we prefer size over speed, always use a function call.
2779 If we do not know the size, use a function call.
2780 If the blocks are not word aligned, use a function call. */
2781 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2783 block_move_call (dst_reg, src_reg, bytes_rtx);
2787 leftover = bytes % MAX_MOVE_BYTES;
2790 /* If necessary, generate a loop to handle the bulk of the copy. */
2793 rtx label = NULL_RTX;
2794 rtx final_src = NULL_RTX;
2795 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2796 rtx rounded_total = GEN_INT (bytes);
2798 /* If we are going to have to perform this loop more than
2799 once, then generate a label and compute the address the
2800 source register will contain upon completion of the final
2802 if (bytes > MAX_MOVE_BYTES)
2804 final_src = gen_reg_rtx (Pmode);
2807 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2810 emit_insn (gen_movsi (final_src, rounded_total));
2811 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2814 label = gen_label_rtx ();
2818 /* It is known that output_block_move() will update src_reg to point
2819 to the word after the end of the source block, and dst_reg to point
2820 to the last word of the destination block, provided that the block
2821 is MAX_MOVE_BYTES long. */
2822 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2823 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2825 if (bytes > MAX_MOVE_BYTES)
2827 emit_insn (gen_cmpsi (src_reg, final_src));
2828 emit_jump_insn (gen_bne (label));
2833 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2837 /* Emit load/stores for a small constant word aligned block_move.
2839 operands[0] is the memory address of the destination.
2840 operands[1] is the memory address of the source.
2841 operands[2] is the number of bytes to move.
2842 operands[3] is a temp register.
2843 operands[4] is a temp register. */
2846 m32r_output_block_move (insn, operands)
2847 rtx insn ATTRIBUTE_UNUSED;
2850 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2854 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2857 /* We do not have a post-increment store available, so the first set of
2858 stores are done without any increment, then the remaining ones can use
2859 the pre-increment addressing mode.
2861 Note: expand_block_move() also relies upon this behaviour when building
2862 loops to copy large blocks. */
2871 output_asm_insn ("ld\t%3, %p1", operands);
2872 output_asm_insn ("ld\t%4, %p1", operands);
2873 output_asm_insn ("st\t%3, @%0", operands);
2874 output_asm_insn ("st\t%4, %s0", operands);
2878 output_asm_insn ("ld\t%3, %p1", operands);
2879 output_asm_insn ("ld\t%4, %p1", operands);
2880 output_asm_insn ("st\t%3, %s0", operands);
2881 output_asm_insn ("st\t%4, %s0", operands);
2886 else if (bytes >= 4)
2891 output_asm_insn ("ld\t%3, %p1", operands);
2894 output_asm_insn ("ld\t%4, %p1", operands);
2897 output_asm_insn ("st\t%3, @%0", operands);
2899 output_asm_insn ("st\t%3, %s0", operands);
2905 /* Get the entire next word, even though we do not want all of it.
2906 The saves us from doing several smaller loads, and we assume that
2907 we cannot cause a page fault when at least part of the word is in
2908 valid memory [since we don't get called if things aren't properly
2910 int dst_offset = first_time ? 0 : 4;
2914 /* If got_extra is true then we have already loaded
2915 the next word as part of loading and storing the previous word. */
2917 output_asm_insn ("ld\t%4, @%1", operands);
2923 output_asm_insn ("sra3\t%3, %4, #16", operands);
2924 my_operands[0] = operands[3];
2925 my_operands[1] = GEN_INT (dst_offset);
2926 my_operands[2] = operands[0];
2927 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2929 /* If there is a byte left to store then increment the
2930 destination address and shift the contents of the source
2931 register down by 8 bits. We could not do the address
2932 increment in the store half word instruction, because it does
2933 not have an auto increment mode. */
2934 if (bytes > 0) /* assert (bytes == 1) */
2945 my_operands[0] = operands[4];
2946 my_operands[1] = GEN_INT (last_shift);
2947 output_asm_insn ("srai\t%0, #%1", my_operands);
2948 my_operands[0] = operands[4];
2949 my_operands[1] = GEN_INT (dst_offset);
2950 my_operands[2] = operands[0];
2951 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2961 /* Return true if op is an integer constant, less than or equal to
2964 m32r_block_immediate_operand (op, mode)
2966 enum machine_mode mode ATTRIBUTE_UNUSED;
2968 if (GET_CODE (op) != CONST_INT
2969 || INTVAL (op) > MAX_MOVE_BYTES
2970 || INTVAL (op) <= 0)