1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
41 #include "target-def.h"
43 /* Save the operands last given to a compare for use when we
44 generate a scc or bcc insn. */
45 rtx m32r_compare_op0, m32r_compare_op1;
47 /* Array of valid operand punctuation characters. */
48 char m32r_punct_chars[256];
50 /* Selected code model. */
51 const char * m32r_model_string = M32R_MODEL_DEFAULT;
52 enum m32r_model m32r_model;
54 /* Selected SDA support. */
55 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
56 enum m32r_sdata m32r_sdata;
58 /* Scheduler support */
59 static int m32r_sched_odd_word_p;
61 /* Forward declaration. */
62 static void init_reg_tables PARAMS ((void));
63 static void block_move_call PARAMS ((rtx, rtx, rtx));
64 static int m32r_is_insn PARAMS ((rtx));
65 const struct attribute_spec m32r_attribute_table[];
66 static tree m32r_handle_model_attribute PARAMS ((tree *, tree, tree, int, bool *));
67 static void m32r_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
68 static void m32r_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
70 static int m32r_adjust_cost PARAMS ((rtx, rtx, rtx, int));
71 static int m32r_adjust_priority PARAMS ((rtx, int));
72 static void m32r_sched_init PARAMS ((FILE *, int, int));
73 static int m32r_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
74 static int m32r_variable_issue PARAMS ((FILE *, int, rtx, int));
75 static int m32r_issue_rate PARAMS ((void));
77 static void m32r_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT));
78 static void m32r_encode_section_info PARAMS ((tree, int));
79 static const char *m32r_strip_name_encoding PARAMS ((const char *));
80 static void init_idents PARAMS ((void));
82 /* Initialize the GCC target structure. */
83 #undef TARGET_ATTRIBUTE_TABLE
84 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
86 #undef TARGET_ASM_ALIGNED_HI_OP
87 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
88 #undef TARGET_ASM_ALIGNED_SI_OP
89 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
91 #undef TARGET_ASM_FUNCTION_PROLOGUE
92 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
93 #undef TARGET_ASM_FUNCTION_EPILOGUE
94 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
96 #undef TARGET_SCHED_ADJUST_COST
97 #define TARGET_SCHED_ADJUST_COST m32r_adjust_cost
98 #undef TARGET_SCHED_ADJUST_PRIORITY
99 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
100 #undef TARGET_SCHED_ISSUE_RATE
101 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
102 #undef TARGET_SCHED_VARIABLE_ISSUE
103 #define TARGET_SCHED_VARIABLE_ISSUE m32r_variable_issue
104 #undef TARGET_SCHED_INIT
105 #define TARGET_SCHED_INIT m32r_sched_init
106 #undef TARGET_SCHED_REORDER
107 #define TARGET_SCHED_REORDER m32r_sched_reorder
109 #undef TARGET_ENCODE_SECTION_INFO
110 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
111 #undef TARGET_STRIP_NAME_ENCODING
112 #define TARGET_STRIP_NAME_ENCODING m32r_strip_name_encoding
114 struct gcc_target targetm = TARGET_INITIALIZER;
116 /* Called by OVERRIDE_OPTIONS to initialize various things. */
123 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
124 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
125 m32r_punct_chars['#'] = 1;
126 m32r_punct_chars['@'] = 1; /* ??? no longer used */
128 /* Provide default value if not specified. */
130 g_switch_value = SDATA_DEFAULT_SIZE;
132 if (strcmp (m32r_model_string, "small") == 0)
133 m32r_model = M32R_MODEL_SMALL;
134 else if (strcmp (m32r_model_string, "medium") == 0)
135 m32r_model = M32R_MODEL_MEDIUM;
136 else if (strcmp (m32r_model_string, "large") == 0)
137 m32r_model = M32R_MODEL_LARGE;
139 error ("bad value (%s) for -mmodel switch", m32r_model_string);
141 if (strcmp (m32r_sdata_string, "none") == 0)
142 m32r_sdata = M32R_SDATA_NONE;
143 else if (strcmp (m32r_sdata_string, "sdata") == 0)
144 m32r_sdata = M32R_SDATA_SDATA;
145 else if (strcmp (m32r_sdata_string, "use") == 0)
146 m32r_sdata = M32R_SDATA_USE;
148 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
151 /* Vectors to keep interesting information about registers where it can easily
152 be got. We use to use the actual mode value as the bit number, but there
153 is (or may be) more than 32 modes now. Instead we use two tables: one
154 indexed by hard register number, and one indexed by mode. */
156 /* The purpose of m32r_mode_class is to shrink the range of modes so that
157 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
158 mapped into one m32r_mode_class mode. */
163 S_MODE, D_MODE, T_MODE, O_MODE,
164 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
167 /* Modes for condition codes. */
168 #define C_MODES (1 << (int) C_MODE)
170 /* Modes for single-word and smaller quantities. */
171 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
173 /* Modes for double-word and smaller quantities. */
174 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
176 /* Modes for quad-word and smaller quantities. */
177 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
179 /* Modes for accumulators. */
180 #define A_MODES (1 << (int) A_MODE)
182 /* Value is 1 if register/mode pair is acceptable on arc. */
184 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
186 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
187 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
188 S_MODES, C_MODES, A_MODES, A_MODES
191 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
193 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
200 for (i = 0; i < NUM_MACHINE_MODES; i++)
202 switch (GET_MODE_CLASS (i))
205 case MODE_PARTIAL_INT:
206 case MODE_COMPLEX_INT:
207 if (GET_MODE_SIZE (i) <= 4)
208 m32r_mode_class[i] = 1 << (int) S_MODE;
209 else if (GET_MODE_SIZE (i) == 8)
210 m32r_mode_class[i] = 1 << (int) D_MODE;
211 else if (GET_MODE_SIZE (i) == 16)
212 m32r_mode_class[i] = 1 << (int) T_MODE;
213 else if (GET_MODE_SIZE (i) == 32)
214 m32r_mode_class[i] = 1 << (int) O_MODE;
216 m32r_mode_class[i] = 0;
219 case MODE_COMPLEX_FLOAT:
220 if (GET_MODE_SIZE (i) <= 4)
221 m32r_mode_class[i] = 1 << (int) SF_MODE;
222 else if (GET_MODE_SIZE (i) == 8)
223 m32r_mode_class[i] = 1 << (int) DF_MODE;
224 else if (GET_MODE_SIZE (i) == 16)
225 m32r_mode_class[i] = 1 << (int) TF_MODE;
226 else if (GET_MODE_SIZE (i) == 32)
227 m32r_mode_class[i] = 1 << (int) OF_MODE;
229 m32r_mode_class[i] = 0;
233 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
234 we must explicitly check for them here. */
235 if (i == (int) CCmode)
236 m32r_mode_class[i] = 1 << (int) C_MODE;
238 m32r_mode_class[i] = 0;
243 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
246 m32r_regno_reg_class[i] = GENERAL_REGS;
247 else if (i == ARG_POINTER_REGNUM)
248 m32r_regno_reg_class[i] = GENERAL_REGS;
250 m32r_regno_reg_class[i] = NO_REGS;
254 /* M32R specific attribute support.
256 interrupt - for interrupt functions
258 model - select code model used to access object
260 small: addresses use 24 bits, use bl to make calls
261 medium: addresses use 32 bits, use bl to make calls
262 large: addresses use 32 bits, use seth/add3/jl to make calls
264 Grep for MODEL in m32r.h for more info.
267 static tree small_ident1;
268 static tree small_ident2;
269 static tree medium_ident1;
270 static tree medium_ident2;
271 static tree large_ident1;
272 static tree large_ident2;
277 if (small_ident1 == 0)
279 small_ident1 = get_identifier ("small");
280 small_ident2 = get_identifier ("__small__");
281 medium_ident1 = get_identifier ("medium");
282 medium_ident2 = get_identifier ("__medium__");
283 large_ident1 = get_identifier ("large");
284 large_ident2 = get_identifier ("__large__");
288 const struct attribute_spec m32r_attribute_table[] =
290 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
291 { "interrupt", 0, 0, true, false, false, NULL },
292 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
293 { NULL, 0, 0, false, false, false, NULL }
297 /* Handle an "model" attribute; arguments as in
298 struct attribute_spec.handler. */
300 m32r_handle_model_attribute (node, name, args, flags, no_add_attrs)
301 tree *node ATTRIBUTE_UNUSED;
304 int flags ATTRIBUTE_UNUSED;
310 arg = TREE_VALUE (args);
312 if (arg != small_ident1
313 && arg != small_ident2
314 && arg != medium_ident1
315 && arg != medium_ident2
316 && arg != large_ident1
317 && arg != large_ident2)
319 warning ("invalid argument of `%s' attribute",
320 IDENTIFIER_POINTER (name));
321 *no_add_attrs = true;
327 /* A C statement or statements to switch to the appropriate
328 section for output of DECL. DECL is either a `VAR_DECL' node
329 or a constant of some sort. RELOC indicates whether forming
330 the initial value of DECL requires link-time relocations. */
333 m32r_select_section (decl, reloc, align)
336 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
338 if (TREE_CODE (decl) == STRING_CST)
340 if (! flag_writable_strings)
341 readonly_data_section ();
345 else if (TREE_CODE (decl) == VAR_DECL)
347 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
349 else if ((flag_pic && reloc)
350 || !TREE_READONLY (decl)
351 || TREE_SIDE_EFFECTS (decl)
352 || !DECL_INITIAL (decl)
353 || (DECL_INITIAL (decl) != error_mark_node
354 && !TREE_CONSTANT (DECL_INITIAL (decl))))
357 readonly_data_section ();
360 readonly_data_section ();
363 /* Encode section information of DECL, which is either a VAR_DECL,
364 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
366 For the M32R we want to record:
368 - whether the object lives in .sdata/.sbss.
369 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
371 - what code model should be used to access the object
372 small: recorded with no flag - for space efficiency since they'll
374 medium: prefixed with MEDIUM_FLAG_CHAR
375 large: prefixed with LARGE_FLAG_CHAR
379 m32r_encode_section_info (decl, first)
389 switch (TREE_CODE (decl))
393 model = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
397 /* ??? document all others that can appear here */
402 /* Only mark the object as being small data area addressable if
403 it hasn't been explicitly marked with a code model.
405 The user can explicitly put an object in the small data area with the
406 section attribute. If the object is in sdata/sbss and marked with a
407 code model do both [put the object in .sdata and mark it as being
408 addressed with a specific code model - don't mark it as being addressed
409 with an SDA reloc though]. This is ok and might be useful at times. If
410 the object doesn't fit the linker will give an error. */
414 if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
415 && DECL_SECTION_NAME (decl) != NULL_TREE)
417 char *name = (char *) TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
418 if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
420 #if 0 /* ??? There's no reason to disallow this, is there? */
421 if (TREE_READONLY (decl))
422 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
424 prefix = SDATA_FLAG_CHAR;
429 if (TREE_CODE (decl) == VAR_DECL
430 && ! TREE_READONLY (decl)
431 && ! TARGET_SDATA_NONE)
433 int size = int_size_in_bytes (TREE_TYPE (decl));
435 if (size > 0 && size <= g_switch_value)
436 prefix = SDATA_FLAG_CHAR;
441 /* If data area not decided yet, check for a code model. */
450 id = TREE_VALUE (TREE_VALUE (model));
452 if (id == small_ident1 || id == small_ident2)
453 ; /* don't mark the symbol specially */
454 else if (id == medium_ident1 || id == medium_ident2)
455 prefix = MEDIUM_FLAG_CHAR;
456 else if (id == large_ident1 || id == large_ident2)
457 prefix = LARGE_FLAG_CHAR;
459 abort (); /* shouldn't happen */
463 if (TARGET_MODEL_SMALL)
464 ; /* don't mark the symbol specially */
465 else if (TARGET_MODEL_MEDIUM)
466 prefix = MEDIUM_FLAG_CHAR;
467 else if (TARGET_MODEL_LARGE)
468 prefix = LARGE_FLAG_CHAR;
470 abort (); /* shouldn't happen */
476 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
477 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
478 const char *str = XSTR (XEXP (rtl, 0), 0);
479 int len = strlen (str);
480 char *newstr = ggc_alloc (len + 2);
482 strcpy (newstr + 1, str);
484 /* Note - we cannot leave the string in the ggc_alloc'ed space.
485 It must reside in the stringtable's domain. */
486 newstr = (char *) ggc_alloc_string (newstr, len + 2);
488 XSTR (XEXP (rtl, 0), 0) = newstr;
492 /* Undo the effects of the above. */
495 m32r_strip_name_encoding (str)
498 str += ENCODED_NAME_P (str);
503 /* Do anything needed before RTL is emitted for each function. */
506 m32r_init_expanders ()
508 /* ??? At one point there was code here. The function is left in
509 to make it easy to experiment. */
512 /* Acceptable arguments to the call insn. */
515 call_address_operand (op, mode)
517 enum machine_mode mode;
519 return symbolic_operand (op, mode);
521 /* Constants and values in registers are not OK, because
522 the m32r BL instruction can only support PC relative branching. */
526 call_operand (op, mode)
528 enum machine_mode mode;
530 if (GET_CODE (op) != MEM)
533 return call_address_operand (op, mode);
536 /* Returns 1 if OP is a symbol reference. */
539 symbolic_operand (op, mode)
541 enum machine_mode mode ATTRIBUTE_UNUSED;
543 switch (GET_CODE (op))
555 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
558 small_data_operand (op, mode)
560 enum machine_mode mode ATTRIBUTE_UNUSED;
562 if (! TARGET_SDATA_USE)
565 if (GET_CODE (op) == SYMBOL_REF)
566 return SDATA_NAME_P (XSTR (op, 0));
568 if (GET_CODE (op) == CONST
569 && GET_CODE (XEXP (op, 0)) == PLUS
570 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
571 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
572 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
573 return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
578 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
581 addr24_operand (op, mode)
583 enum machine_mode mode ATTRIBUTE_UNUSED;
585 if (GET_CODE (op) == LABEL_REF)
586 return TARGET_ADDR24;
588 if (GET_CODE (op) == SYMBOL_REF)
589 return (SMALL_NAME_P (XSTR (op, 0))
591 && (CONSTANT_POOL_ADDRESS_P (op)
592 || LIT_NAME_P (XSTR (op, 0)))));
594 if (GET_CODE (op) == CONST
595 && GET_CODE (XEXP (op, 0)) == PLUS
596 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
597 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
598 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
600 rtx sym = XEXP (XEXP (op, 0), 0);
601 return (SMALL_NAME_P (XSTR (sym, 0))
603 && (CONSTANT_POOL_ADDRESS_P (op)
604 || LIT_NAME_P (XSTR (op, 0)))));
610 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
613 addr32_operand (op, mode)
615 enum machine_mode mode;
617 if (GET_CODE (op) == LABEL_REF)
618 return TARGET_ADDR32;
620 if (GET_CODE (op) == SYMBOL_REF)
621 return (! addr24_operand (op, mode)
622 && ! small_data_operand (op, mode));
624 if (GET_CODE (op) == CONST
625 && GET_CODE (XEXP (op, 0)) == PLUS
626 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
627 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
629 return (! addr24_operand (op, mode)
630 && ! small_data_operand (op, mode));
636 /* Return 1 if OP is a function that can be called with the `bl' insn. */
639 call26_operand (op, mode)
641 enum machine_mode mode ATTRIBUTE_UNUSED;
643 if (GET_CODE (op) == SYMBOL_REF)
644 return ! LARGE_NAME_P (XSTR (op, 0));
646 return TARGET_CALL26;
649 /* Returns 1 if OP is an acceptable operand for seth/add3. */
652 seth_add3_operand (op, mode)
654 enum machine_mode mode ATTRIBUTE_UNUSED;
656 if (GET_CODE (op) == SYMBOL_REF
657 || GET_CODE (op) == LABEL_REF)
660 if (GET_CODE (op) == CONST
661 && GET_CODE (XEXP (op, 0)) == PLUS
662 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
663 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
664 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
670 /* Return true if OP is a signed 8 bit immediate value. */
673 int8_operand (op, mode)
675 enum machine_mode mode ATTRIBUTE_UNUSED;
677 if (GET_CODE (op) != CONST_INT)
679 return INT8_P (INTVAL (op));
682 /* Return true if OP is a signed 16 bit immediate value
683 useful in comparisons. */
686 cmp_int16_operand (op, mode)
688 enum machine_mode mode ATTRIBUTE_UNUSED;
690 if (GET_CODE (op) != CONST_INT)
692 return CMP_INT16_P (INTVAL (op));
695 /* Return true if OP is an unsigned 16 bit immediate value. */
698 uint16_operand (op, mode)
700 enum machine_mode mode ATTRIBUTE_UNUSED;
702 if (GET_CODE (op) != CONST_INT)
704 return UINT16_P (INTVAL (op));
707 /* Return true if OP is a register or signed 16 bit value. */
710 reg_or_int16_operand (op, mode)
712 enum machine_mode mode;
714 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
715 return register_operand (op, mode);
716 if (GET_CODE (op) != CONST_INT)
718 return INT16_P (INTVAL (op));
721 /* Return true if OP is a register or an unsigned 16 bit value. */
724 reg_or_uint16_operand (op, mode)
726 enum machine_mode mode;
728 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
729 return register_operand (op, mode);
730 if (GET_CODE (op) != CONST_INT)
732 return UINT16_P (INTVAL (op));
735 /* Return true if OP is a register or an integer value that can be
736 used is SEQ/SNE. We can use either XOR of the value or ADD of
737 the negative of the value for the constant. Don't allow 0,
738 because that is special cased. */
741 reg_or_eq_int16_operand (op, mode)
743 enum machine_mode mode;
747 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
748 return register_operand (op, mode);
750 if (GET_CODE (op) != CONST_INT)
754 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
757 /* Return true if OP is a register or signed 16 bit value for compares. */
760 reg_or_cmp_int16_operand (op, mode)
762 enum machine_mode mode;
764 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
765 return register_operand (op, mode);
766 if (GET_CODE (op) != CONST_INT)
768 return CMP_INT16_P (INTVAL (op));
771 /* Return true if OP is a register or the constant 0. */
774 reg_or_zero_operand (op, mode)
776 enum machine_mode mode;
778 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
779 return register_operand (op, mode);
781 if (GET_CODE (op) != CONST_INT)
784 return INTVAL (op) == 0;
787 /* Return true if OP is a const_int requiring two instructions to load. */
790 two_insn_const_operand (op, mode)
792 enum machine_mode mode ATTRIBUTE_UNUSED;
794 if (GET_CODE (op) != CONST_INT)
796 if (INT16_P (INTVAL (op))
797 || UINT24_P (INTVAL (op))
798 || UPPER16_P (INTVAL (op)))
803 /* Return true if OP is an acceptable argument for a single word
807 move_src_operand (op, mode)
809 enum machine_mode mode;
811 switch (GET_CODE (op))
815 return addr24_operand (op, mode);
817 /* ??? We allow more cse opportunities if we only allow constants
818 loadable with one insn, and split the rest into two. The instances
819 where this would help should be rare and the current way is
821 if (HOST_BITS_PER_WIDE_INT > 32)
823 HOST_WIDE_INT rest = INTVAL (op) >> 31;
824 return (rest == 0 || rest == -1);
829 return TARGET_ADDR24;
833 else if (mode == SImode)
835 /* Large unsigned constants are represented as const_double's. */
836 unsigned HOST_WIDE_INT low, high;
838 low = CONST_DOUBLE_LOW (op);
839 high = CONST_DOUBLE_HIGH (op);
840 return high == 0 && low <= 0xffffffff;
845 return register_operand (op, mode);
847 /* (subreg (mem ...) ...) can occur here if the inner part was once a
848 pseudo-reg and is now a stack slot. */
849 if (GET_CODE (SUBREG_REG (op)) == MEM)
850 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
852 return register_operand (op, mode);
854 if (GET_CODE (XEXP (op, 0)) == PRE_INC
855 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
856 return 0; /* loads can't do pre-{inc,dec} */
857 return address_operand (XEXP (op, 0), mode);
863 /* Return true if OP is an acceptable argument for a double word
867 move_double_src_operand (op, mode)
869 enum machine_mode mode;
871 switch (GET_CODE (op))
877 return register_operand (op, mode);
879 /* (subreg (mem ...) ...) can occur here if the inner part was once a
880 pseudo-reg and is now a stack slot. */
881 if (GET_CODE (SUBREG_REG (op)) == MEM)
882 return move_double_src_operand (SUBREG_REG (op), mode);
884 return register_operand (op, mode);
886 /* Disallow auto inc/dec for now. */
887 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
888 || GET_CODE (XEXP (op, 0)) == PRE_INC)
890 return address_operand (XEXP (op, 0), mode);
896 /* Return true if OP is an acceptable argument for a move destination. */
899 move_dest_operand (op, mode)
901 enum machine_mode mode;
903 switch (GET_CODE (op))
906 return register_operand (op, mode);
908 /* (subreg (mem ...) ...) can occur here if the inner part was once a
909 pseudo-reg and is now a stack slot. */
910 if (GET_CODE (SUBREG_REG (op)) == MEM)
911 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
913 return register_operand (op, mode);
915 if (GET_CODE (XEXP (op, 0)) == POST_INC)
916 return 0; /* stores can't do post inc */
917 return address_operand (XEXP (op, 0), mode);
923 /* Return 1 if OP is a DImode const we want to handle inline.
924 This must match the code in the movdi pattern.
925 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
931 rtx high_rtx, low_rtx;
932 HOST_WIDE_INT high, low;
934 split_double (op, &high_rtx, &low_rtx);
935 high = INTVAL (high_rtx);
936 low = INTVAL (low_rtx);
937 /* Pick constants loadable with 2 16 bit `ldi' insns. */
938 if (high >= -128 && high <= 127
939 && low >= -128 && low <= 127)
944 /* Return 1 if OP is a DFmode const we want to handle inline.
945 This must match the code in the movdf pattern.
946 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
955 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
956 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
957 if (l[0] == 0 && l[1] == 0)
959 if ((l[0] & 0xffff) == 0 && l[1] == 0)
964 /* Return 1 if OP is an EQ or NE comparison operator. */
967 eqne_comparison_operator (op, mode)
969 enum machine_mode mode ATTRIBUTE_UNUSED;
971 enum rtx_code code = GET_CODE (op);
973 if (GET_RTX_CLASS (code) != '<')
975 return (code == EQ || code == NE);
978 /* Return 1 if OP is a signed comparison operator. */
981 signed_comparison_operator (op, mode)
983 enum machine_mode mode ATTRIBUTE_UNUSED;
985 enum rtx_code code = GET_CODE (op);
987 if (GET_RTX_CLASS (code) != '<')
989 return (code == EQ || code == NE
990 || code == LT || code == LE || code == GT || code == GE);
993 /* Return 1 if OP is (mem (reg ...)).
994 This is used in insn length calcs. */
997 memreg_operand (op, mode)
999 enum machine_mode mode ATTRIBUTE_UNUSED;
1001 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
1004 /* Return true if OP is an acceptable input argument for a zero/sign extend
1008 extend_operand (op, mode)
1010 enum machine_mode mode;
1014 switch (GET_CODE (op))
1018 return register_operand (op, mode);
1021 addr = XEXP (op, 0);
1022 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1023 return 0; /* loads can't do pre inc/pre dec */
1025 return address_operand (addr, mode);
1032 /* Return non-zero if the operand is an insn that is a small insn.
1033 Allow const_int 0 as well, which is a placeholder for NOP slots. */
1036 small_insn_p (op, mode)
1038 enum machine_mode mode ATTRIBUTE_UNUSED;
1040 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1046 return get_attr_length (op) == 2;
1049 /* Return non-zero if the operand is an insn that is a large insn. */
1052 large_insn_p (op, mode)
1054 enum machine_mode mode ATTRIBUTE_UNUSED;
1059 return get_attr_length (op) != 2;
1065 /* X and Y are two things to compare using CODE. Emit the compare insn and
1066 return the rtx for compare [arg0 of the if_then_else].
1067 If need_compare is true then the comparison insn must be generated, rather
1068 than being susummed into the following branch instruction. */
1071 gen_compare (code, x, y, need_compare)
1076 enum rtx_code compare_code, branch_code;
1077 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
1082 case EQ: compare_code = EQ; branch_code = NE; break;
1083 case NE: compare_code = EQ; branch_code = EQ; break;
1084 case LT: compare_code = LT; branch_code = NE; break;
1085 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1086 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1087 case GE: compare_code = LT; branch_code = EQ; break;
1088 case LTU: compare_code = LTU; branch_code = NE; break;
1089 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1090 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1091 case GEU: compare_code = LTU; branch_code = EQ; break;
1099 switch (compare_code)
1102 if (GET_CODE (y) == CONST_INT
1103 && CMP_INT16_P (INTVAL (y)) /* reg equal to small const. */
1106 rtx tmp = gen_reg_rtx (SImode);
1108 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1112 else if (CONSTANT_P (y)) /* reg equal to const. */
1114 rtx tmp = force_reg (GET_MODE (x), y);
1118 if (register_operand (y, SImode) /* reg equal to reg. */
1119 || y == const0_rtx) /* req equal to zero. */
1121 emit_insn (gen_cmp_eqsi_insn (x, y));
1123 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1128 if (register_operand (y, SImode)
1129 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1131 rtx tmp = gen_reg_rtx (SImode); /* reg compared to reg. */
1136 emit_insn (gen_cmp_ltsi_insn (x, y));
1140 if (y == const0_rtx)
1143 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1144 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1148 if (GET_CODE (y) == CONST_INT)
1149 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1151 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1152 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1156 emit_insn (gen_cmp_ltsi_insn (x, y));
1163 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1168 if (register_operand (y, SImode)
1169 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1171 rtx tmp = gen_reg_rtx (SImode); /* reg (unsigned) compared to reg. */
1176 emit_insn (gen_cmp_ltusi_insn (x, y));
1180 if (y == const0_rtx)
1183 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1184 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1188 if (GET_CODE (y) == CONST_INT)
1189 tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1191 emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1192 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1196 emit_insn (gen_cmp_ltusi_insn (x, y));
1203 return gen_rtx (code, CCmode, cc_reg, const0_rtx);
1213 /* reg/reg equal comparison */
1214 if (compare_code == EQ
1215 && register_operand (y, SImode))
1216 return gen_rtx (code, CCmode, x, y);
1218 /* reg/zero signed comparison */
1219 if ((compare_code == EQ || compare_code == LT)
1221 return gen_rtx (code, CCmode, x, y);
1223 /* reg/smallconst equal comparison */
1224 if (compare_code == EQ
1225 && GET_CODE (y) == CONST_INT
1226 && CMP_INT16_P (INTVAL (y)))
1228 rtx tmp = gen_reg_rtx (SImode);
1229 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1230 return gen_rtx (code, CCmode, tmp, const0_rtx);
1233 /* reg/const equal comparison */
1234 if (compare_code == EQ
1237 rtx tmp = force_reg (GET_MODE (x), y);
1238 return gen_rtx (code, CCmode, x, tmp);
1245 y = force_reg (GET_MODE (x), y);
1249 (code == LTU || code == LEU || code == GTU || code == GEU)
1250 ? uint16_operand (y, GET_MODE (y))
1251 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1254 y = force_reg (GET_MODE (x), y);
1258 switch (compare_code)
1261 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1264 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1267 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1274 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
1277 /* Split a 2 word move (DI or DF) into component parts. */
1280 gen_split_move_double (operands)
1283 enum machine_mode mode = GET_MODE (operands[0]);
1284 rtx dest = operands[0];
1285 rtx src = operands[1];
1288 /* We might have (SUBREG (MEM)) here, so just get rid of the
1289 subregs to make this code simpler. It is safe to call
1290 alter_subreg any time after reload. */
1291 if (GET_CODE (dest) == SUBREG)
1292 alter_subreg (&dest);
1293 if (GET_CODE (src) == SUBREG)
1294 alter_subreg (&src);
1297 if (GET_CODE (dest) == REG)
1299 int dregno = REGNO (dest);
1302 if (GET_CODE (src) == REG)
1304 int sregno = REGNO (src);
1306 int reverse = (dregno == sregno + 1);
1308 /* We normally copy the low-numbered register first. However, if
1309 the first register operand 0 is the same as the second register of
1310 operand 1, we must copy in the opposite order. */
1311 emit_insn (gen_rtx_SET (VOIDmode,
1312 operand_subword (dest, reverse, TRUE, mode),
1313 operand_subword (src, reverse, TRUE, mode)));
1315 emit_insn (gen_rtx_SET (VOIDmode,
1316 operand_subword (dest, !reverse, TRUE, mode),
1317 operand_subword (src, !reverse, TRUE, mode)));
1320 /* reg = constant */
1321 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1324 split_double (src, &words[0], &words[1]);
1325 emit_insn (gen_rtx_SET (VOIDmode,
1326 operand_subword (dest, 0, TRUE, mode),
1329 emit_insn (gen_rtx_SET (VOIDmode,
1330 operand_subword (dest, 1, TRUE, mode),
1335 else if (GET_CODE (src) == MEM)
1337 /* If the high-address word is used in the address, we must load it
1338 last. Otherwise, load it first. */
1340 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1342 /* We used to optimize loads from single registers as
1346 if r3 were not used subsequently. However, the REG_NOTES aren't
1347 propigated correctly by the reload phase, and it can cause bad
1348 code to be generated. We could still try:
1350 ld r1,r3+; ld r2,r3; addi r3,-4
1352 which saves 2 bytes and doesn't force longword alignment. */
1353 emit_insn (gen_rtx_SET (VOIDmode,
1354 operand_subword (dest, reverse, TRUE, mode),
1355 adjust_address (src, SImode,
1356 reverse * UNITS_PER_WORD)));
1358 emit_insn (gen_rtx_SET (VOIDmode,
1359 operand_subword (dest, !reverse, TRUE, mode),
1360 adjust_address (src, SImode,
1361 !reverse * UNITS_PER_WORD)));
1369 /* We used to optimize loads from single registers as
1373 if r3 were not used subsequently. However, the REG_NOTES aren't
1374 propigated correctly by the reload phase, and it can cause bad
1375 code to be generated. We could still try:
1377 st r1,r3; st r2,+r3; addi r3,-4
1379 which saves 2 bytes and doesn't force longword alignment. */
1380 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1382 emit_insn (gen_rtx_SET (VOIDmode,
1383 adjust_address (dest, SImode, 0),
1384 operand_subword (src, 0, TRUE, mode)));
1386 emit_insn (gen_rtx_SET (VOIDmode,
1387 adjust_address (dest, SImode, UNITS_PER_WORD),
1388 operand_subword (src, 1, TRUE, mode)));
1400 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1403 function_arg_partial_nregs (cum, mode, type, named)
1404 CUMULATIVE_ARGS *cum;
1405 enum machine_mode mode;
1407 int named ATTRIBUTE_UNUSED;
1411 (((mode == BLKmode && type)
1412 ? (unsigned int) int_size_in_bytes (type)
1413 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1416 if (*cum >= M32R_MAX_PARM_REGS)
1418 else if (*cum + size > M32R_MAX_PARM_REGS)
1419 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1426 /* Do any needed setup for a variadic function. For the M32R, we must
1427 create a register parameter block, and then copy any anonymous arguments
1428 in registers to memory.
1430 CUM has not been updated for the last named argument which has type TYPE
1431 and mode MODE, and we rely on this fact. */
1434 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1435 CUMULATIVE_ARGS *cum;
1436 enum machine_mode mode;
1446 /* All BLKmode values are passed by reference. */
1447 if (mode == BLKmode)
1450 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1451 + ROUND_ADVANCE_ARG (mode, type));
1453 if (first_anon_arg < M32R_MAX_PARM_REGS)
1455 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1456 int first_reg_offset = first_anon_arg;
1457 /* Size in words to "pretend" allocate. */
1458 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1461 regblock = gen_rtx_MEM (BLKmode,
1462 plus_constant (arg_pointer_rtx,
1463 FIRST_PARM_OFFSET (0)));
1464 set_mem_alias_set (regblock, get_varargs_alias_set ());
1465 move_block_from_reg (first_reg_offset, regblock,
1466 size, size * UNITS_PER_WORD);
1468 *pretend_size = (size * UNITS_PER_WORD);
1473 /* Implement `va_arg'. */
1476 m32r_va_arg (valist, type)
1479 HOST_WIDE_INT size, rsize;
1483 size = int_size_in_bytes (type);
1484 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1488 tree type_ptr, type_ptr_ptr;
1490 /* Pass by reference. */
1492 type_ptr = build_pointer_type (type);
1493 type_ptr_ptr = build_pointer_type (type_ptr);
1495 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1496 build_int_2 (UNITS_PER_WORD, 0));
1497 TREE_SIDE_EFFECTS (t) = 1;
1498 t = build1 (NOP_EXPR, type_ptr_ptr, t);
1499 TREE_SIDE_EFFECTS (t) = 1;
1500 t = build1 (INDIRECT_REF, type_ptr, t);
1502 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1506 /* Pass by value. */
1508 if (size < UNITS_PER_WORD)
1510 /* Care for bigendian correction on the aligned address. */
1511 t = build (PLUS_EXPR, ptr_type_node, valist,
1512 build_int_2 (rsize - size, 0));
1513 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1514 addr_rtx = copy_to_reg (addr_rtx);
1517 t = build (PLUS_EXPR, va_list_type_node, valist,
1518 build_int_2 (rsize, 0));
1519 t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1520 TREE_SIDE_EFFECTS (t) = 1;
1521 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1525 t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1526 build_int_2 (rsize, 0));
1527 TREE_SIDE_EFFECTS (t) = 1;
1528 addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1536 m32r_adjust_cost (insn, link, dep_insn, cost)
1537 rtx insn ATTRIBUTE_UNUSED;
1538 rtx link ATTRIBUTE_UNUSED;
1539 rtx dep_insn ATTRIBUTE_UNUSED;
1546 /* Return true if INSN is real instruction bearing insn. */
1552 return (INSN_P (insn)
1553 && GET_CODE (PATTERN (insn)) != USE
1554 && GET_CODE (PATTERN (insn)) != CLOBBER
1555 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1558 /* Increase the priority of long instructions so that the
1559 short instructions are scheduled ahead of the long ones. */
1562 m32r_adjust_priority (insn, priority)
1566 if (m32r_is_insn (insn)
1567 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1574 /* Initialize for scheduling a group of instructions. */
1577 m32r_sched_init (stream, verbose, max_ready)
1578 FILE * stream ATTRIBUTE_UNUSED;
1579 int verbose ATTRIBUTE_UNUSED;
1580 int max_ready ATTRIBUTE_UNUSED;
1582 m32r_sched_odd_word_p = FALSE;
1586 /* Reorder the schedulers priority list if needed */
1589 m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
1594 int clock ATTRIBUTE_UNUSED;
1596 int n_ready = *n_readyp;
1599 return m32r_issue_rate ();
1606 ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1608 (m32r_sched_odd_word_p) ? "odd" : "even");
1612 rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1613 rtx * long_tail = long_head;
1614 rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1615 rtx * short_tail = short_head;
1616 rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1617 rtx * new_tail = new_head + (n_ready - 1);
1620 /* Loop through the instructions, classifing them as short/long. Try
1621 to keep 2 short together and/or 1 long. Note, the ready list is
1622 actually ordered backwards, so keep it in that manner. */
1623 for (i = n_ready-1; i >= 0; i--)
1625 rtx insn = ready[i];
1627 if (! m32r_is_insn (insn))
1629 /* Dump all current short/long insns just in case. */
1630 while (long_head != long_tail)
1631 *new_tail-- = *long_head++;
1633 while (short_head != short_tail)
1634 *new_tail-- = *short_head++;
1639 ";;\t\t::: Skipping non instruction %d\n",
1646 if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1647 *long_tail++ = insn;
1650 *short_tail++ = insn;
1654 /* If we are on an odd word, emit a single short instruction if
1656 if (m32r_sched_odd_word_p && short_head != short_tail)
1657 *new_tail-- = *short_head++;
1659 /* Now dump out all of the long instructions */
1660 while (long_head != long_tail)
1661 *new_tail-- = *long_head++;
1663 /* Now dump out all of the short instructions */
1664 while (short_head != short_tail)
1665 *new_tail-- = *short_head++;
1667 if (new_tail+1 != new_head)
1670 memcpy (ready, new_head, sizeof (rtx) * n_ready);
1674 fprintf (stream, ";;\t\t::: New ready list: ");
1675 for (i = 0; i < n_ready; i++)
1677 rtx insn = ready[i];
1679 fprintf (stream, " %d", INSN_UID (ready[i]));
1681 if (! m32r_is_insn (insn))
1682 fputs ("(?)", stream);
1684 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1685 fputs ("(l)", stream);
1688 fputs ("(s)", stream);
1691 fprintf (stream, "\n");
1694 return m32r_issue_rate ();
1697 /* Indicate how many instructions can be issued at the same time.
1698 This is sort of a lie. The m32r can issue only 1 long insn at
1699 once, but it can issue 2 short insns. The default therefore is
1700 set at 2, but this can be overridden by the command line option
1705 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1708 /* If we have a machine that can issue a variable # of instructions
1709 per cycle, indicate how many more instructions can be issued
1710 after the current one. */
1712 m32r_variable_issue (stream, verbose, insn, how_many)
1718 int orig_odd_word_p = m32r_sched_odd_word_p;
1719 int short_p = FALSE;
1722 if (how_many > 0 && !TARGET_DEBUG)
1724 if (! m32r_is_insn (insn))
1727 else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1730 m32r_sched_odd_word_p = 0;
1734 m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1739 if (verbose > 7 && stream)
1741 ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1742 short_p ? "short" : "long",
1744 orig_odd_word_p ? "odd" : "even",
1750 /* Cost functions. */
1752 /* Provide the costs of an addressing mode that contains ADDR.
1753 If ADDR is not a valid address, its cost is irrelevant.
1755 This function is trivial at the moment. This code doesn't live
1756 in m32r.h so it's easy to experiment. */
1759 m32r_address_cost (addr)
1760 rtx addr ATTRIBUTE_UNUSED;
1765 /* Type of function DECL.
1767 The result is cached. To reset the cache at the end of a function,
1768 call with DECL = NULL_TREE. */
1770 enum m32r_function_type
1771 m32r_compute_function_type (decl)
1775 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1776 /* Last function we were called for. */
1777 static tree last_fn = NULL_TREE;
1779 /* Resetting the cached value? */
1780 if (decl == NULL_TREE)
1782 fn_type = M32R_FUNCTION_UNKNOWN;
1783 last_fn = NULL_TREE;
1787 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1790 /* Compute function type. */
1791 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1792 ? M32R_FUNCTION_INTERRUPT
1793 : M32R_FUNCTION_NORMAL);
1798 \f/* Function prologue/epilogue handlers. */
1800 /* M32R stack frames look like:
1802 Before call After call
1803 +-----------------------+ +-----------------------+
1805 high | local variables, | | local variables, |
1806 mem | reg save area, etc. | | reg save area, etc. |
1808 +-----------------------+ +-----------------------+
1810 | arguments on stack. | | arguments on stack. |
1812 SP+0->+-----------------------+ +-----------------------+
1813 | reg parm save area, |
1814 | only created for |
1815 | variable argument |
1817 +-----------------------+
1818 | previous frame ptr |
1819 +-----------------------+
1821 | register save area |
1823 +-----------------------+
1825 +-----------------------+
1829 +-----------------------+
1831 | alloca allocations |
1833 +-----------------------+
1835 low | arguments on stack |
1837 SP+0->+-----------------------+
1840 1) The "reg parm save area" does not exist for non variable argument fns.
1841 2) The "reg parm save area" can be eliminated completely if we saved regs
1842 containing anonymous args separately but that complicates things too
1843 much (so it's not done).
1844 3) The return address is saved after the register save area so as to have as
1845 many insns as possible between the restoration of `lr' and the `jmp lr'.
1848 /* Structure to be filled in by m32r_compute_frame_size with register
1849 save masks, and offsets for the current function. */
1850 struct m32r_frame_info
1852 unsigned int total_size; /* # bytes that the entire frame takes up */
1853 unsigned int extra_size; /* # bytes of extra stuff */
1854 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1855 unsigned int args_size; /* # bytes that outgoing arguments take up */
1856 unsigned int reg_size; /* # bytes needed to store regs */
1857 unsigned int var_size; /* # bytes that variables take up */
1858 unsigned int gmask; /* mask of saved gp registers */
1859 unsigned int save_fp; /* nonzero if fp must be saved */
1860 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1861 int initialized; /* nonzero if frame size already calculated */
1864 /* Current frame information calculated by m32r_compute_frame_size. */
1865 static struct m32r_frame_info current_frame_info;
1867 /* Zero structure to initialize current_frame_info. */
1868 static struct m32r_frame_info zero_frame_info;
1870 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1871 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1873 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1874 The return address and frame pointer are treated separately.
1875 Don't consider them here. */
1876 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1877 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1878 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1880 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1881 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1883 #define SHORT_INSN_SIZE 2 /* size of small instructions */
1884 #define LONG_INSN_SIZE 4 /* size of long instructions */
1886 /* Return the bytes needed to compute the frame pointer from the current
1889 SIZE is the size needed for local variables. */
1892 m32r_compute_frame_size (size)
1893 int size; /* # of var. bytes allocated. */
1896 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1897 unsigned int reg_size, frame_size;
1899 enum m32r_function_type fn_type;
1902 var_size = M32R_STACK_ALIGN (size);
1903 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1904 pretend_size = current_function_pretend_args_size;
1905 extra_size = FIRST_PARM_OFFSET (0);
1906 total_size = extra_size + pretend_size + args_size + var_size;
1910 /* See if this is an interrupt handler. Call used registers must be saved
1912 fn_type = m32r_compute_function_type (current_function_decl);
1913 interrupt_p = M32R_INTERRUPT_P (fn_type);
1915 /* Calculate space needed for registers. */
1917 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1919 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1921 reg_size += UNITS_PER_WORD;
1922 gmask |= 1 << regno;
1926 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1927 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1929 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1931 total_size += reg_size;
1933 /* ??? Not sure this is necessary, and I don't think the epilogue
1934 handler will do the right thing if this changes total_size. */
1935 total_size = M32R_STACK_ALIGN (total_size);
1937 frame_size = total_size - (pretend_size + reg_size);
1939 /* Save computed information. */
1940 current_frame_info.total_size = total_size;
1941 current_frame_info.extra_size = extra_size;
1942 current_frame_info.pretend_size = pretend_size;
1943 current_frame_info.var_size = var_size;
1944 current_frame_info.args_size = args_size;
1945 current_frame_info.reg_size = reg_size;
1946 current_frame_info.gmask = gmask;
1947 current_frame_info.initialized = reload_completed;
1949 /* Ok, we're done. */
1953 /* When the `length' insn attribute is used, this macro specifies the
1954 value to be assigned to the address of the first insn in a
1955 function. If not specified, 0 is used. */
1958 m32r_first_insn_address ()
1960 if (! current_frame_info.initialized)
1961 m32r_compute_frame_size (get_frame_size ());
1966 /* Expand the m32r prologue as a series of insns. */
1969 m32r_expand_prologue ()
1975 if (! current_frame_info.initialized)
1976 m32r_compute_frame_size (get_frame_size ());
1978 gmask = current_frame_info.gmask;
1980 /* These cases shouldn't happen. Catch them now. */
1981 if (current_frame_info.total_size == 0 && gmask)
1984 /* Allocate space for register arguments if this is a variadic function. */
1985 if (current_frame_info.pretend_size != 0)
1987 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1988 the wrong result on a 64-bit host. */
1989 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1990 emit_insn (gen_addsi3 (stack_pointer_rtx,
1992 GEN_INT (-pretend_size)));
1995 /* Save any registers we need to and set up fp. */
1997 if (current_frame_info.save_fp)
1998 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
2000 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2002 /* Save any needed call-saved regs (and call-used if this is an
2003 interrupt handler). */
2004 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
2006 if ((gmask & (1 << regno)) != 0)
2007 emit_insn (gen_movsi_push (stack_pointer_rtx,
2008 gen_rtx_REG (Pmode, regno)));
2011 if (current_frame_info.save_lr)
2012 emit_insn (gen_movsi_push (stack_pointer_rtx,
2013 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
2015 /* Allocate the stack frame. */
2016 frame_size = (current_frame_info.total_size
2017 - (current_frame_info.pretend_size
2018 + current_frame_info.reg_size));
2020 if (frame_size == 0)
2021 ; /* nothing to do */
2022 else if (frame_size <= 32768)
2023 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2024 GEN_INT (-frame_size)));
2027 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
2028 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
2029 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
2032 if (frame_pointer_needed)
2033 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2035 if (current_function_profile)
2036 emit_insn (gen_blockage ());
2040 /* Set up the stack and frame pointer (if desired) for the function.
2041 Note, if this is changed, you need to mirror the changes in
2042 m32r_compute_frame_size which calculates the prolog size. */
2045 m32r_output_function_prologue (file, size)
2049 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2051 /* If this is an interrupt handler, mark it as such. */
2052 if (M32R_INTERRUPT_P (fn_type))
2054 fprintf (file, "\t%s interrupt handler\n",
2058 if (! current_frame_info.initialized)
2059 m32r_compute_frame_size (size);
2061 /* This is only for the human reader. */
2063 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2065 current_frame_info.var_size,
2066 current_frame_info.reg_size / 4,
2067 current_frame_info.args_size,
2068 current_frame_info.extra_size);
2071 /* Do any necessary cleanup after a function to restore stack, frame,
2075 m32r_output_function_epilogue (file, size)
2077 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2080 int noepilogue = FALSE;
2082 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2084 /* This is only for the human reader. */
2085 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2087 if (!current_frame_info.initialized)
2089 total_size = current_frame_info.total_size;
2091 if (total_size == 0)
2093 rtx insn = get_last_insn ();
2095 /* If the last insn was a BARRIER, we don't have to write any code
2096 because a jump (aka return) was put there. */
2097 if (GET_CODE (insn) == NOTE)
2098 insn = prev_nonnote_insn (insn);
2099 if (insn && GET_CODE (insn) == BARRIER)
2105 unsigned int var_size = current_frame_info.var_size;
2106 unsigned int args_size = current_frame_info.args_size;
2107 unsigned int gmask = current_frame_info.gmask;
2108 int can_trust_sp_p = !current_function_calls_alloca;
2109 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2110 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2112 /* The first thing to do is point the sp at the bottom of the register
2116 unsigned int reg_offset = var_size + args_size;
2117 if (reg_offset == 0)
2118 ; /* nothing to do */
2119 else if (reg_offset < 128)
2120 fprintf (file, "\taddi %s,%s%d\n",
2121 sp_str, IMMEDIATE_PREFIX, reg_offset);
2122 else if (reg_offset < 32768)
2123 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2124 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2126 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2127 reg_names[PROLOGUE_TMP_REGNUM],
2128 IMMEDIATE_PREFIX, reg_offset,
2129 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2131 else if (frame_pointer_needed)
2133 unsigned int reg_offset = var_size + args_size;
2134 if (reg_offset == 0)
2135 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2136 else if (reg_offset < 32768)
2137 fprintf (file, "\tadd3 %s,%s,%s%d\n",
2138 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2140 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2141 reg_names[PROLOGUE_TMP_REGNUM],
2142 IMMEDIATE_PREFIX, reg_offset,
2143 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2148 if (current_frame_info.save_lr)
2149 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2151 /* Restore any saved registers, in reverse order of course. */
2152 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2153 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2155 if ((gmask & (1L << regno)) != 0)
2156 fprintf (file, "\tpop %s\n", reg_names[regno]);
2159 if (current_frame_info.save_fp)
2160 fprintf (file, "\tpop %s\n", fp_str);
2162 /* Remove varargs area if present. */
2163 if (current_frame_info.pretend_size != 0)
2164 fprintf (file, "\taddi %s,%s%d\n",
2165 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2167 /* Emit the return instruction. */
2168 if (M32R_INTERRUPT_P (fn_type))
2169 fprintf (file, "\trte\n");
2171 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2174 #if 0 /* no longer needed */
2175 /* Ensure the function cleanly ends on a 32 bit boundary. */
2176 fprintf (file, "\t.fillinsn\n");
2179 /* Reset state info for each function. */
2180 current_frame_info = zero_frame_info;
2181 m32r_compute_function_type (NULL_TREE);
2184 /* Return non-zero if this function is known to have a null or 1 instruction
2190 if (!reload_completed)
2193 if (! current_frame_info.initialized)
2194 m32r_compute_frame_size (get_frame_size ());
2196 return current_frame_info.total_size == 0;
2202 /* Emit special PIC prologues and epilogues. */
2205 m32r_finalize_pic ()
2210 /* Nested function support. */
2212 /* Emit RTL insns to initialize the variable parts of a trampoline.
2213 FNADDR is an RTX for the address of the function's pure code.
2214 CXT is an RTX for the static chain value for the function. */
2217 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2218 rtx tramp ATTRIBUTE_UNUSED;
2219 rtx fnaddr ATTRIBUTE_UNUSED;
2220 rtx cxt ATTRIBUTE_UNUSED;
2224 /* Set the cpu type and print out other fancy things,
2225 at the top of the file. */
2228 m32r_asm_file_start (file)
2231 if (flag_verbose_asm)
2232 fprintf (file, "%s M32R/D special options: -G %d\n",
2233 ASM_COMMENT_START, g_switch_value);
2236 /* Print operand X (an rtx) in assembler syntax to file FILE.
2237 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2238 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2241 m32r_print_operand (file, x, code)
2250 /* The 's' and 'p' codes are used by output_block_move() to
2251 indicate post-increment 's'tores and 'p're-increment loads. */
2253 if (GET_CODE (x) == REG)
2254 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2256 output_operand_lossage ("invalid operand to %%s code");
2260 if (GET_CODE (x) == REG)
2261 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2263 output_operand_lossage ("invalid operand to %%p code");
2267 /* Write second word of DImode or DFmode reference,
2268 register or memory. */
2269 if (GET_CODE (x) == REG)
2270 fputs (reg_names[REGNO (x)+1], file);
2271 else if (GET_CODE (x) == MEM)
2273 fprintf (file, "@(");
2274 /* Handle possible auto-increment. Since it is pre-increment and
2275 we have already done it, we can just use an offset of four. */
2276 /* ??? This is taken from rs6000.c I think. I don't think it is
2277 currently necessary, but keep it around. */
2278 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2279 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2280 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2282 output_address (plus_constant (XEXP (x, 0), 4));
2286 output_operand_lossage ("invalid operand to %%R code");
2289 case 'H' : /* High word */
2290 case 'L' : /* Low word */
2291 if (GET_CODE (x) == REG)
2293 /* L = least significant word, H = most significant word */
2294 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2295 fputs (reg_names[REGNO (x)], file);
2297 fputs (reg_names[REGNO (x)+1], file);
2299 else if (GET_CODE (x) == CONST_INT
2300 || GET_CODE (x) == CONST_DOUBLE)
2304 split_double (x, &first, &second);
2305 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2306 code == 'L' ? INTVAL (first) : INTVAL (second));
2309 output_operand_lossage ("invalid operand to %%H/%%L code");
2317 if (GET_CODE (x) != CONST_DOUBLE
2318 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2319 fatal_insn ("bad insn for 'A'", x);
2320 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2321 REAL_VALUE_TO_DECIMAL (d, str, -1);
2322 fprintf (file, "%s", str);
2326 case 'B' : /* Bottom half */
2327 case 'T' : /* Top half */
2328 /* Output the argument to a `seth' insn (sets the Top half-word).
2329 For constants output arguments to a seth/or3 pair to set Top and
2330 Bottom halves. For symbols output arguments to a seth/add3 pair to
2331 set Top and Bottom halves. The difference exists because for
2332 constants seth/or3 is more readable but for symbols we need to use
2333 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2334 switch (GET_CODE (x))
2341 split_double (x, &first, &second);
2342 x = WORDS_BIG_ENDIAN ? second : first;
2344 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2350 ? INTVAL (x) & 0xffff
2351 : (INTVAL (x) >> 16) & 0xffff));
2357 && small_data_operand (x, VOIDmode))
2359 fputs ("sda(", file);
2360 output_addr_const (file, x);
2366 fputs (code == 'T' ? "shigh(" : "low(", file);
2367 output_addr_const (file, x);
2371 output_operand_lossage ("invalid operand to %%T/%%B code");
2378 /* Output a load/store with update indicator if appropriate. */
2379 if (GET_CODE (x) == MEM)
2381 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2382 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2386 output_operand_lossage ("invalid operand to %%U code");
2390 /* Print a constant value negated. */
2391 if (GET_CODE (x) == CONST_INT)
2392 output_addr_const (file, GEN_INT (- INTVAL (x)));
2394 output_operand_lossage ("invalid operand to %%N code");
2398 /* Print a const_int in hex. Used in comments. */
2399 if (GET_CODE (x) == CONST_INT)
2401 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2410 fputs (IMMEDIATE_PREFIX, file);
2413 #if 0 /* ??? no longer used */
2415 fputs (reg_names[SDA_REGNUM], file);
2420 /* Do nothing special. */
2425 output_operand_lossage ("invalid operand output code");
2428 switch (GET_CODE (x))
2431 fputs (reg_names[REGNO (x)], file);
2436 if (GET_CODE (addr) == PRE_INC)
2438 if (GET_CODE (XEXP (addr, 0)) != REG)
2439 fatal_insn ("pre-increment address is not a register", x);
2441 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2443 else if (GET_CODE (addr) == PRE_DEC)
2445 if (GET_CODE (XEXP (addr, 0)) != REG)
2446 fatal_insn ("pre-decrement address is not a register", x);
2448 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2450 else if (GET_CODE (addr) == POST_INC)
2452 if (GET_CODE (XEXP (addr, 0)) != REG)
2453 fatal_insn ("post-increment address is not a register", x);
2455 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2460 output_address (XEXP (x, 0));
2466 /* We handle SFmode constants here as output_addr_const doesn't. */
2467 if (GET_MODE (x) == SFmode)
2472 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2473 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2474 fprintf (file, "0x%08lx", l);
2478 /* Fall through. Let output_addr_const deal with it. */
2481 output_addr_const (file, x);
2486 /* Print a memory address as an operand to reference that memory location. */
2489 m32r_print_operand_address (file, addr)
2494 register rtx index = 0;
2497 switch (GET_CODE (addr))
2500 fputs (reg_names[REGNO (addr)], file);
2504 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2505 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2506 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2507 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2509 base = XEXP (addr, 0), index = XEXP (addr, 1);
2510 if (GET_CODE (base) == REG)
2512 /* Print the offset first (if present) to conform to the manual. */
2516 fprintf (file, "%d,", offset);
2517 fputs (reg_names[REGNO (base)], file);
2519 /* The chip doesn't support this, but left in for generality. */
2520 else if (GET_CODE (index) == REG)
2521 fprintf (file, "%s,%s",
2522 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2523 /* Not sure this can happen, but leave in for now. */
2524 else if (GET_CODE (index) == SYMBOL_REF)
2526 output_addr_const (file, index);
2528 fputs (reg_names[REGNO (base)], file);
2531 fatal_insn ("bad address", addr);
2533 else if (GET_CODE (base) == LO_SUM)
2536 || GET_CODE (XEXP (base, 0)) != REG)
2538 if (small_data_operand (XEXP (base, 1), VOIDmode))
2539 fputs ("sda(", file);
2541 fputs ("low(", file);
2542 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2544 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2547 fatal_insn ("bad address", addr);
2551 if (GET_CODE (XEXP (addr, 0)) != REG)
2552 fatal_insn ("lo_sum not of register", addr);
2553 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2554 fputs ("sda(", file);
2556 fputs ("low(", file);
2557 output_addr_const (file, XEXP (addr, 1));
2559 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2562 case PRE_INC : /* Assume SImode */
2563 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2566 case PRE_DEC : /* Assume SImode */
2567 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2570 case POST_INC : /* Assume SImode */
2571 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2575 output_addr_const (file, addr);
2580 /* Return true if the operands are the constants 0 and 1. */
2582 zero_and_one (operand1, operand2)
2587 GET_CODE (operand1) == CONST_INT
2588 && GET_CODE (operand2) == CONST_INT
2589 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2590 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2593 /* Return non-zero if the operand is suitable for use in a conditional move sequence. */
2595 conditional_move_operand (operand, mode)
2597 enum machine_mode mode;
2599 /* Only defined for simple integers so far... */
2600 if (mode != SImode && mode != HImode && mode != QImode)
2603 /* At the moment we can hanndle moving registers and loading constants. */
2604 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2606 switch (GET_CODE (operand))
2612 return INT8_P (INTVAL (operand));
2616 fprintf (stderr, "Test for cond move op of type: %s\n",
2617 GET_RTX_NAME (GET_CODE (operand)));
2623 /* Return true if the code is a test of the carry bit */
2625 carry_compare_operand (op, mode)
2627 enum machine_mode mode ATTRIBUTE_UNUSED;
2631 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2634 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2638 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2642 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2648 /* Generate the correct assembler code to handle the conditional loading of a
2649 value into a register. It is known that the operands satisfy the
2650 conditional_move_operand() function above. The destination is operand[0].
2651 The condition is operand [1]. The 'true' value is operand [2] and the
2652 'false' value is operand [3]. */
2654 emit_cond_move (operands, insn)
2656 rtx insn ATTRIBUTE_UNUSED;
2658 static char buffer [100];
2659 const char * dest = reg_names [REGNO (operands [0])];
2663 /* Destination must be a register. */
2664 if (GET_CODE (operands [0]) != REG)
2666 if (! conditional_move_operand (operands [2], SImode))
2668 if (! conditional_move_operand (operands [3], SImode))
2671 /* Check to see if the test is reversed. */
2672 if (GET_CODE (operands [1]) == NE)
2674 rtx tmp = operands [2];
2675 operands [2] = operands [3];
2679 sprintf (buffer, "mvfc %s, cbr", dest);
2681 /* If the true value was '0' then we need to invert the results of the move. */
2682 if (INTVAL (operands [2]) == 0)
2683 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2689 /* Returns true if the registers contained in the two
2690 rtl expressions are different. */
2692 m32r_not_same_reg (a, b)
2699 while (GET_CODE (a) == SUBREG)
2702 if (GET_CODE (a) == REG)
2705 while (GET_CODE (b) == SUBREG)
2708 if (GET_CODE (b) == REG)
2711 return reg_a != reg_b;
2715 /* Use a library function to move some bytes. */
2717 block_move_call (dest_reg, src_reg, bytes_rtx)
2722 /* We want to pass the size as Pmode, which will normally be SImode
2723 but will be DImode if we are using 64 bit longs and pointers. */
2724 if (GET_MODE (bytes_rtx) != VOIDmode
2725 && GET_MODE (bytes_rtx) != Pmode)
2726 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2728 #ifdef TARGET_MEM_FUNCTIONS
2729 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2730 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2731 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2732 TREE_UNSIGNED (sizetype)),
2733 TYPE_MODE (sizetype));
2735 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2736 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2737 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2738 TREE_UNSIGNED (integer_type_node)),
2739 TYPE_MODE (integer_type_node));
2743 /* The maximum number of bytes to copy using pairs of load/store instructions.
2744 If a block is larger than this then a loop will be generated to copy
2745 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitary choice.
2746 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2747 string copy in it. */
2748 #define MAX_MOVE_BYTES 32
2750 /* Expand string/block move operations.
2752 operands[0] is the pointer to the destination.
2753 operands[1] is the pointer to the source.
2754 operands[2] is the number of bytes to move.
2755 operands[3] is the alignment. */
2758 m32r_expand_block_move (operands)
2761 rtx orig_dst = operands[0];
2762 rtx orig_src = operands[1];
2763 rtx bytes_rtx = operands[2];
2764 rtx align_rtx = operands[3];
2765 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2766 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2767 int align = INTVAL (align_rtx);
2772 if (constp && bytes <= 0)
2775 /* Move the address into scratch registers. */
2776 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2777 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2779 if (align > UNITS_PER_WORD)
2780 align = UNITS_PER_WORD;
2782 /* If we prefer size over speed, always use a function call.
2783 If we do not know the size, use a function call.
2784 If the blocks are not word aligned, use a function call. */
2785 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2787 block_move_call (dst_reg, src_reg, bytes_rtx);
2791 leftover = bytes % MAX_MOVE_BYTES;
2794 /* If necessary, generate a loop to handle the bulk of the copy. */
2797 rtx label = NULL_RTX;
2798 rtx final_src = NULL_RTX;
2799 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2800 rtx rounded_total = GEN_INT (bytes);
2802 /* If we are going to have to perform this loop more than
2803 once, then generate a label and compute the address the
2804 source register will contain upon completion of the final
2806 if (bytes > MAX_MOVE_BYTES)
2808 final_src = gen_reg_rtx (Pmode);
2811 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2814 emit_insn (gen_movsi (final_src, rounded_total));
2815 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2818 label = gen_label_rtx ();
2822 /* It is known that output_block_move() will update src_reg to point
2823 to the word after the end of the source block, and dst_reg to point
2824 to the last word of the destination block, provided that the block
2825 is MAX_MOVE_BYTES long. */
2826 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2827 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2829 if (bytes > MAX_MOVE_BYTES)
2831 emit_insn (gen_cmpsi (src_reg, final_src));
2832 emit_jump_insn (gen_bne (label));
2837 emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2841 /* Emit load/stores for a small constant word aligned block_move.
2843 operands[0] is the memory address of the destination.
2844 operands[1] is the memory address of the source.
2845 operands[2] is the number of bytes to move.
2846 operands[3] is a temp register.
2847 operands[4] is a temp register. */
2850 m32r_output_block_move (insn, operands)
2851 rtx insn ATTRIBUTE_UNUSED;
2854 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2858 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2861 /* We do not have a post-increment store available, so the first set of
2862 stores are done without any increment, then the remaining ones can use
2863 the pre-increment addressing mode.
2865 Note: expand_block_move() also relies upon this behaviour when building
2866 loops to copy large blocks. */
2875 output_asm_insn ("ld\t%3, %p1", operands);
2876 output_asm_insn ("ld\t%4, %p1", operands);
2877 output_asm_insn ("st\t%3, @%0", operands);
2878 output_asm_insn ("st\t%4, %s0", operands);
2882 output_asm_insn ("ld\t%3, %p1", operands);
2883 output_asm_insn ("ld\t%4, %p1", operands);
2884 output_asm_insn ("st\t%3, %s0", operands);
2885 output_asm_insn ("st\t%4, %s0", operands);
2890 else if (bytes >= 4)
2895 output_asm_insn ("ld\t%3, %p1", operands);
2898 output_asm_insn ("ld\t%4, %p1", operands);
2901 output_asm_insn ("st\t%3, @%0", operands);
2903 output_asm_insn ("st\t%3, %s0", operands);
2909 /* Get the entire next word, even though we do not want all of it.
2910 The saves us from doing several smaller loads, and we assume that
2911 we cannot cause a page fault when at least part of the word is in
2912 valid memory [since we don't get called if things aren't properly
2914 int dst_offset = first_time ? 0 : 4;
2918 /* If got_extra is true then we have already loaded
2919 the next word as part of loading and storing the previous word. */
2921 output_asm_insn ("ld\t%4, @%1", operands);
2927 output_asm_insn ("sra3\t%3, %4, #16", operands);
2928 my_operands[0] = operands[3];
2929 my_operands[1] = GEN_INT (dst_offset);
2930 my_operands[2] = operands[0];
2931 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2933 /* If there is a byte left to store then increment the
2934 destination address and shift the contents of the source
2935 register down by 8 bits. We could not do the address
2936 increment in the store half word instruction, because it does
2937 not have an auto increment mode. */
2938 if (bytes > 0) /* assert (bytes == 1) */
2949 my_operands[0] = operands[4];
2950 my_operands[1] = GEN_INT (last_shift);
2951 output_asm_insn ("srai\t%0, #%1", my_operands);
2952 my_operands[0] = operands[4];
2953 my_operands[1] = GEN_INT (dst_offset);
2954 my_operands[2] = operands[0];
2955 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2965 /* Return true if op is an integer constant, less than or equal to
2968 m32r_block_immediate_operand (op, mode)
2970 enum machine_mode mode ATTRIBUTE_UNUSED;
2972 if (GET_CODE (op) != CONST_INT
2973 || INTVAL (op) > MAX_MOVE_BYTES
2974 || INTVAL (op) <= 0)