1 /* Target Code for R8C/M16C/M32C
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
48 #include "target-def.h"
50 #include "langhooks.h"
51 #include "tree-gimple.h"
55 /* Used by m32c_pushm_popm. */
63 static tree interrupt_handler (tree *, tree, tree, int, bool *);
64 static tree function_vector_handler (tree *, tree, tree, int, bool *);
65 static int interrupt_p (tree node);
66 static bool m32c_asm_integer (rtx, unsigned int, int);
67 static int m32c_comp_type_attributes (tree, tree);
68 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
69 static struct machine_function *m32c_init_machine_status (void);
70 static void m32c_insert_attributes (tree, tree *);
71 static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
73 static bool m32c_promote_prototypes (tree);
74 static int m32c_pushm_popm (Push_Pop_Type);
75 static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
76 static rtx m32c_struct_value_rtx (tree, int);
77 static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
78 static int need_to_save (int);
79 int current_function_special_page_vector (rtx);
81 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
83 #define streq(a,b) (strcmp ((a), (b)) == 0)
85 /* Internal support routines */
87 /* Debugging statements are tagged with DEBUG0 only so that they can
88 be easily enabled individually, by replacing the '0' with '1' as
94 /* This is needed by some of the commented-out debug statements
96 static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
98 static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
100 /* These are all to support encode_pattern(). */
101 static char pattern[30], *patternp;
102 static GTY(()) rtx patternr[30];
103 #define RTX_IS(x) (streq (pattern, x))
105 /* Some macros to simplify the logic throughout this file. */
106 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
107 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
109 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
110 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
112 /* We do most RTX matching by converting the RTX into a string, and
113 using string compares. This vastly simplifies the logic in many of
114 the functions in this file.
116 On exit, pattern[] has the encoded string (use RTX_IS("...") to
117 compare it) and patternr[] has pointers to the nodes in the RTX
118 corresponding to each character in the encoded string. The latter
119 is mostly used by print_operand().
121 Unrecognized patterns have '?' in them; this shows up when the
122 assembler complains about syntax errors.
126 encode_pattern_1 (rtx x)
130 if (patternp == pattern + sizeof (pattern) - 2)
136 patternr[patternp - pattern] = x;
138 switch (GET_CODE (x))
144 if (GET_MODE_SIZE (GET_MODE (x)) !=
145 GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
147 encode_pattern_1 (XEXP (x, 0));
152 encode_pattern_1 (XEXP (x, 0));
156 encode_pattern_1 (XEXP (x, 0));
157 encode_pattern_1 (XEXP (x, 1));
161 encode_pattern_1 (XEXP (x, 0));
165 encode_pattern_1 (XEXP (x, 0));
169 encode_pattern_1 (XEXP (x, 0));
170 encode_pattern_1 (XEXP (x, 1));
174 encode_pattern_1 (XEXP (x, 0));
191 *patternp++ = '0' + XCINT (x, 1, UNSPEC);
192 for (i = 0; i < XVECLEN (x, 0); i++)
193 encode_pattern_1 (XVECEXP (x, 0, i));
200 for (i = 0; i < XVECLEN (x, 0); i++)
201 encode_pattern_1 (XVECEXP (x, 0, i));
205 encode_pattern_1 (XEXP (x, 0));
207 encode_pattern_1 (XEXP (x, 1));
212 fprintf (stderr, "can't encode pattern %s\n",
213 GET_RTX_NAME (GET_CODE (x)));
222 encode_pattern (rtx x)
225 encode_pattern_1 (x);
229 /* Since register names indicate the mode they're used in, we need a
230 way to determine which name to refer to the register with. Called
231 by print_operand(). */
234 reg_name_with_mode (int regno, enum machine_mode mode)
236 int mlen = GET_MODE_SIZE (mode);
237 if (regno == R0_REGNO && mlen == 1)
239 if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
241 if (regno == R0_REGNO && mlen == 6)
243 if (regno == R0_REGNO && mlen == 8)
245 if (regno == R1_REGNO && mlen == 1)
247 if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
249 if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
251 return reg_names[regno];
254 /* How many bytes a register uses on stack when it's pushed. We need
255 to know this because the push opcode needs to explicitly indicate
256 the size of the register, even though the name of the register
257 already tells it that. Used by m32c_output_reg_{push,pop}, which
258 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
261 reg_push_size (int regno)
286 static int *class_sizes = 0;
288 /* Given two register classes, find the largest intersection between
289 them. If there is no intersection, return RETURNED_IF_EMPTY
292 reduce_class (int original_class, int limiting_class, int returned_if_empty)
294 int cc = class_contents[original_class][0];
295 int i, best = NO_REGS;
298 if (original_class == limiting_class)
299 return original_class;
304 class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
305 for (i = 0; i < LIM_REG_CLASSES; i++)
308 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
309 if (class_contents[i][0] & (1 << r))
314 cc &= class_contents[limiting_class][0];
315 for (i = 0; i < LIM_REG_CLASSES; i++)
317 int ic = class_contents[i][0];
320 if (best_size < class_sizes[i])
323 best_size = class_sizes[i];
328 return returned_if_empty;
332 /* Returns TRUE If there are any registers that exist in both register
335 classes_intersect (int class1, int class2)
337 return class_contents[class1][0] & class_contents[class2][0];
340 /* Used by m32c_register_move_cost to determine if a move is
341 impossibly expensive. */
343 class_can_hold_mode (int class, enum machine_mode mode)
345 /* Cache the results: 0=untested 1=no 2=yes */
346 static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
347 if (results[class][mode] == 0)
350 results[class][mode] = 1;
351 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
352 if (class_contents[class][0] & (1 << r)
353 && HARD_REGNO_MODE_OK (r, mode))
356 n = HARD_REGNO_NREGS (r, mode);
357 for (i = 1; i < n; i++)
358 if (!(class_contents[class][0] & (1 << (r + i))))
362 results[class][mode] = 2;
368 fprintf (stderr, "class %s can hold %s? %s\n",
369 class_names[class], mode_name[mode],
370 (results[class][mode] == 2) ? "yes" : "no");
372 return results[class][mode] == 2;
375 /* Run-time Target Specification. */
377 /* Memregs are memory locations that gcc treats like general
378 registers, as there are a limited number of true registers and the
379 m32c families can use memory in most places that registers can be
382 However, since memory accesses are more expensive than registers,
383 we allow the user to limit the number of memregs available, in
384 order to try to persuade gcc to try harder to use real registers.
386 Memregs are provided by m32c-lib1.S.
389 int target_memregs = 16;
390 static bool target_memregs_set = FALSE;
391 int ok_to_change_target_memregs = TRUE;
393 #undef TARGET_HANDLE_OPTION
394 #define TARGET_HANDLE_OPTION m32c_handle_option
396 m32c_handle_option (size_t code,
397 const char *arg ATTRIBUTE_UNUSED,
398 int value ATTRIBUTE_UNUSED)
400 if (code == OPT_memregs_)
402 target_memregs_set = TRUE;
403 target_memregs = atoi (arg);
408 /* Implements OVERRIDE_OPTIONS. We limit memregs to 0..16, and
409 provide a default. */
411 m32c_override_options (void)
413 if (target_memregs_set)
415 if (target_memregs < 0 || target_memregs > 16)
416 error ("invalid target memregs value '%d'", target_memregs);
422 /* Defining data structures for per-function information */
424 /* The usual; we set up our machine_function data. */
425 static struct machine_function *
426 m32c_init_machine_status (void)
428 struct machine_function *machine;
430 (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
435 /* Implements INIT_EXPANDERS. We just set up to call the above
438 m32c_init_expanders (void)
440 init_machine_status = m32c_init_machine_status;
445 #undef TARGET_PROMOTE_FUNCTION_RETURN
446 #define TARGET_PROMOTE_FUNCTION_RETURN m32c_promote_function_return
448 m32c_promote_function_return (tree fntype ATTRIBUTE_UNUSED)
453 /* Register Basics */
455 /* Basic Characteristics of Registers */
457 /* Whether a mode fits in a register is complex enough to warrant a
466 } nregs_table[FIRST_PSEUDO_REGISTER] =
468 { 1, 1, 2, 2, 4 }, /* r0 */
469 { 0, 1, 0, 0, 0 }, /* r2 */
470 { 1, 1, 2, 2, 0 }, /* r1 */
471 { 0, 1, 0, 0, 0 }, /* r3 */
472 { 0, 1, 1, 0, 0 }, /* a0 */
473 { 0, 1, 1, 0, 0 }, /* a1 */
474 { 0, 1, 1, 0, 0 }, /* sb */
475 { 0, 1, 1, 0, 0 }, /* fb */
476 { 0, 1, 1, 0, 0 }, /* sp */
477 { 1, 1, 1, 0, 0 }, /* pc */
478 { 0, 0, 0, 0, 0 }, /* fl */
479 { 1, 1, 1, 0, 0 }, /* ap */
480 { 1, 1, 2, 2, 4 }, /* mem0 */
481 { 1, 1, 2, 2, 4 }, /* mem1 */
482 { 1, 1, 2, 2, 4 }, /* mem2 */
483 { 1, 1, 2, 2, 4 }, /* mem3 */
484 { 1, 1, 2, 2, 4 }, /* mem4 */
485 { 1, 1, 2, 2, 0 }, /* mem5 */
486 { 1, 1, 2, 2, 0 }, /* mem6 */
487 { 1, 1, 0, 0, 0 }, /* mem7 */
490 /* Implements CONDITIONAL_REGISTER_USAGE. We adjust the number of
491 available memregs, and select which registers need to be preserved
492 across calls based on the chip family. */
495 m32c_conditional_register_usage (void)
499 if (0 <= target_memregs && target_memregs <= 16)
501 /* The command line option is bytes, but our "registers" are
503 for (i = target_memregs/2; i < 8; i++)
505 fixed_regs[MEM0_REGNO + i] = 1;
506 CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
510 /* M32CM and M32C preserve more registers across function calls. */
513 call_used_regs[R1_REGNO] = 0;
514 call_used_regs[R2_REGNO] = 0;
515 call_used_regs[R3_REGNO] = 0;
516 call_used_regs[A0_REGNO] = 0;
517 call_used_regs[A1_REGNO] = 0;
521 /* How Values Fit in Registers */
523 /* Implements HARD_REGNO_NREGS. This is complicated by the fact that
524 different registers are different sizes from each other, *and* may
525 be different sizes in different chip families. */
527 m32c_hard_regno_nregs (int regno, enum machine_mode mode)
529 if (regno == FLG_REGNO && mode == CCmode)
531 if (regno >= FIRST_PSEUDO_REGISTER)
532 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
534 if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
535 return (GET_MODE_SIZE (mode) + 1) / 2;
537 if (GET_MODE_SIZE (mode) <= 1)
538 return nregs_table[regno].qi_regs;
539 if (GET_MODE_SIZE (mode) <= 2)
540 return nregs_table[regno].hi_regs;
541 if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
543 if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
544 return nregs_table[regno].pi_regs;
545 if (GET_MODE_SIZE (mode) <= 4)
546 return nregs_table[regno].si_regs;
547 if (GET_MODE_SIZE (mode) <= 8)
548 return nregs_table[regno].di_regs;
552 /* Implements HARD_REGNO_MODE_OK. The above function does the work
553 already; just test its return value. */
555 m32c_hard_regno_ok (int regno, enum machine_mode mode)
557 return m32c_hard_regno_nregs (regno, mode) != 0;
560 /* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
561 registers are all different sizes. However, since most modes are
562 bigger than our registers anyway, it's easier to implement this
563 function that way, leaving QImode as the only unique case. */
565 m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
567 if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
571 if (m1 == QImode || m2 == QImode)
578 /* Register Classes */
580 /* Implements REGNO_REG_CLASS. */
582 m32c_regno_reg_class (int regno)
606 if (IS_MEM_REGNO (regno))
612 /* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
613 for certain chip families. */
615 m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
617 if (memcmp (s, "Rsp", 3) == 0)
619 if (memcmp (s, "Rfb", 3) == 0)
621 if (memcmp (s, "Rsb", 3) == 0)
623 if (memcmp (s, "Rcr", 3) == 0)
624 return TARGET_A16 ? CR_REGS : NO_REGS;
625 if (memcmp (s, "Rcl", 3) == 0)
626 return TARGET_A24 ? CR_REGS : NO_REGS;
627 if (memcmp (s, "R0w", 3) == 0)
629 if (memcmp (s, "R1w", 3) == 0)
631 if (memcmp (s, "R2w", 3) == 0)
633 if (memcmp (s, "R3w", 3) == 0)
635 if (memcmp (s, "R02", 3) == 0)
637 if (memcmp (s, "R03", 3) == 0)
639 if (memcmp (s, "Rdi", 3) == 0)
641 if (memcmp (s, "Rhl", 3) == 0)
643 if (memcmp (s, "R23", 3) == 0)
645 if (memcmp (s, "Ra0", 3) == 0)
647 if (memcmp (s, "Ra1", 3) == 0)
649 if (memcmp (s, "Raa", 3) == 0)
651 if (memcmp (s, "Raw", 3) == 0)
652 return TARGET_A16 ? A_REGS : NO_REGS;
653 if (memcmp (s, "Ral", 3) == 0)
654 return TARGET_A24 ? A_REGS : NO_REGS;
655 if (memcmp (s, "Rqi", 3) == 0)
657 if (memcmp (s, "Rad", 3) == 0)
659 if (memcmp (s, "Rsi", 3) == 0)
661 if (memcmp (s, "Rhi", 3) == 0)
663 if (memcmp (s, "Rhc", 3) == 0)
665 if (memcmp (s, "Rra", 3) == 0)
667 if (memcmp (s, "Rfl", 3) == 0)
669 if (memcmp (s, "Rmm", 3) == 0)
671 if (fixed_regs[MEM0_REGNO])
676 /* PSImode registers - i.e. whatever can hold a pointer. */
677 if (memcmp (s, "Rpi", 3) == 0)
682 return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
685 /* We handle this one as an EXTRA_CONSTRAINT. */
686 if (memcmp (s, "Rpa", 3) == 0)
691 fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
698 /* Implements REGNO_OK_FOR_BASE_P. */
700 m32c_regno_ok_for_base_p (int regno)
702 if (regno == A0_REGNO
703 || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
708 #define DEBUG_RELOAD 0
710 /* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
711 registers of the appropriate size. */
713 m32c_preferred_reload_class (rtx x, int rclass)
715 int newclass = rclass;
718 fprintf (stderr, "\npreferred_reload_class for %s is ",
719 class_names[rclass]);
721 if (rclass == NO_REGS)
722 rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
724 if (classes_intersect (rclass, CR_REGS))
726 switch (GET_MODE (x))
732 /* newclass = HI_REGS; */
737 else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
739 else if (GET_MODE_SIZE (GET_MODE (x)) > 4
740 && ~class_contents[rclass][0] & 0x000f)
743 rclass = reduce_class (rclass, newclass, rclass);
745 if (GET_MODE (x) == QImode)
746 rclass = reduce_class (rclass, HL_REGS, rclass);
749 fprintf (stderr, "%s\n", class_names[rclass]);
752 if (GET_CODE (x) == MEM
753 && GET_CODE (XEXP (x, 0)) == PLUS
754 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
755 fprintf (stderr, "Glorm!\n");
760 /* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
762 m32c_preferred_output_reload_class (rtx x, int rclass)
764 return m32c_preferred_reload_class (x, rclass);
767 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
768 address registers for reloads since they're needed for address
771 m32c_limit_reload_class (enum machine_mode mode, int rclass)
774 fprintf (stderr, "limit_reload_class for %s: %s ->",
775 mode_name[mode], class_names[rclass]);
779 rclass = reduce_class (rclass, HL_REGS, rclass);
780 else if (mode == HImode)
781 rclass = reduce_class (rclass, HI_REGS, rclass);
782 else if (mode == SImode)
783 rclass = reduce_class (rclass, SI_REGS, rclass);
785 if (rclass != A_REGS)
786 rclass = reduce_class (rclass, DI_REGS, rclass);
789 fprintf (stderr, " %s\n", class_names[rclass]);
794 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
795 r0 or r1, as those are the only real QImode registers. CR regs get
796 reloaded through appropriately sized general or address
799 m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
801 int cc = class_contents[rclass][0];
803 fprintf (stderr, "\nsecondary reload class %s %s\n",
804 class_names[rclass], mode_name[mode]);
808 && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
810 if (classes_intersect (rclass, CR_REGS)
811 && GET_CODE (x) == REG
812 && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
813 return TARGET_A16 ? HI_REGS : A_REGS;
817 /* Implements CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
820 m32c_class_likely_spilled_p (int regclass)
822 if (regclass == A_REGS)
824 return reg_class_size[regclass] == 1;
827 /* Implements CLASS_MAX_NREGS. We calculate this according to its
828 documented meaning, to avoid potential inconsistencies with actual
829 class definitions. */
831 m32c_class_max_nregs (int regclass, enum machine_mode mode)
835 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
836 if (class_contents[regclass][0] & (1 << rn))
838 int n = m32c_hard_regno_nregs (rn, mode);
845 /* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
846 QI (r0l, r1l) because the chip doesn't support QI ops on other
847 registers (well, it does on a0/a1 but if we let gcc do that, reload
848 suffers). Otherwise, we allow changes to larger modes. */
850 m32c_cannot_change_mode_class (enum machine_mode from,
851 enum machine_mode to, int rclass)
855 fprintf (stderr, "cannot change from %s to %s in %s\n",
856 mode_name[from], mode_name[to], class_names[rclass]);
859 /* If the larger mode isn't allowed in any of these registers, we
860 can't allow the change. */
861 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
862 if (class_contents[rclass][0] & (1 << rn))
863 if (! m32c_hard_regno_ok (rn, to))
867 return (class_contents[rclass][0] & 0x1ffa);
869 if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
870 && GET_MODE_SIZE (from) > 1)
872 if (GET_MODE_SIZE (from) > 2) /* all other regs */
878 /* Helpers for the rest of the file. */
879 /* TRUE if the rtx is a REG rtx for the given register. */
880 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
881 && REGNO (rtx) == regno)
882 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
883 base register in address calculations (hence the "strict"
885 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
886 && (REGNO (rtx) == AP_REGNO \
887 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
889 /* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
890 constraints start with 'I', with the next two characters indicating
891 the type and size of the range allowed. */
893 m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
894 char c ATTRIBUTE_UNUSED, const char *str)
896 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
897 [sun] bits [SUN] bytes, p=pointer size
898 I[-0-9][0-9] matches that number */
899 if (memcmp (str, "Is3", 3) == 0)
901 return (-8 <= value && value <= 7);
903 if (memcmp (str, "IS1", 3) == 0)
905 return (-128 <= value && value <= 127);
907 if (memcmp (str, "IS2", 3) == 0)
909 return (-32768 <= value && value <= 32767);
911 if (memcmp (str, "IU2", 3) == 0)
913 return (0 <= value && value <= 65535);
915 if (memcmp (str, "IU3", 3) == 0)
917 return (0 <= value && value <= 0x00ffffff);
919 if (memcmp (str, "In4", 3) == 0)
921 return (-8 <= value && value && value <= 8);
923 if (memcmp (str, "In5", 3) == 0)
925 return (-16 <= value && value && value <= 16);
927 if (memcmp (str, "In6", 3) == 0)
929 return (-32 <= value && value && value <= 32);
931 if (memcmp (str, "IM2", 3) == 0)
933 return (-65536 <= value && value && value <= -1);
935 if (memcmp (str, "Ilb", 3) == 0)
937 int b = exact_log2 (value);
938 return (b >= 0 && b <= 7);
940 if (memcmp (str, "Imb", 3) == 0)
942 int b = exact_log2 ((value ^ 0xff) & 0xff);
943 return (b >= 0 && b <= 7);
945 if (memcmp (str, "Ilw", 3) == 0)
947 int b = exact_log2 (value);
948 return (b >= 0 && b <= 15);
950 if (memcmp (str, "Imw", 3) == 0)
952 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
953 return (b >= 0 && b <= 15);
955 if (memcmp (str, "I00", 3) == 0)
962 /* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
963 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
964 call return values. */
966 m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
968 encode_pattern (value);
969 if (memcmp (str, "Sd", 2) == 0)
971 /* This is the common "src/dest" address */
973 if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
975 if (RTX_IS ("ms") || RTX_IS ("m+si"))
977 if (RTX_IS ("m++rii"))
979 if (REGNO (patternr[3]) == FB_REGNO
980 && INTVAL (patternr[4]) == 0)
985 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
989 if (REGNO (r) == SP_REGNO)
991 return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
993 else if (memcmp (str, "Sa", 2) == 0)
998 else if (RTX_IS ("m+ri"))
1002 return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
1004 else if (memcmp (str, "Si", 2) == 0)
1006 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
1008 else if (memcmp (str, "Ss", 2) == 0)
1010 return ((RTX_IS ("mr")
1011 && (IS_REG (patternr[1], SP_REGNO)))
1012 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
1014 else if (memcmp (str, "Sf", 2) == 0)
1016 return ((RTX_IS ("mr")
1017 && (IS_REG (patternr[1], FB_REGNO)))
1018 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
1020 else if (memcmp (str, "Sb", 2) == 0)
1022 return ((RTX_IS ("mr")
1023 && (IS_REG (patternr[1], SB_REGNO)))
1024 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
1026 else if (memcmp (str, "Sp", 2) == 0)
1028 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
1029 return (RTX_IS ("mi")
1030 && !(INTVAL (patternr[1]) & ~0x1fff));
1032 else if (memcmp (str, "S1", 2) == 0)
1034 return r1h_operand (value, QImode);
1037 gcc_assert (str[0] != 'S');
1039 if (memcmp (str, "Rpa", 2) == 0)
1040 return GET_CODE (value) == PARALLEL;
1045 /* This is for when we're debugging the above. */
1047 m32c_extra_constraint_p (rtx value, char c, const char *str)
1049 int rv = m32c_extra_constraint_p2 (value, c, str);
1051 fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
1058 /* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1059 starting with 'S'. */
1061 m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1066 /* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1067 but don't currently define any. */
1069 m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1074 /* STACK AND CALLING */
1078 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1079 (yes, THREE bytes) onto the stack for the return address, but we
1080 don't support pointers bigger than 16 bits on those chips. This
1081 will likely wreak havoc with exception unwinding. FIXME. */
1083 m32c_return_addr_rtx (int count)
1085 enum machine_mode mode;
1091 /* we want 2[$fb] */
1100 /* FIXME: it's really 3 bytes */
1106 gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1107 return copy_to_mode_reg (mode, ra_mem);
1110 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1112 m32c_incoming_return_addr_rtx (void)
1115 return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1118 /* Exception Handling Support */
1120 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1123 m32c_eh_return_data_regno (int n)
1132 return INVALID_REGNUM;
1136 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1137 m32c_emit_eh_epilogue. */
1139 m32c_eh_return_stackadj_rtx (void)
1141 if (!cfun->machine->eh_stack_adjust)
1145 sa = gen_reg_rtx (Pmode);
1146 cfun->machine->eh_stack_adjust = sa;
1148 return cfun->machine->eh_stack_adjust;
1151 /* Registers That Address the Stack Frame */
1153 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1154 the original spec called for dwarf numbers to vary with register
1155 width as well, for example, r0l, r0, and r2r0 would each have
1156 different dwarf numbers. GCC doesn't support this, and we don't do
1157 it, and gdb seems to like it this way anyway. */
1159 m32c_dwarf_frame_regnum (int n)
1185 return DWARF_FRAME_REGISTERS + 1;
1189 /* The frame looks like this:
1191 ap -> +------------------------------
1192 | Return address (3 or 4 bytes)
1193 | Saved FB (2 or 4 bytes)
1194 fb -> +------------------------------
1197 | through r0 as needed
1198 sp -> +------------------------------
1201 /* We use this to wrap all emitted insns in the prologue. */
1205 RTX_FRAME_RELATED_P (x) = 1;
1209 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1210 how much the stack pointer moves for each, for each cpu family. */
1219 /* These are in reverse push (nearest-to-sp) order. */
1220 { R0_REGNO, 0x80, 2, 2 },
1221 { R1_REGNO, 0x40, 2, 2 },
1222 { R2_REGNO, 0x20, 2, 2 },
1223 { R3_REGNO, 0x10, 2, 2 },
1224 { A0_REGNO, 0x08, 2, 4 },
1225 { A1_REGNO, 0x04, 2, 4 },
1226 { SB_REGNO, 0x02, 2, 4 },
1227 { FB_REGNO, 0x01, 2, 4 }
1230 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1232 /* Returns TRUE if we need to save/restore the given register. We
1233 save everything for exception handlers, so that any register can be
1234 unwound. For interrupt handlers, we save everything if the handler
1235 calls something else (because we don't know what *that* function
1236 might do), but try to be a bit smarter if the handler is a leaf
1237 function. We always save $a0, though, because we use that in the
1238 epilogue to copy $fb to $sp. */
1240 need_to_save (int regno)
1242 if (fixed_regs[regno])
1244 if (cfun->calls_eh_return)
1246 if (regno == FP_REGNO)
1248 if (cfun->machine->is_interrupt
1249 && (!cfun->machine->is_leaf || regno == A0_REGNO))
1251 if (regs_ever_live[regno]
1252 && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1257 /* This function contains all the intelligence about saving and
1258 restoring registers. It always figures out the register save set.
1259 When called with PP_justcount, it merely returns the size of the
1260 save set (for eliminating the frame pointer, for example). When
1261 called with PP_pushm or PP_popm, it emits the appropriate
1262 instructions for saving (pushm) or restoring (popm) the
1265 m32c_pushm_popm (Push_Pop_Type ppt)
1268 int byte_count = 0, bytes;
1270 rtx dwarf_set[PUSHM_N];
1272 int nosave_mask = 0;
1274 if (cfun->return_rtx
1275 && GET_CODE (cfun->return_rtx) == PARALLEL
1276 && !(cfun->calls_eh_return || cfun->machine->is_interrupt))
1278 rtx exp = XVECEXP (cfun->return_rtx, 0, 0);
1279 rtx rv = XEXP (exp, 0);
1280 int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1283 nosave_mask |= 0x20; /* PSI, SI */
1285 nosave_mask |= 0xf0; /* DF */
1287 nosave_mask |= 0x50; /* DI */
1290 for (i = 0; i < (int) PUSHM_N; i++)
1292 /* Skip if neither register needs saving. */
1293 if (!need_to_save (pushm_info[i].reg1))
1296 if (pushm_info[i].bit & nosave_mask)
1299 reg_mask |= pushm_info[i].bit;
1300 bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1302 if (ppt == PP_pushm)
1304 enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1307 /* Always use stack_pointer_rtx instead of calling
1308 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1309 that there is a single rtx representing the stack pointer,
1310 namely stack_pointer_rtx, and uses == to recognize it. */
1311 addr = stack_pointer_rtx;
1313 if (byte_count != 0)
1314 addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1316 dwarf_set[n_dwarfs++] =
1317 gen_rtx_SET (VOIDmode,
1318 gen_rtx_MEM (mode, addr),
1319 gen_rtx_REG (mode, pushm_info[i].reg1));
1320 F (dwarf_set[n_dwarfs - 1]);
1323 byte_count += bytes;
1326 if (cfun->machine->is_interrupt)
1328 cfun->machine->intr_pushm = reg_mask & 0xfe;
1333 if (cfun->machine->is_interrupt)
1334 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1335 if (need_to_save (i))
1338 cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1341 if (ppt == PP_pushm && byte_count)
1343 rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1348 XVECEXP (note, 0, 0)
1349 = gen_rtx_SET (VOIDmode,
1351 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1353 GEN_INT (-byte_count)));
1354 F (XVECEXP (note, 0, 0));
1356 for (i = 0; i < n_dwarfs; i++)
1357 XVECEXP (note, 0, i + 1) = dwarf_set[i];
1359 pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1361 REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
1365 if (cfun->machine->is_interrupt)
1366 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1367 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1370 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1372 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1376 if (ppt == PP_popm && byte_count)
1378 if (cfun->machine->is_interrupt)
1379 for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1380 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1383 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
1385 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
1388 emit_insn (gen_popm (GEN_INT (reg_mask)));
1394 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1395 diagrams our call frame. */
1397 m32c_initial_elimination_offset (int from, int to)
1401 if (from == AP_REGNO)
1411 ofs += m32c_pushm_popm (PP_justcount);
1412 ofs += get_frame_size ();
1415 /* Account for push rounding. */
1417 ofs = (ofs + 1) & ~1;
1419 fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1425 /* Passing Function Arguments on the Stack */
1427 #undef TARGET_PROMOTE_PROTOTYPES
1428 #define TARGET_PROMOTE_PROTOTYPES m32c_promote_prototypes
1430 m32c_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
1435 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1436 M32C has word stacks. */
1438 m32c_push_rounding (int n)
1440 if (TARGET_R8C || TARGET_M16C)
1442 return (n + 1) & ~1;
1445 /* Passing Arguments in Registers */
1447 /* Implements FUNCTION_ARG. Arguments are passed partly in registers,
1448 partly on stack. If our function returns a struct, a pointer to a
1449 buffer for it is at the top of the stack (last thing pushed). The
1450 first few real arguments may be in registers as follows:
1452 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1453 arg2 in r2 if it's HI (else pushed on stack)
1455 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1458 Structs are not passed in registers, even if they fit. Only
1459 integer and pointer types are passed in registers.
1461 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1464 m32c_function_arg (CUMULATIVE_ARGS * ca,
1465 enum machine_mode mode, tree type, int named)
1467 /* Can return a reg, parallel, or 0 for stack */
1470 fprintf (stderr, "func_arg %d (%s, %d)\n",
1471 ca->parm_num, mode_name[mode], named);
1475 if (mode == VOIDmode)
1478 if (ca->force_mem || !named)
1481 fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1487 if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1490 if (type && AGGREGATE_TYPE_P (type))
1493 switch (ca->parm_num)
1496 if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1497 rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1501 if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1502 rv = gen_rtx_REG (mode, R2_REGNO);
1512 #undef TARGET_PASS_BY_REFERENCE
1513 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1515 m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1516 enum machine_mode mode ATTRIBUTE_UNUSED,
1517 tree type ATTRIBUTE_UNUSED,
1518 bool named ATTRIBUTE_UNUSED)
1523 /* Implements INIT_CUMULATIVE_ARGS. */
1525 m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
1527 rtx libname ATTRIBUTE_UNUSED,
1529 int n_named_args ATTRIBUTE_UNUSED)
1531 if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
1538 /* Implements FUNCTION_ARG_ADVANCE. force_mem is set for functions
1539 returning structures, so we always reset that. Otherwise, we only
1540 need to know the sequence number of the argument to know what to do
1543 m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1544 enum machine_mode mode ATTRIBUTE_UNUSED,
1545 tree type ATTRIBUTE_UNUSED,
1546 int named ATTRIBUTE_UNUSED)
1554 /* Implements FUNCTION_ARG_REGNO_P. */
1556 m32c_function_arg_regno_p (int r)
1559 return (r == R0_REGNO);
1560 return (r == R1_REGNO || r == R2_REGNO);
1563 /* HImode and PSImode are the two "native" modes as far as GCC is
1564 concerned, but the chips also support a 32-bit mode which is used
1565 for some opcodes in R8C/M16C and for reset vectors and such. */
1566 #undef TARGET_VALID_POINTER_MODE
1567 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1569 m32c_valid_pointer_mode (enum machine_mode mode)
1579 /* How Scalar Function Values Are Returned */
1581 /* Implements LIBCALL_VALUE. Most values are returned in $r0, or some
1582 combination of registers starting there (r2r0 for longs, r3r1r2r0
1583 for long long, r3r2r1r0 for doubles), except that that ABI
1584 currently doesn't work because it ends up using all available
1585 general registers and gcc often can't compile it. So, instead, we
1586 return anything bigger than 16 bits in "mem0" (effectively, a
1587 memory location). */
1589 m32c_libcall_value (enum machine_mode mode)
1591 /* return reg or parallel */
1593 /* FIXME: GCC has difficulty returning large values in registers,
1594 because that ties up most of the general registers and gives the
1595 register allocator little to work with. Until we can resolve
1596 this, large values are returned in memory. */
1601 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1602 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1603 gen_rtx_REG (HImode,
1606 XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1607 gen_rtx_REG (HImode,
1610 XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1611 gen_rtx_REG (HImode,
1614 XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1615 gen_rtx_REG (HImode,
1621 if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1625 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1626 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1634 if (GET_MODE_SIZE (mode) > 2)
1635 return gen_rtx_REG (mode, MEM0_REGNO);
1636 return gen_rtx_REG (mode, R0_REGNO);
1639 /* Implements FUNCTION_VALUE. Functions and libcalls have the same
1642 m32c_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
1644 /* return reg or parallel */
1645 enum machine_mode mode = TYPE_MODE (valtype);
1646 return m32c_libcall_value (mode);
1649 /* How Large Values Are Returned */
1651 /* We return structures by pushing the address on the stack, even if
1652 we use registers for the first few "real" arguments. */
1653 #undef TARGET_STRUCT_VALUE_RTX
1654 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1656 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1657 int incoming ATTRIBUTE_UNUSED)
1662 /* Function Entry and Exit */
1664 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1666 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1668 if (cfun->machine->is_interrupt)
1673 /* Implementing the Varargs Macros */
1675 #undef TARGET_STRICT_ARGUMENT_NAMING
1676 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1678 m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1683 /* Trampolines for Nested Functions */
1687 1 0000 75C43412 mov.w #0x1234,a0
1688 2 0004 FC000000 jmp.a label
1691 1 0000 BC563412 mov.l:s #0x123456,a0
1692 2 0004 CC000000 jmp.a label
1695 /* Implements TRAMPOLINE_SIZE. */
1697 m32c_trampoline_size (void)
1699 /* Allocate extra space so we can avoid the messy shifts when we
1700 initialize the trampoline; we just write past the end of the
1702 return TARGET_A16 ? 8 : 10;
1705 /* Implements TRAMPOLINE_ALIGNMENT. */
1707 m32c_trampoline_alignment (void)
1712 /* Implements INITIALIZE_TRAMPOLINE. */
1714 m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
1716 #define A0(m,i) gen_rtx_MEM (m, plus_constant (tramp, i))
1719 /* Note: we subtract a "word" because the moves want signed
1720 constants, not unsigned constants. */
1721 emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1722 emit_move_insn (A0 (HImode, 2), chainval);
1723 emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
1724 /* We use 16-bit addresses here, but store the zero to turn it
1725 into a 24-bit offset. */
1726 emit_move_insn (A0 (HImode, 5), function);
1727 emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1731 /* Note that the PSI moves actually write 4 bytes. Make sure we
1732 write stuff out in the right order, and leave room for the
1733 extra byte at the end. */
1734 emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1735 emit_move_insn (A0 (PSImode, 1), chainval);
1736 emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1737 emit_move_insn (A0 (PSImode, 5), function);
1742 /* Implicit Calls to Library Routines */
1744 #undef TARGET_INIT_LIBFUNCS
1745 #define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
1747 m32c_init_libfuncs (void)
1751 /* We do this because the M32C has an HImode operand, but the
1752 M16C has an 8-bit operand. Since gcc looks at the match data
1753 and not the expanded rtl, we have to reset the array so that
1754 the right modes are found. */
1755 setcc_gen_code[EQ] = CODE_FOR_seq_24;
1756 setcc_gen_code[NE] = CODE_FOR_sne_24;
1757 setcc_gen_code[GT] = CODE_FOR_sgt_24;
1758 setcc_gen_code[GE] = CODE_FOR_sge_24;
1759 setcc_gen_code[LT] = CODE_FOR_slt_24;
1760 setcc_gen_code[LE] = CODE_FOR_sle_24;
1761 setcc_gen_code[GTU] = CODE_FOR_sgtu_24;
1762 setcc_gen_code[GEU] = CODE_FOR_sgeu_24;
1763 setcc_gen_code[LTU] = CODE_FOR_sltu_24;
1764 setcc_gen_code[LEU] = CODE_FOR_sleu_24;
1768 /* Addressing Modes */
1770 /* Used by GO_IF_LEGITIMATE_ADDRESS. The r8c/m32c family supports a
1771 wide range of non-orthogonal addressing modes, including the
1772 ability to double-indirect on *some* of them. Not all insns
1773 support all modes, either, but we rely on predicates and
1774 constraints to deal with that. */
1776 m32c_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1782 /* Wide references to memory will be split after reload, so we must
1783 ensure that all parts of such splits remain legitimate
1785 mode_adjust = GET_MODE_SIZE (mode) - 1;
1787 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1788 if (GET_CODE (x) == PRE_DEC
1789 || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1791 return (GET_CODE (XEXP (x, 0)) == REG
1792 && REGNO (XEXP (x, 0)) == SP_REGNO);
1796 /* This is the double indirection detection, but it currently
1797 doesn't work as cleanly as this code implies, so until we've had
1798 a chance to debug it, leave it disabled. */
1799 if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1802 fprintf (stderr, "double indirect\n");
1811 /* Most indexable registers can be used without displacements,
1812 although some of them will be emitted with an explicit zero
1813 to please the assembler. */
1814 switch (REGNO (patternr[0]))
1824 if (IS_PSEUDO (patternr[0], strict))
1831 /* This is more interesting, because different base registers
1832 allow for different displacements - both range and signedness
1833 - and it differs from chip series to chip series too. */
1834 int rn = REGNO (patternr[1]);
1835 HOST_WIDE_INT offs = INTVAL (patternr[2]);
1841 /* The syntax only allows positive offsets, but when the
1842 offsets span the entire memory range, we can simulate
1843 negative offsets by wrapping. */
1845 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1847 return (offs >= 0 && offs <= 65535 - mode_adjust);
1849 return (offs >= -16777216 && offs <= 16777215);
1853 return (offs >= -128 && offs <= 127 - mode_adjust);
1854 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1857 return (offs >= -128 && offs <= 127 - mode_adjust);
1860 if (IS_PSEUDO (patternr[1], strict))
1865 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1867 rtx reg = patternr[1];
1869 /* We don't know where the symbol is, so only allow base
1870 registers which support displacements spanning the whole
1872 switch (REGNO (reg))
1876 /* $sb needs a secondary reload, but since it's involved in
1877 memory address reloads too, we don't deal with it very
1879 /* case SB_REGNO: */
1882 if (IS_PSEUDO (reg, strict))
1890 /* Implements REG_OK_FOR_BASE_P. */
1892 m32c_reg_ok_for_base_p (rtx x, int strict)
1894 if (GET_CODE (x) != REG)
1905 if (IS_PSEUDO (x, strict))
1911 /* We have three choices for choosing fb->aN offsets. If we choose -128,
1912 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
1914 EB 4B FF mova -128[$fb],$a0
1915 D8 0C FF FF mov.w:Q #0,-1[$a0]
1917 Alternately, we subtract the frame size, and hopefully use 8-bit aN
1920 77 54 00 01 sub #256,$a0
1921 D8 08 01 mov.w:Q #0,1[$a0]
1923 If we don't offset (i.e. offset by zero), we end up with:
1925 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1927 We have to subtract *something* so that we have a PLUS rtx to mark
1928 that we've done this reload. The -128 offset will never result in
1929 an 8-bit aN offset, and the payoff for the second case is five
1930 loads *if* those loads are within 256 bytes of the other end of the
1931 frame, so the third case seems best. Note that we subtract the
1932 zero, but detect that in the addhi3 pattern. */
1934 #define BIG_FB_ADJ 0
1936 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1937 worry about is frame base offsets, as $fb has a limited
1938 displacement range. We deal with this by attempting to reload $fb
1939 itself into an address register; that seems to result in the best
1942 m32c_legitimize_address (rtx * x ATTRIBUTE_UNUSED,
1943 rtx oldx ATTRIBUTE_UNUSED,
1944 enum machine_mode mode ATTRIBUTE_UNUSED)
1947 fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
1949 fprintf (stderr, "\n");
1952 if (GET_CODE (*x) == PLUS
1953 && GET_CODE (XEXP (*x, 0)) == REG
1954 && REGNO (XEXP (*x, 0)) == FB_REGNO
1955 && GET_CODE (XEXP (*x, 1)) == CONST_INT
1956 && (INTVAL (XEXP (*x, 1)) < -128
1957 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
1959 /* reload FB to A_REGS */
1960 rtx temp = gen_reg_rtx (Pmode);
1962 emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (*x, 0)));
1963 XEXP (*x, 0) = temp;
1970 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1972 m32c_legitimize_reload_address (rtx * x,
1973 enum machine_mode mode,
1975 int type, int ind_levels ATTRIBUTE_UNUSED)
1978 fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
1983 /* At one point, this function tried to get $fb copied to an address
1984 register, which in theory would maximize sharing, but gcc was
1985 *also* still trying to reload the whole address, and we'd run out
1986 of address registers. So we let gcc do the naive (but safe)
1987 reload instead, when the above function doesn't handle it for
1990 The code below is a second attempt at the above. */
1992 if (GET_CODE (*x) == PLUS
1993 && GET_CODE (XEXP (*x, 0)) == REG
1994 && REGNO (XEXP (*x, 0)) == FB_REGNO
1995 && GET_CODE (XEXP (*x, 1)) == CONST_INT
1996 && (INTVAL (XEXP (*x, 1)) < -128
1997 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
2000 int offset = INTVAL (XEXP (*x, 1));
2001 int adjustment = -BIG_FB_ADJ;
2003 sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
2004 GEN_INT (adjustment));
2005 *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
2006 if (type == RELOAD_OTHER)
2007 type = RELOAD_FOR_OTHER_ADDRESS;
2008 push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
2009 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2014 if (GET_CODE (*x) == PLUS
2015 && GET_CODE (XEXP (*x, 0)) == PLUS
2016 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
2017 && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
2018 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
2019 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2022 if (type == RELOAD_OTHER)
2023 type = RELOAD_FOR_OTHER_ADDRESS;
2024 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
2025 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2033 /* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
2034 so we can allow anything. */
2036 m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
2042 /* Condition Code Status */
2044 #undef TARGET_FIXED_CONDITION_CODE_REGS
2045 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2047 m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
2050 *p2 = INVALID_REGNUM;
2054 /* Describing Relative Costs of Operations */
2056 /* Implements REGISTER_MOVE_COST. We make impossible moves
2057 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2058 no opcodes to do that). We also discourage use of mem* registers
2059 since they're really memory. */
2061 m32c_register_move_cost (enum machine_mode mode, int from, int to)
2063 int cost = COSTS_N_INSNS (3);
2064 int cc = class_contents[from][0] | class_contents[to][0];
2065 /* FIXME: pick real values, but not 2 for now. */
2066 if (mode == QImode && (cc & class_contents[R23_REGS][0]))
2068 if (!(cc & ~class_contents[R23_REGS][0]))
2069 cost = COSTS_N_INSNS (1000);
2071 cost = COSTS_N_INSNS (80);
2074 if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
2075 cost = COSTS_N_INSNS (1000);
2077 if (classes_intersect (from, CR_REGS))
2078 cost += COSTS_N_INSNS (5);
2080 if (classes_intersect (to, CR_REGS))
2081 cost += COSTS_N_INSNS (5);
2083 if (from == MEM_REGS || to == MEM_REGS)
2084 cost += COSTS_N_INSNS (50);
2085 else if (classes_intersect (from, MEM_REGS)
2086 || classes_intersect (to, MEM_REGS))
2087 cost += COSTS_N_INSNS (10);
2090 fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
2091 mode_name[mode], class_names[from], class_names[to], cost);
2096 /* Implements MEMORY_MOVE_COST. */
2098 m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2099 int reg_class ATTRIBUTE_UNUSED,
2100 int in ATTRIBUTE_UNUSED)
2102 /* FIXME: pick real values. */
2103 return COSTS_N_INSNS (10);
2106 /* Here we try to describe when we use multiple opcodes for one RTX so
2107 that gcc knows when to use them. */
2108 #undef TARGET_RTX_COSTS
2109 #define TARGET_RTX_COSTS m32c_rtx_costs
2111 m32c_rtx_costs (rtx x, int code, int outer_code, int *total)
2116 if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
2117 *total += COSTS_N_INSNS (500);
2119 *total += COSTS_N_INSNS (1);
2125 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2127 /* mov.b r1l, r1h */
2128 *total += COSTS_N_INSNS (1);
2131 if (INTVAL (XEXP (x, 1)) > 8
2132 || INTVAL (XEXP (x, 1)) < -8)
2135 /* mov.b r1l, r1h */
2136 *total += COSTS_N_INSNS (2);
2151 if (outer_code == SET)
2153 *total += COSTS_N_INSNS (2);
2160 rtx dest = XEXP (x, 0);
2161 rtx addr = XEXP (dest, 0);
2162 switch (GET_CODE (addr))
2165 *total += COSTS_N_INSNS (1);
2168 *total += COSTS_N_INSNS (3);
2171 *total += COSTS_N_INSNS (2);
2179 /* Reasonable default. */
2180 if (TARGET_A16 && GET_MODE(x) == SImode)
2181 *total += COSTS_N_INSNS (2);
2187 #undef TARGET_ADDRESS_COST
2188 #define TARGET_ADDRESS_COST m32c_address_cost
2190 m32c_address_cost (rtx addr)
2192 /* fprintf(stderr, "\naddress_cost\n");
2194 switch (GET_CODE (addr))
2197 return COSTS_N_INSNS(1);
2199 return COSTS_N_INSNS(3);
2201 return COSTS_N_INSNS(2);
2207 /* Defining the Output Assembler Language */
2209 /* The Overall Framework of an Assembler File */
2211 #undef TARGET_HAVE_NAMED_SECTIONS
2212 #define TARGET_HAVE_NAMED_SECTIONS true
2214 /* Output of Data */
2216 /* We may have 24 bit sizes, which is the native address size.
2217 Currently unused, but provided for completeness. */
2218 #undef TARGET_ASM_INTEGER
2219 #define TARGET_ASM_INTEGER m32c_asm_integer
2221 m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
2226 fprintf (asm_out_file, "\t.3byte\t");
2227 output_addr_const (asm_out_file, x);
2228 fputc ('\n', asm_out_file);
2231 if (GET_CODE (x) == SYMBOL_REF)
2233 fprintf (asm_out_file, "\t.long\t");
2234 output_addr_const (asm_out_file, x);
2235 fputc ('\n', asm_out_file);
2240 return default_assemble_integer (x, size, aligned_p);
2243 /* Output of Assembler Instructions */
2245 /* We use a lookup table because the addressing modes are non-orthogonal. */
2250 char const *pattern;
2253 const conversions[] = {
2256 { 0, "mr", "z[1]" },
2257 { 0, "m+ri", "3[2]" },
2258 { 0, "m+rs", "3[2]" },
2259 { 0, "m+r+si", "4+5[2]" },
2262 { 0, "m+si", "2+3" },
2264 { 0, "mmr", "[z[2]]" },
2265 { 0, "mm+ri", "[4[3]]" },
2266 { 0, "mm+rs", "[4[3]]" },
2267 { 0, "mm+r+si", "[5+6[3]]" },
2268 { 0, "mms", "[[2]]" },
2269 { 0, "mmi", "[[2]]" },
2270 { 0, "mm+si", "[4[3]]" },
2274 { 0, "+si", "#1+2" },
2280 { 'd', "+si", "1+2" },
2283 { 'D', "+si", "1+2" },
2294 /* This is in order according to the bitfield that pushm/popm use. */
2295 static char const *pushm_regs[] = {
2296 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2299 /* Implements PRINT_OPERAND. */
2301 m32c_print_operand (FILE * file, rtx x, int code)
2306 int unsigned_const = 0;
2309 /* Multiplies; constants are converted to sign-extended format but
2310 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2322 /* This one is only for debugging; you can put it in a pattern to
2323 force this error. */
2326 fprintf (stderr, "dj: unreviewed pattern:");
2327 if (current_output_insn)
2328 debug_rtx (current_output_insn);
2331 /* PSImode operations are either .w or .l depending on the target. */
2335 fprintf (file, "w");
2337 fprintf (file, "l");
2340 /* Inverted conditionals. */
2343 switch (GET_CODE (x))
2349 fputs ("gtu", file);
2355 fputs ("geu", file);
2361 fputs ("leu", file);
2367 fputs ("ltu", file);
2380 /* Regular conditionals. */
2383 switch (GET_CODE (x))
2389 fputs ("leu", file);
2395 fputs ("ltu", file);
2401 fputs ("gtu", file);
2407 fputs ("geu", file);
2420 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2422 if (code == 'h' && GET_MODE (x) == SImode)
2424 x = m32c_subreg (HImode, x, SImode, 0);
2427 if (code == 'H' && GET_MODE (x) == SImode)
2429 x = m32c_subreg (HImode, x, SImode, 2);
2432 if (code == 'h' && GET_MODE (x) == HImode)
2434 x = m32c_subreg (QImode, x, HImode, 0);
2437 if (code == 'H' && GET_MODE (x) == HImode)
2439 /* We can't actually represent this as an rtx. Do it here. */
2440 if (GET_CODE (x) == REG)
2445 fputs ("r0h", file);
2448 fputs ("r1h", file);
2454 /* This should be a MEM. */
2455 x = m32c_subreg (QImode, x, HImode, 1);
2458 /* This is for BMcond, which always wants word register names. */
2459 if (code == 'h' && GET_MODE (x) == QImode)
2461 if (GET_CODE (x) == REG)
2462 x = gen_rtx_REG (HImode, REGNO (x));
2465 /* 'x' and 'X' need to be ignored for non-immediates. */
2466 if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2471 for (i = 0; conversions[i].pattern; i++)
2472 if (conversions[i].code == code
2473 && streq (conversions[i].pattern, pattern))
2475 for (j = 0; conversions[i].format[j]; j++)
2476 /* backslash quotes the next character in the output pattern. */
2477 if (conversions[i].format[j] == '\\')
2479 fputc (conversions[i].format[j + 1], file);
2482 /* Digits in the output pattern indicate that the
2483 corresponding RTX is to be output at that point. */
2484 else if (ISDIGIT (conversions[i].format[j]))
2486 rtx r = patternr[conversions[i].format[j] - '0'];
2487 switch (GET_CODE (r))
2490 fprintf (file, "%s",
2491 reg_name_with_mode (REGNO (r), GET_MODE (r)));
2500 int i = (int) exact_log2 (v);
2502 i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
2504 i = (int) exact_log2 ((v ^ 0xff) & 0xff);
2506 fprintf (file, "%d", i);
2510 /* Unsigned byte. */
2511 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2515 /* Unsigned word. */
2516 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2517 INTVAL (r) & 0xffff);
2520 /* pushm and popm encode a register set into a single byte. */
2522 for (b = 7; b >= 0; b--)
2523 if (INTVAL (r) & (1 << b))
2525 fprintf (file, "%s%s", comma, pushm_regs[b]);
2530 /* "Minus". Output -X */
2531 ival = (-INTVAL (r) & 0xffff);
2533 ival = ival - 0x10000;
2534 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2538 if (conversions[i].format[j + 1] == '[' && ival < 0)
2540 /* We can simulate negative displacements by
2541 taking advantage of address space
2542 wrapping when the offset can span the
2543 entire address range. */
2545 patternr[conversions[i].format[j + 2] - '0'];
2546 if (GET_CODE (base) == REG)
2547 switch (REGNO (base))
2552 ival = 0x1000000 + ival;
2554 ival = 0x10000 + ival;
2558 ival = 0x10000 + ival;
2562 else if (code == 'd' && ival < 0 && j == 0)
2563 /* The "mova" opcode is used to do addition by
2564 computing displacements, but again, we need
2565 displacements to be unsigned *if* they're
2566 the only component of the displacement
2567 (i.e. no "symbol-4" type displacement). */
2568 ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2570 if (conversions[i].format[j] == '0')
2572 /* More conversions to unsigned. */
2573 if (unsigned_const == 2)
2575 if (unsigned_const == 1)
2578 if (streq (conversions[i].pattern, "mi")
2579 || streq (conversions[i].pattern, "mmi"))
2581 /* Integers used as addresses are unsigned. */
2582 ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2584 if (force_sign && ival >= 0)
2586 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2591 /* We don't have const_double constants. If it
2592 happens, make it obvious. */
2593 fprintf (file, "[const_double 0x%lx]",
2594 (unsigned long) CONST_DOUBLE_HIGH (r));
2597 assemble_name (file, XSTR (r, 0));
2600 output_asm_label (r);
2603 fprintf (stderr, "don't know how to print this operand:");
2610 if (conversions[i].format[j] == 'z')
2612 /* Some addressing modes *must* have a displacement,
2613 so insert a zero here if needed. */
2615 for (k = j + 1; conversions[i].format[k]; k++)
2616 if (ISDIGIT (conversions[i].format[k]))
2618 rtx reg = patternr[conversions[i].format[k] - '0'];
2619 if (GET_CODE (reg) == REG
2620 && (REGNO (reg) == SB_REGNO
2621 || REGNO (reg) == FB_REGNO
2622 || REGNO (reg) == SP_REGNO))
2627 /* Signed displacements off symbols need to have signs
2629 if (conversions[i].format[j] == '+'
2630 && (!code || code == 'D' || code == 'd')
2631 && ISDIGIT (conversions[i].format[j + 1])
2632 && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
2638 fputc (conversions[i].format[j], file);
2642 if (!conversions[i].pattern)
2644 fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
2647 fprintf (file, "[%c.%s]", code ? code : '-', pattern);
2653 /* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
2654 above for descriptions of what these do. */
2656 m32c_print_operand_punct_valid_p (int c)
2658 if (c == '&' || c == '!')
2663 /* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2665 m32c_print_operand_address (FILE * stream, rtx address)
2667 gcc_assert (GET_CODE (address) == MEM);
2668 m32c_print_operand (stream, XEXP (address, 0), 0);
2671 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2672 differently than general registers. */
2674 m32c_output_reg_push (FILE * s, int regno)
2676 if (regno == FLG_REGNO)
2677 fprintf (s, "\tpushc\tflg\n");
2679 fprintf (s, "\tpush.%c\t%s\n",
2680 " bwll"[reg_push_size (regno)], reg_names[regno]);
2683 /* Likewise for ASM_OUTPUT_REG_POP. */
2685 m32c_output_reg_pop (FILE * s, int regno)
2687 if (regno == FLG_REGNO)
2688 fprintf (s, "\tpopc\tflg\n");
2690 fprintf (s, "\tpop.%c\t%s\n",
2691 " bwll"[reg_push_size (regno)], reg_names[regno]);
2694 /* Defining target-specific uses of `__attribute__' */
2696 /* Used to simplify the logic below. Find the attributes wherever
2698 #define M32C_ATTRIBUTES(decl) \
2699 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2700 : DECL_ATTRIBUTES (decl) \
2701 ? (DECL_ATTRIBUTES (decl)) \
2702 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2704 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2706 interrupt_p (tree node ATTRIBUTE_UNUSED)
2708 tree list = M32C_ATTRIBUTES (node);
2711 if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
2713 list = TREE_CHAIN (list);
2719 interrupt_handler (tree * node ATTRIBUTE_UNUSED,
2720 tree name ATTRIBUTE_UNUSED,
2721 tree args ATTRIBUTE_UNUSED,
2722 int flags ATTRIBUTE_UNUSED,
2723 bool * no_add_attrs ATTRIBUTE_UNUSED)
2728 /* Returns TRUE if given tree has the "function_vector" attribute. */
2730 m32c_special_page_vector_p (tree func)
2732 if (TREE_CODE (func) != FUNCTION_DECL)
2735 tree list = M32C_ATTRIBUTES (func);
2738 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2740 list = TREE_CHAIN (list);
2746 function_vector_handler (tree * node ATTRIBUTE_UNUSED,
2747 tree name ATTRIBUTE_UNUSED,
2748 tree args ATTRIBUTE_UNUSED,
2749 int flags ATTRIBUTE_UNUSED,
2750 bool * no_add_attrs ATTRIBUTE_UNUSED)
2754 /* The attribute is not supported for R8C target. */
2755 warning (OPT_Wattributes,
2756 "`%s' attribute is not supported for R8C target",
2757 IDENTIFIER_POINTER (name));
2758 *no_add_attrs = true;
2760 else if (TREE_CODE (*node) != FUNCTION_DECL)
2762 /* The attribute must be applied to functions only. */
2763 warning (OPT_Wattributes,
2764 "`%s' attribute applies only to functions",
2765 IDENTIFIER_POINTER (name));
2766 *no_add_attrs = true;
2768 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
2770 /* The argument must be a constant integer. */
2771 warning (OPT_Wattributes,
2772 "`%s' attribute argument not an integer constant",
2773 IDENTIFIER_POINTER (name));
2774 *no_add_attrs = true;
2776 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
2777 || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
2779 /* The argument value must be between 18 to 255. */
2780 warning (OPT_Wattributes,
2781 "`%s' attribute argument should be between 18 to 255",
2782 IDENTIFIER_POINTER (name));
2783 *no_add_attrs = true;
2788 /* If the function is assigned the attribute 'function_vector', it
2789 returns the function vector number, otherwise returns zero. */
2791 current_function_special_page_vector (rtx x)
2795 if ((GET_CODE(x) == SYMBOL_REF)
2796 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2798 tree t = SYMBOL_REF_DECL (x);
2800 if (TREE_CODE (t) != FUNCTION_DECL)
2803 tree list = M32C_ATTRIBUTES (t);
2806 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2808 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
2812 list = TREE_CHAIN (list);
2821 #undef TARGET_ATTRIBUTE_TABLE
2822 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2823 static const struct attribute_spec m32c_attribute_table[] = {
2824 {"interrupt", 0, 0, false, false, false, interrupt_handler},
2825 {"function_vector", 1, 1, true, false, false, function_vector_handler},
2826 {0, 0, 0, 0, 0, 0, 0}
2829 #undef TARGET_COMP_TYPE_ATTRIBUTES
2830 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
2832 m32c_comp_type_attributes (tree type1 ATTRIBUTE_UNUSED,
2833 tree type2 ATTRIBUTE_UNUSED)
2835 /* 0=incompatible 1=compatible 2=warning */
2839 #undef TARGET_INSERT_ATTRIBUTES
2840 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
2842 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
2843 tree * attr_ptr ATTRIBUTE_UNUSED)
2845 /* Nothing to do here. */
2850 /* This is a list of legal subregs of hard regs. */
2851 static const struct {
2852 unsigned char outer_mode_size;
2853 unsigned char inner_mode_size;
2854 unsigned char byte_mask;
2855 unsigned char legal_when;
2857 } legal_subregs[] = {
2858 {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
2859 {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
2860 {1, 2, 0x01, 1, A0_REGNO},
2861 {1, 2, 0x01, 1, A1_REGNO},
2863 {1, 4, 0x01, 1, A0_REGNO},
2864 {1, 4, 0x01, 1, A1_REGNO},
2866 {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
2867 {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
2868 {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
2869 {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
2870 {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
2872 {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
2875 /* Returns TRUE if OP is a subreg of a hard reg which we don't
2878 m32c_illegal_subreg_p (rtx op)
2882 int src_mode, dest_mode;
2884 if (GET_CODE (op) != SUBREG)
2887 dest_mode = GET_MODE (op);
2888 offset = SUBREG_BYTE (op);
2889 op = SUBREG_REG (op);
2890 src_mode = GET_MODE (op);
2892 if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
2894 if (GET_CODE (op) != REG)
2896 if (REGNO (op) >= MEM0_REGNO)
2899 offset = (1 << offset);
2901 for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
2902 if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
2903 && legal_subregs[i].regno == REGNO (op)
2904 && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
2905 && legal_subregs[i].byte_mask & offset)
2907 switch (legal_subregs[i].legal_when)
2924 /* Returns TRUE if we support a move between the first two operands.
2925 At the moment, we just want to discourage mem to mem moves until
2926 after reload, because reload has a hard time with our limited
2927 number of address registers, and we can get into a situation where
2928 we need three of them when we only have two. */
2930 m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
2932 rtx op0 = operands[0];
2933 rtx op1 = operands[1];
2938 #define DEBUG_MOV_OK 0
2940 fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
2945 if (GET_CODE (op0) == SUBREG)
2946 op0 = XEXP (op0, 0);
2947 if (GET_CODE (op1) == SUBREG)
2948 op1 = XEXP (op1, 0);
2950 if (GET_CODE (op0) == MEM
2951 && GET_CODE (op1) == MEM
2952 && ! reload_completed)
2955 fprintf (stderr, " - no, mem to mem\n");
2961 fprintf (stderr, " - ok\n");
2966 /* Returns TRUE if two consecutive HImode mov instructions, generated
2967 for moving an immediate double data to a double data type variable
2968 location, can be combined into single SImode mov instruction. */
2970 m32c_immd_dbl_mov (rtx * operands,
2971 enum machine_mode mode ATTRIBUTE_UNUSED)
2973 int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
2977 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2978 && MEM_SCALAR_P (operands[0])
2979 && !MEM_IN_STRUCT_P (operands[0])
2980 && GET_CODE (XEXP (operands[2], 0)) == CONST
2981 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
2982 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
2983 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
2984 && MEM_SCALAR_P (operands[2])
2985 && !MEM_IN_STRUCT_P (operands[2]))
2988 else if (GET_CODE (XEXP (operands[0], 0)) == CONST
2989 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
2990 && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
2991 && MEM_SCALAR_P (operands[0])
2992 && !MEM_IN_STRUCT_P (operands[0])
2993 && !(XINT (XEXP (XEXP (XEXP (operands[0], 0), 0), 1), 0) %4)
2994 && GET_CODE (XEXP (operands[2], 0)) == CONST
2995 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
2996 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
2997 && MEM_SCALAR_P (operands[2])
2998 && !MEM_IN_STRUCT_P (operands[2]))
3001 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
3002 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
3003 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
3004 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
3005 && MEM_SCALAR_P (operands[0])
3006 && !MEM_IN_STRUCT_P (operands[0])
3007 && !(XINT (XEXP (XEXP (operands[0], 0), 1), 0) %4)
3008 && REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
3009 && GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
3010 && MEM_SCALAR_P (operands[2])
3011 && !MEM_IN_STRUCT_P (operands[2]))
3020 str1 = XSTR (XEXP (operands[0], 0), 0);
3021 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3022 if (strcmp (str1, str2) == 0)
3028 str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
3029 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3030 if (strcmp(str1,str2) == 0)
3036 offset1 = XINT (XEXP (XEXP (operands[0], 0), 1), 0);
3037 offset2 = XINT (XEXP (XEXP (operands[2], 0), 1), 0);
3038 offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
3039 if (((offset2-offset1) == 2) && offsetsign != 0)
3051 operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
3053 val = (XINT (operands[3], 0) << 16) + (XINT (operands[1], 0) & 0xFFFF);
3054 operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
3064 /* Subregs are non-orthogonal for us, because our registers are all
3067 m32c_subreg (enum machine_mode outer,
3068 rtx x, enum machine_mode inner, int byte)
3072 /* Converting MEMs to different types that are the same size, we
3073 just rewrite them. */
3074 if (GET_CODE (x) == SUBREG
3075 && SUBREG_BYTE (x) == 0
3076 && GET_CODE (SUBREG_REG (x)) == MEM
3077 && (GET_MODE_SIZE (GET_MODE (x))
3078 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3081 x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
3082 MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
3085 /* Push/pop get done as smaller push/pops. */
3086 if (GET_CODE (x) == MEM
3087 && (GET_CODE (XEXP (x, 0)) == PRE_DEC
3088 || GET_CODE (XEXP (x, 0)) == POST_INC))
3089 return gen_rtx_MEM (outer, XEXP (x, 0));
3090 if (GET_CODE (x) == SUBREG
3091 && GET_CODE (XEXP (x, 0)) == MEM
3092 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
3093 || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
3094 return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
3096 if (GET_CODE (x) != REG)
3097 return simplify_gen_subreg (outer, x, inner, byte);
3100 if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
3101 return simplify_gen_subreg (outer, x, inner, byte);
3103 if (IS_MEM_REGNO (r))
3104 return simplify_gen_subreg (outer, x, inner, byte);
3106 /* This is where the complexities of our register layout are
3110 else if (outer == HImode)
3112 if (r == R0_REGNO && byte == 2)
3114 else if (r == R0_REGNO && byte == 4)
3116 else if (r == R0_REGNO && byte == 6)
3118 else if (r == R1_REGNO && byte == 2)
3120 else if (r == A0_REGNO && byte == 2)
3123 else if (outer == SImode)
3125 if (r == R0_REGNO && byte == 0)
3127 else if (r == R0_REGNO && byte == 4)
3132 fprintf (stderr, "m32c_subreg %s %s %d\n",
3133 mode_name[outer], mode_name[inner], byte);
3137 return gen_rtx_REG (outer, nr);
3140 /* Used to emit move instructions. We split some moves,
3141 and avoid mem-mem moves. */
3143 m32c_prepare_move (rtx * operands, enum machine_mode mode)
3145 if (TARGET_A16 && mode == PSImode)
3146 return m32c_split_move (operands, mode, 1);
3147 if ((GET_CODE (operands[0]) == MEM)
3148 && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
3150 rtx pmv = XEXP (operands[0], 0);
3151 rtx dest_reg = XEXP (pmv, 0);
3152 rtx dest_mod = XEXP (pmv, 1);
3154 emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
3155 operands[0] = gen_rtx_MEM (mode, dest_reg);
3157 if (!no_new_pseudos && MEM_P (operands[0]) && MEM_P (operands[1]))
3158 operands[1] = copy_to_mode_reg (mode, operands[1]);
3162 #define DEBUG_SPLIT 0
3164 /* Returns TRUE if the given PSImode move should be split. We split
3165 for all r8c/m16c moves, since it doesn't support them, and for
3166 POP.L as we can only *push* SImode. */
3168 m32c_split_psi_p (rtx * operands)
3171 fprintf (stderr, "\nm32c_split_psi_p\n");
3172 debug_rtx (operands[0]);
3173 debug_rtx (operands[1]);
3178 fprintf (stderr, "yes, A16\n");
3182 if (GET_CODE (operands[1]) == MEM
3183 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3186 fprintf (stderr, "yes, pop.l\n");
3191 fprintf (stderr, "no, default\n");
3196 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
3197 (define_expand), 1 if it is not optional (define_insn_and_split),
3198 and 3 for define_split (alternate api). */
3200 m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
3203 int parts, si, di, rev = 0;
3204 int rv = 0, opi = 2;
3205 enum machine_mode submode = HImode;
3206 rtx *ops, local_ops[10];
3208 /* define_split modifies the existing operands, but the other two
3209 emit new insns. OPS is where we store the operand pairs, which
3220 /* Before splitting mem-mem moves, force one operand into a
3222 if (!no_new_pseudos && MEM_P (operands[0]) && MEM_P (operands[1]))
3225 fprintf (stderr, "force_reg...\n");
3226 debug_rtx (operands[1]);
3228 operands[1] = force_reg (mode, operands[1]);
3230 debug_rtx (operands[1]);
3237 fprintf (stderr, "\nsplit_move %d all=%d\n", no_new_pseudos, split_all);
3238 debug_rtx (operands[0]);
3239 debug_rtx (operands[1]);
3242 /* Note that split_all is not used to select the api after this
3243 point, so it's safe to set it to 3 even with define_insn. */
3244 /* None of the chips can move SI operands to sp-relative addresses,
3245 so we always split those. */
3246 if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
3249 /* We don't need to split these. */
3252 && (mode == SImode || mode == PSImode)
3253 && !(GET_CODE (operands[1]) == MEM
3254 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3257 /* First, enumerate the subregs we'll be dealing with. */
3258 for (si = 0; si < parts; si++)
3261 m32c_subreg (submode, operands[0], mode,
3262 si * GET_MODE_SIZE (submode));
3264 m32c_subreg (submode, operands[1], mode,
3265 si * GET_MODE_SIZE (submode));
3268 /* Split pushes by emitting a sequence of smaller pushes. */
3269 if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
3271 for (si = parts - 1; si >= 0; si--)
3273 ops[opi++] = gen_rtx_MEM (submode,
3274 gen_rtx_PRE_DEC (Pmode,
3282 /* Likewise for pops. */
3283 else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
3285 for (di = 0; di < parts; di++)
3288 ops[opi++] = gen_rtx_MEM (submode,
3289 gen_rtx_POST_INC (Pmode,
3297 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3298 for (di = 0; di < parts - 1; di++)
3299 for (si = di + 1; si < parts; si++)
3300 if (reg_mentioned_p (d[di], s[si]))
3304 for (si = 0; si < parts; si++)
3310 for (si = parts - 1; si >= 0; si--)
3317 /* Now emit any moves we may have accumulated. */
3318 if (rv && split_all != 3)
3321 for (i = 2; i < opi; i += 2)
3322 emit_move_insn (ops[i], ops[i + 1]);
3327 /* The m32c has a number of opcodes that act like memcpy, strcmp, and
3328 the like. For the R8C they expect one of the addresses to be in
3329 R1L:An so we need to arrange for that. Otherwise, it's just a
3330 matter of picking out the operands we want and emitting the right
3331 pattern for them. All these expanders, which correspond to
3332 patterns in blkmov.md, must return nonzero if they expand the insn,
3333 or zero if they should FAIL. */
3335 /* This is a memset() opcode. All operands are implied, so we need to
3336 arrange for them to be in the right registers. The opcode wants
3337 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3338 the count (HI), and $2 the value (QI). */
3340 m32c_expand_setmemhi(rtx *operands)
3342 rtx desta, count, val;
3345 desta = XEXP (operands[0], 0);
3346 count = operands[1];
3349 desto = gen_reg_rtx (Pmode);
3350 counto = gen_reg_rtx (HImode);
3352 if (GET_CODE (desta) != REG
3353 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3354 desta = copy_to_mode_reg (Pmode, desta);
3356 /* This looks like an arbitrary restriction, but this is by far the
3357 most common case. For counts 8..14 this actually results in
3358 smaller code with no speed penalty because the half-sized
3359 constant can be loaded with a shorter opcode. */
3360 if (GET_CODE (count) == CONST_INT
3361 && GET_CODE (val) == CONST_INT
3362 && ! (INTVAL (count) & 1)
3363 && (INTVAL (count) > 1)
3364 && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
3366 unsigned v = INTVAL (val) & 0xff;
3368 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3369 val = copy_to_mode_reg (HImode, GEN_INT (v));
3371 emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
3373 emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
3377 /* This is the generalized memset() case. */
3378 if (GET_CODE (val) != REG
3379 || REGNO (val) < FIRST_PSEUDO_REGISTER)
3380 val = copy_to_mode_reg (QImode, val);
3382 if (GET_CODE (count) != REG
3383 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3384 count = copy_to_mode_reg (HImode, count);
3387 emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
3389 emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
3394 /* This is a memcpy() opcode. All operands are implied, so we need to
3395 arrange for them to be in the right registers. The opcode wants
3396 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3397 is the source (MEM:BLK), and $2 the count (HI). */
3399 m32c_expand_movmemhi(rtx *operands)
3401 rtx desta, srca, count;
3402 rtx desto, srco, counto;
3404 desta = XEXP (operands[0], 0);
3405 srca = XEXP (operands[1], 0);
3406 count = operands[2];
3408 desto = gen_reg_rtx (Pmode);
3409 srco = gen_reg_rtx (Pmode);
3410 counto = gen_reg_rtx (HImode);
3412 if (GET_CODE (desta) != REG
3413 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3414 desta = copy_to_mode_reg (Pmode, desta);
3416 if (GET_CODE (srca) != REG
3417 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3418 srca = copy_to_mode_reg (Pmode, srca);
3420 /* Similar to setmem, but we don't need to check the value. */
3421 if (GET_CODE (count) == CONST_INT
3422 && ! (INTVAL (count) & 1)
3423 && (INTVAL (count) > 1))
3425 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3427 emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
3429 emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
3433 /* This is the generalized memset() case. */
3434 if (GET_CODE (count) != REG
3435 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3436 count = copy_to_mode_reg (HImode, count);
3439 emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
3441 emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
3446 /* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3447 the copy, which should point to the NUL at the end of the string,
3448 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3449 Since our opcode leaves the destination pointing *after* the NUL,
3450 we must emit an adjustment. */
3452 m32c_expand_movstr(rtx *operands)
3457 desta = XEXP (operands[1], 0);
3458 srca = XEXP (operands[2], 0);
3460 desto = gen_reg_rtx (Pmode);
3461 srco = gen_reg_rtx (Pmode);
3463 if (GET_CODE (desta) != REG
3464 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3465 desta = copy_to_mode_reg (Pmode, desta);
3467 if (GET_CODE (srca) != REG
3468 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3469 srca = copy_to_mode_reg (Pmode, srca);
3471 emit_insn (gen_movstr_op (desto, srco, desta, srca));
3472 /* desto ends up being a1, which allows this type of add through MOVA. */
3473 emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
3478 /* This is a strcmp() opcode. $0 is the destination (HI) which holds
3479 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3480 $2 is the other (MEM:BLK). We must do the comparison, and then
3481 convert the flags to a signed integer result. */
3483 m32c_expand_cmpstr(rtx *operands)
3487 src1a = XEXP (operands[1], 0);
3488 src2a = XEXP (operands[2], 0);
3490 if (GET_CODE (src1a) != REG
3491 || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
3492 src1a = copy_to_mode_reg (Pmode, src1a);
3494 if (GET_CODE (src2a) != REG
3495 || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
3496 src2a = copy_to_mode_reg (Pmode, src2a);
3498 emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
3499 emit_insn (gen_cond_to_int (operands[0]));
3505 typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
3507 static shift_gen_func
3508 shift_gen_func_for (int mode, int code)
3510 #define GFF(m,c,f) if (mode == m && code == c) return f
3511 GFF(QImode, ASHIFT, gen_ashlqi3_i);
3512 GFF(QImode, ASHIFTRT, gen_ashrqi3_i);
3513 GFF(QImode, LSHIFTRT, gen_lshrqi3_i);
3514 GFF(HImode, ASHIFT, gen_ashlhi3_i);
3515 GFF(HImode, ASHIFTRT, gen_ashrhi3_i);
3516 GFF(HImode, LSHIFTRT, gen_lshrhi3_i);
3517 GFF(PSImode, ASHIFT, gen_ashlpsi3_i);
3518 GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
3519 GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
3520 GFF(SImode, ASHIFT, TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
3521 GFF(SImode, ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
3522 GFF(SImode, LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
3527 /* The m32c only has one shift, but it takes a signed count. GCC
3528 doesn't want this, so we fake it by negating any shift count when
3529 we're pretending to shift the other way. Also, the shift count is
3530 limited to -8..8. It's slightly better to use two shifts for 9..15
3531 than to load the count into r1h, so we do that too. */
3533 m32c_prepare_shift (rtx * operands, int scale, int shift_code)
3535 enum machine_mode mode = GET_MODE (operands[0]);
3536 shift_gen_func func = shift_gen_func_for (mode, shift_code);
3539 if (GET_CODE (operands[2]) == CONST_INT)
3541 int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
3542 int count = INTVAL (operands[2]) * scale;
3544 while (count > maxc)
3546 temp = gen_reg_rtx (mode);
3547 emit_insn (func (temp, operands[1], GEN_INT (maxc)));
3551 while (count < -maxc)
3553 temp = gen_reg_rtx (mode);
3554 emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
3558 emit_insn (func (operands[0], operands[1], GEN_INT (count)));
3562 temp = gen_reg_rtx (QImode);
3564 /* The pattern has a NEG that corresponds to this. */
3565 emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
3566 else if (TARGET_A16 && mode == SImode)
3567 /* We do this because the code below may modify this, we don't
3568 want to modify the origin of this value. */
3569 emit_move_insn (temp, operands[2]);
3571 /* We'll only use it for the shift, no point emitting a move. */
3574 if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
3576 /* The m16c has a limit of -16..16 for SI shifts, even when the
3577 shift count is in a register. Since there are so many targets
3578 of these shifts, it's better to expand the RTL here than to
3579 call a helper function.
3581 The resulting code looks something like this:
3593 We take advantage of the fact that "negative" shifts are
3594 undefined to skip one of the comparisons. */
3597 rtx label, lref, insn, tempvar;
3599 emit_move_insn (operands[0], operands[1]);
3602 label = gen_label_rtx ();
3603 lref = gen_rtx_LABEL_REF (VOIDmode, label);
3604 LABEL_NUSES (label) ++;
3606 tempvar = gen_reg_rtx (mode);
3608 if (shift_code == ASHIFT)
3610 /* This is a left shift. We only need check positive counts. */
3611 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
3612 count, GEN_INT (16), label));
3613 emit_insn (func (tempvar, operands[0], GEN_INT (8)));
3614 emit_insn (func (operands[0], tempvar, GEN_INT (8)));
3615 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
3616 emit_label_after (label, insn);
3620 /* This is a right shift. We only need check negative counts. */
3621 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
3622 count, GEN_INT (-16), label));
3623 emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
3624 emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
3625 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
3626 emit_label_after (label, insn);
3628 operands[1] = operands[0];
3629 emit_insn (func (operands[0], operands[0], count));
3637 /* The m32c has a limited range of operations that work on PSImode
3638 values; we have to expand to SI, do the math, and truncate back to
3639 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3642 m32c_expand_neg_mulpsi3 (rtx * operands)
3644 /* operands: a = b * i */
3645 rtx temp1; /* b as SI */
3646 rtx scale /* i as SI */;
3647 rtx temp2; /* a*b as SI */
3649 temp1 = gen_reg_rtx (SImode);
3650 temp2 = gen_reg_rtx (SImode);
3651 if (GET_CODE (operands[2]) != CONST_INT)
3653 scale = gen_reg_rtx (SImode);
3654 emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
3657 scale = copy_to_mode_reg (SImode, operands[2]);
3659 emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
3660 temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
3661 emit_insn (gen_truncsipsi2 (operands[0], temp2));
3664 static rtx compare_op0, compare_op1;
3667 m32c_pend_compare (rtx *operands)
3669 compare_op0 = operands[0];
3670 compare_op1 = operands[1];
3674 m32c_unpend_compare (void)
3676 switch (GET_MODE (compare_op0))
3679 emit_insn (gen_cmpqi_op (compare_op0, compare_op1));
3681 emit_insn (gen_cmphi_op (compare_op0, compare_op1));
3683 emit_insn (gen_cmppsi_op (compare_op0, compare_op1));
3685 /* Just to silence the "missing case" warnings. */ ;
3690 m32c_expand_scc (int code, rtx *operands)
3692 enum machine_mode mode = TARGET_A16 ? QImode : HImode;
3694 emit_insn (gen_rtx_SET (mode,
3696 gen_rtx_fmt_ee (code,
3702 /* Pattern Output Functions */
3704 /* Returns a (OP (reg:CC FLG_REGNO) (const_int 0)) from some other
3705 match_operand rtx's OP. */
3707 m32c_cmp_flg_0 (rtx cmp)
3709 return gen_rtx_fmt_ee (GET_CODE (cmp),
3711 gen_rtx_REG (CCmode, FLG_REGNO),
3716 m32c_expand_movcc (rtx *operands)
3718 rtx rel = operands[1];
3721 if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
3723 if (GET_CODE (operands[2]) != CONST_INT
3724 || GET_CODE (operands[3]) != CONST_INT)
3726 emit_insn (gen_cmpqi(XEXP (rel, 0), XEXP (rel, 1)));
3727 if (GET_CODE (rel) == NE)
3729 rtx tmp = operands[2];
3730 operands[2] = operands[3];
3734 cmp = gen_rtx_fmt_ee (GET_CODE (rel),
3739 emit_move_insn (operands[0],
3740 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3747 /* Used for the "insv" pattern. Return nonzero to fail, else done. */
3749 m32c_expand_insv (rtx *operands)
3754 if (INTVAL (operands[1]) != 1)
3757 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3758 if (GET_CODE (operands[3]) != CONST_INT)
3760 if (INTVAL (operands[3]) != 0
3761 && INTVAL (operands[3]) != 1
3762 && INTVAL (operands[3]) != -1)
3765 mask = 1 << INTVAL (operands[2]);
3768 if (GET_CODE (op0) == SUBREG
3769 && SUBREG_BYTE (op0) == 0)
3771 rtx sub = SUBREG_REG (op0);
3772 if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
3777 || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
3781 src0 = gen_reg_rtx (GET_MODE (op0));
3782 emit_move_insn (src0, op0);
3785 if (GET_MODE (op0) == HImode
3786 && INTVAL (operands[2]) >= 8
3787 && GET_MODE (op0) == MEM)
3789 /* We are little endian. */
3790 rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
3791 MEM_COPY_ATTRIBUTES (new_mem, op0);
3795 /* First, we generate a mask with the correct polarity. If we are
3796 storing a zero, we want an AND mask, so invert it. */
3797 if (INTVAL (operands[3]) == 0)
3799 /* Storing a zero, use an AND mask */
3800 if (GET_MODE (op0) == HImode)
3805 /* Now we need to properly sign-extend the mask in case we need to
3806 fall back to an AND or OR opcode. */
3807 if (GET_MODE (op0) == HImode)
3818 switch ( (INTVAL (operands[3]) ? 4 : 0)
3819 + ((GET_MODE (op0) == HImode) ? 2 : 0)
3820 + (TARGET_A24 ? 1 : 0))
3822 case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
3823 case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
3824 case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
3825 case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
3826 case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
3827 case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
3828 case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
3829 case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
3837 m32c_scc_pattern(rtx *operands, RTX_CODE code)
3839 static char buf[30];
3840 if (GET_CODE (operands[0]) == REG
3841 && REGNO (operands[0]) == R0_REGNO)
3844 return "stzx\t#1,#0,r0l";
3846 return "stzx\t#0,#1,r0l";
3848 sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
3852 /* Encode symbol attributes of a SYMBOL_REF into its
3853 SYMBOL_REF_FLAGS. */
3855 m32c_encode_section_info (tree decl, rtx rtl, int first)
3857 int extra_flags = 0;
3859 default_encode_section_info (decl, rtl, first);
3860 if (TREE_CODE (decl) == FUNCTION_DECL
3861 && m32c_special_page_vector_p (decl))
3863 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
3866 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
3869 /* Returns TRUE if the current function is a leaf, and thus we can
3870 determine which registers an interrupt function really needs to
3871 save. The logic below is mostly about finding the insn sequence
3872 that's the function, versus any sequence that might be open for the
3875 m32c_leaf_function_p (void)
3877 rtx saved_first, saved_last;
3878 struct sequence_stack *seq;
3881 saved_first = cfun->emit->x_first_insn;
3882 saved_last = cfun->emit->x_last_insn;
3883 for (seq = cfun->emit->sequence_stack; seq && seq->next; seq = seq->next)
3887 cfun->emit->x_first_insn = seq->first;
3888 cfun->emit->x_last_insn = seq->last;
3891 rv = leaf_function_p ();
3893 cfun->emit->x_first_insn = saved_first;
3894 cfun->emit->x_last_insn = saved_last;
3898 /* Returns TRUE if the current function needs to use the ENTER/EXIT
3899 opcodes. If the function doesn't need the frame base or stack
3900 pointer, it can use the simpler RTS opcode. */
3902 m32c_function_needs_enter (void)
3905 struct sequence_stack *seq;
3906 rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
3907 rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
3909 insn = get_insns ();
3910 for (seq = cfun->emit->sequence_stack;
3912 insn = seq->first, seq = seq->next);
3916 if (reg_mentioned_p (sp, insn))
3918 if (reg_mentioned_p (fb, insn))
3920 insn = NEXT_INSN (insn);
3925 /* Mark all the subexpressions of the PARALLEL rtx PAR as
3926 frame-related. Return PAR.
3928 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
3929 PARALLEL rtx other than the first if they do not have the
3930 FRAME_RELATED flag set on them. So this function is handy for
3931 marking up 'enter' instructions. */
3933 m32c_all_frame_related (rtx par)
3935 int len = XVECLEN (par, 0);
3938 for (i = 0; i < len; i++)
3939 F (XVECEXP (par, 0, i));
3944 /* Emits the prologue. See the frame layout comment earlier in this
3945 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
3946 that we manually update sp. */
3948 m32c_emit_prologue (void)
3950 int frame_size, extra_frame_size = 0, reg_save_size;
3951 int complex_prologue = 0;
3953 cfun->machine->is_leaf = m32c_leaf_function_p ();
3954 if (interrupt_p (cfun->decl))
3956 cfun->machine->is_interrupt = 1;
3957 complex_prologue = 1;
3960 reg_save_size = m32c_pushm_popm (PP_justcount);
3962 if (interrupt_p (cfun->decl))
3963 emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
3966 m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
3968 && !cfun->machine->is_interrupt
3969 && !m32c_function_needs_enter ())
3970 cfun->machine->use_rts = 1;
3972 if (frame_size > 254)
3974 extra_frame_size = frame_size - 254;
3977 if (cfun->machine->use_rts == 0)
3978 F (emit_insn (m32c_all_frame_related
3980 ? gen_prologue_enter_16 (GEN_INT (frame_size))
3981 : gen_prologue_enter_24 (GEN_INT (frame_size)))));
3983 if (extra_frame_size)
3985 complex_prologue = 1;
3987 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
3988 gen_rtx_REG (HImode, SP_REGNO),
3989 GEN_INT (-extra_frame_size))));
3991 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
3992 gen_rtx_REG (PSImode, SP_REGNO),
3993 GEN_INT (-extra_frame_size))));
3996 complex_prologue += m32c_pushm_popm (PP_pushm);
3998 /* This just emits a comment into the .s file for debugging. */
3999 if (complex_prologue)
4000 emit_insn (gen_prologue_end ());
4003 /* Likewise, for the epilogue. The only exception is that, for
4004 interrupts, we must manually unwind the frame as the REIT opcode
4007 m32c_emit_epilogue (void)
4009 /* This just emits a comment into the .s file for debugging. */
4010 if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
4011 emit_insn (gen_epilogue_start ());
4013 m32c_pushm_popm (PP_popm);
4015 if (cfun->machine->is_interrupt)
4017 enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
4019 emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
4020 gen_rtx_REG (spmode, FP_REGNO));
4021 emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
4022 gen_rtx_REG (spmode, A0_REGNO));
4024 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
4026 emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
4027 emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
4028 emit_jump_insn (gen_epilogue_reit (GEN_INT (TARGET_A16 ? 4 : 6)));
4030 else if (cfun->machine->use_rts)
4031 emit_jump_insn (gen_epilogue_rts ());
4033 emit_jump_insn (gen_epilogue_exitd (GEN_INT (TARGET_A16 ? 2 : 4)));
4038 m32c_emit_eh_epilogue (rtx ret_addr)
4040 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4041 return to. We have to fudge the stack, pop everything, pop SP
4042 (fudged), and return (fudged). This is actually easier to do in
4043 assembler, so punt to libgcc. */
4044 emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
4045 /* emit_insn (gen_rtx_CLOBBER (HImode, gen_rtx_REG (HImode, R0L_REGNO))); */
4049 /* Indicate which flags must be properly set for a given conditional. */
4051 flags_needed_for_conditional (rtx cond)
4053 switch (GET_CODE (cond))
4077 /* Returns true if a compare insn is redundant because it would only
4078 set flags that are already set correctly. */
4080 m32c_compare_redundant (rtx cmp, rtx *operands)
4095 fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
4099 fprintf(stderr, "operands[%d] = ", i);
4100 debug_rtx(operands[i]);
4104 next = next_nonnote_insn (cmp);
4105 if (!next || !INSN_P (next))
4108 fprintf(stderr, "compare not followed by insn\n");
4113 if (GET_CODE (PATTERN (next)) == SET
4114 && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
4116 next = XEXP (XEXP (PATTERN (next), 1), 0);
4118 else if (GET_CODE (PATTERN (next)) == SET)
4120 /* If this is a conditional, flags_needed will be something
4121 other than FLAGS_N, which we test below. */
4122 next = XEXP (PATTERN (next), 1);
4127 fprintf(stderr, "compare not followed by conditional\n");
4133 fprintf(stderr, "conditional is: ");
4137 flags_needed = flags_needed_for_conditional (next);
4138 if (flags_needed == FLAGS_N)
4141 fprintf(stderr, "compare not followed by conditional\n");
4147 /* Compare doesn't set overflow and carry the same way that
4148 arithmetic instructions do, so we can't replace those. */
4149 if (flags_needed & FLAGS_OC)
4154 prev = prev_nonnote_insn (prev);
4158 fprintf(stderr, "No previous insn.\n");
4165 fprintf(stderr, "Previous insn is a non-insn.\n");
4169 pp = PATTERN (prev);
4170 if (GET_CODE (pp) != SET)
4173 fprintf(stderr, "Previous insn is not a SET.\n");
4177 pflags = get_attr_flags (prev);
4179 /* Looking up attributes of previous insns corrupted the recog
4181 INSN_UID (cmp) = -1;
4182 recog (PATTERN (cmp), cmp, 0);
4184 if (pflags == FLAGS_N
4185 && reg_mentioned_p (op0, pp))
4188 fprintf(stderr, "intermediate non-flags insn uses op:\n");
4193 } while (pflags == FLAGS_N);
4195 fprintf(stderr, "previous flag-setting insn:\n");
4200 if (GET_CODE (pp) == SET
4201 && GET_CODE (XEXP (pp, 0)) == REG
4202 && REGNO (XEXP (pp, 0)) == FLG_REGNO
4203 && GET_CODE (XEXP (pp, 1)) == COMPARE)
4205 /* Adjacent cbranches must have the same operands to be
4207 rtx pop0 = XEXP (XEXP (pp, 1), 0);
4208 rtx pop1 = XEXP (XEXP (pp, 1), 1);
4210 fprintf(stderr, "adjacent cbranches\n");
4214 if (rtx_equal_p (op0, pop0)
4215 && rtx_equal_p (op1, pop1))
4218 fprintf(stderr, "prev cmp not same\n");
4223 /* Else the previous insn must be a SET, with either the source or
4224 dest equal to operands[0], and operands[1] must be zero. */
4226 if (!rtx_equal_p (op1, const0_rtx))
4229 fprintf(stderr, "operands[1] not const0_rtx\n");
4233 if (GET_CODE (pp) != SET)
4236 fprintf (stderr, "pp not set\n");
4240 if (!rtx_equal_p (op0, SET_SRC (pp))
4241 && !rtx_equal_p (op0, SET_DEST (pp)))
4244 fprintf(stderr, "operands[0] not found in set\n");
4250 fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
4252 if ((pflags & flags_needed) == flags_needed)
4258 /* Return the pattern for a compare. This will be commented out if
4259 the compare is redundant, else a normal pattern is returned. Thus,
4260 the assembler output says where the compare would have been. */
4262 m32c_output_compare (rtx insn, rtx *operands)
4264 static char template[] = ";cmp.b\t%1,%0";
4267 template[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
4268 if (m32c_compare_redundant (insn, operands))
4271 fprintf(stderr, "cbranch: cmp not needed\n");
4277 fprintf(stderr, "cbranch: cmp needed: `%s'\n", template);
4279 return template + 1;
4282 #undef TARGET_ENCODE_SECTION_INFO
4283 #define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4285 /* The Global `targetm' Variable. */
4287 struct gcc_target targetm = TARGET_INITIALIZER;
4289 #include "gt-m32c.h"