1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
24 /* ??? Look at ABI group documents for list of preprocessor macros and
25 other features required for ABI compliance. */
27 /* ??? Functions containing a non-local goto target save many registers. Why?
28 See for instance execute/920428-2.c. */
31 /* Run-time target specifications */
33 /* Target CPU builtins. */
34 #define TARGET_CPU_CPP_BUILTINS() \
36 builtin_assert("cpu=ia64"); \
37 builtin_assert("machine=ia64"); \
38 builtin_define("__ia64"); \
39 builtin_define("__ia64__"); \
40 builtin_define("__itanium__"); \
41 if (TARGET_BIG_ENDIAN) \
42 builtin_define("__BIG_ENDIAN__"); \
45 #ifndef SUBTARGET_EXTRA_SPECS
46 #define SUBTARGET_EXTRA_SPECS
50 { "asm_extra", ASM_EXTRA_SPEC }, \
53 #define CC1_SPEC "%(cc1_cpu) "
55 #define ASM_EXTRA_SPEC ""
57 /* Variables which are this size or smaller are put in the sdata/sbss
59 extern unsigned int ia64_section_threshold;
61 /* If the assembler supports thread-local storage, assume that the
62 system does as well. If a particular target system has an
63 assembler that supports TLS -- but the rest of the system does not
64 support TLS -- that system should explicit define TARGET_HAVE_TLS
65 to false in its own configuration file. */
66 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
67 #define TARGET_HAVE_TLS true
70 #define TARGET_TLS14 (ia64_tls_size == 14)
71 #define TARGET_TLS22 (ia64_tls_size == 22)
72 #define TARGET_TLS64 (ia64_tls_size == 64)
75 #define TARGET_HPUX_LD 0
78 #define TARGET_ILP32 0
81 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
82 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
85 /* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and
86 TARGET_INLINE_SQRT. */
95 /* Default target_flags if no switches are specified */
97 #ifndef TARGET_DEFAULT
98 #define TARGET_DEFAULT (MASK_DWARF2_ASM)
101 #ifndef TARGET_CPU_DEFAULT
102 #define TARGET_CPU_DEFAULT 0
105 /* Which processor to schedule for. The cpu attribute defines a list
106 that mirrors this list, so changes to ia64.md must be made at the
111 PROCESSOR_ITANIUM, /* Original Itanium. */
116 extern enum processor_type ia64_tune;
118 /* Sometimes certain combinations of command options do not make sense on a
119 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
120 take account of this. This macro, if defined, is executed once just after
121 all the command options have been parsed. */
123 #define OVERRIDE_OPTIONS ia64_override_options ()
125 /* Some machines may desire to change what optimizations are performed for
126 various optimization levels. This macro, if defined, is executed once just
127 after the optimization level is determined and before the remainder of the
128 command options have been parsed. Values set in this macro are used as the
129 default values for the other command line options. */
131 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
133 /* Driver configuration */
135 /* A C string constant that tells the GCC driver program options to pass to
136 `cc1'. It can also specify how to translate options you give to GCC into
137 options for GCC to pass to the `cc1'. */
140 #define CC1_SPEC "%{G*}"
142 /* A C string constant that tells the GCC driver program options to pass to
143 `cc1plus'. It can also specify how to translate options you give to GCC
144 into options for GCC to pass to the `cc1plus'. */
146 /* #define CC1PLUS_SPEC "" */
150 /* Define this macro to have the value 1 if the most significant bit in a byte
151 has the lowest number; otherwise define it to have the value zero. */
153 #define BITS_BIG_ENDIAN 0
155 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
157 /* Define this macro to have the value 1 if, in a multiword object, the most
158 significant word has the lowest number. */
160 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
162 #if defined(__BIG_ENDIAN__)
163 #define LIBGCC2_WORDS_BIG_ENDIAN 1
165 #define LIBGCC2_WORDS_BIG_ENDIAN 0
168 #define UNITS_PER_WORD 8
170 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
172 /* A C expression whose value is zero if pointers that need to be extended
173 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
174 they are zero-extended and negative one if there is a ptr_extend operation.
176 You need not define this macro if the `POINTER_SIZE' is equal to the width
178 /* Need this for 32 bit pointers, see hpux.h for setting it. */
179 /* #define POINTERS_EXTEND_UNSIGNED */
181 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
182 which has the specified mode and signedness is to be stored in a register.
183 This macro is only called when TYPE is a scalar type. */
184 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
187 if (GET_MODE_CLASS (MODE) == MODE_INT \
188 && GET_MODE_SIZE (MODE) < 4) \
193 #define PARM_BOUNDARY 64
195 /* Define this macro if you wish to preserve a certain alignment for the stack
196 pointer. The definition is a C expression for the desired alignment
197 (measured in bits). */
199 #define STACK_BOUNDARY 128
201 /* Align frames on double word boundaries */
202 #ifndef IA64_STACK_ALIGN
203 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
206 #define FUNCTION_BOUNDARY 128
208 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
209 128 bit integers all require 128 bit alignment. */
210 #define BIGGEST_ALIGNMENT 128
212 /* If defined, a C expression to compute the alignment for a static variable.
213 TYPE is the data type, and ALIGN is the alignment that the object
214 would ordinarily have. The value of this macro is used instead of that
215 alignment to align the object. */
217 #define DATA_ALIGNMENT(TYPE, ALIGN) \
218 (TREE_CODE (TYPE) == ARRAY_TYPE \
219 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
220 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
222 /* If defined, a C expression to compute the alignment given to a constant that
223 is being placed in memory. CONSTANT is the constant and ALIGN is the
224 alignment that the object would ordinarily have. The value of this macro is
225 used instead of that alignment to align the object. */
227 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
228 (TREE_CODE (EXP) == STRING_CST \
229 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
231 #define STRICT_ALIGNMENT 1
233 /* Define this if you wish to imitate the way many other C compilers handle
234 alignment of bitfields and the structures that contain them.
235 The behavior is that the type written for a bit-field (`int', `short', or
236 other integer type) imposes an alignment for the entire structure, as if the
237 structure really did contain an ordinary field of that type. In addition,
238 the bit-field is placed within the structure so that it would fit within such
239 a field, not crossing a boundary for it. */
240 #define PCC_BITFIELD_TYPE_MATTERS 1
242 /* An integer expression for the size in bits of the largest integer machine
243 mode that should actually be used. */
245 /* Allow pairs of registers to be used, which is the intent of the default. */
246 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
248 /* By default, the C++ compiler will use function addresses in the
249 vtable entries. Setting this nonzero tells the compiler to use
250 function descriptors instead. The value of this macro says how
251 many words wide the descriptor is (normally 2). It is assumed
252 that the address of a function descriptor may be treated as a
253 pointer to a function.
255 For reasons known only to HP, the vtable entries (as opposed to
256 normal function descriptors) are 16 bytes wide in 32-bit mode as
257 well, even though the 3rd and 4th words are unused. */
258 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
260 /* Due to silliness in the HPUX linker, vtable entries must be
261 8-byte aligned even in 32-bit mode. Rather than create multiple
262 ABIs, force this restriction on everyone else too. */
263 #define TARGET_VTABLE_ENTRY_ALIGN 64
265 /* Due to the above, we need extra padding for the data entries below 0
266 to retain the alignment of the descriptors. */
267 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
269 /* Layout of Source Language Data Types */
271 #define INT_TYPE_SIZE 32
273 #define SHORT_TYPE_SIZE 16
275 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
277 #define LONG_LONG_TYPE_SIZE 64
279 #define FLOAT_TYPE_SIZE 32
281 #define DOUBLE_TYPE_SIZE 64
283 /* long double is XFmode normally, TFmode for HPUX. */
284 #define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 80)
286 /* We always want the XFmode operations from libgcc2.c. */
287 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
289 #define DEFAULT_SIGNED_CHAR 1
291 /* A C expression for a string describing the name of the data type to use for
292 size values. The typedef name `size_t' is defined using the contents of the
294 /* ??? Needs to be defined for P64 code. */
295 /* #define SIZE_TYPE */
297 /* A C expression for a string describing the name of the data type to use for
298 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
299 defined using the contents of the string. See `SIZE_TYPE' above for more
301 /* ??? Needs to be defined for P64 code. */
302 /* #define PTRDIFF_TYPE */
304 /* A C expression for a string describing the name of the data type to use for
305 wide characters. The typedef name `wchar_t' is defined using the contents
306 of the string. See `SIZE_TYPE' above for more information. */
307 /* #define WCHAR_TYPE */
309 /* A C expression for the size in bits of the data type for wide characters.
310 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
311 /* #define WCHAR_TYPE_SIZE */
314 /* Register Basics */
316 /* Number of hardware registers known to the compiler.
317 We have 128 general registers, 128 floating point registers,
318 64 predicate registers, 8 branch registers, one frame pointer,
319 and several "application" registers. */
321 #define FIRST_PSEUDO_REGISTER 334
323 /* Ranges for the various kinds of registers. */
324 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
325 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
326 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
327 #define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159)
328 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
329 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
330 #define GENERAL_REGNO_P(REGNO) \
331 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
333 #define GR_REG(REGNO) ((REGNO) + 0)
334 #define FR_REG(REGNO) ((REGNO) + 128)
335 #define PR_REG(REGNO) ((REGNO) + 256)
336 #define BR_REG(REGNO) ((REGNO) + 320)
337 #define OUT_REG(REGNO) ((REGNO) + 120)
338 #define IN_REG(REGNO) ((REGNO) + 112)
339 #define LOC_REG(REGNO) ((REGNO) + 32)
341 #define AR_CCV_REGNUM 329
342 #define AR_UNAT_REGNUM 330
343 #define AR_PFS_REGNUM 331
344 #define AR_LC_REGNUM 332
345 #define AR_EC_REGNUM 333
347 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
348 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
349 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
351 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
352 || (REGNO) == AR_UNAT_REGNUM)
353 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
354 && (REGNO) < FIRST_PSEUDO_REGISTER)
355 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
356 && (REGNO) < FIRST_PSEUDO_REGISTER)
359 /* ??? Don't really need two sets of macros. I like this one better because
360 it is less typing. */
361 #define R_GR(REGNO) GR_REG (REGNO)
362 #define R_FR(REGNO) FR_REG (REGNO)
363 #define R_PR(REGNO) PR_REG (REGNO)
364 #define R_BR(REGNO) BR_REG (REGNO)
366 /* An initializer that says which registers are used for fixed purposes all
367 throughout the compiled code and are therefore not available for general
371 r1: global pointer (gp)
372 r12: stack pointer (sp)
373 r13: thread pointer (tp)
377 fp: eliminable frame pointer */
379 /* The last 16 stacked regs are reserved for the 8 input and 8 output
382 #define FIXED_REGISTERS \
383 { /* General registers. */ \
384 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
385 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
386 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
387 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
388 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
389 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
390 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
391 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
392 /* Floating-point registers. */ \
393 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
394 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
395 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
396 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
397 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
398 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
399 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
400 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
401 /* Predicate registers. */ \
402 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
403 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
404 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
405 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
406 /* Branch registers. */ \
407 0, 0, 0, 0, 0, 0, 0, 0, \
408 /*FP CCV UNAT PFS LC EC */ \
412 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
413 (in general) by function calls as well as for fixed registers. This
414 macro therefore identifies the registers that are not available for
415 general allocation of values that must live across function calls. */
417 #define CALL_USED_REGISTERS \
418 { /* General registers. */ \
419 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
420 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
421 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
422 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
423 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
424 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
425 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
426 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
427 /* Floating-point registers. */ \
428 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
429 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
430 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
431 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
432 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
434 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
436 /* Predicate registers. */ \
437 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
438 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
440 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
441 /* Branch registers. */ \
442 1, 0, 0, 0, 0, 0, 1, 1, \
443 /*FP CCV UNAT PFS LC EC */ \
447 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
448 problem which makes CALL_USED_REGISTERS *always* include
449 all the FIXED_REGISTERS. Until this problem has been
450 resolved this macro can be used to overcome this situation.
451 In particular, block_propagate() requires this list
452 be accurate, or we can remove registers which should be live.
453 This macro is used in regs_invalidated_by_call. */
455 #define CALL_REALLY_USED_REGISTERS \
456 { /* General registers. */ \
457 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, \
458 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
464 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
465 /* Floating-point registers. */ \
466 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
468 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
469 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
470 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
471 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
472 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
473 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
474 /* Predicate registers. */ \
475 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
479 /* Branch registers. */ \
480 1, 0, 0, 0, 0, 0, 1, 1, \
481 /*FP CCV UNAT PFS LC EC */ \
486 /* Define this macro if the target machine has register windows. This C
487 expression returns the register number as seen by the called function
488 corresponding to the register number OUT as seen by the calling function.
489 Return OUT if register number OUT is not an outbound register. */
491 #define INCOMING_REGNO(OUT) \
492 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
494 /* Define this macro if the target machine has register windows. This C
495 expression returns the register number as seen by the calling function
496 corresponding to the register number IN as seen by the called function.
497 Return IN if register number IN is not an inbound register. */
499 #define OUTGOING_REGNO(IN) \
500 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
502 /* Define this macro if the target machine has register windows. This
503 C expression returns true if the register is call-saved but is in the
506 #define LOCAL_REGNO(REGNO) \
507 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
509 /* We define CCImode in ia64-modes.def so we need a selector. */
511 #define SELECT_CC_MODE(OP,X,Y) CCmode
513 /* Order of allocation of registers */
515 /* If defined, an initializer for a vector of integers, containing the numbers
516 of hard registers in the order in which GCC should prefer to use them
517 (from most preferred to least).
519 If this macro is not defined, registers are used lowest numbered first (all
522 One use of this macro is on machines where the highest numbered registers
523 must always be saved and the save-multiple-registers instruction supports
524 only sequences of consecutive registers. On such machines, define
525 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
526 allocatable register first. */
528 /* ??? Should the GR return value registers come before or after the rest
529 of the caller-save GRs? */
531 #define REG_ALLOC_ORDER \
533 /* Caller-saved general registers. */ \
534 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
535 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
536 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
537 R_GR (30), R_GR (31), \
538 /* Output registers. */ \
539 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
540 R_GR (126), R_GR (127), \
541 /* Caller-saved general registers, also used for return values. */ \
542 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
543 /* addl caller-saved general registers. */ \
544 R_GR (2), R_GR (3), \
545 /* Caller-saved FP registers. */ \
546 R_FR (6), R_FR (7), \
547 /* Caller-saved FP registers, used for parameters and return values. */ \
548 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
549 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
550 /* Rotating caller-saved FP registers. */ \
551 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
552 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
553 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
554 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
555 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
556 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
557 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
558 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
559 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
560 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
561 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
562 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
563 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
564 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
565 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
566 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
567 R_FR (126), R_FR (127), \
568 /* Caller-saved predicate registers. */ \
569 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
570 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
571 /* Rotating caller-saved predicate registers. */ \
572 R_PR (16), R_PR (17), \
573 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
574 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
575 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
576 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
577 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
578 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
579 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
580 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
581 /* Caller-saved branch registers. */ \
582 R_BR (6), R_BR (7), \
584 /* Stacked callee-saved general registers. */ \
585 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
586 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
587 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
588 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
589 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
590 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
591 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
592 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
593 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
594 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
595 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
596 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
597 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
599 /* Input registers. */ \
600 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
601 R_GR (118), R_GR (119), \
602 /* Callee-saved general registers. */ \
603 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
604 /* Callee-saved FP registers. */ \
605 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
606 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
607 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
608 R_FR (30), R_FR (31), \
609 /* Callee-saved predicate registers. */ \
610 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
611 /* Callee-saved branch registers. */ \
612 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
614 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
615 R_GR (109), R_GR (110), R_GR (111), \
617 /* Special general registers. */ \
618 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
619 /* Special FP registers. */ \
620 R_FR (0), R_FR (1), \
621 /* Special predicate registers. */ \
623 /* Special branch registers. */ \
625 /* Other fixed registers. */ \
626 FRAME_POINTER_REGNUM, \
627 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
631 /* How Values Fit in Registers */
633 /* A C expression for the number of consecutive hard registers, starting at
634 register number REGNO, required to hold a value of mode MODE. */
636 /* ??? We say that BImode PR values require two registers. This allows us to
637 easily store the normal and inverted values. We use CCImode to indicate
638 a single predicate register. */
640 #define HARD_REGNO_NREGS(REGNO, MODE) \
641 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
642 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
643 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
644 : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
645 : FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
646 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
648 /* A C expression that is nonzero if it is permissible to store a value of mode
649 MODE in hard register number REGNO (or in several registers starting with
652 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
653 (FR_REGNO_P (REGNO) ? \
654 GET_MODE_CLASS (MODE) != MODE_CC && \
655 (MODE) != BImode && \
657 : PR_REGNO_P (REGNO) ? \
658 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
659 : GR_REGNO_P (REGNO) ? \
660 (MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode \
661 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
662 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
665 /* A C expression that is nonzero if it is desirable to choose register
666 allocation so as to avoid move instructions between a value of mode MODE1
667 and a value of mode MODE2.
669 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
670 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
672 /* Don't tie integer and FP modes, as that causes us to get integer registers
673 allocated for FP instructions. XFmode only supported in FP registers so
674 we can't tie it with any other modes. */
675 #define MODES_TIEABLE_P(MODE1, MODE2) \
676 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
677 && ((((MODE1) == XFmode) || ((MODE1) == XCmode)) \
678 == (((MODE2) == XFmode) || ((MODE2) == XCmode))) \
679 && (((MODE1) == BImode) == ((MODE2) == BImode)))
681 /* Specify the modes required to caller save a given hard regno.
682 We need to ensure floating pt regs are not saved as DImode. */
684 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
685 ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode \
686 : choose_hard_reg_mode ((REGNO), (NREGS), false))
688 /* Handling Leaf Functions */
690 /* A C initializer for a vector, indexed by hard register number, which
691 contains 1 for a register that is allowable in a candidate for leaf function
693 /* ??? This might be useful. */
694 /* #define LEAF_REGISTERS */
696 /* A C expression whose value is the register number to which REGNO should be
697 renumbered, when a function is treated as a leaf function. */
698 /* ??? This might be useful. */
699 /* #define LEAF_REG_REMAP(REGNO) */
702 /* Register Classes */
704 /* An enumeral type that must be defined with all the register class names as
705 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
706 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
707 which is not a register class but rather tells how many classes there
709 /* ??? When compiling without optimization, it is possible for the only use of
710 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
711 Regclass handles this case specially and does not assign any costs to the
712 pseudo. The pseudo then ends up using the last class before ALL_REGS.
713 Thus we must not let either PR_REGS or BR_REGS be the last class. The
714 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
732 #define GENERAL_REGS GR_REGS
734 /* The number of distinct register classes. */
735 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
737 /* An initializer containing the names of the register classes as C string
738 constants. These names are used in writing some of the debugging dumps. */
739 #define REG_CLASS_NAMES \
740 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
741 "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \
742 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
744 /* An initializer containing the contents of the register classes, as integers
745 which are bit masks. The Nth integer specifies the contents of class N.
746 The way the integer MASK is interpreted is that register R is in the class
747 if `MASK & (1 << R)' is 1. */
748 #define REG_CLASS_CONTENTS \
751 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
752 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
753 0x00000000, 0x00000000, 0x0000 }, \
755 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
756 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
757 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
759 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
760 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
761 0x00000000, 0x00000000, 0x00FF }, \
763 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
764 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
765 0x00000000, 0x00000000, 0x0600 }, \
767 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
768 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
769 0x00000000, 0x00000000, 0x3800 }, \
771 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
772 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
773 0x00000000, 0x00000000, 0x0000 }, \
775 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
776 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
777 0x00000000, 0x00000000, 0x0100 }, \
779 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
780 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \
781 0x00000000, 0x00000000, 0x0000 }, \
783 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
784 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
785 0x00000000, 0x00000000, 0x0000 }, \
786 /* GR_AND_BR_REGS. */ \
787 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
788 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
789 0x00000000, 0x00000000, 0x01FF }, \
790 /* GR_AND_FR_REGS. */ \
791 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
792 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
793 0x00000000, 0x00000000, 0x0100 }, \
795 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
796 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
797 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
800 /* A C expression whose value is a register class containing hard register
801 REGNO. In general there is more than one such class; choose a class which
802 is "minimal", meaning that no smaller class also contains the register. */
803 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
804 may call here with private (invalid) register numbers, such as
806 #define REGNO_REG_CLASS(REGNO) \
807 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
808 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
809 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \
810 && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \
811 : PR_REGNO_P (REGNO) ? PR_REGS \
812 : BR_REGNO_P (REGNO) ? BR_REGS \
813 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
814 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
817 /* A macro whose definition is the name of the class to which a valid base
818 register must belong. A base register is one used in an address which is
819 the register value plus a displacement. */
820 #define BASE_REG_CLASS GENERAL_REGS
822 /* A macro whose definition is the name of the class to which a valid index
823 register must belong. An index register is one used in an address where its
824 value is either multiplied by a scale factor or added to another register
825 (as well as added to a displacement). This is needed for POST_MODIFY. */
826 #define INDEX_REG_CLASS GENERAL_REGS
828 /* A C expression which defines the machine-dependent operand constraint
829 letters for register classes. If CHAR is such a letter, the value should be
830 the register class corresponding to it. Otherwise, the value should be
831 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
832 will not be passed to this macro; you do not need to handle it. */
834 #define REG_CLASS_FROM_LETTER(CHAR) \
835 ((CHAR) == 'f' ? FR_REGS \
836 : (CHAR) == 'a' ? ADDL_REGS \
837 : (CHAR) == 'b' ? BR_REGS \
838 : (CHAR) == 'c' ? PR_REGS \
839 : (CHAR) == 'd' ? AR_M_REGS \
840 : (CHAR) == 'e' ? AR_I_REGS \
841 : (CHAR) == 'x' ? FP_REGS \
844 /* A C expression which is nonzero if register number NUM is suitable for use
845 as a base register in operand addresses. It may be either a suitable hard
846 register or a pseudo register that has been allocated such a hard reg. */
847 #define REGNO_OK_FOR_BASE_P(REGNO) \
848 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
850 /* A C expression which is nonzero if register number NUM is suitable for use
851 as an index register in operand addresses. It may be either a suitable hard
852 register or a pseudo register that has been allocated such a hard reg.
853 This is needed for POST_MODIFY. */
854 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
856 /* A C expression that places additional restrictions on the register class to
857 use when it is necessary to copy value X into a register in class CLASS.
858 The value is a register class; perhaps CLASS, or perhaps another, smaller
861 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
862 ia64_preferred_reload_class (X, CLASS)
864 /* You should define this macro to indicate to the reload phase that it may
865 need to allocate at least one register for a reload in addition to the
866 register to contain the data. Specifically, if copying X to a register
867 CLASS in MODE requires an intermediate register, you should define this
868 to return the largest register class all of whose registers can be used
869 as intermediate registers or scratch registers. */
871 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
872 ia64_secondary_reload_class (CLASS, MODE, X)
874 /* Certain machines have the property that some registers cannot be copied to
875 some other registers without using memory. Define this macro on those
876 machines to be a C expression that is nonzero if objects of mode M in
877 registers of CLASS1 can only be copied to registers of class CLASS2 by
878 storing a register of CLASS1 into memory and loading that memory location
879 into a register of CLASS2. */
882 /* ??? May need this, but since we've disallowed XFmode in GR_REGS,
883 I'm not quite sure how it could be invoked. The normal problems
884 with unions should be solved with the addressof fiddling done by
885 movxf and friends. */
886 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
887 (((MODE) == XFmode || (MODE) == XCmode) \
888 && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
889 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
892 /* A C expression for the maximum number of consecutive registers of
893 class CLASS needed to hold a value of mode MODE.
894 This is closely related to the macro `HARD_REGNO_NREGS'. */
896 #define CLASS_MAX_NREGS(CLASS, MODE) \
897 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
898 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
899 : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
900 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
902 /* In FP regs, we can't change FP values to integer values and vice versa,
903 but we can change e.g. DImode to SImode, and V2SFmode into DImode. */
905 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
906 (SCALAR_FLOAT_MODE_P (FROM) != SCALAR_FLOAT_MODE_P (TO) \
907 ? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
909 /* A C expression that defines the machine-dependent operand constraint
910 letters (`I', `J', `K', .. 'P') that specify particular ranges of
913 /* 14 bit signed immediate for arithmetic instructions. */
914 #define CONST_OK_FOR_I(VALUE) \
915 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
916 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
917 #define CONST_OK_FOR_J(VALUE) \
918 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
919 /* 8 bit signed immediate for logical instructions. */
920 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
921 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
922 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
923 /* 6 bit unsigned immediate for shift counts. */
924 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
925 /* 9 bit signed immediate for load/store post-increments. */
926 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
927 /* 0 for r0. Used by Linux kernel, do not change. */
928 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
929 /* 0 or -1 for dep instruction. */
930 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
932 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
933 ia64_const_ok_for_letter_p (VALUE, C)
935 /* A C expression that defines the machine-dependent operand constraint letters
936 (`G', `H') that specify particular ranges of `const_double' values. */
938 /* 0.0 and 1.0 for fr0 and fr1. */
939 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
940 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
941 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
943 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
944 ia64_const_double_ok_for_letter_p (VALUE, C)
946 /* A C expression that defines the optional machine-dependent constraint
947 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
948 types of operands, usually memory references, for the target machine. */
950 #define EXTRA_CONSTRAINT(VALUE, C) \
951 ia64_extra_constraint (VALUE, C)
953 /* Basic Stack Layout */
955 /* Define this macro if pushing a word onto the stack moves the stack pointer
956 to a smaller address. */
957 #define STACK_GROWS_DOWNWARD 1
959 /* Define this macro to non-zero if the addresses of local variable slots
960 are at negative offsets from the frame pointer. */
961 #define FRAME_GROWS_DOWNWARD 0
963 /* Offset from the frame pointer to the first local variable slot to
965 #define STARTING_FRAME_OFFSET 0
967 /* Offset from the stack pointer register to the first location at which
968 outgoing arguments are placed. If not specified, the default value of zero
969 is used. This is the proper value for most machines. */
970 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
971 #define STACK_POINTER_OFFSET 16
973 /* Offset from the argument pointer register to the first argument's address.
974 On some machines it may depend on the data type of the function. */
975 #define FIRST_PARM_OFFSET(FUNDECL) 0
977 /* A C expression whose value is RTL representing the value of the return
978 address for the frame COUNT steps up from the current frame, after the
981 /* ??? Frames other than zero would likely require interpreting the frame
982 unwind info, so we don't try to support them. We would also need to define
983 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
985 #define RETURN_ADDR_RTX(COUNT, FRAME) \
986 ia64_return_addr_rtx (COUNT, FRAME)
988 /* A C expression whose value is RTL representing the location of the incoming
989 return address at the beginning of any function, before the prologue. This
990 RTL is either a `REG', indicating that the return value is saved in `REG',
991 or a `MEM' representing a location in the stack. This enables DWARF2
992 unwind info for C++ EH. */
993 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
995 /* ??? This is not defined because of three problems.
996 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
997 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
998 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
999 unused register number.
1000 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1001 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1002 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1003 to zero, despite what the documentation implies, because it is tested in
1004 a few places with #ifdef instead of #if. */
1005 #undef INCOMING_RETURN_ADDR_RTX
1007 /* A C expression whose value is an integer giving the offset, in bytes, from
1008 the value of the stack pointer register to the top of the stack frame at the
1009 beginning of any function, before the prologue. The top of the frame is
1010 defined to be the value of the stack pointer in the previous frame, just
1011 before the call instruction. */
1012 #define INCOMING_FRAME_SP_OFFSET 0
1015 /* Register That Address the Stack Frame. */
1017 /* The register number of the stack pointer register, which must also be a
1018 fixed register according to `FIXED_REGISTERS'. On most machines, the
1019 hardware determines which register this is. */
1021 #define STACK_POINTER_REGNUM 12
1023 /* The register number of the frame pointer register, which is used to access
1024 automatic variables in the stack frame. On some machines, the hardware
1025 determines which register this is. On other machines, you can choose any
1026 register you wish for this purpose. */
1028 #define FRAME_POINTER_REGNUM 328
1030 /* Base register for access to local variables of the function. */
1031 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1033 /* The register number of the arg pointer register, which is used to access the
1034 function's argument list. */
1035 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1037 #define ARG_POINTER_REGNUM R_GR(0)
1039 /* Due to the way varargs and argument spilling happens, the argument
1040 pointer is not 16-byte aligned like the stack pointer. */
1041 #define INIT_EXPANDERS \
1043 if (cfun && cfun->emit->regno_pointer_align) \
1044 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
1047 /* Register numbers used for passing a function's static chain pointer. */
1048 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1049 #define STATIC_CHAIN_REGNUM 15
1051 /* Eliminating the Frame Pointer and the Arg Pointer */
1053 /* A C expression which is nonzero if a function must have and use a frame
1054 pointer. This expression is evaluated in the reload pass. If its value is
1055 nonzero the function will have a frame pointer. */
1056 #define FRAME_POINTER_REQUIRED 0
1058 /* Show we can debug even without a frame pointer. */
1059 #define CAN_DEBUG_WITHOUT_FP
1061 /* If defined, this macro specifies a table of register pairs used to eliminate
1062 unneeded registers that point into the stack frame. */
1064 #define ELIMINABLE_REGS \
1066 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1067 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1068 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1069 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1072 /* A C expression that returns nonzero if the compiler is allowed to try to
1073 replace register number FROM with register number TO. The frame pointer
1074 is automatically handled. */
1076 #define CAN_ELIMINATE(FROM, TO) \
1077 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1079 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1080 specifies the initial difference between the specified pair of
1081 registers. This macro must be defined if `ELIMINABLE_REGS' is
1083 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1084 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1086 /* Passing Function Arguments on the Stack */
1088 /* If defined, the maximum amount of space required for outgoing arguments will
1089 be computed and placed into the variable
1090 `current_function_outgoing_args_size'. */
1092 #define ACCUMULATE_OUTGOING_ARGS 1
1094 /* A C expression that should indicate the number of bytes of its own arguments
1095 that a function pops on returning, or 0 if the function pops no arguments
1096 and the caller must therefore pop them all after the function returns. */
1098 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1101 /* Function Arguments in Registers */
1103 #define MAX_ARGUMENT_SLOTS 8
1104 #define MAX_INT_RETURN_SLOTS 4
1105 #define GR_ARG_FIRST IN_REG (0)
1106 #define GR_RET_FIRST GR_REG (8)
1107 #define GR_RET_LAST GR_REG (11)
1108 #define FR_ARG_FIRST FR_REG (8)
1109 #define FR_RET_FIRST FR_REG (8)
1110 #define FR_RET_LAST FR_REG (15)
1111 #define AR_ARG_FIRST OUT_REG (0)
1113 /* A C expression that controls whether a function argument is passed in a
1114 register, and which register. */
1116 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1117 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1119 /* Define this macro if the target machine has "register windows", so that the
1120 register in which a function sees an arguments is not necessarily the same
1121 as the one in which the caller passed the argument. */
1123 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1124 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1126 /* A C type for declaring a variable that is used as the first argument of
1127 `FUNCTION_ARG' and other related values. For some target machines, the type
1128 `int' suffices and can hold the number of bytes of argument so far. */
1130 typedef struct ia64_args
1132 int words; /* # words of arguments so far */
1133 int int_regs; /* # GR registers used so far */
1134 int fp_regs; /* # FR registers used so far */
1135 int prototype; /* whether function prototyped */
1138 /* A C statement (sans semicolon) for initializing the variable CUM for the
1139 state at the beginning of the argument list. */
1141 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1144 (CUM).int_regs = 0; \
1145 (CUM).fp_regs = 0; \
1146 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1149 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1150 arguments for the function being compiled. If this macro is undefined,
1151 `INIT_CUMULATIVE_ARGS' is used instead. */
1153 /* We set prototype to true so that we never try to return a PARALLEL from
1155 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1158 (CUM).int_regs = 0; \
1159 (CUM).fp_regs = 0; \
1160 (CUM).prototype = 1; \
1163 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1164 advance past an argument in the argument list. The values MODE, TYPE and
1165 NAMED describe that argument. Once this is done, the variable CUM is
1166 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1168 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1169 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1171 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1172 argument with the specified mode and type. */
1174 /* Return the alignment boundary in bits for an argument with a specified
1177 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1178 ia64_function_arg_boundary (MODE, TYPE)
1180 /* A C expression that is nonzero if REGNO is the number of a hard register in
1181 which function arguments are sometimes passed. This does *not* include
1182 implicit arguments such as the static chain and the structure-value address.
1183 On many machines, no registers can be used for this purpose since all
1184 function arguments are pushed on the stack. */
1185 #define FUNCTION_ARG_REGNO_P(REGNO) \
1186 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1187 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1189 /* How Scalar Function Values are Returned */
1191 /* A C expression to create an RTX representing the place where a function
1192 returns a value of data type VALTYPE. */
1194 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1195 ia64_function_value (VALTYPE, FUNC)
1197 /* A C expression to create an RTX representing the place where a library
1198 function returns a value of mode MODE. */
1200 #define LIBCALL_VALUE(MODE) \
1201 gen_rtx_REG (MODE, \
1202 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1203 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1205 ? FR_RET_FIRST : GR_RET_FIRST))
1207 /* A C expression that is nonzero if REGNO is the number of a hard register in
1208 which the values of called function may come back. */
1210 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1211 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1212 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1215 /* How Large Values are Returned */
1217 #define DEFAULT_PCC_STRUCT_RETURN 0
1220 /* Caller-Saves Register Allocation */
1222 /* A C expression to determine whether it is worthwhile to consider placing a
1223 pseudo-register in a call-clobbered hard register and saving and restoring
1224 it around each function call. The expression should be 1 when this is worth
1225 doing, and 0 otherwise.
1227 If you don't define this macro, a default is used which is good on most
1228 machines: `4 * CALLS < REFS'. */
1229 /* ??? Investigate. */
1230 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1233 /* Function Entry and Exit */
1235 /* Define this macro as a C expression that is nonzero if the return
1236 instruction or the function epilogue ignores the value of the stack pointer;
1237 in other words, if it is safe to delete an instruction to adjust the stack
1238 pointer before a return from the function. */
1240 #define EXIT_IGNORE_STACK 1
1242 /* Define this macro as a C expression that is nonzero for registers
1243 used by the epilogue or the `return' pattern. */
1245 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1247 /* Nonzero for registers used by the exception handling mechanism. */
1249 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
1251 /* Output part N of a function descriptor for DECL. For ia64, both
1252 words are emitted with a single relocation, so ignore N > 0. */
1253 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1258 fputs ("\tdata8.ua @iplt(", FILE); \
1260 fputs ("\tdata16.ua @iplt(", FILE); \
1261 mark_decl_referenced (DECL); \
1262 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1263 fputs (")\n", FILE); \
1265 fputs ("\tdata8.ua 0\n", FILE); \
1269 /* Generating Code for Profiling. */
1271 /* A C statement or compound statement to output to FILE some assembler code to
1272 call the profiling subroutine `mcount'. */
1274 #undef FUNCTION_PROFILER
1275 #define FUNCTION_PROFILER(FILE, LABELNO) \
1276 ia64_output_function_profiler(FILE, LABELNO)
1278 /* Neither hpux nor linux use profile counters. */
1279 #define NO_PROFILE_COUNTERS 1
1281 /* Trampolines for Nested Functions. */
1283 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1284 the function containing a non-local goto target. */
1286 #define STACK_SAVEAREA_MODE(LEVEL) \
1287 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1289 /* Output assembler code for a block containing the constant parts of
1290 a trampoline, leaving space for the variable parts.
1292 The trampoline should set the static chain pointer to value placed
1293 into the trampoline and should branch to the specified routine.
1294 To make the normal indirect-subroutine calling convention work,
1295 the trampoline must look like a function descriptor; the first
1296 word being the target address and the second being the target's
1299 We abuse the concept of a global pointer by arranging for it
1300 to point to the data we need to load. The complete trampoline
1301 has the following form:
1303 +-------------------+ \
1304 TRAMP: | __ia64_trampoline | |
1305 +-------------------+ > fake function descriptor
1307 +-------------------+ /
1308 | target descriptor |
1309 +-------------------+
1311 +-------------------+
1314 /* A C expression for the size in bytes of the trampoline, as an integer. */
1316 #define TRAMPOLINE_SIZE 32
1318 /* Alignment required for trampolines, in bits. */
1320 #define TRAMPOLINE_ALIGNMENT 64
1322 /* A C statement to initialize the variable parts of a trampoline. */
1324 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1325 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1327 /* Addressing Modes */
1329 /* Define this macro if the machine supports post-increment addressing. */
1331 #define HAVE_POST_INCREMENT 1
1332 #define HAVE_POST_DECREMENT 1
1333 #define HAVE_POST_MODIFY_DISP 1
1334 #define HAVE_POST_MODIFY_REG 1
1336 /* A C expression that is 1 if the RTX X is a constant which is a valid
1339 #define CONSTANT_ADDRESS_P(X) 0
1341 /* The max number of registers that can appear in a valid memory address. */
1343 #define MAX_REGS_PER_ADDRESS 2
1345 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1346 RTX) is a legitimate memory address on the target machine for a memory
1347 operand of mode MODE. */
1349 #define LEGITIMATE_ADDRESS_REG(X) \
1350 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1351 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1352 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1354 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1355 (GET_CODE (X) == PLUS \
1356 && rtx_equal_p (R, XEXP (X, 0)) \
1357 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1358 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1359 && INTVAL (XEXP (X, 1)) >= -256 \
1360 && INTVAL (XEXP (X, 1)) < 256)))
1362 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1364 if (LEGITIMATE_ADDRESS_REG (X)) \
1366 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1367 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1368 && XEXP (X, 0) != arg_pointer_rtx) \
1370 else if (GET_CODE (X) == POST_MODIFY \
1371 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1372 && XEXP (X, 0) != arg_pointer_rtx \
1373 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1377 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1378 use as a base register. */
1380 #ifdef REG_OK_STRICT
1381 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1383 #define REG_OK_FOR_BASE_P(X) \
1384 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1387 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1388 use as an index register. This is needed for POST_MODIFY. */
1390 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1392 /* A C statement or compound statement with a conditional `goto LABEL;'
1393 executed if memory address X (an RTX) can have different meanings depending
1394 on the machine mode of the memory reference it is used for or if the address
1395 is valid for some modes but not others. */
1397 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1398 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1401 /* A C expression that is nonzero if X is a legitimate constant for an
1402 immediate operand on the target machine. */
1404 #define LEGITIMATE_CONSTANT_P(X) ia64_legitimate_constant_p (X)
1406 /* Condition Code Status */
1408 /* One some machines not all possible comparisons are defined, but you can
1409 convert an invalid comparison into a valid one. */
1410 /* ??? Investigate. See the alpha definition. */
1411 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1414 /* Describing Relative Costs of Operations */
1416 /* A C expression for the cost of moving data from a register in class FROM to
1417 one in class TO, using MODE. */
1419 #define REGISTER_MOVE_COST ia64_register_move_cost
1421 /* A C expression for the cost of moving data of mode M between a
1422 register and memory. */
1423 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1424 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS || (CLASS) == FP_REGS \
1425 || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1427 /* A C expression for the cost of a branch instruction. A value of 1 is the
1428 default; other values are interpreted relative to that. Used by the
1429 if-conversion code as max instruction count. */
1430 /* ??? This requires investigation. The primary effect might be how
1431 many additional insn groups we run into, vs how good the dynamic
1432 branch predictor is. */
1434 #define BRANCH_COST 6
1436 /* Define this macro as a C expression which is nonzero if accessing less than
1437 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1440 #define SLOW_BYTE_ACCESS 1
1442 /* Define this macro if it is as good or better to call a constant function
1443 address than to call an address kept in a register.
1445 Indirect function calls are more expensive that direct function calls, so
1446 don't cse function addresses. */
1448 #define NO_FUNCTION_CSE
1451 /* Dividing the output into sections. */
1453 /* A C expression whose value is a string containing the assembler operation
1454 that should precede instructions and read-only data. */
1456 #define TEXT_SECTION_ASM_OP "\t.text"
1458 /* A C expression whose value is a string containing the assembler operation to
1459 identify the following data as writable initialized data. */
1461 #define DATA_SECTION_ASM_OP "\t.data"
1463 /* If defined, a C expression whose value is a string containing the assembler
1464 operation to identify the following data as uninitialized global data. */
1466 #define BSS_SECTION_ASM_OP "\t.bss"
1468 #define IA64_DEFAULT_GVALUE 8
1470 /* Position Independent Code. */
1472 /* The register number of the register used to address a table of static data
1473 addresses in memory. */
1475 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1476 gen_rtx_REG (DImode, 1). */
1478 /* ??? Should we set flag_pic? Probably need to define
1479 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1481 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1483 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1484 clobbered by calls. */
1486 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1489 /* The Overall Framework of an Assembler File. */
1491 /* A C string constant describing how to begin a comment in the target
1492 assembler language. The compiler assumes that the comment will end at the
1495 #define ASM_COMMENT_START "//"
1497 /* A C string constant for text to be output before each `asm' statement or
1498 group of consecutive ones. */
1500 #define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
1502 /* A C string constant for text to be output after each `asm' statement or
1503 group of consecutive ones. */
1505 #define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
1507 /* Output of Uninitialized Variables. */
1509 /* This is all handled by svr4.h. */
1512 /* Output and Generation of Labels. */
1514 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1515 assembler definition of a label named NAME. */
1517 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1518 why ia64_asm_output_label exists. */
1520 extern int ia64_asm_output_label;
1521 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1523 ia64_asm_output_label = 1; \
1524 assemble_name (STREAM, NAME); \
1525 fputs (":\n", STREAM); \
1526 ia64_asm_output_label = 0; \
1529 /* Globalizing directive for a label. */
1530 #define GLOBAL_ASM_OP "\t.global "
1532 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1533 necessary for declaring the name of an external symbol named NAME which is
1534 referenced in this compilation but not defined. */
1536 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1537 ia64_asm_output_external (FILE, DECL, NAME)
1539 /* A C statement to store into the string STRING a label whose name is made
1540 from the string PREFIX and the number NUM. */
1542 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1544 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1547 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1549 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1551 /* A C statement to output to the stdio stream STREAM assembler code which
1552 defines (equates) the symbol NAME to have the value VALUE. */
1554 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1556 assemble_name (STREAM, NAME); \
1557 fputs (" = ", STREAM); \
1558 assemble_name (STREAM, VALUE); \
1559 fputc ('\n', STREAM); \
1563 /* Macros Controlling Initialization Routines. */
1565 /* This is handled by svr4.h and sysv4.h. */
1568 /* Output of Assembler Instructions. */
1570 /* A C initializer containing the assembler's names for the machine registers,
1571 each one as a C string constant. */
1573 #define REGISTER_NAMES \
1575 /* General registers. */ \
1576 "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1577 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1578 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1580 /* Local registers. */ \
1581 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1582 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1583 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1584 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1585 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1586 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1587 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1588 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1589 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1590 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1591 /* Input registers. */ \
1592 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1593 /* Output registers. */ \
1594 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1595 /* Floating-point registers. */ \
1596 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1597 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1598 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1599 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1600 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1601 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1602 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1603 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1604 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1605 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1606 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1607 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1608 "f120","f121","f122","f123","f124","f125","f126","f127", \
1609 /* Predicate registers. */ \
1610 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1611 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1612 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1613 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1614 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1615 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1616 "p60", "p61", "p62", "p63", \
1617 /* Branch registers. */ \
1618 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
1619 /* Frame pointer. Application registers. */ \
1620 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
1623 /* If defined, a C initializer for an array of structures containing a name and
1624 a register number. This macro defines additional names for hard registers,
1625 thus allowing the `asm' option in declarations to refer to registers using
1628 #define ADDITIONAL_REGISTER_NAMES \
1630 { "gp", R_GR (1) }, \
1631 { "sp", R_GR (12) }, \
1632 { "in0", IN_REG (0) }, \
1633 { "in1", IN_REG (1) }, \
1634 { "in2", IN_REG (2) }, \
1635 { "in3", IN_REG (3) }, \
1636 { "in4", IN_REG (4) }, \
1637 { "in5", IN_REG (5) }, \
1638 { "in6", IN_REG (6) }, \
1639 { "in7", IN_REG (7) }, \
1640 { "out0", OUT_REG (0) }, \
1641 { "out1", OUT_REG (1) }, \
1642 { "out2", OUT_REG (2) }, \
1643 { "out3", OUT_REG (3) }, \
1644 { "out4", OUT_REG (4) }, \
1645 { "out5", OUT_REG (5) }, \
1646 { "out6", OUT_REG (6) }, \
1647 { "out7", OUT_REG (7) }, \
1648 { "loc0", LOC_REG (0) }, \
1649 { "loc1", LOC_REG (1) }, \
1650 { "loc2", LOC_REG (2) }, \
1651 { "loc3", LOC_REG (3) }, \
1652 { "loc4", LOC_REG (4) }, \
1653 { "loc5", LOC_REG (5) }, \
1654 { "loc6", LOC_REG (6) }, \
1655 { "loc7", LOC_REG (7) }, \
1656 { "loc8", LOC_REG (8) }, \
1657 { "loc9", LOC_REG (9) }, \
1658 { "loc10", LOC_REG (10) }, \
1659 { "loc11", LOC_REG (11) }, \
1660 { "loc12", LOC_REG (12) }, \
1661 { "loc13", LOC_REG (13) }, \
1662 { "loc14", LOC_REG (14) }, \
1663 { "loc15", LOC_REG (15) }, \
1664 { "loc16", LOC_REG (16) }, \
1665 { "loc17", LOC_REG (17) }, \
1666 { "loc18", LOC_REG (18) }, \
1667 { "loc19", LOC_REG (19) }, \
1668 { "loc20", LOC_REG (20) }, \
1669 { "loc21", LOC_REG (21) }, \
1670 { "loc22", LOC_REG (22) }, \
1671 { "loc23", LOC_REG (23) }, \
1672 { "loc24", LOC_REG (24) }, \
1673 { "loc25", LOC_REG (25) }, \
1674 { "loc26", LOC_REG (26) }, \
1675 { "loc27", LOC_REG (27) }, \
1676 { "loc28", LOC_REG (28) }, \
1677 { "loc29", LOC_REG (29) }, \
1678 { "loc30", LOC_REG (30) }, \
1679 { "loc31", LOC_REG (31) }, \
1680 { "loc32", LOC_REG (32) }, \
1681 { "loc33", LOC_REG (33) }, \
1682 { "loc34", LOC_REG (34) }, \
1683 { "loc35", LOC_REG (35) }, \
1684 { "loc36", LOC_REG (36) }, \
1685 { "loc37", LOC_REG (37) }, \
1686 { "loc38", LOC_REG (38) }, \
1687 { "loc39", LOC_REG (39) }, \
1688 { "loc40", LOC_REG (40) }, \
1689 { "loc41", LOC_REG (41) }, \
1690 { "loc42", LOC_REG (42) }, \
1691 { "loc43", LOC_REG (43) }, \
1692 { "loc44", LOC_REG (44) }, \
1693 { "loc45", LOC_REG (45) }, \
1694 { "loc46", LOC_REG (46) }, \
1695 { "loc47", LOC_REG (47) }, \
1696 { "loc48", LOC_REG (48) }, \
1697 { "loc49", LOC_REG (49) }, \
1698 { "loc50", LOC_REG (50) }, \
1699 { "loc51", LOC_REG (51) }, \
1700 { "loc52", LOC_REG (52) }, \
1701 { "loc53", LOC_REG (53) }, \
1702 { "loc54", LOC_REG (54) }, \
1703 { "loc55", LOC_REG (55) }, \
1704 { "loc56", LOC_REG (56) }, \
1705 { "loc57", LOC_REG (57) }, \
1706 { "loc58", LOC_REG (58) }, \
1707 { "loc59", LOC_REG (59) }, \
1708 { "loc60", LOC_REG (60) }, \
1709 { "loc61", LOC_REG (61) }, \
1710 { "loc62", LOC_REG (62) }, \
1711 { "loc63", LOC_REG (63) }, \
1712 { "loc64", LOC_REG (64) }, \
1713 { "loc65", LOC_REG (65) }, \
1714 { "loc66", LOC_REG (66) }, \
1715 { "loc67", LOC_REG (67) }, \
1716 { "loc68", LOC_REG (68) }, \
1717 { "loc69", LOC_REG (69) }, \
1718 { "loc70", LOC_REG (70) }, \
1719 { "loc71", LOC_REG (71) }, \
1720 { "loc72", LOC_REG (72) }, \
1721 { "loc73", LOC_REG (73) }, \
1722 { "loc74", LOC_REG (74) }, \
1723 { "loc75", LOC_REG (75) }, \
1724 { "loc76", LOC_REG (76) }, \
1725 { "loc77", LOC_REG (77) }, \
1726 { "loc78", LOC_REG (78) }, \
1727 { "loc79", LOC_REG (79) }, \
1730 /* A C compound statement to output to stdio stream STREAM the assembler syntax
1731 for an instruction operand X. X is an RTL expression. */
1733 #define PRINT_OPERAND(STREAM, X, CODE) \
1734 ia64_print_operand (STREAM, X, CODE)
1736 /* A C expression which evaluates to true if CODE is a valid punctuation
1737 character for use in the `PRINT_OPERAND' macro. */
1739 /* ??? Keep this around for now, as we might need it later. */
1741 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1742 ((CODE) == '+' || (CODE) == ',')
1744 /* A C compound statement to output to stdio stream STREAM the assembler syntax
1745 for an instruction operand that is a memory reference whose address is X. X
1746 is an RTL expression. */
1748 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
1749 ia64_print_operand_address (STREAM, X)
1751 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
1752 `%I' options of `asm_fprintf' (see `final.c'). */
1754 #define REGISTER_PREFIX ""
1755 #define LOCAL_LABEL_PREFIX "."
1756 #define USER_LABEL_PREFIX ""
1757 #define IMMEDIATE_PREFIX ""
1760 /* Output of dispatch tables. */
1762 /* This macro should be provided on machines where the addresses in a dispatch
1763 table are relative to the table's own address. */
1765 /* ??? Depends on the pointer size. */
1767 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1770 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
1772 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
1775 /* This is how to output an element of a case-vector that is absolute.
1776 (Ia64 does not use such vectors, but we must define this macro anyway.) */
1778 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) gcc_unreachable ()
1780 /* Jump tables only need 8 byte alignment. */
1782 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
1785 /* Assembler Commands for Exception Regions. */
1787 /* Select a format to encode pointers in exception handling data. CODE
1788 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1789 true if the symbol may be affected by dynamic relocations. */
1790 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1791 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
1792 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \
1793 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
1795 /* Handle special EH pointer encodings. Absolute, pc-relative, and
1796 indirect are handled automatically. */
1797 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1799 const char *reltag = NULL; \
1800 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
1801 reltag = "@segrel("; \
1802 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
1803 reltag = "@gprel("; \
1806 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1807 fputs (reltag, FILE); \
1808 assemble_name (FILE, XSTR (ADDR, 0)); \
1809 fputc (')', FILE); \
1815 /* Assembler Commands for Alignment. */
1817 /* ??? Investigate. */
1819 /* The alignment (log base 2) to put in front of LABEL, which follows
1822 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
1824 /* The desired alignment for the location counter at the beginning
1827 /* #define LOOP_ALIGN(LABEL) */
1829 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
1830 section because it fails put zeros in the bytes that are skipped. */
1832 #define ASM_NO_SKIP_IN_TEXT 1
1834 /* A C statement to output to the stdio stream STREAM an assembler command to
1835 advance the location counter to a multiple of 2 to the POWER bytes. */
1837 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1838 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
1841 /* Macros Affecting all Debug Formats. */
1843 /* This is handled in svr4.h and sysv4.h. */
1846 /* Specific Options for DBX Output. */
1848 /* This is handled by dbxelf.h which is included by svr4.h. */
1851 /* Open ended Hooks for DBX Output. */
1856 /* File names in DBX format. */
1861 /* Macros for SDB and Dwarf Output. */
1863 /* Define this macro if GCC should produce dwarf version 2 format debugging
1864 output in response to the `-g' option. */
1866 #define DWARF2_DEBUGGING_INFO 1
1868 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
1870 /* Use tags for debug info labels, so that they don't break instruction
1871 bundles. This also avoids getting spurious DV warnings from the
1872 assembler. This is similar to (*targetm.asm_out.internal_label), except that we
1873 add brackets around the label. */
1875 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
1876 fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
1878 /* Use section-relative relocations for debugging offsets. Unlike other
1879 targets that fake this by putting the section VMA at 0, IA-64 has
1880 proper relocations for them. */
1881 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
1883 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1884 fputs ("@secrel(", FILE); \
1885 assemble_name (FILE, LABEL); \
1886 fputc (')', FILE); \
1889 /* Emit a PC-relative relocation. */
1890 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1892 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1893 fputs ("@pcrel(", FILE); \
1894 assemble_name (FILE, LABEL); \
1895 fputc (')', FILE); \
1898 /* Register Renaming Parameters. */
1900 /* A C expression that is nonzero if hard register number REGNO2 can be
1901 considered for use as a rename register for REGNO1 */
1903 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
1904 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
1907 /* Miscellaneous Parameters. */
1909 /* Flag to mark data that is in the small address area (addressable
1910 via "addl", that is, within a 2MByte offset of 0. */
1911 #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
1912 #define SYMBOL_REF_SMALL_ADDR_P(X) \
1913 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
1915 /* An alias for a machine mode name. This is the machine mode that elements of
1916 a jump-table should have. */
1918 #define CASE_VECTOR_MODE ptr_mode
1920 /* Define as C expression which evaluates to nonzero if the tablejump
1921 instruction expects the table to contain offsets from the address of the
1924 #define CASE_VECTOR_PC_RELATIVE 1
1926 /* Define this macro if operations between registers with integral mode smaller
1927 than a word are always performed on the entire register. */
1929 #define WORD_REGISTER_OPERATIONS
1931 /* Define this macro to be a C expression indicating when insns that read
1932 memory in MODE, an integral mode narrower than a word, set the bits outside
1933 of MODE to be either the sign-extension or the zero-extension of the data
1936 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1938 /* The maximum number of bytes that a single instruction can move quickly from
1939 memory to memory. */
1942 /* A C expression which is nonzero if on this machine it is safe to "convert"
1943 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
1944 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
1946 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1948 /* A C expression describing the value returned by a comparison operator with
1949 an integral mode and stored by a store-flag instruction (`sCOND') when the
1950 condition is true. */
1952 /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */
1954 /* An alias for the machine mode for pointers. */
1956 /* ??? This would change if we had ILP32 support. */
1958 #define Pmode DImode
1960 /* An alias for the machine mode used for memory references to functions being
1961 called, in `call' RTL expressions. */
1963 #define FUNCTION_MODE Pmode
1965 /* Define this macro to handle System V style pragmas: #pragma pack and
1966 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
1969 /* If this architecture supports prefetch, define this to be the number of
1970 prefetch commands that can be executed in parallel.
1972 ??? This number is bogus and needs to be replaced before the value is
1973 actually used in optimizations. */
1975 #define SIMULTANEOUS_PREFETCHES 6
1977 /* If this architecture supports prefetch, define this to be the size of
1978 the cache line that is prefetched. */
1980 #define PREFETCH_BLOCK 32
1982 #define HANDLE_SYSV_PRAGMA 1
1984 /* A C expression for the maximum number of instructions to execute via
1985 conditional execution instructions instead of a branch. A value of
1986 BRANCH_COST+1 is the default if the machine does not use
1987 cc0, and 1 if it does use cc0. */
1988 /* ??? Investigate. */
1989 #define MAX_CONDITIONAL_EXECUTE 12
1991 extern int ia64_final_schedule;
1993 #define TARGET_UNWIND_INFO 1
1995 #define TARGET_UNWIND_TABLES_DEFAULT true
1997 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
1999 /* This function contains machine specific function data. */
2000 struct machine_function GTY(())
2002 /* The new stack pointer when unwinding from EH. */
2003 rtx ia64_eh_epilogue_sp;
2005 /* The new bsp value when unwinding from EH. */
2006 rtx ia64_eh_epilogue_bsp;
2008 /* The GP value save register. */
2011 /* The number of varargs registers to save. */
2014 /* The number of the next unwind state to copy. */
2018 #define DONT_USE_BUILTIN_SETJMP
2020 /* Output any profiling code before the prologue. */
2022 #undef PROFILE_BEFORE_PROLOGUE
2023 #define PROFILE_BEFORE_PROLOGUE 1
2025 /* Initialize library function table. */
2026 #undef TARGET_INIT_LIBFUNCS
2027 #define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
2030 /* Switch on code for querying unit reservations. */
2031 #define CPU_UNITS_QUERY 1
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