1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
55 /* This is used for communication between ASM_OUTPUT_LABEL and
56 ASM_OUTPUT_LABELREF. */
57 int ia64_asm_output_label = 0;
59 /* Define the information needed to generate branch and scc insns. This is
60 stored from the compare operation. */
61 struct rtx_def * ia64_compare_op0;
62 struct rtx_def * ia64_compare_op1;
64 /* Register names for ia64_expand_prologue. */
65 static const char * const ia64_reg_numbers[96] =
66 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
67 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
68 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
69 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
70 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
71 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
72 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
73 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
74 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
75 "r104","r105","r106","r107","r108","r109","r110","r111",
76 "r112","r113","r114","r115","r116","r117","r118","r119",
77 "r120","r121","r122","r123","r124","r125","r126","r127"};
79 /* ??? These strings could be shared with REGISTER_NAMES. */
80 static const char * const ia64_input_reg_names[8] =
81 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
83 /* ??? These strings could be shared with REGISTER_NAMES. */
84 static const char * const ia64_local_reg_names[80] =
85 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
86 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
87 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
88 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
89 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
90 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
91 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
92 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
93 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
94 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
96 /* ??? These strings could be shared with REGISTER_NAMES. */
97 static const char * const ia64_output_reg_names[8] =
98 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
100 /* String used with the -mfixed-range= option. */
101 const char *ia64_fixed_range_string;
103 /* Determines whether we use adds, addl, or movl to generate our
104 TLS immediate offsets. */
105 int ia64_tls_size = 22;
107 /* String used with the -mtls-size= option. */
108 const char *ia64_tls_size_string;
110 /* Which cpu are we scheduling for. */
111 enum processor_type ia64_tune;
113 /* String used with the -tune= option. */
114 const char *ia64_tune_string;
116 /* Determines whether we run our final scheduling pass or not. We always
117 avoid the normal second scheduling pass. */
118 static int ia64_flag_schedule_insns2;
120 /* Determines whether we run variable tracking in machine dependent
122 static int ia64_flag_var_tracking;
124 /* Variables which are this size or smaller are put in the sdata/sbss
127 unsigned int ia64_section_threshold;
129 /* The following variable is used by the DFA insn scheduler. The value is
130 TRUE if we do insn bundling instead of insn scheduling. */
133 /* Structure to be filled in by ia64_compute_frame_size with register
134 save masks and offsets for the current function. */
136 struct ia64_frame_info
138 HOST_WIDE_INT total_size; /* size of the stack frame, not including
139 the caller's scratch area. */
140 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
141 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
142 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
143 HARD_REG_SET mask; /* mask of saved registers. */
144 unsigned int gr_used_mask; /* mask of registers in use as gr spill
145 registers or long-term scratches. */
146 int n_spilled; /* number of spilled registers. */
147 int reg_fp; /* register for fp. */
148 int reg_save_b0; /* save register for b0. */
149 int reg_save_pr; /* save register for prs. */
150 int reg_save_ar_pfs; /* save register for ar.pfs. */
151 int reg_save_ar_unat; /* save register for ar.unat. */
152 int reg_save_ar_lc; /* save register for ar.lc. */
153 int reg_save_gp; /* save register for gp. */
154 int n_input_regs; /* number of input registers used. */
155 int n_local_regs; /* number of local registers used. */
156 int n_output_regs; /* number of output registers used. */
157 int n_rotate_regs; /* number of rotating registers used. */
159 char need_regstk; /* true if a .regstk directive needed. */
160 char initialized; /* true if the data is finalized. */
163 /* Current frame information calculated by ia64_compute_frame_size. */
164 static struct ia64_frame_info current_frame_info;
166 static int ia64_use_dfa_pipeline_interface (void);
167 static int ia64_first_cycle_multipass_dfa_lookahead (void);
168 static void ia64_dependencies_evaluation_hook (rtx, rtx);
169 static void ia64_init_dfa_pre_cycle_insn (void);
170 static rtx ia64_dfa_pre_cycle_insn (void);
171 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
172 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
173 static rtx gen_tls_get_addr (void);
174 static rtx gen_thread_pointer (void);
175 static rtx ia64_expand_tls_address (enum tls_model, rtx, rtx);
176 static int find_gr_spill (int);
177 static int next_scratch_gr_reg (void);
178 static void mark_reg_gr_used_mask (rtx, void *);
179 static void ia64_compute_frame_size (HOST_WIDE_INT);
180 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
181 static void finish_spill_pointers (void);
182 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
183 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
184 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
185 static rtx gen_movdi_x (rtx, rtx, rtx);
186 static rtx gen_fr_spill_x (rtx, rtx, rtx);
187 static rtx gen_fr_restore_x (rtx, rtx, rtx);
189 static enum machine_mode hfa_element_mode (tree, int);
190 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
192 static bool ia64_function_ok_for_sibcall (tree, tree);
193 static bool ia64_return_in_memory (tree, tree);
194 static bool ia64_rtx_costs (rtx, int, int, int *);
195 static void fix_range (const char *);
196 static struct machine_function * ia64_init_machine_status (void);
197 static void emit_insn_group_barriers (FILE *);
198 static void emit_all_insn_group_barriers (FILE *);
199 static void final_emit_insn_group_barriers (FILE *);
200 static void emit_predicate_relation_info (void);
201 static void ia64_reorg (void);
202 static bool ia64_in_small_data_p (tree);
203 static void process_epilogue (void);
204 static int process_set (FILE *, rtx);
206 static rtx ia64_expand_fetch_and_op (optab, enum machine_mode, tree, rtx);
207 static rtx ia64_expand_op_and_fetch (optab, enum machine_mode, tree, rtx);
208 static rtx ia64_expand_compare_and_swap (enum machine_mode, enum machine_mode,
210 static rtx ia64_expand_lock_test_and_set (enum machine_mode, tree, rtx);
211 static rtx ia64_expand_lock_release (enum machine_mode, tree, rtx);
212 static bool ia64_assemble_integer (rtx, unsigned int, int);
213 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
214 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
215 static void ia64_output_function_end_prologue (FILE *);
217 static int ia64_issue_rate (void);
218 static int ia64_adjust_cost (rtx, rtx, rtx, int);
219 static void ia64_sched_init (FILE *, int, int);
220 static void ia64_sched_finish (FILE *, int);
221 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
222 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
223 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
224 static int ia64_variable_issue (FILE *, int, rtx, int);
226 static struct bundle_state *get_free_bundle_state (void);
227 static void free_bundle_state (struct bundle_state *);
228 static void initiate_bundle_states (void);
229 static void finish_bundle_states (void);
230 static unsigned bundle_state_hash (const void *);
231 static int bundle_state_eq_p (const void *, const void *);
232 static int insert_bundle_state (struct bundle_state *);
233 static void initiate_bundle_state_table (void);
234 static void finish_bundle_state_table (void);
235 static int try_issue_nops (struct bundle_state *, int);
236 static int try_issue_insn (struct bundle_state *, rtx);
237 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
238 static int get_max_pos (state_t);
239 static int get_template (state_t, int);
241 static rtx get_next_important_insn (rtx, rtx);
242 static void bundling (FILE *, int, rtx, rtx);
244 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
245 HOST_WIDE_INT, tree);
246 static void ia64_file_start (void);
248 static void ia64_select_rtx_section (enum machine_mode, rtx,
249 unsigned HOST_WIDE_INT);
250 static void ia64_rwreloc_select_section (tree, int, unsigned HOST_WIDE_INT)
252 static void ia64_rwreloc_unique_section (tree, int)
254 static void ia64_rwreloc_select_rtx_section (enum machine_mode, rtx,
255 unsigned HOST_WIDE_INT)
257 static unsigned int ia64_rwreloc_section_type_flags (tree, const char *, int)
260 static void ia64_hpux_add_extern_decl (tree decl)
262 static void ia64_hpux_file_end (void)
264 static void ia64_hpux_init_libfuncs (void)
266 static void ia64_vms_init_libfuncs (void)
269 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
270 static void ia64_encode_section_info (tree, rtx, int);
271 static rtx ia64_struct_value_rtx (tree, int);
274 /* Table of valid machine attributes. */
275 static const struct attribute_spec ia64_attribute_table[] =
277 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
278 { "syscall_linkage", 0, 0, false, true, true, NULL },
279 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
280 { NULL, 0, 0, false, false, false, NULL }
283 /* Initialize the GCC target structure. */
284 #undef TARGET_ATTRIBUTE_TABLE
285 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
287 #undef TARGET_INIT_BUILTINS
288 #define TARGET_INIT_BUILTINS ia64_init_builtins
290 #undef TARGET_EXPAND_BUILTIN
291 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
293 #undef TARGET_ASM_BYTE_OP
294 #define TARGET_ASM_BYTE_OP "\tdata1\t"
295 #undef TARGET_ASM_ALIGNED_HI_OP
296 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
297 #undef TARGET_ASM_ALIGNED_SI_OP
298 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
299 #undef TARGET_ASM_ALIGNED_DI_OP
300 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
301 #undef TARGET_ASM_UNALIGNED_HI_OP
302 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
303 #undef TARGET_ASM_UNALIGNED_SI_OP
304 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
305 #undef TARGET_ASM_UNALIGNED_DI_OP
306 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
307 #undef TARGET_ASM_INTEGER
308 #define TARGET_ASM_INTEGER ia64_assemble_integer
310 #undef TARGET_ASM_FUNCTION_PROLOGUE
311 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
312 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
313 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
314 #undef TARGET_ASM_FUNCTION_EPILOGUE
315 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
317 #undef TARGET_IN_SMALL_DATA_P
318 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
320 #undef TARGET_SCHED_ADJUST_COST
321 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
322 #undef TARGET_SCHED_ISSUE_RATE
323 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
324 #undef TARGET_SCHED_VARIABLE_ISSUE
325 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
326 #undef TARGET_SCHED_INIT
327 #define TARGET_SCHED_INIT ia64_sched_init
328 #undef TARGET_SCHED_FINISH
329 #define TARGET_SCHED_FINISH ia64_sched_finish
330 #undef TARGET_SCHED_REORDER
331 #define TARGET_SCHED_REORDER ia64_sched_reorder
332 #undef TARGET_SCHED_REORDER2
333 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
335 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
336 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
338 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
339 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
341 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
342 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
344 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
345 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
346 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
347 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
349 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
350 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
351 ia64_first_cycle_multipass_dfa_lookahead_guard
353 #undef TARGET_SCHED_DFA_NEW_CYCLE
354 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
356 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
357 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
359 #undef TARGET_ASM_OUTPUT_MI_THUNK
360 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
361 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
362 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
364 #undef TARGET_ASM_FILE_START
365 #define TARGET_ASM_FILE_START ia64_file_start
367 #undef TARGET_RTX_COSTS
368 #define TARGET_RTX_COSTS ia64_rtx_costs
369 #undef TARGET_ADDRESS_COST
370 #define TARGET_ADDRESS_COST hook_int_rtx_0
372 #undef TARGET_MACHINE_DEPENDENT_REORG
373 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
375 #undef TARGET_ENCODE_SECTION_INFO
376 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
378 /* ??? ABI doesn't allow us to define this. */
380 #undef TARGET_PROMOTE_FUNCTION_ARGS
381 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
384 /* ??? ABI doesn't allow us to define this. */
386 #undef TARGET_PROMOTE_FUNCTION_RETURN
387 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
390 /* ??? Investigate. */
392 #undef TARGET_PROMOTE_PROTOTYPES
393 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
396 #undef TARGET_STRUCT_VALUE_RTX
397 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
398 #undef TARGET_RETURN_IN_MEMORY
399 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
401 #undef TARGET_SETUP_INCOMING_VARARGS
402 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
403 #undef TARGET_STRICT_ARGUMENT_NAMING
404 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
406 struct gcc_target targetm = TARGET_INITIALIZER;
408 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
411 call_operand (rtx op, enum machine_mode mode)
413 if (mode != GET_MODE (op) && mode != VOIDmode)
416 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG
417 || (GET_CODE (op) == SUBREG && GET_CODE (XEXP (op, 0)) == REG));
420 /* Return 1 if OP refers to a symbol in the sdata section. */
423 sdata_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
425 switch (GET_CODE (op))
428 if (GET_CODE (XEXP (op, 0)) != PLUS
429 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF)
431 op = XEXP (XEXP (op, 0), 0);
435 if (CONSTANT_POOL_ADDRESS_P (op))
436 return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold;
438 return SYMBOL_REF_LOCAL_P (op) && SYMBOL_REF_SMALL_P (op);
448 small_addr_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
450 return SYMBOL_REF_SMALL_ADDR_P (op);
453 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
456 got_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
458 switch (GET_CODE (op))
462 if (GET_CODE (op) != PLUS)
464 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
467 if (GET_CODE (op) != CONST_INT)
472 /* Ok if we're not using GOT entries at all. */
473 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
476 /* "Ok" while emitting rtl, since otherwise we won't be provided
477 with the entire offset during emission, which makes it very
478 hard to split the offset into high and low parts. */
479 if (rtx_equal_function_value_matters)
482 /* Force the low 14 bits of the constant to zero so that we do not
483 use up so many GOT entries. */
484 return (INTVAL (op) & 0x3fff) == 0;
487 if (SYMBOL_REF_SMALL_ADDR_P (op))
498 /* Return 1 if OP refers to a symbol. */
501 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
503 switch (GET_CODE (op))
516 /* Return tls_model if OP refers to a TLS symbol. */
519 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
521 if (GET_CODE (op) != SYMBOL_REF)
523 return SYMBOL_REF_TLS_MODEL (op);
527 /* Return 1 if OP refers to a function. */
530 function_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
532 if (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (op))
538 /* Return 1 if OP is setjmp or a similar function. */
540 /* ??? This is an unsatisfying solution. Should rethink. */
543 setjmp_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
548 if (GET_CODE (op) != SYMBOL_REF)
553 /* The following code is borrowed from special_function_p in calls.c. */
555 /* Disregard prefix _, __ or __x. */
558 if (name[1] == '_' && name[2] == 'x')
560 else if (name[1] == '_')
570 && (! strcmp (name, "setjmp")
571 || ! strcmp (name, "setjmp_syscall")))
573 && ! strcmp (name, "sigsetjmp"))
575 && ! strcmp (name, "savectx")));
577 else if ((name[0] == 'q' && name[1] == 's'
578 && ! strcmp (name, "qsetjmp"))
579 || (name[0] == 'v' && name[1] == 'f'
580 && ! strcmp (name, "vfork")))
586 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
589 move_operand (rtx op, enum machine_mode mode)
591 return general_operand (op, mode) && !tls_symbolic_operand (op, mode);
594 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
597 gr_register_operand (rtx op, enum machine_mode mode)
599 if (! register_operand (op, mode))
601 if (GET_CODE (op) == SUBREG)
602 op = SUBREG_REG (op);
603 if (GET_CODE (op) == REG)
605 unsigned int regno = REGNO (op);
606 if (regno < FIRST_PSEUDO_REGISTER)
607 return GENERAL_REGNO_P (regno);
612 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
615 fr_register_operand (rtx op, enum machine_mode mode)
617 if (! register_operand (op, mode))
619 if (GET_CODE (op) == SUBREG)
620 op = SUBREG_REG (op);
621 if (GET_CODE (op) == REG)
623 unsigned int regno = REGNO (op);
624 if (regno < FIRST_PSEUDO_REGISTER)
625 return FR_REGNO_P (regno);
630 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
633 grfr_register_operand (rtx op, enum machine_mode mode)
635 if (! register_operand (op, mode))
637 if (GET_CODE (op) == SUBREG)
638 op = SUBREG_REG (op);
639 if (GET_CODE (op) == REG)
641 unsigned int regno = REGNO (op);
642 if (regno < FIRST_PSEUDO_REGISTER)
643 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
648 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
651 gr_nonimmediate_operand (rtx op, enum machine_mode mode)
653 if (! nonimmediate_operand (op, mode))
655 if (GET_CODE (op) == SUBREG)
656 op = SUBREG_REG (op);
657 if (GET_CODE (op) == REG)
659 unsigned int regno = REGNO (op);
660 if (regno < FIRST_PSEUDO_REGISTER)
661 return GENERAL_REGNO_P (regno);
666 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
669 fr_nonimmediate_operand (rtx op, enum machine_mode mode)
671 if (! nonimmediate_operand (op, mode))
673 if (GET_CODE (op) == SUBREG)
674 op = SUBREG_REG (op);
675 if (GET_CODE (op) == REG)
677 unsigned int regno = REGNO (op);
678 if (regno < FIRST_PSEUDO_REGISTER)
679 return FR_REGNO_P (regno);
684 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
687 grfr_nonimmediate_operand (rtx op, enum machine_mode mode)
689 if (! nonimmediate_operand (op, mode))
691 if (GET_CODE (op) == SUBREG)
692 op = SUBREG_REG (op);
693 if (GET_CODE (op) == REG)
695 unsigned int regno = REGNO (op);
696 if (regno < FIRST_PSEUDO_REGISTER)
697 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
702 /* Return 1 if OP is a GR register operand, or zero. */
705 gr_reg_or_0_operand (rtx op, enum machine_mode mode)
707 return (op == const0_rtx || gr_register_operand (op, mode));
710 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
713 gr_reg_or_5bit_operand (rtx op, enum machine_mode mode)
715 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 32)
716 || GET_CODE (op) == CONSTANT_P_RTX
717 || gr_register_operand (op, mode));
720 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
723 gr_reg_or_6bit_operand (rtx op, enum machine_mode mode)
725 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
726 || GET_CODE (op) == CONSTANT_P_RTX
727 || gr_register_operand (op, mode));
730 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
733 gr_reg_or_8bit_operand (rtx op, enum machine_mode mode)
735 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
736 || GET_CODE (op) == CONSTANT_P_RTX
737 || gr_register_operand (op, mode));
740 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
743 grfr_reg_or_8bit_operand (rtx op, enum machine_mode mode)
745 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
746 || GET_CODE (op) == CONSTANT_P_RTX
747 || grfr_register_operand (op, mode));
750 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
754 gr_reg_or_8bit_adjusted_operand (rtx op, enum machine_mode mode)
756 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
757 || GET_CODE (op) == CONSTANT_P_RTX
758 || gr_register_operand (op, mode));
761 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
762 immediate and an 8 bit adjusted immediate operand. This is necessary
763 because when we emit a compare, we don't know what the condition will be,
764 so we need the union of the immediates accepted by GT and LT. */
767 gr_reg_or_8bit_and_adjusted_operand (rtx op, enum machine_mode mode)
769 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))
770 && CONST_OK_FOR_L (INTVAL (op)))
771 || GET_CODE (op) == CONSTANT_P_RTX
772 || gr_register_operand (op, mode));
775 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
778 gr_reg_or_14bit_operand (rtx op, enum machine_mode mode)
780 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
781 || GET_CODE (op) == CONSTANT_P_RTX
782 || gr_register_operand (op, mode));
785 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
788 gr_reg_or_22bit_operand (rtx op, enum machine_mode mode)
790 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
791 || GET_CODE (op) == CONSTANT_P_RTX
792 || gr_register_operand (op, mode));
795 /* Return 1 if OP is a 6 bit immediate operand. */
798 shift_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
800 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
801 || GET_CODE (op) == CONSTANT_P_RTX);
804 /* Return 1 if OP is a 5 bit immediate operand. */
807 shift_32bit_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
809 return ((GET_CODE (op) == CONST_INT
810 && (INTVAL (op) >= 0 && INTVAL (op) < 32))
811 || GET_CODE (op) == CONSTANT_P_RTX);
814 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
817 shladd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
819 return (GET_CODE (op) == CONST_INT
820 && (INTVAL (op) == 2 || INTVAL (op) == 4
821 || INTVAL (op) == 8 || INTVAL (op) == 16));
824 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
827 fetchadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
829 return (GET_CODE (op) == CONST_INT
830 && (INTVAL (op) == -16 || INTVAL (op) == -8 ||
831 INTVAL (op) == -4 || INTVAL (op) == -1 ||
832 INTVAL (op) == 1 || INTVAL (op) == 4 ||
833 INTVAL (op) == 8 || INTVAL (op) == 16));
836 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
839 fr_reg_or_fp01_operand (rtx op, enum machine_mode mode)
841 return ((GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (op))
842 || fr_register_operand (op, mode));
845 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
846 POST_MODIFY with a REG as displacement. */
849 destination_operand (rtx op, enum machine_mode mode)
851 if (! nonimmediate_operand (op, mode))
853 if (GET_CODE (op) == MEM
854 && GET_CODE (XEXP (op, 0)) == POST_MODIFY
855 && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) == REG)
860 /* Like memory_operand, but don't allow post-increments. */
863 not_postinc_memory_operand (rtx op, enum machine_mode mode)
865 return (memory_operand (op, mode)
866 && GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
869 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
870 signed immediate operand. */
873 normal_comparison_operator (register rtx op, enum machine_mode mode)
875 enum rtx_code code = GET_CODE (op);
876 return ((mode == VOIDmode || GET_MODE (op) == mode)
877 && (code == EQ || code == NE
878 || code == GT || code == LE || code == GTU || code == LEU));
881 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
882 signed immediate operand. */
885 adjusted_comparison_operator (register rtx op, enum machine_mode mode)
887 enum rtx_code code = GET_CODE (op);
888 return ((mode == VOIDmode || GET_MODE (op) == mode)
889 && (code == LT || code == GE || code == LTU || code == GEU));
892 /* Return 1 if this is a signed inequality operator. */
895 signed_inequality_operator (register rtx op, enum machine_mode mode)
897 enum rtx_code code = GET_CODE (op);
898 return ((mode == VOIDmode || GET_MODE (op) == mode)
899 && (code == GE || code == GT
900 || code == LE || code == LT));
903 /* Return 1 if this operator is valid for predication. */
906 predicate_operator (register rtx op, enum machine_mode mode)
908 enum rtx_code code = GET_CODE (op);
909 return ((GET_MODE (op) == mode || mode == VOIDmode)
910 && (code == EQ || code == NE));
913 /* Return 1 if this operator can be used in a conditional operation. */
916 condop_operator (register rtx op, enum machine_mode mode)
918 enum rtx_code code = GET_CODE (op);
919 return ((GET_MODE (op) == mode || mode == VOIDmode)
920 && (code == PLUS || code == MINUS || code == AND
921 || code == IOR || code == XOR));
924 /* Return 1 if this is the ar.lc register. */
927 ar_lc_reg_operand (register rtx op, enum machine_mode mode)
929 return (GET_MODE (op) == DImode
930 && (mode == DImode || mode == VOIDmode)
931 && GET_CODE (op) == REG
932 && REGNO (op) == AR_LC_REGNUM);
935 /* Return 1 if this is the ar.ccv register. */
938 ar_ccv_reg_operand (register rtx op, enum machine_mode mode)
940 return ((GET_MODE (op) == mode || mode == VOIDmode)
941 && GET_CODE (op) == REG
942 && REGNO (op) == AR_CCV_REGNUM);
945 /* Return 1 if this is the ar.pfs register. */
948 ar_pfs_reg_operand (register rtx op, enum machine_mode mode)
950 return ((GET_MODE (op) == mode || mode == VOIDmode)
951 && GET_CODE (op) == REG
952 && REGNO (op) == AR_PFS_REGNUM);
955 /* Like general_operand, but don't allow (mem (addressof)). */
958 general_xfmode_operand (rtx op, enum machine_mode mode)
960 if (! general_operand (op, mode))
962 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
970 destination_xfmode_operand (rtx op, enum machine_mode mode)
972 if (! destination_operand (op, mode))
974 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
982 xfreg_or_fp01_operand (rtx op, enum machine_mode mode)
984 if (GET_CODE (op) == SUBREG)
986 return fr_reg_or_fp01_operand (op, mode);
989 /* Return 1 if OP is valid as a base register in a reg + offset address. */
992 basereg_operand (rtx op, enum machine_mode mode)
994 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
995 checks from pa.c basereg_operand as well? Seems to be OK without them
998 return (register_operand (op, mode) &&
999 REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
1004 ADDR_AREA_NORMAL, /* normal address area */
1005 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
1009 static GTY(()) tree small_ident1;
1010 static GTY(()) tree small_ident2;
1015 if (small_ident1 == 0)
1017 small_ident1 = get_identifier ("small");
1018 small_ident2 = get_identifier ("__small__");
1022 /* Retrieve the address area that has been chosen for the given decl. */
1024 static ia64_addr_area
1025 ia64_get_addr_area (tree decl)
1029 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
1035 id = TREE_VALUE (TREE_VALUE (model_attr));
1036 if (id == small_ident1 || id == small_ident2)
1037 return ADDR_AREA_SMALL;
1039 return ADDR_AREA_NORMAL;
1043 ia64_handle_model_attribute (tree *node, tree name, tree args, int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
1045 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
1046 ia64_addr_area area;
1047 tree arg, decl = *node;
1050 arg = TREE_VALUE (args);
1051 if (arg == small_ident1 || arg == small_ident2)
1053 addr_area = ADDR_AREA_SMALL;
1057 warning ("invalid argument of `%s' attribute",
1058 IDENTIFIER_POINTER (name));
1059 *no_add_attrs = true;
1062 switch (TREE_CODE (decl))
1065 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
1067 && !TREE_STATIC (decl))
1069 error ("%Jan address area attribute cannot be specified for "
1070 "local variables", decl, decl);
1071 *no_add_attrs = true;
1073 area = ia64_get_addr_area (decl);
1074 if (area != ADDR_AREA_NORMAL && addr_area != area)
1076 error ("%Jaddress area of '%s' conflicts with previous "
1077 "declaration", decl, decl);
1078 *no_add_attrs = true;
1083 error ("%Jaddress area attribute cannot be specified for functions",
1085 *no_add_attrs = true;
1089 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
1090 *no_add_attrs = true;
1098 ia64_encode_addr_area (tree decl, rtx symbol)
1102 flags = SYMBOL_REF_FLAGS (symbol);
1103 switch (ia64_get_addr_area (decl))
1105 case ADDR_AREA_NORMAL: break;
1106 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
1109 SYMBOL_REF_FLAGS (symbol) = flags;
1113 ia64_encode_section_info (tree decl, rtx rtl, int first)
1115 default_encode_section_info (decl, rtl, first);
1117 if (TREE_CODE (decl) == VAR_DECL
1118 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
1119 ia64_encode_addr_area (decl, XEXP (rtl, 0));
1122 /* Return 1 if the operands of a move are ok. */
1125 ia64_move_ok (rtx dst, rtx src)
1127 /* If we're under init_recog_no_volatile, we'll not be able to use
1128 memory_operand. So check the code directly and don't worry about
1129 the validity of the underlying address, which should have been
1130 checked elsewhere anyway. */
1131 if (GET_CODE (dst) != MEM)
1133 if (GET_CODE (src) == MEM)
1135 if (register_operand (src, VOIDmode))
1138 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1139 if (INTEGRAL_MODE_P (GET_MODE (dst)))
1140 return src == const0_rtx;
1142 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
1146 addp4_optimize_ok (rtx op1, rtx op2)
1148 return (basereg_operand (op1, GET_MODE(op1)) !=
1149 basereg_operand (op2, GET_MODE(op2)));
1152 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1153 Return the length of the field, or <= 0 on failure. */
1156 ia64_depz_field_mask (rtx rop, rtx rshift)
1158 unsigned HOST_WIDE_INT op = INTVAL (rop);
1159 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
1161 /* Get rid of the zero bits we're shifting in. */
1164 /* We must now have a solid block of 1's at bit 0. */
1165 return exact_log2 (op + 1);
1168 /* Expand a symbolic constant load. */
1171 ia64_expand_load_address (rtx dest, rtx src)
1173 if (tls_symbolic_operand (src, VOIDmode))
1175 if (GET_CODE (dest) != REG)
1178 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1179 having to pointer-extend the value afterward. Other forms of address
1180 computation below are also more natural to compute as 64-bit quantities.
1181 If we've been given an SImode destination register, change it. */
1182 if (GET_MODE (dest) != Pmode)
1183 dest = gen_rtx_REG (Pmode, REGNO (dest));
1185 if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (src))
1187 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
1190 else if (TARGET_AUTO_PIC)
1192 emit_insn (gen_load_gprel64 (dest, src));
1195 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1197 emit_insn (gen_load_fptr (dest, src));
1200 else if (sdata_symbolic_operand (src, VOIDmode))
1202 emit_insn (gen_load_gprel (dest, src));
1206 if (GET_CODE (src) == CONST
1207 && GET_CODE (XEXP (src, 0)) == PLUS
1208 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
1209 && (INTVAL (XEXP (XEXP (src, 0), 1)) & 0x1fff) != 0)
1211 rtx sym = XEXP (XEXP (src, 0), 0);
1212 HOST_WIDE_INT ofs, hi, lo;
1214 /* Split the offset into a sign extended 14-bit low part
1215 and a complementary high part. */
1216 ofs = INTVAL (XEXP (XEXP (src, 0), 1));
1217 lo = ((ofs & 0x3fff) ^ 0x2000) - 0x2000;
1220 ia64_expand_load_address (dest, plus_constant (sym, hi));
1221 emit_insn (gen_adddi3 (dest, dest, GEN_INT (lo)));
1227 tmp = gen_rtx_HIGH (Pmode, src);
1228 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1229 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1231 tmp = gen_rtx_LO_SUM (GET_MODE (dest), dest, src);
1232 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1236 static GTY(()) rtx gen_tls_tga;
1238 gen_tls_get_addr (void)
1241 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1245 static GTY(()) rtx thread_pointer_rtx;
1247 gen_thread_pointer (void)
1249 if (!thread_pointer_rtx)
1251 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1252 RTX_UNCHANGING_P (thread_pointer_rtx) = 1;
1254 return thread_pointer_rtx;
1258 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1)
1260 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1265 case TLS_MODEL_GLOBAL_DYNAMIC:
1268 tga_op1 = gen_reg_rtx (Pmode);
1269 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1270 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1271 RTX_UNCHANGING_P (tga_op1) = 1;
1273 tga_op2 = gen_reg_rtx (Pmode);
1274 emit_insn (gen_load_ltoff_dtprel (tga_op2, op1));
1275 tga_op2 = gen_rtx_MEM (Pmode, tga_op2);
1276 RTX_UNCHANGING_P (tga_op2) = 1;
1278 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1279 LCT_CONST, Pmode, 2, tga_op1,
1280 Pmode, tga_op2, Pmode);
1282 insns = get_insns ();
1285 if (GET_MODE (op0) != Pmode)
1287 emit_libcall_block (insns, op0, tga_ret, op1);
1290 case TLS_MODEL_LOCAL_DYNAMIC:
1291 /* ??? This isn't the completely proper way to do local-dynamic
1292 If the call to __tls_get_addr is used only by a single symbol,
1293 then we should (somehow) move the dtprel to the second arg
1294 to avoid the extra add. */
1297 tga_op1 = gen_reg_rtx (Pmode);
1298 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1299 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1300 RTX_UNCHANGING_P (tga_op1) = 1;
1302 tga_op2 = const0_rtx;
1304 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1305 LCT_CONST, Pmode, 2, tga_op1,
1306 Pmode, tga_op2, Pmode);
1308 insns = get_insns ();
1311 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1313 tmp = gen_reg_rtx (Pmode);
1314 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1316 if (!register_operand (op0, Pmode))
1317 op0 = gen_reg_rtx (Pmode);
1320 emit_insn (gen_load_dtprel (op0, op1));
1321 emit_insn (gen_adddi3 (op0, tmp, op0));
1324 emit_insn (gen_add_dtprel (op0, tmp, op1));
1327 case TLS_MODEL_INITIAL_EXEC:
1328 tmp = gen_reg_rtx (Pmode);
1329 emit_insn (gen_load_ltoff_tprel (tmp, op1));
1330 tmp = gen_rtx_MEM (Pmode, tmp);
1331 RTX_UNCHANGING_P (tmp) = 1;
1332 tmp = force_reg (Pmode, tmp);
1334 if (!register_operand (op0, Pmode))
1335 op0 = gen_reg_rtx (Pmode);
1336 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1339 case TLS_MODEL_LOCAL_EXEC:
1340 if (!register_operand (op0, Pmode))
1341 op0 = gen_reg_rtx (Pmode);
1344 emit_insn (gen_load_tprel (op0, op1));
1345 emit_insn (gen_adddi3 (op0, gen_thread_pointer (), op0));
1348 emit_insn (gen_add_tprel (op0, gen_thread_pointer (), op1));
1355 if (orig_op0 == op0)
1357 if (GET_MODE (orig_op0) == Pmode)
1359 return gen_lowpart (GET_MODE (orig_op0), op0);
1363 ia64_expand_move (rtx op0, rtx op1)
1365 enum machine_mode mode = GET_MODE (op0);
1367 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1368 op1 = force_reg (mode, op1);
1370 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1372 enum tls_model tls_kind;
1373 if ((tls_kind = tls_symbolic_operand (op1, VOIDmode)))
1374 return ia64_expand_tls_address (tls_kind, op0, op1);
1376 if (!TARGET_NO_PIC && reload_completed)
1378 ia64_expand_load_address (op0, op1);
1386 /* Split a move from OP1 to OP0 conditional on COND. */
1389 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1391 rtx insn, first = get_last_insn ();
1393 emit_move_insn (op0, op1);
1395 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1397 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1401 /* Split a post-reload TImode or TFmode reference into two DImode
1402 components. This is made extra difficult by the fact that we do
1403 not get any scratch registers to work with, because reload cannot
1404 be prevented from giving us a scratch that overlaps the register
1405 pair involved. So instead, when addressing memory, we tweak the
1406 pointer register up and back down with POST_INCs. Or up and not
1407 back down when we can get away with it.
1409 REVERSED is true when the loads must be done in reversed order
1410 (high word first) for correctness. DEAD is true when the pointer
1411 dies with the second insn we generate and therefore the second
1412 address must not carry a postmodify.
1414 May return an insn which is to be emitted after the moves. */
1417 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1421 switch (GET_CODE (in))
1424 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1425 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1430 /* Cannot occur reversed. */
1431 if (reversed) abort ();
1433 if (GET_MODE (in) != TFmode)
1434 split_double (in, &out[0], &out[1]);
1436 /* split_double does not understand how to split a TFmode
1437 quantity into a pair of DImode constants. */
1440 unsigned HOST_WIDE_INT p[2];
1441 long l[4]; /* TFmode is 128 bits */
1443 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1444 real_to_target (l, &r, TFmode);
1446 if (FLOAT_WORDS_BIG_ENDIAN)
1448 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1449 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1453 p[0] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1454 p[1] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1456 out[0] = GEN_INT (p[0]);
1457 out[1] = GEN_INT (p[1]);
1463 rtx base = XEXP (in, 0);
1466 switch (GET_CODE (base))
1471 out[0] = adjust_automodify_address
1472 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1473 out[1] = adjust_automodify_address
1474 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1478 /* Reversal requires a pre-increment, which can only
1479 be done as a separate insn. */
1480 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1481 out[0] = adjust_automodify_address
1482 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1483 out[1] = adjust_address (in, DImode, 0);
1488 if (reversed || dead) abort ();
1489 /* Just do the increment in two steps. */
1490 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1491 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1495 if (reversed || dead) abort ();
1496 /* Add 8, subtract 24. */
1497 base = XEXP (base, 0);
1498 out[0] = adjust_automodify_address
1499 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1500 out[1] = adjust_automodify_address
1502 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1507 if (reversed || dead) abort ();
1508 /* Extract and adjust the modification. This case is
1509 trickier than the others, because we might have an
1510 index register, or we might have a combined offset that
1511 doesn't fit a signed 9-bit displacement field. We can
1512 assume the incoming expression is already legitimate. */
1513 offset = XEXP (base, 1);
1514 base = XEXP (base, 0);
1516 out[0] = adjust_automodify_address
1517 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1519 if (GET_CODE (XEXP (offset, 1)) == REG)
1521 /* Can't adjust the postmodify to match. Emit the
1522 original, then a separate addition insn. */
1523 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1524 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1526 else if (GET_CODE (XEXP (offset, 1)) != CONST_INT)
1528 else if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1530 /* Again the postmodify cannot be made to match, but
1531 in this case it's more efficient to get rid of the
1532 postmodify entirely and fix up with an add insn. */
1533 out[1] = adjust_automodify_address (in, DImode, base, 8);
1534 fixup = gen_adddi3 (base, base,
1535 GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1539 /* Combined offset still fits in the displacement field.
1540 (We cannot overflow it at the high end.) */
1541 out[1] = adjust_automodify_address
1543 gen_rtx_POST_MODIFY (Pmode, base,
1544 gen_rtx_PLUS (Pmode, base,
1545 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1563 /* Split a TImode or TFmode move instruction after reload.
1564 This is used by *movtf_internal and *movti_internal. */
1566 ia64_split_tmode_move (rtx operands[])
1568 rtx in[2], out[2], insn;
1571 bool reversed = false;
1573 /* It is possible for reload to decide to overwrite a pointer with
1574 the value it points to. In that case we have to do the loads in
1575 the appropriate order so that the pointer is not destroyed too
1576 early. Also we must not generate a postmodify for that second
1577 load, or rws_access_regno will abort. */
1578 if (GET_CODE (operands[1]) == MEM
1579 && reg_overlap_mentioned_p (operands[0], operands[1]))
1581 rtx base = XEXP (operands[1], 0);
1582 while (GET_CODE (base) != REG)
1583 base = XEXP (base, 0);
1585 if (REGNO (base) == REGNO (operands[0]))
1589 /* Another reason to do the moves in reversed order is if the first
1590 element of the target register pair is also the second element of
1591 the source register pair. */
1592 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1593 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1596 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1597 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1599 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1600 if (GET_CODE (EXP) == MEM \
1601 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1602 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1603 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1604 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1605 XEXP (XEXP (EXP, 0), 0), \
1608 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1609 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1610 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1612 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1613 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1614 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1617 emit_insn (fixup[0]);
1619 emit_insn (fixup[1]);
1621 #undef MAYBE_ADD_REG_INC_NOTE
1624 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1625 through memory plus an extra GR scratch register. Except that you can
1626 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1627 SECONDARY_RELOAD_CLASS, but not both.
1629 We got into problems in the first place by allowing a construct like
1630 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1631 This solution attempts to prevent this situation from occurring. When
1632 we see something like the above, we spill the inner register to memory. */
1635 spill_xfmode_operand (rtx in, int force)
1637 if (GET_CODE (in) == SUBREG
1638 && GET_MODE (SUBREG_REG (in)) == TImode
1639 && GET_CODE (SUBREG_REG (in)) == REG)
1641 rtx mem = gen_mem_addressof (SUBREG_REG (in), NULL_TREE, /*rescan=*/true);
1642 return gen_rtx_MEM (XFmode, copy_to_reg (XEXP (mem, 0)));
1644 else if (force && GET_CODE (in) == REG)
1646 rtx mem = gen_mem_addressof (in, NULL_TREE, /*rescan=*/true);
1647 return gen_rtx_MEM (XFmode, copy_to_reg (XEXP (mem, 0)));
1649 else if (GET_CODE (in) == MEM
1650 && GET_CODE (XEXP (in, 0)) == ADDRESSOF)
1651 return change_address (in, XFmode, copy_to_reg (XEXP (in, 0)));
1656 /* Emit comparison instruction if necessary, returning the expression
1657 that holds the compare result in the proper mode. */
1659 static GTY(()) rtx cmptf_libfunc;
1662 ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
1664 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1667 /* If we have a BImode input, then we already have a compare result, and
1668 do not need to emit another comparison. */
1669 if (GET_MODE (op0) == BImode)
1671 if ((code == NE || code == EQ) && op1 == const0_rtx)
1676 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1677 magic number as its third argument, that indicates what to do.
1678 The return value is an integer to be compared against zero. */
1679 else if (TARGET_HPUX && GET_MODE (op0) == TFmode)
1682 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1688 enum rtx_code ncode;
1690 if (GET_MODE (op1) != TFmode)
1694 /* 1 = equal, 0 = not equal. Equality operators do
1695 not raise FP_INVALID when given an SNaN operand. */
1696 case EQ: magic = QCMP_EQ; ncode = NE; break;
1697 case NE: magic = QCMP_EQ; ncode = EQ; break;
1698 /* isunordered() from C99. */
1699 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1700 /* Relational operators raise FP_INVALID when given
1702 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1703 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1704 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1705 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1706 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1707 Expanders for buneq etc. weuld have to be added to ia64.md
1708 for this to be useful. */
1714 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1715 op0, TFmode, op1, TFmode,
1716 GEN_INT (magic), DImode);
1717 cmp = gen_reg_rtx (BImode);
1718 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1719 gen_rtx_fmt_ee (ncode, BImode,
1722 insns = get_insns ();
1725 emit_libcall_block (insns, cmp, cmp,
1726 gen_rtx_fmt_ee (code, BImode, op0, op1));
1731 cmp = gen_reg_rtx (BImode);
1732 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1733 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1737 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1740 /* Emit the appropriate sequence for a call. */
1743 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
1748 addr = XEXP (addr, 0);
1749 addr = convert_memory_address (DImode, addr);
1750 b0 = gen_rtx_REG (DImode, R_BR (0));
1752 /* ??? Should do this for functions known to bind local too. */
1753 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1756 insn = gen_sibcall_nogp (addr);
1758 insn = gen_call_nogp (addr, b0);
1760 insn = gen_call_value_nogp (retval, addr, b0);
1761 insn = emit_call_insn (insn);
1766 insn = gen_sibcall_gp (addr);
1768 insn = gen_call_gp (addr, b0);
1770 insn = gen_call_value_gp (retval, addr, b0);
1771 insn = emit_call_insn (insn);
1773 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1777 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1781 ia64_reload_gp (void)
1785 if (current_frame_info.reg_save_gp)
1786 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1789 HOST_WIDE_INT offset;
1791 offset = (current_frame_info.spill_cfa_off
1792 + current_frame_info.spill_size);
1793 if (frame_pointer_needed)
1795 tmp = hard_frame_pointer_rtx;
1800 tmp = stack_pointer_rtx;
1801 offset = current_frame_info.total_size - offset;
1804 if (CONST_OK_FOR_I (offset))
1805 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1806 tmp, GEN_INT (offset)));
1809 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
1810 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1811 pic_offset_table_rtx, tmp));
1814 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
1817 emit_move_insn (pic_offset_table_rtx, tmp);
1821 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
1822 rtx scratch_b, int noreturn_p, int sibcall_p)
1825 bool is_desc = false;
1827 /* If we find we're calling through a register, then we're actually
1828 calling through a descriptor, so load up the values. */
1829 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
1834 /* ??? We are currently constrained to *not* use peep2, because
1835 we can legitimately change the global lifetime of the GP
1836 (in the form of killing where previously live). This is
1837 because a call through a descriptor doesn't use the previous
1838 value of the GP, while a direct call does, and we do not
1839 commit to either form until the split here.
1841 That said, this means that we lack precise life info for
1842 whether ADDR is dead after this call. This is not terribly
1843 important, since we can fix things up essentially for free
1844 with the POST_DEC below, but it's nice to not use it when we
1845 can immediately tell it's not necessary. */
1846 addr_dead_p = ((noreturn_p || sibcall_p
1847 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
1849 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
1851 /* Load the code address into scratch_b. */
1852 tmp = gen_rtx_POST_INC (Pmode, addr);
1853 tmp = gen_rtx_MEM (Pmode, tmp);
1854 emit_move_insn (scratch_r, tmp);
1855 emit_move_insn (scratch_b, scratch_r);
1857 /* Load the GP address. If ADDR is not dead here, then we must
1858 revert the change made above via the POST_INCREMENT. */
1860 tmp = gen_rtx_POST_DEC (Pmode, addr);
1863 tmp = gen_rtx_MEM (Pmode, tmp);
1864 emit_move_insn (pic_offset_table_rtx, tmp);
1871 insn = gen_sibcall_nogp (addr);
1873 insn = gen_call_value_nogp (retval, addr, retaddr);
1875 insn = gen_call_nogp (addr, retaddr);
1876 emit_call_insn (insn);
1878 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
1882 /* Begin the assembly file. */
1885 ia64_file_start (void)
1887 default_file_start ();
1888 emit_safe_across_calls ();
1892 emit_safe_across_calls (void)
1894 unsigned int rs, re;
1901 while (rs < 64 && call_used_regs[PR_REG (rs)])
1905 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
1909 fputs ("\t.pred.safe_across_calls ", asm_out_file);
1913 fputc (',', asm_out_file);
1915 fprintf (asm_out_file, "p%u", rs);
1917 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
1921 fputc ('\n', asm_out_file);
1924 /* Helper function for ia64_compute_frame_size: find an appropriate general
1925 register to spill some special register to. SPECIAL_SPILL_MASK contains
1926 bits in GR0 to GR31 that have already been allocated by this routine.
1927 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1930 find_gr_spill (int try_locals)
1934 /* If this is a leaf function, first try an otherwise unused
1935 call-clobbered register. */
1936 if (current_function_is_leaf)
1938 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1939 if (! regs_ever_live[regno]
1940 && call_used_regs[regno]
1941 && ! fixed_regs[regno]
1942 && ! global_regs[regno]
1943 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1945 current_frame_info.gr_used_mask |= 1 << regno;
1952 regno = current_frame_info.n_local_regs;
1953 /* If there is a frame pointer, then we can't use loc79, because
1954 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1955 reg_name switching code in ia64_expand_prologue. */
1956 if (regno < (80 - frame_pointer_needed))
1958 current_frame_info.n_local_regs = regno + 1;
1959 return LOC_REG (0) + regno;
1963 /* Failed to find a general register to spill to. Must use stack. */
1967 /* In order to make for nice schedules, we try to allocate every temporary
1968 to a different register. We must of course stay away from call-saved,
1969 fixed, and global registers. We must also stay away from registers
1970 allocated in current_frame_info.gr_used_mask, since those include regs
1971 used all through the prologue.
1973 Any register allocated here must be used immediately. The idea is to
1974 aid scheduling, not to solve data flow problems. */
1976 static int last_scratch_gr_reg;
1979 next_scratch_gr_reg (void)
1983 for (i = 0; i < 32; ++i)
1985 regno = (last_scratch_gr_reg + i + 1) & 31;
1986 if (call_used_regs[regno]
1987 && ! fixed_regs[regno]
1988 && ! global_regs[regno]
1989 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1991 last_scratch_gr_reg = regno;
1996 /* There must be _something_ available. */
2000 /* Helper function for ia64_compute_frame_size, called through
2001 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2004 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2006 unsigned int regno = REGNO (reg);
2009 unsigned int i, n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2010 for (i = 0; i < n; ++i)
2011 current_frame_info.gr_used_mask |= 1 << (regno + i);
2015 /* Returns the number of bytes offset between the frame pointer and the stack
2016 pointer for the current function. SIZE is the number of bytes of space
2017 needed for local variables. */
2020 ia64_compute_frame_size (HOST_WIDE_INT size)
2022 HOST_WIDE_INT total_size;
2023 HOST_WIDE_INT spill_size = 0;
2024 HOST_WIDE_INT extra_spill_size = 0;
2025 HOST_WIDE_INT pretend_args_size;
2028 int spilled_gr_p = 0;
2029 int spilled_fr_p = 0;
2033 if (current_frame_info.initialized)
2036 memset (¤t_frame_info, 0, sizeof current_frame_info);
2037 CLEAR_HARD_REG_SET (mask);
2039 /* Don't allocate scratches to the return register. */
2040 diddle_return_value (mark_reg_gr_used_mask, NULL);
2042 /* Don't allocate scratches to the EH scratch registers. */
2043 if (cfun->machine->ia64_eh_epilogue_sp)
2044 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2045 if (cfun->machine->ia64_eh_epilogue_bsp)
2046 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2048 /* Find the size of the register stack frame. We have only 80 local
2049 registers, because we reserve 8 for the inputs and 8 for the
2052 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2053 since we'll be adjusting that down later. */
2054 regno = LOC_REG (78) + ! frame_pointer_needed;
2055 for (; regno >= LOC_REG (0); regno--)
2056 if (regs_ever_live[regno])
2058 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2060 /* For functions marked with the syscall_linkage attribute, we must mark
2061 all eight input registers as in use, so that locals aren't visible to
2064 if (cfun->machine->n_varargs > 0
2065 || lookup_attribute ("syscall_linkage",
2066 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2067 current_frame_info.n_input_regs = 8;
2070 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2071 if (regs_ever_live[regno])
2073 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2076 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2077 if (regs_ever_live[regno])
2079 i = regno - OUT_REG (0) + 1;
2081 /* When -p profiling, we need one output register for the mcount argument.
2082 Likewise for -a profiling for the bb_init_func argument. For -ax
2083 profiling, we need two output registers for the two bb_init_trace_func
2085 if (current_function_profile)
2087 current_frame_info.n_output_regs = i;
2089 /* ??? No rotating register support yet. */
2090 current_frame_info.n_rotate_regs = 0;
2092 /* Discover which registers need spilling, and how much room that
2093 will take. Begin with floating point and general registers,
2094 which will always wind up on the stack. */
2096 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2097 if (regs_ever_live[regno] && ! call_used_regs[regno])
2099 SET_HARD_REG_BIT (mask, regno);
2105 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2106 if (regs_ever_live[regno] && ! call_used_regs[regno])
2108 SET_HARD_REG_BIT (mask, regno);
2114 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2115 if (regs_ever_live[regno] && ! call_used_regs[regno])
2117 SET_HARD_REG_BIT (mask, regno);
2122 /* Now come all special registers that might get saved in other
2123 general registers. */
2125 if (frame_pointer_needed)
2127 current_frame_info.reg_fp = find_gr_spill (1);
2128 /* If we did not get a register, then we take LOC79. This is guaranteed
2129 to be free, even if regs_ever_live is already set, because this is
2130 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2131 as we don't count loc79 above. */
2132 if (current_frame_info.reg_fp == 0)
2134 current_frame_info.reg_fp = LOC_REG (79);
2135 current_frame_info.n_local_regs++;
2139 if (! current_function_is_leaf)
2141 /* Emit a save of BR0 if we call other functions. Do this even
2142 if this function doesn't return, as EH depends on this to be
2143 able to unwind the stack. */
2144 SET_HARD_REG_BIT (mask, BR_REG (0));
2146 current_frame_info.reg_save_b0 = find_gr_spill (1);
2147 if (current_frame_info.reg_save_b0 == 0)
2153 /* Similarly for ar.pfs. */
2154 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2155 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2156 if (current_frame_info.reg_save_ar_pfs == 0)
2158 extra_spill_size += 8;
2162 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2163 registers are clobbered, so we fall back to the stack. */
2164 current_frame_info.reg_save_gp
2165 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
2166 if (current_frame_info.reg_save_gp == 0)
2168 SET_HARD_REG_BIT (mask, GR_REG (1));
2175 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
2177 SET_HARD_REG_BIT (mask, BR_REG (0));
2182 if (regs_ever_live[AR_PFS_REGNUM])
2184 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2185 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2186 if (current_frame_info.reg_save_ar_pfs == 0)
2188 extra_spill_size += 8;
2194 /* Unwind descriptor hackery: things are most efficient if we allocate
2195 consecutive GR save registers for RP, PFS, FP in that order. However,
2196 it is absolutely critical that FP get the only hard register that's
2197 guaranteed to be free, so we allocated it first. If all three did
2198 happen to be allocated hard regs, and are consecutive, rearrange them
2199 into the preferred order now. */
2200 if (current_frame_info.reg_fp != 0
2201 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
2202 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
2204 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
2205 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
2206 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
2209 /* See if we need to store the predicate register block. */
2210 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2211 if (regs_ever_live[regno] && ! call_used_regs[regno])
2213 if (regno <= PR_REG (63))
2215 SET_HARD_REG_BIT (mask, PR_REG (0));
2216 current_frame_info.reg_save_pr = find_gr_spill (1);
2217 if (current_frame_info.reg_save_pr == 0)
2219 extra_spill_size += 8;
2223 /* ??? Mark them all as used so that register renaming and such
2224 are free to use them. */
2225 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2226 regs_ever_live[regno] = 1;
2229 /* If we're forced to use st8.spill, we're forced to save and restore
2230 ar.unat as well. The check for existing liveness allows inline asm
2231 to touch ar.unat. */
2232 if (spilled_gr_p || cfun->machine->n_varargs
2233 || regs_ever_live[AR_UNAT_REGNUM])
2235 regs_ever_live[AR_UNAT_REGNUM] = 1;
2236 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2237 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
2238 if (current_frame_info.reg_save_ar_unat == 0)
2240 extra_spill_size += 8;
2245 if (regs_ever_live[AR_LC_REGNUM])
2247 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2248 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
2249 if (current_frame_info.reg_save_ar_lc == 0)
2251 extra_spill_size += 8;
2256 /* If we have an odd number of words of pretend arguments written to
2257 the stack, then the FR save area will be unaligned. We round the
2258 size of this area up to keep things 16 byte aligned. */
2260 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
2262 pretend_args_size = current_function_pretend_args_size;
2264 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2265 + current_function_outgoing_args_size);
2266 total_size = IA64_STACK_ALIGN (total_size);
2268 /* We always use the 16-byte scratch area provided by the caller, but
2269 if we are a leaf function, there's no one to which we need to provide
2271 if (current_function_is_leaf)
2272 total_size = MAX (0, total_size - 16);
2274 current_frame_info.total_size = total_size;
2275 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2276 current_frame_info.spill_size = spill_size;
2277 current_frame_info.extra_spill_size = extra_spill_size;
2278 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2279 current_frame_info.n_spilled = n_spilled;
2280 current_frame_info.initialized = reload_completed;
2283 /* Compute the initial difference between the specified pair of registers. */
2286 ia64_initial_elimination_offset (int from, int to)
2288 HOST_WIDE_INT offset;
2290 ia64_compute_frame_size (get_frame_size ());
2293 case FRAME_POINTER_REGNUM:
2294 if (to == HARD_FRAME_POINTER_REGNUM)
2296 if (current_function_is_leaf)
2297 offset = -current_frame_info.total_size;
2299 offset = -(current_frame_info.total_size
2300 - current_function_outgoing_args_size - 16);
2302 else if (to == STACK_POINTER_REGNUM)
2304 if (current_function_is_leaf)
2307 offset = 16 + current_function_outgoing_args_size;
2313 case ARG_POINTER_REGNUM:
2314 /* Arguments start above the 16 byte save area, unless stdarg
2315 in which case we store through the 16 byte save area. */
2316 if (to == HARD_FRAME_POINTER_REGNUM)
2317 offset = 16 - current_function_pretend_args_size;
2318 else if (to == STACK_POINTER_REGNUM)
2319 offset = (current_frame_info.total_size
2320 + 16 - current_function_pretend_args_size);
2332 /* If there are more than a trivial number of register spills, we use
2333 two interleaved iterators so that we can get two memory references
2336 In order to simplify things in the prologue and epilogue expanders,
2337 we use helper functions to fix up the memory references after the
2338 fact with the appropriate offsets to a POST_MODIFY memory mode.
2339 The following data structure tracks the state of the two iterators
2340 while insns are being emitted. */
2342 struct spill_fill_data
2344 rtx init_after; /* point at which to emit initializations */
2345 rtx init_reg[2]; /* initial base register */
2346 rtx iter_reg[2]; /* the iterator registers */
2347 rtx *prev_addr[2]; /* address of last memory use */
2348 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2349 HOST_WIDE_INT prev_off[2]; /* last offset */
2350 int n_iter; /* number of iterators in use */
2351 int next_iter; /* next iterator to use */
2352 unsigned int save_gr_used_mask;
2355 static struct spill_fill_data spill_fill_data;
2358 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2362 spill_fill_data.init_after = get_last_insn ();
2363 spill_fill_data.init_reg[0] = init_reg;
2364 spill_fill_data.init_reg[1] = init_reg;
2365 spill_fill_data.prev_addr[0] = NULL;
2366 spill_fill_data.prev_addr[1] = NULL;
2367 spill_fill_data.prev_insn[0] = NULL;
2368 spill_fill_data.prev_insn[1] = NULL;
2369 spill_fill_data.prev_off[0] = cfa_off;
2370 spill_fill_data.prev_off[1] = cfa_off;
2371 spill_fill_data.next_iter = 0;
2372 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2374 spill_fill_data.n_iter = 1 + (n_spills > 2);
2375 for (i = 0; i < spill_fill_data.n_iter; ++i)
2377 int regno = next_scratch_gr_reg ();
2378 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2379 current_frame_info.gr_used_mask |= 1 << regno;
2384 finish_spill_pointers (void)
2386 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2390 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2392 int iter = spill_fill_data.next_iter;
2393 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2394 rtx disp_rtx = GEN_INT (disp);
2397 if (spill_fill_data.prev_addr[iter])
2399 if (CONST_OK_FOR_N (disp))
2401 *spill_fill_data.prev_addr[iter]
2402 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2403 gen_rtx_PLUS (DImode,
2404 spill_fill_data.iter_reg[iter],
2406 REG_NOTES (spill_fill_data.prev_insn[iter])
2407 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2408 REG_NOTES (spill_fill_data.prev_insn[iter]));
2412 /* ??? Could use register post_modify for loads. */
2413 if (! CONST_OK_FOR_I (disp))
2415 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2416 emit_move_insn (tmp, disp_rtx);
2419 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2420 spill_fill_data.iter_reg[iter], disp_rtx));
2423 /* Micro-optimization: if we've created a frame pointer, it's at
2424 CFA 0, which may allow the real iterator to be initialized lower,
2425 slightly increasing parallelism. Also, if there are few saves
2426 it may eliminate the iterator entirely. */
2428 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2429 && frame_pointer_needed)
2431 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2432 set_mem_alias_set (mem, get_varargs_alias_set ());
2440 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2441 spill_fill_data.init_reg[iter]);
2446 if (! CONST_OK_FOR_I (disp))
2448 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2449 emit_move_insn (tmp, disp_rtx);
2453 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2454 spill_fill_data.init_reg[iter],
2461 /* Careful for being the first insn in a sequence. */
2462 if (spill_fill_data.init_after)
2463 insn = emit_insn_after (seq, spill_fill_data.init_after);
2466 rtx first = get_insns ();
2468 insn = emit_insn_before (seq, first);
2470 insn = emit_insn (seq);
2472 spill_fill_data.init_after = insn;
2474 /* If DISP is 0, we may or may not have a further adjustment
2475 afterward. If we do, then the load/store insn may be modified
2476 to be a post-modify. If we don't, then this copy may be
2477 eliminated by copyprop_hardreg_forward, which makes this
2478 insn garbage, which runs afoul of the sanity check in
2479 propagate_one_insn. So mark this insn as legal to delete. */
2481 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2485 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2487 /* ??? Not all of the spills are for varargs, but some of them are.
2488 The rest of the spills belong in an alias set of their own. But
2489 it doesn't actually hurt to include them here. */
2490 set_mem_alias_set (mem, get_varargs_alias_set ());
2492 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2493 spill_fill_data.prev_off[iter] = cfa_off;
2495 if (++iter >= spill_fill_data.n_iter)
2497 spill_fill_data.next_iter = iter;
2503 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
2506 int iter = spill_fill_data.next_iter;
2509 mem = spill_restore_mem (reg, cfa_off);
2510 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2511 spill_fill_data.prev_insn[iter] = insn;
2518 RTX_FRAME_RELATED_P (insn) = 1;
2520 /* Don't even pretend that the unwind code can intuit its way
2521 through a pair of interleaved post_modify iterators. Just
2522 provide the correct answer. */
2524 if (frame_pointer_needed)
2526 base = hard_frame_pointer_rtx;
2531 base = stack_pointer_rtx;
2532 off = current_frame_info.total_size - cfa_off;
2536 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2537 gen_rtx_SET (VOIDmode,
2538 gen_rtx_MEM (GET_MODE (reg),
2539 plus_constant (base, off)),
2546 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
2548 int iter = spill_fill_data.next_iter;
2551 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2552 GEN_INT (cfa_off)));
2553 spill_fill_data.prev_insn[iter] = insn;
2556 /* Wrapper functions that discards the CONST_INT spill offset. These
2557 exist so that we can give gr_spill/gr_fill the offset they need and
2558 use a consistent function interface. */
2561 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2563 return gen_movdi (dest, src);
2567 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2569 return gen_fr_spill (dest, src);
2573 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2575 return gen_fr_restore (dest, src);
2578 /* Called after register allocation to add any instructions needed for the
2579 prologue. Using a prologue insn is favored compared to putting all of the
2580 instructions in output_function_prologue(), since it allows the scheduler
2581 to intermix instructions with the saves of the caller saved registers. In
2582 some cases, it might be necessary to emit a barrier instruction as the last
2583 insn to prevent such scheduling.
2585 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2586 so that the debug info generation code can handle them properly.
2588 The register save area is layed out like so:
2590 [ varargs spill area ]
2591 [ fr register spill area ]
2592 [ br register spill area ]
2593 [ ar register spill area ]
2594 [ pr register spill area ]
2595 [ gr register spill area ] */
2597 /* ??? Get inefficient code when the frame size is larger than can fit in an
2598 adds instruction. */
2601 ia64_expand_prologue (void)
2603 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2604 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2607 ia64_compute_frame_size (get_frame_size ());
2608 last_scratch_gr_reg = 15;
2610 /* If there is no epilogue, then we don't need some prologue insns.
2611 We need to avoid emitting the dead prologue insns, because flow
2612 will complain about them. */
2617 for (e = EXIT_BLOCK_PTR->pred; e ; e = e->pred_next)
2618 if ((e->flags & EDGE_FAKE) == 0
2619 && (e->flags & EDGE_FALLTHRU) != 0)
2621 epilogue_p = (e != NULL);
2626 /* Set the local, input, and output register names. We need to do this
2627 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2628 half. If we use in/loc/out register names, then we get assembler errors
2629 in crtn.S because there is no alloc insn or regstk directive in there. */
2630 if (! TARGET_REG_NAMES)
2632 int inputs = current_frame_info.n_input_regs;
2633 int locals = current_frame_info.n_local_regs;
2634 int outputs = current_frame_info.n_output_regs;
2636 for (i = 0; i < inputs; i++)
2637 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2638 for (i = 0; i < locals; i++)
2639 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2640 for (i = 0; i < outputs; i++)
2641 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2644 /* Set the frame pointer register name. The regnum is logically loc79,
2645 but of course we'll not have allocated that many locals. Rather than
2646 worrying about renumbering the existing rtxs, we adjust the name. */
2647 /* ??? This code means that we can never use one local register when
2648 there is a frame pointer. loc79 gets wasted in this case, as it is
2649 renamed to a register that will never be used. See also the try_locals
2650 code in find_gr_spill. */
2651 if (current_frame_info.reg_fp)
2653 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2654 reg_names[HARD_FRAME_POINTER_REGNUM]
2655 = reg_names[current_frame_info.reg_fp];
2656 reg_names[current_frame_info.reg_fp] = tmp;
2659 /* We don't need an alloc instruction if we've used no outputs or locals. */
2660 if (current_frame_info.n_local_regs == 0
2661 && current_frame_info.n_output_regs == 0
2662 && current_frame_info.n_input_regs <= current_function_args_info.int_regs
2663 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
2665 /* If there is no alloc, but there are input registers used, then we
2666 need a .regstk directive. */
2667 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
2668 ar_pfs_save_reg = NULL_RTX;
2672 current_frame_info.need_regstk = 0;
2674 if (current_frame_info.reg_save_ar_pfs)
2675 regno = current_frame_info.reg_save_ar_pfs;
2677 regno = next_scratch_gr_reg ();
2678 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
2680 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
2681 GEN_INT (current_frame_info.n_input_regs),
2682 GEN_INT (current_frame_info.n_local_regs),
2683 GEN_INT (current_frame_info.n_output_regs),
2684 GEN_INT (current_frame_info.n_rotate_regs)));
2685 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
2688 /* Set up frame pointer, stack pointer, and spill iterators. */
2690 n_varargs = cfun->machine->n_varargs;
2691 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
2692 stack_pointer_rtx, 0);
2694 if (frame_pointer_needed)
2696 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2697 RTX_FRAME_RELATED_P (insn) = 1;
2700 if (current_frame_info.total_size != 0)
2702 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
2705 if (CONST_OK_FOR_I (- current_frame_info.total_size))
2706 offset = frame_size_rtx;
2709 regno = next_scratch_gr_reg ();
2710 offset = gen_rtx_REG (DImode, regno);
2711 emit_move_insn (offset, frame_size_rtx);
2714 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
2715 stack_pointer_rtx, offset));
2717 if (! frame_pointer_needed)
2719 RTX_FRAME_RELATED_P (insn) = 1;
2720 if (GET_CODE (offset) != CONST_INT)
2723 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2724 gen_rtx_SET (VOIDmode,
2726 gen_rtx_PLUS (DImode,
2733 /* ??? At this point we must generate a magic insn that appears to
2734 modify the stack pointer, the frame pointer, and all spill
2735 iterators. This would allow the most scheduling freedom. For
2736 now, just hard stop. */
2737 emit_insn (gen_blockage ());
2740 /* Must copy out ar.unat before doing any integer spills. */
2741 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2743 if (current_frame_info.reg_save_ar_unat)
2745 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2748 alt_regno = next_scratch_gr_reg ();
2749 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2750 current_frame_info.gr_used_mask |= 1 << alt_regno;
2753 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2754 insn = emit_move_insn (ar_unat_save_reg, reg);
2755 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
2757 /* Even if we're not going to generate an epilogue, we still
2758 need to save the register so that EH works. */
2759 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
2760 emit_insn (gen_prologue_use (ar_unat_save_reg));
2763 ar_unat_save_reg = NULL_RTX;
2765 /* Spill all varargs registers. Do this before spilling any GR registers,
2766 since we want the UNAT bits for the GR registers to override the UNAT
2767 bits from varargs, which we don't care about. */
2770 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
2772 reg = gen_rtx_REG (DImode, regno);
2773 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
2776 /* Locate the bottom of the register save area. */
2777 cfa_off = (current_frame_info.spill_cfa_off
2778 + current_frame_info.spill_size
2779 + current_frame_info.extra_spill_size);
2781 /* Save the predicate register block either in a register or in memory. */
2782 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2784 reg = gen_rtx_REG (DImode, PR_REG (0));
2785 if (current_frame_info.reg_save_pr != 0)
2787 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2788 insn = emit_move_insn (alt_reg, reg);
2790 /* ??? Denote pr spill/fill by a DImode move that modifies all
2791 64 hard registers. */
2792 RTX_FRAME_RELATED_P (insn) = 1;
2794 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2795 gen_rtx_SET (VOIDmode, alt_reg, reg),
2798 /* Even if we're not going to generate an epilogue, we still
2799 need to save the register so that EH works. */
2801 emit_insn (gen_prologue_use (alt_reg));
2805 alt_regno = next_scratch_gr_reg ();
2806 alt_reg = gen_rtx_REG (DImode, alt_regno);
2807 insn = emit_move_insn (alt_reg, reg);
2808 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2813 /* Handle AR regs in numerical order. All of them get special handling. */
2814 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
2815 && current_frame_info.reg_save_ar_unat == 0)
2817 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2818 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
2822 /* The alloc insn already copied ar.pfs into a general register. The
2823 only thing we have to do now is copy that register to a stack slot
2824 if we'd not allocated a local register for the job. */
2825 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
2826 && current_frame_info.reg_save_ar_pfs == 0)
2828 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2829 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
2833 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2835 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2836 if (current_frame_info.reg_save_ar_lc != 0)
2838 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2839 insn = emit_move_insn (alt_reg, reg);
2840 RTX_FRAME_RELATED_P (insn) = 1;
2842 /* Even if we're not going to generate an epilogue, we still
2843 need to save the register so that EH works. */
2845 emit_insn (gen_prologue_use (alt_reg));
2849 alt_regno = next_scratch_gr_reg ();
2850 alt_reg = gen_rtx_REG (DImode, alt_regno);
2851 emit_move_insn (alt_reg, reg);
2852 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2857 if (current_frame_info.reg_save_gp)
2859 insn = emit_move_insn (gen_rtx_REG (DImode,
2860 current_frame_info.reg_save_gp),
2861 pic_offset_table_rtx);
2862 /* We don't know for sure yet if this is actually needed, since
2863 we've not split the PIC call patterns. If all of the calls
2864 are indirect, and not followed by any uses of the gp, then
2865 this save is dead. Allow it to go away. */
2867 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
2870 /* We should now be at the base of the gr/br/fr spill area. */
2871 if (cfa_off != (current_frame_info.spill_cfa_off
2872 + current_frame_info.spill_size))
2875 /* Spill all general registers. */
2876 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2877 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2879 reg = gen_rtx_REG (DImode, regno);
2880 do_spill (gen_gr_spill, reg, cfa_off, reg);
2884 /* Handle BR0 specially -- it may be getting stored permanently in
2885 some GR register. */
2886 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2888 reg = gen_rtx_REG (DImode, BR_REG (0));
2889 if (current_frame_info.reg_save_b0 != 0)
2891 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2892 insn = emit_move_insn (alt_reg, reg);
2893 RTX_FRAME_RELATED_P (insn) = 1;
2895 /* Even if we're not going to generate an epilogue, we still
2896 need to save the register so that EH works. */
2898 emit_insn (gen_prologue_use (alt_reg));
2902 alt_regno = next_scratch_gr_reg ();
2903 alt_reg = gen_rtx_REG (DImode, alt_regno);
2904 emit_move_insn (alt_reg, reg);
2905 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2910 /* Spill the rest of the BR registers. */
2911 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2912 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2914 alt_regno = next_scratch_gr_reg ();
2915 alt_reg = gen_rtx_REG (DImode, alt_regno);
2916 reg = gen_rtx_REG (DImode, regno);
2917 emit_move_insn (alt_reg, reg);
2918 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2922 /* Align the frame and spill all FR registers. */
2923 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2924 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2928 reg = gen_rtx_REG (XFmode, regno);
2929 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
2933 if (cfa_off != current_frame_info.spill_cfa_off)
2936 finish_spill_pointers ();
2939 /* Called after register allocation to add any instructions needed for the
2940 epilogue. Using an epilogue insn is favored compared to putting all of the
2941 instructions in output_function_prologue(), since it allows the scheduler
2942 to intermix instructions with the saves of the caller saved registers. In
2943 some cases, it might be necessary to emit a barrier instruction as the last
2944 insn to prevent such scheduling. */
2947 ia64_expand_epilogue (int sibcall_p)
2949 rtx insn, reg, alt_reg, ar_unat_save_reg;
2950 int regno, alt_regno, cfa_off;
2952 ia64_compute_frame_size (get_frame_size ());
2954 /* If there is a frame pointer, then we use it instead of the stack
2955 pointer, so that the stack pointer does not need to be valid when
2956 the epilogue starts. See EXIT_IGNORE_STACK. */
2957 if (frame_pointer_needed)
2958 setup_spill_pointers (current_frame_info.n_spilled,
2959 hard_frame_pointer_rtx, 0);
2961 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
2962 current_frame_info.total_size);
2964 if (current_frame_info.total_size != 0)
2966 /* ??? At this point we must generate a magic insn that appears to
2967 modify the spill iterators and the frame pointer. This would
2968 allow the most scheduling freedom. For now, just hard stop. */
2969 emit_insn (gen_blockage ());
2972 /* Locate the bottom of the register save area. */
2973 cfa_off = (current_frame_info.spill_cfa_off
2974 + current_frame_info.spill_size
2975 + current_frame_info.extra_spill_size);
2977 /* Restore the predicate registers. */
2978 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2980 if (current_frame_info.reg_save_pr != 0)
2981 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2984 alt_regno = next_scratch_gr_reg ();
2985 alt_reg = gen_rtx_REG (DImode, alt_regno);
2986 do_restore (gen_movdi_x, alt_reg, cfa_off);
2989 reg = gen_rtx_REG (DImode, PR_REG (0));
2990 emit_move_insn (reg, alt_reg);
2993 /* Restore the application registers. */
2995 /* Load the saved unat from the stack, but do not restore it until
2996 after the GRs have been restored. */
2997 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2999 if (current_frame_info.reg_save_ar_unat != 0)
3001 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
3004 alt_regno = next_scratch_gr_reg ();
3005 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3006 current_frame_info.gr_used_mask |= 1 << alt_regno;
3007 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3012 ar_unat_save_reg = NULL_RTX;
3014 if (current_frame_info.reg_save_ar_pfs != 0)
3016 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
3017 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3018 emit_move_insn (reg, alt_reg);
3020 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3022 alt_regno = next_scratch_gr_reg ();
3023 alt_reg = gen_rtx_REG (DImode, alt_regno);
3024 do_restore (gen_movdi_x, alt_reg, cfa_off);
3026 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3027 emit_move_insn (reg, alt_reg);
3030 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3032 if (current_frame_info.reg_save_ar_lc != 0)
3033 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
3036 alt_regno = next_scratch_gr_reg ();
3037 alt_reg = gen_rtx_REG (DImode, alt_regno);
3038 do_restore (gen_movdi_x, alt_reg, cfa_off);
3041 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3042 emit_move_insn (reg, alt_reg);
3045 /* We should now be at the base of the gr/br/fr spill area. */
3046 if (cfa_off != (current_frame_info.spill_cfa_off
3047 + current_frame_info.spill_size))
3050 /* The GP may be stored on the stack in the prologue, but it's
3051 never restored in the epilogue. Skip the stack slot. */
3052 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3055 /* Restore all general registers. */
3056 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3057 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3059 reg = gen_rtx_REG (DImode, regno);
3060 do_restore (gen_gr_restore, reg, cfa_off);
3064 /* Restore the branch registers. Handle B0 specially, as it may
3065 have gotten stored in some GR register. */
3066 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3068 if (current_frame_info.reg_save_b0 != 0)
3069 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3072 alt_regno = next_scratch_gr_reg ();
3073 alt_reg = gen_rtx_REG (DImode, alt_regno);
3074 do_restore (gen_movdi_x, alt_reg, cfa_off);
3077 reg = gen_rtx_REG (DImode, BR_REG (0));
3078 emit_move_insn (reg, alt_reg);
3081 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3082 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3084 alt_regno = next_scratch_gr_reg ();
3085 alt_reg = gen_rtx_REG (DImode, alt_regno);
3086 do_restore (gen_movdi_x, alt_reg, cfa_off);
3088 reg = gen_rtx_REG (DImode, regno);
3089 emit_move_insn (reg, alt_reg);
3092 /* Restore floating point registers. */
3093 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3094 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3098 reg = gen_rtx_REG (XFmode, regno);
3099 do_restore (gen_fr_restore_x, reg, cfa_off);
3103 /* Restore ar.unat for real. */
3104 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3106 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3107 emit_move_insn (reg, ar_unat_save_reg);
3110 if (cfa_off != current_frame_info.spill_cfa_off)
3113 finish_spill_pointers ();
3115 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
3117 /* ??? At this point we must generate a magic insn that appears to
3118 modify the spill iterators, the stack pointer, and the frame
3119 pointer. This would allow the most scheduling freedom. For now,
3121 emit_insn (gen_blockage ());
3124 if (cfun->machine->ia64_eh_epilogue_sp)
3125 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3126 else if (frame_pointer_needed)
3128 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3129 RTX_FRAME_RELATED_P (insn) = 1;
3131 else if (current_frame_info.total_size)
3133 rtx offset, frame_size_rtx;
3135 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3136 if (CONST_OK_FOR_I (current_frame_info.total_size))
3137 offset = frame_size_rtx;
3140 regno = next_scratch_gr_reg ();
3141 offset = gen_rtx_REG (DImode, regno);
3142 emit_move_insn (offset, frame_size_rtx);
3145 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3148 RTX_FRAME_RELATED_P (insn) = 1;
3149 if (GET_CODE (offset) != CONST_INT)
3152 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3153 gen_rtx_SET (VOIDmode,
3155 gen_rtx_PLUS (DImode,
3162 if (cfun->machine->ia64_eh_epilogue_bsp)
3163 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3166 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3169 int fp = GR_REG (2);
3170 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3171 first available call clobbered register. If there was a frame_pointer
3172 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3173 so we have to make sure we're using the string "r2" when emitting
3174 the register name for the assembler. */
3175 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
3176 fp = HARD_FRAME_POINTER_REGNUM;
3178 /* We must emit an alloc to force the input registers to become output
3179 registers. Otherwise, if the callee tries to pass its parameters
3180 through to another call without an intervening alloc, then these
3182 /* ??? We don't need to preserve all input registers. We only need to
3183 preserve those input registers used as arguments to the sibling call.
3184 It is unclear how to compute that number here. */
3185 if (current_frame_info.n_input_regs != 0)
3186 emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3187 const0_rtx, const0_rtx,
3188 GEN_INT (current_frame_info.n_input_regs),
3193 /* Return 1 if br.ret can do all the work required to return from a
3197 ia64_direct_return (void)
3199 if (reload_completed && ! frame_pointer_needed)
3201 ia64_compute_frame_size (get_frame_size ());
3203 return (current_frame_info.total_size == 0
3204 && current_frame_info.n_spilled == 0
3205 && current_frame_info.reg_save_b0 == 0
3206 && current_frame_info.reg_save_pr == 0
3207 && current_frame_info.reg_save_ar_pfs == 0
3208 && current_frame_info.reg_save_ar_unat == 0
3209 && current_frame_info.reg_save_ar_lc == 0);
3214 /* Return the magic cookie that we use to hold the return address
3215 during early compilation. */
3218 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3222 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3225 /* Split this value after reload, now that we know where the return
3226 address is saved. */
3229 ia64_split_return_addr_rtx (rtx dest)
3233 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3235 if (current_frame_info.reg_save_b0 != 0)
3236 src = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3242 /* Compute offset from CFA for BR0. */
3243 /* ??? Must be kept in sync with ia64_expand_prologue. */
3244 off = (current_frame_info.spill_cfa_off
3245 + current_frame_info.spill_size);
3246 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3247 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3250 /* Convert CFA offset to a register based offset. */
3251 if (frame_pointer_needed)
3252 src = hard_frame_pointer_rtx;
3255 src = stack_pointer_rtx;
3256 off += current_frame_info.total_size;
3259 /* Load address into scratch register. */
3260 if (CONST_OK_FOR_I (off))
3261 emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
3264 emit_move_insn (dest, GEN_INT (off));
3265 emit_insn (gen_adddi3 (dest, src, dest));
3268 src = gen_rtx_MEM (Pmode, dest);
3272 src = gen_rtx_REG (DImode, BR_REG (0));
3274 emit_move_insn (dest, src);
3278 ia64_hard_regno_rename_ok (int from, int to)
3280 /* Don't clobber any of the registers we reserved for the prologue. */
3281 if (to == current_frame_info.reg_fp
3282 || to == current_frame_info.reg_save_b0
3283 || to == current_frame_info.reg_save_pr
3284 || to == current_frame_info.reg_save_ar_pfs
3285 || to == current_frame_info.reg_save_ar_unat
3286 || to == current_frame_info.reg_save_ar_lc)
3289 if (from == current_frame_info.reg_fp
3290 || from == current_frame_info.reg_save_b0
3291 || from == current_frame_info.reg_save_pr
3292 || from == current_frame_info.reg_save_ar_pfs
3293 || from == current_frame_info.reg_save_ar_unat
3294 || from == current_frame_info.reg_save_ar_lc)
3297 /* Don't use output registers outside the register frame. */
3298 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3301 /* Retain even/oddness on predicate register pairs. */
3302 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3303 return (from & 1) == (to & 1);
3308 /* Target hook for assembling integer objects. Handle word-sized
3309 aligned objects and detect the cases when @fptr is needed. */
3312 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3314 if (size == POINTER_SIZE / BITS_PER_UNIT
3316 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3317 && GET_CODE (x) == SYMBOL_REF
3318 && SYMBOL_REF_FUNCTION_P (x))
3320 if (POINTER_SIZE == 32)
3321 fputs ("\tdata4\t@fptr(", asm_out_file);
3323 fputs ("\tdata8\t@fptr(", asm_out_file);
3324 output_addr_const (asm_out_file, x);
3325 fputs (")\n", asm_out_file);
3328 return default_assemble_integer (x, size, aligned_p);
3331 /* Emit the function prologue. */
3334 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3336 int mask, grsave, grsave_prev;
3338 if (current_frame_info.need_regstk)
3339 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3340 current_frame_info.n_input_regs,
3341 current_frame_info.n_local_regs,
3342 current_frame_info.n_output_regs,
3343 current_frame_info.n_rotate_regs);
3345 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3348 /* Emit the .prologue directive. */
3351 grsave = grsave_prev = 0;
3352 if (current_frame_info.reg_save_b0 != 0)
3355 grsave = grsave_prev = current_frame_info.reg_save_b0;
3357 if (current_frame_info.reg_save_ar_pfs != 0
3358 && (grsave_prev == 0
3359 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3362 if (grsave_prev == 0)
3363 grsave = current_frame_info.reg_save_ar_pfs;
3364 grsave_prev = current_frame_info.reg_save_ar_pfs;
3366 if (current_frame_info.reg_fp != 0
3367 && (grsave_prev == 0
3368 || current_frame_info.reg_fp == grsave_prev + 1))
3371 if (grsave_prev == 0)
3372 grsave = HARD_FRAME_POINTER_REGNUM;
3373 grsave_prev = current_frame_info.reg_fp;
3375 if (current_frame_info.reg_save_pr != 0
3376 && (grsave_prev == 0
3377 || current_frame_info.reg_save_pr == grsave_prev + 1))
3380 if (grsave_prev == 0)
3381 grsave = current_frame_info.reg_save_pr;
3384 if (mask && TARGET_GNU_AS)
3385 fprintf (file, "\t.prologue %d, %d\n", mask,
3386 ia64_dbx_register_number (grsave));
3388 fputs ("\t.prologue\n", file);
3390 /* Emit a .spill directive, if necessary, to relocate the base of
3391 the register spill area. */
3392 if (current_frame_info.spill_cfa_off != -16)
3393 fprintf (file, "\t.spill %ld\n",
3394 (long) (current_frame_info.spill_cfa_off
3395 + current_frame_info.spill_size));
3398 /* Emit the .body directive at the scheduled end of the prologue. */
3401 ia64_output_function_end_prologue (FILE *file)
3403 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3406 fputs ("\t.body\n", file);
3409 /* Emit the function epilogue. */
3412 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3413 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3417 if (current_frame_info.reg_fp)
3419 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3420 reg_names[HARD_FRAME_POINTER_REGNUM]
3421 = reg_names[current_frame_info.reg_fp];
3422 reg_names[current_frame_info.reg_fp] = tmp;
3424 if (! TARGET_REG_NAMES)
3426 for (i = 0; i < current_frame_info.n_input_regs; i++)
3427 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3428 for (i = 0; i < current_frame_info.n_local_regs; i++)
3429 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3430 for (i = 0; i < current_frame_info.n_output_regs; i++)
3431 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3434 current_frame_info.initialized = 0;
3438 ia64_dbx_register_number (int regno)
3440 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3441 from its home at loc79 to something inside the register frame. We
3442 must perform the same renumbering here for the debug info. */
3443 if (current_frame_info.reg_fp)
3445 if (regno == HARD_FRAME_POINTER_REGNUM)
3446 regno = current_frame_info.reg_fp;
3447 else if (regno == current_frame_info.reg_fp)
3448 regno = HARD_FRAME_POINTER_REGNUM;
3451 if (IN_REGNO_P (regno))
3452 return 32 + regno - IN_REG (0);
3453 else if (LOC_REGNO_P (regno))
3454 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3455 else if (OUT_REGNO_P (regno))
3456 return (32 + current_frame_info.n_input_regs
3457 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3463 ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
3465 rtx addr_reg, eight = GEN_INT (8);
3467 /* The Intel assembler requires that the global __ia64_trampoline symbol
3468 be declared explicitly */
3471 static bool declared_ia64_trampoline = false;
3473 if (!declared_ia64_trampoline)
3475 declared_ia64_trampoline = true;
3476 (*targetm.asm_out.globalize_label) (asm_out_file,
3477 "__ia64_trampoline");
3481 /* Load up our iterator. */
3482 addr_reg = gen_reg_rtx (Pmode);
3483 emit_move_insn (addr_reg, addr);
3485 /* The first two words are the fake descriptor:
3486 __ia64_trampoline, ADDR+16. */
3487 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3488 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3489 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3491 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3492 copy_to_reg (plus_constant (addr, 16)));
3493 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3495 /* The third word is the target descriptor. */
3496 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3497 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3499 /* The fourth word is the static chain. */
3500 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3503 /* Do any needed setup for a variadic function. CUM has not been updated
3504 for the last named argument which has type TYPE and mode MODE.
3506 We generate the actual spill instructions during prologue generation. */
3509 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3510 tree type, int * pretend_size,
3511 int second_time ATTRIBUTE_UNUSED)
3513 CUMULATIVE_ARGS next_cum = *cum;
3515 /* Skip the current argument. */
3516 ia64_function_arg_advance (&next_cum, mode, type, 1);
3518 if (next_cum.words < MAX_ARGUMENT_SLOTS)
3520 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
3521 *pretend_size = n * UNITS_PER_WORD;
3522 cfun->machine->n_varargs = n;
3526 /* Check whether TYPE is a homogeneous floating point aggregate. If
3527 it is, return the mode of the floating point type that appears
3528 in all leafs. If it is not, return VOIDmode.
3530 An aggregate is a homogeneous floating point aggregate is if all
3531 fields/elements in it have the same floating point type (e.g,
3532 SFmode). 128-bit quad-precision floats are excluded. */
3534 static enum machine_mode
3535 hfa_element_mode (tree type, int nested)
3537 enum machine_mode element_mode = VOIDmode;
3538 enum machine_mode mode;
3539 enum tree_code code = TREE_CODE (type);
3540 int know_element_mode = 0;
3545 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3546 case BOOLEAN_TYPE: case CHAR_TYPE: case POINTER_TYPE:
3547 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3548 case FILE_TYPE: case SET_TYPE: case LANG_TYPE:
3552 /* Fortran complex types are supposed to be HFAs, so we need to handle
3553 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3556 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3557 && TYPE_MODE (type) != TCmode)
3558 return GET_MODE_INNER (TYPE_MODE (type));
3563 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3564 mode if this is contained within an aggregate. */
3565 if (nested && TYPE_MODE (type) != TFmode)
3566 return TYPE_MODE (type);
3571 return hfa_element_mode (TREE_TYPE (type), 1);
3575 case QUAL_UNION_TYPE:
3576 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3578 if (TREE_CODE (t) != FIELD_DECL)
3581 mode = hfa_element_mode (TREE_TYPE (t), 1);
3582 if (know_element_mode)
3584 if (mode != element_mode)
3587 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3591 know_element_mode = 1;
3592 element_mode = mode;
3595 return element_mode;
3598 /* If we reach here, we probably have some front-end specific type
3599 that the backend doesn't know about. This can happen via the
3600 aggregate_value_p call in init_function_start. All we can do is
3601 ignore unknown tree types. */
3608 /* Return the number of words required to hold a quantity of TYPE and MODE
3609 when passed as an argument. */
3611 ia64_function_arg_words (tree type, enum machine_mode mode)
3615 if (mode == BLKmode)
3616 words = int_size_in_bytes (type);
3618 words = GET_MODE_SIZE (mode);
3620 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
3623 /* Return the number of registers that should be skipped so the current
3624 argument (described by TYPE and WORDS) will be properly aligned.
3626 Integer and float arguments larger than 8 bytes start at the next
3627 even boundary. Aggregates larger than 8 bytes start at the next
3628 even boundary if the aggregate has 16 byte alignment. Note that
3629 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3630 but are still to be aligned in registers.
3632 ??? The ABI does not specify how to handle aggregates with
3633 alignment from 9 to 15 bytes, or greater than 16. We handle them
3634 all as if they had 16 byte alignment. Such aggregates can occur
3635 only if gcc extensions are used. */
3637 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
3639 if ((cum->words & 1) == 0)
3643 && TREE_CODE (type) != INTEGER_TYPE
3644 && TREE_CODE (type) != REAL_TYPE)
3645 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
3650 /* Return rtx for register where argument is passed, or zero if it is passed
3652 /* ??? 128-bit quad-precision floats are always passed in general
3656 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
3657 int named, int incoming)
3659 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
3660 int words = ia64_function_arg_words (type, mode);
3661 int offset = ia64_function_arg_offset (cum, type, words);
3662 enum machine_mode hfa_mode = VOIDmode;
3664 /* If all argument slots are used, then it must go on the stack. */
3665 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3668 /* Check for and handle homogeneous FP aggregates. */
3670 hfa_mode = hfa_element_mode (type, 0);
3672 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3673 and unprototyped hfas are passed specially. */
3674 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3678 int fp_regs = cum->fp_regs;
3679 int int_regs = cum->words + offset;
3680 int hfa_size = GET_MODE_SIZE (hfa_mode);
3684 /* If prototyped, pass it in FR regs then GR regs.
3685 If not prototyped, pass it in both FR and GR regs.
3687 If this is an SFmode aggregate, then it is possible to run out of
3688 FR regs while GR regs are still left. In that case, we pass the
3689 remaining part in the GR regs. */
3691 /* Fill the FP regs. We do this always. We stop if we reach the end
3692 of the argument, the last FP register, or the last argument slot. */
3694 byte_size = ((mode == BLKmode)
3695 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3696 args_byte_size = int_regs * UNITS_PER_WORD;
3698 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3699 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
3701 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3702 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
3706 args_byte_size += hfa_size;
3710 /* If no prototype, then the whole thing must go in GR regs. */
3711 if (! cum->prototype)
3713 /* If this is an SFmode aggregate, then we might have some left over
3714 that needs to go in GR regs. */
3715 else if (byte_size != offset)
3716 int_regs += offset / UNITS_PER_WORD;
3718 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3720 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
3722 enum machine_mode gr_mode = DImode;
3723 unsigned int gr_size;
3725 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3726 then this goes in a GR reg left adjusted/little endian, right
3727 adjusted/big endian. */
3728 /* ??? Currently this is handled wrong, because 4-byte hunks are
3729 always right adjusted/little endian. */
3732 /* If we have an even 4 byte hunk because the aggregate is a
3733 multiple of 4 bytes in size, then this goes in a GR reg right
3734 adjusted/little endian. */
3735 else if (byte_size - offset == 4)
3738 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3739 gen_rtx_REG (gr_mode, (basereg
3743 gr_size = GET_MODE_SIZE (gr_mode);
3745 if (gr_size == UNITS_PER_WORD
3746 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
3748 else if (gr_size > UNITS_PER_WORD)
3749 int_regs += gr_size / UNITS_PER_WORD;
3752 /* If we ended up using just one location, just return that one loc, but
3753 change the mode back to the argument mode. */
3755 return gen_rtx_REG (mode, REGNO (XEXP (loc[0], 0)));
3757 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3760 /* Integral and aggregates go in general registers. If we have run out of
3761 FR registers, then FP values must also go in general registers. This can
3762 happen when we have a SFmode HFA. */
3763 else if (mode == TFmode || mode == TCmode
3764 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
3766 int byte_size = ((mode == BLKmode)
3767 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3768 if (BYTES_BIG_ENDIAN
3769 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
3770 && byte_size < UNITS_PER_WORD
3773 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3774 gen_rtx_REG (DImode,
3775 (basereg + cum->words
3778 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
3781 return gen_rtx_REG (mode, basereg + cum->words + offset);
3785 /* If there is a prototype, then FP values go in a FR register when
3786 named, and in a GR register when unnamed. */
3787 else if (cum->prototype)
3790 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
3791 /* In big-endian mode, an anonymous SFmode value must be represented
3792 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
3793 the value into the high half of the general register. */
3794 else if (BYTES_BIG_ENDIAN && mode == SFmode)
3795 return gen_rtx_PARALLEL (mode,
3797 gen_rtx_EXPR_LIST (VOIDmode,
3798 gen_rtx_REG (DImode, basereg + cum->words + offset),
3801 return gen_rtx_REG (mode, basereg + cum->words + offset);
3803 /* If there is no prototype, then FP values go in both FR and GR
3807 /* See comment above. */
3808 enum machine_mode inner_mode =
3809 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
3811 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
3812 gen_rtx_REG (mode, (FR_ARG_FIRST
3815 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3816 gen_rtx_REG (inner_mode,
3817 (basereg + cum->words
3821 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
3825 /* Return number of words, at the beginning of the argument, that must be
3826 put in registers. 0 is the argument is entirely in registers or entirely
3830 ia64_function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3831 tree type, int named ATTRIBUTE_UNUSED)
3833 int words = ia64_function_arg_words (type, mode);
3834 int offset = ia64_function_arg_offset (cum, type, words);
3836 /* If all argument slots are used, then it must go on the stack. */
3837 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3840 /* It doesn't matter whether the argument goes in FR or GR regs. If
3841 it fits within the 8 argument slots, then it goes entirely in
3842 registers. If it extends past the last argument slot, then the rest
3843 goes on the stack. */
3845 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
3848 return MAX_ARGUMENT_SLOTS - cum->words - offset;
3851 /* Update CUM to point after this argument. This is patterned after
3852 ia64_function_arg. */
3855 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3856 tree type, int named)
3858 int words = ia64_function_arg_words (type, mode);
3859 int offset = ia64_function_arg_offset (cum, type, words);
3860 enum machine_mode hfa_mode = VOIDmode;
3862 /* If all arg slots are already full, then there is nothing to do. */
3863 if (cum->words >= MAX_ARGUMENT_SLOTS)
3866 cum->words += words + offset;
3868 /* Check for and handle homogeneous FP aggregates. */
3870 hfa_mode = hfa_element_mode (type, 0);
3872 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3873 and unprototyped hfas are passed specially. */
3874 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3876 int fp_regs = cum->fp_regs;
3877 /* This is the original value of cum->words + offset. */
3878 int int_regs = cum->words - words;
3879 int hfa_size = GET_MODE_SIZE (hfa_mode);
3883 /* If prototyped, pass it in FR regs then GR regs.
3884 If not prototyped, pass it in both FR and GR regs.
3886 If this is an SFmode aggregate, then it is possible to run out of
3887 FR regs while GR regs are still left. In that case, we pass the
3888 remaining part in the GR regs. */
3890 /* Fill the FP regs. We do this always. We stop if we reach the end
3891 of the argument, the last FP register, or the last argument slot. */
3893 byte_size = ((mode == BLKmode)
3894 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3895 args_byte_size = int_regs * UNITS_PER_WORD;
3897 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3898 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
3901 args_byte_size += hfa_size;
3905 cum->fp_regs = fp_regs;
3908 /* Integral and aggregates go in general registers. If we have run out of
3909 FR registers, then FP values must also go in general registers. This can
3910 happen when we have a SFmode HFA. */
3911 else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
3912 cum->int_regs = cum->words;
3914 /* If there is a prototype, then FP values go in a FR register when
3915 named, and in a GR register when unnamed. */
3916 else if (cum->prototype)
3919 cum->int_regs = cum->words;
3921 /* ??? Complex types should not reach here. */
3922 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3924 /* If there is no prototype, then FP values go in both FR and GR
3928 /* ??? Complex types should not reach here. */
3929 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3930 cum->int_regs = cum->words;
3934 /* Variable sized types are passed by reference. */
3935 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3938 ia64_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3939 enum machine_mode mode ATTRIBUTE_UNUSED,
3940 tree type, int named ATTRIBUTE_UNUSED)
3942 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3945 /* True if it is OK to do sibling call optimization for the specified
3946 call expression EXP. DECL will be the called function, or NULL if
3947 this is an indirect call. */
3949 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3951 /* We must always return with our current GP. This means we can
3952 only sibcall to functions defined in the current module. */
3953 return decl && (*targetm.binds_local_p) (decl);
3957 /* Implement va_arg. */
3960 ia64_va_arg (tree valist, tree type)
3964 /* Variable sized types are passed by reference. */
3965 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
3967 rtx addr = force_reg (ptr_mode,
3968 std_expand_builtin_va_arg (valist, build_pointer_type (type)));
3969 #ifdef POINTERS_EXTEND_UNSIGNED
3970 addr = convert_memory_address (Pmode, addr);
3972 return gen_rtx_MEM (ptr_mode, addr);
3975 /* Aggregate arguments with alignment larger than 8 bytes start at
3976 the next even boundary. Integer and floating point arguments
3977 do so if they are larger than 8 bytes, whether or not they are
3978 also aligned larger than 8 bytes. */
3979 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
3980 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3982 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
3983 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
3984 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
3985 build_int_2 (-2 * UNITS_PER_WORD, -1));
3986 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
3987 TREE_SIDE_EFFECTS (t) = 1;
3988 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3991 return std_expand_builtin_va_arg (valist, type);
3994 /* Return 1 if function return value returned in memory. Return 0 if it is
3998 ia64_return_in_memory (tree valtype, tree fntype ATTRIBUTE_UNUSED)
4000 enum machine_mode mode;
4001 enum machine_mode hfa_mode;
4002 HOST_WIDE_INT byte_size;
4004 mode = TYPE_MODE (valtype);
4005 byte_size = GET_MODE_SIZE (mode);
4006 if (mode == BLKmode)
4008 byte_size = int_size_in_bytes (valtype);
4013 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4015 hfa_mode = hfa_element_mode (valtype, 0);
4016 if (hfa_mode != VOIDmode)
4018 int hfa_size = GET_MODE_SIZE (hfa_mode);
4020 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4025 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4031 /* Return rtx for register that holds the function return value. */
4034 ia64_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
4036 enum machine_mode mode;
4037 enum machine_mode hfa_mode;
4039 mode = TYPE_MODE (valtype);
4040 hfa_mode = hfa_element_mode (valtype, 0);
4042 if (hfa_mode != VOIDmode)
4050 hfa_size = GET_MODE_SIZE (hfa_mode);
4051 byte_size = ((mode == BLKmode)
4052 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4054 for (i = 0; offset < byte_size; i++)
4056 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4057 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4063 return XEXP (loc[0], 0);
4065 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4067 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4068 return gen_rtx_REG (mode, FR_ARG_FIRST);
4071 if (BYTES_BIG_ENDIAN
4072 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4080 bytesize = int_size_in_bytes (valtype);
4081 for (i = 0; offset < bytesize; i++)
4083 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4084 gen_rtx_REG (DImode,
4087 offset += UNITS_PER_WORD;
4089 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4092 return gen_rtx_REG (mode, GR_RET_FIRST);
4096 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
4097 We need to emit DTP-relative relocations. */
4100 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4104 fputs ("\tdata8.ua\t@dtprel(", file);
4105 output_addr_const (file, x);
4109 /* Print a memory address as an operand to reference that memory location. */
4111 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4112 also call this from ia64_print_operand for memory addresses. */
4115 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4116 rtx address ATTRIBUTE_UNUSED)
4120 /* Print an operand to an assembler instruction.
4121 C Swap and print a comparison operator.
4122 D Print an FP comparison operator.
4123 E Print 32 - constant, for SImode shifts as extract.
4124 e Print 64 - constant, for DImode rotates.
4125 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4126 a floating point register emitted normally.
4127 I Invert a predicate register by adding 1.
4128 J Select the proper predicate register for a condition.
4129 j Select the inverse predicate register for a condition.
4130 O Append .acq for volatile load.
4131 P Postincrement of a MEM.
4132 Q Append .rel for volatile store.
4133 S Shift amount for shladd instruction.
4134 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4135 for Intel assembler.
4136 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4137 for Intel assembler.
4138 r Print register name, or constant 0 as r0. HP compatibility for
4141 ia64_print_operand (FILE * file, rtx x, int code)
4148 /* Handled below. */
4153 enum rtx_code c = swap_condition (GET_CODE (x));
4154 fputs (GET_RTX_NAME (c), file);
4159 switch (GET_CODE (x))
4171 str = GET_RTX_NAME (GET_CODE (x));
4178 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4182 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4186 if (x == CONST0_RTX (GET_MODE (x)))
4187 str = reg_names [FR_REG (0)];
4188 else if (x == CONST1_RTX (GET_MODE (x)))
4189 str = reg_names [FR_REG (1)];
4190 else if (GET_CODE (x) == REG)
4191 str = reg_names [REGNO (x)];
4198 fputs (reg_names [REGNO (x) + 1], file);
4204 unsigned int regno = REGNO (XEXP (x, 0));
4205 if (GET_CODE (x) == EQ)
4209 fputs (reg_names [regno], file);
4214 if (MEM_VOLATILE_P (x))
4215 fputs(".acq", file);
4220 HOST_WIDE_INT value;
4222 switch (GET_CODE (XEXP (x, 0)))
4228 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
4229 if (GET_CODE (x) == CONST_INT)
4231 else if (GET_CODE (x) == REG)
4233 fprintf (file, ", %s", reg_names[REGNO (x)]);
4241 value = GET_MODE_SIZE (GET_MODE (x));
4245 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
4249 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
4254 if (MEM_VOLATILE_P (x))
4255 fputs(".rel", file);
4259 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4263 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4265 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
4271 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4273 const char *prefix = "0x";
4274 if (INTVAL (x) & 0x80000000)
4276 fprintf (file, "0xffffffff");
4279 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
4285 /* If this operand is the constant zero, write it as register zero.
4286 Any register, zero, or CONST_INT value is OK here. */
4287 if (GET_CODE (x) == REG)
4288 fputs (reg_names[REGNO (x)], file);
4289 else if (x == CONST0_RTX (GET_MODE (x)))
4291 else if (GET_CODE (x) == CONST_INT)
4292 output_addr_const (file, x);
4294 output_operand_lossage ("invalid %%r value");
4301 /* For conditional branches, returns or calls, substitute
4302 sptk, dptk, dpnt, or spnt for %s. */
4303 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4306 int pred_val = INTVAL (XEXP (x, 0));
4308 /* Guess top and bottom 10% statically predicted. */
4309 if (pred_val < REG_BR_PROB_BASE / 50)
4311 else if (pred_val < REG_BR_PROB_BASE / 2)
4313 else if (pred_val < REG_BR_PROB_BASE / 100 * 98)
4318 else if (GET_CODE (current_output_insn) == CALL_INSN)
4323 fputs (which, file);
4328 x = current_insn_predicate;
4331 unsigned int regno = REGNO (XEXP (x, 0));
4332 if (GET_CODE (x) == EQ)
4334 fprintf (file, "(%s) ", reg_names [regno]);
4339 output_operand_lossage ("ia64_print_operand: unknown code");
4343 switch (GET_CODE (x))
4345 /* This happens for the spill/restore instructions. */
4350 /* ... fall through ... */
4353 fputs (reg_names [REGNO (x)], file);
4358 rtx addr = XEXP (x, 0);
4359 if (GET_RTX_CLASS (GET_CODE (addr)) == 'a')
4360 addr = XEXP (addr, 0);
4361 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4366 output_addr_const (file, x);
4373 /* Compute a (partial) cost for rtx X. Return true if the complete
4374 cost has been computed, and false if subexpressions should be
4375 scanned. In either case, *TOTAL contains the cost result. */
4376 /* ??? This is incomplete. */
4379 ia64_rtx_costs (rtx x, int code, int outer_code, int *total)
4387 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4390 if (CONST_OK_FOR_I (INTVAL (x)))
4392 else if (CONST_OK_FOR_J (INTVAL (x)))
4395 *total = COSTS_N_INSNS (1);
4398 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4401 *total = COSTS_N_INSNS (1);
4406 *total = COSTS_N_INSNS (1);
4412 *total = COSTS_N_INSNS (3);
4416 /* For multiplies wider than HImode, we have to go to the FPU,
4417 which normally involves copies. Plus there's the latency
4418 of the multiply itself, and the latency of the instructions to
4419 transfer integer regs to FP regs. */
4420 /* ??? Check for FP mode. */
4421 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4422 *total = COSTS_N_INSNS (10);
4424 *total = COSTS_N_INSNS (2);
4432 *total = COSTS_N_INSNS (1);
4439 /* We make divide expensive, so that divide-by-constant will be
4440 optimized to a multiply. */
4441 *total = COSTS_N_INSNS (60);
4449 /* Calculate the cost of moving data from a register in class FROM to
4450 one in class TO, using MODE. */
4453 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
4456 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4457 if (to == ADDL_REGS)
4459 if (from == ADDL_REGS)
4462 /* All costs are symmetric, so reduce cases by putting the
4463 lower number class as the destination. */
4466 enum reg_class tmp = to;
4467 to = from, from = tmp;
4470 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4471 so that we get secondary memory reloads. Between FR_REGS,
4472 we have to make this at least as expensive as MEMORY_MOVE_COST
4473 to avoid spectacularly poor register class preferencing. */
4476 if (to != GR_REGS || from != GR_REGS)
4477 return MEMORY_MOVE_COST (mode, to, 0);
4485 /* Moving between PR registers takes two insns. */
4486 if (from == PR_REGS)
4488 /* Moving between PR and anything but GR is impossible. */
4489 if (from != GR_REGS)
4490 return MEMORY_MOVE_COST (mode, to, 0);
4494 /* Moving between BR and anything but GR is impossible. */
4495 if (from != GR_REGS && from != GR_AND_BR_REGS)
4496 return MEMORY_MOVE_COST (mode, to, 0);
4501 /* Moving between AR and anything but GR is impossible. */
4502 if (from != GR_REGS)
4503 return MEMORY_MOVE_COST (mode, to, 0);
4508 case GR_AND_FR_REGS:
4509 case GR_AND_BR_REGS:
4520 /* This function returns the register class required for a secondary
4521 register when copying between one of the registers in CLASS, and X,
4522 using MODE. A return value of NO_REGS means that no secondary register
4526 ia64_secondary_reload_class (enum reg_class class,
4527 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
4531 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4532 regno = true_regnum (x);
4539 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4540 interaction. We end up with two pseudos with overlapping lifetimes
4541 both of which are equiv to the same constant, and both which need
4542 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4543 changes depending on the path length, which means the qty_first_reg
4544 check in make_regs_eqv can give different answers at different times.
4545 At some point I'll probably need a reload_indi pattern to handle
4548 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4549 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4550 non-general registers for good measure. */
4551 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4554 /* This is needed if a pseudo used as a call_operand gets spilled to a
4556 if (GET_CODE (x) == MEM)
4561 /* Need to go through general registers to get to other class regs. */
4562 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4565 /* This can happen when a paradoxical subreg is an operand to the
4567 /* ??? This shouldn't be necessary after instruction scheduling is
4568 enabled, because paradoxical subregs are not accepted by
4569 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4570 stop the paradoxical subreg stupidity in the *_operand functions
4572 if (GET_CODE (x) == MEM
4573 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
4574 || GET_MODE (x) == QImode))
4577 /* This can happen because of the ior/and/etc patterns that accept FP
4578 registers as operands. If the third operand is a constant, then it
4579 needs to be reloaded into a FP register. */
4580 if (GET_CODE (x) == CONST_INT)
4583 /* This can happen because of register elimination in a muldi3 insn.
4584 E.g. `26107 * (unsigned long)&u'. */
4585 if (GET_CODE (x) == PLUS)
4590 /* ??? This happens if we cse/gcse a BImode value across a call,
4591 and the function has a nonlocal goto. This is because global
4592 does not allocate call crossing pseudos to hard registers when
4593 current_function_has_nonlocal_goto is true. This is relatively
4594 common for C++ programs that use exceptions. To reproduce,
4595 return NO_REGS and compile libstdc++. */
4596 if (GET_CODE (x) == MEM)
4599 /* This can happen when we take a BImode subreg of a DImode value,
4600 and that DImode value winds up in some non-GR register. */
4601 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
4613 /* Emit text to declare externally defined variables and functions, because
4614 the Intel assembler does not support undefined externals. */
4617 ia64_asm_output_external (FILE *file, tree decl, const char *name)
4619 int save_referenced;
4621 /* GNU as does not need anything here, but the HP linker does need
4622 something for external functions. */
4626 || TREE_CODE (decl) != FUNCTION_DECL
4627 || strstr (name, "__builtin_") == name))
4630 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4631 the linker when we do this, so we need to be careful not to do this for
4632 builtin functions which have no library equivalent. Unfortunately, we
4633 can't tell here whether or not a function will actually be called by
4634 expand_expr, so we pull in library functions even if we may not need
4636 if (! strcmp (name, "__builtin_next_arg")
4637 || ! strcmp (name, "alloca")
4638 || ! strcmp (name, "__builtin_constant_p")
4639 || ! strcmp (name, "__builtin_args_info"))
4643 ia64_hpux_add_extern_decl (decl);
4646 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4648 save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
4649 if (TREE_CODE (decl) == FUNCTION_DECL)
4650 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
4651 (*targetm.asm_out.globalize_label) (file, name);
4652 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
4656 /* Parse the -mfixed-range= option string. */
4659 fix_range (const char *const_str)
4662 char *str, *dash, *comma;
4664 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4665 REG2 are either register names or register numbers. The effect
4666 of this option is to mark the registers in the range from REG1 to
4667 REG2 as ``fixed'' so they won't be used by the compiler. This is
4668 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4670 i = strlen (const_str);
4671 str = (char *) alloca (i + 1);
4672 memcpy (str, const_str, i + 1);
4676 dash = strchr (str, '-');
4679 warning ("value of -mfixed-range must have form REG1-REG2");
4684 comma = strchr (dash + 1, ',');
4688 first = decode_reg_name (str);
4691 warning ("unknown register name: %s", str);
4695 last = decode_reg_name (dash + 1);
4698 warning ("unknown register name: %s", dash + 1);
4706 warning ("%s-%s is an empty range", str, dash + 1);
4710 for (i = first; i <= last; ++i)
4711 fixed_regs[i] = call_used_regs[i] = 1;
4721 static struct machine_function *
4722 ia64_init_machine_status (void)
4724 return ggc_alloc_cleared (sizeof (struct machine_function));
4727 /* Handle TARGET_OPTIONS switches. */
4730 ia64_override_options (void)
4734 const char *const name; /* processor name or nickname. */
4735 const enum processor_type processor;
4737 const processor_alias_table[] =
4739 {"itanium", PROCESSOR_ITANIUM},
4740 {"itanium1", PROCESSOR_ITANIUM},
4741 {"merced", PROCESSOR_ITANIUM},
4742 {"itanium2", PROCESSOR_ITANIUM2},
4743 {"mckinley", PROCESSOR_ITANIUM2},
4746 int const pta_size = ARRAY_SIZE (processor_alias_table);
4749 if (TARGET_AUTO_PIC)
4750 target_flags |= MASK_CONST_GP;
4752 if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
4754 if ((target_flags_explicit & MASK_INLINE_FLOAT_DIV_LAT)
4755 && (target_flags_explicit & MASK_INLINE_FLOAT_DIV_THR))
4757 warning ("cannot optimize floating point division for both latency and throughput");
4758 target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
4762 if (target_flags_explicit & MASK_INLINE_FLOAT_DIV_THR)
4763 target_flags &= ~MASK_INLINE_FLOAT_DIV_LAT;
4765 target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
4769 if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
4771 if ((target_flags_explicit & MASK_INLINE_INT_DIV_LAT)
4772 && (target_flags_explicit & MASK_INLINE_INT_DIV_THR))
4774 warning ("cannot optimize integer division for both latency and throughput");
4775 target_flags &= ~MASK_INLINE_INT_DIV_THR;
4779 if (target_flags_explicit & MASK_INLINE_INT_DIV_THR)
4780 target_flags &= ~MASK_INLINE_INT_DIV_LAT;
4782 target_flags &= ~MASK_INLINE_INT_DIV_THR;
4786 if (TARGET_INLINE_SQRT_LAT && TARGET_INLINE_SQRT_THR)
4788 if ((target_flags_explicit & MASK_INLINE_SQRT_LAT)
4789 && (target_flags_explicit & MASK_INLINE_SQRT_THR))
4791 warning ("cannot optimize square root for both latency and throughput");
4792 target_flags &= ~MASK_INLINE_SQRT_THR;
4796 if (target_flags_explicit & MASK_INLINE_SQRT_THR)
4797 target_flags &= ~MASK_INLINE_SQRT_LAT;
4799 target_flags &= ~MASK_INLINE_SQRT_THR;
4803 if (TARGET_INLINE_SQRT_LAT)
4805 warning ("not yet implemented: latency-optimized inline square root");
4806 target_flags &= ~MASK_INLINE_SQRT_LAT;
4809 if (ia64_fixed_range_string)
4810 fix_range (ia64_fixed_range_string);
4812 if (ia64_tls_size_string)
4815 unsigned long tmp = strtoul (ia64_tls_size_string, &end, 10);
4816 if (*end || (tmp != 14 && tmp != 22 && tmp != 64))
4817 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string);
4819 ia64_tls_size = tmp;
4822 if (!ia64_tune_string)
4823 ia64_tune_string = "itanium2";
4825 for (i = 0; i < pta_size; i++)
4826 if (! strcmp (ia64_tune_string, processor_alias_table[i].name))
4828 ia64_tune = processor_alias_table[i].processor;
4833 error ("bad value (%s) for -tune= switch", ia64_tune_string);
4835 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
4836 flag_schedule_insns_after_reload = 0;
4838 /* Variable tracking should be run after all optimizations which change order
4839 of insns. It also needs a valid CFG. */
4840 ia64_flag_var_tracking = flag_var_tracking;
4841 flag_var_tracking = 0;
4843 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
4845 init_machine_status = ia64_init_machine_status;
4848 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
4849 static enum attr_type ia64_safe_type (rtx);
4851 static enum attr_itanium_class
4852 ia64_safe_itanium_class (rtx insn)
4854 if (recog_memoized (insn) >= 0)
4855 return get_attr_itanium_class (insn);
4857 return ITANIUM_CLASS_UNKNOWN;
4860 static enum attr_type
4861 ia64_safe_type (rtx insn)
4863 if (recog_memoized (insn) >= 0)
4864 return get_attr_type (insn);
4866 return TYPE_UNKNOWN;
4869 /* The following collection of routines emit instruction group stop bits as
4870 necessary to avoid dependencies. */
4872 /* Need to track some additional registers as far as serialization is
4873 concerned so we can properly handle br.call and br.ret. We could
4874 make these registers visible to gcc, but since these registers are
4875 never explicitly used in gcc generated code, it seems wasteful to
4876 do so (plus it would make the call and return patterns needlessly
4878 #define REG_RP (BR_REG (0))
4879 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4880 /* This is used for volatile asms which may require a stop bit immediately
4881 before and after them. */
4882 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4883 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4884 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4886 /* For each register, we keep track of how it has been written in the
4887 current instruction group.
4889 If a register is written unconditionally (no qualifying predicate),
4890 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4892 If a register is written if its qualifying predicate P is true, we
4893 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4894 may be written again by the complement of P (P^1) and when this happens,
4895 WRITE_COUNT gets set to 2.
4897 The result of this is that whenever an insn attempts to write a register
4898 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4900 If a predicate register is written by a floating-point insn, we set
4901 WRITTEN_BY_FP to true.
4903 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4904 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4906 struct reg_write_state
4908 unsigned int write_count : 2;
4909 unsigned int first_pred : 16;
4910 unsigned int written_by_fp : 1;
4911 unsigned int written_by_and : 1;
4912 unsigned int written_by_or : 1;
4915 /* Cumulative info for the current instruction group. */
4916 struct reg_write_state rws_sum[NUM_REGS];
4917 /* Info for the current instruction. This gets copied to rws_sum after a
4918 stop bit is emitted. */
4919 struct reg_write_state rws_insn[NUM_REGS];
4921 /* Indicates whether this is the first instruction after a stop bit,
4922 in which case we don't need another stop bit. Without this, we hit
4923 the abort in ia64_variable_issue when scheduling an alloc. */
4924 static int first_instruction;
4926 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4927 RTL for one instruction. */
4930 unsigned int is_write : 1; /* Is register being written? */
4931 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
4932 unsigned int is_branch : 1; /* Is register used as part of a branch? */
4933 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
4934 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
4935 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
4938 static void rws_update (struct reg_write_state *, int, struct reg_flags, int);
4939 static int rws_access_regno (int, struct reg_flags, int);
4940 static int rws_access_reg (rtx, struct reg_flags, int);
4941 static void update_set_flags (rtx, struct reg_flags *, int *, rtx *);
4942 static int set_src_needs_barrier (rtx, struct reg_flags, int, rtx);
4943 static int rtx_needs_barrier (rtx, struct reg_flags, int);
4944 static void init_insn_group_barriers (void);
4945 static int group_barrier_needed_p (rtx);
4946 static int safe_group_barrier_needed_p (rtx);
4948 /* Update *RWS for REGNO, which is being written by the current instruction,
4949 with predicate PRED, and associated register flags in FLAGS. */
4952 rws_update (struct reg_write_state *rws, int regno, struct reg_flags flags, int pred)
4955 rws[regno].write_count++;
4957 rws[regno].write_count = 2;
4958 rws[regno].written_by_fp |= flags.is_fp;
4959 /* ??? Not tracking and/or across differing predicates. */
4960 rws[regno].written_by_and = flags.is_and;
4961 rws[regno].written_by_or = flags.is_or;
4962 rws[regno].first_pred = pred;
4965 /* Handle an access to register REGNO of type FLAGS using predicate register
4966 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4967 a dependency with an earlier instruction in the same group. */
4970 rws_access_regno (int regno, struct reg_flags flags, int pred)
4972 int need_barrier = 0;
4974 if (regno >= NUM_REGS)
4977 if (! PR_REGNO_P (regno))
4978 flags.is_and = flags.is_or = 0;
4984 /* One insn writes same reg multiple times? */
4985 if (rws_insn[regno].write_count > 0)
4988 /* Update info for current instruction. */
4989 rws_update (rws_insn, regno, flags, pred);
4990 write_count = rws_sum[regno].write_count;
4992 switch (write_count)
4995 /* The register has not been written yet. */
4996 rws_update (rws_sum, regno, flags, pred);
5000 /* The register has been written via a predicate. If this is
5001 not a complementary predicate, then we need a barrier. */
5002 /* ??? This assumes that P and P+1 are always complementary
5003 predicates for P even. */
5004 if (flags.is_and && rws_sum[regno].written_by_and)
5006 else if (flags.is_or && rws_sum[regno].written_by_or)
5008 else if ((rws_sum[regno].first_pred ^ 1) != pred)
5010 rws_update (rws_sum, regno, flags, pred);
5014 /* The register has been unconditionally written already. We
5016 if (flags.is_and && rws_sum[regno].written_by_and)
5018 else if (flags.is_or && rws_sum[regno].written_by_or)
5022 rws_sum[regno].written_by_and = flags.is_and;
5023 rws_sum[regno].written_by_or = flags.is_or;
5032 if (flags.is_branch)
5034 /* Branches have several RAW exceptions that allow to avoid
5037 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
5038 /* RAW dependencies on branch regs are permissible as long
5039 as the writer is a non-branch instruction. Since we
5040 never generate code that uses a branch register written
5041 by a branch instruction, handling this case is
5045 if (REGNO_REG_CLASS (regno) == PR_REGS
5046 && ! rws_sum[regno].written_by_fp)
5047 /* The predicates of a branch are available within the
5048 same insn group as long as the predicate was written by
5049 something other than a floating-point instruction. */
5053 if (flags.is_and && rws_sum[regno].written_by_and)
5055 if (flags.is_or && rws_sum[regno].written_by_or)
5058 switch (rws_sum[regno].write_count)
5061 /* The register has not been written yet. */
5065 /* The register has been written via a predicate. If this is
5066 not a complementary predicate, then we need a barrier. */
5067 /* ??? This assumes that P and P+1 are always complementary
5068 predicates for P even. */
5069 if ((rws_sum[regno].first_pred ^ 1) != pred)
5074 /* The register has been unconditionally written already. We
5084 return need_barrier;
5088 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5090 int regno = REGNO (reg);
5091 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5094 return rws_access_regno (regno, flags, pred);
5097 int need_barrier = 0;
5099 need_barrier |= rws_access_regno (regno + n, flags, pred);
5100 return need_barrier;
5104 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5105 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5108 update_set_flags (rtx x, struct reg_flags *pflags, int *ppred, rtx *pcond)
5110 rtx src = SET_SRC (x);
5114 switch (GET_CODE (src))
5120 if (SET_DEST (x) == pc_rtx)
5121 /* X is a conditional branch. */
5125 int is_complemented = 0;
5127 /* X is a conditional move. */
5128 rtx cond = XEXP (src, 0);
5129 if (GET_CODE (cond) == EQ)
5130 is_complemented = 1;
5131 cond = XEXP (cond, 0);
5132 if (GET_CODE (cond) != REG
5133 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
5136 if (XEXP (src, 1) == SET_DEST (x)
5137 || XEXP (src, 2) == SET_DEST (x))
5139 /* X is a conditional move that conditionally writes the
5142 /* We need another complement in this case. */
5143 if (XEXP (src, 1) == SET_DEST (x))
5144 is_complemented = ! is_complemented;
5146 *ppred = REGNO (cond);
5147 if (is_complemented)
5151 /* ??? If this is a conditional write to the dest, then this
5152 instruction does not actually read one source. This probably
5153 doesn't matter, because that source is also the dest. */
5154 /* ??? Multiple writes to predicate registers are allowed
5155 if they are all AND type compares, or if they are all OR
5156 type compares. We do not generate such instructions
5159 /* ... fall through ... */
5162 if (GET_RTX_CLASS (GET_CODE (src)) == '<'
5163 && GET_MODE_CLASS (GET_MODE (XEXP (src, 0))) == MODE_FLOAT)
5164 /* Set pflags->is_fp to 1 so that we know we're dealing
5165 with a floating point comparison when processing the
5166 destination of the SET. */
5169 /* Discover if this is a parallel comparison. We only handle
5170 and.orcm and or.andcm at present, since we must retain a
5171 strict inverse on the predicate pair. */
5172 else if (GET_CODE (src) == AND)
5174 else if (GET_CODE (src) == IOR)
5181 /* Subroutine of rtx_needs_barrier; this function determines whether the
5182 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5183 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5187 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred, rtx cond)
5189 int need_barrier = 0;
5191 rtx src = SET_SRC (x);
5193 if (GET_CODE (src) == CALL)
5194 /* We don't need to worry about the result registers that
5195 get written by subroutine call. */
5196 return rtx_needs_barrier (src, flags, pred);
5197 else if (SET_DEST (x) == pc_rtx)
5199 /* X is a conditional branch. */
5200 /* ??? This seems redundant, as the caller sets this bit for
5202 flags.is_branch = 1;
5203 return rtx_needs_barrier (src, flags, pred);
5206 need_barrier = rtx_needs_barrier (src, flags, pred);
5208 /* This instruction unconditionally uses a predicate register. */
5210 need_barrier |= rws_access_reg (cond, flags, 0);
5213 if (GET_CODE (dst) == ZERO_EXTRACT)
5215 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
5216 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
5217 dst = XEXP (dst, 0);
5219 return need_barrier;
5222 /* Handle an access to rtx X of type FLAGS using predicate register
5223 PRED. Return 1 if this access creates a dependency with an earlier
5224 instruction in the same group. */
5227 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
5230 int is_complemented = 0;
5231 int need_barrier = 0;
5232 const char *format_ptr;
5233 struct reg_flags new_flags;
5241 switch (GET_CODE (x))
5244 update_set_flags (x, &new_flags, &pred, &cond);
5245 need_barrier = set_src_needs_barrier (x, new_flags, pred, cond);
5246 if (GET_CODE (SET_SRC (x)) != CALL)
5248 new_flags.is_write = 1;
5249 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
5254 new_flags.is_write = 0;
5255 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5257 /* Avoid multiple register writes, in case this is a pattern with
5258 multiple CALL rtx. This avoids an abort in rws_access_reg. */
5259 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
5261 new_flags.is_write = 1;
5262 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
5263 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
5264 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5269 /* X is a predicated instruction. */
5271 cond = COND_EXEC_TEST (x);
5274 need_barrier = rtx_needs_barrier (cond, flags, 0);
5276 if (GET_CODE (cond) == EQ)
5277 is_complemented = 1;
5278 cond = XEXP (cond, 0);
5279 if (GET_CODE (cond) != REG
5280 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
5282 pred = REGNO (cond);
5283 if (is_complemented)
5286 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
5287 return need_barrier;
5291 /* Clobber & use are for earlier compiler-phases only. */
5296 /* We always emit stop bits for traditional asms. We emit stop bits
5297 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5298 if (GET_CODE (x) != ASM_OPERANDS
5299 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5301 /* Avoid writing the register multiple times if we have multiple
5302 asm outputs. This avoids an abort in rws_access_reg. */
5303 if (! rws_insn[REG_VOLATILE].write_count)
5305 new_flags.is_write = 1;
5306 rws_access_regno (REG_VOLATILE, new_flags, pred);
5311 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5312 We can not just fall through here since then we would be confused
5313 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5314 traditional asms unlike their normal usage. */
5316 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5317 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5322 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5324 rtx pat = XVECEXP (x, 0, i);
5325 if (GET_CODE (pat) == SET)
5327 update_set_flags (pat, &new_flags, &pred, &cond);
5328 need_barrier |= set_src_needs_barrier (pat, new_flags, pred, cond);
5330 else if (GET_CODE (pat) == USE
5331 || GET_CODE (pat) == CALL
5332 || GET_CODE (pat) == ASM_OPERANDS)
5333 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5334 else if (GET_CODE (pat) != CLOBBER && GET_CODE (pat) != RETURN)
5337 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5339 rtx pat = XVECEXP (x, 0, i);
5340 if (GET_CODE (pat) == SET)
5342 if (GET_CODE (SET_SRC (pat)) != CALL)
5344 new_flags.is_write = 1;
5345 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5349 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5350 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5358 if (REGNO (x) == AR_UNAT_REGNUM)
5360 for (i = 0; i < 64; ++i)
5361 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5364 need_barrier = rws_access_reg (x, flags, pred);
5368 /* Find the regs used in memory address computation. */
5369 new_flags.is_write = 0;
5370 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5373 case CONST_INT: case CONST_DOUBLE:
5374 case SYMBOL_REF: case LABEL_REF: case CONST:
5377 /* Operators with side-effects. */
5378 case POST_INC: case POST_DEC:
5379 if (GET_CODE (XEXP (x, 0)) != REG)
5382 new_flags.is_write = 0;
5383 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5384 new_flags.is_write = 1;
5385 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5389 if (GET_CODE (XEXP (x, 0)) != REG)
5392 new_flags.is_write = 0;
5393 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5394 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5395 new_flags.is_write = 1;
5396 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5399 /* Handle common unary and binary ops for efficiency. */
5400 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5401 case MOD: case UDIV: case UMOD: case AND: case IOR:
5402 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5403 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5404 case NE: case EQ: case GE: case GT: case LE:
5405 case LT: case GEU: case GTU: case LEU: case LTU:
5406 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5407 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5410 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5411 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5412 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5413 case SQRT: case FFS: case POPCOUNT:
5414 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5418 switch (XINT (x, 1))
5420 case UNSPEC_LTOFF_DTPMOD:
5421 case UNSPEC_LTOFF_DTPREL:
5423 case UNSPEC_LTOFF_TPREL:
5425 case UNSPEC_PRED_REL_MUTEX:
5426 case UNSPEC_PIC_CALL:
5428 case UNSPEC_FETCHADD_ACQ:
5429 case UNSPEC_BSP_VALUE:
5430 case UNSPEC_FLUSHRS:
5431 case UNSPEC_BUNDLE_SELECTOR:
5434 case UNSPEC_GR_SPILL:
5435 case UNSPEC_GR_RESTORE:
5437 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5438 HOST_WIDE_INT bit = (offset >> 3) & 63;
5440 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5441 new_flags.is_write = (XINT (x, 1) == 1);
5442 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5447 case UNSPEC_FR_SPILL:
5448 case UNSPEC_FR_RESTORE:
5449 case UNSPEC_GETF_EXP:
5450 case UNSPEC_SETF_EXP:
5452 case UNSPEC_FR_SQRT_RECIP_APPROX:
5453 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5456 case UNSPEC_FR_RECIP_APPROX:
5457 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5458 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5461 case UNSPEC_CMPXCHG_ACQ:
5462 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5463 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5471 case UNSPEC_VOLATILE:
5472 switch (XINT (x, 1))
5475 /* Alloc must always be the first instruction of a group.
5476 We force this by always returning true. */
5477 /* ??? We might get better scheduling if we explicitly check for
5478 input/local/output register dependencies, and modify the
5479 scheduler so that alloc is always reordered to the start of
5480 the current group. We could then eliminate all of the
5481 first_instruction code. */
5482 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5484 new_flags.is_write = 1;
5485 rws_access_regno (REG_AR_CFM, new_flags, pred);
5488 case UNSPECV_SET_BSP:
5492 case UNSPECV_BLOCKAGE:
5493 case UNSPECV_INSN_GROUP_BARRIER:
5495 case UNSPECV_PSAC_ALL:
5496 case UNSPECV_PSAC_NORMAL:
5505 new_flags.is_write = 0;
5506 need_barrier = rws_access_regno (REG_RP, flags, pred);
5507 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5509 new_flags.is_write = 1;
5510 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5511 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5515 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5516 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5517 switch (format_ptr[i])
5519 case '0': /* unused field */
5520 case 'i': /* integer */
5521 case 'n': /* note */
5522 case 'w': /* wide integer */
5523 case 's': /* pointer to string */
5524 case 'S': /* optional pointer to string */
5528 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5533 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5534 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5543 return need_barrier;
5546 /* Clear out the state for group_barrier_needed_p at the start of a
5547 sequence of insns. */
5550 init_insn_group_barriers (void)
5552 memset (rws_sum, 0, sizeof (rws_sum));
5553 first_instruction = 1;
5556 /* Given the current state, recorded by previous calls to this function,
5557 determine whether a group barrier (a stop bit) is necessary before INSN.
5558 Return nonzero if so. */
5561 group_barrier_needed_p (rtx insn)
5564 int need_barrier = 0;
5565 struct reg_flags flags;
5567 memset (&flags, 0, sizeof (flags));
5568 switch (GET_CODE (insn))
5574 /* A barrier doesn't imply an instruction group boundary. */
5578 memset (rws_insn, 0, sizeof (rws_insn));
5582 flags.is_branch = 1;
5583 flags.is_sibcall = SIBLING_CALL_P (insn);
5584 memset (rws_insn, 0, sizeof (rws_insn));
5586 /* Don't bundle a call following another call. */
5587 if ((pat = prev_active_insn (insn))
5588 && GET_CODE (pat) == CALL_INSN)
5594 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5598 flags.is_branch = 1;
5600 /* Don't bundle a jump following a call. */
5601 if ((pat = prev_active_insn (insn))
5602 && GET_CODE (pat) == CALL_INSN)
5610 if (GET_CODE (PATTERN (insn)) == USE
5611 || GET_CODE (PATTERN (insn)) == CLOBBER)
5612 /* Don't care about USE and CLOBBER "insns"---those are used to
5613 indicate to the optimizer that it shouldn't get rid of
5614 certain operations. */
5617 pat = PATTERN (insn);
5619 /* Ug. Hack hacks hacked elsewhere. */
5620 switch (recog_memoized (insn))
5622 /* We play dependency tricks with the epilogue in order
5623 to get proper schedules. Undo this for dv analysis. */
5624 case CODE_FOR_epilogue_deallocate_stack:
5625 case CODE_FOR_prologue_allocate_stack:
5626 pat = XVECEXP (pat, 0, 0);
5629 /* The pattern we use for br.cloop confuses the code above.
5630 The second element of the vector is representative. */
5631 case CODE_FOR_doloop_end_internal:
5632 pat = XVECEXP (pat, 0, 1);
5635 /* Doesn't generate code. */
5636 case CODE_FOR_pred_rel_mutex:
5637 case CODE_FOR_prologue_use:
5644 memset (rws_insn, 0, sizeof (rws_insn));
5645 need_barrier = rtx_needs_barrier (pat, flags, 0);
5647 /* Check to see if the previous instruction was a volatile
5650 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5657 if (first_instruction && INSN_P (insn)
5658 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5659 && GET_CODE (PATTERN (insn)) != USE
5660 && GET_CODE (PATTERN (insn)) != CLOBBER)
5663 first_instruction = 0;
5666 return need_barrier;
5669 /* Like group_barrier_needed_p, but do not clobber the current state. */
5672 safe_group_barrier_needed_p (rtx insn)
5674 struct reg_write_state rws_saved[NUM_REGS];
5675 int saved_first_instruction;
5678 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
5679 saved_first_instruction = first_instruction;
5681 t = group_barrier_needed_p (insn);
5683 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
5684 first_instruction = saved_first_instruction;
5689 /* Scan the current function and insert stop bits as necessary to
5690 eliminate dependencies. This function assumes that a final
5691 instruction scheduling pass has been run which has already
5692 inserted most of the necessary stop bits. This function only
5693 inserts new ones at basic block boundaries, since these are
5694 invisible to the scheduler. */
5697 emit_insn_group_barriers (FILE *dump)
5701 int insns_since_last_label = 0;
5703 init_insn_group_barriers ();
5705 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5707 if (GET_CODE (insn) == CODE_LABEL)
5709 if (insns_since_last_label)
5711 insns_since_last_label = 0;
5713 else if (GET_CODE (insn) == NOTE
5714 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
5716 if (insns_since_last_label)
5718 insns_since_last_label = 0;
5720 else if (GET_CODE (insn) == INSN
5721 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
5722 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
5724 init_insn_group_barriers ();
5727 else if (INSN_P (insn))
5729 insns_since_last_label = 1;
5731 if (group_barrier_needed_p (insn))
5736 fprintf (dump, "Emitting stop before label %d\n",
5737 INSN_UID (last_label));
5738 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
5741 init_insn_group_barriers ();
5749 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5750 This function has to emit all necessary group barriers. */
5753 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
5757 init_insn_group_barriers ();
5759 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5761 if (GET_CODE (insn) == BARRIER)
5763 rtx last = prev_active_insn (insn);
5767 if (GET_CODE (last) == JUMP_INSN
5768 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
5769 last = prev_active_insn (last);
5770 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
5771 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
5773 init_insn_group_barriers ();
5775 else if (INSN_P (insn))
5777 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
5778 init_insn_group_barriers ();
5779 else if (group_barrier_needed_p (insn))
5781 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5782 init_insn_group_barriers ();
5783 group_barrier_needed_p (insn);
5790 static int errata_find_address_regs (rtx *, void *);
5791 static void errata_emit_nops (rtx);
5792 static void fixup_errata (void);
5794 /* This structure is used to track some details about the previous insns
5795 groups so we can determine if it may be necessary to insert NOPs to
5796 workaround hardware errata. */
5799 HARD_REG_SET p_reg_set;
5800 HARD_REG_SET gr_reg_conditionally_set;
5803 /* Index into the last_group array. */
5804 static int group_idx;
5806 /* Called through for_each_rtx; determines if a hard register that was
5807 conditionally set in the previous group is used as an address register.
5808 It ensures that for_each_rtx returns 1 in that case. */
5810 errata_find_address_regs (rtx *xp, void *data ATTRIBUTE_UNUSED)
5813 if (GET_CODE (x) != MEM)
5816 if (GET_CODE (x) == POST_MODIFY)
5818 if (GET_CODE (x) == REG)
5820 struct group *prev_group = last_group + (group_idx ^ 1);
5821 if (TEST_HARD_REG_BIT (prev_group->gr_reg_conditionally_set,
5829 /* Called for each insn; this function keeps track of the state in
5830 last_group and emits additional NOPs if necessary to work around
5831 an Itanium A/B step erratum. */
5833 errata_emit_nops (rtx insn)
5835 struct group *this_group = last_group + group_idx;
5836 struct group *prev_group = last_group + (group_idx ^ 1);
5837 rtx pat = PATTERN (insn);
5838 rtx cond = GET_CODE (pat) == COND_EXEC ? COND_EXEC_TEST (pat) : 0;
5839 rtx real_pat = cond ? COND_EXEC_CODE (pat) : pat;
5840 enum attr_type type;
5843 if (GET_CODE (real_pat) == USE
5844 || GET_CODE (real_pat) == CLOBBER
5845 || GET_CODE (real_pat) == ASM_INPUT
5846 || GET_CODE (real_pat) == ADDR_VEC
5847 || GET_CODE (real_pat) == ADDR_DIFF_VEC
5848 || asm_noperands (PATTERN (insn)) >= 0)
5851 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5854 if (GET_CODE (set) == PARALLEL)
5857 set = XVECEXP (real_pat, 0, 0);
5858 for (i = 1; i < XVECLEN (real_pat, 0); i++)
5859 if (GET_CODE (XVECEXP (real_pat, 0, i)) != USE
5860 && GET_CODE (XVECEXP (real_pat, 0, i)) != CLOBBER)
5867 if (set && GET_CODE (set) != SET)
5870 type = get_attr_type (insn);
5873 && set && REG_P (SET_DEST (set)) && PR_REGNO_P (REGNO (SET_DEST (set))))
5874 SET_HARD_REG_BIT (this_group->p_reg_set, REGNO (SET_DEST (set)));
5876 if ((type == TYPE_M || type == TYPE_A) && cond && set
5877 && REG_P (SET_DEST (set))
5878 && GET_CODE (SET_SRC (set)) != PLUS
5879 && GET_CODE (SET_SRC (set)) != MINUS
5880 && (GET_CODE (SET_SRC (set)) != ASHIFT
5881 || !shladd_operand (XEXP (SET_SRC (set), 1), VOIDmode))
5882 && (GET_CODE (SET_SRC (set)) != MEM
5883 || GET_CODE (XEXP (SET_SRC (set), 0)) != POST_MODIFY)
5884 && GENERAL_REGNO_P (REGNO (SET_DEST (set))))
5886 if (GET_RTX_CLASS (GET_CODE (cond)) != '<'
5887 || ! REG_P (XEXP (cond, 0)))
5890 if (TEST_HARD_REG_BIT (prev_group->p_reg_set, REGNO (XEXP (cond, 0))))
5891 SET_HARD_REG_BIT (this_group->gr_reg_conditionally_set, REGNO (SET_DEST (set)));
5893 if (for_each_rtx (&real_pat, errata_find_address_regs, NULL))
5895 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5896 emit_insn_before (gen_nop (), insn);
5897 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5899 memset (last_group, 0, sizeof last_group);
5903 /* Emit extra nops if they are required to work around hardware errata. */
5910 if (! TARGET_B_STEP)
5914 memset (last_group, 0, sizeof last_group);
5916 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5921 if (ia64_safe_type (insn) == TYPE_S)
5924 memset (last_group + group_idx, 0, sizeof last_group[group_idx]);
5927 errata_emit_nops (insn);
5932 /* Instruction scheduling support. */
5934 #define NR_BUNDLES 10
5936 /* A list of names of all available bundles. */
5938 static const char *bundle_name [NR_BUNDLES] =
5944 #if NR_BUNDLES == 10
5954 /* Nonzero if we should insert stop bits into the schedule. */
5956 int ia64_final_schedule = 0;
5958 /* Codes of the corresponding quieryied units: */
5960 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
5961 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
5963 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
5964 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
5966 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
5968 /* The following variable value is an insn group barrier. */
5970 static rtx dfa_stop_insn;
5972 /* The following variable value is the last issued insn. */
5974 static rtx last_scheduled_insn;
5976 /* The following variable value is size of the DFA state. */
5978 static size_t dfa_state_size;
5980 /* The following variable value is pointer to a DFA state used as
5981 temporary variable. */
5983 static state_t temp_dfa_state = NULL;
5985 /* The following variable value is DFA state after issuing the last
5988 static state_t prev_cycle_state = NULL;
5990 /* The following array element values are TRUE if the corresponding
5991 insn requires to add stop bits before it. */
5993 static char *stops_p;
5995 /* The following variable is used to set up the mentioned above array. */
5997 static int stop_before_p = 0;
5999 /* The following variable value is length of the arrays `clocks' and
6002 static int clocks_length;
6004 /* The following array element values are cycles on which the
6005 corresponding insn will be issued. The array is used only for
6010 /* The following array element values are numbers of cycles should be
6011 added to improve insn scheduling for MM_insns for Itanium1. */
6013 static int *add_cycles;
6015 static rtx ia64_single_set (rtx);
6016 static void ia64_emit_insn_before (rtx, rtx);
6018 /* Map a bundle number to its pseudo-op. */
6021 get_bundle_name (int b)
6023 return bundle_name[b];
6027 /* Return the maximum number of instructions a cpu can issue. */
6030 ia64_issue_rate (void)
6035 /* Helper function - like single_set, but look inside COND_EXEC. */
6038 ia64_single_set (rtx insn)
6040 rtx x = PATTERN (insn), ret;
6041 if (GET_CODE (x) == COND_EXEC)
6042 x = COND_EXEC_CODE (x);
6043 if (GET_CODE (x) == SET)
6046 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6047 Although they are not classical single set, the second set is there just
6048 to protect it from moving past FP-relative stack accesses. */
6049 switch (recog_memoized (insn))
6051 case CODE_FOR_prologue_allocate_stack:
6052 case CODE_FOR_epilogue_deallocate_stack:
6053 ret = XVECEXP (x, 0, 0);
6057 ret = single_set_2 (insn, x);
6064 /* Adjust the cost of a scheduling dependency. Return the new cost of
6065 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6068 ia64_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
6070 enum attr_itanium_class dep_class;
6071 enum attr_itanium_class insn_class;
6073 if (REG_NOTE_KIND (link) != REG_DEP_OUTPUT)
6076 insn_class = ia64_safe_itanium_class (insn);
6077 dep_class = ia64_safe_itanium_class (dep_insn);
6078 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6079 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6085 /* Like emit_insn_before, but skip cycle_display notes.
6086 ??? When cycle display notes are implemented, update this. */
6089 ia64_emit_insn_before (rtx insn, rtx before)
6091 emit_insn_before (insn, before);
6094 /* The following function marks insns who produce addresses for load
6095 and store insns. Such insns will be placed into M slots because it
6096 decrease latency time for Itanium1 (see function
6097 `ia64_produce_address_p' and the DFA descriptions). */
6100 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6102 rtx insn, link, next, next_tail;
6104 next_tail = NEXT_INSN (tail);
6105 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6108 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6110 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6112 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
6114 next = XEXP (link, 0);
6115 if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_ST
6116 || ia64_safe_itanium_class (next) == ITANIUM_CLASS_STF)
6117 && ia64_st_address_bypass_p (insn, next))
6119 else if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_LD
6120 || ia64_safe_itanium_class (next)
6121 == ITANIUM_CLASS_FLD)
6122 && ia64_ld_address_bypass_p (insn, next))
6125 insn->call = link != 0;
6129 /* We're beginning a new block. Initialize data structures as necessary. */
6132 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6133 int sched_verbose ATTRIBUTE_UNUSED,
6134 int max_ready ATTRIBUTE_UNUSED)
6136 #ifdef ENABLE_CHECKING
6139 if (reload_completed)
6140 for (insn = NEXT_INSN (current_sched_info->prev_head);
6141 insn != current_sched_info->next_tail;
6142 insn = NEXT_INSN (insn))
6143 if (SCHED_GROUP_P (insn))
6146 last_scheduled_insn = NULL_RTX;
6147 init_insn_group_barriers ();
6150 /* We are about to being issuing insns for this clock cycle.
6151 Override the default sort algorithm to better slot instructions. */
6154 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6155 int *pn_ready, int clock_var ATTRIBUTE_UNUSED,
6159 int n_ready = *pn_ready;
6160 rtx *e_ready = ready + n_ready;
6164 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
6166 if (reorder_type == 0)
6168 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6170 for (insnp = ready; insnp < e_ready; insnp++)
6171 if (insnp < e_ready)
6174 enum attr_type t = ia64_safe_type (insn);
6175 if (t == TYPE_UNKNOWN)
6177 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6178 || asm_noperands (PATTERN (insn)) >= 0)
6180 rtx lowest = ready[n_asms];
6181 ready[n_asms] = insn;
6187 rtx highest = ready[n_ready - 1];
6188 ready[n_ready - 1] = insn;
6195 if (n_asms < n_ready)
6197 /* Some normal insns to process. Skip the asms. */
6201 else if (n_ready > 0)
6205 if (ia64_final_schedule)
6208 int nr_need_stop = 0;
6210 for (insnp = ready; insnp < e_ready; insnp++)
6211 if (safe_group_barrier_needed_p (*insnp))
6214 if (reorder_type == 1 && n_ready == nr_need_stop)
6216 if (reorder_type == 0)
6219 /* Move down everything that needs a stop bit, preserving
6221 while (insnp-- > ready + deleted)
6222 while (insnp >= ready + deleted)
6225 if (! safe_group_barrier_needed_p (insn))
6227 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6238 /* We are about to being issuing insns for this clock cycle. Override
6239 the default sort algorithm to better slot instructions. */
6242 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
6245 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
6246 pn_ready, clock_var, 0);
6249 /* Like ia64_sched_reorder, but called after issuing each insn.
6250 Override the default sort algorithm to better slot instructions. */
6253 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
6254 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
6255 int *pn_ready, int clock_var)
6257 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
6258 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
6259 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
6263 /* We are about to issue INSN. Return the number of insns left on the
6264 ready queue that can be issued this cycle. */
6267 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
6268 int sched_verbose ATTRIBUTE_UNUSED,
6269 rtx insn ATTRIBUTE_UNUSED,
6270 int can_issue_more ATTRIBUTE_UNUSED)
6272 last_scheduled_insn = insn;
6273 memcpy (prev_cycle_state, curr_state, dfa_state_size);
6274 if (reload_completed)
6276 if (group_barrier_needed_p (insn))
6278 if (GET_CODE (insn) == CALL_INSN)
6279 init_insn_group_barriers ();
6280 stops_p [INSN_UID (insn)] = stop_before_p;
6286 /* We are choosing insn from the ready queue. Return nonzero if INSN
6290 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
6292 if (insn == NULL_RTX || !INSN_P (insn))
6294 return (!reload_completed
6295 || !safe_group_barrier_needed_p (insn));
6298 /* The following variable value is pseudo-insn used by the DFA insn
6299 scheduler to change the DFA state when the simulated clock is
6302 static rtx dfa_pre_cycle_insn;
6304 /* We are about to being issuing INSN. Return nonzero if we can not
6305 issue it on given cycle CLOCK and return zero if we should not sort
6306 the ready queue on the next clock start. */
6309 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
6310 int clock, int *sort_p)
6312 int setup_clocks_p = FALSE;
6314 if (insn == NULL_RTX || !INSN_P (insn))
6316 if ((reload_completed && safe_group_barrier_needed_p (insn))
6317 || (last_scheduled_insn
6318 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6319 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6320 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6322 init_insn_group_barriers ();
6323 if (verbose && dump)
6324 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6325 last_clock == clock ? " + cycle advance" : "");
6327 if (last_clock == clock)
6329 state_transition (curr_state, dfa_stop_insn);
6330 if (TARGET_EARLY_STOP_BITS)
6331 *sort_p = (last_scheduled_insn == NULL_RTX
6332 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6337 else if (reload_completed)
6338 setup_clocks_p = TRUE;
6339 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6340 state_transition (curr_state, dfa_stop_insn);
6341 state_transition (curr_state, dfa_pre_cycle_insn);
6342 state_transition (curr_state, NULL);
6344 else if (reload_completed)
6345 setup_clocks_p = TRUE;
6346 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM)
6348 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6350 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6355 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6356 if (REG_NOTE_KIND (link) == 0)
6358 enum attr_itanium_class dep_class;
6359 rtx dep_insn = XEXP (link, 0);
6361 dep_class = ia64_safe_itanium_class (dep_insn);
6362 if ((dep_class == ITANIUM_CLASS_MMMUL
6363 || dep_class == ITANIUM_CLASS_MMSHF)
6364 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6366 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6367 d = last_clock - clocks [INSN_UID (dep_insn)];
6370 add_cycles [INSN_UID (insn)] = 3 - d;
6378 /* The following page contains abstract data `bundle states' which are
6379 used for bundling insns (inserting nops and template generation). */
6381 /* The following describes state of insn bundling. */
6385 /* Unique bundle state number to identify them in the debugging
6388 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
6389 /* number nops before and after the insn */
6390 short before_nops_num, after_nops_num;
6391 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
6393 int cost; /* cost of the state in cycles */
6394 int accumulated_insns_num; /* number of all previous insns including
6395 nops. L is considered as 2 insns */
6396 int branch_deviation; /* deviation of previous branches from 3rd slots */
6397 struct bundle_state *next; /* next state with the same insn_num */
6398 struct bundle_state *originator; /* originator (previous insn state) */
6399 /* All bundle states are in the following chain. */
6400 struct bundle_state *allocated_states_chain;
6401 /* The DFA State after issuing the insn and the nops. */
6405 /* The following is map insn number to the corresponding bundle state. */
6407 static struct bundle_state **index_to_bundle_states;
6409 /* The unique number of next bundle state. */
6411 static int bundle_states_num;
6413 /* All allocated bundle states are in the following chain. */
6415 static struct bundle_state *allocated_bundle_states_chain;
6417 /* All allocated but not used bundle states are in the following
6420 static struct bundle_state *free_bundle_state_chain;
6423 /* The following function returns a free bundle state. */
6425 static struct bundle_state *
6426 get_free_bundle_state (void)
6428 struct bundle_state *result;
6430 if (free_bundle_state_chain != NULL)
6432 result = free_bundle_state_chain;
6433 free_bundle_state_chain = result->next;
6437 result = xmalloc (sizeof (struct bundle_state));
6438 result->dfa_state = xmalloc (dfa_state_size);
6439 result->allocated_states_chain = allocated_bundle_states_chain;
6440 allocated_bundle_states_chain = result;
6442 result->unique_num = bundle_states_num++;
6447 /* The following function frees given bundle state. */
6450 free_bundle_state (struct bundle_state *state)
6452 state->next = free_bundle_state_chain;
6453 free_bundle_state_chain = state;
6456 /* Start work with abstract data `bundle states'. */
6459 initiate_bundle_states (void)
6461 bundle_states_num = 0;
6462 free_bundle_state_chain = NULL;
6463 allocated_bundle_states_chain = NULL;
6466 /* Finish work with abstract data `bundle states'. */
6469 finish_bundle_states (void)
6471 struct bundle_state *curr_state, *next_state;
6473 for (curr_state = allocated_bundle_states_chain;
6475 curr_state = next_state)
6477 next_state = curr_state->allocated_states_chain;
6478 free (curr_state->dfa_state);
6483 /* Hash table of the bundle states. The key is dfa_state and insn_num
6484 of the bundle states. */
6486 static htab_t bundle_state_table;
6488 /* The function returns hash of BUNDLE_STATE. */
6491 bundle_state_hash (const void *bundle_state)
6493 const struct bundle_state *state = (struct bundle_state *) bundle_state;
6496 for (result = i = 0; i < dfa_state_size; i++)
6497 result += (((unsigned char *) state->dfa_state) [i]
6498 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
6499 return result + state->insn_num;
6502 /* The function returns nonzero if the bundle state keys are equal. */
6505 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
6507 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
6508 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
6510 return (state1->insn_num == state2->insn_num
6511 && memcmp (state1->dfa_state, state2->dfa_state,
6512 dfa_state_size) == 0);
6515 /* The function inserts the BUNDLE_STATE into the hash table. The
6516 function returns nonzero if the bundle has been inserted into the
6517 table. The table contains the best bundle state with given key. */
6520 insert_bundle_state (struct bundle_state *bundle_state)
6524 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
6525 if (*entry_ptr == NULL)
6527 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
6528 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
6529 *entry_ptr = (void *) bundle_state;
6532 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
6533 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
6534 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
6535 > bundle_state->accumulated_insns_num
6536 || (((struct bundle_state *)
6537 *entry_ptr)->accumulated_insns_num
6538 == bundle_state->accumulated_insns_num
6539 && ((struct bundle_state *)
6540 *entry_ptr)->branch_deviation
6541 > bundle_state->branch_deviation))))
6544 struct bundle_state temp;
6546 temp = *(struct bundle_state *) *entry_ptr;
6547 *(struct bundle_state *) *entry_ptr = *bundle_state;
6548 ((struct bundle_state *) *entry_ptr)->next = temp.next;
6549 *bundle_state = temp;
6554 /* Start work with the hash table. */
6557 initiate_bundle_state_table (void)
6559 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
6563 /* Finish work with the hash table. */
6566 finish_bundle_state_table (void)
6568 htab_delete (bundle_state_table);
6573 /* The following variable is a insn `nop' used to check bundle states
6574 with different number of inserted nops. */
6576 static rtx ia64_nop;
6578 /* The following function tries to issue NOPS_NUM nops for the current
6579 state without advancing processor cycle. If it failed, the
6580 function returns FALSE and frees the current state. */
6583 try_issue_nops (struct bundle_state *curr_state, int nops_num)
6587 for (i = 0; i < nops_num; i++)
6588 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
6590 free_bundle_state (curr_state);
6596 /* The following function tries to issue INSN for the current
6597 state without advancing processor cycle. If it failed, the
6598 function returns FALSE and frees the current state. */
6601 try_issue_insn (struct bundle_state *curr_state, rtx insn)
6603 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
6605 free_bundle_state (curr_state);
6611 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6612 starting with ORIGINATOR without advancing processor cycle. If
6613 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6614 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6615 If it was successful, the function creates new bundle state and
6616 insert into the hash table and into `index_to_bundle_states'. */
6619 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
6620 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
6622 struct bundle_state *curr_state;
6624 curr_state = get_free_bundle_state ();
6625 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
6626 curr_state->insn = insn;
6627 curr_state->insn_num = originator->insn_num + 1;
6628 curr_state->cost = originator->cost;
6629 curr_state->originator = originator;
6630 curr_state->before_nops_num = before_nops_num;
6631 curr_state->after_nops_num = 0;
6632 curr_state->accumulated_insns_num
6633 = originator->accumulated_insns_num + before_nops_num;
6634 curr_state->branch_deviation = originator->branch_deviation;
6635 if (insn == NULL_RTX)
6637 else if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
6639 if (GET_MODE (insn) == TImode)
6641 if (!try_issue_nops (curr_state, before_nops_num))
6643 if (!try_issue_insn (curr_state, insn))
6645 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
6646 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
6647 && curr_state->accumulated_insns_num % 3 != 0)
6649 free_bundle_state (curr_state);
6653 else if (GET_MODE (insn) != TImode)
6655 if (!try_issue_nops (curr_state, before_nops_num))
6657 if (!try_issue_insn (curr_state, insn))
6659 curr_state->accumulated_insns_num++;
6660 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6661 || asm_noperands (PATTERN (insn)) >= 0)
6663 if (ia64_safe_type (insn) == TYPE_L)
6664 curr_state->accumulated_insns_num++;
6668 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
6669 state_transition (curr_state->dfa_state, NULL);
6671 if (!try_issue_nops (curr_state, before_nops_num))
6673 if (!try_issue_insn (curr_state, insn))
6675 curr_state->accumulated_insns_num++;
6676 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6677 || asm_noperands (PATTERN (insn)) >= 0)
6679 /* Finish bundle containing asm insn. */
6680 curr_state->after_nops_num
6681 = 3 - curr_state->accumulated_insns_num % 3;
6682 curr_state->accumulated_insns_num
6683 += 3 - curr_state->accumulated_insns_num % 3;
6685 else if (ia64_safe_type (insn) == TYPE_L)
6686 curr_state->accumulated_insns_num++;
6688 if (ia64_safe_type (insn) == TYPE_B)
6689 curr_state->branch_deviation
6690 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
6691 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
6693 if (!only_bundle_end_p && insert_bundle_state (curr_state))
6696 struct bundle_state *curr_state1;
6697 struct bundle_state *allocated_states_chain;
6699 curr_state1 = get_free_bundle_state ();
6700 dfa_state = curr_state1->dfa_state;
6701 allocated_states_chain = curr_state1->allocated_states_chain;
6702 *curr_state1 = *curr_state;
6703 curr_state1->dfa_state = dfa_state;
6704 curr_state1->allocated_states_chain = allocated_states_chain;
6705 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
6707 curr_state = curr_state1;
6709 if (!try_issue_nops (curr_state,
6710 3 - curr_state->accumulated_insns_num % 3))
6712 curr_state->after_nops_num
6713 = 3 - curr_state->accumulated_insns_num % 3;
6714 curr_state->accumulated_insns_num
6715 += 3 - curr_state->accumulated_insns_num % 3;
6717 if (!insert_bundle_state (curr_state))
6718 free_bundle_state (curr_state);
6722 /* The following function returns position in the two window bundle
6726 get_max_pos (state_t state)
6728 if (cpu_unit_reservation_p (state, pos_6))
6730 else if (cpu_unit_reservation_p (state, pos_5))
6732 else if (cpu_unit_reservation_p (state, pos_4))
6734 else if (cpu_unit_reservation_p (state, pos_3))
6736 else if (cpu_unit_reservation_p (state, pos_2))
6738 else if (cpu_unit_reservation_p (state, pos_1))
6744 /* The function returns code of a possible template for given position
6745 and state. The function should be called only with 2 values of
6746 position equal to 3 or 6. */
6749 get_template (state_t state, int pos)
6754 if (cpu_unit_reservation_p (state, _0mii_))
6756 else if (cpu_unit_reservation_p (state, _0mmi_))
6758 else if (cpu_unit_reservation_p (state, _0mfi_))
6760 else if (cpu_unit_reservation_p (state, _0mmf_))
6762 else if (cpu_unit_reservation_p (state, _0bbb_))
6764 else if (cpu_unit_reservation_p (state, _0mbb_))
6766 else if (cpu_unit_reservation_p (state, _0mib_))
6768 else if (cpu_unit_reservation_p (state, _0mmb_))
6770 else if (cpu_unit_reservation_p (state, _0mfb_))
6772 else if (cpu_unit_reservation_p (state, _0mlx_))
6777 if (cpu_unit_reservation_p (state, _1mii_))
6779 else if (cpu_unit_reservation_p (state, _1mmi_))
6781 else if (cpu_unit_reservation_p (state, _1mfi_))
6783 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
6785 else if (cpu_unit_reservation_p (state, _1bbb_))
6787 else if (cpu_unit_reservation_p (state, _1mbb_))
6789 else if (cpu_unit_reservation_p (state, _1mib_))
6791 else if (cpu_unit_reservation_p (state, _1mmb_))
6793 else if (cpu_unit_reservation_p (state, _1mfb_))
6795 else if (cpu_unit_reservation_p (state, _1mlx_))
6804 /* The following function returns an insn important for insn bundling
6805 followed by INSN and before TAIL. */
6808 get_next_important_insn (rtx insn, rtx tail)
6810 for (; insn && insn != tail; insn = NEXT_INSN (insn))
6812 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6813 && GET_CODE (PATTERN (insn)) != USE
6814 && GET_CODE (PATTERN (insn)) != CLOBBER)
6819 /* The following function does insn bundling. Bundling means
6820 inserting templates and nop insns to fit insn groups into permitted
6821 templates. Instruction scheduling uses NDFA (non-deterministic
6822 finite automata) encoding informations about the templates and the
6823 inserted nops. Nondeterminism of the automata permits follows
6824 all possible insn sequences very fast.
6826 Unfortunately it is not possible to get information about inserting
6827 nop insns and used templates from the automata states. The
6828 automata only says that we can issue an insn possibly inserting
6829 some nops before it and using some template. Therefore insn
6830 bundling in this function is implemented by using DFA
6831 (deterministic finite automata). We follows all possible insn
6832 sequences by inserting 0-2 nops (that is what the NDFA describe for
6833 insn scheduling) before/after each insn being bundled. We know the
6834 start of simulated processor cycle from insn scheduling (insn
6835 starting a new cycle has TImode).
6837 Simple implementation of insn bundling would create enormous
6838 number of possible insn sequences satisfying information about new
6839 cycle ticks taken from the insn scheduling. To make the algorithm
6840 practical we use dynamic programming. Each decision (about
6841 inserting nops and implicitly about previous decisions) is described
6842 by structure bundle_state (see above). If we generate the same
6843 bundle state (key is automaton state after issuing the insns and
6844 nops for it), we reuse already generated one. As consequence we
6845 reject some decisions which can not improve the solution and
6846 reduce memory for the algorithm.
6848 When we reach the end of EBB (extended basic block), we choose the
6849 best sequence and then, moving back in EBB, insert templates for
6850 the best alternative. The templates are taken from querying
6851 automaton state for each insn in chosen bundle states.
6853 So the algorithm makes two (forward and backward) passes through
6854 EBB. There is an additional forward pass through EBB for Itanium1
6855 processor. This pass inserts more nops to make dependency between
6856 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
6859 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
6861 struct bundle_state *curr_state, *next_state, *best_state;
6862 rtx insn, next_insn;
6864 int i, bundle_end_p, only_bundle_end_p, asm_p;
6865 int pos = 0, max_pos, template0, template1;
6868 enum attr_type type;
6871 /* Count insns in the EBB. */
6872 for (insn = NEXT_INSN (prev_head_insn);
6873 insn && insn != tail;
6874 insn = NEXT_INSN (insn))
6880 dfa_clean_insn_cache ();
6881 initiate_bundle_state_table ();
6882 index_to_bundle_states = xmalloc ((insn_num + 2)
6883 * sizeof (struct bundle_state *));
6884 /* First (forward) pass -- generation of bundle states. */
6885 curr_state = get_free_bundle_state ();
6886 curr_state->insn = NULL;
6887 curr_state->before_nops_num = 0;
6888 curr_state->after_nops_num = 0;
6889 curr_state->insn_num = 0;
6890 curr_state->cost = 0;
6891 curr_state->accumulated_insns_num = 0;
6892 curr_state->branch_deviation = 0;
6893 curr_state->next = NULL;
6894 curr_state->originator = NULL;
6895 state_reset (curr_state->dfa_state);
6896 index_to_bundle_states [0] = curr_state;
6898 /* Shift cycle mark if it is put on insn which could be ignored. */
6899 for (insn = NEXT_INSN (prev_head_insn);
6901 insn = NEXT_INSN (insn))
6903 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6904 || GET_CODE (PATTERN (insn)) == USE
6905 || GET_CODE (PATTERN (insn)) == CLOBBER)
6906 && GET_MODE (insn) == TImode)
6908 PUT_MODE (insn, VOIDmode);
6909 for (next_insn = NEXT_INSN (insn);
6911 next_insn = NEXT_INSN (next_insn))
6912 if (INSN_P (next_insn)
6913 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
6914 && GET_CODE (PATTERN (next_insn)) != USE
6915 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
6917 PUT_MODE (next_insn, TImode);
6921 /* Froward pass: generation of bundle states. */
6922 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6927 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6928 || GET_CODE (PATTERN (insn)) == USE
6929 || GET_CODE (PATTERN (insn)) == CLOBBER)
6931 type = ia64_safe_type (insn);
6932 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6934 index_to_bundle_states [insn_num] = NULL;
6935 for (curr_state = index_to_bundle_states [insn_num - 1];
6937 curr_state = next_state)
6939 pos = curr_state->accumulated_insns_num % 3;
6940 next_state = curr_state->next;
6941 /* We must fill up the current bundle in order to start a
6942 subsequent asm insn in a new bundle. Asm insn is always
6943 placed in a separate bundle. */
6945 = (next_insn != NULL_RTX
6946 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
6947 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
6948 /* We may fill up the current bundle if it is the cycle end
6949 without a group barrier. */
6951 = (only_bundle_end_p || next_insn == NULL_RTX
6952 || (GET_MODE (next_insn) == TImode
6953 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
6954 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
6956 /* We need to insert 2 nops for cases like M_MII. To
6957 guarantee issuing all insns on the same cycle for
6958 Itanium 1, we need to issue 2 nops after the first M
6959 insn (MnnMII where n is a nop insn). */
6960 || (type == TYPE_M && ia64_tune == PROCESSOR_ITANIUM
6961 && !bundle_end_p && pos == 1))
6962 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
6964 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
6966 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
6969 if (index_to_bundle_states [insn_num] == NULL)
6971 for (curr_state = index_to_bundle_states [insn_num];
6973 curr_state = curr_state->next)
6974 if (verbose >= 2 && dump)
6976 /* This structure is taken from generated code of the
6977 pipeline hazard recognizer (see file insn-attrtab.c).
6978 Please don't forget to change the structure if a new
6979 automaton is added to .md file. */
6982 unsigned short one_automaton_state;
6983 unsigned short oneb_automaton_state;
6984 unsigned short two_automaton_state;
6985 unsigned short twob_automaton_state;
6990 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6991 curr_state->unique_num,
6992 (curr_state->originator == NULL
6993 ? -1 : curr_state->originator->unique_num),
6995 curr_state->before_nops_num, curr_state->after_nops_num,
6996 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6997 (ia64_tune == PROCESSOR_ITANIUM
6998 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6999 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7003 if (index_to_bundle_states [insn_num] == NULL)
7004 /* We should find a solution because the 2nd insn scheduling has
7007 /* Find a state corresponding to the best insn sequence. */
7009 for (curr_state = index_to_bundle_states [insn_num];
7011 curr_state = curr_state->next)
7012 /* We are just looking at the states with fully filled up last
7013 bundle. The first we prefer insn sequences with minimal cost
7014 then with minimal inserted nops and finally with branch insns
7015 placed in the 3rd slots. */
7016 if (curr_state->accumulated_insns_num % 3 == 0
7017 && (best_state == NULL || best_state->cost > curr_state->cost
7018 || (best_state->cost == curr_state->cost
7019 && (curr_state->accumulated_insns_num
7020 < best_state->accumulated_insns_num
7021 || (curr_state->accumulated_insns_num
7022 == best_state->accumulated_insns_num
7023 && curr_state->branch_deviation
7024 < best_state->branch_deviation)))))
7025 best_state = curr_state;
7026 /* Second (backward) pass: adding nops and templates. */
7027 insn_num = best_state->before_nops_num;
7028 template0 = template1 = -1;
7029 for (curr_state = best_state;
7030 curr_state->originator != NULL;
7031 curr_state = curr_state->originator)
7033 insn = curr_state->insn;
7034 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
7035 || asm_noperands (PATTERN (insn)) >= 0);
7037 if (verbose >= 2 && dump)
7041 unsigned short one_automaton_state;
7042 unsigned short oneb_automaton_state;
7043 unsigned short two_automaton_state;
7044 unsigned short twob_automaton_state;
7049 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7050 curr_state->unique_num,
7051 (curr_state->originator == NULL
7052 ? -1 : curr_state->originator->unique_num),
7054 curr_state->before_nops_num, curr_state->after_nops_num,
7055 curr_state->accumulated_insns_num, curr_state->branch_deviation,
7056 (ia64_tune == PROCESSOR_ITANIUM
7057 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
7058 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7061 /* Find the position in the current bundle window. The window can
7062 contain at most two bundles. Two bundle window means that
7063 the processor will make two bundle rotation. */
7064 max_pos = get_max_pos (curr_state->dfa_state);
7066 /* The following (negative template number) means that the
7067 processor did one bundle rotation. */
7068 || (max_pos == 3 && template0 < 0))
7070 /* We are at the end of the window -- find template(s) for
7074 template0 = get_template (curr_state->dfa_state, 3);
7077 template1 = get_template (curr_state->dfa_state, 3);
7078 template0 = get_template (curr_state->dfa_state, 6);
7081 if (max_pos > 3 && template1 < 0)
7082 /* It may happen when we have the stop inside a bundle. */
7086 template1 = get_template (curr_state->dfa_state, 3);
7090 /* Emit nops after the current insn. */
7091 for (i = 0; i < curr_state->after_nops_num; i++)
7094 emit_insn_after (nop, insn);
7100 /* We are at the start of a bundle: emit the template
7101 (it should be defined). */
7104 b = gen_bundle_selector (GEN_INT (template0));
7105 ia64_emit_insn_before (b, nop);
7106 /* If we have two bundle window, we make one bundle
7107 rotation. Otherwise template0 will be undefined
7108 (negative value). */
7109 template0 = template1;
7113 /* Move the position backward in the window. Group barrier has
7114 no slot. Asm insn takes all bundle. */
7115 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7116 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7117 && asm_noperands (PATTERN (insn)) < 0)
7119 /* Long insn takes 2 slots. */
7120 if (ia64_safe_type (insn) == TYPE_L)
7125 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7126 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7127 && asm_noperands (PATTERN (insn)) < 0)
7129 /* The current insn is at the bundle start: emit the
7133 b = gen_bundle_selector (GEN_INT (template0));
7134 ia64_emit_insn_before (b, insn);
7135 b = PREV_INSN (insn);
7137 /* See comment above in analogous place for emitting nops
7139 template0 = template1;
7142 /* Emit nops after the current insn. */
7143 for (i = 0; i < curr_state->before_nops_num; i++)
7146 ia64_emit_insn_before (nop, insn);
7147 nop = PREV_INSN (insn);
7154 /* See comment above in analogous place for emitting nops
7158 b = gen_bundle_selector (GEN_INT (template0));
7159 ia64_emit_insn_before (b, insn);
7160 b = PREV_INSN (insn);
7162 template0 = template1;
7167 if (ia64_tune == PROCESSOR_ITANIUM)
7168 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
7169 Itanium1 has a strange design, if the distance between an insn
7170 and dependent MM-insn is less 4 then we have a 6 additional
7171 cycles stall. So we make the distance equal to 4 cycles if it
7173 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
7178 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
7179 || GET_CODE (PATTERN (insn)) == USE
7180 || GET_CODE (PATTERN (insn)) == CLOBBER)
7182 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
7183 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
7184 /* We found a MM-insn which needs additional cycles. */
7190 /* Now we are searching for a template of the bundle in
7191 which the MM-insn is placed and the position of the
7192 insn in the bundle (0, 1, 2). Also we are searching
7193 for that there is a stop before the insn. */
7194 last = prev_active_insn (insn);
7195 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
7197 last = prev_active_insn (last);
7199 for (;; last = prev_active_insn (last))
7200 if (recog_memoized (last) == CODE_FOR_bundle_selector)
7202 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
7204 /* The insn is in MLX bundle. Change the template
7205 onto MFI because we will add nops before the
7206 insn. It simplifies subsequent code a lot. */
7208 = gen_bundle_selector (const2_rtx); /* -> MFI */
7211 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7213 /* Some check of correctness: the stop is not at the
7214 bundle start, there are no more 3 insns in the bundle,
7215 and the MM-insn is not at the start of bundle with
7217 if ((pred_stop_p && n == 0) || n > 2
7218 || (template0 == 9 && n != 0))
7220 /* Put nops after the insn in the bundle. */
7221 for (j = 3 - n; j > 0; j --)
7222 ia64_emit_insn_before (gen_nop (), insn);
7223 /* It takes into account that we will add more N nops
7224 before the insn lately -- please see code below. */
7225 add_cycles [INSN_UID (insn)]--;
7226 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
7227 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7230 add_cycles [INSN_UID (insn)]--;
7231 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
7233 /* Insert "MII;" template. */
7234 ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
7236 ia64_emit_insn_before (gen_nop (), insn);
7237 ia64_emit_insn_before (gen_nop (), insn);
7240 /* To decrease code size, we use "MI;I;"
7242 ia64_emit_insn_before
7243 (gen_insn_group_barrier (GEN_INT (3)), insn);
7246 ia64_emit_insn_before (gen_nop (), insn);
7247 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7250 /* Put the MM-insn in the same slot of a bundle with the
7251 same template as the original one. */
7252 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
7254 /* To put the insn in the same slot, add necessary number
7256 for (j = n; j > 0; j --)
7257 ia64_emit_insn_before (gen_nop (), insn);
7258 /* Put the stop if the original bundle had it. */
7260 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7264 free (index_to_bundle_states);
7265 finish_bundle_state_table ();
7267 dfa_clean_insn_cache ();
7270 /* The following function is called at the end of scheduling BB or
7271 EBB. After reload, it inserts stop bits and does insn bundling. */
7274 ia64_sched_finish (FILE *dump, int sched_verbose)
7277 fprintf (dump, "// Finishing schedule.\n");
7278 if (!reload_completed)
7280 if (reload_completed)
7282 final_emit_insn_group_barriers (dump);
7283 bundling (dump, sched_verbose, current_sched_info->prev_head,
7284 current_sched_info->next_tail);
7285 if (sched_verbose && dump)
7286 fprintf (dump, "// finishing %d-%d\n",
7287 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
7288 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
7294 /* The following function inserts stop bits in scheduled BB or EBB. */
7297 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
7300 int need_barrier_p = 0;
7301 rtx prev_insn = NULL_RTX;
7303 init_insn_group_barriers ();
7305 for (insn = NEXT_INSN (current_sched_info->prev_head);
7306 insn != current_sched_info->next_tail;
7307 insn = NEXT_INSN (insn))
7309 if (GET_CODE (insn) == BARRIER)
7311 rtx last = prev_active_insn (insn);
7315 if (GET_CODE (last) == JUMP_INSN
7316 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
7317 last = prev_active_insn (last);
7318 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7319 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
7321 init_insn_group_barriers ();
7323 prev_insn = NULL_RTX;
7325 else if (INSN_P (insn))
7327 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
7329 init_insn_group_barriers ();
7331 prev_insn = NULL_RTX;
7333 else if (need_barrier_p || group_barrier_needed_p (insn))
7335 if (TARGET_EARLY_STOP_BITS)
7340 last != current_sched_info->prev_head;
7341 last = PREV_INSN (last))
7342 if (INSN_P (last) && GET_MODE (last) == TImode
7343 && stops_p [INSN_UID (last)])
7345 if (last == current_sched_info->prev_head)
7347 last = prev_active_insn (last);
7349 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
7350 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7352 init_insn_group_barriers ();
7353 for (last = NEXT_INSN (last);
7355 last = NEXT_INSN (last))
7357 group_barrier_needed_p (last);
7361 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7363 init_insn_group_barriers ();
7365 group_barrier_needed_p (insn);
7366 prev_insn = NULL_RTX;
7368 else if (recog_memoized (insn) >= 0)
7370 need_barrier_p = (GET_CODE (insn) == CALL_INSN
7371 || GET_CODE (PATTERN (insn)) == ASM_INPUT
7372 || asm_noperands (PATTERN (insn)) >= 0);
7379 /* If the following function returns TRUE, we will use the the DFA
7383 ia64_use_dfa_pipeline_interface (void)
7388 /* If the following function returns TRUE, we will use the the DFA
7392 ia64_first_cycle_multipass_dfa_lookahead (void)
7394 return (reload_completed ? 6 : 4);
7397 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7400 ia64_init_dfa_pre_cycle_insn (void)
7402 if (temp_dfa_state == NULL)
7404 dfa_state_size = state_size ();
7405 temp_dfa_state = xmalloc (dfa_state_size);
7406 prev_cycle_state = xmalloc (dfa_state_size);
7408 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
7409 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
7410 recog_memoized (dfa_pre_cycle_insn);
7411 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7412 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
7413 recog_memoized (dfa_stop_insn);
7416 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7417 used by the DFA insn scheduler. */
7420 ia64_dfa_pre_cycle_insn (void)
7422 return dfa_pre_cycle_insn;
7425 /* The following function returns TRUE if PRODUCER (of type ilog or
7426 ld) produces address for CONSUMER (of type st or stf). */
7429 ia64_st_address_bypass_p (rtx producer, rtx consumer)
7433 if (producer == NULL_RTX || consumer == NULL_RTX)
7435 dest = ia64_single_set (producer);
7436 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7437 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7439 if (GET_CODE (reg) == SUBREG)
7440 reg = SUBREG_REG (reg);
7441 dest = ia64_single_set (consumer);
7442 if (dest == NULL_RTX || (mem = SET_DEST (dest)) == NULL_RTX
7443 || GET_CODE (mem) != MEM)
7445 return reg_mentioned_p (reg, mem);
7448 /* The following function returns TRUE if PRODUCER (of type ilog or
7449 ld) produces address for CONSUMER (of type ld or fld). */
7452 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
7454 rtx dest, src, reg, mem;
7456 if (producer == NULL_RTX || consumer == NULL_RTX)
7458 dest = ia64_single_set (producer);
7459 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7460 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7462 if (GET_CODE (reg) == SUBREG)
7463 reg = SUBREG_REG (reg);
7464 src = ia64_single_set (consumer);
7465 if (src == NULL_RTX || (mem = SET_SRC (src)) == NULL_RTX)
7467 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
7468 mem = XVECEXP (mem, 0, 0);
7469 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
7470 mem = XEXP (mem, 0);
7472 /* Note that LO_SUM is used for GOT loads. */
7473 if (GET_CODE (mem) != LO_SUM && GET_CODE (mem) != MEM)
7476 return reg_mentioned_p (reg, mem);
7479 /* The following function returns TRUE if INSN produces address for a
7480 load/store insn. We will place such insns into M slot because it
7481 decreases its latency time. */
7484 ia64_produce_address_p (rtx insn)
7490 /* Emit pseudo-ops for the assembler to describe predicate relations.
7491 At present this assumes that we only consider predicate pairs to
7492 be mutex, and that the assembler can deduce proper values from
7493 straight-line code. */
7496 emit_predicate_relation_info (void)
7500 FOR_EACH_BB_REVERSE (bb)
7503 rtx head = BB_HEAD (bb);
7505 /* We only need such notes at code labels. */
7506 if (GET_CODE (head) != CODE_LABEL)
7508 if (GET_CODE (NEXT_INSN (head)) == NOTE
7509 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
7510 head = NEXT_INSN (head);
7512 for (r = PR_REG (0); r < PR_REG (64); r += 2)
7513 if (REGNO_REG_SET_P (bb->global_live_at_start, r))
7515 rtx p = gen_rtx_REG (BImode, r);
7516 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
7517 if (head == BB_END (bb))
7523 /* Look for conditional calls that do not return, and protect predicate
7524 relations around them. Otherwise the assembler will assume the call
7525 returns, and complain about uses of call-clobbered predicates after
7527 FOR_EACH_BB_REVERSE (bb)
7529 rtx insn = BB_HEAD (bb);
7533 if (GET_CODE (insn) == CALL_INSN
7534 && GET_CODE (PATTERN (insn)) == COND_EXEC
7535 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
7537 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
7538 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
7539 if (BB_HEAD (bb) == insn)
7541 if (BB_END (bb) == insn)
7545 if (insn == BB_END (bb))
7547 insn = NEXT_INSN (insn);
7552 /* Perform machine dependent operations on the rtl chain INSNS. */
7557 /* We are freeing block_for_insn in the toplev to keep compatibility
7558 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7559 compute_bb_for_insn ();
7561 /* If optimizing, we'll have split before scheduling. */
7563 split_all_insns (0);
7565 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7566 non-optimizing bootstrap. */
7567 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
7569 if (ia64_flag_schedule_insns2)
7571 timevar_push (TV_SCHED2);
7572 ia64_final_schedule = 1;
7574 initiate_bundle_states ();
7575 ia64_nop = make_insn_raw (gen_nop ());
7576 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
7577 recog_memoized (ia64_nop);
7578 clocks_length = get_max_uid () + 1;
7579 stops_p = xcalloc (1, clocks_length);
7580 if (ia64_tune == PROCESSOR_ITANIUM)
7582 clocks = xcalloc (clocks_length, sizeof (int));
7583 add_cycles = xcalloc (clocks_length, sizeof (int));
7585 if (ia64_tune == PROCESSOR_ITANIUM2)
7587 pos_1 = get_cpu_unit_code ("2_1");
7588 pos_2 = get_cpu_unit_code ("2_2");
7589 pos_3 = get_cpu_unit_code ("2_3");
7590 pos_4 = get_cpu_unit_code ("2_4");
7591 pos_5 = get_cpu_unit_code ("2_5");
7592 pos_6 = get_cpu_unit_code ("2_6");
7593 _0mii_ = get_cpu_unit_code ("2b_0mii.");
7594 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
7595 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
7596 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
7597 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
7598 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
7599 _0mib_ = get_cpu_unit_code ("2b_0mib.");
7600 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
7601 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
7602 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
7603 _1mii_ = get_cpu_unit_code ("2b_1mii.");
7604 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
7605 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
7606 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
7607 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
7608 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
7609 _1mib_ = get_cpu_unit_code ("2b_1mib.");
7610 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
7611 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
7612 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
7616 pos_1 = get_cpu_unit_code ("1_1");
7617 pos_2 = get_cpu_unit_code ("1_2");
7618 pos_3 = get_cpu_unit_code ("1_3");
7619 pos_4 = get_cpu_unit_code ("1_4");
7620 pos_5 = get_cpu_unit_code ("1_5");
7621 pos_6 = get_cpu_unit_code ("1_6");
7622 _0mii_ = get_cpu_unit_code ("1b_0mii.");
7623 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
7624 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
7625 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
7626 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
7627 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
7628 _0mib_ = get_cpu_unit_code ("1b_0mib.");
7629 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
7630 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
7631 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
7632 _1mii_ = get_cpu_unit_code ("1b_1mii.");
7633 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
7634 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
7635 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
7636 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
7637 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
7638 _1mib_ = get_cpu_unit_code ("1b_1mib.");
7639 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
7640 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
7641 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
7643 schedule_ebbs (dump_file);
7644 finish_bundle_states ();
7645 if (ia64_tune == PROCESSOR_ITANIUM)
7651 emit_insn_group_barriers (dump_file);
7653 ia64_final_schedule = 0;
7654 timevar_pop (TV_SCHED2);
7657 emit_all_insn_group_barriers (dump_file);
7659 /* A call must not be the last instruction in a function, so that the
7660 return address is still within the function, so that unwinding works
7661 properly. Note that IA-64 differs from dwarf2 on this point. */
7662 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7667 insn = get_last_insn ();
7668 if (! INSN_P (insn))
7669 insn = prev_active_insn (insn);
7670 if (GET_CODE (insn) == INSN
7671 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
7672 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
7675 insn = prev_active_insn (insn);
7677 if (GET_CODE (insn) == CALL_INSN)
7680 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7681 emit_insn (gen_break_f ());
7682 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7687 emit_predicate_relation_info ();
7689 if (ia64_flag_var_tracking)
7691 timevar_push (TV_VAR_TRACKING);
7692 variable_tracking_main ();
7693 timevar_pop (TV_VAR_TRACKING);
7697 /* Return true if REGNO is used by the epilogue. */
7700 ia64_epilogue_uses (int regno)
7705 /* With a call to a function in another module, we will write a new
7706 value to "gp". After returning from such a call, we need to make
7707 sure the function restores the original gp-value, even if the
7708 function itself does not use the gp anymore. */
7709 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
7711 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7712 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7713 /* For functions defined with the syscall_linkage attribute, all
7714 input registers are marked as live at all function exits. This
7715 prevents the register allocator from using the input registers,
7716 which in turn makes it possible to restart a system call after
7717 an interrupt without having to save/restore the input registers.
7718 This also prevents kernel data from leaking to application code. */
7719 return lookup_attribute ("syscall_linkage",
7720 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
7723 /* Conditional return patterns can't represent the use of `b0' as
7724 the return address, so we force the value live this way. */
7728 /* Likewise for ar.pfs, which is used by br.ret. */
7736 /* Return true if REGNO is used by the frame unwinder. */
7739 ia64_eh_uses (int regno)
7741 if (! reload_completed)
7744 if (current_frame_info.reg_save_b0
7745 && regno == current_frame_info.reg_save_b0)
7747 if (current_frame_info.reg_save_pr
7748 && regno == current_frame_info.reg_save_pr)
7750 if (current_frame_info.reg_save_ar_pfs
7751 && regno == current_frame_info.reg_save_ar_pfs)
7753 if (current_frame_info.reg_save_ar_unat
7754 && regno == current_frame_info.reg_save_ar_unat)
7756 if (current_frame_info.reg_save_ar_lc
7757 && regno == current_frame_info.reg_save_ar_lc)
7763 /* Return true if this goes in small data/bss. */
7765 /* ??? We could also support own long data here. Generating movl/add/ld8
7766 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7767 code faster because there is one less load. This also includes incomplete
7768 types which can't go in sdata/sbss. */
7771 ia64_in_small_data_p (tree exp)
7773 if (TARGET_NO_SDATA)
7776 /* We want to merge strings, so we never consider them small data. */
7777 if (TREE_CODE (exp) == STRING_CST)
7780 /* Functions are never small data. */
7781 if (TREE_CODE (exp) == FUNCTION_DECL)
7784 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
7786 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
7787 if (strcmp (section, ".sdata") == 0
7788 || strcmp (section, ".sbss") == 0)
7793 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
7795 /* If this is an incomplete type with size 0, then we can't put it
7796 in sdata because it might be too big when completed. */
7797 if (size > 0 && size <= ia64_section_threshold)
7804 /* Output assembly directives for prologue regions. */
7806 /* The current basic block number. */
7808 static bool last_block;
7810 /* True if we need a copy_state command at the start of the next block. */
7812 static bool need_copy_state;
7814 /* The function emits unwind directives for the start of an epilogue. */
7817 process_epilogue (void)
7819 /* If this isn't the last block of the function, then we need to label the
7820 current state, and copy it back in at the start of the next block. */
7824 fprintf (asm_out_file, "\t.label_state 1\n");
7825 need_copy_state = true;
7828 fprintf (asm_out_file, "\t.restore sp\n");
7831 /* This function processes a SET pattern looking for specific patterns
7832 which result in emitting an assembly directive required for unwinding. */
7835 process_set (FILE *asm_out_file, rtx pat)
7837 rtx src = SET_SRC (pat);
7838 rtx dest = SET_DEST (pat);
7839 int src_regno, dest_regno;
7841 /* Look for the ALLOC insn. */
7842 if (GET_CODE (src) == UNSPEC_VOLATILE
7843 && XINT (src, 1) == UNSPECV_ALLOC
7844 && GET_CODE (dest) == REG)
7846 dest_regno = REGNO (dest);
7848 /* If this isn't the final destination for ar.pfs, the alloc
7849 shouldn't have been marked frame related. */
7850 if (dest_regno != current_frame_info.reg_save_ar_pfs)
7853 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
7854 ia64_dbx_register_number (dest_regno));
7858 /* Look for SP = .... */
7859 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
7861 if (GET_CODE (src) == PLUS)
7863 rtx op0 = XEXP (src, 0);
7864 rtx op1 = XEXP (src, 1);
7865 if (op0 == dest && GET_CODE (op1) == CONST_INT)
7867 if (INTVAL (op1) < 0)
7868 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
7871 process_epilogue ();
7876 else if (GET_CODE (src) == REG
7877 && REGNO (src) == HARD_FRAME_POINTER_REGNUM)
7878 process_epilogue ();
7885 /* Register move we need to look at. */
7886 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
7888 src_regno = REGNO (src);
7889 dest_regno = REGNO (dest);
7894 /* Saving return address pointer. */
7895 if (dest_regno != current_frame_info.reg_save_b0)
7897 fprintf (asm_out_file, "\t.save rp, r%d\n",
7898 ia64_dbx_register_number (dest_regno));
7902 if (dest_regno != current_frame_info.reg_save_pr)
7904 fprintf (asm_out_file, "\t.save pr, r%d\n",
7905 ia64_dbx_register_number (dest_regno));
7908 case AR_UNAT_REGNUM:
7909 if (dest_regno != current_frame_info.reg_save_ar_unat)
7911 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
7912 ia64_dbx_register_number (dest_regno));
7916 if (dest_regno != current_frame_info.reg_save_ar_lc)
7918 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
7919 ia64_dbx_register_number (dest_regno));
7922 case STACK_POINTER_REGNUM:
7923 if (dest_regno != HARD_FRAME_POINTER_REGNUM
7924 || ! frame_pointer_needed)
7926 fprintf (asm_out_file, "\t.vframe r%d\n",
7927 ia64_dbx_register_number (dest_regno));
7931 /* Everything else should indicate being stored to memory. */
7936 /* Memory store we need to look at. */
7937 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
7943 if (GET_CODE (XEXP (dest, 0)) == REG)
7945 base = XEXP (dest, 0);
7948 else if (GET_CODE (XEXP (dest, 0)) == PLUS
7949 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT)
7951 base = XEXP (XEXP (dest, 0), 0);
7952 off = INTVAL (XEXP (XEXP (dest, 0), 1));
7957 if (base == hard_frame_pointer_rtx)
7959 saveop = ".savepsp";
7962 else if (base == stack_pointer_rtx)
7967 src_regno = REGNO (src);
7971 if (current_frame_info.reg_save_b0 != 0)
7973 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
7977 if (current_frame_info.reg_save_pr != 0)
7979 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
7983 if (current_frame_info.reg_save_ar_lc != 0)
7985 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
7989 if (current_frame_info.reg_save_ar_pfs != 0)
7991 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
7994 case AR_UNAT_REGNUM:
7995 if (current_frame_info.reg_save_ar_unat != 0)
7997 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
8004 fprintf (asm_out_file, "\t.save.g 0x%x\n",
8005 1 << (src_regno - GR_REG (4)));
8013 fprintf (asm_out_file, "\t.save.b 0x%x\n",
8014 1 << (src_regno - BR_REG (1)));
8021 fprintf (asm_out_file, "\t.save.f 0x%x\n",
8022 1 << (src_regno - FR_REG (2)));
8025 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
8026 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
8027 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
8028 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
8029 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
8030 1 << (src_regno - FR_REG (12)));
8042 /* This function looks at a single insn and emits any directives
8043 required to unwind this insn. */
8045 process_for_unwind_directive (FILE *asm_out_file, rtx insn)
8047 if (flag_unwind_tables
8048 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
8052 if (GET_CODE (insn) == NOTE
8053 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
8055 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
8057 /* Restore unwind state from immediately before the epilogue. */
8058 if (need_copy_state)
8060 fprintf (asm_out_file, "\t.body\n");
8061 fprintf (asm_out_file, "\t.copy_state 1\n");
8062 need_copy_state = false;
8066 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
8069 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
8071 pat = XEXP (pat, 0);
8073 pat = PATTERN (insn);
8075 switch (GET_CODE (pat))
8078 process_set (asm_out_file, pat);
8084 int limit = XVECLEN (pat, 0);
8085 for (par_index = 0; par_index < limit; par_index++)
8087 rtx x = XVECEXP (pat, 0, par_index);
8088 if (GET_CODE (x) == SET)
8089 process_set (asm_out_file, x);
8102 ia64_init_builtins (void)
8104 tree psi_type_node = build_pointer_type (integer_type_node);
8105 tree pdi_type_node = build_pointer_type (long_integer_type_node);
8107 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
8108 tree si_ftype_psi_si_si
8109 = build_function_type_list (integer_type_node,
8110 psi_type_node, integer_type_node,
8111 integer_type_node, NULL_TREE);
8113 /* __sync_val_compare_and_swap_di */
8114 tree di_ftype_pdi_di_di
8115 = build_function_type_list (long_integer_type_node,
8116 pdi_type_node, long_integer_type_node,
8117 long_integer_type_node, NULL_TREE);
8118 /* __sync_bool_compare_and_swap_di */
8119 tree si_ftype_pdi_di_di
8120 = build_function_type_list (integer_type_node,
8121 pdi_type_node, long_integer_type_node,
8122 long_integer_type_node, NULL_TREE);
8123 /* __sync_synchronize */
8124 tree void_ftype_void
8125 = build_function_type (void_type_node, void_list_node);
8127 /* __sync_lock_test_and_set_si */
8128 tree si_ftype_psi_si
8129 = build_function_type_list (integer_type_node,
8130 psi_type_node, integer_type_node, NULL_TREE);
8132 /* __sync_lock_test_and_set_di */
8133 tree di_ftype_pdi_di
8134 = build_function_type_list (long_integer_type_node,
8135 pdi_type_node, long_integer_type_node,
8138 /* __sync_lock_release_si */
8140 = build_function_type_list (void_type_node, psi_type_node, NULL_TREE);
8142 /* __sync_lock_release_di */
8144 = build_function_type_list (void_type_node, pdi_type_node, NULL_TREE);
8149 /* The __fpreg type. */
8150 fpreg_type = make_node (REAL_TYPE);
8151 /* ??? The back end should know to load/save __fpreg variables using
8152 the ldf.fill and stf.spill instructions. */
8153 TYPE_PRECISION (fpreg_type) = 96;
8154 layout_type (fpreg_type);
8155 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
8157 /* The __float80 type. */
8158 float80_type = make_node (REAL_TYPE);
8159 TYPE_PRECISION (float80_type) = 96;
8160 layout_type (float80_type);
8161 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
8163 /* The __float128 type. */
8166 tree float128_type = make_node (REAL_TYPE);
8167 TYPE_PRECISION (float128_type) = 128;
8168 layout_type (float128_type);
8169 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
8172 /* Under HPUX, this is a synonym for "long double". */
8173 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
8176 #define def_builtin(name, type, code) \
8177 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
8179 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si,
8180 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI);
8181 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di,
8182 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI);
8183 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si,
8184 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI);
8185 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di,
8186 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI);
8188 def_builtin ("__sync_synchronize", void_ftype_void,
8189 IA64_BUILTIN_SYNCHRONIZE);
8191 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si,
8192 IA64_BUILTIN_LOCK_TEST_AND_SET_SI);
8193 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di,
8194 IA64_BUILTIN_LOCK_TEST_AND_SET_DI);
8195 def_builtin ("__sync_lock_release_si", void_ftype_psi,
8196 IA64_BUILTIN_LOCK_RELEASE_SI);
8197 def_builtin ("__sync_lock_release_di", void_ftype_pdi,
8198 IA64_BUILTIN_LOCK_RELEASE_DI);
8200 def_builtin ("__builtin_ia64_bsp",
8201 build_function_type (ptr_type_node, void_list_node),
8204 def_builtin ("__builtin_ia64_flushrs",
8205 build_function_type (void_type_node, void_list_node),
8206 IA64_BUILTIN_FLUSHRS);
8208 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si,
8209 IA64_BUILTIN_FETCH_AND_ADD_SI);
8210 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si,
8211 IA64_BUILTIN_FETCH_AND_SUB_SI);
8212 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si,
8213 IA64_BUILTIN_FETCH_AND_OR_SI);
8214 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si,
8215 IA64_BUILTIN_FETCH_AND_AND_SI);
8216 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si,
8217 IA64_BUILTIN_FETCH_AND_XOR_SI);
8218 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si,
8219 IA64_BUILTIN_FETCH_AND_NAND_SI);
8221 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si,
8222 IA64_BUILTIN_ADD_AND_FETCH_SI);
8223 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si,
8224 IA64_BUILTIN_SUB_AND_FETCH_SI);
8225 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si,
8226 IA64_BUILTIN_OR_AND_FETCH_SI);
8227 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si,
8228 IA64_BUILTIN_AND_AND_FETCH_SI);
8229 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si,
8230 IA64_BUILTIN_XOR_AND_FETCH_SI);
8231 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si,
8232 IA64_BUILTIN_NAND_AND_FETCH_SI);
8234 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di,
8235 IA64_BUILTIN_FETCH_AND_ADD_DI);
8236 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di,
8237 IA64_BUILTIN_FETCH_AND_SUB_DI);
8238 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di,
8239 IA64_BUILTIN_FETCH_AND_OR_DI);
8240 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di,
8241 IA64_BUILTIN_FETCH_AND_AND_DI);
8242 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di,
8243 IA64_BUILTIN_FETCH_AND_XOR_DI);
8244 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di,
8245 IA64_BUILTIN_FETCH_AND_NAND_DI);
8247 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di,
8248 IA64_BUILTIN_ADD_AND_FETCH_DI);
8249 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di,
8250 IA64_BUILTIN_SUB_AND_FETCH_DI);
8251 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di,
8252 IA64_BUILTIN_OR_AND_FETCH_DI);
8253 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di,
8254 IA64_BUILTIN_AND_AND_FETCH_DI);
8255 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di,
8256 IA64_BUILTIN_XOR_AND_FETCH_DI);
8257 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di,
8258 IA64_BUILTIN_NAND_AND_FETCH_DI);
8263 /* Expand fetch_and_op intrinsics. The basic code sequence is:
8271 cmpxchgsz.acq tmp = [ptr], tmp
8272 } while (tmp != ret)
8276 ia64_expand_fetch_and_op (optab binoptab, enum machine_mode mode,
8277 tree arglist, rtx target)
8279 rtx ret, label, tmp, ccv, insn, mem, value;
8282 arg0 = TREE_VALUE (arglist);
8283 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8284 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
8285 #ifdef POINTERS_EXTEND_UNSIGNED
8286 if (GET_MODE(mem) != Pmode)
8287 mem = convert_memory_address (Pmode, mem);
8289 value = expand_expr (arg1, NULL_RTX, mode, 0);
8291 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
8292 MEM_VOLATILE_P (mem) = 1;
8294 if (target && register_operand (target, mode))
8297 ret = gen_reg_rtx (mode);
8299 emit_insn (gen_mf ());
8301 /* Special case for fetchadd instructions. */
8302 if (binoptab == add_optab && fetchadd_operand (value, VOIDmode))
8305 insn = gen_fetchadd_acq_si (ret, mem, value);
8307 insn = gen_fetchadd_acq_di (ret, mem, value);
8312 tmp = gen_reg_rtx (mode);
8313 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8314 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8315 emit_move_insn (tmp, mem);
8317 label = gen_label_rtx ();
8319 emit_move_insn (ret, tmp);
8320 convert_move (ccv, tmp, /*unsignedp=*/1);
8322 /* Perform the specific operation. Special case NAND by noticing
8323 one_cmpl_optab instead. */
8324 if (binoptab == one_cmpl_optab)
8326 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
8327 binoptab = and_optab;
8329 tmp = expand_binop (mode, binoptab, tmp, value, tmp, 1, OPTAB_WIDEN);
8332 insn = gen_cmpxchg_acq_si (tmp, mem, tmp, ccv);
8334 insn = gen_cmpxchg_acq_di (tmp, mem, tmp, ccv);
8337 emit_cmp_and_jump_insns (tmp, ret, NE, 0, mode, 1, label);
8342 /* Expand op_and_fetch intrinsics. The basic code sequence is:
8349 ret = tmp <op> value;
8350 cmpxchgsz.acq tmp = [ptr], ret
8351 } while (tmp != old)
8355 ia64_expand_op_and_fetch (optab binoptab, enum machine_mode mode,
8356 tree arglist, rtx target)
8358 rtx old, label, tmp, ret, ccv, insn, mem, value;
8361 arg0 = TREE_VALUE (arglist);
8362 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8363 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
8364 #ifdef POINTERS_EXTEND_UNSIGNED
8365 if (GET_MODE(mem) != Pmode)
8366 mem = convert_memory_address (Pmode, mem);
8369 value = expand_expr (arg1, NULL_RTX, mode, 0);
8371 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
8372 MEM_VOLATILE_P (mem) = 1;
8374 if (target && ! register_operand (target, mode))
8377 emit_insn (gen_mf ());
8378 tmp = gen_reg_rtx (mode);
8379 old = gen_reg_rtx (mode);
8380 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8381 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8383 emit_move_insn (tmp, mem);
8385 label = gen_label_rtx ();
8387 emit_move_insn (old, tmp);
8388 convert_move (ccv, tmp, /*unsignedp=*/1);
8390 /* Perform the specific operation. Special case NAND by noticing
8391 one_cmpl_optab instead. */
8392 if (binoptab == one_cmpl_optab)
8394 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
8395 binoptab = and_optab;
8397 ret = expand_binop (mode, binoptab, tmp, value, target, 1, OPTAB_WIDEN);
8400 insn = gen_cmpxchg_acq_si (tmp, mem, ret, ccv);
8402 insn = gen_cmpxchg_acq_di (tmp, mem, ret, ccv);
8405 emit_cmp_and_jump_insns (tmp, old, NE, 0, mode, 1, label);
8410 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8414 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8417 For bool_ it's the same except return ret == oldval.
8421 ia64_expand_compare_and_swap (enum machine_mode rmode, enum machine_mode mode,
8422 int boolp, tree arglist, rtx target)
8424 tree arg0, arg1, arg2;
8425 rtx mem, old, new, ccv, tmp, insn;
8427 arg0 = TREE_VALUE (arglist);
8428 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8429 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
8430 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8431 old = expand_expr (arg1, NULL_RTX, mode, 0);
8432 new = expand_expr (arg2, NULL_RTX, mode, 0);
8434 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8435 MEM_VOLATILE_P (mem) = 1;
8437 if (GET_MODE (old) != mode)
8438 old = convert_to_mode (mode, old, /*unsignedp=*/1);
8439 if (GET_MODE (new) != mode)
8440 new = convert_to_mode (mode, new, /*unsignedp=*/1);
8442 if (! register_operand (old, mode))
8443 old = copy_to_mode_reg (mode, old);
8444 if (! register_operand (new, mode))
8445 new = copy_to_mode_reg (mode, new);
8447 if (! boolp && target && register_operand (target, mode))
8450 tmp = gen_reg_rtx (mode);
8452 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8453 convert_move (ccv, old, /*unsignedp=*/1);
8454 emit_insn (gen_mf ());
8456 insn = gen_cmpxchg_acq_si (tmp, mem, new, ccv);
8458 insn = gen_cmpxchg_acq_di (tmp, mem, new, ccv);
8464 target = gen_reg_rtx (rmode);
8465 return emit_store_flag_force (target, EQ, tmp, old, mode, 1, 1);
8471 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8474 ia64_expand_lock_test_and_set (enum machine_mode mode, tree arglist,
8478 rtx mem, new, ret, insn;
8480 arg0 = TREE_VALUE (arglist);
8481 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8482 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8483 new = expand_expr (arg1, NULL_RTX, mode, 0);
8485 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8486 MEM_VOLATILE_P (mem) = 1;
8487 if (! register_operand (new, mode))
8488 new = copy_to_mode_reg (mode, new);
8490 if (target && register_operand (target, mode))
8493 ret = gen_reg_rtx (mode);
8496 insn = gen_xchgsi (ret, mem, new);
8498 insn = gen_xchgdi (ret, mem, new);
8504 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8507 ia64_expand_lock_release (enum machine_mode mode, tree arglist,
8508 rtx target ATTRIBUTE_UNUSED)
8513 arg0 = TREE_VALUE (arglist);
8514 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8516 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8517 MEM_VOLATILE_P (mem) = 1;
8519 emit_move_insn (mem, const0_rtx);
8525 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8526 enum machine_mode mode ATTRIBUTE_UNUSED,
8527 int ignore ATTRIBUTE_UNUSED)
8529 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8530 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8531 tree arglist = TREE_OPERAND (exp, 1);
8532 enum machine_mode rmode = VOIDmode;
8536 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8537 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8542 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8543 case IA64_BUILTIN_LOCK_RELEASE_SI:
8544 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8545 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8546 case IA64_BUILTIN_FETCH_AND_OR_SI:
8547 case IA64_BUILTIN_FETCH_AND_AND_SI:
8548 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8549 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8550 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8551 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8552 case IA64_BUILTIN_OR_AND_FETCH_SI:
8553 case IA64_BUILTIN_AND_AND_FETCH_SI:
8554 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8555 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8559 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8564 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8569 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8570 case IA64_BUILTIN_LOCK_RELEASE_DI:
8571 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8572 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8573 case IA64_BUILTIN_FETCH_AND_OR_DI:
8574 case IA64_BUILTIN_FETCH_AND_AND_DI:
8575 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8576 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8577 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8578 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8579 case IA64_BUILTIN_OR_AND_FETCH_DI:
8580 case IA64_BUILTIN_AND_AND_FETCH_DI:
8581 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8582 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8592 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8593 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8594 return ia64_expand_compare_and_swap (rmode, mode, 1, arglist,
8597 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8598 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8599 return ia64_expand_compare_and_swap (rmode, mode, 0, arglist,
8602 case IA64_BUILTIN_SYNCHRONIZE:
8603 emit_insn (gen_mf ());
8606 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8607 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8608 return ia64_expand_lock_test_and_set (mode, arglist, target);
8610 case IA64_BUILTIN_LOCK_RELEASE_SI:
8611 case IA64_BUILTIN_LOCK_RELEASE_DI:
8612 return ia64_expand_lock_release (mode, arglist, target);
8614 case IA64_BUILTIN_BSP:
8615 if (! target || ! register_operand (target, DImode))
8616 target = gen_reg_rtx (DImode);
8617 emit_insn (gen_bsp_value (target));
8618 #ifdef POINTERS_EXTEND_UNSIGNED
8619 target = convert_memory_address (ptr_mode, target);
8623 case IA64_BUILTIN_FLUSHRS:
8624 emit_insn (gen_flushrs ());
8627 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8628 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8629 return ia64_expand_fetch_and_op (add_optab, mode, arglist, target);
8631 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8632 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8633 return ia64_expand_fetch_and_op (sub_optab, mode, arglist, target);
8635 case IA64_BUILTIN_FETCH_AND_OR_SI:
8636 case IA64_BUILTIN_FETCH_AND_OR_DI:
8637 return ia64_expand_fetch_and_op (ior_optab, mode, arglist, target);
8639 case IA64_BUILTIN_FETCH_AND_AND_SI:
8640 case IA64_BUILTIN_FETCH_AND_AND_DI:
8641 return ia64_expand_fetch_and_op (and_optab, mode, arglist, target);
8643 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8644 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8645 return ia64_expand_fetch_and_op (xor_optab, mode, arglist, target);
8647 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8648 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8649 return ia64_expand_fetch_and_op (one_cmpl_optab, mode, arglist, target);
8651 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8652 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8653 return ia64_expand_op_and_fetch (add_optab, mode, arglist, target);
8655 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8656 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8657 return ia64_expand_op_and_fetch (sub_optab, mode, arglist, target);
8659 case IA64_BUILTIN_OR_AND_FETCH_SI:
8660 case IA64_BUILTIN_OR_AND_FETCH_DI:
8661 return ia64_expand_op_and_fetch (ior_optab, mode, arglist, target);
8663 case IA64_BUILTIN_AND_AND_FETCH_SI:
8664 case IA64_BUILTIN_AND_AND_FETCH_DI:
8665 return ia64_expand_op_and_fetch (and_optab, mode, arglist, target);
8667 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8668 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8669 return ia64_expand_op_and_fetch (xor_optab, mode, arglist, target);
8671 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8672 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8673 return ia64_expand_op_and_fetch (one_cmpl_optab, mode, arglist, target);
8682 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8683 most significant bits of the stack slot. */
8686 ia64_hpux_function_arg_padding (enum machine_mode mode, tree type)
8688 /* Exception to normal case for structures/unions/etc. */
8690 if (type && AGGREGATE_TYPE_P (type)
8691 && int_size_in_bytes (type) < UNITS_PER_WORD)
8694 /* Fall back to the default. */
8695 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
8698 /* Linked list of all external functions that are to be emitted by GCC.
8699 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8700 order to avoid putting out names that are never really used. */
8702 struct extern_func_list GTY(())
8704 struct extern_func_list *next;
8708 static GTY(()) struct extern_func_list *extern_func_head;
8711 ia64_hpux_add_extern_decl (tree decl)
8713 struct extern_func_list *p = ggc_alloc (sizeof (struct extern_func_list));
8716 p->next = extern_func_head;
8717 extern_func_head = p;
8720 /* Print out the list of used global functions. */
8723 ia64_hpux_file_end (void)
8725 struct extern_func_list *p;
8727 for (p = extern_func_head; p; p = p->next)
8729 tree decl = p->decl;
8730 tree id = DECL_NAME (decl);
8735 if (!TREE_ASM_WRITTEN (decl) && TREE_SYMBOL_REFERENCED (id))
8737 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8739 TREE_ASM_WRITTEN (decl) = 1;
8740 (*targetm.asm_out.globalize_label) (asm_out_file, name);
8741 fputs (TYPE_ASM_OP, asm_out_file);
8742 assemble_name (asm_out_file, name);
8743 fprintf (asm_out_file, "," TYPE_OPERAND_FMT "\n", "function");
8747 extern_func_head = 0;
8750 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8753 ia64_hpux_init_libfuncs (void)
8755 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
8756 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
8757 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
8758 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
8759 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
8760 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
8761 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
8762 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
8764 /* ia64_expand_compare uses this. */
8765 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
8767 /* These should never be used. */
8768 set_optab_libfunc (eq_optab, TFmode, 0);
8769 set_optab_libfunc (ne_optab, TFmode, 0);
8770 set_optab_libfunc (gt_optab, TFmode, 0);
8771 set_optab_libfunc (ge_optab, TFmode, 0);
8772 set_optab_libfunc (lt_optab, TFmode, 0);
8773 set_optab_libfunc (le_optab, TFmode, 0);
8775 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
8776 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
8777 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
8778 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
8779 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
8780 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
8782 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
8783 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
8784 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
8785 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
8787 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
8788 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
8791 /* Rename the division and modulus functions in VMS. */
8794 ia64_vms_init_libfuncs (void)
8796 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
8797 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
8798 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
8799 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
8800 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
8801 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
8802 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
8803 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
8806 /* Switch to the section to which we should output X. The only thing
8807 special we do here is to honor small data. */
8810 ia64_select_rtx_section (enum machine_mode mode, rtx x,
8811 unsigned HOST_WIDE_INT align)
8813 if (GET_MODE_SIZE (mode) > 0
8814 && GET_MODE_SIZE (mode) <= ia64_section_threshold)
8817 default_elf_select_rtx_section (mode, x, align);
8820 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8821 Pretend flag_pic is always set. */
8824 ia64_rwreloc_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align)
8826 default_elf_select_section_1 (exp, reloc, align, true);
8830 ia64_rwreloc_unique_section (tree decl, int reloc)
8832 default_unique_section_1 (decl, reloc, true);
8836 ia64_rwreloc_select_rtx_section (enum machine_mode mode, rtx x,
8837 unsigned HOST_WIDE_INT align)
8839 int save_pic = flag_pic;
8841 ia64_select_rtx_section (mode, x, align);
8842 flag_pic = save_pic;
8846 ia64_rwreloc_section_type_flags (tree decl, const char *name, int reloc)
8848 return default_section_type_flags_1 (decl, name, reloc, true);
8851 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
8852 structure type and that the address of that type should be passed
8853 in out0, rather than in r8. */
8856 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
8858 tree ret_type = TREE_TYPE (fntype);
8860 /* The Itanium C++ ABI requires that out0, rather than r8, be used
8861 as the structure return address parameter, if the return value
8862 type has a non-trivial copy constructor or destructor. It is not
8863 clear if this same convention should be used for other
8864 programming languages. Until G++ 3.4, we incorrectly used r8 for
8865 these return values. */
8866 return (abi_version_at_least (2)
8868 && TYPE_MODE (ret_type) == BLKmode
8869 && TREE_ADDRESSABLE (ret_type)
8870 && strcmp (lang_hooks.name, "GNU C++") == 0);
8873 /* Output the assembler code for a thunk function. THUNK_DECL is the
8874 declaration for the thunk function itself, FUNCTION is the decl for
8875 the target function. DELTA is an immediate constant offset to be
8876 added to THIS. If VCALL_OFFSET is nonzero, the word at
8877 *(*this + vcall_offset) should be added to THIS. */
8880 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8881 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8884 rtx this, insn, funexp;
8885 unsigned int this_parmno;
8886 unsigned int this_regno;
8888 reload_completed = 1;
8889 epilogue_completed = 1;
8892 /* Set things up as ia64_expand_prologue might. */
8893 last_scratch_gr_reg = 15;
8895 memset (¤t_frame_info, 0, sizeof (current_frame_info));
8896 current_frame_info.spill_cfa_off = -16;
8897 current_frame_info.n_input_regs = 1;
8898 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
8900 /* Mark the end of the (empty) prologue. */
8901 emit_note (NOTE_INSN_PROLOGUE_END);
8903 /* Figure out whether "this" will be the first parameter (the
8904 typical case) or the second parameter (as happens when the
8905 virtual function returns certain class objects). */
8907 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
8909 this_regno = IN_REG (this_parmno);
8910 if (!TARGET_REG_NAMES)
8911 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
8913 this = gen_rtx_REG (Pmode, this_regno);
8916 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
8917 REG_POINTER (tmp) = 1;
8918 if (delta && CONST_OK_FOR_I (delta))
8920 emit_insn (gen_ptr_extend_plus_imm (this, tmp, GEN_INT (delta)));
8924 emit_insn (gen_ptr_extend (this, tmp));
8927 /* Apply the constant offset, if required. */
8930 rtx delta_rtx = GEN_INT (delta);
8932 if (!CONST_OK_FOR_I (delta))
8934 rtx tmp = gen_rtx_REG (Pmode, 2);
8935 emit_move_insn (tmp, delta_rtx);
8938 emit_insn (gen_adddi3 (this, this, delta_rtx));
8941 /* Apply the offset from the vtable, if required. */
8944 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8945 rtx tmp = gen_rtx_REG (Pmode, 2);
8949 rtx t = gen_rtx_REG (ptr_mode, 2);
8950 REG_POINTER (t) = 1;
8951 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this));
8952 if (CONST_OK_FOR_I (vcall_offset))
8954 emit_insn (gen_ptr_extend_plus_imm (tmp, t,
8959 emit_insn (gen_ptr_extend (tmp, t));
8962 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
8966 if (!CONST_OK_FOR_J (vcall_offset))
8968 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
8969 emit_move_insn (tmp2, vcall_offset_rtx);
8970 vcall_offset_rtx = tmp2;
8972 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
8976 emit_move_insn (gen_rtx_REG (ptr_mode, 2),
8977 gen_rtx_MEM (ptr_mode, tmp));
8979 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
8981 emit_insn (gen_adddi3 (this, this, tmp));
8984 /* Generate a tail call to the target function. */
8985 if (! TREE_USED (function))
8987 assemble_external (function);
8988 TREE_USED (function) = 1;
8990 funexp = XEXP (DECL_RTL (function), 0);
8991 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8992 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
8993 insn = get_last_insn ();
8994 SIBLING_CALL_P (insn) = 1;
8996 /* Code generation for calls relies on splitting. */
8997 reload_completed = 1;
8998 epilogue_completed = 1;
8999 try_split (PATTERN (insn), insn, 0);
9003 /* Run just enough of rest_of_compilation to get the insns emitted.
9004 There's not really enough bulk here to make other passes such as
9005 instruction scheduling worth while. Note that use_thunk calls
9006 assemble_start_function and assemble_end_function. */
9008 insn_locators_initialize ();
9009 emit_all_insn_group_barriers (NULL);
9010 insn = get_insns ();
9011 shorten_branches (insn);
9012 final_start_function (insn, file, 1);
9013 final (insn, file, 1, 0);
9014 final_end_function ();
9016 reload_completed = 0;
9017 epilogue_completed = 0;
9021 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9024 ia64_struct_value_rtx (tree fntype,
9025 int incoming ATTRIBUTE_UNUSED)
9027 if (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))
9029 return gen_rtx_REG (Pmode, GR_REG (8));
9032 #include "gt-ia64.h"