1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
55 /* This is used for communication between ASM_OUTPUT_LABEL and
56 ASM_OUTPUT_LABELREF. */
57 int ia64_asm_output_label = 0;
59 /* Define the information needed to generate branch and scc insns. This is
60 stored from the compare operation. */
61 struct rtx_def * ia64_compare_op0;
62 struct rtx_def * ia64_compare_op1;
64 /* Register names for ia64_expand_prologue. */
65 static const char * const ia64_reg_numbers[96] =
66 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
67 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
68 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
69 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
70 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
71 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
72 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
73 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
74 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
75 "r104","r105","r106","r107","r108","r109","r110","r111",
76 "r112","r113","r114","r115","r116","r117","r118","r119",
77 "r120","r121","r122","r123","r124","r125","r126","r127"};
79 /* ??? These strings could be shared with REGISTER_NAMES. */
80 static const char * const ia64_input_reg_names[8] =
81 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
83 /* ??? These strings could be shared with REGISTER_NAMES. */
84 static const char * const ia64_local_reg_names[80] =
85 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
86 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
87 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
88 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
89 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
90 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
91 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
92 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
93 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
94 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
96 /* ??? These strings could be shared with REGISTER_NAMES. */
97 static const char * const ia64_output_reg_names[8] =
98 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
100 /* String used with the -mfixed-range= option. */
101 const char *ia64_fixed_range_string;
103 /* Determines whether we use adds, addl, or movl to generate our
104 TLS immediate offsets. */
105 int ia64_tls_size = 22;
107 /* String used with the -mtls-size= option. */
108 const char *ia64_tls_size_string;
110 /* Which cpu are we scheduling for. */
111 enum processor_type ia64_tune;
113 /* String used with the -tune= option. */
114 const char *ia64_tune_string;
116 /* Determines whether we run our final scheduling pass or not. We always
117 avoid the normal second scheduling pass. */
118 static int ia64_flag_schedule_insns2;
120 /* Determines whether we run variable tracking in machine dependent
122 static int ia64_flag_var_tracking;
124 /* Variables which are this size or smaller are put in the sdata/sbss
127 unsigned int ia64_section_threshold;
129 /* The following variable is used by the DFA insn scheduler. The value is
130 TRUE if we do insn bundling instead of insn scheduling. */
133 /* Structure to be filled in by ia64_compute_frame_size with register
134 save masks and offsets for the current function. */
136 struct ia64_frame_info
138 HOST_WIDE_INT total_size; /* size of the stack frame, not including
139 the caller's scratch area. */
140 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
141 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
142 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
143 HARD_REG_SET mask; /* mask of saved registers. */
144 unsigned int gr_used_mask; /* mask of registers in use as gr spill
145 registers or long-term scratches. */
146 int n_spilled; /* number of spilled registers. */
147 int reg_fp; /* register for fp. */
148 int reg_save_b0; /* save register for b0. */
149 int reg_save_pr; /* save register for prs. */
150 int reg_save_ar_pfs; /* save register for ar.pfs. */
151 int reg_save_ar_unat; /* save register for ar.unat. */
152 int reg_save_ar_lc; /* save register for ar.lc. */
153 int reg_save_gp; /* save register for gp. */
154 int n_input_regs; /* number of input registers used. */
155 int n_local_regs; /* number of local registers used. */
156 int n_output_regs; /* number of output registers used. */
157 int n_rotate_regs; /* number of rotating registers used. */
159 char need_regstk; /* true if a .regstk directive needed. */
160 char initialized; /* true if the data is finalized. */
163 /* Current frame information calculated by ia64_compute_frame_size. */
164 static struct ia64_frame_info current_frame_info;
166 static int ia64_use_dfa_pipeline_interface (void);
167 static int ia64_first_cycle_multipass_dfa_lookahead (void);
168 static void ia64_dependencies_evaluation_hook (rtx, rtx);
169 static void ia64_init_dfa_pre_cycle_insn (void);
170 static rtx ia64_dfa_pre_cycle_insn (void);
171 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
172 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
173 static rtx gen_tls_get_addr (void);
174 static rtx gen_thread_pointer (void);
175 static rtx ia64_expand_tls_address (enum tls_model, rtx, rtx);
176 static int find_gr_spill (int);
177 static int next_scratch_gr_reg (void);
178 static void mark_reg_gr_used_mask (rtx, void *);
179 static void ia64_compute_frame_size (HOST_WIDE_INT);
180 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
181 static void finish_spill_pointers (void);
182 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
183 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
184 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
185 static rtx gen_movdi_x (rtx, rtx, rtx);
186 static rtx gen_fr_spill_x (rtx, rtx, rtx);
187 static rtx gen_fr_restore_x (rtx, rtx, rtx);
189 static enum machine_mode hfa_element_mode (tree, int);
190 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
192 static bool ia64_function_ok_for_sibcall (tree, tree);
193 static bool ia64_return_in_memory (tree, tree);
194 static bool ia64_rtx_costs (rtx, int, int, int *);
195 static void fix_range (const char *);
196 static struct machine_function * ia64_init_machine_status (void);
197 static void emit_insn_group_barriers (FILE *);
198 static void emit_all_insn_group_barriers (FILE *);
199 static void final_emit_insn_group_barriers (FILE *);
200 static void emit_predicate_relation_info (void);
201 static void ia64_reorg (void);
202 static bool ia64_in_small_data_p (tree);
203 static void process_epilogue (void);
204 static int process_set (FILE *, rtx);
206 static rtx ia64_expand_fetch_and_op (optab, enum machine_mode, tree, rtx);
207 static rtx ia64_expand_op_and_fetch (optab, enum machine_mode, tree, rtx);
208 static rtx ia64_expand_compare_and_swap (enum machine_mode, enum machine_mode,
210 static rtx ia64_expand_lock_test_and_set (enum machine_mode, tree, rtx);
211 static rtx ia64_expand_lock_release (enum machine_mode, tree, rtx);
212 static bool ia64_assemble_integer (rtx, unsigned int, int);
213 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
214 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
215 static void ia64_output_function_end_prologue (FILE *);
217 static int ia64_issue_rate (void);
218 static int ia64_adjust_cost (rtx, rtx, rtx, int);
219 static void ia64_sched_init (FILE *, int, int);
220 static void ia64_sched_finish (FILE *, int);
221 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
222 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
223 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
224 static int ia64_variable_issue (FILE *, int, rtx, int);
226 static struct bundle_state *get_free_bundle_state (void);
227 static void free_bundle_state (struct bundle_state *);
228 static void initiate_bundle_states (void);
229 static void finish_bundle_states (void);
230 static unsigned bundle_state_hash (const void *);
231 static int bundle_state_eq_p (const void *, const void *);
232 static int insert_bundle_state (struct bundle_state *);
233 static void initiate_bundle_state_table (void);
234 static void finish_bundle_state_table (void);
235 static int try_issue_nops (struct bundle_state *, int);
236 static int try_issue_insn (struct bundle_state *, rtx);
237 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
238 static int get_max_pos (state_t);
239 static int get_template (state_t, int);
241 static rtx get_next_important_insn (rtx, rtx);
242 static void bundling (FILE *, int, rtx, rtx);
244 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
245 HOST_WIDE_INT, tree);
246 static void ia64_file_start (void);
248 static void ia64_select_rtx_section (enum machine_mode, rtx,
249 unsigned HOST_WIDE_INT);
250 static void ia64_rwreloc_select_section (tree, int, unsigned HOST_WIDE_INT)
252 static void ia64_rwreloc_unique_section (tree, int)
254 static void ia64_rwreloc_select_rtx_section (enum machine_mode, rtx,
255 unsigned HOST_WIDE_INT)
257 static unsigned int ia64_rwreloc_section_type_flags (tree, const char *, int)
260 static void ia64_hpux_add_extern_decl (const char *name)
262 static void ia64_hpux_file_end (void)
264 static void ia64_hpux_init_libfuncs (void)
266 static void ia64_vms_init_libfuncs (void)
269 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
270 static void ia64_encode_section_info (tree, rtx, int);
271 static rtx ia64_struct_value_rtx (tree, int);
274 /* Table of valid machine attributes. */
275 static const struct attribute_spec ia64_attribute_table[] =
277 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
278 { "syscall_linkage", 0, 0, false, true, true, NULL },
279 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
280 { NULL, 0, 0, false, false, false, NULL }
283 /* Initialize the GCC target structure. */
284 #undef TARGET_ATTRIBUTE_TABLE
285 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
287 #undef TARGET_INIT_BUILTINS
288 #define TARGET_INIT_BUILTINS ia64_init_builtins
290 #undef TARGET_EXPAND_BUILTIN
291 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
293 #undef TARGET_ASM_BYTE_OP
294 #define TARGET_ASM_BYTE_OP "\tdata1\t"
295 #undef TARGET_ASM_ALIGNED_HI_OP
296 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
297 #undef TARGET_ASM_ALIGNED_SI_OP
298 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
299 #undef TARGET_ASM_ALIGNED_DI_OP
300 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
301 #undef TARGET_ASM_UNALIGNED_HI_OP
302 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
303 #undef TARGET_ASM_UNALIGNED_SI_OP
304 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
305 #undef TARGET_ASM_UNALIGNED_DI_OP
306 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
307 #undef TARGET_ASM_INTEGER
308 #define TARGET_ASM_INTEGER ia64_assemble_integer
310 #undef TARGET_ASM_FUNCTION_PROLOGUE
311 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
312 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
313 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
314 #undef TARGET_ASM_FUNCTION_EPILOGUE
315 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
317 #undef TARGET_IN_SMALL_DATA_P
318 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
320 #undef TARGET_SCHED_ADJUST_COST
321 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
322 #undef TARGET_SCHED_ISSUE_RATE
323 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
324 #undef TARGET_SCHED_VARIABLE_ISSUE
325 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
326 #undef TARGET_SCHED_INIT
327 #define TARGET_SCHED_INIT ia64_sched_init
328 #undef TARGET_SCHED_FINISH
329 #define TARGET_SCHED_FINISH ia64_sched_finish
330 #undef TARGET_SCHED_REORDER
331 #define TARGET_SCHED_REORDER ia64_sched_reorder
332 #undef TARGET_SCHED_REORDER2
333 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
335 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
336 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
338 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
339 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
341 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
342 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
344 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
345 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
346 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
347 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
349 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
350 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
351 ia64_first_cycle_multipass_dfa_lookahead_guard
353 #undef TARGET_SCHED_DFA_NEW_CYCLE
354 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
356 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
357 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
359 #undef TARGET_ASM_OUTPUT_MI_THUNK
360 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
361 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
362 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
364 #undef TARGET_ASM_FILE_START
365 #define TARGET_ASM_FILE_START ia64_file_start
367 #undef TARGET_RTX_COSTS
368 #define TARGET_RTX_COSTS ia64_rtx_costs
369 #undef TARGET_ADDRESS_COST
370 #define TARGET_ADDRESS_COST hook_int_rtx_0
372 #undef TARGET_MACHINE_DEPENDENT_REORG
373 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
375 #undef TARGET_ENCODE_SECTION_INFO
376 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
378 /* ??? ABI doesn't allow us to define this. */
380 #undef TARGET_PROMOTE_FUNCTION_ARGS
381 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
384 /* ??? ABI doesn't allow us to define this. */
386 #undef TARGET_PROMOTE_FUNCTION_RETURN
387 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
390 /* ??? Investigate. */
392 #undef TARGET_PROMOTE_PROTOTYPES
393 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
396 #undef TARGET_STRUCT_VALUE_RTX
397 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
398 #undef TARGET_RETURN_IN_MEMORY
399 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
401 #undef TARGET_SETUP_INCOMING_VARARGS
402 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
403 #undef TARGET_STRICT_ARGUMENT_NAMING
404 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
406 struct gcc_target targetm = TARGET_INITIALIZER;
408 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
411 call_operand (rtx op, enum machine_mode mode)
413 if (mode != GET_MODE (op) && mode != VOIDmode)
416 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG
417 || (GET_CODE (op) == SUBREG && GET_CODE (XEXP (op, 0)) == REG));
420 /* Return 1 if OP refers to a symbol in the sdata section. */
423 sdata_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
425 switch (GET_CODE (op))
428 if (GET_CODE (XEXP (op, 0)) != PLUS
429 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF)
431 op = XEXP (XEXP (op, 0), 0);
435 if (CONSTANT_POOL_ADDRESS_P (op))
436 return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold;
438 return SYMBOL_REF_LOCAL_P (op) && SYMBOL_REF_SMALL_P (op);
448 small_addr_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
450 return SYMBOL_REF_SMALL_ADDR_P (op);
453 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
456 got_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
458 switch (GET_CODE (op))
462 if (GET_CODE (op) != PLUS)
464 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
467 if (GET_CODE (op) != CONST_INT)
472 /* Ok if we're not using GOT entries at all. */
473 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
476 /* "Ok" while emitting rtl, since otherwise we won't be provided
477 with the entire offset during emission, which makes it very
478 hard to split the offset into high and low parts. */
479 if (rtx_equal_function_value_matters)
482 /* Force the low 14 bits of the constant to zero so that we do not
483 use up so many GOT entries. */
484 return (INTVAL (op) & 0x3fff) == 0;
487 if (SYMBOL_REF_SMALL_ADDR_P (op))
498 /* Return 1 if OP refers to a symbol. */
501 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
503 switch (GET_CODE (op))
516 /* Return tls_model if OP refers to a TLS symbol. */
519 tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
521 if (GET_CODE (op) != SYMBOL_REF)
523 return SYMBOL_REF_TLS_MODEL (op);
527 /* Return 1 if OP refers to a function. */
530 function_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
532 if (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (op))
538 /* Return 1 if OP is setjmp or a similar function. */
540 /* ??? This is an unsatisfying solution. Should rethink. */
543 setjmp_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
548 if (GET_CODE (op) != SYMBOL_REF)
553 /* The following code is borrowed from special_function_p in calls.c. */
555 /* Disregard prefix _, __ or __x. */
558 if (name[1] == '_' && name[2] == 'x')
560 else if (name[1] == '_')
570 && (! strcmp (name, "setjmp")
571 || ! strcmp (name, "setjmp_syscall")))
573 && ! strcmp (name, "sigsetjmp"))
575 && ! strcmp (name, "savectx")));
577 else if ((name[0] == 'q' && name[1] == 's'
578 && ! strcmp (name, "qsetjmp"))
579 || (name[0] == 'v' && name[1] == 'f'
580 && ! strcmp (name, "vfork")))
586 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
589 move_operand (rtx op, enum machine_mode mode)
591 return general_operand (op, mode) && !tls_symbolic_operand (op, mode);
594 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
597 gr_register_operand (rtx op, enum machine_mode mode)
599 if (! register_operand (op, mode))
601 if (GET_CODE (op) == SUBREG)
602 op = SUBREG_REG (op);
603 if (GET_CODE (op) == REG)
605 unsigned int regno = REGNO (op);
606 if (regno < FIRST_PSEUDO_REGISTER)
607 return GENERAL_REGNO_P (regno);
612 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
615 fr_register_operand (rtx op, enum machine_mode mode)
617 if (! register_operand (op, mode))
619 if (GET_CODE (op) == SUBREG)
620 op = SUBREG_REG (op);
621 if (GET_CODE (op) == REG)
623 unsigned int regno = REGNO (op);
624 if (regno < FIRST_PSEUDO_REGISTER)
625 return FR_REGNO_P (regno);
630 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
633 grfr_register_operand (rtx op, enum machine_mode mode)
635 if (! register_operand (op, mode))
637 if (GET_CODE (op) == SUBREG)
638 op = SUBREG_REG (op);
639 if (GET_CODE (op) == REG)
641 unsigned int regno = REGNO (op);
642 if (regno < FIRST_PSEUDO_REGISTER)
643 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
648 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
651 gr_nonimmediate_operand (rtx op, enum machine_mode mode)
653 if (! nonimmediate_operand (op, mode))
655 if (GET_CODE (op) == SUBREG)
656 op = SUBREG_REG (op);
657 if (GET_CODE (op) == REG)
659 unsigned int regno = REGNO (op);
660 if (regno < FIRST_PSEUDO_REGISTER)
661 return GENERAL_REGNO_P (regno);
666 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
669 fr_nonimmediate_operand (rtx op, enum machine_mode mode)
671 if (! nonimmediate_operand (op, mode))
673 if (GET_CODE (op) == SUBREG)
674 op = SUBREG_REG (op);
675 if (GET_CODE (op) == REG)
677 unsigned int regno = REGNO (op);
678 if (regno < FIRST_PSEUDO_REGISTER)
679 return FR_REGNO_P (regno);
684 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
687 grfr_nonimmediate_operand (rtx op, enum machine_mode mode)
689 if (! nonimmediate_operand (op, mode))
691 if (GET_CODE (op) == SUBREG)
692 op = SUBREG_REG (op);
693 if (GET_CODE (op) == REG)
695 unsigned int regno = REGNO (op);
696 if (regno < FIRST_PSEUDO_REGISTER)
697 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
702 /* Return 1 if OP is a GR register operand, or zero. */
705 gr_reg_or_0_operand (rtx op, enum machine_mode mode)
707 return (op == const0_rtx || gr_register_operand (op, mode));
710 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
713 gr_reg_or_5bit_operand (rtx op, enum machine_mode mode)
715 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 32)
716 || GET_CODE (op) == CONSTANT_P_RTX
717 || gr_register_operand (op, mode));
720 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
723 gr_reg_or_6bit_operand (rtx op, enum machine_mode mode)
725 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
726 || GET_CODE (op) == CONSTANT_P_RTX
727 || gr_register_operand (op, mode));
730 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
733 gr_reg_or_8bit_operand (rtx op, enum machine_mode mode)
735 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
736 || GET_CODE (op) == CONSTANT_P_RTX
737 || gr_register_operand (op, mode));
740 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
743 grfr_reg_or_8bit_operand (rtx op, enum machine_mode mode)
745 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
746 || GET_CODE (op) == CONSTANT_P_RTX
747 || grfr_register_operand (op, mode));
750 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
754 gr_reg_or_8bit_adjusted_operand (rtx op, enum machine_mode mode)
756 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
757 || GET_CODE (op) == CONSTANT_P_RTX
758 || gr_register_operand (op, mode));
761 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
762 immediate and an 8 bit adjusted immediate operand. This is necessary
763 because when we emit a compare, we don't know what the condition will be,
764 so we need the union of the immediates accepted by GT and LT. */
767 gr_reg_or_8bit_and_adjusted_operand (rtx op, enum machine_mode mode)
769 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))
770 && CONST_OK_FOR_L (INTVAL (op)))
771 || GET_CODE (op) == CONSTANT_P_RTX
772 || gr_register_operand (op, mode));
775 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
778 gr_reg_or_14bit_operand (rtx op, enum machine_mode mode)
780 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
781 || GET_CODE (op) == CONSTANT_P_RTX
782 || gr_register_operand (op, mode));
785 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
788 gr_reg_or_22bit_operand (rtx op, enum machine_mode mode)
790 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
791 || GET_CODE (op) == CONSTANT_P_RTX
792 || gr_register_operand (op, mode));
795 /* Return 1 if OP is a 6 bit immediate operand. */
798 shift_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
800 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
801 || GET_CODE (op) == CONSTANT_P_RTX);
804 /* Return 1 if OP is a 5 bit immediate operand. */
807 shift_32bit_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
809 return ((GET_CODE (op) == CONST_INT
810 && (INTVAL (op) >= 0 && INTVAL (op) < 32))
811 || GET_CODE (op) == CONSTANT_P_RTX);
814 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
817 shladd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
819 return (GET_CODE (op) == CONST_INT
820 && (INTVAL (op) == 2 || INTVAL (op) == 4
821 || INTVAL (op) == 8 || INTVAL (op) == 16));
824 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
827 fetchadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
829 return (GET_CODE (op) == CONST_INT
830 && (INTVAL (op) == -16 || INTVAL (op) == -8 ||
831 INTVAL (op) == -4 || INTVAL (op) == -1 ||
832 INTVAL (op) == 1 || INTVAL (op) == 4 ||
833 INTVAL (op) == 8 || INTVAL (op) == 16));
836 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
839 fr_reg_or_fp01_operand (rtx op, enum machine_mode mode)
841 return ((GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (op))
842 || fr_register_operand (op, mode));
845 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
846 POST_MODIFY with a REG as displacement. */
849 destination_operand (rtx op, enum machine_mode mode)
851 if (! nonimmediate_operand (op, mode))
853 if (GET_CODE (op) == MEM
854 && GET_CODE (XEXP (op, 0)) == POST_MODIFY
855 && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) == REG)
860 /* Like memory_operand, but don't allow post-increments. */
863 not_postinc_memory_operand (rtx op, enum machine_mode mode)
865 return (memory_operand (op, mode)
866 && GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
869 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
870 signed immediate operand. */
873 normal_comparison_operator (register rtx op, enum machine_mode mode)
875 enum rtx_code code = GET_CODE (op);
876 return ((mode == VOIDmode || GET_MODE (op) == mode)
877 && (code == EQ || code == NE
878 || code == GT || code == LE || code == GTU || code == LEU));
881 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
882 signed immediate operand. */
885 adjusted_comparison_operator (register rtx op, enum machine_mode mode)
887 enum rtx_code code = GET_CODE (op);
888 return ((mode == VOIDmode || GET_MODE (op) == mode)
889 && (code == LT || code == GE || code == LTU || code == GEU));
892 /* Return 1 if this is a signed inequality operator. */
895 signed_inequality_operator (register rtx op, enum machine_mode mode)
897 enum rtx_code code = GET_CODE (op);
898 return ((mode == VOIDmode || GET_MODE (op) == mode)
899 && (code == GE || code == GT
900 || code == LE || code == LT));
903 /* Return 1 if this operator is valid for predication. */
906 predicate_operator (register rtx op, enum machine_mode mode)
908 enum rtx_code code = GET_CODE (op);
909 return ((GET_MODE (op) == mode || mode == VOIDmode)
910 && (code == EQ || code == NE));
913 /* Return 1 if this operator can be used in a conditional operation. */
916 condop_operator (register rtx op, enum machine_mode mode)
918 enum rtx_code code = GET_CODE (op);
919 return ((GET_MODE (op) == mode || mode == VOIDmode)
920 && (code == PLUS || code == MINUS || code == AND
921 || code == IOR || code == XOR));
924 /* Return 1 if this is the ar.lc register. */
927 ar_lc_reg_operand (register rtx op, enum machine_mode mode)
929 return (GET_MODE (op) == DImode
930 && (mode == DImode || mode == VOIDmode)
931 && GET_CODE (op) == REG
932 && REGNO (op) == AR_LC_REGNUM);
935 /* Return 1 if this is the ar.ccv register. */
938 ar_ccv_reg_operand (register rtx op, enum machine_mode mode)
940 return ((GET_MODE (op) == mode || mode == VOIDmode)
941 && GET_CODE (op) == REG
942 && REGNO (op) == AR_CCV_REGNUM);
945 /* Return 1 if this is the ar.pfs register. */
948 ar_pfs_reg_operand (register rtx op, enum machine_mode mode)
950 return ((GET_MODE (op) == mode || mode == VOIDmode)
951 && GET_CODE (op) == REG
952 && REGNO (op) == AR_PFS_REGNUM);
955 /* Like general_operand, but don't allow (mem (addressof)). */
958 general_xfmode_operand (rtx op, enum machine_mode mode)
960 if (! general_operand (op, mode))
962 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
970 destination_xfmode_operand (rtx op, enum machine_mode mode)
972 if (! destination_operand (op, mode))
974 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
982 xfreg_or_fp01_operand (rtx op, enum machine_mode mode)
984 if (GET_CODE (op) == SUBREG)
986 return fr_reg_or_fp01_operand (op, mode);
989 /* Return 1 if OP is valid as a base register in a reg + offset address. */
992 basereg_operand (rtx op, enum machine_mode mode)
994 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
995 checks from pa.c basereg_operand as well? Seems to be OK without them
998 return (register_operand (op, mode) &&
999 REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
1004 ADDR_AREA_NORMAL, /* normal address area */
1005 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
1009 static GTY(()) tree small_ident1;
1010 static GTY(()) tree small_ident2;
1015 if (small_ident1 == 0)
1017 small_ident1 = get_identifier ("small");
1018 small_ident2 = get_identifier ("__small__");
1022 /* Retrieve the address area that has been chosen for the given decl. */
1024 static ia64_addr_area
1025 ia64_get_addr_area (tree decl)
1029 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
1035 id = TREE_VALUE (TREE_VALUE (model_attr));
1036 if (id == small_ident1 || id == small_ident2)
1037 return ADDR_AREA_SMALL;
1039 return ADDR_AREA_NORMAL;
1043 ia64_handle_model_attribute (tree *node, tree name, tree args, int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
1045 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
1046 ia64_addr_area area;
1047 tree arg, decl = *node;
1050 arg = TREE_VALUE (args);
1051 if (arg == small_ident1 || arg == small_ident2)
1053 addr_area = ADDR_AREA_SMALL;
1057 warning ("invalid argument of `%s' attribute",
1058 IDENTIFIER_POINTER (name));
1059 *no_add_attrs = true;
1062 switch (TREE_CODE (decl))
1065 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
1067 && !TREE_STATIC (decl))
1069 error ("%Jan address area attribute cannot be specified for "
1070 "local variables", decl, decl);
1071 *no_add_attrs = true;
1073 area = ia64_get_addr_area (decl);
1074 if (area != ADDR_AREA_NORMAL && addr_area != area)
1076 error ("%Jaddress area of '%s' conflicts with previous "
1077 "declaration", decl, decl);
1078 *no_add_attrs = true;
1083 error ("%Jaddress area attribute cannot be specified for functions",
1085 *no_add_attrs = true;
1089 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
1090 *no_add_attrs = true;
1098 ia64_encode_addr_area (tree decl, rtx symbol)
1102 flags = SYMBOL_REF_FLAGS (symbol);
1103 switch (ia64_get_addr_area (decl))
1105 case ADDR_AREA_NORMAL: break;
1106 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
1109 SYMBOL_REF_FLAGS (symbol) = flags;
1113 ia64_encode_section_info (tree decl, rtx rtl, int first)
1115 default_encode_section_info (decl, rtl, first);
1117 if (TREE_CODE (decl) == VAR_DECL
1118 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
1119 ia64_encode_addr_area (decl, XEXP (rtl, 0));
1122 /* Return 1 if the operands of a move are ok. */
1125 ia64_move_ok (rtx dst, rtx src)
1127 /* If we're under init_recog_no_volatile, we'll not be able to use
1128 memory_operand. So check the code directly and don't worry about
1129 the validity of the underlying address, which should have been
1130 checked elsewhere anyway. */
1131 if (GET_CODE (dst) != MEM)
1133 if (GET_CODE (src) == MEM)
1135 if (register_operand (src, VOIDmode))
1138 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1139 if (INTEGRAL_MODE_P (GET_MODE (dst)))
1140 return src == const0_rtx;
1142 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
1146 addp4_optimize_ok (rtx op1, rtx op2)
1148 return (basereg_operand (op1, GET_MODE(op1)) !=
1149 basereg_operand (op2, GET_MODE(op2)));
1152 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1153 Return the length of the field, or <= 0 on failure. */
1156 ia64_depz_field_mask (rtx rop, rtx rshift)
1158 unsigned HOST_WIDE_INT op = INTVAL (rop);
1159 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
1161 /* Get rid of the zero bits we're shifting in. */
1164 /* We must now have a solid block of 1's at bit 0. */
1165 return exact_log2 (op + 1);
1168 /* Expand a symbolic constant load. */
1171 ia64_expand_load_address (rtx dest, rtx src)
1173 if (tls_symbolic_operand (src, VOIDmode))
1175 if (GET_CODE (dest) != REG)
1178 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1179 having to pointer-extend the value afterward. Other forms of address
1180 computation below are also more natural to compute as 64-bit quantities.
1181 If we've been given an SImode destination register, change it. */
1182 if (GET_MODE (dest) != Pmode)
1183 dest = gen_rtx_REG (Pmode, REGNO (dest));
1185 if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (src))
1187 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
1190 else if (TARGET_AUTO_PIC)
1192 emit_insn (gen_load_gprel64 (dest, src));
1195 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1197 emit_insn (gen_load_fptr (dest, src));
1200 else if (sdata_symbolic_operand (src, VOIDmode))
1202 emit_insn (gen_load_gprel (dest, src));
1206 if (GET_CODE (src) == CONST
1207 && GET_CODE (XEXP (src, 0)) == PLUS
1208 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
1209 && (INTVAL (XEXP (XEXP (src, 0), 1)) & 0x1fff) != 0)
1211 rtx sym = XEXP (XEXP (src, 0), 0);
1212 HOST_WIDE_INT ofs, hi, lo;
1214 /* Split the offset into a sign extended 14-bit low part
1215 and a complementary high part. */
1216 ofs = INTVAL (XEXP (XEXP (src, 0), 1));
1217 lo = ((ofs & 0x3fff) ^ 0x2000) - 0x2000;
1220 ia64_expand_load_address (dest, plus_constant (sym, hi));
1221 emit_insn (gen_adddi3 (dest, dest, GEN_INT (lo)));
1227 tmp = gen_rtx_HIGH (Pmode, src);
1228 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1229 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1231 tmp = gen_rtx_LO_SUM (GET_MODE (dest), dest, src);
1232 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1236 static GTY(()) rtx gen_tls_tga;
1238 gen_tls_get_addr (void)
1241 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1245 static GTY(()) rtx thread_pointer_rtx;
1247 gen_thread_pointer (void)
1249 if (!thread_pointer_rtx)
1251 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1252 RTX_UNCHANGING_P (thread_pointer_rtx) = 1;
1254 return thread_pointer_rtx;
1258 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1)
1260 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1265 case TLS_MODEL_GLOBAL_DYNAMIC:
1268 tga_op1 = gen_reg_rtx (Pmode);
1269 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1270 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1271 RTX_UNCHANGING_P (tga_op1) = 1;
1273 tga_op2 = gen_reg_rtx (Pmode);
1274 emit_insn (gen_load_ltoff_dtprel (tga_op2, op1));
1275 tga_op2 = gen_rtx_MEM (Pmode, tga_op2);
1276 RTX_UNCHANGING_P (tga_op2) = 1;
1278 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1279 LCT_CONST, Pmode, 2, tga_op1,
1280 Pmode, tga_op2, Pmode);
1282 insns = get_insns ();
1285 if (GET_MODE (op0) != Pmode)
1287 emit_libcall_block (insns, op0, tga_ret, op1);
1290 case TLS_MODEL_LOCAL_DYNAMIC:
1291 /* ??? This isn't the completely proper way to do local-dynamic
1292 If the call to __tls_get_addr is used only by a single symbol,
1293 then we should (somehow) move the dtprel to the second arg
1294 to avoid the extra add. */
1297 tga_op1 = gen_reg_rtx (Pmode);
1298 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1299 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1300 RTX_UNCHANGING_P (tga_op1) = 1;
1302 tga_op2 = const0_rtx;
1304 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1305 LCT_CONST, Pmode, 2, tga_op1,
1306 Pmode, tga_op2, Pmode);
1308 insns = get_insns ();
1311 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1313 tmp = gen_reg_rtx (Pmode);
1314 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1316 if (!register_operand (op0, Pmode))
1317 op0 = gen_reg_rtx (Pmode);
1320 emit_insn (gen_load_dtprel (op0, op1));
1321 emit_insn (gen_adddi3 (op0, tmp, op0));
1324 emit_insn (gen_add_dtprel (op0, tmp, op1));
1327 case TLS_MODEL_INITIAL_EXEC:
1328 tmp = gen_reg_rtx (Pmode);
1329 emit_insn (gen_load_ltoff_tprel (tmp, op1));
1330 tmp = gen_rtx_MEM (Pmode, tmp);
1331 RTX_UNCHANGING_P (tmp) = 1;
1332 tmp = force_reg (Pmode, tmp);
1334 if (!register_operand (op0, Pmode))
1335 op0 = gen_reg_rtx (Pmode);
1336 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1339 case TLS_MODEL_LOCAL_EXEC:
1340 if (!register_operand (op0, Pmode))
1341 op0 = gen_reg_rtx (Pmode);
1344 emit_insn (gen_load_tprel (op0, op1));
1345 emit_insn (gen_adddi3 (op0, gen_thread_pointer (), op0));
1348 emit_insn (gen_add_tprel (op0, gen_thread_pointer (), op1));
1355 if (orig_op0 == op0)
1357 if (GET_MODE (orig_op0) == Pmode)
1359 return gen_lowpart (GET_MODE (orig_op0), op0);
1363 ia64_expand_move (rtx op0, rtx op1)
1365 enum machine_mode mode = GET_MODE (op0);
1367 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1368 op1 = force_reg (mode, op1);
1370 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1372 enum tls_model tls_kind;
1373 if ((tls_kind = tls_symbolic_operand (op1, VOIDmode)))
1374 return ia64_expand_tls_address (tls_kind, op0, op1);
1376 if (!TARGET_NO_PIC && reload_completed)
1378 ia64_expand_load_address (op0, op1);
1386 /* Split a move from OP1 to OP0 conditional on COND. */
1389 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1391 rtx insn, first = get_last_insn ();
1393 emit_move_insn (op0, op1);
1395 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1397 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1401 /* Split a post-reload TImode or TFmode reference into two DImode
1402 components. This is made extra difficult by the fact that we do
1403 not get any scratch registers to work with, because reload cannot
1404 be prevented from giving us a scratch that overlaps the register
1405 pair involved. So instead, when addressing memory, we tweak the
1406 pointer register up and back down with POST_INCs. Or up and not
1407 back down when we can get away with it.
1409 REVERSED is true when the loads must be done in reversed order
1410 (high word first) for correctness. DEAD is true when the pointer
1411 dies with the second insn we generate and therefore the second
1412 address must not carry a postmodify.
1414 May return an insn which is to be emitted after the moves. */
1417 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1421 switch (GET_CODE (in))
1424 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1425 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1430 /* Cannot occur reversed. */
1431 if (reversed) abort ();
1433 if (GET_MODE (in) != TFmode)
1434 split_double (in, &out[0], &out[1]);
1436 /* split_double does not understand how to split a TFmode
1437 quantity into a pair of DImode constants. */
1440 unsigned HOST_WIDE_INT p[2];
1441 long l[4]; /* TFmode is 128 bits */
1443 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1444 real_to_target (l, &r, TFmode);
1446 if (FLOAT_WORDS_BIG_ENDIAN)
1448 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1449 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1453 p[0] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1454 p[1] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1456 out[0] = GEN_INT (p[0]);
1457 out[1] = GEN_INT (p[1]);
1463 rtx base = XEXP (in, 0);
1466 switch (GET_CODE (base))
1471 out[0] = adjust_automodify_address
1472 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1473 out[1] = adjust_automodify_address
1474 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1478 /* Reversal requires a pre-increment, which can only
1479 be done as a separate insn. */
1480 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1481 out[0] = adjust_automodify_address
1482 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1483 out[1] = adjust_address (in, DImode, 0);
1488 if (reversed || dead) abort ();
1489 /* Just do the increment in two steps. */
1490 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1491 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1495 if (reversed || dead) abort ();
1496 /* Add 8, subtract 24. */
1497 base = XEXP (base, 0);
1498 out[0] = adjust_automodify_address
1499 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1500 out[1] = adjust_automodify_address
1502 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1507 if (reversed || dead) abort ();
1508 /* Extract and adjust the modification. This case is
1509 trickier than the others, because we might have an
1510 index register, or we might have a combined offset that
1511 doesn't fit a signed 9-bit displacement field. We can
1512 assume the incoming expression is already legitimate. */
1513 offset = XEXP (base, 1);
1514 base = XEXP (base, 0);
1516 out[0] = adjust_automodify_address
1517 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1519 if (GET_CODE (XEXP (offset, 1)) == REG)
1521 /* Can't adjust the postmodify to match. Emit the
1522 original, then a separate addition insn. */
1523 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1524 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1526 else if (GET_CODE (XEXP (offset, 1)) != CONST_INT)
1528 else if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1530 /* Again the postmodify cannot be made to match, but
1531 in this case it's more efficient to get rid of the
1532 postmodify entirely and fix up with an add insn. */
1533 out[1] = adjust_automodify_address (in, DImode, base, 8);
1534 fixup = gen_adddi3 (base, base,
1535 GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1539 /* Combined offset still fits in the displacement field.
1540 (We cannot overflow it at the high end.) */
1541 out[1] = adjust_automodify_address
1543 gen_rtx_POST_MODIFY (Pmode, base,
1544 gen_rtx_PLUS (Pmode, base,
1545 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1563 /* Split a TImode or TFmode move instruction after reload.
1564 This is used by *movtf_internal and *movti_internal. */
1566 ia64_split_tmode_move (rtx operands[])
1568 rtx in[2], out[2], insn;
1571 bool reversed = false;
1573 /* It is possible for reload to decide to overwrite a pointer with
1574 the value it points to. In that case we have to do the loads in
1575 the appropriate order so that the pointer is not destroyed too
1576 early. Also we must not generate a postmodify for that second
1577 load, or rws_access_regno will abort. */
1578 if (GET_CODE (operands[1]) == MEM
1579 && reg_overlap_mentioned_p (operands[0], operands[1]))
1581 rtx base = XEXP (operands[1], 0);
1582 while (GET_CODE (base) != REG)
1583 base = XEXP (base, 0);
1585 if (REGNO (base) == REGNO (operands[0]))
1589 /* Another reason to do the moves in reversed order is if the first
1590 element of the target register pair is also the second element of
1591 the source register pair. */
1592 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1593 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1596 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1597 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1599 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1600 if (GET_CODE (EXP) == MEM \
1601 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1602 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1603 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1604 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1605 XEXP (XEXP (EXP, 0), 0), \
1608 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1609 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1610 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1612 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1613 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1614 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1617 emit_insn (fixup[0]);
1619 emit_insn (fixup[1]);
1621 #undef MAYBE_ADD_REG_INC_NOTE
1624 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1625 through memory plus an extra GR scratch register. Except that you can
1626 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1627 SECONDARY_RELOAD_CLASS, but not both.
1629 We got into problems in the first place by allowing a construct like
1630 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1631 This solution attempts to prevent this situation from occurring. When
1632 we see something like the above, we spill the inner register to memory. */
1635 spill_xfmode_operand (rtx in, int force)
1637 if (GET_CODE (in) == SUBREG
1638 && GET_MODE (SUBREG_REG (in)) == TImode
1639 && GET_CODE (SUBREG_REG (in)) == REG)
1641 rtx mem = gen_mem_addressof (SUBREG_REG (in), NULL_TREE, /*rescan=*/true);
1642 return gen_rtx_MEM (XFmode, copy_to_reg (XEXP (mem, 0)));
1644 else if (force && GET_CODE (in) == REG)
1646 rtx mem = gen_mem_addressof (in, NULL_TREE, /*rescan=*/true);
1647 return gen_rtx_MEM (XFmode, copy_to_reg (XEXP (mem, 0)));
1649 else if (GET_CODE (in) == MEM
1650 && GET_CODE (XEXP (in, 0)) == ADDRESSOF)
1651 return change_address (in, XFmode, copy_to_reg (XEXP (in, 0)));
1656 /* Emit comparison instruction if necessary, returning the expression
1657 that holds the compare result in the proper mode. */
1659 static GTY(()) rtx cmptf_libfunc;
1662 ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
1664 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1667 /* If we have a BImode input, then we already have a compare result, and
1668 do not need to emit another comparison. */
1669 if (GET_MODE (op0) == BImode)
1671 if ((code == NE || code == EQ) && op1 == const0_rtx)
1676 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1677 magic number as its third argument, that indicates what to do.
1678 The return value is an integer to be compared against zero. */
1679 else if (TARGET_HPUX && GET_MODE (op0) == TFmode)
1682 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1688 enum rtx_code ncode;
1690 if (GET_MODE (op1) != TFmode)
1694 /* 1 = equal, 0 = not equal. Equality operators do
1695 not raise FP_INVALID when given an SNaN operand. */
1696 case EQ: magic = QCMP_EQ; ncode = NE; break;
1697 case NE: magic = QCMP_EQ; ncode = EQ; break;
1698 /* isunordered() from C99. */
1699 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1700 /* Relational operators raise FP_INVALID when given
1702 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1703 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1704 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1705 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1706 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1707 Expanders for buneq etc. weuld have to be added to ia64.md
1708 for this to be useful. */
1714 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1715 op0, TFmode, op1, TFmode,
1716 GEN_INT (magic), DImode);
1717 cmp = gen_reg_rtx (BImode);
1718 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1719 gen_rtx_fmt_ee (ncode, BImode,
1722 insns = get_insns ();
1725 emit_libcall_block (insns, cmp, cmp,
1726 gen_rtx_fmt_ee (code, BImode, op0, op1));
1731 cmp = gen_reg_rtx (BImode);
1732 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1733 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1737 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1740 /* Emit the appropriate sequence for a call. */
1743 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
1748 addr = XEXP (addr, 0);
1749 addr = convert_memory_address (DImode, addr);
1750 b0 = gen_rtx_REG (DImode, R_BR (0));
1752 /* ??? Should do this for functions known to bind local too. */
1753 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1756 insn = gen_sibcall_nogp (addr);
1758 insn = gen_call_nogp (addr, b0);
1760 insn = gen_call_value_nogp (retval, addr, b0);
1761 insn = emit_call_insn (insn);
1766 insn = gen_sibcall_gp (addr);
1768 insn = gen_call_gp (addr, b0);
1770 insn = gen_call_value_gp (retval, addr, b0);
1771 insn = emit_call_insn (insn);
1773 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1777 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1781 ia64_reload_gp (void)
1785 if (current_frame_info.reg_save_gp)
1786 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1789 HOST_WIDE_INT offset;
1791 offset = (current_frame_info.spill_cfa_off
1792 + current_frame_info.spill_size);
1793 if (frame_pointer_needed)
1795 tmp = hard_frame_pointer_rtx;
1800 tmp = stack_pointer_rtx;
1801 offset = current_frame_info.total_size - offset;
1804 if (CONST_OK_FOR_I (offset))
1805 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1806 tmp, GEN_INT (offset)));
1809 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
1810 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1811 pic_offset_table_rtx, tmp));
1814 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
1817 emit_move_insn (pic_offset_table_rtx, tmp);
1821 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
1822 rtx scratch_b, int noreturn_p, int sibcall_p)
1825 bool is_desc = false;
1827 /* If we find we're calling through a register, then we're actually
1828 calling through a descriptor, so load up the values. */
1829 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
1834 /* ??? We are currently constrained to *not* use peep2, because
1835 we can legitimately change the global lifetime of the GP
1836 (in the form of killing where previously live). This is
1837 because a call through a descriptor doesn't use the previous
1838 value of the GP, while a direct call does, and we do not
1839 commit to either form until the split here.
1841 That said, this means that we lack precise life info for
1842 whether ADDR is dead after this call. This is not terribly
1843 important, since we can fix things up essentially for free
1844 with the POST_DEC below, but it's nice to not use it when we
1845 can immediately tell it's not necessary. */
1846 addr_dead_p = ((noreturn_p || sibcall_p
1847 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
1849 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
1851 /* Load the code address into scratch_b. */
1852 tmp = gen_rtx_POST_INC (Pmode, addr);
1853 tmp = gen_rtx_MEM (Pmode, tmp);
1854 emit_move_insn (scratch_r, tmp);
1855 emit_move_insn (scratch_b, scratch_r);
1857 /* Load the GP address. If ADDR is not dead here, then we must
1858 revert the change made above via the POST_INCREMENT. */
1860 tmp = gen_rtx_POST_DEC (Pmode, addr);
1863 tmp = gen_rtx_MEM (Pmode, tmp);
1864 emit_move_insn (pic_offset_table_rtx, tmp);
1871 insn = gen_sibcall_nogp (addr);
1873 insn = gen_call_value_nogp (retval, addr, retaddr);
1875 insn = gen_call_nogp (addr, retaddr);
1876 emit_call_insn (insn);
1878 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
1882 /* Begin the assembly file. */
1885 ia64_file_start (void)
1887 default_file_start ();
1888 emit_safe_across_calls ();
1892 emit_safe_across_calls (void)
1894 unsigned int rs, re;
1901 while (rs < 64 && call_used_regs[PR_REG (rs)])
1905 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
1909 fputs ("\t.pred.safe_across_calls ", asm_out_file);
1913 fputc (',', asm_out_file);
1915 fprintf (asm_out_file, "p%u", rs);
1917 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
1921 fputc ('\n', asm_out_file);
1924 /* Helper function for ia64_compute_frame_size: find an appropriate general
1925 register to spill some special register to. SPECIAL_SPILL_MASK contains
1926 bits in GR0 to GR31 that have already been allocated by this routine.
1927 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1930 find_gr_spill (int try_locals)
1934 /* If this is a leaf function, first try an otherwise unused
1935 call-clobbered register. */
1936 if (current_function_is_leaf)
1938 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1939 if (! regs_ever_live[regno]
1940 && call_used_regs[regno]
1941 && ! fixed_regs[regno]
1942 && ! global_regs[regno]
1943 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1945 current_frame_info.gr_used_mask |= 1 << regno;
1952 regno = current_frame_info.n_local_regs;
1953 /* If there is a frame pointer, then we can't use loc79, because
1954 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1955 reg_name switching code in ia64_expand_prologue. */
1956 if (regno < (80 - frame_pointer_needed))
1958 current_frame_info.n_local_regs = regno + 1;
1959 return LOC_REG (0) + regno;
1963 /* Failed to find a general register to spill to. Must use stack. */
1967 /* In order to make for nice schedules, we try to allocate every temporary
1968 to a different register. We must of course stay away from call-saved,
1969 fixed, and global registers. We must also stay away from registers
1970 allocated in current_frame_info.gr_used_mask, since those include regs
1971 used all through the prologue.
1973 Any register allocated here must be used immediately. The idea is to
1974 aid scheduling, not to solve data flow problems. */
1976 static int last_scratch_gr_reg;
1979 next_scratch_gr_reg (void)
1983 for (i = 0; i < 32; ++i)
1985 regno = (last_scratch_gr_reg + i + 1) & 31;
1986 if (call_used_regs[regno]
1987 && ! fixed_regs[regno]
1988 && ! global_regs[regno]
1989 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1991 last_scratch_gr_reg = regno;
1996 /* There must be _something_ available. */
2000 /* Helper function for ia64_compute_frame_size, called through
2001 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2004 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2006 unsigned int regno = REGNO (reg);
2009 unsigned int i, n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2010 for (i = 0; i < n; ++i)
2011 current_frame_info.gr_used_mask |= 1 << (regno + i);
2015 /* Returns the number of bytes offset between the frame pointer and the stack
2016 pointer for the current function. SIZE is the number of bytes of space
2017 needed for local variables. */
2020 ia64_compute_frame_size (HOST_WIDE_INT size)
2022 HOST_WIDE_INT total_size;
2023 HOST_WIDE_INT spill_size = 0;
2024 HOST_WIDE_INT extra_spill_size = 0;
2025 HOST_WIDE_INT pretend_args_size;
2028 int spilled_gr_p = 0;
2029 int spilled_fr_p = 0;
2033 if (current_frame_info.initialized)
2036 memset (¤t_frame_info, 0, sizeof current_frame_info);
2037 CLEAR_HARD_REG_SET (mask);
2039 /* Don't allocate scratches to the return register. */
2040 diddle_return_value (mark_reg_gr_used_mask, NULL);
2042 /* Don't allocate scratches to the EH scratch registers. */
2043 if (cfun->machine->ia64_eh_epilogue_sp)
2044 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2045 if (cfun->machine->ia64_eh_epilogue_bsp)
2046 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2048 /* Find the size of the register stack frame. We have only 80 local
2049 registers, because we reserve 8 for the inputs and 8 for the
2052 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2053 since we'll be adjusting that down later. */
2054 regno = LOC_REG (78) + ! frame_pointer_needed;
2055 for (; regno >= LOC_REG (0); regno--)
2056 if (regs_ever_live[regno])
2058 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2060 /* For functions marked with the syscall_linkage attribute, we must mark
2061 all eight input registers as in use, so that locals aren't visible to
2064 if (cfun->machine->n_varargs > 0
2065 || lookup_attribute ("syscall_linkage",
2066 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2067 current_frame_info.n_input_regs = 8;
2070 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2071 if (regs_ever_live[regno])
2073 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2076 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2077 if (regs_ever_live[regno])
2079 i = regno - OUT_REG (0) + 1;
2081 /* When -p profiling, we need one output register for the mcount argument.
2082 Likewise for -a profiling for the bb_init_func argument. For -ax
2083 profiling, we need two output registers for the two bb_init_trace_func
2085 if (current_function_profile)
2087 current_frame_info.n_output_regs = i;
2089 /* ??? No rotating register support yet. */
2090 current_frame_info.n_rotate_regs = 0;
2092 /* Discover which registers need spilling, and how much room that
2093 will take. Begin with floating point and general registers,
2094 which will always wind up on the stack. */
2096 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2097 if (regs_ever_live[regno] && ! call_used_regs[regno])
2099 SET_HARD_REG_BIT (mask, regno);
2105 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2106 if (regs_ever_live[regno] && ! call_used_regs[regno])
2108 SET_HARD_REG_BIT (mask, regno);
2114 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2115 if (regs_ever_live[regno] && ! call_used_regs[regno])
2117 SET_HARD_REG_BIT (mask, regno);
2122 /* Now come all special registers that might get saved in other
2123 general registers. */
2125 if (frame_pointer_needed)
2127 current_frame_info.reg_fp = find_gr_spill (1);
2128 /* If we did not get a register, then we take LOC79. This is guaranteed
2129 to be free, even if regs_ever_live is already set, because this is
2130 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2131 as we don't count loc79 above. */
2132 if (current_frame_info.reg_fp == 0)
2134 current_frame_info.reg_fp = LOC_REG (79);
2135 current_frame_info.n_local_regs++;
2139 if (! current_function_is_leaf)
2141 /* Emit a save of BR0 if we call other functions. Do this even
2142 if this function doesn't return, as EH depends on this to be
2143 able to unwind the stack. */
2144 SET_HARD_REG_BIT (mask, BR_REG (0));
2146 current_frame_info.reg_save_b0 = find_gr_spill (1);
2147 if (current_frame_info.reg_save_b0 == 0)
2153 /* Similarly for ar.pfs. */
2154 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2155 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2156 if (current_frame_info.reg_save_ar_pfs == 0)
2158 extra_spill_size += 8;
2162 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2163 registers are clobbered, so we fall back to the stack. */
2164 current_frame_info.reg_save_gp
2165 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
2166 if (current_frame_info.reg_save_gp == 0)
2168 SET_HARD_REG_BIT (mask, GR_REG (1));
2175 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
2177 SET_HARD_REG_BIT (mask, BR_REG (0));
2182 if (regs_ever_live[AR_PFS_REGNUM])
2184 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2185 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2186 if (current_frame_info.reg_save_ar_pfs == 0)
2188 extra_spill_size += 8;
2194 /* Unwind descriptor hackery: things are most efficient if we allocate
2195 consecutive GR save registers for RP, PFS, FP in that order. However,
2196 it is absolutely critical that FP get the only hard register that's
2197 guaranteed to be free, so we allocated it first. If all three did
2198 happen to be allocated hard regs, and are consecutive, rearrange them
2199 into the preferred order now. */
2200 if (current_frame_info.reg_fp != 0
2201 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
2202 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
2204 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
2205 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
2206 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
2209 /* See if we need to store the predicate register block. */
2210 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2211 if (regs_ever_live[regno] && ! call_used_regs[regno])
2213 if (regno <= PR_REG (63))
2215 SET_HARD_REG_BIT (mask, PR_REG (0));
2216 current_frame_info.reg_save_pr = find_gr_spill (1);
2217 if (current_frame_info.reg_save_pr == 0)
2219 extra_spill_size += 8;
2223 /* ??? Mark them all as used so that register renaming and such
2224 are free to use them. */
2225 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2226 regs_ever_live[regno] = 1;
2229 /* If we're forced to use st8.spill, we're forced to save and restore
2230 ar.unat as well. The check for existing liveness allows inline asm
2231 to touch ar.unat. */
2232 if (spilled_gr_p || cfun->machine->n_varargs
2233 || regs_ever_live[AR_UNAT_REGNUM])
2235 regs_ever_live[AR_UNAT_REGNUM] = 1;
2236 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2237 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
2238 if (current_frame_info.reg_save_ar_unat == 0)
2240 extra_spill_size += 8;
2245 if (regs_ever_live[AR_LC_REGNUM])
2247 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2248 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
2249 if (current_frame_info.reg_save_ar_lc == 0)
2251 extra_spill_size += 8;
2256 /* If we have an odd number of words of pretend arguments written to
2257 the stack, then the FR save area will be unaligned. We round the
2258 size of this area up to keep things 16 byte aligned. */
2260 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
2262 pretend_args_size = current_function_pretend_args_size;
2264 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2265 + current_function_outgoing_args_size);
2266 total_size = IA64_STACK_ALIGN (total_size);
2268 /* We always use the 16-byte scratch area provided by the caller, but
2269 if we are a leaf function, there's no one to which we need to provide
2271 if (current_function_is_leaf)
2272 total_size = MAX (0, total_size - 16);
2274 current_frame_info.total_size = total_size;
2275 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2276 current_frame_info.spill_size = spill_size;
2277 current_frame_info.extra_spill_size = extra_spill_size;
2278 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2279 current_frame_info.n_spilled = n_spilled;
2280 current_frame_info.initialized = reload_completed;
2283 /* Compute the initial difference between the specified pair of registers. */
2286 ia64_initial_elimination_offset (int from, int to)
2288 HOST_WIDE_INT offset;
2290 ia64_compute_frame_size (get_frame_size ());
2293 case FRAME_POINTER_REGNUM:
2294 if (to == HARD_FRAME_POINTER_REGNUM)
2296 if (current_function_is_leaf)
2297 offset = -current_frame_info.total_size;
2299 offset = -(current_frame_info.total_size
2300 - current_function_outgoing_args_size - 16);
2302 else if (to == STACK_POINTER_REGNUM)
2304 if (current_function_is_leaf)
2307 offset = 16 + current_function_outgoing_args_size;
2313 case ARG_POINTER_REGNUM:
2314 /* Arguments start above the 16 byte save area, unless stdarg
2315 in which case we store through the 16 byte save area. */
2316 if (to == HARD_FRAME_POINTER_REGNUM)
2317 offset = 16 - current_function_pretend_args_size;
2318 else if (to == STACK_POINTER_REGNUM)
2319 offset = (current_frame_info.total_size
2320 + 16 - current_function_pretend_args_size);
2332 /* If there are more than a trivial number of register spills, we use
2333 two interleaved iterators so that we can get two memory references
2336 In order to simplify things in the prologue and epilogue expanders,
2337 we use helper functions to fix up the memory references after the
2338 fact with the appropriate offsets to a POST_MODIFY memory mode.
2339 The following data structure tracks the state of the two iterators
2340 while insns are being emitted. */
2342 struct spill_fill_data
2344 rtx init_after; /* point at which to emit initializations */
2345 rtx init_reg[2]; /* initial base register */
2346 rtx iter_reg[2]; /* the iterator registers */
2347 rtx *prev_addr[2]; /* address of last memory use */
2348 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2349 HOST_WIDE_INT prev_off[2]; /* last offset */
2350 int n_iter; /* number of iterators in use */
2351 int next_iter; /* next iterator to use */
2352 unsigned int save_gr_used_mask;
2355 static struct spill_fill_data spill_fill_data;
2358 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2362 spill_fill_data.init_after = get_last_insn ();
2363 spill_fill_data.init_reg[0] = init_reg;
2364 spill_fill_data.init_reg[1] = init_reg;
2365 spill_fill_data.prev_addr[0] = NULL;
2366 spill_fill_data.prev_addr[1] = NULL;
2367 spill_fill_data.prev_insn[0] = NULL;
2368 spill_fill_data.prev_insn[1] = NULL;
2369 spill_fill_data.prev_off[0] = cfa_off;
2370 spill_fill_data.prev_off[1] = cfa_off;
2371 spill_fill_data.next_iter = 0;
2372 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2374 spill_fill_data.n_iter = 1 + (n_spills > 2);
2375 for (i = 0; i < spill_fill_data.n_iter; ++i)
2377 int regno = next_scratch_gr_reg ();
2378 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2379 current_frame_info.gr_used_mask |= 1 << regno;
2384 finish_spill_pointers (void)
2386 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2390 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2392 int iter = spill_fill_data.next_iter;
2393 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2394 rtx disp_rtx = GEN_INT (disp);
2397 if (spill_fill_data.prev_addr[iter])
2399 if (CONST_OK_FOR_N (disp))
2401 *spill_fill_data.prev_addr[iter]
2402 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2403 gen_rtx_PLUS (DImode,
2404 spill_fill_data.iter_reg[iter],
2406 REG_NOTES (spill_fill_data.prev_insn[iter])
2407 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2408 REG_NOTES (spill_fill_data.prev_insn[iter]));
2412 /* ??? Could use register post_modify for loads. */
2413 if (! CONST_OK_FOR_I (disp))
2415 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2416 emit_move_insn (tmp, disp_rtx);
2419 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2420 spill_fill_data.iter_reg[iter], disp_rtx));
2423 /* Micro-optimization: if we've created a frame pointer, it's at
2424 CFA 0, which may allow the real iterator to be initialized lower,
2425 slightly increasing parallelism. Also, if there are few saves
2426 it may eliminate the iterator entirely. */
2428 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2429 && frame_pointer_needed)
2431 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2432 set_mem_alias_set (mem, get_varargs_alias_set ());
2440 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2441 spill_fill_data.init_reg[iter]);
2446 if (! CONST_OK_FOR_I (disp))
2448 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2449 emit_move_insn (tmp, disp_rtx);
2453 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2454 spill_fill_data.init_reg[iter],
2461 /* Careful for being the first insn in a sequence. */
2462 if (spill_fill_data.init_after)
2463 insn = emit_insn_after (seq, spill_fill_data.init_after);
2466 rtx first = get_insns ();
2468 insn = emit_insn_before (seq, first);
2470 insn = emit_insn (seq);
2472 spill_fill_data.init_after = insn;
2474 /* If DISP is 0, we may or may not have a further adjustment
2475 afterward. If we do, then the load/store insn may be modified
2476 to be a post-modify. If we don't, then this copy may be
2477 eliminated by copyprop_hardreg_forward, which makes this
2478 insn garbage, which runs afoul of the sanity check in
2479 propagate_one_insn. So mark this insn as legal to delete. */
2481 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2485 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2487 /* ??? Not all of the spills are for varargs, but some of them are.
2488 The rest of the spills belong in an alias set of their own. But
2489 it doesn't actually hurt to include them here. */
2490 set_mem_alias_set (mem, get_varargs_alias_set ());
2492 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2493 spill_fill_data.prev_off[iter] = cfa_off;
2495 if (++iter >= spill_fill_data.n_iter)
2497 spill_fill_data.next_iter = iter;
2503 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
2506 int iter = spill_fill_data.next_iter;
2509 mem = spill_restore_mem (reg, cfa_off);
2510 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2511 spill_fill_data.prev_insn[iter] = insn;
2518 RTX_FRAME_RELATED_P (insn) = 1;
2520 /* Don't even pretend that the unwind code can intuit its way
2521 through a pair of interleaved post_modify iterators. Just
2522 provide the correct answer. */
2524 if (frame_pointer_needed)
2526 base = hard_frame_pointer_rtx;
2531 base = stack_pointer_rtx;
2532 off = current_frame_info.total_size - cfa_off;
2536 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2537 gen_rtx_SET (VOIDmode,
2538 gen_rtx_MEM (GET_MODE (reg),
2539 plus_constant (base, off)),
2546 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
2548 int iter = spill_fill_data.next_iter;
2551 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2552 GEN_INT (cfa_off)));
2553 spill_fill_data.prev_insn[iter] = insn;
2556 /* Wrapper functions that discards the CONST_INT spill offset. These
2557 exist so that we can give gr_spill/gr_fill the offset they need and
2558 use a consistent function interface. */
2561 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2563 return gen_movdi (dest, src);
2567 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2569 return gen_fr_spill (dest, src);
2573 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2575 return gen_fr_restore (dest, src);
2578 /* Called after register allocation to add any instructions needed for the
2579 prologue. Using a prologue insn is favored compared to putting all of the
2580 instructions in output_function_prologue(), since it allows the scheduler
2581 to intermix instructions with the saves of the caller saved registers. In
2582 some cases, it might be necessary to emit a barrier instruction as the last
2583 insn to prevent such scheduling.
2585 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2586 so that the debug info generation code can handle them properly.
2588 The register save area is layed out like so:
2590 [ varargs spill area ]
2591 [ fr register spill area ]
2592 [ br register spill area ]
2593 [ ar register spill area ]
2594 [ pr register spill area ]
2595 [ gr register spill area ] */
2597 /* ??? Get inefficient code when the frame size is larger than can fit in an
2598 adds instruction. */
2601 ia64_expand_prologue (void)
2603 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2604 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2607 ia64_compute_frame_size (get_frame_size ());
2608 last_scratch_gr_reg = 15;
2610 /* If there is no epilogue, then we don't need some prologue insns.
2611 We need to avoid emitting the dead prologue insns, because flow
2612 will complain about them. */
2617 for (e = EXIT_BLOCK_PTR->pred; e ; e = e->pred_next)
2618 if ((e->flags & EDGE_FAKE) == 0
2619 && (e->flags & EDGE_FALLTHRU) != 0)
2621 epilogue_p = (e != NULL);
2626 /* Set the local, input, and output register names. We need to do this
2627 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2628 half. If we use in/loc/out register names, then we get assembler errors
2629 in crtn.S because there is no alloc insn or regstk directive in there. */
2630 if (! TARGET_REG_NAMES)
2632 int inputs = current_frame_info.n_input_regs;
2633 int locals = current_frame_info.n_local_regs;
2634 int outputs = current_frame_info.n_output_regs;
2636 for (i = 0; i < inputs; i++)
2637 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2638 for (i = 0; i < locals; i++)
2639 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2640 for (i = 0; i < outputs; i++)
2641 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2644 /* Set the frame pointer register name. The regnum is logically loc79,
2645 but of course we'll not have allocated that many locals. Rather than
2646 worrying about renumbering the existing rtxs, we adjust the name. */
2647 /* ??? This code means that we can never use one local register when
2648 there is a frame pointer. loc79 gets wasted in this case, as it is
2649 renamed to a register that will never be used. See also the try_locals
2650 code in find_gr_spill. */
2651 if (current_frame_info.reg_fp)
2653 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2654 reg_names[HARD_FRAME_POINTER_REGNUM]
2655 = reg_names[current_frame_info.reg_fp];
2656 reg_names[current_frame_info.reg_fp] = tmp;
2659 /* We don't need an alloc instruction if we've used no outputs or locals. */
2660 if (current_frame_info.n_local_regs == 0
2661 && current_frame_info.n_output_regs == 0
2662 && current_frame_info.n_input_regs <= current_function_args_info.int_regs
2663 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
2665 /* If there is no alloc, but there are input registers used, then we
2666 need a .regstk directive. */
2667 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
2668 ar_pfs_save_reg = NULL_RTX;
2672 current_frame_info.need_regstk = 0;
2674 if (current_frame_info.reg_save_ar_pfs)
2675 regno = current_frame_info.reg_save_ar_pfs;
2677 regno = next_scratch_gr_reg ();
2678 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
2680 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
2681 GEN_INT (current_frame_info.n_input_regs),
2682 GEN_INT (current_frame_info.n_local_regs),
2683 GEN_INT (current_frame_info.n_output_regs),
2684 GEN_INT (current_frame_info.n_rotate_regs)));
2685 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
2688 /* Set up frame pointer, stack pointer, and spill iterators. */
2690 n_varargs = cfun->machine->n_varargs;
2691 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
2692 stack_pointer_rtx, 0);
2694 if (frame_pointer_needed)
2696 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2697 RTX_FRAME_RELATED_P (insn) = 1;
2700 if (current_frame_info.total_size != 0)
2702 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
2705 if (CONST_OK_FOR_I (- current_frame_info.total_size))
2706 offset = frame_size_rtx;
2709 regno = next_scratch_gr_reg ();
2710 offset = gen_rtx_REG (DImode, regno);
2711 emit_move_insn (offset, frame_size_rtx);
2714 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
2715 stack_pointer_rtx, offset));
2717 if (! frame_pointer_needed)
2719 RTX_FRAME_RELATED_P (insn) = 1;
2720 if (GET_CODE (offset) != CONST_INT)
2723 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2724 gen_rtx_SET (VOIDmode,
2726 gen_rtx_PLUS (DImode,
2733 /* ??? At this point we must generate a magic insn that appears to
2734 modify the stack pointer, the frame pointer, and all spill
2735 iterators. This would allow the most scheduling freedom. For
2736 now, just hard stop. */
2737 emit_insn (gen_blockage ());
2740 /* Must copy out ar.unat before doing any integer spills. */
2741 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2743 if (current_frame_info.reg_save_ar_unat)
2745 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2748 alt_regno = next_scratch_gr_reg ();
2749 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2750 current_frame_info.gr_used_mask |= 1 << alt_regno;
2753 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2754 insn = emit_move_insn (ar_unat_save_reg, reg);
2755 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
2757 /* Even if we're not going to generate an epilogue, we still
2758 need to save the register so that EH works. */
2759 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
2760 emit_insn (gen_prologue_use (ar_unat_save_reg));
2763 ar_unat_save_reg = NULL_RTX;
2765 /* Spill all varargs registers. Do this before spilling any GR registers,
2766 since we want the UNAT bits for the GR registers to override the UNAT
2767 bits from varargs, which we don't care about. */
2770 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
2772 reg = gen_rtx_REG (DImode, regno);
2773 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
2776 /* Locate the bottom of the register save area. */
2777 cfa_off = (current_frame_info.spill_cfa_off
2778 + current_frame_info.spill_size
2779 + current_frame_info.extra_spill_size);
2781 /* Save the predicate register block either in a register or in memory. */
2782 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2784 reg = gen_rtx_REG (DImode, PR_REG (0));
2785 if (current_frame_info.reg_save_pr != 0)
2787 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2788 insn = emit_move_insn (alt_reg, reg);
2790 /* ??? Denote pr spill/fill by a DImode move that modifies all
2791 64 hard registers. */
2792 RTX_FRAME_RELATED_P (insn) = 1;
2794 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2795 gen_rtx_SET (VOIDmode, alt_reg, reg),
2798 /* Even if we're not going to generate an epilogue, we still
2799 need to save the register so that EH works. */
2801 emit_insn (gen_prologue_use (alt_reg));
2805 alt_regno = next_scratch_gr_reg ();
2806 alt_reg = gen_rtx_REG (DImode, alt_regno);
2807 insn = emit_move_insn (alt_reg, reg);
2808 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2813 /* Handle AR regs in numerical order. All of them get special handling. */
2814 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
2815 && current_frame_info.reg_save_ar_unat == 0)
2817 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2818 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
2822 /* The alloc insn already copied ar.pfs into a general register. The
2823 only thing we have to do now is copy that register to a stack slot
2824 if we'd not allocated a local register for the job. */
2825 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
2826 && current_frame_info.reg_save_ar_pfs == 0)
2828 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2829 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
2833 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2835 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2836 if (current_frame_info.reg_save_ar_lc != 0)
2838 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2839 insn = emit_move_insn (alt_reg, reg);
2840 RTX_FRAME_RELATED_P (insn) = 1;
2842 /* Even if we're not going to generate an epilogue, we still
2843 need to save the register so that EH works. */
2845 emit_insn (gen_prologue_use (alt_reg));
2849 alt_regno = next_scratch_gr_reg ();
2850 alt_reg = gen_rtx_REG (DImode, alt_regno);
2851 emit_move_insn (alt_reg, reg);
2852 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2857 if (current_frame_info.reg_save_gp)
2859 insn = emit_move_insn (gen_rtx_REG (DImode,
2860 current_frame_info.reg_save_gp),
2861 pic_offset_table_rtx);
2862 /* We don't know for sure yet if this is actually needed, since
2863 we've not split the PIC call patterns. If all of the calls
2864 are indirect, and not followed by any uses of the gp, then
2865 this save is dead. Allow it to go away. */
2867 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
2870 /* We should now be at the base of the gr/br/fr spill area. */
2871 if (cfa_off != (current_frame_info.spill_cfa_off
2872 + current_frame_info.spill_size))
2875 /* Spill all general registers. */
2876 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2877 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2879 reg = gen_rtx_REG (DImode, regno);
2880 do_spill (gen_gr_spill, reg, cfa_off, reg);
2884 /* Handle BR0 specially -- it may be getting stored permanently in
2885 some GR register. */
2886 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2888 reg = gen_rtx_REG (DImode, BR_REG (0));
2889 if (current_frame_info.reg_save_b0 != 0)
2891 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2892 insn = emit_move_insn (alt_reg, reg);
2893 RTX_FRAME_RELATED_P (insn) = 1;
2895 /* Even if we're not going to generate an epilogue, we still
2896 need to save the register so that EH works. */
2898 emit_insn (gen_prologue_use (alt_reg));
2902 alt_regno = next_scratch_gr_reg ();
2903 alt_reg = gen_rtx_REG (DImode, alt_regno);
2904 emit_move_insn (alt_reg, reg);
2905 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2910 /* Spill the rest of the BR registers. */
2911 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2912 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2914 alt_regno = next_scratch_gr_reg ();
2915 alt_reg = gen_rtx_REG (DImode, alt_regno);
2916 reg = gen_rtx_REG (DImode, regno);
2917 emit_move_insn (alt_reg, reg);
2918 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2922 /* Align the frame and spill all FR registers. */
2923 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2924 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2928 reg = gen_rtx_REG (XFmode, regno);
2929 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
2933 if (cfa_off != current_frame_info.spill_cfa_off)
2936 finish_spill_pointers ();
2939 /* Called after register allocation to add any instructions needed for the
2940 epilogue. Using an epilogue insn is favored compared to putting all of the
2941 instructions in output_function_prologue(), since it allows the scheduler
2942 to intermix instructions with the saves of the caller saved registers. In
2943 some cases, it might be necessary to emit a barrier instruction as the last
2944 insn to prevent such scheduling. */
2947 ia64_expand_epilogue (int sibcall_p)
2949 rtx insn, reg, alt_reg, ar_unat_save_reg;
2950 int regno, alt_regno, cfa_off;
2952 ia64_compute_frame_size (get_frame_size ());
2954 /* If there is a frame pointer, then we use it instead of the stack
2955 pointer, so that the stack pointer does not need to be valid when
2956 the epilogue starts. See EXIT_IGNORE_STACK. */
2957 if (frame_pointer_needed)
2958 setup_spill_pointers (current_frame_info.n_spilled,
2959 hard_frame_pointer_rtx, 0);
2961 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
2962 current_frame_info.total_size);
2964 if (current_frame_info.total_size != 0)
2966 /* ??? At this point we must generate a magic insn that appears to
2967 modify the spill iterators and the frame pointer. This would
2968 allow the most scheduling freedom. For now, just hard stop. */
2969 emit_insn (gen_blockage ());
2972 /* Locate the bottom of the register save area. */
2973 cfa_off = (current_frame_info.spill_cfa_off
2974 + current_frame_info.spill_size
2975 + current_frame_info.extra_spill_size);
2977 /* Restore the predicate registers. */
2978 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2980 if (current_frame_info.reg_save_pr != 0)
2981 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2984 alt_regno = next_scratch_gr_reg ();
2985 alt_reg = gen_rtx_REG (DImode, alt_regno);
2986 do_restore (gen_movdi_x, alt_reg, cfa_off);
2989 reg = gen_rtx_REG (DImode, PR_REG (0));
2990 emit_move_insn (reg, alt_reg);
2993 /* Restore the application registers. */
2995 /* Load the saved unat from the stack, but do not restore it until
2996 after the GRs have been restored. */
2997 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2999 if (current_frame_info.reg_save_ar_unat != 0)
3001 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
3004 alt_regno = next_scratch_gr_reg ();
3005 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3006 current_frame_info.gr_used_mask |= 1 << alt_regno;
3007 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3012 ar_unat_save_reg = NULL_RTX;
3014 if (current_frame_info.reg_save_ar_pfs != 0)
3016 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
3017 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3018 emit_move_insn (reg, alt_reg);
3020 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3022 alt_regno = next_scratch_gr_reg ();
3023 alt_reg = gen_rtx_REG (DImode, alt_regno);
3024 do_restore (gen_movdi_x, alt_reg, cfa_off);
3026 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3027 emit_move_insn (reg, alt_reg);
3030 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3032 if (current_frame_info.reg_save_ar_lc != 0)
3033 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
3036 alt_regno = next_scratch_gr_reg ();
3037 alt_reg = gen_rtx_REG (DImode, alt_regno);
3038 do_restore (gen_movdi_x, alt_reg, cfa_off);
3041 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3042 emit_move_insn (reg, alt_reg);
3045 /* We should now be at the base of the gr/br/fr spill area. */
3046 if (cfa_off != (current_frame_info.spill_cfa_off
3047 + current_frame_info.spill_size))
3050 /* The GP may be stored on the stack in the prologue, but it's
3051 never restored in the epilogue. Skip the stack slot. */
3052 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3055 /* Restore all general registers. */
3056 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3057 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3059 reg = gen_rtx_REG (DImode, regno);
3060 do_restore (gen_gr_restore, reg, cfa_off);
3064 /* Restore the branch registers. Handle B0 specially, as it may
3065 have gotten stored in some GR register. */
3066 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3068 if (current_frame_info.reg_save_b0 != 0)
3069 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3072 alt_regno = next_scratch_gr_reg ();
3073 alt_reg = gen_rtx_REG (DImode, alt_regno);
3074 do_restore (gen_movdi_x, alt_reg, cfa_off);
3077 reg = gen_rtx_REG (DImode, BR_REG (0));
3078 emit_move_insn (reg, alt_reg);
3081 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3082 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3084 alt_regno = next_scratch_gr_reg ();
3085 alt_reg = gen_rtx_REG (DImode, alt_regno);
3086 do_restore (gen_movdi_x, alt_reg, cfa_off);
3088 reg = gen_rtx_REG (DImode, regno);
3089 emit_move_insn (reg, alt_reg);
3092 /* Restore floating point registers. */
3093 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3094 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3098 reg = gen_rtx_REG (XFmode, regno);
3099 do_restore (gen_fr_restore_x, reg, cfa_off);
3103 /* Restore ar.unat for real. */
3104 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3106 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3107 emit_move_insn (reg, ar_unat_save_reg);
3110 if (cfa_off != current_frame_info.spill_cfa_off)
3113 finish_spill_pointers ();
3115 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
3117 /* ??? At this point we must generate a magic insn that appears to
3118 modify the spill iterators, the stack pointer, and the frame
3119 pointer. This would allow the most scheduling freedom. For now,
3121 emit_insn (gen_blockage ());
3124 if (cfun->machine->ia64_eh_epilogue_sp)
3125 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3126 else if (frame_pointer_needed)
3128 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3129 RTX_FRAME_RELATED_P (insn) = 1;
3131 else if (current_frame_info.total_size)
3133 rtx offset, frame_size_rtx;
3135 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3136 if (CONST_OK_FOR_I (current_frame_info.total_size))
3137 offset = frame_size_rtx;
3140 regno = next_scratch_gr_reg ();
3141 offset = gen_rtx_REG (DImode, regno);
3142 emit_move_insn (offset, frame_size_rtx);
3145 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3148 RTX_FRAME_RELATED_P (insn) = 1;
3149 if (GET_CODE (offset) != CONST_INT)
3152 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3153 gen_rtx_SET (VOIDmode,
3155 gen_rtx_PLUS (DImode,
3162 if (cfun->machine->ia64_eh_epilogue_bsp)
3163 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3166 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3169 int fp = GR_REG (2);
3170 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3171 first available call clobbered register. If there was a frame_pointer
3172 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3173 so we have to make sure we're using the string "r2" when emitting
3174 the register name for the assembler. */
3175 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
3176 fp = HARD_FRAME_POINTER_REGNUM;
3178 /* We must emit an alloc to force the input registers to become output
3179 registers. Otherwise, if the callee tries to pass its parameters
3180 through to another call without an intervening alloc, then these
3182 /* ??? We don't need to preserve all input registers. We only need to
3183 preserve those input registers used as arguments to the sibling call.
3184 It is unclear how to compute that number here. */
3185 if (current_frame_info.n_input_regs != 0)
3186 emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3187 const0_rtx, const0_rtx,
3188 GEN_INT (current_frame_info.n_input_regs),
3193 /* Return 1 if br.ret can do all the work required to return from a
3197 ia64_direct_return (void)
3199 if (reload_completed && ! frame_pointer_needed)
3201 ia64_compute_frame_size (get_frame_size ());
3203 return (current_frame_info.total_size == 0
3204 && current_frame_info.n_spilled == 0
3205 && current_frame_info.reg_save_b0 == 0
3206 && current_frame_info.reg_save_pr == 0
3207 && current_frame_info.reg_save_ar_pfs == 0
3208 && current_frame_info.reg_save_ar_unat == 0
3209 && current_frame_info.reg_save_ar_lc == 0);
3214 /* Return the magic cookie that we use to hold the return address
3215 during early compilation. */
3218 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3222 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3225 /* Split this value after reload, now that we know where the return
3226 address is saved. */
3229 ia64_split_return_addr_rtx (rtx dest)
3233 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3235 if (current_frame_info.reg_save_b0 != 0)
3236 src = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3242 /* Compute offset from CFA for BR0. */
3243 /* ??? Must be kept in sync with ia64_expand_prologue. */
3244 off = (current_frame_info.spill_cfa_off
3245 + current_frame_info.spill_size);
3246 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3247 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3250 /* Convert CFA offset to a register based offset. */
3251 if (frame_pointer_needed)
3252 src = hard_frame_pointer_rtx;
3255 src = stack_pointer_rtx;
3256 off += current_frame_info.total_size;
3259 /* Load address into scratch register. */
3260 if (CONST_OK_FOR_I (off))
3261 emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
3264 emit_move_insn (dest, GEN_INT (off));
3265 emit_insn (gen_adddi3 (dest, src, dest));
3268 src = gen_rtx_MEM (Pmode, dest);
3272 src = gen_rtx_REG (DImode, BR_REG (0));
3274 emit_move_insn (dest, src);
3278 ia64_hard_regno_rename_ok (int from, int to)
3280 /* Don't clobber any of the registers we reserved for the prologue. */
3281 if (to == current_frame_info.reg_fp
3282 || to == current_frame_info.reg_save_b0
3283 || to == current_frame_info.reg_save_pr
3284 || to == current_frame_info.reg_save_ar_pfs
3285 || to == current_frame_info.reg_save_ar_unat
3286 || to == current_frame_info.reg_save_ar_lc)
3289 if (from == current_frame_info.reg_fp
3290 || from == current_frame_info.reg_save_b0
3291 || from == current_frame_info.reg_save_pr
3292 || from == current_frame_info.reg_save_ar_pfs
3293 || from == current_frame_info.reg_save_ar_unat
3294 || from == current_frame_info.reg_save_ar_lc)
3297 /* Don't use output registers outside the register frame. */
3298 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3301 /* Retain even/oddness on predicate register pairs. */
3302 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3303 return (from & 1) == (to & 1);
3308 /* Target hook for assembling integer objects. Handle word-sized
3309 aligned objects and detect the cases when @fptr is needed. */
3312 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3314 if (size == POINTER_SIZE / BITS_PER_UNIT
3316 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3317 && GET_CODE (x) == SYMBOL_REF
3318 && SYMBOL_REF_FUNCTION_P (x))
3320 if (POINTER_SIZE == 32)
3321 fputs ("\tdata4\t@fptr(", asm_out_file);
3323 fputs ("\tdata8\t@fptr(", asm_out_file);
3324 output_addr_const (asm_out_file, x);
3325 fputs (")\n", asm_out_file);
3328 return default_assemble_integer (x, size, aligned_p);
3331 /* Emit the function prologue. */
3334 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3336 int mask, grsave, grsave_prev;
3338 if (current_frame_info.need_regstk)
3339 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3340 current_frame_info.n_input_regs,
3341 current_frame_info.n_local_regs,
3342 current_frame_info.n_output_regs,
3343 current_frame_info.n_rotate_regs);
3345 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3348 /* Emit the .prologue directive. */
3351 grsave = grsave_prev = 0;
3352 if (current_frame_info.reg_save_b0 != 0)
3355 grsave = grsave_prev = current_frame_info.reg_save_b0;
3357 if (current_frame_info.reg_save_ar_pfs != 0
3358 && (grsave_prev == 0
3359 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3362 if (grsave_prev == 0)
3363 grsave = current_frame_info.reg_save_ar_pfs;
3364 grsave_prev = current_frame_info.reg_save_ar_pfs;
3366 if (current_frame_info.reg_fp != 0
3367 && (grsave_prev == 0
3368 || current_frame_info.reg_fp == grsave_prev + 1))
3371 if (grsave_prev == 0)
3372 grsave = HARD_FRAME_POINTER_REGNUM;
3373 grsave_prev = current_frame_info.reg_fp;
3375 if (current_frame_info.reg_save_pr != 0
3376 && (grsave_prev == 0
3377 || current_frame_info.reg_save_pr == grsave_prev + 1))
3380 if (grsave_prev == 0)
3381 grsave = current_frame_info.reg_save_pr;
3384 if (mask && TARGET_GNU_AS)
3385 fprintf (file, "\t.prologue %d, %d\n", mask,
3386 ia64_dbx_register_number (grsave));
3388 fputs ("\t.prologue\n", file);
3390 /* Emit a .spill directive, if necessary, to relocate the base of
3391 the register spill area. */
3392 if (current_frame_info.spill_cfa_off != -16)
3393 fprintf (file, "\t.spill %ld\n",
3394 (long) (current_frame_info.spill_cfa_off
3395 + current_frame_info.spill_size));
3398 /* Emit the .body directive at the scheduled end of the prologue. */
3401 ia64_output_function_end_prologue (FILE *file)
3403 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3406 fputs ("\t.body\n", file);
3409 /* Emit the function epilogue. */
3412 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3413 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3417 if (current_frame_info.reg_fp)
3419 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3420 reg_names[HARD_FRAME_POINTER_REGNUM]
3421 = reg_names[current_frame_info.reg_fp];
3422 reg_names[current_frame_info.reg_fp] = tmp;
3424 if (! TARGET_REG_NAMES)
3426 for (i = 0; i < current_frame_info.n_input_regs; i++)
3427 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3428 for (i = 0; i < current_frame_info.n_local_regs; i++)
3429 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3430 for (i = 0; i < current_frame_info.n_output_regs; i++)
3431 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3434 current_frame_info.initialized = 0;
3438 ia64_dbx_register_number (int regno)
3440 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3441 from its home at loc79 to something inside the register frame. We
3442 must perform the same renumbering here for the debug info. */
3443 if (current_frame_info.reg_fp)
3445 if (regno == HARD_FRAME_POINTER_REGNUM)
3446 regno = current_frame_info.reg_fp;
3447 else if (regno == current_frame_info.reg_fp)
3448 regno = HARD_FRAME_POINTER_REGNUM;
3451 if (IN_REGNO_P (regno))
3452 return 32 + regno - IN_REG (0);
3453 else if (LOC_REGNO_P (regno))
3454 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3455 else if (OUT_REGNO_P (regno))
3456 return (32 + current_frame_info.n_input_regs
3457 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3463 ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
3465 rtx addr_reg, eight = GEN_INT (8);
3467 /* The Intel assembler requires that the global __ia64_trampoline symbol
3468 be declared explicitly */
3471 static bool declared_ia64_trampoline = false;
3473 if (!declared_ia64_trampoline)
3475 declared_ia64_trampoline = true;
3476 (*targetm.asm_out.globalize_label) (asm_out_file,
3477 "__ia64_trampoline");
3481 /* Load up our iterator. */
3482 addr_reg = gen_reg_rtx (Pmode);
3483 emit_move_insn (addr_reg, addr);
3485 /* The first two words are the fake descriptor:
3486 __ia64_trampoline, ADDR+16. */
3487 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3488 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3489 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3491 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3492 copy_to_reg (plus_constant (addr, 16)));
3493 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3495 /* The third word is the target descriptor. */
3496 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3497 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3499 /* The fourth word is the static chain. */
3500 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3503 /* Do any needed setup for a variadic function. CUM has not been updated
3504 for the last named argument which has type TYPE and mode MODE.
3506 We generate the actual spill instructions during prologue generation. */
3509 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3510 tree type, int * pretend_size,
3511 int second_time ATTRIBUTE_UNUSED)
3513 CUMULATIVE_ARGS next_cum = *cum;
3515 /* Skip the current argument. */
3516 ia64_function_arg_advance (&next_cum, mode, type, 1);
3518 if (next_cum.words < MAX_ARGUMENT_SLOTS)
3520 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
3521 *pretend_size = n * UNITS_PER_WORD;
3522 cfun->machine->n_varargs = n;
3526 /* Check whether TYPE is a homogeneous floating point aggregate. If
3527 it is, return the mode of the floating point type that appears
3528 in all leafs. If it is not, return VOIDmode.
3530 An aggregate is a homogeneous floating point aggregate is if all
3531 fields/elements in it have the same floating point type (e.g,
3532 SFmode). 128-bit quad-precision floats are excluded. */
3534 static enum machine_mode
3535 hfa_element_mode (tree type, int nested)
3537 enum machine_mode element_mode = VOIDmode;
3538 enum machine_mode mode;
3539 enum tree_code code = TREE_CODE (type);
3540 int know_element_mode = 0;
3545 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3546 case BOOLEAN_TYPE: case CHAR_TYPE: case POINTER_TYPE:
3547 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3548 case FILE_TYPE: case SET_TYPE: case LANG_TYPE:
3552 /* Fortran complex types are supposed to be HFAs, so we need to handle
3553 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3556 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3557 && TYPE_MODE (type) != TCmode)
3558 return GET_MODE_INNER (TYPE_MODE (type));
3563 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3564 mode if this is contained within an aggregate. */
3565 if (nested && TYPE_MODE (type) != TFmode)
3566 return TYPE_MODE (type);
3571 return hfa_element_mode (TREE_TYPE (type), 1);
3575 case QUAL_UNION_TYPE:
3576 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3578 if (TREE_CODE (t) != FIELD_DECL)
3581 mode = hfa_element_mode (TREE_TYPE (t), 1);
3582 if (know_element_mode)
3584 if (mode != element_mode)
3587 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3591 know_element_mode = 1;
3592 element_mode = mode;
3595 return element_mode;
3598 /* If we reach here, we probably have some front-end specific type
3599 that the backend doesn't know about. This can happen via the
3600 aggregate_value_p call in init_function_start. All we can do is
3601 ignore unknown tree types. */
3608 /* Return the number of words required to hold a quantity of TYPE and MODE
3609 when passed as an argument. */
3611 ia64_function_arg_words (tree type, enum machine_mode mode)
3615 if (mode == BLKmode)
3616 words = int_size_in_bytes (type);
3618 words = GET_MODE_SIZE (mode);
3620 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
3623 /* Return the number of registers that should be skipped so the current
3624 argument (described by TYPE and WORDS) will be properly aligned.
3626 Integer and float arguments larger than 8 bytes start at the next
3627 even boundary. Aggregates larger than 8 bytes start at the next
3628 even boundary if the aggregate has 16 byte alignment. Note that
3629 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3630 but are still to be aligned in registers.
3632 ??? The ABI does not specify how to handle aggregates with
3633 alignment from 9 to 15 bytes, or greater than 16. We handle them
3634 all as if they had 16 byte alignment. Such aggregates can occur
3635 only if gcc extensions are used. */
3637 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
3639 if ((cum->words & 1) == 0)
3643 && TREE_CODE (type) != INTEGER_TYPE
3644 && TREE_CODE (type) != REAL_TYPE)
3645 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
3650 /* Return rtx for register where argument is passed, or zero if it is passed
3652 /* ??? 128-bit quad-precision floats are always passed in general
3656 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
3657 int named, int incoming)
3659 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
3660 int words = ia64_function_arg_words (type, mode);
3661 int offset = ia64_function_arg_offset (cum, type, words);
3662 enum machine_mode hfa_mode = VOIDmode;
3664 /* If all argument slots are used, then it must go on the stack. */
3665 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3668 /* Check for and handle homogeneous FP aggregates. */
3670 hfa_mode = hfa_element_mode (type, 0);
3672 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3673 and unprototyped hfas are passed specially. */
3674 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3678 int fp_regs = cum->fp_regs;
3679 int int_regs = cum->words + offset;
3680 int hfa_size = GET_MODE_SIZE (hfa_mode);
3684 /* If prototyped, pass it in FR regs then GR regs.
3685 If not prototyped, pass it in both FR and GR regs.
3687 If this is an SFmode aggregate, then it is possible to run out of
3688 FR regs while GR regs are still left. In that case, we pass the
3689 remaining part in the GR regs. */
3691 /* Fill the FP regs. We do this always. We stop if we reach the end
3692 of the argument, the last FP register, or the last argument slot. */
3694 byte_size = ((mode == BLKmode)
3695 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3696 args_byte_size = int_regs * UNITS_PER_WORD;
3698 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3699 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
3701 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3702 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
3706 args_byte_size += hfa_size;
3710 /* If no prototype, then the whole thing must go in GR regs. */
3711 if (! cum->prototype)
3713 /* If this is an SFmode aggregate, then we might have some left over
3714 that needs to go in GR regs. */
3715 else if (byte_size != offset)
3716 int_regs += offset / UNITS_PER_WORD;
3718 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3720 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
3722 enum machine_mode gr_mode = DImode;
3723 unsigned int gr_size;
3725 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3726 then this goes in a GR reg left adjusted/little endian, right
3727 adjusted/big endian. */
3728 /* ??? Currently this is handled wrong, because 4-byte hunks are
3729 always right adjusted/little endian. */
3732 /* If we have an even 4 byte hunk because the aggregate is a
3733 multiple of 4 bytes in size, then this goes in a GR reg right
3734 adjusted/little endian. */
3735 else if (byte_size - offset == 4)
3738 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3739 gen_rtx_REG (gr_mode, (basereg
3743 gr_size = GET_MODE_SIZE (gr_mode);
3745 if (gr_size == UNITS_PER_WORD
3746 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
3748 else if (gr_size > UNITS_PER_WORD)
3749 int_regs += gr_size / UNITS_PER_WORD;
3752 /* If we ended up using just one location, just return that one loc, but
3753 change the mode back to the argument mode. */
3755 return gen_rtx_REG (mode, REGNO (XEXP (loc[0], 0)));
3757 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3760 /* Integral and aggregates go in general registers. If we have run out of
3761 FR registers, then FP values must also go in general registers. This can
3762 happen when we have a SFmode HFA. */
3763 else if (mode == TFmode || mode == TCmode
3764 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
3766 int byte_size = ((mode == BLKmode)
3767 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3768 if (BYTES_BIG_ENDIAN
3769 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
3770 && byte_size < UNITS_PER_WORD
3773 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3774 gen_rtx_REG (DImode,
3775 (basereg + cum->words
3778 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
3781 return gen_rtx_REG (mode, basereg + cum->words + offset);
3785 /* If there is a prototype, then FP values go in a FR register when
3786 named, and in a GR register when unnamed. */
3787 else if (cum->prototype)
3790 return gen_rtx_REG (mode, basereg + cum->words + offset);
3792 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
3794 /* If there is no prototype, then FP values go in both FR and GR
3798 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
3799 gen_rtx_REG (mode, (FR_ARG_FIRST
3802 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3804 (basereg + cum->words
3808 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
3812 /* Return number of words, at the beginning of the argument, that must be
3813 put in registers. 0 is the argument is entirely in registers or entirely
3817 ia64_function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3818 tree type, int named ATTRIBUTE_UNUSED)
3820 int words = ia64_function_arg_words (type, mode);
3821 int offset = ia64_function_arg_offset (cum, type, words);
3823 /* If all argument slots are used, then it must go on the stack. */
3824 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3827 /* It doesn't matter whether the argument goes in FR or GR regs. If
3828 it fits within the 8 argument slots, then it goes entirely in
3829 registers. If it extends past the last argument slot, then the rest
3830 goes on the stack. */
3832 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
3835 return MAX_ARGUMENT_SLOTS - cum->words - offset;
3838 /* Update CUM to point after this argument. This is patterned after
3839 ia64_function_arg. */
3842 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3843 tree type, int named)
3845 int words = ia64_function_arg_words (type, mode);
3846 int offset = ia64_function_arg_offset (cum, type, words);
3847 enum machine_mode hfa_mode = VOIDmode;
3849 /* If all arg slots are already full, then there is nothing to do. */
3850 if (cum->words >= MAX_ARGUMENT_SLOTS)
3853 cum->words += words + offset;
3855 /* Check for and handle homogeneous FP aggregates. */
3857 hfa_mode = hfa_element_mode (type, 0);
3859 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3860 and unprototyped hfas are passed specially. */
3861 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3863 int fp_regs = cum->fp_regs;
3864 /* This is the original value of cum->words + offset. */
3865 int int_regs = cum->words - words;
3866 int hfa_size = GET_MODE_SIZE (hfa_mode);
3870 /* If prototyped, pass it in FR regs then GR regs.
3871 If not prototyped, pass it in both FR and GR regs.
3873 If this is an SFmode aggregate, then it is possible to run out of
3874 FR regs while GR regs are still left. In that case, we pass the
3875 remaining part in the GR regs. */
3877 /* Fill the FP regs. We do this always. We stop if we reach the end
3878 of the argument, the last FP register, or the last argument slot. */
3880 byte_size = ((mode == BLKmode)
3881 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3882 args_byte_size = int_regs * UNITS_PER_WORD;
3884 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3885 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
3888 args_byte_size += hfa_size;
3892 cum->fp_regs = fp_regs;
3895 /* Integral and aggregates go in general registers. If we have run out of
3896 FR registers, then FP values must also go in general registers. This can
3897 happen when we have a SFmode HFA. */
3898 else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
3899 cum->int_regs = cum->words;
3901 /* If there is a prototype, then FP values go in a FR register when
3902 named, and in a GR register when unnamed. */
3903 else if (cum->prototype)
3906 cum->int_regs = cum->words;
3908 /* ??? Complex types should not reach here. */
3909 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3911 /* If there is no prototype, then FP values go in both FR and GR
3915 /* ??? Complex types should not reach here. */
3916 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3917 cum->int_regs = cum->words;
3921 /* Variable sized types are passed by reference. */
3922 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3925 ia64_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3926 enum machine_mode mode ATTRIBUTE_UNUSED,
3927 tree type, int named ATTRIBUTE_UNUSED)
3929 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3932 /* True if it is OK to do sibling call optimization for the specified
3933 call expression EXP. DECL will be the called function, or NULL if
3934 this is an indirect call. */
3936 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3938 /* We must always return with our current GP. This means we can
3939 only sibcall to functions defined in the current module. */
3940 return decl && (*targetm.binds_local_p) (decl);
3944 /* Implement va_arg. */
3947 ia64_va_arg (tree valist, tree type)
3951 /* Variable sized types are passed by reference. */
3952 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
3954 rtx addr = force_reg (ptr_mode,
3955 std_expand_builtin_va_arg (valist, build_pointer_type (type)));
3956 #ifdef POINTERS_EXTEND_UNSIGNED
3957 addr = convert_memory_address (Pmode, addr);
3959 return gen_rtx_MEM (ptr_mode, addr);
3962 /* Aggregate arguments with alignment larger than 8 bytes start at
3963 the next even boundary. Integer and floating point arguments
3964 do so if they are larger than 8 bytes, whether or not they are
3965 also aligned larger than 8 bytes. */
3966 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
3967 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3969 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
3970 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
3971 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
3972 build_int_2 (-2 * UNITS_PER_WORD, -1));
3973 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
3974 TREE_SIDE_EFFECTS (t) = 1;
3975 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3978 return std_expand_builtin_va_arg (valist, type);
3981 /* Return 1 if function return value returned in memory. Return 0 if it is
3985 ia64_return_in_memory (tree valtype, tree fntype ATTRIBUTE_UNUSED)
3987 enum machine_mode mode;
3988 enum machine_mode hfa_mode;
3989 HOST_WIDE_INT byte_size;
3991 mode = TYPE_MODE (valtype);
3992 byte_size = GET_MODE_SIZE (mode);
3993 if (mode == BLKmode)
3995 byte_size = int_size_in_bytes (valtype);
4000 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4002 hfa_mode = hfa_element_mode (valtype, 0);
4003 if (hfa_mode != VOIDmode)
4005 int hfa_size = GET_MODE_SIZE (hfa_mode);
4007 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4012 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4018 /* Return rtx for register that holds the function return value. */
4021 ia64_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
4023 enum machine_mode mode;
4024 enum machine_mode hfa_mode;
4026 mode = TYPE_MODE (valtype);
4027 hfa_mode = hfa_element_mode (valtype, 0);
4029 if (hfa_mode != VOIDmode)
4037 hfa_size = GET_MODE_SIZE (hfa_mode);
4038 byte_size = ((mode == BLKmode)
4039 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4041 for (i = 0; offset < byte_size; i++)
4043 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4044 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4050 return XEXP (loc[0], 0);
4052 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4054 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4055 return gen_rtx_REG (mode, FR_ARG_FIRST);
4058 if (BYTES_BIG_ENDIAN
4059 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4067 bytesize = int_size_in_bytes (valtype);
4068 for (i = 0; offset < bytesize; i++)
4070 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4071 gen_rtx_REG (DImode,
4074 offset += UNITS_PER_WORD;
4076 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4079 return gen_rtx_REG (mode, GR_RET_FIRST);
4083 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
4084 We need to emit DTP-relative relocations. */
4087 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4091 fputs ("\tdata8.ua\t@dtprel(", file);
4092 output_addr_const (file, x);
4096 /* Print a memory address as an operand to reference that memory location. */
4098 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4099 also call this from ia64_print_operand for memory addresses. */
4102 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4103 rtx address ATTRIBUTE_UNUSED)
4107 /* Print an operand to an assembler instruction.
4108 C Swap and print a comparison operator.
4109 D Print an FP comparison operator.
4110 E Print 32 - constant, for SImode shifts as extract.
4111 e Print 64 - constant, for DImode rotates.
4112 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4113 a floating point register emitted normally.
4114 I Invert a predicate register by adding 1.
4115 J Select the proper predicate register for a condition.
4116 j Select the inverse predicate register for a condition.
4117 O Append .acq for volatile load.
4118 P Postincrement of a MEM.
4119 Q Append .rel for volatile store.
4120 S Shift amount for shladd instruction.
4121 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4122 for Intel assembler.
4123 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4124 for Intel assembler.
4125 r Print register name, or constant 0 as r0. HP compatibility for
4128 ia64_print_operand (FILE * file, rtx x, int code)
4135 /* Handled below. */
4140 enum rtx_code c = swap_condition (GET_CODE (x));
4141 fputs (GET_RTX_NAME (c), file);
4146 switch (GET_CODE (x))
4158 str = GET_RTX_NAME (GET_CODE (x));
4165 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4169 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4173 if (x == CONST0_RTX (GET_MODE (x)))
4174 str = reg_names [FR_REG (0)];
4175 else if (x == CONST1_RTX (GET_MODE (x)))
4176 str = reg_names [FR_REG (1)];
4177 else if (GET_CODE (x) == REG)
4178 str = reg_names [REGNO (x)];
4185 fputs (reg_names [REGNO (x) + 1], file);
4191 unsigned int regno = REGNO (XEXP (x, 0));
4192 if (GET_CODE (x) == EQ)
4196 fputs (reg_names [regno], file);
4201 if (MEM_VOLATILE_P (x))
4202 fputs(".acq", file);
4207 HOST_WIDE_INT value;
4209 switch (GET_CODE (XEXP (x, 0)))
4215 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
4216 if (GET_CODE (x) == CONST_INT)
4218 else if (GET_CODE (x) == REG)
4220 fprintf (file, ", %s", reg_names[REGNO (x)]);
4228 value = GET_MODE_SIZE (GET_MODE (x));
4232 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
4236 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
4241 if (MEM_VOLATILE_P (x))
4242 fputs(".rel", file);
4246 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4250 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4252 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
4258 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4260 const char *prefix = "0x";
4261 if (INTVAL (x) & 0x80000000)
4263 fprintf (file, "0xffffffff");
4266 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
4272 /* If this operand is the constant zero, write it as register zero.
4273 Any register, zero, or CONST_INT value is OK here. */
4274 if (GET_CODE (x) == REG)
4275 fputs (reg_names[REGNO (x)], file);
4276 else if (x == CONST0_RTX (GET_MODE (x)))
4278 else if (GET_CODE (x) == CONST_INT)
4279 output_addr_const (file, x);
4281 output_operand_lossage ("invalid %%r value");
4288 /* For conditional branches, returns or calls, substitute
4289 sptk, dptk, dpnt, or spnt for %s. */
4290 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4293 int pred_val = INTVAL (XEXP (x, 0));
4295 /* Guess top and bottom 10% statically predicted. */
4296 if (pred_val < REG_BR_PROB_BASE / 50)
4298 else if (pred_val < REG_BR_PROB_BASE / 2)
4300 else if (pred_val < REG_BR_PROB_BASE / 100 * 98)
4305 else if (GET_CODE (current_output_insn) == CALL_INSN)
4310 fputs (which, file);
4315 x = current_insn_predicate;
4318 unsigned int regno = REGNO (XEXP (x, 0));
4319 if (GET_CODE (x) == EQ)
4321 fprintf (file, "(%s) ", reg_names [regno]);
4326 output_operand_lossage ("ia64_print_operand: unknown code");
4330 switch (GET_CODE (x))
4332 /* This happens for the spill/restore instructions. */
4337 /* ... fall through ... */
4340 fputs (reg_names [REGNO (x)], file);
4345 rtx addr = XEXP (x, 0);
4346 if (GET_RTX_CLASS (GET_CODE (addr)) == 'a')
4347 addr = XEXP (addr, 0);
4348 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4353 output_addr_const (file, x);
4360 /* Compute a (partial) cost for rtx X. Return true if the complete
4361 cost has been computed, and false if subexpressions should be
4362 scanned. In either case, *TOTAL contains the cost result. */
4363 /* ??? This is incomplete. */
4366 ia64_rtx_costs (rtx x, int code, int outer_code, int *total)
4374 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4377 if (CONST_OK_FOR_I (INTVAL (x)))
4379 else if (CONST_OK_FOR_J (INTVAL (x)))
4382 *total = COSTS_N_INSNS (1);
4385 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4388 *total = COSTS_N_INSNS (1);
4393 *total = COSTS_N_INSNS (1);
4399 *total = COSTS_N_INSNS (3);
4403 /* For multiplies wider than HImode, we have to go to the FPU,
4404 which normally involves copies. Plus there's the latency
4405 of the multiply itself, and the latency of the instructions to
4406 transfer integer regs to FP regs. */
4407 /* ??? Check for FP mode. */
4408 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4409 *total = COSTS_N_INSNS (10);
4411 *total = COSTS_N_INSNS (2);
4419 *total = COSTS_N_INSNS (1);
4426 /* We make divide expensive, so that divide-by-constant will be
4427 optimized to a multiply. */
4428 *total = COSTS_N_INSNS (60);
4436 /* Calculate the cost of moving data from a register in class FROM to
4437 one in class TO, using MODE. */
4440 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
4443 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4444 if (to == ADDL_REGS)
4446 if (from == ADDL_REGS)
4449 /* All costs are symmetric, so reduce cases by putting the
4450 lower number class as the destination. */
4453 enum reg_class tmp = to;
4454 to = from, from = tmp;
4457 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4458 so that we get secondary memory reloads. Between FR_REGS,
4459 we have to make this at least as expensive as MEMORY_MOVE_COST
4460 to avoid spectacularly poor register class preferencing. */
4463 if (to != GR_REGS || from != GR_REGS)
4464 return MEMORY_MOVE_COST (mode, to, 0);
4472 /* Moving between PR registers takes two insns. */
4473 if (from == PR_REGS)
4475 /* Moving between PR and anything but GR is impossible. */
4476 if (from != GR_REGS)
4477 return MEMORY_MOVE_COST (mode, to, 0);
4481 /* Moving between BR and anything but GR is impossible. */
4482 if (from != GR_REGS && from != GR_AND_BR_REGS)
4483 return MEMORY_MOVE_COST (mode, to, 0);
4488 /* Moving between AR and anything but GR is impossible. */
4489 if (from != GR_REGS)
4490 return MEMORY_MOVE_COST (mode, to, 0);
4495 case GR_AND_FR_REGS:
4496 case GR_AND_BR_REGS:
4507 /* This function returns the register class required for a secondary
4508 register when copying between one of the registers in CLASS, and X,
4509 using MODE. A return value of NO_REGS means that no secondary register
4513 ia64_secondary_reload_class (enum reg_class class,
4514 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
4518 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4519 regno = true_regnum (x);
4526 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4527 interaction. We end up with two pseudos with overlapping lifetimes
4528 both of which are equiv to the same constant, and both which need
4529 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4530 changes depending on the path length, which means the qty_first_reg
4531 check in make_regs_eqv can give different answers at different times.
4532 At some point I'll probably need a reload_indi pattern to handle
4535 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4536 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4537 non-general registers for good measure. */
4538 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4541 /* This is needed if a pseudo used as a call_operand gets spilled to a
4543 if (GET_CODE (x) == MEM)
4548 /* Need to go through general registers to get to other class regs. */
4549 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4552 /* This can happen when a paradoxical subreg is an operand to the
4554 /* ??? This shouldn't be necessary after instruction scheduling is
4555 enabled, because paradoxical subregs are not accepted by
4556 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4557 stop the paradoxical subreg stupidity in the *_operand functions
4559 if (GET_CODE (x) == MEM
4560 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
4561 || GET_MODE (x) == QImode))
4564 /* This can happen because of the ior/and/etc patterns that accept FP
4565 registers as operands. If the third operand is a constant, then it
4566 needs to be reloaded into a FP register. */
4567 if (GET_CODE (x) == CONST_INT)
4570 /* This can happen because of register elimination in a muldi3 insn.
4571 E.g. `26107 * (unsigned long)&u'. */
4572 if (GET_CODE (x) == PLUS)
4577 /* ??? This happens if we cse/gcse a BImode value across a call,
4578 and the function has a nonlocal goto. This is because global
4579 does not allocate call crossing pseudos to hard registers when
4580 current_function_has_nonlocal_goto is true. This is relatively
4581 common for C++ programs that use exceptions. To reproduce,
4582 return NO_REGS and compile libstdc++. */
4583 if (GET_CODE (x) == MEM)
4586 /* This can happen when we take a BImode subreg of a DImode value,
4587 and that DImode value winds up in some non-GR register. */
4588 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
4600 /* Emit text to declare externally defined variables and functions, because
4601 the Intel assembler does not support undefined externals. */
4604 ia64_asm_output_external (FILE *file, tree decl, const char *name)
4606 int save_referenced;
4608 /* GNU as does not need anything here, but the HP linker does need
4609 something for external functions. */
4613 || TREE_CODE (decl) != FUNCTION_DECL
4614 || strstr (name, "__builtin_") == name))
4617 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4618 the linker when we do this, so we need to be careful not to do this for
4619 builtin functions which have no library equivalent. Unfortunately, we
4620 can't tell here whether or not a function will actually be called by
4621 expand_expr, so we pull in library functions even if we may not need
4623 if (! strcmp (name, "__builtin_next_arg")
4624 || ! strcmp (name, "alloca")
4625 || ! strcmp (name, "__builtin_constant_p")
4626 || ! strcmp (name, "__builtin_args_info"))
4630 ia64_hpux_add_extern_decl (name);
4633 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4635 save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
4636 if (TREE_CODE (decl) == FUNCTION_DECL)
4637 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
4638 (*targetm.asm_out.globalize_label) (file, name);
4639 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
4643 /* Parse the -mfixed-range= option string. */
4646 fix_range (const char *const_str)
4649 char *str, *dash, *comma;
4651 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4652 REG2 are either register names or register numbers. The effect
4653 of this option is to mark the registers in the range from REG1 to
4654 REG2 as ``fixed'' so they won't be used by the compiler. This is
4655 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4657 i = strlen (const_str);
4658 str = (char *) alloca (i + 1);
4659 memcpy (str, const_str, i + 1);
4663 dash = strchr (str, '-');
4666 warning ("value of -mfixed-range must have form REG1-REG2");
4671 comma = strchr (dash + 1, ',');
4675 first = decode_reg_name (str);
4678 warning ("unknown register name: %s", str);
4682 last = decode_reg_name (dash + 1);
4685 warning ("unknown register name: %s", dash + 1);
4693 warning ("%s-%s is an empty range", str, dash + 1);
4697 for (i = first; i <= last; ++i)
4698 fixed_regs[i] = call_used_regs[i] = 1;
4708 static struct machine_function *
4709 ia64_init_machine_status (void)
4711 return ggc_alloc_cleared (sizeof (struct machine_function));
4714 /* Handle TARGET_OPTIONS switches. */
4717 ia64_override_options (void)
4721 const char *const name; /* processor name or nickname. */
4722 const enum processor_type processor;
4724 const processor_alias_table[] =
4726 {"itanium", PROCESSOR_ITANIUM},
4727 {"itanium1", PROCESSOR_ITANIUM},
4728 {"merced", PROCESSOR_ITANIUM},
4729 {"itanium2", PROCESSOR_ITANIUM2},
4730 {"mckinley", PROCESSOR_ITANIUM2},
4733 int const pta_size = ARRAY_SIZE (processor_alias_table);
4736 if (TARGET_AUTO_PIC)
4737 target_flags |= MASK_CONST_GP;
4739 if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
4741 warning ("cannot optimize floating point division for both latency and throughput");
4742 target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
4745 if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
4747 warning ("cannot optimize integer division for both latency and throughput");
4748 target_flags &= ~MASK_INLINE_INT_DIV_THR;
4751 if (TARGET_INLINE_SQRT_LAT && TARGET_INLINE_SQRT_THR)
4753 warning ("cannot optimize square root for both latency and throughput");
4754 target_flags &= ~MASK_INLINE_SQRT_THR;
4757 if (TARGET_INLINE_SQRT_LAT)
4759 warning ("not yet implemented: latency-optimized inline square root");
4760 target_flags &= ~MASK_INLINE_SQRT_LAT;
4763 if (ia64_fixed_range_string)
4764 fix_range (ia64_fixed_range_string);
4766 if (ia64_tls_size_string)
4769 unsigned long tmp = strtoul (ia64_tls_size_string, &end, 10);
4770 if (*end || (tmp != 14 && tmp != 22 && tmp != 64))
4771 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string);
4773 ia64_tls_size = tmp;
4776 if (!ia64_tune_string)
4777 ia64_tune_string = "itanium2";
4779 for (i = 0; i < pta_size; i++)
4780 if (! strcmp (ia64_tune_string, processor_alias_table[i].name))
4782 ia64_tune = processor_alias_table[i].processor;
4787 error ("bad value (%s) for -tune= switch", ia64_tune_string);
4789 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
4790 flag_schedule_insns_after_reload = 0;
4792 /* Variable tracking should be run after all optimizations which change order
4793 of insns. It also needs a valid CFG. */
4794 ia64_flag_var_tracking = flag_var_tracking;
4795 flag_var_tracking = 0;
4797 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
4799 init_machine_status = ia64_init_machine_status;
4802 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
4803 static enum attr_type ia64_safe_type (rtx);
4805 static enum attr_itanium_class
4806 ia64_safe_itanium_class (rtx insn)
4808 if (recog_memoized (insn) >= 0)
4809 return get_attr_itanium_class (insn);
4811 return ITANIUM_CLASS_UNKNOWN;
4814 static enum attr_type
4815 ia64_safe_type (rtx insn)
4817 if (recog_memoized (insn) >= 0)
4818 return get_attr_type (insn);
4820 return TYPE_UNKNOWN;
4823 /* The following collection of routines emit instruction group stop bits as
4824 necessary to avoid dependencies. */
4826 /* Need to track some additional registers as far as serialization is
4827 concerned so we can properly handle br.call and br.ret. We could
4828 make these registers visible to gcc, but since these registers are
4829 never explicitly used in gcc generated code, it seems wasteful to
4830 do so (plus it would make the call and return patterns needlessly
4832 #define REG_RP (BR_REG (0))
4833 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4834 /* This is used for volatile asms which may require a stop bit immediately
4835 before and after them. */
4836 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4837 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4838 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4840 /* For each register, we keep track of how it has been written in the
4841 current instruction group.
4843 If a register is written unconditionally (no qualifying predicate),
4844 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4846 If a register is written if its qualifying predicate P is true, we
4847 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4848 may be written again by the complement of P (P^1) and when this happens,
4849 WRITE_COUNT gets set to 2.
4851 The result of this is that whenever an insn attempts to write a register
4852 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4854 If a predicate register is written by a floating-point insn, we set
4855 WRITTEN_BY_FP to true.
4857 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4858 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4860 struct reg_write_state
4862 unsigned int write_count : 2;
4863 unsigned int first_pred : 16;
4864 unsigned int written_by_fp : 1;
4865 unsigned int written_by_and : 1;
4866 unsigned int written_by_or : 1;
4869 /* Cumulative info for the current instruction group. */
4870 struct reg_write_state rws_sum[NUM_REGS];
4871 /* Info for the current instruction. This gets copied to rws_sum after a
4872 stop bit is emitted. */
4873 struct reg_write_state rws_insn[NUM_REGS];
4875 /* Indicates whether this is the first instruction after a stop bit,
4876 in which case we don't need another stop bit. Without this, we hit
4877 the abort in ia64_variable_issue when scheduling an alloc. */
4878 static int first_instruction;
4880 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4881 RTL for one instruction. */
4884 unsigned int is_write : 1; /* Is register being written? */
4885 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
4886 unsigned int is_branch : 1; /* Is register used as part of a branch? */
4887 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
4888 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
4889 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
4892 static void rws_update (struct reg_write_state *, int, struct reg_flags, int);
4893 static int rws_access_regno (int, struct reg_flags, int);
4894 static int rws_access_reg (rtx, struct reg_flags, int);
4895 static void update_set_flags (rtx, struct reg_flags *, int *, rtx *);
4896 static int set_src_needs_barrier (rtx, struct reg_flags, int, rtx);
4897 static int rtx_needs_barrier (rtx, struct reg_flags, int);
4898 static void init_insn_group_barriers (void);
4899 static int group_barrier_needed_p (rtx);
4900 static int safe_group_barrier_needed_p (rtx);
4902 /* Update *RWS for REGNO, which is being written by the current instruction,
4903 with predicate PRED, and associated register flags in FLAGS. */
4906 rws_update (struct reg_write_state *rws, int regno, struct reg_flags flags, int pred)
4909 rws[regno].write_count++;
4911 rws[regno].write_count = 2;
4912 rws[regno].written_by_fp |= flags.is_fp;
4913 /* ??? Not tracking and/or across differing predicates. */
4914 rws[regno].written_by_and = flags.is_and;
4915 rws[regno].written_by_or = flags.is_or;
4916 rws[regno].first_pred = pred;
4919 /* Handle an access to register REGNO of type FLAGS using predicate register
4920 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4921 a dependency with an earlier instruction in the same group. */
4924 rws_access_regno (int regno, struct reg_flags flags, int pred)
4926 int need_barrier = 0;
4928 if (regno >= NUM_REGS)
4931 if (! PR_REGNO_P (regno))
4932 flags.is_and = flags.is_or = 0;
4938 /* One insn writes same reg multiple times? */
4939 if (rws_insn[regno].write_count > 0)
4942 /* Update info for current instruction. */
4943 rws_update (rws_insn, regno, flags, pred);
4944 write_count = rws_sum[regno].write_count;
4946 switch (write_count)
4949 /* The register has not been written yet. */
4950 rws_update (rws_sum, regno, flags, pred);
4954 /* The register has been written via a predicate. If this is
4955 not a complementary predicate, then we need a barrier. */
4956 /* ??? This assumes that P and P+1 are always complementary
4957 predicates for P even. */
4958 if (flags.is_and && rws_sum[regno].written_by_and)
4960 else if (flags.is_or && rws_sum[regno].written_by_or)
4962 else if ((rws_sum[regno].first_pred ^ 1) != pred)
4964 rws_update (rws_sum, regno, flags, pred);
4968 /* The register has been unconditionally written already. We
4970 if (flags.is_and && rws_sum[regno].written_by_and)
4972 else if (flags.is_or && rws_sum[regno].written_by_or)
4976 rws_sum[regno].written_by_and = flags.is_and;
4977 rws_sum[regno].written_by_or = flags.is_or;
4986 if (flags.is_branch)
4988 /* Branches have several RAW exceptions that allow to avoid
4991 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
4992 /* RAW dependencies on branch regs are permissible as long
4993 as the writer is a non-branch instruction. Since we
4994 never generate code that uses a branch register written
4995 by a branch instruction, handling this case is
4999 if (REGNO_REG_CLASS (regno) == PR_REGS
5000 && ! rws_sum[regno].written_by_fp)
5001 /* The predicates of a branch are available within the
5002 same insn group as long as the predicate was written by
5003 something other than a floating-point instruction. */
5007 if (flags.is_and && rws_sum[regno].written_by_and)
5009 if (flags.is_or && rws_sum[regno].written_by_or)
5012 switch (rws_sum[regno].write_count)
5015 /* The register has not been written yet. */
5019 /* The register has been written via a predicate. If this is
5020 not a complementary predicate, then we need a barrier. */
5021 /* ??? This assumes that P and P+1 are always complementary
5022 predicates for P even. */
5023 if ((rws_sum[regno].first_pred ^ 1) != pred)
5028 /* The register has been unconditionally written already. We
5038 return need_barrier;
5042 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5044 int regno = REGNO (reg);
5045 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5048 return rws_access_regno (regno, flags, pred);
5051 int need_barrier = 0;
5053 need_barrier |= rws_access_regno (regno + n, flags, pred);
5054 return need_barrier;
5058 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5059 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5062 update_set_flags (rtx x, struct reg_flags *pflags, int *ppred, rtx *pcond)
5064 rtx src = SET_SRC (x);
5068 switch (GET_CODE (src))
5074 if (SET_DEST (x) == pc_rtx)
5075 /* X is a conditional branch. */
5079 int is_complemented = 0;
5081 /* X is a conditional move. */
5082 rtx cond = XEXP (src, 0);
5083 if (GET_CODE (cond) == EQ)
5084 is_complemented = 1;
5085 cond = XEXP (cond, 0);
5086 if (GET_CODE (cond) != REG
5087 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
5090 if (XEXP (src, 1) == SET_DEST (x)
5091 || XEXP (src, 2) == SET_DEST (x))
5093 /* X is a conditional move that conditionally writes the
5096 /* We need another complement in this case. */
5097 if (XEXP (src, 1) == SET_DEST (x))
5098 is_complemented = ! is_complemented;
5100 *ppred = REGNO (cond);
5101 if (is_complemented)
5105 /* ??? If this is a conditional write to the dest, then this
5106 instruction does not actually read one source. This probably
5107 doesn't matter, because that source is also the dest. */
5108 /* ??? Multiple writes to predicate registers are allowed
5109 if they are all AND type compares, or if they are all OR
5110 type compares. We do not generate such instructions
5113 /* ... fall through ... */
5116 if (GET_RTX_CLASS (GET_CODE (src)) == '<'
5117 && GET_MODE_CLASS (GET_MODE (XEXP (src, 0))) == MODE_FLOAT)
5118 /* Set pflags->is_fp to 1 so that we know we're dealing
5119 with a floating point comparison when processing the
5120 destination of the SET. */
5123 /* Discover if this is a parallel comparison. We only handle
5124 and.orcm and or.andcm at present, since we must retain a
5125 strict inverse on the predicate pair. */
5126 else if (GET_CODE (src) == AND)
5128 else if (GET_CODE (src) == IOR)
5135 /* Subroutine of rtx_needs_barrier; this function determines whether the
5136 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5137 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5141 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred, rtx cond)
5143 int need_barrier = 0;
5145 rtx src = SET_SRC (x);
5147 if (GET_CODE (src) == CALL)
5148 /* We don't need to worry about the result registers that
5149 get written by subroutine call. */
5150 return rtx_needs_barrier (src, flags, pred);
5151 else if (SET_DEST (x) == pc_rtx)
5153 /* X is a conditional branch. */
5154 /* ??? This seems redundant, as the caller sets this bit for
5156 flags.is_branch = 1;
5157 return rtx_needs_barrier (src, flags, pred);
5160 need_barrier = rtx_needs_barrier (src, flags, pred);
5162 /* This instruction unconditionally uses a predicate register. */
5164 need_barrier |= rws_access_reg (cond, flags, 0);
5167 if (GET_CODE (dst) == ZERO_EXTRACT)
5169 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
5170 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
5171 dst = XEXP (dst, 0);
5173 return need_barrier;
5176 /* Handle an access to rtx X of type FLAGS using predicate register
5177 PRED. Return 1 if this access creates a dependency with an earlier
5178 instruction in the same group. */
5181 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
5184 int is_complemented = 0;
5185 int need_barrier = 0;
5186 const char *format_ptr;
5187 struct reg_flags new_flags;
5195 switch (GET_CODE (x))
5198 update_set_flags (x, &new_flags, &pred, &cond);
5199 need_barrier = set_src_needs_barrier (x, new_flags, pred, cond);
5200 if (GET_CODE (SET_SRC (x)) != CALL)
5202 new_flags.is_write = 1;
5203 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
5208 new_flags.is_write = 0;
5209 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5211 /* Avoid multiple register writes, in case this is a pattern with
5212 multiple CALL rtx. This avoids an abort in rws_access_reg. */
5213 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
5215 new_flags.is_write = 1;
5216 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
5217 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
5218 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5223 /* X is a predicated instruction. */
5225 cond = COND_EXEC_TEST (x);
5228 need_barrier = rtx_needs_barrier (cond, flags, 0);
5230 if (GET_CODE (cond) == EQ)
5231 is_complemented = 1;
5232 cond = XEXP (cond, 0);
5233 if (GET_CODE (cond) != REG
5234 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
5236 pred = REGNO (cond);
5237 if (is_complemented)
5240 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
5241 return need_barrier;
5245 /* Clobber & use are for earlier compiler-phases only. */
5250 /* We always emit stop bits for traditional asms. We emit stop bits
5251 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5252 if (GET_CODE (x) != ASM_OPERANDS
5253 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5255 /* Avoid writing the register multiple times if we have multiple
5256 asm outputs. This avoids an abort in rws_access_reg. */
5257 if (! rws_insn[REG_VOLATILE].write_count)
5259 new_flags.is_write = 1;
5260 rws_access_regno (REG_VOLATILE, new_flags, pred);
5265 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5266 We can not just fall through here since then we would be confused
5267 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5268 traditional asms unlike their normal usage. */
5270 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5271 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5276 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5278 rtx pat = XVECEXP (x, 0, i);
5279 if (GET_CODE (pat) == SET)
5281 update_set_flags (pat, &new_flags, &pred, &cond);
5282 need_barrier |= set_src_needs_barrier (pat, new_flags, pred, cond);
5284 else if (GET_CODE (pat) == USE
5285 || GET_CODE (pat) == CALL
5286 || GET_CODE (pat) == ASM_OPERANDS)
5287 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5288 else if (GET_CODE (pat) != CLOBBER && GET_CODE (pat) != RETURN)
5291 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5293 rtx pat = XVECEXP (x, 0, i);
5294 if (GET_CODE (pat) == SET)
5296 if (GET_CODE (SET_SRC (pat)) != CALL)
5298 new_flags.is_write = 1;
5299 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5303 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5304 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5312 if (REGNO (x) == AR_UNAT_REGNUM)
5314 for (i = 0; i < 64; ++i)
5315 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5318 need_barrier = rws_access_reg (x, flags, pred);
5322 /* Find the regs used in memory address computation. */
5323 new_flags.is_write = 0;
5324 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5327 case CONST_INT: case CONST_DOUBLE:
5328 case SYMBOL_REF: case LABEL_REF: case CONST:
5331 /* Operators with side-effects. */
5332 case POST_INC: case POST_DEC:
5333 if (GET_CODE (XEXP (x, 0)) != REG)
5336 new_flags.is_write = 0;
5337 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5338 new_flags.is_write = 1;
5339 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5343 if (GET_CODE (XEXP (x, 0)) != REG)
5346 new_flags.is_write = 0;
5347 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5348 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5349 new_flags.is_write = 1;
5350 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5353 /* Handle common unary and binary ops for efficiency. */
5354 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5355 case MOD: case UDIV: case UMOD: case AND: case IOR:
5356 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5357 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5358 case NE: case EQ: case GE: case GT: case LE:
5359 case LT: case GEU: case GTU: case LEU: case LTU:
5360 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5361 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5364 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5365 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5366 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5367 case SQRT: case FFS: case POPCOUNT:
5368 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5372 switch (XINT (x, 1))
5374 case UNSPEC_LTOFF_DTPMOD:
5375 case UNSPEC_LTOFF_DTPREL:
5377 case UNSPEC_LTOFF_TPREL:
5379 case UNSPEC_PRED_REL_MUTEX:
5380 case UNSPEC_PIC_CALL:
5382 case UNSPEC_FETCHADD_ACQ:
5383 case UNSPEC_BSP_VALUE:
5384 case UNSPEC_FLUSHRS:
5385 case UNSPEC_BUNDLE_SELECTOR:
5388 case UNSPEC_GR_SPILL:
5389 case UNSPEC_GR_RESTORE:
5391 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5392 HOST_WIDE_INT bit = (offset >> 3) & 63;
5394 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5395 new_flags.is_write = (XINT (x, 1) == 1);
5396 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5401 case UNSPEC_FR_SPILL:
5402 case UNSPEC_FR_RESTORE:
5403 case UNSPEC_GETF_EXP:
5404 case UNSPEC_SETF_EXP:
5406 case UNSPEC_FR_SQRT_RECIP_APPROX:
5407 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5410 case UNSPEC_FR_RECIP_APPROX:
5411 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5412 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5415 case UNSPEC_CMPXCHG_ACQ:
5416 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5417 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5425 case UNSPEC_VOLATILE:
5426 switch (XINT (x, 1))
5429 /* Alloc must always be the first instruction of a group.
5430 We force this by always returning true. */
5431 /* ??? We might get better scheduling if we explicitly check for
5432 input/local/output register dependencies, and modify the
5433 scheduler so that alloc is always reordered to the start of
5434 the current group. We could then eliminate all of the
5435 first_instruction code. */
5436 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5438 new_flags.is_write = 1;
5439 rws_access_regno (REG_AR_CFM, new_flags, pred);
5442 case UNSPECV_SET_BSP:
5446 case UNSPECV_BLOCKAGE:
5447 case UNSPECV_INSN_GROUP_BARRIER:
5449 case UNSPECV_PSAC_ALL:
5450 case UNSPECV_PSAC_NORMAL:
5459 new_flags.is_write = 0;
5460 need_barrier = rws_access_regno (REG_RP, flags, pred);
5461 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5463 new_flags.is_write = 1;
5464 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5465 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5469 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5470 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5471 switch (format_ptr[i])
5473 case '0': /* unused field */
5474 case 'i': /* integer */
5475 case 'n': /* note */
5476 case 'w': /* wide integer */
5477 case 's': /* pointer to string */
5478 case 'S': /* optional pointer to string */
5482 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5487 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5488 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5497 return need_barrier;
5500 /* Clear out the state for group_barrier_needed_p at the start of a
5501 sequence of insns. */
5504 init_insn_group_barriers (void)
5506 memset (rws_sum, 0, sizeof (rws_sum));
5507 first_instruction = 1;
5510 /* Given the current state, recorded by previous calls to this function,
5511 determine whether a group barrier (a stop bit) is necessary before INSN.
5512 Return nonzero if so. */
5515 group_barrier_needed_p (rtx insn)
5518 int need_barrier = 0;
5519 struct reg_flags flags;
5521 memset (&flags, 0, sizeof (flags));
5522 switch (GET_CODE (insn))
5528 /* A barrier doesn't imply an instruction group boundary. */
5532 memset (rws_insn, 0, sizeof (rws_insn));
5536 flags.is_branch = 1;
5537 flags.is_sibcall = SIBLING_CALL_P (insn);
5538 memset (rws_insn, 0, sizeof (rws_insn));
5540 /* Don't bundle a call following another call. */
5541 if ((pat = prev_active_insn (insn))
5542 && GET_CODE (pat) == CALL_INSN)
5548 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5552 flags.is_branch = 1;
5554 /* Don't bundle a jump following a call. */
5555 if ((pat = prev_active_insn (insn))
5556 && GET_CODE (pat) == CALL_INSN)
5564 if (GET_CODE (PATTERN (insn)) == USE
5565 || GET_CODE (PATTERN (insn)) == CLOBBER)
5566 /* Don't care about USE and CLOBBER "insns"---those are used to
5567 indicate to the optimizer that it shouldn't get rid of
5568 certain operations. */
5571 pat = PATTERN (insn);
5573 /* Ug. Hack hacks hacked elsewhere. */
5574 switch (recog_memoized (insn))
5576 /* We play dependency tricks with the epilogue in order
5577 to get proper schedules. Undo this for dv analysis. */
5578 case CODE_FOR_epilogue_deallocate_stack:
5579 case CODE_FOR_prologue_allocate_stack:
5580 pat = XVECEXP (pat, 0, 0);
5583 /* The pattern we use for br.cloop confuses the code above.
5584 The second element of the vector is representative. */
5585 case CODE_FOR_doloop_end_internal:
5586 pat = XVECEXP (pat, 0, 1);
5589 /* Doesn't generate code. */
5590 case CODE_FOR_pred_rel_mutex:
5591 case CODE_FOR_prologue_use:
5598 memset (rws_insn, 0, sizeof (rws_insn));
5599 need_barrier = rtx_needs_barrier (pat, flags, 0);
5601 /* Check to see if the previous instruction was a volatile
5604 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5611 if (first_instruction && INSN_P (insn)
5612 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5613 && GET_CODE (PATTERN (insn)) != USE
5614 && GET_CODE (PATTERN (insn)) != CLOBBER)
5617 first_instruction = 0;
5620 return need_barrier;
5623 /* Like group_barrier_needed_p, but do not clobber the current state. */
5626 safe_group_barrier_needed_p (rtx insn)
5628 struct reg_write_state rws_saved[NUM_REGS];
5629 int saved_first_instruction;
5632 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
5633 saved_first_instruction = first_instruction;
5635 t = group_barrier_needed_p (insn);
5637 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
5638 first_instruction = saved_first_instruction;
5643 /* Scan the current function and insert stop bits as necessary to
5644 eliminate dependencies. This function assumes that a final
5645 instruction scheduling pass has been run which has already
5646 inserted most of the necessary stop bits. This function only
5647 inserts new ones at basic block boundaries, since these are
5648 invisible to the scheduler. */
5651 emit_insn_group_barriers (FILE *dump)
5655 int insns_since_last_label = 0;
5657 init_insn_group_barriers ();
5659 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5661 if (GET_CODE (insn) == CODE_LABEL)
5663 if (insns_since_last_label)
5665 insns_since_last_label = 0;
5667 else if (GET_CODE (insn) == NOTE
5668 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
5670 if (insns_since_last_label)
5672 insns_since_last_label = 0;
5674 else if (GET_CODE (insn) == INSN
5675 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
5676 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
5678 init_insn_group_barriers ();
5681 else if (INSN_P (insn))
5683 insns_since_last_label = 1;
5685 if (group_barrier_needed_p (insn))
5690 fprintf (dump, "Emitting stop before label %d\n",
5691 INSN_UID (last_label));
5692 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
5695 init_insn_group_barriers ();
5703 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5704 This function has to emit all necessary group barriers. */
5707 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
5711 init_insn_group_barriers ();
5713 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5715 if (GET_CODE (insn) == BARRIER)
5717 rtx last = prev_active_insn (insn);
5721 if (GET_CODE (last) == JUMP_INSN
5722 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
5723 last = prev_active_insn (last);
5724 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
5725 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
5727 init_insn_group_barriers ();
5729 else if (INSN_P (insn))
5731 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
5732 init_insn_group_barriers ();
5733 else if (group_barrier_needed_p (insn))
5735 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5736 init_insn_group_barriers ();
5737 group_barrier_needed_p (insn);
5744 static int errata_find_address_regs (rtx *, void *);
5745 static void errata_emit_nops (rtx);
5746 static void fixup_errata (void);
5748 /* This structure is used to track some details about the previous insns
5749 groups so we can determine if it may be necessary to insert NOPs to
5750 workaround hardware errata. */
5753 HARD_REG_SET p_reg_set;
5754 HARD_REG_SET gr_reg_conditionally_set;
5757 /* Index into the last_group array. */
5758 static int group_idx;
5760 /* Called through for_each_rtx; determines if a hard register that was
5761 conditionally set in the previous group is used as an address register.
5762 It ensures that for_each_rtx returns 1 in that case. */
5764 errata_find_address_regs (rtx *xp, void *data ATTRIBUTE_UNUSED)
5767 if (GET_CODE (x) != MEM)
5770 if (GET_CODE (x) == POST_MODIFY)
5772 if (GET_CODE (x) == REG)
5774 struct group *prev_group = last_group + (group_idx ^ 1);
5775 if (TEST_HARD_REG_BIT (prev_group->gr_reg_conditionally_set,
5783 /* Called for each insn; this function keeps track of the state in
5784 last_group and emits additional NOPs if necessary to work around
5785 an Itanium A/B step erratum. */
5787 errata_emit_nops (rtx insn)
5789 struct group *this_group = last_group + group_idx;
5790 struct group *prev_group = last_group + (group_idx ^ 1);
5791 rtx pat = PATTERN (insn);
5792 rtx cond = GET_CODE (pat) == COND_EXEC ? COND_EXEC_TEST (pat) : 0;
5793 rtx real_pat = cond ? COND_EXEC_CODE (pat) : pat;
5794 enum attr_type type;
5797 if (GET_CODE (real_pat) == USE
5798 || GET_CODE (real_pat) == CLOBBER
5799 || GET_CODE (real_pat) == ASM_INPUT
5800 || GET_CODE (real_pat) == ADDR_VEC
5801 || GET_CODE (real_pat) == ADDR_DIFF_VEC
5802 || asm_noperands (PATTERN (insn)) >= 0)
5805 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5808 if (GET_CODE (set) == PARALLEL)
5811 set = XVECEXP (real_pat, 0, 0);
5812 for (i = 1; i < XVECLEN (real_pat, 0); i++)
5813 if (GET_CODE (XVECEXP (real_pat, 0, i)) != USE
5814 && GET_CODE (XVECEXP (real_pat, 0, i)) != CLOBBER)
5821 if (set && GET_CODE (set) != SET)
5824 type = get_attr_type (insn);
5827 && set && REG_P (SET_DEST (set)) && PR_REGNO_P (REGNO (SET_DEST (set))))
5828 SET_HARD_REG_BIT (this_group->p_reg_set, REGNO (SET_DEST (set)));
5830 if ((type == TYPE_M || type == TYPE_A) && cond && set
5831 && REG_P (SET_DEST (set))
5832 && GET_CODE (SET_SRC (set)) != PLUS
5833 && GET_CODE (SET_SRC (set)) != MINUS
5834 && (GET_CODE (SET_SRC (set)) != ASHIFT
5835 || !shladd_operand (XEXP (SET_SRC (set), 1), VOIDmode))
5836 && (GET_CODE (SET_SRC (set)) != MEM
5837 || GET_CODE (XEXP (SET_SRC (set), 0)) != POST_MODIFY)
5838 && GENERAL_REGNO_P (REGNO (SET_DEST (set))))
5840 if (GET_RTX_CLASS (GET_CODE (cond)) != '<'
5841 || ! REG_P (XEXP (cond, 0)))
5844 if (TEST_HARD_REG_BIT (prev_group->p_reg_set, REGNO (XEXP (cond, 0))))
5845 SET_HARD_REG_BIT (this_group->gr_reg_conditionally_set, REGNO (SET_DEST (set)));
5847 if (for_each_rtx (&real_pat, errata_find_address_regs, NULL))
5849 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5850 emit_insn_before (gen_nop (), insn);
5851 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5853 memset (last_group, 0, sizeof last_group);
5857 /* Emit extra nops if they are required to work around hardware errata. */
5864 if (! TARGET_B_STEP)
5868 memset (last_group, 0, sizeof last_group);
5870 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5875 if (ia64_safe_type (insn) == TYPE_S)
5878 memset (last_group + group_idx, 0, sizeof last_group[group_idx]);
5881 errata_emit_nops (insn);
5886 /* Instruction scheduling support. */
5888 #define NR_BUNDLES 10
5890 /* A list of names of all available bundles. */
5892 static const char *bundle_name [NR_BUNDLES] =
5898 #if NR_BUNDLES == 10
5908 /* Nonzero if we should insert stop bits into the schedule. */
5910 int ia64_final_schedule = 0;
5912 /* Codes of the corresponding quieryied units: */
5914 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
5915 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
5917 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
5918 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
5920 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
5922 /* The following variable value is an insn group barrier. */
5924 static rtx dfa_stop_insn;
5926 /* The following variable value is the last issued insn. */
5928 static rtx last_scheduled_insn;
5930 /* The following variable value is size of the DFA state. */
5932 static size_t dfa_state_size;
5934 /* The following variable value is pointer to a DFA state used as
5935 temporary variable. */
5937 static state_t temp_dfa_state = NULL;
5939 /* The following variable value is DFA state after issuing the last
5942 static state_t prev_cycle_state = NULL;
5944 /* The following array element values are TRUE if the corresponding
5945 insn requires to add stop bits before it. */
5947 static char *stops_p;
5949 /* The following variable is used to set up the mentioned above array. */
5951 static int stop_before_p = 0;
5953 /* The following variable value is length of the arrays `clocks' and
5956 static int clocks_length;
5958 /* The following array element values are cycles on which the
5959 corresponding insn will be issued. The array is used only for
5964 /* The following array element values are numbers of cycles should be
5965 added to improve insn scheduling for MM_insns for Itanium1. */
5967 static int *add_cycles;
5969 static rtx ia64_single_set (rtx);
5970 static void ia64_emit_insn_before (rtx, rtx);
5972 /* Map a bundle number to its pseudo-op. */
5975 get_bundle_name (int b)
5977 return bundle_name[b];
5981 /* Return the maximum number of instructions a cpu can issue. */
5984 ia64_issue_rate (void)
5989 /* Helper function - like single_set, but look inside COND_EXEC. */
5992 ia64_single_set (rtx insn)
5994 rtx x = PATTERN (insn), ret;
5995 if (GET_CODE (x) == COND_EXEC)
5996 x = COND_EXEC_CODE (x);
5997 if (GET_CODE (x) == SET)
6000 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6001 Although they are not classical single set, the second set is there just
6002 to protect it from moving past FP-relative stack accesses. */
6003 switch (recog_memoized (insn))
6005 case CODE_FOR_prologue_allocate_stack:
6006 case CODE_FOR_epilogue_deallocate_stack:
6007 ret = XVECEXP (x, 0, 0);
6011 ret = single_set_2 (insn, x);
6018 /* Adjust the cost of a scheduling dependency. Return the new cost of
6019 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6022 ia64_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
6024 enum attr_itanium_class dep_class;
6025 enum attr_itanium_class insn_class;
6027 if (REG_NOTE_KIND (link) != REG_DEP_OUTPUT)
6030 insn_class = ia64_safe_itanium_class (insn);
6031 dep_class = ia64_safe_itanium_class (dep_insn);
6032 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6033 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6039 /* Like emit_insn_before, but skip cycle_display notes.
6040 ??? When cycle display notes are implemented, update this. */
6043 ia64_emit_insn_before (rtx insn, rtx before)
6045 emit_insn_before (insn, before);
6048 /* The following function marks insns who produce addresses for load
6049 and store insns. Such insns will be placed into M slots because it
6050 decrease latency time for Itanium1 (see function
6051 `ia64_produce_address_p' and the DFA descriptions). */
6054 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6056 rtx insn, link, next, next_tail;
6058 next_tail = NEXT_INSN (tail);
6059 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6062 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6064 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6066 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
6068 next = XEXP (link, 0);
6069 if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_ST
6070 || ia64_safe_itanium_class (next) == ITANIUM_CLASS_STF)
6071 && ia64_st_address_bypass_p (insn, next))
6073 else if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_LD
6074 || ia64_safe_itanium_class (next)
6075 == ITANIUM_CLASS_FLD)
6076 && ia64_ld_address_bypass_p (insn, next))
6079 insn->call = link != 0;
6083 /* We're beginning a new block. Initialize data structures as necessary. */
6086 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6087 int sched_verbose ATTRIBUTE_UNUSED,
6088 int max_ready ATTRIBUTE_UNUSED)
6090 #ifdef ENABLE_CHECKING
6093 if (reload_completed)
6094 for (insn = NEXT_INSN (current_sched_info->prev_head);
6095 insn != current_sched_info->next_tail;
6096 insn = NEXT_INSN (insn))
6097 if (SCHED_GROUP_P (insn))
6100 last_scheduled_insn = NULL_RTX;
6101 init_insn_group_barriers ();
6104 /* We are about to being issuing insns for this clock cycle.
6105 Override the default sort algorithm to better slot instructions. */
6108 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6109 int *pn_ready, int clock_var ATTRIBUTE_UNUSED,
6113 int n_ready = *pn_ready;
6114 rtx *e_ready = ready + n_ready;
6118 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
6120 if (reorder_type == 0)
6122 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6124 for (insnp = ready; insnp < e_ready; insnp++)
6125 if (insnp < e_ready)
6128 enum attr_type t = ia64_safe_type (insn);
6129 if (t == TYPE_UNKNOWN)
6131 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6132 || asm_noperands (PATTERN (insn)) >= 0)
6134 rtx lowest = ready[n_asms];
6135 ready[n_asms] = insn;
6141 rtx highest = ready[n_ready - 1];
6142 ready[n_ready - 1] = insn;
6149 if (n_asms < n_ready)
6151 /* Some normal insns to process. Skip the asms. */
6155 else if (n_ready > 0)
6159 if (ia64_final_schedule)
6162 int nr_need_stop = 0;
6164 for (insnp = ready; insnp < e_ready; insnp++)
6165 if (safe_group_barrier_needed_p (*insnp))
6168 if (reorder_type == 1 && n_ready == nr_need_stop)
6170 if (reorder_type == 0)
6173 /* Move down everything that needs a stop bit, preserving
6175 while (insnp-- > ready + deleted)
6176 while (insnp >= ready + deleted)
6179 if (! safe_group_barrier_needed_p (insn))
6181 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6192 /* We are about to being issuing insns for this clock cycle. Override
6193 the default sort algorithm to better slot instructions. */
6196 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
6199 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
6200 pn_ready, clock_var, 0);
6203 /* Like ia64_sched_reorder, but called after issuing each insn.
6204 Override the default sort algorithm to better slot instructions. */
6207 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
6208 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
6209 int *pn_ready, int clock_var)
6211 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
6212 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
6213 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
6217 /* We are about to issue INSN. Return the number of insns left on the
6218 ready queue that can be issued this cycle. */
6221 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
6222 int sched_verbose ATTRIBUTE_UNUSED,
6223 rtx insn ATTRIBUTE_UNUSED,
6224 int can_issue_more ATTRIBUTE_UNUSED)
6226 last_scheduled_insn = insn;
6227 memcpy (prev_cycle_state, curr_state, dfa_state_size);
6228 if (reload_completed)
6230 if (group_barrier_needed_p (insn))
6232 if (GET_CODE (insn) == CALL_INSN)
6233 init_insn_group_barriers ();
6234 stops_p [INSN_UID (insn)] = stop_before_p;
6240 /* We are choosing insn from the ready queue. Return nonzero if INSN
6244 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
6246 if (insn == NULL_RTX || !INSN_P (insn))
6248 return (!reload_completed
6249 || !safe_group_barrier_needed_p (insn));
6252 /* The following variable value is pseudo-insn used by the DFA insn
6253 scheduler to change the DFA state when the simulated clock is
6256 static rtx dfa_pre_cycle_insn;
6258 /* We are about to being issuing INSN. Return nonzero if we can not
6259 issue it on given cycle CLOCK and return zero if we should not sort
6260 the ready queue on the next clock start. */
6263 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
6264 int clock, int *sort_p)
6266 int setup_clocks_p = FALSE;
6268 if (insn == NULL_RTX || !INSN_P (insn))
6270 if ((reload_completed && safe_group_barrier_needed_p (insn))
6271 || (last_scheduled_insn
6272 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6273 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6274 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6276 init_insn_group_barriers ();
6277 if (verbose && dump)
6278 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6279 last_clock == clock ? " + cycle advance" : "");
6281 if (last_clock == clock)
6283 state_transition (curr_state, dfa_stop_insn);
6284 if (TARGET_EARLY_STOP_BITS)
6285 *sort_p = (last_scheduled_insn == NULL_RTX
6286 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6291 else if (reload_completed)
6292 setup_clocks_p = TRUE;
6293 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6294 state_transition (curr_state, dfa_stop_insn);
6295 state_transition (curr_state, dfa_pre_cycle_insn);
6296 state_transition (curr_state, NULL);
6298 else if (reload_completed)
6299 setup_clocks_p = TRUE;
6300 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM)
6302 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6304 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6309 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6310 if (REG_NOTE_KIND (link) == 0)
6312 enum attr_itanium_class dep_class;
6313 rtx dep_insn = XEXP (link, 0);
6315 dep_class = ia64_safe_itanium_class (dep_insn);
6316 if ((dep_class == ITANIUM_CLASS_MMMUL
6317 || dep_class == ITANIUM_CLASS_MMSHF)
6318 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6320 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6321 d = last_clock - clocks [INSN_UID (dep_insn)];
6324 add_cycles [INSN_UID (insn)] = 3 - d;
6332 /* The following page contains abstract data `bundle states' which are
6333 used for bundling insns (inserting nops and template generation). */
6335 /* The following describes state of insn bundling. */
6339 /* Unique bundle state number to identify them in the debugging
6342 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
6343 /* number nops before and after the insn */
6344 short before_nops_num, after_nops_num;
6345 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
6347 int cost; /* cost of the state in cycles */
6348 int accumulated_insns_num; /* number of all previous insns including
6349 nops. L is considered as 2 insns */
6350 int branch_deviation; /* deviation of previous branches from 3rd slots */
6351 struct bundle_state *next; /* next state with the same insn_num */
6352 struct bundle_state *originator; /* originator (previous insn state) */
6353 /* All bundle states are in the following chain. */
6354 struct bundle_state *allocated_states_chain;
6355 /* The DFA State after issuing the insn and the nops. */
6359 /* The following is map insn number to the corresponding bundle state. */
6361 static struct bundle_state **index_to_bundle_states;
6363 /* The unique number of next bundle state. */
6365 static int bundle_states_num;
6367 /* All allocated bundle states are in the following chain. */
6369 static struct bundle_state *allocated_bundle_states_chain;
6371 /* All allocated but not used bundle states are in the following
6374 static struct bundle_state *free_bundle_state_chain;
6377 /* The following function returns a free bundle state. */
6379 static struct bundle_state *
6380 get_free_bundle_state (void)
6382 struct bundle_state *result;
6384 if (free_bundle_state_chain != NULL)
6386 result = free_bundle_state_chain;
6387 free_bundle_state_chain = result->next;
6391 result = xmalloc (sizeof (struct bundle_state));
6392 result->dfa_state = xmalloc (dfa_state_size);
6393 result->allocated_states_chain = allocated_bundle_states_chain;
6394 allocated_bundle_states_chain = result;
6396 result->unique_num = bundle_states_num++;
6401 /* The following function frees given bundle state. */
6404 free_bundle_state (struct bundle_state *state)
6406 state->next = free_bundle_state_chain;
6407 free_bundle_state_chain = state;
6410 /* Start work with abstract data `bundle states'. */
6413 initiate_bundle_states (void)
6415 bundle_states_num = 0;
6416 free_bundle_state_chain = NULL;
6417 allocated_bundle_states_chain = NULL;
6420 /* Finish work with abstract data `bundle states'. */
6423 finish_bundle_states (void)
6425 struct bundle_state *curr_state, *next_state;
6427 for (curr_state = allocated_bundle_states_chain;
6429 curr_state = next_state)
6431 next_state = curr_state->allocated_states_chain;
6432 free (curr_state->dfa_state);
6437 /* Hash table of the bundle states. The key is dfa_state and insn_num
6438 of the bundle states. */
6440 static htab_t bundle_state_table;
6442 /* The function returns hash of BUNDLE_STATE. */
6445 bundle_state_hash (const void *bundle_state)
6447 const struct bundle_state *state = (struct bundle_state *) bundle_state;
6450 for (result = i = 0; i < dfa_state_size; i++)
6451 result += (((unsigned char *) state->dfa_state) [i]
6452 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
6453 return result + state->insn_num;
6456 /* The function returns nonzero if the bundle state keys are equal. */
6459 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
6461 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
6462 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
6464 return (state1->insn_num == state2->insn_num
6465 && memcmp (state1->dfa_state, state2->dfa_state,
6466 dfa_state_size) == 0);
6469 /* The function inserts the BUNDLE_STATE into the hash table. The
6470 function returns nonzero if the bundle has been inserted into the
6471 table. The table contains the best bundle state with given key. */
6474 insert_bundle_state (struct bundle_state *bundle_state)
6478 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
6479 if (*entry_ptr == NULL)
6481 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
6482 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
6483 *entry_ptr = (void *) bundle_state;
6486 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
6487 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
6488 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
6489 > bundle_state->accumulated_insns_num
6490 || (((struct bundle_state *)
6491 *entry_ptr)->accumulated_insns_num
6492 == bundle_state->accumulated_insns_num
6493 && ((struct bundle_state *)
6494 *entry_ptr)->branch_deviation
6495 > bundle_state->branch_deviation))))
6498 struct bundle_state temp;
6500 temp = *(struct bundle_state *) *entry_ptr;
6501 *(struct bundle_state *) *entry_ptr = *bundle_state;
6502 ((struct bundle_state *) *entry_ptr)->next = temp.next;
6503 *bundle_state = temp;
6508 /* Start work with the hash table. */
6511 initiate_bundle_state_table (void)
6513 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
6517 /* Finish work with the hash table. */
6520 finish_bundle_state_table (void)
6522 htab_delete (bundle_state_table);
6527 /* The following variable is a insn `nop' used to check bundle states
6528 with different number of inserted nops. */
6530 static rtx ia64_nop;
6532 /* The following function tries to issue NOPS_NUM nops for the current
6533 state without advancing processor cycle. If it failed, the
6534 function returns FALSE and frees the current state. */
6537 try_issue_nops (struct bundle_state *curr_state, int nops_num)
6541 for (i = 0; i < nops_num; i++)
6542 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
6544 free_bundle_state (curr_state);
6550 /* The following function tries to issue INSN for the current
6551 state without advancing processor cycle. If it failed, the
6552 function returns FALSE and frees the current state. */
6555 try_issue_insn (struct bundle_state *curr_state, rtx insn)
6557 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
6559 free_bundle_state (curr_state);
6565 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6566 starting with ORIGINATOR without advancing processor cycle. If
6567 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6568 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6569 If it was successful, the function creates new bundle state and
6570 insert into the hash table and into `index_to_bundle_states'. */
6573 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
6574 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
6576 struct bundle_state *curr_state;
6578 curr_state = get_free_bundle_state ();
6579 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
6580 curr_state->insn = insn;
6581 curr_state->insn_num = originator->insn_num + 1;
6582 curr_state->cost = originator->cost;
6583 curr_state->originator = originator;
6584 curr_state->before_nops_num = before_nops_num;
6585 curr_state->after_nops_num = 0;
6586 curr_state->accumulated_insns_num
6587 = originator->accumulated_insns_num + before_nops_num;
6588 curr_state->branch_deviation = originator->branch_deviation;
6589 if (insn == NULL_RTX)
6591 else if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
6593 if (GET_MODE (insn) == TImode)
6595 if (!try_issue_nops (curr_state, before_nops_num))
6597 if (!try_issue_insn (curr_state, insn))
6599 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
6600 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
6601 && curr_state->accumulated_insns_num % 3 != 0)
6603 free_bundle_state (curr_state);
6607 else if (GET_MODE (insn) != TImode)
6609 if (!try_issue_nops (curr_state, before_nops_num))
6611 if (!try_issue_insn (curr_state, insn))
6613 curr_state->accumulated_insns_num++;
6614 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6615 || asm_noperands (PATTERN (insn)) >= 0)
6617 if (ia64_safe_type (insn) == TYPE_L)
6618 curr_state->accumulated_insns_num++;
6622 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
6623 state_transition (curr_state->dfa_state, NULL);
6625 if (!try_issue_nops (curr_state, before_nops_num))
6627 if (!try_issue_insn (curr_state, insn))
6629 curr_state->accumulated_insns_num++;
6630 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6631 || asm_noperands (PATTERN (insn)) >= 0)
6633 /* Finish bundle containing asm insn. */
6634 curr_state->after_nops_num
6635 = 3 - curr_state->accumulated_insns_num % 3;
6636 curr_state->accumulated_insns_num
6637 += 3 - curr_state->accumulated_insns_num % 3;
6639 else if (ia64_safe_type (insn) == TYPE_L)
6640 curr_state->accumulated_insns_num++;
6642 if (ia64_safe_type (insn) == TYPE_B)
6643 curr_state->branch_deviation
6644 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
6645 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
6647 if (!only_bundle_end_p && insert_bundle_state (curr_state))
6650 struct bundle_state *curr_state1;
6651 struct bundle_state *allocated_states_chain;
6653 curr_state1 = get_free_bundle_state ();
6654 dfa_state = curr_state1->dfa_state;
6655 allocated_states_chain = curr_state1->allocated_states_chain;
6656 *curr_state1 = *curr_state;
6657 curr_state1->dfa_state = dfa_state;
6658 curr_state1->allocated_states_chain = allocated_states_chain;
6659 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
6661 curr_state = curr_state1;
6663 if (!try_issue_nops (curr_state,
6664 3 - curr_state->accumulated_insns_num % 3))
6666 curr_state->after_nops_num
6667 = 3 - curr_state->accumulated_insns_num % 3;
6668 curr_state->accumulated_insns_num
6669 += 3 - curr_state->accumulated_insns_num % 3;
6671 if (!insert_bundle_state (curr_state))
6672 free_bundle_state (curr_state);
6676 /* The following function returns position in the two window bundle
6680 get_max_pos (state_t state)
6682 if (cpu_unit_reservation_p (state, pos_6))
6684 else if (cpu_unit_reservation_p (state, pos_5))
6686 else if (cpu_unit_reservation_p (state, pos_4))
6688 else if (cpu_unit_reservation_p (state, pos_3))
6690 else if (cpu_unit_reservation_p (state, pos_2))
6692 else if (cpu_unit_reservation_p (state, pos_1))
6698 /* The function returns code of a possible template for given position
6699 and state. The function should be called only with 2 values of
6700 position equal to 3 or 6. */
6703 get_template (state_t state, int pos)
6708 if (cpu_unit_reservation_p (state, _0mii_))
6710 else if (cpu_unit_reservation_p (state, _0mmi_))
6712 else if (cpu_unit_reservation_p (state, _0mfi_))
6714 else if (cpu_unit_reservation_p (state, _0mmf_))
6716 else if (cpu_unit_reservation_p (state, _0bbb_))
6718 else if (cpu_unit_reservation_p (state, _0mbb_))
6720 else if (cpu_unit_reservation_p (state, _0mib_))
6722 else if (cpu_unit_reservation_p (state, _0mmb_))
6724 else if (cpu_unit_reservation_p (state, _0mfb_))
6726 else if (cpu_unit_reservation_p (state, _0mlx_))
6731 if (cpu_unit_reservation_p (state, _1mii_))
6733 else if (cpu_unit_reservation_p (state, _1mmi_))
6735 else if (cpu_unit_reservation_p (state, _1mfi_))
6737 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
6739 else if (cpu_unit_reservation_p (state, _1bbb_))
6741 else if (cpu_unit_reservation_p (state, _1mbb_))
6743 else if (cpu_unit_reservation_p (state, _1mib_))
6745 else if (cpu_unit_reservation_p (state, _1mmb_))
6747 else if (cpu_unit_reservation_p (state, _1mfb_))
6749 else if (cpu_unit_reservation_p (state, _1mlx_))
6758 /* The following function returns an insn important for insn bundling
6759 followed by INSN and before TAIL. */
6762 get_next_important_insn (rtx insn, rtx tail)
6764 for (; insn && insn != tail; insn = NEXT_INSN (insn))
6766 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6767 && GET_CODE (PATTERN (insn)) != USE
6768 && GET_CODE (PATTERN (insn)) != CLOBBER)
6773 /* The following function does insn bundling. Bundling means
6774 inserting templates and nop insns to fit insn groups into permitted
6775 templates. Instruction scheduling uses NDFA (non-deterministic
6776 finite automata) encoding informations about the templates and the
6777 inserted nops. Nondeterminism of the automata permits follows
6778 all possible insn sequences very fast.
6780 Unfortunately it is not possible to get information about inserting
6781 nop insns and used templates from the automata states. The
6782 automata only says that we can issue an insn possibly inserting
6783 some nops before it and using some template. Therefore insn
6784 bundling in this function is implemented by using DFA
6785 (deterministic finite automata). We follows all possible insn
6786 sequences by inserting 0-2 nops (that is what the NDFA describe for
6787 insn scheduling) before/after each insn being bundled. We know the
6788 start of simulated processor cycle from insn scheduling (insn
6789 starting a new cycle has TImode).
6791 Simple implementation of insn bundling would create enormous
6792 number of possible insn sequences satisfying information about new
6793 cycle ticks taken from the insn scheduling. To make the algorithm
6794 practical we use dynamic programming. Each decision (about
6795 inserting nops and implicitly about previous decisions) is described
6796 by structure bundle_state (see above). If we generate the same
6797 bundle state (key is automaton state after issuing the insns and
6798 nops for it), we reuse already generated one. As consequence we
6799 reject some decisions which can not improve the solution and
6800 reduce memory for the algorithm.
6802 When we reach the end of EBB (extended basic block), we choose the
6803 best sequence and then, moving back in EBB, insert templates for
6804 the best alternative. The templates are taken from querying
6805 automaton state for each insn in chosen bundle states.
6807 So the algorithm makes two (forward and backward) passes through
6808 EBB. There is an additional forward pass through EBB for Itanium1
6809 processor. This pass inserts more nops to make dependency between
6810 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
6813 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
6815 struct bundle_state *curr_state, *next_state, *best_state;
6816 rtx insn, next_insn;
6818 int i, bundle_end_p, only_bundle_end_p, asm_p;
6819 int pos = 0, max_pos, template0, template1;
6822 enum attr_type type;
6825 /* Count insns in the EBB. */
6826 for (insn = NEXT_INSN (prev_head_insn);
6827 insn && insn != tail;
6828 insn = NEXT_INSN (insn))
6834 dfa_clean_insn_cache ();
6835 initiate_bundle_state_table ();
6836 index_to_bundle_states = xmalloc ((insn_num + 2)
6837 * sizeof (struct bundle_state *));
6838 /* First (forward) pass -- generation of bundle states. */
6839 curr_state = get_free_bundle_state ();
6840 curr_state->insn = NULL;
6841 curr_state->before_nops_num = 0;
6842 curr_state->after_nops_num = 0;
6843 curr_state->insn_num = 0;
6844 curr_state->cost = 0;
6845 curr_state->accumulated_insns_num = 0;
6846 curr_state->branch_deviation = 0;
6847 curr_state->next = NULL;
6848 curr_state->originator = NULL;
6849 state_reset (curr_state->dfa_state);
6850 index_to_bundle_states [0] = curr_state;
6852 /* Shift cycle mark if it is put on insn which could be ignored. */
6853 for (insn = NEXT_INSN (prev_head_insn);
6855 insn = NEXT_INSN (insn))
6857 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6858 || GET_CODE (PATTERN (insn)) == USE
6859 || GET_CODE (PATTERN (insn)) == CLOBBER)
6860 && GET_MODE (insn) == TImode)
6862 PUT_MODE (insn, VOIDmode);
6863 for (next_insn = NEXT_INSN (insn);
6865 next_insn = NEXT_INSN (next_insn))
6866 if (INSN_P (next_insn)
6867 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
6868 && GET_CODE (PATTERN (next_insn)) != USE
6869 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
6871 PUT_MODE (next_insn, TImode);
6875 /* Froward pass: generation of bundle states. */
6876 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6881 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6882 || GET_CODE (PATTERN (insn)) == USE
6883 || GET_CODE (PATTERN (insn)) == CLOBBER)
6885 type = ia64_safe_type (insn);
6886 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6888 index_to_bundle_states [insn_num] = NULL;
6889 for (curr_state = index_to_bundle_states [insn_num - 1];
6891 curr_state = next_state)
6893 pos = curr_state->accumulated_insns_num % 3;
6894 next_state = curr_state->next;
6895 /* We must fill up the current bundle in order to start a
6896 subsequent asm insn in a new bundle. Asm insn is always
6897 placed in a separate bundle. */
6899 = (next_insn != NULL_RTX
6900 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
6901 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
6902 /* We may fill up the current bundle if it is the cycle end
6903 without a group barrier. */
6905 = (only_bundle_end_p || next_insn == NULL_RTX
6906 || (GET_MODE (next_insn) == TImode
6907 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
6908 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
6910 /* We need to insert 2 nops for cases like M_MII. To
6911 guarantee issuing all insns on the same cycle for
6912 Itanium 1, we need to issue 2 nops after the first M
6913 insn (MnnMII where n is a nop insn). */
6914 || (type == TYPE_M && ia64_tune == PROCESSOR_ITANIUM
6915 && !bundle_end_p && pos == 1))
6916 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
6918 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
6920 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
6923 if (index_to_bundle_states [insn_num] == NULL)
6925 for (curr_state = index_to_bundle_states [insn_num];
6927 curr_state = curr_state->next)
6928 if (verbose >= 2 && dump)
6930 /* This structure is taken from generated code of the
6931 pipeline hazard recognizer (see file insn-attrtab.c).
6932 Please don't forget to change the structure if a new
6933 automaton is added to .md file. */
6936 unsigned short one_automaton_state;
6937 unsigned short oneb_automaton_state;
6938 unsigned short two_automaton_state;
6939 unsigned short twob_automaton_state;
6944 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6945 curr_state->unique_num,
6946 (curr_state->originator == NULL
6947 ? -1 : curr_state->originator->unique_num),
6949 curr_state->before_nops_num, curr_state->after_nops_num,
6950 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6951 (ia64_tune == PROCESSOR_ITANIUM
6952 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6953 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6957 if (index_to_bundle_states [insn_num] == NULL)
6958 /* We should find a solution because the 2nd insn scheduling has
6961 /* Find a state corresponding to the best insn sequence. */
6963 for (curr_state = index_to_bundle_states [insn_num];
6965 curr_state = curr_state->next)
6966 /* We are just looking at the states with fully filled up last
6967 bundle. The first we prefer insn sequences with minimal cost
6968 then with minimal inserted nops and finally with branch insns
6969 placed in the 3rd slots. */
6970 if (curr_state->accumulated_insns_num % 3 == 0
6971 && (best_state == NULL || best_state->cost > curr_state->cost
6972 || (best_state->cost == curr_state->cost
6973 && (curr_state->accumulated_insns_num
6974 < best_state->accumulated_insns_num
6975 || (curr_state->accumulated_insns_num
6976 == best_state->accumulated_insns_num
6977 && curr_state->branch_deviation
6978 < best_state->branch_deviation)))))
6979 best_state = curr_state;
6980 /* Second (backward) pass: adding nops and templates. */
6981 insn_num = best_state->before_nops_num;
6982 template0 = template1 = -1;
6983 for (curr_state = best_state;
6984 curr_state->originator != NULL;
6985 curr_state = curr_state->originator)
6987 insn = curr_state->insn;
6988 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
6989 || asm_noperands (PATTERN (insn)) >= 0);
6991 if (verbose >= 2 && dump)
6995 unsigned short one_automaton_state;
6996 unsigned short oneb_automaton_state;
6997 unsigned short two_automaton_state;
6998 unsigned short twob_automaton_state;
7003 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7004 curr_state->unique_num,
7005 (curr_state->originator == NULL
7006 ? -1 : curr_state->originator->unique_num),
7008 curr_state->before_nops_num, curr_state->after_nops_num,
7009 curr_state->accumulated_insns_num, curr_state->branch_deviation,
7010 (ia64_tune == PROCESSOR_ITANIUM
7011 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
7012 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7015 /* Find the position in the current bundle window. The window can
7016 contain at most two bundles. Two bundle window means that
7017 the processor will make two bundle rotation. */
7018 max_pos = get_max_pos (curr_state->dfa_state);
7020 /* The following (negative template number) means that the
7021 processor did one bundle rotation. */
7022 || (max_pos == 3 && template0 < 0))
7024 /* We are at the end of the window -- find template(s) for
7028 template0 = get_template (curr_state->dfa_state, 3);
7031 template1 = get_template (curr_state->dfa_state, 3);
7032 template0 = get_template (curr_state->dfa_state, 6);
7035 if (max_pos > 3 && template1 < 0)
7036 /* It may happen when we have the stop inside a bundle. */
7040 template1 = get_template (curr_state->dfa_state, 3);
7044 /* Emit nops after the current insn. */
7045 for (i = 0; i < curr_state->after_nops_num; i++)
7048 emit_insn_after (nop, insn);
7054 /* We are at the start of a bundle: emit the template
7055 (it should be defined). */
7058 b = gen_bundle_selector (GEN_INT (template0));
7059 ia64_emit_insn_before (b, nop);
7060 /* If we have two bundle window, we make one bundle
7061 rotation. Otherwise template0 will be undefined
7062 (negative value). */
7063 template0 = template1;
7067 /* Move the position backward in the window. Group barrier has
7068 no slot. Asm insn takes all bundle. */
7069 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7070 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7071 && asm_noperands (PATTERN (insn)) < 0)
7073 /* Long insn takes 2 slots. */
7074 if (ia64_safe_type (insn) == TYPE_L)
7079 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7080 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7081 && asm_noperands (PATTERN (insn)) < 0)
7083 /* The current insn is at the bundle start: emit the
7087 b = gen_bundle_selector (GEN_INT (template0));
7088 ia64_emit_insn_before (b, insn);
7089 b = PREV_INSN (insn);
7091 /* See comment above in analogous place for emitting nops
7093 template0 = template1;
7096 /* Emit nops after the current insn. */
7097 for (i = 0; i < curr_state->before_nops_num; i++)
7100 ia64_emit_insn_before (nop, insn);
7101 nop = PREV_INSN (insn);
7108 /* See comment above in analogous place for emitting nops
7112 b = gen_bundle_selector (GEN_INT (template0));
7113 ia64_emit_insn_before (b, insn);
7114 b = PREV_INSN (insn);
7116 template0 = template1;
7121 if (ia64_tune == PROCESSOR_ITANIUM)
7122 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
7123 Itanium1 has a strange design, if the distance between an insn
7124 and dependent MM-insn is less 4 then we have a 6 additional
7125 cycles stall. So we make the distance equal to 4 cycles if it
7127 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
7132 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
7133 || GET_CODE (PATTERN (insn)) == USE
7134 || GET_CODE (PATTERN (insn)) == CLOBBER)
7136 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
7137 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
7138 /* We found a MM-insn which needs additional cycles. */
7144 /* Now we are searching for a template of the bundle in
7145 which the MM-insn is placed and the position of the
7146 insn in the bundle (0, 1, 2). Also we are searching
7147 for that there is a stop before the insn. */
7148 last = prev_active_insn (insn);
7149 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
7151 last = prev_active_insn (last);
7153 for (;; last = prev_active_insn (last))
7154 if (recog_memoized (last) == CODE_FOR_bundle_selector)
7156 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
7158 /* The insn is in MLX bundle. Change the template
7159 onto MFI because we will add nops before the
7160 insn. It simplifies subsequent code a lot. */
7162 = gen_bundle_selector (const2_rtx); /* -> MFI */
7165 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7167 /* Some check of correctness: the stop is not at the
7168 bundle start, there are no more 3 insns in the bundle,
7169 and the MM-insn is not at the start of bundle with
7171 if ((pred_stop_p && n == 0) || n > 2
7172 || (template0 == 9 && n != 0))
7174 /* Put nops after the insn in the bundle. */
7175 for (j = 3 - n; j > 0; j --)
7176 ia64_emit_insn_before (gen_nop (), insn);
7177 /* It takes into account that we will add more N nops
7178 before the insn lately -- please see code below. */
7179 add_cycles [INSN_UID (insn)]--;
7180 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
7181 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7184 add_cycles [INSN_UID (insn)]--;
7185 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
7187 /* Insert "MII;" template. */
7188 ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
7190 ia64_emit_insn_before (gen_nop (), insn);
7191 ia64_emit_insn_before (gen_nop (), insn);
7194 /* To decrease code size, we use "MI;I;"
7196 ia64_emit_insn_before
7197 (gen_insn_group_barrier (GEN_INT (3)), insn);
7200 ia64_emit_insn_before (gen_nop (), insn);
7201 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7204 /* Put the MM-insn in the same slot of a bundle with the
7205 same template as the original one. */
7206 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
7208 /* To put the insn in the same slot, add necessary number
7210 for (j = n; j > 0; j --)
7211 ia64_emit_insn_before (gen_nop (), insn);
7212 /* Put the stop if the original bundle had it. */
7214 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7218 free (index_to_bundle_states);
7219 finish_bundle_state_table ();
7221 dfa_clean_insn_cache ();
7224 /* The following function is called at the end of scheduling BB or
7225 EBB. After reload, it inserts stop bits and does insn bundling. */
7228 ia64_sched_finish (FILE *dump, int sched_verbose)
7231 fprintf (dump, "// Finishing schedule.\n");
7232 if (!reload_completed)
7234 if (reload_completed)
7236 final_emit_insn_group_barriers (dump);
7237 bundling (dump, sched_verbose, current_sched_info->prev_head,
7238 current_sched_info->next_tail);
7239 if (sched_verbose && dump)
7240 fprintf (dump, "// finishing %d-%d\n",
7241 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
7242 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
7248 /* The following function inserts stop bits in scheduled BB or EBB. */
7251 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
7254 int need_barrier_p = 0;
7255 rtx prev_insn = NULL_RTX;
7257 init_insn_group_barriers ();
7259 for (insn = NEXT_INSN (current_sched_info->prev_head);
7260 insn != current_sched_info->next_tail;
7261 insn = NEXT_INSN (insn))
7263 if (GET_CODE (insn) == BARRIER)
7265 rtx last = prev_active_insn (insn);
7269 if (GET_CODE (last) == JUMP_INSN
7270 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
7271 last = prev_active_insn (last);
7272 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7273 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
7275 init_insn_group_barriers ();
7277 prev_insn = NULL_RTX;
7279 else if (INSN_P (insn))
7281 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
7283 init_insn_group_barriers ();
7285 prev_insn = NULL_RTX;
7287 else if (need_barrier_p || group_barrier_needed_p (insn))
7289 if (TARGET_EARLY_STOP_BITS)
7294 last != current_sched_info->prev_head;
7295 last = PREV_INSN (last))
7296 if (INSN_P (last) && GET_MODE (last) == TImode
7297 && stops_p [INSN_UID (last)])
7299 if (last == current_sched_info->prev_head)
7301 last = prev_active_insn (last);
7303 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
7304 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7306 init_insn_group_barriers ();
7307 for (last = NEXT_INSN (last);
7309 last = NEXT_INSN (last))
7311 group_barrier_needed_p (last);
7315 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7317 init_insn_group_barriers ();
7319 group_barrier_needed_p (insn);
7320 prev_insn = NULL_RTX;
7322 else if (recog_memoized (insn) >= 0)
7324 need_barrier_p = (GET_CODE (insn) == CALL_INSN
7325 || GET_CODE (PATTERN (insn)) == ASM_INPUT
7326 || asm_noperands (PATTERN (insn)) >= 0);
7333 /* If the following function returns TRUE, we will use the the DFA
7337 ia64_use_dfa_pipeline_interface (void)
7342 /* If the following function returns TRUE, we will use the the DFA
7346 ia64_first_cycle_multipass_dfa_lookahead (void)
7348 return (reload_completed ? 6 : 4);
7351 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7354 ia64_init_dfa_pre_cycle_insn (void)
7356 if (temp_dfa_state == NULL)
7358 dfa_state_size = state_size ();
7359 temp_dfa_state = xmalloc (dfa_state_size);
7360 prev_cycle_state = xmalloc (dfa_state_size);
7362 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
7363 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
7364 recog_memoized (dfa_pre_cycle_insn);
7365 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7366 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
7367 recog_memoized (dfa_stop_insn);
7370 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7371 used by the DFA insn scheduler. */
7374 ia64_dfa_pre_cycle_insn (void)
7376 return dfa_pre_cycle_insn;
7379 /* The following function returns TRUE if PRODUCER (of type ilog or
7380 ld) produces address for CONSUMER (of type st or stf). */
7383 ia64_st_address_bypass_p (rtx producer, rtx consumer)
7387 if (producer == NULL_RTX || consumer == NULL_RTX)
7389 dest = ia64_single_set (producer);
7390 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7391 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7393 if (GET_CODE (reg) == SUBREG)
7394 reg = SUBREG_REG (reg);
7395 dest = ia64_single_set (consumer);
7396 if (dest == NULL_RTX || (mem = SET_DEST (dest)) == NULL_RTX
7397 || GET_CODE (mem) != MEM)
7399 return reg_mentioned_p (reg, mem);
7402 /* The following function returns TRUE if PRODUCER (of type ilog or
7403 ld) produces address for CONSUMER (of type ld or fld). */
7406 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
7408 rtx dest, src, reg, mem;
7410 if (producer == NULL_RTX || consumer == NULL_RTX)
7412 dest = ia64_single_set (producer);
7413 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7414 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7416 if (GET_CODE (reg) == SUBREG)
7417 reg = SUBREG_REG (reg);
7418 src = ia64_single_set (consumer);
7419 if (src == NULL_RTX || (mem = SET_SRC (src)) == NULL_RTX)
7421 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
7422 mem = XVECEXP (mem, 0, 0);
7423 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
7424 mem = XEXP (mem, 0);
7426 /* Note that LO_SUM is used for GOT loads. */
7427 if (GET_CODE (mem) != LO_SUM && GET_CODE (mem) != MEM)
7430 return reg_mentioned_p (reg, mem);
7433 /* The following function returns TRUE if INSN produces address for a
7434 load/store insn. We will place such insns into M slot because it
7435 decreases its latency time. */
7438 ia64_produce_address_p (rtx insn)
7444 /* Emit pseudo-ops for the assembler to describe predicate relations.
7445 At present this assumes that we only consider predicate pairs to
7446 be mutex, and that the assembler can deduce proper values from
7447 straight-line code. */
7450 emit_predicate_relation_info (void)
7454 FOR_EACH_BB_REVERSE (bb)
7457 rtx head = BB_HEAD (bb);
7459 /* We only need such notes at code labels. */
7460 if (GET_CODE (head) != CODE_LABEL)
7462 if (GET_CODE (NEXT_INSN (head)) == NOTE
7463 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
7464 head = NEXT_INSN (head);
7466 for (r = PR_REG (0); r < PR_REG (64); r += 2)
7467 if (REGNO_REG_SET_P (bb->global_live_at_start, r))
7469 rtx p = gen_rtx_REG (BImode, r);
7470 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
7471 if (head == BB_END (bb))
7477 /* Look for conditional calls that do not return, and protect predicate
7478 relations around them. Otherwise the assembler will assume the call
7479 returns, and complain about uses of call-clobbered predicates after
7481 FOR_EACH_BB_REVERSE (bb)
7483 rtx insn = BB_HEAD (bb);
7487 if (GET_CODE (insn) == CALL_INSN
7488 && GET_CODE (PATTERN (insn)) == COND_EXEC
7489 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
7491 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
7492 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
7493 if (BB_HEAD (bb) == insn)
7495 if (BB_END (bb) == insn)
7499 if (insn == BB_END (bb))
7501 insn = NEXT_INSN (insn);
7506 /* Perform machine dependent operations on the rtl chain INSNS. */
7511 /* We are freeing block_for_insn in the toplev to keep compatibility
7512 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7513 compute_bb_for_insn ();
7515 /* If optimizing, we'll have split before scheduling. */
7517 split_all_insns (0);
7519 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7520 non-optimizing bootstrap. */
7521 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
7523 if (ia64_flag_schedule_insns2)
7525 timevar_push (TV_SCHED2);
7526 ia64_final_schedule = 1;
7528 initiate_bundle_states ();
7529 ia64_nop = make_insn_raw (gen_nop ());
7530 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
7531 recog_memoized (ia64_nop);
7532 clocks_length = get_max_uid () + 1;
7533 stops_p = xcalloc (1, clocks_length);
7534 if (ia64_tune == PROCESSOR_ITANIUM)
7536 clocks = xcalloc (clocks_length, sizeof (int));
7537 add_cycles = xcalloc (clocks_length, sizeof (int));
7539 if (ia64_tune == PROCESSOR_ITANIUM2)
7541 pos_1 = get_cpu_unit_code ("2_1");
7542 pos_2 = get_cpu_unit_code ("2_2");
7543 pos_3 = get_cpu_unit_code ("2_3");
7544 pos_4 = get_cpu_unit_code ("2_4");
7545 pos_5 = get_cpu_unit_code ("2_5");
7546 pos_6 = get_cpu_unit_code ("2_6");
7547 _0mii_ = get_cpu_unit_code ("2b_0mii.");
7548 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
7549 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
7550 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
7551 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
7552 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
7553 _0mib_ = get_cpu_unit_code ("2b_0mib.");
7554 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
7555 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
7556 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
7557 _1mii_ = get_cpu_unit_code ("2b_1mii.");
7558 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
7559 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
7560 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
7561 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
7562 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
7563 _1mib_ = get_cpu_unit_code ("2b_1mib.");
7564 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
7565 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
7566 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
7570 pos_1 = get_cpu_unit_code ("1_1");
7571 pos_2 = get_cpu_unit_code ("1_2");
7572 pos_3 = get_cpu_unit_code ("1_3");
7573 pos_4 = get_cpu_unit_code ("1_4");
7574 pos_5 = get_cpu_unit_code ("1_5");
7575 pos_6 = get_cpu_unit_code ("1_6");
7576 _0mii_ = get_cpu_unit_code ("1b_0mii.");
7577 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
7578 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
7579 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
7580 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
7581 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
7582 _0mib_ = get_cpu_unit_code ("1b_0mib.");
7583 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
7584 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
7585 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
7586 _1mii_ = get_cpu_unit_code ("1b_1mii.");
7587 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
7588 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
7589 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
7590 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
7591 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
7592 _1mib_ = get_cpu_unit_code ("1b_1mib.");
7593 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
7594 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
7595 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
7597 schedule_ebbs (rtl_dump_file);
7598 finish_bundle_states ();
7599 if (ia64_tune == PROCESSOR_ITANIUM)
7605 emit_insn_group_barriers (rtl_dump_file);
7607 ia64_final_schedule = 0;
7608 timevar_pop (TV_SCHED2);
7611 emit_all_insn_group_barriers (rtl_dump_file);
7613 /* A call must not be the last instruction in a function, so that the
7614 return address is still within the function, so that unwinding works
7615 properly. Note that IA-64 differs from dwarf2 on this point. */
7616 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7621 insn = get_last_insn ();
7622 if (! INSN_P (insn))
7623 insn = prev_active_insn (insn);
7624 if (GET_CODE (insn) == INSN
7625 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
7626 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
7629 insn = prev_active_insn (insn);
7631 if (GET_CODE (insn) == CALL_INSN)
7634 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7635 emit_insn (gen_break_f ());
7636 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7641 emit_predicate_relation_info ();
7643 if (ia64_flag_var_tracking)
7645 timevar_push (TV_VAR_TRACKING);
7646 variable_tracking_main ();
7647 timevar_pop (TV_VAR_TRACKING);
7651 /* Return true if REGNO is used by the epilogue. */
7654 ia64_epilogue_uses (int regno)
7659 /* With a call to a function in another module, we will write a new
7660 value to "gp". After returning from such a call, we need to make
7661 sure the function restores the original gp-value, even if the
7662 function itself does not use the gp anymore. */
7663 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
7665 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7666 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7667 /* For functions defined with the syscall_linkage attribute, all
7668 input registers are marked as live at all function exits. This
7669 prevents the register allocator from using the input registers,
7670 which in turn makes it possible to restart a system call after
7671 an interrupt without having to save/restore the input registers.
7672 This also prevents kernel data from leaking to application code. */
7673 return lookup_attribute ("syscall_linkage",
7674 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
7677 /* Conditional return patterns can't represent the use of `b0' as
7678 the return address, so we force the value live this way. */
7682 /* Likewise for ar.pfs, which is used by br.ret. */
7690 /* Return true if REGNO is used by the frame unwinder. */
7693 ia64_eh_uses (int regno)
7695 if (! reload_completed)
7698 if (current_frame_info.reg_save_b0
7699 && regno == current_frame_info.reg_save_b0)
7701 if (current_frame_info.reg_save_pr
7702 && regno == current_frame_info.reg_save_pr)
7704 if (current_frame_info.reg_save_ar_pfs
7705 && regno == current_frame_info.reg_save_ar_pfs)
7707 if (current_frame_info.reg_save_ar_unat
7708 && regno == current_frame_info.reg_save_ar_unat)
7710 if (current_frame_info.reg_save_ar_lc
7711 && regno == current_frame_info.reg_save_ar_lc)
7717 /* Return true if this goes in small data/bss. */
7719 /* ??? We could also support own long data here. Generating movl/add/ld8
7720 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7721 code faster because there is one less load. This also includes incomplete
7722 types which can't go in sdata/sbss. */
7725 ia64_in_small_data_p (tree exp)
7727 if (TARGET_NO_SDATA)
7730 /* We want to merge strings, so we never consider them small data. */
7731 if (TREE_CODE (exp) == STRING_CST)
7734 /* Functions are never small data. */
7735 if (TREE_CODE (exp) == FUNCTION_DECL)
7738 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
7740 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
7741 if (strcmp (section, ".sdata") == 0
7742 || strcmp (section, ".sbss") == 0)
7747 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
7749 /* If this is an incomplete type with size 0, then we can't put it
7750 in sdata because it might be too big when completed. */
7751 if (size > 0 && size <= ia64_section_threshold)
7758 /* Output assembly directives for prologue regions. */
7760 /* The current basic block number. */
7762 static bool last_block;
7764 /* True if we need a copy_state command at the start of the next block. */
7766 static bool need_copy_state;
7768 /* The function emits unwind directives for the start of an epilogue. */
7771 process_epilogue (void)
7773 /* If this isn't the last block of the function, then we need to label the
7774 current state, and copy it back in at the start of the next block. */
7778 fprintf (asm_out_file, "\t.label_state 1\n");
7779 need_copy_state = true;
7782 fprintf (asm_out_file, "\t.restore sp\n");
7785 /* This function processes a SET pattern looking for specific patterns
7786 which result in emitting an assembly directive required for unwinding. */
7789 process_set (FILE *asm_out_file, rtx pat)
7791 rtx src = SET_SRC (pat);
7792 rtx dest = SET_DEST (pat);
7793 int src_regno, dest_regno;
7795 /* Look for the ALLOC insn. */
7796 if (GET_CODE (src) == UNSPEC_VOLATILE
7797 && XINT (src, 1) == UNSPECV_ALLOC
7798 && GET_CODE (dest) == REG)
7800 dest_regno = REGNO (dest);
7802 /* If this isn't the final destination for ar.pfs, the alloc
7803 shouldn't have been marked frame related. */
7804 if (dest_regno != current_frame_info.reg_save_ar_pfs)
7807 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
7808 ia64_dbx_register_number (dest_regno));
7812 /* Look for SP = .... */
7813 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
7815 if (GET_CODE (src) == PLUS)
7817 rtx op0 = XEXP (src, 0);
7818 rtx op1 = XEXP (src, 1);
7819 if (op0 == dest && GET_CODE (op1) == CONST_INT)
7821 if (INTVAL (op1) < 0)
7822 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
7825 process_epilogue ();
7830 else if (GET_CODE (src) == REG
7831 && REGNO (src) == HARD_FRAME_POINTER_REGNUM)
7832 process_epilogue ();
7839 /* Register move we need to look at. */
7840 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
7842 src_regno = REGNO (src);
7843 dest_regno = REGNO (dest);
7848 /* Saving return address pointer. */
7849 if (dest_regno != current_frame_info.reg_save_b0)
7851 fprintf (asm_out_file, "\t.save rp, r%d\n",
7852 ia64_dbx_register_number (dest_regno));
7856 if (dest_regno != current_frame_info.reg_save_pr)
7858 fprintf (asm_out_file, "\t.save pr, r%d\n",
7859 ia64_dbx_register_number (dest_regno));
7862 case AR_UNAT_REGNUM:
7863 if (dest_regno != current_frame_info.reg_save_ar_unat)
7865 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
7866 ia64_dbx_register_number (dest_regno));
7870 if (dest_regno != current_frame_info.reg_save_ar_lc)
7872 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
7873 ia64_dbx_register_number (dest_regno));
7876 case STACK_POINTER_REGNUM:
7877 if (dest_regno != HARD_FRAME_POINTER_REGNUM
7878 || ! frame_pointer_needed)
7880 fprintf (asm_out_file, "\t.vframe r%d\n",
7881 ia64_dbx_register_number (dest_regno));
7885 /* Everything else should indicate being stored to memory. */
7890 /* Memory store we need to look at. */
7891 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
7897 if (GET_CODE (XEXP (dest, 0)) == REG)
7899 base = XEXP (dest, 0);
7902 else if (GET_CODE (XEXP (dest, 0)) == PLUS
7903 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT)
7905 base = XEXP (XEXP (dest, 0), 0);
7906 off = INTVAL (XEXP (XEXP (dest, 0), 1));
7911 if (base == hard_frame_pointer_rtx)
7913 saveop = ".savepsp";
7916 else if (base == stack_pointer_rtx)
7921 src_regno = REGNO (src);
7925 if (current_frame_info.reg_save_b0 != 0)
7927 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
7931 if (current_frame_info.reg_save_pr != 0)
7933 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
7937 if (current_frame_info.reg_save_ar_lc != 0)
7939 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
7943 if (current_frame_info.reg_save_ar_pfs != 0)
7945 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
7948 case AR_UNAT_REGNUM:
7949 if (current_frame_info.reg_save_ar_unat != 0)
7951 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
7958 fprintf (asm_out_file, "\t.save.g 0x%x\n",
7959 1 << (src_regno - GR_REG (4)));
7967 fprintf (asm_out_file, "\t.save.b 0x%x\n",
7968 1 << (src_regno - BR_REG (1)));
7975 fprintf (asm_out_file, "\t.save.f 0x%x\n",
7976 1 << (src_regno - FR_REG (2)));
7979 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7980 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7981 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7982 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7983 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
7984 1 << (src_regno - FR_REG (12)));
7996 /* This function looks at a single insn and emits any directives
7997 required to unwind this insn. */
7999 process_for_unwind_directive (FILE *asm_out_file, rtx insn)
8001 if (flag_unwind_tables
8002 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
8006 if (GET_CODE (insn) == NOTE
8007 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
8009 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
8011 /* Restore unwind state from immediately before the epilogue. */
8012 if (need_copy_state)
8014 fprintf (asm_out_file, "\t.body\n");
8015 fprintf (asm_out_file, "\t.copy_state 1\n");
8016 need_copy_state = false;
8020 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
8023 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
8025 pat = XEXP (pat, 0);
8027 pat = PATTERN (insn);
8029 switch (GET_CODE (pat))
8032 process_set (asm_out_file, pat);
8038 int limit = XVECLEN (pat, 0);
8039 for (par_index = 0; par_index < limit; par_index++)
8041 rtx x = XVECEXP (pat, 0, par_index);
8042 if (GET_CODE (x) == SET)
8043 process_set (asm_out_file, x);
8056 ia64_init_builtins (void)
8058 tree psi_type_node = build_pointer_type (integer_type_node);
8059 tree pdi_type_node = build_pointer_type (long_integer_type_node);
8061 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
8062 tree si_ftype_psi_si_si
8063 = build_function_type_list (integer_type_node,
8064 psi_type_node, integer_type_node,
8065 integer_type_node, NULL_TREE);
8067 /* __sync_val_compare_and_swap_di */
8068 tree di_ftype_pdi_di_di
8069 = build_function_type_list (long_integer_type_node,
8070 pdi_type_node, long_integer_type_node,
8071 long_integer_type_node, NULL_TREE);
8072 /* __sync_bool_compare_and_swap_di */
8073 tree si_ftype_pdi_di_di
8074 = build_function_type_list (integer_type_node,
8075 pdi_type_node, long_integer_type_node,
8076 long_integer_type_node, NULL_TREE);
8077 /* __sync_synchronize */
8078 tree void_ftype_void
8079 = build_function_type (void_type_node, void_list_node);
8081 /* __sync_lock_test_and_set_si */
8082 tree si_ftype_psi_si
8083 = build_function_type_list (integer_type_node,
8084 psi_type_node, integer_type_node, NULL_TREE);
8086 /* __sync_lock_test_and_set_di */
8087 tree di_ftype_pdi_di
8088 = build_function_type_list (long_integer_type_node,
8089 pdi_type_node, long_integer_type_node,
8092 /* __sync_lock_release_si */
8094 = build_function_type_list (void_type_node, psi_type_node, NULL_TREE);
8096 /* __sync_lock_release_di */
8098 = build_function_type_list (void_type_node, pdi_type_node, NULL_TREE);
8103 /* The __fpreg type. */
8104 fpreg_type = make_node (REAL_TYPE);
8105 /* ??? The back end should know to load/save __fpreg variables using
8106 the ldf.fill and stf.spill instructions. */
8107 TYPE_PRECISION (fpreg_type) = 96;
8108 layout_type (fpreg_type);
8109 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
8111 /* The __float80 type. */
8112 float80_type = make_node (REAL_TYPE);
8113 TYPE_PRECISION (float80_type) = 96;
8114 layout_type (float80_type);
8115 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
8117 /* The __float128 type. */
8120 tree float128_type = make_node (REAL_TYPE);
8121 TYPE_PRECISION (float128_type) = 128;
8122 layout_type (float128_type);
8123 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
8126 /* Under HPUX, this is a synonym for "long double". */
8127 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
8130 #define def_builtin(name, type, code) \
8131 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
8133 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si,
8134 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI);
8135 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di,
8136 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI);
8137 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si,
8138 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI);
8139 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di,
8140 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI);
8142 def_builtin ("__sync_synchronize", void_ftype_void,
8143 IA64_BUILTIN_SYNCHRONIZE);
8145 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si,
8146 IA64_BUILTIN_LOCK_TEST_AND_SET_SI);
8147 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di,
8148 IA64_BUILTIN_LOCK_TEST_AND_SET_DI);
8149 def_builtin ("__sync_lock_release_si", void_ftype_psi,
8150 IA64_BUILTIN_LOCK_RELEASE_SI);
8151 def_builtin ("__sync_lock_release_di", void_ftype_pdi,
8152 IA64_BUILTIN_LOCK_RELEASE_DI);
8154 def_builtin ("__builtin_ia64_bsp",
8155 build_function_type (ptr_type_node, void_list_node),
8158 def_builtin ("__builtin_ia64_flushrs",
8159 build_function_type (void_type_node, void_list_node),
8160 IA64_BUILTIN_FLUSHRS);
8162 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si,
8163 IA64_BUILTIN_FETCH_AND_ADD_SI);
8164 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si,
8165 IA64_BUILTIN_FETCH_AND_SUB_SI);
8166 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si,
8167 IA64_BUILTIN_FETCH_AND_OR_SI);
8168 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si,
8169 IA64_BUILTIN_FETCH_AND_AND_SI);
8170 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si,
8171 IA64_BUILTIN_FETCH_AND_XOR_SI);
8172 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si,
8173 IA64_BUILTIN_FETCH_AND_NAND_SI);
8175 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si,
8176 IA64_BUILTIN_ADD_AND_FETCH_SI);
8177 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si,
8178 IA64_BUILTIN_SUB_AND_FETCH_SI);
8179 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si,
8180 IA64_BUILTIN_OR_AND_FETCH_SI);
8181 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si,
8182 IA64_BUILTIN_AND_AND_FETCH_SI);
8183 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si,
8184 IA64_BUILTIN_XOR_AND_FETCH_SI);
8185 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si,
8186 IA64_BUILTIN_NAND_AND_FETCH_SI);
8188 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di,
8189 IA64_BUILTIN_FETCH_AND_ADD_DI);
8190 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di,
8191 IA64_BUILTIN_FETCH_AND_SUB_DI);
8192 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di,
8193 IA64_BUILTIN_FETCH_AND_OR_DI);
8194 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di,
8195 IA64_BUILTIN_FETCH_AND_AND_DI);
8196 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di,
8197 IA64_BUILTIN_FETCH_AND_XOR_DI);
8198 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di,
8199 IA64_BUILTIN_FETCH_AND_NAND_DI);
8201 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di,
8202 IA64_BUILTIN_ADD_AND_FETCH_DI);
8203 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di,
8204 IA64_BUILTIN_SUB_AND_FETCH_DI);
8205 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di,
8206 IA64_BUILTIN_OR_AND_FETCH_DI);
8207 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di,
8208 IA64_BUILTIN_AND_AND_FETCH_DI);
8209 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di,
8210 IA64_BUILTIN_XOR_AND_FETCH_DI);
8211 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di,
8212 IA64_BUILTIN_NAND_AND_FETCH_DI);
8217 /* Expand fetch_and_op intrinsics. The basic code sequence is:
8225 cmpxchgsz.acq tmp = [ptr], tmp
8226 } while (tmp != ret)
8230 ia64_expand_fetch_and_op (optab binoptab, enum machine_mode mode,
8231 tree arglist, rtx target)
8233 rtx ret, label, tmp, ccv, insn, mem, value;
8236 arg0 = TREE_VALUE (arglist);
8237 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8238 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
8239 #ifdef POINTERS_EXTEND_UNSIGNED
8240 if (GET_MODE(mem) != Pmode)
8241 mem = convert_memory_address (Pmode, mem);
8243 value = expand_expr (arg1, NULL_RTX, mode, 0);
8245 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
8246 MEM_VOLATILE_P (mem) = 1;
8248 if (target && register_operand (target, mode))
8251 ret = gen_reg_rtx (mode);
8253 emit_insn (gen_mf ());
8255 /* Special case for fetchadd instructions. */
8256 if (binoptab == add_optab && fetchadd_operand (value, VOIDmode))
8259 insn = gen_fetchadd_acq_si (ret, mem, value);
8261 insn = gen_fetchadd_acq_di (ret, mem, value);
8266 tmp = gen_reg_rtx (mode);
8267 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8268 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8269 emit_move_insn (tmp, mem);
8271 label = gen_label_rtx ();
8273 emit_move_insn (ret, tmp);
8274 convert_move (ccv, tmp, /*unsignedp=*/1);
8276 /* Perform the specific operation. Special case NAND by noticing
8277 one_cmpl_optab instead. */
8278 if (binoptab == one_cmpl_optab)
8280 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
8281 binoptab = and_optab;
8283 tmp = expand_binop (mode, binoptab, tmp, value, tmp, 1, OPTAB_WIDEN);
8286 insn = gen_cmpxchg_acq_si (tmp, mem, tmp, ccv);
8288 insn = gen_cmpxchg_acq_di (tmp, mem, tmp, ccv);
8291 emit_cmp_and_jump_insns (tmp, ret, NE, 0, mode, 1, label);
8296 /* Expand op_and_fetch intrinsics. The basic code sequence is:
8303 ret = tmp <op> value;
8304 cmpxchgsz.acq tmp = [ptr], ret
8305 } while (tmp != old)
8309 ia64_expand_op_and_fetch (optab binoptab, enum machine_mode mode,
8310 tree arglist, rtx target)
8312 rtx old, label, tmp, ret, ccv, insn, mem, value;
8315 arg0 = TREE_VALUE (arglist);
8316 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8317 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
8318 #ifdef POINTERS_EXTEND_UNSIGNED
8319 if (GET_MODE(mem) != Pmode)
8320 mem = convert_memory_address (Pmode, mem);
8323 value = expand_expr (arg1, NULL_RTX, mode, 0);
8325 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
8326 MEM_VOLATILE_P (mem) = 1;
8328 if (target && ! register_operand (target, mode))
8331 emit_insn (gen_mf ());
8332 tmp = gen_reg_rtx (mode);
8333 old = gen_reg_rtx (mode);
8334 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8335 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8337 emit_move_insn (tmp, mem);
8339 label = gen_label_rtx ();
8341 emit_move_insn (old, tmp);
8342 convert_move (ccv, tmp, /*unsignedp=*/1);
8344 /* Perform the specific operation. Special case NAND by noticing
8345 one_cmpl_optab instead. */
8346 if (binoptab == one_cmpl_optab)
8348 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
8349 binoptab = and_optab;
8351 ret = expand_binop (mode, binoptab, tmp, value, target, 1, OPTAB_WIDEN);
8354 insn = gen_cmpxchg_acq_si (tmp, mem, ret, ccv);
8356 insn = gen_cmpxchg_acq_di (tmp, mem, ret, ccv);
8359 emit_cmp_and_jump_insns (tmp, old, NE, 0, mode, 1, label);
8364 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8368 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8371 For bool_ it's the same except return ret == oldval.
8375 ia64_expand_compare_and_swap (enum machine_mode rmode, enum machine_mode mode,
8376 int boolp, tree arglist, rtx target)
8378 tree arg0, arg1, arg2;
8379 rtx mem, old, new, ccv, tmp, insn;
8381 arg0 = TREE_VALUE (arglist);
8382 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8383 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
8384 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8385 old = expand_expr (arg1, NULL_RTX, mode, 0);
8386 new = expand_expr (arg2, NULL_RTX, mode, 0);
8388 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8389 MEM_VOLATILE_P (mem) = 1;
8391 if (GET_MODE (old) != mode)
8392 old = convert_to_mode (mode, old, /*unsignedp=*/1);
8393 if (GET_MODE (new) != mode)
8394 new = convert_to_mode (mode, new, /*unsignedp=*/1);
8396 if (! register_operand (old, mode))
8397 old = copy_to_mode_reg (mode, old);
8398 if (! register_operand (new, mode))
8399 new = copy_to_mode_reg (mode, new);
8401 if (! boolp && target && register_operand (target, mode))
8404 tmp = gen_reg_rtx (mode);
8406 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8407 convert_move (ccv, old, /*unsignedp=*/1);
8408 emit_insn (gen_mf ());
8410 insn = gen_cmpxchg_acq_si (tmp, mem, new, ccv);
8412 insn = gen_cmpxchg_acq_di (tmp, mem, new, ccv);
8418 target = gen_reg_rtx (rmode);
8419 return emit_store_flag_force (target, EQ, tmp, old, mode, 1, 1);
8425 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8428 ia64_expand_lock_test_and_set (enum machine_mode mode, tree arglist,
8432 rtx mem, new, ret, insn;
8434 arg0 = TREE_VALUE (arglist);
8435 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8436 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8437 new = expand_expr (arg1, NULL_RTX, mode, 0);
8439 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8440 MEM_VOLATILE_P (mem) = 1;
8441 if (! register_operand (new, mode))
8442 new = copy_to_mode_reg (mode, new);
8444 if (target && register_operand (target, mode))
8447 ret = gen_reg_rtx (mode);
8450 insn = gen_xchgsi (ret, mem, new);
8452 insn = gen_xchgdi (ret, mem, new);
8458 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8461 ia64_expand_lock_release (enum machine_mode mode, tree arglist,
8462 rtx target ATTRIBUTE_UNUSED)
8467 arg0 = TREE_VALUE (arglist);
8468 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8470 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8471 MEM_VOLATILE_P (mem) = 1;
8473 emit_move_insn (mem, const0_rtx);
8479 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8480 enum machine_mode mode ATTRIBUTE_UNUSED,
8481 int ignore ATTRIBUTE_UNUSED)
8483 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8484 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8485 tree arglist = TREE_OPERAND (exp, 1);
8486 enum machine_mode rmode = VOIDmode;
8490 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8491 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8496 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8497 case IA64_BUILTIN_LOCK_RELEASE_SI:
8498 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8499 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8500 case IA64_BUILTIN_FETCH_AND_OR_SI:
8501 case IA64_BUILTIN_FETCH_AND_AND_SI:
8502 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8503 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8504 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8505 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8506 case IA64_BUILTIN_OR_AND_FETCH_SI:
8507 case IA64_BUILTIN_AND_AND_FETCH_SI:
8508 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8509 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8513 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8518 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8523 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8524 case IA64_BUILTIN_LOCK_RELEASE_DI:
8525 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8526 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8527 case IA64_BUILTIN_FETCH_AND_OR_DI:
8528 case IA64_BUILTIN_FETCH_AND_AND_DI:
8529 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8530 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8531 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8532 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8533 case IA64_BUILTIN_OR_AND_FETCH_DI:
8534 case IA64_BUILTIN_AND_AND_FETCH_DI:
8535 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8536 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8546 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8547 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8548 return ia64_expand_compare_and_swap (rmode, mode, 1, arglist,
8551 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8552 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8553 return ia64_expand_compare_and_swap (rmode, mode, 0, arglist,
8556 case IA64_BUILTIN_SYNCHRONIZE:
8557 emit_insn (gen_mf ());
8560 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8561 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8562 return ia64_expand_lock_test_and_set (mode, arglist, target);
8564 case IA64_BUILTIN_LOCK_RELEASE_SI:
8565 case IA64_BUILTIN_LOCK_RELEASE_DI:
8566 return ia64_expand_lock_release (mode, arglist, target);
8568 case IA64_BUILTIN_BSP:
8569 if (! target || ! register_operand (target, DImode))
8570 target = gen_reg_rtx (DImode);
8571 emit_insn (gen_bsp_value (target));
8572 #ifdef POINTERS_EXTEND_UNSIGNED
8573 target = convert_memory_address (ptr_mode, target);
8577 case IA64_BUILTIN_FLUSHRS:
8578 emit_insn (gen_flushrs ());
8581 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8582 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8583 return ia64_expand_fetch_and_op (add_optab, mode, arglist, target);
8585 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8586 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8587 return ia64_expand_fetch_and_op (sub_optab, mode, arglist, target);
8589 case IA64_BUILTIN_FETCH_AND_OR_SI:
8590 case IA64_BUILTIN_FETCH_AND_OR_DI:
8591 return ia64_expand_fetch_and_op (ior_optab, mode, arglist, target);
8593 case IA64_BUILTIN_FETCH_AND_AND_SI:
8594 case IA64_BUILTIN_FETCH_AND_AND_DI:
8595 return ia64_expand_fetch_and_op (and_optab, mode, arglist, target);
8597 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8598 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8599 return ia64_expand_fetch_and_op (xor_optab, mode, arglist, target);
8601 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8602 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8603 return ia64_expand_fetch_and_op (one_cmpl_optab, mode, arglist, target);
8605 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8606 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8607 return ia64_expand_op_and_fetch (add_optab, mode, arglist, target);
8609 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8610 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8611 return ia64_expand_op_and_fetch (sub_optab, mode, arglist, target);
8613 case IA64_BUILTIN_OR_AND_FETCH_SI:
8614 case IA64_BUILTIN_OR_AND_FETCH_DI:
8615 return ia64_expand_op_and_fetch (ior_optab, mode, arglist, target);
8617 case IA64_BUILTIN_AND_AND_FETCH_SI:
8618 case IA64_BUILTIN_AND_AND_FETCH_DI:
8619 return ia64_expand_op_and_fetch (and_optab, mode, arglist, target);
8621 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8622 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8623 return ia64_expand_op_and_fetch (xor_optab, mode, arglist, target);
8625 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8626 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8627 return ia64_expand_op_and_fetch (one_cmpl_optab, mode, arglist, target);
8636 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8637 most significant bits of the stack slot. */
8640 ia64_hpux_function_arg_padding (enum machine_mode mode, tree type)
8642 /* Exception to normal case for structures/unions/etc. */
8644 if (type && AGGREGATE_TYPE_P (type)
8645 && int_size_in_bytes (type) < UNITS_PER_WORD)
8648 /* Fall back to the default. */
8649 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
8652 /* Linked list of all external functions that are to be emitted by GCC.
8653 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8654 order to avoid putting out names that are never really used. */
8656 struct extern_func_list
8658 struct extern_func_list *next; /* next external */
8659 char *name; /* name of the external */
8660 } *extern_func_head = 0;
8663 ia64_hpux_add_extern_decl (const char *name)
8665 struct extern_func_list *p;
8667 p = (struct extern_func_list *) xmalloc (sizeof (struct extern_func_list));
8668 p->name = xmalloc (strlen (name) + 1);
8669 strcpy(p->name, name);
8670 p->next = extern_func_head;
8671 extern_func_head = p;
8674 /* Print out the list of used global functions. */
8677 ia64_hpux_file_end (void)
8679 while (extern_func_head)
8681 const char *real_name;
8684 real_name = (* targetm.strip_name_encoding) (extern_func_head->name);
8685 decl = maybe_get_identifier (real_name);
8688 || (! TREE_ASM_WRITTEN (decl) && TREE_SYMBOL_REFERENCED (decl)))
8691 TREE_ASM_WRITTEN (decl) = 1;
8692 (*targetm.asm_out.globalize_label) (asm_out_file,
8693 extern_func_head->name);
8694 fputs (TYPE_ASM_OP, asm_out_file);
8695 assemble_name (asm_out_file, extern_func_head->name);
8696 putc (',', asm_out_file);
8697 fprintf (asm_out_file, TYPE_OPERAND_FMT, "function");
8698 putc ('\n', asm_out_file);
8700 extern_func_head = extern_func_head->next;
8704 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8707 ia64_hpux_init_libfuncs (void)
8709 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
8710 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
8711 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
8712 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
8713 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
8714 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
8715 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
8716 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
8718 /* ia64_expand_compare uses this. */
8719 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
8721 /* These should never be used. */
8722 set_optab_libfunc (eq_optab, TFmode, 0);
8723 set_optab_libfunc (ne_optab, TFmode, 0);
8724 set_optab_libfunc (gt_optab, TFmode, 0);
8725 set_optab_libfunc (ge_optab, TFmode, 0);
8726 set_optab_libfunc (lt_optab, TFmode, 0);
8727 set_optab_libfunc (le_optab, TFmode, 0);
8729 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
8730 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
8731 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
8732 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
8733 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
8734 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
8736 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
8737 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
8738 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
8739 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
8741 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
8742 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
8745 /* Rename the division and modulus functions in VMS. */
8748 ia64_vms_init_libfuncs (void)
8750 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
8751 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
8752 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
8753 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
8754 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
8755 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
8756 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
8757 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
8760 /* Switch to the section to which we should output X. The only thing
8761 special we do here is to honor small data. */
8764 ia64_select_rtx_section (enum machine_mode mode, rtx x,
8765 unsigned HOST_WIDE_INT align)
8767 if (GET_MODE_SIZE (mode) > 0
8768 && GET_MODE_SIZE (mode) <= ia64_section_threshold)
8771 default_elf_select_rtx_section (mode, x, align);
8774 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8775 Pretend flag_pic is always set. */
8778 ia64_rwreloc_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align)
8780 default_elf_select_section_1 (exp, reloc, align, true);
8784 ia64_rwreloc_unique_section (tree decl, int reloc)
8786 default_unique_section_1 (decl, reloc, true);
8790 ia64_rwreloc_select_rtx_section (enum machine_mode mode, rtx x,
8791 unsigned HOST_WIDE_INT align)
8793 int save_pic = flag_pic;
8795 ia64_select_rtx_section (mode, x, align);
8796 flag_pic = save_pic;
8800 ia64_rwreloc_section_type_flags (tree decl, const char *name, int reloc)
8802 return default_section_type_flags_1 (decl, name, reloc, true);
8806 /* Output the assembler code for a thunk function. THUNK_DECL is the
8807 declaration for the thunk function itself, FUNCTION is the decl for
8808 the target function. DELTA is an immediate constant offset to be
8809 added to THIS. If VCALL_OFFSET is nonzero, the word at
8810 *(*this + vcall_offset) should be added to THIS. */
8813 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8814 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8817 rtx this, insn, funexp;
8819 reload_completed = 1;
8820 epilogue_completed = 1;
8823 /* Set things up as ia64_expand_prologue might. */
8824 last_scratch_gr_reg = 15;
8826 memset (¤t_frame_info, 0, sizeof (current_frame_info));
8827 current_frame_info.spill_cfa_off = -16;
8828 current_frame_info.n_input_regs = 1;
8829 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
8831 if (!TARGET_REG_NAMES)
8832 reg_names[IN_REG (0)] = ia64_reg_numbers[0];
8834 /* Mark the end of the (empty) prologue. */
8835 emit_note (NOTE_INSN_PROLOGUE_END);
8837 this = gen_rtx_REG (Pmode, IN_REG (0));
8840 rtx tmp = gen_rtx_REG (ptr_mode, IN_REG (0));
8841 REG_POINTER (tmp) = 1;
8842 if (delta && CONST_OK_FOR_I (delta))
8844 emit_insn (gen_ptr_extend_plus_imm (this, tmp, GEN_INT (delta)));
8848 emit_insn (gen_ptr_extend (this, tmp));
8851 /* Apply the constant offset, if required. */
8854 rtx delta_rtx = GEN_INT (delta);
8856 if (!CONST_OK_FOR_I (delta))
8858 rtx tmp = gen_rtx_REG (Pmode, 2);
8859 emit_move_insn (tmp, delta_rtx);
8862 emit_insn (gen_adddi3 (this, this, delta_rtx));
8865 /* Apply the offset from the vtable, if required. */
8868 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8869 rtx tmp = gen_rtx_REG (Pmode, 2);
8873 rtx t = gen_rtx_REG (ptr_mode, 2);
8874 REG_POINTER (t) = 1;
8875 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this));
8876 if (CONST_OK_FOR_I (vcall_offset))
8878 emit_insn (gen_ptr_extend_plus_imm (tmp, t,
8883 emit_insn (gen_ptr_extend (tmp, t));
8886 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
8890 if (!CONST_OK_FOR_J (vcall_offset))
8892 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
8893 emit_move_insn (tmp2, vcall_offset_rtx);
8894 vcall_offset_rtx = tmp2;
8896 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
8900 emit_move_insn (gen_rtx_REG (ptr_mode, 2),
8901 gen_rtx_MEM (ptr_mode, tmp));
8903 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
8905 emit_insn (gen_adddi3 (this, this, tmp));
8908 /* Generate a tail call to the target function. */
8909 if (! TREE_USED (function))
8911 assemble_external (function);
8912 TREE_USED (function) = 1;
8914 funexp = XEXP (DECL_RTL (function), 0);
8915 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8916 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
8917 insn = get_last_insn ();
8918 SIBLING_CALL_P (insn) = 1;
8920 /* Code generation for calls relies on splitting. */
8921 reload_completed = 1;
8922 epilogue_completed = 1;
8923 try_split (PATTERN (insn), insn, 0);
8927 /* Run just enough of rest_of_compilation to get the insns emitted.
8928 There's not really enough bulk here to make other passes such as
8929 instruction scheduling worth while. Note that use_thunk calls
8930 assemble_start_function and assemble_end_function. */
8932 insn_locators_initialize ();
8933 emit_all_insn_group_barriers (NULL);
8934 insn = get_insns ();
8935 shorten_branches (insn);
8936 final_start_function (insn, file, 1);
8937 final (insn, file, 1, 0);
8938 final_end_function ();
8940 reload_completed = 0;
8941 epilogue_completed = 0;
8945 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
8948 ia64_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
8949 int incoming ATTRIBUTE_UNUSED)
8951 return gen_rtx_REG (Pmode, GR_REG (8));
8954 #include "gt-ia64.h"