1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return true if OP is either a i387 or SSE fp register.
22 (define_predicate "any_fp_register_operand"
23 (and (match_code "reg")
24 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
26 ;; Return true if OP is an i387 fp register.
27 (define_predicate "fp_register_operand"
28 (and (match_code "reg")
29 (match_test "FP_REGNO_P (REGNO (op))")))
31 ;; Return true if OP is a non-fp register_operand.
32 (define_predicate "register_and_not_any_fp_reg_operand"
33 (and (match_code "reg")
34 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
36 ;; Return true if OP is a register operand other than an i387 fp register.
37 (define_predicate "register_and_not_fp_reg_operand"
38 (and (match_code "reg")
39 (not (match_test "FP_REGNO_P (REGNO (op))"))))
41 ;; True if the operand is an MMX register.
42 (define_predicate "mmx_reg_operand"
43 (and (match_code "reg")
44 (match_test "MMX_REGNO_P (REGNO (op))")))
46 ;; True if the operand is an SSE register.
47 (define_predicate "sse_reg_operand"
48 (and (match_code "reg")
49 (match_test "SSE_REGNO_P (REGNO (op))")))
51 ;; True if the operand is a Q_REGS class register.
52 (define_predicate "q_regs_operand"
53 (match_operand 0 "register_operand")
55 if (GET_CODE (op) == SUBREG)
57 return ANY_QI_REG_P (op);
60 ;; Match an SI or HImode register for a zero_extract.
61 (define_special_predicate "ext_register_operand"
62 (match_operand 0 "register_operand")
64 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
65 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
67 if (GET_CODE (op) == SUBREG)
70 /* Be careful to accept only registers having upper parts. */
72 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
75 ;; Return true if op is the AX register.
76 (define_predicate "ax_reg_operand"
77 (and (match_code "reg")
78 (match_test "REGNO (op) == AX_REG")))
80 ;; Return true if op is the flags register.
81 (define_predicate "flags_reg_operand"
82 (and (match_code "reg")
83 (match_test "REGNO (op) == FLAGS_REG")))
85 ;; Return true if op is a QImode register operand other than
87 (define_predicate "ext_QIreg_operand"
88 (and (match_code "reg")
89 (match_test "TARGET_64BIT
90 && GET_MODE (op) == QImode
91 && REGNO (op) > BX_REG")))
93 ;; Similarly, but don't check mode of the operand.
94 (define_predicate "ext_QIreg_nomode_operand"
95 (and (match_code "reg")
96 (match_test "TARGET_64BIT
97 && REGNO (op) > BX_REG")))
99 ;; Return true if op is not xmm0 register.
100 (define_predicate "reg_not_xmm0_operand"
101 (match_operand 0 "register_operand")
103 if (GET_CODE (op) == SUBREG)
104 op = SUBREG_REG (op);
106 return !REG_P (op) || REGNO (op) != FIRST_SSE_REG;
109 ;; As above, but allow nonimmediate operands.
110 (define_predicate "nonimm_not_xmm0_operand"
111 (ior (match_operand 0 "memory_operand")
112 (match_operand 0 "reg_not_xmm0_operand")))
114 ;; Return true if VALUE can be stored in a sign extended immediate field.
115 (define_predicate "x86_64_immediate_operand"
116 (match_code "const_int,symbol_ref,label_ref,const")
119 return immediate_operand (op, mode);
121 switch (GET_CODE (op))
124 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
125 to be at least 32 and this all acceptable constants are
126 represented as CONST_INT. */
127 if (HOST_BITS_PER_WIDE_INT == 32)
131 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
132 return trunc_int_for_mode (val, SImode) == val;
137 /* For certain code models, the symbolic references are known to fit.
138 in CM_SMALL_PIC model we know it fits if it is local to the shared
139 library. Don't count TLS SYMBOL_REFs here, since they should fit
140 only if inside of UNSPEC handled below. */
141 /* TLS symbols are not constant. */
142 if (SYMBOL_REF_TLS_MODEL (op))
144 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
145 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
148 /* For certain code models, the code is near as well. */
149 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
150 || ix86_cmodel == CM_KERNEL);
153 /* We also may accept the offsetted memory references in certain
155 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
156 switch (XINT (XEXP (op, 0), 1))
158 case UNSPEC_GOTPCREL:
160 case UNSPEC_GOTNTPOFF:
167 if (GET_CODE (XEXP (op, 0)) == PLUS)
169 rtx op1 = XEXP (XEXP (op, 0), 0);
170 rtx op2 = XEXP (XEXP (op, 0), 1);
171 HOST_WIDE_INT offset;
173 if (ix86_cmodel == CM_LARGE)
175 if (!CONST_INT_P (op2))
177 offset = trunc_int_for_mode (INTVAL (op2), DImode);
178 switch (GET_CODE (op1))
181 /* TLS symbols are not constant. */
182 if (SYMBOL_REF_TLS_MODEL (op1))
184 /* For CM_SMALL assume that latest object is 16MB before
185 end of 31bits boundary. We may also accept pretty
186 large negative constants knowing that all objects are
187 in the positive half of address space. */
188 if ((ix86_cmodel == CM_SMALL
189 || (ix86_cmodel == CM_MEDIUM
190 && !SYMBOL_REF_FAR_ADDR_P (op1)))
191 && offset < 16*1024*1024
192 && trunc_int_for_mode (offset, SImode) == offset)
194 /* For CM_KERNEL we know that all object resist in the
195 negative half of 32bits address space. We may not
196 accept negative offsets, since they may be just off
197 and we may accept pretty large positive ones. */
198 if (ix86_cmodel == CM_KERNEL
200 && trunc_int_for_mode (offset, SImode) == offset)
205 /* These conditions are similar to SYMBOL_REF ones, just the
206 constraints for code models differ. */
207 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
208 && offset < 16*1024*1024
209 && trunc_int_for_mode (offset, SImode) == offset)
211 if (ix86_cmodel == CM_KERNEL
213 && trunc_int_for_mode (offset, SImode) == offset)
218 switch (XINT (op1, 1))
223 && trunc_int_for_mode (offset, SImode) == offset)
241 ;; Return true if VALUE can be stored in the zero extended immediate field.
242 (define_predicate "x86_64_zext_immediate_operand"
243 (match_code "const_double,const_int,symbol_ref,label_ref,const")
245 switch (GET_CODE (op))
248 if (HOST_BITS_PER_WIDE_INT == 32)
249 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
254 if (HOST_BITS_PER_WIDE_INT == 32)
255 return INTVAL (op) >= 0;
257 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
260 /* For certain code models, the symbolic references are known to fit. */
261 /* TLS symbols are not constant. */
262 if (SYMBOL_REF_TLS_MODEL (op))
264 return (ix86_cmodel == CM_SMALL
265 || (ix86_cmodel == CM_MEDIUM
266 && !SYMBOL_REF_FAR_ADDR_P (op)));
269 /* For certain code models, the code is near as well. */
270 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
273 /* We also may accept the offsetted memory references in certain
275 if (GET_CODE (XEXP (op, 0)) == PLUS)
277 rtx op1 = XEXP (XEXP (op, 0), 0);
278 rtx op2 = XEXP (XEXP (op, 0), 1);
280 if (ix86_cmodel == CM_LARGE)
282 switch (GET_CODE (op1))
285 /* TLS symbols are not constant. */
286 if (SYMBOL_REF_TLS_MODEL (op1))
288 /* For small code model we may accept pretty large positive
289 offsets, since one bit is available for free. Negative
290 offsets are limited by the size of NULL pointer area
291 specified by the ABI. */
292 if ((ix86_cmodel == CM_SMALL
293 || (ix86_cmodel == CM_MEDIUM
294 && !SYMBOL_REF_FAR_ADDR_P (op1)))
296 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
297 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
299 /* ??? For the kernel, we may accept adjustment of
300 -0x10000000, since we know that it will just convert
301 negative address space to positive, but perhaps this
302 is not worthwhile. */
306 /* These conditions are similar to SYMBOL_REF ones, just the
307 constraints for code models differ. */
308 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
310 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
311 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
327 ;; Return true if OP is general operand representable on x86_64.
328 (define_predicate "x86_64_general_operand"
329 (if_then_else (match_test "TARGET_64BIT")
330 (ior (match_operand 0 "nonimmediate_operand")
331 (match_operand 0 "x86_64_immediate_operand"))
332 (match_operand 0 "general_operand")))
334 ;; Return true if OP is general operand representable on x86_64
335 ;; as either sign extended or zero extended constant.
336 (define_predicate "x86_64_szext_general_operand"
337 (if_then_else (match_test "TARGET_64BIT")
338 (ior (match_operand 0 "nonimmediate_operand")
339 (match_operand 0 "x86_64_immediate_operand")
340 (match_operand 0 "x86_64_zext_immediate_operand"))
341 (match_operand 0 "general_operand")))
343 ;; Return true if OP is nonmemory operand representable on x86_64.
344 (define_predicate "x86_64_nonmemory_operand"
345 (if_then_else (match_test "TARGET_64BIT")
346 (ior (match_operand 0 "register_operand")
347 (match_operand 0 "x86_64_immediate_operand"))
348 (match_operand 0 "nonmemory_operand")))
350 ;; Return true if OP is nonmemory operand representable on x86_64.
351 (define_predicate "x86_64_szext_nonmemory_operand"
352 (if_then_else (match_test "TARGET_64BIT")
353 (ior (match_operand 0 "register_operand")
354 (match_operand 0 "x86_64_immediate_operand")
355 (match_operand 0 "x86_64_zext_immediate_operand"))
356 (match_operand 0 "nonmemory_operand")))
358 ;; Return true when operand is PIC expression that can be computed by lea
360 (define_predicate "pic_32bit_operand"
361 (match_code "const,symbol_ref,label_ref")
365 /* Rule out relocations that translate into 64bit constants. */
366 if (TARGET_64BIT && GET_CODE (op) == CONST)
369 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
371 if (GET_CODE (op) == UNSPEC
372 && (XINT (op, 1) == UNSPEC_GOTOFF
373 || XINT (op, 1) == UNSPEC_GOT))
376 return symbolic_operand (op, mode);
380 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
381 (define_predicate "x86_64_movabs_operand"
382 (if_then_else (match_test "!TARGET_64BIT || !flag_pic")
383 (match_operand 0 "nonmemory_operand")
384 (ior (match_operand 0 "register_operand")
385 (and (match_operand 0 "const_double_operand")
386 (match_test "GET_MODE_SIZE (mode) <= 8")))))
388 ;; Return true if OP is either a symbol reference or a sum of a symbol
389 ;; reference and a constant.
390 (define_predicate "symbolic_operand"
391 (match_code "symbol_ref,label_ref,const")
393 switch (GET_CODE (op))
401 if (GET_CODE (op) == SYMBOL_REF
402 || GET_CODE (op) == LABEL_REF
403 || (GET_CODE (op) == UNSPEC
404 && (XINT (op, 1) == UNSPEC_GOT
405 || XINT (op, 1) == UNSPEC_GOTOFF
406 || XINT (op, 1) == UNSPEC_GOTPCREL)))
408 if (GET_CODE (op) != PLUS
409 || !CONST_INT_P (XEXP (op, 1)))
413 if (GET_CODE (op) == SYMBOL_REF
414 || GET_CODE (op) == LABEL_REF)
416 /* Only @GOTOFF gets offsets. */
417 if (GET_CODE (op) != UNSPEC
418 || XINT (op, 1) != UNSPEC_GOTOFF)
421 op = XVECEXP (op, 0, 0);
422 if (GET_CODE (op) == SYMBOL_REF
423 || GET_CODE (op) == LABEL_REF)
432 ;; Return true if OP is a symbolic operand that resolves locally.
433 (define_predicate "local_symbolic_operand"
434 (match_code "const,label_ref,symbol_ref")
436 if (GET_CODE (op) == CONST
437 && GET_CODE (XEXP (op, 0)) == PLUS
438 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
439 op = XEXP (XEXP (op, 0), 0);
441 if (GET_CODE (op) == LABEL_REF)
444 if (GET_CODE (op) != SYMBOL_REF)
447 if (SYMBOL_REF_TLS_MODEL (op))
450 if (SYMBOL_REF_LOCAL_P (op))
453 /* There is, however, a not insubstantial body of code in the rest of
454 the compiler that assumes it can just stick the results of
455 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
456 /* ??? This is a hack. Should update the body of the compiler to
457 always create a DECL an invoke targetm.encode_section_info. */
458 if (strncmp (XSTR (op, 0), internal_label_prefix,
459 internal_label_prefix_len) == 0)
465 ;; Test for a legitimate @GOTOFF operand.
467 ;; VxWorks does not impose a fixed gap between segments; the run-time
468 ;; gap can be different from the object-file gap. We therefore can't
469 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
470 ;; same segment as the GOT. Unfortunately, the flexibility of linker
471 ;; scripts means that we can't be sure of that in general, so assume
472 ;; that @GOTOFF is never valid on VxWorks.
473 (define_predicate "gotoff_operand"
474 (and (match_test "!TARGET_VXWORKS_RTP")
475 (match_operand 0 "local_symbolic_operand")))
477 ;; Test for various thread-local symbols.
478 (define_predicate "tls_symbolic_operand"
479 (and (match_code "symbol_ref")
480 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
482 (define_predicate "tls_modbase_operand"
483 (and (match_code "symbol_ref")
484 (match_test "op == ix86_tls_module_base ()")))
486 (define_predicate "tp_or_register_operand"
487 (ior (match_operand 0 "register_operand")
488 (and (match_code "unspec")
489 (match_test "XINT (op, 1) == UNSPEC_TP"))))
491 ;; Test for a pc-relative call operand
492 (define_predicate "constant_call_address_operand"
493 (match_code "symbol_ref")
495 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
497 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
502 ;; True for any non-virtual or eliminable register. Used in places where
503 ;; instantiation of such a register may cause the pattern to not be recognized.
504 (define_predicate "register_no_elim_operand"
505 (match_operand 0 "register_operand")
507 if (GET_CODE (op) == SUBREG)
508 op = SUBREG_REG (op);
509 return !(op == arg_pointer_rtx
510 || op == frame_pointer_rtx
511 || IN_RANGE (REGNO (op),
512 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
515 ;; P6 processors will jump to the address after the decrement when %esp
516 ;; is used as a call operand, so they will execute return address as a code.
517 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
519 (define_predicate "call_register_no_elim_operand"
520 (match_operand 0 "register_operand")
522 if (GET_CODE (op) == SUBREG)
523 op = SUBREG_REG (op);
525 if (!TARGET_64BIT && op == stack_pointer_rtx)
528 return register_no_elim_operand (op, mode);
531 ;; Similarly, but include the stack pointer. This is used to prevent esp
532 ;; from being used as an index reg.
533 (define_predicate "index_register_operand"
534 (match_operand 0 "register_operand")
536 if (GET_CODE (op) == SUBREG)
537 op = SUBREG_REG (op);
538 if (reload_in_progress || reload_completed)
539 return REG_OK_FOR_INDEX_STRICT_P (op);
541 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
544 ;; Return false if this is any eliminable register. Otherwise general_operand.
545 (define_predicate "general_no_elim_operand"
546 (if_then_else (match_code "reg,subreg")
547 (match_operand 0 "register_no_elim_operand")
548 (match_operand 0 "general_operand")))
550 ;; Return false if this is any eliminable register. Otherwise
551 ;; register_operand or a constant.
552 (define_predicate "nonmemory_no_elim_operand"
553 (ior (match_operand 0 "register_no_elim_operand")
554 (match_operand 0 "immediate_operand")))
556 ;; Test for a valid operand for a call instruction.
557 (define_predicate "call_insn_operand"
558 (ior (match_operand 0 "constant_call_address_operand")
559 (match_operand 0 "call_register_no_elim_operand")
560 (match_operand 0 "memory_operand")))
562 ;; Similarly, but for tail calls, in which we cannot allow memory references.
563 (define_predicate "sibcall_insn_operand"
564 (ior (match_operand 0 "constant_call_address_operand")
565 (match_operand 0 "register_no_elim_operand")))
567 ;; Match exactly zero.
568 (define_predicate "const0_operand"
569 (match_code "const_int,const_double,const_vector")
571 if (mode == VOIDmode)
572 mode = GET_MODE (op);
573 return op == CONST0_RTX (mode);
576 ;; Match exactly one.
577 (define_predicate "const1_operand"
578 (and (match_code "const_int")
579 (match_test "op == const1_rtx")))
581 ;; Match exactly eight.
582 (define_predicate "const8_operand"
583 (and (match_code "const_int")
584 (match_test "INTVAL (op) == 8")))
586 ;; Match exactly 128.
587 (define_predicate "const128_operand"
588 (and (match_code "const_int")
589 (match_test "INTVAL (op) == 128")))
591 ;; Match 2, 4, or 8. Used for leal multiplicands.
592 (define_predicate "const248_operand"
593 (match_code "const_int")
595 HOST_WIDE_INT i = INTVAL (op);
596 return i == 2 || i == 4 || i == 8;
600 (define_predicate "const_0_to_1_operand"
601 (and (match_code "const_int")
602 (match_test "op == const0_rtx || op == const1_rtx")))
605 (define_predicate "const_0_to_3_operand"
606 (and (match_code "const_int")
607 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
610 (define_predicate "const_0_to_7_operand"
611 (and (match_code "const_int")
612 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
615 (define_predicate "const_0_to_15_operand"
616 (and (match_code "const_int")
617 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
620 (define_predicate "const_0_to_31_operand"
621 (and (match_code "const_int")
622 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
625 (define_predicate "const_0_to_63_operand"
626 (and (match_code "const_int")
627 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
630 (define_predicate "const_0_to_255_operand"
631 (and (match_code "const_int")
632 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
634 ;; Match (0 to 255) * 8
635 (define_predicate "const_0_to_255_mul_8_operand"
636 (match_code "const_int")
638 unsigned HOST_WIDE_INT val = INTVAL (op);
639 return val <= 255*8 && val % 8 == 0;
642 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
643 ;; for shift & compare patterns, as shifting by 0 does not change flags).
644 (define_predicate "const_1_to_31_operand"
645 (and (match_code "const_int")
646 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
648 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
649 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
650 (define_predicate "const_1_to_63_operand"
651 (and (match_code "const_int")
652 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
655 (define_predicate "const_2_to_3_operand"
656 (and (match_code "const_int")
657 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
660 (define_predicate "const_4_to_5_operand"
661 (and (match_code "const_int")
662 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
665 (define_predicate "const_4_to_7_operand"
666 (and (match_code "const_int")
667 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
670 (define_predicate "const_6_to_7_operand"
671 (and (match_code "const_int")
672 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
675 (define_predicate "const_8_to_11_operand"
676 (and (match_code "const_int")
677 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
680 (define_predicate "const_12_to_15_operand"
681 (and (match_code "const_int")
682 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
684 ;; Match exactly one bit in 2-bit mask.
685 (define_predicate "const_pow2_1_to_2_operand"
686 (and (match_code "const_int")
687 (match_test "INTVAL (op) == 1 || INTVAL (op) == 2")))
689 ;; Match exactly one bit in 4-bit mask.
690 (define_predicate "const_pow2_1_to_8_operand"
691 (match_code "const_int")
693 unsigned int log = exact_log2 (INTVAL (op));
697 ;; Match exactly one bit in 8-bit mask.
698 (define_predicate "const_pow2_1_to_128_operand"
699 (match_code "const_int")
701 unsigned int log = exact_log2 (INTVAL (op));
705 ;; Match exactly one bit in 16-bit mask.
706 (define_predicate "const_pow2_1_to_32768_operand"
707 (match_code "const_int")
709 unsigned int log = exact_log2 (INTVAL (op));
713 ;; True if this is a constant appropriate for an increment or decrement.
714 (define_predicate "incdec_operand"
715 (match_code "const_int")
717 /* On Pentium4, the inc and dec operations causes extra dependency on flag
718 registers, since carry flag is not set. */
719 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
721 return op == const1_rtx || op == constm1_rtx;
724 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
725 (define_predicate "reg_or_pm1_operand"
726 (ior (match_operand 0 "register_operand")
727 (and (match_code "const_int")
728 (match_test "op == const1_rtx || op == constm1_rtx"))))
730 ;; True if OP is acceptable as operand of DImode shift expander.
731 (define_predicate "shiftdi_operand"
732 (if_then_else (match_test "TARGET_64BIT")
733 (match_operand 0 "nonimmediate_operand")
734 (match_operand 0 "register_operand")))
736 (define_predicate "ashldi_input_operand"
737 (if_then_else (match_test "TARGET_64BIT")
738 (match_operand 0 "nonimmediate_operand")
739 (match_operand 0 "reg_or_pm1_operand")))
741 ;; Return true if OP is a vector load from the constant pool with just
742 ;; the first element nonzero.
743 (define_predicate "zero_extended_scalar_load_operand"
747 op = maybe_get_pool_constant (op);
749 if (!(op && GET_CODE (op) == CONST_VECTOR))
752 n_elts = CONST_VECTOR_NUNITS (op);
754 for (n_elts--; n_elts > 0; n_elts--)
756 rtx elt = CONST_VECTOR_ELT (op, n_elts);
757 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
763 /* Return true if operand is a vector constant that is all ones. */
764 (define_predicate "vector_all_ones_operand"
765 (match_code "const_vector")
767 int nunits = GET_MODE_NUNITS (mode);
769 if (GET_CODE (op) == CONST_VECTOR
770 && CONST_VECTOR_NUNITS (op) == nunits)
773 for (i = 0; i < nunits; ++i)
775 rtx x = CONST_VECTOR_ELT (op, i);
776 if (x != constm1_rtx)
785 ; Return true when OP is operand acceptable for standard SSE move.
786 (define_predicate "vector_move_operand"
787 (ior (match_operand 0 "nonimmediate_operand")
788 (match_operand 0 "const0_operand")))
790 ;; Return true when OP is nonimmediate or standard SSE constant.
791 (define_predicate "nonimmediate_or_sse_const_operand"
792 (match_operand 0 "general_operand")
794 if (nonimmediate_operand (op, mode))
796 if (standard_sse_constant_p (op) > 0)
801 ;; Return true if OP is a register or a zero.
802 (define_predicate "reg_or_0_operand"
803 (ior (match_operand 0 "register_operand")
804 (match_operand 0 "const0_operand")))
806 ;; Return true if op if a valid address, and does not contain
807 ;; a segment override.
808 (define_special_predicate "no_seg_address_operand"
809 (match_operand 0 "address_operand")
811 struct ix86_address parts;
814 ok = ix86_decompose_address (op, &parts);
816 return parts.seg == SEG_DEFAULT;
819 ;; Return true if the rtx is known to be at least 32 bits aligned.
820 (define_predicate "aligned_operand"
821 (match_operand 0 "general_operand")
823 struct ix86_address parts;
826 /* Registers and immediate operands are always "aligned". */
830 /* All patterns using aligned_operand on memory operands ends up
831 in promoting memory operand to 64bit and thus causing memory mismatch. */
832 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
835 /* Don't even try to do any aligned optimizations with volatiles. */
836 if (MEM_VOLATILE_P (op))
839 if (MEM_ALIGN (op) >= 32)
844 /* Pushes and pops are only valid on the stack pointer. */
845 if (GET_CODE (op) == PRE_DEC
846 || GET_CODE (op) == POST_INC)
849 /* Decode the address. */
850 ok = ix86_decompose_address (op, &parts);
853 /* Look for some component that isn't known to be aligned. */
856 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
861 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
866 if (!CONST_INT_P (parts.disp)
867 || (INTVAL (parts.disp) & 3))
871 /* Didn't find one -- this must be an aligned address. */
875 ;; Return true if OP is memory operand with a displacement.
876 (define_predicate "memory_displacement_operand"
877 (match_operand 0 "memory_operand")
879 struct ix86_address parts;
882 ok = ix86_decompose_address (XEXP (op, 0), &parts);
884 return parts.disp != NULL_RTX;
887 ;; Return true if OP is memory operand with a displacement only.
888 (define_predicate "memory_displacement_only_operand"
889 (match_operand 0 "memory_operand")
891 struct ix86_address parts;
897 ok = ix86_decompose_address (XEXP (op, 0), &parts);
900 if (parts.base || parts.index)
903 return parts.disp != NULL_RTX;
906 ;; Return true if OP is memory operand which will need zero or
907 ;; one register at most, not counting stack pointer or frame pointer.
908 (define_predicate "cmpxchg8b_pic_memory_operand"
909 (match_operand 0 "memory_operand")
911 struct ix86_address parts;
914 ok = ix86_decompose_address (XEXP (op, 0), &parts);
916 if (parts.base == NULL_RTX
917 || parts.base == arg_pointer_rtx
918 || parts.base == frame_pointer_rtx
919 || parts.base == hard_frame_pointer_rtx
920 || parts.base == stack_pointer_rtx)
923 if (parts.index == NULL_RTX
924 || parts.index == arg_pointer_rtx
925 || parts.index == frame_pointer_rtx
926 || parts.index == hard_frame_pointer_rtx
927 || parts.index == stack_pointer_rtx)
934 ;; Return true if OP is memory operand that cannot be represented
935 ;; by the modRM array.
936 (define_predicate "long_memory_operand"
937 (and (match_operand 0 "memory_operand")
938 (match_test "memory_address_length (op)")))
940 ;; Return true if OP is a comparison operator that can be issued by fcmov.
941 (define_predicate "fcmov_comparison_operator"
942 (match_operand 0 "comparison_operator")
944 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
945 enum rtx_code code = GET_CODE (op);
947 if (inmode == CCFPmode || inmode == CCFPUmode)
949 if (!ix86_trivial_fp_comparison_operator (op, mode))
951 code = ix86_fp_compare_code_to_integer (code);
953 /* i387 supports just limited amount of conditional codes. */
956 case LTU: case GTU: case LEU: case GEU:
957 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
958 || inmode == CCCmode)
961 case ORDERED: case UNORDERED:
969 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
970 ;; The first set are supported directly; the second set can't be done with
971 ;; full IEEE support, i.e. NaNs.
973 ;; ??? It would seem that we have a lot of uses of this predicate that pass
974 ;; it the wrong mode. We got away with this because the old function didn't
975 ;; check the mode at all. Mirror that for now by calling this a special
978 (define_special_predicate "sse_comparison_operator"
979 (match_code "eq,lt,le,unordered,ne,unge,ungt,ordered"))
981 ;; Return true if OP is a comparison operator that can be issued by
982 ;; avx predicate generation instructions
983 (define_predicate "avx_comparison_float_operator"
984 (match_code "ne,eq,ge,gt,le,lt,unordered,ordered,uneq,unge,ungt,unle,unlt,ltgt"))
986 (define_predicate "ix86_comparison_int_operator"
987 (match_code "ne,eq,ge,gt,le,lt"))
989 (define_predicate "ix86_comparison_uns_operator"
990 (match_code "ne,eq,geu,gtu,leu,ltu"))
992 (define_predicate "bt_comparison_operator"
993 (match_code "ne,eq"))
995 ;; Return true if OP is a valid comparison operator in valid mode.
996 (define_predicate "ix86_comparison_operator"
997 (match_operand 0 "comparison_operator")
999 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1000 enum rtx_code code = GET_CODE (op);
1002 if (inmode == CCFPmode || inmode == CCFPUmode)
1003 return ix86_trivial_fp_comparison_operator (op, mode);
1010 if (inmode == CCmode || inmode == CCGCmode
1011 || inmode == CCGOCmode || inmode == CCNOmode)
1014 case LTU: case GTU: case LEU: case GEU:
1015 if (inmode == CCmode || inmode == CCCmode)
1018 case ORDERED: case UNORDERED:
1019 if (inmode == CCmode)
1023 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1031 ;; Return true if OP is a valid comparison operator
1032 ;; testing carry flag to be set.
1033 (define_predicate "ix86_carry_flag_operator"
1034 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1036 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1037 enum rtx_code code = GET_CODE (op);
1039 if (inmode == CCFPmode || inmode == CCFPUmode)
1041 if (!ix86_trivial_fp_comparison_operator (op, mode))
1043 code = ix86_fp_compare_code_to_integer (code);
1045 else if (inmode == CCCmode)
1046 return code == LTU || code == GTU;
1047 else if (inmode != CCmode)
1053 ;; Return true if this comparison only requires testing one flag bit.
1054 (define_predicate "ix86_trivial_fp_comparison_operator"
1055 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1057 ;; Return true if we know how to do this comparison. Others require
1058 ;; testing more than one flag bit, and we let the generic middle-end
1060 (define_predicate "ix86_fp_comparison_operator"
1061 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1062 == IX86_FPCMP_ARITH")
1063 (match_operand 0 "comparison_operator")
1064 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1066 ;; Same as above, but for swapped comparison used in fp_jcc_4_387.
1067 (define_predicate "ix86_swapped_fp_comparison_operator"
1068 (match_operand 0 "comparison_operator")
1070 enum rtx_code code = GET_CODE (op);
1073 PUT_CODE (op, swap_condition (code));
1074 ret = ix86_fp_comparison_operator (op, mode);
1075 PUT_CODE (op, code);
1079 ;; Nearly general operand, but accept any const_double, since we wish
1080 ;; to be able to drop them into memory rather than have them get pulled
1082 (define_predicate "cmp_fp_expander_operand"
1083 (ior (match_code "const_double")
1084 (match_operand 0 "general_operand")))
1086 ;; Return true if this is a valid binary floating-point operation.
1087 (define_predicate "binary_fp_operator"
1088 (match_code "plus,minus,mult,div"))
1090 ;; Return true if this is a multiply operation.
1091 (define_predicate "mult_operator"
1092 (match_code "mult"))
1094 ;; Return true if this is a division operation.
1095 (define_predicate "div_operator"
1098 ;; Return true if this is a float extend operation.
1099 (define_predicate "float_operator"
1100 (match_code "float"))
1102 ;; Return true for ARITHMETIC_P.
1103 (define_predicate "arith_or_logical_operator"
1104 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1105 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1107 ;; Return true for COMMUTATIVE_P.
1108 (define_predicate "commutative_operator"
1109 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1111 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1112 (define_predicate "promotable_binary_operator"
1113 (ior (match_code "plus,and,ior,xor,ashift")
1114 (and (match_code "mult")
1115 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1117 (define_predicate "compare_operator"
1118 (match_code "compare"))
1120 (define_predicate "absneg_operator"
1121 (match_code "abs,neg"))
1123 ;; Return true if OP is misaligned memory operand
1124 (define_predicate "misaligned_operand"
1125 (and (match_code "mem")
1126 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1128 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1129 (define_predicate "emms_operation"
1130 (match_code "parallel")
1134 if (XVECLEN (op, 0) != 17)
1137 for (i = 0; i < 8; i++)
1139 rtx elt = XVECEXP (op, 0, i+1);
1141 if (GET_CODE (elt) != CLOBBER
1142 || GET_CODE (SET_DEST (elt)) != REG
1143 || GET_MODE (SET_DEST (elt)) != XFmode
1144 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1147 elt = XVECEXP (op, 0, i+9);
1149 if (GET_CODE (elt) != CLOBBER
1150 || GET_CODE (SET_DEST (elt)) != REG
1151 || GET_MODE (SET_DEST (elt)) != DImode
1152 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1158 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1159 (define_predicate "vzeroall_operation"
1160 (match_code "parallel")
1162 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1164 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1167 for (i = 0; i < nregs; i++)
1169 rtx elt = XVECEXP (op, 0, i+1);
1171 if (GET_CODE (elt) != SET
1172 || GET_CODE (SET_DEST (elt)) != REG
1173 || GET_MODE (SET_DEST (elt)) != V8SImode
1174 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1175 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1181 ;; Return true if OP is a vzeroupper operation, known to be a PARALLEL.
1182 (define_predicate "vzeroupper_operation"
1183 (match_code "parallel")
1185 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1187 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1190 for (i = 0; i < nregs; i++)
1192 rtx elt = XVECEXP (op, 0, i+1);
1194 if (GET_CODE (elt) != CLOBBER
1195 || GET_CODE (SET_DEST (elt)) != REG
1196 || GET_MODE (SET_DEST (elt)) != V8SImode
1197 || REGNO (SET_DEST (elt)) != SSE_REGNO (i))
1203 ;; Return true if OP is a parallel for a vpermilp[ds] permute.
1204 ;; ??? It would be much easier if the PARALLEL for a VEC_SELECT
1205 ;; had a mode, but it doesn't. So we have 4 copies and install
1206 ;; the mode by hand.
1208 (define_predicate "avx_vpermilp_v8sf_operand"
1209 (and (match_code "parallel")
1210 (match_test "avx_vpermilp_parallel (op, V8SFmode)")))
1212 (define_predicate "avx_vpermilp_v4df_operand"
1213 (and (match_code "parallel")
1214 (match_test "avx_vpermilp_parallel (op, V4DFmode)")))
1216 (define_predicate "avx_vpermilp_v4sf_operand"
1217 (and (match_code "parallel")
1218 (match_test "avx_vpermilp_parallel (op, V4SFmode)")))
1220 (define_predicate "avx_vpermilp_v2df_operand"
1221 (and (match_code "parallel")
1222 (match_test "avx_vpermilp_parallel (op, V2DFmode)")))
1224 ;; Return true if OP is a parallel for a vperm2f128 permute.
1226 (define_predicate "avx_vperm2f128_v8sf_operand"
1227 (and (match_code "parallel")
1228 (match_test "avx_vperm2f128_parallel (op, V8SFmode)")))
1230 (define_predicate "avx_vperm2f128_v8si_operand"
1231 (and (match_code "parallel")
1232 (match_test "avx_vperm2f128_parallel (op, V8SImode)")))
1234 (define_predicate "avx_vperm2f128_v4df_operand"
1235 (and (match_code "parallel")
1236 (match_test "avx_vperm2f128_parallel (op, V4DFmode)")))
1238 ;; Return true if OP is a parallel for a vbroadcast permute.
1240 (define_predicate "avx_vbroadcast_operand"
1241 (and (match_code "parallel")
1242 (match_code "const_int" "a"))
1244 rtx elt = XVECEXP (op, 0, 0);
1245 int i, nelt = XVECLEN (op, 0);
1247 /* Don't bother checking there are the right number of operands,
1248 merely that they're all identical. */
1249 for (i = 1; i < nelt; ++i)
1250 if (XVECEXP (op, 0, i) != elt)