1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; The special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
39 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
40 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
41 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
42 ;; 'J' Print the appropriate jump operand.
44 ;; 'b' Print the QImode name of the register for the indicated operand.
45 ;; %b0 would print %al if operands[0] is reg 0.
46 ;; 'w' Likewise, print the HImode name of the register.
47 ;; 'k' Likewise, print the SImode name of the register.
48 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
49 ;; 'y' Print "st(0)" instead of "st" as a register.
54 [; Relocation specifiers
66 (UNSPEC_STACK_ALLOC 11)
68 (UNSPEC_SSE_PROLOGUE_SAVE 13)
73 (UNSPEC_TLS_LD_BASE 17)
75 ; Other random patterns
85 ; For SSE/MMX support:
96 (UNSPEC_NOP 45) ; prevents combiner cleverness
123 ; x87 Double output FP
124 (UNSPEC_SINCOS_COS 80)
125 (UNSPEC_SINCOS_SIN 81)
128 (UNSPEC_XTRACT_FRACT 84)
129 (UNSPEC_XTRACT_EXP 85)
130 (UNSPEC_FSCALE_FRACT 86)
131 (UNSPEC_FSCALE_EXP 87)
138 (UNSPEC_FRNDINT_FLOOR 96)
139 (UNSPEC_FRNDINT_CEIL 97)
140 (UNSPEC_FRNDINT_TRUNC 98)
141 (UNSPEC_FRNDINT_MASK_PM 99)
146 (UNSPEC_EH_RETURN 76)
150 [(UNSPECV_BLOCKAGE 0)
151 (UNSPECV_STACK_PROBE 10)
162 ;; Registers by name.
171 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
174 ;; In C guard expressions, put expressions which may be compile-time
175 ;; constants first. This allows for better optimization. For
176 ;; example, write "TARGET_64BIT && reload_completed", not
177 ;; "reload_completed && TARGET_64BIT".
180 ;; Processor type. This attribute must exactly match the processor_type
181 ;; enumeration in i386.h.
182 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona"
183 (const (symbol_ref "ix86_tune")))
185 ;; A basic instruction type. Refinements due to arguments to be
186 ;; provided in other attributes.
189 alu,alu1,negnot,imov,imovx,lea,
190 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
191 icmp,test,ibr,setcc,icmov,
192 push,pop,call,callv,leave,
194 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint,
195 sselog,sseiadd,sseishft,sseimul,
196 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
197 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
198 (const_string "other"))
200 ;; Main data type used by the insn
202 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
203 (const_string "unknown"))
205 ;; The CPU unit operations uses.
206 (define_attr "unit" "integer,i387,sse,mmx,unknown"
207 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint")
208 (const_string "i387")
209 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
210 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
212 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
214 (eq_attr "type" "other")
215 (const_string "unknown")]
216 (const_string "integer")))
218 ;; The (bounding maximum) length of an instruction immediate.
219 (define_attr "length_immediate" ""
220 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
222 (eq_attr "unit" "i387,sse,mmx")
224 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
226 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
227 (eq_attr "type" "imov,test")
228 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
229 (eq_attr "type" "call")
230 (if_then_else (match_operand 0 "constant_call_address_operand" "")
233 (eq_attr "type" "callv")
234 (if_then_else (match_operand 1 "constant_call_address_operand" "")
237 ;; We don't know the size before shorten_branches. Expect
238 ;; the instruction to fit for better scheduling.
239 (eq_attr "type" "ibr")
242 (symbol_ref "/* Update immediate_length and other attributes! */
245 ;; The (bounding maximum) length of an instruction address.
246 (define_attr "length_address" ""
247 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
249 (and (eq_attr "type" "call")
250 (match_operand 0 "constant_call_address_operand" ""))
252 (and (eq_attr "type" "callv")
253 (match_operand 1 "constant_call_address_operand" ""))
256 (symbol_ref "ix86_attr_length_address_default (insn)")))
258 ;; Set when length prefix is used.
259 (define_attr "prefix_data16" ""
260 (if_then_else (ior (eq_attr "mode" "HI")
261 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
265 ;; Set when string REP prefix is used.
266 (define_attr "prefix_rep" ""
267 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
271 ;; Set when 0f opcode prefix is used.
272 (define_attr "prefix_0f" ""
274 (ior (eq_attr "type" "imovx,setcc,icmov")
275 (eq_attr "unit" "sse,mmx"))
279 ;; Set when REX opcode prefix is used.
280 (define_attr "prefix_rex" ""
281 (cond [(and (eq_attr "mode" "DI")
282 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
284 (and (eq_attr "mode" "QI")
285 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
288 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
294 ;; Set when modrm byte is used.
295 (define_attr "modrm" ""
296 (cond [(eq_attr "type" "str,cld,leave")
298 (eq_attr "unit" "i387")
300 (and (eq_attr "type" "incdec")
301 (ior (match_operand:SI 1 "register_operand" "")
302 (match_operand:HI 1 "register_operand" "")))
304 (and (eq_attr "type" "push")
305 (not (match_operand 1 "memory_operand" "")))
307 (and (eq_attr "type" "pop")
308 (not (match_operand 0 "memory_operand" "")))
310 (and (eq_attr "type" "imov")
311 (and (match_operand 0 "register_operand" "")
312 (match_operand 1 "immediate_operand" "")))
314 (and (eq_attr "type" "call")
315 (match_operand 0 "constant_call_address_operand" ""))
317 (and (eq_attr "type" "callv")
318 (match_operand 1 "constant_call_address_operand" ""))
323 ;; The (bounding maximum) length of an instruction in bytes.
324 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
325 ;; Later we may want to split them and compute proper length as for
327 (define_attr "length" ""
328 (cond [(eq_attr "type" "other,multi,fistp,frndint")
330 (eq_attr "type" "fcmp")
332 (eq_attr "unit" "i387")
334 (plus (attr "prefix_data16")
335 (attr "length_address")))]
336 (plus (plus (attr "modrm")
337 (plus (attr "prefix_0f")
338 (plus (attr "prefix_rex")
340 (plus (attr "prefix_rep")
341 (plus (attr "prefix_data16")
342 (plus (attr "length_immediate")
343 (attr "length_address")))))))
345 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
346 ;; `store' if there is a simple memory reference therein, or `unknown'
347 ;; if the instruction is complex.
349 (define_attr "memory" "none,load,store,both,unknown"
350 (cond [(eq_attr "type" "other,multi,str")
351 (const_string "unknown")
352 (eq_attr "type" "lea,fcmov,fpspc,cld")
353 (const_string "none")
354 (eq_attr "type" "fistp,leave")
355 (const_string "both")
356 (eq_attr "type" "frndint")
357 (const_string "load")
358 (eq_attr "type" "push")
359 (if_then_else (match_operand 1 "memory_operand" "")
360 (const_string "both")
361 (const_string "store"))
362 (eq_attr "type" "pop")
363 (if_then_else (match_operand 0 "memory_operand" "")
364 (const_string "both")
365 (const_string "load"))
366 (eq_attr "type" "setcc")
367 (if_then_else (match_operand 0 "memory_operand" "")
368 (const_string "store")
369 (const_string "none"))
370 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
371 (if_then_else (ior (match_operand 0 "memory_operand" "")
372 (match_operand 1 "memory_operand" ""))
373 (const_string "load")
374 (const_string "none"))
375 (eq_attr "type" "ibr")
376 (if_then_else (match_operand 0 "memory_operand" "")
377 (const_string "load")
378 (const_string "none"))
379 (eq_attr "type" "call")
380 (if_then_else (match_operand 0 "constant_call_address_operand" "")
381 (const_string "none")
382 (const_string "load"))
383 (eq_attr "type" "callv")
384 (if_then_else (match_operand 1 "constant_call_address_operand" "")
385 (const_string "none")
386 (const_string "load"))
387 (and (eq_attr "type" "alu1,negnot,ishift1")
388 (match_operand 1 "memory_operand" ""))
389 (const_string "both")
390 (and (match_operand 0 "memory_operand" "")
391 (match_operand 1 "memory_operand" ""))
392 (const_string "both")
393 (match_operand 0 "memory_operand" "")
394 (const_string "store")
395 (match_operand 1 "memory_operand" "")
396 (const_string "load")
398 "!alu1,negnot,ishift1,
399 imov,imovx,icmp,test,
401 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
402 mmx,mmxmov,mmxcmp,mmxcvt")
403 (match_operand 2 "memory_operand" ""))
404 (const_string "load")
405 (and (eq_attr "type" "icmov")
406 (match_operand 3 "memory_operand" ""))
407 (const_string "load")
409 (const_string "none")))
411 ;; Indicates if an instruction has both an immediate and a displacement.
413 (define_attr "imm_disp" "false,true,unknown"
414 (cond [(eq_attr "type" "other,multi")
415 (const_string "unknown")
416 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
417 (and (match_operand 0 "memory_displacement_operand" "")
418 (match_operand 1 "immediate_operand" "")))
419 (const_string "true")
420 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
421 (and (match_operand 0 "memory_displacement_operand" "")
422 (match_operand 2 "immediate_operand" "")))
423 (const_string "true")
425 (const_string "false")))
427 ;; Indicates if an FP operation has an integer source.
429 (define_attr "fp_int_src" "false,true"
430 (const_string "false"))
432 ;; Defines rounding mode of an FP operation.
434 (define_attr "i387_cw" "floor,ceil,trunc,mask_pm,any"
435 (const_string "any"))
437 ;; Describe a user's asm statement.
438 (define_asm_attributes
439 [(set_attr "length" "128")
440 (set_attr "type" "multi")])
442 ;; Scheduling descriptions
444 (include "pentium.md")
447 (include "athlon.md")
450 ;; Operand and operator predicates
452 (include "predicates.md")
455 ;; Compare instructions.
457 ;; All compare insns have expanders that save the operands away without
458 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
459 ;; after the cmp) will actually emit the cmpM.
461 (define_expand "cmpdi"
462 [(set (reg:CC FLAGS_REG)
463 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
464 (match_operand:DI 1 "x86_64_general_operand" "")))]
467 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
468 operands[0] = force_reg (DImode, operands[0]);
469 ix86_compare_op0 = operands[0];
470 ix86_compare_op1 = operands[1];
474 (define_expand "cmpsi"
475 [(set (reg:CC FLAGS_REG)
476 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
477 (match_operand:SI 1 "general_operand" "")))]
480 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
481 operands[0] = force_reg (SImode, operands[0]);
482 ix86_compare_op0 = operands[0];
483 ix86_compare_op1 = operands[1];
487 (define_expand "cmphi"
488 [(set (reg:CC FLAGS_REG)
489 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
490 (match_operand:HI 1 "general_operand" "")))]
493 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
494 operands[0] = force_reg (HImode, operands[0]);
495 ix86_compare_op0 = operands[0];
496 ix86_compare_op1 = operands[1];
500 (define_expand "cmpqi"
501 [(set (reg:CC FLAGS_REG)
502 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
503 (match_operand:QI 1 "general_operand" "")))]
506 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
507 operands[0] = force_reg (QImode, operands[0]);
508 ix86_compare_op0 = operands[0];
509 ix86_compare_op1 = operands[1];
513 (define_insn "cmpdi_ccno_1_rex64"
515 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
516 (match_operand:DI 1 "const0_operand" "n,n")))]
517 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
519 test{q}\t{%0, %0|%0, %0}
520 cmp{q}\t{%1, %0|%0, %1}"
521 [(set_attr "type" "test,icmp")
522 (set_attr "length_immediate" "0,1")
523 (set_attr "mode" "DI")])
525 (define_insn "*cmpdi_minus_1_rex64"
527 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
528 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
530 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
531 "cmp{q}\t{%1, %0|%0, %1}"
532 [(set_attr "type" "icmp")
533 (set_attr "mode" "DI")])
535 (define_expand "cmpdi_1_rex64"
536 [(set (reg:CC FLAGS_REG)
537 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
538 (match_operand:DI 1 "general_operand" "")))]
542 (define_insn "cmpdi_1_insn_rex64"
544 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
545 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
546 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
547 "cmp{q}\t{%1, %0|%0, %1}"
548 [(set_attr "type" "icmp")
549 (set_attr "mode" "DI")])
552 (define_insn "*cmpsi_ccno_1"
554 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
555 (match_operand:SI 1 "const0_operand" "n,n")))]
556 "ix86_match_ccmode (insn, CCNOmode)"
558 test{l}\t{%0, %0|%0, %0}
559 cmp{l}\t{%1, %0|%0, %1}"
560 [(set_attr "type" "test,icmp")
561 (set_attr "length_immediate" "0,1")
562 (set_attr "mode" "SI")])
564 (define_insn "*cmpsi_minus_1"
566 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
567 (match_operand:SI 1 "general_operand" "ri,mr"))
569 "ix86_match_ccmode (insn, CCGOCmode)"
570 "cmp{l}\t{%1, %0|%0, %1}"
571 [(set_attr "type" "icmp")
572 (set_attr "mode" "SI")])
574 (define_expand "cmpsi_1"
575 [(set (reg:CC FLAGS_REG)
576 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
577 (match_operand:SI 1 "general_operand" "ri,mr")))]
581 (define_insn "*cmpsi_1_insn"
583 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
584 (match_operand:SI 1 "general_operand" "ri,mr")))]
585 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
586 && ix86_match_ccmode (insn, CCmode)"
587 "cmp{l}\t{%1, %0|%0, %1}"
588 [(set_attr "type" "icmp")
589 (set_attr "mode" "SI")])
591 (define_insn "*cmphi_ccno_1"
593 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
594 (match_operand:HI 1 "const0_operand" "n,n")))]
595 "ix86_match_ccmode (insn, CCNOmode)"
597 test{w}\t{%0, %0|%0, %0}
598 cmp{w}\t{%1, %0|%0, %1}"
599 [(set_attr "type" "test,icmp")
600 (set_attr "length_immediate" "0,1")
601 (set_attr "mode" "HI")])
603 (define_insn "*cmphi_minus_1"
605 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
606 (match_operand:HI 1 "general_operand" "ri,mr"))
608 "ix86_match_ccmode (insn, CCGOCmode)"
609 "cmp{w}\t{%1, %0|%0, %1}"
610 [(set_attr "type" "icmp")
611 (set_attr "mode" "HI")])
613 (define_insn "*cmphi_1"
615 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
616 (match_operand:HI 1 "general_operand" "ri,mr")))]
617 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
618 && ix86_match_ccmode (insn, CCmode)"
619 "cmp{w}\t{%1, %0|%0, %1}"
620 [(set_attr "type" "icmp")
621 (set_attr "mode" "HI")])
623 (define_insn "*cmpqi_ccno_1"
625 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
626 (match_operand:QI 1 "const0_operand" "n,n")))]
627 "ix86_match_ccmode (insn, CCNOmode)"
629 test{b}\t{%0, %0|%0, %0}
630 cmp{b}\t{$0, %0|%0, 0}"
631 [(set_attr "type" "test,icmp")
632 (set_attr "length_immediate" "0,1")
633 (set_attr "mode" "QI")])
635 (define_insn "*cmpqi_1"
637 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
638 (match_operand:QI 1 "general_operand" "qi,mq")))]
639 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
640 && ix86_match_ccmode (insn, CCmode)"
641 "cmp{b}\t{%1, %0|%0, %1}"
642 [(set_attr "type" "icmp")
643 (set_attr "mode" "QI")])
645 (define_insn "*cmpqi_minus_1"
647 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
648 (match_operand:QI 1 "general_operand" "qi,mq"))
650 "ix86_match_ccmode (insn, CCGOCmode)"
651 "cmp{b}\t{%1, %0|%0, %1}"
652 [(set_attr "type" "icmp")
653 (set_attr "mode" "QI")])
655 (define_insn "*cmpqi_ext_1"
658 (match_operand:QI 0 "general_operand" "Qm")
661 (match_operand 1 "ext_register_operand" "Q")
664 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
665 "cmp{b}\t{%h1, %0|%0, %h1}"
666 [(set_attr "type" "icmp")
667 (set_attr "mode" "QI")])
669 (define_insn "*cmpqi_ext_1_rex64"
672 (match_operand:QI 0 "register_operand" "Q")
675 (match_operand 1 "ext_register_operand" "Q")
678 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
679 "cmp{b}\t{%h1, %0|%0, %h1}"
680 [(set_attr "type" "icmp")
681 (set_attr "mode" "QI")])
683 (define_insn "*cmpqi_ext_2"
688 (match_operand 0 "ext_register_operand" "Q")
691 (match_operand:QI 1 "const0_operand" "n")))]
692 "ix86_match_ccmode (insn, CCNOmode)"
694 [(set_attr "type" "test")
695 (set_attr "length_immediate" "0")
696 (set_attr "mode" "QI")])
698 (define_expand "cmpqi_ext_3"
699 [(set (reg:CC FLAGS_REG)
703 (match_operand 0 "ext_register_operand" "")
706 (match_operand:QI 1 "general_operand" "")))]
710 (define_insn "cmpqi_ext_3_insn"
715 (match_operand 0 "ext_register_operand" "Q")
718 (match_operand:QI 1 "general_operand" "Qmn")))]
719 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
720 "cmp{b}\t{%1, %h0|%h0, %1}"
721 [(set_attr "type" "icmp")
722 (set_attr "mode" "QI")])
724 (define_insn "cmpqi_ext_3_insn_rex64"
729 (match_operand 0 "ext_register_operand" "Q")
732 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
733 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
734 "cmp{b}\t{%1, %h0|%h0, %1}"
735 [(set_attr "type" "icmp")
736 (set_attr "mode" "QI")])
738 (define_insn "*cmpqi_ext_4"
743 (match_operand 0 "ext_register_operand" "Q")
748 (match_operand 1 "ext_register_operand" "Q")
751 "ix86_match_ccmode (insn, CCmode)"
752 "cmp{b}\t{%h1, %h0|%h0, %h1}"
753 [(set_attr "type" "icmp")
754 (set_attr "mode" "QI")])
756 ;; These implement float point compares.
757 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
758 ;; which would allow mix and match FP modes on the compares. Which is what
759 ;; the old patterns did, but with many more of them.
761 (define_expand "cmpxf"
762 [(set (reg:CC FLAGS_REG)
763 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
764 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
767 ix86_compare_op0 = operands[0];
768 ix86_compare_op1 = operands[1];
772 (define_expand "cmpdf"
773 [(set (reg:CC FLAGS_REG)
774 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
775 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
776 "TARGET_80387 || TARGET_SSE2"
778 ix86_compare_op0 = operands[0];
779 ix86_compare_op1 = operands[1];
783 (define_expand "cmpsf"
784 [(set (reg:CC FLAGS_REG)
785 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
786 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
787 "TARGET_80387 || TARGET_SSE"
789 ix86_compare_op0 = operands[0];
790 ix86_compare_op1 = operands[1];
794 ;; FP compares, step 1:
795 ;; Set the FP condition codes.
797 ;; CCFPmode compare with exceptions
798 ;; CCFPUmode compare with no exceptions
800 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
801 ;; and that fp moves clobber the condition codes, and that there is
802 ;; currently no way to describe this fact to reg-stack. So there are
803 ;; no splitters yet for this.
805 ;; %%% YIKES! This scheme does not retain a strong connection between
806 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
807 ;; work! Only allow tos/mem with tos in op 0.
809 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
810 ;; things aren't as bad as they sound...
812 (define_insn "*cmpfp_0"
813 [(set (match_operand:HI 0 "register_operand" "=a")
815 [(compare:CCFP (match_operand 1 "register_operand" "f")
816 (match_operand 2 "const0_operand" "X"))]
819 && FLOAT_MODE_P (GET_MODE (operands[1]))
820 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
822 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
823 return "ftst\;fnstsw\t%0\;fstp\t%y0";
825 return "ftst\;fnstsw\t%0";
827 [(set_attr "type" "multi")
829 (cond [(match_operand:SF 1 "" "")
831 (match_operand:DF 1 "" "")
834 (const_string "XF")))])
836 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
837 ;; used to manage the reg stack popping would not be preserved.
839 (define_insn "*cmpfp_2_sf"
840 [(set (reg:CCFP FPSR_REG)
842 (match_operand:SF 0 "register_operand" "f")
843 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
845 "* return output_fp_compare (insn, operands, 0, 0);"
846 [(set_attr "type" "fcmp")
847 (set_attr "mode" "SF")])
849 (define_insn "*cmpfp_2_sf_1"
850 [(set (match_operand:HI 0 "register_operand" "=a")
853 (match_operand:SF 1 "register_operand" "f")
854 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
857 "* return output_fp_compare (insn, operands, 2, 0);"
858 [(set_attr "type" "fcmp")
859 (set_attr "mode" "SF")])
861 (define_insn "*cmpfp_2_df"
862 [(set (reg:CCFP FPSR_REG)
864 (match_operand:DF 0 "register_operand" "f")
865 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
867 "* return output_fp_compare (insn, operands, 0, 0);"
868 [(set_attr "type" "fcmp")
869 (set_attr "mode" "DF")])
871 (define_insn "*cmpfp_2_df_1"
872 [(set (match_operand:HI 0 "register_operand" "=a")
875 (match_operand:DF 1 "register_operand" "f")
876 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
879 "* return output_fp_compare (insn, operands, 2, 0);"
880 [(set_attr "type" "multi")
881 (set_attr "mode" "DF")])
883 (define_insn "*cmpfp_2_xf"
884 [(set (reg:CCFP FPSR_REG)
886 (match_operand:XF 0 "register_operand" "f")
887 (match_operand:XF 1 "register_operand" "f")))]
889 "* return output_fp_compare (insn, operands, 0, 0);"
890 [(set_attr "type" "fcmp")
891 (set_attr "mode" "XF")])
893 (define_insn "*cmpfp_2_xf_1"
894 [(set (match_operand:HI 0 "register_operand" "=a")
897 (match_operand:XF 1 "register_operand" "f")
898 (match_operand:XF 2 "register_operand" "f"))]
901 "* return output_fp_compare (insn, operands, 2, 0);"
902 [(set_attr "type" "multi")
903 (set_attr "mode" "XF")])
905 (define_insn "*cmpfp_2u"
906 [(set (reg:CCFPU FPSR_REG)
908 (match_operand 0 "register_operand" "f")
909 (match_operand 1 "register_operand" "f")))]
911 && FLOAT_MODE_P (GET_MODE (operands[0]))
912 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
913 "* return output_fp_compare (insn, operands, 0, 1);"
914 [(set_attr "type" "fcmp")
916 (cond [(match_operand:SF 1 "" "")
918 (match_operand:DF 1 "" "")
921 (const_string "XF")))])
923 (define_insn "*cmpfp_2u_1"
924 [(set (match_operand:HI 0 "register_operand" "=a")
927 (match_operand 1 "register_operand" "f")
928 (match_operand 2 "register_operand" "f"))]
931 && FLOAT_MODE_P (GET_MODE (operands[1]))
932 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
933 "* return output_fp_compare (insn, operands, 2, 1);"
934 [(set_attr "type" "multi")
936 (cond [(match_operand:SF 1 "" "")
938 (match_operand:DF 1 "" "")
941 (const_string "XF")))])
943 ;; Patterns to match the SImode-in-memory ficom instructions.
945 ;; %%% Play games with accepting gp registers, as otherwise we have to
946 ;; force them to memory during rtl generation, which is no good. We
947 ;; can get rid of this once we teach reload to do memory input reloads
950 (define_insn "*ficom_1"
951 [(set (reg:CCFP FPSR_REG)
953 (match_operand 0 "register_operand" "f,f")
954 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
955 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
956 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
959 ;; Split the not-really-implemented gp register case into a
960 ;; push-op-pop sequence.
962 ;; %%% This is most efficient, but am I gonna get in trouble
963 ;; for separating cc0_setter and cc0_user?
966 [(set (reg:CCFP FPSR_REG)
968 (match_operand:SF 0 "register_operand" "")
969 (float (match_operand:SI 1 "register_operand" ""))))]
970 "0 && TARGET_80387 && reload_completed"
971 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 1))
972 (set (reg:CCFP FPSR_REG) (compare:CCFP (match_dup 0) (match_dup 2)))
973 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
974 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
975 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
976 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
978 ;; FP compares, step 2
979 ;; Move the fpsw to ax.
981 (define_insn "x86_fnstsw_1"
982 [(set (match_operand:HI 0 "register_operand" "=a")
983 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
986 [(set_attr "length" "2")
987 (set_attr "mode" "SI")
988 (set_attr "unit" "i387")])
990 ;; FP compares, step 3
991 ;; Get ax into flags, general case.
993 (define_insn "x86_sahf_1"
994 [(set (reg:CC FLAGS_REG)
995 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
998 [(set_attr "length" "1")
999 (set_attr "athlon_decode" "vector")
1000 (set_attr "mode" "SI")])
1002 ;; Pentium Pro can do steps 1 through 3 in one go.
1004 (define_insn "*cmpfp_i"
1005 [(set (reg:CCFP FLAGS_REG)
1006 (compare:CCFP (match_operand 0 "register_operand" "f")
1007 (match_operand 1 "register_operand" "f")))]
1008 "TARGET_80387 && TARGET_CMOVE
1009 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1010 && FLOAT_MODE_P (GET_MODE (operands[0]))
1011 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1012 "* return output_fp_compare (insn, operands, 1, 0);"
1013 [(set_attr "type" "fcmp")
1015 (cond [(match_operand:SF 1 "" "")
1017 (match_operand:DF 1 "" "")
1020 (const_string "XF")))
1021 (set_attr "athlon_decode" "vector")])
1023 (define_insn "*cmpfp_i_sse"
1024 [(set (reg:CCFP FLAGS_REG)
1025 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1026 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1028 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1029 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1030 "* return output_fp_compare (insn, operands, 1, 0);"
1031 [(set_attr "type" "fcmp,ssecomi")
1033 (if_then_else (match_operand:SF 1 "" "")
1035 (const_string "DF")))
1036 (set_attr "athlon_decode" "vector")])
1038 (define_insn "*cmpfp_i_sse_only"
1039 [(set (reg:CCFP FLAGS_REG)
1040 (compare:CCFP (match_operand 0 "register_operand" "x")
1041 (match_operand 1 "nonimmediate_operand" "xm")))]
1042 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1043 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1044 "* return output_fp_compare (insn, operands, 1, 0);"
1045 [(set_attr "type" "ssecomi")
1047 (if_then_else (match_operand:SF 1 "" "")
1049 (const_string "DF")))
1050 (set_attr "athlon_decode" "vector")])
1052 (define_insn "*cmpfp_iu"
1053 [(set (reg:CCFPU FLAGS_REG)
1054 (compare:CCFPU (match_operand 0 "register_operand" "f")
1055 (match_operand 1 "register_operand" "f")))]
1056 "TARGET_80387 && TARGET_CMOVE
1057 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1058 && FLOAT_MODE_P (GET_MODE (operands[0]))
1059 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1060 "* return output_fp_compare (insn, operands, 1, 1);"
1061 [(set_attr "type" "fcmp")
1063 (cond [(match_operand:SF 1 "" "")
1065 (match_operand:DF 1 "" "")
1068 (const_string "XF")))
1069 (set_attr "athlon_decode" "vector")])
1071 (define_insn "*cmpfp_iu_sse"
1072 [(set (reg:CCFPU FLAGS_REG)
1073 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1074 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1076 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1077 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1078 "* return output_fp_compare (insn, operands, 1, 1);"
1079 [(set_attr "type" "fcmp,ssecomi")
1081 (if_then_else (match_operand:SF 1 "" "")
1083 (const_string "DF")))
1084 (set_attr "athlon_decode" "vector")])
1086 (define_insn "*cmpfp_iu_sse_only"
1087 [(set (reg:CCFPU FLAGS_REG)
1088 (compare:CCFPU (match_operand 0 "register_operand" "x")
1089 (match_operand 1 "nonimmediate_operand" "xm")))]
1090 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1091 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1092 "* return output_fp_compare (insn, operands, 1, 1);"
1093 [(set_attr "type" "ssecomi")
1095 (if_then_else (match_operand:SF 1 "" "")
1097 (const_string "DF")))
1098 (set_attr "athlon_decode" "vector")])
1100 ;; Move instructions.
1102 ;; General case of fullword move.
1104 (define_expand "movsi"
1105 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1106 (match_operand:SI 1 "general_operand" ""))]
1108 "ix86_expand_move (SImode, operands); DONE;")
1110 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1113 ;; %%% We don't use a post-inc memory reference because x86 is not a
1114 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1115 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1116 ;; targets without our curiosities, and it is just as easy to represent
1117 ;; this differently.
1119 (define_insn "*pushsi2"
1120 [(set (match_operand:SI 0 "push_operand" "=<")
1121 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1124 [(set_attr "type" "push")
1125 (set_attr "mode" "SI")])
1127 ;; For 64BIT abi we always round up to 8 bytes.
1128 (define_insn "*pushsi2_rex64"
1129 [(set (match_operand:SI 0 "push_operand" "=X")
1130 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1133 [(set_attr "type" "push")
1134 (set_attr "mode" "SI")])
1136 (define_insn "*pushsi2_prologue"
1137 [(set (match_operand:SI 0 "push_operand" "=<")
1138 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1139 (clobber (mem:BLK (scratch)))]
1142 [(set_attr "type" "push")
1143 (set_attr "mode" "SI")])
1145 (define_insn "*popsi1_epilogue"
1146 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1147 (mem:SI (reg:SI SP_REG)))
1148 (set (reg:SI SP_REG)
1149 (plus:SI (reg:SI SP_REG) (const_int 4)))
1150 (clobber (mem:BLK (scratch)))]
1153 [(set_attr "type" "pop")
1154 (set_attr "mode" "SI")])
1156 (define_insn "popsi1"
1157 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1158 (mem:SI (reg:SI SP_REG)))
1159 (set (reg:SI SP_REG)
1160 (plus:SI (reg:SI SP_REG) (const_int 4)))]
1163 [(set_attr "type" "pop")
1164 (set_attr "mode" "SI")])
1166 (define_insn "*movsi_xor"
1167 [(set (match_operand:SI 0 "register_operand" "=r")
1168 (match_operand:SI 1 "const0_operand" "i"))
1169 (clobber (reg:CC FLAGS_REG))]
1170 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1171 "xor{l}\t{%0, %0|%0, %0}"
1172 [(set_attr "type" "alu1")
1173 (set_attr "mode" "SI")
1174 (set_attr "length_immediate" "0")])
1176 (define_insn "*movsi_or"
1177 [(set (match_operand:SI 0 "register_operand" "=r")
1178 (match_operand:SI 1 "immediate_operand" "i"))
1179 (clobber (reg:CC FLAGS_REG))]
1181 && operands[1] == constm1_rtx
1182 && (TARGET_PENTIUM || optimize_size)"
1184 operands[1] = constm1_rtx;
1185 return "or{l}\t{%1, %0|%0, %1}";
1187 [(set_attr "type" "alu1")
1188 (set_attr "mode" "SI")
1189 (set_attr "length_immediate" "1")])
1191 (define_insn "*movsi_1"
1192 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1193 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1194 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1195 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1197 switch (get_attr_type (insn))
1200 if (get_attr_mode (insn) == MODE_TI)
1201 return "movdqa\t{%1, %0|%0, %1}";
1202 return "movd\t{%1, %0|%0, %1}";
1205 if (get_attr_mode (insn) == MODE_DI)
1206 return "movq\t{%1, %0|%0, %1}";
1207 return "movd\t{%1, %0|%0, %1}";
1210 return "lea{l}\t{%1, %0|%0, %1}";
1213 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1215 return "mov{l}\t{%1, %0|%0, %1}";
1219 (cond [(eq_attr "alternative" "2,3,4")
1220 (const_string "mmxmov")
1221 (eq_attr "alternative" "5,6,7")
1222 (const_string "ssemov")
1223 (and (ne (symbol_ref "flag_pic") (const_int 0))
1224 (match_operand:SI 1 "symbolic_operand" ""))
1225 (const_string "lea")
1227 (const_string "imov")))
1228 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1230 (define_insn "*movsi_1_nointernunit"
1231 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1232 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1233 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1234 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1236 switch (get_attr_type (insn))
1239 if (get_attr_mode (insn) == MODE_TI)
1240 return "movdqa\t{%1, %0|%0, %1}";
1241 return "movd\t{%1, %0|%0, %1}";
1244 if (get_attr_mode (insn) == MODE_DI)
1245 return "movq\t{%1, %0|%0, %1}";
1246 return "movd\t{%1, %0|%0, %1}";
1249 return "lea{l}\t{%1, %0|%0, %1}";
1252 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1254 return "mov{l}\t{%1, %0|%0, %1}";
1258 (cond [(eq_attr "alternative" "2,3,4")
1259 (const_string "mmxmov")
1260 (eq_attr "alternative" "5,6,7")
1261 (const_string "ssemov")
1262 (and (ne (symbol_ref "flag_pic") (const_int 0))
1263 (match_operand:SI 1 "symbolic_operand" ""))
1264 (const_string "lea")
1266 (const_string "imov")))
1267 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1269 ;; Stores and loads of ax to arbitrary constant address.
1270 ;; We fake an second form of instruction to force reload to load address
1271 ;; into register when rax is not available
1272 (define_insn "*movabssi_1_rex64"
1273 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1274 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1275 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1277 movabs{l}\t{%1, %P0|%P0, %1}
1278 mov{l}\t{%1, %a0|%a0, %1}"
1279 [(set_attr "type" "imov")
1280 (set_attr "modrm" "0,*")
1281 (set_attr "length_address" "8,0")
1282 (set_attr "length_immediate" "0,*")
1283 (set_attr "memory" "store")
1284 (set_attr "mode" "SI")])
1286 (define_insn "*movabssi_2_rex64"
1287 [(set (match_operand:SI 0 "register_operand" "=a,r")
1288 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1289 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1291 movabs{l}\t{%P1, %0|%0, %P1}
1292 mov{l}\t{%a1, %0|%0, %a1}"
1293 [(set_attr "type" "imov")
1294 (set_attr "modrm" "0,*")
1295 (set_attr "length_address" "8,0")
1296 (set_attr "length_immediate" "0")
1297 (set_attr "memory" "load")
1298 (set_attr "mode" "SI")])
1300 (define_insn "*swapsi"
1301 [(set (match_operand:SI 0 "register_operand" "+r")
1302 (match_operand:SI 1 "register_operand" "+r"))
1307 [(set_attr "type" "imov")
1308 (set_attr "pent_pair" "np")
1309 (set_attr "athlon_decode" "vector")
1310 (set_attr "mode" "SI")
1311 (set_attr "modrm" "0")])
1313 (define_expand "movhi"
1314 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1315 (match_operand:HI 1 "general_operand" ""))]
1317 "ix86_expand_move (HImode, operands); DONE;")
1319 (define_insn "*pushhi2"
1320 [(set (match_operand:HI 0 "push_operand" "=<,<")
1321 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1324 push{w}\t{|WORD PTR }%1
1326 [(set_attr "type" "push")
1327 (set_attr "mode" "HI")])
1329 ;; For 64BIT abi we always round up to 8 bytes.
1330 (define_insn "*pushhi2_rex64"
1331 [(set (match_operand:HI 0 "push_operand" "=X")
1332 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1335 [(set_attr "type" "push")
1336 (set_attr "mode" "QI")])
1338 (define_insn "*movhi_1"
1339 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1340 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1341 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1343 switch (get_attr_type (insn))
1346 /* movzwl is faster than movw on p2 due to partial word stalls,
1347 though not as fast as an aligned movl. */
1348 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1350 if (get_attr_mode (insn) == MODE_SI)
1351 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1353 return "mov{w}\t{%1, %0|%0, %1}";
1357 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1358 (const_string "imov")
1359 (and (eq_attr "alternative" "0")
1360 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1362 (eq (symbol_ref "TARGET_HIMODE_MATH")
1364 (const_string "imov")
1365 (and (eq_attr "alternative" "1,2")
1366 (match_operand:HI 1 "aligned_operand" ""))
1367 (const_string "imov")
1368 (and (ne (symbol_ref "TARGET_MOVX")
1370 (eq_attr "alternative" "0,2"))
1371 (const_string "imovx")
1373 (const_string "imov")))
1375 (cond [(eq_attr "type" "imovx")
1377 (and (eq_attr "alternative" "1,2")
1378 (match_operand:HI 1 "aligned_operand" ""))
1380 (and (eq_attr "alternative" "0")
1381 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1383 (eq (symbol_ref "TARGET_HIMODE_MATH")
1387 (const_string "HI")))])
1389 ;; Stores and loads of ax to arbitrary constant address.
1390 ;; We fake an second form of instruction to force reload to load address
1391 ;; into register when rax is not available
1392 (define_insn "*movabshi_1_rex64"
1393 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1394 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1395 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1397 movabs{w}\t{%1, %P0|%P0, %1}
1398 mov{w}\t{%1, %a0|%a0, %1}"
1399 [(set_attr "type" "imov")
1400 (set_attr "modrm" "0,*")
1401 (set_attr "length_address" "8,0")
1402 (set_attr "length_immediate" "0,*")
1403 (set_attr "memory" "store")
1404 (set_attr "mode" "HI")])
1406 (define_insn "*movabshi_2_rex64"
1407 [(set (match_operand:HI 0 "register_operand" "=a,r")
1408 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1409 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1411 movabs{w}\t{%P1, %0|%0, %P1}
1412 mov{w}\t{%a1, %0|%0, %a1}"
1413 [(set_attr "type" "imov")
1414 (set_attr "modrm" "0,*")
1415 (set_attr "length_address" "8,0")
1416 (set_attr "length_immediate" "0")
1417 (set_attr "memory" "load")
1418 (set_attr "mode" "HI")])
1420 (define_insn "*swaphi_1"
1421 [(set (match_operand:HI 0 "register_operand" "+r")
1422 (match_operand:HI 1 "register_operand" "+r"))
1425 "TARGET_PARTIAL_REG_STALL"
1427 [(set_attr "type" "imov")
1428 (set_attr "pent_pair" "np")
1429 (set_attr "mode" "HI")
1430 (set_attr "modrm" "0")])
1432 (define_insn "*swaphi_2"
1433 [(set (match_operand:HI 0 "register_operand" "+r")
1434 (match_operand:HI 1 "register_operand" "+r"))
1437 "! TARGET_PARTIAL_REG_STALL"
1439 [(set_attr "type" "imov")
1440 (set_attr "pent_pair" "np")
1441 (set_attr "mode" "SI")
1442 (set_attr "modrm" "0")])
1444 (define_expand "movstricthi"
1445 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1446 (match_operand:HI 1 "general_operand" ""))]
1447 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1449 /* Don't generate memory->memory moves, go through a register */
1450 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1451 operands[1] = force_reg (HImode, operands[1]);
1454 (define_insn "*movstricthi_1"
1455 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1456 (match_operand:HI 1 "general_operand" "rn,m"))]
1457 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1458 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1459 "mov{w}\t{%1, %0|%0, %1}"
1460 [(set_attr "type" "imov")
1461 (set_attr "mode" "HI")])
1463 (define_insn "*movstricthi_xor"
1464 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1465 (match_operand:HI 1 "const0_operand" "i"))
1466 (clobber (reg:CC FLAGS_REG))]
1468 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1469 "xor{w}\t{%0, %0|%0, %0}"
1470 [(set_attr "type" "alu1")
1471 (set_attr "mode" "HI")
1472 (set_attr "length_immediate" "0")])
1474 (define_expand "movqi"
1475 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1476 (match_operand:QI 1 "general_operand" ""))]
1478 "ix86_expand_move (QImode, operands); DONE;")
1480 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1481 ;; "push a byte". But actually we use pushw, which has the effect
1482 ;; of rounding the amount pushed up to a halfword.
1484 (define_insn "*pushqi2"
1485 [(set (match_operand:QI 0 "push_operand" "=X,X")
1486 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1489 push{w}\t{|word ptr }%1
1491 [(set_attr "type" "push")
1492 (set_attr "mode" "HI")])
1494 ;; For 64BIT abi we always round up to 8 bytes.
1495 (define_insn "*pushqi2_rex64"
1496 [(set (match_operand:QI 0 "push_operand" "=X")
1497 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1500 [(set_attr "type" "push")
1501 (set_attr "mode" "QI")])
1503 ;; Situation is quite tricky about when to choose full sized (SImode) move
1504 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1505 ;; partial register dependency machines (such as AMD Athlon), where QImode
1506 ;; moves issue extra dependency and for partial register stalls machines
1507 ;; that don't use QImode patterns (and QImode move cause stall on the next
1510 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1511 ;; register stall machines with, where we use QImode instructions, since
1512 ;; partial register stall can be caused there. Then we use movzx.
1513 (define_insn "*movqi_1"
1514 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1515 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1516 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1518 switch (get_attr_type (insn))
1521 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1523 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1525 if (get_attr_mode (insn) == MODE_SI)
1526 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1528 return "mov{b}\t{%1, %0|%0, %1}";
1532 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1533 (const_string "imov")
1534 (and (eq_attr "alternative" "3")
1535 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1537 (eq (symbol_ref "TARGET_QIMODE_MATH")
1539 (const_string "imov")
1540 (eq_attr "alternative" "3,5")
1541 (const_string "imovx")
1542 (and (ne (symbol_ref "TARGET_MOVX")
1544 (eq_attr "alternative" "2"))
1545 (const_string "imovx")
1547 (const_string "imov")))
1549 (cond [(eq_attr "alternative" "3,4,5")
1551 (eq_attr "alternative" "6")
1553 (eq_attr "type" "imovx")
1555 (and (eq_attr "type" "imov")
1556 (and (eq_attr "alternative" "0,1,2")
1557 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1560 ;; Avoid partial register stalls when not using QImode arithmetic
1561 (and (eq_attr "type" "imov")
1562 (and (eq_attr "alternative" "0,1,2")
1563 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1565 (eq (symbol_ref "TARGET_QIMODE_MATH")
1569 (const_string "QI")))])
1571 (define_expand "reload_outqi"
1572 [(parallel [(match_operand:QI 0 "" "=m")
1573 (match_operand:QI 1 "register_operand" "r")
1574 (match_operand:QI 2 "register_operand" "=&q")])]
1578 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1580 if (reg_overlap_mentioned_p (op2, op0))
1582 if (! q_regs_operand (op1, QImode))
1584 emit_insn (gen_movqi (op2, op1));
1587 emit_insn (gen_movqi (op0, op1));
1591 (define_insn "*swapqi"
1592 [(set (match_operand:QI 0 "register_operand" "+r")
1593 (match_operand:QI 1 "register_operand" "+r"))
1598 [(set_attr "type" "imov")
1599 (set_attr "pent_pair" "np")
1600 (set_attr "mode" "QI")
1601 (set_attr "modrm" "0")])
1603 (define_expand "movstrictqi"
1604 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1605 (match_operand:QI 1 "general_operand" ""))]
1606 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1608 /* Don't generate memory->memory moves, go through a register. */
1609 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1610 operands[1] = force_reg (QImode, operands[1]);
1613 (define_insn "*movstrictqi_1"
1614 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1615 (match_operand:QI 1 "general_operand" "*qn,m"))]
1616 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1617 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1618 "mov{b}\t{%1, %0|%0, %1}"
1619 [(set_attr "type" "imov")
1620 (set_attr "mode" "QI")])
1622 (define_insn "*movstrictqi_xor"
1623 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1624 (match_operand:QI 1 "const0_operand" "i"))
1625 (clobber (reg:CC FLAGS_REG))]
1626 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1627 "xor{b}\t{%0, %0|%0, %0}"
1628 [(set_attr "type" "alu1")
1629 (set_attr "mode" "QI")
1630 (set_attr "length_immediate" "0")])
1632 (define_insn "*movsi_extv_1"
1633 [(set (match_operand:SI 0 "register_operand" "=R")
1634 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1638 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1639 [(set_attr "type" "imovx")
1640 (set_attr "mode" "SI")])
1642 (define_insn "*movhi_extv_1"
1643 [(set (match_operand:HI 0 "register_operand" "=R")
1644 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1648 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1649 [(set_attr "type" "imovx")
1650 (set_attr "mode" "SI")])
1652 (define_insn "*movqi_extv_1"
1653 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1654 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1659 switch (get_attr_type (insn))
1662 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1664 return "mov{b}\t{%h1, %0|%0, %h1}";
1668 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1669 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1670 (ne (symbol_ref "TARGET_MOVX")
1672 (const_string "imovx")
1673 (const_string "imov")))
1675 (if_then_else (eq_attr "type" "imovx")
1677 (const_string "QI")))])
1679 (define_insn "*movqi_extv_1_rex64"
1680 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1681 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1686 switch (get_attr_type (insn))
1689 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1691 return "mov{b}\t{%h1, %0|%0, %h1}";
1695 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1696 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1697 (ne (symbol_ref "TARGET_MOVX")
1699 (const_string "imovx")
1700 (const_string "imov")))
1702 (if_then_else (eq_attr "type" "imovx")
1704 (const_string "QI")))])
1706 ;; Stores and loads of ax to arbitrary constant address.
1707 ;; We fake an second form of instruction to force reload to load address
1708 ;; into register when rax is not available
1709 (define_insn "*movabsqi_1_rex64"
1710 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1711 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1712 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1714 movabs{b}\t{%1, %P0|%P0, %1}
1715 mov{b}\t{%1, %a0|%a0, %1}"
1716 [(set_attr "type" "imov")
1717 (set_attr "modrm" "0,*")
1718 (set_attr "length_address" "8,0")
1719 (set_attr "length_immediate" "0,*")
1720 (set_attr "memory" "store")
1721 (set_attr "mode" "QI")])
1723 (define_insn "*movabsqi_2_rex64"
1724 [(set (match_operand:QI 0 "register_operand" "=a,r")
1725 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1726 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1728 movabs{b}\t{%P1, %0|%0, %P1}
1729 mov{b}\t{%a1, %0|%0, %a1}"
1730 [(set_attr "type" "imov")
1731 (set_attr "modrm" "0,*")
1732 (set_attr "length_address" "8,0")
1733 (set_attr "length_immediate" "0")
1734 (set_attr "memory" "load")
1735 (set_attr "mode" "QI")])
1737 (define_insn "*movsi_extzv_1"
1738 [(set (match_operand:SI 0 "register_operand" "=R")
1739 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1743 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1744 [(set_attr "type" "imovx")
1745 (set_attr "mode" "SI")])
1747 (define_insn "*movqi_extzv_2"
1748 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1749 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1754 switch (get_attr_type (insn))
1757 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1759 return "mov{b}\t{%h1, %0|%0, %h1}";
1763 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1764 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1765 (ne (symbol_ref "TARGET_MOVX")
1767 (const_string "imovx")
1768 (const_string "imov")))
1770 (if_then_else (eq_attr "type" "imovx")
1772 (const_string "QI")))])
1774 (define_insn "*movqi_extzv_2_rex64"
1775 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1776 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1781 switch (get_attr_type (insn))
1784 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1786 return "mov{b}\t{%h1, %0|%0, %h1}";
1790 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1791 (ne (symbol_ref "TARGET_MOVX")
1793 (const_string "imovx")
1794 (const_string "imov")))
1796 (if_then_else (eq_attr "type" "imovx")
1798 (const_string "QI")))])
1800 (define_insn "movsi_insv_1"
1801 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1804 (match_operand:SI 1 "general_operand" "Qmn"))]
1806 "mov{b}\t{%b1, %h0|%h0, %b1}"
1807 [(set_attr "type" "imov")
1808 (set_attr "mode" "QI")])
1810 (define_insn "movdi_insv_1_rex64"
1811 [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
1814 (match_operand:DI 1 "nonmemory_operand" "Qn"))]
1816 "mov{b}\t{%b1, %h0|%h0, %b1}"
1817 [(set_attr "type" "imov")
1818 (set_attr "mode" "QI")])
1820 (define_insn "*movqi_insv_2"
1821 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1824 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1827 "mov{b}\t{%h1, %h0|%h0, %h1}"
1828 [(set_attr "type" "imov")
1829 (set_attr "mode" "QI")])
1831 (define_expand "movdi"
1832 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1833 (match_operand:DI 1 "general_operand" ""))]
1835 "ix86_expand_move (DImode, operands); DONE;")
1837 (define_insn "*pushdi"
1838 [(set (match_operand:DI 0 "push_operand" "=<")
1839 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1843 (define_insn "pushdi2_rex64"
1844 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1845 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1850 [(set_attr "type" "push,multi")
1851 (set_attr "mode" "DI")])
1853 ;; Convert impossible pushes of immediate to existing instructions.
1854 ;; First try to get scratch register and go through it. In case this
1855 ;; fails, push sign extended lower part first and then overwrite
1856 ;; upper part by 32bit move.
1858 [(match_scratch:DI 2 "r")
1859 (set (match_operand:DI 0 "push_operand" "")
1860 (match_operand:DI 1 "immediate_operand" ""))]
1861 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1862 && !x86_64_immediate_operand (operands[1], DImode)"
1863 [(set (match_dup 2) (match_dup 1))
1864 (set (match_dup 0) (match_dup 2))]
1867 ;; We need to define this as both peepholer and splitter for case
1868 ;; peephole2 pass is not run.
1870 [(set (match_operand:DI 0 "push_operand" "")
1871 (match_operand:DI 1 "immediate_operand" ""))]
1872 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1873 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1874 [(set (match_dup 0) (match_dup 1))
1875 (set (match_dup 2) (match_dup 3))]
1876 "split_di (operands + 1, 1, operands + 2, operands + 3);
1877 operands[1] = gen_lowpart (DImode, operands[2]);
1878 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1883 [(set (match_operand:DI 0 "push_operand" "")
1884 (match_operand:DI 1 "immediate_operand" ""))]
1885 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1886 && !symbolic_operand (operands[1], DImode)
1887 && !x86_64_immediate_operand (operands[1], DImode)"
1888 [(set (match_dup 0) (match_dup 1))
1889 (set (match_dup 2) (match_dup 3))]
1890 "split_di (operands + 1, 1, operands + 2, operands + 3);
1891 operands[1] = gen_lowpart (DImode, operands[2]);
1892 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1896 (define_insn "*pushdi2_prologue_rex64"
1897 [(set (match_operand:DI 0 "push_operand" "=<")
1898 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1899 (clobber (mem:BLK (scratch)))]
1902 [(set_attr "type" "push")
1903 (set_attr "mode" "DI")])
1905 (define_insn "*popdi1_epilogue_rex64"
1906 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1907 (mem:DI (reg:DI SP_REG)))
1908 (set (reg:DI SP_REG)
1909 (plus:DI (reg:DI SP_REG) (const_int 8)))
1910 (clobber (mem:BLK (scratch)))]
1913 [(set_attr "type" "pop")
1914 (set_attr "mode" "DI")])
1916 (define_insn "popdi1"
1917 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1918 (mem:DI (reg:DI SP_REG)))
1919 (set (reg:DI SP_REG)
1920 (plus:DI (reg:DI SP_REG) (const_int 8)))]
1923 [(set_attr "type" "pop")
1924 (set_attr "mode" "DI")])
1926 (define_insn "*movdi_xor_rex64"
1927 [(set (match_operand:DI 0 "register_operand" "=r")
1928 (match_operand:DI 1 "const0_operand" "i"))
1929 (clobber (reg:CC FLAGS_REG))]
1930 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1931 && reload_completed"
1932 "xor{l}\t{%k0, %k0|%k0, %k0}"
1933 [(set_attr "type" "alu1")
1934 (set_attr "mode" "SI")
1935 (set_attr "length_immediate" "0")])
1937 (define_insn "*movdi_or_rex64"
1938 [(set (match_operand:DI 0 "register_operand" "=r")
1939 (match_operand:DI 1 "const_int_operand" "i"))
1940 (clobber (reg:CC FLAGS_REG))]
1941 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1943 && operands[1] == constm1_rtx"
1945 operands[1] = constm1_rtx;
1946 return "or{q}\t{%1, %0|%0, %1}";
1948 [(set_attr "type" "alu1")
1949 (set_attr "mode" "DI")
1950 (set_attr "length_immediate" "1")])
1952 (define_insn "*movdi_2"
1953 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1954 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1956 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1960 movq\t{%1, %0|%0, %1}
1961 movq\t{%1, %0|%0, %1}
1962 movq\t{%1, %0|%0, %1}
1963 movdqa\t{%1, %0|%0, %1}
1964 movq\t{%1, %0|%0, %1}"
1965 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1966 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1969 [(set (match_operand:DI 0 "push_operand" "")
1970 (match_operand:DI 1 "general_operand" ""))]
1971 "!TARGET_64BIT && reload_completed
1972 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1974 "ix86_split_long_move (operands); DONE;")
1976 ;; %%% This multiword shite has got to go.
1978 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1979 (match_operand:DI 1 "general_operand" ""))]
1980 "!TARGET_64BIT && reload_completed
1981 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1982 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1984 "ix86_split_long_move (operands); DONE;")
1986 (define_insn "*movdi_1_rex64"
1987 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y,!*Y,!*y")
1988 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm,*y,*Y"))]
1990 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1991 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1993 switch (get_attr_type (insn))
1996 if (which_alternative == 11)
1997 return "movq2dq\t{%1, %0|%0, %1}";
1999 return "movdq2q\t{%1, %0|%0, %1}";
2001 if (get_attr_mode (insn) == MODE_TI)
2002 return "movdqa\t{%1, %0|%0, %1}";
2005 /* Moves from and into integer register is done using movd opcode with
2007 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
2008 return "movd\t{%1, %0|%0, %1}";
2009 return "movq\t{%1, %0|%0, %1}";
2013 return "lea{q}\t{%a1, %0|%0, %a1}";
2015 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2017 if (get_attr_mode (insn) == MODE_SI)
2018 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2019 else if (which_alternative == 2)
2020 return "movabs{q}\t{%1, %0|%0, %1}";
2022 return "mov{q}\t{%1, %0|%0, %1}";
2026 (cond [(eq_attr "alternative" "5,6,7")
2027 (const_string "mmxmov")
2028 (eq_attr "alternative" "8,9,10")
2029 (const_string "ssemov")
2030 (eq_attr "alternative" "11,12")
2031 (const_string "ssecvt")
2032 (eq_attr "alternative" "4")
2033 (const_string "multi")
2034 (and (ne (symbol_ref "flag_pic") (const_int 0))
2035 (match_operand:DI 1 "symbolic_operand" ""))
2036 (const_string "lea")
2038 (const_string "imov")))
2039 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*")
2040 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*")
2041 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI,DI,DI")])
2043 (define_insn "*movdi_1_rex64_nointerunit"
2044 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
2045 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
2047 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2048 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2050 switch (get_attr_type (insn))
2053 if (get_attr_mode (insn) == MODE_TI)
2054 return "movdqa\t{%1, %0|%0, %1}";
2057 return "movq\t{%1, %0|%0, %1}";
2061 return "lea{q}\t{%a1, %0|%0, %a1}";
2063 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2065 if (get_attr_mode (insn) == MODE_SI)
2066 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2067 else if (which_alternative == 2)
2068 return "movabs{q}\t{%1, %0|%0, %1}";
2070 return "mov{q}\t{%1, %0|%0, %1}";
2074 (cond [(eq_attr "alternative" "5,6,7")
2075 (const_string "mmxmov")
2076 (eq_attr "alternative" "8,9,10")
2077 (const_string "ssemov")
2078 (eq_attr "alternative" "4")
2079 (const_string "multi")
2080 (and (ne (symbol_ref "flag_pic") (const_int 0))
2081 (match_operand:DI 1 "symbolic_operand" ""))
2082 (const_string "lea")
2084 (const_string "imov")))
2085 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2086 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2087 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2089 ;; Stores and loads of ax to arbitrary constant address.
2090 ;; We fake an second form of instruction to force reload to load address
2091 ;; into register when rax is not available
2092 (define_insn "*movabsdi_1_rex64"
2093 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2094 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2095 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2097 movabs{q}\t{%1, %P0|%P0, %1}
2098 mov{q}\t{%1, %a0|%a0, %1}"
2099 [(set_attr "type" "imov")
2100 (set_attr "modrm" "0,*")
2101 (set_attr "length_address" "8,0")
2102 (set_attr "length_immediate" "0,*")
2103 (set_attr "memory" "store")
2104 (set_attr "mode" "DI")])
2106 (define_insn "*movabsdi_2_rex64"
2107 [(set (match_operand:DI 0 "register_operand" "=a,r")
2108 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2109 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2111 movabs{q}\t{%P1, %0|%0, %P1}
2112 mov{q}\t{%a1, %0|%0, %a1}"
2113 [(set_attr "type" "imov")
2114 (set_attr "modrm" "0,*")
2115 (set_attr "length_address" "8,0")
2116 (set_attr "length_immediate" "0")
2117 (set_attr "memory" "load")
2118 (set_attr "mode" "DI")])
2120 ;; Convert impossible stores of immediate to existing instructions.
2121 ;; First try to get scratch register and go through it. In case this
2122 ;; fails, move by 32bit parts.
2124 [(match_scratch:DI 2 "r")
2125 (set (match_operand:DI 0 "memory_operand" "")
2126 (match_operand:DI 1 "immediate_operand" ""))]
2127 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2128 && !x86_64_immediate_operand (operands[1], DImode)"
2129 [(set (match_dup 2) (match_dup 1))
2130 (set (match_dup 0) (match_dup 2))]
2133 ;; We need to define this as both peepholer and splitter for case
2134 ;; peephole2 pass is not run.
2136 [(set (match_operand:DI 0 "memory_operand" "")
2137 (match_operand:DI 1 "immediate_operand" ""))]
2138 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2139 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2140 [(set (match_dup 2) (match_dup 3))
2141 (set (match_dup 4) (match_dup 5))]
2142 "split_di (operands, 2, operands + 2, operands + 4);")
2145 [(set (match_operand:DI 0 "memory_operand" "")
2146 (match_operand:DI 1 "immediate_operand" ""))]
2147 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2148 && !symbolic_operand (operands[1], DImode)
2149 && !x86_64_immediate_operand (operands[1], DImode)"
2150 [(set (match_dup 2) (match_dup 3))
2151 (set (match_dup 4) (match_dup 5))]
2152 "split_di (operands, 2, operands + 2, operands + 4);")
2154 (define_insn "*swapdi_rex64"
2155 [(set (match_operand:DI 0 "register_operand" "+r")
2156 (match_operand:DI 1 "register_operand" "+r"))
2161 [(set_attr "type" "imov")
2162 (set_attr "pent_pair" "np")
2163 (set_attr "athlon_decode" "vector")
2164 (set_attr "mode" "DI")
2165 (set_attr "modrm" "0")])
2168 (define_expand "movsf"
2169 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2170 (match_operand:SF 1 "general_operand" ""))]
2172 "ix86_expand_move (SFmode, operands); DONE;")
2174 (define_insn "*pushsf"
2175 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2176 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2179 switch (which_alternative)
2182 return "push{l}\t%1";
2185 /* This insn should be already split before reg-stack. */
2189 [(set_attr "type" "multi,push,multi")
2190 (set_attr "mode" "SF,SI,SF")])
2192 (define_insn "*pushsf_rex64"
2193 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2194 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2197 switch (which_alternative)
2200 return "push{q}\t%q1";
2203 /* This insn should be already split before reg-stack. */
2207 [(set_attr "type" "multi,push,multi")
2208 (set_attr "mode" "SF,DI,SF")])
2211 [(set (match_operand:SF 0 "push_operand" "")
2212 (match_operand:SF 1 "memory_operand" ""))]
2214 && GET_CODE (operands[1]) == MEM
2215 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2216 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2219 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2222 ;; %%% Kill this when call knows how to work this out.
2224 [(set (match_operand:SF 0 "push_operand" "")
2225 (match_operand:SF 1 "any_fp_register_operand" ""))]
2227 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
2228 (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])
2231 [(set (match_operand:SF 0 "push_operand" "")
2232 (match_operand:SF 1 "any_fp_register_operand" ""))]
2234 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2235 (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
2237 (define_insn "*movsf_1"
2238 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2239 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2240 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2241 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2242 && (reload_in_progress || reload_completed
2243 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2244 || GET_CODE (operands[1]) != CONST_DOUBLE
2245 || memory_operand (operands[0], SFmode))"
2247 switch (which_alternative)
2250 return output_387_reg_move (insn, operands);
2253 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2254 return "fstp%z0\t%y0";
2256 return "fst%z0\t%y0";
2259 return standard_80387_constant_opcode (operands[1]);
2263 return "mov{l}\t{%1, %0|%0, %1}";
2265 if (get_attr_mode (insn) == MODE_TI)
2266 return "pxor\t%0, %0";
2268 return "xorps\t%0, %0";
2270 if (get_attr_mode (insn) == MODE_V4SF)
2271 return "movaps\t{%1, %0|%0, %1}";
2273 return "movss\t{%1, %0|%0, %1}";
2276 return "movss\t{%1, %0|%0, %1}";
2280 return "movd\t{%1, %0|%0, %1}";
2283 return "movq\t{%1, %0|%0, %1}";
2289 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2291 (cond [(eq_attr "alternative" "3,4,9,10")
2293 (eq_attr "alternative" "5")
2295 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2297 (ne (symbol_ref "TARGET_SSE2")
2299 (eq (symbol_ref "optimize_size")
2302 (const_string "V4SF"))
2303 /* For architectures resolving dependencies on
2304 whole SSE registers use APS move to break dependency
2305 chains, otherwise use short move to avoid extra work.
2307 Do the same for architectures resolving dependencies on
2308 the parts. While in DF mode it is better to always handle
2309 just register parts, the SF mode is different due to lack
2310 of instructions to load just part of the register. It is
2311 better to maintain the whole registers in single format
2312 to avoid problems on using packed logical operations. */
2313 (eq_attr "alternative" "6")
2315 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2317 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2319 (const_string "V4SF")
2320 (const_string "SF"))
2321 (eq_attr "alternative" "11")
2322 (const_string "DI")]
2323 (const_string "SF")))])
2325 (define_insn "*movsf_1_nointerunit"
2326 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2327 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2328 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2329 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2330 && (reload_in_progress || reload_completed
2331 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2332 || GET_CODE (operands[1]) != CONST_DOUBLE
2333 || memory_operand (operands[0], SFmode))"
2335 switch (which_alternative)
2338 return output_387_reg_move (insn, operands);
2341 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2342 return "fstp%z0\t%y0";
2344 return "fst%z0\t%y0";
2347 return standard_80387_constant_opcode (operands[1]);
2351 return "mov{l}\t{%1, %0|%0, %1}";
2353 if (get_attr_mode (insn) == MODE_TI)
2354 return "pxor\t%0, %0";
2356 return "xorps\t%0, %0";
2358 if (get_attr_mode (insn) == MODE_V4SF)
2359 return "movaps\t{%1, %0|%0, %1}";
2361 return "movss\t{%1, %0|%0, %1}";
2364 return "movss\t{%1, %0|%0, %1}";
2368 return "movd\t{%1, %0|%0, %1}";
2371 return "movq\t{%1, %0|%0, %1}";
2377 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2379 (cond [(eq_attr "alternative" "3,4,9,10")
2381 (eq_attr "alternative" "5")
2383 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2385 (ne (symbol_ref "TARGET_SSE2")
2387 (eq (symbol_ref "optimize_size")
2390 (const_string "V4SF"))
2391 /* For architectures resolving dependencies on
2392 whole SSE registers use APS move to break dependency
2393 chains, otherwise use short move to avoid extra work.
2395 Do the same for architectures resolving dependencies on
2396 the parts. While in DF mode it is better to always handle
2397 just register parts, the SF mode is different due to lack
2398 of instructions to load just part of the register. It is
2399 better to maintain the whole registers in single format
2400 to avoid problems on using packed logical operations. */
2401 (eq_attr "alternative" "6")
2403 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2405 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2407 (const_string "V4SF")
2408 (const_string "SF"))
2409 (eq_attr "alternative" "11")
2410 (const_string "DI")]
2411 (const_string "SF")))])
2413 (define_insn "*swapsf"
2414 [(set (match_operand:SF 0 "register_operand" "+f")
2415 (match_operand:SF 1 "register_operand" "+f"))
2418 "reload_completed || !TARGET_SSE"
2420 if (STACK_TOP_P (operands[0]))
2425 [(set_attr "type" "fxch")
2426 (set_attr "mode" "SF")])
2428 (define_expand "movdf"
2429 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2430 (match_operand:DF 1 "general_operand" ""))]
2432 "ix86_expand_move (DFmode, operands); DONE;")
2434 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2435 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2436 ;; On the average, pushdf using integers can be still shorter. Allow this
2437 ;; pattern for optimize_size too.
2439 (define_insn "*pushdf_nointeger"
2440 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2441 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2442 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2444 /* This insn should be already split before reg-stack. */
2447 [(set_attr "type" "multi")
2448 (set_attr "mode" "DF,SI,SI,DF")])
2450 (define_insn "*pushdf_integer"
2451 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2452 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2453 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2455 /* This insn should be already split before reg-stack. */
2458 [(set_attr "type" "multi")
2459 (set_attr "mode" "DF,SI,DF")])
2461 ;; %%% Kill this when call knows how to work this out.
2463 [(set (match_operand:DF 0 "push_operand" "")
2464 (match_operand:DF 1 "any_fp_register_operand" ""))]
2465 "!TARGET_64BIT && reload_completed"
2466 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
2467 (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
2471 [(set (match_operand:DF 0 "push_operand" "")
2472 (match_operand:DF 1 "any_fp_register_operand" ""))]
2473 "TARGET_64BIT && reload_completed"
2474 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2475 (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
2479 [(set (match_operand:DF 0 "push_operand" "")
2480 (match_operand:DF 1 "general_operand" ""))]
2483 "ix86_split_long_move (operands); DONE;")
2485 ;; Moving is usually shorter when only FP registers are used. This separate
2486 ;; movdf pattern avoids the use of integer registers for FP operations
2487 ;; when optimizing for size.
2489 (define_insn "*movdf_nointeger"
2490 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2491 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2492 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2493 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2494 && (reload_in_progress || reload_completed
2495 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2496 || GET_CODE (operands[1]) != CONST_DOUBLE
2497 || memory_operand (operands[0], DFmode))"
2499 switch (which_alternative)
2502 return output_387_reg_move (insn, operands);
2505 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2506 return "fstp%z0\t%y0";
2508 return "fst%z0\t%y0";
2511 return standard_80387_constant_opcode (operands[1]);
2517 switch (get_attr_mode (insn))
2520 return "xorps\t%0, %0";
2522 return "xorpd\t%0, %0";
2524 return "pxor\t%0, %0";
2529 switch (get_attr_mode (insn))
2532 return "movaps\t{%1, %0|%0, %1}";
2534 return "movapd\t{%1, %0|%0, %1}";
2536 return "movsd\t{%1, %0|%0, %1}";
2541 if (get_attr_mode (insn) == MODE_V2DF)
2542 return "movlpd\t{%1, %0|%0, %1}";
2544 return "movsd\t{%1, %0|%0, %1}";
2546 return "movsd\t{%1, %0|%0, %1}";
2552 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2554 (cond [(eq_attr "alternative" "3,4")
2556 /* xorps is one byte shorter. */
2557 (eq_attr "alternative" "5")
2558 (cond [(ne (symbol_ref "optimize_size")
2560 (const_string "V4SF")
2561 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2563 (const_string "TI")]
2564 (const_string "V2DF"))
2565 /* For architectures resolving dependencies on
2566 whole SSE registers use APD move to break dependency
2567 chains, otherwise use short move to avoid extra work.
2569 movaps encodes one byte shorter. */
2570 (eq_attr "alternative" "6")
2572 [(ne (symbol_ref "optimize_size")
2574 (const_string "V4SF")
2575 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2577 (const_string "V2DF")]
2578 (const_string "DF"))
2579 /* For architectures resolving dependencies on register
2580 parts we may avoid extra work to zero out upper part
2582 (eq_attr "alternative" "7")
2584 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2586 (const_string "V2DF")
2587 (const_string "DF"))]
2588 (const_string "DF")))])
2590 (define_insn "*movdf_integer"
2591 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2592 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2593 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2594 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2595 && (reload_in_progress || reload_completed
2596 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2597 || GET_CODE (operands[1]) != CONST_DOUBLE
2598 || memory_operand (operands[0], DFmode))"
2600 switch (which_alternative)
2603 return output_387_reg_move (insn, operands);
2606 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2607 return "fstp%z0\t%y0";
2609 return "fst%z0\t%y0";
2612 return standard_80387_constant_opcode (operands[1]);
2619 switch (get_attr_mode (insn))
2622 return "xorps\t%0, %0";
2624 return "xorpd\t%0, %0";
2626 return "pxor\t%0, %0";
2631 switch (get_attr_mode (insn))
2634 return "movaps\t{%1, %0|%0, %1}";
2636 return "movapd\t{%1, %0|%0, %1}";
2638 return "movsd\t{%1, %0|%0, %1}";
2643 if (get_attr_mode (insn) == MODE_V2DF)
2644 return "movlpd\t{%1, %0|%0, %1}";
2646 return "movsd\t{%1, %0|%0, %1}";
2648 return "movsd\t{%1, %0|%0, %1}";
2654 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2656 (cond [(eq_attr "alternative" "3,4")
2658 /* xorps is one byte shorter. */
2659 (eq_attr "alternative" "5")
2660 (cond [(ne (symbol_ref "optimize_size")
2662 (const_string "V4SF")
2663 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2665 (const_string "TI")]
2666 (const_string "V2DF"))
2667 /* For architectures resolving dependencies on
2668 whole SSE registers use APD move to break dependency
2669 chains, otherwise use short move to avoid extra work.
2671 movaps encodes one byte shorter. */
2672 (eq_attr "alternative" "6")
2674 [(ne (symbol_ref "optimize_size")
2676 (const_string "V4SF")
2677 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2679 (const_string "V2DF")]
2680 (const_string "DF"))
2681 /* For architectures resolving dependencies on register
2682 parts we may avoid extra work to zero out upper part
2684 (eq_attr "alternative" "7")
2686 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2688 (const_string "V2DF")
2689 (const_string "DF"))]
2690 (const_string "DF")))])
2693 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2694 (match_operand:DF 1 "general_operand" ""))]
2696 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2697 && ! (ANY_FP_REG_P (operands[0]) ||
2698 (GET_CODE (operands[0]) == SUBREG
2699 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2700 && ! (ANY_FP_REG_P (operands[1]) ||
2701 (GET_CODE (operands[1]) == SUBREG
2702 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2704 "ix86_split_long_move (operands); DONE;")
2706 (define_insn "*swapdf"
2707 [(set (match_operand:DF 0 "register_operand" "+f")
2708 (match_operand:DF 1 "register_operand" "+f"))
2711 "reload_completed || !TARGET_SSE2"
2713 if (STACK_TOP_P (operands[0]))
2718 [(set_attr "type" "fxch")
2719 (set_attr "mode" "DF")])
2721 (define_expand "movxf"
2722 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2723 (match_operand:XF 1 "general_operand" ""))]
2725 "ix86_expand_move (XFmode, operands); DONE;")
2727 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2728 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2729 ;; Pushing using integer instructions is longer except for constants
2730 ;; and direct memory references.
2731 ;; (assuming that any given constant is pushed only once, but this ought to be
2732 ;; handled elsewhere).
2734 (define_insn "*pushxf_nointeger"
2735 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2736 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2739 /* This insn should be already split before reg-stack. */
2742 [(set_attr "type" "multi")
2743 (set_attr "mode" "XF,SI,SI")])
2745 (define_insn "*pushxf_integer"
2746 [(set (match_operand:XF 0 "push_operand" "=<,<")
2747 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2750 /* This insn should be already split before reg-stack. */
2753 [(set_attr "type" "multi")
2754 (set_attr "mode" "XF,SI")])
2757 [(set (match_operand 0 "push_operand" "")
2758 (match_operand 1 "general_operand" ""))]
2760 && (GET_MODE (operands[0]) == XFmode
2761 || GET_MODE (operands[0]) == DFmode)
2762 && !ANY_FP_REG_P (operands[1])"
2764 "ix86_split_long_move (operands); DONE;")
2767 [(set (match_operand:XF 0 "push_operand" "")
2768 (match_operand:XF 1 "any_fp_register_operand" ""))]
2770 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
2771 (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
2772 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2775 [(set (match_operand:XF 0 "push_operand" "")
2776 (match_operand:XF 1 "any_fp_register_operand" ""))]
2778 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
2779 (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
2780 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2782 ;; Do not use integer registers when optimizing for size
2783 (define_insn "*movxf_nointeger"
2784 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2785 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2787 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2788 && (reload_in_progress || reload_completed
2789 || GET_CODE (operands[1]) != CONST_DOUBLE
2790 || memory_operand (operands[0], XFmode))"
2792 switch (which_alternative)
2795 return output_387_reg_move (insn, operands);
2798 /* There is no non-popping store to memory for XFmode. So if
2799 we need one, follow the store with a load. */
2800 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2801 return "fstp%z0\t%y0\;fld%z0\t%y0";
2803 return "fstp%z0\t%y0";
2806 return standard_80387_constant_opcode (operands[1]);
2813 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2814 (set_attr "mode" "XF,XF,XF,SI,SI")])
2816 (define_insn "*movxf_integer"
2817 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2818 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2820 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2821 && (reload_in_progress || reload_completed
2822 || GET_CODE (operands[1]) != CONST_DOUBLE
2823 || memory_operand (operands[0], XFmode))"
2825 switch (which_alternative)
2828 return output_387_reg_move (insn, operands);
2831 /* There is no non-popping store to memory for XFmode. So if
2832 we need one, follow the store with a load. */
2833 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2834 return "fstp%z0\t%y0\;fld%z0\t%y0";
2836 return "fstp%z0\t%y0";
2839 return standard_80387_constant_opcode (operands[1]);
2846 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2847 (set_attr "mode" "XF,XF,XF,SI,SI")])
2850 [(set (match_operand 0 "nonimmediate_operand" "")
2851 (match_operand 1 "general_operand" ""))]
2853 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2854 && GET_MODE (operands[0]) == XFmode
2855 && ! (ANY_FP_REG_P (operands[0]) ||
2856 (GET_CODE (operands[0]) == SUBREG
2857 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2858 && ! (ANY_FP_REG_P (operands[1]) ||
2859 (GET_CODE (operands[1]) == SUBREG
2860 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2862 "ix86_split_long_move (operands); DONE;")
2865 [(set (match_operand 0 "register_operand" "")
2866 (match_operand 1 "memory_operand" ""))]
2868 && GET_CODE (operands[1]) == MEM
2869 && (GET_MODE (operands[0]) == XFmode
2870 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2871 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2872 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2873 [(set (match_dup 0) (match_dup 1))]
2875 rtx c = get_pool_constant (XEXP (operands[1], 0));
2876 rtx r = operands[0];
2878 if (GET_CODE (r) == SUBREG)
2883 if (!standard_sse_constant_p (c))
2886 else if (FP_REG_P (r))
2888 if (!standard_80387_constant_p (c))
2891 else if (MMX_REG_P (r))
2897 (define_insn "swapxf"
2898 [(set (match_operand:XF 0 "register_operand" "+f")
2899 (match_operand:XF 1 "register_operand" "+f"))
2904 if (STACK_TOP_P (operands[0]))
2909 [(set_attr "type" "fxch")
2910 (set_attr "mode" "XF")])
2912 ;; Zero extension instructions
2914 (define_expand "zero_extendhisi2"
2915 [(set (match_operand:SI 0 "register_operand" "")
2916 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2919 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2921 operands[1] = force_reg (HImode, operands[1]);
2922 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2927 (define_insn "zero_extendhisi2_and"
2928 [(set (match_operand:SI 0 "register_operand" "=r")
2929 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2930 (clobber (reg:CC FLAGS_REG))]
2931 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2933 [(set_attr "type" "alu1")
2934 (set_attr "mode" "SI")])
2937 [(set (match_operand:SI 0 "register_operand" "")
2938 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2939 (clobber (reg:CC FLAGS_REG))]
2940 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2941 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2942 (clobber (reg:CC FLAGS_REG))])]
2945 (define_insn "*zero_extendhisi2_movzwl"
2946 [(set (match_operand:SI 0 "register_operand" "=r")
2947 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2948 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2949 "movz{wl|x}\t{%1, %0|%0, %1}"
2950 [(set_attr "type" "imovx")
2951 (set_attr "mode" "SI")])
2953 (define_expand "zero_extendqihi2"
2955 [(set (match_operand:HI 0 "register_operand" "")
2956 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2957 (clobber (reg:CC FLAGS_REG))])]
2961 (define_insn "*zero_extendqihi2_and"
2962 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2963 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2964 (clobber (reg:CC FLAGS_REG))]
2965 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2967 [(set_attr "type" "alu1")
2968 (set_attr "mode" "HI")])
2970 (define_insn "*zero_extendqihi2_movzbw_and"
2971 [(set (match_operand:HI 0 "register_operand" "=r,r")
2972 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2973 (clobber (reg:CC FLAGS_REG))]
2974 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2976 [(set_attr "type" "imovx,alu1")
2977 (set_attr "mode" "HI")])
2979 (define_insn "*zero_extendqihi2_movzbw"
2980 [(set (match_operand:HI 0 "register_operand" "=r")
2981 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2982 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2983 "movz{bw|x}\t{%1, %0|%0, %1}"
2984 [(set_attr "type" "imovx")
2985 (set_attr "mode" "HI")])
2987 ;; For the movzbw case strip only the clobber
2989 [(set (match_operand:HI 0 "register_operand" "")
2990 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2991 (clobber (reg:CC FLAGS_REG))]
2993 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2994 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
2995 [(set (match_operand:HI 0 "register_operand" "")
2996 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
2998 ;; When source and destination does not overlap, clear destination
2999 ;; first and then do the movb
3001 [(set (match_operand:HI 0 "register_operand" "")
3002 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3003 (clobber (reg:CC FLAGS_REG))]
3005 && ANY_QI_REG_P (operands[0])
3006 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3007 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3008 [(set (match_dup 0) (const_int 0))
3009 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3010 "operands[2] = gen_lowpart (QImode, operands[0]);")
3012 ;; Rest is handled by single and.
3014 [(set (match_operand:HI 0 "register_operand" "")
3015 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3016 (clobber (reg:CC FLAGS_REG))]
3018 && true_regnum (operands[0]) == true_regnum (operands[1])"
3019 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3020 (clobber (reg:CC FLAGS_REG))])]
3023 (define_expand "zero_extendqisi2"
3025 [(set (match_operand:SI 0 "register_operand" "")
3026 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3027 (clobber (reg:CC FLAGS_REG))])]
3031 (define_insn "*zero_extendqisi2_and"
3032 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3033 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3034 (clobber (reg:CC FLAGS_REG))]
3035 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3037 [(set_attr "type" "alu1")
3038 (set_attr "mode" "SI")])
3040 (define_insn "*zero_extendqisi2_movzbw_and"
3041 [(set (match_operand:SI 0 "register_operand" "=r,r")
3042 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3043 (clobber (reg:CC FLAGS_REG))]
3044 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3046 [(set_attr "type" "imovx,alu1")
3047 (set_attr "mode" "SI")])
3049 (define_insn "*zero_extendqisi2_movzbw"
3050 [(set (match_operand:SI 0 "register_operand" "=r")
3051 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3052 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3053 "movz{bl|x}\t{%1, %0|%0, %1}"
3054 [(set_attr "type" "imovx")
3055 (set_attr "mode" "SI")])
3057 ;; For the movzbl case strip only the clobber
3059 [(set (match_operand:SI 0 "register_operand" "")
3060 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3061 (clobber (reg:CC FLAGS_REG))]
3063 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3064 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3066 (zero_extend:SI (match_dup 1)))])
3068 ;; When source and destination does not overlap, clear destination
3069 ;; first and then do the movb
3071 [(set (match_operand:SI 0 "register_operand" "")
3072 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3073 (clobber (reg:CC FLAGS_REG))]
3075 && ANY_QI_REG_P (operands[0])
3076 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3077 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3078 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3079 [(set (match_dup 0) (const_int 0))
3080 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3081 "operands[2] = gen_lowpart (QImode, operands[0]);")
3083 ;; Rest is handled by single and.
3085 [(set (match_operand:SI 0 "register_operand" "")
3086 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3087 (clobber (reg:CC FLAGS_REG))]
3089 && true_regnum (operands[0]) == true_regnum (operands[1])"
3090 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3091 (clobber (reg:CC FLAGS_REG))])]
3094 ;; %%% Kill me once multi-word ops are sane.
3095 (define_expand "zero_extendsidi2"
3096 [(set (match_operand:DI 0 "register_operand" "=r")
3097 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3101 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3106 (define_insn "zero_extendsidi2_32"
3107 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3108 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
3109 (clobber (reg:CC FLAGS_REG))]
3110 "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3115 movd\t{%1, %0|%0, %1}
3116 movd\t{%1, %0|%0, %1}"
3117 [(set_attr "mode" "SI,SI,SI,DI,TI")
3118 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3120 (define_insn "*zero_extendsidi2_32_1"
3121 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3122 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
3123 (clobber (reg:CC FLAGS_REG))]
3124 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3129 movd\t{%1, %0|%0, %1}
3130 movd\t{%1, %0|%0, %1}"
3131 [(set_attr "mode" "SI,SI,SI,DI,TI")
3132 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3134 (define_insn "zero_extendsidi2_rex64"
3135 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
3136 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
3137 "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3139 mov\t{%k1, %k0|%k0, %k1}
3141 movd\t{%1, %0|%0, %1}
3142 movd\t{%1, %0|%0, %1}"
3143 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3144 (set_attr "mode" "SI,DI,DI,TI")])
3146 (define_insn "*zero_extendsidi2_rex64_1"
3147 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
3148 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
3149 "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3151 mov\t{%k1, %k0|%k0, %k1}
3153 movd\t{%1, %0|%0, %1}
3154 movd\t{%1, %0|%0, %1}"
3155 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3156 (set_attr "mode" "SI,DI,SI,SI")])
3159 [(set (match_operand:DI 0 "memory_operand" "")
3160 (zero_extend:DI (match_dup 0)))]
3162 [(set (match_dup 4) (const_int 0))]
3163 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3166 [(set (match_operand:DI 0 "register_operand" "")
3167 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3168 (clobber (reg:CC FLAGS_REG))]
3169 "!TARGET_64BIT && reload_completed
3170 && true_regnum (operands[0]) == true_regnum (operands[1])"
3171 [(set (match_dup 4) (const_int 0))]
3172 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3175 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3176 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3177 (clobber (reg:CC FLAGS_REG))]
3178 "!TARGET_64BIT && reload_completed
3179 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3180 [(set (match_dup 3) (match_dup 1))
3181 (set (match_dup 4) (const_int 0))]
3182 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3184 (define_insn "zero_extendhidi2"
3185 [(set (match_operand:DI 0 "register_operand" "=r,r")
3186 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3189 movz{wl|x}\t{%1, %k0|%k0, %1}
3190 movz{wq|x}\t{%1, %0|%0, %1}"
3191 [(set_attr "type" "imovx")
3192 (set_attr "mode" "SI,DI")])
3194 (define_insn "zero_extendqidi2"
3195 [(set (match_operand:DI 0 "register_operand" "=r,r")
3196 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3199 movz{bl|x}\t{%1, %k0|%k0, %1}
3200 movz{bq|x}\t{%1, %0|%0, %1}"
3201 [(set_attr "type" "imovx")
3202 (set_attr "mode" "SI,DI")])
3204 ;; Sign extension instructions
3206 (define_expand "extendsidi2"
3207 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3208 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3209 (clobber (reg:CC FLAGS_REG))
3210 (clobber (match_scratch:SI 2 ""))])]
3215 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3220 (define_insn "*extendsidi2_1"
3221 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3222 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3223 (clobber (reg:CC FLAGS_REG))
3224 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3228 (define_insn "extendsidi2_rex64"
3229 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3230 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3234 movs{lq|x}\t{%1,%0|%0, %1}"
3235 [(set_attr "type" "imovx")
3236 (set_attr "mode" "DI")
3237 (set_attr "prefix_0f" "0")
3238 (set_attr "modrm" "0,1")])
3240 (define_insn "extendhidi2"
3241 [(set (match_operand:DI 0 "register_operand" "=r")
3242 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3244 "movs{wq|x}\t{%1,%0|%0, %1}"
3245 [(set_attr "type" "imovx")
3246 (set_attr "mode" "DI")])
3248 (define_insn "extendqidi2"
3249 [(set (match_operand:DI 0 "register_operand" "=r")
3250 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3252 "movs{bq|x}\t{%1,%0|%0, %1}"
3253 [(set_attr "type" "imovx")
3254 (set_attr "mode" "DI")])
3256 ;; Extend to memory case when source register does die.
3258 [(set (match_operand:DI 0 "memory_operand" "")
3259 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3260 (clobber (reg:CC FLAGS_REG))
3261 (clobber (match_operand:SI 2 "register_operand" ""))]
3263 && dead_or_set_p (insn, operands[1])
3264 && !reg_mentioned_p (operands[1], operands[0]))"
3265 [(set (match_dup 3) (match_dup 1))
3266 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3267 (clobber (reg:CC FLAGS_REG))])
3268 (set (match_dup 4) (match_dup 1))]
3269 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3271 ;; Extend to memory case when source register does not die.
3273 [(set (match_operand:DI 0 "memory_operand" "")
3274 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3275 (clobber (reg:CC FLAGS_REG))
3276 (clobber (match_operand:SI 2 "register_operand" ""))]
3280 split_di (&operands[0], 1, &operands[3], &operands[4]);
3282 emit_move_insn (operands[3], operands[1]);
3284 /* Generate a cltd if possible and doing so it profitable. */
3285 if (true_regnum (operands[1]) == 0
3286 && true_regnum (operands[2]) == 1
3287 && (optimize_size || TARGET_USE_CLTD))
3289 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3293 emit_move_insn (operands[2], operands[1]);
3294 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3296 emit_move_insn (operands[4], operands[2]);
3300 ;; Extend to register case. Optimize case where source and destination
3301 ;; registers match and cases where we can use cltd.
3303 [(set (match_operand:DI 0 "register_operand" "")
3304 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3305 (clobber (reg:CC FLAGS_REG))
3306 (clobber (match_scratch:SI 2 ""))]
3310 split_di (&operands[0], 1, &operands[3], &operands[4]);
3312 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3313 emit_move_insn (operands[3], operands[1]);
3315 /* Generate a cltd if possible and doing so it profitable. */
3316 if (true_regnum (operands[3]) == 0
3317 && (optimize_size || TARGET_USE_CLTD))
3319 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3323 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3324 emit_move_insn (operands[4], operands[1]);
3326 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3330 (define_insn "extendhisi2"
3331 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3332 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3335 switch (get_attr_prefix_0f (insn))
3338 return "{cwtl|cwde}";
3340 return "movs{wl|x}\t{%1,%0|%0, %1}";
3343 [(set_attr "type" "imovx")
3344 (set_attr "mode" "SI")
3345 (set (attr "prefix_0f")
3346 ;; movsx is short decodable while cwtl is vector decoded.
3347 (if_then_else (and (eq_attr "cpu" "!k6")
3348 (eq_attr "alternative" "0"))
3350 (const_string "1")))
3352 (if_then_else (eq_attr "prefix_0f" "0")
3354 (const_string "1")))])
3356 (define_insn "*extendhisi2_zext"
3357 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3359 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3362 switch (get_attr_prefix_0f (insn))
3365 return "{cwtl|cwde}";
3367 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3370 [(set_attr "type" "imovx")
3371 (set_attr "mode" "SI")
3372 (set (attr "prefix_0f")
3373 ;; movsx is short decodable while cwtl is vector decoded.
3374 (if_then_else (and (eq_attr "cpu" "!k6")
3375 (eq_attr "alternative" "0"))
3377 (const_string "1")))
3379 (if_then_else (eq_attr "prefix_0f" "0")
3381 (const_string "1")))])
3383 (define_insn "extendqihi2"
3384 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3385 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3388 switch (get_attr_prefix_0f (insn))
3391 return "{cbtw|cbw}";
3393 return "movs{bw|x}\t{%1,%0|%0, %1}";
3396 [(set_attr "type" "imovx")
3397 (set_attr "mode" "HI")
3398 (set (attr "prefix_0f")
3399 ;; movsx is short decodable while cwtl is vector decoded.
3400 (if_then_else (and (eq_attr "cpu" "!k6")
3401 (eq_attr "alternative" "0"))
3403 (const_string "1")))
3405 (if_then_else (eq_attr "prefix_0f" "0")
3407 (const_string "1")))])
3409 (define_insn "extendqisi2"
3410 [(set (match_operand:SI 0 "register_operand" "=r")
3411 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3413 "movs{bl|x}\t{%1,%0|%0, %1}"
3414 [(set_attr "type" "imovx")
3415 (set_attr "mode" "SI")])
3417 (define_insn "*extendqisi2_zext"
3418 [(set (match_operand:DI 0 "register_operand" "=r")
3420 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3422 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3423 [(set_attr "type" "imovx")
3424 (set_attr "mode" "SI")])
3426 ;; Conversions between float and double.
3428 ;; These are all no-ops in the model used for the 80387. So just
3431 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3432 (define_insn "*dummy_extendsfdf2"
3433 [(set (match_operand:DF 0 "push_operand" "=<")
3434 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3439 [(set (match_operand:DF 0 "push_operand" "")
3440 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3442 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
3443 (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
3446 [(set (match_operand:DF 0 "push_operand" "")
3447 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3449 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
3450 (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
3452 (define_insn "*dummy_extendsfxf2"
3453 [(set (match_operand:XF 0 "push_operand" "=<")
3454 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3459 [(set (match_operand:XF 0 "push_operand" "")
3460 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3462 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3463 (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3464 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3467 [(set (match_operand:XF 0 "push_operand" "")
3468 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3470 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3471 (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3472 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3475 [(set (match_operand:XF 0 "push_operand" "")
3476 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3478 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3479 (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3480 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3483 [(set (match_operand:XF 0 "push_operand" "")
3484 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3486 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3487 (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3488 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3490 (define_expand "extendsfdf2"
3491 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3492 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3493 "TARGET_80387 || TARGET_SSE2"
3495 /* ??? Needed for compress_float_constant since all fp constants
3496 are LEGITIMATE_CONSTANT_P. */
3497 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3498 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3499 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3500 operands[1] = force_reg (SFmode, operands[1]);
3503 (define_insn "*extendsfdf2_1"
3504 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3505 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3506 "(TARGET_80387 || TARGET_SSE2)
3507 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3509 switch (which_alternative)
3512 return output_387_reg_move (insn, operands);
3515 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3516 return "fstp%z0\t%y0";
3518 return "fst%z0\t%y0";
3521 return "cvtss2sd\t{%1, %0|%0, %1}";
3527 [(set_attr "type" "fmov,fmov,ssecvt")
3528 (set_attr "mode" "SF,XF,DF")])
3530 (define_insn "*extendsfdf2_1_sse_only"
3531 [(set (match_operand:DF 0 "register_operand" "=Y")
3532 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3533 "!TARGET_80387 && TARGET_SSE2
3534 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3535 "cvtss2sd\t{%1, %0|%0, %1}"
3536 [(set_attr "type" "ssecvt")
3537 (set_attr "mode" "DF")])
3539 (define_expand "extendsfxf2"
3540 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3541 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3544 /* ??? Needed for compress_float_constant since all fp constants
3545 are LEGITIMATE_CONSTANT_P. */
3546 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3547 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3548 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3549 operands[1] = force_reg (SFmode, operands[1]);
3552 (define_insn "*extendsfxf2_1"
3553 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3554 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3556 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3558 switch (which_alternative)
3561 return output_387_reg_move (insn, operands);
3564 /* There is no non-popping store to memory for XFmode. So if
3565 we need one, follow the store with a load. */
3566 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3567 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3569 return "fstp%z0\t%y0";
3575 [(set_attr "type" "fmov")
3576 (set_attr "mode" "SF,XF")])
3578 (define_expand "extenddfxf2"
3579 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3580 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3583 /* ??? Needed for compress_float_constant since all fp constants
3584 are LEGITIMATE_CONSTANT_P. */
3585 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3586 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3587 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3588 operands[1] = force_reg (DFmode, operands[1]);
3591 (define_insn "*extenddfxf2_1"
3592 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3593 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3595 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3597 switch (which_alternative)
3600 return output_387_reg_move (insn, operands);
3603 /* There is no non-popping store to memory for XFmode. So if
3604 we need one, follow the store with a load. */
3605 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3606 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3608 return "fstp%z0\t%y0";
3614 [(set_attr "type" "fmov")
3615 (set_attr "mode" "DF,XF")])
3617 ;; %%% This seems bad bad news.
3618 ;; This cannot output into an f-reg because there is no way to be sure
3619 ;; of truncating in that case. Otherwise this is just like a simple move
3620 ;; insn. So we pretend we can output to a reg in order to get better
3621 ;; register preferencing, but we really use a stack slot.
3623 (define_expand "truncdfsf2"
3624 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3626 (match_operand:DF 1 "register_operand" "")))
3627 (clobber (match_dup 2))])]
3628 "TARGET_80387 || TARGET_SSE2"
3632 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3635 else if (flag_unsafe_math_optimizations)
3637 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3638 emit_insn (gen_truncdfsf2_noop (reg, operands[1]));
3639 if (reg != operands[0])
3640 emit_move_insn (operands[0], reg);
3644 operands[2] = assign_386_stack_local (SFmode, 0);
3647 (define_insn "truncdfsf2_noop"
3648 [(set (match_operand:SF 0 "register_operand" "=f")
3649 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3650 "TARGET_80387 && flag_unsafe_math_optimizations"
3652 return output_387_reg_move (insn, operands);
3654 [(set_attr "type" "fmov")
3655 (set_attr "mode" "SF")])
3657 (define_insn "*truncdfsf2_1"
3658 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3660 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3661 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3662 "TARGET_80387 && !TARGET_SSE2"
3664 switch (which_alternative)
3667 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3668 return "fstp%z0\t%y0";
3670 return "fst%z0\t%y0";
3675 [(set_attr "type" "fmov,multi,multi,multi")
3676 (set_attr "mode" "SF,SF,SF,SF")])
3678 (define_insn "*truncdfsf2_1_sse"
3679 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3681 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3682 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3683 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3685 switch (which_alternative)
3688 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3689 return "fstp%z0\t%y0";
3691 return "fst%z0\t%y0";
3698 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3699 (set_attr "mode" "SF,SF,SF,SF,DF")])
3701 (define_insn "*truncdfsf2_1_sse_nooverlap"
3702 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3704 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3705 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3706 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3708 switch (which_alternative)
3711 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3712 return "fstp%z0\t%y0";
3714 return "fst%z0\t%y0";
3721 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3722 (set_attr "mode" "SF,SF,SF,SF,DF")])
3724 (define_insn "*truncdfsf2_2"
3725 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3727 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3728 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3729 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3731 switch (which_alternative)
3735 return "cvtsd2ss\t{%1, %0|%0, %1}";
3737 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3738 return "fstp%z0\t%y0";
3740 return "fst%z0\t%y0";
3745 [(set_attr "type" "ssecvt,ssecvt,fmov")
3746 (set_attr "athlon_decode" "vector,double,*")
3747 (set_attr "mode" "SF,SF,SF")])
3749 (define_insn "*truncdfsf2_2_nooverlap"
3750 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
3752 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3753 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3754 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3756 switch (which_alternative)
3761 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3762 return "fstp%z0\t%y0";
3764 return "fst%z0\t%y0";
3769 [(set_attr "type" "ssecvt,fmov")
3770 (set_attr "mode" "DF,SF")])
3772 (define_insn "*truncdfsf2_3"
3773 [(set (match_operand:SF 0 "memory_operand" "=m")
3775 (match_operand:DF 1 "register_operand" "f")))]
3778 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3779 return "fstp%z0\t%y0";
3781 return "fst%z0\t%y0";
3783 [(set_attr "type" "fmov")
3784 (set_attr "mode" "SF")])
3786 (define_insn "truncdfsf2_sse_only"
3787 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
3789 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
3790 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3791 "cvtsd2ss\t{%1, %0|%0, %1}"
3792 [(set_attr "type" "ssecvt")
3793 (set_attr "athlon_decode" "vector,double")
3794 (set_attr "mode" "SF")])
3796 (define_insn "*truncdfsf2_sse_only_nooverlap"
3797 [(set (match_operand:SF 0 "register_operand" "=&Y")
3799 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3800 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3802 [(set_attr "type" "ssecvt")
3803 (set_attr "mode" "DF")])
3806 [(set (match_operand:SF 0 "memory_operand" "")
3808 (match_operand:DF 1 "register_operand" "")))
3809 (clobber (match_operand:SF 2 "memory_operand" ""))]
3811 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3814 ; Avoid possible reformatting penalty on the destination by first
3817 [(set (match_operand:SF 0 "register_operand" "")
3819 (match_operand:DF 1 "nonimmediate_operand" "")))
3820 (clobber (match_operand 2 "" ""))]
3821 "TARGET_80387 && reload_completed
3822 && SSE_REG_P (operands[0])
3823 && !STACK_REG_P (operands[1])"
3827 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
3828 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3831 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3832 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3833 /* simplify_gen_subreg refuses to widen memory references. */
3834 if (GET_CODE (src) == SUBREG)
3835 alter_subreg (&src);
3836 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3838 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3839 emit_insn (gen_cvtsd2ss (dest, dest, src));
3845 [(set (match_operand:SF 0 "register_operand" "")
3847 (match_operand:DF 1 "nonimmediate_operand" "")))]
3848 "TARGET_80387 && reload_completed
3849 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3853 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3854 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3855 /* simplify_gen_subreg refuses to widen memory references. */
3856 if (GET_CODE (src) == SUBREG)
3857 alter_subreg (&src);
3858 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3860 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3861 emit_insn (gen_cvtsd2ss (dest, dest, src));
3866 [(set (match_operand:SF 0 "register_operand" "")
3868 (match_operand:DF 1 "fp_register_operand" "")))
3869 (clobber (match_operand:SF 2 "memory_operand" ""))]
3870 "TARGET_80387 && reload_completed"
3871 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3872 (set (match_dup 0) (match_dup 2))]
3875 (define_expand "truncxfsf2"
3876 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3878 (match_operand:XF 1 "register_operand" "")))
3879 (clobber (match_dup 2))])]
3882 if (flag_unsafe_math_optimizations)
3884 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3885 emit_insn (gen_truncxfsf2_noop (reg, operands[1]));
3886 if (reg != operands[0])
3887 emit_move_insn (operands[0], reg);
3891 operands[2] = assign_386_stack_local (SFmode, 0);
3894 (define_insn "truncxfsf2_noop"
3895 [(set (match_operand:SF 0 "register_operand" "=f")
3896 (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
3897 "TARGET_80387 && flag_unsafe_math_optimizations"
3899 return output_387_reg_move (insn, operands);
3901 [(set_attr "type" "fmov")
3902 (set_attr "mode" "SF")])
3904 (define_insn "*truncxfsf2_1"
3905 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3907 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3908 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3911 switch (which_alternative)
3914 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3915 return "fstp%z0\t%y0";
3917 return "fst%z0\t%y0";
3922 [(set_attr "type" "fmov,multi,multi,multi")
3923 (set_attr "mode" "SF")])
3925 (define_insn "*truncxfsf2_2"
3926 [(set (match_operand:SF 0 "memory_operand" "=m")
3928 (match_operand:XF 1 "register_operand" "f")))]
3931 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3932 return "fstp%z0\t%y0";
3934 return "fst%z0\t%y0";
3936 [(set_attr "type" "fmov")
3937 (set_attr "mode" "SF")])
3940 [(set (match_operand:SF 0 "memory_operand" "")
3942 (match_operand:XF 1 "register_operand" "")))
3943 (clobber (match_operand:SF 2 "memory_operand" ""))]
3945 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3949 [(set (match_operand:SF 0 "register_operand" "")
3951 (match_operand:XF 1 "register_operand" "")))
3952 (clobber (match_operand:SF 2 "memory_operand" ""))]
3953 "TARGET_80387 && reload_completed"
3954 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3955 (set (match_dup 0) (match_dup 2))]
3958 (define_expand "truncxfdf2"
3959 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3961 (match_operand:XF 1 "register_operand" "")))
3962 (clobber (match_dup 2))])]
3965 if (flag_unsafe_math_optimizations)
3967 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DFmode);
3968 emit_insn (gen_truncxfdf2_noop (reg, operands[1]));
3969 if (reg != operands[0])
3970 emit_move_insn (operands[0], reg);
3974 operands[2] = assign_386_stack_local (DFmode, 0);
3977 (define_insn "truncxfdf2_noop"
3978 [(set (match_operand:DF 0 "register_operand" "=f")
3979 (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
3980 "TARGET_80387 && flag_unsafe_math_optimizations"
3982 return output_387_reg_move (insn, operands);
3984 [(set_attr "type" "fmov")
3985 (set_attr "mode" "DF")])
3987 (define_insn "*truncxfdf2_1"
3988 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3990 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3991 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3994 switch (which_alternative)
3997 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3998 return "fstp%z0\t%y0";
4000 return "fst%z0\t%y0";
4006 [(set_attr "type" "fmov,multi,multi,multi")
4007 (set_attr "mode" "DF")])
4009 (define_insn "*truncxfdf2_2"
4010 [(set (match_operand:DF 0 "memory_operand" "=m")
4012 (match_operand:XF 1 "register_operand" "f")))]
4015 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4016 return "fstp%z0\t%y0";
4018 return "fst%z0\t%y0";
4020 [(set_attr "type" "fmov")
4021 (set_attr "mode" "DF")])
4024 [(set (match_operand:DF 0 "memory_operand" "")
4026 (match_operand:XF 1 "register_operand" "")))
4027 (clobber (match_operand:DF 2 "memory_operand" ""))]
4029 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4033 [(set (match_operand:DF 0 "register_operand" "")
4035 (match_operand:XF 1 "register_operand" "")))
4036 (clobber (match_operand:DF 2 "memory_operand" ""))]
4037 "TARGET_80387 && reload_completed"
4038 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4039 (set (match_dup 0) (match_dup 2))]
4043 ;; %%% Break up all these bad boys.
4045 ;; Signed conversion to DImode.
4047 (define_expand "fix_truncxfdi2"
4048 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4049 (fix:DI (match_operand:XF 1 "register_operand" "")))
4050 (clobber (reg:CC FLAGS_REG))])]
4054 (define_expand "fix_truncdfdi2"
4055 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4056 (fix:DI (match_operand:DF 1 "register_operand" "")))
4057 (clobber (reg:CC FLAGS_REG))])]
4058 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4060 if (TARGET_64BIT && TARGET_SSE2)
4062 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4063 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4064 if (out != operands[0])
4065 emit_move_insn (operands[0], out);
4070 (define_expand "fix_truncsfdi2"
4071 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4072 (fix:DI (match_operand:SF 1 "register_operand" "")))
4073 (clobber (reg:CC FLAGS_REG))])]
4074 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4076 if (TARGET_SSE && TARGET_64BIT)
4078 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4079 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4080 if (out != operands[0])
4081 emit_move_insn (operands[0], out);
4086 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4087 ;; of the machinery.
4088 (define_insn_and_split "*fix_truncdi_1"
4089 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4090 (fix:DI (match_operand 1 "register_operand" "f,f")))
4091 (clobber (reg:CC FLAGS_REG))]
4092 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4093 && !reload_completed && !reload_in_progress
4094 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4099 ix86_optimize_mode_switching = 1;
4100 operands[2] = assign_386_stack_local (HImode, 1);
4101 operands[3] = assign_386_stack_local (HImode, 2);
4102 if (memory_operand (operands[0], VOIDmode))
4103 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4104 operands[2], operands[3]));
4107 operands[4] = assign_386_stack_local (DImode, 0);
4108 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4109 operands[2], operands[3],
4114 [(set_attr "type" "fistp")
4115 (set_attr "i387_cw" "trunc")
4116 (set_attr "mode" "DI")])
4118 (define_insn "fix_truncdi_nomemory"
4119 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4120 (fix:DI (match_operand 1 "register_operand" "f,f")))
4121 (use (match_operand:HI 2 "memory_operand" "m,m"))
4122 (use (match_operand:HI 3 "memory_operand" "m,m"))
4123 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4124 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4125 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4126 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4128 [(set_attr "type" "fistp")
4129 (set_attr "i387_cw" "trunc")
4130 (set_attr "mode" "DI")])
4132 (define_insn "fix_truncdi_memory"
4133 [(set (match_operand:DI 0 "memory_operand" "=m")
4134 (fix:DI (match_operand 1 "register_operand" "f")))
4135 (use (match_operand:HI 2 "memory_operand" "m"))
4136 (use (match_operand:HI 3 "memory_operand" "m"))
4137 (clobber (match_scratch:DF 4 "=&1f"))]
4138 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4139 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4140 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4141 [(set_attr "type" "fistp")
4142 (set_attr "i387_cw" "trunc")
4143 (set_attr "mode" "DI")])
4146 [(set (match_operand:DI 0 "register_operand" "")
4147 (fix:DI (match_operand 1 "register_operand" "")))
4148 (use (match_operand:HI 2 "memory_operand" ""))
4149 (use (match_operand:HI 3 "memory_operand" ""))
4150 (clobber (match_operand:DI 4 "memory_operand" ""))
4151 (clobber (match_scratch 5 ""))]
4153 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4156 (clobber (match_dup 5))])
4157 (set (match_dup 0) (match_dup 4))]
4161 [(set (match_operand:DI 0 "memory_operand" "")
4162 (fix:DI (match_operand 1 "register_operand" "")))
4163 (use (match_operand:HI 2 "memory_operand" ""))
4164 (use (match_operand:HI 3 "memory_operand" ""))
4165 (clobber (match_operand:DI 4 "memory_operand" ""))
4166 (clobber (match_scratch 5 ""))]
4168 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4171 (clobber (match_dup 5))])]
4174 ;; When SSE available, it is always faster to use it!
4175 (define_insn "fix_truncsfdi_sse"
4176 [(set (match_operand:DI 0 "register_operand" "=r,r")
4177 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4178 "TARGET_64BIT && TARGET_SSE"
4179 "cvttss2si{q}\t{%1, %0|%0, %1}"
4180 [(set_attr "type" "sseicvt")
4181 (set_attr "mode" "SF")
4182 (set_attr "athlon_decode" "double,vector")])
4184 ;; Avoid vector decoded form of the instruction.
4186 [(match_scratch:SF 2 "x")
4187 (set (match_operand:DI 0 "register_operand" "")
4188 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4189 "TARGET_K8 && !optimize_size"
4190 [(set (match_dup 2) (match_dup 1))
4191 (set (match_dup 0) (fix:DI (match_dup 2)))]
4194 (define_insn "fix_truncdfdi_sse"
4195 [(set (match_operand:DI 0 "register_operand" "=r,r")
4196 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4197 "TARGET_64BIT && TARGET_SSE2"
4198 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4199 [(set_attr "type" "sseicvt,sseicvt")
4200 (set_attr "mode" "DF")
4201 (set_attr "athlon_decode" "double,vector")])
4203 ;; Avoid vector decoded form of the instruction.
4205 [(match_scratch:DF 2 "Y")
4206 (set (match_operand:DI 0 "register_operand" "")
4207 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4208 "TARGET_K8 && !optimize_size"
4209 [(set (match_dup 2) (match_dup 1))
4210 (set (match_dup 0) (fix:DI (match_dup 2)))]
4213 ;; Signed conversion to SImode.
4215 (define_expand "fix_truncxfsi2"
4216 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4217 (fix:SI (match_operand:XF 1 "register_operand" "")))
4218 (clobber (reg:CC FLAGS_REG))])]
4222 (define_expand "fix_truncdfsi2"
4223 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4224 (fix:SI (match_operand:DF 1 "register_operand" "")))
4225 (clobber (reg:CC FLAGS_REG))])]
4226 "TARGET_80387 || TARGET_SSE2"
4230 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4231 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4232 if (out != operands[0])
4233 emit_move_insn (operands[0], out);
4238 (define_expand "fix_truncsfsi2"
4239 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4240 (fix:SI (match_operand:SF 1 "register_operand" "")))
4241 (clobber (reg:CC FLAGS_REG))])]
4242 "TARGET_80387 || TARGET_SSE"
4246 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4247 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4248 if (out != operands[0])
4249 emit_move_insn (operands[0], out);
4254 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4255 ;; of the machinery.
4256 (define_insn_and_split "*fix_truncsi_1"
4257 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4258 (fix:SI (match_operand 1 "register_operand" "f,f")))
4259 (clobber (reg:CC FLAGS_REG))]
4260 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4261 && !reload_completed && !reload_in_progress
4262 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4267 ix86_optimize_mode_switching = 1;
4268 operands[2] = assign_386_stack_local (HImode, 1);
4269 operands[3] = assign_386_stack_local (HImode, 2);
4270 if (memory_operand (operands[0], VOIDmode))
4271 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4272 operands[2], operands[3]));
4275 operands[4] = assign_386_stack_local (SImode, 0);
4276 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4277 operands[2], operands[3],
4282 [(set_attr "type" "fistp")
4283 (set_attr "i387_cw" "trunc")
4284 (set_attr "mode" "SI")])
4286 (define_insn "fix_truncsi_nomemory"
4287 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4288 (fix:SI (match_operand 1 "register_operand" "f,f")))
4289 (use (match_operand:HI 2 "memory_operand" "m,m"))
4290 (use (match_operand:HI 3 "memory_operand" "m,m"))
4291 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4292 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4293 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4295 [(set_attr "type" "fistp")
4296 (set_attr "i387_cw" "trunc")
4297 (set_attr "mode" "SI")])
4299 (define_insn "fix_truncsi_memory"
4300 [(set (match_operand:SI 0 "memory_operand" "=m")
4301 (fix:SI (match_operand 1 "register_operand" "f")))
4302 (use (match_operand:HI 2 "memory_operand" "m"))
4303 (use (match_operand:HI 3 "memory_operand" "m"))]
4304 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4305 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4306 "* return output_fix_trunc (insn, operands);"
4307 [(set_attr "type" "fistp")
4308 (set_attr "i387_cw" "trunc")
4309 (set_attr "mode" "SI")])
4311 ;; When SSE available, it is always faster to use it!
4312 (define_insn "fix_truncsfsi_sse"
4313 [(set (match_operand:SI 0 "register_operand" "=r,r")
4314 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4316 "cvttss2si\t{%1, %0|%0, %1}"
4317 [(set_attr "type" "sseicvt")
4318 (set_attr "mode" "DF")
4319 (set_attr "athlon_decode" "double,vector")])
4321 ;; Avoid vector decoded form of the instruction.
4323 [(match_scratch:SF 2 "x")
4324 (set (match_operand:SI 0 "register_operand" "")
4325 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4326 "TARGET_K8 && !optimize_size"
4327 [(set (match_dup 2) (match_dup 1))
4328 (set (match_dup 0) (fix:SI (match_dup 2)))]
4331 (define_insn "fix_truncdfsi_sse"
4332 [(set (match_operand:SI 0 "register_operand" "=r,r")
4333 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4335 "cvttsd2si\t{%1, %0|%0, %1}"
4336 [(set_attr "type" "sseicvt")
4337 (set_attr "mode" "DF")
4338 (set_attr "athlon_decode" "double,vector")])
4340 ;; Avoid vector decoded form of the instruction.
4342 [(match_scratch:DF 2 "Y")
4343 (set (match_operand:SI 0 "register_operand" "")
4344 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4345 "TARGET_K8 && !optimize_size"
4346 [(set (match_dup 2) (match_dup 1))
4347 (set (match_dup 0) (fix:SI (match_dup 2)))]
4351 [(set (match_operand:SI 0 "register_operand" "")
4352 (fix:SI (match_operand 1 "register_operand" "")))
4353 (use (match_operand:HI 2 "memory_operand" ""))
4354 (use (match_operand:HI 3 "memory_operand" ""))
4355 (clobber (match_operand:SI 4 "memory_operand" ""))]
4357 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4359 (use (match_dup 3))])
4360 (set (match_dup 0) (match_dup 4))]
4364 [(set (match_operand:SI 0 "memory_operand" "")
4365 (fix:SI (match_operand 1 "register_operand" "")))
4366 (use (match_operand:HI 2 "memory_operand" ""))
4367 (use (match_operand:HI 3 "memory_operand" ""))
4368 (clobber (match_operand:SI 4 "memory_operand" ""))]
4370 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4372 (use (match_dup 3))])]
4375 ;; Signed conversion to HImode.
4377 (define_expand "fix_truncxfhi2"
4378 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4379 (fix:HI (match_operand:XF 1 "register_operand" "")))
4380 (clobber (reg:CC FLAGS_REG))])]
4384 (define_expand "fix_truncdfhi2"
4385 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4386 (fix:HI (match_operand:DF 1 "register_operand" "")))
4387 (clobber (reg:CC FLAGS_REG))])]
4388 "TARGET_80387 && !TARGET_SSE2"
4391 (define_expand "fix_truncsfhi2"
4392 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4393 (fix:HI (match_operand:SF 1 "register_operand" "")))
4394 (clobber (reg:CC FLAGS_REG))])]
4395 "TARGET_80387 && !TARGET_SSE"
4398 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4399 ;; of the machinery.
4400 (define_insn_and_split "*fix_trunchi_1"
4401 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4402 (fix:HI (match_operand 1 "register_operand" "f,f")))
4403 (clobber (reg:CC FLAGS_REG))]
4404 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4405 && !reload_completed && !reload_in_progress
4406 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4411 ix86_optimize_mode_switching = 1;
4412 operands[2] = assign_386_stack_local (HImode, 1);
4413 operands[3] = assign_386_stack_local (HImode, 2);
4414 if (memory_operand (operands[0], VOIDmode))
4415 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4416 operands[2], operands[3]));
4419 operands[4] = assign_386_stack_local (HImode, 0);
4420 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4421 operands[2], operands[3],
4426 [(set_attr "type" "fistp")
4427 (set_attr "i387_cw" "trunc")
4428 (set_attr "mode" "HI")])
4430 (define_insn "fix_trunchi_nomemory"
4431 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4432 (fix:HI (match_operand 1 "register_operand" "f,f")))
4433 (use (match_operand:HI 2 "memory_operand" "m,m"))
4434 (use (match_operand:HI 3 "memory_operand" "m,m"))
4435 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4436 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4437 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4439 [(set_attr "type" "fistp")
4440 (set_attr "i387_cw" "trunc")
4441 (set_attr "mode" "HI")])
4443 (define_insn "fix_trunchi_memory"
4444 [(set (match_operand:HI 0 "memory_operand" "=m")
4445 (fix:HI (match_operand 1 "register_operand" "f")))
4446 (use (match_operand:HI 2 "memory_operand" "m"))
4447 (use (match_operand:HI 3 "memory_operand" "m"))]
4448 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4449 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4450 "* return output_fix_trunc (insn, operands);"
4451 [(set_attr "type" "fistp")
4452 (set_attr "i387_cw" "trunc")
4453 (set_attr "mode" "HI")])
4456 [(set (match_operand:HI 0 "memory_operand" "")
4457 (fix:HI (match_operand 1 "register_operand" "")))
4458 (use (match_operand:HI 2 "memory_operand" ""))
4459 (use (match_operand:HI 3 "memory_operand" ""))
4460 (clobber (match_operand:HI 4 "memory_operand" ""))]
4462 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4464 (use (match_dup 3))])]
4468 [(set (match_operand:HI 0 "register_operand" "")
4469 (fix:HI (match_operand 1 "register_operand" "")))
4470 (use (match_operand:HI 2 "memory_operand" ""))
4471 (use (match_operand:HI 3 "memory_operand" ""))
4472 (clobber (match_operand:HI 4 "memory_operand" ""))]
4474 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4477 (clobber (match_dup 4))])
4478 (set (match_dup 0) (match_dup 4))]
4481 (define_insn "x86_fnstcw_1"
4482 [(set (match_operand:HI 0 "memory_operand" "=m")
4483 (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
4486 [(set_attr "length" "2")
4487 (set_attr "mode" "HI")
4488 (set_attr "unit" "i387")])
4490 (define_insn "x86_fldcw_1"
4491 [(set (reg:HI FPSR_REG)
4492 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4495 [(set_attr "length" "2")
4496 (set_attr "mode" "HI")
4497 (set_attr "unit" "i387")
4498 (set_attr "athlon_decode" "vector")])
4500 ;; Conversion between fixed point and floating point.
4502 ;; Even though we only accept memory inputs, the backend _really_
4503 ;; wants to be able to do this between registers.
4505 (define_expand "floathisf2"
4506 [(set (match_operand:SF 0 "register_operand" "")
4507 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4508 "TARGET_SSE || TARGET_80387"
4510 if (TARGET_SSE && TARGET_SSE_MATH)
4512 emit_insn (gen_floatsisf2 (operands[0],
4513 convert_to_mode (SImode, operands[1], 0)));
4518 (define_insn "*floathisf2_1"
4519 [(set (match_operand:SF 0 "register_operand" "=f,f")
4520 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4521 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4525 [(set_attr "type" "fmov,multi")
4526 (set_attr "mode" "SF")
4527 (set_attr "fp_int_src" "true")])
4529 (define_expand "floatsisf2"
4530 [(set (match_operand:SF 0 "register_operand" "")
4531 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4532 "TARGET_SSE || TARGET_80387"
4535 (define_insn "*floatsisf2_i387"
4536 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4537 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4538 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4542 cvtsi2ss\t{%1, %0|%0, %1}
4543 cvtsi2ss\t{%1, %0|%0, %1}"
4544 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4545 (set_attr "mode" "SF")
4546 (set_attr "athlon_decode" "*,*,vector,double")
4547 (set_attr "fp_int_src" "true")])
4549 (define_insn "*floatsisf2_sse"
4550 [(set (match_operand:SF 0 "register_operand" "=x,x")
4551 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4553 "cvtsi2ss\t{%1, %0|%0, %1}"
4554 [(set_attr "type" "sseicvt")
4555 (set_attr "mode" "SF")
4556 (set_attr "athlon_decode" "vector,double")
4557 (set_attr "fp_int_src" "true")])
4559 ; Avoid possible reformatting penalty on the destination by first
4562 [(set (match_operand:SF 0 "register_operand" "")
4563 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4564 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4565 && SSE_REG_P (operands[0])"
4569 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4570 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4571 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4575 (define_expand "floatdisf2"
4576 [(set (match_operand:SF 0 "register_operand" "")
4577 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4578 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4581 (define_insn "*floatdisf2_i387_only"
4582 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4583 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4584 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4588 [(set_attr "type" "fmov,multi")
4589 (set_attr "mode" "SF")
4590 (set_attr "fp_int_src" "true")])
4592 (define_insn "*floatdisf2_i387"
4593 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4594 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4595 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4599 cvtsi2ss{q}\t{%1, %0|%0, %1}
4600 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4601 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4602 (set_attr "mode" "SF")
4603 (set_attr "athlon_decode" "*,*,vector,double")
4604 (set_attr "fp_int_src" "true")])
4606 (define_insn "*floatdisf2_sse"
4607 [(set (match_operand:SF 0 "register_operand" "=x,x")
4608 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4609 "TARGET_64BIT && TARGET_SSE"
4610 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4611 [(set_attr "type" "sseicvt")
4612 (set_attr "mode" "SF")
4613 (set_attr "athlon_decode" "vector,double")
4614 (set_attr "fp_int_src" "true")])
4616 ; Avoid possible reformatting penalty on the destination by first
4619 [(set (match_operand:SF 0 "register_operand" "")
4620 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4621 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4622 && SSE_REG_P (operands[0])"
4626 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4627 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4628 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4632 (define_expand "floathidf2"
4633 [(set (match_operand:DF 0 "register_operand" "")
4634 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4635 "TARGET_SSE2 || TARGET_80387"
4637 if (TARGET_SSE && TARGET_SSE_MATH)
4639 emit_insn (gen_floatsidf2 (operands[0],
4640 convert_to_mode (SImode, operands[1], 0)));
4645 (define_insn "*floathidf2_1"
4646 [(set (match_operand:DF 0 "register_operand" "=f,f")
4647 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4648 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4652 [(set_attr "type" "fmov,multi")
4653 (set_attr "mode" "DF")
4654 (set_attr "fp_int_src" "true")])
4656 (define_expand "floatsidf2"
4657 [(set (match_operand:DF 0 "register_operand" "")
4658 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4659 "TARGET_80387 || TARGET_SSE2"
4662 (define_insn "*floatsidf2_i387"
4663 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4664 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4665 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4669 cvtsi2sd\t{%1, %0|%0, %1}
4670 cvtsi2sd\t{%1, %0|%0, %1}"
4671 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4672 (set_attr "mode" "DF")
4673 (set_attr "athlon_decode" "*,*,double,direct")
4674 (set_attr "fp_int_src" "true")])
4676 (define_insn "*floatsidf2_sse"
4677 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4678 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4680 "cvtsi2sd\t{%1, %0|%0, %1}"
4681 [(set_attr "type" "sseicvt")
4682 (set_attr "mode" "DF")
4683 (set_attr "athlon_decode" "double,direct")
4684 (set_attr "fp_int_src" "true")])
4686 (define_expand "floatdidf2"
4687 [(set (match_operand:DF 0 "register_operand" "")
4688 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4689 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4692 (define_insn "*floatdidf2_i387_only"
4693 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4694 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4695 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4699 [(set_attr "type" "fmov,multi")
4700 (set_attr "mode" "DF")
4701 (set_attr "fp_int_src" "true")])
4703 (define_insn "*floatdidf2_i387"
4704 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4705 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4706 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4710 cvtsi2sd{q}\t{%1, %0|%0, %1}
4711 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4712 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4713 (set_attr "mode" "DF")
4714 (set_attr "athlon_decode" "*,*,double,direct")
4715 (set_attr "fp_int_src" "true")])
4717 (define_insn "*floatdidf2_sse"
4718 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4719 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4721 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4722 [(set_attr "type" "sseicvt")
4723 (set_attr "mode" "DF")
4724 (set_attr "athlon_decode" "double,direct")
4725 (set_attr "fp_int_src" "true")])
4727 (define_insn "floathixf2"
4728 [(set (match_operand:XF 0 "register_operand" "=f,f")
4729 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4734 [(set_attr "type" "fmov,multi")
4735 (set_attr "mode" "XF")
4736 (set_attr "fp_int_src" "true")])
4738 (define_insn "floatsixf2"
4739 [(set (match_operand:XF 0 "register_operand" "=f,f")
4740 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4745 [(set_attr "type" "fmov,multi")
4746 (set_attr "mode" "XF")
4747 (set_attr "fp_int_src" "true")])
4749 (define_insn "floatdixf2"
4750 [(set (match_operand:XF 0 "register_operand" "=f,f")
4751 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4756 [(set_attr "type" "fmov,multi")
4757 (set_attr "mode" "XF")
4758 (set_attr "fp_int_src" "true")])
4760 ;; %%% Kill these when reload knows how to do it.
4762 [(set (match_operand 0 "fp_register_operand" "")
4763 (float (match_operand 1 "register_operand" "")))]
4764 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4767 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4768 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4769 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4770 ix86_free_from_memory (GET_MODE (operands[1]));
4774 (define_expand "floatunssisf2"
4775 [(use (match_operand:SF 0 "register_operand" ""))
4776 (use (match_operand:SI 1 "register_operand" ""))]
4777 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
4778 "x86_emit_floatuns (operands); DONE;")
4780 (define_expand "floatunsdisf2"
4781 [(use (match_operand:SF 0 "register_operand" ""))
4782 (use (match_operand:DI 1 "register_operand" ""))]
4783 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
4784 "x86_emit_floatuns (operands); DONE;")
4786 (define_expand "floatunsdidf2"
4787 [(use (match_operand:DF 0 "register_operand" ""))
4788 (use (match_operand:DI 1 "register_operand" ""))]
4789 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
4790 "x86_emit_floatuns (operands); DONE;")
4792 ;; SSE extract/set expanders
4794 (define_expand "vec_setv2df"
4795 [(match_operand:V2DF 0 "register_operand" "")
4796 (match_operand:DF 1 "register_operand" "")
4797 (match_operand 2 "const_int_operand" "")]
4800 switch (INTVAL (operands[2]))
4803 emit_insn (gen_sse2_movsd (operands[0], operands[0],
4804 simplify_gen_subreg (V2DFmode, operands[1],
4809 rtx op1 = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4811 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], op1));
4820 (define_expand "vec_extractv2df"
4821 [(match_operand:DF 0 "register_operand" "")
4822 (match_operand:V2DF 1 "register_operand" "")
4823 (match_operand 2 "const_int_operand" "")]
4826 switch (INTVAL (operands[2]))
4829 emit_move_insn (operands[0], gen_lowpart (DFmode, operands[1]));
4833 rtx dest = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
4835 emit_insn (gen_sse2_unpckhpd (dest, operands[1], operands[1]));
4844 (define_expand "vec_initv2df"
4845 [(match_operand:V2DF 0 "register_operand" "")
4846 (match_operand 1 "" "")]
4849 ix86_expand_vector_init (operands[0], operands[1]);
4853 (define_expand "vec_setv4sf"
4854 [(match_operand:V4SF 0 "register_operand" "")
4855 (match_operand:SF 1 "register_operand" "")
4856 (match_operand 2 "const_int_operand" "")]
4859 switch (INTVAL (operands[2]))
4862 emit_insn (gen_sse_movss (operands[0], operands[0],
4863 simplify_gen_subreg (V4SFmode, operands[1],
4868 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4869 rtx tmp = gen_reg_rtx (V4SFmode);
4871 emit_move_insn (tmp, operands[0]);
4872 emit_insn (gen_sse_unpcklps (operands[0], operands[0], operands[0]));
4873 emit_insn (gen_sse_movss (operands[0], operands[0], op1));
4874 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4875 GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
4880 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4881 rtx tmp = gen_reg_rtx (V4SFmode);
4883 emit_move_insn (tmp, operands[0]);
4884 emit_insn (gen_sse_movss (tmp, tmp, op1));
4885 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4886 GEN_INT (0 + (1<<2) + (0<<4) + (3<<6))));
4891 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4892 rtx tmp = gen_reg_rtx (V4SFmode);
4894 emit_move_insn (tmp, operands[0]);
4895 emit_insn (gen_sse_movss (tmp, tmp, op1));
4896 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4897 GEN_INT (0 + (1<<2) + (2<<4) + (0<<6))));
4906 (define_expand "vec_extractv4sf"
4907 [(match_operand:SF 0 "register_operand" "")
4908 (match_operand:V4SF 1 "register_operand" "")
4909 (match_operand 2 "const_int_operand" "")]
4912 switch (INTVAL (operands[2]))
4915 emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1]));
4919 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4920 rtx tmp = gen_reg_rtx (V4SFmode);
4922 emit_move_insn (tmp, operands[1]);
4923 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4929 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4930 rtx tmp = gen_reg_rtx (V4SFmode);
4932 emit_move_insn (tmp, operands[1]);
4933 emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
4938 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4939 rtx tmp = gen_reg_rtx (V4SFmode);
4941 emit_move_insn (tmp, operands[1]);
4942 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4952 (define_expand "vec_initv4sf"
4953 [(match_operand:V4SF 0 "register_operand" "")
4954 (match_operand 1 "" "")]
4957 ix86_expand_vector_init (operands[0], operands[1]);
4963 ;; %%% splits for addsidi3
4964 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4965 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4966 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4968 (define_expand "adddi3"
4969 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4970 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4971 (match_operand:DI 2 "x86_64_general_operand" "")))
4972 (clobber (reg:CC FLAGS_REG))]
4974 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4976 (define_insn "*adddi3_1"
4977 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4978 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4979 (match_operand:DI 2 "general_operand" "roiF,riF")))
4980 (clobber (reg:CC FLAGS_REG))]
4981 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4985 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4986 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4987 (match_operand:DI 2 "general_operand" "")))
4988 (clobber (reg:CC FLAGS_REG))]
4989 "!TARGET_64BIT && reload_completed"
4990 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
4992 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4993 (parallel [(set (match_dup 3)
4994 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
4997 (clobber (reg:CC FLAGS_REG))])]
4998 "split_di (operands+0, 1, operands+0, operands+3);
4999 split_di (operands+1, 1, operands+1, operands+4);
5000 split_di (operands+2, 1, operands+2, operands+5);")
5002 (define_insn "adddi3_carry_rex64"
5003 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5004 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
5005 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5006 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5007 (clobber (reg:CC FLAGS_REG))]
5008 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5009 "adc{q}\t{%2, %0|%0, %2}"
5010 [(set_attr "type" "alu")
5011 (set_attr "pent_pair" "pu")
5012 (set_attr "mode" "DI")])
5014 (define_insn "*adddi3_cc_rex64"
5015 [(set (reg:CC FLAGS_REG)
5016 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5017 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
5019 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5020 (plus:DI (match_dup 1) (match_dup 2)))]
5021 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5022 "add{q}\t{%2, %0|%0, %2}"
5023 [(set_attr "type" "alu")
5024 (set_attr "mode" "DI")])
5026 (define_insn "addqi3_carry"
5027 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5028 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
5029 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
5030 (match_operand:QI 2 "general_operand" "qi,qm")))
5031 (clobber (reg:CC FLAGS_REG))]
5032 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5033 "adc{b}\t{%2, %0|%0, %2}"
5034 [(set_attr "type" "alu")
5035 (set_attr "pent_pair" "pu")
5036 (set_attr "mode" "QI")])
5038 (define_insn "addhi3_carry"
5039 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5040 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5041 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5042 (match_operand:HI 2 "general_operand" "ri,rm")))
5043 (clobber (reg:CC FLAGS_REG))]
5044 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5045 "adc{w}\t{%2, %0|%0, %2}"
5046 [(set_attr "type" "alu")
5047 (set_attr "pent_pair" "pu")
5048 (set_attr "mode" "HI")])
5050 (define_insn "addsi3_carry"
5051 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5052 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5053 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5054 (match_operand:SI 2 "general_operand" "ri,rm")))
5055 (clobber (reg:CC FLAGS_REG))]
5056 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5057 "adc{l}\t{%2, %0|%0, %2}"
5058 [(set_attr "type" "alu")
5059 (set_attr "pent_pair" "pu")
5060 (set_attr "mode" "SI")])
5062 (define_insn "*addsi3_carry_zext"
5063 [(set (match_operand:DI 0 "register_operand" "=r")
5065 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5066 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5067 (match_operand:SI 2 "general_operand" "rim"))))
5068 (clobber (reg:CC FLAGS_REG))]
5069 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5070 "adc{l}\t{%2, %k0|%k0, %2}"
5071 [(set_attr "type" "alu")
5072 (set_attr "pent_pair" "pu")
5073 (set_attr "mode" "SI")])
5075 (define_insn "*addsi3_cc"
5076 [(set (reg:CC FLAGS_REG)
5077 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5078 (match_operand:SI 2 "general_operand" "ri,rm")]
5080 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5081 (plus:SI (match_dup 1) (match_dup 2)))]
5082 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5083 "add{l}\t{%2, %0|%0, %2}"
5084 [(set_attr "type" "alu")
5085 (set_attr "mode" "SI")])
5087 (define_insn "addqi3_cc"
5088 [(set (reg:CC FLAGS_REG)
5089 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5090 (match_operand:QI 2 "general_operand" "qi,qm")]
5092 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5093 (plus:QI (match_dup 1) (match_dup 2)))]
5094 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5095 "add{b}\t{%2, %0|%0, %2}"
5096 [(set_attr "type" "alu")
5097 (set_attr "mode" "QI")])
5099 (define_expand "addsi3"
5100 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5101 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5102 (match_operand:SI 2 "general_operand" "")))
5103 (clobber (reg:CC FLAGS_REG))])]
5105 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5107 (define_insn "*lea_1"
5108 [(set (match_operand:SI 0 "register_operand" "=r")
5109 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5111 "lea{l}\t{%a1, %0|%0, %a1}"
5112 [(set_attr "type" "lea")
5113 (set_attr "mode" "SI")])
5115 (define_insn "*lea_1_rex64"
5116 [(set (match_operand:SI 0 "register_operand" "=r")
5117 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5119 "lea{l}\t{%a1, %0|%0, %a1}"
5120 [(set_attr "type" "lea")
5121 (set_attr "mode" "SI")])
5123 (define_insn "*lea_1_zext"
5124 [(set (match_operand:DI 0 "register_operand" "=r")
5126 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5128 "lea{l}\t{%a1, %k0|%k0, %a1}"
5129 [(set_attr "type" "lea")
5130 (set_attr "mode" "SI")])
5132 (define_insn "*lea_2_rex64"
5133 [(set (match_operand:DI 0 "register_operand" "=r")
5134 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5136 "lea{q}\t{%a1, %0|%0, %a1}"
5137 [(set_attr "type" "lea")
5138 (set_attr "mode" "DI")])
5140 ;; The lea patterns for non-Pmodes needs to be matched by several
5141 ;; insns converted to real lea by splitters.
5143 (define_insn_and_split "*lea_general_1"
5144 [(set (match_operand 0 "register_operand" "=r")
5145 (plus (plus (match_operand 1 "index_register_operand" "r")
5146 (match_operand 2 "register_operand" "r"))
5147 (match_operand 3 "immediate_operand" "i")))]
5148 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5149 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5150 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5151 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5152 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5153 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5154 || GET_MODE (operands[3]) == VOIDmode)"
5156 "&& reload_completed"
5160 operands[0] = gen_lowpart (SImode, operands[0]);
5161 operands[1] = gen_lowpart (Pmode, operands[1]);
5162 operands[2] = gen_lowpart (Pmode, operands[2]);
5163 operands[3] = gen_lowpart (Pmode, operands[3]);
5164 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5166 if (Pmode != SImode)
5167 pat = gen_rtx_SUBREG (SImode, pat, 0);
5168 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5171 [(set_attr "type" "lea")
5172 (set_attr "mode" "SI")])
5174 (define_insn_and_split "*lea_general_1_zext"
5175 [(set (match_operand:DI 0 "register_operand" "=r")
5177 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5178 (match_operand:SI 2 "register_operand" "r"))
5179 (match_operand:SI 3 "immediate_operand" "i"))))]
5182 "&& reload_completed"
5184 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5186 (match_dup 3)) 0)))]
5188 operands[1] = gen_lowpart (Pmode, operands[1]);
5189 operands[2] = gen_lowpart (Pmode, operands[2]);
5190 operands[3] = gen_lowpart (Pmode, operands[3]);
5192 [(set_attr "type" "lea")
5193 (set_attr "mode" "SI")])
5195 (define_insn_and_split "*lea_general_2"
5196 [(set (match_operand 0 "register_operand" "=r")
5197 (plus (mult (match_operand 1 "index_register_operand" "r")
5198 (match_operand 2 "const248_operand" "i"))
5199 (match_operand 3 "nonmemory_operand" "ri")))]
5200 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5201 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5202 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5203 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5204 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5205 || GET_MODE (operands[3]) == VOIDmode)"
5207 "&& reload_completed"
5211 operands[0] = gen_lowpart (SImode, operands[0]);
5212 operands[1] = gen_lowpart (Pmode, operands[1]);
5213 operands[3] = gen_lowpart (Pmode, operands[3]);
5214 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5216 if (Pmode != SImode)
5217 pat = gen_rtx_SUBREG (SImode, pat, 0);
5218 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5221 [(set_attr "type" "lea")
5222 (set_attr "mode" "SI")])
5224 (define_insn_and_split "*lea_general_2_zext"
5225 [(set (match_operand:DI 0 "register_operand" "=r")
5227 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5228 (match_operand:SI 2 "const248_operand" "n"))
5229 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5232 "&& reload_completed"
5234 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5236 (match_dup 3)) 0)))]
5238 operands[1] = gen_lowpart (Pmode, operands[1]);
5239 operands[3] = gen_lowpart (Pmode, operands[3]);
5241 [(set_attr "type" "lea")
5242 (set_attr "mode" "SI")])
5244 (define_insn_and_split "*lea_general_3"
5245 [(set (match_operand 0 "register_operand" "=r")
5246 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5247 (match_operand 2 "const248_operand" "i"))
5248 (match_operand 3 "register_operand" "r"))
5249 (match_operand 4 "immediate_operand" "i")))]
5250 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5251 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5252 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5253 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5254 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5256 "&& reload_completed"
5260 operands[0] = gen_lowpart (SImode, operands[0]);
5261 operands[1] = gen_lowpart (Pmode, operands[1]);
5262 operands[3] = gen_lowpart (Pmode, operands[3]);
5263 operands[4] = gen_lowpart (Pmode, operands[4]);
5264 pat = gen_rtx_PLUS (Pmode,
5265 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5269 if (Pmode != SImode)
5270 pat = gen_rtx_SUBREG (SImode, pat, 0);
5271 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5274 [(set_attr "type" "lea")
5275 (set_attr "mode" "SI")])
5277 (define_insn_and_split "*lea_general_3_zext"
5278 [(set (match_operand:DI 0 "register_operand" "=r")
5280 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5281 (match_operand:SI 2 "const248_operand" "n"))
5282 (match_operand:SI 3 "register_operand" "r"))
5283 (match_operand:SI 4 "immediate_operand" "i"))))]
5286 "&& reload_completed"
5288 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5291 (match_dup 4)) 0)))]
5293 operands[1] = gen_lowpart (Pmode, operands[1]);
5294 operands[3] = gen_lowpart (Pmode, operands[3]);
5295 operands[4] = gen_lowpart (Pmode, operands[4]);
5297 [(set_attr "type" "lea")
5298 (set_attr "mode" "SI")])
5300 (define_insn "*adddi_1_rex64"
5301 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5302 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5303 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5304 (clobber (reg:CC FLAGS_REG))]
5305 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5307 switch (get_attr_type (insn))
5310 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5311 return "lea{q}\t{%a2, %0|%0, %a2}";
5314 if (! rtx_equal_p (operands[0], operands[1]))
5316 if (operands[2] == const1_rtx)
5317 return "inc{q}\t%0";
5318 else if (operands[2] == constm1_rtx)
5319 return "dec{q}\t%0";
5324 if (! rtx_equal_p (operands[0], operands[1]))
5327 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5328 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5329 if (GET_CODE (operands[2]) == CONST_INT
5330 /* Avoid overflows. */
5331 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5332 && (INTVAL (operands[2]) == 128
5333 || (INTVAL (operands[2]) < 0
5334 && INTVAL (operands[2]) != -128)))
5336 operands[2] = GEN_INT (-INTVAL (operands[2]));
5337 return "sub{q}\t{%2, %0|%0, %2}";
5339 return "add{q}\t{%2, %0|%0, %2}";
5343 (cond [(eq_attr "alternative" "2")
5344 (const_string "lea")
5345 ; Current assemblers are broken and do not allow @GOTOFF in
5346 ; ought but a memory context.
5347 (match_operand:DI 2 "pic_symbolic_operand" "")
5348 (const_string "lea")
5349 (match_operand:DI 2 "incdec_operand" "")
5350 (const_string "incdec")
5352 (const_string "alu")))
5353 (set_attr "mode" "DI")])
5355 ;; Convert lea to the lea pattern to avoid flags dependency.
5357 [(set (match_operand:DI 0 "register_operand" "")
5358 (plus:DI (match_operand:DI 1 "register_operand" "")
5359 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5360 (clobber (reg:CC FLAGS_REG))]
5361 "TARGET_64BIT && reload_completed
5362 && true_regnum (operands[0]) != true_regnum (operands[1])"
5364 (plus:DI (match_dup 1)
5368 (define_insn "*adddi_2_rex64"
5371 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5372 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5374 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5375 (plus:DI (match_dup 1) (match_dup 2)))]
5376 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5377 && ix86_binary_operator_ok (PLUS, DImode, operands)
5378 /* Current assemblers are broken and do not allow @GOTOFF in
5379 ought but a memory context. */
5380 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5382 switch (get_attr_type (insn))
5385 if (! rtx_equal_p (operands[0], operands[1]))
5387 if (operands[2] == const1_rtx)
5388 return "inc{q}\t%0";
5389 else if (operands[2] == constm1_rtx)
5390 return "dec{q}\t%0";
5395 if (! rtx_equal_p (operands[0], operands[1]))
5397 /* ???? We ought to handle there the 32bit case too
5398 - do we need new constraint? */
5399 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5400 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5401 if (GET_CODE (operands[2]) == CONST_INT
5402 /* Avoid overflows. */
5403 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5404 && (INTVAL (operands[2]) == 128
5405 || (INTVAL (operands[2]) < 0
5406 && INTVAL (operands[2]) != -128)))
5408 operands[2] = GEN_INT (-INTVAL (operands[2]));
5409 return "sub{q}\t{%2, %0|%0, %2}";
5411 return "add{q}\t{%2, %0|%0, %2}";
5415 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5416 (const_string "incdec")
5417 (const_string "alu")))
5418 (set_attr "mode" "DI")])
5420 (define_insn "*adddi_3_rex64"
5422 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5423 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5424 (clobber (match_scratch:DI 0 "=r"))]
5426 && ix86_match_ccmode (insn, CCZmode)
5427 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5428 /* Current assemblers are broken and do not allow @GOTOFF in
5429 ought but a memory context. */
5430 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5432 switch (get_attr_type (insn))
5435 if (! rtx_equal_p (operands[0], operands[1]))
5437 if (operands[2] == const1_rtx)
5438 return "inc{q}\t%0";
5439 else if (operands[2] == constm1_rtx)
5440 return "dec{q}\t%0";
5445 if (! rtx_equal_p (operands[0], operands[1]))
5447 /* ???? We ought to handle there the 32bit case too
5448 - do we need new constraint? */
5449 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5450 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5451 if (GET_CODE (operands[2]) == CONST_INT
5452 /* Avoid overflows. */
5453 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5454 && (INTVAL (operands[2]) == 128
5455 || (INTVAL (operands[2]) < 0
5456 && INTVAL (operands[2]) != -128)))
5458 operands[2] = GEN_INT (-INTVAL (operands[2]));
5459 return "sub{q}\t{%2, %0|%0, %2}";
5461 return "add{q}\t{%2, %0|%0, %2}";
5465 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5466 (const_string "incdec")
5467 (const_string "alu")))
5468 (set_attr "mode" "DI")])
5470 ; For comparisons against 1, -1 and 128, we may generate better code
5471 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5472 ; is matched then. We can't accept general immediate, because for
5473 ; case of overflows, the result is messed up.
5474 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5476 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5477 ; only for comparisons not depending on it.
5478 (define_insn "*adddi_4_rex64"
5480 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5481 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5482 (clobber (match_scratch:DI 0 "=rm"))]
5484 && ix86_match_ccmode (insn, CCGCmode)"
5486 switch (get_attr_type (insn))
5489 if (operands[2] == constm1_rtx)
5490 return "inc{q}\t%0";
5491 else if (operands[2] == const1_rtx)
5492 return "dec{q}\t%0";
5497 if (! rtx_equal_p (operands[0], operands[1]))
5499 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5500 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5501 if ((INTVAL (operands[2]) == -128
5502 || (INTVAL (operands[2]) > 0
5503 && INTVAL (operands[2]) != 128))
5504 /* Avoid overflows. */
5505 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5506 return "sub{q}\t{%2, %0|%0, %2}";
5507 operands[2] = GEN_INT (-INTVAL (operands[2]));
5508 return "add{q}\t{%2, %0|%0, %2}";
5512 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5513 (const_string "incdec")
5514 (const_string "alu")))
5515 (set_attr "mode" "DI")])
5517 (define_insn "*adddi_5_rex64"
5520 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5521 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5523 (clobber (match_scratch:DI 0 "=r"))]
5525 && ix86_match_ccmode (insn, CCGOCmode)
5526 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5527 /* Current assemblers are broken and do not allow @GOTOFF in
5528 ought but a memory context. */
5529 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5531 switch (get_attr_type (insn))
5534 if (! rtx_equal_p (operands[0], operands[1]))
5536 if (operands[2] == const1_rtx)
5537 return "inc{q}\t%0";
5538 else if (operands[2] == constm1_rtx)
5539 return "dec{q}\t%0";
5544 if (! rtx_equal_p (operands[0], operands[1]))
5546 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5547 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5548 if (GET_CODE (operands[2]) == CONST_INT
5549 /* Avoid overflows. */
5550 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5551 && (INTVAL (operands[2]) == 128
5552 || (INTVAL (operands[2]) < 0
5553 && INTVAL (operands[2]) != -128)))
5555 operands[2] = GEN_INT (-INTVAL (operands[2]));
5556 return "sub{q}\t{%2, %0|%0, %2}";
5558 return "add{q}\t{%2, %0|%0, %2}";
5562 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5563 (const_string "incdec")
5564 (const_string "alu")))
5565 (set_attr "mode" "DI")])
5568 (define_insn "*addsi_1"
5569 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5570 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5571 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5572 (clobber (reg:CC FLAGS_REG))]
5573 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5575 switch (get_attr_type (insn))
5578 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5579 return "lea{l}\t{%a2, %0|%0, %a2}";
5582 if (! rtx_equal_p (operands[0], operands[1]))
5584 if (operands[2] == const1_rtx)
5585 return "inc{l}\t%0";
5586 else if (operands[2] == constm1_rtx)
5587 return "dec{l}\t%0";
5592 if (! rtx_equal_p (operands[0], operands[1]))
5595 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5596 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5597 if (GET_CODE (operands[2]) == CONST_INT
5598 && (INTVAL (operands[2]) == 128
5599 || (INTVAL (operands[2]) < 0
5600 && INTVAL (operands[2]) != -128)))
5602 operands[2] = GEN_INT (-INTVAL (operands[2]));
5603 return "sub{l}\t{%2, %0|%0, %2}";
5605 return "add{l}\t{%2, %0|%0, %2}";
5609 (cond [(eq_attr "alternative" "2")
5610 (const_string "lea")
5611 ; Current assemblers are broken and do not allow @GOTOFF in
5612 ; ought but a memory context.
5613 (match_operand:SI 2 "pic_symbolic_operand" "")
5614 (const_string "lea")
5615 (match_operand:SI 2 "incdec_operand" "")
5616 (const_string "incdec")
5618 (const_string "alu")))
5619 (set_attr "mode" "SI")])
5621 ;; Convert lea to the lea pattern to avoid flags dependency.
5623 [(set (match_operand 0 "register_operand" "")
5624 (plus (match_operand 1 "register_operand" "")
5625 (match_operand 2 "nonmemory_operand" "")))
5626 (clobber (reg:CC FLAGS_REG))]
5628 && true_regnum (operands[0]) != true_regnum (operands[1])"
5632 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5633 may confuse gen_lowpart. */
5634 if (GET_MODE (operands[0]) != Pmode)
5636 operands[1] = gen_lowpart (Pmode, operands[1]);
5637 operands[2] = gen_lowpart (Pmode, operands[2]);
5639 operands[0] = gen_lowpart (SImode, operands[0]);
5640 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5641 if (Pmode != SImode)
5642 pat = gen_rtx_SUBREG (SImode, pat, 0);
5643 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5647 ;; It may seem that nonimmediate operand is proper one for operand 1.
5648 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5649 ;; we take care in ix86_binary_operator_ok to not allow two memory
5650 ;; operands so proper swapping will be done in reload. This allow
5651 ;; patterns constructed from addsi_1 to match.
5652 (define_insn "addsi_1_zext"
5653 [(set (match_operand:DI 0 "register_operand" "=r,r")
5655 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5656 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5657 (clobber (reg:CC FLAGS_REG))]
5658 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5660 switch (get_attr_type (insn))
5663 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5664 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5667 if (operands[2] == const1_rtx)
5668 return "inc{l}\t%k0";
5669 else if (operands[2] == constm1_rtx)
5670 return "dec{l}\t%k0";
5675 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5676 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5677 if (GET_CODE (operands[2]) == CONST_INT
5678 && (INTVAL (operands[2]) == 128
5679 || (INTVAL (operands[2]) < 0
5680 && INTVAL (operands[2]) != -128)))
5682 operands[2] = GEN_INT (-INTVAL (operands[2]));
5683 return "sub{l}\t{%2, %k0|%k0, %2}";
5685 return "add{l}\t{%2, %k0|%k0, %2}";
5689 (cond [(eq_attr "alternative" "1")
5690 (const_string "lea")
5691 ; Current assemblers are broken and do not allow @GOTOFF in
5692 ; ought but a memory context.
5693 (match_operand:SI 2 "pic_symbolic_operand" "")
5694 (const_string "lea")
5695 (match_operand:SI 2 "incdec_operand" "")
5696 (const_string "incdec")
5698 (const_string "alu")))
5699 (set_attr "mode" "SI")])
5701 ;; Convert lea to the lea pattern to avoid flags dependency.
5703 [(set (match_operand:DI 0 "register_operand" "")
5705 (plus:SI (match_operand:SI 1 "register_operand" "")
5706 (match_operand:SI 2 "nonmemory_operand" ""))))
5707 (clobber (reg:CC FLAGS_REG))]
5708 "TARGET_64BIT && reload_completed
5709 && true_regnum (operands[0]) != true_regnum (operands[1])"
5711 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5713 operands[1] = gen_lowpart (Pmode, operands[1]);
5714 operands[2] = gen_lowpart (Pmode, operands[2]);
5717 (define_insn "*addsi_2"
5720 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5721 (match_operand:SI 2 "general_operand" "rmni,rni"))
5723 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5724 (plus:SI (match_dup 1) (match_dup 2)))]
5725 "ix86_match_ccmode (insn, CCGOCmode)
5726 && ix86_binary_operator_ok (PLUS, SImode, operands)
5727 /* Current assemblers are broken and do not allow @GOTOFF in
5728 ought but a memory context. */
5729 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5731 switch (get_attr_type (insn))
5734 if (! rtx_equal_p (operands[0], operands[1]))
5736 if (operands[2] == const1_rtx)
5737 return "inc{l}\t%0";
5738 else if (operands[2] == constm1_rtx)
5739 return "dec{l}\t%0";
5744 if (! rtx_equal_p (operands[0], operands[1]))
5746 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5747 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5748 if (GET_CODE (operands[2]) == CONST_INT
5749 && (INTVAL (operands[2]) == 128
5750 || (INTVAL (operands[2]) < 0
5751 && INTVAL (operands[2]) != -128)))
5753 operands[2] = GEN_INT (-INTVAL (operands[2]));
5754 return "sub{l}\t{%2, %0|%0, %2}";
5756 return "add{l}\t{%2, %0|%0, %2}";
5760 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5761 (const_string "incdec")
5762 (const_string "alu")))
5763 (set_attr "mode" "SI")])
5765 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5766 (define_insn "*addsi_2_zext"
5769 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5770 (match_operand:SI 2 "general_operand" "rmni"))
5772 (set (match_operand:DI 0 "register_operand" "=r")
5773 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5774 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5775 && ix86_binary_operator_ok (PLUS, SImode, operands)
5776 /* Current assemblers are broken and do not allow @GOTOFF in
5777 ought but a memory context. */
5778 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5780 switch (get_attr_type (insn))
5783 if (operands[2] == const1_rtx)
5784 return "inc{l}\t%k0";
5785 else if (operands[2] == constm1_rtx)
5786 return "dec{l}\t%k0";
5791 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5792 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5793 if (GET_CODE (operands[2]) == CONST_INT
5794 && (INTVAL (operands[2]) == 128
5795 || (INTVAL (operands[2]) < 0
5796 && INTVAL (operands[2]) != -128)))
5798 operands[2] = GEN_INT (-INTVAL (operands[2]));
5799 return "sub{l}\t{%2, %k0|%k0, %2}";
5801 return "add{l}\t{%2, %k0|%k0, %2}";
5805 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5806 (const_string "incdec")
5807 (const_string "alu")))
5808 (set_attr "mode" "SI")])
5810 (define_insn "*addsi_3"
5812 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5813 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5814 (clobber (match_scratch:SI 0 "=r"))]
5815 "ix86_match_ccmode (insn, CCZmode)
5816 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5817 /* Current assemblers are broken and do not allow @GOTOFF in
5818 ought but a memory context. */
5819 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5821 switch (get_attr_type (insn))
5824 if (! rtx_equal_p (operands[0], operands[1]))
5826 if (operands[2] == const1_rtx)
5827 return "inc{l}\t%0";
5828 else if (operands[2] == constm1_rtx)
5829 return "dec{l}\t%0";
5834 if (! rtx_equal_p (operands[0], operands[1]))
5836 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5837 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5838 if (GET_CODE (operands[2]) == CONST_INT
5839 && (INTVAL (operands[2]) == 128
5840 || (INTVAL (operands[2]) < 0
5841 && INTVAL (operands[2]) != -128)))
5843 operands[2] = GEN_INT (-INTVAL (operands[2]));
5844 return "sub{l}\t{%2, %0|%0, %2}";
5846 return "add{l}\t{%2, %0|%0, %2}";
5850 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5851 (const_string "incdec")
5852 (const_string "alu")))
5853 (set_attr "mode" "SI")])
5855 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5856 (define_insn "*addsi_3_zext"
5858 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5859 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5860 (set (match_operand:DI 0 "register_operand" "=r")
5861 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5862 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5863 && ix86_binary_operator_ok (PLUS, SImode, operands)
5864 /* Current assemblers are broken and do not allow @GOTOFF in
5865 ought but a memory context. */
5866 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5868 switch (get_attr_type (insn))
5871 if (operands[2] == const1_rtx)
5872 return "inc{l}\t%k0";
5873 else if (operands[2] == constm1_rtx)
5874 return "dec{l}\t%k0";
5879 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5880 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5881 if (GET_CODE (operands[2]) == CONST_INT
5882 && (INTVAL (operands[2]) == 128
5883 || (INTVAL (operands[2]) < 0
5884 && INTVAL (operands[2]) != -128)))
5886 operands[2] = GEN_INT (-INTVAL (operands[2]));
5887 return "sub{l}\t{%2, %k0|%k0, %2}";
5889 return "add{l}\t{%2, %k0|%k0, %2}";
5893 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5894 (const_string "incdec")
5895 (const_string "alu")))
5896 (set_attr "mode" "SI")])
5898 ; For comparisons against 1, -1 and 128, we may generate better code
5899 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5900 ; is matched then. We can't accept general immediate, because for
5901 ; case of overflows, the result is messed up.
5902 ; This pattern also don't hold of 0x80000000, since the value overflows
5904 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5905 ; only for comparisons not depending on it.
5906 (define_insn "*addsi_4"
5908 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5909 (match_operand:SI 2 "const_int_operand" "n")))
5910 (clobber (match_scratch:SI 0 "=rm"))]
5911 "ix86_match_ccmode (insn, CCGCmode)
5912 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5914 switch (get_attr_type (insn))
5917 if (operands[2] == constm1_rtx)
5918 return "inc{l}\t%0";
5919 else if (operands[2] == const1_rtx)
5920 return "dec{l}\t%0";
5925 if (! rtx_equal_p (operands[0], operands[1]))
5927 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5928 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5929 if ((INTVAL (operands[2]) == -128
5930 || (INTVAL (operands[2]) > 0
5931 && INTVAL (operands[2]) != 128)))
5932 return "sub{l}\t{%2, %0|%0, %2}";
5933 operands[2] = GEN_INT (-INTVAL (operands[2]));
5934 return "add{l}\t{%2, %0|%0, %2}";
5938 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5939 (const_string "incdec")
5940 (const_string "alu")))
5941 (set_attr "mode" "SI")])
5943 (define_insn "*addsi_5"
5946 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5947 (match_operand:SI 2 "general_operand" "rmni"))
5949 (clobber (match_scratch:SI 0 "=r"))]
5950 "ix86_match_ccmode (insn, CCGOCmode)
5951 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5952 /* Current assemblers are broken and do not allow @GOTOFF in
5953 ought but a memory context. */
5954 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5956 switch (get_attr_type (insn))
5959 if (! rtx_equal_p (operands[0], operands[1]))
5961 if (operands[2] == const1_rtx)
5962 return "inc{l}\t%0";
5963 else if (operands[2] == constm1_rtx)
5964 return "dec{l}\t%0";
5969 if (! rtx_equal_p (operands[0], operands[1]))
5971 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5972 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5973 if (GET_CODE (operands[2]) == CONST_INT
5974 && (INTVAL (operands[2]) == 128
5975 || (INTVAL (operands[2]) < 0
5976 && INTVAL (operands[2]) != -128)))
5978 operands[2] = GEN_INT (-INTVAL (operands[2]));
5979 return "sub{l}\t{%2, %0|%0, %2}";
5981 return "add{l}\t{%2, %0|%0, %2}";
5985 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5986 (const_string "incdec")
5987 (const_string "alu")))
5988 (set_attr "mode" "SI")])
5990 (define_expand "addhi3"
5991 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5992 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5993 (match_operand:HI 2 "general_operand" "")))
5994 (clobber (reg:CC FLAGS_REG))])]
5995 "TARGET_HIMODE_MATH"
5996 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5998 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5999 ;; type optimizations enabled by define-splits. This is not important
6000 ;; for PII, and in fact harmful because of partial register stalls.
6002 (define_insn "*addhi_1_lea"
6003 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6004 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6005 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6006 (clobber (reg:CC FLAGS_REG))]
6007 "!TARGET_PARTIAL_REG_STALL
6008 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6010 switch (get_attr_type (insn))
6015 if (operands[2] == const1_rtx)
6016 return "inc{w}\t%0";
6017 else if (operands[2] == constm1_rtx)
6018 return "dec{w}\t%0";
6022 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6023 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6024 if (GET_CODE (operands[2]) == CONST_INT
6025 && (INTVAL (operands[2]) == 128
6026 || (INTVAL (operands[2]) < 0
6027 && INTVAL (operands[2]) != -128)))
6029 operands[2] = GEN_INT (-INTVAL (operands[2]));
6030 return "sub{w}\t{%2, %0|%0, %2}";
6032 return "add{w}\t{%2, %0|%0, %2}";
6036 (if_then_else (eq_attr "alternative" "2")
6037 (const_string "lea")
6038 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6039 (const_string "incdec")
6040 (const_string "alu"))))
6041 (set_attr "mode" "HI,HI,SI")])
6043 (define_insn "*addhi_1"
6044 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6045 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6046 (match_operand:HI 2 "general_operand" "ri,rm")))
6047 (clobber (reg:CC FLAGS_REG))]
6048 "TARGET_PARTIAL_REG_STALL
6049 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6051 switch (get_attr_type (insn))
6054 if (operands[2] == const1_rtx)
6055 return "inc{w}\t%0";
6056 else if (operands[2] == constm1_rtx)
6057 return "dec{w}\t%0";
6061 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6062 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6063 if (GET_CODE (operands[2]) == CONST_INT
6064 && (INTVAL (operands[2]) == 128
6065 || (INTVAL (operands[2]) < 0
6066 && INTVAL (operands[2]) != -128)))
6068 operands[2] = GEN_INT (-INTVAL (operands[2]));
6069 return "sub{w}\t{%2, %0|%0, %2}";
6071 return "add{w}\t{%2, %0|%0, %2}";
6075 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6076 (const_string "incdec")
6077 (const_string "alu")))
6078 (set_attr "mode" "HI")])
6080 (define_insn "*addhi_2"
6083 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6084 (match_operand:HI 2 "general_operand" "rmni,rni"))
6086 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6087 (plus:HI (match_dup 1) (match_dup 2)))]
6088 "ix86_match_ccmode (insn, CCGOCmode)
6089 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6091 switch (get_attr_type (insn))
6094 if (operands[2] == const1_rtx)
6095 return "inc{w}\t%0";
6096 else if (operands[2] == constm1_rtx)
6097 return "dec{w}\t%0";
6101 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6102 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6103 if (GET_CODE (operands[2]) == CONST_INT
6104 && (INTVAL (operands[2]) == 128
6105 || (INTVAL (operands[2]) < 0
6106 && INTVAL (operands[2]) != -128)))
6108 operands[2] = GEN_INT (-INTVAL (operands[2]));
6109 return "sub{w}\t{%2, %0|%0, %2}";
6111 return "add{w}\t{%2, %0|%0, %2}";
6115 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6116 (const_string "incdec")
6117 (const_string "alu")))
6118 (set_attr "mode" "HI")])
6120 (define_insn "*addhi_3"
6122 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6123 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6124 (clobber (match_scratch:HI 0 "=r"))]
6125 "ix86_match_ccmode (insn, CCZmode)
6126 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6128 switch (get_attr_type (insn))
6131 if (operands[2] == const1_rtx)
6132 return "inc{w}\t%0";
6133 else if (operands[2] == constm1_rtx)
6134 return "dec{w}\t%0";
6138 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6139 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6140 if (GET_CODE (operands[2]) == CONST_INT
6141 && (INTVAL (operands[2]) == 128
6142 || (INTVAL (operands[2]) < 0
6143 && INTVAL (operands[2]) != -128)))
6145 operands[2] = GEN_INT (-INTVAL (operands[2]));
6146 return "sub{w}\t{%2, %0|%0, %2}";
6148 return "add{w}\t{%2, %0|%0, %2}";
6152 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6153 (const_string "incdec")
6154 (const_string "alu")))
6155 (set_attr "mode" "HI")])
6157 ; See comments above addsi_3_imm for details.
6158 (define_insn "*addhi_4"
6160 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6161 (match_operand:HI 2 "const_int_operand" "n")))
6162 (clobber (match_scratch:HI 0 "=rm"))]
6163 "ix86_match_ccmode (insn, CCGCmode)
6164 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6166 switch (get_attr_type (insn))
6169 if (operands[2] == constm1_rtx)
6170 return "inc{w}\t%0";
6171 else if (operands[2] == const1_rtx)
6172 return "dec{w}\t%0";
6177 if (! rtx_equal_p (operands[0], operands[1]))
6179 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6180 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6181 if ((INTVAL (operands[2]) == -128
6182 || (INTVAL (operands[2]) > 0
6183 && INTVAL (operands[2]) != 128)))
6184 return "sub{w}\t{%2, %0|%0, %2}";
6185 operands[2] = GEN_INT (-INTVAL (operands[2]));
6186 return "add{w}\t{%2, %0|%0, %2}";
6190 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6191 (const_string "incdec")
6192 (const_string "alu")))
6193 (set_attr "mode" "SI")])
6196 (define_insn "*addhi_5"
6199 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6200 (match_operand:HI 2 "general_operand" "rmni"))
6202 (clobber (match_scratch:HI 0 "=r"))]
6203 "ix86_match_ccmode (insn, CCGOCmode)
6204 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6206 switch (get_attr_type (insn))
6209 if (operands[2] == const1_rtx)
6210 return "inc{w}\t%0";
6211 else if (operands[2] == constm1_rtx)
6212 return "dec{w}\t%0";
6216 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6217 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6218 if (GET_CODE (operands[2]) == CONST_INT
6219 && (INTVAL (operands[2]) == 128
6220 || (INTVAL (operands[2]) < 0
6221 && INTVAL (operands[2]) != -128)))
6223 operands[2] = GEN_INT (-INTVAL (operands[2]));
6224 return "sub{w}\t{%2, %0|%0, %2}";
6226 return "add{w}\t{%2, %0|%0, %2}";
6230 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6231 (const_string "incdec")
6232 (const_string "alu")))
6233 (set_attr "mode" "HI")])
6235 (define_expand "addqi3"
6236 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6237 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6238 (match_operand:QI 2 "general_operand" "")))
6239 (clobber (reg:CC FLAGS_REG))])]
6240 "TARGET_QIMODE_MATH"
6241 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6243 ;; %%% Potential partial reg stall on alternative 2. What to do?
6244 (define_insn "*addqi_1_lea"
6245 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6246 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6247 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6248 (clobber (reg:CC FLAGS_REG))]
6249 "!TARGET_PARTIAL_REG_STALL
6250 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6252 int widen = (which_alternative == 2);
6253 switch (get_attr_type (insn))
6258 if (operands[2] == const1_rtx)
6259 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6260 else if (operands[2] == constm1_rtx)
6261 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6265 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6266 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6267 if (GET_CODE (operands[2]) == CONST_INT
6268 && (INTVAL (operands[2]) == 128
6269 || (INTVAL (operands[2]) < 0
6270 && INTVAL (operands[2]) != -128)))
6272 operands[2] = GEN_INT (-INTVAL (operands[2]));
6274 return "sub{l}\t{%2, %k0|%k0, %2}";
6276 return "sub{b}\t{%2, %0|%0, %2}";
6279 return "add{l}\t{%k2, %k0|%k0, %k2}";
6281 return "add{b}\t{%2, %0|%0, %2}";
6285 (if_then_else (eq_attr "alternative" "3")
6286 (const_string "lea")
6287 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6288 (const_string "incdec")
6289 (const_string "alu"))))
6290 (set_attr "mode" "QI,QI,SI,SI")])
6292 (define_insn "*addqi_1"
6293 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6294 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6295 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6296 (clobber (reg:CC FLAGS_REG))]
6297 "TARGET_PARTIAL_REG_STALL
6298 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6300 int widen = (which_alternative == 2);
6301 switch (get_attr_type (insn))
6304 if (operands[2] == const1_rtx)
6305 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6306 else if (operands[2] == constm1_rtx)
6307 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6311 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6312 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6313 if (GET_CODE (operands[2]) == CONST_INT
6314 && (INTVAL (operands[2]) == 128
6315 || (INTVAL (operands[2]) < 0
6316 && INTVAL (operands[2]) != -128)))
6318 operands[2] = GEN_INT (-INTVAL (operands[2]));
6320 return "sub{l}\t{%2, %k0|%k0, %2}";
6322 return "sub{b}\t{%2, %0|%0, %2}";
6325 return "add{l}\t{%k2, %k0|%k0, %k2}";
6327 return "add{b}\t{%2, %0|%0, %2}";
6331 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6332 (const_string "incdec")
6333 (const_string "alu")))
6334 (set_attr "mode" "QI,QI,SI")])
6336 (define_insn "*addqi_1_slp"
6337 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6338 (plus:QI (match_dup 0)
6339 (match_operand:QI 1 "general_operand" "qn,qnm")))
6340 (clobber (reg:CC FLAGS_REG))]
6341 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6342 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6344 switch (get_attr_type (insn))
6347 if (operands[1] == const1_rtx)
6348 return "inc{b}\t%0";
6349 else if (operands[1] == constm1_rtx)
6350 return "dec{b}\t%0";
6354 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6355 if (GET_CODE (operands[1]) == CONST_INT
6356 && INTVAL (operands[1]) < 0)
6358 operands[1] = GEN_INT (-INTVAL (operands[1]));
6359 return "sub{b}\t{%1, %0|%0, %1}";
6361 return "add{b}\t{%1, %0|%0, %1}";
6365 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6366 (const_string "incdec")
6367 (const_string "alu1")))
6368 (set_attr "mode" "QI")])
6370 (define_insn "*addqi_2"
6373 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6374 (match_operand:QI 2 "general_operand" "qmni,qni"))
6376 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6377 (plus:QI (match_dup 1) (match_dup 2)))]
6378 "ix86_match_ccmode (insn, CCGOCmode)
6379 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6381 switch (get_attr_type (insn))
6384 if (operands[2] == const1_rtx)
6385 return "inc{b}\t%0";
6386 else if (operands[2] == constm1_rtx
6387 || (GET_CODE (operands[2]) == CONST_INT
6388 && INTVAL (operands[2]) == 255))
6389 return "dec{b}\t%0";
6393 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6394 if (GET_CODE (operands[2]) == CONST_INT
6395 && INTVAL (operands[2]) < 0)
6397 operands[2] = GEN_INT (-INTVAL (operands[2]));
6398 return "sub{b}\t{%2, %0|%0, %2}";
6400 return "add{b}\t{%2, %0|%0, %2}";
6404 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6405 (const_string "incdec")
6406 (const_string "alu")))
6407 (set_attr "mode" "QI")])
6409 (define_insn "*addqi_3"
6411 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6412 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6413 (clobber (match_scratch:QI 0 "=q"))]
6414 "ix86_match_ccmode (insn, CCZmode)
6415 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6417 switch (get_attr_type (insn))
6420 if (operands[2] == const1_rtx)
6421 return "inc{b}\t%0";
6422 else if (operands[2] == constm1_rtx
6423 || (GET_CODE (operands[2]) == CONST_INT
6424 && INTVAL (operands[2]) == 255))
6425 return "dec{b}\t%0";
6429 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6430 if (GET_CODE (operands[2]) == CONST_INT
6431 && INTVAL (operands[2]) < 0)
6433 operands[2] = GEN_INT (-INTVAL (operands[2]));
6434 return "sub{b}\t{%2, %0|%0, %2}";
6436 return "add{b}\t{%2, %0|%0, %2}";
6440 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6441 (const_string "incdec")
6442 (const_string "alu")))
6443 (set_attr "mode" "QI")])
6445 ; See comments above addsi_3_imm for details.
6446 (define_insn "*addqi_4"
6448 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6449 (match_operand:QI 2 "const_int_operand" "n")))
6450 (clobber (match_scratch:QI 0 "=qm"))]
6451 "ix86_match_ccmode (insn, CCGCmode)
6452 && (INTVAL (operands[2]) & 0xff) != 0x80"
6454 switch (get_attr_type (insn))
6457 if (operands[2] == constm1_rtx
6458 || (GET_CODE (operands[2]) == CONST_INT
6459 && INTVAL (operands[2]) == 255))
6460 return "inc{b}\t%0";
6461 else if (operands[2] == const1_rtx)
6462 return "dec{b}\t%0";
6467 if (! rtx_equal_p (operands[0], operands[1]))
6469 if (INTVAL (operands[2]) < 0)
6471 operands[2] = GEN_INT (-INTVAL (operands[2]));
6472 return "add{b}\t{%2, %0|%0, %2}";
6474 return "sub{b}\t{%2, %0|%0, %2}";
6478 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6479 (const_string "incdec")
6480 (const_string "alu")))
6481 (set_attr "mode" "QI")])
6484 (define_insn "*addqi_5"
6487 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6488 (match_operand:QI 2 "general_operand" "qmni"))
6490 (clobber (match_scratch:QI 0 "=q"))]
6491 "ix86_match_ccmode (insn, CCGOCmode)
6492 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6494 switch (get_attr_type (insn))
6497 if (operands[2] == const1_rtx)
6498 return "inc{b}\t%0";
6499 else if (operands[2] == constm1_rtx
6500 || (GET_CODE (operands[2]) == CONST_INT
6501 && INTVAL (operands[2]) == 255))
6502 return "dec{b}\t%0";
6506 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6507 if (GET_CODE (operands[2]) == CONST_INT
6508 && INTVAL (operands[2]) < 0)
6510 operands[2] = GEN_INT (-INTVAL (operands[2]));
6511 return "sub{b}\t{%2, %0|%0, %2}";
6513 return "add{b}\t{%2, %0|%0, %2}";
6517 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6518 (const_string "incdec")
6519 (const_string "alu")))
6520 (set_attr "mode" "QI")])
6523 (define_insn "addqi_ext_1"
6524 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6529 (match_operand 1 "ext_register_operand" "0")
6532 (match_operand:QI 2 "general_operand" "Qmn")))
6533 (clobber (reg:CC FLAGS_REG))]
6536 switch (get_attr_type (insn))
6539 if (operands[2] == const1_rtx)
6540 return "inc{b}\t%h0";
6541 else if (operands[2] == constm1_rtx
6542 || (GET_CODE (operands[2]) == CONST_INT
6543 && INTVAL (operands[2]) == 255))
6544 return "dec{b}\t%h0";
6548 return "add{b}\t{%2, %h0|%h0, %2}";
6552 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6553 (const_string "incdec")
6554 (const_string "alu")))
6555 (set_attr "mode" "QI")])
6557 (define_insn "*addqi_ext_1_rex64"
6558 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6563 (match_operand 1 "ext_register_operand" "0")
6566 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6567 (clobber (reg:CC FLAGS_REG))]
6570 switch (get_attr_type (insn))
6573 if (operands[2] == const1_rtx)
6574 return "inc{b}\t%h0";
6575 else if (operands[2] == constm1_rtx
6576 || (GET_CODE (operands[2]) == CONST_INT
6577 && INTVAL (operands[2]) == 255))
6578 return "dec{b}\t%h0";
6582 return "add{b}\t{%2, %h0|%h0, %2}";
6586 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6587 (const_string "incdec")
6588 (const_string "alu")))
6589 (set_attr "mode" "QI")])
6591 (define_insn "*addqi_ext_2"
6592 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6597 (match_operand 1 "ext_register_operand" "%0")
6601 (match_operand 2 "ext_register_operand" "Q")
6604 (clobber (reg:CC FLAGS_REG))]
6606 "add{b}\t{%h2, %h0|%h0, %h2}"
6607 [(set_attr "type" "alu")
6608 (set_attr "mode" "QI")])
6610 ;; The patterns that match these are at the end of this file.
6612 (define_expand "addxf3"
6613 [(set (match_operand:XF 0 "register_operand" "")
6614 (plus:XF (match_operand:XF 1 "register_operand" "")
6615 (match_operand:XF 2 "register_operand" "")))]
6619 (define_expand "adddf3"
6620 [(set (match_operand:DF 0 "register_operand" "")
6621 (plus:DF (match_operand:DF 1 "register_operand" "")
6622 (match_operand:DF 2 "nonimmediate_operand" "")))]
6623 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6626 (define_expand "addsf3"
6627 [(set (match_operand:SF 0 "register_operand" "")
6628 (plus:SF (match_operand:SF 1 "register_operand" "")
6629 (match_operand:SF 2 "nonimmediate_operand" "")))]
6630 "TARGET_80387 || TARGET_SSE_MATH"
6633 ;; Subtract instructions
6635 ;; %%% splits for subsidi3
6637 (define_expand "subdi3"
6638 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6639 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6640 (match_operand:DI 2 "x86_64_general_operand" "")))
6641 (clobber (reg:CC FLAGS_REG))])]
6643 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6645 (define_insn "*subdi3_1"
6646 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6647 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6648 (match_operand:DI 2 "general_operand" "roiF,riF")))
6649 (clobber (reg:CC FLAGS_REG))]
6650 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6654 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6655 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6656 (match_operand:DI 2 "general_operand" "")))
6657 (clobber (reg:CC FLAGS_REG))]
6658 "!TARGET_64BIT && reload_completed"
6659 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
6660 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6661 (parallel [(set (match_dup 3)
6662 (minus:SI (match_dup 4)
6663 (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
6665 (clobber (reg:CC FLAGS_REG))])]
6666 "split_di (operands+0, 1, operands+0, operands+3);
6667 split_di (operands+1, 1, operands+1, operands+4);
6668 split_di (operands+2, 1, operands+2, operands+5);")
6670 (define_insn "subdi3_carry_rex64"
6671 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6672 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6673 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6674 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6675 (clobber (reg:CC FLAGS_REG))]
6676 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6677 "sbb{q}\t{%2, %0|%0, %2}"
6678 [(set_attr "type" "alu")
6679 (set_attr "pent_pair" "pu")
6680 (set_attr "mode" "DI")])
6682 (define_insn "*subdi_1_rex64"
6683 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6684 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6685 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6686 (clobber (reg:CC FLAGS_REG))]
6687 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6688 "sub{q}\t{%2, %0|%0, %2}"
6689 [(set_attr "type" "alu")
6690 (set_attr "mode" "DI")])
6692 (define_insn "*subdi_2_rex64"
6695 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6696 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6698 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6699 (minus:DI (match_dup 1) (match_dup 2)))]
6700 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6701 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6702 "sub{q}\t{%2, %0|%0, %2}"
6703 [(set_attr "type" "alu")
6704 (set_attr "mode" "DI")])
6706 (define_insn "*subdi_3_rex63"
6708 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6709 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6710 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6711 (minus:DI (match_dup 1) (match_dup 2)))]
6712 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6713 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6714 "sub{q}\t{%2, %0|%0, %2}"
6715 [(set_attr "type" "alu")
6716 (set_attr "mode" "DI")])
6718 (define_insn "subqi3_carry"
6719 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6720 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6721 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6722 (match_operand:QI 2 "general_operand" "qi,qm"))))
6723 (clobber (reg:CC FLAGS_REG))]
6724 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6725 "sbb{b}\t{%2, %0|%0, %2}"
6726 [(set_attr "type" "alu")
6727 (set_attr "pent_pair" "pu")
6728 (set_attr "mode" "QI")])
6730 (define_insn "subhi3_carry"
6731 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6732 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6733 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6734 (match_operand:HI 2 "general_operand" "ri,rm"))))
6735 (clobber (reg:CC FLAGS_REG))]
6736 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6737 "sbb{w}\t{%2, %0|%0, %2}"
6738 [(set_attr "type" "alu")
6739 (set_attr "pent_pair" "pu")
6740 (set_attr "mode" "HI")])
6742 (define_insn "subsi3_carry"
6743 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6744 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6745 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6746 (match_operand:SI 2 "general_operand" "ri,rm"))))
6747 (clobber (reg:CC FLAGS_REG))]
6748 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6749 "sbb{l}\t{%2, %0|%0, %2}"
6750 [(set_attr "type" "alu")
6751 (set_attr "pent_pair" "pu")
6752 (set_attr "mode" "SI")])
6754 (define_insn "subsi3_carry_zext"
6755 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6757 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6758 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6759 (match_operand:SI 2 "general_operand" "ri,rm")))))
6760 (clobber (reg:CC FLAGS_REG))]
6761 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6762 "sbb{l}\t{%2, %k0|%k0, %2}"
6763 [(set_attr "type" "alu")
6764 (set_attr "pent_pair" "pu")
6765 (set_attr "mode" "SI")])
6767 (define_expand "subsi3"
6768 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6769 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6770 (match_operand:SI 2 "general_operand" "")))
6771 (clobber (reg:CC FLAGS_REG))])]
6773 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6775 (define_insn "*subsi_1"
6776 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6777 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6778 (match_operand:SI 2 "general_operand" "ri,rm")))
6779 (clobber (reg:CC FLAGS_REG))]
6780 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6781 "sub{l}\t{%2, %0|%0, %2}"
6782 [(set_attr "type" "alu")
6783 (set_attr "mode" "SI")])
6785 (define_insn "*subsi_1_zext"
6786 [(set (match_operand:DI 0 "register_operand" "=r")
6788 (minus:SI (match_operand:SI 1 "register_operand" "0")
6789 (match_operand:SI 2 "general_operand" "rim"))))
6790 (clobber (reg:CC FLAGS_REG))]
6791 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6792 "sub{l}\t{%2, %k0|%k0, %2}"
6793 [(set_attr "type" "alu")
6794 (set_attr "mode" "SI")])
6796 (define_insn "*subsi_2"
6799 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6800 (match_operand:SI 2 "general_operand" "ri,rm"))
6802 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6803 (minus:SI (match_dup 1) (match_dup 2)))]
6804 "ix86_match_ccmode (insn, CCGOCmode)
6805 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6806 "sub{l}\t{%2, %0|%0, %2}"
6807 [(set_attr "type" "alu")
6808 (set_attr "mode" "SI")])
6810 (define_insn "*subsi_2_zext"
6813 (minus:SI (match_operand:SI 1 "register_operand" "0")
6814 (match_operand:SI 2 "general_operand" "rim"))
6816 (set (match_operand:DI 0 "register_operand" "=r")
6818 (minus:SI (match_dup 1)
6820 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6821 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6822 "sub{l}\t{%2, %k0|%k0, %2}"
6823 [(set_attr "type" "alu")
6824 (set_attr "mode" "SI")])
6826 (define_insn "*subsi_3"
6828 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6829 (match_operand:SI 2 "general_operand" "ri,rm")))
6830 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6831 (minus:SI (match_dup 1) (match_dup 2)))]
6832 "ix86_match_ccmode (insn, CCmode)
6833 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6834 "sub{l}\t{%2, %0|%0, %2}"
6835 [(set_attr "type" "alu")
6836 (set_attr "mode" "SI")])
6838 (define_insn "*subsi_3_zext"
6840 (compare (match_operand:SI 1 "register_operand" "0")
6841 (match_operand:SI 2 "general_operand" "rim")))
6842 (set (match_operand:DI 0 "register_operand" "=r")
6844 (minus:SI (match_dup 1)
6846 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6847 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6848 "sub{q}\t{%2, %0|%0, %2}"
6849 [(set_attr "type" "alu")
6850 (set_attr "mode" "DI")])
6852 (define_expand "subhi3"
6853 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6854 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6855 (match_operand:HI 2 "general_operand" "")))
6856 (clobber (reg:CC FLAGS_REG))])]
6857 "TARGET_HIMODE_MATH"
6858 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6860 (define_insn "*subhi_1"
6861 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6862 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6863 (match_operand:HI 2 "general_operand" "ri,rm")))
6864 (clobber (reg:CC FLAGS_REG))]
6865 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6866 "sub{w}\t{%2, %0|%0, %2}"
6867 [(set_attr "type" "alu")
6868 (set_attr "mode" "HI")])
6870 (define_insn "*subhi_2"
6873 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6874 (match_operand:HI 2 "general_operand" "ri,rm"))
6876 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6877 (minus:HI (match_dup 1) (match_dup 2)))]
6878 "ix86_match_ccmode (insn, CCGOCmode)
6879 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6880 "sub{w}\t{%2, %0|%0, %2}"
6881 [(set_attr "type" "alu")
6882 (set_attr "mode" "HI")])
6884 (define_insn "*subhi_3"
6886 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6887 (match_operand:HI 2 "general_operand" "ri,rm")))
6888 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6889 (minus:HI (match_dup 1) (match_dup 2)))]
6890 "ix86_match_ccmode (insn, CCmode)
6891 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6892 "sub{w}\t{%2, %0|%0, %2}"
6893 [(set_attr "type" "alu")
6894 (set_attr "mode" "HI")])
6896 (define_expand "subqi3"
6897 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6898 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6899 (match_operand:QI 2 "general_operand" "")))
6900 (clobber (reg:CC FLAGS_REG))])]
6901 "TARGET_QIMODE_MATH"
6902 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6904 (define_insn "*subqi_1"
6905 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6906 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6907 (match_operand:QI 2 "general_operand" "qn,qmn")))
6908 (clobber (reg:CC FLAGS_REG))]
6909 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6910 "sub{b}\t{%2, %0|%0, %2}"
6911 [(set_attr "type" "alu")
6912 (set_attr "mode" "QI")])
6914 (define_insn "*subqi_1_slp"
6915 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6916 (minus:QI (match_dup 0)
6917 (match_operand:QI 1 "general_operand" "qn,qmn")))
6918 (clobber (reg:CC FLAGS_REG))]
6919 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6920 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6921 "sub{b}\t{%1, %0|%0, %1}"
6922 [(set_attr "type" "alu1")
6923 (set_attr "mode" "QI")])
6925 (define_insn "*subqi_2"
6928 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6929 (match_operand:QI 2 "general_operand" "qi,qm"))
6931 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6932 (minus:HI (match_dup 1) (match_dup 2)))]
6933 "ix86_match_ccmode (insn, CCGOCmode)
6934 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6935 "sub{b}\t{%2, %0|%0, %2}"
6936 [(set_attr "type" "alu")
6937 (set_attr "mode" "QI")])
6939 (define_insn "*subqi_3"
6941 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6942 (match_operand:QI 2 "general_operand" "qi,qm")))
6943 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6944 (minus:HI (match_dup 1) (match_dup 2)))]
6945 "ix86_match_ccmode (insn, CCmode)
6946 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6947 "sub{b}\t{%2, %0|%0, %2}"
6948 [(set_attr "type" "alu")
6949 (set_attr "mode" "QI")])
6951 ;; The patterns that match these are at the end of this file.
6953 (define_expand "subxf3"
6954 [(set (match_operand:XF 0 "register_operand" "")
6955 (minus:XF (match_operand:XF 1 "register_operand" "")
6956 (match_operand:XF 2 "register_operand" "")))]
6960 (define_expand "subdf3"
6961 [(set (match_operand:DF 0 "register_operand" "")
6962 (minus:DF (match_operand:DF 1 "register_operand" "")
6963 (match_operand:DF 2 "nonimmediate_operand" "")))]
6964 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6967 (define_expand "subsf3"
6968 [(set (match_operand:SF 0 "register_operand" "")
6969 (minus:SF (match_operand:SF 1 "register_operand" "")
6970 (match_operand:SF 2 "nonimmediate_operand" "")))]
6971 "TARGET_80387 || TARGET_SSE_MATH"
6974 ;; Multiply instructions
6976 (define_expand "muldi3"
6977 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6978 (mult:DI (match_operand:DI 1 "register_operand" "")
6979 (match_operand:DI 2 "x86_64_general_operand" "")))
6980 (clobber (reg:CC FLAGS_REG))])]
6984 (define_insn "*muldi3_1_rex64"
6985 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6986 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6987 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6988 (clobber (reg:CC FLAGS_REG))]
6990 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6992 imul{q}\t{%2, %1, %0|%0, %1, %2}
6993 imul{q}\t{%2, %1, %0|%0, %1, %2}
6994 imul{q}\t{%2, %0|%0, %2}"
6995 [(set_attr "type" "imul")
6996 (set_attr "prefix_0f" "0,0,1")
6997 (set (attr "athlon_decode")
6998 (cond [(eq_attr "cpu" "athlon")
6999 (const_string "vector")
7000 (eq_attr "alternative" "1")
7001 (const_string "vector")
7002 (and (eq_attr "alternative" "2")
7003 (match_operand 1 "memory_operand" ""))
7004 (const_string "vector")]
7005 (const_string "direct")))
7006 (set_attr "mode" "DI")])
7008 (define_expand "mulsi3"
7009 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7010 (mult:SI (match_operand:SI 1 "register_operand" "")
7011 (match_operand:SI 2 "general_operand" "")))
7012 (clobber (reg:CC FLAGS_REG))])]
7016 (define_insn "*mulsi3_1"
7017 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7018 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7019 (match_operand:SI 2 "general_operand" "K,i,mr")))
7020 (clobber (reg:CC FLAGS_REG))]
7021 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7023 imul{l}\t{%2, %1, %0|%0, %1, %2}
7024 imul{l}\t{%2, %1, %0|%0, %1, %2}
7025 imul{l}\t{%2, %0|%0, %2}"
7026 [(set_attr "type" "imul")
7027 (set_attr "prefix_0f" "0,0,1")
7028 (set (attr "athlon_decode")
7029 (cond [(eq_attr "cpu" "athlon")
7030 (const_string "vector")
7031 (eq_attr "alternative" "1")
7032 (const_string "vector")
7033 (and (eq_attr "alternative" "2")
7034 (match_operand 1 "memory_operand" ""))
7035 (const_string "vector")]
7036 (const_string "direct")))
7037 (set_attr "mode" "SI")])
7039 (define_insn "*mulsi3_1_zext"
7040 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7042 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7043 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7044 (clobber (reg:CC FLAGS_REG))]
7046 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7048 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7049 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7050 imul{l}\t{%2, %k0|%k0, %2}"
7051 [(set_attr "type" "imul")
7052 (set_attr "prefix_0f" "0,0,1")
7053 (set (attr "athlon_decode")
7054 (cond [(eq_attr "cpu" "athlon")
7055 (const_string "vector")
7056 (eq_attr "alternative" "1")
7057 (const_string "vector")
7058 (and (eq_attr "alternative" "2")
7059 (match_operand 1 "memory_operand" ""))
7060 (const_string "vector")]
7061 (const_string "direct")))
7062 (set_attr "mode" "SI")])
7064 (define_expand "mulhi3"
7065 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7066 (mult:HI (match_operand:HI 1 "register_operand" "")
7067 (match_operand:HI 2 "general_operand" "")))
7068 (clobber (reg:CC FLAGS_REG))])]
7069 "TARGET_HIMODE_MATH"
7072 (define_insn "*mulhi3_1"
7073 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7074 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7075 (match_operand:HI 2 "general_operand" "K,i,mr")))
7076 (clobber (reg:CC FLAGS_REG))]
7077 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7079 imul{w}\t{%2, %1, %0|%0, %1, %2}
7080 imul{w}\t{%2, %1, %0|%0, %1, %2}
7081 imul{w}\t{%2, %0|%0, %2}"
7082 [(set_attr "type" "imul")
7083 (set_attr "prefix_0f" "0,0,1")
7084 (set (attr "athlon_decode")
7085 (cond [(eq_attr "cpu" "athlon")
7086 (const_string "vector")
7087 (eq_attr "alternative" "1,2")
7088 (const_string "vector")]
7089 (const_string "direct")))
7090 (set_attr "mode" "HI")])
7092 (define_expand "mulqi3"
7093 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7094 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7095 (match_operand:QI 2 "register_operand" "")))
7096 (clobber (reg:CC FLAGS_REG))])]
7097 "TARGET_QIMODE_MATH"
7100 (define_insn "*mulqi3_1"
7101 [(set (match_operand:QI 0 "register_operand" "=a")
7102 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7103 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7104 (clobber (reg:CC FLAGS_REG))]
7106 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7108 [(set_attr "type" "imul")
7109 (set_attr "length_immediate" "0")
7110 (set (attr "athlon_decode")
7111 (if_then_else (eq_attr "cpu" "athlon")
7112 (const_string "vector")
7113 (const_string "direct")))
7114 (set_attr "mode" "QI")])
7116 (define_expand "umulqihi3"
7117 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7118 (mult:HI (zero_extend:HI
7119 (match_operand:QI 1 "nonimmediate_operand" ""))
7121 (match_operand:QI 2 "register_operand" ""))))
7122 (clobber (reg:CC FLAGS_REG))])]
7123 "TARGET_QIMODE_MATH"
7126 (define_insn "*umulqihi3_1"
7127 [(set (match_operand:HI 0 "register_operand" "=a")
7128 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7129 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7130 (clobber (reg:CC FLAGS_REG))]
7132 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7134 [(set_attr "type" "imul")
7135 (set_attr "length_immediate" "0")
7136 (set (attr "athlon_decode")
7137 (if_then_else (eq_attr "cpu" "athlon")
7138 (const_string "vector")
7139 (const_string "direct")))
7140 (set_attr "mode" "QI")])
7142 (define_expand "mulqihi3"
7143 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7144 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7145 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7146 (clobber (reg:CC FLAGS_REG))])]
7147 "TARGET_QIMODE_MATH"
7150 (define_insn "*mulqihi3_insn"
7151 [(set (match_operand:HI 0 "register_operand" "=a")
7152 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7153 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7154 (clobber (reg:CC FLAGS_REG))]
7156 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7158 [(set_attr "type" "imul")
7159 (set_attr "length_immediate" "0")
7160 (set (attr "athlon_decode")
7161 (if_then_else (eq_attr "cpu" "athlon")
7162 (const_string "vector")
7163 (const_string "direct")))
7164 (set_attr "mode" "QI")])
7166 (define_expand "umulditi3"
7167 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7168 (mult:TI (zero_extend:TI
7169 (match_operand:DI 1 "nonimmediate_operand" ""))
7171 (match_operand:DI 2 "register_operand" ""))))
7172 (clobber (reg:CC FLAGS_REG))])]
7176 (define_insn "*umulditi3_insn"
7177 [(set (match_operand:TI 0 "register_operand" "=A")
7178 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7179 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7180 (clobber (reg:CC FLAGS_REG))]
7182 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7184 [(set_attr "type" "imul")
7185 (set_attr "length_immediate" "0")
7186 (set (attr "athlon_decode")
7187 (if_then_else (eq_attr "cpu" "athlon")
7188 (const_string "vector")
7189 (const_string "double")))
7190 (set_attr "mode" "DI")])
7192 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7193 (define_expand "umulsidi3"
7194 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7195 (mult:DI (zero_extend:DI
7196 (match_operand:SI 1 "nonimmediate_operand" ""))
7198 (match_operand:SI 2 "register_operand" ""))))
7199 (clobber (reg:CC FLAGS_REG))])]
7203 (define_insn "*umulsidi3_insn"
7204 [(set (match_operand:DI 0 "register_operand" "=A")
7205 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7206 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7207 (clobber (reg:CC FLAGS_REG))]
7209 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7211 [(set_attr "type" "imul")
7212 (set_attr "length_immediate" "0")
7213 (set (attr "athlon_decode")
7214 (if_then_else (eq_attr "cpu" "athlon")
7215 (const_string "vector")
7216 (const_string "double")))
7217 (set_attr "mode" "SI")])
7219 (define_expand "mulditi3"
7220 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7221 (mult:TI (sign_extend:TI
7222 (match_operand:DI 1 "nonimmediate_operand" ""))
7224 (match_operand:DI 2 "register_operand" ""))))
7225 (clobber (reg:CC FLAGS_REG))])]
7229 (define_insn "*mulditi3_insn"
7230 [(set (match_operand:TI 0 "register_operand" "=A")
7231 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7232 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7233 (clobber (reg:CC FLAGS_REG))]
7235 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7237 [(set_attr "type" "imul")
7238 (set_attr "length_immediate" "0")
7239 (set (attr "athlon_decode")
7240 (if_then_else (eq_attr "cpu" "athlon")
7241 (const_string "vector")
7242 (const_string "double")))
7243 (set_attr "mode" "DI")])
7245 (define_expand "mulsidi3"
7246 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7247 (mult:DI (sign_extend:DI
7248 (match_operand:SI 1 "nonimmediate_operand" ""))
7250 (match_operand:SI 2 "register_operand" ""))))
7251 (clobber (reg:CC FLAGS_REG))])]
7255 (define_insn "*mulsidi3_insn"
7256 [(set (match_operand:DI 0 "register_operand" "=A")
7257 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7258 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7259 (clobber (reg:CC FLAGS_REG))]
7261 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7263 [(set_attr "type" "imul")
7264 (set_attr "length_immediate" "0")
7265 (set (attr "athlon_decode")
7266 (if_then_else (eq_attr "cpu" "athlon")
7267 (const_string "vector")
7268 (const_string "double")))
7269 (set_attr "mode" "SI")])
7271 (define_expand "umuldi3_highpart"
7272 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7275 (mult:TI (zero_extend:TI
7276 (match_operand:DI 1 "nonimmediate_operand" ""))
7278 (match_operand:DI 2 "register_operand" "")))
7280 (clobber (match_scratch:DI 3 ""))
7281 (clobber (reg:CC FLAGS_REG))])]
7285 (define_insn "*umuldi3_highpart_rex64"
7286 [(set (match_operand:DI 0 "register_operand" "=d")
7289 (mult:TI (zero_extend:TI
7290 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7292 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7294 (clobber (match_scratch:DI 3 "=1"))
7295 (clobber (reg:CC FLAGS_REG))]
7297 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7299 [(set_attr "type" "imul")
7300 (set_attr "length_immediate" "0")
7301 (set (attr "athlon_decode")
7302 (if_then_else (eq_attr "cpu" "athlon")
7303 (const_string "vector")
7304 (const_string "double")))
7305 (set_attr "mode" "DI")])
7307 (define_expand "umulsi3_highpart"
7308 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7311 (mult:DI (zero_extend:DI
7312 (match_operand:SI 1 "nonimmediate_operand" ""))
7314 (match_operand:SI 2 "register_operand" "")))
7316 (clobber (match_scratch:SI 3 ""))
7317 (clobber (reg:CC FLAGS_REG))])]
7321 (define_insn "*umulsi3_highpart_insn"
7322 [(set (match_operand:SI 0 "register_operand" "=d")
7325 (mult:DI (zero_extend:DI
7326 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7328 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7330 (clobber (match_scratch:SI 3 "=1"))
7331 (clobber (reg:CC FLAGS_REG))]
7332 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7334 [(set_attr "type" "imul")
7335 (set_attr "length_immediate" "0")
7336 (set (attr "athlon_decode")
7337 (if_then_else (eq_attr "cpu" "athlon")
7338 (const_string "vector")
7339 (const_string "double")))
7340 (set_attr "mode" "SI")])
7342 (define_insn "*umulsi3_highpart_zext"
7343 [(set (match_operand:DI 0 "register_operand" "=d")
7344 (zero_extend:DI (truncate:SI
7346 (mult:DI (zero_extend:DI
7347 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7349 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7351 (clobber (match_scratch:SI 3 "=1"))
7352 (clobber (reg:CC FLAGS_REG))]
7354 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7356 [(set_attr "type" "imul")
7357 (set_attr "length_immediate" "0")
7358 (set (attr "athlon_decode")
7359 (if_then_else (eq_attr "cpu" "athlon")
7360 (const_string "vector")
7361 (const_string "double")))
7362 (set_attr "mode" "SI")])
7364 (define_expand "smuldi3_highpart"
7365 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7368 (mult:TI (sign_extend:TI
7369 (match_operand:DI 1 "nonimmediate_operand" ""))
7371 (match_operand:DI 2 "register_operand" "")))
7373 (clobber (match_scratch:DI 3 ""))
7374 (clobber (reg:CC FLAGS_REG))])]
7378 (define_insn "*smuldi3_highpart_rex64"
7379 [(set (match_operand:DI 0 "register_operand" "=d")
7382 (mult:TI (sign_extend:TI
7383 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7385 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7387 (clobber (match_scratch:DI 3 "=1"))
7388 (clobber (reg:CC FLAGS_REG))]
7390 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7392 [(set_attr "type" "imul")
7393 (set (attr "athlon_decode")
7394 (if_then_else (eq_attr "cpu" "athlon")
7395 (const_string "vector")
7396 (const_string "double")))
7397 (set_attr "mode" "DI")])
7399 (define_expand "smulsi3_highpart"
7400 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7403 (mult:DI (sign_extend:DI
7404 (match_operand:SI 1 "nonimmediate_operand" ""))
7406 (match_operand:SI 2 "register_operand" "")))
7408 (clobber (match_scratch:SI 3 ""))
7409 (clobber (reg:CC FLAGS_REG))])]
7413 (define_insn "*smulsi3_highpart_insn"
7414 [(set (match_operand:SI 0 "register_operand" "=d")
7417 (mult:DI (sign_extend:DI
7418 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7420 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7422 (clobber (match_scratch:SI 3 "=1"))
7423 (clobber (reg:CC FLAGS_REG))]
7424 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7426 [(set_attr "type" "imul")
7427 (set (attr "athlon_decode")
7428 (if_then_else (eq_attr "cpu" "athlon")
7429 (const_string "vector")
7430 (const_string "double")))
7431 (set_attr "mode" "SI")])
7433 (define_insn "*smulsi3_highpart_zext"
7434 [(set (match_operand:DI 0 "register_operand" "=d")
7435 (zero_extend:DI (truncate:SI
7437 (mult:DI (sign_extend:DI
7438 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7440 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7442 (clobber (match_scratch:SI 3 "=1"))
7443 (clobber (reg:CC FLAGS_REG))]
7445 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7447 [(set_attr "type" "imul")
7448 (set (attr "athlon_decode")
7449 (if_then_else (eq_attr "cpu" "athlon")
7450 (const_string "vector")
7451 (const_string "double")))
7452 (set_attr "mode" "SI")])
7454 ;; The patterns that match these are at the end of this file.
7456 (define_expand "mulxf3"
7457 [(set (match_operand:XF 0 "register_operand" "")
7458 (mult:XF (match_operand:XF 1 "register_operand" "")
7459 (match_operand:XF 2 "register_operand" "")))]
7463 (define_expand "muldf3"
7464 [(set (match_operand:DF 0 "register_operand" "")
7465 (mult:DF (match_operand:DF 1 "register_operand" "")
7466 (match_operand:DF 2 "nonimmediate_operand" "")))]
7467 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7470 (define_expand "mulsf3"
7471 [(set (match_operand:SF 0 "register_operand" "")
7472 (mult:SF (match_operand:SF 1 "register_operand" "")
7473 (match_operand:SF 2 "nonimmediate_operand" "")))]
7474 "TARGET_80387 || TARGET_SSE_MATH"
7477 ;; Divide instructions
7479 (define_insn "divqi3"
7480 [(set (match_operand:QI 0 "register_operand" "=a")
7481 (div:QI (match_operand:HI 1 "register_operand" "0")
7482 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7483 (clobber (reg:CC FLAGS_REG))]
7484 "TARGET_QIMODE_MATH"
7486 [(set_attr "type" "idiv")
7487 (set_attr "mode" "QI")])
7489 (define_insn "udivqi3"
7490 [(set (match_operand:QI 0 "register_operand" "=a")
7491 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7492 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7493 (clobber (reg:CC FLAGS_REG))]
7494 "TARGET_QIMODE_MATH"
7496 [(set_attr "type" "idiv")
7497 (set_attr "mode" "QI")])
7499 ;; The patterns that match these are at the end of this file.
7501 (define_expand "divxf3"
7502 [(set (match_operand:XF 0 "register_operand" "")
7503 (div:XF (match_operand:XF 1 "register_operand" "")
7504 (match_operand:XF 2 "register_operand" "")))]
7508 (define_expand "divdf3"
7509 [(set (match_operand:DF 0 "register_operand" "")
7510 (div:DF (match_operand:DF 1 "register_operand" "")
7511 (match_operand:DF 2 "nonimmediate_operand" "")))]
7512 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7515 (define_expand "divsf3"
7516 [(set (match_operand:SF 0 "register_operand" "")
7517 (div:SF (match_operand:SF 1 "register_operand" "")
7518 (match_operand:SF 2 "nonimmediate_operand" "")))]
7519 "TARGET_80387 || TARGET_SSE_MATH"
7522 ;; Remainder instructions.
7524 (define_expand "divmoddi4"
7525 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7526 (div:DI (match_operand:DI 1 "register_operand" "")
7527 (match_operand:DI 2 "nonimmediate_operand" "")))
7528 (set (match_operand:DI 3 "register_operand" "")
7529 (mod:DI (match_dup 1) (match_dup 2)))
7530 (clobber (reg:CC FLAGS_REG))])]
7534 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7535 ;; Penalize eax case slightly because it results in worse scheduling
7537 (define_insn "*divmoddi4_nocltd_rex64"
7538 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7539 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7540 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7541 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7542 (mod:DI (match_dup 2) (match_dup 3)))
7543 (clobber (reg:CC FLAGS_REG))]
7544 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7546 [(set_attr "type" "multi")])
7548 (define_insn "*divmoddi4_cltd_rex64"
7549 [(set (match_operand:DI 0 "register_operand" "=a")
7550 (div:DI (match_operand:DI 2 "register_operand" "a")
7551 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7552 (set (match_operand:DI 1 "register_operand" "=&d")
7553 (mod:DI (match_dup 2) (match_dup 3)))
7554 (clobber (reg:CC FLAGS_REG))]
7555 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7557 [(set_attr "type" "multi")])
7559 (define_insn "*divmoddi_noext_rex64"
7560 [(set (match_operand:DI 0 "register_operand" "=a")
7561 (div:DI (match_operand:DI 1 "register_operand" "0")
7562 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7563 (set (match_operand:DI 3 "register_operand" "=d")
7564 (mod:DI (match_dup 1) (match_dup 2)))
7565 (use (match_operand:DI 4 "register_operand" "3"))
7566 (clobber (reg:CC FLAGS_REG))]
7569 [(set_attr "type" "idiv")
7570 (set_attr "mode" "DI")])
7573 [(set (match_operand:DI 0 "register_operand" "")
7574 (div:DI (match_operand:DI 1 "register_operand" "")
7575 (match_operand:DI 2 "nonimmediate_operand" "")))
7576 (set (match_operand:DI 3 "register_operand" "")
7577 (mod:DI (match_dup 1) (match_dup 2)))
7578 (clobber (reg:CC FLAGS_REG))]
7579 "TARGET_64BIT && reload_completed"
7580 [(parallel [(set (match_dup 3)
7581 (ashiftrt:DI (match_dup 4) (const_int 63)))
7582 (clobber (reg:CC FLAGS_REG))])
7583 (parallel [(set (match_dup 0)
7584 (div:DI (reg:DI 0) (match_dup 2)))
7586 (mod:DI (reg:DI 0) (match_dup 2)))
7588 (clobber (reg:CC FLAGS_REG))])]
7590 /* Avoid use of cltd in favor of a mov+shift. */
7591 if (!TARGET_USE_CLTD && !optimize_size)
7593 if (true_regnum (operands[1]))
7594 emit_move_insn (operands[0], operands[1]);
7596 emit_move_insn (operands[3], operands[1]);
7597 operands[4] = operands[3];
7601 if (true_regnum (operands[1]))
7603 operands[4] = operands[1];
7608 (define_expand "divmodsi4"
7609 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7610 (div:SI (match_operand:SI 1 "register_operand" "")
7611 (match_operand:SI 2 "nonimmediate_operand" "")))
7612 (set (match_operand:SI 3 "register_operand" "")
7613 (mod:SI (match_dup 1) (match_dup 2)))
7614 (clobber (reg:CC FLAGS_REG))])]
7618 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7619 ;; Penalize eax case slightly because it results in worse scheduling
7621 (define_insn "*divmodsi4_nocltd"
7622 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7623 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7624 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7625 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7626 (mod:SI (match_dup 2) (match_dup 3)))
7627 (clobber (reg:CC FLAGS_REG))]
7628 "!optimize_size && !TARGET_USE_CLTD"
7630 [(set_attr "type" "multi")])
7632 (define_insn "*divmodsi4_cltd"
7633 [(set (match_operand:SI 0 "register_operand" "=a")
7634 (div:SI (match_operand:SI 2 "register_operand" "a")
7635 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7636 (set (match_operand:SI 1 "register_operand" "=&d")
7637 (mod:SI (match_dup 2) (match_dup 3)))
7638 (clobber (reg:CC FLAGS_REG))]
7639 "optimize_size || TARGET_USE_CLTD"
7641 [(set_attr "type" "multi")])
7643 (define_insn "*divmodsi_noext"
7644 [(set (match_operand:SI 0 "register_operand" "=a")
7645 (div:SI (match_operand:SI 1 "register_operand" "0")
7646 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7647 (set (match_operand:SI 3 "register_operand" "=d")
7648 (mod:SI (match_dup 1) (match_dup 2)))
7649 (use (match_operand:SI 4 "register_operand" "3"))
7650 (clobber (reg:CC FLAGS_REG))]
7653 [(set_attr "type" "idiv")
7654 (set_attr "mode" "SI")])
7657 [(set (match_operand:SI 0 "register_operand" "")
7658 (div:SI (match_operand:SI 1 "register_operand" "")
7659 (match_operand:SI 2 "nonimmediate_operand" "")))
7660 (set (match_operand:SI 3 "register_operand" "")
7661 (mod:SI (match_dup 1) (match_dup 2)))
7662 (clobber (reg:CC FLAGS_REG))]
7664 [(parallel [(set (match_dup 3)
7665 (ashiftrt:SI (match_dup 4) (const_int 31)))
7666 (clobber (reg:CC FLAGS_REG))])
7667 (parallel [(set (match_dup 0)
7668 (div:SI (reg:SI 0) (match_dup 2)))
7670 (mod:SI (reg:SI 0) (match_dup 2)))
7672 (clobber (reg:CC FLAGS_REG))])]
7674 /* Avoid use of cltd in favor of a mov+shift. */
7675 if (!TARGET_USE_CLTD && !optimize_size)
7677 if (true_regnum (operands[1]))
7678 emit_move_insn (operands[0], operands[1]);
7680 emit_move_insn (operands[3], operands[1]);
7681 operands[4] = operands[3];
7685 if (true_regnum (operands[1]))
7687 operands[4] = operands[1];
7691 (define_insn "divmodhi4"
7692 [(set (match_operand:HI 0 "register_operand" "=a")
7693 (div:HI (match_operand:HI 1 "register_operand" "0")
7694 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7695 (set (match_operand:HI 3 "register_operand" "=&d")
7696 (mod:HI (match_dup 1) (match_dup 2)))
7697 (clobber (reg:CC FLAGS_REG))]
7698 "TARGET_HIMODE_MATH"
7700 [(set_attr "type" "multi")
7701 (set_attr "length_immediate" "0")
7702 (set_attr "mode" "SI")])
7704 (define_insn "udivmoddi4"
7705 [(set (match_operand:DI 0 "register_operand" "=a")
7706 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7707 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7708 (set (match_operand:DI 3 "register_operand" "=&d")
7709 (umod:DI (match_dup 1) (match_dup 2)))
7710 (clobber (reg:CC FLAGS_REG))]
7712 "xor{q}\t%3, %3\;div{q}\t%2"
7713 [(set_attr "type" "multi")
7714 (set_attr "length_immediate" "0")
7715 (set_attr "mode" "DI")])
7717 (define_insn "*udivmoddi4_noext"
7718 [(set (match_operand:DI 0 "register_operand" "=a")
7719 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7720 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7721 (set (match_operand:DI 3 "register_operand" "=d")
7722 (umod:DI (match_dup 1) (match_dup 2)))
7724 (clobber (reg:CC FLAGS_REG))]
7727 [(set_attr "type" "idiv")
7728 (set_attr "mode" "DI")])
7731 [(set (match_operand:DI 0 "register_operand" "")
7732 (udiv:DI (match_operand:DI 1 "register_operand" "")
7733 (match_operand:DI 2 "nonimmediate_operand" "")))
7734 (set (match_operand:DI 3 "register_operand" "")
7735 (umod:DI (match_dup 1) (match_dup 2)))
7736 (clobber (reg:CC FLAGS_REG))]
7737 "TARGET_64BIT && reload_completed"
7738 [(set (match_dup 3) (const_int 0))
7739 (parallel [(set (match_dup 0)
7740 (udiv:DI (match_dup 1) (match_dup 2)))
7742 (umod:DI (match_dup 1) (match_dup 2)))
7744 (clobber (reg:CC FLAGS_REG))])]
7747 (define_insn "udivmodsi4"
7748 [(set (match_operand:SI 0 "register_operand" "=a")
7749 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7750 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7751 (set (match_operand:SI 3 "register_operand" "=&d")
7752 (umod:SI (match_dup 1) (match_dup 2)))
7753 (clobber (reg:CC FLAGS_REG))]
7755 "xor{l}\t%3, %3\;div{l}\t%2"
7756 [(set_attr "type" "multi")
7757 (set_attr "length_immediate" "0")
7758 (set_attr "mode" "SI")])
7760 (define_insn "*udivmodsi4_noext"
7761 [(set (match_operand:SI 0 "register_operand" "=a")
7762 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7763 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7764 (set (match_operand:SI 3 "register_operand" "=d")
7765 (umod:SI (match_dup 1) (match_dup 2)))
7767 (clobber (reg:CC FLAGS_REG))]
7770 [(set_attr "type" "idiv")
7771 (set_attr "mode" "SI")])
7774 [(set (match_operand:SI 0 "register_operand" "")
7775 (udiv:SI (match_operand:SI 1 "register_operand" "")
7776 (match_operand:SI 2 "nonimmediate_operand" "")))
7777 (set (match_operand:SI 3 "register_operand" "")
7778 (umod:SI (match_dup 1) (match_dup 2)))
7779 (clobber (reg:CC FLAGS_REG))]
7781 [(set (match_dup 3) (const_int 0))
7782 (parallel [(set (match_dup 0)
7783 (udiv:SI (match_dup 1) (match_dup 2)))
7785 (umod:SI (match_dup 1) (match_dup 2)))
7787 (clobber (reg:CC FLAGS_REG))])]
7790 (define_expand "udivmodhi4"
7791 [(set (match_dup 4) (const_int 0))
7792 (parallel [(set (match_operand:HI 0 "register_operand" "")
7793 (udiv:HI (match_operand:HI 1 "register_operand" "")
7794 (match_operand:HI 2 "nonimmediate_operand" "")))
7795 (set (match_operand:HI 3 "register_operand" "")
7796 (umod:HI (match_dup 1) (match_dup 2)))
7798 (clobber (reg:CC FLAGS_REG))])]
7799 "TARGET_HIMODE_MATH"
7800 "operands[4] = gen_reg_rtx (HImode);")
7802 (define_insn "*udivmodhi_noext"
7803 [(set (match_operand:HI 0 "register_operand" "=a")
7804 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7805 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7806 (set (match_operand:HI 3 "register_operand" "=d")
7807 (umod:HI (match_dup 1) (match_dup 2)))
7808 (use (match_operand:HI 4 "register_operand" "3"))
7809 (clobber (reg:CC FLAGS_REG))]
7812 [(set_attr "type" "idiv")
7813 (set_attr "mode" "HI")])
7815 ;; We cannot use div/idiv for double division, because it causes
7816 ;; "division by zero" on the overflow and that's not what we expect
7817 ;; from truncate. Because true (non truncating) double division is
7818 ;; never generated, we can't create this insn anyway.
7821 ; [(set (match_operand:SI 0 "register_operand" "=a")
7823 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7825 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7826 ; (set (match_operand:SI 3 "register_operand" "=d")
7828 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7829 ; (clobber (reg:CC FLAGS_REG))]
7831 ; "div{l}\t{%2, %0|%0, %2}"
7832 ; [(set_attr "type" "idiv")])
7834 ;;- Logical AND instructions
7836 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7837 ;; Note that this excludes ah.
7839 (define_insn "*testdi_1_rex64"
7842 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7843 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7845 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7846 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7848 test{l}\t{%k1, %k0|%k0, %k1}
7849 test{l}\t{%k1, %k0|%k0, %k1}
7850 test{q}\t{%1, %0|%0, %1}
7851 test{q}\t{%1, %0|%0, %1}
7852 test{q}\t{%1, %0|%0, %1}"
7853 [(set_attr "type" "test")
7854 (set_attr "modrm" "0,1,0,1,1")
7855 (set_attr "mode" "SI,SI,DI,DI,DI")
7856 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7858 (define_insn "testsi_1"
7861 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
7862 (match_operand:SI 1 "general_operand" "in,in,rin"))
7864 "ix86_match_ccmode (insn, CCNOmode)
7865 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7866 "test{l}\t{%1, %0|%0, %1}"
7867 [(set_attr "type" "test")
7868 (set_attr "modrm" "0,1,1")
7869 (set_attr "mode" "SI")
7870 (set_attr "pent_pair" "uv,np,uv")])
7872 (define_expand "testsi_ccno_1"
7873 [(set (reg:CCNO FLAGS_REG)
7875 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7876 (match_operand:SI 1 "nonmemory_operand" ""))
7881 (define_insn "*testhi_1"
7883 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
7884 (match_operand:HI 1 "general_operand" "n,n,rn"))
7886 "ix86_match_ccmode (insn, CCNOmode)
7887 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7888 "test{w}\t{%1, %0|%0, %1}"
7889 [(set_attr "type" "test")
7890 (set_attr "modrm" "0,1,1")
7891 (set_attr "mode" "HI")
7892 (set_attr "pent_pair" "uv,np,uv")])
7894 (define_expand "testqi_ccz_1"
7895 [(set (reg:CCZ FLAGS_REG)
7896 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7897 (match_operand:QI 1 "nonmemory_operand" ""))
7902 (define_insn "*testqi_1"
7904 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7905 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7907 "ix86_match_ccmode (insn, CCNOmode)
7908 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7910 if (which_alternative == 3)
7912 if (GET_CODE (operands[1]) == CONST_INT
7913 && (INTVAL (operands[1]) & 0xffffff00))
7914 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7915 return "test{l}\t{%1, %k0|%k0, %1}";
7917 return "test{b}\t{%1, %0|%0, %1}";
7919 [(set_attr "type" "test")
7920 (set_attr "modrm" "0,1,1,1")
7921 (set_attr "mode" "QI,QI,QI,SI")
7922 (set_attr "pent_pair" "uv,np,uv,np")])
7924 (define_expand "testqi_ext_ccno_0"
7925 [(set (reg:CCNO FLAGS_REG)
7929 (match_operand 0 "ext_register_operand" "")
7932 (match_operand 1 "const_int_operand" ""))
7937 (define_insn "*testqi_ext_0"
7942 (match_operand 0 "ext_register_operand" "Q")
7945 (match_operand 1 "const_int_operand" "n"))
7947 "ix86_match_ccmode (insn, CCNOmode)"
7948 "test{b}\t{%1, %h0|%h0, %1}"
7949 [(set_attr "type" "test")
7950 (set_attr "mode" "QI")
7951 (set_attr "length_immediate" "1")
7952 (set_attr "pent_pair" "np")])
7954 (define_insn "*testqi_ext_1"
7959 (match_operand 0 "ext_register_operand" "Q")
7963 (match_operand:QI 1 "general_operand" "Qm")))
7965 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7966 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7967 "test{b}\t{%1, %h0|%h0, %1}"
7968 [(set_attr "type" "test")
7969 (set_attr "mode" "QI")])
7971 (define_insn "*testqi_ext_1_rex64"
7976 (match_operand 0 "ext_register_operand" "Q")
7980 (match_operand:QI 1 "register_operand" "Q")))
7982 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7983 "test{b}\t{%1, %h0|%h0, %1}"
7984 [(set_attr "type" "test")
7985 (set_attr "mode" "QI")])
7987 (define_insn "*testqi_ext_2"
7992 (match_operand 0 "ext_register_operand" "Q")
7996 (match_operand 1 "ext_register_operand" "Q")
8000 "ix86_match_ccmode (insn, CCNOmode)"
8001 "test{b}\t{%h1, %h0|%h0, %h1}"
8002 [(set_attr "type" "test")
8003 (set_attr "mode" "QI")])
8005 ;; Combine likes to form bit extractions for some tests. Humor it.
8006 (define_insn "*testqi_ext_3"
8008 (compare (zero_extract:SI
8009 (match_operand 0 "nonimmediate_operand" "rm")
8010 (match_operand:SI 1 "const_int_operand" "")
8011 (match_operand:SI 2 "const_int_operand" ""))
8013 "ix86_match_ccmode (insn, CCNOmode)
8014 && (GET_MODE (operands[0]) == SImode
8015 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8016 || GET_MODE (operands[0]) == HImode
8017 || GET_MODE (operands[0]) == QImode)"
8020 (define_insn "*testqi_ext_3_rex64"
8022 (compare (zero_extract:DI
8023 (match_operand 0 "nonimmediate_operand" "rm")
8024 (match_operand:DI 1 "const_int_operand" "")
8025 (match_operand:DI 2 "const_int_operand" ""))
8028 && ix86_match_ccmode (insn, CCNOmode)
8029 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8030 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8031 /* Ensure that resulting mask is zero or sign extended operand. */
8032 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8033 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8034 && INTVAL (operands[1]) > 32))
8035 && (GET_MODE (operands[0]) == SImode
8036 || GET_MODE (operands[0]) == DImode
8037 || GET_MODE (operands[0]) == HImode
8038 || GET_MODE (operands[0]) == QImode)"
8043 (compare (zero_extract
8044 (match_operand 0 "nonimmediate_operand" "")
8045 (match_operand 1 "const_int_operand" "")
8046 (match_operand 2 "const_int_operand" ""))
8048 "ix86_match_ccmode (insn, CCNOmode)"
8049 [(set (reg:CCNO FLAGS_REG) (compare:CCNO (match_dup 3) (const_int 0)))]
8051 HOST_WIDE_INT len = INTVAL (operands[1]);
8052 HOST_WIDE_INT pos = INTVAL (operands[2]);
8054 enum machine_mode mode, submode;
8056 mode = GET_MODE (operands[0]);
8057 if (GET_CODE (operands[0]) == MEM)
8059 /* ??? Combine likes to put non-volatile mem extractions in QImode
8060 no matter the size of the test. So find a mode that works. */
8061 if (! MEM_VOLATILE_P (operands[0]))
8063 mode = smallest_mode_for_size (pos + len, MODE_INT);
8064 operands[0] = adjust_address (operands[0], mode, 0);
8067 else if (GET_CODE (operands[0]) == SUBREG
8068 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8069 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8070 && pos + len <= GET_MODE_BITSIZE (submode))
8072 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8074 operands[0] = SUBREG_REG (operands[0]);
8076 else if (mode == HImode && pos + len <= 8)
8078 /* Small HImode tests can be converted to QImode. */
8080 operands[0] = gen_lowpart (QImode, operands[0]);
8083 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8084 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8086 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8089 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8090 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8091 ;; this is relatively important trick.
8092 ;; Do the conversion only post-reload to avoid limiting of the register class
8097 (and (match_operand 0 "register_operand" "")
8098 (match_operand 1 "const_int_operand" ""))
8101 && QI_REG_P (operands[0])
8102 && ((ix86_match_ccmode (insn, CCZmode)
8103 && !(INTVAL (operands[1]) & ~(255 << 8)))
8104 || (ix86_match_ccmode (insn, CCNOmode)
8105 && !(INTVAL (operands[1]) & ~(127 << 8))))
8106 && GET_MODE (operands[0]) != QImode"
8107 [(set (reg:CCNO FLAGS_REG)
8109 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8112 "operands[0] = gen_lowpart (SImode, operands[0]);
8113 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8118 (and (match_operand 0 "nonimmediate_operand" "")
8119 (match_operand 1 "const_int_operand" ""))
8122 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8123 && ((ix86_match_ccmode (insn, CCZmode)
8124 && !(INTVAL (operands[1]) & ~255))
8125 || (ix86_match_ccmode (insn, CCNOmode)
8126 && !(INTVAL (operands[1]) & ~127)))
8127 && GET_MODE (operands[0]) != QImode"
8128 [(set (reg:CCNO FLAGS_REG)
8130 (and:QI (match_dup 0)
8133 "operands[0] = gen_lowpart (QImode, operands[0]);
8134 operands[1] = gen_lowpart (QImode, operands[1]);")
8137 ;; %%% This used to optimize known byte-wide and operations to memory,
8138 ;; and sometimes to QImode registers. If this is considered useful,
8139 ;; it should be done with splitters.
8141 (define_expand "anddi3"
8142 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8143 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8144 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8145 (clobber (reg:CC FLAGS_REG))]
8147 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8149 (define_insn "*anddi_1_rex64"
8150 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8151 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8152 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8153 (clobber (reg:CC FLAGS_REG))]
8154 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8156 switch (get_attr_type (insn))
8160 enum machine_mode mode;
8162 if (GET_CODE (operands[2]) != CONST_INT)
8164 if (INTVAL (operands[2]) == 0xff)
8166 else if (INTVAL (operands[2]) == 0xffff)
8171 operands[1] = gen_lowpart (mode, operands[1]);
8173 return "movz{bq|x}\t{%1,%0|%0, %1}";
8175 return "movz{wq|x}\t{%1,%0|%0, %1}";
8179 if (! rtx_equal_p (operands[0], operands[1]))
8181 if (get_attr_mode (insn) == MODE_SI)
8182 return "and{l}\t{%k2, %k0|%k0, %k2}";
8184 return "and{q}\t{%2, %0|%0, %2}";
8187 [(set_attr "type" "alu,alu,alu,imovx")
8188 (set_attr "length_immediate" "*,*,*,0")
8189 (set_attr "mode" "SI,DI,DI,DI")])
8191 (define_insn "*anddi_2"
8193 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8194 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8196 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8197 (and:DI (match_dup 1) (match_dup 2)))]
8198 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8199 && ix86_binary_operator_ok (AND, DImode, operands)"
8201 and{l}\t{%k2, %k0|%k0, %k2}
8202 and{q}\t{%2, %0|%0, %2}
8203 and{q}\t{%2, %0|%0, %2}"
8204 [(set_attr "type" "alu")
8205 (set_attr "mode" "SI,DI,DI")])
8207 (define_expand "andsi3"
8208 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8209 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8210 (match_operand:SI 2 "general_operand" "")))
8211 (clobber (reg:CC FLAGS_REG))]
8213 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8215 (define_insn "*andsi_1"
8216 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8217 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8218 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8219 (clobber (reg:CC FLAGS_REG))]
8220 "ix86_binary_operator_ok (AND, SImode, operands)"
8222 switch (get_attr_type (insn))
8226 enum machine_mode mode;
8228 if (GET_CODE (operands[2]) != CONST_INT)
8230 if (INTVAL (operands[2]) == 0xff)
8232 else if (INTVAL (operands[2]) == 0xffff)
8237 operands[1] = gen_lowpart (mode, operands[1]);
8239 return "movz{bl|x}\t{%1,%0|%0, %1}";
8241 return "movz{wl|x}\t{%1,%0|%0, %1}";
8245 if (! rtx_equal_p (operands[0], operands[1]))
8247 return "and{l}\t{%2, %0|%0, %2}";
8250 [(set_attr "type" "alu,alu,imovx")
8251 (set_attr "length_immediate" "*,*,0")
8252 (set_attr "mode" "SI")])
8255 [(set (match_operand 0 "register_operand" "")
8257 (const_int -65536)))
8258 (clobber (reg:CC FLAGS_REG))]
8259 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8260 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8261 "operands[1] = gen_lowpart (HImode, operands[0]);")
8264 [(set (match_operand 0 "ext_register_operand" "")
8267 (clobber (reg:CC FLAGS_REG))]
8268 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8269 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8270 "operands[1] = gen_lowpart (QImode, operands[0]);")
8273 [(set (match_operand 0 "ext_register_operand" "")
8275 (const_int -65281)))
8276 (clobber (reg:CC FLAGS_REG))]
8277 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8278 [(parallel [(set (zero_extract:SI (match_dup 0)
8282 (zero_extract:SI (match_dup 0)
8285 (zero_extract:SI (match_dup 0)
8288 (clobber (reg:CC FLAGS_REG))])]
8289 "operands[0] = gen_lowpart (SImode, operands[0]);")
8291 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8292 (define_insn "*andsi_1_zext"
8293 [(set (match_operand:DI 0 "register_operand" "=r")
8295 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8296 (match_operand:SI 2 "general_operand" "rim"))))
8297 (clobber (reg:CC FLAGS_REG))]
8298 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8299 "and{l}\t{%2, %k0|%k0, %2}"
8300 [(set_attr "type" "alu")
8301 (set_attr "mode" "SI")])
8303 (define_insn "*andsi_2"
8305 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8306 (match_operand:SI 2 "general_operand" "rim,ri"))
8308 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8309 (and:SI (match_dup 1) (match_dup 2)))]
8310 "ix86_match_ccmode (insn, CCNOmode)
8311 && ix86_binary_operator_ok (AND, SImode, operands)"
8312 "and{l}\t{%2, %0|%0, %2}"
8313 [(set_attr "type" "alu")
8314 (set_attr "mode" "SI")])
8316 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8317 (define_insn "*andsi_2_zext"
8319 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8320 (match_operand:SI 2 "general_operand" "rim"))
8322 (set (match_operand:DI 0 "register_operand" "=r")
8323 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8324 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8325 && ix86_binary_operator_ok (AND, SImode, operands)"
8326 "and{l}\t{%2, %k0|%k0, %2}"
8327 [(set_attr "type" "alu")
8328 (set_attr "mode" "SI")])
8330 (define_expand "andhi3"
8331 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8332 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8333 (match_operand:HI 2 "general_operand" "")))
8334 (clobber (reg:CC FLAGS_REG))]
8335 "TARGET_HIMODE_MATH"
8336 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8338 (define_insn "*andhi_1"
8339 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8340 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8341 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8342 (clobber (reg:CC FLAGS_REG))]
8343 "ix86_binary_operator_ok (AND, HImode, operands)"
8345 switch (get_attr_type (insn))
8348 if (GET_CODE (operands[2]) != CONST_INT)
8350 if (INTVAL (operands[2]) == 0xff)
8351 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8355 if (! rtx_equal_p (operands[0], operands[1]))
8358 return "and{w}\t{%2, %0|%0, %2}";
8361 [(set_attr "type" "alu,alu,imovx")
8362 (set_attr "length_immediate" "*,*,0")
8363 (set_attr "mode" "HI,HI,SI")])
8365 (define_insn "*andhi_2"
8367 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8368 (match_operand:HI 2 "general_operand" "rim,ri"))
8370 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8371 (and:HI (match_dup 1) (match_dup 2)))]
8372 "ix86_match_ccmode (insn, CCNOmode)
8373 && ix86_binary_operator_ok (AND, HImode, operands)"
8374 "and{w}\t{%2, %0|%0, %2}"
8375 [(set_attr "type" "alu")
8376 (set_attr "mode" "HI")])
8378 (define_expand "andqi3"
8379 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8380 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8381 (match_operand:QI 2 "general_operand" "")))
8382 (clobber (reg:CC FLAGS_REG))]
8383 "TARGET_QIMODE_MATH"
8384 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8386 ;; %%% Potential partial reg stall on alternative 2. What to do?
8387 (define_insn "*andqi_1"
8388 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8389 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8390 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8391 (clobber (reg:CC FLAGS_REG))]
8392 "ix86_binary_operator_ok (AND, QImode, operands)"
8394 and{b}\t{%2, %0|%0, %2}
8395 and{b}\t{%2, %0|%0, %2}
8396 and{l}\t{%k2, %k0|%k0, %k2}"
8397 [(set_attr "type" "alu")
8398 (set_attr "mode" "QI,QI,SI")])
8400 (define_insn "*andqi_1_slp"
8401 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8402 (and:QI (match_dup 0)
8403 (match_operand:QI 1 "general_operand" "qi,qmi")))
8404 (clobber (reg:CC FLAGS_REG))]
8405 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8406 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8407 "and{b}\t{%1, %0|%0, %1}"
8408 [(set_attr "type" "alu1")
8409 (set_attr "mode" "QI")])
8411 (define_insn "*andqi_2"
8414 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8415 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8417 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8418 (and:QI (match_dup 1) (match_dup 2)))]
8419 "ix86_match_ccmode (insn, CCNOmode)
8420 && ix86_binary_operator_ok (AND, QImode, operands)"
8422 if (which_alternative == 2)
8424 if (GET_CODE (operands[2]) == CONST_INT
8425 && (INTVAL (operands[2]) & 0xffffff00))
8426 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8427 return "and{l}\t{%2, %k0|%k0, %2}";
8429 return "and{b}\t{%2, %0|%0, %2}";
8431 [(set_attr "type" "alu")
8432 (set_attr "mode" "QI,QI,SI")])
8434 (define_insn "*andqi_2_slp"
8437 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8438 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8440 (set (strict_low_part (match_dup 0))
8441 (and:QI (match_dup 0) (match_dup 1)))]
8442 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8443 && ix86_match_ccmode (insn, CCNOmode)
8444 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8445 "and{b}\t{%1, %0|%0, %1}"
8446 [(set_attr "type" "alu1")
8447 (set_attr "mode" "QI")])
8449 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8450 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8451 ;; for a QImode operand, which of course failed.
8453 (define_insn "andqi_ext_0"
8454 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8459 (match_operand 1 "ext_register_operand" "0")
8462 (match_operand 2 "const_int_operand" "n")))
8463 (clobber (reg:CC FLAGS_REG))]
8465 "and{b}\t{%2, %h0|%h0, %2}"
8466 [(set_attr "type" "alu")
8467 (set_attr "length_immediate" "1")
8468 (set_attr "mode" "QI")])
8470 ;; Generated by peephole translating test to and. This shows up
8471 ;; often in fp comparisons.
8473 (define_insn "*andqi_ext_0_cc"
8478 (match_operand 1 "ext_register_operand" "0")
8481 (match_operand 2 "const_int_operand" "n"))
8483 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8492 "ix86_match_ccmode (insn, CCNOmode)"
8493 "and{b}\t{%2, %h0|%h0, %2}"
8494 [(set_attr "type" "alu")
8495 (set_attr "length_immediate" "1")
8496 (set_attr "mode" "QI")])
8498 (define_insn "*andqi_ext_1"
8499 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8504 (match_operand 1 "ext_register_operand" "0")
8508 (match_operand:QI 2 "general_operand" "Qm"))))
8509 (clobber (reg:CC FLAGS_REG))]
8511 "and{b}\t{%2, %h0|%h0, %2}"
8512 [(set_attr "type" "alu")
8513 (set_attr "length_immediate" "0")
8514 (set_attr "mode" "QI")])
8516 (define_insn "*andqi_ext_1_rex64"
8517 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8522 (match_operand 1 "ext_register_operand" "0")
8526 (match_operand 2 "ext_register_operand" "Q"))))
8527 (clobber (reg:CC FLAGS_REG))]
8529 "and{b}\t{%2, %h0|%h0, %2}"
8530 [(set_attr "type" "alu")
8531 (set_attr "length_immediate" "0")
8532 (set_attr "mode" "QI")])
8534 (define_insn "*andqi_ext_2"
8535 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8540 (match_operand 1 "ext_register_operand" "%0")
8544 (match_operand 2 "ext_register_operand" "Q")
8547 (clobber (reg:CC FLAGS_REG))]
8549 "and{b}\t{%h2, %h0|%h0, %h2}"
8550 [(set_attr "type" "alu")
8551 (set_attr "length_immediate" "0")
8552 (set_attr "mode" "QI")])
8554 ;; Convert wide AND instructions with immediate operand to shorter QImode
8555 ;; equivalents when possible.
8556 ;; Don't do the splitting with memory operands, since it introduces risk
8557 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8558 ;; for size, but that can (should?) be handled by generic code instead.
8560 [(set (match_operand 0 "register_operand" "")
8561 (and (match_operand 1 "register_operand" "")
8562 (match_operand 2 "const_int_operand" "")))
8563 (clobber (reg:CC FLAGS_REG))]
8565 && QI_REG_P (operands[0])
8566 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8567 && !(~INTVAL (operands[2]) & ~(255 << 8))
8568 && GET_MODE (operands[0]) != QImode"
8569 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8570 (and:SI (zero_extract:SI (match_dup 1)
8571 (const_int 8) (const_int 8))
8573 (clobber (reg:CC FLAGS_REG))])]
8574 "operands[0] = gen_lowpart (SImode, operands[0]);
8575 operands[1] = gen_lowpart (SImode, operands[1]);
8576 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8578 ;; Since AND can be encoded with sign extended immediate, this is only
8579 ;; profitable when 7th bit is not set.
8581 [(set (match_operand 0 "register_operand" "")
8582 (and (match_operand 1 "general_operand" "")
8583 (match_operand 2 "const_int_operand" "")))
8584 (clobber (reg:CC FLAGS_REG))]
8586 && ANY_QI_REG_P (operands[0])
8587 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8588 && !(~INTVAL (operands[2]) & ~255)
8589 && !(INTVAL (operands[2]) & 128)
8590 && GET_MODE (operands[0]) != QImode"
8591 [(parallel [(set (strict_low_part (match_dup 0))
8592 (and:QI (match_dup 1)
8594 (clobber (reg:CC FLAGS_REG))])]
8595 "operands[0] = gen_lowpart (QImode, operands[0]);
8596 operands[1] = gen_lowpart (QImode, operands[1]);
8597 operands[2] = gen_lowpart (QImode, operands[2]);")
8599 ;; Logical inclusive OR instructions
8601 ;; %%% This used to optimize known byte-wide and operations to memory.
8602 ;; If this is considered useful, it should be done with splitters.
8604 (define_expand "iordi3"
8605 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8606 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8607 (match_operand:DI 2 "x86_64_general_operand" "")))
8608 (clobber (reg:CC FLAGS_REG))]
8610 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8612 (define_insn "*iordi_1_rex64"
8613 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8614 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8615 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8616 (clobber (reg:CC FLAGS_REG))]
8618 && ix86_binary_operator_ok (IOR, DImode, operands)"
8619 "or{q}\t{%2, %0|%0, %2}"
8620 [(set_attr "type" "alu")
8621 (set_attr "mode" "DI")])
8623 (define_insn "*iordi_2_rex64"
8625 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8626 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8628 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8629 (ior:DI (match_dup 1) (match_dup 2)))]
8631 && ix86_match_ccmode (insn, CCNOmode)
8632 && ix86_binary_operator_ok (IOR, DImode, operands)"
8633 "or{q}\t{%2, %0|%0, %2}"
8634 [(set_attr "type" "alu")
8635 (set_attr "mode" "DI")])
8637 (define_insn "*iordi_3_rex64"
8639 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8640 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8642 (clobber (match_scratch:DI 0 "=r"))]
8644 && ix86_match_ccmode (insn, CCNOmode)
8645 && ix86_binary_operator_ok (IOR, DImode, operands)"
8646 "or{q}\t{%2, %0|%0, %2}"
8647 [(set_attr "type" "alu")
8648 (set_attr "mode" "DI")])
8651 (define_expand "iorsi3"
8652 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8653 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8654 (match_operand:SI 2 "general_operand" "")))
8655 (clobber (reg:CC FLAGS_REG))]
8657 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8659 (define_insn "*iorsi_1"
8660 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8661 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8662 (match_operand:SI 2 "general_operand" "ri,rmi")))
8663 (clobber (reg:CC FLAGS_REG))]
8664 "ix86_binary_operator_ok (IOR, SImode, operands)"
8665 "or{l}\t{%2, %0|%0, %2}"
8666 [(set_attr "type" "alu")
8667 (set_attr "mode" "SI")])
8669 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8670 (define_insn "*iorsi_1_zext"
8671 [(set (match_operand:DI 0 "register_operand" "=rm")
8673 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8674 (match_operand:SI 2 "general_operand" "rim"))))
8675 (clobber (reg:CC FLAGS_REG))]
8676 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8677 "or{l}\t{%2, %k0|%k0, %2}"
8678 [(set_attr "type" "alu")
8679 (set_attr "mode" "SI")])
8681 (define_insn "*iorsi_1_zext_imm"
8682 [(set (match_operand:DI 0 "register_operand" "=rm")
8683 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8684 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8685 (clobber (reg:CC FLAGS_REG))]
8687 "or{l}\t{%2, %k0|%k0, %2}"
8688 [(set_attr "type" "alu")
8689 (set_attr "mode" "SI")])
8691 (define_insn "*iorsi_2"
8693 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8694 (match_operand:SI 2 "general_operand" "rim,ri"))
8696 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8697 (ior:SI (match_dup 1) (match_dup 2)))]
8698 "ix86_match_ccmode (insn, CCNOmode)
8699 && ix86_binary_operator_ok (IOR, SImode, operands)"
8700 "or{l}\t{%2, %0|%0, %2}"
8701 [(set_attr "type" "alu")
8702 (set_attr "mode" "SI")])
8704 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8705 ;; ??? Special case for immediate operand is missing - it is tricky.
8706 (define_insn "*iorsi_2_zext"
8708 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8709 (match_operand:SI 2 "general_operand" "rim"))
8711 (set (match_operand:DI 0 "register_operand" "=r")
8712 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8713 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8714 && ix86_binary_operator_ok (IOR, SImode, operands)"
8715 "or{l}\t{%2, %k0|%k0, %2}"
8716 [(set_attr "type" "alu")
8717 (set_attr "mode" "SI")])
8719 (define_insn "*iorsi_2_zext_imm"
8721 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8722 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8724 (set (match_operand:DI 0 "register_operand" "=r")
8725 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8726 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8727 && ix86_binary_operator_ok (IOR, SImode, operands)"
8728 "or{l}\t{%2, %k0|%k0, %2}"
8729 [(set_attr "type" "alu")
8730 (set_attr "mode" "SI")])
8732 (define_insn "*iorsi_3"
8734 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8735 (match_operand:SI 2 "general_operand" "rim"))
8737 (clobber (match_scratch:SI 0 "=r"))]
8738 "ix86_match_ccmode (insn, CCNOmode)
8739 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8740 "or{l}\t{%2, %0|%0, %2}"
8741 [(set_attr "type" "alu")
8742 (set_attr "mode" "SI")])
8744 (define_expand "iorhi3"
8745 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8746 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8747 (match_operand:HI 2 "general_operand" "")))
8748 (clobber (reg:CC FLAGS_REG))]
8749 "TARGET_HIMODE_MATH"
8750 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8752 (define_insn "*iorhi_1"
8753 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8754 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8755 (match_operand:HI 2 "general_operand" "rmi,ri")))
8756 (clobber (reg:CC FLAGS_REG))]
8757 "ix86_binary_operator_ok (IOR, HImode, operands)"
8758 "or{w}\t{%2, %0|%0, %2}"
8759 [(set_attr "type" "alu")
8760 (set_attr "mode" "HI")])
8762 (define_insn "*iorhi_2"
8764 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8765 (match_operand:HI 2 "general_operand" "rim,ri"))
8767 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8768 (ior:HI (match_dup 1) (match_dup 2)))]
8769 "ix86_match_ccmode (insn, CCNOmode)
8770 && ix86_binary_operator_ok (IOR, HImode, operands)"
8771 "or{w}\t{%2, %0|%0, %2}"
8772 [(set_attr "type" "alu")
8773 (set_attr "mode" "HI")])
8775 (define_insn "*iorhi_3"
8777 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8778 (match_operand:HI 2 "general_operand" "rim"))
8780 (clobber (match_scratch:HI 0 "=r"))]
8781 "ix86_match_ccmode (insn, CCNOmode)
8782 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8783 "or{w}\t{%2, %0|%0, %2}"
8784 [(set_attr "type" "alu")
8785 (set_attr "mode" "HI")])
8787 (define_expand "iorqi3"
8788 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8789 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8790 (match_operand:QI 2 "general_operand" "")))
8791 (clobber (reg:CC FLAGS_REG))]
8792 "TARGET_QIMODE_MATH"
8793 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8795 ;; %%% Potential partial reg stall on alternative 2. What to do?
8796 (define_insn "*iorqi_1"
8797 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8798 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8799 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8800 (clobber (reg:CC FLAGS_REG))]
8801 "ix86_binary_operator_ok (IOR, QImode, operands)"
8803 or{b}\t{%2, %0|%0, %2}
8804 or{b}\t{%2, %0|%0, %2}
8805 or{l}\t{%k2, %k0|%k0, %k2}"
8806 [(set_attr "type" "alu")
8807 (set_attr "mode" "QI,QI,SI")])
8809 (define_insn "*iorqi_1_slp"
8810 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8811 (ior:QI (match_dup 0)
8812 (match_operand:QI 1 "general_operand" "qmi,qi")))
8813 (clobber (reg:CC FLAGS_REG))]
8814 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8815 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8816 "or{b}\t{%1, %0|%0, %1}"
8817 [(set_attr "type" "alu1")
8818 (set_attr "mode" "QI")])
8820 (define_insn "*iorqi_2"
8822 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8823 (match_operand:QI 2 "general_operand" "qim,qi"))
8825 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8826 (ior:QI (match_dup 1) (match_dup 2)))]
8827 "ix86_match_ccmode (insn, CCNOmode)
8828 && ix86_binary_operator_ok (IOR, QImode, operands)"
8829 "or{b}\t{%2, %0|%0, %2}"
8830 [(set_attr "type" "alu")
8831 (set_attr "mode" "QI")])
8833 (define_insn "*iorqi_2_slp"
8835 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8836 (match_operand:QI 1 "general_operand" "qim,qi"))
8838 (set (strict_low_part (match_dup 0))
8839 (ior:QI (match_dup 0) (match_dup 1)))]
8840 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8841 && ix86_match_ccmode (insn, CCNOmode)
8842 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8843 "or{b}\t{%1, %0|%0, %1}"
8844 [(set_attr "type" "alu1")
8845 (set_attr "mode" "QI")])
8847 (define_insn "*iorqi_3"
8849 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8850 (match_operand:QI 2 "general_operand" "qim"))
8852 (clobber (match_scratch:QI 0 "=q"))]
8853 "ix86_match_ccmode (insn, CCNOmode)
8854 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8855 "or{b}\t{%2, %0|%0, %2}"
8856 [(set_attr "type" "alu")
8857 (set_attr "mode" "QI")])
8859 (define_insn "iorqi_ext_0"
8860 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8865 (match_operand 1 "ext_register_operand" "0")
8868 (match_operand 2 "const_int_operand" "n")))
8869 (clobber (reg:CC FLAGS_REG))]
8870 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8871 "or{b}\t{%2, %h0|%h0, %2}"
8872 [(set_attr "type" "alu")
8873 (set_attr "length_immediate" "1")
8874 (set_attr "mode" "QI")])
8876 (define_insn "*iorqi_ext_1"
8877 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8882 (match_operand 1 "ext_register_operand" "0")
8886 (match_operand:QI 2 "general_operand" "Qm"))))
8887 (clobber (reg:CC FLAGS_REG))]
8889 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8890 "or{b}\t{%2, %h0|%h0, %2}"
8891 [(set_attr "type" "alu")
8892 (set_attr "length_immediate" "0")
8893 (set_attr "mode" "QI")])
8895 (define_insn "*iorqi_ext_1_rex64"
8896 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8901 (match_operand 1 "ext_register_operand" "0")
8905 (match_operand 2 "ext_register_operand" "Q"))))
8906 (clobber (reg:CC FLAGS_REG))]
8908 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8909 "or{b}\t{%2, %h0|%h0, %2}"
8910 [(set_attr "type" "alu")
8911 (set_attr "length_immediate" "0")
8912 (set_attr "mode" "QI")])
8914 (define_insn "*iorqi_ext_2"
8915 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8919 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8922 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8925 (clobber (reg:CC FLAGS_REG))]
8926 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8927 "ior{b}\t{%h2, %h0|%h0, %h2}"
8928 [(set_attr "type" "alu")
8929 (set_attr "length_immediate" "0")
8930 (set_attr "mode" "QI")])
8933 [(set (match_operand 0 "register_operand" "")
8934 (ior (match_operand 1 "register_operand" "")
8935 (match_operand 2 "const_int_operand" "")))
8936 (clobber (reg:CC FLAGS_REG))]
8938 && QI_REG_P (operands[0])
8939 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8940 && !(INTVAL (operands[2]) & ~(255 << 8))
8941 && GET_MODE (operands[0]) != QImode"
8942 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8943 (ior:SI (zero_extract:SI (match_dup 1)
8944 (const_int 8) (const_int 8))
8946 (clobber (reg:CC FLAGS_REG))])]
8947 "operands[0] = gen_lowpart (SImode, operands[0]);
8948 operands[1] = gen_lowpart (SImode, operands[1]);
8949 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8951 ;; Since OR can be encoded with sign extended immediate, this is only
8952 ;; profitable when 7th bit is set.
8954 [(set (match_operand 0 "register_operand" "")
8955 (ior (match_operand 1 "general_operand" "")
8956 (match_operand 2 "const_int_operand" "")))
8957 (clobber (reg:CC FLAGS_REG))]
8959 && ANY_QI_REG_P (operands[0])
8960 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8961 && !(INTVAL (operands[2]) & ~255)
8962 && (INTVAL (operands[2]) & 128)
8963 && GET_MODE (operands[0]) != QImode"
8964 [(parallel [(set (strict_low_part (match_dup 0))
8965 (ior:QI (match_dup 1)
8967 (clobber (reg:CC FLAGS_REG))])]
8968 "operands[0] = gen_lowpart (QImode, operands[0]);
8969 operands[1] = gen_lowpart (QImode, operands[1]);
8970 operands[2] = gen_lowpart (QImode, operands[2]);")
8972 ;; Logical XOR instructions
8974 ;; %%% This used to optimize known byte-wide and operations to memory.
8975 ;; If this is considered useful, it should be done with splitters.
8977 (define_expand "xordi3"
8978 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8979 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8980 (match_operand:DI 2 "x86_64_general_operand" "")))
8981 (clobber (reg:CC FLAGS_REG))]
8983 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8985 (define_insn "*xordi_1_rex64"
8986 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8987 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8988 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8989 (clobber (reg:CC FLAGS_REG))]
8991 && ix86_binary_operator_ok (XOR, DImode, operands)"
8993 xor{q}\t{%2, %0|%0, %2}
8994 xor{q}\t{%2, %0|%0, %2}"
8995 [(set_attr "type" "alu")
8996 (set_attr "mode" "DI,DI")])
8998 (define_insn "*xordi_2_rex64"
9000 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9001 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9003 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9004 (xor:DI (match_dup 1) (match_dup 2)))]
9006 && ix86_match_ccmode (insn, CCNOmode)
9007 && ix86_binary_operator_ok (XOR, DImode, operands)"
9009 xor{q}\t{%2, %0|%0, %2}
9010 xor{q}\t{%2, %0|%0, %2}"
9011 [(set_attr "type" "alu")
9012 (set_attr "mode" "DI,DI")])
9014 (define_insn "*xordi_3_rex64"
9016 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9017 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9019 (clobber (match_scratch:DI 0 "=r"))]
9021 && ix86_match_ccmode (insn, CCNOmode)
9022 && ix86_binary_operator_ok (XOR, DImode, operands)"
9023 "xor{q}\t{%2, %0|%0, %2}"
9024 [(set_attr "type" "alu")
9025 (set_attr "mode" "DI")])
9027 (define_expand "xorsi3"
9028 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9029 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9030 (match_operand:SI 2 "general_operand" "")))
9031 (clobber (reg:CC FLAGS_REG))]
9033 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9035 (define_insn "*xorsi_1"
9036 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9037 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9038 (match_operand:SI 2 "general_operand" "ri,rm")))
9039 (clobber (reg:CC FLAGS_REG))]
9040 "ix86_binary_operator_ok (XOR, SImode, operands)"
9041 "xor{l}\t{%2, %0|%0, %2}"
9042 [(set_attr "type" "alu")
9043 (set_attr "mode" "SI")])
9045 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9046 ;; Add speccase for immediates
9047 (define_insn "*xorsi_1_zext"
9048 [(set (match_operand:DI 0 "register_operand" "=r")
9050 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9051 (match_operand:SI 2 "general_operand" "rim"))))
9052 (clobber (reg:CC FLAGS_REG))]
9053 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9054 "xor{l}\t{%2, %k0|%k0, %2}"
9055 [(set_attr "type" "alu")
9056 (set_attr "mode" "SI")])
9058 (define_insn "*xorsi_1_zext_imm"
9059 [(set (match_operand:DI 0 "register_operand" "=r")
9060 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9061 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9062 (clobber (reg:CC FLAGS_REG))]
9063 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9064 "xor{l}\t{%2, %k0|%k0, %2}"
9065 [(set_attr "type" "alu")
9066 (set_attr "mode" "SI")])
9068 (define_insn "*xorsi_2"
9070 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9071 (match_operand:SI 2 "general_operand" "rim,ri"))
9073 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9074 (xor:SI (match_dup 1) (match_dup 2)))]
9075 "ix86_match_ccmode (insn, CCNOmode)
9076 && ix86_binary_operator_ok (XOR, SImode, operands)"
9077 "xor{l}\t{%2, %0|%0, %2}"
9078 [(set_attr "type" "alu")
9079 (set_attr "mode" "SI")])
9081 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9082 ;; ??? Special case for immediate operand is missing - it is tricky.
9083 (define_insn "*xorsi_2_zext"
9085 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9086 (match_operand:SI 2 "general_operand" "rim"))
9088 (set (match_operand:DI 0 "register_operand" "=r")
9089 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9090 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9091 && ix86_binary_operator_ok (XOR, SImode, operands)"
9092 "xor{l}\t{%2, %k0|%k0, %2}"
9093 [(set_attr "type" "alu")
9094 (set_attr "mode" "SI")])
9096 (define_insn "*xorsi_2_zext_imm"
9098 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9099 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9101 (set (match_operand:DI 0 "register_operand" "=r")
9102 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9103 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9104 && ix86_binary_operator_ok (XOR, SImode, operands)"
9105 "xor{l}\t{%2, %k0|%k0, %2}"
9106 [(set_attr "type" "alu")
9107 (set_attr "mode" "SI")])
9109 (define_insn "*xorsi_3"
9111 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9112 (match_operand:SI 2 "general_operand" "rim"))
9114 (clobber (match_scratch:SI 0 "=r"))]
9115 "ix86_match_ccmode (insn, CCNOmode)
9116 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9117 "xor{l}\t{%2, %0|%0, %2}"
9118 [(set_attr "type" "alu")
9119 (set_attr "mode" "SI")])
9121 (define_expand "xorhi3"
9122 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9123 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9124 (match_operand:HI 2 "general_operand" "")))
9125 (clobber (reg:CC FLAGS_REG))]
9126 "TARGET_HIMODE_MATH"
9127 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9129 (define_insn "*xorhi_1"
9130 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9131 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9132 (match_operand:HI 2 "general_operand" "rmi,ri")))
9133 (clobber (reg:CC FLAGS_REG))]
9134 "ix86_binary_operator_ok (XOR, HImode, operands)"
9135 "xor{w}\t{%2, %0|%0, %2}"
9136 [(set_attr "type" "alu")
9137 (set_attr "mode" "HI")])
9139 (define_insn "*xorhi_2"
9141 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9142 (match_operand:HI 2 "general_operand" "rim,ri"))
9144 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9145 (xor:HI (match_dup 1) (match_dup 2)))]
9146 "ix86_match_ccmode (insn, CCNOmode)
9147 && ix86_binary_operator_ok (XOR, HImode, operands)"
9148 "xor{w}\t{%2, %0|%0, %2}"
9149 [(set_attr "type" "alu")
9150 (set_attr "mode" "HI")])
9152 (define_insn "*xorhi_3"
9154 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9155 (match_operand:HI 2 "general_operand" "rim"))
9157 (clobber (match_scratch:HI 0 "=r"))]
9158 "ix86_match_ccmode (insn, CCNOmode)
9159 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9160 "xor{w}\t{%2, %0|%0, %2}"
9161 [(set_attr "type" "alu")
9162 (set_attr "mode" "HI")])
9164 (define_expand "xorqi3"
9165 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9166 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9167 (match_operand:QI 2 "general_operand" "")))
9168 (clobber (reg:CC FLAGS_REG))]
9169 "TARGET_QIMODE_MATH"
9170 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9172 ;; %%% Potential partial reg stall on alternative 2. What to do?
9173 (define_insn "*xorqi_1"
9174 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9175 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9176 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9177 (clobber (reg:CC FLAGS_REG))]
9178 "ix86_binary_operator_ok (XOR, QImode, operands)"
9180 xor{b}\t{%2, %0|%0, %2}
9181 xor{b}\t{%2, %0|%0, %2}
9182 xor{l}\t{%k2, %k0|%k0, %k2}"
9183 [(set_attr "type" "alu")
9184 (set_attr "mode" "QI,QI,SI")])
9186 (define_insn "*xorqi_1_slp"
9187 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9188 (xor:QI (match_dup 0)
9189 (match_operand:QI 1 "general_operand" "qi,qmi")))
9190 (clobber (reg:CC FLAGS_REG))]
9191 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9192 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9193 "xor{b}\t{%1, %0|%0, %1}"
9194 [(set_attr "type" "alu1")
9195 (set_attr "mode" "QI")])
9197 (define_insn "xorqi_ext_0"
9198 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9203 (match_operand 1 "ext_register_operand" "0")
9206 (match_operand 2 "const_int_operand" "n")))
9207 (clobber (reg:CC FLAGS_REG))]
9208 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9209 "xor{b}\t{%2, %h0|%h0, %2}"
9210 [(set_attr "type" "alu")
9211 (set_attr "length_immediate" "1")
9212 (set_attr "mode" "QI")])
9214 (define_insn "*xorqi_ext_1"
9215 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9220 (match_operand 1 "ext_register_operand" "0")
9224 (match_operand:QI 2 "general_operand" "Qm"))))
9225 (clobber (reg:CC FLAGS_REG))]
9227 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9228 "xor{b}\t{%2, %h0|%h0, %2}"
9229 [(set_attr "type" "alu")
9230 (set_attr "length_immediate" "0")
9231 (set_attr "mode" "QI")])
9233 (define_insn "*xorqi_ext_1_rex64"
9234 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9239 (match_operand 1 "ext_register_operand" "0")
9243 (match_operand 2 "ext_register_operand" "Q"))))
9244 (clobber (reg:CC FLAGS_REG))]
9246 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9247 "xor{b}\t{%2, %h0|%h0, %2}"
9248 [(set_attr "type" "alu")
9249 (set_attr "length_immediate" "0")
9250 (set_attr "mode" "QI")])
9252 (define_insn "*xorqi_ext_2"
9253 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9257 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9260 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9263 (clobber (reg:CC FLAGS_REG))]
9264 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9265 "xor{b}\t{%h2, %h0|%h0, %h2}"
9266 [(set_attr "type" "alu")
9267 (set_attr "length_immediate" "0")
9268 (set_attr "mode" "QI")])
9270 (define_insn "*xorqi_cc_1"
9273 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9274 (match_operand:QI 2 "general_operand" "qim,qi"))
9276 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9277 (xor:QI (match_dup 1) (match_dup 2)))]
9278 "ix86_match_ccmode (insn, CCNOmode)
9279 && ix86_binary_operator_ok (XOR, QImode, operands)"
9280 "xor{b}\t{%2, %0|%0, %2}"
9281 [(set_attr "type" "alu")
9282 (set_attr "mode" "QI")])
9284 (define_insn "*xorqi_2_slp"
9286 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9287 (match_operand:QI 1 "general_operand" "qim,qi"))
9289 (set (strict_low_part (match_dup 0))
9290 (xor:QI (match_dup 0) (match_dup 1)))]
9291 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9292 && ix86_match_ccmode (insn, CCNOmode)
9293 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9294 "xor{b}\t{%1, %0|%0, %1}"
9295 [(set_attr "type" "alu1")
9296 (set_attr "mode" "QI")])
9298 (define_insn "*xorqi_cc_2"
9301 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9302 (match_operand:QI 2 "general_operand" "qim"))
9304 (clobber (match_scratch:QI 0 "=q"))]
9305 "ix86_match_ccmode (insn, CCNOmode)
9306 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9307 "xor{b}\t{%2, %0|%0, %2}"
9308 [(set_attr "type" "alu")
9309 (set_attr "mode" "QI")])
9311 (define_insn "*xorqi_cc_ext_1"
9316 (match_operand 1 "ext_register_operand" "0")
9319 (match_operand:QI 2 "general_operand" "qmn"))
9321 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9325 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9327 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9328 "xor{b}\t{%2, %h0|%h0, %2}"
9329 [(set_attr "type" "alu")
9330 (set_attr "mode" "QI")])
9332 (define_insn "*xorqi_cc_ext_1_rex64"
9337 (match_operand 1 "ext_register_operand" "0")
9340 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9342 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9346 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9348 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9349 "xor{b}\t{%2, %h0|%h0, %2}"
9350 [(set_attr "type" "alu")
9351 (set_attr "mode" "QI")])
9353 (define_expand "xorqi_cc_ext_1"
9355 (set (reg:CCNO FLAGS_REG)
9359 (match_operand 1 "ext_register_operand" "")
9362 (match_operand:QI 2 "general_operand" ""))
9364 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9368 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9374 [(set (match_operand 0 "register_operand" "")
9375 (xor (match_operand 1 "register_operand" "")
9376 (match_operand 2 "const_int_operand" "")))
9377 (clobber (reg:CC FLAGS_REG))]
9379 && QI_REG_P (operands[0])
9380 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9381 && !(INTVAL (operands[2]) & ~(255 << 8))
9382 && GET_MODE (operands[0]) != QImode"
9383 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9384 (xor:SI (zero_extract:SI (match_dup 1)
9385 (const_int 8) (const_int 8))
9387 (clobber (reg:CC FLAGS_REG))])]
9388 "operands[0] = gen_lowpart (SImode, operands[0]);
9389 operands[1] = gen_lowpart (SImode, operands[1]);
9390 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9392 ;; Since XOR can be encoded with sign extended immediate, this is only
9393 ;; profitable when 7th bit is set.
9395 [(set (match_operand 0 "register_operand" "")
9396 (xor (match_operand 1 "general_operand" "")
9397 (match_operand 2 "const_int_operand" "")))
9398 (clobber (reg:CC FLAGS_REG))]
9400 && ANY_QI_REG_P (operands[0])
9401 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9402 && !(INTVAL (operands[2]) & ~255)
9403 && (INTVAL (operands[2]) & 128)
9404 && GET_MODE (operands[0]) != QImode"
9405 [(parallel [(set (strict_low_part (match_dup 0))
9406 (xor:QI (match_dup 1)
9408 (clobber (reg:CC FLAGS_REG))])]
9409 "operands[0] = gen_lowpart (QImode, operands[0]);
9410 operands[1] = gen_lowpart (QImode, operands[1]);
9411 operands[2] = gen_lowpart (QImode, operands[2]);")
9413 ;; Negation instructions
9415 (define_expand "negdi2"
9416 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9417 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9418 (clobber (reg:CC FLAGS_REG))])]
9420 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9422 (define_insn "*negdi2_1"
9423 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9424 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9425 (clobber (reg:CC FLAGS_REG))]
9427 && ix86_unary_operator_ok (NEG, DImode, operands)"
9431 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9432 (neg:DI (match_operand:DI 1 "general_operand" "")))
9433 (clobber (reg:CC FLAGS_REG))]
9434 "!TARGET_64BIT && reload_completed"
9436 [(set (reg:CCZ FLAGS_REG)
9437 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9438 (set (match_dup 0) (neg:SI (match_dup 2)))])
9441 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
9444 (clobber (reg:CC FLAGS_REG))])
9447 (neg:SI (match_dup 1)))
9448 (clobber (reg:CC FLAGS_REG))])]
9449 "split_di (operands+1, 1, operands+2, operands+3);
9450 split_di (operands+0, 1, operands+0, operands+1);")
9452 (define_insn "*negdi2_1_rex64"
9453 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9454 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9455 (clobber (reg:CC FLAGS_REG))]
9456 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9458 [(set_attr "type" "negnot")
9459 (set_attr "mode" "DI")])
9461 ;; The problem with neg is that it does not perform (compare x 0),
9462 ;; it really performs (compare 0 x), which leaves us with the zero
9463 ;; flag being the only useful item.
9465 (define_insn "*negdi2_cmpz_rex64"
9466 [(set (reg:CCZ FLAGS_REG)
9467 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9469 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9470 (neg:DI (match_dup 1)))]
9471 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9473 [(set_attr "type" "negnot")
9474 (set_attr "mode" "DI")])
9477 (define_expand "negsi2"
9478 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9479 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9480 (clobber (reg:CC FLAGS_REG))])]
9482 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9484 (define_insn "*negsi2_1"
9485 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9486 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9487 (clobber (reg:CC FLAGS_REG))]
9488 "ix86_unary_operator_ok (NEG, SImode, operands)"
9490 [(set_attr "type" "negnot")
9491 (set_attr "mode" "SI")])
9493 ;; Combine is quite creative about this pattern.
9494 (define_insn "*negsi2_1_zext"
9495 [(set (match_operand:DI 0 "register_operand" "=r")
9496 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9499 (clobber (reg:CC FLAGS_REG))]
9500 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9502 [(set_attr "type" "negnot")
9503 (set_attr "mode" "SI")])
9505 ;; The problem with neg is that it does not perform (compare x 0),
9506 ;; it really performs (compare 0 x), which leaves us with the zero
9507 ;; flag being the only useful item.
9509 (define_insn "*negsi2_cmpz"
9510 [(set (reg:CCZ FLAGS_REG)
9511 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9513 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9514 (neg:SI (match_dup 1)))]
9515 "ix86_unary_operator_ok (NEG, SImode, operands)"
9517 [(set_attr "type" "negnot")
9518 (set_attr "mode" "SI")])
9520 (define_insn "*negsi2_cmpz_zext"
9521 [(set (reg:CCZ FLAGS_REG)
9522 (compare:CCZ (lshiftrt:DI
9524 (match_operand:DI 1 "register_operand" "0")
9528 (set (match_operand:DI 0 "register_operand" "=r")
9529 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9532 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9534 [(set_attr "type" "negnot")
9535 (set_attr "mode" "SI")])
9537 (define_expand "neghi2"
9538 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9539 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9540 (clobber (reg:CC FLAGS_REG))])]
9541 "TARGET_HIMODE_MATH"
9542 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9544 (define_insn "*neghi2_1"
9545 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9546 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9547 (clobber (reg:CC FLAGS_REG))]
9548 "ix86_unary_operator_ok (NEG, HImode, operands)"
9550 [(set_attr "type" "negnot")
9551 (set_attr "mode" "HI")])
9553 (define_insn "*neghi2_cmpz"
9554 [(set (reg:CCZ FLAGS_REG)
9555 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9557 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9558 (neg:HI (match_dup 1)))]
9559 "ix86_unary_operator_ok (NEG, HImode, operands)"
9561 [(set_attr "type" "negnot")
9562 (set_attr "mode" "HI")])
9564 (define_expand "negqi2"
9565 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9566 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9567 (clobber (reg:CC FLAGS_REG))])]
9568 "TARGET_QIMODE_MATH"
9569 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9571 (define_insn "*negqi2_1"
9572 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9573 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9574 (clobber (reg:CC FLAGS_REG))]
9575 "ix86_unary_operator_ok (NEG, QImode, operands)"
9577 [(set_attr "type" "negnot")
9578 (set_attr "mode" "QI")])
9580 (define_insn "*negqi2_cmpz"
9581 [(set (reg:CCZ FLAGS_REG)
9582 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9584 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9585 (neg:QI (match_dup 1)))]
9586 "ix86_unary_operator_ok (NEG, QImode, operands)"
9588 [(set_attr "type" "negnot")
9589 (set_attr "mode" "QI")])
9591 ;; Changing of sign for FP values is doable using integer unit too.
9593 (define_expand "negsf2"
9594 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9595 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9596 (clobber (reg:CC FLAGS_REG))])]
9600 /* In case operand is in memory, we will not use SSE. */
9601 if (memory_operand (operands[0], VOIDmode)
9602 && rtx_equal_p (operands[0], operands[1]))
9603 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9606 /* Using SSE is tricky, since we need bitwise negation of -0
9608 rtx reg = gen_reg_rtx (SFmode);
9609 rtx dest = operands[0];
9610 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9612 operands[1] = force_reg (SFmode, operands[1]);
9613 operands[0] = force_reg (SFmode, operands[0]);
9614 reg = force_reg (V4SFmode,
9615 gen_rtx_CONST_VECTOR (V4SFmode,
9616 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9617 CONST0_RTX (SFmode),
9618 CONST0_RTX (SFmode))));
9619 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9620 if (dest != operands[0])
9621 emit_move_insn (dest, operands[0]);
9625 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9627 (define_insn "negsf2_memory"
9628 [(set (match_operand:SF 0 "memory_operand" "=m")
9629 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9630 (clobber (reg:CC FLAGS_REG))]
9631 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9634 (define_insn "negsf2_ifs"
9635 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9636 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9637 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9638 (clobber (reg:CC FLAGS_REG))]
9640 && (reload_in_progress || reload_completed
9641 || (register_operand (operands[0], VOIDmode)
9642 && register_operand (operands[1], VOIDmode)))"
9646 [(set (match_operand:SF 0 "memory_operand" "")
9647 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9648 (use (match_operand:SF 2 "" ""))
9649 (clobber (reg:CC FLAGS_REG))]
9651 [(parallel [(set (match_dup 0)
9652 (neg:SF (match_dup 1)))
9653 (clobber (reg:CC FLAGS_REG))])])
9656 [(set (match_operand:SF 0 "register_operand" "")
9657 (neg:SF (match_operand:SF 1 "register_operand" "")))
9658 (use (match_operand:V4SF 2 "" ""))
9659 (clobber (reg:CC FLAGS_REG))]
9660 "reload_completed && !SSE_REG_P (operands[0])"
9661 [(parallel [(set (match_dup 0)
9662 (neg:SF (match_dup 1)))
9663 (clobber (reg:CC FLAGS_REG))])])
9666 [(set (match_operand:SF 0 "register_operand" "")
9667 (neg:SF (match_operand:SF 1 "register_operand" "")))
9668 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9669 (clobber (reg:CC FLAGS_REG))]
9670 "reload_completed && SSE_REG_P (operands[0])"
9672 (xor:V4SF (match_dup 1)
9675 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
9676 operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
9677 if (operands_match_p (operands[0], operands[2]))
9681 operands[1] = operands[2];
9687 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9688 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9690 (define_insn "*negsf2_if"
9691 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9692 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9693 (clobber (reg:CC FLAGS_REG))]
9694 "TARGET_80387 && !TARGET_SSE
9695 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9699 [(set (match_operand:SF 0 "fp_register_operand" "")
9700 (neg:SF (match_operand:SF 1 "register_operand" "")))
9701 (clobber (reg:CC FLAGS_REG))]
9702 "TARGET_80387 && reload_completed"
9704 (neg:SF (match_dup 1)))]
9708 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9709 (neg:SF (match_operand:SF 1 "register_operand" "")))
9710 (clobber (reg:CC FLAGS_REG))]
9711 "TARGET_80387 && reload_completed"
9712 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9713 (clobber (reg:CC FLAGS_REG))])]
9714 "operands[1] = gen_int_mode (0x80000000, SImode);
9715 operands[0] = gen_lowpart (SImode, operands[0]);")
9718 [(set (match_operand 0 "memory_operand" "")
9719 (neg (match_operand 1 "memory_operand" "")))
9720 (clobber (reg:CC FLAGS_REG))]
9721 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9722 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9723 (clobber (reg:CC FLAGS_REG))])]
9725 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9727 if (GET_MODE (operands[1]) == XFmode)
9729 operands[0] = adjust_address (operands[0], QImode, size - 1);
9730 operands[1] = gen_int_mode (0x80, QImode);
9733 (define_expand "negdf2"
9734 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9735 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9736 (clobber (reg:CC FLAGS_REG))])]
9740 /* In case operand is in memory, we will not use SSE. */
9741 if (memory_operand (operands[0], VOIDmode)
9742 && rtx_equal_p (operands[0], operands[1]))
9743 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9746 /* Using SSE is tricky, since we need bitwise negation of -0
9749 #if HOST_BITS_PER_WIDE_INT >= 64
9750 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9752 rtx imm = immed_double_const (0, 0x80000000, DImode);
9754 rtx dest = operands[0];
9756 operands[1] = force_reg (DFmode, operands[1]);
9757 operands[0] = force_reg (DFmode, operands[0]);
9758 imm = gen_lowpart (DFmode, imm);
9759 reg = force_reg (V2DFmode,
9760 gen_rtx_CONST_VECTOR (V2DFmode,
9761 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
9762 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9763 if (dest != operands[0])
9764 emit_move_insn (dest, operands[0]);
9768 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9770 (define_insn "negdf2_memory"
9771 [(set (match_operand:DF 0 "memory_operand" "=m")
9772 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9773 (clobber (reg:CC FLAGS_REG))]
9774 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9777 (define_insn "negdf2_ifs"
9778 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9779 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9780 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
9781 (clobber (reg:CC FLAGS_REG))]
9782 "!TARGET_64BIT && TARGET_SSE2
9783 && (reload_in_progress || reload_completed
9784 || (register_operand (operands[0], VOIDmode)
9785 && register_operand (operands[1], VOIDmode)))"
9788 (define_insn "*negdf2_ifs_rex64"
9789 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
9790 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
9791 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
9792 (clobber (reg:CC FLAGS_REG))]
9793 "TARGET_64BIT && TARGET_SSE2
9794 && (reload_in_progress || reload_completed
9795 || (register_operand (operands[0], VOIDmode)
9796 && register_operand (operands[1], VOIDmode)))"
9800 [(set (match_operand:DF 0 "memory_operand" "")
9801 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9802 (use (match_operand:V2DF 2 "" ""))
9803 (clobber (reg:CC FLAGS_REG))]
9805 [(parallel [(set (match_dup 0)
9806 (neg:DF (match_dup 1)))
9807 (clobber (reg:CC FLAGS_REG))])])
9810 [(set (match_operand:DF 0 "register_operand" "")
9811 (neg:DF (match_operand:DF 1 "register_operand" "")))
9812 (use (match_operand:V2DF 2 "" ""))
9813 (clobber (reg:CC FLAGS_REG))]
9814 "reload_completed && !SSE_REG_P (operands[0])
9815 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9816 [(parallel [(set (match_dup 0)
9817 (neg:DF (match_dup 1)))
9818 (clobber (reg:CC FLAGS_REG))])])
9821 [(set (match_operand:DF 0 "register_operand" "")
9822 (neg:DF (match_operand:DF 1 "register_operand" "")))
9823 (use (match_operand:V2DF 2 "" ""))
9824 (clobber (reg:CC FLAGS_REG))]
9825 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9826 [(parallel [(set (match_dup 0)
9827 (xor:DI (match_dup 1) (match_dup 2)))
9828 (clobber (reg:CC FLAGS_REG))])]
9829 "operands[0] = gen_lowpart (DImode, operands[0]);
9830 operands[1] = gen_lowpart (DImode, operands[1]);
9831 operands[2] = gen_lowpart (DImode, operands[2]);")
9834 [(set (match_operand:DF 0 "register_operand" "")
9835 (neg:DF (match_operand:DF 1 "register_operand" "")))
9836 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
9837 (clobber (reg:CC FLAGS_REG))]
9838 "reload_completed && SSE_REG_P (operands[0])"
9840 (xor:V2DF (match_dup 1)
9843 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
9844 operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
9845 /* Avoid possible reformatting on the operands. */
9846 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
9847 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
9848 if (operands_match_p (operands[0], operands[2]))
9852 operands[1] = operands[2];
9857 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9858 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9860 (define_insn "*negdf2_if"
9861 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9862 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9863 (clobber (reg:CC FLAGS_REG))]
9864 "!TARGET_64BIT && TARGET_80387
9865 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9868 ;; FIXME: We should to allow integer registers here. Problem is that
9869 ;; we need another scratch register to get constant from.
9870 ;; Forcing constant to mem if no register available in peep2 should be
9871 ;; safe even for PIC mode, because of RIP relative addressing.
9872 (define_insn "*negdf2_if_rex64"
9873 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9874 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9875 (clobber (reg:CC FLAGS_REG))]
9876 "TARGET_64BIT && TARGET_80387
9877 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9881 [(set (match_operand:DF 0 "fp_register_operand" "")
9882 (neg:DF (match_operand:DF 1 "register_operand" "")))
9883 (clobber (reg:CC FLAGS_REG))]
9884 "TARGET_80387 && reload_completed"
9886 (neg:DF (match_dup 1)))]
9890 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9891 (neg:DF (match_operand:DF 1 "register_operand" "")))
9892 (clobber (reg:CC FLAGS_REG))]
9893 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9894 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9895 (clobber (reg:CC FLAGS_REG))])]
9896 "operands[4] = gen_int_mode (0x80000000, SImode);
9897 split_di (operands+0, 1, operands+2, operands+3);")
9899 (define_expand "negxf2"
9900 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9901 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9902 (clobber (reg:CC FLAGS_REG))])]
9904 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9906 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9907 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9909 (define_insn "*negxf2_if"
9910 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9911 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9912 (clobber (reg:CC FLAGS_REG))]
9914 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9918 [(set (match_operand:XF 0 "fp_register_operand" "")
9919 (neg:XF (match_operand:XF 1 "register_operand" "")))
9920 (clobber (reg:CC FLAGS_REG))]
9921 "TARGET_80387 && reload_completed"
9923 (neg:XF (match_dup 1)))]
9927 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
9928 (neg:XF (match_operand:XF 1 "register_operand" "")))
9929 (clobber (reg:CC FLAGS_REG))]
9930 "TARGET_80387 && reload_completed"
9931 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9932 (clobber (reg:CC FLAGS_REG))])]
9933 "operands[1] = GEN_INT (0x8000);
9934 operands[0] = gen_rtx_REG (SImode,
9935 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9937 ;; Conditionalize these after reload. If they matches before reload, we
9938 ;; lose the clobber and ability to use integer instructions.
9940 (define_insn "*negsf2_1"
9941 [(set (match_operand:SF 0 "register_operand" "=f")
9942 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9943 "TARGET_80387 && reload_completed"
9945 [(set_attr "type" "fsgn")
9946 (set_attr "mode" "SF")])
9948 (define_insn "*negdf2_1"
9949 [(set (match_operand:DF 0 "register_operand" "=f")
9950 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9951 "TARGET_80387 && reload_completed"
9953 [(set_attr "type" "fsgn")
9954 (set_attr "mode" "DF")])
9956 (define_insn "*negextendsfdf2"
9957 [(set (match_operand:DF 0 "register_operand" "=f")
9958 (neg:DF (float_extend:DF
9959 (match_operand:SF 1 "register_operand" "0"))))]
9962 [(set_attr "type" "fsgn")
9963 (set_attr "mode" "DF")])
9965 (define_insn "*negxf2_1"
9966 [(set (match_operand:XF 0 "register_operand" "=f")
9967 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9968 "TARGET_80387 && reload_completed"
9970 [(set_attr "type" "fsgn")
9971 (set_attr "mode" "XF")])
9973 (define_insn "*negextenddfxf2"
9974 [(set (match_operand:XF 0 "register_operand" "=f")
9975 (neg:XF (float_extend:XF
9976 (match_operand:DF 1 "register_operand" "0"))))]
9979 [(set_attr "type" "fsgn")
9980 (set_attr "mode" "XF")])
9982 (define_insn "*negextendsfxf2"
9983 [(set (match_operand:XF 0 "register_operand" "=f")
9984 (neg:XF (float_extend:XF
9985 (match_operand:SF 1 "register_operand" "0"))))]
9988 [(set_attr "type" "fsgn")
9989 (set_attr "mode" "XF")])
9991 ;; Absolute value instructions
9993 (define_expand "abssf2"
9994 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9995 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9996 (clobber (reg:CC FLAGS_REG))])]
10000 /* In case operand is in memory, we will not use SSE. */
10001 if (memory_operand (operands[0], VOIDmode)
10002 && rtx_equal_p (operands[0], operands[1]))
10003 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10006 /* Using SSE is tricky, since we need bitwise negation of -0
10008 rtx reg = gen_reg_rtx (V4SFmode);
10009 rtx dest = operands[0];
10012 operands[1] = force_reg (SFmode, operands[1]);
10013 operands[0] = force_reg (SFmode, operands[0]);
10014 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
10015 reg = force_reg (V4SFmode,
10016 gen_rtx_CONST_VECTOR (V4SFmode,
10017 gen_rtvec (4, imm, CONST0_RTX (SFmode),
10018 CONST0_RTX (SFmode),
10019 CONST0_RTX (SFmode))));
10020 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10021 if (dest != operands[0])
10022 emit_move_insn (dest, operands[0]);
10026 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10028 (define_insn "abssf2_memory"
10029 [(set (match_operand:SF 0 "memory_operand" "=m")
10030 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10031 (clobber (reg:CC FLAGS_REG))]
10032 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10035 (define_insn "abssf2_ifs"
10036 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10037 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10038 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10039 (clobber (reg:CC FLAGS_REG))]
10041 && (reload_in_progress || reload_completed
10042 || (register_operand (operands[0], VOIDmode)
10043 && register_operand (operands[1], VOIDmode)))"
10047 [(set (match_operand:SF 0 "memory_operand" "")
10048 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10049 (use (match_operand:V4SF 2 "" ""))
10050 (clobber (reg:CC FLAGS_REG))]
10052 [(parallel [(set (match_dup 0)
10053 (abs:SF (match_dup 1)))
10054 (clobber (reg:CC FLAGS_REG))])])
10057 [(set (match_operand:SF 0 "register_operand" "")
10058 (abs:SF (match_operand:SF 1 "register_operand" "")))
10059 (use (match_operand:V4SF 2 "" ""))
10060 (clobber (reg:CC FLAGS_REG))]
10061 "reload_completed && !SSE_REG_P (operands[0])"
10062 [(parallel [(set (match_dup 0)
10063 (abs:SF (match_dup 1)))
10064 (clobber (reg:CC FLAGS_REG))])])
10067 [(set (match_operand:SF 0 "register_operand" "")
10068 (abs:SF (match_operand:SF 1 "register_operand" "")))
10069 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10070 (clobber (reg:CC FLAGS_REG))]
10071 "reload_completed && SSE_REG_P (operands[0])"
10072 [(set (match_dup 0)
10073 (and:V4SF (match_dup 1)
10076 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
10077 operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
10078 if (operands_match_p (operands[0], operands[2]))
10082 operands[1] = operands[2];
10087 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10088 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10090 (define_insn "*abssf2_if"
10091 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10092 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10093 (clobber (reg:CC FLAGS_REG))]
10094 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10098 [(set (match_operand:SF 0 "fp_register_operand" "")
10099 (abs:SF (match_operand:SF 1 "register_operand" "")))
10100 (clobber (reg:CC FLAGS_REG))]
10101 "TARGET_80387 && reload_completed"
10102 [(set (match_dup 0)
10103 (abs:SF (match_dup 1)))]
10107 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10108 (abs:SF (match_operand:SF 1 "register_operand" "")))
10109 (clobber (reg:CC FLAGS_REG))]
10110 "TARGET_80387 && reload_completed"
10111 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10112 (clobber (reg:CC FLAGS_REG))])]
10113 "operands[1] = gen_int_mode (~0x80000000, SImode);
10114 operands[0] = gen_lowpart (SImode, operands[0]);")
10117 [(set (match_operand 0 "memory_operand" "")
10118 (abs (match_operand 1 "memory_operand" "")))
10119 (clobber (reg:CC FLAGS_REG))]
10120 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10121 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10122 (clobber (reg:CC FLAGS_REG))])]
10124 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10126 if (GET_MODE (operands[1]) == XFmode)
10128 operands[0] = adjust_address (operands[0], QImode, size - 1);
10129 operands[1] = gen_int_mode (~0x80, QImode);
10132 (define_expand "absdf2"
10133 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10134 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10135 (clobber (reg:CC FLAGS_REG))])]
10139 /* In case operand is in memory, we will not use SSE. */
10140 if (memory_operand (operands[0], VOIDmode)
10141 && rtx_equal_p (operands[0], operands[1]))
10142 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10145 /* Using SSE is tricky, since we need bitwise negation of -0
10147 rtx reg = gen_reg_rtx (V2DFmode);
10148 #if HOST_BITS_PER_WIDE_INT >= 64
10149 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10151 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10153 rtx dest = operands[0];
10155 operands[1] = force_reg (DFmode, operands[1]);
10156 operands[0] = force_reg (DFmode, operands[0]);
10158 /* Produce LONG_DOUBLE with the proper immediate argument. */
10159 imm = gen_lowpart (DFmode, imm);
10160 reg = force_reg (V2DFmode,
10161 gen_rtx_CONST_VECTOR (V2DFmode,
10162 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10163 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10164 if (dest != operands[0])
10165 emit_move_insn (dest, operands[0]);
10169 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10171 (define_insn "absdf2_memory"
10172 [(set (match_operand:DF 0 "memory_operand" "=m")
10173 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10174 (clobber (reg:CC FLAGS_REG))]
10175 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10178 (define_insn "absdf2_ifs"
10179 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10180 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10181 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10182 (clobber (reg:CC FLAGS_REG))]
10183 "!TARGET_64BIT && TARGET_SSE2
10184 && (reload_in_progress || reload_completed
10185 || (register_operand (operands[0], VOIDmode)
10186 && register_operand (operands[1], VOIDmode)))"
10189 (define_insn "*absdf2_ifs_rex64"
10190 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10191 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10192 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10193 (clobber (reg:CC FLAGS_REG))]
10194 "TARGET_64BIT && TARGET_SSE2
10195 && (reload_in_progress || reload_completed
10196 || (register_operand (operands[0], VOIDmode)
10197 && register_operand (operands[1], VOIDmode)))"
10201 [(set (match_operand:DF 0 "memory_operand" "")
10202 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10203 (use (match_operand:V2DF 2 "" ""))
10204 (clobber (reg:CC FLAGS_REG))]
10206 [(parallel [(set (match_dup 0)
10207 (abs:DF (match_dup 1)))
10208 (clobber (reg:CC FLAGS_REG))])])
10211 [(set (match_operand:DF 0 "register_operand" "")
10212 (abs:DF (match_operand:DF 1 "register_operand" "")))
10213 (use (match_operand:V2DF 2 "" ""))
10214 (clobber (reg:CC FLAGS_REG))]
10215 "reload_completed && !SSE_REG_P (operands[0])"
10216 [(parallel [(set (match_dup 0)
10217 (abs:DF (match_dup 1)))
10218 (clobber (reg:CC FLAGS_REG))])])
10221 [(set (match_operand:DF 0 "register_operand" "")
10222 (abs:DF (match_operand:DF 1 "register_operand" "")))
10223 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10224 (clobber (reg:CC FLAGS_REG))]
10225 "reload_completed && SSE_REG_P (operands[0])"
10226 [(set (match_dup 0)
10227 (and:V2DF (match_dup 1)
10230 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10231 operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
10232 /* Avoid possible reformatting on the operands. */
10233 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10234 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10235 if (operands_match_p (operands[0], operands[2]))
10239 operands[1] = operands[2];
10245 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10246 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10248 (define_insn "*absdf2_if"
10249 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10250 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10251 (clobber (reg:CC FLAGS_REG))]
10252 "!TARGET_64BIT && TARGET_80387
10253 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10256 ;; FIXME: We should to allow integer registers here. Problem is that
10257 ;; we need another scratch register to get constant from.
10258 ;; Forcing constant to mem if no register available in peep2 should be
10259 ;; safe even for PIC mode, because of RIP relative addressing.
10260 (define_insn "*absdf2_if_rex64"
10261 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10262 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10263 (clobber (reg:CC FLAGS_REG))]
10264 "TARGET_64BIT && TARGET_80387
10265 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10269 [(set (match_operand:DF 0 "fp_register_operand" "")
10270 (abs:DF (match_operand:DF 1 "register_operand" "")))
10271 (clobber (reg:CC FLAGS_REG))]
10272 "TARGET_80387 && reload_completed"
10273 [(set (match_dup 0)
10274 (abs:DF (match_dup 1)))]
10278 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10279 (abs:DF (match_operand:DF 1 "register_operand" "")))
10280 (clobber (reg:CC FLAGS_REG))]
10281 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10282 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10283 (clobber (reg:CC FLAGS_REG))])]
10284 "operands[4] = gen_int_mode (~0x80000000, SImode);
10285 split_di (operands+0, 1, operands+2, operands+3);")
10287 (define_expand "absxf2"
10288 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10289 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10290 (clobber (reg:CC FLAGS_REG))])]
10292 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10294 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10295 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10297 (define_insn "*absxf2_if"
10298 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10299 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10300 (clobber (reg:CC FLAGS_REG))]
10302 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10306 [(set (match_operand:XF 0 "fp_register_operand" "")
10307 (abs:XF (match_operand:XF 1 "register_operand" "")))
10308 (clobber (reg:CC FLAGS_REG))]
10309 "TARGET_80387 && reload_completed"
10310 [(set (match_dup 0)
10311 (abs:XF (match_dup 1)))]
10315 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10316 (abs:XF (match_operand:XF 1 "register_operand" "")))
10317 (clobber (reg:CC FLAGS_REG))]
10318 "TARGET_80387 && reload_completed"
10319 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10320 (clobber (reg:CC FLAGS_REG))])]
10321 "operands[1] = GEN_INT (~0x8000);
10322 operands[0] = gen_rtx_REG (SImode,
10323 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10325 (define_insn "*abssf2_1"
10326 [(set (match_operand:SF 0 "register_operand" "=f")
10327 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10328 "TARGET_80387 && reload_completed"
10330 [(set_attr "type" "fsgn")
10331 (set_attr "mode" "SF")])
10333 (define_insn "*absdf2_1"
10334 [(set (match_operand:DF 0 "register_operand" "=f")
10335 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10336 "TARGET_80387 && reload_completed"
10338 [(set_attr "type" "fsgn")
10339 (set_attr "mode" "DF")])
10341 (define_insn "*absextendsfdf2"
10342 [(set (match_operand:DF 0 "register_operand" "=f")
10343 (abs:DF (float_extend:DF
10344 (match_operand:SF 1 "register_operand" "0"))))]
10347 [(set_attr "type" "fsgn")
10348 (set_attr "mode" "DF")])
10350 (define_insn "*absxf2_1"
10351 [(set (match_operand:XF 0 "register_operand" "=f")
10352 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10353 "TARGET_80387 && reload_completed"
10355 [(set_attr "type" "fsgn")
10356 (set_attr "mode" "DF")])
10358 (define_insn "*absextenddfxf2"
10359 [(set (match_operand:XF 0 "register_operand" "=f")
10360 (abs:XF (float_extend:XF
10361 (match_operand:DF 1 "register_operand" "0"))))]
10364 [(set_attr "type" "fsgn")
10365 (set_attr "mode" "XF")])
10367 (define_insn "*absextendsfxf2"
10368 [(set (match_operand:XF 0 "register_operand" "=f")
10369 (abs:XF (float_extend:XF
10370 (match_operand:SF 1 "register_operand" "0"))))]
10373 [(set_attr "type" "fsgn")
10374 (set_attr "mode" "XF")])
10376 ;; One complement instructions
10378 (define_expand "one_cmpldi2"
10379 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10380 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10382 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10384 (define_insn "*one_cmpldi2_1_rex64"
10385 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10386 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10387 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10389 [(set_attr "type" "negnot")
10390 (set_attr "mode" "DI")])
10392 (define_insn "*one_cmpldi2_2_rex64"
10394 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10396 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10397 (not:DI (match_dup 1)))]
10398 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10399 && ix86_unary_operator_ok (NOT, DImode, operands)"
10401 [(set_attr "type" "alu1")
10402 (set_attr "mode" "DI")])
10406 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10408 (set (match_operand:DI 0 "nonimmediate_operand" "")
10409 (not:DI (match_dup 1)))]
10410 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10411 [(parallel [(set (reg:CCNO FLAGS_REG)
10412 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10415 (xor:DI (match_dup 1) (const_int -1)))])]
10418 (define_expand "one_cmplsi2"
10419 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10420 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10422 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10424 (define_insn "*one_cmplsi2_1"
10425 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10426 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10427 "ix86_unary_operator_ok (NOT, SImode, operands)"
10429 [(set_attr "type" "negnot")
10430 (set_attr "mode" "SI")])
10432 ;; ??? Currently never generated - xor is used instead.
10433 (define_insn "*one_cmplsi2_1_zext"
10434 [(set (match_operand:DI 0 "register_operand" "=r")
10435 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10436 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10438 [(set_attr "type" "negnot")
10439 (set_attr "mode" "SI")])
10441 (define_insn "*one_cmplsi2_2"
10443 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10445 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10446 (not:SI (match_dup 1)))]
10447 "ix86_match_ccmode (insn, CCNOmode)
10448 && ix86_unary_operator_ok (NOT, SImode, operands)"
10450 [(set_attr "type" "alu1")
10451 (set_attr "mode" "SI")])
10455 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10457 (set (match_operand:SI 0 "nonimmediate_operand" "")
10458 (not:SI (match_dup 1)))]
10459 "ix86_match_ccmode (insn, CCNOmode)"
10460 [(parallel [(set (reg:CCNO FLAGS_REG)
10461 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10464 (xor:SI (match_dup 1) (const_int -1)))])]
10467 ;; ??? Currently never generated - xor is used instead.
10468 (define_insn "*one_cmplsi2_2_zext"
10470 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10472 (set (match_operand:DI 0 "register_operand" "=r")
10473 (zero_extend:DI (not:SI (match_dup 1))))]
10474 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10475 && ix86_unary_operator_ok (NOT, SImode, operands)"
10477 [(set_attr "type" "alu1")
10478 (set_attr "mode" "SI")])
10482 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10484 (set (match_operand:DI 0 "register_operand" "")
10485 (zero_extend:DI (not:SI (match_dup 1))))]
10486 "ix86_match_ccmode (insn, CCNOmode)"
10487 [(parallel [(set (reg:CCNO FLAGS_REG)
10488 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10491 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10494 (define_expand "one_cmplhi2"
10495 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10496 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10497 "TARGET_HIMODE_MATH"
10498 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10500 (define_insn "*one_cmplhi2_1"
10501 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10502 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10503 "ix86_unary_operator_ok (NOT, HImode, operands)"
10505 [(set_attr "type" "negnot")
10506 (set_attr "mode" "HI")])
10508 (define_insn "*one_cmplhi2_2"
10510 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10512 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10513 (not:HI (match_dup 1)))]
10514 "ix86_match_ccmode (insn, CCNOmode)
10515 && ix86_unary_operator_ok (NEG, HImode, operands)"
10517 [(set_attr "type" "alu1")
10518 (set_attr "mode" "HI")])
10522 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10524 (set (match_operand:HI 0 "nonimmediate_operand" "")
10525 (not:HI (match_dup 1)))]
10526 "ix86_match_ccmode (insn, CCNOmode)"
10527 [(parallel [(set (reg:CCNO FLAGS_REG)
10528 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10531 (xor:HI (match_dup 1) (const_int -1)))])]
10534 ;; %%% Potential partial reg stall on alternative 1. What to do?
10535 (define_expand "one_cmplqi2"
10536 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10537 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10538 "TARGET_QIMODE_MATH"
10539 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10541 (define_insn "*one_cmplqi2_1"
10542 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10543 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10544 "ix86_unary_operator_ok (NOT, QImode, operands)"
10548 [(set_attr "type" "negnot")
10549 (set_attr "mode" "QI,SI")])
10551 (define_insn "*one_cmplqi2_2"
10553 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10555 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10556 (not:QI (match_dup 1)))]
10557 "ix86_match_ccmode (insn, CCNOmode)
10558 && ix86_unary_operator_ok (NOT, QImode, operands)"
10560 [(set_attr "type" "alu1")
10561 (set_attr "mode" "QI")])
10565 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10567 (set (match_operand:QI 0 "nonimmediate_operand" "")
10568 (not:QI (match_dup 1)))]
10569 "ix86_match_ccmode (insn, CCNOmode)"
10570 [(parallel [(set (reg:CCNO FLAGS_REG)
10571 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10574 (xor:QI (match_dup 1) (const_int -1)))])]
10577 ;; Arithmetic shift instructions
10579 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10580 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10581 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10582 ;; from the assembler input.
10584 ;; This instruction shifts the target reg/mem as usual, but instead of
10585 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10586 ;; is a left shift double, bits are taken from the high order bits of
10587 ;; reg, else if the insn is a shift right double, bits are taken from the
10588 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10589 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10591 ;; Since sh[lr]d does not change the `reg' operand, that is done
10592 ;; separately, making all shifts emit pairs of shift double and normal
10593 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10594 ;; support a 63 bit shift, each shift where the count is in a reg expands
10595 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10597 ;; If the shift count is a constant, we need never emit more than one
10598 ;; shift pair, instead using moves and sign extension for counts greater
10601 (define_expand "ashldi3"
10602 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10603 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10604 (match_operand:QI 2 "nonmemory_operand" "")))
10605 (clobber (reg:CC FLAGS_REG))])]
10608 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10610 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10613 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10617 (define_insn "*ashldi3_1_rex64"
10618 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10619 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10620 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10621 (clobber (reg:CC FLAGS_REG))]
10622 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10624 switch (get_attr_type (insn))
10627 if (operands[2] != const1_rtx)
10629 if (!rtx_equal_p (operands[0], operands[1]))
10631 return "add{q}\t{%0, %0|%0, %0}";
10634 if (GET_CODE (operands[2]) != CONST_INT
10635 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10637 operands[1] = gen_rtx_MULT (DImode, operands[1],
10638 GEN_INT (1 << INTVAL (operands[2])));
10639 return "lea{q}\t{%a1, %0|%0, %a1}";
10642 if (REG_P (operands[2]))
10643 return "sal{q}\t{%b2, %0|%0, %b2}";
10644 else if (operands[2] == const1_rtx
10645 && (TARGET_SHIFT1 || optimize_size))
10646 return "sal{q}\t%0";
10648 return "sal{q}\t{%2, %0|%0, %2}";
10651 [(set (attr "type")
10652 (cond [(eq_attr "alternative" "1")
10653 (const_string "lea")
10654 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10656 (match_operand 0 "register_operand" ""))
10657 (match_operand 2 "const1_operand" ""))
10658 (const_string "alu")
10660 (const_string "ishift")))
10661 (set_attr "mode" "DI")])
10663 ;; Convert lea to the lea pattern to avoid flags dependency.
10665 [(set (match_operand:DI 0 "register_operand" "")
10666 (ashift:DI (match_operand:DI 1 "register_operand" "")
10667 (match_operand:QI 2 "immediate_operand" "")))
10668 (clobber (reg:CC FLAGS_REG))]
10669 "TARGET_64BIT && reload_completed
10670 && true_regnum (operands[0]) != true_regnum (operands[1])"
10671 [(set (match_dup 0)
10672 (mult:DI (match_dup 1)
10674 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10676 ;; This pattern can't accept a variable shift count, since shifts by
10677 ;; zero don't affect the flags. We assume that shifts by constant
10678 ;; zero are optimized away.
10679 (define_insn "*ashldi3_cmp_rex64"
10682 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10683 (match_operand:QI 2 "immediate_operand" "e"))
10685 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10686 (ashift:DI (match_dup 1) (match_dup 2)))]
10687 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10688 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10690 switch (get_attr_type (insn))
10693 if (operands[2] != const1_rtx)
10695 return "add{q}\t{%0, %0|%0, %0}";
10698 if (REG_P (operands[2]))
10699 return "sal{q}\t{%b2, %0|%0, %b2}";
10700 else if (operands[2] == const1_rtx
10701 && (TARGET_SHIFT1 || optimize_size))
10702 return "sal{q}\t%0";
10704 return "sal{q}\t{%2, %0|%0, %2}";
10707 [(set (attr "type")
10708 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10710 (match_operand 0 "register_operand" ""))
10711 (match_operand 2 "const1_operand" ""))
10712 (const_string "alu")
10714 (const_string "ishift")))
10715 (set_attr "mode" "DI")])
10717 (define_insn "ashldi3_1"
10718 [(set (match_operand:DI 0 "register_operand" "=r")
10719 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10720 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10721 (clobber (match_scratch:SI 3 "=&r"))
10722 (clobber (reg:CC FLAGS_REG))]
10723 "!TARGET_64BIT && TARGET_CMOVE"
10725 [(set_attr "type" "multi")])
10727 (define_insn "*ashldi3_2"
10728 [(set (match_operand:DI 0 "register_operand" "=r")
10729 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10730 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10731 (clobber (reg:CC FLAGS_REG))]
10734 [(set_attr "type" "multi")])
10737 [(set (match_operand:DI 0 "register_operand" "")
10738 (ashift:DI (match_operand:DI 1 "register_operand" "")
10739 (match_operand:QI 2 "nonmemory_operand" "")))
10740 (clobber (match_scratch:SI 3 ""))
10741 (clobber (reg:CC FLAGS_REG))]
10742 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10744 "ix86_split_ashldi (operands, operands[3]); DONE;")
10747 [(set (match_operand:DI 0 "register_operand" "")
10748 (ashift:DI (match_operand:DI 1 "register_operand" "")
10749 (match_operand:QI 2 "nonmemory_operand" "")))
10750 (clobber (reg:CC FLAGS_REG))]
10751 "!TARGET_64BIT && reload_completed"
10753 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10755 (define_insn "x86_shld_1"
10756 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10757 (ior:SI (ashift:SI (match_dup 0)
10758 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10759 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10760 (minus:QI (const_int 32) (match_dup 2)))))
10761 (clobber (reg:CC FLAGS_REG))]
10764 shld{l}\t{%2, %1, %0|%0, %1, %2}
10765 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10766 [(set_attr "type" "ishift")
10767 (set_attr "prefix_0f" "1")
10768 (set_attr "mode" "SI")
10769 (set_attr "pent_pair" "np")
10770 (set_attr "athlon_decode" "vector")])
10772 (define_expand "x86_shift_adj_1"
10773 [(set (reg:CCZ FLAGS_REG)
10774 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10777 (set (match_operand:SI 0 "register_operand" "")
10778 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10779 (match_operand:SI 1 "register_operand" "")
10782 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10783 (match_operand:SI 3 "register_operand" "r")
10788 (define_expand "x86_shift_adj_2"
10789 [(use (match_operand:SI 0 "register_operand" ""))
10790 (use (match_operand:SI 1 "register_operand" ""))
10791 (use (match_operand:QI 2 "register_operand" ""))]
10794 rtx label = gen_label_rtx ();
10797 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10799 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10800 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10801 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10802 gen_rtx_LABEL_REF (VOIDmode, label),
10804 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10805 JUMP_LABEL (tmp) = label;
10807 emit_move_insn (operands[0], operands[1]);
10808 emit_move_insn (operands[1], const0_rtx);
10810 emit_label (label);
10811 LABEL_NUSES (label) = 1;
10816 (define_expand "ashlsi3"
10817 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10818 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10819 (match_operand:QI 2 "nonmemory_operand" "")))
10820 (clobber (reg:CC FLAGS_REG))]
10822 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10824 (define_insn "*ashlsi3_1"
10825 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10826 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10827 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10828 (clobber (reg:CC FLAGS_REG))]
10829 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10831 switch (get_attr_type (insn))
10834 if (operands[2] != const1_rtx)
10836 if (!rtx_equal_p (operands[0], operands[1]))
10838 return "add{l}\t{%0, %0|%0, %0}";
10844 if (REG_P (operands[2]))
10845 return "sal{l}\t{%b2, %0|%0, %b2}";
10846 else if (operands[2] == const1_rtx
10847 && (TARGET_SHIFT1 || optimize_size))
10848 return "sal{l}\t%0";
10850 return "sal{l}\t{%2, %0|%0, %2}";
10853 [(set (attr "type")
10854 (cond [(eq_attr "alternative" "1")
10855 (const_string "lea")
10856 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10858 (match_operand 0 "register_operand" ""))
10859 (match_operand 2 "const1_operand" ""))
10860 (const_string "alu")
10862 (const_string "ishift")))
10863 (set_attr "mode" "SI")])
10865 ;; Convert lea to the lea pattern to avoid flags dependency.
10867 [(set (match_operand 0 "register_operand" "")
10868 (ashift (match_operand 1 "index_register_operand" "")
10869 (match_operand:QI 2 "const_int_operand" "")))
10870 (clobber (reg:CC FLAGS_REG))]
10872 && true_regnum (operands[0]) != true_regnum (operands[1])"
10876 operands[0] = gen_lowpart (SImode, operands[0]);
10877 operands[1] = gen_lowpart (Pmode, operands[1]);
10878 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10879 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10880 if (Pmode != SImode)
10881 pat = gen_rtx_SUBREG (SImode, pat, 0);
10882 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10886 ;; Rare case of shifting RSP is handled by generating move and shift
10888 [(set (match_operand 0 "register_operand" "")
10889 (ashift (match_operand 1 "register_operand" "")
10890 (match_operand:QI 2 "const_int_operand" "")))
10891 (clobber (reg:CC FLAGS_REG))]
10893 && true_regnum (operands[0]) != true_regnum (operands[1])"
10897 emit_move_insn (operands[1], operands[0]);
10898 pat = gen_rtx_SET (VOIDmode, operands[0],
10899 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10900 operands[0], operands[2]));
10901 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10902 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10906 (define_insn "*ashlsi3_1_zext"
10907 [(set (match_operand:DI 0 "register_operand" "=r,r")
10908 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10909 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10910 (clobber (reg:CC FLAGS_REG))]
10911 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10913 switch (get_attr_type (insn))
10916 if (operands[2] != const1_rtx)
10918 return "add{l}\t{%k0, %k0|%k0, %k0}";
10924 if (REG_P (operands[2]))
10925 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10926 else if (operands[2] == const1_rtx
10927 && (TARGET_SHIFT1 || optimize_size))
10928 return "sal{l}\t%k0";
10930 return "sal{l}\t{%2, %k0|%k0, %2}";
10933 [(set (attr "type")
10934 (cond [(eq_attr "alternative" "1")
10935 (const_string "lea")
10936 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10938 (match_operand 2 "const1_operand" ""))
10939 (const_string "alu")
10941 (const_string "ishift")))
10942 (set_attr "mode" "SI")])
10944 ;; Convert lea to the lea pattern to avoid flags dependency.
10946 [(set (match_operand:DI 0 "register_operand" "")
10947 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10948 (match_operand:QI 2 "const_int_operand" ""))))
10949 (clobber (reg:CC FLAGS_REG))]
10950 "TARGET_64BIT && reload_completed
10951 && true_regnum (operands[0]) != true_regnum (operands[1])"
10952 [(set (match_dup 0) (zero_extend:DI
10953 (subreg:SI (mult:SI (match_dup 1)
10954 (match_dup 2)) 0)))]
10956 operands[1] = gen_lowpart (Pmode, operands[1]);
10957 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10960 ;; This pattern can't accept a variable shift count, since shifts by
10961 ;; zero don't affect the flags. We assume that shifts by constant
10962 ;; zero are optimized away.
10963 (define_insn "*ashlsi3_cmp"
10966 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10967 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10969 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10970 (ashift:SI (match_dup 1) (match_dup 2)))]
10971 "ix86_match_ccmode (insn, CCGOCmode)
10972 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10974 switch (get_attr_type (insn))
10977 if (operands[2] != const1_rtx)
10979 return "add{l}\t{%0, %0|%0, %0}";
10982 if (REG_P (operands[2]))
10983 return "sal{l}\t{%b2, %0|%0, %b2}";
10984 else if (operands[2] == const1_rtx
10985 && (TARGET_SHIFT1 || optimize_size))
10986 return "sal{l}\t%0";
10988 return "sal{l}\t{%2, %0|%0, %2}";
10991 [(set (attr "type")
10992 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10994 (match_operand 0 "register_operand" ""))
10995 (match_operand 2 "const1_operand" ""))
10996 (const_string "alu")
10998 (const_string "ishift")))
10999 (set_attr "mode" "SI")])
11001 (define_insn "*ashlsi3_cmp_zext"
11004 (ashift:SI (match_operand:SI 1 "register_operand" "0")
11005 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11007 (set (match_operand:DI 0 "register_operand" "=r")
11008 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
11009 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11010 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11012 switch (get_attr_type (insn))
11015 if (operands[2] != const1_rtx)
11017 return "add{l}\t{%k0, %k0|%k0, %k0}";
11020 if (REG_P (operands[2]))
11021 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11022 else if (operands[2] == const1_rtx
11023 && (TARGET_SHIFT1 || optimize_size))
11024 return "sal{l}\t%k0";
11026 return "sal{l}\t{%2, %k0|%k0, %2}";
11029 [(set (attr "type")
11030 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11032 (match_operand 2 "const1_operand" ""))
11033 (const_string "alu")
11035 (const_string "ishift")))
11036 (set_attr "mode" "SI")])
11038 (define_expand "ashlhi3"
11039 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11040 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11041 (match_operand:QI 2 "nonmemory_operand" "")))
11042 (clobber (reg:CC FLAGS_REG))]
11043 "TARGET_HIMODE_MATH"
11044 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11046 (define_insn "*ashlhi3_1_lea"
11047 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11048 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11049 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11050 (clobber (reg:CC FLAGS_REG))]
11051 "!TARGET_PARTIAL_REG_STALL
11052 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11054 switch (get_attr_type (insn))
11059 if (operands[2] != const1_rtx)
11061 return "add{w}\t{%0, %0|%0, %0}";
11064 if (REG_P (operands[2]))
11065 return "sal{w}\t{%b2, %0|%0, %b2}";
11066 else if (operands[2] == const1_rtx
11067 && (TARGET_SHIFT1 || optimize_size))
11068 return "sal{w}\t%0";
11070 return "sal{w}\t{%2, %0|%0, %2}";
11073 [(set (attr "type")
11074 (cond [(eq_attr "alternative" "1")
11075 (const_string "lea")
11076 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11078 (match_operand 0 "register_operand" ""))
11079 (match_operand 2 "const1_operand" ""))
11080 (const_string "alu")
11082 (const_string "ishift")))
11083 (set_attr "mode" "HI,SI")])
11085 (define_insn "*ashlhi3_1"
11086 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11087 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11088 (match_operand:QI 2 "nonmemory_operand" "cI")))
11089 (clobber (reg:CC FLAGS_REG))]
11090 "TARGET_PARTIAL_REG_STALL
11091 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11093 switch (get_attr_type (insn))
11096 if (operands[2] != const1_rtx)
11098 return "add{w}\t{%0, %0|%0, %0}";
11101 if (REG_P (operands[2]))
11102 return "sal{w}\t{%b2, %0|%0, %b2}";
11103 else if (operands[2] == const1_rtx
11104 && (TARGET_SHIFT1 || optimize_size))
11105 return "sal{w}\t%0";
11107 return "sal{w}\t{%2, %0|%0, %2}";
11110 [(set (attr "type")
11111 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11113 (match_operand 0 "register_operand" ""))
11114 (match_operand 2 "const1_operand" ""))
11115 (const_string "alu")
11117 (const_string "ishift")))
11118 (set_attr "mode" "HI")])
11120 ;; This pattern can't accept a variable shift count, since shifts by
11121 ;; zero don't affect the flags. We assume that shifts by constant
11122 ;; zero are optimized away.
11123 (define_insn "*ashlhi3_cmp"
11126 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11127 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11129 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11130 (ashift:HI (match_dup 1) (match_dup 2)))]
11131 "ix86_match_ccmode (insn, CCGOCmode)
11132 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11134 switch (get_attr_type (insn))
11137 if (operands[2] != const1_rtx)
11139 return "add{w}\t{%0, %0|%0, %0}";
11142 if (REG_P (operands[2]))
11143 return "sal{w}\t{%b2, %0|%0, %b2}";
11144 else if (operands[2] == const1_rtx
11145 && (TARGET_SHIFT1 || optimize_size))
11146 return "sal{w}\t%0";
11148 return "sal{w}\t{%2, %0|%0, %2}";
11151 [(set (attr "type")
11152 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11154 (match_operand 0 "register_operand" ""))
11155 (match_operand 2 "const1_operand" ""))
11156 (const_string "alu")
11158 (const_string "ishift")))
11159 (set_attr "mode" "HI")])
11161 (define_expand "ashlqi3"
11162 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11163 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11164 (match_operand:QI 2 "nonmemory_operand" "")))
11165 (clobber (reg:CC FLAGS_REG))]
11166 "TARGET_QIMODE_MATH"
11167 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11169 ;; %%% Potential partial reg stall on alternative 2. What to do?
11171 (define_insn "*ashlqi3_1_lea"
11172 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11173 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11174 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11175 (clobber (reg:CC FLAGS_REG))]
11176 "!TARGET_PARTIAL_REG_STALL
11177 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11179 switch (get_attr_type (insn))
11184 if (operands[2] != const1_rtx)
11186 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11187 return "add{l}\t{%k0, %k0|%k0, %k0}";
11189 return "add{b}\t{%0, %0|%0, %0}";
11192 if (REG_P (operands[2]))
11194 if (get_attr_mode (insn) == MODE_SI)
11195 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11197 return "sal{b}\t{%b2, %0|%0, %b2}";
11199 else if (operands[2] == const1_rtx
11200 && (TARGET_SHIFT1 || optimize_size))
11202 if (get_attr_mode (insn) == MODE_SI)
11203 return "sal{l}\t%0";
11205 return "sal{b}\t%0";
11209 if (get_attr_mode (insn) == MODE_SI)
11210 return "sal{l}\t{%2, %k0|%k0, %2}";
11212 return "sal{b}\t{%2, %0|%0, %2}";
11216 [(set (attr "type")
11217 (cond [(eq_attr "alternative" "2")
11218 (const_string "lea")
11219 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11221 (match_operand 0 "register_operand" ""))
11222 (match_operand 2 "const1_operand" ""))
11223 (const_string "alu")
11225 (const_string "ishift")))
11226 (set_attr "mode" "QI,SI,SI")])
11228 (define_insn "*ashlqi3_1"
11229 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11230 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11231 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11232 (clobber (reg:CC FLAGS_REG))]
11233 "TARGET_PARTIAL_REG_STALL
11234 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11236 switch (get_attr_type (insn))
11239 if (operands[2] != const1_rtx)
11241 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11242 return "add{l}\t{%k0, %k0|%k0, %k0}";
11244 return "add{b}\t{%0, %0|%0, %0}";
11247 if (REG_P (operands[2]))
11249 if (get_attr_mode (insn) == MODE_SI)
11250 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11252 return "sal{b}\t{%b2, %0|%0, %b2}";
11254 else if (operands[2] == const1_rtx
11255 && (TARGET_SHIFT1 || optimize_size))
11257 if (get_attr_mode (insn) == MODE_SI)
11258 return "sal{l}\t%0";
11260 return "sal{b}\t%0";
11264 if (get_attr_mode (insn) == MODE_SI)
11265 return "sal{l}\t{%2, %k0|%k0, %2}";
11267 return "sal{b}\t{%2, %0|%0, %2}";
11271 [(set (attr "type")
11272 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11274 (match_operand 0 "register_operand" ""))
11275 (match_operand 2 "const1_operand" ""))
11276 (const_string "alu")
11278 (const_string "ishift")))
11279 (set_attr "mode" "QI,SI")])
11281 ;; This pattern can't accept a variable shift count, since shifts by
11282 ;; zero don't affect the flags. We assume that shifts by constant
11283 ;; zero are optimized away.
11284 (define_insn "*ashlqi3_cmp"
11287 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11288 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11290 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11291 (ashift:QI (match_dup 1) (match_dup 2)))]
11292 "ix86_match_ccmode (insn, CCGOCmode)
11293 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11295 switch (get_attr_type (insn))
11298 if (operands[2] != const1_rtx)
11300 return "add{b}\t{%0, %0|%0, %0}";
11303 if (REG_P (operands[2]))
11304 return "sal{b}\t{%b2, %0|%0, %b2}";
11305 else if (operands[2] == const1_rtx
11306 && (TARGET_SHIFT1 || optimize_size))
11307 return "sal{b}\t%0";
11309 return "sal{b}\t{%2, %0|%0, %2}";
11312 [(set (attr "type")
11313 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11315 (match_operand 0 "register_operand" ""))
11316 (match_operand 2 "const1_operand" ""))
11317 (const_string "alu")
11319 (const_string "ishift")))
11320 (set_attr "mode" "QI")])
11322 ;; See comment above `ashldi3' about how this works.
11324 (define_expand "ashrdi3"
11325 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11326 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11327 (match_operand:QI 2 "nonmemory_operand" "")))
11328 (clobber (reg:CC FLAGS_REG))])]
11331 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11333 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11336 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11340 (define_insn "ashrdi3_63_rex64"
11341 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11342 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11343 (match_operand:DI 2 "const_int_operand" "i,i")))
11344 (clobber (reg:CC FLAGS_REG))]
11345 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11346 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11349 sar{q}\t{%2, %0|%0, %2}"
11350 [(set_attr "type" "imovx,ishift")
11351 (set_attr "prefix_0f" "0,*")
11352 (set_attr "length_immediate" "0,*")
11353 (set_attr "modrm" "0,1")
11354 (set_attr "mode" "DI")])
11356 (define_insn "*ashrdi3_1_one_bit_rex64"
11357 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11358 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11359 (match_operand:QI 2 "const1_operand" "")))
11360 (clobber (reg:CC FLAGS_REG))]
11361 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11362 && (TARGET_SHIFT1 || optimize_size)"
11364 [(set_attr "type" "ishift")
11365 (set (attr "length")
11366 (if_then_else (match_operand:DI 0 "register_operand" "")
11368 (const_string "*")))])
11370 (define_insn "*ashrdi3_1_rex64"
11371 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11372 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11373 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11374 (clobber (reg:CC FLAGS_REG))]
11375 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11377 sar{q}\t{%2, %0|%0, %2}
11378 sar{q}\t{%b2, %0|%0, %b2}"
11379 [(set_attr "type" "ishift")
11380 (set_attr "mode" "DI")])
11382 ;; This pattern can't accept a variable shift count, since shifts by
11383 ;; zero don't affect the flags. We assume that shifts by constant
11384 ;; zero are optimized away.
11385 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11388 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11389 (match_operand:QI 2 "const1_operand" ""))
11391 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11392 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11393 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11394 && (TARGET_SHIFT1 || optimize_size)
11395 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11397 [(set_attr "type" "ishift")
11398 (set (attr "length")
11399 (if_then_else (match_operand:DI 0 "register_operand" "")
11401 (const_string "*")))])
11403 ;; This pattern can't accept a variable shift count, since shifts by
11404 ;; zero don't affect the flags. We assume that shifts by constant
11405 ;; zero are optimized away.
11406 (define_insn "*ashrdi3_cmp_rex64"
11409 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11410 (match_operand:QI 2 "const_int_operand" "n"))
11412 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11413 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11414 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11415 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11416 "sar{q}\t{%2, %0|%0, %2}"
11417 [(set_attr "type" "ishift")
11418 (set_attr "mode" "DI")])
11421 (define_insn "ashrdi3_1"
11422 [(set (match_operand:DI 0 "register_operand" "=r")
11423 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11424 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11425 (clobber (match_scratch:SI 3 "=&r"))
11426 (clobber (reg:CC FLAGS_REG))]
11427 "!TARGET_64BIT && TARGET_CMOVE"
11429 [(set_attr "type" "multi")])
11431 (define_insn "*ashrdi3_2"
11432 [(set (match_operand:DI 0 "register_operand" "=r")
11433 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11434 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11435 (clobber (reg:CC FLAGS_REG))]
11438 [(set_attr "type" "multi")])
11441 [(set (match_operand:DI 0 "register_operand" "")
11442 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11443 (match_operand:QI 2 "nonmemory_operand" "")))
11444 (clobber (match_scratch:SI 3 ""))
11445 (clobber (reg:CC FLAGS_REG))]
11446 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11448 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11451 [(set (match_operand:DI 0 "register_operand" "")
11452 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11453 (match_operand:QI 2 "nonmemory_operand" "")))
11454 (clobber (reg:CC FLAGS_REG))]
11455 "!TARGET_64BIT && reload_completed"
11457 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11459 (define_insn "x86_shrd_1"
11460 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11461 (ior:SI (ashiftrt:SI (match_dup 0)
11462 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11463 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11464 (minus:QI (const_int 32) (match_dup 2)))))
11465 (clobber (reg:CC FLAGS_REG))]
11468 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11469 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11470 [(set_attr "type" "ishift")
11471 (set_attr "prefix_0f" "1")
11472 (set_attr "pent_pair" "np")
11473 (set_attr "mode" "SI")])
11475 (define_expand "x86_shift_adj_3"
11476 [(use (match_operand:SI 0 "register_operand" ""))
11477 (use (match_operand:SI 1 "register_operand" ""))
11478 (use (match_operand:QI 2 "register_operand" ""))]
11481 rtx label = gen_label_rtx ();
11484 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11486 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11487 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11488 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11489 gen_rtx_LABEL_REF (VOIDmode, label),
11491 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11492 JUMP_LABEL (tmp) = label;
11494 emit_move_insn (operands[0], operands[1]);
11495 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11497 emit_label (label);
11498 LABEL_NUSES (label) = 1;
11503 (define_insn "ashrsi3_31"
11504 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11505 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11506 (match_operand:SI 2 "const_int_operand" "i,i")))
11507 (clobber (reg:CC FLAGS_REG))]
11508 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11509 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11512 sar{l}\t{%2, %0|%0, %2}"
11513 [(set_attr "type" "imovx,ishift")
11514 (set_attr "prefix_0f" "0,*")
11515 (set_attr "length_immediate" "0,*")
11516 (set_attr "modrm" "0,1")
11517 (set_attr "mode" "SI")])
11519 (define_insn "*ashrsi3_31_zext"
11520 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11521 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11522 (match_operand:SI 2 "const_int_operand" "i,i"))))
11523 (clobber (reg:CC FLAGS_REG))]
11524 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11525 && INTVAL (operands[2]) == 31
11526 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11529 sar{l}\t{%2, %k0|%k0, %2}"
11530 [(set_attr "type" "imovx,ishift")
11531 (set_attr "prefix_0f" "0,*")
11532 (set_attr "length_immediate" "0,*")
11533 (set_attr "modrm" "0,1")
11534 (set_attr "mode" "SI")])
11536 (define_expand "ashrsi3"
11537 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11538 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11539 (match_operand:QI 2 "nonmemory_operand" "")))
11540 (clobber (reg:CC FLAGS_REG))]
11542 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11544 (define_insn "*ashrsi3_1_one_bit"
11545 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11546 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11547 (match_operand:QI 2 "const1_operand" "")))
11548 (clobber (reg:CC FLAGS_REG))]
11549 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11550 && (TARGET_SHIFT1 || optimize_size)"
11552 [(set_attr "type" "ishift")
11553 (set (attr "length")
11554 (if_then_else (match_operand:SI 0 "register_operand" "")
11556 (const_string "*")))])
11558 (define_insn "*ashrsi3_1_one_bit_zext"
11559 [(set (match_operand:DI 0 "register_operand" "=r")
11560 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11561 (match_operand:QI 2 "const1_operand" ""))))
11562 (clobber (reg:CC FLAGS_REG))]
11563 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11564 && (TARGET_SHIFT1 || optimize_size)"
11566 [(set_attr "type" "ishift")
11567 (set_attr "length" "2")])
11569 (define_insn "*ashrsi3_1"
11570 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11571 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11572 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11573 (clobber (reg:CC FLAGS_REG))]
11574 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11576 sar{l}\t{%2, %0|%0, %2}
11577 sar{l}\t{%b2, %0|%0, %b2}"
11578 [(set_attr "type" "ishift")
11579 (set_attr "mode" "SI")])
11581 (define_insn "*ashrsi3_1_zext"
11582 [(set (match_operand:DI 0 "register_operand" "=r,r")
11583 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11584 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11585 (clobber (reg:CC FLAGS_REG))]
11586 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11588 sar{l}\t{%2, %k0|%k0, %2}
11589 sar{l}\t{%b2, %k0|%k0, %b2}"
11590 [(set_attr "type" "ishift")
11591 (set_attr "mode" "SI")])
11593 ;; This pattern can't accept a variable shift count, since shifts by
11594 ;; zero don't affect the flags. We assume that shifts by constant
11595 ;; zero are optimized away.
11596 (define_insn "*ashrsi3_one_bit_cmp"
11599 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11600 (match_operand:QI 2 "const1_operand" ""))
11602 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11603 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11604 "ix86_match_ccmode (insn, CCGOCmode)
11605 && (TARGET_SHIFT1 || optimize_size)
11606 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11608 [(set_attr "type" "ishift")
11609 (set (attr "length")
11610 (if_then_else (match_operand:SI 0 "register_operand" "")
11612 (const_string "*")))])
11614 (define_insn "*ashrsi3_one_bit_cmp_zext"
11617 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11618 (match_operand:QI 2 "const1_operand" ""))
11620 (set (match_operand:DI 0 "register_operand" "=r")
11621 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11622 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11623 && (TARGET_SHIFT1 || optimize_size)
11624 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11626 [(set_attr "type" "ishift")
11627 (set_attr "length" "2")])
11629 ;; This pattern can't accept a variable shift count, since shifts by
11630 ;; zero don't affect the flags. We assume that shifts by constant
11631 ;; zero are optimized away.
11632 (define_insn "*ashrsi3_cmp"
11635 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11636 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11638 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11639 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11640 "ix86_match_ccmode (insn, CCGOCmode)
11641 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11642 "sar{l}\t{%2, %0|%0, %2}"
11643 [(set_attr "type" "ishift")
11644 (set_attr "mode" "SI")])
11646 (define_insn "*ashrsi3_cmp_zext"
11649 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11650 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11652 (set (match_operand:DI 0 "register_operand" "=r")
11653 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11654 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11655 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11656 "sar{l}\t{%2, %k0|%k0, %2}"
11657 [(set_attr "type" "ishift")
11658 (set_attr "mode" "SI")])
11660 (define_expand "ashrhi3"
11661 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11662 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11663 (match_operand:QI 2 "nonmemory_operand" "")))
11664 (clobber (reg:CC FLAGS_REG))]
11665 "TARGET_HIMODE_MATH"
11666 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11668 (define_insn "*ashrhi3_1_one_bit"
11669 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11670 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11671 (match_operand:QI 2 "const1_operand" "")))
11672 (clobber (reg:CC FLAGS_REG))]
11673 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11674 && (TARGET_SHIFT1 || optimize_size)"
11676 [(set_attr "type" "ishift")
11677 (set (attr "length")
11678 (if_then_else (match_operand 0 "register_operand" "")
11680 (const_string "*")))])
11682 (define_insn "*ashrhi3_1"
11683 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11684 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11685 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11686 (clobber (reg:CC FLAGS_REG))]
11687 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11689 sar{w}\t{%2, %0|%0, %2}
11690 sar{w}\t{%b2, %0|%0, %b2}"
11691 [(set_attr "type" "ishift")
11692 (set_attr "mode" "HI")])
11694 ;; This pattern can't accept a variable shift count, since shifts by
11695 ;; zero don't affect the flags. We assume that shifts by constant
11696 ;; zero are optimized away.
11697 (define_insn "*ashrhi3_one_bit_cmp"
11700 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11701 (match_operand:QI 2 "const1_operand" ""))
11703 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11704 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11705 "ix86_match_ccmode (insn, CCGOCmode)
11706 && (TARGET_SHIFT1 || optimize_size)
11707 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11709 [(set_attr "type" "ishift")
11710 (set (attr "length")
11711 (if_then_else (match_operand 0 "register_operand" "")
11713 (const_string "*")))])
11715 ;; This pattern can't accept a variable shift count, since shifts by
11716 ;; zero don't affect the flags. We assume that shifts by constant
11717 ;; zero are optimized away.
11718 (define_insn "*ashrhi3_cmp"
11721 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11722 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11724 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11725 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11726 "ix86_match_ccmode (insn, CCGOCmode)
11727 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11728 "sar{w}\t{%2, %0|%0, %2}"
11729 [(set_attr "type" "ishift")
11730 (set_attr "mode" "HI")])
11732 (define_expand "ashrqi3"
11733 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11734 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11735 (match_operand:QI 2 "nonmemory_operand" "")))
11736 (clobber (reg:CC FLAGS_REG))]
11737 "TARGET_QIMODE_MATH"
11738 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11740 (define_insn "*ashrqi3_1_one_bit"
11741 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11742 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11743 (match_operand:QI 2 "const1_operand" "")))
11744 (clobber (reg:CC FLAGS_REG))]
11745 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11746 && (TARGET_SHIFT1 || optimize_size)"
11748 [(set_attr "type" "ishift")
11749 (set (attr "length")
11750 (if_then_else (match_operand 0 "register_operand" "")
11752 (const_string "*")))])
11754 (define_insn "*ashrqi3_1_one_bit_slp"
11755 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11756 (ashiftrt:QI (match_dup 0)
11757 (match_operand:QI 1 "const1_operand" "")))
11758 (clobber (reg:CC FLAGS_REG))]
11759 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11760 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11761 && (TARGET_SHIFT1 || optimize_size)"
11763 [(set_attr "type" "ishift1")
11764 (set (attr "length")
11765 (if_then_else (match_operand 0 "register_operand" "")
11767 (const_string "*")))])
11769 (define_insn "*ashrqi3_1"
11770 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11771 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11772 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11773 (clobber (reg:CC FLAGS_REG))]
11774 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11776 sar{b}\t{%2, %0|%0, %2}
11777 sar{b}\t{%b2, %0|%0, %b2}"
11778 [(set_attr "type" "ishift")
11779 (set_attr "mode" "QI")])
11781 (define_insn "*ashrqi3_1_slp"
11782 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11783 (ashiftrt:QI (match_dup 0)
11784 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11785 (clobber (reg:CC FLAGS_REG))]
11786 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11787 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11789 sar{b}\t{%1, %0|%0, %1}
11790 sar{b}\t{%b1, %0|%0, %b1}"
11791 [(set_attr "type" "ishift1")
11792 (set_attr "mode" "QI")])
11794 ;; This pattern can't accept a variable shift count, since shifts by
11795 ;; zero don't affect the flags. We assume that shifts by constant
11796 ;; zero are optimized away.
11797 (define_insn "*ashrqi3_one_bit_cmp"
11800 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11801 (match_operand:QI 2 "const1_operand" "I"))
11803 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11804 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11805 "ix86_match_ccmode (insn, CCGOCmode)
11806 && (TARGET_SHIFT1 || optimize_size)
11807 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11809 [(set_attr "type" "ishift")
11810 (set (attr "length")
11811 (if_then_else (match_operand 0 "register_operand" "")
11813 (const_string "*")))])
11815 ;; This pattern can't accept a variable shift count, since shifts by
11816 ;; zero don't affect the flags. We assume that shifts by constant
11817 ;; zero are optimized away.
11818 (define_insn "*ashrqi3_cmp"
11821 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11822 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11824 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11825 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11826 "ix86_match_ccmode (insn, CCGOCmode)
11827 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11828 "sar{b}\t{%2, %0|%0, %2}"
11829 [(set_attr "type" "ishift")
11830 (set_attr "mode" "QI")])
11832 ;; Logical shift instructions
11834 ;; See comment above `ashldi3' about how this works.
11836 (define_expand "lshrdi3"
11837 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11838 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11839 (match_operand:QI 2 "nonmemory_operand" "")))
11840 (clobber (reg:CC FLAGS_REG))])]
11843 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11845 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11848 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11852 (define_insn "*lshrdi3_1_one_bit_rex64"
11853 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11854 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11855 (match_operand:QI 2 "const1_operand" "")))
11856 (clobber (reg:CC FLAGS_REG))]
11857 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11858 && (TARGET_SHIFT1 || optimize_size)"
11860 [(set_attr "type" "ishift")
11861 (set (attr "length")
11862 (if_then_else (match_operand:DI 0 "register_operand" "")
11864 (const_string "*")))])
11866 (define_insn "*lshrdi3_1_rex64"
11867 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11868 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11869 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11870 (clobber (reg:CC FLAGS_REG))]
11871 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11873 shr{q}\t{%2, %0|%0, %2}
11874 shr{q}\t{%b2, %0|%0, %b2}"
11875 [(set_attr "type" "ishift")
11876 (set_attr "mode" "DI")])
11878 ;; This pattern can't accept a variable shift count, since shifts by
11879 ;; zero don't affect the flags. We assume that shifts by constant
11880 ;; zero are optimized away.
11881 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11884 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11885 (match_operand:QI 2 "const1_operand" ""))
11887 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11888 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11889 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11890 && (TARGET_SHIFT1 || optimize_size)
11891 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11893 [(set_attr "type" "ishift")
11894 (set (attr "length")
11895 (if_then_else (match_operand:DI 0 "register_operand" "")
11897 (const_string "*")))])
11899 ;; This pattern can't accept a variable shift count, since shifts by
11900 ;; zero don't affect the flags. We assume that shifts by constant
11901 ;; zero are optimized away.
11902 (define_insn "*lshrdi3_cmp_rex64"
11905 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11906 (match_operand:QI 2 "const_int_operand" "e"))
11908 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11909 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11910 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11911 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11912 "shr{q}\t{%2, %0|%0, %2}"
11913 [(set_attr "type" "ishift")
11914 (set_attr "mode" "DI")])
11916 (define_insn "lshrdi3_1"
11917 [(set (match_operand:DI 0 "register_operand" "=r")
11918 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11919 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11920 (clobber (match_scratch:SI 3 "=&r"))
11921 (clobber (reg:CC FLAGS_REG))]
11922 "!TARGET_64BIT && TARGET_CMOVE"
11924 [(set_attr "type" "multi")])
11926 (define_insn "*lshrdi3_2"
11927 [(set (match_operand:DI 0 "register_operand" "=r")
11928 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11929 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11930 (clobber (reg:CC FLAGS_REG))]
11933 [(set_attr "type" "multi")])
11936 [(set (match_operand:DI 0 "register_operand" "")
11937 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11938 (match_operand:QI 2 "nonmemory_operand" "")))
11939 (clobber (match_scratch:SI 3 ""))
11940 (clobber (reg:CC FLAGS_REG))]
11941 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11943 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11946 [(set (match_operand:DI 0 "register_operand" "")
11947 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11948 (match_operand:QI 2 "nonmemory_operand" "")))
11949 (clobber (reg:CC FLAGS_REG))]
11950 "!TARGET_64BIT && reload_completed"
11952 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11954 (define_expand "lshrsi3"
11955 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11956 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11957 (match_operand:QI 2 "nonmemory_operand" "")))
11958 (clobber (reg:CC FLAGS_REG))]
11960 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11962 (define_insn "*lshrsi3_1_one_bit"
11963 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11964 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11965 (match_operand:QI 2 "const1_operand" "")))
11966 (clobber (reg:CC FLAGS_REG))]
11967 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11968 && (TARGET_SHIFT1 || optimize_size)"
11970 [(set_attr "type" "ishift")
11971 (set (attr "length")
11972 (if_then_else (match_operand:SI 0 "register_operand" "")
11974 (const_string "*")))])
11976 (define_insn "*lshrsi3_1_one_bit_zext"
11977 [(set (match_operand:DI 0 "register_operand" "=r")
11978 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11979 (match_operand:QI 2 "const1_operand" "")))
11980 (clobber (reg:CC FLAGS_REG))]
11981 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11982 && (TARGET_SHIFT1 || optimize_size)"
11984 [(set_attr "type" "ishift")
11985 (set_attr "length" "2")])
11987 (define_insn "*lshrsi3_1"
11988 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11989 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11990 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11991 (clobber (reg:CC FLAGS_REG))]
11992 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11994 shr{l}\t{%2, %0|%0, %2}
11995 shr{l}\t{%b2, %0|%0, %b2}"
11996 [(set_attr "type" "ishift")
11997 (set_attr "mode" "SI")])
11999 (define_insn "*lshrsi3_1_zext"
12000 [(set (match_operand:DI 0 "register_operand" "=r,r")
12002 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12003 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12004 (clobber (reg:CC FLAGS_REG))]
12005 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12007 shr{l}\t{%2, %k0|%k0, %2}
12008 shr{l}\t{%b2, %k0|%k0, %b2}"
12009 [(set_attr "type" "ishift")
12010 (set_attr "mode" "SI")])
12012 ;; This pattern can't accept a variable shift count, since shifts by
12013 ;; zero don't affect the flags. We assume that shifts by constant
12014 ;; zero are optimized away.
12015 (define_insn "*lshrsi3_one_bit_cmp"
12018 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12019 (match_operand:QI 2 "const1_operand" ""))
12021 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12022 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12023 "ix86_match_ccmode (insn, CCGOCmode)
12024 && (TARGET_SHIFT1 || optimize_size)
12025 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12027 [(set_attr "type" "ishift")
12028 (set (attr "length")
12029 (if_then_else (match_operand:SI 0 "register_operand" "")
12031 (const_string "*")))])
12033 (define_insn "*lshrsi3_cmp_one_bit_zext"
12036 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12037 (match_operand:QI 2 "const1_operand" ""))
12039 (set (match_operand:DI 0 "register_operand" "=r")
12040 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12041 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12042 && (TARGET_SHIFT1 || optimize_size)
12043 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12045 [(set_attr "type" "ishift")
12046 (set_attr "length" "2")])
12048 ;; This pattern can't accept a variable shift count, since shifts by
12049 ;; zero don't affect the flags. We assume that shifts by constant
12050 ;; zero are optimized away.
12051 (define_insn "*lshrsi3_cmp"
12054 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12055 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12057 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12058 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12059 "ix86_match_ccmode (insn, CCGOCmode)
12060 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12061 "shr{l}\t{%2, %0|%0, %2}"
12062 [(set_attr "type" "ishift")
12063 (set_attr "mode" "SI")])
12065 (define_insn "*lshrsi3_cmp_zext"
12068 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12069 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12071 (set (match_operand:DI 0 "register_operand" "=r")
12072 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12073 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12074 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12075 "shr{l}\t{%2, %k0|%k0, %2}"
12076 [(set_attr "type" "ishift")
12077 (set_attr "mode" "SI")])
12079 (define_expand "lshrhi3"
12080 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12081 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12082 (match_operand:QI 2 "nonmemory_operand" "")))
12083 (clobber (reg:CC FLAGS_REG))]
12084 "TARGET_HIMODE_MATH"
12085 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12087 (define_insn "*lshrhi3_1_one_bit"
12088 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12089 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12090 (match_operand:QI 2 "const1_operand" "")))
12091 (clobber (reg:CC FLAGS_REG))]
12092 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12093 && (TARGET_SHIFT1 || optimize_size)"
12095 [(set_attr "type" "ishift")
12096 (set (attr "length")
12097 (if_then_else (match_operand 0 "register_operand" "")
12099 (const_string "*")))])
12101 (define_insn "*lshrhi3_1"
12102 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12103 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12104 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12105 (clobber (reg:CC FLAGS_REG))]
12106 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12108 shr{w}\t{%2, %0|%0, %2}
12109 shr{w}\t{%b2, %0|%0, %b2}"
12110 [(set_attr "type" "ishift")
12111 (set_attr "mode" "HI")])
12113 ;; This pattern can't accept a variable shift count, since shifts by
12114 ;; zero don't affect the flags. We assume that shifts by constant
12115 ;; zero are optimized away.
12116 (define_insn "*lshrhi3_one_bit_cmp"
12119 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12120 (match_operand:QI 2 "const1_operand" ""))
12122 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12123 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12124 "ix86_match_ccmode (insn, CCGOCmode)
12125 && (TARGET_SHIFT1 || optimize_size)
12126 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12128 [(set_attr "type" "ishift")
12129 (set (attr "length")
12130 (if_then_else (match_operand:SI 0 "register_operand" "")
12132 (const_string "*")))])
12134 ;; This pattern can't accept a variable shift count, since shifts by
12135 ;; zero don't affect the flags. We assume that shifts by constant
12136 ;; zero are optimized away.
12137 (define_insn "*lshrhi3_cmp"
12140 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12141 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12143 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12144 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12145 "ix86_match_ccmode (insn, CCGOCmode)
12146 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12147 "shr{w}\t{%2, %0|%0, %2}"
12148 [(set_attr "type" "ishift")
12149 (set_attr "mode" "HI")])
12151 (define_expand "lshrqi3"
12152 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12153 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12154 (match_operand:QI 2 "nonmemory_operand" "")))
12155 (clobber (reg:CC FLAGS_REG))]
12156 "TARGET_QIMODE_MATH"
12157 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12159 (define_insn "*lshrqi3_1_one_bit"
12160 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12161 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12162 (match_operand:QI 2 "const1_operand" "")))
12163 (clobber (reg:CC FLAGS_REG))]
12164 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12165 && (TARGET_SHIFT1 || optimize_size)"
12167 [(set_attr "type" "ishift")
12168 (set (attr "length")
12169 (if_then_else (match_operand 0 "register_operand" "")
12171 (const_string "*")))])
12173 (define_insn "*lshrqi3_1_one_bit_slp"
12174 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12175 (lshiftrt:QI (match_dup 0)
12176 (match_operand:QI 1 "const1_operand" "")))
12177 (clobber (reg:CC FLAGS_REG))]
12178 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12179 && (TARGET_SHIFT1 || optimize_size)"
12181 [(set_attr "type" "ishift1")
12182 (set (attr "length")
12183 (if_then_else (match_operand 0 "register_operand" "")
12185 (const_string "*")))])
12187 (define_insn "*lshrqi3_1"
12188 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12189 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12190 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12191 (clobber (reg:CC FLAGS_REG))]
12192 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12194 shr{b}\t{%2, %0|%0, %2}
12195 shr{b}\t{%b2, %0|%0, %b2}"
12196 [(set_attr "type" "ishift")
12197 (set_attr "mode" "QI")])
12199 (define_insn "*lshrqi3_1_slp"
12200 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12201 (lshiftrt:QI (match_dup 0)
12202 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12203 (clobber (reg:CC FLAGS_REG))]
12204 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12205 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12207 shr{b}\t{%1, %0|%0, %1}
12208 shr{b}\t{%b1, %0|%0, %b1}"
12209 [(set_attr "type" "ishift1")
12210 (set_attr "mode" "QI")])
12212 ;; This pattern can't accept a variable shift count, since shifts by
12213 ;; zero don't affect the flags. We assume that shifts by constant
12214 ;; zero are optimized away.
12215 (define_insn "*lshrqi2_one_bit_cmp"
12218 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12219 (match_operand:QI 2 "const1_operand" ""))
12221 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12222 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12223 "ix86_match_ccmode (insn, CCGOCmode)
12224 && (TARGET_SHIFT1 || optimize_size)
12225 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12227 [(set_attr "type" "ishift")
12228 (set (attr "length")
12229 (if_then_else (match_operand:SI 0 "register_operand" "")
12231 (const_string "*")))])
12233 ;; This pattern can't accept a variable shift count, since shifts by
12234 ;; zero don't affect the flags. We assume that shifts by constant
12235 ;; zero are optimized away.
12236 (define_insn "*lshrqi2_cmp"
12239 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12240 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12242 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12243 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12244 "ix86_match_ccmode (insn, CCGOCmode)
12245 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12246 "shr{b}\t{%2, %0|%0, %2}"
12247 [(set_attr "type" "ishift")
12248 (set_attr "mode" "QI")])
12250 ;; Rotate instructions
12252 (define_expand "rotldi3"
12253 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12254 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12255 (match_operand:QI 2 "nonmemory_operand" "")))
12256 (clobber (reg:CC FLAGS_REG))]
12258 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12260 (define_insn "*rotlsi3_1_one_bit_rex64"
12261 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12262 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12263 (match_operand:QI 2 "const1_operand" "")))
12264 (clobber (reg:CC FLAGS_REG))]
12265 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12266 && (TARGET_SHIFT1 || optimize_size)"
12268 [(set_attr "type" "rotate")
12269 (set (attr "length")
12270 (if_then_else (match_operand:DI 0 "register_operand" "")
12272 (const_string "*")))])
12274 (define_insn "*rotldi3_1_rex64"
12275 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12276 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12277 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12278 (clobber (reg:CC FLAGS_REG))]
12279 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12281 rol{q}\t{%2, %0|%0, %2}
12282 rol{q}\t{%b2, %0|%0, %b2}"
12283 [(set_attr "type" "rotate")
12284 (set_attr "mode" "DI")])
12286 (define_expand "rotlsi3"
12287 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12288 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12289 (match_operand:QI 2 "nonmemory_operand" "")))
12290 (clobber (reg:CC FLAGS_REG))]
12292 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12294 (define_insn "*rotlsi3_1_one_bit"
12295 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12296 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12297 (match_operand:QI 2 "const1_operand" "")))
12298 (clobber (reg:CC FLAGS_REG))]
12299 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12300 && (TARGET_SHIFT1 || optimize_size)"
12302 [(set_attr "type" "rotate")
12303 (set (attr "length")
12304 (if_then_else (match_operand:SI 0 "register_operand" "")
12306 (const_string "*")))])
12308 (define_insn "*rotlsi3_1_one_bit_zext"
12309 [(set (match_operand:DI 0 "register_operand" "=r")
12311 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12312 (match_operand:QI 2 "const1_operand" ""))))
12313 (clobber (reg:CC FLAGS_REG))]
12314 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12315 && (TARGET_SHIFT1 || optimize_size)"
12317 [(set_attr "type" "rotate")
12318 (set_attr "length" "2")])
12320 (define_insn "*rotlsi3_1"
12321 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12322 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12323 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12324 (clobber (reg:CC FLAGS_REG))]
12325 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12327 rol{l}\t{%2, %0|%0, %2}
12328 rol{l}\t{%b2, %0|%0, %b2}"
12329 [(set_attr "type" "rotate")
12330 (set_attr "mode" "SI")])
12332 (define_insn "*rotlsi3_1_zext"
12333 [(set (match_operand:DI 0 "register_operand" "=r,r")
12335 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12336 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12337 (clobber (reg:CC FLAGS_REG))]
12338 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12340 rol{l}\t{%2, %k0|%k0, %2}
12341 rol{l}\t{%b2, %k0|%k0, %b2}"
12342 [(set_attr "type" "rotate")
12343 (set_attr "mode" "SI")])
12345 (define_expand "rotlhi3"
12346 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12347 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12348 (match_operand:QI 2 "nonmemory_operand" "")))
12349 (clobber (reg:CC FLAGS_REG))]
12350 "TARGET_HIMODE_MATH"
12351 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12353 (define_insn "*rotlhi3_1_one_bit"
12354 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12355 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12356 (match_operand:QI 2 "const1_operand" "")))
12357 (clobber (reg:CC FLAGS_REG))]
12358 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12359 && (TARGET_SHIFT1 || optimize_size)"
12361 [(set_attr "type" "rotate")
12362 (set (attr "length")
12363 (if_then_else (match_operand 0 "register_operand" "")
12365 (const_string "*")))])
12367 (define_insn "*rotlhi3_1"
12368 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12369 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12370 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12371 (clobber (reg:CC FLAGS_REG))]
12372 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12374 rol{w}\t{%2, %0|%0, %2}
12375 rol{w}\t{%b2, %0|%0, %b2}"
12376 [(set_attr "type" "rotate")
12377 (set_attr "mode" "HI")])
12379 (define_expand "rotlqi3"
12380 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12381 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12382 (match_operand:QI 2 "nonmemory_operand" "")))
12383 (clobber (reg:CC FLAGS_REG))]
12384 "TARGET_QIMODE_MATH"
12385 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12387 (define_insn "*rotlqi3_1_one_bit_slp"
12388 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12389 (rotate:QI (match_dup 0)
12390 (match_operand:QI 1 "const1_operand" "")))
12391 (clobber (reg:CC FLAGS_REG))]
12392 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12393 && (TARGET_SHIFT1 || optimize_size)"
12395 [(set_attr "type" "rotate1")
12396 (set (attr "length")
12397 (if_then_else (match_operand 0 "register_operand" "")
12399 (const_string "*")))])
12401 (define_insn "*rotlqi3_1_one_bit"
12402 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12403 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12404 (match_operand:QI 2 "const1_operand" "")))
12405 (clobber (reg:CC FLAGS_REG))]
12406 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12407 && (TARGET_SHIFT1 || optimize_size)"
12409 [(set_attr "type" "rotate")
12410 (set (attr "length")
12411 (if_then_else (match_operand 0 "register_operand" "")
12413 (const_string "*")))])
12415 (define_insn "*rotlqi3_1_slp"
12416 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12417 (rotate:QI (match_dup 0)
12418 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12419 (clobber (reg:CC FLAGS_REG))]
12420 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12421 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12423 rol{b}\t{%1, %0|%0, %1}
12424 rol{b}\t{%b1, %0|%0, %b1}"
12425 [(set_attr "type" "rotate1")
12426 (set_attr "mode" "QI")])
12428 (define_insn "*rotlqi3_1"
12429 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12430 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12431 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12432 (clobber (reg:CC FLAGS_REG))]
12433 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12435 rol{b}\t{%2, %0|%0, %2}
12436 rol{b}\t{%b2, %0|%0, %b2}"
12437 [(set_attr "type" "rotate")
12438 (set_attr "mode" "QI")])
12440 (define_expand "rotrdi3"
12441 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12442 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12443 (match_operand:QI 2 "nonmemory_operand" "")))
12444 (clobber (reg:CC FLAGS_REG))]
12446 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12448 (define_insn "*rotrdi3_1_one_bit_rex64"
12449 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12450 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12451 (match_operand:QI 2 "const1_operand" "")))
12452 (clobber (reg:CC FLAGS_REG))]
12453 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12454 && (TARGET_SHIFT1 || optimize_size)"
12456 [(set_attr "type" "rotate")
12457 (set (attr "length")
12458 (if_then_else (match_operand:DI 0 "register_operand" "")
12460 (const_string "*")))])
12462 (define_insn "*rotrdi3_1_rex64"
12463 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12464 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12465 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12466 (clobber (reg:CC FLAGS_REG))]
12467 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12469 ror{q}\t{%2, %0|%0, %2}
12470 ror{q}\t{%b2, %0|%0, %b2}"
12471 [(set_attr "type" "rotate")
12472 (set_attr "mode" "DI")])
12474 (define_expand "rotrsi3"
12475 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12476 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12477 (match_operand:QI 2 "nonmemory_operand" "")))
12478 (clobber (reg:CC FLAGS_REG))]
12480 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12482 (define_insn "*rotrsi3_1_one_bit"
12483 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12484 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12485 (match_operand:QI 2 "const1_operand" "")))
12486 (clobber (reg:CC FLAGS_REG))]
12487 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12488 && (TARGET_SHIFT1 || optimize_size)"
12490 [(set_attr "type" "rotate")
12491 (set (attr "length")
12492 (if_then_else (match_operand:SI 0 "register_operand" "")
12494 (const_string "*")))])
12496 (define_insn "*rotrsi3_1_one_bit_zext"
12497 [(set (match_operand:DI 0 "register_operand" "=r")
12499 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12500 (match_operand:QI 2 "const1_operand" ""))))
12501 (clobber (reg:CC FLAGS_REG))]
12502 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12503 && (TARGET_SHIFT1 || optimize_size)"
12505 [(set_attr "type" "rotate")
12506 (set (attr "length")
12507 (if_then_else (match_operand:SI 0 "register_operand" "")
12509 (const_string "*")))])
12511 (define_insn "*rotrsi3_1"
12512 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12513 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12514 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12515 (clobber (reg:CC FLAGS_REG))]
12516 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12518 ror{l}\t{%2, %0|%0, %2}
12519 ror{l}\t{%b2, %0|%0, %b2}"
12520 [(set_attr "type" "rotate")
12521 (set_attr "mode" "SI")])
12523 (define_insn "*rotrsi3_1_zext"
12524 [(set (match_operand:DI 0 "register_operand" "=r,r")
12526 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12527 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12528 (clobber (reg:CC FLAGS_REG))]
12529 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12531 ror{l}\t{%2, %k0|%k0, %2}
12532 ror{l}\t{%b2, %k0|%k0, %b2}"
12533 [(set_attr "type" "rotate")
12534 (set_attr "mode" "SI")])
12536 (define_expand "rotrhi3"
12537 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12538 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12539 (match_operand:QI 2 "nonmemory_operand" "")))
12540 (clobber (reg:CC FLAGS_REG))]
12541 "TARGET_HIMODE_MATH"
12542 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12544 (define_insn "*rotrhi3_one_bit"
12545 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12546 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12547 (match_operand:QI 2 "const1_operand" "")))
12548 (clobber (reg:CC FLAGS_REG))]
12549 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12550 && (TARGET_SHIFT1 || optimize_size)"
12552 [(set_attr "type" "rotate")
12553 (set (attr "length")
12554 (if_then_else (match_operand 0 "register_operand" "")
12556 (const_string "*")))])
12558 (define_insn "*rotrhi3"
12559 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12560 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12561 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12562 (clobber (reg:CC FLAGS_REG))]
12563 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12565 ror{w}\t{%2, %0|%0, %2}
12566 ror{w}\t{%b2, %0|%0, %b2}"
12567 [(set_attr "type" "rotate")
12568 (set_attr "mode" "HI")])
12570 (define_expand "rotrqi3"
12571 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12572 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12573 (match_operand:QI 2 "nonmemory_operand" "")))
12574 (clobber (reg:CC FLAGS_REG))]
12575 "TARGET_QIMODE_MATH"
12576 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12578 (define_insn "*rotrqi3_1_one_bit"
12579 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12580 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12581 (match_operand:QI 2 "const1_operand" "")))
12582 (clobber (reg:CC FLAGS_REG))]
12583 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12584 && (TARGET_SHIFT1 || optimize_size)"
12586 [(set_attr "type" "rotate")
12587 (set (attr "length")
12588 (if_then_else (match_operand 0 "register_operand" "")
12590 (const_string "*")))])
12592 (define_insn "*rotrqi3_1_one_bit_slp"
12593 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12594 (rotatert:QI (match_dup 0)
12595 (match_operand:QI 1 "const1_operand" "")))
12596 (clobber (reg:CC FLAGS_REG))]
12597 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12598 && (TARGET_SHIFT1 || optimize_size)"
12600 [(set_attr "type" "rotate1")
12601 (set (attr "length")
12602 (if_then_else (match_operand 0 "register_operand" "")
12604 (const_string "*")))])
12606 (define_insn "*rotrqi3_1"
12607 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12608 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12609 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12610 (clobber (reg:CC FLAGS_REG))]
12611 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12613 ror{b}\t{%2, %0|%0, %2}
12614 ror{b}\t{%b2, %0|%0, %b2}"
12615 [(set_attr "type" "rotate")
12616 (set_attr "mode" "QI")])
12618 (define_insn "*rotrqi3_1_slp"
12619 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12620 (rotatert:QI (match_dup 0)
12621 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12622 (clobber (reg:CC FLAGS_REG))]
12623 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12624 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12626 ror{b}\t{%1, %0|%0, %1}
12627 ror{b}\t{%b1, %0|%0, %b1}"
12628 [(set_attr "type" "rotate1")
12629 (set_attr "mode" "QI")])
12631 ;; Bit set / bit test instructions
12633 (define_expand "extv"
12634 [(set (match_operand:SI 0 "register_operand" "")
12635 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12636 (match_operand:SI 2 "immediate_operand" "")
12637 (match_operand:SI 3 "immediate_operand" "")))]
12640 /* Handle extractions from %ah et al. */
12641 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12644 /* From mips.md: extract_bit_field doesn't verify that our source
12645 matches the predicate, so check it again here. */
12646 if (! register_operand (operands[1], VOIDmode))
12650 (define_expand "extzv"
12651 [(set (match_operand:SI 0 "register_operand" "")
12652 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12653 (match_operand:SI 2 "immediate_operand" "")
12654 (match_operand:SI 3 "immediate_operand" "")))]
12657 /* Handle extractions from %ah et al. */
12658 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12661 /* From mips.md: extract_bit_field doesn't verify that our source
12662 matches the predicate, so check it again here. */
12663 if (! register_operand (operands[1], VOIDmode))
12667 (define_expand "insv"
12668 [(set (zero_extract (match_operand 0 "ext_register_operand" "")
12669 (match_operand 1 "immediate_operand" "")
12670 (match_operand 2 "immediate_operand" ""))
12671 (match_operand 3 "register_operand" ""))]
12674 /* Handle extractions from %ah et al. */
12675 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12678 /* From mips.md: insert_bit_field doesn't verify that our source
12679 matches the predicate, so check it again here. */
12680 if (! register_operand (operands[0], VOIDmode))
12684 emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
12686 emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
12691 ;; %%% bts, btr, btc, bt.
12693 ;; Store-flag instructions.
12695 ;; For all sCOND expanders, also expand the compare or test insn that
12696 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12698 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12699 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12700 ;; way, which can later delete the movzx if only QImode is needed.
12702 (define_expand "seq"
12703 [(set (match_operand:QI 0 "register_operand" "")
12704 (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12706 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12708 (define_expand "sne"
12709 [(set (match_operand:QI 0 "register_operand" "")
12710 (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
12712 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12714 (define_expand "sgt"
12715 [(set (match_operand:QI 0 "register_operand" "")
12716 (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12718 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12720 (define_expand "sgtu"
12721 [(set (match_operand:QI 0 "register_operand" "")
12722 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12724 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12726 (define_expand "slt"
12727 [(set (match_operand:QI 0 "register_operand" "")
12728 (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12730 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12732 (define_expand "sltu"
12733 [(set (match_operand:QI 0 "register_operand" "")
12734 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12736 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12738 (define_expand "sge"
12739 [(set (match_operand:QI 0 "register_operand" "")
12740 (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12742 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12744 (define_expand "sgeu"
12745 [(set (match_operand:QI 0 "register_operand" "")
12746 (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12748 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12750 (define_expand "sle"
12751 [(set (match_operand:QI 0 "register_operand" "")
12752 (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
12754 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12756 (define_expand "sleu"
12757 [(set (match_operand:QI 0 "register_operand" "")
12758 (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12760 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12762 (define_expand "sunordered"
12763 [(set (match_operand:QI 0 "register_operand" "")
12764 (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12765 "TARGET_80387 || TARGET_SSE"
12766 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12768 (define_expand "sordered"
12769 [(set (match_operand:QI 0 "register_operand" "")
12770 (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12772 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12774 (define_expand "suneq"
12775 [(set (match_operand:QI 0 "register_operand" "")
12776 (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12777 "TARGET_80387 || TARGET_SSE"
12778 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12780 (define_expand "sunge"
12781 [(set (match_operand:QI 0 "register_operand" "")
12782 (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12783 "TARGET_80387 || TARGET_SSE"
12784 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12786 (define_expand "sungt"
12787 [(set (match_operand:QI 0 "register_operand" "")
12788 (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12789 "TARGET_80387 || TARGET_SSE"
12790 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12792 (define_expand "sunle"
12793 [(set (match_operand:QI 0 "register_operand" "")
12794 (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
12795 "TARGET_80387 || TARGET_SSE"
12796 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12798 (define_expand "sunlt"
12799 [(set (match_operand:QI 0 "register_operand" "")
12800 (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12801 "TARGET_80387 || TARGET_SSE"
12802 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12804 (define_expand "sltgt"
12805 [(set (match_operand:QI 0 "register_operand" "")
12806 (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12807 "TARGET_80387 || TARGET_SSE"
12808 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12810 (define_insn "*setcc_1"
12811 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12812 (match_operator:QI 1 "ix86_comparison_operator"
12813 [(reg 17) (const_int 0)]))]
12816 [(set_attr "type" "setcc")
12817 (set_attr "mode" "QI")])
12819 (define_insn "setcc_2"
12820 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12821 (match_operator:QI 1 "ix86_comparison_operator"
12822 [(reg 17) (const_int 0)]))]
12825 [(set_attr "type" "setcc")
12826 (set_attr "mode" "QI")])
12828 ;; In general it is not safe to assume too much about CCmode registers,
12829 ;; so simplify-rtx stops when it sees a second one. Under certain
12830 ;; conditions this is safe on x86, so help combine not create
12837 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12838 (ne:QI (match_operator 1 "ix86_comparison_operator"
12839 [(reg 17) (const_int 0)])
12842 [(set (match_dup 0) (match_dup 1))]
12844 PUT_MODE (operands[1], QImode);
12848 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12849 (ne:QI (match_operator 1 "ix86_comparison_operator"
12850 [(reg 17) (const_int 0)])
12853 [(set (match_dup 0) (match_dup 1))]
12855 PUT_MODE (operands[1], QImode);
12859 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12860 (eq:QI (match_operator 1 "ix86_comparison_operator"
12861 [(reg 17) (const_int 0)])
12864 [(set (match_dup 0) (match_dup 1))]
12866 rtx new_op1 = copy_rtx (operands[1]);
12867 operands[1] = new_op1;
12868 PUT_MODE (new_op1, QImode);
12869 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12870 GET_MODE (XEXP (new_op1, 0))));
12872 /* Make sure that (a) the CCmode we have for the flags is strong
12873 enough for the reversed compare or (b) we have a valid FP compare. */
12874 if (! ix86_comparison_operator (new_op1, VOIDmode))
12879 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12880 (eq:QI (match_operator 1 "ix86_comparison_operator"
12881 [(reg 17) (const_int 0)])
12884 [(set (match_dup 0) (match_dup 1))]
12886 rtx new_op1 = copy_rtx (operands[1]);
12887 operands[1] = new_op1;
12888 PUT_MODE (new_op1, QImode);
12889 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12890 GET_MODE (XEXP (new_op1, 0))));
12892 /* Make sure that (a) the CCmode we have for the flags is strong
12893 enough for the reversed compare or (b) we have a valid FP compare. */
12894 if (! ix86_comparison_operator (new_op1, VOIDmode))
12898 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12899 ;; subsequent logical operations are used to imitate conditional moves.
12900 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12901 ;; it directly. Further holding this value in pseudo register might bring
12902 ;; problem in implicit normalization in spill code.
12903 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12904 ;; instructions after reload by splitting the conditional move patterns.
12906 (define_insn "*sse_setccsf"
12907 [(set (match_operand:SF 0 "register_operand" "=x")
12908 (match_operator:SF 1 "sse_comparison_operator"
12909 [(match_operand:SF 2 "register_operand" "0")
12910 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12911 "TARGET_SSE && reload_completed"
12912 "cmp%D1ss\t{%3, %0|%0, %3}"
12913 [(set_attr "type" "ssecmp")
12914 (set_attr "mode" "SF")])
12916 (define_insn "*sse_setccdf"
12917 [(set (match_operand:DF 0 "register_operand" "=Y")
12918 (match_operator:DF 1 "sse_comparison_operator"
12919 [(match_operand:DF 2 "register_operand" "0")
12920 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12921 "TARGET_SSE2 && reload_completed"
12922 "cmp%D1sd\t{%3, %0|%0, %3}"
12923 [(set_attr "type" "ssecmp")
12924 (set_attr "mode" "DF")])
12926 ;; Basic conditional jump instructions.
12927 ;; We ignore the overflow flag for signed branch instructions.
12929 ;; For all bCOND expanders, also expand the compare or test insn that
12930 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12932 (define_expand "beq"
12934 (if_then_else (match_dup 1)
12935 (label_ref (match_operand 0 "" ""))
12938 "ix86_expand_branch (EQ, operands[0]); DONE;")
12940 (define_expand "bne"
12942 (if_then_else (match_dup 1)
12943 (label_ref (match_operand 0 "" ""))
12946 "ix86_expand_branch (NE, operands[0]); DONE;")
12948 (define_expand "bgt"
12950 (if_then_else (match_dup 1)
12951 (label_ref (match_operand 0 "" ""))
12954 "ix86_expand_branch (GT, operands[0]); DONE;")
12956 (define_expand "bgtu"
12958 (if_then_else (match_dup 1)
12959 (label_ref (match_operand 0 "" ""))
12962 "ix86_expand_branch (GTU, operands[0]); DONE;")
12964 (define_expand "blt"
12966 (if_then_else (match_dup 1)
12967 (label_ref (match_operand 0 "" ""))
12970 "ix86_expand_branch (LT, operands[0]); DONE;")
12972 (define_expand "bltu"
12974 (if_then_else (match_dup 1)
12975 (label_ref (match_operand 0 "" ""))
12978 "ix86_expand_branch (LTU, operands[0]); DONE;")
12980 (define_expand "bge"
12982 (if_then_else (match_dup 1)
12983 (label_ref (match_operand 0 "" ""))
12986 "ix86_expand_branch (GE, operands[0]); DONE;")
12988 (define_expand "bgeu"
12990 (if_then_else (match_dup 1)
12991 (label_ref (match_operand 0 "" ""))
12994 "ix86_expand_branch (GEU, operands[0]); DONE;")
12996 (define_expand "ble"
12998 (if_then_else (match_dup 1)
12999 (label_ref (match_operand 0 "" ""))
13002 "ix86_expand_branch (LE, operands[0]); DONE;")
13004 (define_expand "bleu"
13006 (if_then_else (match_dup 1)
13007 (label_ref (match_operand 0 "" ""))
13010 "ix86_expand_branch (LEU, operands[0]); DONE;")
13012 (define_expand "bunordered"
13014 (if_then_else (match_dup 1)
13015 (label_ref (match_operand 0 "" ""))
13017 "TARGET_80387 || TARGET_SSE"
13018 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
13020 (define_expand "bordered"
13022 (if_then_else (match_dup 1)
13023 (label_ref (match_operand 0 "" ""))
13025 "TARGET_80387 || TARGET_SSE"
13026 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13028 (define_expand "buneq"
13030 (if_then_else (match_dup 1)
13031 (label_ref (match_operand 0 "" ""))
13033 "TARGET_80387 || TARGET_SSE"
13034 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13036 (define_expand "bunge"
13038 (if_then_else (match_dup 1)
13039 (label_ref (match_operand 0 "" ""))
13041 "TARGET_80387 || TARGET_SSE"
13042 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13044 (define_expand "bungt"
13046 (if_then_else (match_dup 1)
13047 (label_ref (match_operand 0 "" ""))
13049 "TARGET_80387 || TARGET_SSE"
13050 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13052 (define_expand "bunle"
13054 (if_then_else (match_dup 1)
13055 (label_ref (match_operand 0 "" ""))
13057 "TARGET_80387 || TARGET_SSE"
13058 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13060 (define_expand "bunlt"
13062 (if_then_else (match_dup 1)
13063 (label_ref (match_operand 0 "" ""))
13065 "TARGET_80387 || TARGET_SSE"
13066 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13068 (define_expand "bltgt"
13070 (if_then_else (match_dup 1)
13071 (label_ref (match_operand 0 "" ""))
13073 "TARGET_80387 || TARGET_SSE"
13074 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13076 (define_insn "*jcc_1"
13078 (if_then_else (match_operator 1 "ix86_comparison_operator"
13079 [(reg 17) (const_int 0)])
13080 (label_ref (match_operand 0 "" ""))
13084 [(set_attr "type" "ibr")
13085 (set_attr "modrm" "0")
13086 (set (attr "length")
13087 (if_then_else (and (ge (minus (match_dup 0) (pc))
13089 (lt (minus (match_dup 0) (pc))
13094 (define_insn "*jcc_2"
13096 (if_then_else (match_operator 1 "ix86_comparison_operator"
13097 [(reg 17) (const_int 0)])
13099 (label_ref (match_operand 0 "" ""))))]
13102 [(set_attr "type" "ibr")
13103 (set_attr "modrm" "0")
13104 (set (attr "length")
13105 (if_then_else (and (ge (minus (match_dup 0) (pc))
13107 (lt (minus (match_dup 0) (pc))
13112 ;; In general it is not safe to assume too much about CCmode registers,
13113 ;; so simplify-rtx stops when it sees a second one. Under certain
13114 ;; conditions this is safe on x86, so help combine not create
13122 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13123 [(reg 17) (const_int 0)])
13125 (label_ref (match_operand 1 "" ""))
13129 (if_then_else (match_dup 0)
13130 (label_ref (match_dup 1))
13133 PUT_MODE (operands[0], VOIDmode);
13138 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13139 [(reg 17) (const_int 0)])
13141 (label_ref (match_operand 1 "" ""))
13145 (if_then_else (match_dup 0)
13146 (label_ref (match_dup 1))
13149 rtx new_op0 = copy_rtx (operands[0]);
13150 operands[0] = new_op0;
13151 PUT_MODE (new_op0, VOIDmode);
13152 PUT_CODE (new_op0, ix86_reverse_condition (GET_CODE (new_op0),
13153 GET_MODE (XEXP (new_op0, 0))));
13155 /* Make sure that (a) the CCmode we have for the flags is strong
13156 enough for the reversed compare or (b) we have a valid FP compare. */
13157 if (! ix86_comparison_operator (new_op0, VOIDmode))
13161 ;; Define combination compare-and-branch fp compare instructions to use
13162 ;; during early optimization. Splitting the operation apart early makes
13163 ;; for bad code when we want to reverse the operation.
13165 (define_insn "*fp_jcc_1"
13167 (if_then_else (match_operator 0 "comparison_operator"
13168 [(match_operand 1 "register_operand" "f")
13169 (match_operand 2 "register_operand" "f")])
13170 (label_ref (match_operand 3 "" ""))
13172 (clobber (reg:CCFP FPSR_REG))
13173 (clobber (reg:CCFP FLAGS_REG))]
13174 "TARGET_CMOVE && TARGET_80387
13175 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13176 && FLOAT_MODE_P (GET_MODE (operands[1]))
13177 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13178 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13181 (define_insn "*fp_jcc_1_sse"
13183 (if_then_else (match_operator 0 "comparison_operator"
13184 [(match_operand 1 "register_operand" "f#x,x#f")
13185 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13186 (label_ref (match_operand 3 "" ""))
13188 (clobber (reg:CCFP FPSR_REG))
13189 (clobber (reg:CCFP FLAGS_REG))]
13191 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13192 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13193 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13196 (define_insn "*fp_jcc_1_sse_only"
13198 (if_then_else (match_operator 0 "comparison_operator"
13199 [(match_operand 1 "register_operand" "x")
13200 (match_operand 2 "nonimmediate_operand" "xm")])
13201 (label_ref (match_operand 3 "" ""))
13203 (clobber (reg:CCFP FPSR_REG))
13204 (clobber (reg:CCFP FLAGS_REG))]
13205 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13206 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13207 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13210 (define_insn "*fp_jcc_2"
13212 (if_then_else (match_operator 0 "comparison_operator"
13213 [(match_operand 1 "register_operand" "f")
13214 (match_operand 2 "register_operand" "f")])
13216 (label_ref (match_operand 3 "" ""))))
13217 (clobber (reg:CCFP FPSR_REG))
13218 (clobber (reg:CCFP FLAGS_REG))]
13219 "TARGET_CMOVE && TARGET_80387
13220 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13221 && FLOAT_MODE_P (GET_MODE (operands[1]))
13222 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13223 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13226 (define_insn "*fp_jcc_2_sse"
13228 (if_then_else (match_operator 0 "comparison_operator"
13229 [(match_operand 1 "register_operand" "f#x,x#f")
13230 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13232 (label_ref (match_operand 3 "" ""))))
13233 (clobber (reg:CCFP FPSR_REG))
13234 (clobber (reg:CCFP FLAGS_REG))]
13236 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13237 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13238 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13241 (define_insn "*fp_jcc_2_sse_only"
13243 (if_then_else (match_operator 0 "comparison_operator"
13244 [(match_operand 1 "register_operand" "x")
13245 (match_operand 2 "nonimmediate_operand" "xm")])
13247 (label_ref (match_operand 3 "" ""))))
13248 (clobber (reg:CCFP FPSR_REG))
13249 (clobber (reg:CCFP FLAGS_REG))]
13250 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13251 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13252 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13255 (define_insn "*fp_jcc_3"
13257 (if_then_else (match_operator 0 "comparison_operator"
13258 [(match_operand 1 "register_operand" "f")
13259 (match_operand 2 "nonimmediate_operand" "fm")])
13260 (label_ref (match_operand 3 "" ""))
13262 (clobber (reg:CCFP FPSR_REG))
13263 (clobber (reg:CCFP FLAGS_REG))
13264 (clobber (match_scratch:HI 4 "=a"))]
13266 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13267 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13268 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13269 && SELECT_CC_MODE (GET_CODE (operands[0]),
13270 operands[1], operands[2]) == CCFPmode
13271 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13274 (define_insn "*fp_jcc_4"
13276 (if_then_else (match_operator 0 "comparison_operator"
13277 [(match_operand 1 "register_operand" "f")
13278 (match_operand 2 "nonimmediate_operand" "fm")])
13280 (label_ref (match_operand 3 "" ""))))
13281 (clobber (reg:CCFP FPSR_REG))
13282 (clobber (reg:CCFP FLAGS_REG))
13283 (clobber (match_scratch:HI 4 "=a"))]
13285 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13286 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13287 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13288 && SELECT_CC_MODE (GET_CODE (operands[0]),
13289 operands[1], operands[2]) == CCFPmode
13290 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13293 (define_insn "*fp_jcc_5"
13295 (if_then_else (match_operator 0 "comparison_operator"
13296 [(match_operand 1 "register_operand" "f")
13297 (match_operand 2 "register_operand" "f")])
13298 (label_ref (match_operand 3 "" ""))
13300 (clobber (reg:CCFP FPSR_REG))
13301 (clobber (reg:CCFP FLAGS_REG))
13302 (clobber (match_scratch:HI 4 "=a"))]
13304 && FLOAT_MODE_P (GET_MODE (operands[1]))
13305 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13306 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13309 (define_insn "*fp_jcc_6"
13311 (if_then_else (match_operator 0 "comparison_operator"
13312 [(match_operand 1 "register_operand" "f")
13313 (match_operand 2 "register_operand" "f")])
13315 (label_ref (match_operand 3 "" ""))))
13316 (clobber (reg:CCFP FPSR_REG))
13317 (clobber (reg:CCFP FLAGS_REG))
13318 (clobber (match_scratch:HI 4 "=a"))]
13320 && FLOAT_MODE_P (GET_MODE (operands[1]))
13321 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13322 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13327 (if_then_else (match_operator 0 "comparison_operator"
13328 [(match_operand 1 "register_operand" "")
13329 (match_operand 2 "nonimmediate_operand" "")])
13330 (match_operand 3 "" "")
13331 (match_operand 4 "" "")))
13332 (clobber (reg:CCFP FPSR_REG))
13333 (clobber (reg:CCFP FLAGS_REG))]
13337 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13338 operands[3], operands[4], NULL_RTX);
13344 (if_then_else (match_operator 0 "comparison_operator"
13345 [(match_operand 1 "register_operand" "")
13346 (match_operand 2 "nonimmediate_operand" "")])
13347 (match_operand 3 "" "")
13348 (match_operand 4 "" "")))
13349 (clobber (reg:CCFP FPSR_REG))
13350 (clobber (reg:CCFP FLAGS_REG))
13351 (clobber (match_scratch:HI 5 "=a"))]
13354 (if_then_else (match_dup 6)
13358 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13359 operands[3], operands[4], operands[5]);
13363 ;; Unconditional and other jump instructions
13365 (define_insn "jump"
13367 (label_ref (match_operand 0 "" "")))]
13370 [(set_attr "type" "ibr")
13371 (set (attr "length")
13372 (if_then_else (and (ge (minus (match_dup 0) (pc))
13374 (lt (minus (match_dup 0) (pc))
13378 (set_attr "modrm" "0")])
13380 (define_expand "indirect_jump"
13381 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13385 (define_insn "*indirect_jump"
13386 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13389 [(set_attr "type" "ibr")
13390 (set_attr "length_immediate" "0")])
13392 (define_insn "*indirect_jump_rtx64"
13393 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13396 [(set_attr "type" "ibr")
13397 (set_attr "length_immediate" "0")])
13399 (define_expand "tablejump"
13400 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13401 (use (label_ref (match_operand 1 "" "")))])]
13404 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13405 relative. Convert the relative address to an absolute address. */
13409 enum rtx_code code;
13415 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13417 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13421 op1 = pic_offset_table_rtx;
13426 op0 = pic_offset_table_rtx;
13430 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13435 (define_insn "*tablejump_1"
13436 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13437 (use (label_ref (match_operand 1 "" "")))]
13440 [(set_attr "type" "ibr")
13441 (set_attr "length_immediate" "0")])
13443 (define_insn "*tablejump_1_rtx64"
13444 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13445 (use (label_ref (match_operand 1 "" "")))]
13448 [(set_attr "type" "ibr")
13449 (set_attr "length_immediate" "0")])
13451 ;; Loop instruction
13453 ;; This is all complicated by the fact that since this is a jump insn
13454 ;; we must handle our own reloads.
13456 (define_expand "doloop_end"
13457 [(use (match_operand 0 "" "")) ; loop pseudo
13458 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13459 (use (match_operand 2 "" "")) ; max iterations
13460 (use (match_operand 3 "" "")) ; loop level
13461 (use (match_operand 4 "" ""))] ; label
13462 "!TARGET_64BIT && TARGET_USE_LOOP"
13465 /* Only use cloop on innermost loops. */
13466 if (INTVAL (operands[3]) > 1)
13468 if (GET_MODE (operands[0]) != SImode)
13470 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13475 (define_insn "doloop_end_internal"
13477 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13479 (label_ref (match_operand 0 "" ""))
13481 (set (match_operand:SI 2 "nonimmediate_operand" "=1,1,*m*r")
13482 (plus:SI (match_dup 1)
13484 (clobber (match_scratch:SI 3 "=X,X,r"))
13485 (clobber (reg:CC FLAGS_REG))]
13486 "!TARGET_64BIT && TARGET_USE_LOOP
13487 && (reload_in_progress || reload_completed
13488 || register_operand (operands[2], VOIDmode))"
13490 if (which_alternative != 0)
13492 if (get_attr_length (insn) == 2)
13493 return "%+loop\t%l0";
13495 return "dec{l}\t%1\;%+jne\t%l0";
13497 [(set (attr "length")
13498 (if_then_else (and (eq_attr "alternative" "0")
13499 (and (ge (minus (match_dup 0) (pc))
13501 (lt (minus (match_dup 0) (pc))
13505 ;; We don't know the type before shorten branches. Optimistically expect
13506 ;; the loop instruction to match.
13507 (set (attr "type") (const_string "ibr"))])
13511 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13513 (match_operand 0 "" "")
13516 (plus:SI (match_dup 1)
13518 (clobber (match_scratch:SI 2 ""))
13519 (clobber (reg:CC FLAGS_REG))]
13520 "!TARGET_64BIT && TARGET_USE_LOOP
13521 && reload_completed
13522 && REGNO (operands[1]) != 2"
13523 [(parallel [(set (reg:CCZ FLAGS_REG)
13524 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13526 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13527 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13534 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13536 (match_operand 0 "" "")
13538 (set (match_operand:SI 2 "nonimmediate_operand" "")
13539 (plus:SI (match_dup 1)
13541 (clobber (match_scratch:SI 3 ""))
13542 (clobber (reg:CC FLAGS_REG))]
13543 "!TARGET_64BIT && TARGET_USE_LOOP
13544 && reload_completed
13545 && (! REG_P (operands[2])
13546 || ! rtx_equal_p (operands[1], operands[2]))"
13547 [(set (match_dup 3) (match_dup 1))
13548 (parallel [(set (reg:CCZ FLAGS_REG)
13549 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13551 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13552 (set (match_dup 2) (match_dup 3))
13553 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13558 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13561 [(set (reg 17) (match_operand 0 "" ""))
13562 (set (match_operand:QI 1 "register_operand" "")
13563 (match_operator:QI 2 "ix86_comparison_operator"
13564 [(reg 17) (const_int 0)]))
13565 (set (match_operand 3 "q_regs_operand" "")
13566 (zero_extend (match_dup 1)))]
13567 "(peep2_reg_dead_p (3, operands[1])
13568 || operands_match_p (operands[1], operands[3]))
13569 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13570 [(set (match_dup 4) (match_dup 0))
13571 (set (strict_low_part (match_dup 5))
13574 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13575 operands[5] = gen_lowpart (QImode, operands[3]);
13576 ix86_expand_clear (operands[3]);
13579 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13582 [(set (reg 17) (match_operand 0 "" ""))
13583 (set (match_operand:QI 1 "register_operand" "")
13584 (match_operator:QI 2 "ix86_comparison_operator"
13585 [(reg 17) (const_int 0)]))
13586 (parallel [(set (match_operand 3 "q_regs_operand" "")
13587 (zero_extend (match_dup 1)))
13588 (clobber (reg:CC FLAGS_REG))])]
13589 "(peep2_reg_dead_p (3, operands[1])
13590 || operands_match_p (operands[1], operands[3]))
13591 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13592 [(set (match_dup 4) (match_dup 0))
13593 (set (strict_low_part (match_dup 5))
13596 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13597 operands[5] = gen_lowpart (QImode, operands[3]);
13598 ix86_expand_clear (operands[3]);
13601 ;; Call instructions.
13603 ;; The predicates normally associated with named expanders are not properly
13604 ;; checked for calls. This is a bug in the generic code, but it isn't that
13605 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13607 ;; Call subroutine returning no value.
13609 (define_expand "call_pop"
13610 [(parallel [(call (match_operand:QI 0 "" "")
13611 (match_operand:SI 1 "" ""))
13612 (set (reg:SI SP_REG)
13613 (plus:SI (reg:SI SP_REG)
13614 (match_operand:SI 3 "" "")))])]
13617 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13621 (define_insn "*call_pop_0"
13622 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13623 (match_operand:SI 1 "" ""))
13624 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13625 (match_operand:SI 2 "immediate_operand" "")))]
13628 if (SIBLING_CALL_P (insn))
13631 return "call\t%P0";
13633 [(set_attr "type" "call")])
13635 (define_insn "*call_pop_1"
13636 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13637 (match_operand:SI 1 "" ""))
13638 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13639 (match_operand:SI 2 "immediate_operand" "i")))]
13642 if (constant_call_address_operand (operands[0], Pmode))
13644 if (SIBLING_CALL_P (insn))
13647 return "call\t%P0";
13649 if (SIBLING_CALL_P (insn))
13652 return "call\t%A0";
13654 [(set_attr "type" "call")])
13656 (define_expand "call"
13657 [(call (match_operand:QI 0 "" "")
13658 (match_operand 1 "" ""))
13659 (use (match_operand 2 "" ""))]
13662 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13666 (define_expand "sibcall"
13667 [(call (match_operand:QI 0 "" "")
13668 (match_operand 1 "" ""))
13669 (use (match_operand 2 "" ""))]
13672 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13676 (define_insn "*call_0"
13677 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13678 (match_operand 1 "" ""))]
13681 if (SIBLING_CALL_P (insn))
13684 return "call\t%P0";
13686 [(set_attr "type" "call")])
13688 (define_insn "*call_1"
13689 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13690 (match_operand 1 "" ""))]
13691 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13693 if (constant_call_address_operand (operands[0], Pmode))
13694 return "call\t%P0";
13695 return "call\t%A0";
13697 [(set_attr "type" "call")])
13699 (define_insn "*sibcall_1"
13700 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13701 (match_operand 1 "" ""))]
13702 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13704 if (constant_call_address_operand (operands[0], Pmode))
13708 [(set_attr "type" "call")])
13710 (define_insn "*call_1_rex64"
13711 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13712 (match_operand 1 "" ""))]
13713 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13715 if (constant_call_address_operand (operands[0], Pmode))
13716 return "call\t%P0";
13717 return "call\t%A0";
13719 [(set_attr "type" "call")])
13721 (define_insn "*sibcall_1_rex64"
13722 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13723 (match_operand 1 "" ""))]
13724 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13726 [(set_attr "type" "call")])
13728 (define_insn "*sibcall_1_rex64_v"
13729 [(call (mem:QI (reg:DI 40))
13730 (match_operand 0 "" ""))]
13731 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13733 [(set_attr "type" "call")])
13736 ;; Call subroutine, returning value in operand 0
13738 (define_expand "call_value_pop"
13739 [(parallel [(set (match_operand 0 "" "")
13740 (call (match_operand:QI 1 "" "")
13741 (match_operand:SI 2 "" "")))
13742 (set (reg:SI SP_REG)
13743 (plus:SI (reg:SI SP_REG)
13744 (match_operand:SI 4 "" "")))])]
13747 ix86_expand_call (operands[0], operands[1], operands[2],
13748 operands[3], operands[4], 0);
13752 (define_expand "call_value"
13753 [(set (match_operand 0 "" "")
13754 (call (match_operand:QI 1 "" "")
13755 (match_operand:SI 2 "" "")))
13756 (use (match_operand:SI 3 "" ""))]
13757 ;; Operand 2 not used on the i386.
13760 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13764 (define_expand "sibcall_value"
13765 [(set (match_operand 0 "" "")
13766 (call (match_operand:QI 1 "" "")
13767 (match_operand:SI 2 "" "")))
13768 (use (match_operand:SI 3 "" ""))]
13769 ;; Operand 2 not used on the i386.
13772 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13776 ;; Call subroutine returning any type.
13778 (define_expand "untyped_call"
13779 [(parallel [(call (match_operand 0 "" "")
13781 (match_operand 1 "" "")
13782 (match_operand 2 "" "")])]
13787 /* In order to give reg-stack an easier job in validating two
13788 coprocessor registers as containing a possible return value,
13789 simply pretend the untyped call returns a complex long double
13792 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13793 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13794 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13797 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13799 rtx set = XVECEXP (operands[2], 0, i);
13800 emit_move_insn (SET_DEST (set), SET_SRC (set));
13803 /* The optimizer does not know that the call sets the function value
13804 registers we stored in the result block. We avoid problems by
13805 claiming that all hard registers are used and clobbered at this
13807 emit_insn (gen_blockage (const0_rtx));
13812 ;; Prologue and epilogue instructions
13814 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13815 ;; all of memory. This blocks insns from being moved across this point.
13817 (define_insn "blockage"
13818 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13821 [(set_attr "length" "0")])
13823 ;; Insn emitted into the body of a function to return from a function.
13824 ;; This is only done if the function's epilogue is known to be simple.
13825 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13827 (define_expand "return"
13829 "ix86_can_use_return_insn_p ()"
13831 if (current_function_pops_args)
13833 rtx popc = GEN_INT (current_function_pops_args);
13834 emit_jump_insn (gen_return_pop_internal (popc));
13839 (define_insn "return_internal"
13843 [(set_attr "length" "1")
13844 (set_attr "length_immediate" "0")
13845 (set_attr "modrm" "0")])
13847 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
13848 ;; instruction Athlon and K8 have.
13850 (define_insn "return_internal_long"
13852 (unspec [(const_int 0)] UNSPEC_REP)]
13855 [(set_attr "length" "1")
13856 (set_attr "length_immediate" "0")
13857 (set_attr "prefix_rep" "1")
13858 (set_attr "modrm" "0")])
13860 (define_insn "return_pop_internal"
13862 (use (match_operand:SI 0 "const_int_operand" ""))]
13865 [(set_attr "length" "3")
13866 (set_attr "length_immediate" "2")
13867 (set_attr "modrm" "0")])
13869 (define_insn "return_indirect_internal"
13871 (use (match_operand:SI 0 "register_operand" "r"))]
13874 [(set_attr "type" "ibr")
13875 (set_attr "length_immediate" "0")])
13881 [(set_attr "length" "1")
13882 (set_attr "length_immediate" "0")
13883 (set_attr "modrm" "0")])
13885 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
13886 ;; branch prediction penalty for the third jump in a 16-byte
13889 (define_insn "align"
13890 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
13893 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
13894 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
13896 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
13897 The align insn is used to avoid 3 jump instructions in the row to improve
13898 branch prediction and the benefits hardly outweight the cost of extra 8
13899 nops on the average inserted by full alignment pseudo operation. */
13903 [(set_attr "length" "16")])
13905 (define_expand "prologue"
13908 "ix86_expand_prologue (); DONE;")
13910 (define_insn "set_got"
13911 [(set (match_operand:SI 0 "register_operand" "=r")
13912 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13913 (clobber (reg:CC FLAGS_REG))]
13915 { return output_set_got (operands[0]); }
13916 [(set_attr "type" "multi")
13917 (set_attr "length" "12")])
13919 (define_expand "epilogue"
13922 "ix86_expand_epilogue (1); DONE;")
13924 (define_expand "sibcall_epilogue"
13927 "ix86_expand_epilogue (0); DONE;")
13929 (define_expand "eh_return"
13930 [(use (match_operand 0 "register_operand" ""))]
13933 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13935 /* Tricky bit: we write the address of the handler to which we will
13936 be returning into someone else's stack frame, one word below the
13937 stack address we wish to restore. */
13938 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13939 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13940 tmp = gen_rtx_MEM (Pmode, tmp);
13941 emit_move_insn (tmp, ra);
13943 if (Pmode == SImode)
13944 emit_jump_insn (gen_eh_return_si (sa));
13946 emit_jump_insn (gen_eh_return_di (sa));
13951 (define_insn_and_split "eh_return_si"
13953 (unspec [(match_operand:SI 0 "register_operand" "c")]
13954 UNSPEC_EH_RETURN))]
13959 "ix86_expand_epilogue (2); DONE;")
13961 (define_insn_and_split "eh_return_di"
13963 (unspec [(match_operand:DI 0 "register_operand" "c")]
13964 UNSPEC_EH_RETURN))]
13969 "ix86_expand_epilogue (2); DONE;")
13971 (define_insn "leave"
13972 [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
13973 (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
13974 (clobber (mem:BLK (scratch)))]
13977 [(set_attr "type" "leave")])
13979 (define_insn "leave_rex64"
13980 [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
13981 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
13982 (clobber (mem:BLK (scratch)))]
13985 [(set_attr "type" "leave")])
13987 (define_expand "ffssi2"
13989 [(set (match_operand:SI 0 "register_operand" "")
13990 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
13991 (clobber (match_scratch:SI 2 ""))
13992 (clobber (reg:CC FLAGS_REG))])]
13996 (define_insn_and_split "*ffs_cmove"
13997 [(set (match_operand:SI 0 "register_operand" "=r")
13998 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13999 (clobber (match_scratch:SI 2 "=&r"))
14000 (clobber (reg:CC FLAGS_REG))]
14003 "&& reload_completed"
14004 [(set (match_dup 2) (const_int -1))
14005 (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
14006 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14007 (set (match_dup 0) (if_then_else:SI
14008 (eq (reg:CCZ FLAGS_REG) (const_int 0))
14011 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14012 (clobber (reg:CC FLAGS_REG))])]
14015 (define_insn_and_split "*ffs_no_cmove"
14016 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
14017 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14018 (clobber (match_scratch:SI 2 "=&q"))
14019 (clobber (reg:CC FLAGS_REG))]
14023 [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
14024 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14025 (set (strict_low_part (match_dup 3))
14026 (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
14027 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
14028 (clobber (reg:CC FLAGS_REG))])
14029 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14030 (clobber (reg:CC FLAGS_REG))])
14031 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14032 (clobber (reg:CC FLAGS_REG))])]
14034 operands[3] = gen_lowpart (QImode, operands[2]);
14035 ix86_expand_clear (operands[2]);
14038 (define_insn "*ffssi_1"
14039 [(set (reg:CCZ FLAGS_REG)
14040 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14042 (set (match_operand:SI 0 "register_operand" "=r")
14043 (ctz:SI (match_dup 1)))]
14045 "bsf{l}\t{%1, %0|%0, %1}"
14046 [(set_attr "prefix_0f" "1")])
14048 (define_expand "ffsdi2"
14050 [(set (match_operand:DI 0 "register_operand" "")
14051 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
14052 (clobber (match_scratch:DI 2 ""))
14053 (clobber (reg:CC 17))])]
14054 "TARGET_64BIT && TARGET_CMOVE"
14057 (define_insn_and_split "*ffs_rex64"
14058 [(set (match_operand:DI 0 "register_operand" "=r")
14059 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
14060 (clobber (match_scratch:DI 2 "=&r"))
14061 (clobber (reg:CC 17))]
14062 "TARGET_64BIT && TARGET_CMOVE"
14064 "&& reload_completed"
14065 [(set (match_dup 2) (const_int -1))
14066 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14067 (set (match_dup 0) (ctz:DI (match_dup 1)))])
14068 (set (match_dup 0) (if_then_else:DI
14069 (eq (reg:CCZ 17) (const_int 0))
14072 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14073 (clobber (reg:CC 17))])]
14076 (define_insn "*ffsdi_1"
14078 (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
14080 (set (match_operand:DI 0 "register_operand" "=r")
14081 (ctz:DI (match_dup 1)))]
14083 "bsf{q}\t{%1, %0|%0, %1}"
14084 [(set_attr "prefix_0f" "1")])
14086 (define_insn "ctzsi2"
14087 [(set (match_operand:SI 0 "register_operand" "=r")
14088 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14089 (clobber (reg:CC FLAGS_REG))]
14091 "bsf{l}\t{%1, %0|%0, %1}"
14092 [(set_attr "prefix_0f" "1")])
14094 (define_insn "ctzdi2"
14095 [(set (match_operand:DI 0 "register_operand" "=r")
14096 (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
14097 (clobber (reg:CC 17))]
14099 "bsf{q}\t{%1, %0|%0, %1}"
14100 [(set_attr "prefix_0f" "1")])
14102 (define_expand "clzsi2"
14104 [(set (match_operand:SI 0 "register_operand" "")
14105 (minus:SI (const_int 31)
14106 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14107 (clobber (reg:CC FLAGS_REG))])
14109 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14110 (clobber (reg:CC FLAGS_REG))])]
14114 (define_insn "*bsr"
14115 [(set (match_operand:SI 0 "register_operand" "=r")
14116 (minus:SI (const_int 31)
14117 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14118 (clobber (reg:CC FLAGS_REG))]
14120 "bsr{l}\t{%1, %0|%0, %1}"
14121 [(set_attr "prefix_0f" "1")])
14123 (define_expand "clzdi2"
14125 [(set (match_operand:DI 0 "register_operand" "")
14126 (minus:DI (const_int 63)
14127 (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
14128 (clobber (reg:CC 17))])
14130 [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
14131 (clobber (reg:CC 17))])]
14135 (define_insn "*bsr_rex64"
14136 [(set (match_operand:DI 0 "register_operand" "=r")
14137 (minus:DI (const_int 63)
14138 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
14139 (clobber (reg:CC 17))]
14141 "bsr{q}\t{%1, %0|%0, %1}"
14142 [(set_attr "prefix_0f" "1")])
14144 ;; Thread-local storage patterns for ELF.
14146 ;; Note that these code sequences must appear exactly as shown
14147 ;; in order to allow linker relaxation.
14149 (define_insn "*tls_global_dynamic_32_gnu"
14150 [(set (match_operand:SI 0 "register_operand" "=a")
14151 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14152 (match_operand:SI 2 "tls_symbolic_operand" "")
14153 (match_operand:SI 3 "call_insn_operand" "")]
14155 (clobber (match_scratch:SI 4 "=d"))
14156 (clobber (match_scratch:SI 5 "=c"))
14157 (clobber (reg:CC FLAGS_REG))]
14158 "!TARGET_64BIT && TARGET_GNU_TLS"
14159 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14160 [(set_attr "type" "multi")
14161 (set_attr "length" "12")])
14163 (define_insn "*tls_global_dynamic_32_sun"
14164 [(set (match_operand:SI 0 "register_operand" "=a")
14165 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14166 (match_operand:SI 2 "tls_symbolic_operand" "")
14167 (match_operand:SI 3 "call_insn_operand" "")]
14169 (clobber (match_scratch:SI 4 "=d"))
14170 (clobber (match_scratch:SI 5 "=c"))
14171 (clobber (reg:CC FLAGS_REG))]
14172 "!TARGET_64BIT && TARGET_SUN_TLS"
14173 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14174 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14175 [(set_attr "type" "multi")
14176 (set_attr "length" "14")])
14178 (define_expand "tls_global_dynamic_32"
14179 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14182 (match_operand:SI 1 "tls_symbolic_operand" "")
14185 (clobber (match_scratch:SI 4 ""))
14186 (clobber (match_scratch:SI 5 ""))
14187 (clobber (reg:CC FLAGS_REG))])]
14191 operands[2] = pic_offset_table_rtx;
14194 operands[2] = gen_reg_rtx (Pmode);
14195 emit_insn (gen_set_got (operands[2]));
14197 operands[3] = ix86_tls_get_addr ();
14200 (define_insn "*tls_global_dynamic_64"
14201 [(set (match_operand:DI 0 "register_operand" "=a")
14202 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14203 (match_operand:DI 3 "" "")))
14204 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14207 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14208 [(set_attr "type" "multi")
14209 (set_attr "length" "16")])
14211 (define_expand "tls_global_dynamic_64"
14212 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14213 (call (mem:QI (match_dup 2)) (const_int 0)))
14214 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14218 operands[2] = ix86_tls_get_addr ();
14221 (define_insn "*tls_local_dynamic_base_32_gnu"
14222 [(set (match_operand:SI 0 "register_operand" "=a")
14223 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14224 (match_operand:SI 2 "call_insn_operand" "")]
14225 UNSPEC_TLS_LD_BASE))
14226 (clobber (match_scratch:SI 3 "=d"))
14227 (clobber (match_scratch:SI 4 "=c"))
14228 (clobber (reg:CC FLAGS_REG))]
14229 "!TARGET_64BIT && TARGET_GNU_TLS"
14230 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14231 [(set_attr "type" "multi")
14232 (set_attr "length" "11")])
14234 (define_insn "*tls_local_dynamic_base_32_sun"
14235 [(set (match_operand:SI 0 "register_operand" "=a")
14236 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14237 (match_operand:SI 2 "call_insn_operand" "")]
14238 UNSPEC_TLS_LD_BASE))
14239 (clobber (match_scratch:SI 3 "=d"))
14240 (clobber (match_scratch:SI 4 "=c"))
14241 (clobber (reg:CC FLAGS_REG))]
14242 "!TARGET_64BIT && TARGET_SUN_TLS"
14243 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14244 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14245 [(set_attr "type" "multi")
14246 (set_attr "length" "13")])
14248 (define_expand "tls_local_dynamic_base_32"
14249 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14250 (unspec:SI [(match_dup 1) (match_dup 2)]
14251 UNSPEC_TLS_LD_BASE))
14252 (clobber (match_scratch:SI 3 ""))
14253 (clobber (match_scratch:SI 4 ""))
14254 (clobber (reg:CC FLAGS_REG))])]
14258 operands[1] = pic_offset_table_rtx;
14261 operands[1] = gen_reg_rtx (Pmode);
14262 emit_insn (gen_set_got (operands[1]));
14264 operands[2] = ix86_tls_get_addr ();
14267 (define_insn "*tls_local_dynamic_base_64"
14268 [(set (match_operand:DI 0 "register_operand" "=a")
14269 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14270 (match_operand:DI 2 "" "")))
14271 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14273 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14274 [(set_attr "type" "multi")
14275 (set_attr "length" "12")])
14277 (define_expand "tls_local_dynamic_base_64"
14278 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14279 (call (mem:QI (match_dup 1)) (const_int 0)))
14280 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14283 operands[1] = ix86_tls_get_addr ();
14286 ;; Local dynamic of a single variable is a lose. Show combine how
14287 ;; to convert that back to global dynamic.
14289 (define_insn_and_split "*tls_local_dynamic_32_once"
14290 [(set (match_operand:SI 0 "register_operand" "=a")
14291 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14292 (match_operand:SI 2 "call_insn_operand" "")]
14293 UNSPEC_TLS_LD_BASE)
14294 (const:SI (unspec:SI
14295 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14297 (clobber (match_scratch:SI 4 "=d"))
14298 (clobber (match_scratch:SI 5 "=c"))
14299 (clobber (reg:CC FLAGS_REG))]
14303 [(parallel [(set (match_dup 0)
14304 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14306 (clobber (match_dup 4))
14307 (clobber (match_dup 5))
14308 (clobber (reg:CC FLAGS_REG))])]
14311 ;; Load and add the thread base pointer from %gs:0.
14313 (define_insn "*load_tp_si"
14314 [(set (match_operand:SI 0 "register_operand" "=r")
14315 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14317 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14318 [(set_attr "type" "imov")
14319 (set_attr "modrm" "0")
14320 (set_attr "length" "7")
14321 (set_attr "memory" "load")
14322 (set_attr "imm_disp" "false")])
14324 (define_insn "*add_tp_si"
14325 [(set (match_operand:SI 0 "register_operand" "=r")
14326 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14327 (match_operand:SI 1 "register_operand" "0")))
14328 (clobber (reg:CC FLAGS_REG))]
14330 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14331 [(set_attr "type" "alu")
14332 (set_attr "modrm" "0")
14333 (set_attr "length" "7")
14334 (set_attr "memory" "load")
14335 (set_attr "imm_disp" "false")])
14337 (define_insn "*load_tp_di"
14338 [(set (match_operand:DI 0 "register_operand" "=r")
14339 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14341 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14342 [(set_attr "type" "imov")
14343 (set_attr "modrm" "0")
14344 (set_attr "length" "7")
14345 (set_attr "memory" "load")
14346 (set_attr "imm_disp" "false")])
14348 (define_insn "*add_tp_di"
14349 [(set (match_operand:DI 0 "register_operand" "=r")
14350 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14351 (match_operand:DI 1 "register_operand" "0")))
14352 (clobber (reg:CC FLAGS_REG))]
14354 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14355 [(set_attr "type" "alu")
14356 (set_attr "modrm" "0")
14357 (set_attr "length" "7")
14358 (set_attr "memory" "load")
14359 (set_attr "imm_disp" "false")])
14361 ;; These patterns match the binary 387 instructions for addM3, subM3,
14362 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14363 ;; SFmode. The first is the normal insn, the second the same insn but
14364 ;; with one operand a conversion, and the third the same insn but with
14365 ;; the other operand a conversion. The conversion may be SFmode or
14366 ;; SImode if the target mode DFmode, but only SImode if the target mode
14369 ;; Gcc is slightly more smart about handling normal two address instructions
14370 ;; so use special patterns for add and mull.
14371 (define_insn "*fop_sf_comm_nosse"
14372 [(set (match_operand:SF 0 "register_operand" "=f")
14373 (match_operator:SF 3 "binary_fp_operator"
14374 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14375 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14376 "TARGET_80387 && !TARGET_SSE_MATH
14377 && COMMUTATIVE_ARITH_P (operands[3])
14378 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14379 "* return output_387_binary_op (insn, operands);"
14380 [(set (attr "type")
14381 (if_then_else (match_operand:SF 3 "mult_operator" "")
14382 (const_string "fmul")
14383 (const_string "fop")))
14384 (set_attr "mode" "SF")])
14386 (define_insn "*fop_sf_comm"
14387 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14388 (match_operator:SF 3 "binary_fp_operator"
14389 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14390 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14391 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14392 && COMMUTATIVE_ARITH_P (operands[3])
14393 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14394 "* return output_387_binary_op (insn, operands);"
14395 [(set (attr "type")
14396 (if_then_else (eq_attr "alternative" "1")
14397 (if_then_else (match_operand:SF 3 "mult_operator" "")
14398 (const_string "ssemul")
14399 (const_string "sseadd"))
14400 (if_then_else (match_operand:SF 3 "mult_operator" "")
14401 (const_string "fmul")
14402 (const_string "fop"))))
14403 (set_attr "mode" "SF")])
14405 (define_insn "*fop_sf_comm_sse"
14406 [(set (match_operand:SF 0 "register_operand" "=x")
14407 (match_operator:SF 3 "binary_fp_operator"
14408 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14409 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14410 "TARGET_SSE_MATH && COMMUTATIVE_ARITH_P (operands[3])
14411 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14412 "* return output_387_binary_op (insn, operands);"
14413 [(set (attr "type")
14414 (if_then_else (match_operand:SF 3 "mult_operator" "")
14415 (const_string "ssemul")
14416 (const_string "sseadd")))
14417 (set_attr "mode" "SF")])
14419 (define_insn "*fop_df_comm_nosse"
14420 [(set (match_operand:DF 0 "register_operand" "=f")
14421 (match_operator:DF 3 "binary_fp_operator"
14422 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14423 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14424 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14425 && COMMUTATIVE_ARITH_P (operands[3])
14426 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14427 "* return output_387_binary_op (insn, operands);"
14428 [(set (attr "type")
14429 (if_then_else (match_operand:SF 3 "mult_operator" "")
14430 (const_string "fmul")
14431 (const_string "fop")))
14432 (set_attr "mode" "DF")])
14434 (define_insn "*fop_df_comm"
14435 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14436 (match_operator:DF 3 "binary_fp_operator"
14437 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14438 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14439 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14440 && COMMUTATIVE_ARITH_P (operands[3])
14441 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14442 "* return output_387_binary_op (insn, operands);"
14443 [(set (attr "type")
14444 (if_then_else (eq_attr "alternative" "1")
14445 (if_then_else (match_operand:SF 3 "mult_operator" "")
14446 (const_string "ssemul")
14447 (const_string "sseadd"))
14448 (if_then_else (match_operand:SF 3 "mult_operator" "")
14449 (const_string "fmul")
14450 (const_string "fop"))))
14451 (set_attr "mode" "DF")])
14453 (define_insn "*fop_df_comm_sse"
14454 [(set (match_operand:DF 0 "register_operand" "=Y")
14455 (match_operator:DF 3 "binary_fp_operator"
14456 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14457 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14458 "TARGET_SSE2 && TARGET_SSE_MATH
14459 && COMMUTATIVE_ARITH_P (operands[3])
14460 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14461 "* return output_387_binary_op (insn, operands);"
14462 [(set (attr "type")
14463 (if_then_else (match_operand:SF 3 "mult_operator" "")
14464 (const_string "ssemul")
14465 (const_string "sseadd")))
14466 (set_attr "mode" "DF")])
14468 (define_insn "*fop_xf_comm"
14469 [(set (match_operand:XF 0 "register_operand" "=f")
14470 (match_operator:XF 3 "binary_fp_operator"
14471 [(match_operand:XF 1 "register_operand" "%0")
14472 (match_operand:XF 2 "register_operand" "f")]))]
14474 && COMMUTATIVE_ARITH_P (operands[3])"
14475 "* return output_387_binary_op (insn, operands);"
14476 [(set (attr "type")
14477 (if_then_else (match_operand:XF 3 "mult_operator" "")
14478 (const_string "fmul")
14479 (const_string "fop")))
14480 (set_attr "mode" "XF")])
14482 (define_insn "*fop_sf_1_nosse"
14483 [(set (match_operand:SF 0 "register_operand" "=f,f")
14484 (match_operator:SF 3 "binary_fp_operator"
14485 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14486 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14487 "TARGET_80387 && !TARGET_SSE_MATH
14488 && !COMMUTATIVE_ARITH_P (operands[3])
14489 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14490 "* return output_387_binary_op (insn, operands);"
14491 [(set (attr "type")
14492 (cond [(match_operand:SF 3 "mult_operator" "")
14493 (const_string "fmul")
14494 (match_operand:SF 3 "div_operator" "")
14495 (const_string "fdiv")
14497 (const_string "fop")))
14498 (set_attr "mode" "SF")])
14500 (define_insn "*fop_sf_1"
14501 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14502 (match_operator:SF 3 "binary_fp_operator"
14503 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14504 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14505 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14506 && !COMMUTATIVE_ARITH_P (operands[3])
14507 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14508 "* return output_387_binary_op (insn, operands);"
14509 [(set (attr "type")
14510 (cond [(and (eq_attr "alternative" "2")
14511 (match_operand:SF 3 "mult_operator" ""))
14512 (const_string "ssemul")
14513 (and (eq_attr "alternative" "2")
14514 (match_operand:SF 3 "div_operator" ""))
14515 (const_string "ssediv")
14516 (eq_attr "alternative" "2")
14517 (const_string "sseadd")
14518 (match_operand:SF 3 "mult_operator" "")
14519 (const_string "fmul")
14520 (match_operand:SF 3 "div_operator" "")
14521 (const_string "fdiv")
14523 (const_string "fop")))
14524 (set_attr "mode" "SF")])
14526 (define_insn "*fop_sf_1_sse"
14527 [(set (match_operand:SF 0 "register_operand" "=x")
14528 (match_operator:SF 3 "binary_fp_operator"
14529 [(match_operand:SF 1 "register_operand" "0")
14530 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14532 && !COMMUTATIVE_ARITH_P (operands[3])"
14533 "* return output_387_binary_op (insn, operands);"
14534 [(set (attr "type")
14535 (cond [(match_operand:SF 3 "mult_operator" "")
14536 (const_string "ssemul")
14537 (match_operand:SF 3 "div_operator" "")
14538 (const_string "ssediv")
14540 (const_string "sseadd")))
14541 (set_attr "mode" "SF")])
14543 ;; ??? Add SSE splitters for these!
14544 (define_insn "*fop_sf_2"
14545 [(set (match_operand:SF 0 "register_operand" "=f,f")
14546 (match_operator:SF 3 "binary_fp_operator"
14547 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14548 (match_operand:SF 2 "register_operand" "0,0")]))]
14549 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14550 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14551 [(set (attr "type")
14552 (cond [(match_operand:SF 3 "mult_operator" "")
14553 (const_string "fmul")
14554 (match_operand:SF 3 "div_operator" "")
14555 (const_string "fdiv")
14557 (const_string "fop")))
14558 (set_attr "fp_int_src" "true")
14559 (set_attr "mode" "SI")])
14561 (define_insn "*fop_sf_3"
14562 [(set (match_operand:SF 0 "register_operand" "=f,f")
14563 (match_operator:SF 3 "binary_fp_operator"
14564 [(match_operand:SF 1 "register_operand" "0,0")
14565 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14566 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14567 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14568 [(set (attr "type")
14569 (cond [(match_operand:SF 3 "mult_operator" "")
14570 (const_string "fmul")
14571 (match_operand:SF 3 "div_operator" "")
14572 (const_string "fdiv")
14574 (const_string "fop")))
14575 (set_attr "fp_int_src" "true")
14576 (set_attr "mode" "SI")])
14578 (define_insn "*fop_df_1_nosse"
14579 [(set (match_operand:DF 0 "register_operand" "=f,f")
14580 (match_operator:DF 3 "binary_fp_operator"
14581 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14582 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14583 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14584 && !COMMUTATIVE_ARITH_P (operands[3])
14585 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14586 "* return output_387_binary_op (insn, operands);"
14587 [(set (attr "type")
14588 (cond [(match_operand:DF 3 "mult_operator" "")
14589 (const_string "fmul")
14590 (match_operand:DF 3 "div_operator" "")
14591 (const_string "fdiv")
14593 (const_string "fop")))
14594 (set_attr "mode" "DF")])
14597 (define_insn "*fop_df_1"
14598 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14599 (match_operator:DF 3 "binary_fp_operator"
14600 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14601 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14602 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14603 && !COMMUTATIVE_ARITH_P (operands[3])
14604 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14605 "* return output_387_binary_op (insn, operands);"
14606 [(set (attr "type")
14607 (cond [(and (eq_attr "alternative" "2")
14608 (match_operand:SF 3 "mult_operator" ""))
14609 (const_string "ssemul")
14610 (and (eq_attr "alternative" "2")
14611 (match_operand:SF 3 "div_operator" ""))
14612 (const_string "ssediv")
14613 (eq_attr "alternative" "2")
14614 (const_string "sseadd")
14615 (match_operand:DF 3 "mult_operator" "")
14616 (const_string "fmul")
14617 (match_operand:DF 3 "div_operator" "")
14618 (const_string "fdiv")
14620 (const_string "fop")))
14621 (set_attr "mode" "DF")])
14623 (define_insn "*fop_df_1_sse"
14624 [(set (match_operand:DF 0 "register_operand" "=Y")
14625 (match_operator:DF 3 "binary_fp_operator"
14626 [(match_operand:DF 1 "register_operand" "0")
14627 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14628 "TARGET_SSE2 && TARGET_SSE_MATH
14629 && !COMMUTATIVE_ARITH_P (operands[3])"
14630 "* return output_387_binary_op (insn, operands);"
14631 [(set_attr "mode" "DF")
14633 (cond [(match_operand:SF 3 "mult_operator" "")
14634 (const_string "ssemul")
14635 (match_operand:SF 3 "div_operator" "")
14636 (const_string "ssediv")
14638 (const_string "sseadd")))])
14640 ;; ??? Add SSE splitters for these!
14641 (define_insn "*fop_df_2"
14642 [(set (match_operand:DF 0 "register_operand" "=f,f")
14643 (match_operator:DF 3 "binary_fp_operator"
14644 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14645 (match_operand:DF 2 "register_operand" "0,0")]))]
14646 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14647 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14648 [(set (attr "type")
14649 (cond [(match_operand:DF 3 "mult_operator" "")
14650 (const_string "fmul")
14651 (match_operand:DF 3 "div_operator" "")
14652 (const_string "fdiv")
14654 (const_string "fop")))
14655 (set_attr "fp_int_src" "true")
14656 (set_attr "mode" "SI")])
14658 (define_insn "*fop_df_3"
14659 [(set (match_operand:DF 0 "register_operand" "=f,f")
14660 (match_operator:DF 3 "binary_fp_operator"
14661 [(match_operand:DF 1 "register_operand" "0,0")
14662 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14663 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14664 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14665 [(set (attr "type")
14666 (cond [(match_operand:DF 3 "mult_operator" "")
14667 (const_string "fmul")
14668 (match_operand:DF 3 "div_operator" "")
14669 (const_string "fdiv")
14671 (const_string "fop")))
14672 (set_attr "fp_int_src" "true")
14673 (set_attr "mode" "SI")])
14675 (define_insn "*fop_df_4"
14676 [(set (match_operand:DF 0 "register_operand" "=f,f")
14677 (match_operator:DF 3 "binary_fp_operator"
14678 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14679 (match_operand:DF 2 "register_operand" "0,f")]))]
14680 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14681 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14682 "* return output_387_binary_op (insn, operands);"
14683 [(set (attr "type")
14684 (cond [(match_operand:DF 3 "mult_operator" "")
14685 (const_string "fmul")
14686 (match_operand:DF 3 "div_operator" "")
14687 (const_string "fdiv")
14689 (const_string "fop")))
14690 (set_attr "mode" "SF")])
14692 (define_insn "*fop_df_5"
14693 [(set (match_operand:DF 0 "register_operand" "=f,f")
14694 (match_operator:DF 3 "binary_fp_operator"
14695 [(match_operand:DF 1 "register_operand" "0,f")
14697 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14698 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14699 "* return output_387_binary_op (insn, operands);"
14700 [(set (attr "type")
14701 (cond [(match_operand:DF 3 "mult_operator" "")
14702 (const_string "fmul")
14703 (match_operand:DF 3 "div_operator" "")
14704 (const_string "fdiv")
14706 (const_string "fop")))
14707 (set_attr "mode" "SF")])
14709 (define_insn "*fop_df_6"
14710 [(set (match_operand:DF 0 "register_operand" "=f,f")
14711 (match_operator:DF 3 "binary_fp_operator"
14713 (match_operand:SF 1 "register_operand" "0,f"))
14715 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14716 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14717 "* return output_387_binary_op (insn, operands);"
14718 [(set (attr "type")
14719 (cond [(match_operand:DF 3 "mult_operator" "")
14720 (const_string "fmul")
14721 (match_operand:DF 3 "div_operator" "")
14722 (const_string "fdiv")
14724 (const_string "fop")))
14725 (set_attr "mode" "SF")])
14727 (define_insn "*fop_xf_1"
14728 [(set (match_operand:XF 0 "register_operand" "=f,f")
14729 (match_operator:XF 3 "binary_fp_operator"
14730 [(match_operand:XF 1 "register_operand" "0,f")
14731 (match_operand:XF 2 "register_operand" "f,0")]))]
14733 && !COMMUTATIVE_ARITH_P (operands[3])"
14734 "* return output_387_binary_op (insn, operands);"
14735 [(set (attr "type")
14736 (cond [(match_operand:XF 3 "mult_operator" "")
14737 (const_string "fmul")
14738 (match_operand:XF 3 "div_operator" "")
14739 (const_string "fdiv")
14741 (const_string "fop")))
14742 (set_attr "mode" "XF")])
14744 (define_insn "*fop_xf_2"
14745 [(set (match_operand:XF 0 "register_operand" "=f,f")
14746 (match_operator:XF 3 "binary_fp_operator"
14747 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14748 (match_operand:XF 2 "register_operand" "0,0")]))]
14749 "TARGET_80387 && TARGET_USE_FIOP"
14750 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14751 [(set (attr "type")
14752 (cond [(match_operand:XF 3 "mult_operator" "")
14753 (const_string "fmul")
14754 (match_operand:XF 3 "div_operator" "")
14755 (const_string "fdiv")
14757 (const_string "fop")))
14758 (set_attr "fp_int_src" "true")
14759 (set_attr "mode" "SI")])
14761 (define_insn "*fop_xf_3"
14762 [(set (match_operand:XF 0 "register_operand" "=f,f")
14763 (match_operator:XF 3 "binary_fp_operator"
14764 [(match_operand:XF 1 "register_operand" "0,0")
14765 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14766 "TARGET_80387 && TARGET_USE_FIOP"
14767 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14768 [(set (attr "type")
14769 (cond [(match_operand:XF 3 "mult_operator" "")
14770 (const_string "fmul")
14771 (match_operand:XF 3 "div_operator" "")
14772 (const_string "fdiv")
14774 (const_string "fop")))
14775 (set_attr "fp_int_src" "true")
14776 (set_attr "mode" "SI")])
14778 (define_insn "*fop_xf_4"
14779 [(set (match_operand:XF 0 "register_operand" "=f,f")
14780 (match_operator:XF 3 "binary_fp_operator"
14781 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14782 (match_operand:XF 2 "register_operand" "0,f")]))]
14784 "* return output_387_binary_op (insn, operands);"
14785 [(set (attr "type")
14786 (cond [(match_operand:XF 3 "mult_operator" "")
14787 (const_string "fmul")
14788 (match_operand:XF 3 "div_operator" "")
14789 (const_string "fdiv")
14791 (const_string "fop")))
14792 (set_attr "mode" "SF")])
14794 (define_insn "*fop_xf_5"
14795 [(set (match_operand:XF 0 "register_operand" "=f,f")
14796 (match_operator:XF 3 "binary_fp_operator"
14797 [(match_operand:XF 1 "register_operand" "0,f")
14799 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14801 "* return output_387_binary_op (insn, operands);"
14802 [(set (attr "type")
14803 (cond [(match_operand:XF 3 "mult_operator" "")
14804 (const_string "fmul")
14805 (match_operand:XF 3 "div_operator" "")
14806 (const_string "fdiv")
14808 (const_string "fop")))
14809 (set_attr "mode" "SF")])
14811 (define_insn "*fop_xf_6"
14812 [(set (match_operand:XF 0 "register_operand" "=f,f")
14813 (match_operator:XF 3 "binary_fp_operator"
14815 (match_operand 1 "register_operand" "0,f"))
14817 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14819 "* return output_387_binary_op (insn, operands);"
14820 [(set (attr "type")
14821 (cond [(match_operand:XF 3 "mult_operator" "")
14822 (const_string "fmul")
14823 (match_operand:XF 3 "div_operator" "")
14824 (const_string "fdiv")
14826 (const_string "fop")))
14827 (set_attr "mode" "SF")])
14830 [(set (match_operand 0 "register_operand" "")
14831 (match_operator 3 "binary_fp_operator"
14832 [(float (match_operand:SI 1 "register_operand" ""))
14833 (match_operand 2 "register_operand" "")]))]
14834 "TARGET_80387 && reload_completed
14835 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14838 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14839 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14840 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14841 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14842 GET_MODE (operands[3]),
14845 ix86_free_from_memory (GET_MODE (operands[1]));
14850 [(set (match_operand 0 "register_operand" "")
14851 (match_operator 3 "binary_fp_operator"
14852 [(match_operand 1 "register_operand" "")
14853 (float (match_operand:SI 2 "register_operand" ""))]))]
14854 "TARGET_80387 && reload_completed
14855 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14858 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14859 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14860 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14861 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14862 GET_MODE (operands[3]),
14865 ix86_free_from_memory (GET_MODE (operands[2]));
14869 ;; FPU special functions.
14871 (define_expand "sqrtsf2"
14872 [(set (match_operand:SF 0 "register_operand" "")
14873 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14874 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
14876 if (!TARGET_SSE_MATH)
14877 operands[1] = force_reg (SFmode, operands[1]);
14880 (define_insn "sqrtsf2_1"
14881 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14882 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14883 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14884 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14887 sqrtss\t{%1, %0|%0, %1}"
14888 [(set_attr "type" "fpspc,sse")
14889 (set_attr "mode" "SF,SF")
14890 (set_attr "athlon_decode" "direct,*")])
14892 (define_insn "sqrtsf2_1_sse_only"
14893 [(set (match_operand:SF 0 "register_operand" "=x")
14894 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14895 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14896 "sqrtss\t{%1, %0|%0, %1}"
14897 [(set_attr "type" "sse")
14898 (set_attr "mode" "SF")
14899 (set_attr "athlon_decode" "*")])
14901 (define_insn "sqrtsf2_i387"
14902 [(set (match_operand:SF 0 "register_operand" "=f")
14903 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14904 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14905 && !TARGET_SSE_MATH"
14907 [(set_attr "type" "fpspc")
14908 (set_attr "mode" "SF")
14909 (set_attr "athlon_decode" "direct")])
14911 (define_expand "sqrtdf2"
14912 [(set (match_operand:DF 0 "register_operand" "")
14913 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14914 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
14915 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14917 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
14918 operands[1] = force_reg (DFmode, operands[1]);
14921 (define_insn "sqrtdf2_1"
14922 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14923 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14924 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14925 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14928 sqrtsd\t{%1, %0|%0, %1}"
14929 [(set_attr "type" "fpspc,sse")
14930 (set_attr "mode" "DF,DF")
14931 (set_attr "athlon_decode" "direct,*")])
14933 (define_insn "sqrtdf2_1_sse_only"
14934 [(set (match_operand:DF 0 "register_operand" "=Y")
14935 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14936 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14937 "sqrtsd\t{%1, %0|%0, %1}"
14938 [(set_attr "type" "sse")
14939 (set_attr "mode" "DF")
14940 (set_attr "athlon_decode" "*")])
14942 (define_insn "sqrtdf2_i387"
14943 [(set (match_operand:DF 0 "register_operand" "=f")
14944 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14945 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14946 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
14948 [(set_attr "type" "fpspc")
14949 (set_attr "mode" "DF")
14950 (set_attr "athlon_decode" "direct")])
14952 (define_insn "*sqrtextendsfdf2"
14953 [(set (match_operand:DF 0 "register_operand" "=f")
14954 (sqrt:DF (float_extend:DF
14955 (match_operand:SF 1 "register_operand" "0"))))]
14956 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14957 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14959 [(set_attr "type" "fpspc")
14960 (set_attr "mode" "DF")
14961 (set_attr "athlon_decode" "direct")])
14963 (define_insn "sqrtxf2"
14964 [(set (match_operand:XF 0 "register_operand" "=f")
14965 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14966 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14967 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14969 [(set_attr "type" "fpspc")
14970 (set_attr "mode" "XF")
14971 (set_attr "athlon_decode" "direct")])
14973 (define_insn "*sqrtextenddfxf2"
14974 [(set (match_operand:XF 0 "register_operand" "=f")
14975 (sqrt:XF (float_extend:XF
14976 (match_operand:DF 1 "register_operand" "0"))))]
14977 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14979 [(set_attr "type" "fpspc")
14980 (set_attr "mode" "XF")
14981 (set_attr "athlon_decode" "direct")])
14983 (define_insn "*sqrtextendsfxf2"
14984 [(set (match_operand:XF 0 "register_operand" "=f")
14985 (sqrt:XF (float_extend:XF
14986 (match_operand:SF 1 "register_operand" "0"))))]
14987 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14989 [(set_attr "type" "fpspc")
14990 (set_attr "mode" "XF")
14991 (set_attr "athlon_decode" "direct")])
14993 (define_insn "fpremxf4"
14994 [(set (match_operand:XF 0 "register_operand" "=f")
14995 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14996 (match_operand:XF 3 "register_operand" "1")]
14998 (set (match_operand:XF 1 "register_operand" "=u")
14999 (unspec:XF [(match_dup 2) (match_dup 3)]
15001 (set (reg:CCFP FPSR_REG)
15002 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
15003 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15004 && flag_unsafe_math_optimizations"
15006 [(set_attr "type" "fpspc")
15007 (set_attr "mode" "XF")])
15009 (define_expand "fmodsf3"
15010 [(use (match_operand:SF 0 "register_operand" ""))
15011 (use (match_operand:SF 1 "register_operand" ""))
15012 (use (match_operand:SF 2 "register_operand" ""))]
15013 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15014 && flag_unsafe_math_optimizations"
15016 rtx label = gen_label_rtx ();
15018 rtx op1 = gen_reg_rtx (XFmode);
15019 rtx op2 = gen_reg_rtx (XFmode);
15021 emit_insn(gen_extendsfxf2 (op1, operands[1]));
15022 emit_insn(gen_extendsfxf2 (op2, operands[2]));
15024 emit_label (label);
15026 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
15027 ix86_emit_fp_unordered_jump (label);
15029 emit_insn (gen_truncxfsf2_noop (operands[0], op1));
15033 (define_expand "fmoddf3"
15034 [(use (match_operand:DF 0 "register_operand" ""))
15035 (use (match_operand:DF 1 "register_operand" ""))
15036 (use (match_operand:DF 2 "register_operand" ""))]
15037 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15038 && flag_unsafe_math_optimizations"
15040 rtx label = gen_label_rtx ();
15042 rtx op1 = gen_reg_rtx (XFmode);
15043 rtx op2 = gen_reg_rtx (XFmode);
15045 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15046 emit_insn (gen_extenddfxf2 (op2, operands[2]));
15048 emit_label (label);
15050 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
15051 ix86_emit_fp_unordered_jump (label);
15053 emit_insn (gen_truncxfdf2_noop (operands[0], op1));
15057 (define_expand "fmodxf3"
15058 [(use (match_operand:XF 0 "register_operand" ""))
15059 (use (match_operand:XF 1 "register_operand" ""))
15060 (use (match_operand:XF 2 "register_operand" ""))]
15061 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15062 && flag_unsafe_math_optimizations"
15064 rtx label = gen_label_rtx ();
15066 emit_label (label);
15068 emit_insn (gen_fpremxf4 (operands[1], operands[2],
15069 operands[1], operands[2]));
15070 ix86_emit_fp_unordered_jump (label);
15072 emit_move_insn (operands[0], operands[1]);
15076 (define_insn "fprem1xf4"
15077 [(set (match_operand:XF 0 "register_operand" "=f")
15078 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15079 (match_operand:XF 3 "register_operand" "1")]
15081 (set (match_operand:XF 1 "register_operand" "=u")
15082 (unspec:XF [(match_dup 2) (match_dup 3)]
15084 (set (reg:CCFP FPSR_REG)
15085 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
15086 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15087 && flag_unsafe_math_optimizations"
15089 [(set_attr "type" "fpspc")
15090 (set_attr "mode" "XF")])
15092 (define_expand "dremsf3"
15093 [(use (match_operand:SF 0 "register_operand" ""))
15094 (use (match_operand:SF 1 "register_operand" ""))
15095 (use (match_operand:SF 2 "register_operand" ""))]
15096 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15097 && flag_unsafe_math_optimizations"
15099 rtx label = gen_label_rtx ();
15101 rtx op1 = gen_reg_rtx (XFmode);
15102 rtx op2 = gen_reg_rtx (XFmode);
15104 emit_insn(gen_extendsfxf2 (op1, operands[1]));
15105 emit_insn(gen_extendsfxf2 (op2, operands[2]));
15107 emit_label (label);
15109 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
15110 ix86_emit_fp_unordered_jump (label);
15112 emit_insn (gen_truncxfsf2_noop (operands[0], op1));
15116 (define_expand "dremdf3"
15117 [(use (match_operand:DF 0 "register_operand" ""))
15118 (use (match_operand:DF 1 "register_operand" ""))
15119 (use (match_operand:DF 2 "register_operand" ""))]
15120 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15121 && flag_unsafe_math_optimizations"
15123 rtx label = gen_label_rtx ();
15125 rtx op1 = gen_reg_rtx (XFmode);
15126 rtx op2 = gen_reg_rtx (XFmode);
15128 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15129 emit_insn (gen_extenddfxf2 (op2, operands[2]));
15131 emit_label (label);
15133 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
15134 ix86_emit_fp_unordered_jump (label);
15136 emit_insn (gen_truncxfdf2_noop (operands[0], op1));
15140 (define_expand "dremxf3"
15141 [(use (match_operand:XF 0 "register_operand" ""))
15142 (use (match_operand:XF 1 "register_operand" ""))
15143 (use (match_operand:XF 2 "register_operand" ""))]
15144 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15145 && flag_unsafe_math_optimizations"
15147 rtx label = gen_label_rtx ();
15149 emit_label (label);
15151 emit_insn (gen_fprem1xf4 (operands[1], operands[2],
15152 operands[1], operands[2]));
15153 ix86_emit_fp_unordered_jump (label);
15155 emit_move_insn (operands[0], operands[1]);
15159 (define_insn "*sindf2"
15160 [(set (match_operand:DF 0 "register_operand" "=f")
15161 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
15162 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15163 && flag_unsafe_math_optimizations"
15165 [(set_attr "type" "fpspc")
15166 (set_attr "mode" "DF")])
15168 (define_insn "*sinsf2"
15169 [(set (match_operand:SF 0 "register_operand" "=f")
15170 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
15171 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15172 && flag_unsafe_math_optimizations"
15174 [(set_attr "type" "fpspc")
15175 (set_attr "mode" "SF")])
15177 (define_insn "*sinextendsfdf2"
15178 [(set (match_operand:DF 0 "register_operand" "=f")
15179 (unspec:DF [(float_extend:DF
15180 (match_operand:SF 1 "register_operand" "0"))]
15182 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15183 && flag_unsafe_math_optimizations"
15185 [(set_attr "type" "fpspc")
15186 (set_attr "mode" "DF")])
15188 (define_insn "*sinxf2"
15189 [(set (match_operand:XF 0 "register_operand" "=f")
15190 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
15191 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15192 && flag_unsafe_math_optimizations"
15194 [(set_attr "type" "fpspc")
15195 (set_attr "mode" "XF")])
15197 (define_insn "*cosdf2"
15198 [(set (match_operand:DF 0 "register_operand" "=f")
15199 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
15200 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15201 && flag_unsafe_math_optimizations"
15203 [(set_attr "type" "fpspc")
15204 (set_attr "mode" "DF")])
15206 (define_insn "*cossf2"
15207 [(set (match_operand:SF 0 "register_operand" "=f")
15208 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
15209 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15210 && flag_unsafe_math_optimizations"
15212 [(set_attr "type" "fpspc")
15213 (set_attr "mode" "SF")])
15215 (define_insn "*cosextendsfdf2"
15216 [(set (match_operand:DF 0 "register_operand" "=f")
15217 (unspec:DF [(float_extend:DF
15218 (match_operand:SF 1 "register_operand" "0"))]
15220 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15221 && flag_unsafe_math_optimizations"
15223 [(set_attr "type" "fpspc")
15224 (set_attr "mode" "DF")])
15226 (define_insn "*cosxf2"
15227 [(set (match_operand:XF 0 "register_operand" "=f")
15228 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
15229 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15230 && flag_unsafe_math_optimizations"
15232 [(set_attr "type" "fpspc")
15233 (set_attr "mode" "XF")])
15235 ;; With sincos pattern defined, sin and cos builtin function will be
15236 ;; expanded to sincos pattern with one of its outputs left unused.
15237 ;; Cse pass will detected, if two sincos patterns can be combined,
15238 ;; otherwise sincos pattern will be split back to sin or cos pattern,
15239 ;; depending on the unused output.
15241 (define_insn "sincosdf3"
15242 [(set (match_operand:DF 0 "register_operand" "=f")
15243 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15244 UNSPEC_SINCOS_COS))
15245 (set (match_operand:DF 1 "register_operand" "=u")
15246 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15247 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15248 && flag_unsafe_math_optimizations"
15250 [(set_attr "type" "fpspc")
15251 (set_attr "mode" "DF")])
15254 [(set (match_operand:DF 0 "register_operand" "")
15255 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15256 UNSPEC_SINCOS_COS))
15257 (set (match_operand:DF 1 "register_operand" "")
15258 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15259 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15260 && !reload_completed && !reload_in_progress"
15261 [(set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_SIN))]
15265 [(set (match_operand:DF 0 "register_operand" "")
15266 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15267 UNSPEC_SINCOS_COS))
15268 (set (match_operand:DF 1 "register_operand" "")
15269 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15270 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15271 && !reload_completed && !reload_in_progress"
15272 [(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_COS))]
15275 (define_insn "sincossf3"
15276 [(set (match_operand:SF 0 "register_operand" "=f")
15277 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15278 UNSPEC_SINCOS_COS))
15279 (set (match_operand:SF 1 "register_operand" "=u")
15280 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15281 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15282 && flag_unsafe_math_optimizations"
15284 [(set_attr "type" "fpspc")
15285 (set_attr "mode" "SF")])
15288 [(set (match_operand:SF 0 "register_operand" "")
15289 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15290 UNSPEC_SINCOS_COS))
15291 (set (match_operand:SF 1 "register_operand" "")
15292 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15293 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15294 && !reload_completed && !reload_in_progress"
15295 [(set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_SIN))]
15299 [(set (match_operand:SF 0 "register_operand" "")
15300 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15301 UNSPEC_SINCOS_COS))
15302 (set (match_operand:SF 1 "register_operand" "")
15303 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15304 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15305 && !reload_completed && !reload_in_progress"
15306 [(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_COS))]
15309 (define_insn "*sincosextendsfdf3"
15310 [(set (match_operand:DF 0 "register_operand" "=f")
15311 (unspec:DF [(float_extend:DF
15312 (match_operand:SF 2 "register_operand" "0"))]
15313 UNSPEC_SINCOS_COS))
15314 (set (match_operand:DF 1 "register_operand" "=u")
15315 (unspec:DF [(float_extend:DF
15316 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15317 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15318 && flag_unsafe_math_optimizations"
15320 [(set_attr "type" "fpspc")
15321 (set_attr "mode" "DF")])
15324 [(set (match_operand:DF 0 "register_operand" "")
15325 (unspec:DF [(float_extend:DF
15326 (match_operand:SF 2 "register_operand" ""))]
15327 UNSPEC_SINCOS_COS))
15328 (set (match_operand:DF 1 "register_operand" "")
15329 (unspec:DF [(float_extend:DF
15330 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15331 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15332 && !reload_completed && !reload_in_progress"
15333 [(set (match_dup 1) (unspec:DF [(float_extend:DF
15334 (match_dup 2))] UNSPEC_SIN))]
15338 [(set (match_operand:DF 0 "register_operand" "")
15339 (unspec:DF [(float_extend:DF
15340 (match_operand:SF 2 "register_operand" ""))]
15341 UNSPEC_SINCOS_COS))
15342 (set (match_operand:DF 1 "register_operand" "")
15343 (unspec:DF [(float_extend:DF
15344 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15345 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15346 && !reload_completed && !reload_in_progress"
15347 [(set (match_dup 0) (unspec:DF [(float_extend:DF
15348 (match_dup 2))] UNSPEC_COS))]
15351 (define_insn "sincosxf3"
15352 [(set (match_operand:XF 0 "register_operand" "=f")
15353 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15354 UNSPEC_SINCOS_COS))
15355 (set (match_operand:XF 1 "register_operand" "=u")
15356 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15357 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15358 && flag_unsafe_math_optimizations"
15360 [(set_attr "type" "fpspc")
15361 (set_attr "mode" "XF")])
15364 [(set (match_operand:XF 0 "register_operand" "")
15365 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15366 UNSPEC_SINCOS_COS))
15367 (set (match_operand:XF 1 "register_operand" "")
15368 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15369 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15370 && !reload_completed && !reload_in_progress"
15371 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
15375 [(set (match_operand:XF 0 "register_operand" "")
15376 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15377 UNSPEC_SINCOS_COS))
15378 (set (match_operand:XF 1 "register_operand" "")
15379 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15380 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15381 && !reload_completed && !reload_in_progress"
15382 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
15385 (define_insn "*tandf3_1"
15386 [(set (match_operand:DF 0 "register_operand" "=f")
15387 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15389 (set (match_operand:DF 1 "register_operand" "=u")
15390 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
15391 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15392 && flag_unsafe_math_optimizations"
15394 [(set_attr "type" "fpspc")
15395 (set_attr "mode" "DF")])
15397 ;; optimize sequence: fptan
15400 ;; into fptan insn.
15403 [(parallel[(set (match_operand:DF 0 "register_operand" "")
15404 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15406 (set (match_operand:DF 1 "register_operand" "")
15407 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])
15409 (match_operand:DF 3 "immediate_operand" ""))]
15410 "standard_80387_constant_p (operands[3]) == 2"
15411 [(parallel[(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_TAN_ONE))
15412 (set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15415 (define_expand "tandf2"
15416 [(parallel [(set (match_dup 2)
15417 (unspec:DF [(match_operand:DF 1 "register_operand" "")]
15419 (set (match_operand:DF 0 "register_operand" "")
15420 (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15421 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15422 && flag_unsafe_math_optimizations"
15424 operands[2] = gen_reg_rtx (DFmode);
15427 (define_insn "*tansf3_1"
15428 [(set (match_operand:SF 0 "register_operand" "=f")
15429 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15431 (set (match_operand:SF 1 "register_operand" "=u")
15432 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
15433 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15434 && flag_unsafe_math_optimizations"
15436 [(set_attr "type" "fpspc")
15437 (set_attr "mode" "SF")])
15439 ;; optimize sequence: fptan
15442 ;; into fptan insn.
15445 [(parallel[(set (match_operand:SF 0 "register_operand" "")
15446 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15448 (set (match_operand:SF 1 "register_operand" "")
15449 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])
15451 (match_operand:SF 3 "immediate_operand" ""))]
15452 "standard_80387_constant_p (operands[3]) == 2"
15453 [(parallel[(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_TAN_ONE))
15454 (set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15457 (define_expand "tansf2"
15458 [(parallel [(set (match_dup 2)
15459 (unspec:SF [(match_operand:SF 1 "register_operand" "")]
15461 (set (match_operand:SF 0 "register_operand" "")
15462 (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15463 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15464 && flag_unsafe_math_optimizations"
15466 operands[2] = gen_reg_rtx (SFmode);
15469 (define_insn "*tanxf3_1"
15470 [(set (match_operand:XF 0 "register_operand" "=f")
15471 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15473 (set (match_operand:XF 1 "register_operand" "=u")
15474 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
15475 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15476 && flag_unsafe_math_optimizations"
15478 [(set_attr "type" "fpspc")
15479 (set_attr "mode" "XF")])
15481 ;; optimize sequence: fptan
15484 ;; into fptan insn.
15487 [(parallel[(set (match_operand:XF 0 "register_operand" "")
15488 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15490 (set (match_operand:XF 1 "register_operand" "")
15491 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])
15493 (match_operand:XF 3 "immediate_operand" ""))]
15494 "standard_80387_constant_p (operands[3]) == 2"
15495 [(parallel[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_TAN_ONE))
15496 (set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15499 (define_expand "tanxf2"
15500 [(parallel [(set (match_dup 2)
15501 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15503 (set (match_operand:XF 0 "register_operand" "")
15504 (unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15505 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15506 && flag_unsafe_math_optimizations"
15508 operands[2] = gen_reg_rtx (XFmode);
15511 (define_insn "atan2df3_1"
15512 [(set (match_operand:DF 0 "register_operand" "=f")
15513 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15514 (match_operand:DF 1 "register_operand" "u")]
15516 (clobber (match_scratch:DF 3 "=1"))]
15517 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15518 && flag_unsafe_math_optimizations"
15520 [(set_attr "type" "fpspc")
15521 (set_attr "mode" "DF")])
15523 (define_expand "atan2df3"
15524 [(use (match_operand:DF 0 "register_operand" "=f"))
15525 (use (match_operand:DF 2 "register_operand" "0"))
15526 (use (match_operand:DF 1 "register_operand" "u"))]
15527 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15528 && flag_unsafe_math_optimizations"
15530 rtx copy = gen_reg_rtx (DFmode);
15531 emit_move_insn (copy, operands[1]);
15532 emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
15536 (define_expand "atandf2"
15537 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15538 (unspec:DF [(match_dup 2)
15539 (match_operand:DF 1 "register_operand" "")]
15541 (clobber (match_scratch:DF 3 ""))])]
15542 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15543 && flag_unsafe_math_optimizations"
15545 operands[2] = gen_reg_rtx (DFmode);
15546 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15549 (define_insn "atan2sf3_1"
15550 [(set (match_operand:SF 0 "register_operand" "=f")
15551 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15552 (match_operand:SF 1 "register_operand" "u")]
15554 (clobber (match_scratch:SF 3 "=1"))]
15555 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15556 && flag_unsafe_math_optimizations"
15558 [(set_attr "type" "fpspc")
15559 (set_attr "mode" "SF")])
15561 (define_expand "atan2sf3"
15562 [(use (match_operand:SF 0 "register_operand" "=f"))
15563 (use (match_operand:SF 2 "register_operand" "0"))
15564 (use (match_operand:SF 1 "register_operand" "u"))]
15565 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15566 && flag_unsafe_math_optimizations"
15568 rtx copy = gen_reg_rtx (SFmode);
15569 emit_move_insn (copy, operands[1]);
15570 emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
15574 (define_expand "atansf2"
15575 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15576 (unspec:SF [(match_dup 2)
15577 (match_operand:SF 1 "register_operand" "")]
15579 (clobber (match_scratch:SF 3 ""))])]
15580 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15581 && flag_unsafe_math_optimizations"
15583 operands[2] = gen_reg_rtx (SFmode);
15584 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15587 (define_insn "atan2xf3_1"
15588 [(set (match_operand:XF 0 "register_operand" "=f")
15589 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15590 (match_operand:XF 1 "register_operand" "u")]
15592 (clobber (match_scratch:XF 3 "=1"))]
15593 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15594 && flag_unsafe_math_optimizations"
15596 [(set_attr "type" "fpspc")
15597 (set_attr "mode" "XF")])
15599 (define_expand "atan2xf3"
15600 [(use (match_operand:XF 0 "register_operand" "=f"))
15601 (use (match_operand:XF 2 "register_operand" "0"))
15602 (use (match_operand:XF 1 "register_operand" "u"))]
15603 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15604 && flag_unsafe_math_optimizations"
15606 rtx copy = gen_reg_rtx (XFmode);
15607 emit_move_insn (copy, operands[1]);
15608 emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
15612 (define_expand "atanxf2"
15613 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15614 (unspec:XF [(match_dup 2)
15615 (match_operand:XF 1 "register_operand" "")]
15617 (clobber (match_scratch:XF 3 ""))])]
15618 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15619 && flag_unsafe_math_optimizations"
15621 operands[2] = gen_reg_rtx (XFmode);
15622 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15625 (define_expand "asindf2"
15626 [(set (match_dup 2)
15627 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15628 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15629 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15630 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15631 (parallel [(set (match_dup 7)
15632 (unspec:XF [(match_dup 6) (match_dup 2)]
15634 (clobber (match_scratch:XF 8 ""))])
15635 (set (match_operand:DF 0 "register_operand" "")
15636 (float_truncate:DF (match_dup 7)))]
15637 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15638 && flag_unsafe_math_optimizations"
15642 for (i=2; i<8; i++)
15643 operands[i] = gen_reg_rtx (XFmode);
15645 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15648 (define_expand "asinsf2"
15649 [(set (match_dup 2)
15650 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15651 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15652 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15653 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15654 (parallel [(set (match_dup 7)
15655 (unspec:XF [(match_dup 6) (match_dup 2)]
15657 (clobber (match_scratch:XF 8 ""))])
15658 (set (match_operand:SF 0 "register_operand" "")
15659 (float_truncate:SF (match_dup 7)))]
15660 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15661 && flag_unsafe_math_optimizations"
15665 for (i=2; i<8; i++)
15666 operands[i] = gen_reg_rtx (XFmode);
15668 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15671 (define_expand "asinxf2"
15672 [(set (match_dup 2)
15673 (mult:XF (match_operand:XF 1 "register_operand" "")
15675 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15676 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15677 (parallel [(set (match_operand:XF 0 "register_operand" "")
15678 (unspec:XF [(match_dup 5) (match_dup 1)]
15680 (clobber (match_scratch:XF 6 ""))])]
15681 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15682 && flag_unsafe_math_optimizations"
15686 for (i=2; i<6; i++)
15687 operands[i] = gen_reg_rtx (XFmode);
15689 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15692 (define_expand "acosdf2"
15693 [(set (match_dup 2)
15694 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15695 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15696 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15697 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15698 (parallel [(set (match_dup 7)
15699 (unspec:XF [(match_dup 2) (match_dup 6)]
15701 (clobber (match_scratch:XF 8 ""))])
15702 (set (match_operand:DF 0 "register_operand" "")
15703 (float_truncate:DF (match_dup 7)))]
15704 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15705 && flag_unsafe_math_optimizations"
15709 for (i=2; i<8; i++)
15710 operands[i] = gen_reg_rtx (XFmode);
15712 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15715 (define_expand "acossf2"
15716 [(set (match_dup 2)
15717 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15718 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15719 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15720 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15721 (parallel [(set (match_dup 7)
15722 (unspec:XF [(match_dup 2) (match_dup 6)]
15724 (clobber (match_scratch:XF 8 ""))])
15725 (set (match_operand:SF 0 "register_operand" "")
15726 (float_truncate:SF (match_dup 7)))]
15727 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15728 && flag_unsafe_math_optimizations"
15732 for (i=2; i<8; i++)
15733 operands[i] = gen_reg_rtx (XFmode);
15735 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15738 (define_expand "acosxf2"
15739 [(set (match_dup 2)
15740 (mult:XF (match_operand:XF 1 "register_operand" "")
15742 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15743 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15744 (parallel [(set (match_operand:XF 0 "register_operand" "")
15745 (unspec:XF [(match_dup 1) (match_dup 5)]
15747 (clobber (match_scratch:XF 6 ""))])]
15748 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15749 && flag_unsafe_math_optimizations"
15753 for (i=2; i<6; i++)
15754 operands[i] = gen_reg_rtx (XFmode);
15756 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15759 (define_insn "fyl2x_xf3"
15760 [(set (match_operand:XF 0 "register_operand" "=f")
15761 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15762 (match_operand:XF 1 "register_operand" "u")]
15764 (clobber (match_scratch:XF 3 "=1"))]
15765 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15766 && flag_unsafe_math_optimizations"
15768 [(set_attr "type" "fpspc")
15769 (set_attr "mode" "XF")])
15771 (define_expand "logsf2"
15772 [(set (match_dup 2)
15773 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15774 (parallel [(set (match_dup 4)
15775 (unspec:XF [(match_dup 2)
15776 (match_dup 3)] UNSPEC_FYL2X))
15777 (clobber (match_scratch:XF 5 ""))])
15778 (set (match_operand:SF 0 "register_operand" "")
15779 (float_truncate:SF (match_dup 4)))]
15780 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15781 && flag_unsafe_math_optimizations"
15785 operands[2] = gen_reg_rtx (XFmode);
15786 operands[3] = gen_reg_rtx (XFmode);
15787 operands[4] = gen_reg_rtx (XFmode);
15789 temp = standard_80387_constant_rtx (4); /* fldln2 */
15790 emit_move_insn (operands[3], temp);
15793 (define_expand "logdf2"
15794 [(set (match_dup 2)
15795 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15796 (parallel [(set (match_dup 4)
15797 (unspec:XF [(match_dup 2)
15798 (match_dup 3)] UNSPEC_FYL2X))
15799 (clobber (match_scratch:XF 5 ""))])
15800 (set (match_operand:DF 0 "register_operand" "")
15801 (float_truncate:DF (match_dup 4)))]
15802 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15803 && flag_unsafe_math_optimizations"
15807 operands[2] = gen_reg_rtx (XFmode);
15808 operands[3] = gen_reg_rtx (XFmode);
15809 operands[4] = gen_reg_rtx (XFmode);
15811 temp = standard_80387_constant_rtx (4); /* fldln2 */
15812 emit_move_insn (operands[3], temp);
15815 (define_expand "logxf2"
15816 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15817 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15818 (match_dup 2)] UNSPEC_FYL2X))
15819 (clobber (match_scratch:XF 3 ""))])]
15820 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15821 && flag_unsafe_math_optimizations"
15825 operands[2] = gen_reg_rtx (XFmode);
15826 temp = standard_80387_constant_rtx (4); /* fldln2 */
15827 emit_move_insn (operands[2], temp);
15830 (define_expand "log10sf2"
15831 [(set (match_dup 2)
15832 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15833 (parallel [(set (match_dup 4)
15834 (unspec:XF [(match_dup 2)
15835 (match_dup 3)] UNSPEC_FYL2X))
15836 (clobber (match_scratch:XF 5 ""))])
15837 (set (match_operand:SF 0 "register_operand" "")
15838 (float_truncate:SF (match_dup 4)))]
15839 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15840 && flag_unsafe_math_optimizations"
15844 operands[2] = gen_reg_rtx (XFmode);
15845 operands[3] = gen_reg_rtx (XFmode);
15846 operands[4] = gen_reg_rtx (XFmode);
15848 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15849 emit_move_insn (operands[3], temp);
15852 (define_expand "log10df2"
15853 [(set (match_dup 2)
15854 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15855 (parallel [(set (match_dup 4)
15856 (unspec:XF [(match_dup 2)
15857 (match_dup 3)] UNSPEC_FYL2X))
15858 (clobber (match_scratch:XF 5 ""))])
15859 (set (match_operand:DF 0 "register_operand" "")
15860 (float_truncate:DF (match_dup 4)))]
15861 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15862 && flag_unsafe_math_optimizations"
15866 operands[2] = gen_reg_rtx (XFmode);
15867 operands[3] = gen_reg_rtx (XFmode);
15868 operands[4] = gen_reg_rtx (XFmode);
15870 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15871 emit_move_insn (operands[3], temp);
15874 (define_expand "log10xf2"
15875 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15876 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15877 (match_dup 2)] UNSPEC_FYL2X))
15878 (clobber (match_scratch:XF 3 ""))])]
15879 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15880 && flag_unsafe_math_optimizations"
15884 operands[2] = gen_reg_rtx (XFmode);
15885 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15886 emit_move_insn (operands[2], temp);
15889 (define_expand "log2sf2"
15890 [(set (match_dup 2)
15891 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15892 (parallel [(set (match_dup 4)
15893 (unspec:XF [(match_dup 2)
15894 (match_dup 3)] UNSPEC_FYL2X))
15895 (clobber (match_scratch:XF 5 ""))])
15896 (set (match_operand:SF 0 "register_operand" "")
15897 (float_truncate:SF (match_dup 4)))]
15898 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15899 && flag_unsafe_math_optimizations"
15901 operands[2] = gen_reg_rtx (XFmode);
15902 operands[3] = gen_reg_rtx (XFmode);
15903 operands[4] = gen_reg_rtx (XFmode);
15905 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15908 (define_expand "log2df2"
15909 [(set (match_dup 2)
15910 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15911 (parallel [(set (match_dup 4)
15912 (unspec:XF [(match_dup 2)
15913 (match_dup 3)] UNSPEC_FYL2X))
15914 (clobber (match_scratch:XF 5 ""))])
15915 (set (match_operand:DF 0 "register_operand" "")
15916 (float_truncate:DF (match_dup 4)))]
15917 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15918 && flag_unsafe_math_optimizations"
15920 operands[2] = gen_reg_rtx (XFmode);
15921 operands[3] = gen_reg_rtx (XFmode);
15922 operands[4] = gen_reg_rtx (XFmode);
15924 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15927 (define_expand "log2xf2"
15928 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15929 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15930 (match_dup 2)] UNSPEC_FYL2X))
15931 (clobber (match_scratch:XF 3 ""))])]
15932 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15933 && flag_unsafe_math_optimizations"
15935 operands[2] = gen_reg_rtx (XFmode);
15936 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15939 (define_insn "fyl2xp1_xf3"
15940 [(set (match_operand:XF 0 "register_operand" "=f")
15941 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15942 (match_operand:XF 1 "register_operand" "u")]
15944 (clobber (match_scratch:XF 3 "=1"))]
15945 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15946 && flag_unsafe_math_optimizations"
15948 [(set_attr "type" "fpspc")
15949 (set_attr "mode" "XF")])
15951 (define_expand "log1psf2"
15952 [(use (match_operand:XF 0 "register_operand" ""))
15953 (use (match_operand:XF 1 "register_operand" ""))]
15954 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15955 && flag_unsafe_math_optimizations"
15957 rtx op0 = gen_reg_rtx (XFmode);
15958 rtx op1 = gen_reg_rtx (XFmode);
15960 emit_insn (gen_extendsfxf2 (op1, operands[1]));
15961 ix86_emit_i387_log1p (op0, op1);
15962 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
15966 (define_expand "log1pdf2"
15967 [(use (match_operand:XF 0 "register_operand" ""))
15968 (use (match_operand:XF 1 "register_operand" ""))]
15969 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15970 && flag_unsafe_math_optimizations"
15972 rtx op0 = gen_reg_rtx (XFmode);
15973 rtx op1 = gen_reg_rtx (XFmode);
15975 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15976 ix86_emit_i387_log1p (op0, op1);
15977 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
15981 (define_expand "log1pxf2"
15982 [(use (match_operand:XF 0 "register_operand" ""))
15983 (use (match_operand:XF 1 "register_operand" ""))]
15984 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15985 && flag_unsafe_math_optimizations"
15987 ix86_emit_i387_log1p (operands[0], operands[1]);
15991 (define_insn "*fxtractxf3"
15992 [(set (match_operand:XF 0 "register_operand" "=f")
15993 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15994 UNSPEC_XTRACT_FRACT))
15995 (set (match_operand:XF 1 "register_operand" "=u")
15996 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
15997 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15998 && flag_unsafe_math_optimizations"
16000 [(set_attr "type" "fpspc")
16001 (set_attr "mode" "XF")])
16003 (define_expand "logbsf2"
16004 [(set (match_dup 2)
16005 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16006 (parallel [(set (match_dup 3)
16007 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
16009 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
16010 (set (match_operand:SF 0 "register_operand" "")
16011 (float_truncate:SF (match_dup 4)))]
16012 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16013 && flag_unsafe_math_optimizations"
16015 operands[2] = gen_reg_rtx (XFmode);
16016 operands[3] = gen_reg_rtx (XFmode);
16017 operands[4] = gen_reg_rtx (XFmode);
16020 (define_expand "logbdf2"
16021 [(set (match_dup 2)
16022 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16023 (parallel [(set (match_dup 3)
16024 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
16026 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
16027 (set (match_operand:DF 0 "register_operand" "")
16028 (float_truncate:DF (match_dup 4)))]
16029 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16030 && flag_unsafe_math_optimizations"
16032 operands[2] = gen_reg_rtx (XFmode);
16033 operands[3] = gen_reg_rtx (XFmode);
16034 operands[4] = gen_reg_rtx (XFmode);
16037 (define_expand "logbxf2"
16038 [(parallel [(set (match_dup 2)
16039 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
16040 UNSPEC_XTRACT_FRACT))
16041 (set (match_operand:XF 0 "register_operand" "")
16042 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
16043 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16044 && flag_unsafe_math_optimizations"
16046 operands[2] = gen_reg_rtx (XFmode);
16049 (define_expand "ilogbsi2"
16050 [(parallel [(set (match_dup 2)
16051 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
16052 UNSPEC_XTRACT_FRACT))
16053 (set (match_operand:XF 3 "register_operand" "")
16054 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])
16055 (parallel [(set (match_operand:SI 0 "register_operand" "")
16056 (fix:SI (match_dup 3)))
16057 (clobber (reg:CC FLAGS_REG))])]
16058 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16059 && flag_unsafe_math_optimizations"
16061 operands[2] = gen_reg_rtx (XFmode);
16062 operands[3] = gen_reg_rtx (XFmode);
16065 (define_insn "*f2xm1xf2"
16066 [(set (match_operand:XF 0 "register_operand" "=f")
16067 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16069 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16070 && flag_unsafe_math_optimizations"
16072 [(set_attr "type" "fpspc")
16073 (set_attr "mode" "XF")])
16075 (define_insn "*fscalexf4"
16076 [(set (match_operand:XF 0 "register_operand" "=f")
16077 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
16078 (match_operand:XF 3 "register_operand" "1")]
16079 UNSPEC_FSCALE_FRACT))
16080 (set (match_operand:XF 1 "register_operand" "=u")
16081 (unspec:XF [(match_dup 2) (match_dup 3)]
16082 UNSPEC_FSCALE_EXP))]
16083 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16084 && flag_unsafe_math_optimizations"
16086 [(set_attr "type" "fpspc")
16087 (set_attr "mode" "XF")])
16089 (define_expand "expsf2"
16090 [(set (match_dup 2)
16091 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16092 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16093 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16094 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16095 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16096 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16097 (parallel [(set (match_dup 10)
16098 (unspec:XF [(match_dup 9) (match_dup 5)]
16099 UNSPEC_FSCALE_FRACT))
16100 (set (match_dup 11)
16101 (unspec:XF [(match_dup 9) (match_dup 5)]
16102 UNSPEC_FSCALE_EXP))])
16103 (set (match_operand:SF 0 "register_operand" "")
16104 (float_truncate:SF (match_dup 10)))]
16105 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16106 && flag_unsafe_math_optimizations"
16111 for (i=2; i<12; i++)
16112 operands[i] = gen_reg_rtx (XFmode);
16113 temp = standard_80387_constant_rtx (5); /* fldl2e */
16114 emit_move_insn (operands[3], temp);
16115 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16118 (define_expand "expdf2"
16119 [(set (match_dup 2)
16120 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16121 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16122 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16123 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16124 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16125 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16126 (parallel [(set (match_dup 10)
16127 (unspec:XF [(match_dup 9) (match_dup 5)]
16128 UNSPEC_FSCALE_FRACT))
16129 (set (match_dup 11)
16130 (unspec:XF [(match_dup 9) (match_dup 5)]
16131 UNSPEC_FSCALE_EXP))])
16132 (set (match_operand:DF 0 "register_operand" "")
16133 (float_truncate:DF (match_dup 10)))]
16134 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16135 && flag_unsafe_math_optimizations"
16140 for (i=2; i<12; i++)
16141 operands[i] = gen_reg_rtx (XFmode);
16142 temp = standard_80387_constant_rtx (5); /* fldl2e */
16143 emit_move_insn (operands[3], temp);
16144 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16147 (define_expand "expxf2"
16148 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16150 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16151 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16152 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16153 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
16154 (parallel [(set (match_operand:XF 0 "register_operand" "")
16155 (unspec:XF [(match_dup 8) (match_dup 4)]
16156 UNSPEC_FSCALE_FRACT))
16158 (unspec:XF [(match_dup 8) (match_dup 4)]
16159 UNSPEC_FSCALE_EXP))])]
16160 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16161 && flag_unsafe_math_optimizations"
16166 for (i=2; i<10; i++)
16167 operands[i] = gen_reg_rtx (XFmode);
16168 temp = standard_80387_constant_rtx (5); /* fldl2e */
16169 emit_move_insn (operands[2], temp);
16170 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
16173 (define_expand "exp10sf2"
16174 [(set (match_dup 2)
16175 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16176 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16177 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16178 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16179 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16180 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16181 (parallel [(set (match_dup 10)
16182 (unspec:XF [(match_dup 9) (match_dup 5)]
16183 UNSPEC_FSCALE_FRACT))
16184 (set (match_dup 11)
16185 (unspec:XF [(match_dup 9) (match_dup 5)]
16186 UNSPEC_FSCALE_EXP))])
16187 (set (match_operand:SF 0 "register_operand" "")
16188 (float_truncate:SF (match_dup 10)))]
16189 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16190 && flag_unsafe_math_optimizations"
16195 for (i=2; i<12; i++)
16196 operands[i] = gen_reg_rtx (XFmode);
16197 temp = standard_80387_constant_rtx (6); /* fldl2t */
16198 emit_move_insn (operands[3], temp);
16199 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16202 (define_expand "exp10df2"
16203 [(set (match_dup 2)
16204 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16205 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16206 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16207 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16208 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16209 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16210 (parallel [(set (match_dup 10)
16211 (unspec:XF [(match_dup 9) (match_dup 5)]
16212 UNSPEC_FSCALE_FRACT))
16213 (set (match_dup 11)
16214 (unspec:XF [(match_dup 9) (match_dup 5)]
16215 UNSPEC_FSCALE_EXP))])
16216 (set (match_operand:DF 0 "register_operand" "")
16217 (float_truncate:DF (match_dup 10)))]
16218 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16219 && flag_unsafe_math_optimizations"
16224 for (i=2; i<12; i++)
16225 operands[i] = gen_reg_rtx (XFmode);
16226 temp = standard_80387_constant_rtx (6); /* fldl2t */
16227 emit_move_insn (operands[3], temp);
16228 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16231 (define_expand "exp10xf2"
16232 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16234 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16235 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16236 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16237 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
16238 (parallel [(set (match_operand:XF 0 "register_operand" "")
16239 (unspec:XF [(match_dup 8) (match_dup 4)]
16240 UNSPEC_FSCALE_FRACT))
16242 (unspec:XF [(match_dup 8) (match_dup 4)]
16243 UNSPEC_FSCALE_EXP))])]
16244 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16245 && flag_unsafe_math_optimizations"
16250 for (i=2; i<10; i++)
16251 operands[i] = gen_reg_rtx (XFmode);
16252 temp = standard_80387_constant_rtx (6); /* fldl2t */
16253 emit_move_insn (operands[2], temp);
16254 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
16257 (define_expand "exp2sf2"
16258 [(set (match_dup 2)
16259 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16260 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16261 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16262 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16263 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16264 (parallel [(set (match_dup 8)
16265 (unspec:XF [(match_dup 7) (match_dup 3)]
16266 UNSPEC_FSCALE_FRACT))
16268 (unspec:XF [(match_dup 7) (match_dup 3)]
16269 UNSPEC_FSCALE_EXP))])
16270 (set (match_operand:SF 0 "register_operand" "")
16271 (float_truncate:SF (match_dup 8)))]
16272 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16273 && flag_unsafe_math_optimizations"
16277 for (i=2; i<10; i++)
16278 operands[i] = gen_reg_rtx (XFmode);
16279 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16282 (define_expand "exp2df2"
16283 [(set (match_dup 2)
16284 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16285 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16286 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16287 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16288 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16289 (parallel [(set (match_dup 8)
16290 (unspec:XF [(match_dup 7) (match_dup 3)]
16291 UNSPEC_FSCALE_FRACT))
16293 (unspec:XF [(match_dup 7) (match_dup 3)]
16294 UNSPEC_FSCALE_EXP))])
16295 (set (match_operand:DF 0 "register_operand" "")
16296 (float_truncate:DF (match_dup 8)))]
16297 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16298 && flag_unsafe_math_optimizations"
16302 for (i=2; i<10; i++)
16303 operands[i] = gen_reg_rtx (XFmode);
16304 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16307 (define_expand "exp2xf2"
16308 [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
16309 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16310 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16311 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16312 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16313 (parallel [(set (match_operand:XF 0 "register_operand" "")
16314 (unspec:XF [(match_dup 7) (match_dup 3)]
16315 UNSPEC_FSCALE_FRACT))
16317 (unspec:XF [(match_dup 7) (match_dup 3)]
16318 UNSPEC_FSCALE_EXP))])]
16319 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16320 && flag_unsafe_math_optimizations"
16324 for (i=2; i<9; i++)
16325 operands[i] = gen_reg_rtx (XFmode);
16326 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16329 (define_expand "expm1df2"
16330 [(set (match_dup 2)
16331 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16332 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16333 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16334 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16335 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16336 (parallel [(set (match_dup 8)
16337 (unspec:XF [(match_dup 7) (match_dup 5)]
16338 UNSPEC_FSCALE_FRACT))
16340 (unspec:XF [(match_dup 7) (match_dup 5)]
16341 UNSPEC_FSCALE_EXP))])
16342 (parallel [(set (match_dup 11)
16343 (unspec:XF [(match_dup 10) (match_dup 9)]
16344 UNSPEC_FSCALE_FRACT))
16345 (set (match_dup 12)
16346 (unspec:XF [(match_dup 10) (match_dup 9)]
16347 UNSPEC_FSCALE_EXP))])
16348 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16349 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16350 (set (match_operand:DF 0 "register_operand" "")
16351 (float_truncate:DF (match_dup 14)))]
16352 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16353 && flag_unsafe_math_optimizations"
16358 for (i=2; i<15; i++)
16359 operands[i] = gen_reg_rtx (XFmode);
16360 temp = standard_80387_constant_rtx (5); /* fldl2e */
16361 emit_move_insn (operands[3], temp);
16362 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16365 (define_expand "expm1sf2"
16366 [(set (match_dup 2)
16367 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16368 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16369 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16370 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16371 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16372 (parallel [(set (match_dup 8)
16373 (unspec:XF [(match_dup 7) (match_dup 5)]
16374 UNSPEC_FSCALE_FRACT))
16376 (unspec:XF [(match_dup 7) (match_dup 5)]
16377 UNSPEC_FSCALE_EXP))])
16378 (parallel [(set (match_dup 11)
16379 (unspec:XF [(match_dup 10) (match_dup 9)]
16380 UNSPEC_FSCALE_FRACT))
16381 (set (match_dup 12)
16382 (unspec:XF [(match_dup 10) (match_dup 9)]
16383 UNSPEC_FSCALE_EXP))])
16384 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16385 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16386 (set (match_operand:SF 0 "register_operand" "")
16387 (float_truncate:SF (match_dup 14)))]
16388 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16389 && flag_unsafe_math_optimizations"
16394 for (i=2; i<15; i++)
16395 operands[i] = gen_reg_rtx (XFmode);
16396 temp = standard_80387_constant_rtx (5); /* fldl2e */
16397 emit_move_insn (operands[3], temp);
16398 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16401 (define_expand "expm1xf2"
16402 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16404 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16405 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16406 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16407 (parallel [(set (match_dup 7)
16408 (unspec:XF [(match_dup 6) (match_dup 4)]
16409 UNSPEC_FSCALE_FRACT))
16411 (unspec:XF [(match_dup 6) (match_dup 4)]
16412 UNSPEC_FSCALE_EXP))])
16413 (parallel [(set (match_dup 10)
16414 (unspec:XF [(match_dup 9) (match_dup 8)]
16415 UNSPEC_FSCALE_FRACT))
16416 (set (match_dup 11)
16417 (unspec:XF [(match_dup 9) (match_dup 8)]
16418 UNSPEC_FSCALE_EXP))])
16419 (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
16420 (set (match_operand:XF 0 "register_operand" "")
16421 (plus:XF (match_dup 12) (match_dup 7)))]
16422 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16423 && flag_unsafe_math_optimizations"
16428 for (i=2; i<13; i++)
16429 operands[i] = gen_reg_rtx (XFmode);
16430 temp = standard_80387_constant_rtx (5); /* fldl2e */
16431 emit_move_insn (operands[2], temp);
16432 emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
16436 (define_insn "frndintxf2"
16437 [(set (match_operand:XF 0 "register_operand" "=f")
16438 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16440 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16441 && flag_unsafe_math_optimizations"
16443 [(set_attr "type" "fpspc")
16444 (set_attr "mode" "XF")])
16446 (define_expand "rintdf2"
16447 [(use (match_operand:DF 0 "register_operand" ""))
16448 (use (match_operand:DF 1 "register_operand" ""))]
16449 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16450 && flag_unsafe_math_optimizations"
16452 rtx op0 = gen_reg_rtx (XFmode);
16453 rtx op1 = gen_reg_rtx (XFmode);
16455 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16456 emit_insn (gen_frndintxf2 (op0, op1));
16458 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16462 (define_expand "rintsf2"
16463 [(use (match_operand:SF 0 "register_operand" ""))
16464 (use (match_operand:SF 1 "register_operand" ""))]
16465 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16466 && flag_unsafe_math_optimizations"
16468 rtx op0 = gen_reg_rtx (XFmode);
16469 rtx op1 = gen_reg_rtx (XFmode);
16471 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16472 emit_insn (gen_frndintxf2 (op0, op1));
16474 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16478 (define_expand "rintxf2"
16479 [(use (match_operand:XF 0 "register_operand" ""))
16480 (use (match_operand:XF 1 "register_operand" ""))]
16481 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16482 && flag_unsafe_math_optimizations"
16484 emit_insn (gen_frndintxf2 (operands[0], operands[1]));
16488 (define_insn "frndintxf2_floor"
16489 [(set (match_operand:XF 0 "register_operand" "=f")
16490 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16491 UNSPEC_FRNDINT_FLOOR))
16492 (use (match_operand:HI 2 "memory_operand" "m"))
16493 (use (match_operand:HI 3 "memory_operand" "m"))]
16494 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16495 && flag_unsafe_math_optimizations"
16496 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16497 [(set_attr "type" "frndint")
16498 (set_attr "i387_cw" "floor")
16499 (set_attr "mode" "XF")])
16501 (define_expand "floordf2"
16502 [(use (match_operand:DF 0 "register_operand" ""))
16503 (use (match_operand:DF 1 "register_operand" ""))]
16504 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16505 && flag_unsafe_math_optimizations"
16507 rtx op0 = gen_reg_rtx (XFmode);
16508 rtx op1 = gen_reg_rtx (XFmode);
16509 rtx op2 = assign_386_stack_local (HImode, 1);
16510 rtx op3 = assign_386_stack_local (HImode, 2);
16512 ix86_optimize_mode_switching = 1;
16514 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16515 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16517 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16521 (define_expand "floorsf2"
16522 [(use (match_operand:SF 0 "register_operand" ""))
16523 (use (match_operand:SF 1 "register_operand" ""))]
16524 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16525 && flag_unsafe_math_optimizations"
16527 rtx op0 = gen_reg_rtx (XFmode);
16528 rtx op1 = gen_reg_rtx (XFmode);
16529 rtx op2 = assign_386_stack_local (HImode, 1);
16530 rtx op3 = assign_386_stack_local (HImode, 2);
16532 ix86_optimize_mode_switching = 1;
16534 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16535 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16537 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16541 (define_expand "floorxf2"
16542 [(use (match_operand:XF 0 "register_operand" ""))
16543 (use (match_operand:XF 1 "register_operand" ""))]
16544 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16545 && flag_unsafe_math_optimizations"
16547 rtx op2 = assign_386_stack_local (HImode, 1);
16548 rtx op3 = assign_386_stack_local (HImode, 2);
16550 ix86_optimize_mode_switching = 1;
16552 emit_insn (gen_frndintxf2_floor (operands[0], operands[1], op2, op3));
16556 (define_insn "frndintxf2_ceil"
16557 [(set (match_operand:XF 0 "register_operand" "=f")
16558 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16559 UNSPEC_FRNDINT_CEIL))
16560 (use (match_operand:HI 2 "memory_operand" "m"))
16561 (use (match_operand:HI 3 "memory_operand" "m"))]
16562 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16563 && flag_unsafe_math_optimizations"
16564 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16565 [(set_attr "type" "frndint")
16566 (set_attr "i387_cw" "ceil")
16567 (set_attr "mode" "XF")])
16569 (define_expand "ceildf2"
16570 [(use (match_operand:DF 0 "register_operand" ""))
16571 (use (match_operand:DF 1 "register_operand" ""))]
16572 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16573 && flag_unsafe_math_optimizations"
16575 rtx op0 = gen_reg_rtx (XFmode);
16576 rtx op1 = gen_reg_rtx (XFmode);
16577 rtx op2 = assign_386_stack_local (HImode, 1);
16578 rtx op3 = assign_386_stack_local (HImode, 2);
16580 ix86_optimize_mode_switching = 1;
16582 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16583 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16585 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16589 (define_expand "ceilsf2"
16590 [(use (match_operand:SF 0 "register_operand" ""))
16591 (use (match_operand:SF 1 "register_operand" ""))]
16592 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16593 && flag_unsafe_math_optimizations"
16595 rtx op0 = gen_reg_rtx (XFmode);
16596 rtx op1 = gen_reg_rtx (XFmode);
16597 rtx op2 = assign_386_stack_local (HImode, 1);
16598 rtx op3 = assign_386_stack_local (HImode, 2);
16600 ix86_optimize_mode_switching = 1;
16602 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16603 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16605 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16609 (define_expand "ceilxf2"
16610 [(use (match_operand:XF 0 "register_operand" ""))
16611 (use (match_operand:XF 1 "register_operand" ""))]
16612 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16613 && flag_unsafe_math_optimizations"
16615 rtx op2 = assign_386_stack_local (HImode, 1);
16616 rtx op3 = assign_386_stack_local (HImode, 2);
16618 ix86_optimize_mode_switching = 1;
16620 emit_insn (gen_frndintxf2_ceil (operands[0], operands[1], op2, op3));
16624 (define_insn "frndintxf2_trunc"
16625 [(set (match_operand:XF 0 "register_operand" "=f")
16626 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16627 UNSPEC_FRNDINT_TRUNC))
16628 (use (match_operand:HI 2 "memory_operand" "m"))
16629 (use (match_operand:HI 3 "memory_operand" "m"))]
16630 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16631 && flag_unsafe_math_optimizations"
16632 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16633 [(set_attr "type" "frndint")
16634 (set_attr "i387_cw" "trunc")
16635 (set_attr "mode" "XF")])
16637 (define_expand "btruncdf2"
16638 [(use (match_operand:DF 0 "register_operand" ""))
16639 (use (match_operand:DF 1 "register_operand" ""))]
16640 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16641 && flag_unsafe_math_optimizations"
16643 rtx op0 = gen_reg_rtx (XFmode);
16644 rtx op1 = gen_reg_rtx (XFmode);
16645 rtx op2 = assign_386_stack_local (HImode, 1);
16646 rtx op3 = assign_386_stack_local (HImode, 2);
16648 ix86_optimize_mode_switching = 1;
16650 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16651 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16653 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16657 (define_expand "btruncsf2"
16658 [(use (match_operand:SF 0 "register_operand" ""))
16659 (use (match_operand:SF 1 "register_operand" ""))]
16660 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16661 && flag_unsafe_math_optimizations"
16663 rtx op0 = gen_reg_rtx (XFmode);
16664 rtx op1 = gen_reg_rtx (XFmode);
16665 rtx op2 = assign_386_stack_local (HImode, 1);
16666 rtx op3 = assign_386_stack_local (HImode, 2);
16668 ix86_optimize_mode_switching = 1;
16670 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16671 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16673 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16677 (define_expand "btruncxf2"
16678 [(use (match_operand:XF 0 "register_operand" ""))
16679 (use (match_operand:XF 1 "register_operand" ""))]
16680 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16681 && flag_unsafe_math_optimizations"
16683 rtx op2 = assign_386_stack_local (HImode, 1);
16684 rtx op3 = assign_386_stack_local (HImode, 2);
16686 ix86_optimize_mode_switching = 1;
16688 emit_insn (gen_frndintxf2_trunc (operands[0], operands[1], op2, op3));
16692 (define_insn "frndintxf2_mask_pm"
16693 [(set (match_operand:XF 0 "register_operand" "=f")
16694 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16695 UNSPEC_FRNDINT_MASK_PM))
16696 (use (match_operand:HI 2 "memory_operand" "m"))
16697 (use (match_operand:HI 3 "memory_operand" "m"))]
16698 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16699 && flag_unsafe_math_optimizations"
16700 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
16701 [(set_attr "type" "frndint")
16702 (set_attr "i387_cw" "mask_pm")
16703 (set_attr "mode" "XF")])
16705 (define_expand "nearbyintdf2"
16706 [(use (match_operand:DF 0 "register_operand" ""))
16707 (use (match_operand:DF 1 "register_operand" ""))]
16708 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16709 && flag_unsafe_math_optimizations"
16711 rtx op0 = gen_reg_rtx (XFmode);
16712 rtx op1 = gen_reg_rtx (XFmode);
16713 rtx op2 = assign_386_stack_local (HImode, 1);
16714 rtx op3 = assign_386_stack_local (HImode, 2);
16716 ix86_optimize_mode_switching = 1;
16718 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16719 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16721 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16725 (define_expand "nearbyintsf2"
16726 [(use (match_operand:SF 0 "register_operand" ""))
16727 (use (match_operand:SF 1 "register_operand" ""))]
16728 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16729 && flag_unsafe_math_optimizations"
16731 rtx op0 = gen_reg_rtx (XFmode);
16732 rtx op1 = gen_reg_rtx (XFmode);
16733 rtx op2 = assign_386_stack_local (HImode, 1);
16734 rtx op3 = assign_386_stack_local (HImode, 2);
16736 ix86_optimize_mode_switching = 1;
16738 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16739 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16741 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16745 (define_expand "nearbyintxf2"
16746 [(use (match_operand:XF 0 "register_operand" ""))
16747 (use (match_operand:XF 1 "register_operand" ""))]
16748 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
16749 && flag_unsafe_math_optimizations"
16751 rtx op2 = assign_386_stack_local (HImode, 1);
16752 rtx op3 = assign_386_stack_local (HImode, 2);
16754 ix86_optimize_mode_switching = 1;
16756 emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1],
16762 ;; Block operation instructions
16765 [(set (reg:SI DIRFLAG_REG) (const_int 0))]
16768 [(set_attr "type" "cld")])
16770 (define_expand "movmemsi"
16771 [(use (match_operand:BLK 0 "memory_operand" ""))
16772 (use (match_operand:BLK 1 "memory_operand" ""))
16773 (use (match_operand:SI 2 "nonmemory_operand" ""))
16774 (use (match_operand:SI 3 "const_int_operand" ""))]
16777 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16783 (define_expand "movmemdi"
16784 [(use (match_operand:BLK 0 "memory_operand" ""))
16785 (use (match_operand:BLK 1 "memory_operand" ""))
16786 (use (match_operand:DI 2 "nonmemory_operand" ""))
16787 (use (match_operand:DI 3 "const_int_operand" ""))]
16790 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16796 ;; Most CPUs don't like single string operations
16797 ;; Handle this case here to simplify previous expander.
16799 (define_expand "strmov"
16800 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
16801 (set (match_operand 1 "memory_operand" "") (match_dup 4))
16802 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
16803 (clobber (reg:CC FLAGS_REG))])
16804 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
16805 (clobber (reg:CC FLAGS_REG))])]
16808 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
16810 /* If .md ever supports :P for Pmode, these can be directly
16811 in the pattern above. */
16812 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
16813 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
16815 if (TARGET_SINGLE_STRINGOP || optimize_size)
16817 emit_insn (gen_strmov_singleop (operands[0], operands[1],
16818 operands[2], operands[3],
16819 operands[5], operands[6]));
16823 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
16826 (define_expand "strmov_singleop"
16827 [(parallel [(set (match_operand 1 "memory_operand" "")
16828 (match_operand 3 "memory_operand" ""))
16829 (set (match_operand 0 "register_operand" "")
16830 (match_operand 4 "" ""))
16831 (set (match_operand 2 "register_operand" "")
16832 (match_operand 5 "" ""))
16833 (use (reg:SI DIRFLAG_REG))])]
16834 "TARGET_SINGLE_STRINGOP || optimize_size"
16837 (define_insn "*strmovdi_rex_1"
16838 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
16839 (mem:DI (match_operand:DI 3 "register_operand" "1")))
16840 (set (match_operand:DI 0 "register_operand" "=D")
16841 (plus:DI (match_dup 2)
16843 (set (match_operand:DI 1 "register_operand" "=S")
16844 (plus:DI (match_dup 3)
16846 (use (reg:SI DIRFLAG_REG))]
16847 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16849 [(set_attr "type" "str")
16850 (set_attr "mode" "DI")
16851 (set_attr "memory" "both")])
16853 (define_insn "*strmovsi_1"
16854 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
16855 (mem:SI (match_operand:SI 3 "register_operand" "1")))
16856 (set (match_operand:SI 0 "register_operand" "=D")
16857 (plus:SI (match_dup 2)
16859 (set (match_operand:SI 1 "register_operand" "=S")
16860 (plus:SI (match_dup 3)
16862 (use (reg:SI DIRFLAG_REG))]
16863 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16865 [(set_attr "type" "str")
16866 (set_attr "mode" "SI")
16867 (set_attr "memory" "both")])
16869 (define_insn "*strmovsi_rex_1"
16870 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
16871 (mem:SI (match_operand:DI 3 "register_operand" "1")))
16872 (set (match_operand:DI 0 "register_operand" "=D")
16873 (plus:DI (match_dup 2)
16875 (set (match_operand:DI 1 "register_operand" "=S")
16876 (plus:DI (match_dup 3)
16878 (use (reg:SI DIRFLAG_REG))]
16879 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16881 [(set_attr "type" "str")
16882 (set_attr "mode" "SI")
16883 (set_attr "memory" "both")])
16885 (define_insn "*strmovhi_1"
16886 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
16887 (mem:HI (match_operand:SI 3 "register_operand" "1")))
16888 (set (match_operand:SI 0 "register_operand" "=D")
16889 (plus:SI (match_dup 2)
16891 (set (match_operand:SI 1 "register_operand" "=S")
16892 (plus:SI (match_dup 3)
16894 (use (reg:SI DIRFLAG_REG))]
16895 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16897 [(set_attr "type" "str")
16898 (set_attr "memory" "both")
16899 (set_attr "mode" "HI")])
16901 (define_insn "*strmovhi_rex_1"
16902 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
16903 (mem:HI (match_operand:DI 3 "register_operand" "1")))
16904 (set (match_operand:DI 0 "register_operand" "=D")
16905 (plus:DI (match_dup 2)
16907 (set (match_operand:DI 1 "register_operand" "=S")
16908 (plus:DI (match_dup 3)
16910 (use (reg:SI DIRFLAG_REG))]
16911 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16913 [(set_attr "type" "str")
16914 (set_attr "memory" "both")
16915 (set_attr "mode" "HI")])
16917 (define_insn "*strmovqi_1"
16918 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
16919 (mem:QI (match_operand:SI 3 "register_operand" "1")))
16920 (set (match_operand:SI 0 "register_operand" "=D")
16921 (plus:SI (match_dup 2)
16923 (set (match_operand:SI 1 "register_operand" "=S")
16924 (plus:SI (match_dup 3)
16926 (use (reg:SI DIRFLAG_REG))]
16927 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16929 [(set_attr "type" "str")
16930 (set_attr "memory" "both")
16931 (set_attr "mode" "QI")])
16933 (define_insn "*strmovqi_rex_1"
16934 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
16935 (mem:QI (match_operand:DI 3 "register_operand" "1")))
16936 (set (match_operand:DI 0 "register_operand" "=D")
16937 (plus:DI (match_dup 2)
16939 (set (match_operand:DI 1 "register_operand" "=S")
16940 (plus:DI (match_dup 3)
16942 (use (reg:SI DIRFLAG_REG))]
16943 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16945 [(set_attr "type" "str")
16946 (set_attr "memory" "both")
16947 (set_attr "mode" "QI")])
16949 (define_expand "rep_mov"
16950 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
16951 (set (match_operand 0 "register_operand" "")
16952 (match_operand 5 "" ""))
16953 (set (match_operand 2 "register_operand" "")
16954 (match_operand 6 "" ""))
16955 (set (match_operand 1 "memory_operand" "")
16956 (match_operand 3 "memory_operand" ""))
16957 (use (match_dup 4))
16958 (use (reg:SI DIRFLAG_REG))])]
16962 (define_insn "*rep_movdi_rex64"
16963 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16964 (set (match_operand:DI 0 "register_operand" "=D")
16965 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16967 (match_operand:DI 3 "register_operand" "0")))
16968 (set (match_operand:DI 1 "register_operand" "=S")
16969 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
16970 (match_operand:DI 4 "register_operand" "1")))
16971 (set (mem:BLK (match_dup 3))
16972 (mem:BLK (match_dup 4)))
16973 (use (match_dup 5))
16974 (use (reg:SI DIRFLAG_REG))]
16976 "{rep\;movsq|rep movsq}"
16977 [(set_attr "type" "str")
16978 (set_attr "prefix_rep" "1")
16979 (set_attr "memory" "both")
16980 (set_attr "mode" "DI")])
16982 (define_insn "*rep_movsi"
16983 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16984 (set (match_operand:SI 0 "register_operand" "=D")
16985 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
16987 (match_operand:SI 3 "register_operand" "0")))
16988 (set (match_operand:SI 1 "register_operand" "=S")
16989 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
16990 (match_operand:SI 4 "register_operand" "1")))
16991 (set (mem:BLK (match_dup 3))
16992 (mem:BLK (match_dup 4)))
16993 (use (match_dup 5))
16994 (use (reg:SI DIRFLAG_REG))]
16996 "{rep\;movsl|rep movsd}"
16997 [(set_attr "type" "str")
16998 (set_attr "prefix_rep" "1")
16999 (set_attr "memory" "both")
17000 (set_attr "mode" "SI")])
17002 (define_insn "*rep_movsi_rex64"
17003 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
17004 (set (match_operand:DI 0 "register_operand" "=D")
17005 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
17007 (match_operand:DI 3 "register_operand" "0")))
17008 (set (match_operand:DI 1 "register_operand" "=S")
17009 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
17010 (match_operand:DI 4 "register_operand" "1")))
17011 (set (mem:BLK (match_dup 3))
17012 (mem:BLK (match_dup 4)))
17013 (use (match_dup 5))
17014 (use (reg:SI DIRFLAG_REG))]
17016 "{rep\;movsl|rep movsd}"
17017 [(set_attr "type" "str")
17018 (set_attr "prefix_rep" "1")
17019 (set_attr "memory" "both")
17020 (set_attr "mode" "SI")])
17022 (define_insn "*rep_movqi"
17023 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
17024 (set (match_operand:SI 0 "register_operand" "=D")
17025 (plus:SI (match_operand:SI 3 "register_operand" "0")
17026 (match_operand:SI 5 "register_operand" "2")))
17027 (set (match_operand:SI 1 "register_operand" "=S")
17028 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
17029 (set (mem:BLK (match_dup 3))
17030 (mem:BLK (match_dup 4)))
17031 (use (match_dup 5))
17032 (use (reg:SI DIRFLAG_REG))]
17034 "{rep\;movsb|rep movsb}"
17035 [(set_attr "type" "str")
17036 (set_attr "prefix_rep" "1")
17037 (set_attr "memory" "both")
17038 (set_attr "mode" "SI")])
17040 (define_insn "*rep_movqi_rex64"
17041 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
17042 (set (match_operand:DI 0 "register_operand" "=D")
17043 (plus:DI (match_operand:DI 3 "register_operand" "0")
17044 (match_operand:DI 5 "register_operand" "2")))
17045 (set (match_operand:DI 1 "register_operand" "=S")
17046 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
17047 (set (mem:BLK (match_dup 3))
17048 (mem:BLK (match_dup 4)))
17049 (use (match_dup 5))
17050 (use (reg:SI DIRFLAG_REG))]
17052 "{rep\;movsb|rep movsb}"
17053 [(set_attr "type" "str")
17054 (set_attr "prefix_rep" "1")
17055 (set_attr "memory" "both")
17056 (set_attr "mode" "SI")])
17058 (define_expand "clrmemsi"
17059 [(use (match_operand:BLK 0 "memory_operand" ""))
17060 (use (match_operand:SI 1 "nonmemory_operand" ""))
17061 (use (match_operand 2 "const_int_operand" ""))]
17064 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
17070 (define_expand "clrmemdi"
17071 [(use (match_operand:BLK 0 "memory_operand" ""))
17072 (use (match_operand:DI 1 "nonmemory_operand" ""))
17073 (use (match_operand 2 "const_int_operand" ""))]
17076 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
17082 ;; Most CPUs don't like single string operations
17083 ;; Handle this case here to simplify previous expander.
17085 (define_expand "strset"
17086 [(set (match_operand 1 "memory_operand" "")
17087 (match_operand 2 "register_operand" ""))
17088 (parallel [(set (match_operand 0 "register_operand" "")
17090 (clobber (reg:CC FLAGS_REG))])]
17093 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
17094 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
17096 /* If .md ever supports :P for Pmode, this can be directly
17097 in the pattern above. */
17098 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
17099 GEN_INT (GET_MODE_SIZE (GET_MODE
17101 if (TARGET_SINGLE_STRINGOP || optimize_size)
17103 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
17109 (define_expand "strset_singleop"
17110 [(parallel [(set (match_operand 1 "memory_operand" "")
17111 (match_operand 2 "register_operand" ""))
17112 (set (match_operand 0 "register_operand" "")
17113 (match_operand 3 "" ""))
17114 (use (reg:SI DIRFLAG_REG))])]
17115 "TARGET_SINGLE_STRINGOP || optimize_size"
17118 (define_insn "*strsetdi_rex_1"
17119 [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
17120 (match_operand:DI 2 "register_operand" "a"))
17121 (set (match_operand:DI 0 "register_operand" "=D")
17122 (plus:DI (match_dup 1)
17124 (use (reg:SI DIRFLAG_REG))]
17125 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17127 [(set_attr "type" "str")
17128 (set_attr "memory" "store")
17129 (set_attr "mode" "DI")])
17131 (define_insn "*strsetsi_1"
17132 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
17133 (match_operand:SI 2 "register_operand" "a"))
17134 (set (match_operand:SI 0 "register_operand" "=D")
17135 (plus:SI (match_dup 1)
17137 (use (reg:SI DIRFLAG_REG))]
17138 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17140 [(set_attr "type" "str")
17141 (set_attr "memory" "store")
17142 (set_attr "mode" "SI")])
17144 (define_insn "*strsetsi_rex_1"
17145 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
17146 (match_operand:SI 2 "register_operand" "a"))
17147 (set (match_operand:DI 0 "register_operand" "=D")
17148 (plus:DI (match_dup 1)
17150 (use (reg:SI DIRFLAG_REG))]
17151 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17153 [(set_attr "type" "str")
17154 (set_attr "memory" "store")
17155 (set_attr "mode" "SI")])
17157 (define_insn "*strsethi_1"
17158 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
17159 (match_operand:HI 2 "register_operand" "a"))
17160 (set (match_operand:SI 0 "register_operand" "=D")
17161 (plus:SI (match_dup 1)
17163 (use (reg:SI DIRFLAG_REG))]
17164 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17166 [(set_attr "type" "str")
17167 (set_attr "memory" "store")
17168 (set_attr "mode" "HI")])
17170 (define_insn "*strsethi_rex_1"
17171 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
17172 (match_operand:HI 2 "register_operand" "a"))
17173 (set (match_operand:DI 0 "register_operand" "=D")
17174 (plus:DI (match_dup 1)
17176 (use (reg:SI DIRFLAG_REG))]
17177 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17179 [(set_attr "type" "str")
17180 (set_attr "memory" "store")
17181 (set_attr "mode" "HI")])
17183 (define_insn "*strsetqi_1"
17184 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
17185 (match_operand:QI 2 "register_operand" "a"))
17186 (set (match_operand:SI 0 "register_operand" "=D")
17187 (plus:SI (match_dup 1)
17189 (use (reg:SI DIRFLAG_REG))]
17190 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17192 [(set_attr "type" "str")
17193 (set_attr "memory" "store")
17194 (set_attr "mode" "QI")])
17196 (define_insn "*strsetqi_rex_1"
17197 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
17198 (match_operand:QI 2 "register_operand" "a"))
17199 (set (match_operand:DI 0 "register_operand" "=D")
17200 (plus:DI (match_dup 1)
17202 (use (reg:SI DIRFLAG_REG))]
17203 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17205 [(set_attr "type" "str")
17206 (set_attr "memory" "store")
17207 (set_attr "mode" "QI")])
17209 (define_expand "rep_stos"
17210 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
17211 (set (match_operand 0 "register_operand" "")
17212 (match_operand 4 "" ""))
17213 (set (match_operand 2 "memory_operand" "") (const_int 0))
17214 (use (match_operand 3 "register_operand" ""))
17215 (use (match_dup 1))
17216 (use (reg:SI DIRFLAG_REG))])]
17220 (define_insn "*rep_stosdi_rex64"
17221 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17222 (set (match_operand:DI 0 "register_operand" "=D")
17223 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
17225 (match_operand:DI 3 "register_operand" "0")))
17226 (set (mem:BLK (match_dup 3))
17228 (use (match_operand:DI 2 "register_operand" "a"))
17229 (use (match_dup 4))
17230 (use (reg:SI DIRFLAG_REG))]
17232 "{rep\;stosq|rep stosq}"
17233 [(set_attr "type" "str")
17234 (set_attr "prefix_rep" "1")
17235 (set_attr "memory" "store")
17236 (set_attr "mode" "DI")])
17238 (define_insn "*rep_stossi"
17239 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17240 (set (match_operand:SI 0 "register_operand" "=D")
17241 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
17243 (match_operand:SI 3 "register_operand" "0")))
17244 (set (mem:BLK (match_dup 3))
17246 (use (match_operand:SI 2 "register_operand" "a"))
17247 (use (match_dup 4))
17248 (use (reg:SI DIRFLAG_REG))]
17250 "{rep\;stosl|rep stosd}"
17251 [(set_attr "type" "str")
17252 (set_attr "prefix_rep" "1")
17253 (set_attr "memory" "store")
17254 (set_attr "mode" "SI")])
17256 (define_insn "*rep_stossi_rex64"
17257 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17258 (set (match_operand:DI 0 "register_operand" "=D")
17259 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
17261 (match_operand:DI 3 "register_operand" "0")))
17262 (set (mem:BLK (match_dup 3))
17264 (use (match_operand:SI 2 "register_operand" "a"))
17265 (use (match_dup 4))
17266 (use (reg:SI DIRFLAG_REG))]
17268 "{rep\;stosl|rep stosd}"
17269 [(set_attr "type" "str")
17270 (set_attr "prefix_rep" "1")
17271 (set_attr "memory" "store")
17272 (set_attr "mode" "SI")])
17274 (define_insn "*rep_stosqi"
17275 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17276 (set (match_operand:SI 0 "register_operand" "=D")
17277 (plus:SI (match_operand:SI 3 "register_operand" "0")
17278 (match_operand:SI 4 "register_operand" "1")))
17279 (set (mem:BLK (match_dup 3))
17281 (use (match_operand:QI 2 "register_operand" "a"))
17282 (use (match_dup 4))
17283 (use (reg:SI DIRFLAG_REG))]
17285 "{rep\;stosb|rep stosb}"
17286 [(set_attr "type" "str")
17287 (set_attr "prefix_rep" "1")
17288 (set_attr "memory" "store")
17289 (set_attr "mode" "QI")])
17291 (define_insn "*rep_stosqi_rex64"
17292 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17293 (set (match_operand:DI 0 "register_operand" "=D")
17294 (plus:DI (match_operand:DI 3 "register_operand" "0")
17295 (match_operand:DI 4 "register_operand" "1")))
17296 (set (mem:BLK (match_dup 3))
17298 (use (match_operand:QI 2 "register_operand" "a"))
17299 (use (match_dup 4))
17300 (use (reg:SI DIRFLAG_REG))]
17302 "{rep\;stosb|rep stosb}"
17303 [(set_attr "type" "str")
17304 (set_attr "prefix_rep" "1")
17305 (set_attr "memory" "store")
17306 (set_attr "mode" "QI")])
17308 (define_expand "cmpstrsi"
17309 [(set (match_operand:SI 0 "register_operand" "")
17310 (compare:SI (match_operand:BLK 1 "general_operand" "")
17311 (match_operand:BLK 2 "general_operand" "")))
17312 (use (match_operand 3 "general_operand" ""))
17313 (use (match_operand 4 "immediate_operand" ""))]
17314 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
17316 rtx addr1, addr2, out, outlow, count, countreg, align;
17318 /* Can't use this if the user has appropriated esi or edi. */
17319 if (global_regs[4] || global_regs[5])
17323 if (GET_CODE (out) != REG)
17324 out = gen_reg_rtx (SImode);
17326 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
17327 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
17328 if (addr1 != XEXP (operands[1], 0))
17329 operands[1] = replace_equiv_address_nv (operands[1], addr1);
17330 if (addr2 != XEXP (operands[2], 0))
17331 operands[2] = replace_equiv_address_nv (operands[2], addr2);
17333 count = operands[3];
17334 countreg = ix86_zero_extend_to_Pmode (count);
17336 /* %%% Iff we are testing strict equality, we can use known alignment
17337 to good advantage. This may be possible with combine, particularly
17338 once cc0 is dead. */
17339 align = operands[4];
17341 emit_insn (gen_cld ());
17342 if (GET_CODE (count) == CONST_INT)
17344 if (INTVAL (count) == 0)
17346 emit_move_insn (operands[0], const0_rtx);
17349 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
17350 operands[1], operands[2]));
17355 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
17357 emit_insn (gen_cmpsi_1 (countreg, countreg));
17358 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
17359 operands[1], operands[2]));
17362 outlow = gen_lowpart (QImode, out);
17363 emit_insn (gen_cmpintqi (outlow));
17364 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
17366 if (operands[0] != out)
17367 emit_move_insn (operands[0], out);
17372 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
17374 (define_expand "cmpintqi"
17375 [(set (match_dup 1)
17376 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17378 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17379 (parallel [(set (match_operand:QI 0 "register_operand" "")
17380 (minus:QI (match_dup 1)
17382 (clobber (reg:CC FLAGS_REG))])]
17384 "operands[1] = gen_reg_rtx (QImode);
17385 operands[2] = gen_reg_rtx (QImode);")
17387 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
17388 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
17390 (define_expand "cmpstrqi_nz_1"
17391 [(parallel [(set (reg:CC FLAGS_REG)
17392 (compare:CC (match_operand 4 "memory_operand" "")
17393 (match_operand 5 "memory_operand" "")))
17394 (use (match_operand 2 "register_operand" ""))
17395 (use (match_operand:SI 3 "immediate_operand" ""))
17396 (use (reg:SI DIRFLAG_REG))
17397 (clobber (match_operand 0 "register_operand" ""))
17398 (clobber (match_operand 1 "register_operand" ""))
17399 (clobber (match_dup 2))])]
17403 (define_insn "*cmpstrqi_nz_1"
17404 [(set (reg:CC FLAGS_REG)
17405 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17406 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
17407 (use (match_operand:SI 6 "register_operand" "2"))
17408 (use (match_operand:SI 3 "immediate_operand" "i"))
17409 (use (reg:SI DIRFLAG_REG))
17410 (clobber (match_operand:SI 0 "register_operand" "=S"))
17411 (clobber (match_operand:SI 1 "register_operand" "=D"))
17412 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17415 [(set_attr "type" "str")
17416 (set_attr "mode" "QI")
17417 (set_attr "prefix_rep" "1")])
17419 (define_insn "*cmpstrqi_nz_rex_1"
17420 [(set (reg:CC FLAGS_REG)
17421 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17422 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
17423 (use (match_operand:DI 6 "register_operand" "2"))
17424 (use (match_operand:SI 3 "immediate_operand" "i"))
17425 (use (reg:SI DIRFLAG_REG))
17426 (clobber (match_operand:DI 0 "register_operand" "=S"))
17427 (clobber (match_operand:DI 1 "register_operand" "=D"))
17428 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17431 [(set_attr "type" "str")
17432 (set_attr "mode" "QI")
17433 (set_attr "prefix_rep" "1")])
17435 ;; The same, but the count is not known to not be zero.
17437 (define_expand "cmpstrqi_1"
17438 [(parallel [(set (reg:CC FLAGS_REG)
17439 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
17441 (compare:CC (match_operand 4 "memory_operand" "")
17442 (match_operand 5 "memory_operand" ""))
17444 (use (match_operand:SI 3 "immediate_operand" ""))
17445 (use (reg:CC FLAGS_REG))
17446 (use (reg:SI DIRFLAG_REG))
17447 (clobber (match_operand 0 "register_operand" ""))
17448 (clobber (match_operand 1 "register_operand" ""))
17449 (clobber (match_dup 2))])]
17453 (define_insn "*cmpstrqi_1"
17454 [(set (reg:CC FLAGS_REG)
17455 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
17457 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17458 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
17460 (use (match_operand:SI 3 "immediate_operand" "i"))
17461 (use (reg:CC FLAGS_REG))
17462 (use (reg:SI DIRFLAG_REG))
17463 (clobber (match_operand:SI 0 "register_operand" "=S"))
17464 (clobber (match_operand:SI 1 "register_operand" "=D"))
17465 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17468 [(set_attr "type" "str")
17469 (set_attr "mode" "QI")
17470 (set_attr "prefix_rep" "1")])
17472 (define_insn "*cmpstrqi_rex_1"
17473 [(set (reg:CC FLAGS_REG)
17474 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
17476 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17477 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
17479 (use (match_operand:SI 3 "immediate_operand" "i"))
17480 (use (reg:CC FLAGS_REG))
17481 (use (reg:SI DIRFLAG_REG))
17482 (clobber (match_operand:DI 0 "register_operand" "=S"))
17483 (clobber (match_operand:DI 1 "register_operand" "=D"))
17484 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17487 [(set_attr "type" "str")
17488 (set_attr "mode" "QI")
17489 (set_attr "prefix_rep" "1")])
17491 (define_expand "strlensi"
17492 [(set (match_operand:SI 0 "register_operand" "")
17493 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
17494 (match_operand:QI 2 "immediate_operand" "")
17495 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17498 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17504 (define_expand "strlendi"
17505 [(set (match_operand:DI 0 "register_operand" "")
17506 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
17507 (match_operand:QI 2 "immediate_operand" "")
17508 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17511 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17517 (define_expand "strlenqi_1"
17518 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
17519 (use (reg:SI DIRFLAG_REG))
17520 (clobber (match_operand 1 "register_operand" ""))
17521 (clobber (reg:CC FLAGS_REG))])]
17525 (define_insn "*strlenqi_1"
17526 [(set (match_operand:SI 0 "register_operand" "=&c")
17527 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
17528 (match_operand:QI 2 "register_operand" "a")
17529 (match_operand:SI 3 "immediate_operand" "i")
17530 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
17531 (use (reg:SI DIRFLAG_REG))
17532 (clobber (match_operand:SI 1 "register_operand" "=D"))
17533 (clobber (reg:CC FLAGS_REG))]
17536 [(set_attr "type" "str")
17537 (set_attr "mode" "QI")
17538 (set_attr "prefix_rep" "1")])
17540 (define_insn "*strlenqi_rex_1"
17541 [(set (match_operand:DI 0 "register_operand" "=&c")
17542 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
17543 (match_operand:QI 2 "register_operand" "a")
17544 (match_operand:DI 3 "immediate_operand" "i")
17545 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
17546 (use (reg:SI DIRFLAG_REG))
17547 (clobber (match_operand:DI 1 "register_operand" "=D"))
17548 (clobber (reg:CC FLAGS_REG))]
17551 [(set_attr "type" "str")
17552 (set_attr "mode" "QI")
17553 (set_attr "prefix_rep" "1")])
17555 ;; Peephole optimizations to clean up after cmpstr*. This should be
17556 ;; handled in combine, but it is not currently up to the task.
17557 ;; When used for their truth value, the cmpstr* expanders generate
17566 ;; The intermediate three instructions are unnecessary.
17568 ;; This one handles cmpstr*_nz_1...
17571 (set (reg:CC FLAGS_REG)
17572 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17573 (mem:BLK (match_operand 5 "register_operand" ""))))
17574 (use (match_operand 6 "register_operand" ""))
17575 (use (match_operand:SI 3 "immediate_operand" ""))
17576 (use (reg:SI DIRFLAG_REG))
17577 (clobber (match_operand 0 "register_operand" ""))
17578 (clobber (match_operand 1 "register_operand" ""))
17579 (clobber (match_operand 2 "register_operand" ""))])
17580 (set (match_operand:QI 7 "register_operand" "")
17581 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17582 (set (match_operand:QI 8 "register_operand" "")
17583 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17585 (compare (match_dup 7) (match_dup 8)))
17587 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17589 (set (reg:CC FLAGS_REG)
17590 (compare:CC (mem:BLK (match_dup 4))
17591 (mem:BLK (match_dup 5))))
17592 (use (match_dup 6))
17593 (use (match_dup 3))
17594 (use (reg:SI DIRFLAG_REG))
17595 (clobber (match_dup 0))
17596 (clobber (match_dup 1))
17597 (clobber (match_dup 2))])]
17600 ;; ...and this one handles cmpstr*_1.
17603 (set (reg:CC FLAGS_REG)
17604 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
17606 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17607 (mem:BLK (match_operand 5 "register_operand" "")))
17609 (use (match_operand:SI 3 "immediate_operand" ""))
17610 (use (reg:CC FLAGS_REG))
17611 (use (reg:SI DIRFLAG_REG))
17612 (clobber (match_operand 0 "register_operand" ""))
17613 (clobber (match_operand 1 "register_operand" ""))
17614 (clobber (match_operand 2 "register_operand" ""))])
17615 (set (match_operand:QI 7 "register_operand" "")
17616 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17617 (set (match_operand:QI 8 "register_operand" "")
17618 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17620 (compare (match_dup 7) (match_dup 8)))
17622 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17624 (set (reg:CC FLAGS_REG)
17625 (if_then_else:CC (ne (match_dup 6)
17627 (compare:CC (mem:BLK (match_dup 4))
17628 (mem:BLK (match_dup 5)))
17630 (use (match_dup 3))
17631 (use (reg:CC FLAGS_REG))
17632 (use (reg:SI DIRFLAG_REG))
17633 (clobber (match_dup 0))
17634 (clobber (match_dup 1))
17635 (clobber (match_dup 2))])]
17640 ;; Conditional move instructions.
17642 (define_expand "movdicc"
17643 [(set (match_operand:DI 0 "register_operand" "")
17644 (if_then_else:DI (match_operand 1 "comparison_operator" "")
17645 (match_operand:DI 2 "general_operand" "")
17646 (match_operand:DI 3 "general_operand" "")))]
17648 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17650 (define_insn "x86_movdicc_0_m1_rex64"
17651 [(set (match_operand:DI 0 "register_operand" "=r")
17652 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
17655 (clobber (reg:CC FLAGS_REG))]
17658 ; Since we don't have the proper number of operands for an alu insn,
17659 ; fill in all the blanks.
17660 [(set_attr "type" "alu")
17661 (set_attr "pent_pair" "pu")
17662 (set_attr "memory" "none")
17663 (set_attr "imm_disp" "false")
17664 (set_attr "mode" "DI")
17665 (set_attr "length_immediate" "0")])
17667 (define_insn "movdicc_c_rex64"
17668 [(set (match_operand:DI 0 "register_operand" "=r,r")
17669 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
17670 [(reg 17) (const_int 0)])
17671 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
17672 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
17673 "TARGET_64BIT && TARGET_CMOVE
17674 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17676 cmov%O2%C1\t{%2, %0|%0, %2}
17677 cmov%O2%c1\t{%3, %0|%0, %3}"
17678 [(set_attr "type" "icmov")
17679 (set_attr "mode" "DI")])
17681 (define_expand "movsicc"
17682 [(set (match_operand:SI 0 "register_operand" "")
17683 (if_then_else:SI (match_operand 1 "comparison_operator" "")
17684 (match_operand:SI 2 "general_operand" "")
17685 (match_operand:SI 3 "general_operand" "")))]
17687 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17689 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
17690 ;; the register first winds up with `sbbl $0,reg', which is also weird.
17691 ;; So just document what we're doing explicitly.
17693 (define_insn "x86_movsicc_0_m1"
17694 [(set (match_operand:SI 0 "register_operand" "=r")
17695 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
17698 (clobber (reg:CC FLAGS_REG))]
17701 ; Since we don't have the proper number of operands for an alu insn,
17702 ; fill in all the blanks.
17703 [(set_attr "type" "alu")
17704 (set_attr "pent_pair" "pu")
17705 (set_attr "memory" "none")
17706 (set_attr "imm_disp" "false")
17707 (set_attr "mode" "SI")
17708 (set_attr "length_immediate" "0")])
17710 (define_insn "*movsicc_noc"
17711 [(set (match_operand:SI 0 "register_operand" "=r,r")
17712 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
17713 [(reg 17) (const_int 0)])
17714 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
17715 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
17717 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17719 cmov%O2%C1\t{%2, %0|%0, %2}
17720 cmov%O2%c1\t{%3, %0|%0, %3}"
17721 [(set_attr "type" "icmov")
17722 (set_attr "mode" "SI")])
17724 (define_expand "movhicc"
17725 [(set (match_operand:HI 0 "register_operand" "")
17726 (if_then_else:HI (match_operand 1 "comparison_operator" "")
17727 (match_operand:HI 2 "general_operand" "")
17728 (match_operand:HI 3 "general_operand" "")))]
17729 "TARGET_HIMODE_MATH"
17730 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17732 (define_insn "*movhicc_noc"
17733 [(set (match_operand:HI 0 "register_operand" "=r,r")
17734 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
17735 [(reg 17) (const_int 0)])
17736 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
17737 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
17739 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17741 cmov%O2%C1\t{%2, %0|%0, %2}
17742 cmov%O2%c1\t{%3, %0|%0, %3}"
17743 [(set_attr "type" "icmov")
17744 (set_attr "mode" "HI")])
17746 (define_expand "movqicc"
17747 [(set (match_operand:QI 0 "register_operand" "")
17748 (if_then_else:QI (match_operand 1 "comparison_operator" "")
17749 (match_operand:QI 2 "general_operand" "")
17750 (match_operand:QI 3 "general_operand" "")))]
17751 "TARGET_QIMODE_MATH"
17752 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17754 (define_insn_and_split "*movqicc_noc"
17755 [(set (match_operand:QI 0 "register_operand" "=r,r")
17756 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
17757 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17758 (match_operand:QI 2 "register_operand" "r,0")
17759 (match_operand:QI 3 "register_operand" "0,r")))]
17760 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
17762 "&& reload_completed"
17763 [(set (match_dup 0)
17764 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17767 "operands[0] = gen_lowpart (SImode, operands[0]);
17768 operands[2] = gen_lowpart (SImode, operands[2]);
17769 operands[3] = gen_lowpart (SImode, operands[3]);"
17770 [(set_attr "type" "icmov")
17771 (set_attr "mode" "SI")])
17773 (define_expand "movsfcc"
17774 [(set (match_operand:SF 0 "register_operand" "")
17775 (if_then_else:SF (match_operand 1 "comparison_operator" "")
17776 (match_operand:SF 2 "register_operand" "")
17777 (match_operand:SF 3 "register_operand" "")))]
17779 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17781 (define_insn "*movsfcc_1"
17782 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17783 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17784 [(reg 17) (const_int 0)])
17785 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17786 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17788 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17790 fcmov%F1\t{%2, %0|%0, %2}
17791 fcmov%f1\t{%3, %0|%0, %3}
17792 cmov%O2%C1\t{%2, %0|%0, %2}
17793 cmov%O2%c1\t{%3, %0|%0, %3}"
17794 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17795 (set_attr "mode" "SF,SF,SI,SI")])
17797 (define_expand "movdfcc"
17798 [(set (match_operand:DF 0 "register_operand" "")
17799 (if_then_else:DF (match_operand 1 "comparison_operator" "")
17800 (match_operand:DF 2 "register_operand" "")
17801 (match_operand:DF 3 "register_operand" "")))]
17803 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17805 (define_insn "*movdfcc_1"
17806 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
17807 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17808 [(reg 17) (const_int 0)])
17809 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17810 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17811 "!TARGET_64BIT && TARGET_CMOVE
17812 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17814 fcmov%F1\t{%2, %0|%0, %2}
17815 fcmov%f1\t{%3, %0|%0, %3}
17818 [(set_attr "type" "fcmov,fcmov,multi,multi")
17819 (set_attr "mode" "DF")])
17821 (define_insn "*movdfcc_1_rex64"
17822 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17823 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17824 [(reg 17) (const_int 0)])
17825 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
17826 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
17827 "TARGET_64BIT && TARGET_CMOVE
17828 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17830 fcmov%F1\t{%2, %0|%0, %2}
17831 fcmov%f1\t{%3, %0|%0, %3}
17832 cmov%O2%C1\t{%2, %0|%0, %2}
17833 cmov%O2%c1\t{%3, %0|%0, %3}"
17834 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17835 (set_attr "mode" "DF")])
17838 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
17839 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17840 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17841 (match_operand:DF 2 "nonimmediate_operand" "")
17842 (match_operand:DF 3 "nonimmediate_operand" "")))]
17843 "!TARGET_64BIT && reload_completed"
17844 [(set (match_dup 2)
17845 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17849 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17852 "split_di (operands+2, 1, operands+5, operands+6);
17853 split_di (operands+3, 1, operands+7, operands+8);
17854 split_di (operands, 1, operands+2, operands+3);")
17856 (define_expand "movxfcc"
17857 [(set (match_operand:XF 0 "register_operand" "")
17858 (if_then_else:XF (match_operand 1 "comparison_operator" "")
17859 (match_operand:XF 2 "register_operand" "")
17860 (match_operand:XF 3 "register_operand" "")))]
17862 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17864 (define_insn "*movxfcc_1"
17865 [(set (match_operand:XF 0 "register_operand" "=f,f")
17866 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
17867 [(reg 17) (const_int 0)])
17868 (match_operand:XF 2 "register_operand" "f,0")
17869 (match_operand:XF 3 "register_operand" "0,f")))]
17872 fcmov%F1\t{%2, %0|%0, %2}
17873 fcmov%f1\t{%3, %0|%0, %3}"
17874 [(set_attr "type" "fcmov")
17875 (set_attr "mode" "XF")])
17877 (define_expand "minsf3"
17879 (set (match_operand:SF 0 "register_operand" "")
17880 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17881 (match_operand:SF 2 "nonimmediate_operand" ""))
17884 (clobber (reg:CC FLAGS_REG))])]
17888 (define_insn "*minsf"
17889 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17890 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
17891 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17894 (clobber (reg:CC FLAGS_REG))]
17895 "TARGET_SSE && TARGET_IEEE_FP"
17898 (define_insn "*minsf_nonieee"
17899 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17900 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17901 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17904 (clobber (reg:CC FLAGS_REG))]
17905 "TARGET_SSE && !TARGET_IEEE_FP
17906 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17910 [(set (match_operand:SF 0 "register_operand" "")
17911 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17912 (match_operand:SF 2 "nonimmediate_operand" ""))
17913 (match_operand:SF 3 "register_operand" "")
17914 (match_operand:SF 4 "nonimmediate_operand" "")))
17915 (clobber (reg:CC FLAGS_REG))]
17916 "SSE_REG_P (operands[0]) && reload_completed
17917 && ((operands_match_p (operands[1], operands[3])
17918 && operands_match_p (operands[2], operands[4]))
17919 || (operands_match_p (operands[1], operands[4])
17920 && operands_match_p (operands[2], operands[3])))"
17921 [(set (match_dup 0)
17922 (if_then_else:SF (lt (match_dup 1)
17927 ;; Conditional addition patterns
17928 (define_expand "addqicc"
17929 [(match_operand:QI 0 "register_operand" "")
17930 (match_operand 1 "comparison_operator" "")
17931 (match_operand:QI 2 "register_operand" "")
17932 (match_operand:QI 3 "const_int_operand" "")]
17934 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17936 (define_expand "addhicc"
17937 [(match_operand:HI 0 "register_operand" "")
17938 (match_operand 1 "comparison_operator" "")
17939 (match_operand:HI 2 "register_operand" "")
17940 (match_operand:HI 3 "const_int_operand" "")]
17942 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17944 (define_expand "addsicc"
17945 [(match_operand:SI 0 "register_operand" "")
17946 (match_operand 1 "comparison_operator" "")
17947 (match_operand:SI 2 "register_operand" "")
17948 (match_operand:SI 3 "const_int_operand" "")]
17950 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17952 (define_expand "adddicc"
17953 [(match_operand:DI 0 "register_operand" "")
17954 (match_operand 1 "comparison_operator" "")
17955 (match_operand:DI 2 "register_operand" "")
17956 (match_operand:DI 3 "const_int_operand" "")]
17958 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17960 ;; We can't represent the LT test directly. Do this by swapping the operands.
17963 [(set (match_operand:SF 0 "fp_register_operand" "")
17964 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17965 (match_operand:SF 2 "register_operand" ""))
17966 (match_operand:SF 3 "register_operand" "")
17967 (match_operand:SF 4 "register_operand" "")))
17968 (clobber (reg:CC FLAGS_REG))]
17970 && ((operands_match_p (operands[1], operands[3])
17971 && operands_match_p (operands[2], operands[4]))
17972 || (operands_match_p (operands[1], operands[4])
17973 && operands_match_p (operands[2], operands[3])))"
17974 [(set (reg:CCFP FLAGS_REG)
17975 (compare:CCFP (match_dup 2)
17978 (if_then_else:SF (ge (reg:CCFP FLAGS_REG) (const_int 0))
17982 (define_insn "*minsf_sse"
17983 [(set (match_operand:SF 0 "register_operand" "=x")
17984 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
17985 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17988 "TARGET_SSE && reload_completed"
17989 "minss\t{%2, %0|%0, %2}"
17990 [(set_attr "type" "sse")
17991 (set_attr "mode" "SF")])
17993 (define_expand "mindf3"
17995 (set (match_operand:DF 0 "register_operand" "")
17996 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17997 (match_operand:DF 2 "nonimmediate_operand" ""))
18000 (clobber (reg:CC FLAGS_REG))])]
18001 "TARGET_SSE2 && TARGET_SSE_MATH"
18004 (define_insn "*mindf"
18005 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
18006 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
18007 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
18010 (clobber (reg:CC FLAGS_REG))]
18011 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
18014 (define_insn "*mindf_nonieee"
18015 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
18016 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
18017 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
18020 (clobber (reg:CC FLAGS_REG))]
18021 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
18022 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18026 [(set (match_operand:DF 0 "register_operand" "")
18027 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
18028 (match_operand:DF 2 "nonimmediate_operand" ""))
18029 (match_operand:DF 3 "register_operand" "")
18030 (match_operand:DF 4 "nonimmediate_operand" "")))
18031 (clobber (reg:CC FLAGS_REG))]
18032 "SSE_REG_P (operands[0]) && reload_completed
18033 && ((operands_match_p (operands[1], operands[3])
18034 && operands_match_p (operands[2], operands[4]))
18035 || (operands_match_p (operands[1], operands[4])
18036 && operands_match_p (operands[2], operands[3])))"
18037 [(set (match_dup 0)
18038 (if_then_else:DF (lt (match_dup 1)
18043 ;; We can't represent the LT test directly. Do this by swapping the operands.
18045 [(set (match_operand:DF 0 "fp_register_operand" "")
18046 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
18047 (match_operand:DF 2 "register_operand" ""))
18048 (match_operand:DF 3 "register_operand" "")
18049 (match_operand:DF 4 "register_operand" "")))
18050 (clobber (reg:CC FLAGS_REG))]
18052 && ((operands_match_p (operands[1], operands[3])
18053 && operands_match_p (operands[2], operands[4]))
18054 || (operands_match_p (operands[1], operands[4])
18055 && operands_match_p (operands[2], operands[3])))"
18056 [(set (reg:CCFP FLAGS_REG)
18057 (compare:CCFP (match_dup 2)
18060 (if_then_else:DF (ge (reg:CCFP FLAGS_REG) (const_int 0))
18064 (define_insn "*mindf_sse"
18065 [(set (match_operand:DF 0 "register_operand" "=Y")
18066 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
18067 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
18070 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
18071 "minsd\t{%2, %0|%0, %2}"
18072 [(set_attr "type" "sse")
18073 (set_attr "mode" "DF")])
18075 (define_expand "maxsf3"
18077 (set (match_operand:SF 0 "register_operand" "")
18078 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
18079 (match_operand:SF 2 "nonimmediate_operand" ""))
18082 (clobber (reg:CC FLAGS_REG))])]
18086 (define_insn "*maxsf"
18087 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
18088 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
18089 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
18092 (clobber (reg:CC FLAGS_REG))]
18093 "TARGET_SSE && TARGET_IEEE_FP"
18096 (define_insn "*maxsf_nonieee"
18097 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
18098 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
18099 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
18102 (clobber (reg:CC FLAGS_REG))]
18103 "TARGET_SSE && !TARGET_IEEE_FP
18104 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18108 [(set (match_operand:SF 0 "register_operand" "")
18109 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
18110 (match_operand:SF 2 "nonimmediate_operand" ""))
18111 (match_operand:SF 3 "register_operand" "")
18112 (match_operand:SF 4 "nonimmediate_operand" "")))
18113 (clobber (reg:CC FLAGS_REG))]
18114 "SSE_REG_P (operands[0]) && reload_completed
18115 && ((operands_match_p (operands[1], operands[3])
18116 && operands_match_p (operands[2], operands[4]))
18117 || (operands_match_p (operands[1], operands[4])
18118 && operands_match_p (operands[2], operands[3])))"
18119 [(set (match_dup 0)
18120 (if_then_else:SF (gt (match_dup 1)
18126 [(set (match_operand:SF 0 "fp_register_operand" "")
18127 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
18128 (match_operand:SF 2 "register_operand" ""))
18129 (match_operand:SF 3 "register_operand" "")
18130 (match_operand:SF 4 "register_operand" "")))
18131 (clobber (reg:CC FLAGS_REG))]
18133 && ((operands_match_p (operands[1], operands[3])
18134 && operands_match_p (operands[2], operands[4]))
18135 || (operands_match_p (operands[1], operands[4])
18136 && operands_match_p (operands[2], operands[3])))"
18137 [(set (reg:CCFP FLAGS_REG)
18138 (compare:CCFP (match_dup 1)
18141 (if_then_else:SF (gt (reg:CCFP FLAGS_REG) (const_int 0))
18145 (define_insn "*maxsf_sse"
18146 [(set (match_operand:SF 0 "register_operand" "=x")
18147 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
18148 (match_operand:SF 2 "nonimmediate_operand" "xm"))
18151 "TARGET_SSE && reload_completed"
18152 "maxss\t{%2, %0|%0, %2}"
18153 [(set_attr "type" "sse")
18154 (set_attr "mode" "SF")])
18156 (define_expand "maxdf3"
18158 (set (match_operand:DF 0 "register_operand" "")
18159 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
18160 (match_operand:DF 2 "nonimmediate_operand" ""))
18163 (clobber (reg:CC FLAGS_REG))])]
18164 "TARGET_SSE2 && TARGET_SSE_MATH"
18167 (define_insn "*maxdf"
18168 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
18169 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
18170 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
18173 (clobber (reg:CC FLAGS_REG))]
18174 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
18177 (define_insn "*maxdf_nonieee"
18178 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
18179 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
18180 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
18183 (clobber (reg:CC FLAGS_REG))]
18184 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
18185 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18189 [(set (match_operand:DF 0 "register_operand" "")
18190 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
18191 (match_operand:DF 2 "nonimmediate_operand" ""))
18192 (match_operand:DF 3 "register_operand" "")
18193 (match_operand:DF 4 "nonimmediate_operand" "")))
18194 (clobber (reg:CC FLAGS_REG))]
18195 "SSE_REG_P (operands[0]) && reload_completed
18196 && ((operands_match_p (operands[1], operands[3])
18197 && operands_match_p (operands[2], operands[4]))
18198 || (operands_match_p (operands[1], operands[4])
18199 && operands_match_p (operands[2], operands[3])))"
18200 [(set (match_dup 0)
18201 (if_then_else:DF (gt (match_dup 1)
18207 [(set (match_operand:DF 0 "fp_register_operand" "")
18208 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
18209 (match_operand:DF 2 "register_operand" ""))
18210 (match_operand:DF 3 "register_operand" "")
18211 (match_operand:DF 4 "register_operand" "")))
18212 (clobber (reg:CC FLAGS_REG))]
18214 && ((operands_match_p (operands[1], operands[3])
18215 && operands_match_p (operands[2], operands[4]))
18216 || (operands_match_p (operands[1], operands[4])
18217 && operands_match_p (operands[2], operands[3])))"
18218 [(set (reg:CCFP FLAGS_REG)
18219 (compare:CCFP (match_dup 1)
18222 (if_then_else:DF (gt (reg:CCFP FLAGS_REG) (const_int 0))
18226 (define_insn "*maxdf_sse"
18227 [(set (match_operand:DF 0 "register_operand" "=Y")
18228 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
18229 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
18232 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
18233 "maxsd\t{%2, %0|%0, %2}"
18234 [(set_attr "type" "sse")
18235 (set_attr "mode" "DF")])
18237 ;; Misc patterns (?)
18239 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
18240 ;; Otherwise there will be nothing to keep
18242 ;; [(set (reg ebp) (reg esp))]
18243 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
18244 ;; (clobber (eflags)]
18245 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
18247 ;; in proper program order.
18248 (define_insn "pro_epilogue_adjust_stack_1"
18249 [(set (match_operand:SI 0 "register_operand" "=r,r")
18250 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
18251 (match_operand:SI 2 "immediate_operand" "i,i")))
18252 (clobber (reg:CC FLAGS_REG))
18253 (clobber (mem:BLK (scratch)))]
18256 switch (get_attr_type (insn))
18259 return "mov{l}\t{%1, %0|%0, %1}";
18262 if (GET_CODE (operands[2]) == CONST_INT
18263 && (INTVAL (operands[2]) == 128
18264 || (INTVAL (operands[2]) < 0
18265 && INTVAL (operands[2]) != -128)))
18267 operands[2] = GEN_INT (-INTVAL (operands[2]));
18268 return "sub{l}\t{%2, %0|%0, %2}";
18270 return "add{l}\t{%2, %0|%0, %2}";
18273 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18274 return "lea{l}\t{%a2, %0|%0, %a2}";
18280 [(set (attr "type")
18281 (cond [(eq_attr "alternative" "0")
18282 (const_string "alu")
18283 (match_operand:SI 2 "const0_operand" "")
18284 (const_string "imov")
18286 (const_string "lea")))
18287 (set_attr "mode" "SI")])
18289 (define_insn "pro_epilogue_adjust_stack_rex64"
18290 [(set (match_operand:DI 0 "register_operand" "=r,r")
18291 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18292 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
18293 (clobber (reg:CC FLAGS_REG))
18294 (clobber (mem:BLK (scratch)))]
18297 switch (get_attr_type (insn))
18300 return "mov{q}\t{%1, %0|%0, %1}";
18303 if (GET_CODE (operands[2]) == CONST_INT
18304 /* Avoid overflows. */
18305 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
18306 && (INTVAL (operands[2]) == 128
18307 || (INTVAL (operands[2]) < 0
18308 && INTVAL (operands[2]) != -128)))
18310 operands[2] = GEN_INT (-INTVAL (operands[2]));
18311 return "sub{q}\t{%2, %0|%0, %2}";
18313 return "add{q}\t{%2, %0|%0, %2}";
18316 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18317 return "lea{q}\t{%a2, %0|%0, %a2}";
18323 [(set (attr "type")
18324 (cond [(eq_attr "alternative" "0")
18325 (const_string "alu")
18326 (match_operand:DI 2 "const0_operand" "")
18327 (const_string "imov")
18329 (const_string "lea")))
18330 (set_attr "mode" "DI")])
18332 (define_insn "pro_epilogue_adjust_stack_rex64_2"
18333 [(set (match_operand:DI 0 "register_operand" "=r,r")
18334 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18335 (match_operand:DI 3 "immediate_operand" "i,i")))
18336 (use (match_operand:DI 2 "register_operand" "r,r"))
18337 (clobber (reg:CC FLAGS_REG))
18338 (clobber (mem:BLK (scratch)))]
18341 switch (get_attr_type (insn))
18344 return "add{q}\t{%2, %0|%0, %2}";
18347 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
18348 return "lea{q}\t{%a2, %0|%0, %a2}";
18354 [(set_attr "type" "alu,lea")
18355 (set_attr "mode" "DI")])
18357 ;; Placeholder for the conditional moves. This one is split either to SSE
18358 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
18359 ;; fact is that compares supported by the cmp??ss instructions are exactly
18360 ;; swapped of those supported by cmove sequence.
18361 ;; The EQ/NE comparisons also needs bit care, since they are not directly
18362 ;; supported by i387 comparisons and we do need to emit two conditional moves
18365 (define_insn "sse_movsfcc"
18366 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
18367 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18368 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
18369 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
18370 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
18371 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
18372 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18373 (clobber (reg:CC FLAGS_REG))]
18375 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18376 /* Avoid combine from being smart and converting min/max
18377 instruction patterns into conditional moves. */
18378 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18379 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18380 || !rtx_equal_p (operands[4], operands[2])
18381 || !rtx_equal_p (operands[5], operands[3]))
18382 && (!TARGET_IEEE_FP
18383 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18386 (define_insn "sse_movsfcc_eq"
18387 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
18388 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
18389 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
18390 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
18391 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
18392 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
18393 (clobber (reg:CC FLAGS_REG))]
18395 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18398 (define_insn "sse_movdfcc"
18399 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
18400 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18401 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
18402 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
18403 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
18404 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
18405 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18406 (clobber (reg:CC FLAGS_REG))]
18408 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18409 /* Avoid combine from being smart and converting min/max
18410 instruction patterns into conditional moves. */
18411 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18412 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18413 || !rtx_equal_p (operands[4], operands[2])
18414 || !rtx_equal_p (operands[5], operands[3]))
18415 && (!TARGET_IEEE_FP
18416 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18419 (define_insn "sse_movdfcc_eq"
18420 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
18421 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
18422 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
18423 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
18424 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
18425 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
18426 (clobber (reg:CC FLAGS_REG))]
18428 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18431 ;; For non-sse moves just expand the usual cmove sequence.
18433 [(set (match_operand 0 "register_operand" "")
18434 (if_then_else (match_operator 1 "comparison_operator"
18435 [(match_operand 4 "nonimmediate_operand" "")
18436 (match_operand 5 "register_operand" "")])
18437 (match_operand 2 "nonimmediate_operand" "")
18438 (match_operand 3 "nonimmediate_operand" "")))
18439 (clobber (match_operand 6 "" ""))
18440 (clobber (reg:CC FLAGS_REG))]
18441 "!SSE_REG_P (operands[0]) && reload_completed
18442 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
18445 ix86_compare_op0 = operands[5];
18446 ix86_compare_op1 = operands[4];
18447 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
18448 VOIDmode, operands[5], operands[4]);
18449 ix86_expand_fp_movcc (operands);
18453 ;; Split SSE based conditional move into sequence:
18454 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
18455 ;; and op2, op0 - zero op2 if comparison was false
18456 ;; nand op0, op3 - load op3 to op0 if comparison was false
18457 ;; or op2, op0 - get the nonzero one into the result.
18459 [(set (match_operand:SF 0 "register_operand" "")
18460 (if_then_else (match_operator:SF 1 "sse_comparison_operator"
18461 [(match_operand:SF 4 "register_operand" "")
18462 (match_operand:SF 5 "nonimmediate_operand" "")])
18463 (match_operand:SF 2 "register_operand" "")
18464 (match_operand:SF 3 "register_operand" "")))
18465 (clobber (match_operand 6 "" ""))
18466 (clobber (reg:CC FLAGS_REG))]
18467 "SSE_REG_P (operands[0]) && reload_completed"
18468 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18469 (set (match_dup 2) (and:V4SF (match_dup 2)
18471 (set (match_dup 8) (and:V4SF (not:V4SF (match_dup 8))
18473 (set (match_dup 0) (ior:V4SF (match_dup 6)
18476 /* If op2 == op3, op3 would be clobbered before it is used. */
18477 if (operands_match_p (operands[2], operands[3]))
18479 emit_move_insn (operands[0], operands[2]);
18483 PUT_MODE (operands[1], GET_MODE (operands[0]));
18484 if (operands_match_p (operands[0], operands[4]))
18485 operands[6] = operands[4], operands[7] = operands[2];
18487 operands[6] = operands[2], operands[7] = operands[4];
18488 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18489 operands[2] = simplify_gen_subreg (V4SFmode, operands[2], SFmode, 0);
18490 operands[3] = simplify_gen_subreg (V4SFmode, operands[3], SFmode, 0);
18491 operands[8] = simplify_gen_subreg (V4SFmode, operands[4], SFmode, 0);
18492 operands[6] = simplify_gen_subreg (V4SFmode, operands[6], SFmode, 0);
18493 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18497 [(set (match_operand:DF 0 "register_operand" "")
18498 (if_then_else (match_operator:DF 1 "sse_comparison_operator"
18499 [(match_operand:DF 4 "register_operand" "")
18500 (match_operand:DF 5 "nonimmediate_operand" "")])
18501 (match_operand:DF 2 "register_operand" "")
18502 (match_operand:DF 3 "register_operand" "")))
18503 (clobber (match_operand 6 "" ""))
18504 (clobber (reg:CC FLAGS_REG))]
18505 "SSE_REG_P (operands[0]) && reload_completed"
18506 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18507 (set (match_dup 2) (and:V2DF (match_dup 2)
18509 (set (match_dup 8) (and:V2DF (not:V2DF (match_dup 8))
18511 (set (match_dup 0) (ior:V2DF (match_dup 6)
18514 if (GET_MODE (operands[2]) == DFmode
18515 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
18517 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18518 emit_insn (gen_sse2_unpcklpd (op, op, op));
18519 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18520 emit_insn (gen_sse2_unpcklpd (op, op, op));
18523 /* If op2 == op3, op3 would be clobbered before it is used. */
18524 if (operands_match_p (operands[2], operands[3]))
18526 emit_move_insn (operands[0], operands[2]);
18530 PUT_MODE (operands[1], GET_MODE (operands[0]));
18531 if (operands_match_p (operands[0], operands[4]))
18532 operands[6] = operands[4], operands[7] = operands[2];
18534 operands[6] = operands[2], operands[7] = operands[4];
18535 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18536 operands[2] = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18537 operands[3] = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18538 operands[8] = simplify_gen_subreg (V2DFmode, operands[4], DFmode, 0);
18539 operands[6] = simplify_gen_subreg (V2DFmode, operands[6], DFmode, 0);
18540 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18543 ;; Special case of conditional move we can handle effectively.
18544 ;; Do not brother with the integer/floating point case, since these are
18545 ;; bot considerably slower, unlike in the generic case.
18546 (define_insn "*sse_movsfcc_const0_1"
18547 [(set (match_operand:SF 0 "register_operand" "=&x")
18548 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18549 [(match_operand:SF 4 "register_operand" "0")
18550 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18551 (match_operand:SF 2 "register_operand" "x")
18552 (match_operand:SF 3 "const0_operand" "X")))]
18556 (define_insn "*sse_movsfcc_const0_2"
18557 [(set (match_operand:SF 0 "register_operand" "=&x")
18558 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18559 [(match_operand:SF 4 "register_operand" "0")
18560 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18561 (match_operand:SF 2 "const0_operand" "X")
18562 (match_operand:SF 3 "register_operand" "x")))]
18566 (define_insn "*sse_movsfcc_const0_3"
18567 [(set (match_operand:SF 0 "register_operand" "=&x")
18568 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18569 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18570 (match_operand:SF 5 "register_operand" "0")])
18571 (match_operand:SF 2 "register_operand" "x")
18572 (match_operand:SF 3 "const0_operand" "X")))]
18576 (define_insn "*sse_movsfcc_const0_4"
18577 [(set (match_operand:SF 0 "register_operand" "=&x")
18578 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18579 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18580 (match_operand:SF 5 "register_operand" "0")])
18581 (match_operand:SF 2 "const0_operand" "X")
18582 (match_operand:SF 3 "register_operand" "x")))]
18586 (define_insn "*sse_movdfcc_const0_1"
18587 [(set (match_operand:DF 0 "register_operand" "=&Y")
18588 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18589 [(match_operand:DF 4 "register_operand" "0")
18590 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18591 (match_operand:DF 2 "register_operand" "Y")
18592 (match_operand:DF 3 "const0_operand" "X")))]
18596 (define_insn "*sse_movdfcc_const0_2"
18597 [(set (match_operand:DF 0 "register_operand" "=&Y")
18598 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18599 [(match_operand:DF 4 "register_operand" "0")
18600 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18601 (match_operand:DF 2 "const0_operand" "X")
18602 (match_operand:DF 3 "register_operand" "Y")))]
18606 (define_insn "*sse_movdfcc_const0_3"
18607 [(set (match_operand:DF 0 "register_operand" "=&Y")
18608 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18609 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18610 (match_operand:DF 5 "register_operand" "0")])
18611 (match_operand:DF 2 "register_operand" "Y")
18612 (match_operand:DF 3 "const0_operand" "X")))]
18616 (define_insn "*sse_movdfcc_const0_4"
18617 [(set (match_operand:DF 0 "register_operand" "=&Y")
18618 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18619 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18620 (match_operand:DF 5 "register_operand" "0")])
18621 (match_operand:DF 2 "const0_operand" "X")
18622 (match_operand:DF 3 "register_operand" "Y")))]
18627 [(set (match_operand:SF 0 "register_operand" "")
18628 (if_then_else (match_operator 1 "comparison_operator"
18629 [(match_operand:SF 4 "nonimmediate_operand" "")
18630 (match_operand:SF 5 "nonimmediate_operand" "")])
18631 (match_operand:SF 2 "nonmemory_operand" "")
18632 (match_operand:SF 3 "nonmemory_operand" "")))]
18633 "SSE_REG_P (operands[0]) && reload_completed
18634 && (const0_operand (operands[2], GET_MODE (operands[0]))
18635 || const0_operand (operands[3], GET_MODE (operands[0])))"
18636 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18637 (set (match_dup 8) (and:V4SF (match_dup 6) (match_dup 7)))]
18639 PUT_MODE (operands[1], GET_MODE (operands[0]));
18640 if (!sse_comparison_operator (operands[1], VOIDmode)
18641 || !rtx_equal_p (operands[0], operands[4]))
18643 rtx tmp = operands[5];
18644 operands[5] = operands[4];
18646 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18648 if (!rtx_equal_p (operands[0], operands[4]))
18650 operands[8] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18651 if (const0_operand (operands[2], GET_MODE (operands[2])))
18653 operands[7] = operands[3];
18654 operands[6] = gen_rtx_NOT (V4SFmode, operands[8]);
18658 operands[7] = operands[2];
18659 operands[6] = operands[8];
18661 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18665 [(set (match_operand:DF 0 "register_operand" "")
18666 (if_then_else (match_operator 1 "comparison_operator"
18667 [(match_operand:DF 4 "nonimmediate_operand" "")
18668 (match_operand:DF 5 "nonimmediate_operand" "")])
18669 (match_operand:DF 2 "nonmemory_operand" "")
18670 (match_operand:DF 3 "nonmemory_operand" "")))]
18671 "SSE_REG_P (operands[0]) && reload_completed
18672 && (const0_operand (operands[2], GET_MODE (operands[0]))
18673 || const0_operand (operands[3], GET_MODE (operands[0])))"
18674 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18675 (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))]
18677 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
18678 && GET_MODE (operands[2]) == DFmode)
18680 if (REG_P (operands[2]))
18682 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18683 emit_insn (gen_sse2_unpcklpd (op, op, op));
18685 if (REG_P (operands[3]))
18687 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18688 emit_insn (gen_sse2_unpcklpd (op, op, op));
18691 PUT_MODE (operands[1], GET_MODE (operands[0]));
18692 if (!sse_comparison_operator (operands[1], VOIDmode)
18693 || !rtx_equal_p (operands[0], operands[4]))
18695 rtx tmp = operands[5];
18696 operands[5] = operands[4];
18698 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18700 if (!rtx_equal_p (operands[0], operands[4]))
18702 operands[8] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18703 if (const0_operand (operands[2], GET_MODE (operands[2])))
18705 operands[7] = operands[3];
18706 operands[6] = gen_rtx_NOT (V2DFmode, operands[8]);
18710 operands[7] = operands[2];
18711 operands[6] = operands[8];
18713 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18716 (define_expand "allocate_stack_worker"
18717 [(match_operand:SI 0 "register_operand" "")]
18718 "TARGET_STACK_PROBE"
18720 if (reload_completed)
18723 emit_insn (gen_allocate_stack_worker_rex64_postreload (operands[0]));
18725 emit_insn (gen_allocate_stack_worker_postreload (operands[0]));
18730 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
18732 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
18737 (define_insn "allocate_stack_worker_1"
18738 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18739 UNSPECV_STACK_PROBE)
18740 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18741 (clobber (match_scratch:SI 1 "=0"))
18742 (clobber (reg:CC FLAGS_REG))]
18743 "!TARGET_64BIT && TARGET_STACK_PROBE"
18745 [(set_attr "type" "multi")
18746 (set_attr "length" "5")])
18748 (define_expand "allocate_stack_worker_postreload"
18749 [(parallel [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18750 UNSPECV_STACK_PROBE)
18751 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18752 (clobber (match_dup 0))
18753 (clobber (reg:CC FLAGS_REG))])]
18757 (define_insn "allocate_stack_worker_rex64"
18758 [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18759 UNSPECV_STACK_PROBE)
18760 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18761 (clobber (match_scratch:DI 1 "=0"))
18762 (clobber (reg:CC FLAGS_REG))]
18763 "TARGET_64BIT && TARGET_STACK_PROBE"
18765 [(set_attr "type" "multi")
18766 (set_attr "length" "5")])
18768 (define_expand "allocate_stack_worker_rex64_postreload"
18769 [(parallel [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18770 UNSPECV_STACK_PROBE)
18771 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18772 (clobber (match_dup 0))
18773 (clobber (reg:CC FLAGS_REG))])]
18777 (define_expand "allocate_stack"
18778 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
18779 (minus:SI (reg:SI SP_REG)
18780 (match_operand:SI 1 "general_operand" "")))
18781 (clobber (reg:CC FLAGS_REG))])
18782 (parallel [(set (reg:SI SP_REG)
18783 (minus:SI (reg:SI SP_REG) (match_dup 1)))
18784 (clobber (reg:CC FLAGS_REG))])]
18785 "TARGET_STACK_PROBE"
18787 #ifdef CHECK_STACK_LIMIT
18788 if (GET_CODE (operands[1]) == CONST_INT
18789 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
18790 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
18794 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
18797 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
18801 (define_expand "builtin_setjmp_receiver"
18802 [(label_ref (match_operand 0 "" ""))]
18803 "!TARGET_64BIT && flag_pic"
18805 emit_insn (gen_set_got (pic_offset_table_rtx));
18809 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
18812 [(set (match_operand 0 "register_operand" "")
18813 (match_operator 3 "promotable_binary_operator"
18814 [(match_operand 1 "register_operand" "")
18815 (match_operand 2 "aligned_operand" "")]))
18816 (clobber (reg:CC FLAGS_REG))]
18817 "! TARGET_PARTIAL_REG_STALL && reload_completed
18818 && ((GET_MODE (operands[0]) == HImode
18819 && ((!optimize_size && !TARGET_FAST_PREFIX)
18820 || GET_CODE (operands[2]) != CONST_INT
18821 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
18822 || (GET_MODE (operands[0]) == QImode
18823 && (TARGET_PROMOTE_QImode || optimize_size)))"
18824 [(parallel [(set (match_dup 0)
18825 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18826 (clobber (reg:CC FLAGS_REG))])]
18827 "operands[0] = gen_lowpart (SImode, operands[0]);
18828 operands[1] = gen_lowpart (SImode, operands[1]);
18829 if (GET_CODE (operands[3]) != ASHIFT)
18830 operands[2] = gen_lowpart (SImode, operands[2]);
18831 PUT_MODE (operands[3], SImode);")
18833 ; Promote the QImode tests, as i386 has encoding of the AND
18834 ; instruction with 32-bit sign-extended immediate and thus the
18835 ; instruction size is unchanged, except in the %eax case for
18836 ; which it is increased by one byte, hence the ! optimize_size.
18839 (compare (and (match_operand 1 "aligned_operand" "")
18840 (match_operand 2 "const_int_operand" ""))
18842 (set (match_operand 0 "register_operand" "")
18843 (and (match_dup 1) (match_dup 2)))]
18844 "! TARGET_PARTIAL_REG_STALL && reload_completed
18845 /* Ensure that the operand will remain sign-extended immediate. */
18846 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
18848 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
18849 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
18850 [(parallel [(set (reg:CCNO FLAGS_REG)
18851 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
18854 (and:SI (match_dup 1) (match_dup 2)))])]
18856 = gen_int_mode (INTVAL (operands[2])
18857 & GET_MODE_MASK (GET_MODE (operands[0])),
18859 operands[0] = gen_lowpart (SImode, operands[0]);
18860 operands[1] = gen_lowpart (SImode, operands[1]);")
18862 ; Don't promote the QImode tests, as i386 doesn't have encoding of
18863 ; the TEST instruction with 32-bit sign-extended immediate and thus
18864 ; the instruction size would at least double, which is not what we
18865 ; want even with ! optimize_size.
18868 (compare (and (match_operand:HI 0 "aligned_operand" "")
18869 (match_operand:HI 1 "const_int_operand" ""))
18871 "! TARGET_PARTIAL_REG_STALL && reload_completed
18872 /* Ensure that the operand will remain sign-extended immediate. */
18873 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
18874 && ! TARGET_FAST_PREFIX
18875 && ! optimize_size"
18876 [(set (reg:CCNO FLAGS_REG)
18877 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
18880 = gen_int_mode (INTVAL (operands[1])
18881 & GET_MODE_MASK (GET_MODE (operands[0])),
18883 operands[0] = gen_lowpart (SImode, operands[0]);")
18886 [(set (match_operand 0 "register_operand" "")
18887 (neg (match_operand 1 "register_operand" "")))
18888 (clobber (reg:CC FLAGS_REG))]
18889 "! TARGET_PARTIAL_REG_STALL && reload_completed
18890 && (GET_MODE (operands[0]) == HImode
18891 || (GET_MODE (operands[0]) == QImode
18892 && (TARGET_PROMOTE_QImode || optimize_size)))"
18893 [(parallel [(set (match_dup 0)
18894 (neg:SI (match_dup 1)))
18895 (clobber (reg:CC FLAGS_REG))])]
18896 "operands[0] = gen_lowpart (SImode, operands[0]);
18897 operands[1] = gen_lowpart (SImode, operands[1]);")
18900 [(set (match_operand 0 "register_operand" "")
18901 (not (match_operand 1 "register_operand" "")))]
18902 "! TARGET_PARTIAL_REG_STALL && reload_completed
18903 && (GET_MODE (operands[0]) == HImode
18904 || (GET_MODE (operands[0]) == QImode
18905 && (TARGET_PROMOTE_QImode || optimize_size)))"
18906 [(set (match_dup 0)
18907 (not:SI (match_dup 1)))]
18908 "operands[0] = gen_lowpart (SImode, operands[0]);
18909 operands[1] = gen_lowpart (SImode, operands[1]);")
18912 [(set (match_operand 0 "register_operand" "")
18913 (if_then_else (match_operator 1 "comparison_operator"
18914 [(reg 17) (const_int 0)])
18915 (match_operand 2 "register_operand" "")
18916 (match_operand 3 "register_operand" "")))]
18917 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
18918 && (GET_MODE (operands[0]) == HImode
18919 || (GET_MODE (operands[0]) == QImode
18920 && (TARGET_PROMOTE_QImode || optimize_size)))"
18921 [(set (match_dup 0)
18922 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
18923 "operands[0] = gen_lowpart (SImode, operands[0]);
18924 operands[2] = gen_lowpart (SImode, operands[2]);
18925 operands[3] = gen_lowpart (SImode, operands[3]);")
18928 ;; RTL Peephole optimizations, run before sched2. These primarily look to
18929 ;; transform a complex memory operation into two memory to register operations.
18931 ;; Don't push memory operands
18933 [(set (match_operand:SI 0 "push_operand" "")
18934 (match_operand:SI 1 "memory_operand" ""))
18935 (match_scratch:SI 2 "r")]
18936 "! optimize_size && ! TARGET_PUSH_MEMORY"
18937 [(set (match_dup 2) (match_dup 1))
18938 (set (match_dup 0) (match_dup 2))]
18942 [(set (match_operand:DI 0 "push_operand" "")
18943 (match_operand:DI 1 "memory_operand" ""))
18944 (match_scratch:DI 2 "r")]
18945 "! optimize_size && ! TARGET_PUSH_MEMORY"
18946 [(set (match_dup 2) (match_dup 1))
18947 (set (match_dup 0) (match_dup 2))]
18950 ;; We need to handle SFmode only, because DFmode and XFmode is split to
18953 [(set (match_operand:SF 0 "push_operand" "")
18954 (match_operand:SF 1 "memory_operand" ""))
18955 (match_scratch:SF 2 "r")]
18956 "! optimize_size && ! TARGET_PUSH_MEMORY"
18957 [(set (match_dup 2) (match_dup 1))
18958 (set (match_dup 0) (match_dup 2))]
18962 [(set (match_operand:HI 0 "push_operand" "")
18963 (match_operand:HI 1 "memory_operand" ""))
18964 (match_scratch:HI 2 "r")]
18965 "! optimize_size && ! TARGET_PUSH_MEMORY"
18966 [(set (match_dup 2) (match_dup 1))
18967 (set (match_dup 0) (match_dup 2))]
18971 [(set (match_operand:QI 0 "push_operand" "")
18972 (match_operand:QI 1 "memory_operand" ""))
18973 (match_scratch:QI 2 "q")]
18974 "! optimize_size && ! TARGET_PUSH_MEMORY"
18975 [(set (match_dup 2) (match_dup 1))
18976 (set (match_dup 0) (match_dup 2))]
18979 ;; Don't move an immediate directly to memory when the instruction
18982 [(match_scratch:SI 1 "r")
18983 (set (match_operand:SI 0 "memory_operand" "")
18986 && ! TARGET_USE_MOV0
18987 && TARGET_SPLIT_LONG_MOVES
18988 && get_attr_length (insn) >= ix86_cost->large_insn
18989 && peep2_regno_dead_p (0, FLAGS_REG)"
18990 [(parallel [(set (match_dup 1) (const_int 0))
18991 (clobber (reg:CC FLAGS_REG))])
18992 (set (match_dup 0) (match_dup 1))]
18996 [(match_scratch:HI 1 "r")
18997 (set (match_operand:HI 0 "memory_operand" "")
19000 && ! TARGET_USE_MOV0
19001 && TARGET_SPLIT_LONG_MOVES
19002 && get_attr_length (insn) >= ix86_cost->large_insn
19003 && peep2_regno_dead_p (0, FLAGS_REG)"
19004 [(parallel [(set (match_dup 2) (const_int 0))
19005 (clobber (reg:CC FLAGS_REG))])
19006 (set (match_dup 0) (match_dup 1))]
19007 "operands[2] = gen_lowpart (SImode, operands[1]);")
19010 [(match_scratch:QI 1 "q")
19011 (set (match_operand:QI 0 "memory_operand" "")
19014 && ! TARGET_USE_MOV0
19015 && TARGET_SPLIT_LONG_MOVES
19016 && get_attr_length (insn) >= ix86_cost->large_insn
19017 && peep2_regno_dead_p (0, FLAGS_REG)"
19018 [(parallel [(set (match_dup 2) (const_int 0))
19019 (clobber (reg:CC FLAGS_REG))])
19020 (set (match_dup 0) (match_dup 1))]
19021 "operands[2] = gen_lowpart (SImode, operands[1]);")
19024 [(match_scratch:SI 2 "r")
19025 (set (match_operand:SI 0 "memory_operand" "")
19026 (match_operand:SI 1 "immediate_operand" ""))]
19028 && get_attr_length (insn) >= ix86_cost->large_insn
19029 && TARGET_SPLIT_LONG_MOVES"
19030 [(set (match_dup 2) (match_dup 1))
19031 (set (match_dup 0) (match_dup 2))]
19035 [(match_scratch:HI 2 "r")
19036 (set (match_operand:HI 0 "memory_operand" "")
19037 (match_operand:HI 1 "immediate_operand" ""))]
19038 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
19039 && TARGET_SPLIT_LONG_MOVES"
19040 [(set (match_dup 2) (match_dup 1))
19041 (set (match_dup 0) (match_dup 2))]
19045 [(match_scratch:QI 2 "q")
19046 (set (match_operand:QI 0 "memory_operand" "")
19047 (match_operand:QI 1 "immediate_operand" ""))]
19048 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
19049 && TARGET_SPLIT_LONG_MOVES"
19050 [(set (match_dup 2) (match_dup 1))
19051 (set (match_dup 0) (match_dup 2))]
19054 ;; Don't compare memory with zero, load and use a test instead.
19057 (compare (match_operand:SI 0 "memory_operand" "")
19059 (match_scratch:SI 3 "r")]
19060 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
19061 [(set (match_dup 3) (match_dup 0))
19062 (set (reg:CCNO FLAGS_REG) (compare:CCNO (match_dup 3) (const_int 0)))]
19065 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
19066 ;; Don't split NOTs with a displacement operand, because resulting XOR
19067 ;; will not be pairable anyway.
19069 ;; On AMD K6, NOT is vector decoded with memory operand that cannot be
19070 ;; represented using a modRM byte. The XOR replacement is long decoded,
19071 ;; so this split helps here as well.
19073 ;; Note: Can't do this as a regular split because we can't get proper
19074 ;; lifetime information then.
19077 [(set (match_operand:SI 0 "nonimmediate_operand" "")
19078 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
19080 && peep2_regno_dead_p (0, FLAGS_REG)
19081 && ((TARGET_PENTIUM
19082 && (GET_CODE (operands[0]) != MEM
19083 || !memory_displacement_operand (operands[0], SImode)))
19084 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
19085 [(parallel [(set (match_dup 0)
19086 (xor:SI (match_dup 1) (const_int -1)))
19087 (clobber (reg:CC FLAGS_REG))])]
19091 [(set (match_operand:HI 0 "nonimmediate_operand" "")
19092 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
19094 && peep2_regno_dead_p (0, FLAGS_REG)
19095 && ((TARGET_PENTIUM
19096 && (GET_CODE (operands[0]) != MEM
19097 || !memory_displacement_operand (operands[0], HImode)))
19098 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
19099 [(parallel [(set (match_dup 0)
19100 (xor:HI (match_dup 1) (const_int -1)))
19101 (clobber (reg:CC FLAGS_REG))])]
19105 [(set (match_operand:QI 0 "nonimmediate_operand" "")
19106 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
19108 && peep2_regno_dead_p (0, FLAGS_REG)
19109 && ((TARGET_PENTIUM
19110 && (GET_CODE (operands[0]) != MEM
19111 || !memory_displacement_operand (operands[0], QImode)))
19112 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
19113 [(parallel [(set (match_dup 0)
19114 (xor:QI (match_dup 1) (const_int -1)))
19115 (clobber (reg:CC FLAGS_REG))])]
19118 ;; Non pairable "test imm, reg" instructions can be translated to
19119 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
19120 ;; byte opcode instead of two, have a short form for byte operands),
19121 ;; so do it for other CPUs as well. Given that the value was dead,
19122 ;; this should not create any new dependencies. Pass on the sub-word
19123 ;; versions if we're concerned about partial register stalls.
19127 (compare (and:SI (match_operand:SI 0 "register_operand" "")
19128 (match_operand:SI 1 "immediate_operand" ""))
19130 "ix86_match_ccmode (insn, CCNOmode)
19131 && (true_regnum (operands[0]) != 0
19132 || (GET_CODE (operands[1]) == CONST_INT
19133 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
19134 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19136 [(set (reg:CCNO FLAGS_REG)
19137 (compare:CCNO (and:SI (match_dup 0)
19141 (and:SI (match_dup 0) (match_dup 1)))])]
19144 ;; We don't need to handle HImode case, because it will be promoted to SImode
19145 ;; on ! TARGET_PARTIAL_REG_STALL
19149 (compare (and:QI (match_operand:QI 0 "register_operand" "")
19150 (match_operand:QI 1 "immediate_operand" ""))
19152 "! TARGET_PARTIAL_REG_STALL
19153 && ix86_match_ccmode (insn, CCNOmode)
19154 && true_regnum (operands[0]) != 0
19155 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19157 [(set (reg:CCNO FLAGS_REG)
19158 (compare:CCNO (and:QI (match_dup 0)
19162 (and:QI (match_dup 0) (match_dup 1)))])]
19170 (match_operand 0 "ext_register_operand" "")
19173 (match_operand 1 "const_int_operand" ""))
19175 "! TARGET_PARTIAL_REG_STALL
19176 && ix86_match_ccmode (insn, CCNOmode)
19177 && true_regnum (operands[0]) != 0
19178 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19179 [(parallel [(set (reg:CCNO FLAGS_REG)
19188 (set (zero_extract:SI (match_dup 0)
19199 ;; Don't do logical operations with memory inputs.
19201 [(match_scratch:SI 2 "r")
19202 (parallel [(set (match_operand:SI 0 "register_operand" "")
19203 (match_operator:SI 3 "arith_or_logical_operator"
19205 (match_operand:SI 1 "memory_operand" "")]))
19206 (clobber (reg:CC FLAGS_REG))])]
19207 "! optimize_size && ! TARGET_READ_MODIFY"
19208 [(set (match_dup 2) (match_dup 1))
19209 (parallel [(set (match_dup 0)
19210 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
19211 (clobber (reg:CC FLAGS_REG))])]
19215 [(match_scratch:SI 2 "r")
19216 (parallel [(set (match_operand:SI 0 "register_operand" "")
19217 (match_operator:SI 3 "arith_or_logical_operator"
19218 [(match_operand:SI 1 "memory_operand" "")
19220 (clobber (reg:CC FLAGS_REG))])]
19221 "! optimize_size && ! TARGET_READ_MODIFY"
19222 [(set (match_dup 2) (match_dup 1))
19223 (parallel [(set (match_dup 0)
19224 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
19225 (clobber (reg:CC FLAGS_REG))])]
19228 ; Don't do logical operations with memory outputs
19230 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
19231 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
19232 ; the same decoder scheduling characteristics as the original.
19235 [(match_scratch:SI 2 "r")
19236 (parallel [(set (match_operand:SI 0 "memory_operand" "")
19237 (match_operator:SI 3 "arith_or_logical_operator"
19239 (match_operand:SI 1 "nonmemory_operand" "")]))
19240 (clobber (reg:CC FLAGS_REG))])]
19241 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
19242 [(set (match_dup 2) (match_dup 0))
19243 (parallel [(set (match_dup 2)
19244 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
19245 (clobber (reg:CC FLAGS_REG))])
19246 (set (match_dup 0) (match_dup 2))]
19250 [(match_scratch:SI 2 "r")
19251 (parallel [(set (match_operand:SI 0 "memory_operand" "")
19252 (match_operator:SI 3 "arith_or_logical_operator"
19253 [(match_operand:SI 1 "nonmemory_operand" "")
19255 (clobber (reg:CC FLAGS_REG))])]
19256 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
19257 [(set (match_dup 2) (match_dup 0))
19258 (parallel [(set (match_dup 2)
19259 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
19260 (clobber (reg:CC FLAGS_REG))])
19261 (set (match_dup 0) (match_dup 2))]
19264 ;; Attempt to always use XOR for zeroing registers.
19266 [(set (match_operand 0 "register_operand" "")
19268 "(GET_MODE (operands[0]) == QImode
19269 || GET_MODE (operands[0]) == HImode
19270 || GET_MODE (operands[0]) == SImode
19271 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19272 && (! TARGET_USE_MOV0 || optimize_size)
19273 && peep2_regno_dead_p (0, FLAGS_REG)"
19274 [(parallel [(set (match_dup 0) (const_int 0))
19275 (clobber (reg:CC FLAGS_REG))])]
19276 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19280 [(set (strict_low_part (match_operand 0 "register_operand" ""))
19282 "(GET_MODE (operands[0]) == QImode
19283 || GET_MODE (operands[0]) == HImode)
19284 && (! TARGET_USE_MOV0 || optimize_size)
19285 && peep2_regno_dead_p (0, FLAGS_REG)"
19286 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
19287 (clobber (reg:CC FLAGS_REG))])])
19289 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
19291 [(set (match_operand 0 "register_operand" "")
19293 "(GET_MODE (operands[0]) == HImode
19294 || GET_MODE (operands[0]) == SImode
19295 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19296 && (optimize_size || TARGET_PENTIUM)
19297 && peep2_regno_dead_p (0, FLAGS_REG)"
19298 [(parallel [(set (match_dup 0) (const_int -1))
19299 (clobber (reg:CC FLAGS_REG))])]
19300 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19303 ;; Attempt to convert simple leas to adds. These can be created by
19306 [(set (match_operand:SI 0 "register_operand" "")
19307 (plus:SI (match_dup 0)
19308 (match_operand:SI 1 "nonmemory_operand" "")))]
19309 "peep2_regno_dead_p (0, FLAGS_REG)"
19310 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
19311 (clobber (reg:CC FLAGS_REG))])]
19315 [(set (match_operand:SI 0 "register_operand" "")
19316 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
19317 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
19318 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
19319 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
19320 (clobber (reg:CC FLAGS_REG))])]
19321 "operands[2] = gen_lowpart (SImode, operands[2]);")
19324 [(set (match_operand:DI 0 "register_operand" "")
19325 (plus:DI (match_dup 0)
19326 (match_operand:DI 1 "x86_64_general_operand" "")))]
19327 "peep2_regno_dead_p (0, FLAGS_REG)"
19328 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
19329 (clobber (reg:CC FLAGS_REG))])]
19333 [(set (match_operand:SI 0 "register_operand" "")
19334 (mult:SI (match_dup 0)
19335 (match_operand:SI 1 "const_int_operand" "")))]
19336 "exact_log2 (INTVAL (operands[1])) >= 0
19337 && peep2_regno_dead_p (0, FLAGS_REG)"
19338 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19339 (clobber (reg:CC FLAGS_REG))])]
19340 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19343 [(set (match_operand:DI 0 "register_operand" "")
19344 (mult:DI (match_dup 0)
19345 (match_operand:DI 1 "const_int_operand" "")))]
19346 "exact_log2 (INTVAL (operands[1])) >= 0
19347 && peep2_regno_dead_p (0, FLAGS_REG)"
19348 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
19349 (clobber (reg:CC FLAGS_REG))])]
19350 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19353 [(set (match_operand:SI 0 "register_operand" "")
19354 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
19355 (match_operand:DI 2 "const_int_operand" "")) 0))]
19356 "exact_log2 (INTVAL (operands[2])) >= 0
19357 && REGNO (operands[0]) == REGNO (operands[1])
19358 && peep2_regno_dead_p (0, FLAGS_REG)"
19359 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19360 (clobber (reg:CC FLAGS_REG))])]
19361 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
19363 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
19364 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
19365 ;; many CPUs it is also faster, since special hardware to avoid esp
19366 ;; dependencies is present.
19368 ;; While some of these conversions may be done using splitters, we use peepholes
19369 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
19371 ;; Convert prologue esp subtractions to push.
19372 ;; We need register to push. In order to keep verify_flow_info happy we have
19374 ;; - use scratch and clobber it in order to avoid dependencies
19375 ;; - use already live register
19376 ;; We can't use the second way right now, since there is no reliable way how to
19377 ;; verify that given register is live. First choice will also most likely in
19378 ;; fewer dependencies. On the place of esp adjustments it is very likely that
19379 ;; call clobbered registers are dead. We may want to use base pointer as an
19380 ;; alternative when no register is available later.
19383 [(match_scratch:SI 0 "r")
19384 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19385 (clobber (reg:CC FLAGS_REG))
19386 (clobber (mem:BLK (scratch)))])]
19387 "optimize_size || !TARGET_SUB_ESP_4"
19388 [(clobber (match_dup 0))
19389 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19390 (clobber (mem:BLK (scratch)))])])
19393 [(match_scratch:SI 0 "r")
19394 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19395 (clobber (reg:CC FLAGS_REG))
19396 (clobber (mem:BLK (scratch)))])]
19397 "optimize_size || !TARGET_SUB_ESP_8"
19398 [(clobber (match_dup 0))
19399 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19400 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19401 (clobber (mem:BLK (scratch)))])])
19403 ;; Convert esp subtractions to push.
19405 [(match_scratch:SI 0 "r")
19406 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19407 (clobber (reg:CC FLAGS_REG))])]
19408 "optimize_size || !TARGET_SUB_ESP_4"
19409 [(clobber (match_dup 0))
19410 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19413 [(match_scratch:SI 0 "r")
19414 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19415 (clobber (reg:CC FLAGS_REG))])]
19416 "optimize_size || !TARGET_SUB_ESP_8"
19417 [(clobber (match_dup 0))
19418 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19419 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19421 ;; Convert epilogue deallocator to pop.
19423 [(match_scratch:SI 0 "r")
19424 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19425 (clobber (reg:CC FLAGS_REG))
19426 (clobber (mem:BLK (scratch)))])]
19427 "optimize_size || !TARGET_ADD_ESP_4"
19428 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19429 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19430 (clobber (mem:BLK (scratch)))])]
19433 ;; Two pops case is tricky, since pop causes dependency on destination register.
19434 ;; We use two registers if available.
19436 [(match_scratch:SI 0 "r")
19437 (match_scratch:SI 1 "r")
19438 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19439 (clobber (reg:CC FLAGS_REG))
19440 (clobber (mem:BLK (scratch)))])]
19441 "optimize_size || !TARGET_ADD_ESP_8"
19442 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19443 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19444 (clobber (mem:BLK (scratch)))])
19445 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19446 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19450 [(match_scratch:SI 0 "r")
19451 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19452 (clobber (reg:CC FLAGS_REG))
19453 (clobber (mem:BLK (scratch)))])]
19455 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19456 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19457 (clobber (mem:BLK (scratch)))])
19458 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19459 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19462 ;; Convert esp additions to pop.
19464 [(match_scratch:SI 0 "r")
19465 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19466 (clobber (reg:CC FLAGS_REG))])]
19468 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19469 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19472 ;; Two pops case is tricky, since pop causes dependency on destination register.
19473 ;; We use two registers if available.
19475 [(match_scratch:SI 0 "r")
19476 (match_scratch:SI 1 "r")
19477 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19478 (clobber (reg:CC FLAGS_REG))])]
19480 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19481 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19482 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19483 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19487 [(match_scratch:SI 0 "r")
19488 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19489 (clobber (reg:CC FLAGS_REG))])]
19491 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19492 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19493 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19494 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19497 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
19498 ;; required and register dies.
19501 (compare (match_operand:SI 0 "register_operand" "")
19502 (match_operand:SI 1 "incdec_operand" "")))]
19503 "ix86_match_ccmode (insn, CCGCmode)
19504 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19505 [(parallel [(set (reg:CCGC FLAGS_REG)
19506 (compare:CCGC (match_dup 0)
19508 (clobber (match_dup 0))])]
19513 (compare (match_operand:HI 0 "register_operand" "")
19514 (match_operand:HI 1 "incdec_operand" "")))]
19515 "ix86_match_ccmode (insn, CCGCmode)
19516 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19517 [(parallel [(set (reg:CCGC FLAGS_REG)
19518 (compare:CCGC (match_dup 0)
19520 (clobber (match_dup 0))])]
19525 (compare (match_operand:QI 0 "register_operand" "")
19526 (match_operand:QI 1 "incdec_operand" "")))]
19527 "ix86_match_ccmode (insn, CCGCmode)
19528 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19529 [(parallel [(set (reg:CCGC FLAGS_REG)
19530 (compare:CCGC (match_dup 0)
19532 (clobber (match_dup 0))])]
19535 ;; Convert compares with 128 to shorter add -128
19538 (compare (match_operand:SI 0 "register_operand" "")
19540 "ix86_match_ccmode (insn, CCGCmode)
19541 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19542 [(parallel [(set (reg:CCGC FLAGS_REG)
19543 (compare:CCGC (match_dup 0)
19545 (clobber (match_dup 0))])]
19550 (compare (match_operand:HI 0 "register_operand" "")
19552 "ix86_match_ccmode (insn, CCGCmode)
19553 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
19554 [(parallel [(set (reg:CCGC FLAGS_REG)
19555 (compare:CCGC (match_dup 0)
19557 (clobber (match_dup 0))])]
19561 [(match_scratch:DI 0 "r")
19562 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19563 (clobber (reg:CC FLAGS_REG))
19564 (clobber (mem:BLK (scratch)))])]
19565 "optimize_size || !TARGET_SUB_ESP_4"
19566 [(clobber (match_dup 0))
19567 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19568 (clobber (mem:BLK (scratch)))])])
19571 [(match_scratch:DI 0 "r")
19572 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19573 (clobber (reg:CC FLAGS_REG))
19574 (clobber (mem:BLK (scratch)))])]
19575 "optimize_size || !TARGET_SUB_ESP_8"
19576 [(clobber (match_dup 0))
19577 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19578 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19579 (clobber (mem:BLK (scratch)))])])
19581 ;; Convert esp subtractions to push.
19583 [(match_scratch:DI 0 "r")
19584 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19585 (clobber (reg:CC FLAGS_REG))])]
19586 "optimize_size || !TARGET_SUB_ESP_4"
19587 [(clobber (match_dup 0))
19588 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19591 [(match_scratch:DI 0 "r")
19592 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19593 (clobber (reg:CC FLAGS_REG))])]
19594 "optimize_size || !TARGET_SUB_ESP_8"
19595 [(clobber (match_dup 0))
19596 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19597 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19599 ;; Convert epilogue deallocator to pop.
19601 [(match_scratch:DI 0 "r")
19602 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19603 (clobber (reg:CC FLAGS_REG))
19604 (clobber (mem:BLK (scratch)))])]
19605 "optimize_size || !TARGET_ADD_ESP_4"
19606 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19607 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19608 (clobber (mem:BLK (scratch)))])]
19611 ;; Two pops case is tricky, since pop causes dependency on destination register.
19612 ;; We use two registers if available.
19614 [(match_scratch:DI 0 "r")
19615 (match_scratch:DI 1 "r")
19616 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19617 (clobber (reg:CC FLAGS_REG))
19618 (clobber (mem:BLK (scratch)))])]
19619 "optimize_size || !TARGET_ADD_ESP_8"
19620 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19621 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19622 (clobber (mem:BLK (scratch)))])
19623 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19624 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19628 [(match_scratch:DI 0 "r")
19629 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19630 (clobber (reg:CC FLAGS_REG))
19631 (clobber (mem:BLK (scratch)))])]
19633 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19634 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19635 (clobber (mem:BLK (scratch)))])
19636 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19637 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19640 ;; Convert esp additions to pop.
19642 [(match_scratch:DI 0 "r")
19643 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19644 (clobber (reg:CC FLAGS_REG))])]
19646 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19647 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19650 ;; Two pops case is tricky, since pop causes dependency on destination register.
19651 ;; We use two registers if available.
19653 [(match_scratch:DI 0 "r")
19654 (match_scratch:DI 1 "r")
19655 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19656 (clobber (reg:CC FLAGS_REG))])]
19658 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19659 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19660 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19661 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19665 [(match_scratch:DI 0 "r")
19666 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19667 (clobber (reg:CC FLAGS_REG))])]
19669 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19670 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19671 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19672 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19675 ;; Convert imul by three, five and nine into lea
19678 [(set (match_operand:SI 0 "register_operand" "")
19679 (mult:SI (match_operand:SI 1 "register_operand" "")
19680 (match_operand:SI 2 "const_int_operand" "")))
19681 (clobber (reg:CC FLAGS_REG))])]
19682 "INTVAL (operands[2]) == 3
19683 || INTVAL (operands[2]) == 5
19684 || INTVAL (operands[2]) == 9"
19685 [(set (match_dup 0)
19686 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
19688 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19692 [(set (match_operand:SI 0 "register_operand" "")
19693 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19694 (match_operand:SI 2 "const_int_operand" "")))
19695 (clobber (reg:CC FLAGS_REG))])]
19697 && (INTVAL (operands[2]) == 3
19698 || INTVAL (operands[2]) == 5
19699 || INTVAL (operands[2]) == 9)"
19700 [(set (match_dup 0) (match_dup 1))
19702 (plus:SI (mult:SI (match_dup 0) (match_dup 2))
19704 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19708 [(set (match_operand:DI 0 "register_operand" "")
19709 (mult:DI (match_operand:DI 1 "register_operand" "")
19710 (match_operand:DI 2 "const_int_operand" "")))
19711 (clobber (reg:CC FLAGS_REG))])]
19713 && (INTVAL (operands[2]) == 3
19714 || INTVAL (operands[2]) == 5
19715 || INTVAL (operands[2]) == 9)"
19716 [(set (match_dup 0)
19717 (plus:DI (mult:DI (match_dup 1) (match_dup 2))
19719 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19723 [(set (match_operand:DI 0 "register_operand" "")
19724 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19725 (match_operand:DI 2 "const_int_operand" "")))
19726 (clobber (reg:CC FLAGS_REG))])]
19729 && (INTVAL (operands[2]) == 3
19730 || INTVAL (operands[2]) == 5
19731 || INTVAL (operands[2]) == 9)"
19732 [(set (match_dup 0) (match_dup 1))
19734 (plus:DI (mult:DI (match_dup 0) (match_dup 2))
19736 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19738 ;; Imul $32bit_imm, mem, reg is vector decoded, while
19739 ;; imul $32bit_imm, reg, reg is direct decoded.
19741 [(match_scratch:DI 3 "r")
19742 (parallel [(set (match_operand:DI 0 "register_operand" "")
19743 (mult:DI (match_operand:DI 1 "memory_operand" "")
19744 (match_operand:DI 2 "immediate_operand" "")))
19745 (clobber (reg:CC FLAGS_REG))])]
19746 "TARGET_K8 && !optimize_size
19747 && (GET_CODE (operands[2]) != CONST_INT
19748 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19749 [(set (match_dup 3) (match_dup 1))
19750 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
19751 (clobber (reg:CC FLAGS_REG))])]
19755 [(match_scratch:SI 3 "r")
19756 (parallel [(set (match_operand:SI 0 "register_operand" "")
19757 (mult:SI (match_operand:SI 1 "memory_operand" "")
19758 (match_operand:SI 2 "immediate_operand" "")))
19759 (clobber (reg:CC FLAGS_REG))])]
19760 "TARGET_K8 && !optimize_size
19761 && (GET_CODE (operands[2]) != CONST_INT
19762 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19763 [(set (match_dup 3) (match_dup 1))
19764 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
19765 (clobber (reg:CC FLAGS_REG))])]
19769 [(match_scratch:SI 3 "r")
19770 (parallel [(set (match_operand:DI 0 "register_operand" "")
19772 (mult:SI (match_operand:SI 1 "memory_operand" "")
19773 (match_operand:SI 2 "immediate_operand" ""))))
19774 (clobber (reg:CC FLAGS_REG))])]
19775 "TARGET_K8 && !optimize_size
19776 && (GET_CODE (operands[2]) != CONST_INT
19777 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19778 [(set (match_dup 3) (match_dup 1))
19779 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
19780 (clobber (reg:CC FLAGS_REG))])]
19783 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
19784 ;; Convert it into imul reg, reg
19785 ;; It would be better to force assembler to encode instruction using long
19786 ;; immediate, but there is apparently no way to do so.
19788 [(parallel [(set (match_operand:DI 0 "register_operand" "")
19789 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19790 (match_operand:DI 2 "const_int_operand" "")))
19791 (clobber (reg:CC FLAGS_REG))])
19792 (match_scratch:DI 3 "r")]
19793 "TARGET_K8 && !optimize_size
19794 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19795 [(set (match_dup 3) (match_dup 2))
19796 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
19797 (clobber (reg:CC FLAGS_REG))])]
19799 if (!rtx_equal_p (operands[0], operands[1]))
19800 emit_move_insn (operands[0], operands[1]);
19804 [(parallel [(set (match_operand:SI 0 "register_operand" "")
19805 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19806 (match_operand:SI 2 "const_int_operand" "")))
19807 (clobber (reg:CC FLAGS_REG))])
19808 (match_scratch:SI 3 "r")]
19809 "TARGET_K8 && !optimize_size
19810 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19811 [(set (match_dup 3) (match_dup 2))
19812 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
19813 (clobber (reg:CC FLAGS_REG))])]
19815 if (!rtx_equal_p (operands[0], operands[1]))
19816 emit_move_insn (operands[0], operands[1]);
19820 [(parallel [(set (match_operand:HI 0 "register_operand" "")
19821 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
19822 (match_operand:HI 2 "immediate_operand" "")))
19823 (clobber (reg:CC FLAGS_REG))])
19824 (match_scratch:HI 3 "r")]
19825 "TARGET_K8 && !optimize_size"
19826 [(set (match_dup 3) (match_dup 2))
19827 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
19828 (clobber (reg:CC FLAGS_REG))])]
19830 if (!rtx_equal_p (operands[0], operands[1]))
19831 emit_move_insn (operands[0], operands[1]);
19834 ;; Call-value patterns last so that the wildcard operand does not
19835 ;; disrupt insn-recog's switch tables.
19837 (define_insn "*call_value_pop_0"
19838 [(set (match_operand 0 "" "")
19839 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19840 (match_operand:SI 2 "" "")))
19841 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19842 (match_operand:SI 3 "immediate_operand" "")))]
19845 if (SIBLING_CALL_P (insn))
19848 return "call\t%P1";
19850 [(set_attr "type" "callv")])
19852 (define_insn "*call_value_pop_1"
19853 [(set (match_operand 0 "" "")
19854 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19855 (match_operand:SI 2 "" "")))
19856 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19857 (match_operand:SI 3 "immediate_operand" "i")))]
19860 if (constant_call_address_operand (operands[1], Pmode))
19862 if (SIBLING_CALL_P (insn))
19865 return "call\t%P1";
19867 if (SIBLING_CALL_P (insn))
19870 return "call\t%A1";
19872 [(set_attr "type" "callv")])
19874 (define_insn "*call_value_0"
19875 [(set (match_operand 0 "" "")
19876 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19877 (match_operand:SI 2 "" "")))]
19880 if (SIBLING_CALL_P (insn))
19883 return "call\t%P1";
19885 [(set_attr "type" "callv")])
19887 (define_insn "*call_value_0_rex64"
19888 [(set (match_operand 0 "" "")
19889 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19890 (match_operand:DI 2 "const_int_operand" "")))]
19893 if (SIBLING_CALL_P (insn))
19896 return "call\t%P1";
19898 [(set_attr "type" "callv")])
19900 (define_insn "*call_value_1"
19901 [(set (match_operand 0 "" "")
19902 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19903 (match_operand:SI 2 "" "")))]
19904 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
19906 if (constant_call_address_operand (operands[1], Pmode))
19907 return "call\t%P1";
19908 return "call\t%*%1";
19910 [(set_attr "type" "callv")])
19912 (define_insn "*sibcall_value_1"
19913 [(set (match_operand 0 "" "")
19914 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
19915 (match_operand:SI 2 "" "")))]
19916 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
19918 if (constant_call_address_operand (operands[1], Pmode))
19920 return "jmp\t%*%1";
19922 [(set_attr "type" "callv")])
19924 (define_insn "*call_value_1_rex64"
19925 [(set (match_operand 0 "" "")
19926 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
19927 (match_operand:DI 2 "" "")))]
19928 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
19930 if (constant_call_address_operand (operands[1], Pmode))
19931 return "call\t%P1";
19932 return "call\t%A1";
19934 [(set_attr "type" "callv")])
19936 (define_insn "*sibcall_value_1_rex64"
19937 [(set (match_operand 0 "" "")
19938 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19939 (match_operand:DI 2 "" "")))]
19940 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19942 [(set_attr "type" "callv")])
19944 (define_insn "*sibcall_value_1_rex64_v"
19945 [(set (match_operand 0 "" "")
19946 (call (mem:QI (reg:DI 40))
19947 (match_operand:DI 1 "" "")))]
19948 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19950 [(set_attr "type" "callv")])
19952 (define_insn "trap"
19953 [(trap_if (const_int 1) (const_int 5))]
19957 ;;; ix86 doesn't have conditional trap instructions, but we fake them
19958 ;;; for the sake of bounds checking. By emitting bounds checks as
19959 ;;; conditional traps rather than as conditional jumps around
19960 ;;; unconditional traps we avoid introducing spurious basic-block
19961 ;;; boundaries and facilitate elimination of redundant checks. In
19962 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
19965 ;;; FIXME: Static branch prediction rules for ix86 are such that
19966 ;;; forward conditional branches predict as untaken. As implemented
19967 ;;; below, pseudo conditional traps violate that rule. We should use
19968 ;;; .pushsection/.popsection to place all of the `int 5's in a special
19969 ;;; section loaded at the end of the text segment and branch forward
19970 ;;; there on bounds-failure, and then jump back immediately (in case
19971 ;;; the system chooses to ignore bounds violations, or to report
19972 ;;; violations and continue execution).
19974 (define_expand "conditional_trap"
19975 [(trap_if (match_operator 0 "comparison_operator"
19976 [(match_dup 2) (const_int 0)])
19977 (match_operand 1 "const_int_operand" ""))]
19980 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
19981 ix86_expand_compare (GET_CODE (operands[0]),
19987 (define_insn "*conditional_trap_1"
19988 [(trap_if (match_operator 0 "comparison_operator"
19989 [(reg 17) (const_int 0)])
19990 (match_operand 1 "const_int_operand" ""))]
19993 operands[2] = gen_label_rtx ();
19994 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
19995 (*targetm.asm_out.internal_label) (asm_out_file, "L",
19996 CODE_LABEL_NUMBER (operands[2]));
20000 ;; Pentium III SIMD instructions.
20002 ;; Moves for SSE/MMX regs.
20004 (define_insn "movv4sf_internal"
20005 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
20006 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
20010 movaps\t{%1, %0|%0, %1}
20011 movaps\t{%1, %0|%0, %1}"
20012 [(set_attr "type" "ssemov")
20013 (set_attr "mode" "V4SF")])
20016 [(set (match_operand:V4SF 0 "register_operand" "")
20017 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
20019 [(set (match_dup 0)
20021 (vec_duplicate:V4SF (match_dup 1))
20025 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
20026 operands[2] = CONST0_RTX (V4SFmode);
20029 (define_insn "movv4si_internal"
20030 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
20031 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
20034 switch (which_alternative)
20037 if (get_attr_mode (insn) == MODE_V4SF)
20038 return "xorps\t%0, %0";
20040 return "pxor\t%0, %0";
20043 if (get_attr_mode (insn) == MODE_V4SF)
20044 return "movaps\t{%1, %0|%0, %1}";
20046 return "movdqa\t{%1, %0|%0, %1}";
20051 [(set_attr "type" "ssemov")
20053 (cond [(eq_attr "alternative" "0,1")
20055 (ne (symbol_ref "optimize_size")
20057 (const_string "V4SF")
20058 (const_string "TI"))
20059 (eq_attr "alternative" "2")
20061 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20063 (ne (symbol_ref "optimize_size")
20065 (const_string "V4SF")
20066 (const_string "TI"))]
20067 (const_string "TI")))])
20069 (define_insn "movv2di_internal"
20070 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
20071 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
20074 switch (which_alternative)
20077 if (get_attr_mode (insn) == MODE_V4SF)
20078 return "xorps\t%0, %0";
20080 return "pxor\t%0, %0";
20083 if (get_attr_mode (insn) == MODE_V4SF)
20084 return "movaps\t{%1, %0|%0, %1}";
20086 return "movdqa\t{%1, %0|%0, %1}";
20091 [(set_attr "type" "ssemov")
20093 (cond [(eq_attr "alternative" "0,1")
20095 (ne (symbol_ref "optimize_size")
20097 (const_string "V4SF")
20098 (const_string "TI"))
20099 (eq_attr "alternative" "2")
20101 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20103 (ne (symbol_ref "optimize_size")
20105 (const_string "V4SF")
20106 (const_string "TI"))]
20107 (const_string "TI")))])
20110 [(set (match_operand:V2DF 0 "register_operand" "")
20111 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
20113 [(set (match_dup 0)
20115 (vec_duplicate:V2DF (match_dup 1))
20119 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
20120 operands[2] = CONST0_RTX (V2DFmode);
20123 (define_insn "movv8qi_internal"
20124 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
20125 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
20127 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20130 movq\t{%1, %0|%0, %1}
20131 movq\t{%1, %0|%0, %1}
20132 movdq2q\t{%1, %0|%0, %1}
20133 movq2dq\t{%1, %0|%0, %1}
20134 movq\t{%1, %0|%0, %1}
20135 movq\t{%1, %0|%0, %1}"
20136 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
20137 (set_attr "mode" "DI")])
20139 (define_insn "movv4hi_internal"
20140 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
20141 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
20143 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20146 movq\t{%1, %0|%0, %1}
20147 movq\t{%1, %0|%0, %1}
20148 movdq2q\t{%1, %0|%0, %1}
20149 movq2dq\t{%1, %0|%0, %1}
20150 movq\t{%1, %0|%0, %1}
20151 movq\t{%1, %0|%0, %1}"
20152 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
20153 (set_attr "mode" "DI")])
20155 (define_insn "*movv2si_internal"
20156 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
20157 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
20159 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20162 movq\t{%1, %0|%0, %1}
20163 movq\t{%1, %0|%0, %1}
20164 movdq2q\t{%1, %0|%0, %1}
20165 movq2dq\t{%1, %0|%0, %1}
20166 movq\t{%1, %0|%0, %1}
20167 movq\t{%1, %0|%0, %1}"
20168 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
20169 (set_attr "mode" "DI")])
20171 (define_insn "movv2sf_internal"
20172 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*x,?m")
20173 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y,*Y,y,*xm,*x"))]
20175 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20178 movq\t{%1, %0|%0, %1}
20179 movq\t{%1, %0|%0, %1}
20180 movdq2q\t{%1, %0|%0, %1}
20181 movq2dq\t{%1, %0|%0, %1}
20182 movlps\t{%1, %0|%0, %1}
20183 movlps\t{%1, %0|%0, %1}"
20184 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
20185 (set_attr "mode" "DI,DI,DI,DI,DI,V2SF,V2SF")])
20187 (define_expand "movti"
20188 [(set (match_operand:TI 0 "nonimmediate_operand" "")
20189 (match_operand:TI 1 "nonimmediate_operand" ""))]
20190 "TARGET_SSE || TARGET_64BIT"
20193 ix86_expand_move (TImode, operands);
20195 ix86_expand_vector_move (TImode, operands);
20199 (define_expand "movtf"
20200 [(set (match_operand:TF 0 "nonimmediate_operand" "")
20201 (match_operand:TF 1 "nonimmediate_operand" ""))]
20205 ix86_expand_move (TFmode, operands);
20207 ix86_expand_vector_move (TFmode, operands);
20211 (define_insn "movv2df_internal"
20212 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
20213 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
20215 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20217 switch (which_alternative)
20220 if (get_attr_mode (insn) == MODE_V4SF)
20221 return "xorps\t%0, %0";
20223 return "xorpd\t%0, %0";
20226 if (get_attr_mode (insn) == MODE_V4SF)
20227 return "movaps\t{%1, %0|%0, %1}";
20229 return "movapd\t{%1, %0|%0, %1}";
20234 [(set_attr "type" "ssemov")
20236 (cond [(eq_attr "alternative" "0,1")
20238 (ne (symbol_ref "optimize_size")
20240 (const_string "V4SF")
20241 (const_string "V2DF"))
20242 (eq_attr "alternative" "2")
20244 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20246 (ne (symbol_ref "optimize_size")
20248 (const_string "V4SF")
20249 (const_string "V2DF"))]
20250 (const_string "V2DF")))])
20252 (define_insn "movv8hi_internal"
20253 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
20254 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
20256 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20258 switch (which_alternative)
20261 if (get_attr_mode (insn) == MODE_V4SF)
20262 return "xorps\t%0, %0";
20264 return "pxor\t%0, %0";
20267 if (get_attr_mode (insn) == MODE_V4SF)
20268 return "movaps\t{%1, %0|%0, %1}";
20270 return "movdqa\t{%1, %0|%0, %1}";
20275 [(set_attr "type" "ssemov")
20277 (cond [(eq_attr "alternative" "0,1")
20279 (ne (symbol_ref "optimize_size")
20281 (const_string "V4SF")
20282 (const_string "TI"))
20283 (eq_attr "alternative" "2")
20285 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20287 (ne (symbol_ref "optimize_size")
20289 (const_string "V4SF")
20290 (const_string "TI"))]
20291 (const_string "TI")))])
20293 (define_insn "movv16qi_internal"
20294 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
20295 (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))]
20297 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20299 switch (which_alternative)
20302 if (get_attr_mode (insn) == MODE_V4SF)
20303 return "xorps\t%0, %0";
20305 return "pxor\t%0, %0";
20308 if (get_attr_mode (insn) == MODE_V4SF)
20309 return "movaps\t{%1, %0|%0, %1}";
20311 return "movdqa\t{%1, %0|%0, %1}";
20316 [(set_attr "type" "ssemov")
20318 (cond [(eq_attr "alternative" "0,1")
20320 (ne (symbol_ref "optimize_size")
20322 (const_string "V4SF")
20323 (const_string "TI"))
20324 (eq_attr "alternative" "2")
20326 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20328 (ne (symbol_ref "optimize_size")
20330 (const_string "V4SF")
20331 (const_string "TI"))]
20332 (const_string "TI")))])
20334 (define_expand "movv2df"
20335 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
20336 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
20339 ix86_expand_vector_move (V2DFmode, operands);
20343 (define_expand "movv8hi"
20344 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
20345 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
20348 ix86_expand_vector_move (V8HImode, operands);
20352 (define_expand "movv16qi"
20353 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
20354 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
20357 ix86_expand_vector_move (V16QImode, operands);
20361 (define_expand "movv4sf"
20362 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20363 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
20366 ix86_expand_vector_move (V4SFmode, operands);
20370 (define_expand "movv4si"
20371 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
20372 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
20375 ix86_expand_vector_move (V4SImode, operands);
20379 (define_expand "movv2di"
20380 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
20381 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
20384 ix86_expand_vector_move (V2DImode, operands);
20388 (define_expand "movv2si"
20389 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
20390 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
20393 ix86_expand_vector_move (V2SImode, operands);
20397 (define_expand "movv4hi"
20398 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
20399 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
20402 ix86_expand_vector_move (V4HImode, operands);
20406 (define_expand "movv8qi"
20407 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
20408 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
20411 ix86_expand_vector_move (V8QImode, operands);
20415 (define_expand "movv2sf"
20416 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
20417 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
20420 ix86_expand_vector_move (V2SFmode, operands);
20424 (define_insn "*pushti"
20425 [(set (match_operand:TI 0 "push_operand" "=<")
20426 (match_operand:TI 1 "register_operand" "x"))]
20430 (define_insn "*pushv2df"
20431 [(set (match_operand:V2DF 0 "push_operand" "=<")
20432 (match_operand:V2DF 1 "register_operand" "x"))]
20436 (define_insn "*pushv2di"
20437 [(set (match_operand:V2DI 0 "push_operand" "=<")
20438 (match_operand:V2DI 1 "register_operand" "x"))]
20442 (define_insn "*pushv8hi"
20443 [(set (match_operand:V8HI 0 "push_operand" "=<")
20444 (match_operand:V8HI 1 "register_operand" "x"))]
20448 (define_insn "*pushv16qi"
20449 [(set (match_operand:V16QI 0 "push_operand" "=<")
20450 (match_operand:V16QI 1 "register_operand" "x"))]
20454 (define_insn "*pushv4sf"
20455 [(set (match_operand:V4SF 0 "push_operand" "=<")
20456 (match_operand:V4SF 1 "register_operand" "x"))]
20460 (define_insn "*pushv4si"
20461 [(set (match_operand:V4SI 0 "push_operand" "=<")
20462 (match_operand:V4SI 1 "register_operand" "x"))]
20466 (define_insn "*pushv2si"
20467 [(set (match_operand:V2SI 0 "push_operand" "=<")
20468 (match_operand:V2SI 1 "register_operand" "y"))]
20472 (define_insn "*pushv4hi"
20473 [(set (match_operand:V4HI 0 "push_operand" "=<")
20474 (match_operand:V4HI 1 "register_operand" "y"))]
20478 (define_insn "*pushv8qi"
20479 [(set (match_operand:V8QI 0 "push_operand" "=<")
20480 (match_operand:V8QI 1 "register_operand" "y"))]
20484 (define_insn "*pushv2sf"
20485 [(set (match_operand:V2SF 0 "push_operand" "=<")
20486 (match_operand:V2SF 1 "register_operand" "y"))]
20491 [(set (match_operand 0 "push_operand" "")
20492 (match_operand 1 "register_operand" ""))]
20493 "!TARGET_64BIT && reload_completed
20494 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
20495 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 3)))
20496 (set (match_dup 2) (match_dup 1))]
20497 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
20498 stack_pointer_rtx);
20499 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
20502 [(set (match_operand 0 "push_operand" "")
20503 (match_operand 1 "register_operand" ""))]
20504 "TARGET_64BIT && reload_completed
20505 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
20506 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 3)))
20507 (set (match_dup 2) (match_dup 1))]
20508 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
20509 stack_pointer_rtx);
20510 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
20513 (define_insn "movti_internal"
20514 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
20515 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
20516 "TARGET_SSE && !TARGET_64BIT
20517 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20519 switch (which_alternative)
20522 if (get_attr_mode (insn) == MODE_V4SF)
20523 return "xorps\t%0, %0";
20525 return "pxor\t%0, %0";
20528 if (get_attr_mode (insn) == MODE_V4SF)
20529 return "movaps\t{%1, %0|%0, %1}";
20531 return "movdqa\t{%1, %0|%0, %1}";
20536 [(set_attr "type" "ssemov,ssemov,ssemov")
20538 (cond [(eq_attr "alternative" "0,1")
20540 (ne (symbol_ref "optimize_size")
20542 (const_string "V4SF")
20543 (const_string "TI"))
20544 (eq_attr "alternative" "2")
20546 (ne (symbol_ref "optimize_size")
20548 (const_string "V4SF")
20549 (const_string "TI"))]
20550 (const_string "TI")))])
20552 (define_insn "*movti_rex64"
20553 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
20554 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
20556 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20558 switch (which_alternative)
20564 if (get_attr_mode (insn) == MODE_V4SF)
20565 return "xorps\t%0, %0";
20567 return "pxor\t%0, %0";
20570 if (get_attr_mode (insn) == MODE_V4SF)
20571 return "movaps\t{%1, %0|%0, %1}";
20573 return "movdqa\t{%1, %0|%0, %1}";
20578 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
20580 (cond [(eq_attr "alternative" "2,3")
20582 (ne (symbol_ref "optimize_size")
20584 (const_string "V4SF")
20585 (const_string "TI"))
20586 (eq_attr "alternative" "4")
20588 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20590 (ne (symbol_ref "optimize_size")
20592 (const_string "V4SF")
20593 (const_string "TI"))]
20594 (const_string "DI")))])
20596 (define_insn "*movtf_rex64"
20597 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
20598 (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
20600 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20602 switch (which_alternative)
20608 if (get_attr_mode (insn) == MODE_V4SF)
20609 return "xorps\t%0, %0";
20611 return "pxor\t%0, %0";
20614 if (get_attr_mode (insn) == MODE_V4SF)
20615 return "movaps\t{%1, %0|%0, %1}";
20617 return "movdqa\t{%1, %0|%0, %1}";
20622 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
20624 (cond [(eq_attr "alternative" "2,3")
20626 (ne (symbol_ref "optimize_size")
20628 (const_string "V4SF")
20629 (const_string "TI"))
20630 (eq_attr "alternative" "4")
20632 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20634 (ne (symbol_ref "optimize_size")
20636 (const_string "V4SF")
20637 (const_string "TI"))]
20638 (const_string "DI")))])
20641 [(set (match_operand:TI 0 "nonimmediate_operand" "")
20642 (match_operand:TI 1 "general_operand" ""))]
20643 "reload_completed && !SSE_REG_P (operands[0])
20644 && !SSE_REG_P (operands[1])"
20646 "ix86_split_long_move (operands); DONE;")
20649 [(set (match_operand:TF 0 "nonimmediate_operand" "")
20650 (match_operand:TF 1 "general_operand" ""))]
20651 "reload_completed && !SSE_REG_P (operands[0])
20652 && !SSE_REG_P (operands[1])"
20654 "ix86_split_long_move (operands); DONE;")
20656 ;; These two patterns are useful for specifying exactly whether to use
20657 ;; movaps or movups
20658 (define_expand "sse_movaps"
20659 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20660 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
20664 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
20666 rtx tmp = gen_reg_rtx (V4SFmode);
20667 emit_insn (gen_sse_movaps (tmp, operands[1]));
20668 emit_move_insn (operands[0], tmp);
20673 (define_insn "*sse_movaps_1"
20674 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20675 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
20678 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20679 "movaps\t{%1, %0|%0, %1}"
20680 [(set_attr "type" "ssemov,ssemov")
20681 (set_attr "mode" "V4SF")])
20683 (define_expand "sse_movups"
20684 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20685 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
20689 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
20691 rtx tmp = gen_reg_rtx (V4SFmode);
20692 emit_insn (gen_sse_movups (tmp, operands[1]));
20693 emit_move_insn (operands[0], tmp);
20698 (define_insn "*sse_movups_1"
20699 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20700 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
20703 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20704 "movups\t{%1, %0|%0, %1}"
20705 [(set_attr "type" "ssecvt,ssecvt")
20706 (set_attr "mode" "V4SF")])
20708 ;; SSE Strange Moves.
20710 (define_insn "sse_movmskps"
20711 [(set (match_operand:SI 0 "register_operand" "=r")
20712 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
20715 "movmskps\t{%1, %0|%0, %1}"
20716 [(set_attr "type" "ssecvt")
20717 (set_attr "mode" "V4SF")])
20719 (define_insn "mmx_pmovmskb"
20720 [(set (match_operand:SI 0 "register_operand" "=r")
20721 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
20723 "TARGET_SSE || TARGET_3DNOW_A"
20724 "pmovmskb\t{%1, %0|%0, %1}"
20725 [(set_attr "type" "ssecvt")
20726 (set_attr "mode" "V4SF")])
20729 (define_insn "mmx_maskmovq"
20730 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
20731 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
20732 (match_operand:V8QI 2 "register_operand" "y")]
20734 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
20735 ;; @@@ check ordering of operands in intel/nonintel syntax
20736 "maskmovq\t{%2, %1|%1, %2}"
20737 [(set_attr "type" "mmxcvt")
20738 (set_attr "mode" "DI")])
20740 (define_insn "mmx_maskmovq_rex"
20741 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
20742 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
20743 (match_operand:V8QI 2 "register_operand" "y")]
20745 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
20746 ;; @@@ check ordering of operands in intel/nonintel syntax
20747 "maskmovq\t{%2, %1|%1, %2}"
20748 [(set_attr "type" "mmxcvt")
20749 (set_attr "mode" "DI")])
20751 (define_insn "sse_movntv4sf"
20752 [(set (match_operand:V4SF 0 "memory_operand" "=m")
20753 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
20756 "movntps\t{%1, %0|%0, %1}"
20757 [(set_attr "type" "ssemov")
20758 (set_attr "mode" "V4SF")])
20760 (define_insn "sse_movntdi"
20761 [(set (match_operand:DI 0 "memory_operand" "=m")
20762 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
20764 "TARGET_SSE || TARGET_3DNOW_A"
20765 "movntq\t{%1, %0|%0, %1}"
20766 [(set_attr "type" "mmxmov")
20767 (set_attr "mode" "DI")])
20769 (define_insn "sse_movhlps"
20770 [(set (match_operand:V4SF 0 "register_operand" "=x")
20772 (match_operand:V4SF 1 "register_operand" "0")
20773 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20774 (parallel [(const_int 2)
20780 "movhlps\t{%2, %0|%0, %2}"
20781 [(set_attr "type" "ssecvt")
20782 (set_attr "mode" "V4SF")])
20784 (define_insn "sse_movlhps"
20785 [(set (match_operand:V4SF 0 "register_operand" "=x")
20787 (match_operand:V4SF 1 "register_operand" "0")
20788 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20789 (parallel [(const_int 2)
20795 "movlhps\t{%2, %0|%0, %2}"
20796 [(set_attr "type" "ssecvt")
20797 (set_attr "mode" "V4SF")])
20799 (define_insn "sse_movhps"
20800 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20802 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
20803 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
20806 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
20807 "movhps\t{%2, %0|%0, %2}"
20808 [(set_attr "type" "ssecvt")
20809 (set_attr "mode" "V4SF")])
20811 (define_insn "sse_movlps"
20812 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20814 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
20815 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
20818 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
20819 "movlps\t{%2, %0|%0, %2}"
20820 [(set_attr "type" "ssecvt")
20821 (set_attr "mode" "V4SF")])
20823 (define_expand "sse_loadss"
20824 [(match_operand:V4SF 0 "register_operand" "")
20825 (match_operand:SF 1 "memory_operand" "")]
20828 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
20829 CONST0_RTX (V4SFmode)));
20833 (define_insn "sse_loadss_1"
20834 [(set (match_operand:V4SF 0 "register_operand" "=x")
20836 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
20837 (match_operand:V4SF 2 "const0_operand" "X")
20840 "movss\t{%1, %0|%0, %1}"
20841 [(set_attr "type" "ssemov")
20842 (set_attr "mode" "SF")])
20844 (define_insn "sse_movss"
20845 [(set (match_operand:V4SF 0 "register_operand" "=x")
20847 (match_operand:V4SF 1 "register_operand" "0")
20848 (match_operand:V4SF 2 "register_operand" "x")
20851 "movss\t{%2, %0|%0, %2}"
20852 [(set_attr "type" "ssemov")
20853 (set_attr "mode" "SF")])
20855 (define_insn "sse_storess"
20856 [(set (match_operand:SF 0 "memory_operand" "=m")
20858 (match_operand:V4SF 1 "register_operand" "x")
20859 (parallel [(const_int 0)])))]
20861 "movss\t{%1, %0|%0, %1}"
20862 [(set_attr "type" "ssemov")
20863 (set_attr "mode" "SF")])
20865 (define_insn "sse_shufps"
20866 [(set (match_operand:V4SF 0 "register_operand" "=x")
20867 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
20868 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
20869 (match_operand:SI 3 "immediate_operand" "i")]
20872 ;; @@@ check operand order for intel/nonintel syntax
20873 "shufps\t{%3, %2, %0|%0, %2, %3}"
20874 [(set_attr "type" "ssecvt")
20875 (set_attr "mode" "V4SF")])
20880 (define_insn "addv4sf3"
20881 [(set (match_operand:V4SF 0 "register_operand" "=x")
20882 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20883 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20885 "addps\t{%2, %0|%0, %2}"
20886 [(set_attr "type" "sseadd")
20887 (set_attr "mode" "V4SF")])
20889 (define_insn "vmaddv4sf3"
20890 [(set (match_operand:V4SF 0 "register_operand" "=x")
20892 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20893 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20897 "addss\t{%2, %0|%0, %2}"
20898 [(set_attr "type" "sseadd")
20899 (set_attr "mode" "SF")])
20901 (define_insn "subv4sf3"
20902 [(set (match_operand:V4SF 0 "register_operand" "=x")
20903 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20904 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20906 "subps\t{%2, %0|%0, %2}"
20907 [(set_attr "type" "sseadd")
20908 (set_attr "mode" "V4SF")])
20910 (define_insn "vmsubv4sf3"
20911 [(set (match_operand:V4SF 0 "register_operand" "=x")
20913 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20914 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20918 "subss\t{%2, %0|%0, %2}"
20919 [(set_attr "type" "sseadd")
20920 (set_attr "mode" "SF")])
20922 ;; ??? Should probably be done by generic code instead.
20923 (define_expand "negv4sf2"
20924 [(set (match_operand:V4SF 0 "register_operand" "")
20925 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
20929 rtx m0 = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
20930 rtx vm0 = gen_rtx_CONST_VECTOR (V4SFmode, gen_rtvec (4, m0, m0, m0, m0));
20931 operands[2] = force_reg (V4SFmode, vm0);
20934 (define_insn "mulv4sf3"
20935 [(set (match_operand:V4SF 0 "register_operand" "=x")
20936 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
20937 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20939 "mulps\t{%2, %0|%0, %2}"
20940 [(set_attr "type" "ssemul")
20941 (set_attr "mode" "V4SF")])
20943 (define_insn "vmmulv4sf3"
20944 [(set (match_operand:V4SF 0 "register_operand" "=x")
20946 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
20947 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20951 "mulss\t{%2, %0|%0, %2}"
20952 [(set_attr "type" "ssemul")
20953 (set_attr "mode" "SF")])
20955 (define_insn "divv4sf3"
20956 [(set (match_operand:V4SF 0 "register_operand" "=x")
20957 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20958 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20960 "divps\t{%2, %0|%0, %2}"
20961 [(set_attr "type" "ssediv")
20962 (set_attr "mode" "V4SF")])
20964 (define_insn "vmdivv4sf3"
20965 [(set (match_operand:V4SF 0 "register_operand" "=x")
20967 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20968 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20972 "divss\t{%2, %0|%0, %2}"
20973 [(set_attr "type" "ssediv")
20974 (set_attr "mode" "SF")])
20977 ;; SSE square root/reciprocal
20979 (define_insn "rcpv4sf2"
20980 [(set (match_operand:V4SF 0 "register_operand" "=x")
20982 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
20984 "rcpps\t{%1, %0|%0, %1}"
20985 [(set_attr "type" "sse")
20986 (set_attr "mode" "V4SF")])
20988 (define_insn "vmrcpv4sf2"
20989 [(set (match_operand:V4SF 0 "register_operand" "=x")
20991 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20993 (match_operand:V4SF 2 "register_operand" "0")
20996 "rcpss\t{%1, %0|%0, %1}"
20997 [(set_attr "type" "sse")
20998 (set_attr "mode" "SF")])
21000 (define_insn "rsqrtv4sf2"
21001 [(set (match_operand:V4SF 0 "register_operand" "=x")
21003 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
21005 "rsqrtps\t{%1, %0|%0, %1}"
21006 [(set_attr "type" "sse")
21007 (set_attr "mode" "V4SF")])
21009 (define_insn "vmrsqrtv4sf2"
21010 [(set (match_operand:V4SF 0 "register_operand" "=x")
21012 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21014 (match_operand:V4SF 2 "register_operand" "0")
21017 "rsqrtss\t{%1, %0|%0, %1}"
21018 [(set_attr "type" "sse")
21019 (set_attr "mode" "SF")])
21021 (define_insn "sqrtv4sf2"
21022 [(set (match_operand:V4SF 0 "register_operand" "=x")
21023 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
21025 "sqrtps\t{%1, %0|%0, %1}"
21026 [(set_attr "type" "sse")
21027 (set_attr "mode" "V4SF")])
21029 (define_insn "vmsqrtv4sf2"
21030 [(set (match_operand:V4SF 0 "register_operand" "=x")
21032 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
21033 (match_operand:V4SF 2 "register_operand" "0")
21036 "sqrtss\t{%1, %0|%0, %1}"
21037 [(set_attr "type" "sse")
21038 (set_attr "mode" "SF")])
21040 ;; SSE logical operations.
21042 ;; SSE defines logical operations on floating point values. This brings
21043 ;; interesting challenge to RTL representation where logicals are only valid
21044 ;; on integral types. We deal with this by representing the floating point
21045 ;; logical as logical on arguments casted to TImode as this is what hardware
21046 ;; really does. Unfortunately hardware requires the type information to be
21047 ;; present and thus we must avoid subregs from being simplified and eliminated
21048 ;; in later compilation phases.
21050 ;; We have following variants from each instruction:
21051 ;; sse_andsf3 - the operation taking V4SF vector operands
21052 ;; and doing TImode cast on them
21053 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
21054 ;; TImode, since backend insist on eliminating casts
21055 ;; on memory operands
21056 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
21057 ;; We cannot accept memory operand here as instruction reads
21058 ;; whole scalar. This is generated only post reload by GCC
21059 ;; scalar float operations that expands to logicals (fabs)
21060 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
21061 ;; memory operand. Eventually combine can be able
21062 ;; to synthesize these using splitter.
21063 ;; sse2_anddf3, *sse2_anddf3_memory
21066 ;; These are not called andti3 etc. because we really really don't want
21067 ;; the compiler to widen DImode ands to TImode ands and then try to move
21068 ;; into DImode subregs of SSE registers, and them together, and move out
21069 ;; of DImode subregs again!
21070 ;; SSE1 single precision floating point logical operation
21071 (define_expand "sse_andv4sf3"
21072 [(set (match_operand:V4SF 0 "register_operand" "")
21073 (and:V4SF (match_operand:V4SF 1 "register_operand" "")
21074 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
21078 (define_insn "*sse_andv4sf3"
21079 [(set (match_operand:V4SF 0 "register_operand" "=x")
21080 (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
21081 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21083 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21084 "andps\t{%2, %0|%0, %2}"
21085 [(set_attr "type" "sselog")
21086 (set_attr "mode" "V4SF")])
21088 (define_expand "sse_nandv4sf3"
21089 [(set (match_operand:V4SF 0 "register_operand" "")
21090 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" ""))
21091 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
21095 (define_insn "*sse_nandv4sf3"
21096 [(set (match_operand:V4SF 0 "register_operand" "=x")
21097 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "0"))
21098 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21100 "andnps\t{%2, %0|%0, %2}"
21101 [(set_attr "type" "sselog")
21102 (set_attr "mode" "V4SF")])
21104 (define_expand "sse_iorv4sf3"
21105 [(set (match_operand:V4SF 0 "register_operand" "")
21106 (ior:V4SF (match_operand:V4SF 1 "register_operand" "")
21107 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
21111 (define_insn "*sse_iorv4sf3"
21112 [(set (match_operand:V4SF 0 "register_operand" "=x")
21113 (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
21114 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21116 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21117 "orps\t{%2, %0|%0, %2}"
21118 [(set_attr "type" "sselog")
21119 (set_attr "mode" "V4SF")])
21121 (define_expand "sse_xorv4sf3"
21122 [(set (match_operand:V4SF 0 "register_operand" "")
21123 (xor:V4SF (match_operand:V4SF 1 "register_operand" "")
21124 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
21128 (define_insn "*sse_xorv4sf3"
21129 [(set (match_operand:V4SF 0 "register_operand" "=x")
21130 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
21131 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21133 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21134 "xorps\t{%2, %0|%0, %2}"
21135 [(set_attr "type" "sselog")
21136 (set_attr "mode" "V4SF")])
21138 ;; SSE2 double precision floating point logical operation
21140 (define_expand "sse2_andv2df3"
21141 [(set (match_operand:V2DF 0 "register_operand" "")
21142 (and:V2DF (match_operand:V2DF 1 "register_operand" "")
21143 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
21147 (define_insn "*sse2_andv2df3"
21148 [(set (match_operand:V2DF 0 "register_operand" "=x")
21149 (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
21150 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21152 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21153 "andpd\t{%2, %0|%0, %2}"
21154 [(set_attr "type" "sselog")
21155 (set_attr "mode" "V2DF")])
21157 (define_expand "sse2_nandv2df3"
21158 [(set (match_operand:V2DF 0 "register_operand" "")
21159 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" ""))
21160 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
21164 (define_insn "*sse2_nandv2df3"
21165 [(set (match_operand:V2DF 0 "register_operand" "=x")
21166 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "0"))
21167 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21169 "andnpd\t{%2, %0|%0, %2}"
21170 [(set_attr "type" "sselog")
21171 (set_attr "mode" "V2DF")])
21173 (define_expand "sse2_iorv2df3"
21174 [(set (match_operand:V2DF 0 "register_operand" "")
21175 (ior:V2DF (match_operand:V2DF 1 "register_operand" "")
21176 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
21180 (define_insn "*sse2_iorv2df3"
21181 [(set (match_operand:V2DF 0 "register_operand" "=x")
21182 (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
21183 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21185 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21186 "orpd\t{%2, %0|%0, %2}"
21187 [(set_attr "type" "sselog")
21188 (set_attr "mode" "V2DF")])
21190 (define_expand "sse2_xorv2df3"
21191 [(set (match_operand:V2DF 0 "register_operand" "")
21192 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
21193 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
21197 (define_insn "*sse2_xorv2df3"
21198 [(set (match_operand:V2DF 0 "register_operand" "=x")
21199 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
21200 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21202 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21203 "xorpd\t{%2, %0|%0, %2}"
21204 [(set_attr "type" "sselog")
21205 (set_attr "mode" "V2DF")])
21207 ;; SSE2 integral logicals. These patterns must always come after floating
21208 ;; point ones since we don't want compiler to use integer opcodes on floating
21209 ;; point SSE values to avoid matching of subregs in the match_operand.
21210 (define_insn "*sse2_andti3"
21211 [(set (match_operand:TI 0 "register_operand" "=x")
21212 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
21213 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
21215 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21216 "pand\t{%2, %0|%0, %2}"
21217 [(set_attr "type" "sselog")
21218 (set_attr "mode" "TI")])
21220 (define_insn "sse2_andv2di3"
21221 [(set (match_operand:V2DI 0 "register_operand" "=x")
21222 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
21223 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21225 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21226 "pand\t{%2, %0|%0, %2}"
21227 [(set_attr "type" "sselog")
21228 (set_attr "mode" "TI")])
21230 (define_insn "*sse2_nandti3"
21231 [(set (match_operand:TI 0 "register_operand" "=x")
21232 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
21233 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
21235 "pandn\t{%2, %0|%0, %2}"
21236 [(set_attr "type" "sselog")
21237 (set_attr "mode" "TI")])
21239 (define_insn "sse2_nandv2di3"
21240 [(set (match_operand:V2DI 0 "register_operand" "=x")
21241 (and:V2DI (not:V2DI (match_operand:V2DI 1 "register_operand" "0"))
21242 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21244 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21245 "pandn\t{%2, %0|%0, %2}"
21246 [(set_attr "type" "sselog")
21247 (set_attr "mode" "TI")])
21249 (define_insn "*sse2_iorti3"
21250 [(set (match_operand:TI 0 "register_operand" "=x")
21251 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
21252 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
21254 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21255 "por\t{%2, %0|%0, %2}"
21256 [(set_attr "type" "sselog")
21257 (set_attr "mode" "TI")])
21259 (define_insn "sse2_iorv2di3"
21260 [(set (match_operand:V2DI 0 "register_operand" "=x")
21261 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
21262 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21264 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21265 "por\t{%2, %0|%0, %2}"
21266 [(set_attr "type" "sselog")
21267 (set_attr "mode" "TI")])
21269 (define_insn "*sse2_xorti3"
21270 [(set (match_operand:TI 0 "register_operand" "=x")
21271 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
21272 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
21274 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21275 "pxor\t{%2, %0|%0, %2}"
21276 [(set_attr "type" "sselog")
21277 (set_attr "mode" "TI")])
21279 (define_insn "sse2_xorv2di3"
21280 [(set (match_operand:V2DI 0 "register_operand" "=x")
21281 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
21282 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21284 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
21285 "pxor\t{%2, %0|%0, %2}"
21286 [(set_attr "type" "sselog")
21287 (set_attr "mode" "TI")])
21289 ;; Use xor, but don't show input operands so they aren't live before
21291 (define_insn "sse_clrv4sf"
21292 [(set (match_operand:V4SF 0 "register_operand" "=x")
21293 (match_operand:V4SF 1 "const0_operand" "X"))]
21296 if (get_attr_mode (insn) == MODE_TI)
21297 return "pxor\t{%0, %0|%0, %0}";
21299 return "xorps\t{%0, %0|%0, %0}";
21301 [(set_attr "type" "sselog")
21302 (set_attr "memory" "none")
21305 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
21307 (ne (symbol_ref "TARGET_SSE2")
21309 (eq (symbol_ref "optimize_size")
21311 (const_string "TI")
21312 (const_string "V4SF")))])
21314 ;; Use xor, but don't show input operands so they aren't live before
21316 (define_insn "sse_clrv2df"
21317 [(set (match_operand:V2DF 0 "register_operand" "=x")
21318 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
21320 "xorpd\t{%0, %0|%0, %0}"
21321 [(set_attr "type" "sselog")
21322 (set_attr "memory" "none")
21323 (set_attr "mode" "V4SF")])
21325 ;; SSE mask-generating compares
21327 (define_insn "maskcmpv4sf3"
21328 [(set (match_operand:V4SI 0 "register_operand" "=x")
21329 (match_operator:V4SI 3 "sse_comparison_operator"
21330 [(match_operand:V4SF 1 "register_operand" "0")
21331 (match_operand:V4SF 2 "register_operand" "x")]))]
21333 "cmp%D3ps\t{%2, %0|%0, %2}"
21334 [(set_attr "type" "ssecmp")
21335 (set_attr "mode" "V4SF")])
21337 (define_insn "maskncmpv4sf3"
21338 [(set (match_operand:V4SI 0 "register_operand" "=x")
21340 (match_operator:V4SI 3 "sse_comparison_operator"
21341 [(match_operand:V4SF 1 "register_operand" "0")
21342 (match_operand:V4SF 2 "register_operand" "x")])))]
21345 if (GET_CODE (operands[3]) == UNORDERED)
21346 return "cmpordps\t{%2, %0|%0, %2}";
21348 return "cmpn%D3ps\t{%2, %0|%0, %2}";
21350 [(set_attr "type" "ssecmp")
21351 (set_attr "mode" "V4SF")])
21353 (define_insn "vmmaskcmpv4sf3"
21354 [(set (match_operand:V4SI 0 "register_operand" "=x")
21356 (match_operator:V4SI 3 "sse_comparison_operator"
21357 [(match_operand:V4SF 1 "register_operand" "0")
21358 (match_operand:V4SF 2 "register_operand" "x")])
21359 (subreg:V4SI (match_dup 1) 0)
21362 "cmp%D3ss\t{%2, %0|%0, %2}"
21363 [(set_attr "type" "ssecmp")
21364 (set_attr "mode" "SF")])
21366 (define_insn "vmmaskncmpv4sf3"
21367 [(set (match_operand:V4SI 0 "register_operand" "=x")
21370 (match_operator:V4SI 3 "sse_comparison_operator"
21371 [(match_operand:V4SF 1 "register_operand" "0")
21372 (match_operand:V4SF 2 "register_operand" "x")]))
21373 (subreg:V4SI (match_dup 1) 0)
21377 if (GET_CODE (operands[3]) == UNORDERED)
21378 return "cmpordss\t{%2, %0|%0, %2}";
21380 return "cmpn%D3ss\t{%2, %0|%0, %2}";
21382 [(set_attr "type" "ssecmp")
21383 (set_attr "mode" "SF")])
21385 (define_insn "sse_comi"
21386 [(set (reg:CCFP FLAGS_REG)
21387 (compare:CCFP (vec_select:SF
21388 (match_operand:V4SF 0 "register_operand" "x")
21389 (parallel [(const_int 0)]))
21391 (match_operand:V4SF 1 "register_operand" "x")
21392 (parallel [(const_int 0)]))))]
21394 "comiss\t{%1, %0|%0, %1}"
21395 [(set_attr "type" "ssecomi")
21396 (set_attr "mode" "SF")])
21398 (define_insn "sse_ucomi"
21399 [(set (reg:CCFPU FLAGS_REG)
21400 (compare:CCFPU (vec_select:SF
21401 (match_operand:V4SF 0 "register_operand" "x")
21402 (parallel [(const_int 0)]))
21404 (match_operand:V4SF 1 "register_operand" "x")
21405 (parallel [(const_int 0)]))))]
21407 "ucomiss\t{%1, %0|%0, %1}"
21408 [(set_attr "type" "ssecomi")
21409 (set_attr "mode" "SF")])
21414 (define_insn "sse_unpckhps"
21415 [(set (match_operand:V4SF 0 "register_operand" "=x")
21417 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
21418 (parallel [(const_int 2)
21422 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
21423 (parallel [(const_int 0)
21429 "unpckhps\t{%2, %0|%0, %2}"
21430 [(set_attr "type" "ssecvt")
21431 (set_attr "mode" "V4SF")])
21433 (define_insn "sse_unpcklps"
21434 [(set (match_operand:V4SF 0 "register_operand" "=x")
21436 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
21437 (parallel [(const_int 0)
21441 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
21442 (parallel [(const_int 2)
21448 "unpcklps\t{%2, %0|%0, %2}"
21449 [(set_attr "type" "ssecvt")
21450 (set_attr "mode" "V4SF")])
21455 (define_insn "smaxv4sf3"
21456 [(set (match_operand:V4SF 0 "register_operand" "=x")
21457 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
21458 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21460 "maxps\t{%2, %0|%0, %2}"
21461 [(set_attr "type" "sse")
21462 (set_attr "mode" "V4SF")])
21464 (define_insn "vmsmaxv4sf3"
21465 [(set (match_operand:V4SF 0 "register_operand" "=x")
21467 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
21468 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
21472 "maxss\t{%2, %0|%0, %2}"
21473 [(set_attr "type" "sse")
21474 (set_attr "mode" "SF")])
21476 (define_insn "sminv4sf3"
21477 [(set (match_operand:V4SF 0 "register_operand" "=x")
21478 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
21479 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21481 "minps\t{%2, %0|%0, %2}"
21482 [(set_attr "type" "sse")
21483 (set_attr "mode" "V4SF")])
21485 (define_insn "vmsminv4sf3"
21486 [(set (match_operand:V4SF 0 "register_operand" "=x")
21488 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
21489 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
21493 "minss\t{%2, %0|%0, %2}"
21494 [(set_attr "type" "sse")
21495 (set_attr "mode" "SF")])
21497 ;; SSE <-> integer/MMX conversions
21499 (define_insn "cvtpi2ps"
21500 [(set (match_operand:V4SF 0 "register_operand" "=x")
21502 (match_operand:V4SF 1 "register_operand" "0")
21503 (vec_duplicate:V4SF
21504 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
21507 "cvtpi2ps\t{%2, %0|%0, %2}"
21508 [(set_attr "type" "ssecvt")
21509 (set_attr "mode" "V4SF")])
21511 (define_insn "cvtps2pi"
21512 [(set (match_operand:V2SI 0 "register_operand" "=y")
21514 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
21515 (parallel [(const_int 0) (const_int 1)])))]
21517 "cvtps2pi\t{%1, %0|%0, %1}"
21518 [(set_attr "type" "ssecvt")
21519 (set_attr "mode" "V4SF")])
21521 (define_insn "cvttps2pi"
21522 [(set (match_operand:V2SI 0 "register_operand" "=y")
21524 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21526 (parallel [(const_int 0) (const_int 1)])))]
21528 "cvttps2pi\t{%1, %0|%0, %1}"
21529 [(set_attr "type" "ssecvt")
21530 (set_attr "mode" "SF")])
21532 (define_insn "cvtsi2ss"
21533 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21535 (match_operand:V4SF 1 "register_operand" "0,0")
21536 (vec_duplicate:V4SF
21537 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
21540 "cvtsi2ss\t{%2, %0|%0, %2}"
21541 [(set_attr "type" "sseicvt")
21542 (set_attr "athlon_decode" "vector,double")
21543 (set_attr "mode" "SF")])
21545 (define_insn "cvtsi2ssq"
21546 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21548 (match_operand:V4SF 1 "register_operand" "0,0")
21549 (vec_duplicate:V4SF
21550 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
21552 "TARGET_SSE && TARGET_64BIT"
21553 "cvtsi2ssq\t{%2, %0|%0, %2}"
21554 [(set_attr "type" "sseicvt")
21555 (set_attr "athlon_decode" "vector,double")
21556 (set_attr "mode" "SF")])
21558 (define_insn "cvtss2si"
21559 [(set (match_operand:SI 0 "register_operand" "=r,r")
21561 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
21562 (parallel [(const_int 0)])))]
21564 "cvtss2si\t{%1, %0|%0, %1}"
21565 [(set_attr "type" "sseicvt")
21566 (set_attr "athlon_decode" "double,vector")
21567 (set_attr "mode" "SI")])
21569 (define_insn "cvtss2siq"
21570 [(set (match_operand:DI 0 "register_operand" "=r,r")
21572 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
21573 (parallel [(const_int 0)])))]
21575 "cvtss2siq\t{%1, %0|%0, %1}"
21576 [(set_attr "type" "sseicvt")
21577 (set_attr "athlon_decode" "double,vector")
21578 (set_attr "mode" "DI")])
21580 (define_insn "cvttss2si"
21581 [(set (match_operand:SI 0 "register_operand" "=r,r")
21583 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
21585 (parallel [(const_int 0)])))]
21587 "cvttss2si\t{%1, %0|%0, %1}"
21588 [(set_attr "type" "sseicvt")
21589 (set_attr "mode" "SF")
21590 (set_attr "athlon_decode" "double,vector")])
21592 (define_insn "cvttss2siq"
21593 [(set (match_operand:DI 0 "register_operand" "=r,r")
21595 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
21597 (parallel [(const_int 0)])))]
21598 "TARGET_SSE && TARGET_64BIT"
21599 "cvttss2siq\t{%1, %0|%0, %1}"
21600 [(set_attr "type" "sseicvt")
21601 (set_attr "mode" "SF")
21602 (set_attr "athlon_decode" "double,vector")])
21609 (define_insn "addv8qi3"
21610 [(set (match_operand:V8QI 0 "register_operand" "=y")
21611 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21612 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21614 "paddb\t{%2, %0|%0, %2}"
21615 [(set_attr "type" "mmxadd")
21616 (set_attr "mode" "DI")])
21618 (define_insn "addv4hi3"
21619 [(set (match_operand:V4HI 0 "register_operand" "=y")
21620 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21621 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21623 "paddw\t{%2, %0|%0, %2}"
21624 [(set_attr "type" "mmxadd")
21625 (set_attr "mode" "DI")])
21627 (define_insn "addv2si3"
21628 [(set (match_operand:V2SI 0 "register_operand" "=y")
21629 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
21630 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21632 "paddd\t{%2, %0|%0, %2}"
21633 [(set_attr "type" "mmxadd")
21634 (set_attr "mode" "DI")])
21636 (define_insn "mmx_adddi3"
21637 [(set (match_operand:DI 0 "register_operand" "=y")
21639 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
21640 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21643 "paddq\t{%2, %0|%0, %2}"
21644 [(set_attr "type" "mmxadd")
21645 (set_attr "mode" "DI")])
21647 (define_insn "ssaddv8qi3"
21648 [(set (match_operand:V8QI 0 "register_operand" "=y")
21649 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21650 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21652 "paddsb\t{%2, %0|%0, %2}"
21653 [(set_attr "type" "mmxadd")
21654 (set_attr "mode" "DI")])
21656 (define_insn "ssaddv4hi3"
21657 [(set (match_operand:V4HI 0 "register_operand" "=y")
21658 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21659 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21661 "paddsw\t{%2, %0|%0, %2}"
21662 [(set_attr "type" "mmxadd")
21663 (set_attr "mode" "DI")])
21665 (define_insn "usaddv8qi3"
21666 [(set (match_operand:V8QI 0 "register_operand" "=y")
21667 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21668 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21670 "paddusb\t{%2, %0|%0, %2}"
21671 [(set_attr "type" "mmxadd")
21672 (set_attr "mode" "DI")])
21674 (define_insn "usaddv4hi3"
21675 [(set (match_operand:V4HI 0 "register_operand" "=y")
21676 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21677 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21679 "paddusw\t{%2, %0|%0, %2}"
21680 [(set_attr "type" "mmxadd")
21681 (set_attr "mode" "DI")])
21683 (define_insn "subv8qi3"
21684 [(set (match_operand:V8QI 0 "register_operand" "=y")
21685 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21686 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21688 "psubb\t{%2, %0|%0, %2}"
21689 [(set_attr "type" "mmxadd")
21690 (set_attr "mode" "DI")])
21692 (define_insn "subv4hi3"
21693 [(set (match_operand:V4HI 0 "register_operand" "=y")
21694 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21695 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21697 "psubw\t{%2, %0|%0, %2}"
21698 [(set_attr "type" "mmxadd")
21699 (set_attr "mode" "DI")])
21701 (define_insn "subv2si3"
21702 [(set (match_operand:V2SI 0 "register_operand" "=y")
21703 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
21704 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21706 "psubd\t{%2, %0|%0, %2}"
21707 [(set_attr "type" "mmxadd")
21708 (set_attr "mode" "DI")])
21710 (define_insn "mmx_subdi3"
21711 [(set (match_operand:DI 0 "register_operand" "=y")
21713 [(minus:DI (match_operand:DI 1 "register_operand" "0")
21714 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21717 "psubq\t{%2, %0|%0, %2}"
21718 [(set_attr "type" "mmxadd")
21719 (set_attr "mode" "DI")])
21721 (define_insn "sssubv8qi3"
21722 [(set (match_operand:V8QI 0 "register_operand" "=y")
21723 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21724 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21726 "psubsb\t{%2, %0|%0, %2}"
21727 [(set_attr "type" "mmxadd")
21728 (set_attr "mode" "DI")])
21730 (define_insn "sssubv4hi3"
21731 [(set (match_operand:V4HI 0 "register_operand" "=y")
21732 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21733 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21735 "psubsw\t{%2, %0|%0, %2}"
21736 [(set_attr "type" "mmxadd")
21737 (set_attr "mode" "DI")])
21739 (define_insn "ussubv8qi3"
21740 [(set (match_operand:V8QI 0 "register_operand" "=y")
21741 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21742 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21744 "psubusb\t{%2, %0|%0, %2}"
21745 [(set_attr "type" "mmxadd")
21746 (set_attr "mode" "DI")])
21748 (define_insn "ussubv4hi3"
21749 [(set (match_operand:V4HI 0 "register_operand" "=y")
21750 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21751 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21753 "psubusw\t{%2, %0|%0, %2}"
21754 [(set_attr "type" "mmxadd")
21755 (set_attr "mode" "DI")])
21757 (define_insn "mulv4hi3"
21758 [(set (match_operand:V4HI 0 "register_operand" "=y")
21759 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
21760 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21762 "pmullw\t{%2, %0|%0, %2}"
21763 [(set_attr "type" "mmxmul")
21764 (set_attr "mode" "DI")])
21766 (define_insn "smulv4hi3_highpart"
21767 [(set (match_operand:V4HI 0 "register_operand" "=y")
21770 (mult:V4SI (sign_extend:V4SI
21771 (match_operand:V4HI 1 "register_operand" "0"))
21773 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21776 "pmulhw\t{%2, %0|%0, %2}"
21777 [(set_attr "type" "mmxmul")
21778 (set_attr "mode" "DI")])
21780 (define_insn "umulv4hi3_highpart"
21781 [(set (match_operand:V4HI 0 "register_operand" "=y")
21784 (mult:V4SI (zero_extend:V4SI
21785 (match_operand:V4HI 1 "register_operand" "0"))
21787 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21789 "TARGET_SSE || TARGET_3DNOW_A"
21790 "pmulhuw\t{%2, %0|%0, %2}"
21791 [(set_attr "type" "mmxmul")
21792 (set_attr "mode" "DI")])
21794 (define_insn "mmx_pmaddwd"
21795 [(set (match_operand:V2SI 0 "register_operand" "=y")
21799 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
21800 (parallel [(const_int 0) (const_int 2)])))
21802 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
21803 (parallel [(const_int 0) (const_int 2)]))))
21805 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
21806 (parallel [(const_int 1)
21808 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
21809 (parallel [(const_int 1)
21810 (const_int 3)]))))))]
21812 "pmaddwd\t{%2, %0|%0, %2}"
21813 [(set_attr "type" "mmxmul")
21814 (set_attr "mode" "DI")])
21817 ;; MMX logical operations
21818 ;; Note we don't want to declare these as regular iordi3 insns to prevent
21819 ;; normal code that also wants to use the FPU from getting broken.
21820 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
21821 (define_insn "mmx_iordi3"
21822 [(set (match_operand:DI 0 "register_operand" "=y")
21824 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
21825 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21828 "por\t{%2, %0|%0, %2}"
21829 [(set_attr "type" "mmxadd")
21830 (set_attr "mode" "DI")])
21832 (define_insn "mmx_xordi3"
21833 [(set (match_operand:DI 0 "register_operand" "=y")
21835 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
21836 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21839 "pxor\t{%2, %0|%0, %2}"
21840 [(set_attr "type" "mmxadd")
21841 (set_attr "mode" "DI")
21842 (set_attr "memory" "none")])
21844 ;; Same as pxor, but don't show input operands so that we don't think
21846 (define_insn "mmx_clrdi"
21847 [(set (match_operand:DI 0 "register_operand" "=y")
21848 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
21850 "pxor\t{%0, %0|%0, %0}"
21851 [(set_attr "type" "mmxadd")
21852 (set_attr "mode" "DI")
21853 (set_attr "memory" "none")])
21855 (define_insn "mmx_anddi3"
21856 [(set (match_operand:DI 0 "register_operand" "=y")
21858 [(and:DI (match_operand:DI 1 "register_operand" "%0")
21859 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21862 "pand\t{%2, %0|%0, %2}"
21863 [(set_attr "type" "mmxadd")
21864 (set_attr "mode" "DI")])
21866 (define_insn "mmx_nanddi3"
21867 [(set (match_operand:DI 0 "register_operand" "=y")
21869 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
21870 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21873 "pandn\t{%2, %0|%0, %2}"
21874 [(set_attr "type" "mmxadd")
21875 (set_attr "mode" "DI")])
21878 ;; MMX unsigned averages/sum of absolute differences
21880 (define_insn "mmx_uavgv8qi3"
21881 [(set (match_operand:V8QI 0 "register_operand" "=y")
21883 (plus:V8QI (plus:V8QI
21884 (match_operand:V8QI 1 "register_operand" "0")
21885 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
21886 (const_vector:V8QI [(const_int 1)
21895 "TARGET_SSE || TARGET_3DNOW_A"
21896 "pavgb\t{%2, %0|%0, %2}"
21897 [(set_attr "type" "mmxshft")
21898 (set_attr "mode" "DI")])
21900 (define_insn "mmx_uavgv4hi3"
21901 [(set (match_operand:V4HI 0 "register_operand" "=y")
21903 (plus:V4HI (plus:V4HI
21904 (match_operand:V4HI 1 "register_operand" "0")
21905 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
21906 (const_vector:V4HI [(const_int 1)
21911 "TARGET_SSE || TARGET_3DNOW_A"
21912 "pavgw\t{%2, %0|%0, %2}"
21913 [(set_attr "type" "mmxshft")
21914 (set_attr "mode" "DI")])
21916 (define_insn "mmx_psadbw"
21917 [(set (match_operand:DI 0 "register_operand" "=y")
21918 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
21919 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21921 "TARGET_SSE || TARGET_3DNOW_A"
21922 "psadbw\t{%2, %0|%0, %2}"
21923 [(set_attr "type" "mmxshft")
21924 (set_attr "mode" "DI")])
21927 ;; MMX insert/extract/shuffle
21929 (define_insn "mmx_pinsrw"
21930 [(set (match_operand:V4HI 0 "register_operand" "=y")
21931 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
21932 (vec_duplicate:V4HI
21933 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
21934 (match_operand:SI 3 "const_0_to_15_operand" "N")))]
21935 "TARGET_SSE || TARGET_3DNOW_A"
21936 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
21937 [(set_attr "type" "mmxcvt")
21938 (set_attr "mode" "DI")])
21940 (define_insn "mmx_pextrw"
21941 [(set (match_operand:SI 0 "register_operand" "=r")
21942 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
21944 [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
21945 "TARGET_SSE || TARGET_3DNOW_A"
21946 "pextrw\t{%2, %1, %0|%0, %1, %2}"
21947 [(set_attr "type" "mmxcvt")
21948 (set_attr "mode" "DI")])
21950 (define_insn "mmx_pshufw"
21951 [(set (match_operand:V4HI 0 "register_operand" "=y")
21952 (unspec:V4HI [(match_operand:V4HI 1 "nonimmediate_operand" "ym")
21953 (match_operand:SI 2 "immediate_operand" "i")]
21955 "TARGET_SSE || TARGET_3DNOW_A"
21956 "pshufw\t{%2, %1, %0|%0, %1, %2}"
21957 [(set_attr "type" "mmxcvt")
21958 (set_attr "mode" "DI")])
21961 ;; MMX mask-generating comparisons
21963 (define_insn "eqv8qi3"
21964 [(set (match_operand:V8QI 0 "register_operand" "=y")
21965 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
21966 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21968 "pcmpeqb\t{%2, %0|%0, %2}"
21969 [(set_attr "type" "mmxcmp")
21970 (set_attr "mode" "DI")])
21972 (define_insn "eqv4hi3"
21973 [(set (match_operand:V4HI 0 "register_operand" "=y")
21974 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
21975 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21977 "pcmpeqw\t{%2, %0|%0, %2}"
21978 [(set_attr "type" "mmxcmp")
21979 (set_attr "mode" "DI")])
21981 (define_insn "eqv2si3"
21982 [(set (match_operand:V2SI 0 "register_operand" "=y")
21983 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
21984 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21986 "pcmpeqd\t{%2, %0|%0, %2}"
21987 [(set_attr "type" "mmxcmp")
21988 (set_attr "mode" "DI")])
21990 (define_insn "gtv8qi3"
21991 [(set (match_operand:V8QI 0 "register_operand" "=y")
21992 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
21993 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21995 "pcmpgtb\t{%2, %0|%0, %2}"
21996 [(set_attr "type" "mmxcmp")
21997 (set_attr "mode" "DI")])
21999 (define_insn "gtv4hi3"
22000 [(set (match_operand:V4HI 0 "register_operand" "=y")
22001 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
22002 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
22004 "pcmpgtw\t{%2, %0|%0, %2}"
22005 [(set_attr "type" "mmxcmp")
22006 (set_attr "mode" "DI")])
22008 (define_insn "gtv2si3"
22009 [(set (match_operand:V2SI 0 "register_operand" "=y")
22010 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
22011 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
22013 "pcmpgtd\t{%2, %0|%0, %2}"
22014 [(set_attr "type" "mmxcmp")
22015 (set_attr "mode" "DI")])
22018 ;; MMX max/min insns
22020 (define_insn "umaxv8qi3"
22021 [(set (match_operand:V8QI 0 "register_operand" "=y")
22022 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
22023 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
22024 "TARGET_SSE || TARGET_3DNOW_A"
22025 "pmaxub\t{%2, %0|%0, %2}"
22026 [(set_attr "type" "mmxadd")
22027 (set_attr "mode" "DI")])
22029 (define_insn "smaxv4hi3"
22030 [(set (match_operand:V4HI 0 "register_operand" "=y")
22031 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
22032 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
22033 "TARGET_SSE || TARGET_3DNOW_A"
22034 "pmaxsw\t{%2, %0|%0, %2}"
22035 [(set_attr "type" "mmxadd")
22036 (set_attr "mode" "DI")])
22038 (define_insn "uminv8qi3"
22039 [(set (match_operand:V8QI 0 "register_operand" "=y")
22040 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
22041 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
22042 "TARGET_SSE || TARGET_3DNOW_A"
22043 "pminub\t{%2, %0|%0, %2}"
22044 [(set_attr "type" "mmxadd")
22045 (set_attr "mode" "DI")])
22047 (define_insn "sminv4hi3"
22048 [(set (match_operand:V4HI 0 "register_operand" "=y")
22049 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
22050 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
22051 "TARGET_SSE || TARGET_3DNOW_A"
22052 "pminsw\t{%2, %0|%0, %2}"
22053 [(set_attr "type" "mmxadd")
22054 (set_attr "mode" "DI")])
22059 (define_insn "ashrv4hi3"
22060 [(set (match_operand:V4HI 0 "register_operand" "=y")
22061 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
22062 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22064 "psraw\t{%2, %0|%0, %2}"
22065 [(set_attr "type" "mmxshft")
22066 (set_attr "mode" "DI")])
22068 (define_insn "ashrv2si3"
22069 [(set (match_operand:V2SI 0 "register_operand" "=y")
22070 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
22071 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22073 "psrad\t{%2, %0|%0, %2}"
22074 [(set_attr "type" "mmxshft")
22075 (set_attr "mode" "DI")])
22077 (define_insn "lshrv4hi3"
22078 [(set (match_operand:V4HI 0 "register_operand" "=y")
22079 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
22080 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22082 "psrlw\t{%2, %0|%0, %2}"
22083 [(set_attr "type" "mmxshft")
22084 (set_attr "mode" "DI")])
22086 (define_insn "lshrv2si3"
22087 [(set (match_operand:V2SI 0 "register_operand" "=y")
22088 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
22089 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22091 "psrld\t{%2, %0|%0, %2}"
22092 [(set_attr "type" "mmxshft")
22093 (set_attr "mode" "DI")])
22095 ;; See logical MMX insns.
22096 (define_insn "mmx_lshrdi3"
22097 [(set (match_operand:DI 0 "register_operand" "=y")
22099 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
22100 (match_operand:DI 2 "nonmemory_operand" "yi"))]
22103 "psrlq\t{%2, %0|%0, %2}"
22104 [(set_attr "type" "mmxshft")
22105 (set_attr "mode" "DI")])
22107 (define_insn "ashlv4hi3"
22108 [(set (match_operand:V4HI 0 "register_operand" "=y")
22109 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
22110 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22112 "psllw\t{%2, %0|%0, %2}"
22113 [(set_attr "type" "mmxshft")
22114 (set_attr "mode" "DI")])
22116 (define_insn "ashlv2si3"
22117 [(set (match_operand:V2SI 0 "register_operand" "=y")
22118 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
22119 (match_operand:DI 2 "nonmemory_operand" "yi")))]
22121 "pslld\t{%2, %0|%0, %2}"
22122 [(set_attr "type" "mmxshft")
22123 (set_attr "mode" "DI")])
22125 ;; See logical MMX insns.
22126 (define_insn "mmx_ashldi3"
22127 [(set (match_operand:DI 0 "register_operand" "=y")
22129 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
22130 (match_operand:DI 2 "nonmemory_operand" "yi"))]
22133 "psllq\t{%2, %0|%0, %2}"
22134 [(set_attr "type" "mmxshft")
22135 (set_attr "mode" "DI")])
22138 ;; MMX pack/unpack insns.
22140 (define_insn "mmx_packsswb"
22141 [(set (match_operand:V8QI 0 "register_operand" "=y")
22143 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
22144 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
22146 "packsswb\t{%2, %0|%0, %2}"
22147 [(set_attr "type" "mmxshft")
22148 (set_attr "mode" "DI")])
22150 (define_insn "mmx_packssdw"
22151 [(set (match_operand:V4HI 0 "register_operand" "=y")
22153 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
22154 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
22156 "packssdw\t{%2, %0|%0, %2}"
22157 [(set_attr "type" "mmxshft")
22158 (set_attr "mode" "DI")])
22160 (define_insn "mmx_packuswb"
22161 [(set (match_operand:V8QI 0 "register_operand" "=y")
22163 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
22164 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
22166 "packuswb\t{%2, %0|%0, %2}"
22167 [(set_attr "type" "mmxshft")
22168 (set_attr "mode" "DI")])
22170 (define_insn "mmx_punpckhbw"
22171 [(set (match_operand:V8QI 0 "register_operand" "=y")
22173 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
22174 (parallel [(const_int 4)
22182 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
22183 (parallel [(const_int 0)
22193 "punpckhbw\t{%2, %0|%0, %2}"
22194 [(set_attr "type" "mmxcvt")
22195 (set_attr "mode" "DI")])
22197 (define_insn "mmx_punpckhwd"
22198 [(set (match_operand:V4HI 0 "register_operand" "=y")
22200 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
22201 (parallel [(const_int 0)
22205 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
22206 (parallel [(const_int 2)
22212 "punpckhwd\t{%2, %0|%0, %2}"
22213 [(set_attr "type" "mmxcvt")
22214 (set_attr "mode" "DI")])
22216 (define_insn "mmx_punpckhdq"
22217 [(set (match_operand:V2SI 0 "register_operand" "=y")
22219 (match_operand:V2SI 1 "register_operand" "0")
22220 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
22221 (parallel [(const_int 1)
22225 "punpckhdq\t{%2, %0|%0, %2}"
22226 [(set_attr "type" "mmxcvt")
22227 (set_attr "mode" "DI")])
22229 (define_insn "mmx_punpcklbw"
22230 [(set (match_operand:V8QI 0 "register_operand" "=y")
22232 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
22233 (parallel [(const_int 0)
22241 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
22242 (parallel [(const_int 4)
22252 "punpcklbw\t{%2, %0|%0, %2}"
22253 [(set_attr "type" "mmxcvt")
22254 (set_attr "mode" "DI")])
22256 (define_insn "mmx_punpcklwd"
22257 [(set (match_operand:V4HI 0 "register_operand" "=y")
22259 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
22260 (parallel [(const_int 2)
22264 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
22265 (parallel [(const_int 0)
22271 "punpcklwd\t{%2, %0|%0, %2}"
22272 [(set_attr "type" "mmxcvt")
22273 (set_attr "mode" "DI")])
22275 (define_insn "mmx_punpckldq"
22276 [(set (match_operand:V2SI 0 "register_operand" "=y")
22278 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
22279 (parallel [(const_int 1)
22281 (match_operand:V2SI 2 "register_operand" "y")
22284 "punpckldq\t{%2, %0|%0, %2}"
22285 [(set_attr "type" "mmxcvt")
22286 (set_attr "mode" "DI")])
22289 ;; Miscellaneous stuff
22291 (define_insn "emms"
22292 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
22293 (clobber (reg:XF 8))
22294 (clobber (reg:XF 9))
22295 (clobber (reg:XF 10))
22296 (clobber (reg:XF 11))
22297 (clobber (reg:XF 12))
22298 (clobber (reg:XF 13))
22299 (clobber (reg:XF 14))
22300 (clobber (reg:XF 15))
22301 (clobber (reg:DI 29))
22302 (clobber (reg:DI 30))
22303 (clobber (reg:DI 31))
22304 (clobber (reg:DI 32))
22305 (clobber (reg:DI 33))
22306 (clobber (reg:DI 34))
22307 (clobber (reg:DI 35))
22308 (clobber (reg:DI 36))]
22311 [(set_attr "type" "mmx")
22312 (set_attr "memory" "unknown")])
22314 (define_insn "ldmxcsr"
22315 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
22319 [(set_attr "type" "sse")
22320 (set_attr "memory" "load")])
22322 (define_insn "stmxcsr"
22323 [(set (match_operand:SI 0 "memory_operand" "=m")
22324 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
22327 [(set_attr "type" "sse")
22328 (set_attr "memory" "store")])
22330 (define_expand "sfence"
22331 [(set (match_dup 0)
22332 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
22333 "TARGET_SSE || TARGET_3DNOW_A"
22335 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22336 MEM_VOLATILE_P (operands[0]) = 1;
22339 (define_insn "*sfence_insn"
22340 [(set (match_operand:BLK 0 "" "")
22341 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
22342 "TARGET_SSE || TARGET_3DNOW_A"
22344 [(set_attr "type" "sse")
22345 (set_attr "memory" "unknown")])
22347 (define_expand "sse_prologue_save"
22348 [(parallel [(set (match_operand:BLK 0 "" "")
22349 (unspec:BLK [(reg:DI 21)
22356 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
22357 (use (match_operand:DI 1 "register_operand" ""))
22358 (use (match_operand:DI 2 "immediate_operand" ""))
22359 (use (label_ref:DI (match_operand 3 "" "")))])]
22363 (define_insn "*sse_prologue_save_insn"
22364 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
22365 (match_operand:DI 4 "const_int_operand" "n")))
22366 (unspec:BLK [(reg:DI 21)
22373 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
22374 (use (match_operand:DI 1 "register_operand" "r"))
22375 (use (match_operand:DI 2 "const_int_operand" "i"))
22376 (use (label_ref:DI (match_operand 3 "" "X")))]
22378 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
22379 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
22383 operands[0] = gen_rtx_MEM (Pmode,
22384 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
22385 output_asm_insn (\"jmp\\t%A1\", operands);
22386 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
22388 operands[4] = adjust_address (operands[0], DImode, i*16);
22389 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
22390 PUT_MODE (operands[4], TImode);
22391 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
22392 output_asm_insn (\"rex\", operands);
22393 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
22395 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
22396 CODE_LABEL_NUMBER (operands[3]));
22400 [(set_attr "type" "other")
22401 (set_attr "length_immediate" "0")
22402 (set_attr "length_address" "0")
22403 (set_attr "length" "135")
22404 (set_attr "memory" "store")
22405 (set_attr "modrm" "0")
22406 (set_attr "mode" "DI")])
22408 ;; 3Dnow! instructions
22410 (define_insn "addv2sf3"
22411 [(set (match_operand:V2SF 0 "register_operand" "=y")
22412 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
22413 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22415 "pfadd\\t{%2, %0|%0, %2}"
22416 [(set_attr "type" "mmxadd")
22417 (set_attr "mode" "V2SF")])
22419 (define_insn "subv2sf3"
22420 [(set (match_operand:V2SF 0 "register_operand" "=y")
22421 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
22422 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22424 "pfsub\\t{%2, %0|%0, %2}"
22425 [(set_attr "type" "mmxadd")
22426 (set_attr "mode" "V2SF")])
22428 (define_insn "subrv2sf3"
22429 [(set (match_operand:V2SF 0 "register_operand" "=y")
22430 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
22431 (match_operand:V2SF 1 "register_operand" "0")))]
22433 "pfsubr\\t{%2, %0|%0, %2}"
22434 [(set_attr "type" "mmxadd")
22435 (set_attr "mode" "V2SF")])
22437 (define_insn "gtv2sf3"
22438 [(set (match_operand:V2SI 0 "register_operand" "=y")
22439 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
22440 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22442 "pfcmpgt\\t{%2, %0|%0, %2}"
22443 [(set_attr "type" "mmxcmp")
22444 (set_attr "mode" "V2SF")])
22446 (define_insn "gev2sf3"
22447 [(set (match_operand:V2SI 0 "register_operand" "=y")
22448 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
22449 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22451 "pfcmpge\\t{%2, %0|%0, %2}"
22452 [(set_attr "type" "mmxcmp")
22453 (set_attr "mode" "V2SF")])
22455 (define_insn "eqv2sf3"
22456 [(set (match_operand:V2SI 0 "register_operand" "=y")
22457 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
22458 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22460 "pfcmpeq\\t{%2, %0|%0, %2}"
22461 [(set_attr "type" "mmxcmp")
22462 (set_attr "mode" "V2SF")])
22464 (define_insn "pfmaxv2sf3"
22465 [(set (match_operand:V2SF 0 "register_operand" "=y")
22466 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
22467 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22469 "pfmax\\t{%2, %0|%0, %2}"
22470 [(set_attr "type" "mmxadd")
22471 (set_attr "mode" "V2SF")])
22473 (define_insn "pfminv2sf3"
22474 [(set (match_operand:V2SF 0 "register_operand" "=y")
22475 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
22476 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22478 "pfmin\\t{%2, %0|%0, %2}"
22479 [(set_attr "type" "mmxadd")
22480 (set_attr "mode" "V2SF")])
22482 (define_insn "mulv2sf3"
22483 [(set (match_operand:V2SF 0 "register_operand" "=y")
22484 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
22485 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22487 "pfmul\\t{%2, %0|%0, %2}"
22488 [(set_attr "type" "mmxmul")
22489 (set_attr "mode" "V2SF")])
22491 (define_insn "femms"
22492 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
22493 (clobber (reg:XF 8))
22494 (clobber (reg:XF 9))
22495 (clobber (reg:XF 10))
22496 (clobber (reg:XF 11))
22497 (clobber (reg:XF 12))
22498 (clobber (reg:XF 13))
22499 (clobber (reg:XF 14))
22500 (clobber (reg:XF 15))
22501 (clobber (reg:DI 29))
22502 (clobber (reg:DI 30))
22503 (clobber (reg:DI 31))
22504 (clobber (reg:DI 32))
22505 (clobber (reg:DI 33))
22506 (clobber (reg:DI 34))
22507 (clobber (reg:DI 35))
22508 (clobber (reg:DI 36))]
22511 [(set_attr "type" "mmx")
22512 (set_attr "memory" "none")])
22514 (define_insn "pf2id"
22515 [(set (match_operand:V2SI 0 "register_operand" "=y")
22516 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
22518 "pf2id\\t{%1, %0|%0, %1}"
22519 [(set_attr "type" "mmxcvt")
22520 (set_attr "mode" "V2SF")])
22522 (define_insn "pf2iw"
22523 [(set (match_operand:V2SI 0 "register_operand" "=y")
22526 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
22528 "pf2iw\\t{%1, %0|%0, %1}"
22529 [(set_attr "type" "mmxcvt")
22530 (set_attr "mode" "V2SF")])
22532 (define_insn "pfacc"
22533 [(set (match_operand:V2SF 0 "register_operand" "=y")
22536 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22537 (parallel [(const_int 0)]))
22538 (vec_select:SF (match_dup 1)
22539 (parallel [(const_int 1)])))
22541 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22542 (parallel [(const_int 0)]))
22543 (vec_select:SF (match_dup 2)
22544 (parallel [(const_int 1)])))))]
22546 "pfacc\\t{%2, %0|%0, %2}"
22547 [(set_attr "type" "mmxadd")
22548 (set_attr "mode" "V2SF")])
22550 (define_insn "pfnacc"
22551 [(set (match_operand:V2SF 0 "register_operand" "=y")
22554 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22555 (parallel [(const_int 0)]))
22556 (vec_select:SF (match_dup 1)
22557 (parallel [(const_int 1)])))
22559 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22560 (parallel [(const_int 0)]))
22561 (vec_select:SF (match_dup 2)
22562 (parallel [(const_int 1)])))))]
22564 "pfnacc\\t{%2, %0|%0, %2}"
22565 [(set_attr "type" "mmxadd")
22566 (set_attr "mode" "V2SF")])
22568 (define_insn "pfpnacc"
22569 [(set (match_operand:V2SF 0 "register_operand" "=y")
22572 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22573 (parallel [(const_int 0)]))
22574 (vec_select:SF (match_dup 1)
22575 (parallel [(const_int 1)])))
22577 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22578 (parallel [(const_int 0)]))
22579 (vec_select:SF (match_dup 2)
22580 (parallel [(const_int 1)])))))]
22582 "pfpnacc\\t{%2, %0|%0, %2}"
22583 [(set_attr "type" "mmxadd")
22584 (set_attr "mode" "V2SF")])
22586 (define_insn "pi2fw"
22587 [(set (match_operand:V2SF 0 "register_operand" "=y")
22592 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
22593 (parallel [(const_int 0)]))))
22596 (vec_select:SI (match_dup 1)
22597 (parallel [(const_int 1)])))))))]
22599 "pi2fw\\t{%1, %0|%0, %1}"
22600 [(set_attr "type" "mmxcvt")
22601 (set_attr "mode" "V2SF")])
22603 (define_insn "floatv2si2"
22604 [(set (match_operand:V2SF 0 "register_operand" "=y")
22605 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22607 "pi2fd\\t{%1, %0|%0, %1}"
22608 [(set_attr "type" "mmxcvt")
22609 (set_attr "mode" "V2SF")])
22611 ;; This insn is identical to pavgb in operation, but the opcode is
22612 ;; different. To avoid accidentally matching pavgb, use an unspec.
22614 (define_insn "pavgusb"
22615 [(set (match_operand:V8QI 0 "register_operand" "=y")
22617 [(match_operand:V8QI 1 "register_operand" "0")
22618 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
22621 "pavgusb\\t{%2, %0|%0, %2}"
22622 [(set_attr "type" "mmxshft")
22623 (set_attr "mode" "TI")])
22625 ;; 3DNow reciprocal and sqrt
22627 (define_insn "pfrcpv2sf2"
22628 [(set (match_operand:V2SF 0 "register_operand" "=y")
22629 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
22632 "pfrcp\\t{%1, %0|%0, %1}"
22633 [(set_attr "type" "mmx")
22634 (set_attr "mode" "TI")])
22636 (define_insn "pfrcpit1v2sf3"
22637 [(set (match_operand:V2SF 0 "register_operand" "=y")
22638 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22639 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22642 "pfrcpit1\\t{%2, %0|%0, %2}"
22643 [(set_attr "type" "mmx")
22644 (set_attr "mode" "TI")])
22646 (define_insn "pfrcpit2v2sf3"
22647 [(set (match_operand:V2SF 0 "register_operand" "=y")
22648 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22649 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22652 "pfrcpit2\\t{%2, %0|%0, %2}"
22653 [(set_attr "type" "mmx")
22654 (set_attr "mode" "TI")])
22656 (define_insn "pfrsqrtv2sf2"
22657 [(set (match_operand:V2SF 0 "register_operand" "=y")
22658 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
22661 "pfrsqrt\\t{%1, %0|%0, %1}"
22662 [(set_attr "type" "mmx")
22663 (set_attr "mode" "TI")])
22665 (define_insn "pfrsqit1v2sf3"
22666 [(set (match_operand:V2SF 0 "register_operand" "=y")
22667 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22668 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22671 "pfrsqit1\\t{%2, %0|%0, %2}"
22672 [(set_attr "type" "mmx")
22673 (set_attr "mode" "TI")])
22675 (define_insn "pmulhrwv4hi3"
22676 [(set (match_operand:V4HI 0 "register_operand" "=y")
22682 (match_operand:V4HI 1 "register_operand" "0"))
22684 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
22685 (const_vector:V4SI [(const_int 32768)
22688 (const_int 32768)]))
22691 "pmulhrw\\t{%2, %0|%0, %2}"
22692 [(set_attr "type" "mmxmul")
22693 (set_attr "mode" "TI")])
22695 (define_insn "pswapdv2si2"
22696 [(set (match_operand:V2SI 0 "register_operand" "=y")
22697 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
22698 (parallel [(const_int 1) (const_int 0)])))]
22700 "pswapd\\t{%1, %0|%0, %1}"
22701 [(set_attr "type" "mmxcvt")
22702 (set_attr "mode" "TI")])
22704 (define_insn "pswapdv2sf2"
22705 [(set (match_operand:V2SF 0 "register_operand" "=y")
22706 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
22707 (parallel [(const_int 1) (const_int 0)])))]
22709 "pswapd\\t{%1, %0|%0, %1}"
22710 [(set_attr "type" "mmxcvt")
22711 (set_attr "mode" "TI")])
22713 (define_expand "prefetch"
22714 [(prefetch (match_operand 0 "address_operand" "")
22715 (match_operand:SI 1 "const_int_operand" "")
22716 (match_operand:SI 2 "const_int_operand" ""))]
22717 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
22719 int rw = INTVAL (operands[1]);
22720 int locality = INTVAL (operands[2]);
22722 if (rw != 0 && rw != 1)
22724 if (locality < 0 || locality > 3)
22726 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
22729 /* Use 3dNOW prefetch in case we are asking for write prefetch not
22730 suported by SSE counterpart or the SSE prefetch is not available
22731 (K6 machines). Otherwise use SSE prefetch as it allows specifying
22733 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
22734 operands[2] = GEN_INT (3);
22736 operands[1] = const0_rtx;
22739 (define_insn "*prefetch_sse"
22740 [(prefetch (match_operand:SI 0 "address_operand" "p")
22742 (match_operand:SI 1 "const_int_operand" ""))]
22743 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
22745 static const char * const patterns[4] = {
22746 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
22749 int locality = INTVAL (operands[1]);
22750 if (locality < 0 || locality > 3)
22753 return patterns[locality];
22755 [(set_attr "type" "sse")
22756 (set_attr "memory" "none")])
22758 (define_insn "*prefetch_sse_rex"
22759 [(prefetch (match_operand:DI 0 "address_operand" "p")
22761 (match_operand:SI 1 "const_int_operand" ""))]
22762 "TARGET_PREFETCH_SSE && TARGET_64BIT"
22764 static const char * const patterns[4] = {
22765 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
22768 int locality = INTVAL (operands[1]);
22769 if (locality < 0 || locality > 3)
22772 return patterns[locality];
22774 [(set_attr "type" "sse")
22775 (set_attr "memory" "none")])
22777 (define_insn "*prefetch_3dnow"
22778 [(prefetch (match_operand:SI 0 "address_operand" "p")
22779 (match_operand:SI 1 "const_int_operand" "n")
22781 "TARGET_3DNOW && !TARGET_64BIT"
22783 if (INTVAL (operands[1]) == 0)
22784 return "prefetch\t%a0";
22786 return "prefetchw\t%a0";
22788 [(set_attr "type" "mmx")
22789 (set_attr "memory" "none")])
22791 (define_insn "*prefetch_3dnow_rex"
22792 [(prefetch (match_operand:DI 0 "address_operand" "p")
22793 (match_operand:SI 1 "const_int_operand" "n")
22795 "TARGET_3DNOW && TARGET_64BIT"
22797 if (INTVAL (operands[1]) == 0)
22798 return "prefetch\t%a0";
22800 return "prefetchw\t%a0";
22802 [(set_attr "type" "mmx")
22803 (set_attr "memory" "none")])
22807 (define_insn "addv2df3"
22808 [(set (match_operand:V2DF 0 "register_operand" "=x")
22809 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22810 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22812 "addpd\t{%2, %0|%0, %2}"
22813 [(set_attr "type" "sseadd")
22814 (set_attr "mode" "V2DF")])
22816 (define_insn "vmaddv2df3"
22817 [(set (match_operand:V2DF 0 "register_operand" "=x")
22818 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22819 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22823 "addsd\t{%2, %0|%0, %2}"
22824 [(set_attr "type" "sseadd")
22825 (set_attr "mode" "DF")])
22827 (define_insn "subv2df3"
22828 [(set (match_operand:V2DF 0 "register_operand" "=x")
22829 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22830 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22832 "subpd\t{%2, %0|%0, %2}"
22833 [(set_attr "type" "sseadd")
22834 (set_attr "mode" "V2DF")])
22836 (define_insn "vmsubv2df3"
22837 [(set (match_operand:V2DF 0 "register_operand" "=x")
22838 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22839 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22843 "subsd\t{%2, %0|%0, %2}"
22844 [(set_attr "type" "sseadd")
22845 (set_attr "mode" "DF")])
22847 (define_insn "mulv2df3"
22848 [(set (match_operand:V2DF 0 "register_operand" "=x")
22849 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
22850 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22852 "mulpd\t{%2, %0|%0, %2}"
22853 [(set_attr "type" "ssemul")
22854 (set_attr "mode" "V2DF")])
22856 (define_insn "vmmulv2df3"
22857 [(set (match_operand:V2DF 0 "register_operand" "=x")
22858 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
22859 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22863 "mulsd\t{%2, %0|%0, %2}"
22864 [(set_attr "type" "ssemul")
22865 (set_attr "mode" "DF")])
22867 (define_insn "divv2df3"
22868 [(set (match_operand:V2DF 0 "register_operand" "=x")
22869 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22870 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22872 "divpd\t{%2, %0|%0, %2}"
22873 [(set_attr "type" "ssediv")
22874 (set_attr "mode" "V2DF")])
22876 (define_insn "vmdivv2df3"
22877 [(set (match_operand:V2DF 0 "register_operand" "=x")
22878 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22879 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22883 "divsd\t{%2, %0|%0, %2}"
22884 [(set_attr "type" "ssediv")
22885 (set_attr "mode" "DF")])
22889 (define_insn "smaxv2df3"
22890 [(set (match_operand:V2DF 0 "register_operand" "=x")
22891 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22892 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22894 "maxpd\t{%2, %0|%0, %2}"
22895 [(set_attr "type" "sseadd")
22896 (set_attr "mode" "V2DF")])
22898 (define_insn "vmsmaxv2df3"
22899 [(set (match_operand:V2DF 0 "register_operand" "=x")
22900 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22901 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22905 "maxsd\t{%2, %0|%0, %2}"
22906 [(set_attr "type" "sseadd")
22907 (set_attr "mode" "DF")])
22909 (define_insn "sminv2df3"
22910 [(set (match_operand:V2DF 0 "register_operand" "=x")
22911 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22912 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22914 "minpd\t{%2, %0|%0, %2}"
22915 [(set_attr "type" "sseadd")
22916 (set_attr "mode" "V2DF")])
22918 (define_insn "vmsminv2df3"
22919 [(set (match_operand:V2DF 0 "register_operand" "=x")
22920 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22921 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22925 "minsd\t{%2, %0|%0, %2}"
22926 [(set_attr "type" "sseadd")
22927 (set_attr "mode" "DF")])
22928 ;; SSE2 square root. There doesn't appear to be an extension for the
22929 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
22931 (define_insn "sqrtv2df2"
22932 [(set (match_operand:V2DF 0 "register_operand" "=x")
22933 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
22935 "sqrtpd\t{%1, %0|%0, %1}"
22936 [(set_attr "type" "sse")
22937 (set_attr "mode" "V2DF")])
22939 (define_insn "vmsqrtv2df2"
22940 [(set (match_operand:V2DF 0 "register_operand" "=x")
22941 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
22942 (match_operand:V2DF 2 "register_operand" "0")
22945 "sqrtsd\t{%1, %0|%0, %1}"
22946 [(set_attr "type" "sse")
22947 (set_attr "mode" "SF")])
22949 ;; SSE mask-generating compares
22951 (define_insn "maskcmpv2df3"
22952 [(set (match_operand:V2DI 0 "register_operand" "=x")
22953 (match_operator:V2DI 3 "sse_comparison_operator"
22954 [(match_operand:V2DF 1 "register_operand" "0")
22955 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
22957 "cmp%D3pd\t{%2, %0|%0, %2}"
22958 [(set_attr "type" "ssecmp")
22959 (set_attr "mode" "V2DF")])
22961 (define_insn "maskncmpv2df3"
22962 [(set (match_operand:V2DI 0 "register_operand" "=x")
22964 (match_operator:V2DI 3 "sse_comparison_operator"
22965 [(match_operand:V2DF 1 "register_operand" "0")
22966 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
22969 if (GET_CODE (operands[3]) == UNORDERED)
22970 return "cmpordps\t{%2, %0|%0, %2}";
22972 return "cmpn%D3pd\t{%2, %0|%0, %2}";
22974 [(set_attr "type" "ssecmp")
22975 (set_attr "mode" "V2DF")])
22977 (define_insn "vmmaskcmpv2df3"
22978 [(set (match_operand:V2DI 0 "register_operand" "=x")
22980 (match_operator:V2DI 3 "sse_comparison_operator"
22981 [(match_operand:V2DF 1 "register_operand" "0")
22982 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
22983 (subreg:V2DI (match_dup 1) 0)
22986 "cmp%D3sd\t{%2, %0|%0, %2}"
22987 [(set_attr "type" "ssecmp")
22988 (set_attr "mode" "DF")])
22990 (define_insn "vmmaskncmpv2df3"
22991 [(set (match_operand:V2DI 0 "register_operand" "=x")
22994 (match_operator:V2DI 3 "sse_comparison_operator"
22995 [(match_operand:V2DF 1 "register_operand" "0")
22996 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
22997 (subreg:V2DI (match_dup 1) 0)
23001 if (GET_CODE (operands[3]) == UNORDERED)
23002 return "cmpordsd\t{%2, %0|%0, %2}";
23004 return "cmpn%D3sd\t{%2, %0|%0, %2}";
23006 [(set_attr "type" "ssecmp")
23007 (set_attr "mode" "DF")])
23009 (define_insn "sse2_comi"
23010 [(set (reg:CCFP FLAGS_REG)
23011 (compare:CCFP (vec_select:DF
23012 (match_operand:V2DF 0 "register_operand" "x")
23013 (parallel [(const_int 0)]))
23015 (match_operand:V2DF 1 "register_operand" "x")
23016 (parallel [(const_int 0)]))))]
23018 "comisd\t{%1, %0|%0, %1}"
23019 [(set_attr "type" "ssecomi")
23020 (set_attr "mode" "DF")])
23022 (define_insn "sse2_ucomi"
23023 [(set (reg:CCFPU FLAGS_REG)
23024 (compare:CCFPU (vec_select:DF
23025 (match_operand:V2DF 0 "register_operand" "x")
23026 (parallel [(const_int 0)]))
23028 (match_operand:V2DF 1 "register_operand" "x")
23029 (parallel [(const_int 0)]))))]
23031 "ucomisd\t{%1, %0|%0, %1}"
23032 [(set_attr "type" "ssecomi")
23033 (set_attr "mode" "DF")])
23035 ;; SSE Strange Moves.
23037 (define_insn "sse2_movmskpd"
23038 [(set (match_operand:SI 0 "register_operand" "=r")
23039 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
23042 "movmskpd\t{%1, %0|%0, %1}"
23043 [(set_attr "type" "ssecvt")
23044 (set_attr "mode" "V2DF")])
23046 (define_insn "sse2_pmovmskb"
23047 [(set (match_operand:SI 0 "register_operand" "=r")
23048 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
23051 "pmovmskb\t{%1, %0|%0, %1}"
23052 [(set_attr "type" "ssecvt")
23053 (set_attr "mode" "V2DF")])
23055 (define_insn "sse2_maskmovdqu"
23056 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
23057 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
23058 (match_operand:V16QI 2 "register_operand" "x")]
23061 ;; @@@ check ordering of operands in intel/nonintel syntax
23062 "maskmovdqu\t{%2, %1|%1, %2}"
23063 [(set_attr "type" "ssecvt")
23064 (set_attr "mode" "TI")])
23066 (define_insn "sse2_maskmovdqu_rex64"
23067 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
23068 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
23069 (match_operand:V16QI 2 "register_operand" "x")]
23072 ;; @@@ check ordering of operands in intel/nonintel syntax
23073 "maskmovdqu\t{%2, %1|%1, %2}"
23074 [(set_attr "type" "ssecvt")
23075 (set_attr "mode" "TI")])
23077 (define_insn "sse2_movntv2df"
23078 [(set (match_operand:V2DF 0 "memory_operand" "=m")
23079 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
23082 "movntpd\t{%1, %0|%0, %1}"
23083 [(set_attr "type" "ssecvt")
23084 (set_attr "mode" "V2DF")])
23086 (define_insn "sse2_movntv2di"
23087 [(set (match_operand:V2DI 0 "memory_operand" "=m")
23088 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
23091 "movntdq\t{%1, %0|%0, %1}"
23092 [(set_attr "type" "ssecvt")
23093 (set_attr "mode" "TI")])
23095 (define_insn "sse2_movntsi"
23096 [(set (match_operand:SI 0 "memory_operand" "=m")
23097 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
23100 "movnti\t{%1, %0|%0, %1}"
23101 [(set_attr "type" "ssecvt")
23102 (set_attr "mode" "V2DF")])
23104 ;; SSE <-> integer/MMX conversions
23106 ;; Conversions between SI and SF
23108 (define_insn "cvtdq2ps"
23109 [(set (match_operand:V4SF 0 "register_operand" "=x")
23110 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
23112 "cvtdq2ps\t{%1, %0|%0, %1}"
23113 [(set_attr "type" "ssecvt")
23114 (set_attr "mode" "V2DF")])
23116 (define_insn "cvtps2dq"
23117 [(set (match_operand:V4SI 0 "register_operand" "=x")
23118 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
23120 "cvtps2dq\t{%1, %0|%0, %1}"
23121 [(set_attr "type" "ssecvt")
23122 (set_attr "mode" "TI")])
23124 (define_insn "cvttps2dq"
23125 [(set (match_operand:V4SI 0 "register_operand" "=x")
23126 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
23129 "cvttps2dq\t{%1, %0|%0, %1}"
23130 [(set_attr "type" "ssecvt")
23131 (set_attr "mode" "TI")])
23133 ;; Conversions between SI and DF
23135 (define_insn "cvtdq2pd"
23136 [(set (match_operand:V2DF 0 "register_operand" "=x")
23137 (float:V2DF (vec_select:V2SI
23138 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
23141 (const_int 1)]))))]
23143 "cvtdq2pd\t{%1, %0|%0, %1}"
23144 [(set_attr "type" "ssecvt")
23145 (set_attr "mode" "V2DF")])
23147 (define_insn "cvtpd2dq"
23148 [(set (match_operand:V4SI 0 "register_operand" "=x")
23150 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
23151 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
23153 "cvtpd2dq\t{%1, %0|%0, %1}"
23154 [(set_attr "type" "ssecvt")
23155 (set_attr "mode" "TI")])
23157 (define_insn "cvttpd2dq"
23158 [(set (match_operand:V4SI 0 "register_operand" "=x")
23160 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
23162 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
23164 "cvttpd2dq\t{%1, %0|%0, %1}"
23165 [(set_attr "type" "ssecvt")
23166 (set_attr "mode" "TI")])
23168 (define_insn "cvtpd2pi"
23169 [(set (match_operand:V2SI 0 "register_operand" "=y")
23170 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
23172 "cvtpd2pi\t{%1, %0|%0, %1}"
23173 [(set_attr "type" "ssecvt")
23174 (set_attr "mode" "TI")])
23176 (define_insn "cvttpd2pi"
23177 [(set (match_operand:V2SI 0 "register_operand" "=y")
23178 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
23181 "cvttpd2pi\t{%1, %0|%0, %1}"
23182 [(set_attr "type" "ssecvt")
23183 (set_attr "mode" "TI")])
23185 (define_insn "cvtpi2pd"
23186 [(set (match_operand:V2DF 0 "register_operand" "=x")
23187 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
23189 "cvtpi2pd\t{%1, %0|%0, %1}"
23190 [(set_attr "type" "ssecvt")
23191 (set_attr "mode" "TI")])
23193 ;; Conversions between SI and DF
23195 (define_insn "cvtsd2si"
23196 [(set (match_operand:SI 0 "register_operand" "=r,r")
23197 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
23198 (parallel [(const_int 0)]))))]
23200 "cvtsd2si\t{%1, %0|%0, %1}"
23201 [(set_attr "type" "sseicvt")
23202 (set_attr "athlon_decode" "double,vector")
23203 (set_attr "mode" "SI")])
23205 (define_insn "cvtsd2siq"
23206 [(set (match_operand:DI 0 "register_operand" "=r,r")
23207 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
23208 (parallel [(const_int 0)]))))]
23209 "TARGET_SSE2 && TARGET_64BIT"
23210 "cvtsd2siq\t{%1, %0|%0, %1}"
23211 [(set_attr "type" "sseicvt")
23212 (set_attr "athlon_decode" "double,vector")
23213 (set_attr "mode" "DI")])
23215 (define_insn "cvttsd2si"
23216 [(set (match_operand:SI 0 "register_operand" "=r,r")
23217 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
23218 (parallel [(const_int 0)]))] UNSPEC_FIX))]
23220 "cvttsd2si\t{%1, %0|%0, %1}"
23221 [(set_attr "type" "sseicvt")
23222 (set_attr "mode" "SI")
23223 (set_attr "athlon_decode" "double,vector")])
23225 (define_insn "cvttsd2siq"
23226 [(set (match_operand:DI 0 "register_operand" "=r,r")
23227 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
23228 (parallel [(const_int 0)]))] UNSPEC_FIX))]
23229 "TARGET_SSE2 && TARGET_64BIT"
23230 "cvttsd2siq\t{%1, %0|%0, %1}"
23231 [(set_attr "type" "sseicvt")
23232 (set_attr "mode" "DI")
23233 (set_attr "athlon_decode" "double,vector")])
23235 (define_insn "cvtsi2sd"
23236 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
23237 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
23238 (vec_duplicate:V2DF
23240 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
23243 "cvtsi2sd\t{%2, %0|%0, %2}"
23244 [(set_attr "type" "sseicvt")
23245 (set_attr "mode" "DF")
23246 (set_attr "athlon_decode" "double,direct")])
23248 (define_insn "cvtsi2sdq"
23249 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
23250 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
23251 (vec_duplicate:V2DF
23253 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
23255 "TARGET_SSE2 && TARGET_64BIT"
23256 "cvtsi2sdq\t{%2, %0|%0, %2}"
23257 [(set_attr "type" "sseicvt")
23258 (set_attr "mode" "DF")
23259 (set_attr "athlon_decode" "double,direct")])
23261 ;; Conversions between SF and DF
23263 (define_insn "cvtsd2ss"
23264 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
23265 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
23266 (vec_duplicate:V4SF
23267 (float_truncate:V2SF
23268 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
23271 "cvtsd2ss\t{%2, %0|%0, %2}"
23272 [(set_attr "type" "ssecvt")
23273 (set_attr "athlon_decode" "vector,double")
23274 (set_attr "mode" "SF")])
23276 (define_insn "cvtss2sd"
23277 [(set (match_operand:V2DF 0 "register_operand" "=x")
23278 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
23281 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
23282 (parallel [(const_int 0)
23286 "cvtss2sd\t{%2, %0|%0, %2}"
23287 [(set_attr "type" "ssecvt")
23288 (set_attr "mode" "DF")])
23290 (define_insn "cvtpd2ps"
23291 [(set (match_operand:V4SF 0 "register_operand" "=x")
23294 (subreg:V2SI (float_truncate:V2SF
23295 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
23296 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
23298 "cvtpd2ps\t{%1, %0|%0, %1}"
23299 [(set_attr "type" "ssecvt")
23300 (set_attr "mode" "V4SF")])
23302 (define_insn "cvtps2pd"
23303 [(set (match_operand:V2DF 0 "register_operand" "=x")
23305 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
23306 (parallel [(const_int 0)
23307 (const_int 1)]))))]
23309 "cvtps2pd\t{%1, %0|%0, %1}"
23310 [(set_attr "type" "ssecvt")
23311 (set_attr "mode" "V2DF")])
23313 ;; SSE2 variants of MMX insns
23317 (define_insn "addv16qi3"
23318 [(set (match_operand:V16QI 0 "register_operand" "=x")
23319 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23320 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23322 "paddb\t{%2, %0|%0, %2}"
23323 [(set_attr "type" "sseiadd")
23324 (set_attr "mode" "TI")])
23326 (define_insn "addv8hi3"
23327 [(set (match_operand:V8HI 0 "register_operand" "=x")
23328 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23329 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23331 "paddw\t{%2, %0|%0, %2}"
23332 [(set_attr "type" "sseiadd")
23333 (set_attr "mode" "TI")])
23335 (define_insn "addv4si3"
23336 [(set (match_operand:V4SI 0 "register_operand" "=x")
23337 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
23338 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23340 "paddd\t{%2, %0|%0, %2}"
23341 [(set_attr "type" "sseiadd")
23342 (set_attr "mode" "TI")])
23344 (define_insn "addv2di3"
23345 [(set (match_operand:V2DI 0 "register_operand" "=x")
23346 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
23347 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
23349 "paddq\t{%2, %0|%0, %2}"
23350 [(set_attr "type" "sseiadd")
23351 (set_attr "mode" "TI")])
23353 (define_insn "ssaddv16qi3"
23354 [(set (match_operand:V16QI 0 "register_operand" "=x")
23355 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23356 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23358 "paddsb\t{%2, %0|%0, %2}"
23359 [(set_attr "type" "sseiadd")
23360 (set_attr "mode" "TI")])
23362 (define_insn "ssaddv8hi3"
23363 [(set (match_operand:V8HI 0 "register_operand" "=x")
23364 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23365 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23367 "paddsw\t{%2, %0|%0, %2}"
23368 [(set_attr "type" "sseiadd")
23369 (set_attr "mode" "TI")])
23371 (define_insn "usaddv16qi3"
23372 [(set (match_operand:V16QI 0 "register_operand" "=x")
23373 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23374 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23376 "paddusb\t{%2, %0|%0, %2}"
23377 [(set_attr "type" "sseiadd")
23378 (set_attr "mode" "TI")])
23380 (define_insn "usaddv8hi3"
23381 [(set (match_operand:V8HI 0 "register_operand" "=x")
23382 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23383 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23385 "paddusw\t{%2, %0|%0, %2}"
23386 [(set_attr "type" "sseiadd")
23387 (set_attr "mode" "TI")])
23389 (define_insn "subv16qi3"
23390 [(set (match_operand:V16QI 0 "register_operand" "=x")
23391 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23392 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23394 "psubb\t{%2, %0|%0, %2}"
23395 [(set_attr "type" "sseiadd")
23396 (set_attr "mode" "TI")])
23398 (define_insn "subv8hi3"
23399 [(set (match_operand:V8HI 0 "register_operand" "=x")
23400 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23401 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23403 "psubw\t{%2, %0|%0, %2}"
23404 [(set_attr "type" "sseiadd")
23405 (set_attr "mode" "TI")])
23407 (define_insn "subv4si3"
23408 [(set (match_operand:V4SI 0 "register_operand" "=x")
23409 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
23410 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23412 "psubd\t{%2, %0|%0, %2}"
23413 [(set_attr "type" "sseiadd")
23414 (set_attr "mode" "TI")])
23416 (define_insn "subv2di3"
23417 [(set (match_operand:V2DI 0 "register_operand" "=x")
23418 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
23419 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
23421 "psubq\t{%2, %0|%0, %2}"
23422 [(set_attr "type" "sseiadd")
23423 (set_attr "mode" "TI")])
23425 (define_insn "sssubv16qi3"
23426 [(set (match_operand:V16QI 0 "register_operand" "=x")
23427 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23428 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23430 "psubsb\t{%2, %0|%0, %2}"
23431 [(set_attr "type" "sseiadd")
23432 (set_attr "mode" "TI")])
23434 (define_insn "sssubv8hi3"
23435 [(set (match_operand:V8HI 0 "register_operand" "=x")
23436 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23437 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23439 "psubsw\t{%2, %0|%0, %2}"
23440 [(set_attr "type" "sseiadd")
23441 (set_attr "mode" "TI")])
23443 (define_insn "ussubv16qi3"
23444 [(set (match_operand:V16QI 0 "register_operand" "=x")
23445 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23446 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23448 "psubusb\t{%2, %0|%0, %2}"
23449 [(set_attr "type" "sseiadd")
23450 (set_attr "mode" "TI")])
23452 (define_insn "ussubv8hi3"
23453 [(set (match_operand:V8HI 0 "register_operand" "=x")
23454 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23455 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23457 "psubusw\t{%2, %0|%0, %2}"
23458 [(set_attr "type" "sseiadd")
23459 (set_attr "mode" "TI")])
23461 (define_insn "mulv8hi3"
23462 [(set (match_operand:V8HI 0 "register_operand" "=x")
23463 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
23464 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23466 "pmullw\t{%2, %0|%0, %2}"
23467 [(set_attr "type" "sseimul")
23468 (set_attr "mode" "TI")])
23470 (define_insn "smulv8hi3_highpart"
23471 [(set (match_operand:V8HI 0 "register_operand" "=x")
23474 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
23475 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
23478 "pmulhw\t{%2, %0|%0, %2}"
23479 [(set_attr "type" "sseimul")
23480 (set_attr "mode" "TI")])
23482 (define_insn "umulv8hi3_highpart"
23483 [(set (match_operand:V8HI 0 "register_operand" "=x")
23486 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
23487 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
23490 "pmulhuw\t{%2, %0|%0, %2}"
23491 [(set_attr "type" "sseimul")
23492 (set_attr "mode" "TI")])
23494 (define_insn "sse2_umulsidi3"
23495 [(set (match_operand:DI 0 "register_operand" "=y")
23496 (mult:DI (zero_extend:DI (vec_select:SI
23497 (match_operand:V2SI 1 "register_operand" "0")
23498 (parallel [(const_int 0)])))
23499 (zero_extend:DI (vec_select:SI
23500 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
23501 (parallel [(const_int 0)])))))]
23503 "pmuludq\t{%2, %0|%0, %2}"
23504 [(set_attr "type" "mmxmul")
23505 (set_attr "mode" "DI")])
23507 (define_insn "sse2_umulv2siv2di3"
23508 [(set (match_operand:V2DI 0 "register_operand" "=x")
23509 (mult:V2DI (zero_extend:V2DI
23511 (match_operand:V4SI 1 "register_operand" "0")
23512 (parallel [(const_int 0) (const_int 2)])))
23515 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
23516 (parallel [(const_int 0) (const_int 2)])))))]
23518 "pmuludq\t{%2, %0|%0, %2}"
23519 [(set_attr "type" "sseimul")
23520 (set_attr "mode" "TI")])
23522 (define_insn "sse2_pmaddwd"
23523 [(set (match_operand:V4SI 0 "register_operand" "=x")
23526 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
23527 (parallel [(const_int 0)
23531 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
23532 (parallel [(const_int 0)
23537 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
23538 (parallel [(const_int 1)
23542 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
23543 (parallel [(const_int 1)
23546 (const_int 7)]))))))]
23548 "pmaddwd\t{%2, %0|%0, %2}"
23549 [(set_attr "type" "sseiadd")
23550 (set_attr "mode" "TI")])
23552 ;; Same as pxor, but don't show input operands so that we don't think
23554 (define_insn "sse2_clrti"
23555 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
23558 if (get_attr_mode (insn) == MODE_TI)
23559 return "pxor\t%0, %0";
23561 return "xorps\t%0, %0";
23563 [(set_attr "type" "ssemov")
23564 (set_attr "memory" "none")
23567 (ne (symbol_ref "optimize_size")
23569 (const_string "V4SF")
23570 (const_string "TI")))])
23572 ;; MMX unsigned averages/sum of absolute differences
23574 (define_insn "sse2_uavgv16qi3"
23575 [(set (match_operand:V16QI 0 "register_operand" "=x")
23577 (plus:V16QI (plus:V16QI
23578 (match_operand:V16QI 1 "register_operand" "0")
23579 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
23580 (const_vector:V16QI [(const_int 1) (const_int 1)
23581 (const_int 1) (const_int 1)
23582 (const_int 1) (const_int 1)
23583 (const_int 1) (const_int 1)
23584 (const_int 1) (const_int 1)
23585 (const_int 1) (const_int 1)
23586 (const_int 1) (const_int 1)
23587 (const_int 1) (const_int 1)]))
23590 "pavgb\t{%2, %0|%0, %2}"
23591 [(set_attr "type" "sseiadd")
23592 (set_attr "mode" "TI")])
23594 (define_insn "sse2_uavgv8hi3"
23595 [(set (match_operand:V8HI 0 "register_operand" "=x")
23597 (plus:V8HI (plus:V8HI
23598 (match_operand:V8HI 1 "register_operand" "0")
23599 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
23600 (const_vector:V8HI [(const_int 1) (const_int 1)
23601 (const_int 1) (const_int 1)
23602 (const_int 1) (const_int 1)
23603 (const_int 1) (const_int 1)]))
23606 "pavgw\t{%2, %0|%0, %2}"
23607 [(set_attr "type" "sseiadd")
23608 (set_attr "mode" "TI")])
23610 ;; @@@ this isn't the right representation.
23611 (define_insn "sse2_psadbw"
23612 [(set (match_operand:V2DI 0 "register_operand" "=x")
23613 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
23614 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
23617 "psadbw\t{%2, %0|%0, %2}"
23618 [(set_attr "type" "sseiadd")
23619 (set_attr "mode" "TI")])
23622 ;; MMX insert/extract/shuffle
23624 (define_insn "sse2_pinsrw"
23625 [(set (match_operand:V8HI 0 "register_operand" "=x")
23626 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
23627 (vec_duplicate:V8HI
23629 (match_operand:SI 2 "nonimmediate_operand" "rm")))
23630 (match_operand:SI 3 "const_0_to_255_operand" "N")))]
23632 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
23633 [(set_attr "type" "ssecvt")
23634 (set_attr "mode" "TI")])
23636 (define_insn "sse2_pextrw"
23637 [(set (match_operand:SI 0 "register_operand" "=r")
23639 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
23641 [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
23643 "pextrw\t{%2, %1, %0|%0, %1, %2}"
23644 [(set_attr "type" "ssecvt")
23645 (set_attr "mode" "TI")])
23647 (define_insn "sse2_pshufd"
23648 [(set (match_operand:V4SI 0 "register_operand" "=x")
23649 (unspec:V4SI [(match_operand:V4SI 1 "nonimmediate_operand" "xm")
23650 (match_operand:SI 2 "immediate_operand" "i")]
23653 "pshufd\t{%2, %1, %0|%0, %1, %2}"
23654 [(set_attr "type" "ssecvt")
23655 (set_attr "mode" "TI")])
23657 (define_insn "sse2_pshuflw"
23658 [(set (match_operand:V8HI 0 "register_operand" "=x")
23659 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
23660 (match_operand:SI 2 "immediate_operand" "i")]
23663 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
23664 [(set_attr "type" "ssecvt")
23665 (set_attr "mode" "TI")])
23667 (define_insn "sse2_pshufhw"
23668 [(set (match_operand:V8HI 0 "register_operand" "=x")
23669 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
23670 (match_operand:SI 2 "immediate_operand" "i")]
23673 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
23674 [(set_attr "type" "ssecvt")
23675 (set_attr "mode" "TI")])
23677 ;; MMX mask-generating comparisons
23679 (define_insn "eqv16qi3"
23680 [(set (match_operand:V16QI 0 "register_operand" "=x")
23681 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
23682 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23684 "pcmpeqb\t{%2, %0|%0, %2}"
23685 [(set_attr "type" "ssecmp")
23686 (set_attr "mode" "TI")])
23688 (define_insn "eqv8hi3"
23689 [(set (match_operand:V8HI 0 "register_operand" "=x")
23690 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
23691 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23693 "pcmpeqw\t{%2, %0|%0, %2}"
23694 [(set_attr "type" "ssecmp")
23695 (set_attr "mode" "TI")])
23697 (define_insn "eqv4si3"
23698 [(set (match_operand:V4SI 0 "register_operand" "=x")
23699 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
23700 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23702 "pcmpeqd\t{%2, %0|%0, %2}"
23703 [(set_attr "type" "ssecmp")
23704 (set_attr "mode" "TI")])
23706 (define_insn "gtv16qi3"
23707 [(set (match_operand:V16QI 0 "register_operand" "=x")
23708 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
23709 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23711 "pcmpgtb\t{%2, %0|%0, %2}"
23712 [(set_attr "type" "ssecmp")
23713 (set_attr "mode" "TI")])
23715 (define_insn "gtv8hi3"
23716 [(set (match_operand:V8HI 0 "register_operand" "=x")
23717 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23718 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23720 "pcmpgtw\t{%2, %0|%0, %2}"
23721 [(set_attr "type" "ssecmp")
23722 (set_attr "mode" "TI")])
23724 (define_insn "gtv4si3"
23725 [(set (match_operand:V4SI 0 "register_operand" "=x")
23726 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23727 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23729 "pcmpgtd\t{%2, %0|%0, %2}"
23730 [(set_attr "type" "ssecmp")
23731 (set_attr "mode" "TI")])
23734 ;; MMX max/min insns
23736 (define_insn "umaxv16qi3"
23737 [(set (match_operand:V16QI 0 "register_operand" "=x")
23738 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
23739 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23741 "pmaxub\t{%2, %0|%0, %2}"
23742 [(set_attr "type" "sseiadd")
23743 (set_attr "mode" "TI")])
23745 (define_insn "smaxv8hi3"
23746 [(set (match_operand:V8HI 0 "register_operand" "=x")
23747 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
23748 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23750 "pmaxsw\t{%2, %0|%0, %2}"
23751 [(set_attr "type" "sseiadd")
23752 (set_attr "mode" "TI")])
23754 (define_insn "uminv16qi3"
23755 [(set (match_operand:V16QI 0 "register_operand" "=x")
23756 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
23757 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23759 "pminub\t{%2, %0|%0, %2}"
23760 [(set_attr "type" "sseiadd")
23761 (set_attr "mode" "TI")])
23763 (define_insn "sminv8hi3"
23764 [(set (match_operand:V8HI 0 "register_operand" "=x")
23765 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
23766 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23768 "pminsw\t{%2, %0|%0, %2}"
23769 [(set_attr "type" "sseiadd")
23770 (set_attr "mode" "TI")])
23775 (define_insn "ashrv8hi3"
23776 [(set (match_operand:V8HI 0 "register_operand" "=x")
23777 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23778 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23780 "psraw\t{%2, %0|%0, %2}"
23781 [(set_attr "type" "sseishft")
23782 (set_attr "mode" "TI")])
23784 (define_insn "ashrv4si3"
23785 [(set (match_operand:V4SI 0 "register_operand" "=x")
23786 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23787 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23789 "psrad\t{%2, %0|%0, %2}"
23790 [(set_attr "type" "sseishft")
23791 (set_attr "mode" "TI")])
23793 (define_insn "lshrv8hi3"
23794 [(set (match_operand:V8HI 0 "register_operand" "=x")
23795 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23796 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23798 "psrlw\t{%2, %0|%0, %2}"
23799 [(set_attr "type" "sseishft")
23800 (set_attr "mode" "TI")])
23802 (define_insn "lshrv4si3"
23803 [(set (match_operand:V4SI 0 "register_operand" "=x")
23804 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23805 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23807 "psrld\t{%2, %0|%0, %2}"
23808 [(set_attr "type" "sseishft")
23809 (set_attr "mode" "TI")])
23811 (define_insn "lshrv2di3"
23812 [(set (match_operand:V2DI 0 "register_operand" "=x")
23813 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23814 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23816 "psrlq\t{%2, %0|%0, %2}"
23817 [(set_attr "type" "sseishft")
23818 (set_attr "mode" "TI")])
23820 (define_insn "ashlv8hi3"
23821 [(set (match_operand:V8HI 0 "register_operand" "=x")
23822 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23823 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23825 "psllw\t{%2, %0|%0, %2}"
23826 [(set_attr "type" "sseishft")
23827 (set_attr "mode" "TI")])
23829 (define_insn "ashlv4si3"
23830 [(set (match_operand:V4SI 0 "register_operand" "=x")
23831 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23832 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23834 "pslld\t{%2, %0|%0, %2}"
23835 [(set_attr "type" "sseishft")
23836 (set_attr "mode" "TI")])
23838 (define_insn "ashlv2di3"
23839 [(set (match_operand:V2DI 0 "register_operand" "=x")
23840 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23841 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23843 "psllq\t{%2, %0|%0, %2}"
23844 [(set_attr "type" "sseishft")
23845 (set_attr "mode" "TI")])
23847 (define_insn "ashrv8hi3_ti"
23848 [(set (match_operand:V8HI 0 "register_operand" "=x")
23849 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23850 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23852 "psraw\t{%2, %0|%0, %2}"
23853 [(set_attr "type" "sseishft")
23854 (set_attr "mode" "TI")])
23856 (define_insn "ashrv4si3_ti"
23857 [(set (match_operand:V4SI 0 "register_operand" "=x")
23858 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23859 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23861 "psrad\t{%2, %0|%0, %2}"
23862 [(set_attr "type" "sseishft")
23863 (set_attr "mode" "TI")])
23865 (define_insn "lshrv8hi3_ti"
23866 [(set (match_operand:V8HI 0 "register_operand" "=x")
23867 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23868 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23870 "psrlw\t{%2, %0|%0, %2}"
23871 [(set_attr "type" "sseishft")
23872 (set_attr "mode" "TI")])
23874 (define_insn "lshrv4si3_ti"
23875 [(set (match_operand:V4SI 0 "register_operand" "=x")
23876 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23877 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23879 "psrld\t{%2, %0|%0, %2}"
23880 [(set_attr "type" "sseishft")
23881 (set_attr "mode" "TI")])
23883 (define_insn "lshrv2di3_ti"
23884 [(set (match_operand:V2DI 0 "register_operand" "=x")
23885 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23886 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23888 "psrlq\t{%2, %0|%0, %2}"
23889 [(set_attr "type" "sseishft")
23890 (set_attr "mode" "TI")])
23892 (define_insn "ashlv8hi3_ti"
23893 [(set (match_operand:V8HI 0 "register_operand" "=x")
23894 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23895 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23897 "psllw\t{%2, %0|%0, %2}"
23898 [(set_attr "type" "sseishft")
23899 (set_attr "mode" "TI")])
23901 (define_insn "ashlv4si3_ti"
23902 [(set (match_operand:V4SI 0 "register_operand" "=x")
23903 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23904 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23906 "pslld\t{%2, %0|%0, %2}"
23907 [(set_attr "type" "sseishft")
23908 (set_attr "mode" "TI")])
23910 (define_insn "ashlv2di3_ti"
23911 [(set (match_operand:V2DI 0 "register_operand" "=x")
23912 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23913 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23915 "psllq\t{%2, %0|%0, %2}"
23916 [(set_attr "type" "sseishft")
23917 (set_attr "mode" "TI")])
23919 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
23920 ;; we wouldn't need here it since we never generate TImode arithmetic.
23922 ;; There has to be some kind of prize for the weirdest new instruction...
23923 (define_insn "sse2_ashlti3"
23924 [(set (match_operand:TI 0 "register_operand" "=x")
23926 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
23927 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23928 (const_int 8)))] UNSPEC_NOP))]
23930 "pslldq\t{%2, %0|%0, %2}"
23931 [(set_attr "type" "sseishft")
23932 (set_attr "mode" "TI")])
23934 (define_insn "sse2_lshrti3"
23935 [(set (match_operand:TI 0 "register_operand" "=x")
23937 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
23938 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23939 (const_int 8)))] UNSPEC_NOP))]
23941 "psrldq\t{%2, %0|%0, %2}"
23942 [(set_attr "type" "sseishft")
23943 (set_attr "mode" "TI")])
23947 (define_insn "sse2_unpckhpd"
23948 [(set (match_operand:V2DF 0 "register_operand" "=x")
23950 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23951 (parallel [(const_int 1)]))
23952 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23953 (parallel [(const_int 1)]))))]
23955 "unpckhpd\t{%2, %0|%0, %2}"
23956 [(set_attr "type" "ssecvt")
23957 (set_attr "mode" "V2DF")])
23959 (define_insn "sse2_unpcklpd"
23960 [(set (match_operand:V2DF 0 "register_operand" "=x")
23962 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23963 (parallel [(const_int 0)]))
23964 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23965 (parallel [(const_int 0)]))))]
23967 "unpcklpd\t{%2, %0|%0, %2}"
23968 [(set_attr "type" "ssecvt")
23969 (set_attr "mode" "V2DF")])
23971 ;; MMX pack/unpack insns.
23973 (define_insn "sse2_packsswb"
23974 [(set (match_operand:V16QI 0 "register_operand" "=x")
23976 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23977 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23979 "packsswb\t{%2, %0|%0, %2}"
23980 [(set_attr "type" "ssecvt")
23981 (set_attr "mode" "TI")])
23983 (define_insn "sse2_packssdw"
23984 [(set (match_operand:V8HI 0 "register_operand" "=x")
23986 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
23987 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
23989 "packssdw\t{%2, %0|%0, %2}"
23990 [(set_attr "type" "ssecvt")
23991 (set_attr "mode" "TI")])
23993 (define_insn "sse2_packuswb"
23994 [(set (match_operand:V16QI 0 "register_operand" "=x")
23996 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23997 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23999 "packuswb\t{%2, %0|%0, %2}"
24000 [(set_attr "type" "ssecvt")
24001 (set_attr "mode" "TI")])
24003 (define_insn "sse2_punpckhbw"
24004 [(set (match_operand:V16QI 0 "register_operand" "=x")
24006 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
24007 (parallel [(const_int 8) (const_int 0)
24008 (const_int 9) (const_int 1)
24009 (const_int 10) (const_int 2)
24010 (const_int 11) (const_int 3)
24011 (const_int 12) (const_int 4)
24012 (const_int 13) (const_int 5)
24013 (const_int 14) (const_int 6)
24014 (const_int 15) (const_int 7)]))
24015 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
24016 (parallel [(const_int 0) (const_int 8)
24017 (const_int 1) (const_int 9)
24018 (const_int 2) (const_int 10)
24019 (const_int 3) (const_int 11)
24020 (const_int 4) (const_int 12)
24021 (const_int 5) (const_int 13)
24022 (const_int 6) (const_int 14)
24023 (const_int 7) (const_int 15)]))
24024 (const_int 21845)))]
24026 "punpckhbw\t{%2, %0|%0, %2}"
24027 [(set_attr "type" "ssecvt")
24028 (set_attr "mode" "TI")])
24030 (define_insn "sse2_punpckhwd"
24031 [(set (match_operand:V8HI 0 "register_operand" "=x")
24033 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
24034 (parallel [(const_int 4) (const_int 0)
24035 (const_int 5) (const_int 1)
24036 (const_int 6) (const_int 2)
24037 (const_int 7) (const_int 3)]))
24038 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
24039 (parallel [(const_int 0) (const_int 4)
24040 (const_int 1) (const_int 5)
24041 (const_int 2) (const_int 6)
24042 (const_int 3) (const_int 7)]))
24045 "punpckhwd\t{%2, %0|%0, %2}"
24046 [(set_attr "type" "ssecvt")
24047 (set_attr "mode" "TI")])
24049 (define_insn "sse2_punpckhdq"
24050 [(set (match_operand:V4SI 0 "register_operand" "=x")
24052 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
24053 (parallel [(const_int 2) (const_int 0)
24054 (const_int 3) (const_int 1)]))
24055 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
24056 (parallel [(const_int 0) (const_int 2)
24057 (const_int 1) (const_int 3)]))
24060 "punpckhdq\t{%2, %0|%0, %2}"
24061 [(set_attr "type" "ssecvt")
24062 (set_attr "mode" "TI")])
24064 (define_insn "sse2_punpcklbw"
24065 [(set (match_operand:V16QI 0 "register_operand" "=x")
24067 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
24068 (parallel [(const_int 0) (const_int 8)
24069 (const_int 1) (const_int 9)
24070 (const_int 2) (const_int 10)
24071 (const_int 3) (const_int 11)
24072 (const_int 4) (const_int 12)
24073 (const_int 5) (const_int 13)
24074 (const_int 6) (const_int 14)
24075 (const_int 7) (const_int 15)]))
24076 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
24077 (parallel [(const_int 8) (const_int 0)
24078 (const_int 9) (const_int 1)
24079 (const_int 10) (const_int 2)
24080 (const_int 11) (const_int 3)
24081 (const_int 12) (const_int 4)
24082 (const_int 13) (const_int 5)
24083 (const_int 14) (const_int 6)
24084 (const_int 15) (const_int 7)]))
24085 (const_int 21845)))]
24087 "punpcklbw\t{%2, %0|%0, %2}"
24088 [(set_attr "type" "ssecvt")
24089 (set_attr "mode" "TI")])
24091 (define_insn "sse2_punpcklwd"
24092 [(set (match_operand:V8HI 0 "register_operand" "=x")
24094 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
24095 (parallel [(const_int 0) (const_int 4)
24096 (const_int 1) (const_int 5)
24097 (const_int 2) (const_int 6)
24098 (const_int 3) (const_int 7)]))
24099 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
24100 (parallel [(const_int 4) (const_int 0)
24101 (const_int 5) (const_int 1)
24102 (const_int 6) (const_int 2)
24103 (const_int 7) (const_int 3)]))
24106 "punpcklwd\t{%2, %0|%0, %2}"
24107 [(set_attr "type" "ssecvt")
24108 (set_attr "mode" "TI")])
24110 (define_insn "sse2_punpckldq"
24111 [(set (match_operand:V4SI 0 "register_operand" "=x")
24113 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
24114 (parallel [(const_int 0) (const_int 2)
24115 (const_int 1) (const_int 3)]))
24116 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
24117 (parallel [(const_int 2) (const_int 0)
24118 (const_int 3) (const_int 1)]))
24121 "punpckldq\t{%2, %0|%0, %2}"
24122 [(set_attr "type" "ssecvt")
24123 (set_attr "mode" "TI")])
24125 (define_insn "sse2_punpcklqdq"
24126 [(set (match_operand:V2DI 0 "register_operand" "=x")
24128 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
24129 (parallel [(const_int 1)
24131 (match_operand:V2DI 1 "register_operand" "0")
24134 "punpcklqdq\t{%2, %0|%0, %2}"
24135 [(set_attr "type" "ssecvt")
24136 (set_attr "mode" "TI")])
24138 (define_insn "sse2_punpckhqdq"
24139 [(set (match_operand:V2DI 0 "register_operand" "=x")
24141 (match_operand:V2DI 1 "register_operand" "0")
24142 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
24143 (parallel [(const_int 1)
24147 "punpckhqdq\t{%2, %0|%0, %2}"
24148 [(set_attr "type" "ssecvt")
24149 (set_attr "mode" "TI")])
24153 (define_insn "sse2_movapd"
24154 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
24155 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
24158 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
24159 "movapd\t{%1, %0|%0, %1}"
24160 [(set_attr "type" "ssemov")
24161 (set_attr "mode" "V2DF")])
24163 (define_insn "sse2_movupd"
24164 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
24165 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
24168 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
24169 "movupd\t{%1, %0|%0, %1}"
24170 [(set_attr "type" "ssecvt")
24171 (set_attr "mode" "V2DF")])
24173 (define_insn "sse2_movdqa"
24174 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
24175 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
24178 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
24179 "movdqa\t{%1, %0|%0, %1}"
24180 [(set_attr "type" "ssemov")
24181 (set_attr "mode" "TI")])
24183 (define_insn "sse2_movdqu"
24184 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
24185 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
24188 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
24189 "movdqu\t{%1, %0|%0, %1}"
24190 [(set_attr "type" "ssecvt")
24191 (set_attr "mode" "TI")])
24193 (define_insn "sse2_movdq2q"
24194 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
24195 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
24196 (parallel [(const_int 0)])))]
24197 "TARGET_SSE2 && !TARGET_64BIT"
24199 movq\t{%1, %0|%0, %1}
24200 movdq2q\t{%1, %0|%0, %1}"
24201 [(set_attr "type" "ssecvt")
24202 (set_attr "mode" "TI")])
24204 (define_insn "sse2_movdq2q_rex64"
24205 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
24206 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
24207 (parallel [(const_int 0)])))]
24208 "TARGET_SSE2 && TARGET_64BIT"
24210 movq\t{%1, %0|%0, %1}
24211 movdq2q\t{%1, %0|%0, %1}
24212 movd\t{%1, %0|%0, %1}"
24213 [(set_attr "type" "ssecvt")
24214 (set_attr "mode" "TI")])
24216 (define_insn "sse2_movq2dq"
24217 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
24218 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
24220 "TARGET_SSE2 && !TARGET_64BIT"
24222 movq\t{%1, %0|%0, %1}
24223 movq2dq\t{%1, %0|%0, %1}"
24224 [(set_attr "type" "ssecvt,ssemov")
24225 (set_attr "mode" "TI")])
24227 (define_insn "sse2_movq2dq_rex64"
24228 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
24229 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
24231 "TARGET_SSE2 && TARGET_64BIT"
24233 movq\t{%1, %0|%0, %1}
24234 movq2dq\t{%1, %0|%0, %1}
24235 movd\t{%1, %0|%0, %1}"
24236 [(set_attr "type" "ssecvt,ssemov,ssecvt")
24237 (set_attr "mode" "TI")])
24239 (define_insn "sse2_movq"
24240 [(set (match_operand:V2DI 0 "register_operand" "=x")
24241 (vec_concat:V2DI (vec_select:DI
24242 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
24243 (parallel [(const_int 0)]))
24246 "movq\t{%1, %0|%0, %1}"
24247 [(set_attr "type" "ssemov")
24248 (set_attr "mode" "TI")])
24250 (define_insn "sse2_loadd"
24251 [(set (match_operand:V4SI 0 "register_operand" "=x")
24253 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
24254 (const_vector:V4SI [(const_int 0)
24260 "movd\t{%1, %0|%0, %1}"
24261 [(set_attr "type" "ssemov")
24262 (set_attr "mode" "TI")])
24264 (define_insn "sse2_stored"
24265 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
24267 (match_operand:V4SI 1 "register_operand" "x")
24268 (parallel [(const_int 0)])))]
24270 "movd\t{%1, %0|%0, %1}"
24271 [(set_attr "type" "ssemov")
24272 (set_attr "mode" "TI")])
24274 (define_insn "sse2_movhpd"
24275 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
24277 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
24278 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
24280 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
24281 "movhpd\t{%2, %0|%0, %2}"
24282 [(set_attr "type" "ssecvt")
24283 (set_attr "mode" "V2DF")])
24285 (define_expand "sse2_loadsd"
24286 [(match_operand:V2DF 0 "register_operand" "")
24287 (match_operand:DF 1 "memory_operand" "")]
24290 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
24291 CONST0_RTX (V2DFmode)));
24295 (define_insn "sse2_loadsd_1"
24296 [(set (match_operand:V2DF 0 "register_operand" "=x")
24298 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
24299 (match_operand:V2DF 2 "const0_operand" "X")
24302 "movsd\t{%1, %0|%0, %1}"
24303 [(set_attr "type" "ssecvt")
24304 (set_attr "mode" "DF")])
24306 (define_insn "sse2_movsd"
24307 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
24309 (match_operand:V2DF 1 "nonimmediate_operand" "0,0,0")
24310 (match_operand:V2DF 2 "nonimmediate_operand" "x,m,x")
24312 "TARGET_SSE2 && ix86_binary_operator_ok (UNKNOWN, V2DFmode, operands)"
24313 "@movsd\t{%2, %0|%0, %2}
24314 movlpd\t{%2, %0|%0, %2}
24315 movlpd\t{%2, %0|%0, %2}"
24316 [(set_attr "type" "ssecvt")
24317 (set_attr "mode" "DF,V2DF,V2DF")])
24319 (define_insn "sse2_storesd"
24320 [(set (match_operand:DF 0 "memory_operand" "=m")
24322 (match_operand:V2DF 1 "register_operand" "x")
24323 (parallel [(const_int 0)])))]
24325 "movsd\t{%1, %0|%0, %1}"
24326 [(set_attr "type" "ssecvt")
24327 (set_attr "mode" "DF")])
24329 (define_insn "sse2_shufpd"
24330 [(set (match_operand:V2DF 0 "register_operand" "=x")
24331 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24332 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
24333 (match_operand:SI 3 "immediate_operand" "i")]
24336 ;; @@@ check operand order for intel/nonintel syntax
24337 "shufpd\t{%3, %2, %0|%0, %2, %3}"
24338 [(set_attr "type" "ssecvt")
24339 (set_attr "mode" "V2DF")])
24341 (define_insn "sse2_clflush"
24342 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
24346 [(set_attr "type" "sse")
24347 (set_attr "memory" "unknown")])
24349 (define_expand "sse2_mfence"
24350 [(set (match_dup 0)
24351 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
24354 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
24355 MEM_VOLATILE_P (operands[0]) = 1;
24358 (define_insn "*mfence_insn"
24359 [(set (match_operand:BLK 0 "" "")
24360 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
24363 [(set_attr "type" "sse")
24364 (set_attr "memory" "unknown")])
24366 (define_expand "sse2_lfence"
24367 [(set (match_dup 0)
24368 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
24371 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
24372 MEM_VOLATILE_P (operands[0]) = 1;
24375 (define_insn "*lfence_insn"
24376 [(set (match_operand:BLK 0 "" "")
24377 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
24380 [(set_attr "type" "sse")
24381 (set_attr "memory" "unknown")])
24385 (define_insn "mwait"
24386 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
24387 (match_operand:SI 1 "register_operand" "c")]
24391 [(set_attr "length" "3")])
24393 (define_insn "monitor"
24394 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
24395 (match_operand:SI 1 "register_operand" "c")
24396 (match_operand:SI 2 "register_operand" "d")]
24399 "monitor\t%0, %1, %2"
24400 [(set_attr "length" "3")])
24404 (define_insn "addsubv4sf3"
24405 [(set (match_operand:V4SF 0 "register_operand" "=x")
24406 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24407 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24410 "addsubps\t{%2, %0|%0, %2}"
24411 [(set_attr "type" "sseadd")
24412 (set_attr "mode" "V4SF")])
24414 (define_insn "addsubv2df3"
24415 [(set (match_operand:V2DF 0 "register_operand" "=x")
24416 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24417 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24420 "addsubpd\t{%2, %0|%0, %2}"
24421 [(set_attr "type" "sseadd")
24422 (set_attr "mode" "V2DF")])
24424 (define_insn "haddv4sf3"
24425 [(set (match_operand:V4SF 0 "register_operand" "=x")
24426 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24427 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24430 "haddps\t{%2, %0|%0, %2}"
24431 [(set_attr "type" "sseadd")
24432 (set_attr "mode" "V4SF")])
24434 (define_insn "haddv2df3"
24435 [(set (match_operand:V2DF 0 "register_operand" "=x")
24436 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24437 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24440 "haddpd\t{%2, %0|%0, %2}"
24441 [(set_attr "type" "sseadd")
24442 (set_attr "mode" "V2DF")])
24444 (define_insn "hsubv4sf3"
24445 [(set (match_operand:V4SF 0 "register_operand" "=x")
24446 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24447 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24450 "hsubps\t{%2, %0|%0, %2}"
24451 [(set_attr "type" "sseadd")
24452 (set_attr "mode" "V4SF")])
24454 (define_insn "hsubv2df3"
24455 [(set (match_operand:V2DF 0 "register_operand" "=x")
24456 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24457 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24460 "hsubpd\t{%2, %0|%0, %2}"
24461 [(set_attr "type" "sseadd")
24462 (set_attr "mode" "V2DF")])
24464 (define_insn "movshdup"
24465 [(set (match_operand:V4SF 0 "register_operand" "=x")
24467 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
24469 "movshdup\t{%1, %0|%0, %1}"
24470 [(set_attr "type" "sse")
24471 (set_attr "mode" "V4SF")])
24473 (define_insn "movsldup"
24474 [(set (match_operand:V4SF 0 "register_operand" "=x")
24476 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
24478 "movsldup\t{%1, %0|%0, %1}"
24479 [(set_attr "type" "sse")
24480 (set_attr "mode" "V4SF")])
24482 (define_insn "lddqu"
24483 [(set (match_operand:V16QI 0 "register_operand" "=x")
24484 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
24487 "lddqu\t{%1, %0|%0, %1}"
24488 [(set_attr "type" "ssecvt")
24489 (set_attr "mode" "TI")])
24491 (define_insn "loadddup"
24492 [(set (match_operand:V2DF 0 "register_operand" "=x")
24493 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
24495 "movddup\t{%1, %0|%0, %1}"
24496 [(set_attr "type" "ssecvt")
24497 (set_attr "mode" "DF")])
24499 (define_insn "movddup"
24500 [(set (match_operand:V2DF 0 "register_operand" "=x")
24501 (vec_duplicate:V2DF
24502 (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
24503 (parallel [(const_int 0)]))))]
24505 "movddup\t{%1, %0|%0, %1}"
24506 [(set_attr "type" "ssecvt")
24507 (set_attr "mode" "DF")])