1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
56 [; Relocation specifiers
66 (UNSPEC_STACK_PROBE 10)
67 (UNSPEC_STACK_ALLOC 11)
69 (UNSPEC_SSE_PROLOGUE_SAVE 13)
74 (UNSPEC_TLS_LD_BASE 17)
76 ; Other random patterns
87 ; For SSE/MMX support:
98 (UNSPEC_NOP 45) ; prevents combiner cleverness
113 [(UNSPECV_BLOCKAGE 0)
114 (UNSPECV_EH_RETURN 13)
122 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
125 ;; In C guard expressions, put expressions which may be compile-time
126 ;; constants first. This allows for better optimization. For
127 ;; example, write "TARGET_64BIT && reload_completed", not
128 ;; "reload_completed && TARGET_64BIT".
131 ;; Processor type. This attribute must exactly match the processor_type
132 ;; enumeration in i386.h.
133 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
134 (const (symbol_ref "ix86_cpu")))
136 ;; A basic instruction type. Refinements due to arguments to be
137 ;; provided in other attributes.
140 alu,alu1,negnot,imov,imovx,lea,
141 incdec,ishift,rotate,imul,idiv,
142 icmp,test,ibr,setcc,icmov,
145 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
146 sselog,sseiadd,sseishft,sseimul,
147 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv,
148 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
149 (const_string "other"))
151 ;; Main data type used by the insn
153 "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI,V4SF,V2DF,V2SF"
154 (const_string "unknown"))
156 ;; The CPU unit operations uses.
157 (define_attr "unit" "integer,i387,sse,mmx,unknown"
158 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
159 (const_string "i387")
160 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
161 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv")
163 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
164 (const_string "mmx")]
165 (const_string "integer")))
167 ;; The (bounding maximum) length of an instruction immediate.
168 (define_attr "length_immediate" ""
169 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv")
171 (eq_attr "unit" "i387,sse,mmx")
173 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,imul,
175 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
176 (eq_attr "type" "imov,test")
177 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
178 (eq_attr "type" "call")
179 (if_then_else (match_operand 0 "constant_call_address_operand" "")
182 (eq_attr "type" "callv")
183 (if_then_else (match_operand 1 "constant_call_address_operand" "")
186 (eq_attr "type" "ibr")
187 (if_then_else (and (ge (minus (match_dup 0) (pc))
189 (lt (minus (match_dup 0) (pc))
194 (symbol_ref "/* Update immediate_length and other attributes! */
197 ;; The (bounding maximum) length of an instruction address.
198 (define_attr "length_address" ""
199 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
201 (and (eq_attr "type" "call")
202 (match_operand 0 "constant_call_address_operand" ""))
204 (and (eq_attr "type" "callv")
205 (match_operand 1 "constant_call_address_operand" ""))
208 (symbol_ref "ix86_attr_length_address_default (insn)")))
210 ;; Set when length prefix is used.
211 (define_attr "prefix_data16" ""
212 (if_then_else (ior (eq_attr "mode" "HI")
213 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
217 ;; Set when string REP prefix is used.
218 (define_attr "prefix_rep" ""
219 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
223 ;; Set when 0f opcode prefix is used.
224 (define_attr "prefix_0f" ""
228 sselog,sseiadd,sseishft,sseimul,
229 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv,
230 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
234 ;; Set when modrm byte is used.
235 (define_attr "modrm" ""
236 (cond [(eq_attr "type" "str,cld")
238 (eq_attr "unit" "i387")
240 (and (eq_attr "type" "incdec")
241 (ior (match_operand:SI 1 "register_operand" "")
242 (match_operand:HI 1 "register_operand" "")))
244 (and (eq_attr "type" "push")
245 (not (match_operand 1 "memory_operand" "")))
247 (and (eq_attr "type" "pop")
248 (not (match_operand 0 "memory_operand" "")))
250 (and (eq_attr "type" "imov")
251 (and (match_operand 0 "register_operand" "")
252 (match_operand 1 "immediate_operand" "")))
254 (and (eq_attr "type" "call")
255 (match_operand 0 "constant_call_address_operand" ""))
257 (and (eq_attr "type" "callv")
258 (match_operand 1 "constant_call_address_operand" ""))
263 ;; The (bounding maximum) length of an instruction in bytes.
264 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
265 ;; to split it and compute proper length as for other insns.
266 (define_attr "length" ""
267 (cond [(eq_attr "type" "other,multi,fistp")
269 (eq_attr "unit" "i387")
271 (plus (attr "prefix_data16")
272 (attr "length_address")))]
273 (plus (plus (attr "modrm")
274 (plus (attr "prefix_0f")
276 (plus (attr "prefix_rep")
277 (plus (attr "prefix_data16")
278 (plus (attr "length_immediate")
279 (attr "length_address")))))))
281 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
282 ;; `store' if there is a simple memory reference therein, or `unknown'
283 ;; if the instruction is complex.
285 (define_attr "memory" "none,load,store,both,unknown"
286 (cond [(eq_attr "type" "other,multi,str")
287 (const_string "unknown")
288 (eq_attr "type" "lea,fcmov,fpspc,cld")
289 (const_string "none")
290 (eq_attr "type" "fistp")
291 (const_string "both")
292 (eq_attr "type" "push")
293 (if_then_else (match_operand 1 "memory_operand" "")
294 (const_string "both")
295 (const_string "store"))
296 (eq_attr "type" "pop,setcc")
297 (if_then_else (match_operand 0 "memory_operand" "")
298 (const_string "both")
299 (const_string "load"))
300 (eq_attr "type" "icmp,test,ssecmp,mmxcmp,fcmp")
301 (if_then_else (ior (match_operand 0 "memory_operand" "")
302 (match_operand 1 "memory_operand" ""))
303 (const_string "load")
304 (const_string "none"))
305 (eq_attr "type" "ibr")
306 (if_then_else (match_operand 0 "memory_operand" "")
307 (const_string "load")
308 (const_string "none"))
309 (eq_attr "type" "call")
310 (if_then_else (match_operand 0 "constant_call_address_operand" "")
311 (const_string "none")
312 (const_string "load"))
313 (eq_attr "type" "callv")
314 (if_then_else (match_operand 1 "constant_call_address_operand" "")
315 (const_string "none")
316 (const_string "load"))
317 (and (eq_attr "type" "alu1,negnot")
318 (match_operand 1 "memory_operand" ""))
319 (const_string "both")
320 (and (match_operand 0 "memory_operand" "")
321 (match_operand 1 "memory_operand" ""))
322 (const_string "both")
323 (match_operand 0 "memory_operand" "")
324 (const_string "store")
325 (match_operand 1 "memory_operand" "")
326 (const_string "load")
329 imov,imovx,icmp,test,
331 sse,ssemov,ssecmp,ssecvt,
332 mmx,mmxmov,mmxcmp,mmxcvt")
333 (match_operand 2 "memory_operand" ""))
334 (const_string "load")
335 (and (eq_attr "type" "icmov")
336 (match_operand 3 "memory_operand" ""))
337 (const_string "load")
339 (const_string "none")))
341 ;; Indicates if an instruction has both an immediate and a displacement.
343 (define_attr "imm_disp" "false,true,unknown"
344 (cond [(eq_attr "type" "other,multi")
345 (const_string "unknown")
346 (and (eq_attr "type" "icmp,test,imov")
347 (and (match_operand 0 "memory_displacement_operand" "")
348 (match_operand 1 "immediate_operand" "")))
349 (const_string "true")
350 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
351 (and (match_operand 0 "memory_displacement_operand" "")
352 (match_operand 2 "immediate_operand" "")))
353 (const_string "true")
355 (const_string "false")))
357 ;; Indicates if an FP operation has an integer source.
359 (define_attr "fp_int_src" "false,true"
360 (const_string "false"))
362 ;; Describe a user's asm statement.
363 (define_asm_attributes
364 [(set_attr "length" "128")
365 (set_attr "type" "multi")])
367 (include "pentium.md")
370 (include "athlon.md")
372 ;; Compare instructions.
374 ;; All compare insns have expanders that save the operands away without
375 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
376 ;; after the cmp) will actually emit the cmpM.
378 (define_expand "cmpdi"
380 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
381 (match_operand:DI 1 "x86_64_general_operand" "")))]
384 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
385 operands[0] = force_reg (DImode, operands[0]);
386 ix86_compare_op0 = operands[0];
387 ix86_compare_op1 = operands[1];
391 (define_expand "cmpsi"
393 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
394 (match_operand:SI 1 "general_operand" "")))]
397 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
398 operands[0] = force_reg (SImode, operands[0]);
399 ix86_compare_op0 = operands[0];
400 ix86_compare_op1 = operands[1];
404 (define_expand "cmphi"
406 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
407 (match_operand:HI 1 "general_operand" "")))]
410 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
411 operands[0] = force_reg (HImode, operands[0]);
412 ix86_compare_op0 = operands[0];
413 ix86_compare_op1 = operands[1];
417 (define_expand "cmpqi"
419 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
420 (match_operand:QI 1 "general_operand" "")))]
423 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
424 operands[0] = force_reg (QImode, operands[0]);
425 ix86_compare_op0 = operands[0];
426 ix86_compare_op1 = operands[1];
430 (define_insn "cmpdi_ccno_1_rex64"
432 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
433 (match_operand:DI 1 "const0_operand" "n,n")))]
434 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
436 test{q}\t{%0, %0|%0, %0}
437 cmp{q}\t{%1, %0|%0, %1}"
438 [(set_attr "type" "test,icmp")
439 (set_attr "length_immediate" "0,1")
440 (set_attr "mode" "DI")])
442 (define_insn "*cmpdi_minus_1_rex64"
444 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
445 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
447 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
448 "cmp{q}\t{%1, %0|%0, %1}"
449 [(set_attr "type" "icmp")
450 (set_attr "mode" "DI")])
452 (define_expand "cmpdi_1_rex64"
454 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
455 (match_operand:DI 1 "general_operand" "")))]
459 (define_insn "cmpdi_1_insn_rex64"
461 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
462 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
463 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
464 "cmp{q}\t{%1, %0|%0, %1}"
465 [(set_attr "type" "icmp")
466 (set_attr "mode" "DI")])
469 (define_insn "*cmpsi_ccno_1"
471 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
472 (match_operand:SI 1 "const0_operand" "n,n")))]
473 "ix86_match_ccmode (insn, CCNOmode)"
475 test{l}\t{%0, %0|%0, %0}
476 cmp{l}\t{%1, %0|%0, %1}"
477 [(set_attr "type" "test,icmp")
478 (set_attr "length_immediate" "0,1")
479 (set_attr "mode" "SI")])
481 (define_insn "*cmpsi_minus_1"
483 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
484 (match_operand:SI 1 "general_operand" "ri,mr"))
486 "ix86_match_ccmode (insn, CCGOCmode)"
487 "cmp{l}\t{%1, %0|%0, %1}"
488 [(set_attr "type" "icmp")
489 (set_attr "mode" "SI")])
491 (define_expand "cmpsi_1"
493 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
494 (match_operand:SI 1 "general_operand" "ri,mr")))]
498 (define_insn "*cmpsi_1_insn"
500 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
501 (match_operand:SI 1 "general_operand" "ri,mr")))]
502 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
503 && ix86_match_ccmode (insn, CCmode)"
504 "cmp{l}\t{%1, %0|%0, %1}"
505 [(set_attr "type" "icmp")
506 (set_attr "mode" "SI")])
508 (define_insn "*cmphi_ccno_1"
510 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
511 (match_operand:HI 1 "const0_operand" "n,n")))]
512 "ix86_match_ccmode (insn, CCNOmode)"
514 test{w}\t{%0, %0|%0, %0}
515 cmp{w}\t{%1, %0|%0, %1}"
516 [(set_attr "type" "test,icmp")
517 (set_attr "length_immediate" "0,1")
518 (set_attr "mode" "HI")])
520 (define_insn "*cmphi_minus_1"
522 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
523 (match_operand:HI 1 "general_operand" "ri,mr"))
525 "ix86_match_ccmode (insn, CCGOCmode)"
526 "cmp{w}\t{%1, %0|%0, %1}"
527 [(set_attr "type" "icmp")
528 (set_attr "mode" "HI")])
530 (define_insn "*cmphi_1"
532 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
533 (match_operand:HI 1 "general_operand" "ri,mr")))]
534 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
535 && ix86_match_ccmode (insn, CCmode)"
536 "cmp{w}\t{%1, %0|%0, %1}"
537 [(set_attr "type" "icmp")
538 (set_attr "mode" "HI")])
540 (define_insn "*cmpqi_ccno_1"
542 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
543 (match_operand:QI 1 "const0_operand" "n,n")))]
544 "ix86_match_ccmode (insn, CCNOmode)"
546 test{b}\t{%0, %0|%0, %0}
547 cmp{b}\t{$0, %0|%0, 0}"
548 [(set_attr "type" "test,icmp")
549 (set_attr "length_immediate" "0,1")
550 (set_attr "mode" "QI")])
552 (define_insn "*cmpqi_1"
554 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
555 (match_operand:QI 1 "general_operand" "qi,mq")))]
556 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
557 && ix86_match_ccmode (insn, CCmode)"
558 "cmp{b}\t{%1, %0|%0, %1}"
559 [(set_attr "type" "icmp")
560 (set_attr "mode" "QI")])
562 (define_insn "*cmpqi_minus_1"
564 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
565 (match_operand:QI 1 "general_operand" "qi,mq"))
567 "ix86_match_ccmode (insn, CCGOCmode)"
568 "cmp{b}\t{%1, %0|%0, %1}"
569 [(set_attr "type" "icmp")
570 (set_attr "mode" "QI")])
572 (define_insn "*cmpqi_ext_1"
575 (match_operand:QI 0 "general_operand" "Qm")
578 (match_operand 1 "ext_register_operand" "Q")
581 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
582 "cmp{b}\t{%h1, %0|%0, %h1}"
583 [(set_attr "type" "icmp")
584 (set_attr "mode" "QI")])
586 (define_insn "*cmpqi_ext_1_rex64"
589 (match_operand:QI 0 "register_operand" "Q")
592 (match_operand 1 "ext_register_operand" "Q")
595 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
596 "cmp{b}\t{%h1, %0|%0, %h1}"
597 [(set_attr "type" "icmp")
598 (set_attr "mode" "QI")])
600 (define_insn "*cmpqi_ext_2"
605 (match_operand 0 "ext_register_operand" "Q")
608 (match_operand:QI 1 "const0_operand" "n")))]
609 "ix86_match_ccmode (insn, CCNOmode)"
611 [(set_attr "type" "test")
612 (set_attr "length_immediate" "0")
613 (set_attr "mode" "QI")])
615 (define_expand "cmpqi_ext_3"
620 (match_operand 0 "ext_register_operand" "")
623 (match_operand:QI 1 "general_operand" "")))]
627 (define_insn "cmpqi_ext_3_insn"
632 (match_operand 0 "ext_register_operand" "Q")
635 (match_operand:QI 1 "general_operand" "Qmn")))]
636 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
637 "cmp{b}\t{%1, %h0|%h0, %1}"
638 [(set_attr "type" "icmp")
639 (set_attr "mode" "QI")])
641 (define_insn "cmpqi_ext_3_insn_rex64"
646 (match_operand 0 "ext_register_operand" "Q")
649 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
650 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
651 "cmp{b}\t{%1, %h0|%h0, %1}"
652 [(set_attr "type" "icmp")
653 (set_attr "mode" "QI")])
655 (define_insn "*cmpqi_ext_4"
660 (match_operand 0 "ext_register_operand" "Q")
665 (match_operand 1 "ext_register_operand" "Q")
668 "ix86_match_ccmode (insn, CCmode)"
669 "cmp{b}\t{%h1, %h0|%h0, %h1}"
670 [(set_attr "type" "icmp")
671 (set_attr "mode" "QI")])
673 ;; These implement float point compares.
674 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
675 ;; which would allow mix and match FP modes on the compares. Which is what
676 ;; the old patterns did, but with many more of them.
678 (define_expand "cmpxf"
680 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
681 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
682 "!TARGET_64BIT && TARGET_80387"
684 ix86_compare_op0 = operands[0];
685 ix86_compare_op1 = operands[1];
689 (define_expand "cmptf"
691 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
692 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
695 ix86_compare_op0 = operands[0];
696 ix86_compare_op1 = operands[1];
700 (define_expand "cmpdf"
702 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
703 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
704 "TARGET_80387 || TARGET_SSE2"
706 ix86_compare_op0 = operands[0];
707 ix86_compare_op1 = operands[1];
711 (define_expand "cmpsf"
713 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
714 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
715 "TARGET_80387 || TARGET_SSE"
717 ix86_compare_op0 = operands[0];
718 ix86_compare_op1 = operands[1];
722 ;; FP compares, step 1:
723 ;; Set the FP condition codes.
725 ;; CCFPmode compare with exceptions
726 ;; CCFPUmode compare with no exceptions
728 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
729 ;; and that fp moves clobber the condition codes, and that there is
730 ;; currently no way to describe this fact to reg-stack. So there are
731 ;; no splitters yet for this.
733 ;; %%% YIKES! This scheme does not retain a strong connection between
734 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
735 ;; work! Only allow tos/mem with tos in op 0.
737 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
738 ;; things aren't as bad as they sound...
740 (define_insn "*cmpfp_0"
741 [(set (match_operand:HI 0 "register_operand" "=a")
743 [(compare:CCFP (match_operand 1 "register_operand" "f")
744 (match_operand 2 "const0_operand" "X"))]
747 && FLOAT_MODE_P (GET_MODE (operands[1]))
748 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
750 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
751 return "ftst\;fnstsw\t%0\;fstp\t%y0";
753 return "ftst\;fnstsw\t%0";
755 [(set_attr "type" "multi")
756 (set_attr "mode" "unknownfp")])
758 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
759 ;; used to manage the reg stack popping would not be preserved.
761 (define_insn "*cmpfp_2_sf"
764 (match_operand:SF 0 "register_operand" "f")
765 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
767 "* return output_fp_compare (insn, operands, 0, 0);"
768 [(set_attr "type" "fcmp")
769 (set_attr "mode" "SF")])
771 (define_insn "*cmpfp_2_sf_1"
772 [(set (match_operand:HI 0 "register_operand" "=a")
775 (match_operand:SF 1 "register_operand" "f")
776 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
779 "* return output_fp_compare (insn, operands, 2, 0);"
780 [(set_attr "type" "fcmp")
781 (set_attr "mode" "SF")])
783 (define_insn "*cmpfp_2_df"
786 (match_operand:DF 0 "register_operand" "f")
787 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
789 "* return output_fp_compare (insn, operands, 0, 0);"
790 [(set_attr "type" "fcmp")
791 (set_attr "mode" "DF")])
793 (define_insn "*cmpfp_2_df_1"
794 [(set (match_operand:HI 0 "register_operand" "=a")
797 (match_operand:DF 1 "register_operand" "f")
798 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
801 "* return output_fp_compare (insn, operands, 2, 0);"
802 [(set_attr "type" "multi")
803 (set_attr "mode" "DF")])
805 (define_insn "*cmpfp_2_xf"
808 (match_operand:XF 0 "register_operand" "f")
809 (match_operand:XF 1 "register_operand" "f")))]
810 "!TARGET_64BIT && TARGET_80387"
811 "* return output_fp_compare (insn, operands, 0, 0);"
812 [(set_attr "type" "fcmp")
813 (set_attr "mode" "XF")])
815 (define_insn "*cmpfp_2_tf"
818 (match_operand:TF 0 "register_operand" "f")
819 (match_operand:TF 1 "register_operand" "f")))]
821 "* return output_fp_compare (insn, operands, 0, 0);"
822 [(set_attr "type" "fcmp")
823 (set_attr "mode" "XF")])
825 (define_insn "*cmpfp_2_xf_1"
826 [(set (match_operand:HI 0 "register_operand" "=a")
829 (match_operand:XF 1 "register_operand" "f")
830 (match_operand:XF 2 "register_operand" "f"))]
832 "!TARGET_64BIT && TARGET_80387"
833 "* return output_fp_compare (insn, operands, 2, 0);"
834 [(set_attr "type" "multi")
835 (set_attr "mode" "XF")])
837 (define_insn "*cmpfp_2_tf_1"
838 [(set (match_operand:HI 0 "register_operand" "=a")
841 (match_operand:TF 1 "register_operand" "f")
842 (match_operand:TF 2 "register_operand" "f"))]
845 "* return output_fp_compare (insn, operands, 2, 0);"
846 [(set_attr "type" "multi")
847 (set_attr "mode" "XF")])
849 (define_insn "*cmpfp_2u"
852 (match_operand 0 "register_operand" "f")
853 (match_operand 1 "register_operand" "f")))]
855 && FLOAT_MODE_P (GET_MODE (operands[0]))
856 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
857 "* return output_fp_compare (insn, operands, 0, 1);"
858 [(set_attr "type" "fcmp")
859 (set_attr "mode" "unknownfp")])
861 (define_insn "*cmpfp_2u_1"
862 [(set (match_operand:HI 0 "register_operand" "=a")
865 (match_operand 1 "register_operand" "f")
866 (match_operand 2 "register_operand" "f"))]
869 && FLOAT_MODE_P (GET_MODE (operands[1]))
870 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
871 "* return output_fp_compare (insn, operands, 2, 1);"
872 [(set_attr "type" "multi")
873 (set_attr "mode" "unknownfp")])
875 ;; Patterns to match the SImode-in-memory ficom instructions.
877 ;; %%% Play games with accepting gp registers, as otherwise we have to
878 ;; force them to memory during rtl generation, which is no good. We
879 ;; can get rid of this once we teach reload to do memory input reloads
882 (define_insn "*ficom_1"
885 (match_operand 0 "register_operand" "f,f")
886 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
887 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
888 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
891 ;; Split the not-really-implemented gp register case into a
892 ;; push-op-pop sequence.
894 ;; %%% This is most efficient, but am I gonna get in trouble
895 ;; for separating cc0_setter and cc0_user?
900 (match_operand:SF 0 "register_operand" "")
901 (float (match_operand:SI 1 "register_operand" ""))))]
902 "0 && TARGET_80387 && reload_completed"
903 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
904 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
905 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
906 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
907 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
908 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
910 ;; FP compares, step 2
911 ;; Move the fpsw to ax.
913 (define_insn "x86_fnstsw_1"
914 [(set (match_operand:HI 0 "register_operand" "=a")
915 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
918 [(set_attr "length" "2")
919 (set_attr "mode" "SI")
920 (set_attr "unit" "i387")
921 (set_attr "ppro_uops" "few")])
923 ;; FP compares, step 3
924 ;; Get ax into flags, general case.
926 (define_insn "x86_sahf_1"
928 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
931 [(set_attr "length" "1")
932 (set_attr "athlon_decode" "vector")
933 (set_attr "mode" "SI")
934 (set_attr "ppro_uops" "one")])
936 ;; Pentium Pro can do steps 1 through 3 in one go.
938 (define_insn "*cmpfp_i"
940 (compare:CCFP (match_operand 0 "register_operand" "f")
941 (match_operand 1 "register_operand" "f")))]
942 "TARGET_80387 && TARGET_CMOVE
943 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
944 && FLOAT_MODE_P (GET_MODE (operands[0]))
945 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
946 "* return output_fp_compare (insn, operands, 1, 0);"
947 [(set_attr "type" "fcmp")
948 (set_attr "mode" "unknownfp")
949 (set_attr "athlon_decode" "vector")])
951 (define_insn "*cmpfp_i_sse"
953 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
954 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
956 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
957 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
958 "* return output_fp_compare (insn, operands, 1, 0);"
959 [(set_attr "type" "fcmp,ssecmp")
960 (set_attr "mode" "unknownfp")
961 (set_attr "athlon_decode" "vector")])
963 (define_insn "*cmpfp_i_sse_only"
965 (compare:CCFP (match_operand 0 "register_operand" "x")
966 (match_operand 1 "nonimmediate_operand" "xm")))]
967 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
968 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
969 "* return output_fp_compare (insn, operands, 1, 0);"
970 [(set_attr "type" "ssecmp")
971 (set_attr "mode" "unknownfp")
972 (set_attr "athlon_decode" "vector")])
974 (define_insn "*cmpfp_iu"
976 (compare:CCFPU (match_operand 0 "register_operand" "f")
977 (match_operand 1 "register_operand" "f")))]
978 "TARGET_80387 && TARGET_CMOVE
979 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
980 && FLOAT_MODE_P (GET_MODE (operands[0]))
981 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
982 "* return output_fp_compare (insn, operands, 1, 1);"
983 [(set_attr "type" "fcmp")
984 (set_attr "mode" "unknownfp")
985 (set_attr "athlon_decode" "vector")])
987 (define_insn "*cmpfp_iu_sse"
989 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
990 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
992 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
993 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
994 "* return output_fp_compare (insn, operands, 1, 1);"
995 [(set_attr "type" "fcmp,ssecmp")
996 (set_attr "mode" "unknownfp")
997 (set_attr "athlon_decode" "vector")])
999 (define_insn "*cmpfp_iu_sse_only"
1000 [(set (reg:CCFPU 17)
1001 (compare:CCFPU (match_operand 0 "register_operand" "x")
1002 (match_operand 1 "nonimmediate_operand" "xm")))]
1003 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1004 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1005 "* return output_fp_compare (insn, operands, 1, 1);"
1006 [(set_attr "type" "ssecmp")
1007 (set_attr "mode" "unknownfp")
1008 (set_attr "athlon_decode" "vector")])
1010 ;; Move instructions.
1012 ;; General case of fullword move.
1014 (define_expand "movsi"
1015 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1016 (match_operand:SI 1 "general_operand" ""))]
1018 "ix86_expand_move (SImode, operands); DONE;")
1020 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1023 ;; %%% We don't use a post-inc memory reference because x86 is not a
1024 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1025 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1026 ;; targets without our curiosities, and it is just as easy to represent
1027 ;; this differently.
1029 (define_insn "*pushsi2"
1030 [(set (match_operand:SI 0 "push_operand" "=<")
1031 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1034 [(set_attr "type" "push")
1035 (set_attr "mode" "SI")])
1037 ;; For 64BIT abi we always round up to 8 bytes.
1038 (define_insn "*pushsi2_rex64"
1039 [(set (match_operand:SI 0 "push_operand" "=X")
1040 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1043 [(set_attr "type" "push")
1044 (set_attr "mode" "SI")])
1046 (define_insn "*pushsi2_prologue"
1047 [(set (match_operand:SI 0 "push_operand" "=<")
1048 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1049 (clobber (mem:BLK (scratch)))]
1052 [(set_attr "type" "push")
1053 (set_attr "mode" "SI")])
1055 (define_insn "*popsi1_epilogue"
1056 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1057 (mem:SI (reg:SI 7)))
1059 (plus:SI (reg:SI 7) (const_int 4)))
1060 (clobber (mem:BLK (scratch)))]
1063 [(set_attr "type" "pop")
1064 (set_attr "mode" "SI")])
1066 (define_insn "popsi1"
1067 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1068 (mem:SI (reg:SI 7)))
1070 (plus:SI (reg:SI 7) (const_int 4)))]
1073 [(set_attr "type" "pop")
1074 (set_attr "mode" "SI")])
1076 (define_insn "*movsi_xor"
1077 [(set (match_operand:SI 0 "register_operand" "=r")
1078 (match_operand:SI 1 "const0_operand" "i"))
1079 (clobber (reg:CC 17))]
1080 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1081 "xor{l}\t{%0, %0|%0, %0}"
1082 [(set_attr "type" "alu1")
1083 (set_attr "mode" "SI")
1084 (set_attr "length_immediate" "0")])
1086 (define_insn "*movsi_or"
1087 [(set (match_operand:SI 0 "register_operand" "=r")
1088 (match_operand:SI 1 "immediate_operand" "i"))
1089 (clobber (reg:CC 17))]
1090 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1091 && INTVAL (operands[1]) == -1
1092 && (TARGET_PENTIUM || optimize_size)"
1094 operands[1] = constm1_rtx;
1095 return "or{l}\t{%1, %0|%0, %1}";
1097 [(set_attr "type" "alu1")
1098 (set_attr "mode" "SI")
1099 (set_attr "length_immediate" "1")])
1101 ; The first alternative is used only to compute proper length of instruction.
1102 ; Reload's algorithm does not take into account the cost of spill instructions
1103 ; needed to free register in given class, so avoid it from choosing the first
1104 ; alternative when eax is not available.
1106 (define_insn "*movsi_1"
1107 [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1108 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
1109 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1111 switch (get_attr_type (insn))
1114 if (get_attr_mode (insn) == TImode)
1115 return "movdqa\t{%1, %0|%0, %1}";
1116 return "movd\t{%1, %0|%0, %1}";
1119 if (get_attr_mode (insn) == DImode)
1120 return "movq\t{%1, %0|%0, %1}";
1121 return "movd\t{%1, %0|%0, %1}";
1124 return "lea{l}\t{%1, %0|%0, %1}";
1127 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1129 return "mov{l}\t{%1, %0|%0, %1}";
1133 (cond [(eq_attr "alternative" "4,5,6")
1134 (const_string "mmxmov")
1135 (eq_attr "alternative" "7,8,9")
1136 (const_string "ssemov")
1137 (and (ne (symbol_ref "flag_pic") (const_int 0))
1138 (match_operand:SI 1 "symbolic_operand" ""))
1139 (const_string "lea")
1141 (const_string "imov")))
1142 (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
1143 (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")])
1145 ;; Stores and loads of ax to arbitary constant address.
1146 ;; We fake an second form of instruction to force reload to load address
1147 ;; into register when rax is not available
1148 (define_insn "*movabssi_1_rex64"
1149 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1150 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1153 movabs{l}\t{%1, %P0|%P0, %1}
1154 mov{l}\t{%1, %a0|%a0, %1}
1155 movabs{l}\t{%1, %a0|%a0, %1}"
1156 [(set_attr "type" "imov")
1157 (set_attr "modrm" "0,*,*")
1158 (set_attr "length_address" "8,0,0")
1159 (set_attr "length_immediate" "0,*,*")
1160 (set_attr "memory" "store")
1161 (set_attr "mode" "SI")])
1163 (define_insn "*movabssi_2_rex64"
1164 [(set (match_operand:SI 0 "register_operand" "=a,r")
1165 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1168 movabs{l}\t{%P1, %0|%0, %P1}
1169 mov{l}\t{%a1, %0|%0, %a1}"
1170 [(set_attr "type" "imov")
1171 (set_attr "modrm" "0,*")
1172 (set_attr "length_address" "8,0")
1173 (set_attr "length_immediate" "0")
1174 (set_attr "memory" "load")
1175 (set_attr "mode" "SI")])
1177 (define_insn "*swapsi"
1178 [(set (match_operand:SI 0 "register_operand" "+r")
1179 (match_operand:SI 1 "register_operand" "+r"))
1184 [(set_attr "type" "imov")
1185 (set_attr "pent_pair" "np")
1186 (set_attr "athlon_decode" "vector")
1187 (set_attr "mode" "SI")
1188 (set_attr "modrm" "0")
1189 (set_attr "ppro_uops" "few")])
1191 (define_expand "movhi"
1192 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1193 (match_operand:HI 1 "general_operand" ""))]
1195 "ix86_expand_move (HImode, operands); DONE;")
1197 (define_insn "*pushhi2"
1198 [(set (match_operand:HI 0 "push_operand" "=<,<")
1199 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1202 push{w}\t{|WORD PTR }%1
1204 [(set_attr "type" "push")
1205 (set_attr "mode" "HI")])
1207 ;; For 64BIT abi we always round up to 8 bytes.
1208 (define_insn "*pushhi2_rex64"
1209 [(set (match_operand:HI 0 "push_operand" "=X")
1210 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1213 [(set_attr "type" "push")
1214 (set_attr "mode" "QI")])
1216 ; The first alternative is used only to compute proper length of instruction.
1217 ; Reload's algorithm does not take into account the cost of spill instructions
1218 ; needed to free register in given class, so avoid it from choosing the first
1219 ; alternative when eax is not available.
1221 (define_insn "*movhi_1"
1222 [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
1223 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1224 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1226 switch (get_attr_type (insn))
1229 /* movzwl is faster than movw on p2 due to partial word stalls,
1230 though not as fast as an aligned movl. */
1231 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1233 if (get_attr_mode (insn) == MODE_SI)
1234 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1236 return "mov{w}\t{%1, %0|%0, %1}";
1240 (cond [(and (eq_attr "alternative" "0,1")
1241 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1243 (eq (symbol_ref "TARGET_HIMODE_MATH")
1245 (const_string "imov")
1246 (and (eq_attr "alternative" "2,3,4")
1247 (match_operand:HI 1 "aligned_operand" ""))
1248 (const_string "imov")
1249 (and (ne (symbol_ref "TARGET_MOVX")
1251 (eq_attr "alternative" "0,1,3,4"))
1252 (const_string "imovx")
1254 (const_string "imov")))
1256 (cond [(eq_attr "type" "imovx")
1258 (and (eq_attr "alternative" "2,3,4")
1259 (match_operand:HI 1 "aligned_operand" ""))
1261 (and (eq_attr "alternative" "0,1")
1262 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1264 (eq (symbol_ref "TARGET_HIMODE_MATH")
1268 (const_string "HI")))
1269 (set_attr "modrm" "0,*,*,0,*,*")])
1271 ;; Stores and loads of ax to arbitary constant address.
1272 ;; We fake an second form of instruction to force reload to load address
1273 ;; into register when rax is not available
1274 (define_insn "*movabshi_1_rex64"
1275 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1276 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1279 movabs{w}\t{%1, %P0|%P0, %1}
1280 mov{w}\t{%1, %a0|%a0, %1}
1281 movabs{w}\t{%1, %a0|%a0, %1}"
1282 [(set_attr "type" "imov")
1283 (set_attr "modrm" "0,*,*")
1284 (set_attr "length_address" "8,0,0")
1285 (set_attr "length_immediate" "0,*,*")
1286 (set_attr "memory" "store")
1287 (set_attr "mode" "HI")])
1289 (define_insn "*movabshi_2_rex64"
1290 [(set (match_operand:HI 0 "register_operand" "=a,r")
1291 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1294 movabs{w}\t{%P1, %0|%0, %P1}
1295 mov{w}\t{%a1, %0|%0, %a1}"
1296 [(set_attr "type" "imov")
1297 (set_attr "modrm" "0,*")
1298 (set_attr "length_address" "8,0")
1299 (set_attr "length_immediate" "0")
1300 (set_attr "memory" "load")
1301 (set_attr "mode" "HI")])
1303 (define_insn "*swaphi_1"
1304 [(set (match_operand:HI 0 "register_operand" "+r")
1305 (match_operand:HI 1 "register_operand" "+r"))
1308 "TARGET_PARTIAL_REG_STALL"
1310 [(set_attr "type" "imov")
1311 (set_attr "pent_pair" "np")
1312 (set_attr "mode" "HI")
1313 (set_attr "modrm" "0")
1314 (set_attr "ppro_uops" "few")])
1316 (define_insn "*swaphi_2"
1317 [(set (match_operand:HI 0 "register_operand" "+r")
1318 (match_operand:HI 1 "register_operand" "+r"))
1321 "! TARGET_PARTIAL_REG_STALL"
1323 [(set_attr "type" "imov")
1324 (set_attr "pent_pair" "np")
1325 (set_attr "mode" "SI")
1326 (set_attr "modrm" "0")
1327 (set_attr "ppro_uops" "few")])
1329 (define_expand "movstricthi"
1330 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1331 (match_operand:HI 1 "general_operand" ""))]
1332 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1334 /* Don't generate memory->memory moves, go through a register */
1335 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1336 operands[1] = force_reg (HImode, operands[1]);
1339 (define_insn "*movstricthi_1"
1340 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1341 (match_operand:HI 1 "general_operand" "rn,m"))]
1342 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1343 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1344 "mov{w}\t{%1, %0|%0, %1}"
1345 [(set_attr "type" "imov")
1346 (set_attr "mode" "HI")])
1348 (define_insn "*movstricthi_xor"
1349 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1350 (match_operand:HI 1 "const0_operand" "i"))
1351 (clobber (reg:CC 17))]
1353 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1354 "xor{w}\t{%0, %0|%0, %0}"
1355 [(set_attr "type" "alu1")
1356 (set_attr "mode" "HI")
1357 (set_attr "length_immediate" "0")])
1359 (define_expand "movqi"
1360 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1361 (match_operand:QI 1 "general_operand" ""))]
1363 "ix86_expand_move (QImode, operands); DONE;")
1365 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1366 ;; "push a byte". But actually we use pushw, which has the effect
1367 ;; of rounding the amount pushed up to a halfword.
1369 (define_insn "*pushqi2"
1370 [(set (match_operand:QI 0 "push_operand" "=X,X")
1371 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1374 push{w}\t{|word ptr }%1
1376 [(set_attr "type" "push")
1377 (set_attr "mode" "HI")])
1379 ;; For 64BIT abi we always round up to 8 bytes.
1380 (define_insn "*pushqi2_rex64"
1381 [(set (match_operand:QI 0 "push_operand" "=X")
1382 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1385 [(set_attr "type" "push")
1386 (set_attr "mode" "QI")])
1388 ;; Situation is quite tricky about when to choose full sized (SImode) move
1389 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1390 ;; partial register dependency machines (such as AMD Athlon), where QImode
1391 ;; moves issue extra dependency and for partial register stalls machines
1392 ;; that don't use QImode patterns (and QImode move cause stall on the next
1395 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1396 ;; register stall machines with, where we use QImode instructions, since
1397 ;; partial register stall can be caused there. Then we use movzx.
1398 (define_insn "*movqi_1"
1399 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1400 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1401 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1403 switch (get_attr_type (insn))
1406 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1408 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1410 if (get_attr_mode (insn) == MODE_SI)
1411 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1413 return "mov{b}\t{%1, %0|%0, %1}";
1417 (cond [(and (eq_attr "alternative" "3")
1418 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1420 (eq (symbol_ref "TARGET_QIMODE_MATH")
1422 (const_string "imov")
1423 (eq_attr "alternative" "3,5")
1424 (const_string "imovx")
1425 (and (ne (symbol_ref "TARGET_MOVX")
1427 (eq_attr "alternative" "2"))
1428 (const_string "imovx")
1430 (const_string "imov")))
1432 (cond [(eq_attr "alternative" "3,4,5")
1434 (eq_attr "alternative" "6")
1436 (eq_attr "type" "imovx")
1438 (and (eq_attr "type" "imov")
1439 (and (eq_attr "alternative" "0,1,2")
1440 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1443 ;; Avoid partial register stalls when not using QImode arithmetic
1444 (and (eq_attr "type" "imov")
1445 (and (eq_attr "alternative" "0,1,2")
1446 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1448 (eq (symbol_ref "TARGET_QIMODE_MATH")
1452 (const_string "QI")))])
1454 (define_expand "reload_outqi"
1455 [(parallel [(match_operand:QI 0 "" "=m")
1456 (match_operand:QI 1 "register_operand" "r")
1457 (match_operand:QI 2 "register_operand" "=&q")])]
1461 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1463 if (reg_overlap_mentioned_p (op2, op0))
1465 if (! q_regs_operand (op1, QImode))
1467 emit_insn (gen_movqi (op2, op1));
1470 emit_insn (gen_movqi (op0, op1));
1474 (define_insn "*swapqi"
1475 [(set (match_operand:QI 0 "register_operand" "+r")
1476 (match_operand:QI 1 "register_operand" "+r"))
1481 [(set_attr "type" "imov")
1482 (set_attr "pent_pair" "np")
1483 (set_attr "mode" "QI")
1484 (set_attr "modrm" "0")
1485 (set_attr "ppro_uops" "few")])
1487 (define_expand "movstrictqi"
1488 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1489 (match_operand:QI 1 "general_operand" ""))]
1490 "! TARGET_PARTIAL_REG_STALL"
1492 /* Don't generate memory->memory moves, go through a register. */
1493 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1494 operands[1] = force_reg (QImode, operands[1]);
1497 (define_insn "*movstrictqi_1"
1498 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1499 (match_operand:QI 1 "general_operand" "*qn,m"))]
1500 "! TARGET_PARTIAL_REG_STALL
1501 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1502 "mov{b}\t{%1, %0|%0, %1}"
1503 [(set_attr "type" "imov")
1504 (set_attr "mode" "QI")])
1506 (define_insn "*movstrictqi_xor"
1507 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1508 (match_operand:QI 1 "const0_operand" "i"))
1509 (clobber (reg:CC 17))]
1510 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1511 "xor{b}\t{%0, %0|%0, %0}"
1512 [(set_attr "type" "alu1")
1513 (set_attr "mode" "QI")
1514 (set_attr "length_immediate" "0")])
1516 (define_insn "*movsi_extv_1"
1517 [(set (match_operand:SI 0 "register_operand" "=R")
1518 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1522 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1523 [(set_attr "type" "imovx")
1524 (set_attr "mode" "SI")])
1526 (define_insn "*movhi_extv_1"
1527 [(set (match_operand:HI 0 "register_operand" "=R")
1528 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1532 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1533 [(set_attr "type" "imovx")
1534 (set_attr "mode" "SI")])
1536 (define_insn "*movqi_extv_1"
1537 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1538 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1543 switch (get_attr_type (insn))
1546 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1548 return "mov{b}\t{%h1, %0|%0, %h1}";
1552 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1553 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1554 (ne (symbol_ref "TARGET_MOVX")
1556 (const_string "imovx")
1557 (const_string "imov")))
1559 (if_then_else (eq_attr "type" "imovx")
1561 (const_string "QI")))])
1563 (define_insn "*movqi_extv_1_rex64"
1564 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1565 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1570 switch (get_attr_type (insn))
1573 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1575 return "mov{b}\t{%h1, %0|%0, %h1}";
1579 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1580 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1581 (ne (symbol_ref "TARGET_MOVX")
1583 (const_string "imovx")
1584 (const_string "imov")))
1586 (if_then_else (eq_attr "type" "imovx")
1588 (const_string "QI")))])
1590 ;; Stores and loads of ax to arbitary constant address.
1591 ;; We fake an second form of instruction to force reload to load address
1592 ;; into register when rax is not available
1593 (define_insn "*movabsqi_1_rex64"
1594 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1595 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
1598 movabs{b}\t{%1, %P0|%P0, %1}
1599 mov{b}\t{%1, %a0|%a0, %1}
1600 movabs{b}\t{%1, %a0|%a0, %1}"
1601 [(set_attr "type" "imov")
1602 (set_attr "modrm" "0,*,*")
1603 (set_attr "length_address" "8,0,0")
1604 (set_attr "length_immediate" "0,*,*")
1605 (set_attr "memory" "store")
1606 (set_attr "mode" "QI")])
1608 (define_insn "*movabsqi_2_rex64"
1609 [(set (match_operand:QI 0 "register_operand" "=a,r")
1610 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1613 movabs{b}\t{%P1, %0|%0, %P1}
1614 mov{b}\t{%a1, %0|%0, %a1}"
1615 [(set_attr "type" "imov")
1616 (set_attr "modrm" "0,*")
1617 (set_attr "length_address" "8,0")
1618 (set_attr "length_immediate" "0")
1619 (set_attr "memory" "load")
1620 (set_attr "mode" "QI")])
1622 (define_insn "*movsi_extzv_1"
1623 [(set (match_operand:SI 0 "register_operand" "=R")
1624 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1628 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1629 [(set_attr "type" "imovx")
1630 (set_attr "mode" "SI")])
1632 (define_insn "*movqi_extzv_2"
1633 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1634 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1639 switch (get_attr_type (insn))
1642 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1644 return "mov{b}\t{%h1, %0|%0, %h1}";
1648 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1649 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1650 (ne (symbol_ref "TARGET_MOVX")
1652 (const_string "imovx")
1653 (const_string "imov")))
1655 (if_then_else (eq_attr "type" "imovx")
1657 (const_string "QI")))])
1659 (define_insn "*movqi_extzv_2_rex64"
1660 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1661 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1666 switch (get_attr_type (insn))
1669 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1671 return "mov{b}\t{%h1, %0|%0, %h1}";
1675 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1676 (ne (symbol_ref "TARGET_MOVX")
1678 (const_string "imovx")
1679 (const_string "imov")))
1681 (if_then_else (eq_attr "type" "imovx")
1683 (const_string "QI")))])
1685 (define_insn "movsi_insv_1"
1686 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1689 (match_operand:SI 1 "general_operand" "Qmn"))]
1691 "mov{b}\t{%b1, %h0|%h0, %b1}"
1692 [(set_attr "type" "imov")
1693 (set_attr "mode" "QI")])
1695 (define_insn "*movsi_insv_1_rex64"
1696 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1699 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1701 "mov{b}\t{%b1, %h0|%h0, %b1}"
1702 [(set_attr "type" "imov")
1703 (set_attr "mode" "QI")])
1705 (define_insn "*movqi_insv_2"
1706 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1709 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1713 "mov{b}\t{%h1, %h0|%h0, %h1}"
1714 [(set_attr "type" "imov")
1715 (set_attr "mode" "QI")])
1717 (define_expand "movdi"
1718 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1719 (match_operand:DI 1 "general_operand" ""))]
1721 "ix86_expand_move (DImode, operands); DONE;")
1723 (define_insn "*pushdi"
1724 [(set (match_operand:DI 0 "push_operand" "=<")
1725 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1729 (define_insn "pushdi2_rex64"
1730 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1731 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1736 [(set_attr "type" "push,multi")
1737 (set_attr "mode" "DI")])
1739 ;; Convert impossible pushes of immediate to existing instructions.
1740 ;; First try to get scratch register and go through it. In case this
1741 ;; fails, push sign extended lower part first and then overwrite
1742 ;; upper part by 32bit move.
1744 [(match_scratch:DI 2 "r")
1745 (set (match_operand:DI 0 "push_operand" "")
1746 (match_operand:DI 1 "immediate_operand" ""))]
1747 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1748 && !x86_64_immediate_operand (operands[1], DImode)"
1749 [(set (match_dup 2) (match_dup 1))
1750 (set (match_dup 0) (match_dup 2))]
1753 ;; We need to define this as both peepholer and splitter for case
1754 ;; peephole2 pass is not run.
1756 [(set (match_operand:DI 0 "push_operand" "")
1757 (match_operand:DI 1 "immediate_operand" ""))]
1758 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1759 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1760 [(set (match_dup 0) (match_dup 1))
1761 (set (match_dup 2) (match_dup 3))]
1762 "split_di (operands + 1, 1, operands + 2, operands + 3);
1763 operands[1] = gen_lowpart (DImode, operands[2]);
1764 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1769 [(set (match_operand:DI 0 "push_operand" "")
1770 (match_operand:DI 1 "immediate_operand" ""))]
1771 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1772 && !symbolic_operand (operands[1], DImode)
1773 && !x86_64_immediate_operand (operands[1], DImode)"
1774 [(set (match_dup 0) (match_dup 1))
1775 (set (match_dup 2) (match_dup 3))]
1776 "split_di (operands + 1, 1, operands + 2, operands + 3);
1777 operands[1] = gen_lowpart (DImode, operands[2]);
1778 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1782 (define_insn "*pushdi2_prologue_rex64"
1783 [(set (match_operand:DI 0 "push_operand" "=<")
1784 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1785 (clobber (mem:BLK (scratch)))]
1788 [(set_attr "type" "push")
1789 (set_attr "mode" "DI")])
1791 (define_insn "*popdi1_epilogue_rex64"
1792 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1793 (mem:DI (reg:DI 7)))
1795 (plus:DI (reg:DI 7) (const_int 8)))
1796 (clobber (mem:BLK (scratch)))]
1799 [(set_attr "type" "pop")
1800 (set_attr "mode" "DI")])
1802 (define_insn "popdi1"
1803 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1804 (mem:DI (reg:DI 7)))
1806 (plus:DI (reg:DI 7) (const_int 8)))]
1809 [(set_attr "type" "pop")
1810 (set_attr "mode" "DI")])
1812 (define_insn "*movdi_xor_rex64"
1813 [(set (match_operand:DI 0 "register_operand" "=r")
1814 (match_operand:DI 1 "const0_operand" "i"))
1815 (clobber (reg:CC 17))]
1816 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1817 && reload_completed"
1818 "xor{l}\t{%k0, %k0|%k0, %k0}"
1819 [(set_attr "type" "alu1")
1820 (set_attr "mode" "SI")
1821 (set_attr "length_immediate" "0")])
1823 (define_insn "*movdi_or_rex64"
1824 [(set (match_operand:DI 0 "register_operand" "=r")
1825 (match_operand:DI 1 "const_int_operand" "i"))
1826 (clobber (reg:CC 17))]
1827 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1829 && GET_CODE (operands[1]) == CONST_INT
1830 && INTVAL (operands[1]) == -1"
1832 operands[1] = constm1_rtx;
1833 return "or{q}\t{%1, %0|%0, %1}";
1835 [(set_attr "type" "alu1")
1836 (set_attr "mode" "DI")
1837 (set_attr "length_immediate" "1")])
1839 (define_insn "*movdi_2"
1840 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1841 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1843 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1847 movq\t{%1, %0|%0, %1}
1848 movq\t{%1, %0|%0, %1}
1849 movq\t{%1, %0|%0, %1}
1850 movdqa\t{%1, %0|%0, %1}
1851 movq\t{%1, %0|%0, %1}"
1852 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1853 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1856 [(set (match_operand:DI 0 "push_operand" "")
1857 (match_operand:DI 1 "general_operand" ""))]
1858 "!TARGET_64BIT && reload_completed
1859 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1861 "ix86_split_long_move (operands); DONE;")
1863 ;; %%% This multiword shite has got to go.
1865 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1866 (match_operand:DI 1 "general_operand" ""))]
1867 "!TARGET_64BIT && reload_completed
1868 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1869 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1871 "ix86_split_long_move (operands); DONE;")
1873 (define_insn "*movdi_1_rex64"
1874 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
1875 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
1877 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1879 switch (get_attr_type (insn))
1882 if (register_operand (operands[0], DImode)
1883 && register_operand (operands[1], DImode))
1884 return "movdqa\t{%1, %0|%0, %1}";
1887 return "movq\t{%1, %0|%0, %1}";
1891 return "lea{q}\t{%a1, %0|%0, %a1}";
1893 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1895 if (get_attr_mode (insn) == MODE_SI)
1896 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1897 else if (which_alternative == 2)
1898 return "movabs{q}\t{%1, %0|%0, %1}";
1900 return "mov{q}\t{%1, %0|%0, %1}";
1904 (cond [(eq_attr "alternative" "5,6")
1905 (const_string "mmxmov")
1906 (eq_attr "alternative" "7,8")
1907 (const_string "ssemov")
1908 (eq_attr "alternative" "4")
1909 (const_string "multi")
1910 (and (ne (symbol_ref "flag_pic") (const_int 0))
1911 (match_operand:DI 1 "symbolic_operand" ""))
1912 (const_string "lea")
1914 (const_string "imov")))
1915 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
1916 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
1917 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
1919 ;; Stores and loads of ax to arbitary constant address.
1920 ;; We fake an second form of instruction to force reload to load address
1921 ;; into register when rax is not available
1922 (define_insn "*movabsdi_1_rex64"
1923 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1924 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
1927 movabs{q}\t{%1, %P0|%P0, %1}
1928 mov{q}\t{%1, %a0|%a0, %1}
1929 movabs{q}\t{%1, %a0|%a0, %1}"
1930 [(set_attr "type" "imov")
1931 (set_attr "modrm" "0,*,*")
1932 (set_attr "length_address" "8,0,0")
1933 (set_attr "length_immediate" "0,*,*")
1934 (set_attr "memory" "store")
1935 (set_attr "mode" "DI")])
1937 (define_insn "*movabsdi_2_rex64"
1938 [(set (match_operand:DI 0 "register_operand" "=a,r")
1939 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1942 movabs{q}\t{%P1, %0|%0, %P1}
1943 mov{q}\t{%a1, %0|%0, %a1}"
1944 [(set_attr "type" "imov")
1945 (set_attr "modrm" "0,*")
1946 (set_attr "length_address" "8,0")
1947 (set_attr "length_immediate" "0")
1948 (set_attr "memory" "load")
1949 (set_attr "mode" "DI")])
1951 ;; Convert impossible stores of immediate to existing instructions.
1952 ;; First try to get scratch register and go through it. In case this
1953 ;; fails, move by 32bit parts.
1955 [(match_scratch:DI 2 "r")
1956 (set (match_operand:DI 0 "memory_operand" "")
1957 (match_operand:DI 1 "immediate_operand" ""))]
1958 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1959 && !x86_64_immediate_operand (operands[1], DImode)"
1960 [(set (match_dup 2) (match_dup 1))
1961 (set (match_dup 0) (match_dup 2))]
1964 ;; We need to define this as both peepholer and splitter for case
1965 ;; peephole2 pass is not run.
1967 [(set (match_operand:DI 0 "memory_operand" "")
1968 (match_operand:DI 1 "immediate_operand" ""))]
1969 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1970 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1971 [(set (match_dup 2) (match_dup 3))
1972 (set (match_dup 4) (match_dup 5))]
1973 "split_di (operands, 2, operands + 2, operands + 4);")
1976 [(set (match_operand:DI 0 "memory_operand" "")
1977 (match_operand:DI 1 "immediate_operand" ""))]
1978 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1979 && !symbolic_operand (operands[1], DImode)
1980 && !x86_64_immediate_operand (operands[1], DImode)"
1981 [(set (match_dup 2) (match_dup 3))
1982 (set (match_dup 4) (match_dup 5))]
1983 "split_di (operands, 2, operands + 2, operands + 4);")
1985 (define_insn "*swapdi_rex64"
1986 [(set (match_operand:DI 0 "register_operand" "+r")
1987 (match_operand:DI 1 "register_operand" "+r"))
1992 [(set_attr "type" "imov")
1993 (set_attr "pent_pair" "np")
1994 (set_attr "athlon_decode" "vector")
1995 (set_attr "mode" "DI")
1996 (set_attr "modrm" "0")
1997 (set_attr "ppro_uops" "few")])
2000 (define_expand "movsf"
2001 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2002 (match_operand:SF 1 "general_operand" ""))]
2004 "ix86_expand_move (SFmode, operands); DONE;")
2006 (define_insn "*pushsf"
2007 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2008 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2011 switch (which_alternative)
2014 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2015 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2016 operands[2] = stack_pointer_rtx;
2017 operands[3] = GEN_INT (4);
2018 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2019 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2021 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2024 return "push{l}\t%1";
2032 [(set_attr "type" "multi,push,multi")
2033 (set_attr "mode" "SF,SI,SF")])
2035 (define_insn "*pushsf_rex64"
2036 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2037 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2040 switch (which_alternative)
2043 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2044 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2045 operands[2] = stack_pointer_rtx;
2046 operands[3] = GEN_INT (8);
2047 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2048 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2050 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2053 return "push{q}\t%q1";
2062 [(set_attr "type" "multi,push,multi")
2063 (set_attr "mode" "SF,DI,SF")])
2066 [(set (match_operand:SF 0 "push_operand" "")
2067 (match_operand:SF 1 "memory_operand" ""))]
2069 && GET_CODE (operands[1]) == MEM
2070 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2071 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2074 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2077 ;; %%% Kill this when call knows how to work this out.
2079 [(set (match_operand:SF 0 "push_operand" "")
2080 (match_operand:SF 1 "register_operand" ""))]
2081 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2082 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2083 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2086 [(set (match_operand:SF 0 "push_operand" "")
2087 (match_operand:SF 1 "register_operand" ""))]
2088 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2089 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2090 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2092 (define_insn "*movsf_1"
2093 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2094 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))]
2095 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2096 && (reload_in_progress || reload_completed
2097 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2098 || GET_CODE (operands[1]) != CONST_DOUBLE
2099 || memory_operand (operands[0], SFmode))"
2101 switch (which_alternative)
2104 if (REG_P (operands[1])
2105 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2107 else if (STACK_TOP_P (operands[0]))
2108 return "fld%z1\t%y1";
2113 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2114 return "fstp%z0\t%y0";
2116 return "fst%z0\t%y0";
2119 switch (standard_80387_constant_p (operands[1]))
2130 return "mov{l}\t{%1, %0|%0, %1}";
2132 if (TARGET_SSE2 && !TARGET_ATHLON)
2133 return "pxor\t%0, %0";
2135 return "xorps\t%0, %0";
2137 if (TARGET_PARTIAL_REG_DEPENDENCY)
2138 return "movaps\t{%1, %0|%0, %1}";
2140 return "movss\t{%1, %0|%0, %1}";
2143 return "movss\t{%1, %0|%0, %1}";
2147 return "movd\t{%1, %0|%0, %1}";
2150 return "movq\t{%1, %0|%0, %1}";
2156 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2157 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
2159 (define_insn "*swapsf"
2160 [(set (match_operand:SF 0 "register_operand" "+f")
2161 (match_operand:SF 1 "register_operand" "+f"))
2164 "reload_completed || !TARGET_SSE"
2166 if (STACK_TOP_P (operands[0]))
2171 [(set_attr "type" "fxch")
2172 (set_attr "mode" "SF")])
2174 (define_expand "movdf"
2175 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2176 (match_operand:DF 1 "general_operand" ""))]
2178 "ix86_expand_move (DFmode, operands); DONE;")
2180 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2181 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2182 ;; On the average, pushdf using integers can be still shorter. Allow this
2183 ;; pattern for optimize_size too.
2185 (define_insn "*pushdf_nointeger"
2186 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2187 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2188 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2190 switch (which_alternative)
2193 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2194 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2195 operands[2] = stack_pointer_rtx;
2196 operands[3] = GEN_INT (8);
2197 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2198 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2200 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2211 [(set_attr "type" "multi")
2212 (set_attr "mode" "DF,SI,SI,DF")])
2214 (define_insn "*pushdf_integer"
2215 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2216 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2217 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2219 switch (which_alternative)
2222 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2223 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2224 operands[2] = stack_pointer_rtx;
2225 operands[3] = GEN_INT (8);
2227 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2228 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2230 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2232 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2233 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2235 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2246 [(set_attr "type" "multi")
2247 (set_attr "mode" "DF,SI,DF")])
2249 ;; %%% Kill this when call knows how to work this out.
2251 [(set (match_operand:DF 0 "push_operand" "")
2252 (match_operand:DF 1 "register_operand" ""))]
2253 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2254 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2255 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2259 [(set (match_operand:DF 0 "push_operand" "")
2260 (match_operand:DF 1 "register_operand" ""))]
2261 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2262 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2263 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2267 [(set (match_operand:DF 0 "push_operand" "")
2268 (match_operand:DF 1 "general_operand" ""))]
2271 "ix86_split_long_move (operands); DONE;")
2273 ;; Moving is usually shorter when only FP registers are used. This separate
2274 ;; movdf pattern avoids the use of integer registers for FP operations
2275 ;; when optimizing for size.
2277 (define_insn "*movdf_nointeger"
2278 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2279 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2280 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2281 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2282 && (reload_in_progress || reload_completed
2283 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2284 || GET_CODE (operands[1]) != CONST_DOUBLE
2285 || memory_operand (operands[0], DFmode))"
2287 switch (which_alternative)
2290 if (REG_P (operands[1])
2291 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2293 else if (STACK_TOP_P (operands[0]))
2294 return "fld%z1\t%y1";
2299 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2300 return "fstp%z0\t%y0";
2302 return "fst%z0\t%y0";
2305 switch (standard_80387_constant_p (operands[1]))
2319 return "xorpd\t%0, %0";
2321 return "pxor\t%0, %0";
2323 if (TARGET_PARTIAL_REG_DEPENDENCY)
2324 return "movapd\t{%1, %0|%0, %1}";
2326 return "movsd\t{%1, %0|%0, %1}";
2329 return "movsd\t{%1, %0|%0, %1}";
2335 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2336 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2338 (define_insn "*movdf_integer"
2339 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2340 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2341 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2342 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2343 && (reload_in_progress || reload_completed
2344 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2345 || GET_CODE (operands[1]) != CONST_DOUBLE
2346 || memory_operand (operands[0], DFmode))"
2348 switch (which_alternative)
2351 if (REG_P (operands[1])
2352 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2354 else if (STACK_TOP_P (operands[0]))
2355 return "fld%z1\t%y1";
2360 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2361 return "fstp%z0\t%y0";
2363 return "fst%z0\t%y0";
2366 switch (standard_80387_constant_p (operands[1]))
2381 return "xorpd\t%0, %0";
2383 return "pxor\t%0, %0";
2385 if (TARGET_PARTIAL_REG_DEPENDENCY)
2386 return "movapd\t{%1, %0|%0, %1}";
2388 return "movsd\t{%1, %0|%0, %1}";
2391 return "movsd\t{%1, %0|%0, %1}";
2397 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2398 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2401 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2402 (match_operand:DF 1 "general_operand" ""))]
2404 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2405 && ! (ANY_FP_REG_P (operands[0]) ||
2406 (GET_CODE (operands[0]) == SUBREG
2407 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2408 && ! (ANY_FP_REG_P (operands[1]) ||
2409 (GET_CODE (operands[1]) == SUBREG
2410 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2412 "ix86_split_long_move (operands); DONE;")
2414 (define_insn "*swapdf"
2415 [(set (match_operand:DF 0 "register_operand" "+f")
2416 (match_operand:DF 1 "register_operand" "+f"))
2419 "reload_completed || !TARGET_SSE2"
2421 if (STACK_TOP_P (operands[0]))
2426 [(set_attr "type" "fxch")
2427 (set_attr "mode" "DF")])
2429 (define_expand "movxf"
2430 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2431 (match_operand:XF 1 "general_operand" ""))]
2433 "ix86_expand_move (XFmode, operands); DONE;")
2435 (define_expand "movtf"
2436 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2437 (match_operand:TF 1 "general_operand" ""))]
2439 "ix86_expand_move (TFmode, operands); DONE;")
2441 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2442 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
2443 ;; Pushing using integer instructions is longer except for constants
2444 ;; and direct memory references.
2445 ;; (assuming that any given constant is pushed only once, but this ought to be
2446 ;; handled elsewhere).
2448 (define_insn "*pushxf_nointeger"
2449 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2450 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2451 "!TARGET_64BIT && optimize_size"
2453 switch (which_alternative)
2456 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2457 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2458 operands[2] = stack_pointer_rtx;
2459 operands[3] = GEN_INT (12);
2460 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2461 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2463 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2473 [(set_attr "type" "multi")
2474 (set_attr "mode" "XF,SI,SI")])
2476 (define_insn "*pushtf_nointeger"
2477 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2478 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2481 switch (which_alternative)
2484 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2485 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2486 operands[2] = stack_pointer_rtx;
2487 operands[3] = GEN_INT (16);
2488 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2489 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2491 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2501 [(set_attr "type" "multi")
2502 (set_attr "mode" "XF,SI,SI")])
2504 (define_insn "*pushxf_integer"
2505 [(set (match_operand:XF 0 "push_operand" "=<,<")
2506 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2507 "!TARGET_64BIT && !optimize_size"
2509 switch (which_alternative)
2512 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2513 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2514 operands[2] = stack_pointer_rtx;
2515 operands[3] = GEN_INT (12);
2516 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2517 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2519 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2528 [(set_attr "type" "multi")
2529 (set_attr "mode" "XF,SI")])
2531 (define_insn "*pushtf_integer"
2532 [(set (match_operand:TF 0 "push_operand" "=<,<")
2533 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2536 switch (which_alternative)
2539 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2540 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2541 operands[2] = stack_pointer_rtx;
2542 operands[3] = GEN_INT (16);
2544 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2545 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2547 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2549 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2550 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2552 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2561 [(set_attr "type" "multi")
2562 (set_attr "mode" "XF,SI")])
2565 [(set (match_operand 0 "push_operand" "")
2566 (match_operand 1 "general_operand" ""))]
2568 && (GET_MODE (operands[0]) == XFmode
2569 || GET_MODE (operands[0]) == TFmode
2570 || GET_MODE (operands[0]) == DFmode)
2571 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
2573 "ix86_split_long_move (operands); DONE;")
2576 [(set (match_operand:XF 0 "push_operand" "")
2577 (match_operand:XF 1 "register_operand" ""))]
2578 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2579 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2580 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2583 [(set (match_operand:TF 0 "push_operand" "")
2584 (match_operand:TF 1 "register_operand" ""))]
2585 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2586 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2587 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2590 [(set (match_operand:TF 0 "push_operand" "")
2591 (match_operand:TF 1 "register_operand" ""))]
2592 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2593 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2594 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2596 ;; Do not use integer registers when optimizing for size
2597 (define_insn "*movxf_nointeger"
2598 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2599 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2602 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2603 && (reload_in_progress || reload_completed
2604 || GET_CODE (operands[1]) != CONST_DOUBLE
2605 || memory_operand (operands[0], XFmode))"
2607 switch (which_alternative)
2610 if (REG_P (operands[1])
2611 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2613 else if (STACK_TOP_P (operands[0]))
2614 return "fld%z1\t%y1";
2619 /* There is no non-popping store to memory for XFmode. So if
2620 we need one, follow the store with a load. */
2621 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2622 return "fstp%z0\t%y0\;fld%z0\t%y0";
2624 return "fstp%z0\t%y0";
2627 switch (standard_80387_constant_p (operands[1]))
2641 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2642 (set_attr "mode" "XF,XF,XF,SI,SI")])
2644 (define_insn "*movtf_nointeger"
2645 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2646 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2647 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2649 && (reload_in_progress || reload_completed
2650 || GET_CODE (operands[1]) != CONST_DOUBLE
2651 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2652 || memory_operand (operands[0], TFmode))"
2654 switch (which_alternative)
2657 if (REG_P (operands[1])
2658 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2660 else if (STACK_TOP_P (operands[0]))
2661 return "fld%z1\t%y1";
2666 /* There is no non-popping store to memory for XFmode. So if
2667 we need one, follow the store with a load. */
2668 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2669 return "fstp%z0\t%y0\;fld%z0\t%y0";
2671 return "fstp%z0\t%y0";
2674 switch (standard_80387_constant_p (operands[1]))
2688 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2689 (set_attr "mode" "XF,XF,XF,SI,SI")])
2691 (define_insn "*movxf_integer"
2692 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2693 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2696 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2697 && (reload_in_progress || reload_completed
2698 || GET_CODE (operands[1]) != CONST_DOUBLE
2699 || memory_operand (operands[0], XFmode))"
2701 switch (which_alternative)
2704 if (REG_P (operands[1])
2705 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2707 else if (STACK_TOP_P (operands[0]))
2708 return "fld%z1\t%y1";
2713 /* There is no non-popping store to memory for XFmode. So if
2714 we need one, follow the store with a load. */
2715 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2716 return "fstp%z0\t%y0\;fld%z0\t%y0";
2718 return "fstp%z0\t%y0";
2721 switch (standard_80387_constant_p (operands[1]))
2735 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2736 (set_attr "mode" "XF,XF,XF,SI,SI")])
2738 (define_insn "*movtf_integer"
2739 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2740 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2741 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2743 && (reload_in_progress || reload_completed
2744 || GET_CODE (operands[1]) != CONST_DOUBLE
2745 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2746 || memory_operand (operands[0], TFmode))"
2748 switch (which_alternative)
2751 if (REG_P (operands[1])
2752 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2754 else if (STACK_TOP_P (operands[0]))
2755 return "fld%z1\t%y1";
2760 /* There is no non-popping store to memory for XFmode. So if
2761 we need one, follow the store with a load. */
2762 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2763 return "fstp%z0\t%y0\;fld%z0\t%y0";
2765 return "fstp%z0\t%y0";
2768 switch (standard_80387_constant_p (operands[1]))
2782 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2783 (set_attr "mode" "XF,XF,XF,SI,SI")])
2786 [(set (match_operand 0 "nonimmediate_operand" "")
2787 (match_operand 1 "general_operand" ""))]
2789 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2790 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
2791 && ! (ANY_FP_REG_P (operands[0]) ||
2792 (GET_CODE (operands[0]) == SUBREG
2793 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2794 && ! (ANY_FP_REG_P (operands[1]) ||
2795 (GET_CODE (operands[1]) == SUBREG
2796 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2798 "ix86_split_long_move (operands); DONE;")
2801 [(set (match_operand 0 "register_operand" "")
2802 (match_operand 1 "memory_operand" ""))]
2804 && GET_CODE (operands[1]) == MEM
2805 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
2806 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2807 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2808 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
2809 && (!(SSE_REG_P (operands[0]) ||
2810 (GET_CODE (operands[0]) == SUBREG
2811 && SSE_REG_P (SUBREG_REG (operands[0]))))
2812 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
2813 && (!(FP_REG_P (operands[0]) ||
2814 (GET_CODE (operands[0]) == SUBREG
2815 && FP_REG_P (SUBREG_REG (operands[0]))))
2816 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
2819 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2821 (define_insn "swapxf"
2822 [(set (match_operand:XF 0 "register_operand" "+f")
2823 (match_operand:XF 1 "register_operand" "+f"))
2828 if (STACK_TOP_P (operands[0]))
2833 [(set_attr "type" "fxch")
2834 (set_attr "mode" "XF")])
2836 (define_insn "swaptf"
2837 [(set (match_operand:TF 0 "register_operand" "+f")
2838 (match_operand:TF 1 "register_operand" "+f"))
2843 if (STACK_TOP_P (operands[0]))
2848 [(set_attr "type" "fxch")
2849 (set_attr "mode" "XF")])
2851 ;; Zero extension instructions
2853 (define_expand "zero_extendhisi2"
2854 [(set (match_operand:SI 0 "register_operand" "")
2855 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2858 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2860 operands[1] = force_reg (HImode, operands[1]);
2861 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2866 (define_insn "zero_extendhisi2_and"
2867 [(set (match_operand:SI 0 "register_operand" "=r")
2868 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2869 (clobber (reg:CC 17))]
2870 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2872 [(set_attr "type" "alu1")
2873 (set_attr "mode" "SI")])
2876 [(set (match_operand:SI 0 "register_operand" "")
2877 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2878 (clobber (reg:CC 17))]
2879 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2880 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2881 (clobber (reg:CC 17))])]
2884 (define_insn "*zero_extendhisi2_movzwl"
2885 [(set (match_operand:SI 0 "register_operand" "=r")
2886 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2887 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2888 "movz{wl|x}\t{%1, %0|%0, %1}"
2889 [(set_attr "type" "imovx")
2890 (set_attr "mode" "SI")])
2892 (define_expand "zero_extendqihi2"
2894 [(set (match_operand:HI 0 "register_operand" "")
2895 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2896 (clobber (reg:CC 17))])]
2900 (define_insn "*zero_extendqihi2_and"
2901 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2902 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2903 (clobber (reg:CC 17))]
2904 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2906 [(set_attr "type" "alu1")
2907 (set_attr "mode" "HI")])
2909 (define_insn "*zero_extendqihi2_movzbw_and"
2910 [(set (match_operand:HI 0 "register_operand" "=r,r")
2911 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2912 (clobber (reg:CC 17))]
2913 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2915 [(set_attr "type" "imovx,alu1")
2916 (set_attr "mode" "HI")])
2918 (define_insn "*zero_extendqihi2_movzbw"
2919 [(set (match_operand:HI 0 "register_operand" "=r")
2920 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2921 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2922 "movz{bw|x}\t{%1, %0|%0, %1}"
2923 [(set_attr "type" "imovx")
2924 (set_attr "mode" "HI")])
2926 ;; For the movzbw case strip only the clobber
2928 [(set (match_operand:HI 0 "register_operand" "")
2929 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2930 (clobber (reg:CC 17))]
2932 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2933 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
2934 [(set (match_operand:HI 0 "register_operand" "")
2935 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
2937 ;; When source and destination does not overlap, clear destination
2938 ;; first and then do the movb
2940 [(set (match_operand:HI 0 "register_operand" "")
2941 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2942 (clobber (reg:CC 17))]
2944 && ANY_QI_REG_P (operands[0])
2945 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2946 && !reg_overlap_mentioned_p (operands[0], operands[1])"
2947 [(set (match_dup 0) (const_int 0))
2948 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2949 "operands[2] = gen_lowpart (QImode, operands[0]);")
2951 ;; Rest is handled by single and.
2953 [(set (match_operand:HI 0 "register_operand" "")
2954 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
2955 (clobber (reg:CC 17))]
2957 && true_regnum (operands[0]) == true_regnum (operands[1])"
2958 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
2959 (clobber (reg:CC 17))])]
2962 (define_expand "zero_extendqisi2"
2964 [(set (match_operand:SI 0 "register_operand" "")
2965 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
2966 (clobber (reg:CC 17))])]
2970 (define_insn "*zero_extendqisi2_and"
2971 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
2972 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2973 (clobber (reg:CC 17))]
2974 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2976 [(set_attr "type" "alu1")
2977 (set_attr "mode" "SI")])
2979 (define_insn "*zero_extendqisi2_movzbw_and"
2980 [(set (match_operand:SI 0 "register_operand" "=r,r")
2981 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2982 (clobber (reg:CC 17))]
2983 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2985 [(set_attr "type" "imovx,alu1")
2986 (set_attr "mode" "SI")])
2988 (define_insn "*zero_extendqisi2_movzbw"
2989 [(set (match_operand:SI 0 "register_operand" "=r")
2990 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2991 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2992 "movz{bl|x}\t{%1, %0|%0, %1}"
2993 [(set_attr "type" "imovx")
2994 (set_attr "mode" "SI")])
2996 ;; For the movzbl case strip only the clobber
2998 [(set (match_operand:SI 0 "register_operand" "")
2999 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3000 (clobber (reg:CC 17))]
3002 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3003 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3005 (zero_extend:SI (match_dup 1)))])
3007 ;; When source and destination does not overlap, clear destination
3008 ;; first and then do the movb
3010 [(set (match_operand:SI 0 "register_operand" "")
3011 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3012 (clobber (reg:CC 17))]
3014 && ANY_QI_REG_P (operands[0])
3015 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3016 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3017 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3018 [(set (match_dup 0) (const_int 0))
3019 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3020 "operands[2] = gen_lowpart (QImode, operands[0]);")
3022 ;; Rest is handled by single and.
3024 [(set (match_operand:SI 0 "register_operand" "")
3025 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3026 (clobber (reg:CC 17))]
3028 && true_regnum (operands[0]) == true_regnum (operands[1])"
3029 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3030 (clobber (reg:CC 17))])]
3033 ;; %%% Kill me once multi-word ops are sane.
3034 (define_expand "zero_extendsidi2"
3035 [(set (match_operand:DI 0 "register_operand" "=r")
3036 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3040 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3045 (define_insn "zero_extendsidi2_32"
3046 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3047 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3048 (clobber (reg:CC 17))]
3051 [(set_attr "mode" "SI")])
3053 (define_insn "zero_extendsidi2_rex64"
3054 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3055 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3058 mov\t{%k1, %k0|%k0, %k1}
3060 [(set_attr "type" "imovx,imov")
3061 (set_attr "mode" "SI,DI")])
3064 [(set (match_operand:DI 0 "memory_operand" "")
3065 (zero_extend:DI (match_dup 0)))]
3067 [(set (match_dup 4) (const_int 0))]
3068 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3071 [(set (match_operand:DI 0 "register_operand" "")
3072 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3073 (clobber (reg:CC 17))]
3074 "!TARGET_64BIT && reload_completed
3075 && true_regnum (operands[0]) == true_regnum (operands[1])"
3076 [(set (match_dup 4) (const_int 0))]
3077 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3080 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3081 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3082 (clobber (reg:CC 17))]
3083 "!TARGET_64BIT && reload_completed"
3084 [(set (match_dup 3) (match_dup 1))
3085 (set (match_dup 4) (const_int 0))]
3086 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3088 (define_insn "zero_extendhidi2"
3089 [(set (match_operand:DI 0 "register_operand" "=r,r")
3090 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3093 movz{wl|x}\t{%1, %k0|%k0, %1}
3094 movz{wq|x}\t{%1, %0|%0, %1}"
3095 [(set_attr "type" "imovx")
3096 (set_attr "mode" "SI,DI")])
3098 (define_insn "zero_extendqidi2"
3099 [(set (match_operand:DI 0 "register_operand" "=r,r")
3100 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3103 movz{bl|x}\t{%1, %k0|%k0, %1}
3104 movz{bq|x}\t{%1, %0|%0, %1}"
3105 [(set_attr "type" "imovx")
3106 (set_attr "mode" "SI,DI")])
3108 ;; Sign extension instructions
3110 (define_expand "extendsidi2"
3111 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3112 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3113 (clobber (reg:CC 17))
3114 (clobber (match_scratch:SI 2 ""))])]
3119 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3124 (define_insn "*extendsidi2_1"
3125 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3126 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3127 (clobber (reg:CC 17))
3128 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3132 (define_insn "extendsidi2_rex64"
3133 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3134 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3138 movs{lq|x}\t{%1,%0|%0, %1}"
3139 [(set_attr "type" "imovx")
3140 (set_attr "mode" "DI")
3141 (set_attr "prefix_0f" "0")
3142 (set_attr "modrm" "0,1")])
3144 (define_insn "extendhidi2"
3145 [(set (match_operand:DI 0 "register_operand" "=r")
3146 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3148 "movs{wq|x}\t{%1,%0|%0, %1}"
3149 [(set_attr "type" "imovx")
3150 (set_attr "mode" "DI")])
3152 (define_insn "extendqidi2"
3153 [(set (match_operand:DI 0 "register_operand" "=r")
3154 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3156 "movs{bq|x}\t{%1,%0|%0, %1}"
3157 [(set_attr "type" "imovx")
3158 (set_attr "mode" "DI")])
3160 ;; Extend to memory case when source register does die.
3162 [(set (match_operand:DI 0 "memory_operand" "")
3163 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3164 (clobber (reg:CC 17))
3165 (clobber (match_operand:SI 2 "register_operand" ""))]
3167 && dead_or_set_p (insn, operands[1])
3168 && !reg_mentioned_p (operands[1], operands[0]))"
3169 [(set (match_dup 3) (match_dup 1))
3170 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3171 (clobber (reg:CC 17))])
3172 (set (match_dup 4) (match_dup 1))]
3173 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3175 ;; Extend to memory case when source register does not die.
3177 [(set (match_operand:DI 0 "memory_operand" "")
3178 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3179 (clobber (reg:CC 17))
3180 (clobber (match_operand:SI 2 "register_operand" ""))]
3184 split_di (&operands[0], 1, &operands[3], &operands[4]);
3186 emit_move_insn (operands[3], operands[1]);
3188 /* Generate a cltd if possible and doing so it profitable. */
3189 if (true_regnum (operands[1]) == 0
3190 && true_regnum (operands[2]) == 1
3191 && (optimize_size || TARGET_USE_CLTD))
3193 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3197 emit_move_insn (operands[2], operands[1]);
3198 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3200 emit_move_insn (operands[4], operands[2]);
3204 ;; Extend to register case. Optimize case where source and destination
3205 ;; registers match and cases where we can use cltd.
3207 [(set (match_operand:DI 0 "register_operand" "")
3208 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3209 (clobber (reg:CC 17))
3210 (clobber (match_scratch:SI 2 ""))]
3214 split_di (&operands[0], 1, &operands[3], &operands[4]);
3216 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3217 emit_move_insn (operands[3], operands[1]);
3219 /* Generate a cltd if possible and doing so it profitable. */
3220 if (true_regnum (operands[3]) == 0
3221 && (optimize_size || TARGET_USE_CLTD))
3223 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3227 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3228 emit_move_insn (operands[4], operands[1]);
3230 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3234 (define_insn "extendhisi2"
3235 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3236 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3239 switch (get_attr_prefix_0f (insn))
3242 return "{cwtl|cwde}";
3244 return "movs{wl|x}\t{%1,%0|%0, %1}";
3247 [(set_attr "type" "imovx")
3248 (set_attr "mode" "SI")
3249 (set (attr "prefix_0f")
3250 ;; movsx is short decodable while cwtl is vector decoded.
3251 (if_then_else (and (eq_attr "cpu" "!k6")
3252 (eq_attr "alternative" "0"))
3254 (const_string "1")))
3256 (if_then_else (eq_attr "prefix_0f" "0")
3258 (const_string "1")))])
3260 (define_insn "*extendhisi2_zext"
3261 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3263 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3266 switch (get_attr_prefix_0f (insn))
3269 return "{cwtl|cwde}";
3271 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3274 [(set_attr "type" "imovx")
3275 (set_attr "mode" "SI")
3276 (set (attr "prefix_0f")
3277 ;; movsx is short decodable while cwtl is vector decoded.
3278 (if_then_else (and (eq_attr "cpu" "!k6")
3279 (eq_attr "alternative" "0"))
3281 (const_string "1")))
3283 (if_then_else (eq_attr "prefix_0f" "0")
3285 (const_string "1")))])
3287 (define_insn "extendqihi2"
3288 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3289 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3292 switch (get_attr_prefix_0f (insn))
3295 return "{cbtw|cbw}";
3297 return "movs{bw|x}\t{%1,%0|%0, %1}";
3300 [(set_attr "type" "imovx")
3301 (set_attr "mode" "HI")
3302 (set (attr "prefix_0f")
3303 ;; movsx is short decodable while cwtl is vector decoded.
3304 (if_then_else (and (eq_attr "cpu" "!k6")
3305 (eq_attr "alternative" "0"))
3307 (const_string "1")))
3309 (if_then_else (eq_attr "prefix_0f" "0")
3311 (const_string "1")))])
3313 (define_insn "extendqisi2"
3314 [(set (match_operand:SI 0 "register_operand" "=r")
3315 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3317 "movs{bl|x}\t{%1,%0|%0, %1}"
3318 [(set_attr "type" "imovx")
3319 (set_attr "mode" "SI")])
3321 (define_insn "*extendqisi2_zext"
3322 [(set (match_operand:DI 0 "register_operand" "=r")
3324 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3326 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3327 [(set_attr "type" "imovx")
3328 (set_attr "mode" "SI")])
3330 ;; Conversions between float and double.
3332 ;; These are all no-ops in the model used for the 80387. So just
3335 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3336 (define_insn "*dummy_extendsfdf2"
3337 [(set (match_operand:DF 0 "push_operand" "=<")
3338 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3343 [(set (match_operand:DF 0 "push_operand" "")
3344 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3345 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3346 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3347 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3350 [(set (match_operand:DF 0 "push_operand" "")
3351 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3352 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3353 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3354 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3356 (define_insn "*dummy_extendsfxf2"
3357 [(set (match_operand:XF 0 "push_operand" "=<")
3358 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3363 [(set (match_operand:XF 0 "push_operand" "")
3364 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
3365 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3366 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3367 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3369 (define_insn "*dummy_extendsftf2"
3370 [(set (match_operand:TF 0 "push_operand" "=<")
3371 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3376 [(set (match_operand:TF 0 "push_operand" "")
3377 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3378 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3379 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3380 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3383 [(set (match_operand:TF 0 "push_operand" "")
3384 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3385 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3386 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3387 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3389 (define_insn "*dummy_extenddfxf2"
3390 [(set (match_operand:XF 0 "push_operand" "=<")
3391 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3396 [(set (match_operand:XF 0 "push_operand" "")
3397 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
3398 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3399 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3400 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3402 (define_insn "*dummy_extenddftf2"
3403 [(set (match_operand:TF 0 "push_operand" "=<")
3404 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3409 [(set (match_operand:TF 0 "push_operand" "")
3410 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
3411 "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3412 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3413 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3416 [(set (match_operand:TF 0 "push_operand" "")
3417 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
3418 "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
3419 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3420 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3422 (define_expand "extendsfdf2"
3423 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3424 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3425 "TARGET_80387 || TARGET_SSE2"
3427 /* ??? Needed for compress_float_constant since all fp constants
3428 are LEGITIMATE_CONSTANT_P. */
3429 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3430 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3431 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3432 operands[1] = force_reg (SFmode, operands[1]);
3435 (define_insn "*extendsfdf2_1"
3436 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3437 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3438 "(TARGET_80387 || TARGET_SSE2)
3439 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3441 switch (which_alternative)
3444 if (REG_P (operands[1])
3445 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3447 else if (STACK_TOP_P (operands[0]))
3448 return "fld%z1\t%y1";
3453 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3454 return "fstp%z0\t%y0";
3457 return "fst%z0\t%y0";
3459 return "cvtss2sd\t{%1, %0|%0, %1}";
3465 [(set_attr "type" "fmov,fmov,ssecvt")
3466 (set_attr "mode" "SF,XF,DF")])
3468 (define_insn "*extendsfdf2_1_sse_only"
3469 [(set (match_operand:DF 0 "register_operand" "=Y")
3470 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3471 "!TARGET_80387 && TARGET_SSE2
3472 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3473 "cvtss2sd\t{%1, %0|%0, %1}"
3474 [(set_attr "type" "ssecvt")
3475 (set_attr "mode" "DF")])
3477 (define_expand "extendsfxf2"
3478 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3479 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3480 "!TARGET_64BIT && TARGET_80387"
3482 /* ??? Needed for compress_float_constant since all fp constants
3483 are LEGITIMATE_CONSTANT_P. */
3484 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3485 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3486 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3487 operands[1] = force_reg (SFmode, operands[1]);
3490 (define_insn "*extendsfxf2_1"
3491 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3492 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3493 "!TARGET_64BIT && TARGET_80387
3494 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3496 switch (which_alternative)
3499 if (REG_P (operands[1])
3500 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3502 else if (STACK_TOP_P (operands[0]))
3503 return "fld%z1\t%y1";
3508 /* There is no non-popping store to memory for XFmode. So if
3509 we need one, follow the store with a load. */
3510 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3511 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3513 return "fstp%z0\t%y0";
3519 [(set_attr "type" "fmov")
3520 (set_attr "mode" "SF,XF")])
3522 (define_expand "extendsftf2"
3523 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3524 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3527 /* ??? Needed for compress_float_constant since all fp constants
3528 are LEGITIMATE_CONSTANT_P. */
3529 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3530 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3531 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3532 operands[1] = force_reg (SFmode, operands[1]);
3535 (define_insn "*extendsftf2_1"
3536 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3537 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3539 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3541 switch (which_alternative)
3544 if (REG_P (operands[1])
3545 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3547 else if (STACK_TOP_P (operands[0]))
3548 return "fld%z1\t%y1";
3553 /* There is no non-popping store to memory for XFmode. So if
3554 we need one, follow the store with a load. */
3555 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3556 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3558 return "fstp%z0\t%y0";
3564 [(set_attr "type" "fmov")
3565 (set_attr "mode" "SF,XF")])
3567 (define_expand "extenddfxf2"
3568 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3569 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3570 "!TARGET_64BIT && TARGET_80387"
3572 /* ??? Needed for compress_float_constant since all fp constants
3573 are LEGITIMATE_CONSTANT_P. */
3574 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3575 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3576 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3577 operands[1] = force_reg (DFmode, operands[1]);
3580 (define_insn "*extenddfxf2_1"
3581 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3582 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3583 "!TARGET_64BIT && TARGET_80387
3584 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3586 switch (which_alternative)
3589 if (REG_P (operands[1])
3590 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3592 else if (STACK_TOP_P (operands[0]))
3593 return "fld%z1\t%y1";
3598 /* There is no non-popping store to memory for XFmode. So if
3599 we need one, follow the store with a load. */
3600 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3601 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3603 return "fstp%z0\t%y0";
3609 [(set_attr "type" "fmov")
3610 (set_attr "mode" "DF,XF")])
3612 (define_expand "extenddftf2"
3613 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3614 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3617 /* ??? Needed for compress_float_constant since all fp constants
3618 are LEGITIMATE_CONSTANT_P. */
3619 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3620 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3621 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3622 operands[1] = force_reg (DFmode, operands[1]);
3625 (define_insn "*extenddftf2_1"
3626 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3627 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3629 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3631 switch (which_alternative)
3634 if (REG_P (operands[1])
3635 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3637 else if (STACK_TOP_P (operands[0]))
3638 return "fld%z1\t%y1";
3643 /* There is no non-popping store to memory for XFmode. So if
3644 we need one, follow the store with a load. */
3645 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3646 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3648 return "fstp%z0\t%y0";
3654 [(set_attr "type" "fmov")
3655 (set_attr "mode" "DF,XF")])
3657 ;; %%% This seems bad bad news.
3658 ;; This cannot output into an f-reg because there is no way to be sure
3659 ;; of truncating in that case. Otherwise this is just like a simple move
3660 ;; insn. So we pretend we can output to a reg in order to get better
3661 ;; register preferencing, but we really use a stack slot.
3663 (define_expand "truncdfsf2"
3664 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3666 (match_operand:DF 1 "register_operand" "")))
3667 (clobber (match_dup 2))])]
3668 "TARGET_80387 || TARGET_SSE2"
3671 operands[2] = assign_386_stack_local (SFmode, 0);
3674 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3679 (define_insn "*truncdfsf2_1"
3680 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3682 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3683 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3684 "TARGET_80387 && !TARGET_SSE2"
3686 switch (which_alternative)
3689 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3690 return "fstp%z0\t%y0";
3692 return "fst%z0\t%y0";
3697 [(set_attr "type" "fmov,multi,multi,multi")
3698 (set_attr "mode" "SF,SF,SF,SF")])
3700 (define_insn "*truncdfsf2_1_sse"
3701 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y")
3703 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
3704 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3705 "TARGET_80387 && TARGET_SSE2"
3707 switch (which_alternative)
3710 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3711 return "fstp%z0\t%y0";
3713 return "fst%z0\t%y0";
3715 return "cvtsd2ss\t{%1, %0|%0, %1}";
3720 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3721 (set_attr "mode" "SF,SF,SF,SF,DF")])
3723 (define_insn "*truncdfsf2_2"
3724 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
3726 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3727 "TARGET_80387 && TARGET_SSE2
3728 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3730 switch (which_alternative)
3733 return "cvtsd2ss\t{%1, %0|%0, %1}";
3735 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3736 return "fstp%z0\t%y0";
3738 return "fst%z0\t%y0";
3743 [(set_attr "type" "ssecvt,fmov")
3744 (set_attr "mode" "DF,SF")])
3746 (define_insn "truncdfsf2_3"
3747 [(set (match_operand:SF 0 "memory_operand" "=m")
3749 (match_operand:DF 1 "register_operand" "f")))]
3752 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3753 return "fstp%z0\t%y0";
3755 return "fst%z0\t%y0";
3757 [(set_attr "type" "fmov")
3758 (set_attr "mode" "SF")])
3760 (define_insn "truncdfsf2_sse_only"
3761 [(set (match_operand:SF 0 "register_operand" "=Y")
3763 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3764 "!TARGET_80387 && TARGET_SSE2"
3765 "cvtsd2ss\t{%1, %0|%0, %1}"
3766 [(set_attr "type" "ssecvt")
3767 (set_attr "mode" "DF")])
3770 [(set (match_operand:SF 0 "memory_operand" "")
3772 (match_operand:DF 1 "register_operand" "")))
3773 (clobber (match_operand:SF 2 "memory_operand" ""))]
3775 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3779 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3781 (match_operand:DF 1 "nonimmediate_operand" "")))
3782 (clobber (match_operand 2 "" ""))]
3783 "TARGET_80387 && reload_completed
3784 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
3785 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3789 [(set (match_operand:SF 0 "register_operand" "")
3791 (match_operand:DF 1 "register_operand" "")))
3792 (clobber (match_operand:SF 2 "memory_operand" ""))]
3793 "TARGET_80387 && reload_completed
3794 && FP_REG_P (operands[1])"
3795 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3796 (set (match_dup 0) (match_dup 2))]
3799 (define_expand "truncxfsf2"
3800 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3802 (match_operand:XF 1 "register_operand" "")))
3803 (clobber (match_dup 2))])]
3804 "!TARGET_64BIT && TARGET_80387"
3805 "operands[2] = assign_386_stack_local (SFmode, 0);")
3807 (define_insn "*truncxfsf2_1"
3808 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3810 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3811 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3812 "!TARGET_64BIT && TARGET_80387"
3814 switch (which_alternative)
3817 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3818 return "fstp%z0\t%y0";
3820 return "fst%z0\t%y0";
3825 [(set_attr "type" "fmov,multi,multi,multi")
3826 (set_attr "mode" "SF")])
3828 (define_insn "*truncxfsf2_2"
3829 [(set (match_operand:SF 0 "memory_operand" "=m")
3831 (match_operand:XF 1 "register_operand" "f")))]
3832 "!TARGET_64BIT && TARGET_80387"
3834 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3835 return "fstp%z0\t%y0";
3837 return "fst%z0\t%y0";
3839 [(set_attr "type" "fmov")
3840 (set_attr "mode" "SF")])
3843 [(set (match_operand:SF 0 "memory_operand" "")
3845 (match_operand:XF 1 "register_operand" "")))
3846 (clobber (match_operand:SF 2 "memory_operand" ""))]
3848 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3852 [(set (match_operand:SF 0 "register_operand" "")
3854 (match_operand:XF 1 "register_operand" "")))
3855 (clobber (match_operand:SF 2 "memory_operand" ""))]
3856 "TARGET_80387 && reload_completed"
3857 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3858 (set (match_dup 0) (match_dup 2))]
3861 (define_expand "trunctfsf2"
3862 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3864 (match_operand:TF 1 "register_operand" "")))
3865 (clobber (match_dup 2))])]
3867 "operands[2] = assign_386_stack_local (SFmode, 0);")
3869 (define_insn "*trunctfsf2_1"
3870 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3872 (match_operand:TF 1 "register_operand" "f,f,f,f")))
3873 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3876 switch (which_alternative)
3879 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3880 return "fstp%z0\t%y0";
3882 return "fst%z0\t%y0";
3887 [(set_attr "type" "fmov,multi,multi,multi")
3888 (set_attr "mode" "SF")])
3890 (define_insn "*trunctfsf2_2"
3891 [(set (match_operand:SF 0 "memory_operand" "=m")
3893 (match_operand:TF 1 "register_operand" "f")))]
3896 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3897 return "fstp%z0\t%y0";
3899 return "fst%z0\t%y0";
3901 [(set_attr "type" "fmov")
3902 (set_attr "mode" "SF")])
3905 [(set (match_operand:SF 0 "memory_operand" "")
3907 (match_operand:TF 1 "register_operand" "")))
3908 (clobber (match_operand:SF 2 "memory_operand" ""))]
3910 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3914 [(set (match_operand:SF 0 "register_operand" "")
3916 (match_operand:TF 1 "register_operand" "")))
3917 (clobber (match_operand:SF 2 "memory_operand" ""))]
3918 "TARGET_80387 && reload_completed"
3919 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3920 (set (match_dup 0) (match_dup 2))]
3924 (define_expand "truncxfdf2"
3925 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3927 (match_operand:XF 1 "register_operand" "")))
3928 (clobber (match_dup 2))])]
3929 "!TARGET_64BIT && TARGET_80387"
3930 "operands[2] = assign_386_stack_local (DFmode, 0);")
3932 (define_insn "*truncxfdf2_1"
3933 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3935 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3936 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3937 "!TARGET_64BIT && TARGET_80387"
3939 switch (which_alternative)
3942 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3943 return "fstp%z0\t%y0";
3945 return "fst%z0\t%y0";
3951 [(set_attr "type" "fmov,multi,multi,multi")
3952 (set_attr "mode" "DF")])
3954 (define_insn "*truncxfdf2_2"
3955 [(set (match_operand:DF 0 "memory_operand" "=m")
3957 (match_operand:XF 1 "register_operand" "f")))]
3958 "!TARGET_64BIT && TARGET_80387"
3960 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3961 return "fstp%z0\t%y0";
3963 return "fst%z0\t%y0";
3965 [(set_attr "type" "fmov")
3966 (set_attr "mode" "DF")])
3969 [(set (match_operand:DF 0 "memory_operand" "")
3971 (match_operand:XF 1 "register_operand" "")))
3972 (clobber (match_operand:DF 2 "memory_operand" ""))]
3974 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
3978 [(set (match_operand:DF 0 "register_operand" "")
3980 (match_operand:XF 1 "register_operand" "")))
3981 (clobber (match_operand:DF 2 "memory_operand" ""))]
3982 "TARGET_80387 && reload_completed"
3983 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
3984 (set (match_dup 0) (match_dup 2))]
3987 (define_expand "trunctfdf2"
3988 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3990 (match_operand:TF 1 "register_operand" "")))
3991 (clobber (match_dup 2))])]
3993 "operands[2] = assign_386_stack_local (DFmode, 0);")
3995 (define_insn "*trunctfdf2_1"
3996 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3998 (match_operand:TF 1 "register_operand" "f,f,f,f")))
3999 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4002 switch (which_alternative)
4005 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4006 return "fstp%z0\t%y0";
4008 return "fst%z0\t%y0";
4014 [(set_attr "type" "fmov,multi,multi,multi")
4015 (set_attr "mode" "DF")])
4017 (define_insn "*trunctfdf2_2"
4018 [(set (match_operand:DF 0 "memory_operand" "=m")
4020 (match_operand:TF 1 "register_operand" "f")))]
4023 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4024 return "fstp%z0\t%y0";
4026 return "fst%z0\t%y0";
4028 [(set_attr "type" "fmov")
4029 (set_attr "mode" "DF")])
4032 [(set (match_operand:DF 0 "memory_operand" "")
4034 (match_operand:TF 1 "register_operand" "")))
4035 (clobber (match_operand:DF 2 "memory_operand" ""))]
4037 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4041 [(set (match_operand:DF 0 "register_operand" "")
4043 (match_operand:TF 1 "register_operand" "")))
4044 (clobber (match_operand:DF 2 "memory_operand" ""))]
4045 "TARGET_80387 && reload_completed"
4046 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4047 (set (match_dup 0) (match_dup 2))]
4051 ;; %%% Break up all these bad boys.
4053 ;; Signed conversion to DImode.
4055 (define_expand "fix_truncxfdi2"
4056 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4057 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4058 "!TARGET_64BIT && TARGET_80387"
4061 (define_expand "fix_trunctfdi2"
4062 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4063 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4067 (define_expand "fix_truncdfdi2"
4068 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4069 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4070 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4072 if (TARGET_64BIT && TARGET_SSE2)
4074 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4075 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4076 if (out != operands[0])
4077 emit_move_insn (operands[0], out);
4082 (define_expand "fix_truncsfdi2"
4083 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4084 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4085 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4087 if (TARGET_SSE && TARGET_64BIT)
4089 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4090 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4091 if (out != operands[0])
4092 emit_move_insn (operands[0], out);
4097 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4098 ;; of the machinery.
4099 (define_insn_and_split "*fix_truncdi_1"
4100 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4101 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4102 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4103 && !reload_completed && !reload_in_progress
4104 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4109 operands[2] = assign_386_stack_local (HImode, 1);
4110 operands[3] = assign_386_stack_local (HImode, 2);
4111 if (memory_operand (operands[0], VOIDmode))
4112 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4113 operands[2], operands[3]));
4116 operands[4] = assign_386_stack_local (DImode, 0);
4117 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4118 operands[2], operands[3],
4123 [(set_attr "type" "fistp")])
4125 (define_insn "fix_truncdi_nomemory"
4126 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4127 (fix:DI (match_operand 1 "register_operand" "f,f")))
4128 (use (match_operand:HI 2 "memory_operand" "m,m"))
4129 (use (match_operand:HI 3 "memory_operand" "m,m"))
4130 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4131 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4132 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4133 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4135 [(set_attr "type" "fistp")])
4137 (define_insn "fix_truncdi_memory"
4138 [(set (match_operand:DI 0 "memory_operand" "=m")
4139 (fix:DI (match_operand 1 "register_operand" "f")))
4140 (use (match_operand:HI 2 "memory_operand" "m"))
4141 (use (match_operand:HI 3 "memory_operand" "m"))
4142 (clobber (match_scratch:DF 4 "=&1f"))]
4143 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4144 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4145 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4146 [(set_attr "type" "fistp")])
4149 [(set (match_operand:DI 0 "register_operand" "")
4150 (fix:DI (match_operand 1 "register_operand" "")))
4151 (use (match_operand:HI 2 "memory_operand" ""))
4152 (use (match_operand:HI 3 "memory_operand" ""))
4153 (clobber (match_operand:DI 4 "memory_operand" ""))
4154 (clobber (match_scratch 5 ""))]
4156 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4159 (clobber (match_dup 5))])
4160 (set (match_dup 0) (match_dup 4))]
4164 [(set (match_operand:DI 0 "memory_operand" "")
4165 (fix:DI (match_operand 1 "register_operand" "")))
4166 (use (match_operand:HI 2 "memory_operand" ""))
4167 (use (match_operand:HI 3 "memory_operand" ""))
4168 (clobber (match_operand:DI 4 "memory_operand" ""))
4169 (clobber (match_scratch 5 ""))]
4171 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4174 (clobber (match_dup 5))])]
4177 ;; When SSE available, it is always faster to use it!
4178 (define_insn "fix_truncsfdi_sse"
4179 [(set (match_operand:DI 0 "register_operand" "=r")
4180 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4181 "TARGET_64BIT && TARGET_SSE"
4182 "cvttss2si{q}\t{%1, %0|%0, %1}"
4183 [(set_attr "type" "ssecvt")])
4185 (define_insn "fix_truncdfdi_sse"
4186 [(set (match_operand:DI 0 "register_operand" "=r")
4187 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4188 "TARGET_64BIT && TARGET_SSE2"
4189 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4190 [(set_attr "type" "ssecvt")])
4192 ;; Signed conversion to SImode.
4194 (define_expand "fix_truncxfsi2"
4195 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4196 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4197 "!TARGET_64BIT && TARGET_80387"
4200 (define_expand "fix_trunctfsi2"
4201 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4202 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4206 (define_expand "fix_truncdfsi2"
4207 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4208 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4209 "TARGET_80387 || TARGET_SSE2"
4213 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4214 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4215 if (out != operands[0])
4216 emit_move_insn (operands[0], out);
4221 (define_expand "fix_truncsfsi2"
4222 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4223 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4224 "TARGET_80387 || TARGET_SSE"
4228 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4229 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4230 if (out != operands[0])
4231 emit_move_insn (operands[0], out);
4236 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4237 ;; of the machinery.
4238 (define_insn_and_split "*fix_truncsi_1"
4239 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4240 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4241 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4242 && !reload_completed && !reload_in_progress
4243 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4248 operands[2] = assign_386_stack_local (HImode, 1);
4249 operands[3] = assign_386_stack_local (HImode, 2);
4250 if (memory_operand (operands[0], VOIDmode))
4251 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4252 operands[2], operands[3]));
4255 operands[4] = assign_386_stack_local (SImode, 0);
4256 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4257 operands[2], operands[3],
4262 [(set_attr "type" "fistp")])
4264 (define_insn "fix_truncsi_nomemory"
4265 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4266 (fix:SI (match_operand 1 "register_operand" "f,f")))
4267 (use (match_operand:HI 2 "memory_operand" "m,m"))
4268 (use (match_operand:HI 3 "memory_operand" "m,m"))
4269 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4270 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4271 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4273 [(set_attr "type" "fistp")])
4275 (define_insn "fix_truncsi_memory"
4276 [(set (match_operand:SI 0 "memory_operand" "=m")
4277 (fix:SI (match_operand 1 "register_operand" "f")))
4278 (use (match_operand:HI 2 "memory_operand" "m"))
4279 (use (match_operand:HI 3 "memory_operand" "m"))]
4280 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4281 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4282 "* return output_fix_trunc (insn, operands);"
4283 [(set_attr "type" "fistp")])
4285 ;; When SSE available, it is always faster to use it!
4286 (define_insn "fix_truncsfsi_sse"
4287 [(set (match_operand:SI 0 "register_operand" "=r")
4288 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4290 "cvttss2si\t{%1, %0|%0, %1}"
4291 [(set_attr "type" "ssecvt")])
4293 (define_insn "fix_truncdfsi_sse"
4294 [(set (match_operand:SI 0 "register_operand" "=r")
4295 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4297 "cvttsd2si\t{%1, %0|%0, %1}"
4298 [(set_attr "type" "ssecvt")])
4301 [(set (match_operand:SI 0 "register_operand" "")
4302 (fix:SI (match_operand 1 "register_operand" "")))
4303 (use (match_operand:HI 2 "memory_operand" ""))
4304 (use (match_operand:HI 3 "memory_operand" ""))
4305 (clobber (match_operand:SI 4 "memory_operand" ""))]
4307 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4309 (use (match_dup 3))])
4310 (set (match_dup 0) (match_dup 4))]
4314 [(set (match_operand:SI 0 "memory_operand" "")
4315 (fix:SI (match_operand 1 "register_operand" "")))
4316 (use (match_operand:HI 2 "memory_operand" ""))
4317 (use (match_operand:HI 3 "memory_operand" ""))
4318 (clobber (match_operand:SI 4 "memory_operand" ""))]
4320 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4322 (use (match_dup 3))])]
4325 ;; Signed conversion to HImode.
4327 (define_expand "fix_truncxfhi2"
4328 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4329 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4330 "!TARGET_64BIT && TARGET_80387"
4333 (define_expand "fix_trunctfhi2"
4334 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4335 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4339 (define_expand "fix_truncdfhi2"
4340 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4341 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4342 "TARGET_80387 && !TARGET_SSE2"
4345 (define_expand "fix_truncsfhi2"
4346 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4347 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4348 "TARGET_80387 && !TARGET_SSE"
4351 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4352 ;; of the machinery.
4353 (define_insn_and_split "*fix_trunchi_1"
4354 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4355 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4356 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4357 && !reload_completed && !reload_in_progress
4358 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4363 operands[2] = assign_386_stack_local (HImode, 1);
4364 operands[3] = assign_386_stack_local (HImode, 2);
4365 if (memory_operand (operands[0], VOIDmode))
4366 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4367 operands[2], operands[3]));
4370 operands[4] = assign_386_stack_local (HImode, 0);
4371 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4372 operands[2], operands[3],
4377 [(set_attr "type" "fistp")])
4379 (define_insn "fix_trunchi_nomemory"
4380 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4381 (fix:HI (match_operand 1 "register_operand" "f,f")))
4382 (use (match_operand:HI 2 "memory_operand" "m,m"))
4383 (use (match_operand:HI 3 "memory_operand" "m,m"))
4384 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4385 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4386 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4388 [(set_attr "type" "fistp")])
4390 (define_insn "fix_trunchi_memory"
4391 [(set (match_operand:HI 0 "memory_operand" "=m")
4392 (fix:HI (match_operand 1 "register_operand" "f")))
4393 (use (match_operand:HI 2 "memory_operand" "m"))
4394 (use (match_operand:HI 3 "memory_operand" "m"))]
4395 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4396 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4397 "* return output_fix_trunc (insn, operands);"
4398 [(set_attr "type" "fistp")])
4401 [(set (match_operand:HI 0 "memory_operand" "")
4402 (fix:HI (match_operand 1 "register_operand" "")))
4403 (use (match_operand:HI 2 "memory_operand" ""))
4404 (use (match_operand:HI 3 "memory_operand" ""))
4405 (clobber (match_operand:HI 4 "memory_operand" ""))]
4407 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4409 (use (match_dup 3))])]
4413 [(set (match_operand:HI 0 "register_operand" "")
4414 (fix:HI (match_operand 1 "register_operand" "")))
4415 (use (match_operand:HI 2 "memory_operand" ""))
4416 (use (match_operand:HI 3 "memory_operand" ""))
4417 (clobber (match_operand:HI 4 "memory_operand" ""))]
4419 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4422 (clobber (match_dup 4))])
4423 (set (match_dup 0) (match_dup 4))]
4427 (define_insn "x86_fnstcw_1"
4428 [(set (match_operand:HI 0 "memory_operand" "=m")
4429 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4432 [(set_attr "length" "2")
4433 (set_attr "mode" "HI")
4434 (set_attr "unit" "i387")
4435 (set_attr "ppro_uops" "few")])
4437 (define_insn "x86_fldcw_1"
4439 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4442 [(set_attr "length" "2")
4443 (set_attr "mode" "HI")
4444 (set_attr "unit" "i387")
4445 (set_attr "athlon_decode" "vector")
4446 (set_attr "ppro_uops" "few")])
4448 ;; Conversion between fixed point and floating point.
4450 ;; Even though we only accept memory inputs, the backend _really_
4451 ;; wants to be able to do this between registers.
4453 (define_insn "floathisf2"
4454 [(set (match_operand:SF 0 "register_operand" "=f,f")
4455 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4456 "TARGET_80387 && !TARGET_SSE"
4460 [(set_attr "type" "fmov,multi")
4461 (set_attr "mode" "SF")
4462 (set_attr "fp_int_src" "true")])
4464 (define_expand "floatsisf2"
4465 [(set (match_operand:SF 0 "register_operand" "")
4466 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4467 "TARGET_SSE || TARGET_80387"
4470 (define_insn "*floatsisf2_i387"
4471 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4472 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4473 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4477 cvtsi2ss\t{%1, %0|%0, %1}"
4478 [(set_attr "type" "fmov,multi,ssecvt")
4479 (set_attr "mode" "SF")
4480 (set_attr "fp_int_src" "true")])
4482 (define_insn "*floatsisf2_sse"
4483 [(set (match_operand:SF 0 "register_operand" "=x")
4484 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4486 "cvtsi2ss\t{%1, %0|%0, %1}"
4487 [(set_attr "type" "ssecvt")
4488 (set_attr "mode" "SF")
4489 (set_attr "fp_int_src" "true")])
4491 (define_expand "floatdisf2"
4492 [(set (match_operand:SF 0 "register_operand" "")
4493 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4494 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4497 (define_insn "*floatdisf2_i387_only"
4498 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4499 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4500 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4504 [(set_attr "type" "fmov,multi")
4505 (set_attr "mode" "SF")
4506 (set_attr "fp_int_src" "true")])
4508 (define_insn "*floatdisf2_i387"
4509 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4510 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
4511 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4515 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4516 [(set_attr "type" "fmov,multi,ssecvt")
4517 (set_attr "mode" "SF")
4518 (set_attr "fp_int_src" "true")])
4520 (define_insn "*floatdisf2_sse"
4521 [(set (match_operand:SF 0 "register_operand" "=x")
4522 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
4523 "TARGET_64BIT && TARGET_SSE"
4524 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4525 [(set_attr "type" "ssecvt")
4526 (set_attr "mode" "SF")
4527 (set_attr "fp_int_src" "true")])
4529 (define_insn "floathidf2"
4530 [(set (match_operand:DF 0 "register_operand" "=f,f")
4531 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4532 "TARGET_80387 && !TARGET_SSE2"
4536 [(set_attr "type" "fmov,multi")
4537 (set_attr "mode" "DF")
4538 (set_attr "fp_int_src" "true")])
4540 (define_expand "floatsidf2"
4541 [(set (match_operand:DF 0 "register_operand" "")
4542 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4543 "TARGET_80387 || TARGET_SSE2"
4546 (define_insn "*floatsidf2_i387"
4547 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4548 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4549 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4553 cvtsi2sd\t{%1, %0|%0, %1}"
4554 [(set_attr "type" "fmov,multi,ssecvt")
4555 (set_attr "mode" "DF")
4556 (set_attr "fp_int_src" "true")])
4558 (define_insn "*floatsidf2_sse"
4559 [(set (match_operand:DF 0 "register_operand" "=Y")
4560 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4562 "cvtsi2sd\t{%1, %0|%0, %1}"
4563 [(set_attr "type" "ssecvt")
4564 (set_attr "mode" "DF")
4565 (set_attr "fp_int_src" "true")])
4567 (define_expand "floatdidf2"
4568 [(set (match_operand:DF 0 "register_operand" "")
4569 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4570 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4573 (define_insn "*floatdidf2_i387_only"
4574 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4575 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4576 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4580 [(set_attr "type" "fmov,multi")
4581 (set_attr "mode" "DF")
4582 (set_attr "fp_int_src" "true")])
4584 (define_insn "*floatdidf2_i387"
4585 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4586 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
4587 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4591 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4592 [(set_attr "type" "fmov,multi,ssecvt")
4593 (set_attr "mode" "DF")
4594 (set_attr "fp_int_src" "true")])
4596 (define_insn "*floatdidf2_sse"
4597 [(set (match_operand:DF 0 "register_operand" "=Y")
4598 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
4600 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4601 [(set_attr "type" "ssecvt")
4602 (set_attr "mode" "DF")
4603 (set_attr "fp_int_src" "true")])
4605 (define_insn "floathixf2"
4606 [(set (match_operand:XF 0 "register_operand" "=f,f")
4607 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4608 "!TARGET_64BIT && TARGET_80387"
4612 [(set_attr "type" "fmov,multi")
4613 (set_attr "mode" "XF")
4614 (set_attr "fp_int_src" "true")])
4616 (define_insn "floathitf2"
4617 [(set (match_operand:TF 0 "register_operand" "=f,f")
4618 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4623 [(set_attr "type" "fmov,multi")
4624 (set_attr "mode" "XF")
4625 (set_attr "fp_int_src" "true")])
4627 (define_insn "floatsixf2"
4628 [(set (match_operand:XF 0 "register_operand" "=f,f")
4629 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4630 "!TARGET_64BIT && TARGET_80387"
4634 [(set_attr "type" "fmov,multi")
4635 (set_attr "mode" "XF")
4636 (set_attr "fp_int_src" "true")])
4638 (define_insn "floatsitf2"
4639 [(set (match_operand:TF 0 "register_operand" "=f,f")
4640 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4645 [(set_attr "type" "fmov,multi")
4646 (set_attr "mode" "XF")
4647 (set_attr "fp_int_src" "true")])
4649 (define_insn "floatdixf2"
4650 [(set (match_operand:XF 0 "register_operand" "=f,f")
4651 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4652 "!TARGET_64BIT && TARGET_80387"
4656 [(set_attr "type" "fmov,multi")
4657 (set_attr "mode" "XF")
4658 (set_attr "fp_int_src" "true")])
4660 (define_insn "floatditf2"
4661 [(set (match_operand:TF 0 "register_operand" "=f,f")
4662 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4667 [(set_attr "type" "fmov,multi")
4668 (set_attr "mode" "XF")
4669 (set_attr "fp_int_src" "true")])
4671 ;; %%% Kill these when reload knows how to do it.
4673 [(set (match_operand 0 "register_operand" "")
4674 (float (match_operand 1 "register_operand" "")))]
4675 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
4676 && FP_REG_P (operands[0])"
4679 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4680 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4681 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4682 ix86_free_from_memory (GET_MODE (operands[1]));
4688 ;; %%% splits for addsidi3
4689 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4690 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4691 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4693 (define_expand "adddi3"
4694 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4695 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4696 (match_operand:DI 2 "x86_64_general_operand" "")))
4697 (clobber (reg:CC 17))]
4699 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4701 (define_insn "*adddi3_1"
4702 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4703 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4704 (match_operand:DI 2 "general_operand" "roiF,riF")))
4705 (clobber (reg:CC 17))]
4710 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4711 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4712 (match_operand:DI 2 "general_operand" "")))
4713 (clobber (reg:CC 17))]
4714 "!TARGET_64BIT && reload_completed"
4715 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
4717 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4718 (parallel [(set (match_dup 3)
4719 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4722 (clobber (reg:CC 17))])]
4723 "split_di (operands+0, 1, operands+0, operands+3);
4724 split_di (operands+1, 1, operands+1, operands+4);
4725 split_di (operands+2, 1, operands+2, operands+5);")
4727 (define_insn "*adddi3_carry_rex64"
4728 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4729 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
4730 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4731 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4732 (clobber (reg:CC 17))]
4733 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4734 "adc{q}\t{%2, %0|%0, %2}"
4735 [(set_attr "type" "alu")
4736 (set_attr "pent_pair" "pu")
4737 (set_attr "mode" "DI")
4738 (set_attr "ppro_uops" "few")])
4740 (define_insn "*adddi3_cc_rex64"
4742 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4743 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4745 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4746 (plus:DI (match_dup 1) (match_dup 2)))]
4747 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4748 "add{q}\t{%2, %0|%0, %2}"
4749 [(set_attr "type" "alu")
4750 (set_attr "mode" "DI")])
4752 (define_insn "*addsi3_carry"
4753 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4754 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4755 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
4756 (match_operand:SI 2 "general_operand" "ri,rm")))
4757 (clobber (reg:CC 17))]
4758 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4759 "adc{l}\t{%2, %0|%0, %2}"
4760 [(set_attr "type" "alu")
4761 (set_attr "pent_pair" "pu")
4762 (set_attr "mode" "SI")
4763 (set_attr "ppro_uops" "few")])
4765 (define_insn "*addsi3_carry_zext"
4766 [(set (match_operand:DI 0 "register_operand" "=r")
4768 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4769 (match_operand:SI 1 "nonimmediate_operand" "%0"))
4770 (match_operand:SI 2 "general_operand" "rim"))))
4771 (clobber (reg:CC 17))]
4772 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
4773 "adc{l}\t{%2, %k0|%k0, %2}"
4774 [(set_attr "type" "alu")
4775 (set_attr "pent_pair" "pu")
4776 (set_attr "mode" "SI")
4777 (set_attr "ppro_uops" "few")])
4779 (define_insn "*addsi3_cc"
4781 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
4782 (match_operand:SI 2 "general_operand" "ri,rm")]
4784 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4785 (plus:SI (match_dup 1) (match_dup 2)))]
4786 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4787 "add{l}\t{%2, %0|%0, %2}"
4788 [(set_attr "type" "alu")
4789 (set_attr "mode" "SI")])
4791 (define_insn "addqi3_cc"
4793 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
4794 (match_operand:QI 2 "general_operand" "qi,qm")]
4796 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4797 (plus:QI (match_dup 1) (match_dup 2)))]
4798 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4799 "add{b}\t{%2, %0|%0, %2}"
4800 [(set_attr "type" "alu")
4801 (set_attr "mode" "QI")])
4803 (define_expand "addsi3"
4804 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4805 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4806 (match_operand:SI 2 "general_operand" "")))
4807 (clobber (reg:CC 17))])]
4809 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
4811 (define_insn "*lea_1"
4812 [(set (match_operand:SI 0 "register_operand" "=r")
4813 (match_operand:SI 1 "address_operand" "p"))]
4815 "lea{l}\t{%a1, %0|%0, %a1}"
4816 [(set_attr "type" "lea")
4817 (set_attr "mode" "SI")])
4819 (define_insn "*lea_1_rex64"
4820 [(set (match_operand:SI 0 "register_operand" "=r")
4821 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
4823 "lea{l}\t{%a1, %0|%0, %a1}"
4824 [(set_attr "type" "lea")
4825 (set_attr "mode" "SI")])
4827 (define_insn "*lea_1_zext"
4828 [(set (match_operand:DI 0 "register_operand" "=r")
4829 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
4831 "lea{l}\t{%a1, %k0|%k0, %a1}"
4832 [(set_attr "type" "lea")
4833 (set_attr "mode" "SI")])
4835 (define_insn "*lea_2_rex64"
4836 [(set (match_operand:DI 0 "register_operand" "=r")
4837 (match_operand:DI 1 "address_operand" "p"))]
4839 "lea{q}\t{%a1, %0|%0, %a1}"
4840 [(set_attr "type" "lea")
4841 (set_attr "mode" "DI")])
4843 ;; The lea patterns for non-Pmodes needs to be matched by several
4844 ;; insns converted to real lea by splitters.
4846 (define_insn_and_split "*lea_general_1"
4847 [(set (match_operand 0 "register_operand" "=r")
4848 (plus (plus (match_operand 1 "register_operand" "r")
4849 (match_operand 2 "register_operand" "r"))
4850 (match_operand 3 "immediate_operand" "i")))]
4851 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4852 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4853 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4854 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4855 && GET_MODE (operands[0]) == GET_MODE (operands[2])
4856 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4857 || GET_MODE (operands[3]) == VOIDmode)"
4859 "&& reload_completed"
4863 operands[0] = gen_lowpart (SImode, operands[0]);
4864 operands[1] = gen_lowpart (Pmode, operands[1]);
4865 operands[2] = gen_lowpart (Pmode, operands[2]);
4866 operands[3] = gen_lowpart (Pmode, operands[3]);
4867 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
4869 if (Pmode != SImode)
4870 pat = gen_rtx_SUBREG (SImode, pat, 0);
4871 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4874 [(set_attr "type" "lea")
4875 (set_attr "mode" "SI")])
4877 (define_insn_and_split "*lea_general_1_zext"
4878 [(set (match_operand:DI 0 "register_operand" "=r")
4880 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
4881 (match_operand:SI 2 "register_operand" "r"))
4882 (match_operand:SI 3 "immediate_operand" "i"))))]
4885 "&& reload_completed"
4887 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
4889 (match_dup 3)) 0)))]
4891 operands[1] = gen_lowpart (Pmode, operands[1]);
4892 operands[2] = gen_lowpart (Pmode, operands[2]);
4893 operands[3] = gen_lowpart (Pmode, operands[3]);
4895 [(set_attr "type" "lea")
4896 (set_attr "mode" "SI")])
4898 (define_insn_and_split "*lea_general_2"
4899 [(set (match_operand 0 "register_operand" "=r")
4900 (plus (mult (match_operand 1 "register_operand" "r")
4901 (match_operand 2 "const248_operand" "i"))
4902 (match_operand 3 "nonmemory_operand" "ri")))]
4903 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4904 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4905 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4906 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4907 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4908 || GET_MODE (operands[3]) == VOIDmode)"
4910 "&& reload_completed"
4914 operands[0] = gen_lowpart (SImode, operands[0]);
4915 operands[1] = gen_lowpart (Pmode, operands[1]);
4916 operands[3] = gen_lowpart (Pmode, operands[3]);
4917 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
4919 if (Pmode != SImode)
4920 pat = gen_rtx_SUBREG (SImode, pat, 0);
4921 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4924 [(set_attr "type" "lea")
4925 (set_attr "mode" "SI")])
4927 (define_insn_and_split "*lea_general_2_zext"
4928 [(set (match_operand:DI 0 "register_operand" "=r")
4930 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4931 (match_operand:SI 2 "const248_operand" "n"))
4932 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
4935 "&& reload_completed"
4937 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
4939 (match_dup 3)) 0)))]
4941 operands[1] = gen_lowpart (Pmode, operands[1]);
4942 operands[3] = gen_lowpart (Pmode, operands[3]);
4944 [(set_attr "type" "lea")
4945 (set_attr "mode" "SI")])
4947 (define_insn_and_split "*lea_general_3"
4948 [(set (match_operand 0 "register_operand" "=r")
4949 (plus (plus (mult (match_operand 1 "register_operand" "r")
4950 (match_operand 2 "const248_operand" "i"))
4951 (match_operand 3 "register_operand" "r"))
4952 (match_operand 4 "immediate_operand" "i")))]
4953 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4954 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4955 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4956 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4957 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
4959 "&& reload_completed"
4963 operands[0] = gen_lowpart (SImode, operands[0]);
4964 operands[1] = gen_lowpart (Pmode, operands[1]);
4965 operands[3] = gen_lowpart (Pmode, operands[3]);
4966 operands[4] = gen_lowpart (Pmode, operands[4]);
4967 pat = gen_rtx_PLUS (Pmode,
4968 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
4972 if (Pmode != SImode)
4973 pat = gen_rtx_SUBREG (SImode, pat, 0);
4974 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4977 [(set_attr "type" "lea")
4978 (set_attr "mode" "SI")])
4980 (define_insn_and_split "*lea_general_3_zext"
4981 [(set (match_operand:DI 0 "register_operand" "=r")
4983 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4984 (match_operand:SI 2 "const248_operand" "n"))
4985 (match_operand:SI 3 "register_operand" "r"))
4986 (match_operand:SI 4 "immediate_operand" "i"))))]
4989 "&& reload_completed"
4991 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
4994 (match_dup 4)) 0)))]
4996 operands[1] = gen_lowpart (Pmode, operands[1]);
4997 operands[3] = gen_lowpart (Pmode, operands[3]);
4998 operands[4] = gen_lowpart (Pmode, operands[4]);
5000 [(set_attr "type" "lea")
5001 (set_attr "mode" "SI")])
5003 (define_insn "*adddi_1_rex64"
5004 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5005 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5006 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5007 (clobber (reg:CC 17))]
5008 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5010 switch (get_attr_type (insn))
5013 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5014 return "lea{q}\t{%a2, %0|%0, %a2}";
5017 if (! rtx_equal_p (operands[0], operands[1]))
5019 if (operands[2] == const1_rtx)
5020 return "inc{q}\t%0";
5021 else if (operands[2] == constm1_rtx)
5022 return "dec{q}\t%0";
5027 if (! rtx_equal_p (operands[0], operands[1]))
5030 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5031 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5032 if (GET_CODE (operands[2]) == CONST_INT
5033 /* Avoid overflows. */
5034 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5035 && (INTVAL (operands[2]) == 128
5036 || (INTVAL (operands[2]) < 0
5037 && INTVAL (operands[2]) != -128)))
5039 operands[2] = GEN_INT (-INTVAL (operands[2]));
5040 return "sub{q}\t{%2, %0|%0, %2}";
5042 return "add{q}\t{%2, %0|%0, %2}";
5046 (cond [(eq_attr "alternative" "2")
5047 (const_string "lea")
5048 ; Current assemblers are broken and do not allow @GOTOFF in
5049 ; ought but a memory context.
5050 (match_operand:DI 2 "pic_symbolic_operand" "")
5051 (const_string "lea")
5052 (match_operand:DI 2 "incdec_operand" "")
5053 (const_string "incdec")
5055 (const_string "alu")))
5056 (set_attr "mode" "DI")])
5058 ;; Convert lea to the lea pattern to avoid flags dependency.
5060 [(set (match_operand:DI 0 "register_operand" "")
5061 (plus:DI (match_operand:DI 1 "register_operand" "")
5062 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5063 (clobber (reg:CC 17))]
5064 "TARGET_64BIT && reload_completed
5065 && true_regnum (operands[0]) != true_regnum (operands[1])"
5067 (plus:DI (match_dup 1)
5071 (define_insn "*adddi_2_rex64"
5074 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5075 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5077 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5078 (plus:DI (match_dup 1) (match_dup 2)))]
5079 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5080 && ix86_binary_operator_ok (PLUS, DImode, operands)
5081 /* Current assemblers are broken and do not allow @GOTOFF in
5082 ought but a memory context. */
5083 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5085 switch (get_attr_type (insn))
5088 if (! rtx_equal_p (operands[0], operands[1]))
5090 if (operands[2] == const1_rtx)
5091 return "inc{q}\t%0";
5092 else if (operands[2] == constm1_rtx)
5093 return "dec{q}\t%0";
5098 if (! rtx_equal_p (operands[0], operands[1]))
5100 /* ???? We ought to handle there the 32bit case too
5101 - do we need new constrant? */
5102 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5103 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5104 if (GET_CODE (operands[2]) == CONST_INT
5105 /* Avoid overflows. */
5106 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5107 && (INTVAL (operands[2]) == 128
5108 || (INTVAL (operands[2]) < 0
5109 && INTVAL (operands[2]) != -128)))
5111 operands[2] = GEN_INT (-INTVAL (operands[2]));
5112 return "sub{q}\t{%2, %0|%0, %2}";
5114 return "add{q}\t{%2, %0|%0, %2}";
5118 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5119 (const_string "incdec")
5120 (const_string "alu")))
5121 (set_attr "mode" "DI")])
5123 (define_insn "*adddi_3_rex64"
5125 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5126 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5127 (clobber (match_scratch:DI 0 "=r"))]
5129 && ix86_match_ccmode (insn, CCZmode)
5130 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5131 /* Current assemblers are broken and do not allow @GOTOFF in
5132 ought but a memory context. */
5133 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5135 switch (get_attr_type (insn))
5138 if (! rtx_equal_p (operands[0], operands[1]))
5140 if (operands[2] == const1_rtx)
5141 return "inc{q}\t%0";
5142 else if (operands[2] == constm1_rtx)
5143 return "dec{q}\t%0";
5148 if (! rtx_equal_p (operands[0], operands[1]))
5150 /* ???? We ought to handle there the 32bit case too
5151 - do we need new constrant? */
5152 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5153 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5154 if (GET_CODE (operands[2]) == CONST_INT
5155 /* Avoid overflows. */
5156 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5157 && (INTVAL (operands[2]) == 128
5158 || (INTVAL (operands[2]) < 0
5159 && INTVAL (operands[2]) != -128)))
5161 operands[2] = GEN_INT (-INTVAL (operands[2]));
5162 return "sub{q}\t{%2, %0|%0, %2}";
5164 return "add{q}\t{%2, %0|%0, %2}";
5168 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5169 (const_string "incdec")
5170 (const_string "alu")))
5171 (set_attr "mode" "DI")])
5173 ; For comparisons against 1, -1 and 128, we may generate better code
5174 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5175 ; is matched then. We can't accept general immediate, because for
5176 ; case of overflows, the result is messed up.
5177 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5179 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5180 ; only for comparisons not depending on it.
5181 (define_insn "*adddi_4_rex64"
5183 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5184 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5185 (clobber (match_scratch:DI 0 "=rm"))]
5187 && ix86_match_ccmode (insn, CCGCmode)"
5189 switch (get_attr_type (insn))
5192 if (operands[2] == constm1_rtx)
5193 return "inc{q}\t%0";
5194 else if (operands[2] == const1_rtx)
5195 return "dec{q}\t%0";
5200 if (! rtx_equal_p (operands[0], operands[1]))
5202 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5203 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5204 if ((INTVAL (operands[2]) == -128
5205 || (INTVAL (operands[2]) > 0
5206 && INTVAL (operands[2]) != 128))
5207 /* Avoid overflows. */
5208 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5209 return "sub{q}\t{%2, %0|%0, %2}";
5210 operands[2] = GEN_INT (-INTVAL (operands[2]));
5211 return "add{q}\t{%2, %0|%0, %2}";
5215 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5216 (const_string "incdec")
5217 (const_string "alu")))
5218 (set_attr "mode" "DI")])
5220 (define_insn "*adddi_5_rex64"
5223 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5224 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5226 (clobber (match_scratch:DI 0 "=r"))]
5228 && ix86_match_ccmode (insn, CCGOCmode)
5229 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5230 /* Current assemblers are broken and do not allow @GOTOFF in
5231 ought but a memory context. */
5232 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5234 switch (get_attr_type (insn))
5237 if (! rtx_equal_p (operands[0], operands[1]))
5239 if (operands[2] == const1_rtx)
5240 return "inc{q}\t%0";
5241 else if (operands[2] == constm1_rtx)
5242 return "dec{q}\t%0";
5247 if (! rtx_equal_p (operands[0], operands[1]))
5249 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5250 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5251 if (GET_CODE (operands[2]) == CONST_INT
5252 /* Avoid overflows. */
5253 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5254 && (INTVAL (operands[2]) == 128
5255 || (INTVAL (operands[2]) < 0
5256 && INTVAL (operands[2]) != -128)))
5258 operands[2] = GEN_INT (-INTVAL (operands[2]));
5259 return "sub{q}\t{%2, %0|%0, %2}";
5261 return "add{q}\t{%2, %0|%0, %2}";
5265 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5266 (const_string "incdec")
5267 (const_string "alu")))
5268 (set_attr "mode" "DI")])
5271 (define_insn "*addsi_1"
5272 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5273 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5274 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5275 (clobber (reg:CC 17))]
5276 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5278 switch (get_attr_type (insn))
5281 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5282 return "lea{l}\t{%a2, %0|%0, %a2}";
5285 if (! rtx_equal_p (operands[0], operands[1]))
5287 if (operands[2] == const1_rtx)
5288 return "inc{l}\t%0";
5289 else if (operands[2] == constm1_rtx)
5290 return "dec{l}\t%0";
5295 if (! rtx_equal_p (operands[0], operands[1]))
5298 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5299 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5300 if (GET_CODE (operands[2]) == CONST_INT
5301 && (INTVAL (operands[2]) == 128
5302 || (INTVAL (operands[2]) < 0
5303 && INTVAL (operands[2]) != -128)))
5305 operands[2] = GEN_INT (-INTVAL (operands[2]));
5306 return "sub{l}\t{%2, %0|%0, %2}";
5308 return "add{l}\t{%2, %0|%0, %2}";
5312 (cond [(eq_attr "alternative" "2")
5313 (const_string "lea")
5314 ; Current assemblers are broken and do not allow @GOTOFF in
5315 ; ought but a memory context.
5316 (match_operand:SI 2 "pic_symbolic_operand" "")
5317 (const_string "lea")
5318 (match_operand:SI 2 "incdec_operand" "")
5319 (const_string "incdec")
5321 (const_string "alu")))
5322 (set_attr "mode" "SI")])
5324 ;; Convert lea to the lea pattern to avoid flags dependency.
5326 [(set (match_operand 0 "register_operand" "")
5327 (plus (match_operand 1 "register_operand" "")
5328 (match_operand 2 "nonmemory_operand" "")))
5329 (clobber (reg:CC 17))]
5331 && true_regnum (operands[0]) != true_regnum (operands[1])"
5335 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5336 may confuse gen_lowpart. */
5337 if (GET_MODE (operands[0]) != Pmode)
5339 operands[1] = gen_lowpart (Pmode, operands[1]);
5340 operands[2] = gen_lowpart (Pmode, operands[2]);
5342 operands[0] = gen_lowpart (SImode, operands[0]);
5343 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5344 if (Pmode != SImode)
5345 pat = gen_rtx_SUBREG (SImode, pat, 0);
5346 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5350 ;; It may seem that nonimmediate operand is proper one for operand 1.
5351 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5352 ;; we take care in ix86_binary_operator_ok to not allow two memory
5353 ;; operands so proper swapping will be done in reload. This allow
5354 ;; patterns constructed from addsi_1 to match.
5355 (define_insn "addsi_1_zext"
5356 [(set (match_operand:DI 0 "register_operand" "=r,r")
5358 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5359 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5360 (clobber (reg:CC 17))]
5361 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5363 switch (get_attr_type (insn))
5366 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5367 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5370 if (operands[2] == const1_rtx)
5371 return "inc{l}\t%k0";
5372 else if (operands[2] == constm1_rtx)
5373 return "dec{l}\t%k0";
5378 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5379 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5380 if (GET_CODE (operands[2]) == CONST_INT
5381 && (INTVAL (operands[2]) == 128
5382 || (INTVAL (operands[2]) < 0
5383 && INTVAL (operands[2]) != -128)))
5385 operands[2] = GEN_INT (-INTVAL (operands[2]));
5386 return "sub{l}\t{%2, %k0|%k0, %2}";
5388 return "add{l}\t{%2, %k0|%k0, %2}";
5392 (cond [(eq_attr "alternative" "1")
5393 (const_string "lea")
5394 ; Current assemblers are broken and do not allow @GOTOFF in
5395 ; ought but a memory context.
5396 (match_operand:SI 2 "pic_symbolic_operand" "")
5397 (const_string "lea")
5398 (match_operand:SI 2 "incdec_operand" "")
5399 (const_string "incdec")
5401 (const_string "alu")))
5402 (set_attr "mode" "SI")])
5404 ;; Convert lea to the lea pattern to avoid flags dependency.
5406 [(set (match_operand:DI 0 "register_operand" "")
5408 (plus:SI (match_operand:SI 1 "register_operand" "")
5409 (match_operand:SI 2 "nonmemory_operand" ""))))
5410 (clobber (reg:CC 17))]
5412 && true_regnum (operands[0]) != true_regnum (operands[1])"
5414 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5416 operands[1] = gen_lowpart (Pmode, operands[1]);
5417 operands[2] = gen_lowpart (Pmode, operands[2]);
5420 (define_insn "*addsi_2"
5423 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5424 (match_operand:SI 2 "general_operand" "rmni,rni"))
5426 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5427 (plus:SI (match_dup 1) (match_dup 2)))]
5428 "ix86_match_ccmode (insn, CCGOCmode)
5429 && ix86_binary_operator_ok (PLUS, SImode, operands)
5430 /* Current assemblers are broken and do not allow @GOTOFF in
5431 ought but a memory context. */
5432 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5434 switch (get_attr_type (insn))
5437 if (! rtx_equal_p (operands[0], operands[1]))
5439 if (operands[2] == const1_rtx)
5440 return "inc{l}\t%0";
5441 else if (operands[2] == constm1_rtx)
5442 return "dec{l}\t%0";
5447 if (! rtx_equal_p (operands[0], operands[1]))
5449 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5450 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5451 if (GET_CODE (operands[2]) == CONST_INT
5452 && (INTVAL (operands[2]) == 128
5453 || (INTVAL (operands[2]) < 0
5454 && INTVAL (operands[2]) != -128)))
5456 operands[2] = GEN_INT (-INTVAL (operands[2]));
5457 return "sub{l}\t{%2, %0|%0, %2}";
5459 return "add{l}\t{%2, %0|%0, %2}";
5463 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5464 (const_string "incdec")
5465 (const_string "alu")))
5466 (set_attr "mode" "SI")])
5468 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5469 (define_insn "*addsi_2_zext"
5472 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5473 (match_operand:SI 2 "general_operand" "rmni"))
5475 (set (match_operand:DI 0 "register_operand" "=r")
5476 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5477 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5478 && ix86_binary_operator_ok (PLUS, SImode, operands)
5479 /* Current assemblers are broken and do not allow @GOTOFF in
5480 ought but a memory context. */
5481 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5483 switch (get_attr_type (insn))
5486 if (operands[2] == const1_rtx)
5487 return "inc{l}\t%k0";
5488 else if (operands[2] == constm1_rtx)
5489 return "dec{l}\t%k0";
5494 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5495 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5496 if (GET_CODE (operands[2]) == CONST_INT
5497 && (INTVAL (operands[2]) == 128
5498 || (INTVAL (operands[2]) < 0
5499 && INTVAL (operands[2]) != -128)))
5501 operands[2] = GEN_INT (-INTVAL (operands[2]));
5502 return "sub{l}\t{%2, %k0|%k0, %2}";
5504 return "add{l}\t{%2, %k0|%k0, %2}";
5508 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5509 (const_string "incdec")
5510 (const_string "alu")))
5511 (set_attr "mode" "SI")])
5513 (define_insn "*addsi_3"
5515 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5516 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5517 (clobber (match_scratch:SI 0 "=r"))]
5518 "ix86_match_ccmode (insn, CCZmode)
5519 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5520 /* Current assemblers are broken and do not allow @GOTOFF in
5521 ought but a memory context. */
5522 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5524 switch (get_attr_type (insn))
5527 if (! rtx_equal_p (operands[0], operands[1]))
5529 if (operands[2] == const1_rtx)
5530 return "inc{l}\t%0";
5531 else if (operands[2] == constm1_rtx)
5532 return "dec{l}\t%0";
5537 if (! rtx_equal_p (operands[0], operands[1]))
5539 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5540 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5541 if (GET_CODE (operands[2]) == CONST_INT
5542 && (INTVAL (operands[2]) == 128
5543 || (INTVAL (operands[2]) < 0
5544 && INTVAL (operands[2]) != -128)))
5546 operands[2] = GEN_INT (-INTVAL (operands[2]));
5547 return "sub{l}\t{%2, %0|%0, %2}";
5549 return "add{l}\t{%2, %0|%0, %2}";
5553 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5554 (const_string "incdec")
5555 (const_string "alu")))
5556 (set_attr "mode" "SI")])
5558 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5559 (define_insn "*addsi_3_zext"
5561 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5562 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5563 (set (match_operand:DI 0 "register_operand" "=r")
5564 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5565 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5566 && ix86_binary_operator_ok (PLUS, SImode, operands)
5567 /* Current assemblers are broken and do not allow @GOTOFF in
5568 ought but a memory context. */
5569 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5571 switch (get_attr_type (insn))
5574 if (operands[2] == const1_rtx)
5575 return "inc{l}\t%k0";
5576 else if (operands[2] == constm1_rtx)
5577 return "dec{l}\t%k0";
5582 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5583 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5584 if (GET_CODE (operands[2]) == CONST_INT
5585 && (INTVAL (operands[2]) == 128
5586 || (INTVAL (operands[2]) < 0
5587 && INTVAL (operands[2]) != -128)))
5589 operands[2] = GEN_INT (-INTVAL (operands[2]));
5590 return "sub{l}\t{%2, %k0|%k0, %2}";
5592 return "add{l}\t{%2, %k0|%k0, %2}";
5596 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5597 (const_string "incdec")
5598 (const_string "alu")))
5599 (set_attr "mode" "SI")])
5601 ; For comparisons agains 1, -1 and 128, we may generate better code
5602 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5603 ; is matched then. We can't accept general immediate, because for
5604 ; case of overflows, the result is messed up.
5605 ; This pattern also don't hold of 0x80000000, since the value overflows
5607 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5608 ; only for comparisons not depending on it.
5609 (define_insn "*addsi_4"
5611 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5612 (match_operand:SI 2 "const_int_operand" "n")))
5613 (clobber (match_scratch:SI 0 "=rm"))]
5614 "ix86_match_ccmode (insn, CCGCmode)
5615 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5617 switch (get_attr_type (insn))
5620 if (operands[2] == constm1_rtx)
5621 return "inc{l}\t%0";
5622 else if (operands[2] == const1_rtx)
5623 return "dec{l}\t%0";
5628 if (! rtx_equal_p (operands[0], operands[1]))
5630 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5631 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5632 if ((INTVAL (operands[2]) == -128
5633 || (INTVAL (operands[2]) > 0
5634 && INTVAL (operands[2]) != 128)))
5635 return "sub{l}\t{%2, %0|%0, %2}";
5636 operands[2] = GEN_INT (-INTVAL (operands[2]));
5637 return "add{l}\t{%2, %0|%0, %2}";
5641 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5642 (const_string "incdec")
5643 (const_string "alu")))
5644 (set_attr "mode" "SI")])
5646 (define_insn "*addsi_5"
5649 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5650 (match_operand:SI 2 "general_operand" "rmni"))
5652 (clobber (match_scratch:SI 0 "=r"))]
5653 "ix86_match_ccmode (insn, CCGOCmode)
5654 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5655 /* Current assemblers are broken and do not allow @GOTOFF in
5656 ought but a memory context. */
5657 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5659 switch (get_attr_type (insn))
5662 if (! rtx_equal_p (operands[0], operands[1]))
5664 if (operands[2] == const1_rtx)
5665 return "inc{l}\t%0";
5666 else if (operands[2] == constm1_rtx)
5667 return "dec{l}\t%0";
5672 if (! rtx_equal_p (operands[0], operands[1]))
5674 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5675 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5676 if (GET_CODE (operands[2]) == CONST_INT
5677 && (INTVAL (operands[2]) == 128
5678 || (INTVAL (operands[2]) < 0
5679 && INTVAL (operands[2]) != -128)))
5681 operands[2] = GEN_INT (-INTVAL (operands[2]));
5682 return "sub{l}\t{%2, %0|%0, %2}";
5684 return "add{l}\t{%2, %0|%0, %2}";
5688 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5689 (const_string "incdec")
5690 (const_string "alu")))
5691 (set_attr "mode" "SI")])
5693 (define_expand "addhi3"
5694 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5695 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5696 (match_operand:HI 2 "general_operand" "")))
5697 (clobber (reg:CC 17))])]
5698 "TARGET_HIMODE_MATH"
5699 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5701 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5702 ;; type optimizations enabled by define-splits. This is not important
5703 ;; for PII, and in fact harmful because of partial register stalls.
5705 (define_insn "*addhi_1_lea"
5706 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5707 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5708 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
5709 (clobber (reg:CC 17))]
5710 "!TARGET_PARTIAL_REG_STALL
5711 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5713 switch (get_attr_type (insn))
5718 if (operands[2] == const1_rtx)
5719 return "inc{w}\t%0";
5720 else if (operands[2] == constm1_rtx)
5721 return "dec{w}\t%0";
5725 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5726 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5727 if (GET_CODE (operands[2]) == CONST_INT
5728 && (INTVAL (operands[2]) == 128
5729 || (INTVAL (operands[2]) < 0
5730 && INTVAL (operands[2]) != -128)))
5732 operands[2] = GEN_INT (-INTVAL (operands[2]));
5733 return "sub{w}\t{%2, %0|%0, %2}";
5735 return "add{w}\t{%2, %0|%0, %2}";
5739 (if_then_else (eq_attr "alternative" "2")
5740 (const_string "lea")
5741 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5742 (const_string "incdec")
5743 (const_string "alu"))))
5744 (set_attr "mode" "HI,HI,SI")])
5746 (define_insn "*addhi_1"
5747 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5748 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5749 (match_operand:HI 2 "general_operand" "ri,rm")))
5750 (clobber (reg:CC 17))]
5751 "TARGET_PARTIAL_REG_STALL
5752 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5754 switch (get_attr_type (insn))
5757 if (operands[2] == const1_rtx)
5758 return "inc{w}\t%0";
5759 else if (operands[2] == constm1_rtx)
5760 return "dec{w}\t%0";
5764 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5765 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5766 if (GET_CODE (operands[2]) == CONST_INT
5767 && (INTVAL (operands[2]) == 128
5768 || (INTVAL (operands[2]) < 0
5769 && INTVAL (operands[2]) != -128)))
5771 operands[2] = GEN_INT (-INTVAL (operands[2]));
5772 return "sub{w}\t{%2, %0|%0, %2}";
5774 return "add{w}\t{%2, %0|%0, %2}";
5778 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5779 (const_string "incdec")
5780 (const_string "alu")))
5781 (set_attr "mode" "HI")])
5783 (define_insn "*addhi_2"
5786 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5787 (match_operand:HI 2 "general_operand" "rmni,rni"))
5789 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
5790 (plus:HI (match_dup 1) (match_dup 2)))]
5791 "ix86_match_ccmode (insn, CCGOCmode)
5792 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5794 switch (get_attr_type (insn))
5797 if (operands[2] == const1_rtx)
5798 return "inc{w}\t%0";
5799 else if (operands[2] == constm1_rtx)
5800 return "dec{w}\t%0";
5804 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5805 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5806 if (GET_CODE (operands[2]) == CONST_INT
5807 && (INTVAL (operands[2]) == 128
5808 || (INTVAL (operands[2]) < 0
5809 && INTVAL (operands[2]) != -128)))
5811 operands[2] = GEN_INT (-INTVAL (operands[2]));
5812 return "sub{w}\t{%2, %0|%0, %2}";
5814 return "add{w}\t{%2, %0|%0, %2}";
5818 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5819 (const_string "incdec")
5820 (const_string "alu")))
5821 (set_attr "mode" "HI")])
5823 (define_insn "*addhi_3"
5825 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
5826 (match_operand:HI 1 "nonimmediate_operand" "%0")))
5827 (clobber (match_scratch:HI 0 "=r"))]
5828 "ix86_match_ccmode (insn, CCZmode)
5829 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5831 switch (get_attr_type (insn))
5834 if (operands[2] == const1_rtx)
5835 return "inc{w}\t%0";
5836 else if (operands[2] == constm1_rtx)
5837 return "dec{w}\t%0";
5841 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5842 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5843 if (GET_CODE (operands[2]) == CONST_INT
5844 && (INTVAL (operands[2]) == 128
5845 || (INTVAL (operands[2]) < 0
5846 && INTVAL (operands[2]) != -128)))
5848 operands[2] = GEN_INT (-INTVAL (operands[2]));
5849 return "sub{w}\t{%2, %0|%0, %2}";
5851 return "add{w}\t{%2, %0|%0, %2}";
5855 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5856 (const_string "incdec")
5857 (const_string "alu")))
5858 (set_attr "mode" "HI")])
5860 ; See comments above addsi_3_imm for details.
5861 (define_insn "*addhi_4"
5863 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
5864 (match_operand:HI 2 "const_int_operand" "n")))
5865 (clobber (match_scratch:HI 0 "=rm"))]
5866 "ix86_match_ccmode (insn, CCGCmode)
5867 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
5869 switch (get_attr_type (insn))
5872 if (operands[2] == constm1_rtx)
5873 return "inc{w}\t%0";
5874 else if (operands[2] == const1_rtx)
5875 return "dec{w}\t%0";
5880 if (! rtx_equal_p (operands[0], operands[1]))
5882 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5883 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5884 if ((INTVAL (operands[2]) == -128
5885 || (INTVAL (operands[2]) > 0
5886 && INTVAL (operands[2]) != 128)))
5887 return "sub{w}\t{%2, %0|%0, %2}";
5888 operands[2] = GEN_INT (-INTVAL (operands[2]));
5889 return "add{w}\t{%2, %0|%0, %2}";
5893 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5894 (const_string "incdec")
5895 (const_string "alu")))
5896 (set_attr "mode" "SI")])
5899 (define_insn "*addhi_5"
5902 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
5903 (match_operand:HI 2 "general_operand" "rmni"))
5905 (clobber (match_scratch:HI 0 "=r"))]
5906 "ix86_match_ccmode (insn, CCGOCmode)
5907 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5909 switch (get_attr_type (insn))
5912 if (operands[2] == const1_rtx)
5913 return "inc{w}\t%0";
5914 else if (operands[2] == constm1_rtx)
5915 return "dec{w}\t%0";
5919 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5920 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5921 if (GET_CODE (operands[2]) == CONST_INT
5922 && (INTVAL (operands[2]) == 128
5923 || (INTVAL (operands[2]) < 0
5924 && INTVAL (operands[2]) != -128)))
5926 operands[2] = GEN_INT (-INTVAL (operands[2]));
5927 return "sub{w}\t{%2, %0|%0, %2}";
5929 return "add{w}\t{%2, %0|%0, %2}";
5933 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5934 (const_string "incdec")
5935 (const_string "alu")))
5936 (set_attr "mode" "HI")])
5938 (define_expand "addqi3"
5939 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
5940 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
5941 (match_operand:QI 2 "general_operand" "")))
5942 (clobber (reg:CC 17))])]
5943 "TARGET_QIMODE_MATH"
5944 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
5946 ;; %%% Potential partial reg stall on alternative 2. What to do?
5947 (define_insn "*addqi_1_lea"
5948 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
5949 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
5950 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
5951 (clobber (reg:CC 17))]
5952 "!TARGET_PARTIAL_REG_STALL
5953 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5955 int widen = (which_alternative == 2);
5956 switch (get_attr_type (insn))
5961 if (operands[2] == const1_rtx)
5962 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
5963 else if (operands[2] == constm1_rtx)
5964 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
5968 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5969 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5970 if (GET_CODE (operands[2]) == CONST_INT
5971 && (INTVAL (operands[2]) == 128
5972 || (INTVAL (operands[2]) < 0
5973 && INTVAL (operands[2]) != -128)))
5975 operands[2] = GEN_INT (-INTVAL (operands[2]));
5977 return "sub{l}\t{%2, %k0|%k0, %2}";
5979 return "sub{b}\t{%2, %0|%0, %2}";
5982 return "add{l}\t{%k2, %k0|%k0, %k2}";
5984 return "add{b}\t{%2, %0|%0, %2}";
5988 (if_then_else (eq_attr "alternative" "3")
5989 (const_string "lea")
5990 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5991 (const_string "incdec")
5992 (const_string "alu"))))
5993 (set_attr "mode" "QI,QI,SI,SI")])
5995 (define_insn "*addqi_1"
5996 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
5997 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5998 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
5999 (clobber (reg:CC 17))]
6000 "TARGET_PARTIAL_REG_STALL
6001 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6003 int widen = (which_alternative == 2);
6004 switch (get_attr_type (insn))
6007 if (operands[2] == const1_rtx)
6008 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6009 else if (operands[2] == constm1_rtx)
6010 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6014 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6015 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6016 if (GET_CODE (operands[2]) == CONST_INT
6017 && (INTVAL (operands[2]) == 128
6018 || (INTVAL (operands[2]) < 0
6019 && INTVAL (operands[2]) != -128)))
6021 operands[2] = GEN_INT (-INTVAL (operands[2]));
6023 return "sub{l}\t{%2, %k0|%k0, %2}";
6025 return "sub{b}\t{%2, %0|%0, %2}";
6028 return "add{l}\t{%k2, %k0|%k0, %k2}";
6030 return "add{b}\t{%2, %0|%0, %2}";
6034 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6035 (const_string "incdec")
6036 (const_string "alu")))
6037 (set_attr "mode" "QI,QI,SI")])
6039 (define_insn "*addqi_1_slp"
6040 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6041 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6042 (match_operand:QI 2 "general_operand" "qn,qnm")))
6043 (clobber (reg:CC 17))]
6044 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6045 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6047 switch (get_attr_type (insn))
6050 if (operands[2] == const1_rtx)
6051 return "inc{b}\t%0";
6052 else if (operands[2] == constm1_rtx)
6053 return "dec{b}\t%0";
6057 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6058 if (GET_CODE (operands[2]) == CONST_INT
6059 && INTVAL (operands[2]) < 0)
6061 operands[2] = GEN_INT (-INTVAL (operands[2]));
6062 return "sub{b}\t{%2, %0|%0, %2}";
6064 return "add{b}\t{%2, %0|%0, %2}";
6068 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6069 (const_string "incdec")
6070 (const_string "alu")))
6071 (set_attr "mode" "QI")])
6073 (define_insn "*addqi_2"
6076 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6077 (match_operand:QI 2 "general_operand" "qmni,qni"))
6079 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6080 (plus:QI (match_dup 1) (match_dup 2)))]
6081 "ix86_match_ccmode (insn, CCGOCmode)
6082 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6084 switch (get_attr_type (insn))
6087 if (operands[2] == const1_rtx)
6088 return "inc{b}\t%0";
6089 else if (operands[2] == constm1_rtx
6090 || (GET_CODE (operands[2]) == CONST_INT
6091 && INTVAL (operands[2]) == 255))
6092 return "dec{b}\t%0";
6096 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6097 if (GET_CODE (operands[2]) == CONST_INT
6098 && INTVAL (operands[2]) < 0)
6100 operands[2] = GEN_INT (-INTVAL (operands[2]));
6101 return "sub{b}\t{%2, %0|%0, %2}";
6103 return "add{b}\t{%2, %0|%0, %2}";
6107 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6108 (const_string "incdec")
6109 (const_string "alu")))
6110 (set_attr "mode" "QI")])
6112 (define_insn "*addqi_3"
6114 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6115 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6116 (clobber (match_scratch:QI 0 "=q"))]
6117 "ix86_match_ccmode (insn, CCZmode)
6118 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6120 switch (get_attr_type (insn))
6123 if (operands[2] == const1_rtx)
6124 return "inc{b}\t%0";
6125 else if (operands[2] == constm1_rtx
6126 || (GET_CODE (operands[2]) == CONST_INT
6127 && INTVAL (operands[2]) == 255))
6128 return "dec{b}\t%0";
6132 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6133 if (GET_CODE (operands[2]) == CONST_INT
6134 && INTVAL (operands[2]) < 0)
6136 operands[2] = GEN_INT (-INTVAL (operands[2]));
6137 return "sub{b}\t{%2, %0|%0, %2}";
6139 return "add{b}\t{%2, %0|%0, %2}";
6143 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6144 (const_string "incdec")
6145 (const_string "alu")))
6146 (set_attr "mode" "QI")])
6148 ; See comments above addsi_3_imm for details.
6149 (define_insn "*addqi_4"
6151 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6152 (match_operand:QI 2 "const_int_operand" "n")))
6153 (clobber (match_scratch:QI 0 "=qm"))]
6154 "ix86_match_ccmode (insn, CCGCmode)
6155 && (INTVAL (operands[2]) & 0xff) != 0x80"
6157 switch (get_attr_type (insn))
6160 if (operands[2] == constm1_rtx
6161 || (GET_CODE (operands[2]) == CONST_INT
6162 && INTVAL (operands[2]) == 255))
6163 return "inc{b}\t%0";
6164 else if (operands[2] == const1_rtx)
6165 return "dec{b}\t%0";
6170 if (! rtx_equal_p (operands[0], operands[1]))
6172 if (INTVAL (operands[2]) < 0)
6174 operands[2] = GEN_INT (-INTVAL (operands[2]));
6175 return "add{b}\t{%2, %0|%0, %2}";
6177 return "sub{b}\t{%2, %0|%0, %2}";
6181 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6182 (const_string "incdec")
6183 (const_string "alu")))
6184 (set_attr "mode" "QI")])
6187 (define_insn "*addqi_5"
6190 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6191 (match_operand:QI 2 "general_operand" "qmni"))
6193 (clobber (match_scratch:QI 0 "=q"))]
6194 "ix86_match_ccmode (insn, CCGOCmode)
6195 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6197 switch (get_attr_type (insn))
6200 if (operands[2] == const1_rtx)
6201 return "inc{b}\t%0";
6202 else if (operands[2] == constm1_rtx
6203 || (GET_CODE (operands[2]) == CONST_INT
6204 && INTVAL (operands[2]) == 255))
6205 return "dec{b}\t%0";
6209 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6210 if (GET_CODE (operands[2]) == CONST_INT
6211 && INTVAL (operands[2]) < 0)
6213 operands[2] = GEN_INT (-INTVAL (operands[2]));
6214 return "sub{b}\t{%2, %0|%0, %2}";
6216 return "add{b}\t{%2, %0|%0, %2}";
6220 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6221 (const_string "incdec")
6222 (const_string "alu")))
6223 (set_attr "mode" "QI")])
6226 (define_insn "addqi_ext_1"
6227 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6232 (match_operand 1 "ext_register_operand" "0")
6235 (match_operand:QI 2 "general_operand" "Qmn")))
6236 (clobber (reg:CC 17))]
6239 switch (get_attr_type (insn))
6242 if (operands[2] == const1_rtx)
6243 return "inc{b}\t%h0";
6244 else if (operands[2] == constm1_rtx
6245 || (GET_CODE (operands[2]) == CONST_INT
6246 && INTVAL (operands[2]) == 255))
6247 return "dec{b}\t%h0";
6251 return "add{b}\t{%2, %h0|%h0, %2}";
6255 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6256 (const_string "incdec")
6257 (const_string "alu")))
6258 (set_attr "mode" "QI")])
6260 (define_insn "*addqi_ext_1_rex64"
6261 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6266 (match_operand 1 "ext_register_operand" "0")
6269 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6270 (clobber (reg:CC 17))]
6273 switch (get_attr_type (insn))
6276 if (operands[2] == const1_rtx)
6277 return "inc{b}\t%h0";
6278 else if (operands[2] == constm1_rtx
6279 || (GET_CODE (operands[2]) == CONST_INT
6280 && INTVAL (operands[2]) == 255))
6281 return "dec{b}\t%h0";
6285 return "add{b}\t{%2, %h0|%h0, %2}";
6289 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6290 (const_string "incdec")
6291 (const_string "alu")))
6292 (set_attr "mode" "QI")])
6294 (define_insn "*addqi_ext_2"
6295 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6300 (match_operand 1 "ext_register_operand" "%0")
6304 (match_operand 2 "ext_register_operand" "Q")
6307 (clobber (reg:CC 17))]
6309 "add{b}\t{%h2, %h0|%h0, %h2}"
6310 [(set_attr "type" "alu")
6311 (set_attr "mode" "QI")])
6313 ;; The patterns that match these are at the end of this file.
6315 (define_expand "addxf3"
6316 [(set (match_operand:XF 0 "register_operand" "")
6317 (plus:XF (match_operand:XF 1 "register_operand" "")
6318 (match_operand:XF 2 "register_operand" "")))]
6319 "!TARGET_64BIT && TARGET_80387"
6322 (define_expand "addtf3"
6323 [(set (match_operand:TF 0 "register_operand" "")
6324 (plus:TF (match_operand:TF 1 "register_operand" "")
6325 (match_operand:TF 2 "register_operand" "")))]
6329 (define_expand "adddf3"
6330 [(set (match_operand:DF 0 "register_operand" "")
6331 (plus:DF (match_operand:DF 1 "register_operand" "")
6332 (match_operand:DF 2 "nonimmediate_operand" "")))]
6333 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6336 (define_expand "addsf3"
6337 [(set (match_operand:SF 0 "register_operand" "")
6338 (plus:SF (match_operand:SF 1 "register_operand" "")
6339 (match_operand:SF 2 "nonimmediate_operand" "")))]
6340 "TARGET_80387 || TARGET_SSE_MATH"
6343 ;; Subtract instructions
6345 ;; %%% splits for subsidi3
6347 (define_expand "subdi3"
6348 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6349 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6350 (match_operand:DI 2 "x86_64_general_operand" "")))
6351 (clobber (reg:CC 17))])]
6353 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6355 (define_insn "*subdi3_1"
6356 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6357 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6358 (match_operand:DI 2 "general_operand" "roiF,riF")))
6359 (clobber (reg:CC 17))]
6364 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6365 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6366 (match_operand:DI 2 "general_operand" "")))
6367 (clobber (reg:CC 17))]
6368 "!TARGET_64BIT && reload_completed"
6369 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6370 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6371 (parallel [(set (match_dup 3)
6372 (minus:SI (match_dup 4)
6373 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6375 (clobber (reg:CC 17))])]
6376 "split_di (operands+0, 1, operands+0, operands+3);
6377 split_di (operands+1, 1, operands+1, operands+4);
6378 split_di (operands+2, 1, operands+2, operands+5);")
6380 (define_insn "subdi3_carry_rex64"
6381 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6382 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6383 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6384 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6385 (clobber (reg:CC 17))]
6386 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6387 "sbb{q}\t{%2, %0|%0, %2}"
6388 [(set_attr "type" "alu")
6389 (set_attr "pent_pair" "pu")
6390 (set_attr "ppro_uops" "few")
6391 (set_attr "mode" "DI")])
6393 (define_insn "*subdi_1_rex64"
6394 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6395 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6396 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6397 (clobber (reg:CC 17))]
6398 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6399 "sub{q}\t{%2, %0|%0, %2}"
6400 [(set_attr "type" "alu")
6401 (set_attr "mode" "DI")])
6403 (define_insn "*subdi_2_rex64"
6406 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6407 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6409 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6410 (minus:DI (match_dup 1) (match_dup 2)))]
6411 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6412 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6413 "sub{q}\t{%2, %0|%0, %2}"
6414 [(set_attr "type" "alu")
6415 (set_attr "mode" "DI")])
6417 (define_insn "*subdi_3_rex63"
6419 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6420 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6421 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6422 (minus:DI (match_dup 1) (match_dup 2)))]
6423 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6424 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6425 "sub{q}\t{%2, %0|%0, %2}"
6426 [(set_attr "type" "alu")
6427 (set_attr "mode" "DI")])
6430 (define_insn "subsi3_carry"
6431 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6432 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6433 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6434 (match_operand:SI 2 "general_operand" "ri,rm"))))
6435 (clobber (reg:CC 17))]
6436 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6437 "sbb{l}\t{%2, %0|%0, %2}"
6438 [(set_attr "type" "alu")
6439 (set_attr "pent_pair" "pu")
6440 (set_attr "ppro_uops" "few")
6441 (set_attr "mode" "SI")])
6443 (define_insn "subsi3_carry_zext"
6444 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6446 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6447 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6448 (match_operand:SI 2 "general_operand" "ri,rm")))))
6449 (clobber (reg:CC 17))]
6450 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6451 "sbb{l}\t{%2, %k0|%k0, %2}"
6452 [(set_attr "type" "alu")
6453 (set_attr "pent_pair" "pu")
6454 (set_attr "ppro_uops" "few")
6455 (set_attr "mode" "SI")])
6457 (define_expand "subsi3"
6458 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6459 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6460 (match_operand:SI 2 "general_operand" "")))
6461 (clobber (reg:CC 17))])]
6463 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6465 (define_insn "*subsi_1"
6466 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6467 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6468 (match_operand:SI 2 "general_operand" "ri,rm")))
6469 (clobber (reg:CC 17))]
6470 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6471 "sub{l}\t{%2, %0|%0, %2}"
6472 [(set_attr "type" "alu")
6473 (set_attr "mode" "SI")])
6475 (define_insn "*subsi_1_zext"
6476 [(set (match_operand:DI 0 "register_operand" "=r")
6478 (minus:SI (match_operand:SI 1 "register_operand" "0")
6479 (match_operand:SI 2 "general_operand" "rim"))))
6480 (clobber (reg:CC 17))]
6481 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6482 "sub{l}\t{%2, %k0|%k0, %2}"
6483 [(set_attr "type" "alu")
6484 (set_attr "mode" "SI")])
6486 (define_insn "*subsi_2"
6489 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6490 (match_operand:SI 2 "general_operand" "ri,rm"))
6492 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6493 (minus:SI (match_dup 1) (match_dup 2)))]
6494 "ix86_match_ccmode (insn, CCGOCmode)
6495 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6496 "sub{l}\t{%2, %0|%0, %2}"
6497 [(set_attr "type" "alu")
6498 (set_attr "mode" "SI")])
6500 (define_insn "*subsi_2_zext"
6503 (minus:SI (match_operand:SI 1 "register_operand" "0")
6504 (match_operand:SI 2 "general_operand" "rim"))
6506 (set (match_operand:DI 0 "register_operand" "=r")
6508 (minus:SI (match_dup 1)
6510 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6511 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6512 "sub{l}\t{%2, %k0|%k0, %2}"
6513 [(set_attr "type" "alu")
6514 (set_attr "mode" "SI")])
6516 (define_insn "*subsi_3"
6518 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6519 (match_operand:SI 2 "general_operand" "ri,rm")))
6520 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6521 (minus:SI (match_dup 1) (match_dup 2)))]
6522 "ix86_match_ccmode (insn, CCmode)
6523 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6524 "sub{l}\t{%2, %0|%0, %2}"
6525 [(set_attr "type" "alu")
6526 (set_attr "mode" "SI")])
6528 (define_insn "*subsi_3_zext"
6530 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6531 (match_operand:SI 2 "general_operand" "rim")))
6532 (set (match_operand:DI 0 "register_operand" "=r")
6534 (minus:SI (match_dup 1)
6536 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6537 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6538 "sub{q}\t{%2, %0|%0, %2}"
6539 [(set_attr "type" "alu")
6540 (set_attr "mode" "DI")])
6542 (define_expand "subhi3"
6543 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6544 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6545 (match_operand:HI 2 "general_operand" "")))
6546 (clobber (reg:CC 17))])]
6547 "TARGET_HIMODE_MATH"
6548 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6550 (define_insn "*subhi_1"
6551 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6552 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6553 (match_operand:HI 2 "general_operand" "ri,rm")))
6554 (clobber (reg:CC 17))]
6555 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6556 "sub{w}\t{%2, %0|%0, %2}"
6557 [(set_attr "type" "alu")
6558 (set_attr "mode" "HI")])
6560 (define_insn "*subhi_2"
6563 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6564 (match_operand:HI 2 "general_operand" "ri,rm"))
6566 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6567 (minus:HI (match_dup 1) (match_dup 2)))]
6568 "ix86_match_ccmode (insn, CCGOCmode)
6569 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6570 "sub{w}\t{%2, %0|%0, %2}"
6571 [(set_attr "type" "alu")
6572 (set_attr "mode" "HI")])
6574 (define_insn "*subhi_3"
6576 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6577 (match_operand:HI 2 "general_operand" "ri,rm")))
6578 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6579 (minus:HI (match_dup 1) (match_dup 2)))]
6580 "ix86_match_ccmode (insn, CCmode)
6581 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6582 "sub{w}\t{%2, %0|%0, %2}"
6583 [(set_attr "type" "alu")
6584 (set_attr "mode" "HI")])
6586 (define_expand "subqi3"
6587 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6588 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6589 (match_operand:QI 2 "general_operand" "")))
6590 (clobber (reg:CC 17))])]
6591 "TARGET_QIMODE_MATH"
6592 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6594 (define_insn "*subqi_1"
6595 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6596 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6597 (match_operand:QI 2 "general_operand" "qn,qmn")))
6598 (clobber (reg:CC 17))]
6599 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6600 "sub{b}\t{%2, %0|%0, %2}"
6601 [(set_attr "type" "alu")
6602 (set_attr "mode" "QI")])
6604 (define_insn "*subqi_1_slp"
6605 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6606 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6607 (match_operand:QI 2 "general_operand" "qn,qmn")))
6608 (clobber (reg:CC 17))]
6609 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6610 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6611 "sub{b}\t{%2, %0|%0, %2}"
6612 [(set_attr "type" "alu")
6613 (set_attr "mode" "QI")])
6615 (define_insn "*subqi_2"
6618 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6619 (match_operand:QI 2 "general_operand" "qi,qm"))
6621 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6622 (minus:HI (match_dup 1) (match_dup 2)))]
6623 "ix86_match_ccmode (insn, CCGOCmode)
6624 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6625 "sub{b}\t{%2, %0|%0, %2}"
6626 [(set_attr "type" "alu")
6627 (set_attr "mode" "QI")])
6629 (define_insn "*subqi_3"
6631 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6632 (match_operand:QI 2 "general_operand" "qi,qm")))
6633 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6634 (minus:HI (match_dup 1) (match_dup 2)))]
6635 "ix86_match_ccmode (insn, CCmode)
6636 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6637 "sub{b}\t{%2, %0|%0, %2}"
6638 [(set_attr "type" "alu")
6639 (set_attr "mode" "QI")])
6641 ;; The patterns that match these are at the end of this file.
6643 (define_expand "subxf3"
6644 [(set (match_operand:XF 0 "register_operand" "")
6645 (minus:XF (match_operand:XF 1 "register_operand" "")
6646 (match_operand:XF 2 "register_operand" "")))]
6647 "!TARGET_64BIT && TARGET_80387"
6650 (define_expand "subtf3"
6651 [(set (match_operand:TF 0 "register_operand" "")
6652 (minus:TF (match_operand:TF 1 "register_operand" "")
6653 (match_operand:TF 2 "register_operand" "")))]
6657 (define_expand "subdf3"
6658 [(set (match_operand:DF 0 "register_operand" "")
6659 (minus:DF (match_operand:DF 1 "register_operand" "")
6660 (match_operand:DF 2 "nonimmediate_operand" "")))]
6661 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6664 (define_expand "subsf3"
6665 [(set (match_operand:SF 0 "register_operand" "")
6666 (minus:SF (match_operand:SF 1 "register_operand" "")
6667 (match_operand:SF 2 "nonimmediate_operand" "")))]
6668 "TARGET_80387 || TARGET_SSE_MATH"
6671 ;; Multiply instructions
6673 (define_expand "muldi3"
6674 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6675 (mult:DI (match_operand:DI 1 "register_operand" "")
6676 (match_operand:DI 2 "x86_64_general_operand" "")))
6677 (clobber (reg:CC 17))])]
6681 (define_insn "*muldi3_1_rex64"
6682 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6683 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
6684 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6685 (clobber (reg:CC 17))]
6687 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6689 imul{q}\t{%2, %1, %0|%0, %1, %2}
6690 imul{q}\t{%2, %1, %0|%0, %1, %2}
6691 imul{q}\t{%2, %0|%0, %2}"
6692 [(set_attr "type" "imul")
6693 (set_attr "prefix_0f" "0,0,1")
6694 (set_attr "mode" "DI")])
6696 (define_expand "mulsi3"
6697 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6698 (mult:SI (match_operand:SI 1 "register_operand" "")
6699 (match_operand:SI 2 "general_operand" "")))
6700 (clobber (reg:CC 17))])]
6704 (define_insn "*mulsi3_1"
6705 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6706 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
6707 (match_operand:SI 2 "general_operand" "K,i,mr")))
6708 (clobber (reg:CC 17))]
6709 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6710 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
6711 ; there are two ways of writing the exact same machine instruction
6712 ; in assembly language. One, for example, is:
6716 ; while the other is:
6718 ; imul $12, %eax, %eax
6720 ; The first is simply short-hand for the latter. But, some assemblers,
6721 ; like the SCO OSR5 COFF assembler, don't handle the first form.
6723 imul{l}\t{%2, %1, %0|%0, %1, %2}
6724 imul{l}\t{%2, %1, %0|%0, %1, %2}
6725 imul{l}\t{%2, %0|%0, %2}"
6726 [(set_attr "type" "imul")
6727 (set_attr "prefix_0f" "0,0,1")
6728 (set_attr "mode" "SI")])
6730 (define_insn "*mulsi3_1_zext"
6731 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6733 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
6734 (match_operand:SI 2 "general_operand" "K,i,mr"))))
6735 (clobber (reg:CC 17))]
6737 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6738 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
6739 ; there are two ways of writing the exact same machine instruction
6740 ; in assembly language. One, for example, is:
6744 ; while the other is:
6746 ; imul $12, %eax, %eax
6748 ; The first is simply short-hand for the latter. But, some assemblers,
6749 ; like the SCO OSR5 COFF assembler, don't handle the first form.
6751 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6752 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6753 imul{l}\t{%2, %k0|%k0, %2}"
6754 [(set_attr "type" "imul")
6755 (set_attr "prefix_0f" "0,0,1")
6756 (set_attr "mode" "SI")])
6758 (define_expand "mulhi3"
6759 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6760 (mult:HI (match_operand:HI 1 "register_operand" "")
6761 (match_operand:HI 2 "general_operand" "")))
6762 (clobber (reg:CC 17))])]
6763 "TARGET_HIMODE_MATH"
6766 (define_insn "*mulhi3_1"
6767 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
6768 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
6769 (match_operand:HI 2 "general_operand" "K,i,mr")))
6770 (clobber (reg:CC 17))]
6771 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6772 ; %%% There was a note about "Assembler has weird restrictions",
6773 ; concerning alternative 1 when op1 == op0. True?
6775 imul{w}\t{%2, %1, %0|%0, %1, %2}
6776 imul{w}\t{%2, %1, %0|%0, %1, %2}
6777 imul{w}\t{%2, %0|%0, %2}"
6778 [(set_attr "type" "imul")
6779 (set_attr "prefix_0f" "0,0,1")
6780 (set_attr "mode" "HI")])
6782 (define_expand "mulqi3"
6783 [(parallel [(set (match_operand:QI 0 "register_operand" "")
6784 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
6785 (match_operand:QI 2 "register_operand" "")))
6786 (clobber (reg:CC 17))])]
6787 "TARGET_QIMODE_MATH"
6790 (define_insn "*mulqi3_1"
6791 [(set (match_operand:QI 0 "register_operand" "=a")
6792 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6793 (match_operand:QI 2 "nonimmediate_operand" "qm")))
6794 (clobber (reg:CC 17))]
6796 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6798 [(set_attr "type" "imul")
6799 (set_attr "length_immediate" "0")
6800 (set_attr "mode" "QI")])
6802 (define_expand "umulqihi3"
6803 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6804 (mult:HI (zero_extend:HI
6805 (match_operand:QI 1 "nonimmediate_operand" ""))
6807 (match_operand:QI 2 "register_operand" ""))))
6808 (clobber (reg:CC 17))])]
6809 "TARGET_QIMODE_MATH"
6812 (define_insn "*umulqihi3_1"
6813 [(set (match_operand:HI 0 "register_operand" "=a")
6814 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
6815 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6816 (clobber (reg:CC 17))]
6818 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6820 [(set_attr "type" "imul")
6821 (set_attr "length_immediate" "0")
6822 (set_attr "mode" "QI")])
6824 (define_expand "mulqihi3"
6825 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6826 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
6827 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
6828 (clobber (reg:CC 17))])]
6829 "TARGET_QIMODE_MATH"
6832 (define_insn "*mulqihi3_insn"
6833 [(set (match_operand:HI 0 "register_operand" "=a")
6834 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
6835 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6836 (clobber (reg:CC 17))]
6838 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6840 [(set_attr "type" "imul")
6841 (set_attr "length_immediate" "0")
6842 (set_attr "mode" "QI")])
6844 (define_expand "umulditi3"
6845 [(parallel [(set (match_operand:TI 0 "register_operand" "")
6846 (mult:TI (zero_extend:TI
6847 (match_operand:DI 1 "nonimmediate_operand" ""))
6849 (match_operand:DI 2 "register_operand" ""))))
6850 (clobber (reg:CC 17))])]
6854 (define_insn "*umulditi3_insn"
6855 [(set (match_operand:TI 0 "register_operand" "=A")
6856 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
6857 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
6858 (clobber (reg:CC 17))]
6860 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6862 [(set_attr "type" "imul")
6863 (set_attr "ppro_uops" "few")
6864 (set_attr "length_immediate" "0")
6865 (set_attr "mode" "DI")])
6867 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
6868 (define_expand "umulsidi3"
6869 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6870 (mult:DI (zero_extend:DI
6871 (match_operand:SI 1 "nonimmediate_operand" ""))
6873 (match_operand:SI 2 "register_operand" ""))))
6874 (clobber (reg:CC 17))])]
6878 (define_insn "*umulsidi3_insn"
6879 [(set (match_operand:DI 0 "register_operand" "=A")
6880 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
6881 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
6882 (clobber (reg:CC 17))]
6884 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6886 [(set_attr "type" "imul")
6887 (set_attr "ppro_uops" "few")
6888 (set_attr "length_immediate" "0")
6889 (set_attr "mode" "SI")])
6891 (define_expand "mulditi3"
6892 [(parallel [(set (match_operand:TI 0 "register_operand" "")
6893 (mult:TI (sign_extend:TI
6894 (match_operand:DI 1 "nonimmediate_operand" ""))
6896 (match_operand:DI 2 "register_operand" ""))))
6897 (clobber (reg:CC 17))])]
6901 (define_insn "*mulditi3_insn"
6902 [(set (match_operand:TI 0 "register_operand" "=A")
6903 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
6904 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
6905 (clobber (reg:CC 17))]
6907 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6909 [(set_attr "type" "imul")
6910 (set_attr "length_immediate" "0")
6911 (set_attr "mode" "DI")])
6913 (define_expand "mulsidi3"
6914 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6915 (mult:DI (sign_extend:DI
6916 (match_operand:SI 1 "nonimmediate_operand" ""))
6918 (match_operand:SI 2 "register_operand" ""))))
6919 (clobber (reg:CC 17))])]
6923 (define_insn "*mulsidi3_insn"
6924 [(set (match_operand:DI 0 "register_operand" "=A")
6925 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
6926 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
6927 (clobber (reg:CC 17))]
6929 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6931 [(set_attr "type" "imul")
6932 (set_attr "length_immediate" "0")
6933 (set_attr "mode" "SI")])
6935 (define_expand "umuldi3_highpart"
6936 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6939 (mult:TI (zero_extend:TI
6940 (match_operand:DI 1 "nonimmediate_operand" ""))
6942 (match_operand:DI 2 "register_operand" "")))
6944 (clobber (match_scratch:DI 3 ""))
6945 (clobber (reg:CC 17))])]
6949 (define_insn "*umuldi3_highpart_rex64"
6950 [(set (match_operand:DI 0 "register_operand" "=d")
6953 (mult:TI (zero_extend:TI
6954 (match_operand:DI 1 "nonimmediate_operand" "%a"))
6956 (match_operand:DI 2 "nonimmediate_operand" "rm")))
6958 (clobber (match_scratch:DI 3 "=1"))
6959 (clobber (reg:CC 17))]
6961 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6963 [(set_attr "type" "imul")
6964 (set_attr "ppro_uops" "few")
6965 (set_attr "length_immediate" "0")
6966 (set_attr "mode" "DI")])
6968 (define_expand "umulsi3_highpart"
6969 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6972 (mult:DI (zero_extend:DI
6973 (match_operand:SI 1 "nonimmediate_operand" ""))
6975 (match_operand:SI 2 "register_operand" "")))
6977 (clobber (match_scratch:SI 3 ""))
6978 (clobber (reg:CC 17))])]
6982 (define_insn "*umulsi3_highpart_insn"
6983 [(set (match_operand:SI 0 "register_operand" "=d")
6986 (mult:DI (zero_extend:DI
6987 (match_operand:SI 1 "nonimmediate_operand" "%a"))
6989 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6991 (clobber (match_scratch:SI 3 "=1"))
6992 (clobber (reg:CC 17))]
6993 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6995 [(set_attr "type" "imul")
6996 (set_attr "ppro_uops" "few")
6997 (set_attr "length_immediate" "0")
6998 (set_attr "mode" "SI")])
7000 (define_insn "*umulsi3_highpart_zext"
7001 [(set (match_operand:DI 0 "register_operand" "=d")
7002 (zero_extend:DI (truncate:SI
7004 (mult:DI (zero_extend:DI
7005 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7007 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7009 (clobber (match_scratch:SI 3 "=1"))
7010 (clobber (reg:CC 17))]
7012 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7014 [(set_attr "type" "imul")
7015 (set_attr "ppro_uops" "few")
7016 (set_attr "length_immediate" "0")
7017 (set_attr "mode" "SI")])
7019 (define_expand "smuldi3_highpart"
7020 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7023 (mult:TI (sign_extend:TI
7024 (match_operand:DI 1 "nonimmediate_operand" ""))
7026 (match_operand:DI 2 "register_operand" "")))
7028 (clobber (match_scratch:DI 3 ""))
7029 (clobber (reg:CC 17))])]
7033 (define_insn "*smuldi3_highpart_rex64"
7034 [(set (match_operand:DI 0 "register_operand" "=d")
7037 (mult:TI (sign_extend:TI
7038 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7040 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7042 (clobber (match_scratch:DI 3 "=1"))
7043 (clobber (reg:CC 17))]
7045 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7047 [(set_attr "type" "imul")
7048 (set_attr "ppro_uops" "few")
7049 (set_attr "mode" "DI")])
7051 (define_expand "smulsi3_highpart"
7052 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7055 (mult:DI (sign_extend:DI
7056 (match_operand:SI 1 "nonimmediate_operand" ""))
7058 (match_operand:SI 2 "register_operand" "")))
7060 (clobber (match_scratch:SI 3 ""))
7061 (clobber (reg:CC 17))])]
7065 (define_insn "*smulsi3_highpart_insn"
7066 [(set (match_operand:SI 0 "register_operand" "=d")
7069 (mult:DI (sign_extend:DI
7070 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7072 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7074 (clobber (match_scratch:SI 3 "=1"))
7075 (clobber (reg:CC 17))]
7076 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7078 [(set_attr "type" "imul")
7079 (set_attr "ppro_uops" "few")
7080 (set_attr "mode" "SI")])
7082 (define_insn "*smulsi3_highpart_zext"
7083 [(set (match_operand:DI 0 "register_operand" "=d")
7084 (zero_extend:DI (truncate:SI
7086 (mult:DI (sign_extend:DI
7087 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7089 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7091 (clobber (match_scratch:SI 3 "=1"))
7092 (clobber (reg:CC 17))]
7094 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7096 [(set_attr "type" "imul")
7097 (set_attr "ppro_uops" "few")
7098 (set_attr "mode" "SI")])
7100 ;; The patterns that match these are at the end of this file.
7102 (define_expand "mulxf3"
7103 [(set (match_operand:XF 0 "register_operand" "")
7104 (mult:XF (match_operand:XF 1 "register_operand" "")
7105 (match_operand:XF 2 "register_operand" "")))]
7106 "!TARGET_64BIT && TARGET_80387"
7109 (define_expand "multf3"
7110 [(set (match_operand:TF 0 "register_operand" "")
7111 (mult:TF (match_operand:TF 1 "register_operand" "")
7112 (match_operand:TF 2 "register_operand" "")))]
7116 (define_expand "muldf3"
7117 [(set (match_operand:DF 0 "register_operand" "")
7118 (mult:DF (match_operand:DF 1 "register_operand" "")
7119 (match_operand:DF 2 "nonimmediate_operand" "")))]
7120 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7123 (define_expand "mulsf3"
7124 [(set (match_operand:SF 0 "register_operand" "")
7125 (mult:SF (match_operand:SF 1 "register_operand" "")
7126 (match_operand:SF 2 "nonimmediate_operand" "")))]
7127 "TARGET_80387 || TARGET_SSE_MATH"
7130 ;; Divide instructions
7132 (define_insn "divqi3"
7133 [(set (match_operand:QI 0 "register_operand" "=a")
7134 (div:QI (match_operand:HI 1 "register_operand" "0")
7135 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7136 (clobber (reg:CC 17))]
7137 "TARGET_QIMODE_MATH"
7139 [(set_attr "type" "idiv")
7140 (set_attr "mode" "QI")
7141 (set_attr "ppro_uops" "few")])
7143 (define_insn "udivqi3"
7144 [(set (match_operand:QI 0 "register_operand" "=a")
7145 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7146 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7147 (clobber (reg:CC 17))]
7148 "TARGET_QIMODE_MATH"
7150 [(set_attr "type" "idiv")
7151 (set_attr "mode" "QI")
7152 (set_attr "ppro_uops" "few")])
7154 ;; The patterns that match these are at the end of this file.
7156 (define_expand "divxf3"
7157 [(set (match_operand:XF 0 "register_operand" "")
7158 (div:XF (match_operand:XF 1 "register_operand" "")
7159 (match_operand:XF 2 "register_operand" "")))]
7160 "!TARGET_64BIT && TARGET_80387"
7163 (define_expand "divtf3"
7164 [(set (match_operand:TF 0 "register_operand" "")
7165 (div:TF (match_operand:TF 1 "register_operand" "")
7166 (match_operand:TF 2 "register_operand" "")))]
7170 (define_expand "divdf3"
7171 [(set (match_operand:DF 0 "register_operand" "")
7172 (div:DF (match_operand:DF 1 "register_operand" "")
7173 (match_operand:DF 2 "nonimmediate_operand" "")))]
7174 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7177 (define_expand "divsf3"
7178 [(set (match_operand:SF 0 "register_operand" "")
7179 (div:SF (match_operand:SF 1 "register_operand" "")
7180 (match_operand:SF 2 "nonimmediate_operand" "")))]
7181 "TARGET_80387 || TARGET_SSE_MATH"
7184 ;; Remainder instructions.
7186 (define_expand "divmoddi4"
7187 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7188 (div:DI (match_operand:DI 1 "register_operand" "")
7189 (match_operand:DI 2 "nonimmediate_operand" "")))
7190 (set (match_operand:DI 3 "register_operand" "")
7191 (mod:DI (match_dup 1) (match_dup 2)))
7192 (clobber (reg:CC 17))])]
7196 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7197 ;; Penalize eax case sligthly because it results in worse scheduling
7199 (define_insn "*divmoddi4_nocltd_rex64"
7200 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7201 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7202 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7203 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7204 (mod:DI (match_dup 2) (match_dup 3)))
7205 (clobber (reg:CC 17))]
7206 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7208 [(set_attr "type" "multi")])
7210 (define_insn "*divmoddi4_cltd_rex64"
7211 [(set (match_operand:DI 0 "register_operand" "=a")
7212 (div:DI (match_operand:DI 2 "register_operand" "a")
7213 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7214 (set (match_operand:DI 1 "register_operand" "=&d")
7215 (mod:DI (match_dup 2) (match_dup 3)))
7216 (clobber (reg:CC 17))]
7217 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7219 [(set_attr "type" "multi")])
7221 (define_insn "*divmoddi_noext_rex64"
7222 [(set (match_operand:DI 0 "register_operand" "=a")
7223 (div:DI (match_operand:DI 1 "register_operand" "0")
7224 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7225 (set (match_operand:DI 3 "register_operand" "=d")
7226 (mod:DI (match_dup 1) (match_dup 2)))
7227 (use (match_operand:DI 4 "register_operand" "3"))
7228 (clobber (reg:CC 17))]
7231 [(set_attr "type" "idiv")
7232 (set_attr "mode" "DI")
7233 (set_attr "ppro_uops" "few")])
7236 [(set (match_operand:DI 0 "register_operand" "")
7237 (div:DI (match_operand:DI 1 "register_operand" "")
7238 (match_operand:DI 2 "nonimmediate_operand" "")))
7239 (set (match_operand:DI 3 "register_operand" "")
7240 (mod:DI (match_dup 1) (match_dup 2)))
7241 (clobber (reg:CC 17))]
7242 "TARGET_64BIT && reload_completed"
7243 [(parallel [(set (match_dup 3)
7244 (ashiftrt:DI (match_dup 4) (const_int 63)))
7245 (clobber (reg:CC 17))])
7246 (parallel [(set (match_dup 0)
7247 (div:DI (reg:DI 0) (match_dup 2)))
7249 (mod:DI (reg:DI 0) (match_dup 2)))
7251 (clobber (reg:CC 17))])]
7253 /* Avoid use of cltd in favour of a mov+shift. */
7254 if (!TARGET_USE_CLTD && !optimize_size)
7256 if (true_regnum (operands[1]))
7257 emit_move_insn (operands[0], operands[1]);
7259 emit_move_insn (operands[3], operands[1]);
7260 operands[4] = operands[3];
7264 if (true_regnum (operands[1]))
7266 operands[4] = operands[1];
7271 (define_expand "divmodsi4"
7272 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7273 (div:SI (match_operand:SI 1 "register_operand" "")
7274 (match_operand:SI 2 "nonimmediate_operand" "")))
7275 (set (match_operand:SI 3 "register_operand" "")
7276 (mod:SI (match_dup 1) (match_dup 2)))
7277 (clobber (reg:CC 17))])]
7281 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7282 ;; Penalize eax case sligthly because it results in worse scheduling
7284 (define_insn "*divmodsi4_nocltd"
7285 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7286 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7287 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7288 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7289 (mod:SI (match_dup 2) (match_dup 3)))
7290 (clobber (reg:CC 17))]
7291 "!optimize_size && !TARGET_USE_CLTD"
7293 [(set_attr "type" "multi")])
7295 (define_insn "*divmodsi4_cltd"
7296 [(set (match_operand:SI 0 "register_operand" "=a")
7297 (div:SI (match_operand:SI 2 "register_operand" "a")
7298 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7299 (set (match_operand:SI 1 "register_operand" "=&d")
7300 (mod:SI (match_dup 2) (match_dup 3)))
7301 (clobber (reg:CC 17))]
7302 "optimize_size || TARGET_USE_CLTD"
7304 [(set_attr "type" "multi")])
7306 (define_insn "*divmodsi_noext"
7307 [(set (match_operand:SI 0 "register_operand" "=a")
7308 (div:SI (match_operand:SI 1 "register_operand" "0")
7309 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7310 (set (match_operand:SI 3 "register_operand" "=d")
7311 (mod:SI (match_dup 1) (match_dup 2)))
7312 (use (match_operand:SI 4 "register_operand" "3"))
7313 (clobber (reg:CC 17))]
7316 [(set_attr "type" "idiv")
7317 (set_attr "mode" "SI")
7318 (set_attr "ppro_uops" "few")])
7321 [(set (match_operand:SI 0 "register_operand" "")
7322 (div:SI (match_operand:SI 1 "register_operand" "")
7323 (match_operand:SI 2 "nonimmediate_operand" "")))
7324 (set (match_operand:SI 3 "register_operand" "")
7325 (mod:SI (match_dup 1) (match_dup 2)))
7326 (clobber (reg:CC 17))]
7328 [(parallel [(set (match_dup 3)
7329 (ashiftrt:SI (match_dup 4) (const_int 31)))
7330 (clobber (reg:CC 17))])
7331 (parallel [(set (match_dup 0)
7332 (div:SI (reg:SI 0) (match_dup 2)))
7334 (mod:SI (reg:SI 0) (match_dup 2)))
7336 (clobber (reg:CC 17))])]
7338 /* Avoid use of cltd in favour of a mov+shift. */
7339 if (!TARGET_USE_CLTD && !optimize_size)
7341 if (true_regnum (operands[1]))
7342 emit_move_insn (operands[0], operands[1]);
7344 emit_move_insn (operands[3], operands[1]);
7345 operands[4] = operands[3];
7349 if (true_regnum (operands[1]))
7351 operands[4] = operands[1];
7355 (define_insn "divmodhi4"
7356 [(set (match_operand:HI 0 "register_operand" "=a")
7357 (div:HI (match_operand:HI 1 "register_operand" "0")
7358 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7359 (set (match_operand:HI 3 "register_operand" "=&d")
7360 (mod:HI (match_dup 1) (match_dup 2)))
7361 (clobber (reg:CC 17))]
7362 "TARGET_HIMODE_MATH"
7364 [(set_attr "type" "multi")
7365 (set_attr "length_immediate" "0")
7366 (set_attr "mode" "SI")])
7368 (define_insn "udivmoddi4"
7369 [(set (match_operand:DI 0 "register_operand" "=a")
7370 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7371 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7372 (set (match_operand:DI 3 "register_operand" "=&d")
7373 (umod:DI (match_dup 1) (match_dup 2)))
7374 (clobber (reg:CC 17))]
7376 "xor{q}\t%3, %3\;div{q}\t%2"
7377 [(set_attr "type" "multi")
7378 (set_attr "length_immediate" "0")
7379 (set_attr "mode" "DI")])
7381 (define_insn "*udivmoddi4_noext"
7382 [(set (match_operand:DI 0 "register_operand" "=a")
7383 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7384 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7385 (set (match_operand:DI 3 "register_operand" "=d")
7386 (umod:DI (match_dup 1) (match_dup 2)))
7388 (clobber (reg:CC 17))]
7391 [(set_attr "type" "idiv")
7392 (set_attr "ppro_uops" "few")
7393 (set_attr "mode" "DI")])
7396 [(set (match_operand:DI 0 "register_operand" "")
7397 (udiv:DI (match_operand:DI 1 "register_operand" "")
7398 (match_operand:DI 2 "nonimmediate_operand" "")))
7399 (set (match_operand:DI 3 "register_operand" "")
7400 (umod:DI (match_dup 1) (match_dup 2)))
7401 (clobber (reg:CC 17))]
7402 "TARGET_64BIT && reload_completed"
7403 [(set (match_dup 3) (const_int 0))
7404 (parallel [(set (match_dup 0)
7405 (udiv:DI (match_dup 1) (match_dup 2)))
7407 (umod:DI (match_dup 1) (match_dup 2)))
7409 (clobber (reg:CC 17))])]
7412 (define_insn "udivmodsi4"
7413 [(set (match_operand:SI 0 "register_operand" "=a")
7414 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7415 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7416 (set (match_operand:SI 3 "register_operand" "=&d")
7417 (umod:SI (match_dup 1) (match_dup 2)))
7418 (clobber (reg:CC 17))]
7420 "xor{l}\t%3, %3\;div{l}\t%2"
7421 [(set_attr "type" "multi")
7422 (set_attr "length_immediate" "0")
7423 (set_attr "mode" "SI")])
7425 (define_insn "*udivmodsi4_noext"
7426 [(set (match_operand:SI 0 "register_operand" "=a")
7427 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7428 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7429 (set (match_operand:SI 3 "register_operand" "=d")
7430 (umod:SI (match_dup 1) (match_dup 2)))
7432 (clobber (reg:CC 17))]
7435 [(set_attr "type" "idiv")
7436 (set_attr "ppro_uops" "few")
7437 (set_attr "mode" "SI")])
7440 [(set (match_operand:SI 0 "register_operand" "")
7441 (udiv:SI (match_operand:SI 1 "register_operand" "")
7442 (match_operand:SI 2 "nonimmediate_operand" "")))
7443 (set (match_operand:SI 3 "register_operand" "")
7444 (umod:SI (match_dup 1) (match_dup 2)))
7445 (clobber (reg:CC 17))]
7447 [(set (match_dup 3) (const_int 0))
7448 (parallel [(set (match_dup 0)
7449 (udiv:SI (match_dup 1) (match_dup 2)))
7451 (umod:SI (match_dup 1) (match_dup 2)))
7453 (clobber (reg:CC 17))])]
7456 (define_expand "udivmodhi4"
7457 [(set (match_dup 4) (const_int 0))
7458 (parallel [(set (match_operand:HI 0 "register_operand" "")
7459 (udiv:HI (match_operand:HI 1 "register_operand" "")
7460 (match_operand:HI 2 "nonimmediate_operand" "")))
7461 (set (match_operand:HI 3 "register_operand" "")
7462 (umod:HI (match_dup 1) (match_dup 2)))
7464 (clobber (reg:CC 17))])]
7465 "TARGET_HIMODE_MATH"
7466 "operands[4] = gen_reg_rtx (HImode);")
7468 (define_insn "*udivmodhi_noext"
7469 [(set (match_operand:HI 0 "register_operand" "=a")
7470 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7471 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7472 (set (match_operand:HI 3 "register_operand" "=d")
7473 (umod:HI (match_dup 1) (match_dup 2)))
7474 (use (match_operand:HI 4 "register_operand" "3"))
7475 (clobber (reg:CC 17))]
7478 [(set_attr "type" "idiv")
7479 (set_attr "mode" "HI")
7480 (set_attr "ppro_uops" "few")])
7482 ;; We can not use div/idiv for double division, because it causes
7483 ;; "division by zero" on the overflow and that's not what we expect
7484 ;; from truncate. Because true (non truncating) double division is
7485 ;; never generated, we can't create this insn anyway.
7488 ; [(set (match_operand:SI 0 "register_operand" "=a")
7490 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7492 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7493 ; (set (match_operand:SI 3 "register_operand" "=d")
7495 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7496 ; (clobber (reg:CC 17))]
7498 ; "div{l}\t{%2, %0|%0, %2}"
7499 ; [(set_attr "type" "idiv")
7500 ; (set_attr "ppro_uops" "few")])
7502 ;;- Logical AND instructions
7504 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7505 ;; Note that this excludes ah.
7507 (define_insn "*testdi_1_rex64"
7510 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7511 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7513 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7515 test{l}\t{%k1, %k0|%k0, %k1}
7516 test{l}\t{%k1, %k0|%k0, %k1}
7517 test{q}\t{%1, %0|%0, %1}
7518 test{q}\t{%1, %0|%0, %1}
7519 test{q}\t{%1, %0|%0, %1}"
7520 [(set_attr "type" "test")
7521 (set_attr "modrm" "0,1,0,1,1")
7522 (set_attr "mode" "SI,SI,DI,DI,DI")
7523 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7525 (define_insn "testsi_1"
7528 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7529 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7531 "ix86_match_ccmode (insn, CCNOmode)"
7532 "test{l}\t{%1, %0|%0, %1}"
7533 [(set_attr "type" "test")
7534 (set_attr "modrm" "0,1,1")
7535 (set_attr "mode" "SI")
7536 (set_attr "pent_pair" "uv,np,uv")])
7538 (define_expand "testsi_ccno_1"
7541 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7542 (match_operand:SI 1 "nonmemory_operand" ""))
7547 (define_insn "*testhi_1"
7549 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7550 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7552 "ix86_match_ccmode (insn, CCNOmode)"
7553 "test{w}\t{%1, %0|%0, %1}"
7554 [(set_attr "type" "test")
7555 (set_attr "modrm" "0,1,1")
7556 (set_attr "mode" "HI")
7557 (set_attr "pent_pair" "uv,np,uv")])
7559 (define_expand "testqi_ccz_1"
7561 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7562 (match_operand:QI 1 "nonmemory_operand" ""))
7567 (define_insn "*testqi_1"
7569 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7570 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7572 "ix86_match_ccmode (insn, CCNOmode)"
7574 if (which_alternative == 3)
7576 if (GET_CODE (operands[1]) == CONST_INT
7577 && (INTVAL (operands[1]) & 0xffffff00))
7578 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7579 return "test{l}\t{%1, %k0|%k0, %1}";
7581 return "test{b}\t{%1, %0|%0, %1}";
7583 [(set_attr "type" "test")
7584 (set_attr "modrm" "0,1,1,1")
7585 (set_attr "mode" "QI,QI,QI,SI")
7586 (set_attr "pent_pair" "uv,np,uv,np")])
7588 (define_expand "testqi_ext_ccno_0"
7593 (match_operand 0 "ext_register_operand" "")
7596 (match_operand 1 "const_int_operand" ""))
7601 (define_insn "*testqi_ext_0"
7606 (match_operand 0 "ext_register_operand" "Q")
7609 (match_operand 1 "const_int_operand" "n"))
7611 "ix86_match_ccmode (insn, CCNOmode)"
7612 "test{b}\t{%1, %h0|%h0, %1}"
7613 [(set_attr "type" "test")
7614 (set_attr "mode" "QI")
7615 (set_attr "length_immediate" "1")
7616 (set_attr "pent_pair" "np")])
7618 (define_insn "*testqi_ext_1"
7623 (match_operand 0 "ext_register_operand" "Q")
7627 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
7629 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7630 "test{b}\t{%1, %h0|%h0, %1}"
7631 [(set_attr "type" "test")
7632 (set_attr "mode" "QI")])
7634 (define_insn "*testqi_ext_1_rex64"
7639 (match_operand 0 "ext_register_operand" "Q")
7643 (match_operand:QI 1 "register_operand" "Q")))
7645 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7646 "test{b}\t{%1, %h0|%h0, %1}"
7647 [(set_attr "type" "test")
7648 (set_attr "mode" "QI")])
7650 (define_insn "*testqi_ext_2"
7655 (match_operand 0 "ext_register_operand" "Q")
7659 (match_operand 1 "ext_register_operand" "Q")
7663 "ix86_match_ccmode (insn, CCNOmode)"
7664 "test{b}\t{%h1, %h0|%h0, %h1}"
7665 [(set_attr "type" "test")
7666 (set_attr "mode" "QI")])
7668 ;; Combine likes to form bit extractions for some tests. Humor it.
7669 (define_insn "*testqi_ext_3"
7671 (compare (zero_extract:SI
7672 (match_operand 0 "nonimmediate_operand" "rm")
7673 (match_operand:SI 1 "const_int_operand" "")
7674 (match_operand:SI 2 "const_int_operand" ""))
7676 "ix86_match_ccmode (insn, CCNOmode)
7677 && (GET_MODE (operands[0]) == SImode
7678 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7679 || GET_MODE (operands[0]) == HImode
7680 || GET_MODE (operands[0]) == QImode)"
7683 (define_insn "*testqi_ext_3_rex64"
7685 (compare (zero_extract:DI
7686 (match_operand 0 "nonimmediate_operand" "rm")
7687 (match_operand:DI 1 "const_int_operand" "")
7688 (match_operand:DI 2 "const_int_operand" ""))
7691 && ix86_match_ccmode (insn, CCNOmode)
7692 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
7693 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
7694 /* Ensure that resulting mask is zero or sign extended operand. */
7695 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7696 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
7697 && INTVAL (operands[1]) > 32))
7698 && (GET_MODE (operands[0]) == SImode
7699 || GET_MODE (operands[0]) == DImode
7700 || GET_MODE (operands[0]) == HImode
7701 || GET_MODE (operands[0]) == QImode)"
7706 (compare (zero_extract
7707 (match_operand 0 "nonimmediate_operand" "")
7708 (match_operand 1 "const_int_operand" "")
7709 (match_operand 2 "const_int_operand" ""))
7711 "ix86_match_ccmode (insn, CCNOmode)"
7712 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
7714 HOST_WIDE_INT len = INTVAL (operands[1]);
7715 HOST_WIDE_INT pos = INTVAL (operands[2]);
7717 enum machine_mode mode, submode;
7719 mode = GET_MODE (operands[0]);
7720 if (GET_CODE (operands[0]) == MEM)
7722 /* ??? Combine likes to put non-volatile mem extractions in QImode
7723 no matter the size of the test. So find a mode that works. */
7724 if (! MEM_VOLATILE_P (operands[0]))
7726 mode = smallest_mode_for_size (pos + len, MODE_INT);
7727 operands[0] = adjust_address (operands[0], mode, 0);
7730 else if (GET_CODE (operands[0]) == SUBREG
7731 && (submode = GET_MODE (SUBREG_REG (operands[0])),
7732 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
7733 && pos + len <= GET_MODE_BITSIZE (submode))
7735 /* Narrow a paradoxical subreg to prevent partial register stalls. */
7737 operands[0] = SUBREG_REG (operands[0]);
7739 else if (mode == HImode && pos + len <= 8)
7741 /* Small HImode tests can be converted to QImode. */
7743 operands[0] = gen_lowpart (QImode, operands[0]);
7746 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
7747 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
7749 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
7752 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
7753 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
7754 ;; this is relatively important trick.
7755 ;; Do the converison only post-reload to avoid limiting of the register class
7760 (and (match_operand 0 "register_operand" "")
7761 (match_operand 1 "const_int_operand" ""))
7764 && QI_REG_P (operands[0])
7765 && ((ix86_match_ccmode (insn, CCZmode)
7766 && !(INTVAL (operands[1]) & ~(255 << 8)))
7767 || (ix86_match_ccmode (insn, CCNOmode)
7768 && !(INTVAL (operands[1]) & ~(127 << 8))))
7769 && GET_MODE (operands[0]) != QImode"
7772 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
7775 "operands[0] = gen_lowpart (SImode, operands[0]);
7776 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
7781 (and (match_operand 0 "nonimmediate_operand" "")
7782 (match_operand 1 "const_int_operand" ""))
7785 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
7786 && ((ix86_match_ccmode (insn, CCZmode)
7787 && !(INTVAL (operands[1]) & ~255))
7788 || (ix86_match_ccmode (insn, CCNOmode)
7789 && !(INTVAL (operands[1]) & ~127)))
7790 && GET_MODE (operands[0]) != QImode"
7793 (and:QI (match_dup 0)
7796 "operands[0] = gen_lowpart (QImode, operands[0]);
7797 operands[1] = gen_lowpart (QImode, operands[1]);")
7800 ;; %%% This used to optimize known byte-wide and operations to memory,
7801 ;; and sometimes to QImode registers. If this is considered useful,
7802 ;; it should be done with splitters.
7804 (define_expand "anddi3"
7805 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7806 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
7807 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
7808 (clobber (reg:CC 17))]
7810 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
7812 (define_insn "*anddi_1_rex64"
7813 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
7814 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
7815 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
7816 (clobber (reg:CC 17))]
7817 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
7819 switch (get_attr_type (insn))
7823 enum machine_mode mode;
7825 if (GET_CODE (operands[2]) != CONST_INT)
7827 if (INTVAL (operands[2]) == 0xff)
7829 else if (INTVAL (operands[2]) == 0xffff)
7834 operands[1] = gen_lowpart (mode, operands[1]);
7836 return "movz{bq|x}\t{%1,%0|%0, %1}";
7838 return "movz{wq|x}\t{%1,%0|%0, %1}";
7842 if (! rtx_equal_p (operands[0], operands[1]))
7844 if (get_attr_mode (insn) == MODE_SI)
7845 return "and{l}\t{%k2, %k0|%k0, %k2}";
7847 return "and{q}\t{%2, %0|%0, %2}";
7850 [(set_attr "type" "alu,alu,alu,imovx")
7851 (set_attr "length_immediate" "*,*,*,0")
7852 (set_attr "mode" "SI,DI,DI,DI")])
7854 (define_insn "*anddi_2"
7856 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
7857 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
7859 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
7860 (and:DI (match_dup 1) (match_dup 2)))]
7861 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7862 && ix86_binary_operator_ok (AND, DImode, operands)"
7864 and{l}\t{%k2, %k0|%k0, %k2}
7865 and{q}\t{%2, %0|%0, %2}
7866 and{q}\t{%2, %0|%0, %2}"
7867 [(set_attr "type" "alu")
7868 (set_attr "mode" "SI,DI,DI")])
7870 (define_expand "andsi3"
7871 [(set (match_operand:SI 0 "nonimmediate_operand" "")
7872 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
7873 (match_operand:SI 2 "general_operand" "")))
7874 (clobber (reg:CC 17))]
7876 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
7878 (define_insn "*andsi_1"
7879 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
7880 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
7881 (match_operand:SI 2 "general_operand" "ri,rm,L")))
7882 (clobber (reg:CC 17))]
7883 "ix86_binary_operator_ok (AND, SImode, operands)"
7885 switch (get_attr_type (insn))
7889 enum machine_mode mode;
7891 if (GET_CODE (operands[2]) != CONST_INT)
7893 if (INTVAL (operands[2]) == 0xff)
7895 else if (INTVAL (operands[2]) == 0xffff)
7900 operands[1] = gen_lowpart (mode, operands[1]);
7902 return "movz{bl|x}\t{%1,%0|%0, %1}";
7904 return "movz{wl|x}\t{%1,%0|%0, %1}";
7908 if (! rtx_equal_p (operands[0], operands[1]))
7910 return "and{l}\t{%2, %0|%0, %2}";
7913 [(set_attr "type" "alu,alu,imovx")
7914 (set_attr "length_immediate" "*,*,0")
7915 (set_attr "mode" "SI")])
7918 [(set (match_operand 0 "register_operand" "")
7920 (const_int -65536)))
7921 (clobber (reg:CC 17))]
7922 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
7923 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7924 "operands[1] = gen_lowpart (HImode, operands[0]);")
7927 [(set (match_operand 0 "ext_register_operand" "")
7930 (clobber (reg:CC 17))]
7931 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
7932 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7933 "operands[1] = gen_lowpart (QImode, operands[0]);")
7936 [(set (match_operand 0 "ext_register_operand" "")
7938 (const_int -65281)))
7939 (clobber (reg:CC 17))]
7940 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
7941 [(parallel [(set (zero_extract:SI (match_dup 0)
7945 (zero_extract:SI (match_dup 0)
7948 (zero_extract:SI (match_dup 0)
7951 (clobber (reg:CC 17))])]
7952 "operands[0] = gen_lowpart (SImode, operands[0]);")
7954 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
7955 (define_insn "*andsi_1_zext"
7956 [(set (match_operand:DI 0 "register_operand" "=r")
7958 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7959 (match_operand:SI 2 "general_operand" "rim"))))
7960 (clobber (reg:CC 17))]
7961 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
7962 "and{l}\t{%2, %k0|%k0, %2}"
7963 [(set_attr "type" "alu")
7964 (set_attr "mode" "SI")])
7966 (define_insn "*andsi_2"
7968 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
7969 (match_operand:SI 2 "general_operand" "rim,ri"))
7971 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
7972 (and:SI (match_dup 1) (match_dup 2)))]
7973 "ix86_match_ccmode (insn, CCNOmode)
7974 && ix86_binary_operator_ok (AND, SImode, operands)"
7975 "and{l}\t{%2, %0|%0, %2}"
7976 [(set_attr "type" "alu")
7977 (set_attr "mode" "SI")])
7979 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
7980 (define_insn "*andsi_2_zext"
7982 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7983 (match_operand:SI 2 "general_operand" "rim"))
7985 (set (match_operand:DI 0 "register_operand" "=r")
7986 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
7987 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7988 && ix86_binary_operator_ok (AND, SImode, operands)"
7989 "and{l}\t{%2, %k0|%k0, %2}"
7990 [(set_attr "type" "alu")
7991 (set_attr "mode" "SI")])
7993 (define_expand "andhi3"
7994 [(set (match_operand:HI 0 "nonimmediate_operand" "")
7995 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
7996 (match_operand:HI 2 "general_operand" "")))
7997 (clobber (reg:CC 17))]
7998 "TARGET_HIMODE_MATH"
7999 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8001 (define_insn "*andhi_1"
8002 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8003 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8004 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8005 (clobber (reg:CC 17))]
8006 "ix86_binary_operator_ok (AND, HImode, operands)"
8008 switch (get_attr_type (insn))
8011 if (GET_CODE (operands[2]) != CONST_INT)
8013 if (INTVAL (operands[2]) == 0xff)
8014 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8018 if (! rtx_equal_p (operands[0], operands[1]))
8021 return "and{w}\t{%2, %0|%0, %2}";
8024 [(set_attr "type" "alu,alu,imovx")
8025 (set_attr "length_immediate" "*,*,0")
8026 (set_attr "mode" "HI,HI,SI")])
8028 (define_insn "*andhi_2"
8030 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8031 (match_operand:HI 2 "general_operand" "rim,ri"))
8033 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8034 (and:HI (match_dup 1) (match_dup 2)))]
8035 "ix86_match_ccmode (insn, CCNOmode)
8036 && ix86_binary_operator_ok (AND, HImode, operands)"
8037 "and{w}\t{%2, %0|%0, %2}"
8038 [(set_attr "type" "alu")
8039 (set_attr "mode" "HI")])
8041 (define_expand "andqi3"
8042 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8043 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8044 (match_operand:QI 2 "general_operand" "")))
8045 (clobber (reg:CC 17))]
8046 "TARGET_QIMODE_MATH"
8047 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8049 ;; %%% Potential partial reg stall on alternative 2. What to do?
8050 (define_insn "*andqi_1"
8051 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8052 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8053 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8054 (clobber (reg:CC 17))]
8055 "ix86_binary_operator_ok (AND, QImode, operands)"
8057 and{b}\t{%2, %0|%0, %2}
8058 and{b}\t{%2, %0|%0, %2}
8059 and{l}\t{%k2, %k0|%k0, %k2}"
8060 [(set_attr "type" "alu")
8061 (set_attr "mode" "QI,QI,SI")])
8063 (define_insn "*andqi_1_slp"
8064 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8065 (and:QI (match_dup 0)
8066 (match_operand:QI 1 "general_operand" "qi,qmi")))
8067 (clobber (reg:CC 17))]
8068 "! TARGET_PARTIAL_REG_STALL || optimize_size"
8069 "and{b}\t{%1, %0|%0, %1}"
8070 [(set_attr "type" "alu1")
8071 (set_attr "mode" "QI")])
8073 (define_insn "*andqi_2"
8076 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8077 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8079 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8080 (and:QI (match_dup 1) (match_dup 2)))]
8081 "ix86_match_ccmode (insn, CCNOmode)
8082 && ix86_binary_operator_ok (AND, QImode, operands)"
8084 if (which_alternative == 2)
8086 if (GET_CODE (operands[2]) == CONST_INT
8087 && (INTVAL (operands[2]) & 0xffffff00))
8088 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8089 return "and{l}\t{%2, %k0|%k0, %2}";
8091 return "and{b}\t{%2, %0|%0, %2}";
8093 [(set_attr "type" "alu")
8094 (set_attr "mode" "QI,QI,SI")])
8096 (define_insn "*andqi_2_slp"
8099 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8100 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8102 (set (strict_low_part (match_dup 0))
8103 (and:QI (match_dup 0) (match_dup 1)))]
8104 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8105 && ix86_match_ccmode (insn, CCNOmode)"
8106 "and{b}\t{%1, %0|%0, %1}"
8107 [(set_attr "type" "alu1")
8108 (set_attr "mode" "QI")])
8110 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8111 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8112 ;; for a QImode operand, which of course failed.
8114 (define_insn "andqi_ext_0"
8115 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8120 (match_operand 1 "ext_register_operand" "0")
8123 (match_operand 2 "const_int_operand" "n")))
8124 (clobber (reg:CC 17))]
8126 "and{b}\t{%2, %h0|%h0, %2}"
8127 [(set_attr "type" "alu")
8128 (set_attr "length_immediate" "1")
8129 (set_attr "mode" "QI")])
8131 ;; Generated by peephole translating test to and. This shows up
8132 ;; often in fp comparisons.
8134 (define_insn "*andqi_ext_0_cc"
8139 (match_operand 1 "ext_register_operand" "0")
8142 (match_operand 2 "const_int_operand" "n"))
8144 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8153 "ix86_match_ccmode (insn, CCNOmode)"
8154 "and{b}\t{%2, %h0|%h0, %2}"
8155 [(set_attr "type" "alu")
8156 (set_attr "length_immediate" "1")
8157 (set_attr "mode" "QI")])
8159 (define_insn "*andqi_ext_1"
8160 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8165 (match_operand 1 "ext_register_operand" "0")
8169 (match_operand:QI 2 "general_operand" "Qm"))))
8170 (clobber (reg:CC 17))]
8172 "and{b}\t{%2, %h0|%h0, %2}"
8173 [(set_attr "type" "alu")
8174 (set_attr "length_immediate" "0")
8175 (set_attr "mode" "QI")])
8177 (define_insn "*andqi_ext_1_rex64"
8178 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8183 (match_operand 1 "ext_register_operand" "0")
8187 (match_operand 2 "ext_register_operand" "Q"))))
8188 (clobber (reg:CC 17))]
8190 "and{b}\t{%2, %h0|%h0, %2}"
8191 [(set_attr "type" "alu")
8192 (set_attr "length_immediate" "0")
8193 (set_attr "mode" "QI")])
8195 (define_insn "*andqi_ext_2"
8196 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8201 (match_operand 1 "ext_register_operand" "%0")
8205 (match_operand 2 "ext_register_operand" "Q")
8208 (clobber (reg:CC 17))]
8210 "and{b}\t{%h2, %h0|%h0, %h2}"
8211 [(set_attr "type" "alu")
8212 (set_attr "length_immediate" "0")
8213 (set_attr "mode" "QI")])
8215 ;; Convert wide AND instructions with immediate operand to shorter QImode
8216 ;; equivalents when possible.
8217 ;; Don't do the splitting with memory operands, since it intoduces risc
8218 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8219 ;; for size, but that can (should?) be handled by generic code instead.
8221 [(set (match_operand 0 "register_operand" "")
8222 (and (match_operand 1 "register_operand" "")
8223 (match_operand 2 "const_int_operand" "")))
8224 (clobber (reg:CC 17))]
8226 && QI_REG_P (operands[0])
8227 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8228 && !(~INTVAL (operands[2]) & ~(255 << 8))
8229 && GET_MODE (operands[0]) != QImode"
8230 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8231 (and:SI (zero_extract:SI (match_dup 1)
8232 (const_int 8) (const_int 8))
8234 (clobber (reg:CC 17))])]
8235 "operands[0] = gen_lowpart (SImode, operands[0]);
8236 operands[1] = gen_lowpart (SImode, operands[1]);
8237 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8239 ;; Since AND can be encoded with sign extended immediate, this is only
8240 ;; profitable when 7th bit is not set.
8242 [(set (match_operand 0 "register_operand" "")
8243 (and (match_operand 1 "general_operand" "")
8244 (match_operand 2 "const_int_operand" "")))
8245 (clobber (reg:CC 17))]
8247 && ANY_QI_REG_P (operands[0])
8248 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8249 && !(~INTVAL (operands[2]) & ~255)
8250 && !(INTVAL (operands[2]) & 128)
8251 && GET_MODE (operands[0]) != QImode"
8252 [(parallel [(set (strict_low_part (match_dup 0))
8253 (and:QI (match_dup 1)
8255 (clobber (reg:CC 17))])]
8256 "operands[0] = gen_lowpart (QImode, operands[0]);
8257 operands[1] = gen_lowpart (QImode, operands[1]);
8258 operands[2] = gen_lowpart (QImode, operands[2]);")
8260 ;; Logical inclusive OR instructions
8262 ;; %%% This used to optimize known byte-wide and operations to memory.
8263 ;; If this is considered useful, it should be done with splitters.
8265 (define_expand "iordi3"
8266 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8267 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8268 (match_operand:DI 2 "x86_64_general_operand" "")))
8269 (clobber (reg:CC 17))]
8271 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8273 (define_insn "*iordi_1_rex64"
8274 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8275 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8276 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8277 (clobber (reg:CC 17))]
8279 && ix86_binary_operator_ok (IOR, DImode, operands)"
8280 "or{q}\t{%2, %0|%0, %2}"
8281 [(set_attr "type" "alu")
8282 (set_attr "mode" "DI")])
8284 (define_insn "*iordi_2_rex64"
8286 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8287 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8289 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8290 (ior:DI (match_dup 1) (match_dup 2)))]
8292 && ix86_match_ccmode (insn, CCNOmode)
8293 && ix86_binary_operator_ok (IOR, DImode, operands)"
8294 "or{q}\t{%2, %0|%0, %2}"
8295 [(set_attr "type" "alu")
8296 (set_attr "mode" "DI")])
8298 (define_insn "*iordi_3_rex64"
8300 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8301 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8303 (clobber (match_scratch:DI 0 "=r"))]
8305 && ix86_match_ccmode (insn, CCNOmode)
8306 && ix86_binary_operator_ok (IOR, DImode, operands)"
8307 "or{q}\t{%2, %0|%0, %2}"
8308 [(set_attr "type" "alu")
8309 (set_attr "mode" "DI")])
8312 (define_expand "iorsi3"
8313 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8314 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8315 (match_operand:SI 2 "general_operand" "")))
8316 (clobber (reg:CC 17))]
8318 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8320 (define_insn "*iorsi_1"
8321 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8322 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8323 (match_operand:SI 2 "general_operand" "ri,rmi")))
8324 (clobber (reg:CC 17))]
8325 "ix86_binary_operator_ok (IOR, SImode, operands)"
8326 "or{l}\t{%2, %0|%0, %2}"
8327 [(set_attr "type" "alu")
8328 (set_attr "mode" "SI")])
8330 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8331 (define_insn "*iorsi_1_zext"
8332 [(set (match_operand:DI 0 "register_operand" "=rm")
8334 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8335 (match_operand:SI 2 "general_operand" "rim"))))
8336 (clobber (reg:CC 17))]
8337 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8338 "or{l}\t{%2, %k0|%k0, %2}"
8339 [(set_attr "type" "alu")
8340 (set_attr "mode" "SI")])
8342 (define_insn "*iorsi_1_zext_imm"
8343 [(set (match_operand:DI 0 "register_operand" "=rm")
8344 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8345 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8346 (clobber (reg:CC 17))]
8348 "or{l}\t{%2, %k0|%k0, %2}"
8349 [(set_attr "type" "alu")
8350 (set_attr "mode" "SI")])
8352 (define_insn "*iorsi_2"
8354 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8355 (match_operand:SI 2 "general_operand" "rim,ri"))
8357 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8358 (ior:SI (match_dup 1) (match_dup 2)))]
8359 "ix86_match_ccmode (insn, CCNOmode)
8360 && ix86_binary_operator_ok (IOR, SImode, operands)"
8361 "or{l}\t{%2, %0|%0, %2}"
8362 [(set_attr "type" "alu")
8363 (set_attr "mode" "SI")])
8365 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8366 ;; ??? Special case for immediate operand is missing - it is tricky.
8367 (define_insn "*iorsi_2_zext"
8369 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8370 (match_operand:SI 2 "general_operand" "rim"))
8372 (set (match_operand:DI 0 "register_operand" "=r")
8373 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8374 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8375 && ix86_binary_operator_ok (IOR, SImode, operands)"
8376 "or{l}\t{%2, %k0|%k0, %2}"
8377 [(set_attr "type" "alu")
8378 (set_attr "mode" "SI")])
8380 (define_insn "*iorsi_2_zext_imm"
8382 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8383 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8385 (set (match_operand:DI 0 "register_operand" "=r")
8386 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8387 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8388 && ix86_binary_operator_ok (IOR, SImode, operands)"
8389 "or{l}\t{%2, %k0|%k0, %2}"
8390 [(set_attr "type" "alu")
8391 (set_attr "mode" "SI")])
8393 (define_insn "*iorsi_3"
8395 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8396 (match_operand:SI 2 "general_operand" "rim"))
8398 (clobber (match_scratch:SI 0 "=r"))]
8399 "ix86_match_ccmode (insn, CCNOmode)
8400 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8401 "or{l}\t{%2, %0|%0, %2}"
8402 [(set_attr "type" "alu")
8403 (set_attr "mode" "SI")])
8405 (define_expand "iorhi3"
8406 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8407 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8408 (match_operand:HI 2 "general_operand" "")))
8409 (clobber (reg:CC 17))]
8410 "TARGET_HIMODE_MATH"
8411 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8413 (define_insn "*iorhi_1"
8414 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8415 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8416 (match_operand:HI 2 "general_operand" "rmi,ri")))
8417 (clobber (reg:CC 17))]
8418 "ix86_binary_operator_ok (IOR, HImode, operands)"
8419 "or{w}\t{%2, %0|%0, %2}"
8420 [(set_attr "type" "alu")
8421 (set_attr "mode" "HI")])
8423 (define_insn "*iorhi_2"
8425 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8426 (match_operand:HI 2 "general_operand" "rim,ri"))
8428 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8429 (ior:HI (match_dup 1) (match_dup 2)))]
8430 "ix86_match_ccmode (insn, CCNOmode)
8431 && ix86_binary_operator_ok (IOR, HImode, operands)"
8432 "or{w}\t{%2, %0|%0, %2}"
8433 [(set_attr "type" "alu")
8434 (set_attr "mode" "HI")])
8436 (define_insn "*iorhi_3"
8438 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8439 (match_operand:HI 2 "general_operand" "rim"))
8441 (clobber (match_scratch:HI 0 "=r"))]
8442 "ix86_match_ccmode (insn, CCNOmode)
8443 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8444 "or{w}\t{%2, %0|%0, %2}"
8445 [(set_attr "type" "alu")
8446 (set_attr "mode" "HI")])
8448 (define_expand "iorqi3"
8449 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8450 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8451 (match_operand:QI 2 "general_operand" "")))
8452 (clobber (reg:CC 17))]
8453 "TARGET_QIMODE_MATH"
8454 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8456 ;; %%% Potential partial reg stall on alternative 2. What to do?
8457 (define_insn "*iorqi_1"
8458 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8459 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8460 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8461 (clobber (reg:CC 17))]
8462 "ix86_binary_operator_ok (IOR, QImode, operands)"
8464 or{b}\t{%2, %0|%0, %2}
8465 or{b}\t{%2, %0|%0, %2}
8466 or{l}\t{%k2, %k0|%k0, %k2}"
8467 [(set_attr "type" "alu")
8468 (set_attr "mode" "QI,QI,SI")])
8470 (define_insn "*iorqi_1_slp"
8471 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8472 (ior:QI (match_dup 0)
8473 (match_operand:QI 1 "general_operand" "qmi,qi")))
8474 (clobber (reg:CC 17))]
8475 "! TARGET_PARTIAL_REG_STALL || optimize_size"
8476 "or{b}\t{%1, %0|%0, %1}"
8477 [(set_attr "type" "alu1")
8478 (set_attr "mode" "QI")])
8480 (define_insn "*iorqi_2"
8482 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8483 (match_operand:QI 2 "general_operand" "qim,qi"))
8485 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8486 (ior:QI (match_dup 1) (match_dup 2)))]
8487 "ix86_match_ccmode (insn, CCNOmode)
8488 && ix86_binary_operator_ok (IOR, QImode, operands)"
8489 "or{b}\t{%2, %0|%0, %2}"
8490 [(set_attr "type" "alu")
8491 (set_attr "mode" "QI")])
8493 (define_insn "*iorqi_2_slp"
8495 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8496 (match_operand:QI 1 "general_operand" "qim,qi"))
8498 (set (strict_low_part (match_dup 0))
8499 (ior:QI (match_dup 0) (match_dup 1)))]
8500 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8501 && ix86_match_ccmode (insn, CCNOmode)"
8502 "or{b}\t{%1, %0|%0, %1}"
8503 [(set_attr "type" "alu1")
8504 (set_attr "mode" "QI")])
8506 (define_insn "*iorqi_3"
8508 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8509 (match_operand:QI 2 "general_operand" "qim"))
8511 (clobber (match_scratch:QI 0 "=q"))]
8512 "ix86_match_ccmode (insn, CCNOmode)
8513 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8514 "or{b}\t{%2, %0|%0, %2}"
8515 [(set_attr "type" "alu")
8516 (set_attr "mode" "QI")])
8518 (define_insn "iorqi_ext_0"
8519 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8524 (match_operand 1 "ext_register_operand" "0")
8527 (match_operand 2 "const_int_operand" "n")))
8528 (clobber (reg:CC 17))]
8529 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8530 "or{b}\t{%2, %h0|%h0, %2}"
8531 [(set_attr "type" "alu")
8532 (set_attr "length_immediate" "1")
8533 (set_attr "mode" "QI")])
8535 (define_insn "*iorqi_ext_1"
8536 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8541 (match_operand 1 "ext_register_operand" "0")
8545 (match_operand:QI 2 "general_operand" "Qm"))))
8546 (clobber (reg:CC 17))]
8548 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8549 "or{b}\t{%2, %h0|%h0, %2}"
8550 [(set_attr "type" "alu")
8551 (set_attr "length_immediate" "0")
8552 (set_attr "mode" "QI")])
8554 (define_insn "*iorqi_ext_1_rex64"
8555 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8560 (match_operand 1 "ext_register_operand" "0")
8564 (match_operand 2 "ext_register_operand" "Q"))))
8565 (clobber (reg:CC 17))]
8567 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8568 "or{b}\t{%2, %h0|%h0, %2}"
8569 [(set_attr "type" "alu")
8570 (set_attr "length_immediate" "0")
8571 (set_attr "mode" "QI")])
8573 (define_insn "*iorqi_ext_2"
8574 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8578 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8581 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8584 (clobber (reg:CC 17))]
8585 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8586 "ior{b}\t{%h2, %h0|%h0, %h2}"
8587 [(set_attr "type" "alu")
8588 (set_attr "length_immediate" "0")
8589 (set_attr "mode" "QI")])
8592 [(set (match_operand 0 "register_operand" "")
8593 (ior (match_operand 1 "register_operand" "")
8594 (match_operand 2 "const_int_operand" "")))
8595 (clobber (reg:CC 17))]
8597 && QI_REG_P (operands[0])
8598 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8599 && !(INTVAL (operands[2]) & ~(255 << 8))
8600 && GET_MODE (operands[0]) != QImode"
8601 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8602 (ior:SI (zero_extract:SI (match_dup 1)
8603 (const_int 8) (const_int 8))
8605 (clobber (reg:CC 17))])]
8606 "operands[0] = gen_lowpart (SImode, operands[0]);
8607 operands[1] = gen_lowpart (SImode, operands[1]);
8608 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8610 ;; Since OR can be encoded with sign extended immediate, this is only
8611 ;; profitable when 7th bit is set.
8613 [(set (match_operand 0 "register_operand" "")
8614 (ior (match_operand 1 "general_operand" "")
8615 (match_operand 2 "const_int_operand" "")))
8616 (clobber (reg:CC 17))]
8618 && ANY_QI_REG_P (operands[0])
8619 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8620 && !(INTVAL (operands[2]) & ~255)
8621 && (INTVAL (operands[2]) & 128)
8622 && GET_MODE (operands[0]) != QImode"
8623 [(parallel [(set (strict_low_part (match_dup 0))
8624 (ior:QI (match_dup 1)
8626 (clobber (reg:CC 17))])]
8627 "operands[0] = gen_lowpart (QImode, operands[0]);
8628 operands[1] = gen_lowpart (QImode, operands[1]);
8629 operands[2] = gen_lowpart (QImode, operands[2]);")
8631 ;; Logical XOR instructions
8633 ;; %%% This used to optimize known byte-wide and operations to memory.
8634 ;; If this is considered useful, it should be done with splitters.
8636 (define_expand "xordi3"
8637 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8638 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8639 (match_operand:DI 2 "x86_64_general_operand" "")))
8640 (clobber (reg:CC 17))]
8642 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8644 (define_insn "*xordi_1_rex64"
8645 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8646 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8647 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8648 (clobber (reg:CC 17))]
8650 && ix86_binary_operator_ok (XOR, DImode, operands)"
8652 xor{q}\t{%2, %0|%0, %2}
8653 xor{q}\t{%2, %0|%0, %2}"
8654 [(set_attr "type" "alu")
8655 (set_attr "mode" "DI,DI")])
8657 (define_insn "*xordi_2_rex64"
8659 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8660 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8662 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8663 (xor:DI (match_dup 1) (match_dup 2)))]
8665 && ix86_match_ccmode (insn, CCNOmode)
8666 && ix86_binary_operator_ok (XOR, DImode, operands)"
8668 xor{q}\t{%2, %0|%0, %2}
8669 xor{q}\t{%2, %0|%0, %2}"
8670 [(set_attr "type" "alu")
8671 (set_attr "mode" "DI,DI")])
8673 (define_insn "*xordi_3_rex64"
8675 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8676 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8678 (clobber (match_scratch:DI 0 "=r"))]
8680 && ix86_match_ccmode (insn, CCNOmode)
8681 && ix86_binary_operator_ok (XOR, DImode, operands)"
8682 "xor{q}\t{%2, %0|%0, %2}"
8683 [(set_attr "type" "alu")
8684 (set_attr "mode" "DI")])
8686 (define_expand "xorsi3"
8687 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8688 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8689 (match_operand:SI 2 "general_operand" "")))
8690 (clobber (reg:CC 17))]
8692 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8694 (define_insn "*xorsi_1"
8695 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8696 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8697 (match_operand:SI 2 "general_operand" "ri,rm")))
8698 (clobber (reg:CC 17))]
8699 "ix86_binary_operator_ok (XOR, SImode, operands)"
8700 "xor{l}\t{%2, %0|%0, %2}"
8701 [(set_attr "type" "alu")
8702 (set_attr "mode" "SI")])
8704 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8705 ;; Add speccase for immediates
8706 (define_insn "*xorsi_1_zext"
8707 [(set (match_operand:DI 0 "register_operand" "=r")
8709 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8710 (match_operand:SI 2 "general_operand" "rim"))))
8711 (clobber (reg:CC 17))]
8712 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8713 "xor{l}\t{%2, %k0|%k0, %2}"
8714 [(set_attr "type" "alu")
8715 (set_attr "mode" "SI")])
8717 (define_insn "*xorsi_1_zext_imm"
8718 [(set (match_operand:DI 0 "register_operand" "=r")
8719 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8720 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8721 (clobber (reg:CC 17))]
8722 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8723 "xor{l}\t{%2, %k0|%k0, %2}"
8724 [(set_attr "type" "alu")
8725 (set_attr "mode" "SI")])
8727 (define_insn "*xorsi_2"
8729 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8730 (match_operand:SI 2 "general_operand" "rim,ri"))
8732 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8733 (xor:SI (match_dup 1) (match_dup 2)))]
8734 "ix86_match_ccmode (insn, CCNOmode)
8735 && ix86_binary_operator_ok (XOR, SImode, operands)"
8736 "xor{l}\t{%2, %0|%0, %2}"
8737 [(set_attr "type" "alu")
8738 (set_attr "mode" "SI")])
8740 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8741 ;; ??? Special case for immediate operand is missing - it is tricky.
8742 (define_insn "*xorsi_2_zext"
8744 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8745 (match_operand:SI 2 "general_operand" "rim"))
8747 (set (match_operand:DI 0 "register_operand" "=r")
8748 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8749 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8750 && ix86_binary_operator_ok (XOR, SImode, operands)"
8751 "xor{l}\t{%2, %k0|%k0, %2}"
8752 [(set_attr "type" "alu")
8753 (set_attr "mode" "SI")])
8755 (define_insn "*xorsi_2_zext_imm"
8757 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8758 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8760 (set (match_operand:DI 0 "register_operand" "=r")
8761 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8762 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8763 && ix86_binary_operator_ok (XOR, SImode, operands)"
8764 "xor{l}\t{%2, %k0|%k0, %2}"
8765 [(set_attr "type" "alu")
8766 (set_attr "mode" "SI")])
8768 (define_insn "*xorsi_3"
8770 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8771 (match_operand:SI 2 "general_operand" "rim"))
8773 (clobber (match_scratch:SI 0 "=r"))]
8774 "ix86_match_ccmode (insn, CCNOmode)
8775 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8776 "xor{l}\t{%2, %0|%0, %2}"
8777 [(set_attr "type" "alu")
8778 (set_attr "mode" "SI")])
8780 (define_expand "xorhi3"
8781 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8782 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
8783 (match_operand:HI 2 "general_operand" "")))
8784 (clobber (reg:CC 17))]
8785 "TARGET_HIMODE_MATH"
8786 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
8788 (define_insn "*xorhi_1"
8789 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8790 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8791 (match_operand:HI 2 "general_operand" "rmi,ri")))
8792 (clobber (reg:CC 17))]
8793 "ix86_binary_operator_ok (XOR, HImode, operands)"
8794 "xor{w}\t{%2, %0|%0, %2}"
8795 [(set_attr "type" "alu")
8796 (set_attr "mode" "HI")])
8798 (define_insn "*xorhi_2"
8800 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8801 (match_operand:HI 2 "general_operand" "rim,ri"))
8803 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8804 (xor:HI (match_dup 1) (match_dup 2)))]
8805 "ix86_match_ccmode (insn, CCNOmode)
8806 && ix86_binary_operator_ok (XOR, HImode, operands)"
8807 "xor{w}\t{%2, %0|%0, %2}"
8808 [(set_attr "type" "alu")
8809 (set_attr "mode" "HI")])
8811 (define_insn "*xorhi_3"
8813 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8814 (match_operand:HI 2 "general_operand" "rim"))
8816 (clobber (match_scratch:HI 0 "=r"))]
8817 "ix86_match_ccmode (insn, CCNOmode)
8818 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8819 "xor{w}\t{%2, %0|%0, %2}"
8820 [(set_attr "type" "alu")
8821 (set_attr "mode" "HI")])
8823 (define_expand "xorqi3"
8824 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8825 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
8826 (match_operand:QI 2 "general_operand" "")))
8827 (clobber (reg:CC 17))]
8828 "TARGET_QIMODE_MATH"
8829 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
8831 ;; %%% Potential partial reg stall on alternative 2. What to do?
8832 (define_insn "*xorqi_1"
8833 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8834 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8835 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8836 (clobber (reg:CC 17))]
8837 "ix86_binary_operator_ok (XOR, QImode, operands)"
8839 xor{b}\t{%2, %0|%0, %2}
8840 xor{b}\t{%2, %0|%0, %2}
8841 xor{l}\t{%k2, %k0|%k0, %k2}"
8842 [(set_attr "type" "alu")
8843 (set_attr "mode" "QI,QI,SI")])
8845 (define_insn "*xorqi_1_slp"
8846 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8847 (xor:QI (match_dup 0)
8848 (match_operand:QI 1 "general_operand" "qi,qmi")))
8849 (clobber (reg:CC 17))]
8850 "! TARGET_PARTIAL_REG_STALL || optimize_size"
8851 "xor{b}\t{%1, %0|%0, %1}"
8852 [(set_attr "type" "alu1")
8853 (set_attr "mode" "QI")])
8855 (define_insn "xorqi_ext_0"
8856 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8861 (match_operand 1 "ext_register_operand" "0")
8864 (match_operand 2 "const_int_operand" "n")))
8865 (clobber (reg:CC 17))]
8866 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8867 "xor{b}\t{%2, %h0|%h0, %2}"
8868 [(set_attr "type" "alu")
8869 (set_attr "length_immediate" "1")
8870 (set_attr "mode" "QI")])
8872 (define_insn "*xorqi_ext_1"
8873 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8878 (match_operand 1 "ext_register_operand" "0")
8882 (match_operand:QI 2 "general_operand" "Qm"))))
8883 (clobber (reg:CC 17))]
8885 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8886 "xor{b}\t{%2, %h0|%h0, %2}"
8887 [(set_attr "type" "alu")
8888 (set_attr "length_immediate" "0")
8889 (set_attr "mode" "QI")])
8891 (define_insn "*xorqi_ext_1_rex64"
8892 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8897 (match_operand 1 "ext_register_operand" "0")
8901 (match_operand 2 "ext_register_operand" "Q"))))
8902 (clobber (reg:CC 17))]
8904 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8905 "xor{b}\t{%2, %h0|%h0, %2}"
8906 [(set_attr "type" "alu")
8907 (set_attr "length_immediate" "0")
8908 (set_attr "mode" "QI")])
8910 (define_insn "*xorqi_ext_2"
8911 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8915 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8918 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8921 (clobber (reg:CC 17))]
8922 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8923 "xor{b}\t{%h2, %h0|%h0, %h2}"
8924 [(set_attr "type" "alu")
8925 (set_attr "length_immediate" "0")
8926 (set_attr "mode" "QI")])
8928 (define_insn "*xorqi_cc_1"
8931 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8932 (match_operand:QI 2 "general_operand" "qim,qi"))
8934 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8935 (xor:QI (match_dup 1) (match_dup 2)))]
8936 "ix86_match_ccmode (insn, CCNOmode)
8937 && ix86_binary_operator_ok (XOR, QImode, operands)"
8938 "xor{b}\t{%2, %0|%0, %2}"
8939 [(set_attr "type" "alu")
8940 (set_attr "mode" "QI")])
8942 (define_insn "*xorqi_2_slp"
8944 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8945 (match_operand:QI 1 "general_operand" "qim,qi"))
8947 (set (strict_low_part (match_dup 0))
8948 (xor:QI (match_dup 0) (match_dup 1)))]
8949 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8950 && ix86_match_ccmode (insn, CCNOmode)"
8951 "xor{b}\t{%1, %0|%0, %1}"
8952 [(set_attr "type" "alu1")
8953 (set_attr "mode" "QI")])
8955 (define_insn "*xorqi_cc_2"
8958 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8959 (match_operand:QI 2 "general_operand" "qim"))
8961 (clobber (match_scratch:QI 0 "=q"))]
8962 "ix86_match_ccmode (insn, CCNOmode)
8963 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8964 "xor{b}\t{%2, %0|%0, %2}"
8965 [(set_attr "type" "alu")
8966 (set_attr "mode" "QI")])
8968 (define_insn "*xorqi_cc_ext_1"
8973 (match_operand 1 "ext_register_operand" "0")
8976 (match_operand:QI 2 "general_operand" "qmn"))
8978 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
8982 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
8984 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8985 "xor{b}\t{%2, %h0|%h0, %2}"
8986 [(set_attr "type" "alu")
8987 (set_attr "mode" "QI")])
8989 (define_insn "*xorqi_cc_ext_1_rex64"
8994 (match_operand 1 "ext_register_operand" "0")
8997 (match_operand:QI 2 "nonmemory_operand" "Qn"))
8999 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9003 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9005 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9006 "xor{b}\t{%2, %h0|%h0, %2}"
9007 [(set_attr "type" "alu")
9008 (set_attr "mode" "QI")])
9010 (define_expand "xorqi_cc_ext_1"
9016 (match_operand 1 "ext_register_operand" "")
9019 (match_operand:QI 2 "general_operand" ""))
9021 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9025 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9031 [(set (match_operand 0 "register_operand" "")
9032 (xor (match_operand 1 "register_operand" "")
9033 (match_operand 2 "const_int_operand" "")))
9034 (clobber (reg:CC 17))]
9036 && QI_REG_P (operands[0])
9037 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9038 && !(INTVAL (operands[2]) & ~(255 << 8))
9039 && GET_MODE (operands[0]) != QImode"
9040 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9041 (xor:SI (zero_extract:SI (match_dup 1)
9042 (const_int 8) (const_int 8))
9044 (clobber (reg:CC 17))])]
9045 "operands[0] = gen_lowpart (SImode, operands[0]);
9046 operands[1] = gen_lowpart (SImode, operands[1]);
9047 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9049 ;; Since XOR can be encoded with sign extended immediate, this is only
9050 ;; profitable when 7th bit is set.
9052 [(set (match_operand 0 "register_operand" "")
9053 (xor (match_operand 1 "general_operand" "")
9054 (match_operand 2 "const_int_operand" "")))
9055 (clobber (reg:CC 17))]
9057 && ANY_QI_REG_P (operands[0])
9058 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9059 && !(INTVAL (operands[2]) & ~255)
9060 && (INTVAL (operands[2]) & 128)
9061 && GET_MODE (operands[0]) != QImode"
9062 [(parallel [(set (strict_low_part (match_dup 0))
9063 (xor:QI (match_dup 1)
9065 (clobber (reg:CC 17))])]
9066 "operands[0] = gen_lowpart (QImode, operands[0]);
9067 operands[1] = gen_lowpart (QImode, operands[1]);
9068 operands[2] = gen_lowpart (QImode, operands[2]);")
9070 ;; Negation instructions
9072 (define_expand "negdi2"
9073 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9074 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9075 (clobber (reg:CC 17))])]
9077 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9079 (define_insn "*negdi2_1"
9080 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9081 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9082 (clobber (reg:CC 17))]
9084 && ix86_unary_operator_ok (NEG, DImode, operands)"
9088 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9089 (neg:DI (match_operand:DI 1 "general_operand" "")))
9090 (clobber (reg:CC 17))]
9091 "!TARGET_64BIT && reload_completed"
9094 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9095 (set (match_dup 0) (neg:SI (match_dup 2)))])
9098 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9101 (clobber (reg:CC 17))])
9104 (neg:SI (match_dup 1)))
9105 (clobber (reg:CC 17))])]
9106 "split_di (operands+1, 1, operands+2, operands+3);
9107 split_di (operands+0, 1, operands+0, operands+1);")
9109 (define_insn "*negdi2_1_rex64"
9110 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9111 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9112 (clobber (reg:CC 17))]
9113 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9115 [(set_attr "type" "negnot")
9116 (set_attr "mode" "DI")])
9118 ;; The problem with neg is that it does not perform (compare x 0),
9119 ;; it really performs (compare 0 x), which leaves us with the zero
9120 ;; flag being the only useful item.
9122 (define_insn "*negdi2_cmpz_rex64"
9124 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9126 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9127 (neg:DI (match_dup 1)))]
9128 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9130 [(set_attr "type" "negnot")
9131 (set_attr "mode" "DI")])
9134 (define_expand "negsi2"
9135 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9136 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9137 (clobber (reg:CC 17))])]
9139 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9141 (define_insn "*negsi2_1"
9142 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9143 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9144 (clobber (reg:CC 17))]
9145 "ix86_unary_operator_ok (NEG, SImode, operands)"
9147 [(set_attr "type" "negnot")
9148 (set_attr "mode" "SI")])
9150 ;; Combine is quite creative about this pattern.
9151 (define_insn "*negsi2_1_zext"
9152 [(set (match_operand:DI 0 "register_operand" "=r")
9153 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9156 (clobber (reg:CC 17))]
9157 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9159 [(set_attr "type" "negnot")
9160 (set_attr "mode" "SI")])
9162 ;; The problem with neg is that it does not perform (compare x 0),
9163 ;; it really performs (compare 0 x), which leaves us with the zero
9164 ;; flag being the only useful item.
9166 (define_insn "*negsi2_cmpz"
9168 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9170 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9171 (neg:SI (match_dup 1)))]
9172 "ix86_unary_operator_ok (NEG, SImode, operands)"
9174 [(set_attr "type" "negnot")
9175 (set_attr "mode" "SI")])
9177 (define_insn "*negsi2_cmpz_zext"
9179 (compare:CCZ (lshiftrt:DI
9181 (match_operand:DI 1 "register_operand" "0")
9185 (set (match_operand:DI 0 "register_operand" "=r")
9186 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9189 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9191 [(set_attr "type" "negnot")
9192 (set_attr "mode" "SI")])
9194 (define_expand "neghi2"
9195 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9196 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9197 (clobber (reg:CC 17))])]
9198 "TARGET_HIMODE_MATH"
9199 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9201 (define_insn "*neghi2_1"
9202 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9203 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9204 (clobber (reg:CC 17))]
9205 "ix86_unary_operator_ok (NEG, HImode, operands)"
9207 [(set_attr "type" "negnot")
9208 (set_attr "mode" "HI")])
9210 (define_insn "*neghi2_cmpz"
9212 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9214 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9215 (neg:HI (match_dup 1)))]
9216 "ix86_unary_operator_ok (NEG, HImode, operands)"
9218 [(set_attr "type" "negnot")
9219 (set_attr "mode" "HI")])
9221 (define_expand "negqi2"
9222 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9223 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9224 (clobber (reg:CC 17))])]
9225 "TARGET_QIMODE_MATH"
9226 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9228 (define_insn "*negqi2_1"
9229 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9230 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9231 (clobber (reg:CC 17))]
9232 "ix86_unary_operator_ok (NEG, QImode, operands)"
9234 [(set_attr "type" "negnot")
9235 (set_attr "mode" "QI")])
9237 (define_insn "*negqi2_cmpz"
9239 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9241 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9242 (neg:QI (match_dup 1)))]
9243 "ix86_unary_operator_ok (NEG, QImode, operands)"
9245 [(set_attr "type" "negnot")
9246 (set_attr "mode" "QI")])
9248 ;; Changing of sign for FP values is doable using integer unit too.
9250 (define_expand "negsf2"
9251 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9252 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9253 (clobber (reg:CC 17))])]
9257 /* In case operand is in memory, we will not use SSE. */
9258 if (memory_operand (operands[0], VOIDmode)
9259 && rtx_equal_p (operands[0], operands[1]))
9260 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9263 /* Using SSE is tricky, since we need bitwise negation of -0
9265 rtx reg = gen_reg_rtx (SFmode);
9266 rtx dest = operands[0];
9268 operands[1] = force_reg (SFmode, operands[1]);
9269 operands[0] = force_reg (SFmode, operands[0]);
9270 emit_move_insn (reg,
9271 gen_lowpart (SFmode,
9272 gen_int_mode (0x80000000, SImode)));
9273 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9274 if (dest != operands[0])
9275 emit_move_insn (dest, operands[0]);
9279 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9281 (define_insn "negsf2_memory"
9282 [(set (match_operand:SF 0 "memory_operand" "=m")
9283 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9284 (clobber (reg:CC 17))]
9285 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9288 (define_insn "negsf2_ifs"
9289 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9290 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9291 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x"))
9292 (clobber (reg:CC 17))]
9294 && (reload_in_progress || reload_completed
9295 || (register_operand (operands[0], VOIDmode)
9296 && register_operand (operands[1], VOIDmode)))"
9300 [(set (match_operand:SF 0 "memory_operand" "")
9301 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9302 (use (match_operand:SF 2 "" ""))
9303 (clobber (reg:CC 17))]
9305 [(parallel [(set (match_dup 0)
9306 (neg:SF (match_dup 1)))
9307 (clobber (reg:CC 17))])])
9310 [(set (match_operand:SF 0 "register_operand" "")
9311 (neg:SF (match_operand:SF 1 "register_operand" "")))
9312 (use (match_operand:SF 2 "" ""))
9313 (clobber (reg:CC 17))]
9314 "reload_completed && !SSE_REG_P (operands[0])"
9315 [(parallel [(set (match_dup 0)
9316 (neg:SF (match_dup 1)))
9317 (clobber (reg:CC 17))])])
9320 [(set (match_operand:SF 0 "register_operand" "")
9321 (neg:SF (match_operand:SF 1 "register_operand" "")))
9322 (use (match_operand:SF 2 "register_operand" ""))
9323 (clobber (reg:CC 17))]
9324 "reload_completed && SSE_REG_P (operands[0])"
9325 [(set (subreg:TI (match_dup 0) 0)
9326 (xor:TI (subreg:TI (match_dup 1) 0)
9327 (subreg:TI (match_dup 2) 0)))]
9329 if (operands_match_p (operands[0], operands[2]))
9333 operands[1] = operands[2];
9339 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9340 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9342 (define_insn "*negsf2_if"
9343 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9344 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9345 (clobber (reg:CC 17))]
9346 "TARGET_80387 && !TARGET_SSE
9347 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9351 [(set (match_operand:SF 0 "register_operand" "")
9352 (neg:SF (match_operand:SF 1 "register_operand" "")))
9353 (clobber (reg:CC 17))]
9354 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9356 (neg:SF (match_dup 1)))]
9360 [(set (match_operand:SF 0 "register_operand" "")
9361 (neg:SF (match_operand:SF 1 "register_operand" "")))
9362 (clobber (reg:CC 17))]
9363 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9364 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9365 (clobber (reg:CC 17))])]
9366 "operands[1] = gen_int_mode (0x80000000, SImode);
9367 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9370 [(set (match_operand 0 "memory_operand" "")
9371 (neg (match_operand 1 "memory_operand" "")))
9372 (clobber (reg:CC 17))]
9373 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9374 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9375 (clobber (reg:CC 17))])]
9377 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9379 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9382 operands[0] = adjust_address (operands[0], QImode, size - 1);
9383 operands[1] = gen_int_mode (0x80, QImode);
9386 (define_expand "negdf2"
9387 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9388 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9389 (clobber (reg:CC 17))])]
9393 /* In case operand is in memory, we will not use SSE. */
9394 if (memory_operand (operands[0], VOIDmode)
9395 && rtx_equal_p (operands[0], operands[1]))
9396 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9399 /* Using SSE is tricky, since we need bitwise negation of -0
9401 rtx reg = gen_reg_rtx (DFmode);
9402 #if HOST_BITS_PER_WIDE_INT >= 64
9403 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9405 rtx imm = immed_double_const (0, 0x80000000, DImode);
9407 rtx dest = operands[0];
9409 operands[1] = force_reg (DFmode, operands[1]);
9410 operands[0] = force_reg (DFmode, operands[0]);
9411 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9412 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9413 if (dest != operands[0])
9414 emit_move_insn (dest, operands[0]);
9418 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9420 (define_insn "negdf2_memory"
9421 [(set (match_operand:DF 0 "memory_operand" "=m")
9422 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9423 (clobber (reg:CC 17))]
9424 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9427 (define_insn "negdf2_ifs"
9428 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9429 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9430 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
9431 (clobber (reg:CC 17))]
9432 "!TARGET_64BIT && TARGET_SSE2
9433 && (reload_in_progress || reload_completed
9434 || (register_operand (operands[0], VOIDmode)
9435 && register_operand (operands[1], VOIDmode)))"
9438 (define_insn "*negdf2_ifs_rex64"
9439 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9440 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9441 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9442 (clobber (reg:CC 17))]
9443 "TARGET_64BIT && TARGET_SSE2
9444 && (reload_in_progress || reload_completed
9445 || (register_operand (operands[0], VOIDmode)
9446 && register_operand (operands[1], VOIDmode)))"
9450 [(set (match_operand:DF 0 "memory_operand" "")
9451 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9452 (use (match_operand:DF 2 "" ""))
9453 (clobber (reg:CC 17))]
9455 [(parallel [(set (match_dup 0)
9456 (neg:DF (match_dup 1)))
9457 (clobber (reg:CC 17))])])
9460 [(set (match_operand:DF 0 "register_operand" "")
9461 (neg:DF (match_operand:DF 1 "register_operand" "")))
9462 (use (match_operand:DF 2 "" ""))
9463 (clobber (reg:CC 17))]
9464 "reload_completed && !SSE_REG_P (operands[0])
9465 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9466 [(parallel [(set (match_dup 0)
9467 (neg:DF (match_dup 1)))
9468 (clobber (reg:CC 17))])])
9471 [(set (match_operand:DF 0 "register_operand" "")
9472 (neg:DF (match_operand:DF 1 "register_operand" "")))
9473 (use (match_operand:DF 2 "" ""))
9474 (clobber (reg:CC 17))]
9475 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9476 [(parallel [(set (match_dup 0)
9477 (xor:DI (match_dup 1) (match_dup 2)))
9478 (clobber (reg:CC 17))])]
9479 "operands[0] = gen_lowpart (DImode, operands[0]);
9480 operands[1] = gen_lowpart (DImode, operands[1]);
9481 operands[2] = gen_lowpart (DImode, operands[2]);")
9484 [(set (match_operand:DF 0 "register_operand" "")
9485 (neg:DF (match_operand:DF 1 "register_operand" "")))
9486 (use (match_operand:DF 2 "register_operand" ""))
9487 (clobber (reg:CC 17))]
9488 "reload_completed && SSE_REG_P (operands[0])"
9489 [(set (subreg:TI (match_dup 0) 0)
9490 (xor:TI (subreg:TI (match_dup 1) 0)
9491 (subreg:TI (match_dup 2) 0)))]
9493 if (operands_match_p (operands[0], operands[2]))
9497 operands[1] = operands[2];
9502 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9503 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9505 (define_insn "*negdf2_if"
9506 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9507 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9508 (clobber (reg:CC 17))]
9509 "!TARGET_64BIT && TARGET_80387
9510 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9513 ;; FIXME: We should to allow integer registers here. Problem is that
9514 ;; we need another scratch register to get constant from.
9515 ;; Forcing constant to mem if no register available in peep2 should be
9516 ;; safe even for PIC mode, because of RIP relative addressing.
9517 (define_insn "*negdf2_if_rex64"
9518 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9519 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9520 (clobber (reg:CC 17))]
9521 "TARGET_64BIT && TARGET_80387
9522 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9526 [(set (match_operand:DF 0 "register_operand" "")
9527 (neg:DF (match_operand:DF 1 "register_operand" "")))
9528 (clobber (reg:CC 17))]
9529 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9531 (neg:DF (match_dup 1)))]
9535 [(set (match_operand:DF 0 "register_operand" "")
9536 (neg:DF (match_operand:DF 1 "register_operand" "")))
9537 (clobber (reg:CC 17))]
9538 "!TARGET_64BIT && TARGET_80387 && reload_completed
9539 && !FP_REGNO_P (REGNO (operands[0]))"
9540 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9541 (clobber (reg:CC 17))])]
9542 "operands[4] = gen_int_mode (0x80000000, SImode);
9543 split_di (operands+0, 1, operands+2, operands+3);")
9545 (define_expand "negxf2"
9546 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9547 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9548 (clobber (reg:CC 17))])]
9549 "!TARGET_64BIT && TARGET_80387"
9550 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9552 (define_expand "negtf2"
9553 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9554 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9555 (clobber (reg:CC 17))])]
9557 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9559 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9560 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9562 (define_insn "*negxf2_if"
9563 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9564 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9565 (clobber (reg:CC 17))]
9566 "!TARGET_64BIT && TARGET_80387
9567 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9571 [(set (match_operand:XF 0 "register_operand" "")
9572 (neg:XF (match_operand:XF 1 "register_operand" "")))
9573 (clobber (reg:CC 17))]
9574 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9576 (neg:XF (match_dup 1)))]
9580 [(set (match_operand:XF 0 "register_operand" "")
9581 (neg:XF (match_operand:XF 1 "register_operand" "")))
9582 (clobber (reg:CC 17))]
9583 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9584 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9585 (clobber (reg:CC 17))])]
9586 "operands[1] = GEN_INT (0x8000);
9587 operands[0] = gen_rtx_REG (SImode,
9588 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9590 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9591 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9593 (define_insn "*negtf2_if"
9594 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9595 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9596 (clobber (reg:CC 17))]
9597 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9601 [(set (match_operand:TF 0 "register_operand" "")
9602 (neg:TF (match_operand:TF 1 "register_operand" "")))
9603 (clobber (reg:CC 17))]
9604 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9606 (neg:TF (match_dup 1)))]
9610 [(set (match_operand:TF 0 "register_operand" "")
9611 (neg:TF (match_operand:TF 1 "register_operand" "")))
9612 (clobber (reg:CC 17))]
9613 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9614 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9615 (clobber (reg:CC 17))])]
9616 "operands[1] = GEN_INT (0x8000);
9617 operands[0] = gen_rtx_REG (SImode,
9618 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9620 ;; Conditionize these after reload. If they matches before reload, we
9621 ;; lose the clobber and ability to use integer instructions.
9623 (define_insn "*negsf2_1"
9624 [(set (match_operand:SF 0 "register_operand" "=f")
9625 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9626 "TARGET_80387 && reload_completed"
9628 [(set_attr "type" "fsgn")
9629 (set_attr "mode" "SF")
9630 (set_attr "ppro_uops" "few")])
9632 (define_insn "*negdf2_1"
9633 [(set (match_operand:DF 0 "register_operand" "=f")
9634 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9635 "TARGET_80387 && reload_completed"
9637 [(set_attr "type" "fsgn")
9638 (set_attr "mode" "DF")
9639 (set_attr "ppro_uops" "few")])
9641 (define_insn "*negextendsfdf2"
9642 [(set (match_operand:DF 0 "register_operand" "=f")
9643 (neg:DF (float_extend:DF
9644 (match_operand:SF 1 "register_operand" "0"))))]
9647 [(set_attr "type" "fsgn")
9648 (set_attr "mode" "DF")
9649 (set_attr "ppro_uops" "few")])
9651 (define_insn "*negxf2_1"
9652 [(set (match_operand:XF 0 "register_operand" "=f")
9653 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9654 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9656 [(set_attr "type" "fsgn")
9657 (set_attr "mode" "XF")
9658 (set_attr "ppro_uops" "few")])
9660 (define_insn "*negextenddfxf2"
9661 [(set (match_operand:XF 0 "register_operand" "=f")
9662 (neg:XF (float_extend:XF
9663 (match_operand:DF 1 "register_operand" "0"))))]
9664 "!TARGET_64BIT && TARGET_80387"
9666 [(set_attr "type" "fsgn")
9667 (set_attr "mode" "XF")
9668 (set_attr "ppro_uops" "few")])
9670 (define_insn "*negextendsfxf2"
9671 [(set (match_operand:XF 0 "register_operand" "=f")
9672 (neg:XF (float_extend:XF
9673 (match_operand:SF 1 "register_operand" "0"))))]
9674 "!TARGET_64BIT && TARGET_80387"
9676 [(set_attr "type" "fsgn")
9677 (set_attr "mode" "XF")
9678 (set_attr "ppro_uops" "few")])
9680 (define_insn "*negtf2_1"
9681 [(set (match_operand:TF 0 "register_operand" "=f")
9682 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9683 "TARGET_80387 && reload_completed"
9685 [(set_attr "type" "fsgn")
9686 (set_attr "mode" "XF")
9687 (set_attr "ppro_uops" "few")])
9689 (define_insn "*negextenddftf2"
9690 [(set (match_operand:TF 0 "register_operand" "=f")
9691 (neg:TF (float_extend:TF
9692 (match_operand:DF 1 "register_operand" "0"))))]
9695 [(set_attr "type" "fsgn")
9696 (set_attr "mode" "XF")
9697 (set_attr "ppro_uops" "few")])
9699 (define_insn "*negextendsftf2"
9700 [(set (match_operand:TF 0 "register_operand" "=f")
9701 (neg:TF (float_extend:TF
9702 (match_operand:SF 1 "register_operand" "0"))))]
9705 [(set_attr "type" "fsgn")
9706 (set_attr "mode" "XF")
9707 (set_attr "ppro_uops" "few")])
9709 ;; Absolute value instructions
9711 (define_expand "abssf2"
9712 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9713 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9714 (clobber (reg:CC 17))])]
9718 /* In case operand is in memory, we will not use SSE. */
9719 if (memory_operand (operands[0], VOIDmode)
9720 && rtx_equal_p (operands[0], operands[1]))
9721 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9724 /* Using SSE is tricky, since we need bitwise negation of -0
9726 rtx reg = gen_reg_rtx (SFmode);
9727 rtx dest = operands[0];
9729 operands[1] = force_reg (SFmode, operands[1]);
9730 operands[0] = force_reg (SFmode, operands[0]);
9731 emit_move_insn (reg,
9732 gen_lowpart (SFmode,
9733 gen_int_mode (0x80000000, SImode)));
9734 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9735 if (dest != operands[0])
9736 emit_move_insn (dest, operands[0]);
9740 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9742 (define_insn "abssf2_memory"
9743 [(set (match_operand:SF 0 "memory_operand" "=m")
9744 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9745 (clobber (reg:CC 17))]
9746 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9749 (define_insn "abssf2_ifs"
9750 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf")
9751 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9752 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x"))
9753 (clobber (reg:CC 17))]
9755 && (reload_in_progress || reload_completed
9756 || (register_operand (operands[0], VOIDmode)
9757 && register_operand (operands[1], VOIDmode)))"
9761 [(set (match_operand:SF 0 "memory_operand" "")
9762 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9763 (use (match_operand:SF 2 "" ""))
9764 (clobber (reg:CC 17))]
9766 [(parallel [(set (match_dup 0)
9767 (abs:SF (match_dup 1)))
9768 (clobber (reg:CC 17))])])
9771 [(set (match_operand:SF 0 "register_operand" "")
9772 (abs:SF (match_operand:SF 1 "register_operand" "")))
9773 (use (match_operand:SF 2 "" ""))
9774 (clobber (reg:CC 17))]
9775 "reload_completed && !SSE_REG_P (operands[0])"
9776 [(parallel [(set (match_dup 0)
9777 (abs:SF (match_dup 1)))
9778 (clobber (reg:CC 17))])])
9781 [(set (match_operand:SF 0 "register_operand" "")
9782 (abs:SF (match_operand:SF 1 "register_operand" "")))
9783 (use (match_operand:SF 2 "register_operand" ""))
9784 (clobber (reg:CC 17))]
9785 "reload_completed && SSE_REG_P (operands[0])"
9786 [(set (subreg:TI (match_dup 0) 0)
9787 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9788 (subreg:TI (match_dup 1) 0)))])
9790 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9791 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9793 (define_insn "*abssf2_if"
9794 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9795 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9796 (clobber (reg:CC 17))]
9797 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9801 [(set (match_operand:SF 0 "register_operand" "")
9802 (abs:SF (match_operand:SF 1 "register_operand" "")))
9803 (clobber (reg:CC 17))]
9804 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9806 (abs:SF (match_dup 1)))]
9810 [(set (match_operand:SF 0 "register_operand" "")
9811 (abs:SF (match_operand:SF 1 "register_operand" "")))
9812 (clobber (reg:CC 17))]
9813 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9814 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9815 (clobber (reg:CC 17))])]
9816 "operands[1] = gen_int_mode (~0x80000000, SImode);
9817 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9820 [(set (match_operand 0 "memory_operand" "")
9821 (abs (match_operand 1 "memory_operand" "")))
9822 (clobber (reg:CC 17))]
9823 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9824 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9825 (clobber (reg:CC 17))])]
9827 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9829 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9832 operands[0] = adjust_address (operands[0], QImode, size - 1);
9833 operands[1] = gen_int_mode (~0x80, QImode);
9836 (define_expand "absdf2"
9837 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9838 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9839 (clobber (reg:CC 17))])]
9843 /* In case operand is in memory, we will not use SSE. */
9844 if (memory_operand (operands[0], VOIDmode)
9845 && rtx_equal_p (operands[0], operands[1]))
9846 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9849 /* Using SSE is tricky, since we need bitwise negation of -0
9851 rtx reg = gen_reg_rtx (DFmode);
9852 #if HOST_BITS_PER_WIDE_INT >= 64
9853 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9855 rtx imm = immed_double_const (0, 0x80000000, DImode);
9857 rtx dest = operands[0];
9859 operands[1] = force_reg (DFmode, operands[1]);
9860 operands[0] = force_reg (DFmode, operands[0]);
9861 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9862 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9863 if (dest != operands[0])
9864 emit_move_insn (dest, operands[0]);
9868 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9870 (define_insn "absdf2_memory"
9871 [(set (match_operand:DF 0 "memory_operand" "=m")
9872 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9873 (clobber (reg:CC 17))]
9874 "ix86_unary_operator_ok (ABS, DFmode, operands)"
9877 (define_insn "absdf2_ifs"
9878 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf")
9879 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
9880 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
9881 (clobber (reg:CC 17))]
9882 "!TARGET_64BIT && TARGET_SSE2
9883 && (reload_in_progress || reload_completed
9884 || (register_operand (operands[0], VOIDmode)
9885 && register_operand (operands[1], VOIDmode)))"
9888 (define_insn "*absdf2_ifs_rex64"
9889 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr")
9890 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
9891 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
9892 (clobber (reg:CC 17))]
9893 "TARGET_64BIT && TARGET_SSE2
9894 && (reload_in_progress || reload_completed
9895 || (register_operand (operands[0], VOIDmode)
9896 && register_operand (operands[1], VOIDmode)))"
9900 [(set (match_operand:DF 0 "memory_operand" "")
9901 (abs:DF (match_operand:DF 1 "memory_operand" "")))
9902 (use (match_operand:DF 2 "" ""))
9903 (clobber (reg:CC 17))]
9905 [(parallel [(set (match_dup 0)
9906 (abs:DF (match_dup 1)))
9907 (clobber (reg:CC 17))])])
9910 [(set (match_operand:DF 0 "register_operand" "")
9911 (abs:DF (match_operand:DF 1 "register_operand" "")))
9912 (use (match_operand:DF 2 "" ""))
9913 (clobber (reg:CC 17))]
9914 "reload_completed && !SSE_REG_P (operands[0])"
9915 [(parallel [(set (match_dup 0)
9916 (abs:DF (match_dup 1)))
9917 (clobber (reg:CC 17))])])
9920 [(set (match_operand:DF 0 "register_operand" "")
9921 (abs:DF (match_operand:DF 1 "register_operand" "")))
9922 (use (match_operand:DF 2 "register_operand" ""))
9923 (clobber (reg:CC 17))]
9924 "reload_completed && SSE_REG_P (operands[0])"
9925 [(set (subreg:TI (match_dup 0) 0)
9926 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9927 (subreg:TI (match_dup 1) 0)))])
9930 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9931 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9933 (define_insn "*absdf2_if"
9934 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9935 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9936 (clobber (reg:CC 17))]
9937 "!TARGET_64BIT && TARGET_80387
9938 && ix86_unary_operator_ok (ABS, DFmode, operands)"
9941 ;; FIXME: We should to allow integer registers here. Problem is that
9942 ;; we need another scratch register to get constant from.
9943 ;; Forcing constant to mem if no register available in peep2 should be
9944 ;; safe even for PIC mode, because of RIP relative addressing.
9945 (define_insn "*absdf2_if_rex64"
9946 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9947 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9948 (clobber (reg:CC 17))]
9949 "TARGET_64BIT && TARGET_80387
9950 && ix86_unary_operator_ok (ABS, DFmode, operands)"
9954 [(set (match_operand:DF 0 "register_operand" "")
9955 (abs:DF (match_operand:DF 1 "register_operand" "")))
9956 (clobber (reg:CC 17))]
9957 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9959 (abs:DF (match_dup 1)))]
9963 [(set (match_operand:DF 0 "register_operand" "")
9964 (abs:DF (match_operand:DF 1 "register_operand" "")))
9965 (clobber (reg:CC 17))]
9966 "!TARGET_64BIT && TARGET_80387 && reload_completed &&
9967 !FP_REGNO_P (REGNO (operands[0]))"
9968 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
9969 (clobber (reg:CC 17))])]
9970 "operands[4] = gen_int_mode (~0x80000000, SImode);
9971 split_di (operands+0, 1, operands+2, operands+3);")
9973 (define_expand "absxf2"
9974 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9975 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9976 (clobber (reg:CC 17))])]
9977 "!TARGET_64BIT && TARGET_80387"
9978 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
9980 (define_expand "abstf2"
9981 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9982 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9983 (clobber (reg:CC 17))])]
9985 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
9987 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9988 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9990 (define_insn "*absxf2_if"
9991 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9992 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9993 (clobber (reg:CC 17))]
9994 "!TARGET_64BIT && TARGET_80387
9995 && ix86_unary_operator_ok (ABS, XFmode, operands)"
9999 [(set (match_operand:XF 0 "register_operand" "")
10000 (abs:XF (match_operand:XF 1 "register_operand" "")))
10001 (clobber (reg:CC 17))]
10002 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10003 [(set (match_dup 0)
10004 (abs:XF (match_dup 1)))]
10008 [(set (match_operand:XF 0 "register_operand" "")
10009 (abs:XF (match_operand:XF 1 "register_operand" "")))
10010 (clobber (reg:CC 17))]
10011 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10012 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10013 (clobber (reg:CC 17))])]
10014 "operands[1] = GEN_INT (~0x8000);
10015 operands[0] = gen_rtx_REG (SImode,
10016 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10018 (define_insn "*abstf2_if"
10019 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10020 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10021 (clobber (reg:CC 17))]
10022 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10026 [(set (match_operand:TF 0 "register_operand" "")
10027 (abs:TF (match_operand:TF 1 "register_operand" "")))
10028 (clobber (reg:CC 17))]
10029 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10030 [(set (match_dup 0)
10031 (abs:TF (match_dup 1)))]
10035 [(set (match_operand:TF 0 "register_operand" "")
10036 (abs:TF (match_operand:TF 1 "register_operand" "")))
10037 (clobber (reg:CC 17))]
10038 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10039 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10040 (clobber (reg:CC 17))])]
10041 "operands[1] = GEN_INT (~0x8000);
10042 operands[0] = gen_rtx_REG (SImode,
10043 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10045 (define_insn "*abssf2_1"
10046 [(set (match_operand:SF 0 "register_operand" "=f")
10047 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10048 "TARGET_80387 && reload_completed"
10050 [(set_attr "type" "fsgn")
10051 (set_attr "mode" "SF")])
10053 (define_insn "*absdf2_1"
10054 [(set (match_operand:DF 0 "register_operand" "=f")
10055 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10056 "TARGET_80387 && reload_completed"
10058 [(set_attr "type" "fsgn")
10059 (set_attr "mode" "DF")])
10061 (define_insn "*absextendsfdf2"
10062 [(set (match_operand:DF 0 "register_operand" "=f")
10063 (abs:DF (float_extend:DF
10064 (match_operand:SF 1 "register_operand" "0"))))]
10067 [(set_attr "type" "fsgn")
10068 (set_attr "mode" "DF")])
10070 (define_insn "*absxf2_1"
10071 [(set (match_operand:XF 0 "register_operand" "=f")
10072 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10073 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10075 [(set_attr "type" "fsgn")
10076 (set_attr "mode" "DF")])
10078 (define_insn "*absextenddfxf2"
10079 [(set (match_operand:XF 0 "register_operand" "=f")
10080 (abs:XF (float_extend:XF
10081 (match_operand:DF 1 "register_operand" "0"))))]
10082 "!TARGET_64BIT && TARGET_80387"
10084 [(set_attr "type" "fsgn")
10085 (set_attr "mode" "XF")])
10087 (define_insn "*absextendsfxf2"
10088 [(set (match_operand:XF 0 "register_operand" "=f")
10089 (abs:XF (float_extend:XF
10090 (match_operand:SF 1 "register_operand" "0"))))]
10091 "!TARGET_64BIT && TARGET_80387"
10093 [(set_attr "type" "fsgn")
10094 (set_attr "mode" "XF")])
10096 (define_insn "*abstf2_1"
10097 [(set (match_operand:TF 0 "register_operand" "=f")
10098 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10099 "TARGET_80387 && reload_completed"
10101 [(set_attr "type" "fsgn")
10102 (set_attr "mode" "DF")])
10104 (define_insn "*absextenddftf2"
10105 [(set (match_operand:TF 0 "register_operand" "=f")
10106 (abs:TF (float_extend:TF
10107 (match_operand:DF 1 "register_operand" "0"))))]
10110 [(set_attr "type" "fsgn")
10111 (set_attr "mode" "XF")])
10113 (define_insn "*absextendsftf2"
10114 [(set (match_operand:TF 0 "register_operand" "=f")
10115 (abs:TF (float_extend:TF
10116 (match_operand:SF 1 "register_operand" "0"))))]
10119 [(set_attr "type" "fsgn")
10120 (set_attr "mode" "XF")])
10122 ;; One complement instructions
10124 (define_expand "one_cmpldi2"
10125 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10126 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10128 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10130 (define_insn "*one_cmpldi2_1_rex64"
10131 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10132 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10133 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10135 [(set_attr "type" "negnot")
10136 (set_attr "mode" "DI")])
10138 (define_insn "*one_cmpldi2_2_rex64"
10140 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10142 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10143 (not:DI (match_dup 1)))]
10144 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10145 && ix86_unary_operator_ok (NOT, DImode, operands)"
10147 [(set_attr "type" "alu1")
10148 (set_attr "mode" "DI")])
10152 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10154 (set (match_operand:DI 0 "nonimmediate_operand" "")
10155 (not:DI (match_dup 1)))]
10156 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10157 [(parallel [(set (reg:CCNO 17)
10158 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10161 (xor:DI (match_dup 1) (const_int -1)))])]
10164 (define_expand "one_cmplsi2"
10165 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10166 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10168 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10170 (define_insn "*one_cmplsi2_1"
10171 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10172 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10173 "ix86_unary_operator_ok (NOT, SImode, operands)"
10175 [(set_attr "type" "negnot")
10176 (set_attr "mode" "SI")])
10178 ;; ??? Currently never generated - xor is used instead.
10179 (define_insn "*one_cmplsi2_1_zext"
10180 [(set (match_operand:DI 0 "register_operand" "=r")
10181 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10182 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10184 [(set_attr "type" "negnot")
10185 (set_attr "mode" "SI")])
10187 (define_insn "*one_cmplsi2_2"
10189 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10191 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10192 (not:SI (match_dup 1)))]
10193 "ix86_match_ccmode (insn, CCNOmode)
10194 && ix86_unary_operator_ok (NOT, SImode, operands)"
10196 [(set_attr "type" "alu1")
10197 (set_attr "mode" "SI")])
10201 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10203 (set (match_operand:SI 0 "nonimmediate_operand" "")
10204 (not:SI (match_dup 1)))]
10205 "ix86_match_ccmode (insn, CCNOmode)"
10206 [(parallel [(set (reg:CCNO 17)
10207 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10210 (xor:SI (match_dup 1) (const_int -1)))])]
10213 ;; ??? Currently never generated - xor is used instead.
10214 (define_insn "*one_cmplsi2_2_zext"
10216 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10218 (set (match_operand:DI 0 "register_operand" "=r")
10219 (zero_extend:DI (not:SI (match_dup 1))))]
10220 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10221 && ix86_unary_operator_ok (NOT, SImode, operands)"
10223 [(set_attr "type" "alu1")
10224 (set_attr "mode" "SI")])
10228 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10230 (set (match_operand:DI 0 "register_operand" "")
10231 (zero_extend:DI (not:SI (match_dup 1))))]
10232 "ix86_match_ccmode (insn, CCNOmode)"
10233 [(parallel [(set (reg:CCNO 17)
10234 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10237 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10240 (define_expand "one_cmplhi2"
10241 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10242 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10243 "TARGET_HIMODE_MATH"
10244 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10246 (define_insn "*one_cmplhi2_1"
10247 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10248 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10249 "ix86_unary_operator_ok (NOT, HImode, operands)"
10251 [(set_attr "type" "negnot")
10252 (set_attr "mode" "HI")])
10254 (define_insn "*one_cmplhi2_2"
10256 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10258 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10259 (not:HI (match_dup 1)))]
10260 "ix86_match_ccmode (insn, CCNOmode)
10261 && ix86_unary_operator_ok (NEG, HImode, operands)"
10263 [(set_attr "type" "alu1")
10264 (set_attr "mode" "HI")])
10268 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10270 (set (match_operand:HI 0 "nonimmediate_operand" "")
10271 (not:HI (match_dup 1)))]
10272 "ix86_match_ccmode (insn, CCNOmode)"
10273 [(parallel [(set (reg:CCNO 17)
10274 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10277 (xor:HI (match_dup 1) (const_int -1)))])]
10280 ;; %%% Potential partial reg stall on alternative 1. What to do?
10281 (define_expand "one_cmplqi2"
10282 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10283 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10284 "TARGET_QIMODE_MATH"
10285 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10287 (define_insn "*one_cmplqi2_1"
10288 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10289 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10290 "ix86_unary_operator_ok (NOT, QImode, operands)"
10294 [(set_attr "type" "negnot")
10295 (set_attr "mode" "QI,SI")])
10297 (define_insn "*one_cmplqi2_2"
10299 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10301 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10302 (not:QI (match_dup 1)))]
10303 "ix86_match_ccmode (insn, CCNOmode)
10304 && ix86_unary_operator_ok (NOT, QImode, operands)"
10306 [(set_attr "type" "alu1")
10307 (set_attr "mode" "QI")])
10311 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10313 (set (match_operand:QI 0 "nonimmediate_operand" "")
10314 (not:QI (match_dup 1)))]
10315 "ix86_match_ccmode (insn, CCNOmode)"
10316 [(parallel [(set (reg:CCNO 17)
10317 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10320 (xor:QI (match_dup 1) (const_int -1)))])]
10323 ;; Arithmetic shift instructions
10325 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10326 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10327 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10328 ;; from the assembler input.
10330 ;; This instruction shifts the target reg/mem as usual, but instead of
10331 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10332 ;; is a left shift double, bits are taken from the high order bits of
10333 ;; reg, else if the insn is a shift right double, bits are taken from the
10334 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10335 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10337 ;; Since sh[lr]d does not change the `reg' operand, that is done
10338 ;; separately, making all shifts emit pairs of shift double and normal
10339 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10340 ;; support a 63 bit shift, each shift where the count is in a reg expands
10341 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10343 ;; If the shift count is a constant, we need never emit more than one
10344 ;; shift pair, instead using moves and sign extension for counts greater
10347 (define_expand "ashldi3"
10348 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10349 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10350 (match_operand:QI 2 "nonmemory_operand" "")))
10351 (clobber (reg:CC 17))])]
10354 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10356 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10359 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10363 (define_insn "*ashldi3_1_rex64"
10364 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10365 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10366 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10367 (clobber (reg:CC 17))]
10368 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10370 switch (get_attr_type (insn))
10373 if (operands[2] != const1_rtx)
10375 if (!rtx_equal_p (operands[0], operands[1]))
10377 return "add{q}\t{%0, %0|%0, %0}";
10380 if (GET_CODE (operands[2]) != CONST_INT
10381 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10383 operands[1] = gen_rtx_MULT (DImode, operands[1],
10384 GEN_INT (1 << INTVAL (operands[2])));
10385 return "lea{q}\t{%a1, %0|%0, %a1}";
10388 if (REG_P (operands[2]))
10389 return "sal{q}\t{%b2, %0|%0, %b2}";
10390 else if (GET_CODE (operands[2]) == CONST_INT
10391 && INTVAL (operands[2]) == 1
10392 && (TARGET_SHIFT1 || optimize_size))
10393 return "sal{q}\t%0";
10395 return "sal{q}\t{%2, %0|%0, %2}";
10398 [(set (attr "type")
10399 (cond [(eq_attr "alternative" "1")
10400 (const_string "lea")
10401 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10403 (match_operand 0 "register_operand" ""))
10404 (match_operand 2 "const1_operand" ""))
10405 (const_string "alu")
10407 (const_string "ishift")))
10408 (set_attr "mode" "DI")])
10410 ;; Convert lea to the lea pattern to avoid flags dependency.
10412 [(set (match_operand:DI 0 "register_operand" "")
10413 (ashift:DI (match_operand:DI 1 "register_operand" "")
10414 (match_operand:QI 2 "immediate_operand" "")))
10415 (clobber (reg:CC 17))]
10416 "TARGET_64BIT && reload_completed
10417 && true_regnum (operands[0]) != true_regnum (operands[1])"
10418 [(set (match_dup 0)
10419 (mult:DI (match_dup 1)
10421 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10423 ;; This pattern can't accept a variable shift count, since shifts by
10424 ;; zero don't affect the flags. We assume that shifts by constant
10425 ;; zero are optimized away.
10426 (define_insn "*ashldi3_cmp_rex64"
10429 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10430 (match_operand:QI 2 "immediate_operand" "e"))
10432 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10433 (ashift:DI (match_dup 1) (match_dup 2)))]
10434 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10435 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10437 switch (get_attr_type (insn))
10440 if (operands[2] != const1_rtx)
10442 return "add{q}\t{%0, %0|%0, %0}";
10445 if (REG_P (operands[2]))
10446 return "sal{q}\t{%b2, %0|%0, %b2}";
10447 else if (GET_CODE (operands[2]) == CONST_INT
10448 && INTVAL (operands[2]) == 1
10449 && (TARGET_SHIFT1 || optimize_size))
10450 return "sal{q}\t%0";
10452 return "sal{q}\t{%2, %0|%0, %2}";
10455 [(set (attr "type")
10456 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10458 (match_operand 0 "register_operand" ""))
10459 (match_operand 2 "const1_operand" ""))
10460 (const_string "alu")
10462 (const_string "ishift")))
10463 (set_attr "mode" "DI")])
10465 (define_insn "ashldi3_1"
10466 [(set (match_operand:DI 0 "register_operand" "=r")
10467 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10468 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10469 (clobber (match_scratch:SI 3 "=&r"))
10470 (clobber (reg:CC 17))]
10471 "!TARGET_64BIT && TARGET_CMOVE"
10473 [(set_attr "type" "multi")])
10475 (define_insn "*ashldi3_2"
10476 [(set (match_operand:DI 0 "register_operand" "=r")
10477 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10478 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10479 (clobber (reg:CC 17))]
10482 [(set_attr "type" "multi")])
10485 [(set (match_operand:DI 0 "register_operand" "")
10486 (ashift:DI (match_operand:DI 1 "register_operand" "")
10487 (match_operand:QI 2 "nonmemory_operand" "")))
10488 (clobber (match_scratch:SI 3 ""))
10489 (clobber (reg:CC 17))]
10490 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10492 "ix86_split_ashldi (operands, operands[3]); DONE;")
10495 [(set (match_operand:DI 0 "register_operand" "")
10496 (ashift:DI (match_operand:DI 1 "register_operand" "")
10497 (match_operand:QI 2 "nonmemory_operand" "")))
10498 (clobber (reg:CC 17))]
10499 "!TARGET_64BIT && reload_completed"
10501 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10503 (define_insn "x86_shld_1"
10504 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10505 (ior:SI (ashift:SI (match_dup 0)
10506 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10507 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10508 (minus:QI (const_int 32) (match_dup 2)))))
10509 (clobber (reg:CC 17))]
10512 shld{l}\t{%2, %1, %0|%0, %1, %2}
10513 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10514 [(set_attr "type" "ishift")
10515 (set_attr "prefix_0f" "1")
10516 (set_attr "mode" "SI")
10517 (set_attr "pent_pair" "np")
10518 (set_attr "athlon_decode" "vector")
10519 (set_attr "ppro_uops" "few")])
10521 (define_expand "x86_shift_adj_1"
10523 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10526 (set (match_operand:SI 0 "register_operand" "")
10527 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10528 (match_operand:SI 1 "register_operand" "")
10531 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10532 (match_operand:SI 3 "register_operand" "r")
10537 (define_expand "x86_shift_adj_2"
10538 [(use (match_operand:SI 0 "register_operand" ""))
10539 (use (match_operand:SI 1 "register_operand" ""))
10540 (use (match_operand:QI 2 "register_operand" ""))]
10543 rtx label = gen_label_rtx ();
10546 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10548 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10549 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10550 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10551 gen_rtx_LABEL_REF (VOIDmode, label),
10553 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10554 JUMP_LABEL (tmp) = label;
10556 emit_move_insn (operands[0], operands[1]);
10557 emit_move_insn (operands[1], const0_rtx);
10559 emit_label (label);
10560 LABEL_NUSES (label) = 1;
10565 (define_expand "ashlsi3"
10566 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10567 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10568 (match_operand:QI 2 "nonmemory_operand" "")))
10569 (clobber (reg:CC 17))]
10571 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10573 (define_insn "*ashlsi3_1"
10574 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10575 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10576 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10577 (clobber (reg:CC 17))]
10578 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10580 switch (get_attr_type (insn))
10583 if (operands[2] != const1_rtx)
10585 if (!rtx_equal_p (operands[0], operands[1]))
10587 return "add{l}\t{%0, %0|%0, %0}";
10593 if (REG_P (operands[2]))
10594 return "sal{l}\t{%b2, %0|%0, %b2}";
10595 else if (GET_CODE (operands[2]) == CONST_INT
10596 && INTVAL (operands[2]) == 1
10597 && (TARGET_SHIFT1 || optimize_size))
10598 return "sal{l}\t%0";
10600 return "sal{l}\t{%2, %0|%0, %2}";
10603 [(set (attr "type")
10604 (cond [(eq_attr "alternative" "1")
10605 (const_string "lea")
10606 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10608 (match_operand 0 "register_operand" ""))
10609 (match_operand 2 "const1_operand" ""))
10610 (const_string "alu")
10612 (const_string "ishift")))
10613 (set_attr "mode" "SI")])
10615 ;; Convert lea to the lea pattern to avoid flags dependency.
10617 [(set (match_operand 0 "register_operand" "")
10618 (ashift (match_operand 1 "register_operand" "")
10619 (match_operand:QI 2 "const_int_operand" "")))
10620 (clobber (reg:CC 17))]
10622 && true_regnum (operands[0]) != true_regnum (operands[1])"
10626 operands[0] = gen_lowpart (SImode, operands[0]);
10627 operands[1] = gen_lowpart (Pmode, operands[1]);
10628 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10629 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10630 if (Pmode != SImode)
10631 pat = gen_rtx_SUBREG (SImode, pat, 0);
10632 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10636 (define_insn "*ashlsi3_1_zext"
10637 [(set (match_operand:DI 0 "register_operand" "=r,r")
10638 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10639 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10640 (clobber (reg:CC 17))]
10641 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10643 switch (get_attr_type (insn))
10646 if (operands[2] != const1_rtx)
10648 return "add{l}\t{%k0, %k0|%k0, %k0}";
10654 if (REG_P (operands[2]))
10655 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10656 else if (GET_CODE (operands[2]) == CONST_INT
10657 && INTVAL (operands[2]) == 1
10658 && (TARGET_SHIFT1 || optimize_size))
10659 return "sal{l}\t%k0";
10661 return "sal{l}\t{%2, %k0|%k0, %2}";
10664 [(set (attr "type")
10665 (cond [(eq_attr "alternative" "1")
10666 (const_string "lea")
10667 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10669 (match_operand 2 "const1_operand" ""))
10670 (const_string "alu")
10672 (const_string "ishift")))
10673 (set_attr "mode" "SI")])
10675 ;; Convert lea to the lea pattern to avoid flags dependency.
10677 [(set (match_operand:DI 0 "register_operand" "")
10678 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10679 (match_operand:QI 2 "const_int_operand" ""))))
10680 (clobber (reg:CC 17))]
10682 && true_regnum (operands[0]) != true_regnum (operands[1])"
10683 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10685 operands[1] = gen_lowpart (Pmode, operands[1]);
10686 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10689 ;; This pattern can't accept a variable shift count, since shifts by
10690 ;; zero don't affect the flags. We assume that shifts by constant
10691 ;; zero are optimized away.
10692 (define_insn "*ashlsi3_cmp"
10695 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10696 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10698 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10699 (ashift:SI (match_dup 1) (match_dup 2)))]
10700 "ix86_match_ccmode (insn, CCGOCmode)
10701 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10703 switch (get_attr_type (insn))
10706 if (operands[2] != const1_rtx)
10708 return "add{l}\t{%0, %0|%0, %0}";
10711 if (REG_P (operands[2]))
10712 return "sal{l}\t{%b2, %0|%0, %b2}";
10713 else if (GET_CODE (operands[2]) == CONST_INT
10714 && INTVAL (operands[2]) == 1
10715 && (TARGET_SHIFT1 || optimize_size))
10716 return "sal{l}\t%0";
10718 return "sal{l}\t{%2, %0|%0, %2}";
10721 [(set (attr "type")
10722 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10724 (match_operand 0 "register_operand" ""))
10725 (match_operand 2 "const1_operand" ""))
10726 (const_string "alu")
10728 (const_string "ishift")))
10729 (set_attr "mode" "SI")])
10731 (define_insn "*ashlsi3_cmp_zext"
10734 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10735 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10737 (set (match_operand:DI 0 "register_operand" "=r")
10738 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10739 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10740 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10742 switch (get_attr_type (insn))
10745 if (operands[2] != const1_rtx)
10747 return "add{l}\t{%k0, %k0|%k0, %k0}";
10750 if (REG_P (operands[2]))
10751 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10752 else if (GET_CODE (operands[2]) == CONST_INT
10753 && INTVAL (operands[2]) == 1
10754 && (TARGET_SHIFT1 || optimize_size))
10755 return "sal{l}\t%k0";
10757 return "sal{l}\t{%2, %k0|%k0, %2}";
10760 [(set (attr "type")
10761 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10763 (match_operand 2 "const1_operand" ""))
10764 (const_string "alu")
10766 (const_string "ishift")))
10767 (set_attr "mode" "SI")])
10769 (define_expand "ashlhi3"
10770 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10771 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10772 (match_operand:QI 2 "nonmemory_operand" "")))
10773 (clobber (reg:CC 17))]
10774 "TARGET_HIMODE_MATH"
10775 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10777 (define_insn "*ashlhi3_1_lea"
10778 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10779 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10780 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10781 (clobber (reg:CC 17))]
10782 "!TARGET_PARTIAL_REG_STALL
10783 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10785 switch (get_attr_type (insn))
10790 if (operands[2] != const1_rtx)
10792 return "add{w}\t{%0, %0|%0, %0}";
10795 if (REG_P (operands[2]))
10796 return "sal{w}\t{%b2, %0|%0, %b2}";
10797 else if (GET_CODE (operands[2]) == CONST_INT
10798 && INTVAL (operands[2]) == 1
10799 && (TARGET_SHIFT1 || optimize_size))
10800 return "sal{w}\t%0";
10802 return "sal{w}\t{%2, %0|%0, %2}";
10805 [(set (attr "type")
10806 (cond [(eq_attr "alternative" "1")
10807 (const_string "lea")
10808 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10810 (match_operand 0 "register_operand" ""))
10811 (match_operand 2 "const1_operand" ""))
10812 (const_string "alu")
10814 (const_string "ishift")))
10815 (set_attr "mode" "HI,SI")])
10817 (define_insn "*ashlhi3_1"
10818 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10819 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10820 (match_operand:QI 2 "nonmemory_operand" "cI")))
10821 (clobber (reg:CC 17))]
10822 "TARGET_PARTIAL_REG_STALL
10823 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10825 switch (get_attr_type (insn))
10828 if (operands[2] != const1_rtx)
10830 return "add{w}\t{%0, %0|%0, %0}";
10833 if (REG_P (operands[2]))
10834 return "sal{w}\t{%b2, %0|%0, %b2}";
10835 else if (GET_CODE (operands[2]) == CONST_INT
10836 && INTVAL (operands[2]) == 1
10837 && (TARGET_SHIFT1 || optimize_size))
10838 return "sal{w}\t%0";
10840 return "sal{w}\t{%2, %0|%0, %2}";
10843 [(set (attr "type")
10844 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10846 (match_operand 0 "register_operand" ""))
10847 (match_operand 2 "const1_operand" ""))
10848 (const_string "alu")
10850 (const_string "ishift")))
10851 (set_attr "mode" "HI")])
10853 ;; This pattern can't accept a variable shift count, since shifts by
10854 ;; zero don't affect the flags. We assume that shifts by constant
10855 ;; zero are optimized away.
10856 (define_insn "*ashlhi3_cmp"
10859 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10860 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10862 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10863 (ashift:HI (match_dup 1) (match_dup 2)))]
10864 "ix86_match_ccmode (insn, CCGOCmode)
10865 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10867 switch (get_attr_type (insn))
10870 if (operands[2] != const1_rtx)
10872 return "add{w}\t{%0, %0|%0, %0}";
10875 if (REG_P (operands[2]))
10876 return "sal{w}\t{%b2, %0|%0, %b2}";
10877 else if (GET_CODE (operands[2]) == CONST_INT
10878 && INTVAL (operands[2]) == 1
10879 && (TARGET_SHIFT1 || optimize_size))
10880 return "sal{w}\t%0";
10882 return "sal{w}\t{%2, %0|%0, %2}";
10885 [(set (attr "type")
10886 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10888 (match_operand 0 "register_operand" ""))
10889 (match_operand 2 "const1_operand" ""))
10890 (const_string "alu")
10892 (const_string "ishift")))
10893 (set_attr "mode" "HI")])
10895 (define_expand "ashlqi3"
10896 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10897 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10898 (match_operand:QI 2 "nonmemory_operand" "")))
10899 (clobber (reg:CC 17))]
10900 "TARGET_QIMODE_MATH"
10901 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10903 ;; %%% Potential partial reg stall on alternative 2. What to do?
10905 (define_insn "*ashlqi3_1_lea"
10906 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10907 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
10908 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10909 (clobber (reg:CC 17))]
10910 "!TARGET_PARTIAL_REG_STALL
10911 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10913 switch (get_attr_type (insn))
10918 if (operands[2] != const1_rtx)
10920 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10921 return "add{l}\t{%k0, %k0|%k0, %k0}";
10923 return "add{b}\t{%0, %0|%0, %0}";
10926 if (REG_P (operands[2]))
10928 if (get_attr_mode (insn) == MODE_SI)
10929 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10931 return "sal{b}\t{%b2, %0|%0, %b2}";
10933 else if (GET_CODE (operands[2]) == CONST_INT
10934 && INTVAL (operands[2]) == 1
10935 && (TARGET_SHIFT1 || optimize_size))
10937 if (get_attr_mode (insn) == MODE_SI)
10938 return "sal{l}\t%0";
10940 return "sal{b}\t%0";
10944 if (get_attr_mode (insn) == MODE_SI)
10945 return "sal{l}\t{%2, %k0|%k0, %2}";
10947 return "sal{b}\t{%2, %0|%0, %2}";
10951 [(set (attr "type")
10952 (cond [(eq_attr "alternative" "2")
10953 (const_string "lea")
10954 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10956 (match_operand 0 "register_operand" ""))
10957 (match_operand 2 "const1_operand" ""))
10958 (const_string "alu")
10960 (const_string "ishift")))
10961 (set_attr "mode" "QI,SI,SI")])
10963 (define_insn "*ashlqi3_1"
10964 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10965 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
10966 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
10967 (clobber (reg:CC 17))]
10968 "TARGET_PARTIAL_REG_STALL
10969 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10971 switch (get_attr_type (insn))
10974 if (operands[2] != const1_rtx)
10976 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10977 return "add{l}\t{%k0, %k0|%k0, %k0}";
10979 return "add{b}\t{%0, %0|%0, %0}";
10982 if (REG_P (operands[2]))
10984 if (get_attr_mode (insn) == MODE_SI)
10985 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10987 return "sal{b}\t{%b2, %0|%0, %b2}";
10989 else if (GET_CODE (operands[2]) == CONST_INT
10990 && INTVAL (operands[2]) == 1
10991 && (TARGET_SHIFT1 || optimize_size))
10993 if (get_attr_mode (insn) == MODE_SI)
10994 return "sal{l}\t%0";
10996 return "sal{b}\t%0";
11000 if (get_attr_mode (insn) == MODE_SI)
11001 return "sal{l}\t{%2, %k0|%k0, %2}";
11003 return "sal{b}\t{%2, %0|%0, %2}";
11007 [(set (attr "type")
11008 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11010 (match_operand 0 "register_operand" ""))
11011 (match_operand 2 "const1_operand" ""))
11012 (const_string "alu")
11014 (const_string "ishift")))
11015 (set_attr "mode" "QI,SI")])
11017 ;; This pattern can't accept a variable shift count, since shifts by
11018 ;; zero don't affect the flags. We assume that shifts by constant
11019 ;; zero are optimized away.
11020 (define_insn "*ashlqi3_cmp"
11023 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11024 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11026 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11027 (ashift:QI (match_dup 1) (match_dup 2)))]
11028 "ix86_match_ccmode (insn, CCGOCmode)
11029 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11031 switch (get_attr_type (insn))
11034 if (operands[2] != const1_rtx)
11036 return "add{b}\t{%0, %0|%0, %0}";
11039 if (REG_P (operands[2]))
11040 return "sal{b}\t{%b2, %0|%0, %b2}";
11041 else if (GET_CODE (operands[2]) == CONST_INT
11042 && INTVAL (operands[2]) == 1
11043 && (TARGET_SHIFT1 || optimize_size))
11044 return "sal{b}\t%0";
11046 return "sal{b}\t{%2, %0|%0, %2}";
11049 [(set (attr "type")
11050 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11052 (match_operand 0 "register_operand" ""))
11053 (match_operand 2 "const1_operand" ""))
11054 (const_string "alu")
11056 (const_string "ishift")))
11057 (set_attr "mode" "QI")])
11059 ;; See comment above `ashldi3' about how this works.
11061 (define_expand "ashrdi3"
11062 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11063 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11064 (match_operand:QI 2 "nonmemory_operand" "")))
11065 (clobber (reg:CC 17))])]
11068 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11070 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11073 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11077 (define_insn "ashrdi3_63_rex64"
11078 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11079 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11080 (match_operand:DI 2 "const_int_operand" "i,i")))
11081 (clobber (reg:CC 17))]
11082 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11083 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11086 sar{q}\t{%2, %0|%0, %2}"
11087 [(set_attr "type" "imovx,ishift")
11088 (set_attr "prefix_0f" "0,*")
11089 (set_attr "length_immediate" "0,*")
11090 (set_attr "modrm" "0,1")
11091 (set_attr "mode" "DI")])
11093 (define_insn "*ashrdi3_1_one_bit_rex64"
11094 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11095 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11096 (match_operand:QI 2 "const_int_1_operand" "")))
11097 (clobber (reg:CC 17))]
11098 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11099 && (TARGET_SHIFT1 || optimize_size)"
11101 [(set_attr "type" "ishift")
11102 (set (attr "length")
11103 (if_then_else (match_operand:DI 0 "register_operand" "")
11105 (const_string "*")))])
11107 (define_insn "*ashrdi3_1_rex64"
11108 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11109 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11110 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11111 (clobber (reg:CC 17))]
11112 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11114 sar{q}\t{%2, %0|%0, %2}
11115 sar{q}\t{%b2, %0|%0, %b2}"
11116 [(set_attr "type" "ishift")
11117 (set_attr "mode" "DI")])
11119 ;; This pattern can't accept a variable shift count, since shifts by
11120 ;; zero don't affect the flags. We assume that shifts by constant
11121 ;; zero are optimized away.
11122 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11125 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11126 (match_operand:QI 2 "const_int_1_operand" ""))
11128 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11129 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11130 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11131 && (TARGET_SHIFT1 || optimize_size)
11132 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11134 [(set_attr "type" "ishift")
11135 (set (attr "length")
11136 (if_then_else (match_operand:DI 0 "register_operand" "")
11138 (const_string "*")))])
11140 ;; This pattern can't accept a variable shift count, since shifts by
11141 ;; zero don't affect the flags. We assume that shifts by constant
11142 ;; zero are optimized away.
11143 (define_insn "*ashrdi3_cmp_rex64"
11146 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11147 (match_operand:QI 2 "const_int_operand" "n"))
11149 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11150 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11151 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11152 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11153 "sar{q}\t{%2, %0|%0, %2}"
11154 [(set_attr "type" "ishift")
11155 (set_attr "mode" "DI")])
11158 (define_insn "ashrdi3_1"
11159 [(set (match_operand:DI 0 "register_operand" "=r")
11160 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11161 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11162 (clobber (match_scratch:SI 3 "=&r"))
11163 (clobber (reg:CC 17))]
11164 "!TARGET_64BIT && TARGET_CMOVE"
11166 [(set_attr "type" "multi")])
11168 (define_insn "*ashrdi3_2"
11169 [(set (match_operand:DI 0 "register_operand" "=r")
11170 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11171 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11172 (clobber (reg:CC 17))]
11175 [(set_attr "type" "multi")])
11178 [(set (match_operand:DI 0 "register_operand" "")
11179 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11180 (match_operand:QI 2 "nonmemory_operand" "")))
11181 (clobber (match_scratch:SI 3 ""))
11182 (clobber (reg:CC 17))]
11183 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11185 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11188 [(set (match_operand:DI 0 "register_operand" "")
11189 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11190 (match_operand:QI 2 "nonmemory_operand" "")))
11191 (clobber (reg:CC 17))]
11192 "!TARGET_64BIT && reload_completed"
11194 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11196 (define_insn "x86_shrd_1"
11197 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11198 (ior:SI (ashiftrt:SI (match_dup 0)
11199 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11200 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11201 (minus:QI (const_int 32) (match_dup 2)))))
11202 (clobber (reg:CC 17))]
11205 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11206 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11207 [(set_attr "type" "ishift")
11208 (set_attr "prefix_0f" "1")
11209 (set_attr "pent_pair" "np")
11210 (set_attr "ppro_uops" "few")
11211 (set_attr "mode" "SI")])
11213 (define_expand "x86_shift_adj_3"
11214 [(use (match_operand:SI 0 "register_operand" ""))
11215 (use (match_operand:SI 1 "register_operand" ""))
11216 (use (match_operand:QI 2 "register_operand" ""))]
11219 rtx label = gen_label_rtx ();
11222 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11224 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11225 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11226 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11227 gen_rtx_LABEL_REF (VOIDmode, label),
11229 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11230 JUMP_LABEL (tmp) = label;
11232 emit_move_insn (operands[0], operands[1]);
11233 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11235 emit_label (label);
11236 LABEL_NUSES (label) = 1;
11241 (define_insn "ashrsi3_31"
11242 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11243 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11244 (match_operand:SI 2 "const_int_operand" "i,i")))
11245 (clobber (reg:CC 17))]
11246 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11247 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11250 sar{l}\t{%2, %0|%0, %2}"
11251 [(set_attr "type" "imovx,ishift")
11252 (set_attr "prefix_0f" "0,*")
11253 (set_attr "length_immediate" "0,*")
11254 (set_attr "modrm" "0,1")
11255 (set_attr "mode" "SI")])
11257 (define_insn "*ashrsi3_31_zext"
11258 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11259 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11260 (match_operand:SI 2 "const_int_operand" "i,i"))))
11261 (clobber (reg:CC 17))]
11262 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11263 && INTVAL (operands[2]) == 31
11264 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11267 sar{l}\t{%2, %k0|%k0, %2}"
11268 [(set_attr "type" "imovx,ishift")
11269 (set_attr "prefix_0f" "0,*")
11270 (set_attr "length_immediate" "0,*")
11271 (set_attr "modrm" "0,1")
11272 (set_attr "mode" "SI")])
11274 (define_expand "ashrsi3"
11275 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11276 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11277 (match_operand:QI 2 "nonmemory_operand" "")))
11278 (clobber (reg:CC 17))]
11280 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11282 (define_insn "*ashrsi3_1_one_bit"
11283 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11284 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11285 (match_operand:QI 2 "const_int_1_operand" "")))
11286 (clobber (reg:CC 17))]
11287 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11288 && (TARGET_SHIFT1 || optimize_size)"
11290 [(set_attr "type" "ishift")
11291 (set (attr "length")
11292 (if_then_else (match_operand:SI 0 "register_operand" "")
11294 (const_string "*")))])
11296 (define_insn "*ashrsi3_1_one_bit_zext"
11297 [(set (match_operand:DI 0 "register_operand" "=r")
11298 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11299 (match_operand:QI 2 "const_int_1_operand" ""))))
11300 (clobber (reg:CC 17))]
11301 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11302 && (TARGET_SHIFT1 || optimize_size)"
11304 [(set_attr "type" "ishift")
11305 (set_attr "length" "2")])
11307 (define_insn "*ashrsi3_1"
11308 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11309 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11310 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11311 (clobber (reg:CC 17))]
11312 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11314 sar{l}\t{%2, %0|%0, %2}
11315 sar{l}\t{%b2, %0|%0, %b2}"
11316 [(set_attr "type" "ishift")
11317 (set_attr "mode" "SI")])
11319 (define_insn "*ashrsi3_1_zext"
11320 [(set (match_operand:DI 0 "register_operand" "=r,r")
11321 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11322 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11323 (clobber (reg:CC 17))]
11324 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11326 sar{l}\t{%2, %k0|%k0, %2}
11327 sar{l}\t{%b2, %k0|%k0, %b2}"
11328 [(set_attr "type" "ishift")
11329 (set_attr "mode" "SI")])
11331 ;; This pattern can't accept a variable shift count, since shifts by
11332 ;; zero don't affect the flags. We assume that shifts by constant
11333 ;; zero are optimized away.
11334 (define_insn "*ashrsi3_one_bit_cmp"
11337 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11338 (match_operand:QI 2 "const_int_1_operand" ""))
11340 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11341 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11342 "ix86_match_ccmode (insn, CCGOCmode)
11343 && (TARGET_SHIFT1 || optimize_size)
11344 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11346 [(set_attr "type" "ishift")
11347 (set (attr "length")
11348 (if_then_else (match_operand:SI 0 "register_operand" "")
11350 (const_string "*")))])
11352 (define_insn "*ashrsi3_one_bit_cmp_zext"
11355 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11356 (match_operand:QI 2 "const_int_1_operand" ""))
11358 (set (match_operand:DI 0 "register_operand" "=r")
11359 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11360 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11361 && (TARGET_SHIFT1 || optimize_size)
11362 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11364 [(set_attr "type" "ishift")
11365 (set_attr "length" "2")])
11367 ;; This pattern can't accept a variable shift count, since shifts by
11368 ;; zero don't affect the flags. We assume that shifts by constant
11369 ;; zero are optimized away.
11370 (define_insn "*ashrsi3_cmp"
11373 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11374 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11376 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11377 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11378 "ix86_match_ccmode (insn, CCGOCmode)
11379 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11380 "sar{l}\t{%2, %0|%0, %2}"
11381 [(set_attr "type" "ishift")
11382 (set_attr "mode" "SI")])
11384 (define_insn "*ashrsi3_cmp_zext"
11387 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11388 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11390 (set (match_operand:DI 0 "register_operand" "=r")
11391 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11392 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11393 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11394 "sar{l}\t{%2, %k0|%k0, %2}"
11395 [(set_attr "type" "ishift")
11396 (set_attr "mode" "SI")])
11398 (define_expand "ashrhi3"
11399 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11400 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11401 (match_operand:QI 2 "nonmemory_operand" "")))
11402 (clobber (reg:CC 17))]
11403 "TARGET_HIMODE_MATH"
11404 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11406 (define_insn "*ashrhi3_1_one_bit"
11407 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11408 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11409 (match_operand:QI 2 "const_int_1_operand" "")))
11410 (clobber (reg:CC 17))]
11411 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11412 && (TARGET_SHIFT1 || optimize_size)"
11414 [(set_attr "type" "ishift")
11415 (set (attr "length")
11416 (if_then_else (match_operand 0 "register_operand" "")
11418 (const_string "*")))])
11420 (define_insn "*ashrhi3_1"
11421 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11422 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11423 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11424 (clobber (reg:CC 17))]
11425 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11427 sar{w}\t{%2, %0|%0, %2}
11428 sar{w}\t{%b2, %0|%0, %b2}"
11429 [(set_attr "type" "ishift")
11430 (set_attr "mode" "HI")])
11432 ;; This pattern can't accept a variable shift count, since shifts by
11433 ;; zero don't affect the flags. We assume that shifts by constant
11434 ;; zero are optimized away.
11435 (define_insn "*ashrhi3_one_bit_cmp"
11438 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11439 (match_operand:QI 2 "const_int_1_operand" ""))
11441 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11442 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11443 "ix86_match_ccmode (insn, CCGOCmode)
11444 && (TARGET_SHIFT1 || optimize_size)
11445 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11447 [(set_attr "type" "ishift")
11448 (set (attr "length")
11449 (if_then_else (match_operand 0 "register_operand" "")
11451 (const_string "*")))])
11453 ;; This pattern can't accept a variable shift count, since shifts by
11454 ;; zero don't affect the flags. We assume that shifts by constant
11455 ;; zero are optimized away.
11456 (define_insn "*ashrhi3_cmp"
11459 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11460 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11462 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11463 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11464 "ix86_match_ccmode (insn, CCGOCmode)
11465 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11466 "sar{w}\t{%2, %0|%0, %2}"
11467 [(set_attr "type" "ishift")
11468 (set_attr "mode" "HI")])
11470 (define_expand "ashrqi3"
11471 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11472 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11473 (match_operand:QI 2 "nonmemory_operand" "")))
11474 (clobber (reg:CC 17))]
11475 "TARGET_QIMODE_MATH"
11476 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11478 (define_insn "*ashrqi3_1_one_bit"
11479 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11480 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11481 (match_operand:QI 2 "const_int_1_operand" "")))
11482 (clobber (reg:CC 17))]
11483 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11484 && (TARGET_SHIFT1 || optimize_size)"
11486 [(set_attr "type" "ishift")
11487 (set (attr "length")
11488 (if_then_else (match_operand 0 "register_operand" "")
11490 (const_string "*")))])
11492 (define_insn "*ashrqi3_1_one_bit_slp"
11493 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11494 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11495 (match_operand:QI 2 "const_int_1_operand" "")))
11496 (clobber (reg:CC 17))]
11497 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11498 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11499 && (TARGET_SHIFT1 || optimize_size)"
11501 [(set_attr "type" "ishift")
11502 (set (attr "length")
11503 (if_then_else (match_operand 0 "register_operand" "")
11505 (const_string "*")))])
11507 (define_insn "*ashrqi3_1"
11508 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11509 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11510 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11511 (clobber (reg:CC 17))]
11512 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11514 sar{b}\t{%2, %0|%0, %2}
11515 sar{b}\t{%b2, %0|%0, %b2}"
11516 [(set_attr "type" "ishift")
11517 (set_attr "mode" "QI")])
11519 (define_insn "*ashrqi3_1_slp"
11520 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11521 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11522 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11523 (clobber (reg:CC 17))]
11524 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11525 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11527 sar{b}\t{%2, %0|%0, %2}
11528 sar{b}\t{%b2, %0|%0, %b2}"
11529 [(set_attr "type" "ishift")
11530 (set_attr "mode" "QI")])
11532 ;; This pattern can't accept a variable shift count, since shifts by
11533 ;; zero don't affect the flags. We assume that shifts by constant
11534 ;; zero are optimized away.
11535 (define_insn "*ashrqi3_one_bit_cmp"
11538 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11539 (match_operand:QI 2 "const_int_1_operand" "I"))
11541 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11542 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11543 "ix86_match_ccmode (insn, CCGOCmode)
11544 && (TARGET_SHIFT1 || optimize_size)
11545 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11547 [(set_attr "type" "ishift")
11548 (set (attr "length")
11549 (if_then_else (match_operand 0 "register_operand" "")
11551 (const_string "*")))])
11553 ;; This pattern can't accept a variable shift count, since shifts by
11554 ;; zero don't affect the flags. We assume that shifts by constant
11555 ;; zero are optimized away.
11556 (define_insn "*ashrqi3_cmp"
11559 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11560 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11562 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11563 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11564 "ix86_match_ccmode (insn, CCGOCmode)
11565 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11566 "sar{b}\t{%2, %0|%0, %2}"
11567 [(set_attr "type" "ishift")
11568 (set_attr "mode" "QI")])
11570 ;; Logical shift instructions
11572 ;; See comment above `ashldi3' about how this works.
11574 (define_expand "lshrdi3"
11575 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11576 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11577 (match_operand:QI 2 "nonmemory_operand" "")))
11578 (clobber (reg:CC 17))])]
11581 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11583 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11586 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11590 (define_insn "*lshrdi3_1_one_bit_rex64"
11591 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11592 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11593 (match_operand:QI 2 "const_int_1_operand" "")))
11594 (clobber (reg:CC 17))]
11595 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11596 && (TARGET_SHIFT1 || optimize_size)"
11598 [(set_attr "type" "ishift")
11599 (set (attr "length")
11600 (if_then_else (match_operand:DI 0 "register_operand" "")
11602 (const_string "*")))])
11604 (define_insn "*lshrdi3_1_rex64"
11605 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11606 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11607 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11608 (clobber (reg:CC 17))]
11609 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11611 shr{q}\t{%2, %0|%0, %2}
11612 shr{q}\t{%b2, %0|%0, %b2}"
11613 [(set_attr "type" "ishift")
11614 (set_attr "mode" "DI")])
11616 ;; This pattern can't accept a variable shift count, since shifts by
11617 ;; zero don't affect the flags. We assume that shifts by constant
11618 ;; zero are optimized away.
11619 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11622 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11623 (match_operand:QI 2 "const_int_1_operand" ""))
11625 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11626 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11627 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11628 && (TARGET_SHIFT1 || optimize_size)
11629 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11631 [(set_attr "type" "ishift")
11632 (set (attr "length")
11633 (if_then_else (match_operand:DI 0 "register_operand" "")
11635 (const_string "*")))])
11637 ;; This pattern can't accept a variable shift count, since shifts by
11638 ;; zero don't affect the flags. We assume that shifts by constant
11639 ;; zero are optimized away.
11640 (define_insn "*lshrdi3_cmp_rex64"
11643 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11644 (match_operand:QI 2 "const_int_operand" "e"))
11646 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11647 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11648 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11649 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11650 "shr{q}\t{%2, %0|%0, %2}"
11651 [(set_attr "type" "ishift")
11652 (set_attr "mode" "DI")])
11654 (define_insn "lshrdi3_1"
11655 [(set (match_operand:DI 0 "register_operand" "=r")
11656 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11657 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11658 (clobber (match_scratch:SI 3 "=&r"))
11659 (clobber (reg:CC 17))]
11660 "!TARGET_64BIT && TARGET_CMOVE"
11662 [(set_attr "type" "multi")])
11664 (define_insn "*lshrdi3_2"
11665 [(set (match_operand:DI 0 "register_operand" "=r")
11666 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11667 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11668 (clobber (reg:CC 17))]
11671 [(set_attr "type" "multi")])
11674 [(set (match_operand:DI 0 "register_operand" "")
11675 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11676 (match_operand:QI 2 "nonmemory_operand" "")))
11677 (clobber (match_scratch:SI 3 ""))
11678 (clobber (reg:CC 17))]
11679 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11681 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11684 [(set (match_operand:DI 0 "register_operand" "")
11685 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11686 (match_operand:QI 2 "nonmemory_operand" "")))
11687 (clobber (reg:CC 17))]
11688 "!TARGET_64BIT && reload_completed"
11690 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11692 (define_expand "lshrsi3"
11693 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11694 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11695 (match_operand:QI 2 "nonmemory_operand" "")))
11696 (clobber (reg:CC 17))]
11698 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11700 (define_insn "*lshrsi3_1_one_bit"
11701 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11702 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11703 (match_operand:QI 2 "const_int_1_operand" "")))
11704 (clobber (reg:CC 17))]
11705 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11706 && (TARGET_SHIFT1 || optimize_size)"
11708 [(set_attr "type" "ishift")
11709 (set (attr "length")
11710 (if_then_else (match_operand:SI 0 "register_operand" "")
11712 (const_string "*")))])
11714 (define_insn "*lshrsi3_1_one_bit_zext"
11715 [(set (match_operand:DI 0 "register_operand" "=r")
11716 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11717 (match_operand:QI 2 "const_int_1_operand" "")))
11718 (clobber (reg:CC 17))]
11719 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11720 && (TARGET_SHIFT1 || optimize_size)"
11722 [(set_attr "type" "ishift")
11723 (set_attr "length" "2")])
11725 (define_insn "*lshrsi3_1"
11726 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11727 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11728 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11729 (clobber (reg:CC 17))]
11730 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11732 shr{l}\t{%2, %0|%0, %2}
11733 shr{l}\t{%b2, %0|%0, %b2}"
11734 [(set_attr "type" "ishift")
11735 (set_attr "mode" "SI")])
11737 (define_insn "*lshrsi3_1_zext"
11738 [(set (match_operand:DI 0 "register_operand" "=r,r")
11740 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11741 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11742 (clobber (reg:CC 17))]
11743 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11745 shr{l}\t{%2, %k0|%k0, %2}
11746 shr{l}\t{%b2, %k0|%k0, %b2}"
11747 [(set_attr "type" "ishift")
11748 (set_attr "mode" "SI")])
11750 ;; This pattern can't accept a variable shift count, since shifts by
11751 ;; zero don't affect the flags. We assume that shifts by constant
11752 ;; zero are optimized away.
11753 (define_insn "*lshrsi3_one_bit_cmp"
11756 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11757 (match_operand:QI 2 "const_int_1_operand" ""))
11759 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11760 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11761 "ix86_match_ccmode (insn, CCGOCmode)
11762 && (TARGET_SHIFT1 || optimize_size)
11763 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11765 [(set_attr "type" "ishift")
11766 (set (attr "length")
11767 (if_then_else (match_operand:SI 0 "register_operand" "")
11769 (const_string "*")))])
11771 (define_insn "*lshrsi3_cmp_one_bit_zext"
11774 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11775 (match_operand:QI 2 "const_int_1_operand" ""))
11777 (set (match_operand:DI 0 "register_operand" "=r")
11778 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11779 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11780 && (TARGET_SHIFT1 || optimize_size)
11781 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11783 [(set_attr "type" "ishift")
11784 (set_attr "length" "2")])
11786 ;; This pattern can't accept a variable shift count, since shifts by
11787 ;; zero don't affect the flags. We assume that shifts by constant
11788 ;; zero are optimized away.
11789 (define_insn "*lshrsi3_cmp"
11792 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11793 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11795 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11796 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11797 "ix86_match_ccmode (insn, CCGOCmode)
11798 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11799 "shr{l}\t{%2, %0|%0, %2}"
11800 [(set_attr "type" "ishift")
11801 (set_attr "mode" "SI")])
11803 (define_insn "*lshrsi3_cmp_zext"
11806 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11807 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11809 (set (match_operand:DI 0 "register_operand" "=r")
11810 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11811 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11812 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11813 "shr{l}\t{%2, %k0|%k0, %2}"
11814 [(set_attr "type" "ishift")
11815 (set_attr "mode" "SI")])
11817 (define_expand "lshrhi3"
11818 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11819 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11820 (match_operand:QI 2 "nonmemory_operand" "")))
11821 (clobber (reg:CC 17))]
11822 "TARGET_HIMODE_MATH"
11823 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11825 (define_insn "*lshrhi3_1_one_bit"
11826 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11827 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11828 (match_operand:QI 2 "const_int_1_operand" "")))
11829 (clobber (reg:CC 17))]
11830 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11831 && (TARGET_SHIFT1 || optimize_size)"
11833 [(set_attr "type" "ishift")
11834 (set (attr "length")
11835 (if_then_else (match_operand 0 "register_operand" "")
11837 (const_string "*")))])
11839 (define_insn "*lshrhi3_1"
11840 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11841 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11842 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11843 (clobber (reg:CC 17))]
11844 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11846 shr{w}\t{%2, %0|%0, %2}
11847 shr{w}\t{%b2, %0|%0, %b2}"
11848 [(set_attr "type" "ishift")
11849 (set_attr "mode" "HI")])
11851 ;; This pattern can't accept a variable shift count, since shifts by
11852 ;; zero don't affect the flags. We assume that shifts by constant
11853 ;; zero are optimized away.
11854 (define_insn "*lshrhi3_one_bit_cmp"
11857 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11858 (match_operand:QI 2 "const_int_1_operand" ""))
11860 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11861 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11862 "ix86_match_ccmode (insn, CCGOCmode)
11863 && (TARGET_SHIFT1 || optimize_size)
11864 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11866 [(set_attr "type" "ishift")
11867 (set (attr "length")
11868 (if_then_else (match_operand:SI 0 "register_operand" "")
11870 (const_string "*")))])
11872 ;; This pattern can't accept a variable shift count, since shifts by
11873 ;; zero don't affect the flags. We assume that shifts by constant
11874 ;; zero are optimized away.
11875 (define_insn "*lshrhi3_cmp"
11878 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11879 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11881 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11882 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11883 "ix86_match_ccmode (insn, CCGOCmode)
11884 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11885 "shr{w}\t{%2, %0|%0, %2}"
11886 [(set_attr "type" "ishift")
11887 (set_attr "mode" "HI")])
11889 (define_expand "lshrqi3"
11890 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11891 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11892 (match_operand:QI 2 "nonmemory_operand" "")))
11893 (clobber (reg:CC 17))]
11894 "TARGET_QIMODE_MATH"
11895 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11897 (define_insn "*lshrqi3_1_one_bit"
11898 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11899 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11900 (match_operand:QI 2 "const_int_1_operand" "")))
11901 (clobber (reg:CC 17))]
11902 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11903 && (TARGET_SHIFT1 || optimize_size)"
11905 [(set_attr "type" "ishift")
11906 (set (attr "length")
11907 (if_then_else (match_operand 0 "register_operand" "")
11909 (const_string "*")))])
11911 (define_insn "*lshrqi3_1_one_bit_slp"
11912 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11913 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11914 (match_operand:QI 2 "const_int_1_operand" "")))
11915 (clobber (reg:CC 17))]
11916 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11917 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11918 && (TARGET_SHIFT1 || optimize_size)"
11920 [(set_attr "type" "ishift")
11921 (set (attr "length")
11922 (if_then_else (match_operand 0 "register_operand" "")
11924 (const_string "*")))])
11926 (define_insn "*lshrqi3_1"
11927 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11928 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11929 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11930 (clobber (reg:CC 17))]
11931 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11933 shr{b}\t{%2, %0|%0, %2}
11934 shr{b}\t{%b2, %0|%0, %b2}"
11935 [(set_attr "type" "ishift")
11936 (set_attr "mode" "QI")])
11938 (define_insn "*lshrqi3_1_slp"
11939 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11940 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11941 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11942 (clobber (reg:CC 17))]
11943 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11944 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11946 shr{b}\t{%2, %0|%0, %2}
11947 shr{b}\t{%b2, %0|%0, %b2}"
11948 [(set_attr "type" "ishift")
11949 (set_attr "mode" "QI")])
11951 ;; This pattern can't accept a variable shift count, since shifts by
11952 ;; zero don't affect the flags. We assume that shifts by constant
11953 ;; zero are optimized away.
11954 (define_insn "*lshrqi2_one_bit_cmp"
11957 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11958 (match_operand:QI 2 "const_int_1_operand" ""))
11960 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11961 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11962 "ix86_match_ccmode (insn, CCGOCmode)
11963 && (TARGET_SHIFT1 || optimize_size)
11964 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11966 [(set_attr "type" "ishift")
11967 (set (attr "length")
11968 (if_then_else (match_operand:SI 0 "register_operand" "")
11970 (const_string "*")))])
11972 ;; This pattern can't accept a variable shift count, since shifts by
11973 ;; zero don't affect the flags. We assume that shifts by constant
11974 ;; zero are optimized away.
11975 (define_insn "*lshrqi2_cmp"
11978 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11979 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11981 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11982 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11983 "ix86_match_ccmode (insn, CCGOCmode)
11984 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11985 "shr{b}\t{%2, %0|%0, %2}"
11986 [(set_attr "type" "ishift")
11987 (set_attr "mode" "QI")])
11989 ;; Rotate instructions
11991 (define_expand "rotldi3"
11992 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11993 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
11994 (match_operand:QI 2 "nonmemory_operand" "")))
11995 (clobber (reg:CC 17))]
11997 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
11999 (define_insn "*rotlsi3_1_one_bit_rex64"
12000 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12001 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12002 (match_operand:QI 2 "const_int_1_operand" "")))
12003 (clobber (reg:CC 17))]
12004 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12005 && (TARGET_SHIFT1 || optimize_size)"
12007 [(set_attr "type" "rotate")
12008 (set (attr "length")
12009 (if_then_else (match_operand:DI 0 "register_operand" "")
12011 (const_string "*")))])
12013 (define_insn "*rotldi3_1_rex64"
12014 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12015 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12016 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12017 (clobber (reg:CC 17))]
12018 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12020 rol{q}\t{%2, %0|%0, %2}
12021 rol{q}\t{%b2, %0|%0, %b2}"
12022 [(set_attr "type" "rotate")
12023 (set_attr "mode" "DI")])
12025 (define_expand "rotlsi3"
12026 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12027 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12028 (match_operand:QI 2 "nonmemory_operand" "")))
12029 (clobber (reg:CC 17))]
12031 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12033 (define_insn "*rotlsi3_1_one_bit"
12034 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12035 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12036 (match_operand:QI 2 "const_int_1_operand" "")))
12037 (clobber (reg:CC 17))]
12038 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12039 && (TARGET_SHIFT1 || optimize_size)"
12041 [(set_attr "type" "rotate")
12042 (set (attr "length")
12043 (if_then_else (match_operand:SI 0 "register_operand" "")
12045 (const_string "*")))])
12047 (define_insn "*rotlsi3_1_one_bit_zext"
12048 [(set (match_operand:DI 0 "register_operand" "=r")
12050 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12051 (match_operand:QI 2 "const_int_1_operand" ""))))
12052 (clobber (reg:CC 17))]
12053 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12054 && (TARGET_SHIFT1 || optimize_size)"
12056 [(set_attr "type" "rotate")
12057 (set_attr "length" "2")])
12059 (define_insn "*rotlsi3_1"
12060 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12061 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12062 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12063 (clobber (reg:CC 17))]
12064 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12066 rol{l}\t{%2, %0|%0, %2}
12067 rol{l}\t{%b2, %0|%0, %b2}"
12068 [(set_attr "type" "rotate")
12069 (set_attr "mode" "SI")])
12071 (define_insn "*rotlsi3_1_zext"
12072 [(set (match_operand:DI 0 "register_operand" "=r,r")
12074 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12075 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12076 (clobber (reg:CC 17))]
12077 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12079 rol{l}\t{%2, %k0|%k0, %2}
12080 rol{l}\t{%b2, %k0|%k0, %b2}"
12081 [(set_attr "type" "rotate")
12082 (set_attr "mode" "SI")])
12084 (define_expand "rotlhi3"
12085 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12086 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12087 (match_operand:QI 2 "nonmemory_operand" "")))
12088 (clobber (reg:CC 17))]
12089 "TARGET_HIMODE_MATH"
12090 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12092 (define_insn "*rotlhi3_1_one_bit"
12093 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12094 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12095 (match_operand:QI 2 "const_int_1_operand" "")))
12096 (clobber (reg:CC 17))]
12097 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12098 && (TARGET_SHIFT1 || optimize_size)"
12100 [(set_attr "type" "rotate")
12101 (set (attr "length")
12102 (if_then_else (match_operand 0 "register_operand" "")
12104 (const_string "*")))])
12106 (define_insn "*rotlhi3_1"
12107 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12108 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12109 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12110 (clobber (reg:CC 17))]
12111 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12113 rol{w}\t{%2, %0|%0, %2}
12114 rol{w}\t{%b2, %0|%0, %b2}"
12115 [(set_attr "type" "rotate")
12116 (set_attr "mode" "HI")])
12118 (define_expand "rotlqi3"
12119 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12120 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12121 (match_operand:QI 2 "nonmemory_operand" "")))
12122 (clobber (reg:CC 17))]
12123 "TARGET_QIMODE_MATH"
12124 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12126 (define_insn "*rotlqi3_1_one_bit_slp"
12127 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12128 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12129 (match_operand:QI 2 "const_int_1_operand" "")))
12130 (clobber (reg:CC 17))]
12131 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12132 && ix86_binary_operator_ok (ROTATE, QImode, operands)
12133 && (TARGET_SHIFT1 || optimize_size)"
12135 [(set_attr "type" "rotate")
12136 (set (attr "length")
12137 (if_then_else (match_operand 0 "register_operand" "")
12139 (const_string "*")))])
12141 (define_insn "*rotlqi3_1_one_bit"
12142 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12143 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12144 (match_operand:QI 2 "const_int_1_operand" "")))
12145 (clobber (reg:CC 17))]
12146 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12147 && (TARGET_SHIFT1 || optimize_size)"
12149 [(set_attr "type" "rotate")
12150 (set (attr "length")
12151 (if_then_else (match_operand 0 "register_operand" "")
12153 (const_string "*")))])
12155 (define_insn "*rotlqi3_1_slp"
12156 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12157 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12158 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12159 (clobber (reg:CC 17))]
12160 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12161 && ix86_binary_operator_ok (ROTATE, QImode, operands)"
12163 rol{b}\t{%2, %0|%0, %2}
12164 rol{b}\t{%b2, %0|%0, %b2}"
12165 [(set_attr "type" "rotate")
12166 (set_attr "mode" "QI")])
12168 (define_insn "*rotlqi3_1"
12169 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12170 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12171 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12172 (clobber (reg:CC 17))]
12173 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12175 rol{b}\t{%2, %0|%0, %2}
12176 rol{b}\t{%b2, %0|%0, %b2}"
12177 [(set_attr "type" "rotate")
12178 (set_attr "mode" "QI")])
12180 (define_expand "rotrdi3"
12181 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12182 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12183 (match_operand:QI 2 "nonmemory_operand" "")))
12184 (clobber (reg:CC 17))]
12186 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12188 (define_insn "*rotrdi3_1_one_bit_rex64"
12189 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12190 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12191 (match_operand:QI 2 "const_int_1_operand" "")))
12192 (clobber (reg:CC 17))]
12193 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12194 && (TARGET_SHIFT1 || optimize_size)"
12196 [(set_attr "type" "rotate")
12197 (set (attr "length")
12198 (if_then_else (match_operand:DI 0 "register_operand" "")
12200 (const_string "*")))])
12202 (define_insn "*rotrdi3_1_rex64"
12203 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12204 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12205 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12206 (clobber (reg:CC 17))]
12207 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12209 ror{q}\t{%2, %0|%0, %2}
12210 ror{q}\t{%b2, %0|%0, %b2}"
12211 [(set_attr "type" "rotate")
12212 (set_attr "mode" "DI")])
12214 (define_expand "rotrsi3"
12215 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12216 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12217 (match_operand:QI 2 "nonmemory_operand" "")))
12218 (clobber (reg:CC 17))]
12220 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12222 (define_insn "*rotrsi3_1_one_bit"
12223 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12224 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12225 (match_operand:QI 2 "const_int_1_operand" "")))
12226 (clobber (reg:CC 17))]
12227 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12228 && (TARGET_SHIFT1 || optimize_size)"
12230 [(set_attr "type" "rotate")
12231 (set (attr "length")
12232 (if_then_else (match_operand:SI 0 "register_operand" "")
12234 (const_string "*")))])
12236 (define_insn "*rotrsi3_1_one_bit_zext"
12237 [(set (match_operand:DI 0 "register_operand" "=r")
12239 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12240 (match_operand:QI 2 "const_int_1_operand" ""))))
12241 (clobber (reg:CC 17))]
12242 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12243 && (TARGET_SHIFT1 || optimize_size)"
12245 [(set_attr "type" "rotate")
12246 (set (attr "length")
12247 (if_then_else (match_operand:SI 0 "register_operand" "")
12249 (const_string "*")))])
12251 (define_insn "*rotrsi3_1"
12252 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12253 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12254 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12255 (clobber (reg:CC 17))]
12256 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12258 ror{l}\t{%2, %0|%0, %2}
12259 ror{l}\t{%b2, %0|%0, %b2}"
12260 [(set_attr "type" "rotate")
12261 (set_attr "mode" "SI")])
12263 (define_insn "*rotrsi3_1_zext"
12264 [(set (match_operand:DI 0 "register_operand" "=r,r")
12266 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12267 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12268 (clobber (reg:CC 17))]
12269 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12271 ror{l}\t{%2, %k0|%k0, %2}
12272 ror{l}\t{%b2, %k0|%k0, %b2}"
12273 [(set_attr "type" "rotate")
12274 (set_attr "mode" "SI")])
12276 (define_expand "rotrhi3"
12277 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12278 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12279 (match_operand:QI 2 "nonmemory_operand" "")))
12280 (clobber (reg:CC 17))]
12281 "TARGET_HIMODE_MATH"
12282 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12284 (define_insn "*rotrhi3_one_bit"
12285 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12286 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12287 (match_operand:QI 2 "const_int_1_operand" "")))
12288 (clobber (reg:CC 17))]
12289 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12290 && (TARGET_SHIFT1 || optimize_size)"
12292 [(set_attr "type" "rotate")
12293 (set (attr "length")
12294 (if_then_else (match_operand 0 "register_operand" "")
12296 (const_string "*")))])
12298 (define_insn "*rotrhi3"
12299 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12300 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12301 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12302 (clobber (reg:CC 17))]
12303 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12305 ror{w}\t{%2, %0|%0, %2}
12306 ror{w}\t{%b2, %0|%0, %b2}"
12307 [(set_attr "type" "rotate")
12308 (set_attr "mode" "HI")])
12310 (define_expand "rotrqi3"
12311 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12312 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12313 (match_operand:QI 2 "nonmemory_operand" "")))
12314 (clobber (reg:CC 17))]
12315 "TARGET_QIMODE_MATH"
12316 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12318 (define_insn "*rotrqi3_1_one_bit"
12319 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12320 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12321 (match_operand:QI 2 "const_int_1_operand" "")))
12322 (clobber (reg:CC 17))]
12323 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12324 && (TARGET_SHIFT1 || optimize_size)"
12326 [(set_attr "type" "rotate")
12327 (set (attr "length")
12328 (if_then_else (match_operand 0 "register_operand" "")
12330 (const_string "*")))])
12332 (define_insn "*rotrqi3_1_one_bit_slp"
12333 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12334 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12335 (match_operand:QI 2 "const_int_1_operand" "")))
12336 (clobber (reg:CC 17))]
12337 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12338 && ix86_binary_operator_ok (ROTATERT, QImode, operands)
12339 && (TARGET_SHIFT1 || optimize_size)"
12341 [(set_attr "type" "rotate")
12342 (set (attr "length")
12343 (if_then_else (match_operand 0 "register_operand" "")
12345 (const_string "*")))])
12347 (define_insn "*rotrqi3_1"
12348 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12349 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12350 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12351 (clobber (reg:CC 17))]
12352 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12354 ror{b}\t{%2, %0|%0, %2}
12355 ror{b}\t{%b2, %0|%0, %b2}"
12356 [(set_attr "type" "rotate")
12357 (set_attr "mode" "QI")])
12359 (define_insn "*rotrqi3_1_slp"
12360 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12361 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12362 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12363 (clobber (reg:CC 17))]
12364 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12365 && ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12367 ror{b}\t{%2, %0|%0, %2}
12368 ror{b}\t{%b2, %0|%0, %b2}"
12369 [(set_attr "type" "rotate")
12370 (set_attr "mode" "QI")])
12372 ;; Bit set / bit test instructions
12374 (define_expand "extv"
12375 [(set (match_operand:SI 0 "register_operand" "")
12376 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12377 (match_operand:SI 2 "immediate_operand" "")
12378 (match_operand:SI 3 "immediate_operand" "")))]
12381 /* Handle extractions from %ah et al. */
12382 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12385 /* From mips.md: extract_bit_field doesn't verify that our source
12386 matches the predicate, so check it again here. */
12387 if (! register_operand (operands[1], VOIDmode))
12391 (define_expand "extzv"
12392 [(set (match_operand:SI 0 "register_operand" "")
12393 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12394 (match_operand:SI 2 "immediate_operand" "")
12395 (match_operand:SI 3 "immediate_operand" "")))]
12398 /* Handle extractions from %ah et al. */
12399 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12402 /* From mips.md: extract_bit_field doesn't verify that our source
12403 matches the predicate, so check it again here. */
12404 if (! register_operand (operands[1], VOIDmode))
12408 (define_expand "insv"
12409 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12410 (match_operand:SI 1 "immediate_operand" "")
12411 (match_operand:SI 2 "immediate_operand" ""))
12412 (match_operand:SI 3 "register_operand" ""))]
12415 /* Handle extractions from %ah et al. */
12416 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12419 /* From mips.md: insert_bit_field doesn't verify that our source
12420 matches the predicate, so check it again here. */
12421 if (! register_operand (operands[0], VOIDmode))
12425 ;; %%% bts, btr, btc, bt.
12427 ;; Store-flag instructions.
12429 ;; For all sCOND expanders, also expand the compare or test insn that
12430 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12432 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12433 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12434 ;; way, which can later delete the movzx if only QImode is needed.
12436 (define_expand "seq"
12437 [(set (match_operand:QI 0 "register_operand" "")
12438 (eq:QI (reg:CC 17) (const_int 0)))]
12440 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12442 (define_expand "sne"
12443 [(set (match_operand:QI 0 "register_operand" "")
12444 (ne:QI (reg:CC 17) (const_int 0)))]
12446 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12448 (define_expand "sgt"
12449 [(set (match_operand:QI 0 "register_operand" "")
12450 (gt:QI (reg:CC 17) (const_int 0)))]
12452 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12454 (define_expand "sgtu"
12455 [(set (match_operand:QI 0 "register_operand" "")
12456 (gtu:QI (reg:CC 17) (const_int 0)))]
12458 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12460 (define_expand "slt"
12461 [(set (match_operand:QI 0 "register_operand" "")
12462 (lt:QI (reg:CC 17) (const_int 0)))]
12464 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12466 (define_expand "sltu"
12467 [(set (match_operand:QI 0 "register_operand" "")
12468 (ltu:QI (reg:CC 17) (const_int 0)))]
12470 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12472 (define_expand "sge"
12473 [(set (match_operand:QI 0 "register_operand" "")
12474 (ge:QI (reg:CC 17) (const_int 0)))]
12476 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12478 (define_expand "sgeu"
12479 [(set (match_operand:QI 0 "register_operand" "")
12480 (geu:QI (reg:CC 17) (const_int 0)))]
12482 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12484 (define_expand "sle"
12485 [(set (match_operand:QI 0 "register_operand" "")
12486 (le:QI (reg:CC 17) (const_int 0)))]
12488 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12490 (define_expand "sleu"
12491 [(set (match_operand:QI 0 "register_operand" "")
12492 (leu:QI (reg:CC 17) (const_int 0)))]
12494 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12496 (define_expand "sunordered"
12497 [(set (match_operand:QI 0 "register_operand" "")
12498 (unordered:QI (reg:CC 17) (const_int 0)))]
12499 "TARGET_80387 || TARGET_SSE"
12500 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12502 (define_expand "sordered"
12503 [(set (match_operand:QI 0 "register_operand" "")
12504 (ordered:QI (reg:CC 17) (const_int 0)))]
12506 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12508 (define_expand "suneq"
12509 [(set (match_operand:QI 0 "register_operand" "")
12510 (uneq:QI (reg:CC 17) (const_int 0)))]
12511 "TARGET_80387 || TARGET_SSE"
12512 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12514 (define_expand "sunge"
12515 [(set (match_operand:QI 0 "register_operand" "")
12516 (unge:QI (reg:CC 17) (const_int 0)))]
12517 "TARGET_80387 || TARGET_SSE"
12518 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12520 (define_expand "sungt"
12521 [(set (match_operand:QI 0 "register_operand" "")
12522 (ungt:QI (reg:CC 17) (const_int 0)))]
12523 "TARGET_80387 || TARGET_SSE"
12524 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12526 (define_expand "sunle"
12527 [(set (match_operand:QI 0 "register_operand" "")
12528 (unle:QI (reg:CC 17) (const_int 0)))]
12529 "TARGET_80387 || TARGET_SSE"
12530 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12532 (define_expand "sunlt"
12533 [(set (match_operand:QI 0 "register_operand" "")
12534 (unlt:QI (reg:CC 17) (const_int 0)))]
12535 "TARGET_80387 || TARGET_SSE"
12536 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12538 (define_expand "sltgt"
12539 [(set (match_operand:QI 0 "register_operand" "")
12540 (ltgt:QI (reg:CC 17) (const_int 0)))]
12541 "TARGET_80387 || TARGET_SSE"
12542 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12544 (define_insn "*setcc_1"
12545 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12546 (match_operator:QI 1 "ix86_comparison_operator"
12547 [(reg 17) (const_int 0)]))]
12550 [(set_attr "type" "setcc")
12551 (set_attr "mode" "QI")])
12553 (define_insn "setcc_2"
12554 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12555 (match_operator:QI 1 "ix86_comparison_operator"
12556 [(reg 17) (const_int 0)]))]
12559 [(set_attr "type" "setcc")
12560 (set_attr "mode" "QI")])
12562 ;; In general it is not safe to assume too much about CCmode registers,
12563 ;; so simplify-rtx stops when it sees a second one. Under certain
12564 ;; conditions this is safe on x86, so help combine not create
12571 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12572 (ne:QI (match_operator 1 "ix86_comparison_operator"
12573 [(reg 17) (const_int 0)])
12576 [(set (match_dup 0) (match_dup 1))]
12578 PUT_MODE (operands[1], QImode);
12582 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12583 (ne:QI (match_operator 1 "ix86_comparison_operator"
12584 [(reg 17) (const_int 0)])
12587 [(set (match_dup 0) (match_dup 1))]
12589 PUT_MODE (operands[1], QImode);
12593 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12594 (eq:QI (match_operator 1 "ix86_comparison_operator"
12595 [(reg 17) (const_int 0)])
12598 [(set (match_dup 0) (match_dup 1))]
12600 rtx new_op1 = copy_rtx (operands[1]);
12601 operands[1] = new_op1;
12602 PUT_MODE (new_op1, QImode);
12603 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12604 GET_MODE (XEXP (new_op1, 0))));
12606 /* Make sure that (a) the CCmode we have for the flags is strong
12607 enough for the reversed compare or (b) we have a valid FP compare. */
12608 if (! ix86_comparison_operator (new_op1, VOIDmode))
12613 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12614 (eq:QI (match_operator 1 "ix86_comparison_operator"
12615 [(reg 17) (const_int 0)])
12618 [(set (match_dup 0) (match_dup 1))]
12620 rtx new_op1 = copy_rtx (operands[1]);
12621 operands[1] = new_op1;
12622 PUT_MODE (new_op1, QImode);
12623 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12624 GET_MODE (XEXP (new_op1, 0))));
12626 /* Make sure that (a) the CCmode we have for the flags is strong
12627 enough for the reversed compare or (b) we have a valid FP compare. */
12628 if (! ix86_comparison_operator (new_op1, VOIDmode))
12632 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12633 ;; subsequent logical operations are used to imitate conditional moves.
12634 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12635 ;; it directly. Futher holding this value in pseudo register might bring
12636 ;; problem in implicit normalization in spill code.
12637 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12638 ;; instructions after reload by splitting the conditional move patterns.
12640 (define_insn "*sse_setccsf"
12641 [(set (match_operand:SF 0 "register_operand" "=x")
12642 (match_operator:SF 1 "sse_comparison_operator"
12643 [(match_operand:SF 2 "register_operand" "0")
12644 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12645 "TARGET_SSE && reload_completed"
12646 "cmp%D1ss\t{%3, %0|%0, %3}"
12647 [(set_attr "type" "ssecmp")
12648 (set_attr "mode" "SF")])
12650 (define_insn "*sse_setccdf"
12651 [(set (match_operand:DF 0 "register_operand" "=Y")
12652 (match_operator:DF 1 "sse_comparison_operator"
12653 [(match_operand:DF 2 "register_operand" "0")
12654 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12655 "TARGET_SSE2 && reload_completed"
12656 "cmp%D1sd\t{%3, %0|%0, %3}"
12657 [(set_attr "type" "ssecmp")
12658 (set_attr "mode" "DF")])
12660 ;; Basic conditional jump instructions.
12661 ;; We ignore the overflow flag for signed branch instructions.
12663 ;; For all bCOND expanders, also expand the compare or test insn that
12664 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12666 (define_expand "beq"
12668 (if_then_else (match_dup 1)
12669 (label_ref (match_operand 0 "" ""))
12672 "ix86_expand_branch (EQ, operands[0]); DONE;")
12674 (define_expand "bne"
12676 (if_then_else (match_dup 1)
12677 (label_ref (match_operand 0 "" ""))
12680 "ix86_expand_branch (NE, operands[0]); DONE;")
12682 (define_expand "bgt"
12684 (if_then_else (match_dup 1)
12685 (label_ref (match_operand 0 "" ""))
12688 "ix86_expand_branch (GT, operands[0]); DONE;")
12690 (define_expand "bgtu"
12692 (if_then_else (match_dup 1)
12693 (label_ref (match_operand 0 "" ""))
12696 "ix86_expand_branch (GTU, operands[0]); DONE;")
12698 (define_expand "blt"
12700 (if_then_else (match_dup 1)
12701 (label_ref (match_operand 0 "" ""))
12704 "ix86_expand_branch (LT, operands[0]); DONE;")
12706 (define_expand "bltu"
12708 (if_then_else (match_dup 1)
12709 (label_ref (match_operand 0 "" ""))
12712 "ix86_expand_branch (LTU, operands[0]); DONE;")
12714 (define_expand "bge"
12716 (if_then_else (match_dup 1)
12717 (label_ref (match_operand 0 "" ""))
12720 "ix86_expand_branch (GE, operands[0]); DONE;")
12722 (define_expand "bgeu"
12724 (if_then_else (match_dup 1)
12725 (label_ref (match_operand 0 "" ""))
12728 "ix86_expand_branch (GEU, operands[0]); DONE;")
12730 (define_expand "ble"
12732 (if_then_else (match_dup 1)
12733 (label_ref (match_operand 0 "" ""))
12736 "ix86_expand_branch (LE, operands[0]); DONE;")
12738 (define_expand "bleu"
12740 (if_then_else (match_dup 1)
12741 (label_ref (match_operand 0 "" ""))
12744 "ix86_expand_branch (LEU, operands[0]); DONE;")
12746 (define_expand "bunordered"
12748 (if_then_else (match_dup 1)
12749 (label_ref (match_operand 0 "" ""))
12751 "TARGET_80387 || TARGET_SSE"
12752 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12754 (define_expand "bordered"
12756 (if_then_else (match_dup 1)
12757 (label_ref (match_operand 0 "" ""))
12759 "TARGET_80387 || TARGET_SSE"
12760 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12762 (define_expand "buneq"
12764 (if_then_else (match_dup 1)
12765 (label_ref (match_operand 0 "" ""))
12767 "TARGET_80387 || TARGET_SSE"
12768 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12770 (define_expand "bunge"
12772 (if_then_else (match_dup 1)
12773 (label_ref (match_operand 0 "" ""))
12775 "TARGET_80387 || TARGET_SSE"
12776 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12778 (define_expand "bungt"
12780 (if_then_else (match_dup 1)
12781 (label_ref (match_operand 0 "" ""))
12783 "TARGET_80387 || TARGET_SSE"
12784 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12786 (define_expand "bunle"
12788 (if_then_else (match_dup 1)
12789 (label_ref (match_operand 0 "" ""))
12791 "TARGET_80387 || TARGET_SSE"
12792 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12794 (define_expand "bunlt"
12796 (if_then_else (match_dup 1)
12797 (label_ref (match_operand 0 "" ""))
12799 "TARGET_80387 || TARGET_SSE"
12800 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12802 (define_expand "bltgt"
12804 (if_then_else (match_dup 1)
12805 (label_ref (match_operand 0 "" ""))
12807 "TARGET_80387 || TARGET_SSE"
12808 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12810 (define_insn "*jcc_1"
12812 (if_then_else (match_operator 1 "ix86_comparison_operator"
12813 [(reg 17) (const_int 0)])
12814 (label_ref (match_operand 0 "" ""))
12818 [(set_attr "type" "ibr")
12819 (set_attr "modrm" "0")
12820 (set (attr "prefix_0f")
12821 (if_then_else (and (ge (minus (match_dup 0) (pc))
12823 (lt (minus (match_dup 0) (pc))
12828 (define_insn "*jcc_2"
12830 (if_then_else (match_operator 1 "ix86_comparison_operator"
12831 [(reg 17) (const_int 0)])
12833 (label_ref (match_operand 0 "" ""))))]
12836 [(set_attr "type" "ibr")
12837 (set_attr "modrm" "0")
12838 (set (attr "prefix_0f")
12839 (if_then_else (and (ge (minus (match_dup 0) (pc))
12841 (lt (minus (match_dup 0) (pc))
12846 ;; In general it is not safe to assume too much about CCmode registers,
12847 ;; so simplify-rtx stops when it sees a second one. Under certain
12848 ;; conditions this is safe on x86, so help combine not create
12856 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
12857 [(reg 17) (const_int 0)])
12859 (label_ref (match_operand 1 "" ""))
12863 (if_then_else (match_dup 0)
12864 (label_ref (match_dup 1))
12867 PUT_MODE (operands[0], VOIDmode);
12872 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
12873 [(reg 17) (const_int 0)])
12875 (label_ref (match_operand 1 "" ""))
12879 (if_then_else (match_dup 0)
12880 (label_ref (match_dup 1))
12883 rtx new_op0 = copy_rtx (operands[0]);
12884 operands[0] = new_op0;
12885 PUT_MODE (new_op0, VOIDmode);
12886 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
12887 GET_MODE (XEXP (new_op0, 0))));
12889 /* Make sure that (a) the CCmode we have for the flags is strong
12890 enough for the reversed compare or (b) we have a valid FP compare. */
12891 if (! ix86_comparison_operator (new_op0, VOIDmode))
12895 ;; Define combination compare-and-branch fp compare instructions to use
12896 ;; during early optimization. Splitting the operation apart early makes
12897 ;; for bad code when we want to reverse the operation.
12899 (define_insn "*fp_jcc_1"
12901 (if_then_else (match_operator 0 "comparison_operator"
12902 [(match_operand 1 "register_operand" "f")
12903 (match_operand 2 "register_operand" "f")])
12904 (label_ref (match_operand 3 "" ""))
12906 (clobber (reg:CCFP 18))
12907 (clobber (reg:CCFP 17))]
12908 "TARGET_CMOVE && TARGET_80387
12909 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12910 && FLOAT_MODE_P (GET_MODE (operands[1]))
12911 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12912 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12915 (define_insn "*fp_jcc_1_sse"
12917 (if_then_else (match_operator 0 "comparison_operator"
12918 [(match_operand 1 "register_operand" "f#x,x#f")
12919 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12920 (label_ref (match_operand 3 "" ""))
12922 (clobber (reg:CCFP 18))
12923 (clobber (reg:CCFP 17))]
12925 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12926 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12927 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12930 (define_insn "*fp_jcc_1_sse_only"
12932 (if_then_else (match_operator 0 "comparison_operator"
12933 [(match_operand 1 "register_operand" "x")
12934 (match_operand 2 "nonimmediate_operand" "xm")])
12935 (label_ref (match_operand 3 "" ""))
12937 (clobber (reg:CCFP 18))
12938 (clobber (reg:CCFP 17))]
12939 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12940 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12941 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12944 (define_insn "*fp_jcc_2"
12946 (if_then_else (match_operator 0 "comparison_operator"
12947 [(match_operand 1 "register_operand" "f")
12948 (match_operand 2 "register_operand" "f")])
12950 (label_ref (match_operand 3 "" ""))))
12951 (clobber (reg:CCFP 18))
12952 (clobber (reg:CCFP 17))]
12953 "TARGET_CMOVE && TARGET_80387
12954 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12955 && FLOAT_MODE_P (GET_MODE (operands[1]))
12956 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12957 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12960 (define_insn "*fp_jcc_2_sse"
12962 (if_then_else (match_operator 0 "comparison_operator"
12963 [(match_operand 1 "register_operand" "f#x,x#f")
12964 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12966 (label_ref (match_operand 3 "" ""))))
12967 (clobber (reg:CCFP 18))
12968 (clobber (reg:CCFP 17))]
12970 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12971 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12972 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12975 (define_insn "*fp_jcc_2_sse_only"
12977 (if_then_else (match_operator 0 "comparison_operator"
12978 [(match_operand 1 "register_operand" "x")
12979 (match_operand 2 "nonimmediate_operand" "xm")])
12981 (label_ref (match_operand 3 "" ""))))
12982 (clobber (reg:CCFP 18))
12983 (clobber (reg:CCFP 17))]
12984 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12985 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12986 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12989 (define_insn "*fp_jcc_3"
12991 (if_then_else (match_operator 0 "comparison_operator"
12992 [(match_operand 1 "register_operand" "f")
12993 (match_operand 2 "nonimmediate_operand" "fm")])
12994 (label_ref (match_operand 3 "" ""))
12996 (clobber (reg:CCFP 18))
12997 (clobber (reg:CCFP 17))
12998 (clobber (match_scratch:HI 4 "=a"))]
13000 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13001 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13002 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13003 && SELECT_CC_MODE (GET_CODE (operands[0]),
13004 operands[1], operands[2]) == CCFPmode
13005 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13008 (define_insn "*fp_jcc_4"
13010 (if_then_else (match_operator 0 "comparison_operator"
13011 [(match_operand 1 "register_operand" "f")
13012 (match_operand 2 "nonimmediate_operand" "fm")])
13014 (label_ref (match_operand 3 "" ""))))
13015 (clobber (reg:CCFP 18))
13016 (clobber (reg:CCFP 17))
13017 (clobber (match_scratch:HI 4 "=a"))]
13019 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13020 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13021 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13022 && SELECT_CC_MODE (GET_CODE (operands[0]),
13023 operands[1], operands[2]) == CCFPmode
13024 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13027 (define_insn "*fp_jcc_5"
13029 (if_then_else (match_operator 0 "comparison_operator"
13030 [(match_operand 1 "register_operand" "f")
13031 (match_operand 2 "register_operand" "f")])
13032 (label_ref (match_operand 3 "" ""))
13034 (clobber (reg:CCFP 18))
13035 (clobber (reg:CCFP 17))
13036 (clobber (match_scratch:HI 4 "=a"))]
13038 && FLOAT_MODE_P (GET_MODE (operands[1]))
13039 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13040 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13043 (define_insn "*fp_jcc_6"
13045 (if_then_else (match_operator 0 "comparison_operator"
13046 [(match_operand 1 "register_operand" "f")
13047 (match_operand 2 "register_operand" "f")])
13049 (label_ref (match_operand 3 "" ""))))
13050 (clobber (reg:CCFP 18))
13051 (clobber (reg:CCFP 17))
13052 (clobber (match_scratch:HI 4 "=a"))]
13054 && FLOAT_MODE_P (GET_MODE (operands[1]))
13055 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13056 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13061 (if_then_else (match_operator 0 "comparison_operator"
13062 [(match_operand 1 "register_operand" "")
13063 (match_operand 2 "nonimmediate_operand" "")])
13064 (match_operand 3 "" "")
13065 (match_operand 4 "" "")))
13066 (clobber (reg:CCFP 18))
13067 (clobber (reg:CCFP 17))]
13071 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13072 operands[3], operands[4], NULL_RTX);
13078 (if_then_else (match_operator 0 "comparison_operator"
13079 [(match_operand 1 "register_operand" "")
13080 (match_operand 2 "nonimmediate_operand" "")])
13081 (match_operand 3 "" "")
13082 (match_operand 4 "" "")))
13083 (clobber (reg:CCFP 18))
13084 (clobber (reg:CCFP 17))
13085 (clobber (match_scratch:HI 5 "=a"))]
13088 (if_then_else (match_dup 6)
13092 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13093 operands[3], operands[4], operands[5]);
13097 ;; Unconditional and other jump instructions
13099 (define_insn "jump"
13101 (label_ref (match_operand 0 "" "")))]
13104 [(set_attr "type" "ibr")
13105 (set_attr "modrm" "0")])
13107 (define_expand "indirect_jump"
13108 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13112 (define_insn "*indirect_jump"
13113 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13116 [(set_attr "type" "ibr")
13117 (set_attr "length_immediate" "0")])
13119 (define_insn "*indirect_jump_rtx64"
13120 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13123 [(set_attr "type" "ibr")
13124 (set_attr "length_immediate" "0")])
13126 (define_expand "tablejump"
13127 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13128 (use (label_ref (match_operand 1 "" "")))])]
13131 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13132 relative. Convert the relative address to an absolute address. */
13136 enum rtx_code code;
13142 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13144 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13148 op1 = pic_offset_table_rtx;
13153 op0 = pic_offset_table_rtx;
13157 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13162 (define_insn "*tablejump_1"
13163 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13164 (use (label_ref (match_operand 1 "" "")))]
13167 [(set_attr "type" "ibr")
13168 (set_attr "length_immediate" "0")])
13170 (define_insn "*tablejump_1_rtx64"
13171 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13172 (use (label_ref (match_operand 1 "" "")))]
13175 [(set_attr "type" "ibr")
13176 (set_attr "length_immediate" "0")])
13178 ;; Loop instruction
13180 ;; This is all complicated by the fact that since this is a jump insn
13181 ;; we must handle our own reloads.
13183 (define_expand "doloop_end"
13184 [(use (match_operand 0 "" "")) ; loop pseudo
13185 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13186 (use (match_operand 2 "" "")) ; max iterations
13187 (use (match_operand 3 "" "")) ; loop level
13188 (use (match_operand 4 "" ""))] ; label
13189 "!TARGET_64BIT && TARGET_USE_LOOP"
13192 /* Only use cloop on innermost loops. */
13193 if (INTVAL (operands[3]) > 1)
13195 if (GET_MODE (operands[0]) != SImode)
13197 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13202 (define_insn "doloop_end_internal"
13204 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13206 (label_ref (match_operand 0 "" ""))
13208 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13209 (plus:SI (match_dup 1)
13211 (clobber (match_scratch:SI 3 "=X,X,r"))
13212 (clobber (reg:CC 17))]
13213 "!TARGET_64BIT && TARGET_USE_LOOP"
13215 if (which_alternative != 0)
13217 if (get_attr_length (insn) == 2)
13218 return "%+loop\t%l0";
13220 return "dec{l}\t%1\;%+jne\t%l0";
13222 [(set_attr "ppro_uops" "many")
13223 (set (attr "length")
13224 (if_then_else (and (eq_attr "alternative" "0")
13225 (and (ge (minus (match_dup 0) (pc))
13227 (lt (minus (match_dup 0) (pc))
13232 (if_then_else (and (eq_attr "alternative" "0")
13233 (and (ge (minus (match_dup 0) (pc))
13235 (lt (minus (match_dup 0) (pc))
13237 (const_string "ibr")
13238 (const_string "multi")))])
13242 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13244 (match_operand 0 "" "")
13247 (plus:SI (match_dup 1)
13249 (clobber (match_scratch:SI 2 ""))
13250 (clobber (reg:CC 17))]
13251 "!TARGET_64BIT && TARGET_USE_LOOP
13252 && reload_completed
13253 && REGNO (operands[1]) != 2"
13254 [(parallel [(set (reg:CCZ 17)
13255 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13257 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13258 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13265 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13267 (match_operand 0 "" "")
13269 (set (match_operand:SI 2 "nonimmediate_operand" "")
13270 (plus:SI (match_dup 1)
13272 (clobber (match_scratch:SI 3 ""))
13273 (clobber (reg:CC 17))]
13274 "!TARGET_64BIT && TARGET_USE_LOOP
13275 && reload_completed
13276 && (! REG_P (operands[2])
13277 || ! rtx_equal_p (operands[1], operands[2]))"
13278 [(set (match_dup 3) (match_dup 1))
13279 (parallel [(set (reg:CCZ 17)
13280 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13282 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13283 (set (match_dup 2) (match_dup 3))
13284 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13289 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13292 [(set (reg 17) (match_operand 0 "" ""))
13293 (set (match_operand:QI 1 "register_operand" "")
13294 (match_operator:QI 2 "ix86_comparison_operator"
13295 [(reg 17) (const_int 0)]))
13296 (set (match_operand 3 "q_regs_operand" "")
13297 (zero_extend (match_dup 1)))]
13298 "(peep2_reg_dead_p (3, operands[1])
13299 || operands_match_p (operands[1], operands[3]))
13300 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13301 [(set (match_dup 4) (match_dup 0))
13302 (set (strict_low_part (match_dup 5))
13305 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13306 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
13307 ix86_expand_clear (operands[3]);
13310 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13313 [(set (reg 17) (match_operand 0 "" ""))
13314 (set (match_operand:QI 1 "register_operand" "")
13315 (match_operator:QI 2 "ix86_comparison_operator"
13316 [(reg 17) (const_int 0)]))
13317 (parallel [(set (match_operand 3 "q_regs_operand" "")
13318 (zero_extend (match_dup 1)))
13319 (clobber (reg:CC 17))])]
13320 "(peep2_reg_dead_p (3, operands[1])
13321 || operands_match_p (operands[1], operands[3]))
13322 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13323 [(set (match_dup 4) (match_dup 0))
13324 (set (strict_low_part (match_dup 5))
13327 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13328 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
13329 ix86_expand_clear (operands[3]);
13332 ;; Call instructions.
13334 ;; The predicates normally associated with named expanders are not properly
13335 ;; checked for calls. This is a bug in the generic code, but it isn't that
13336 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13338 ;; Call subroutine returning no value.
13340 (define_expand "call_pop"
13341 [(parallel [(call (match_operand:QI 0 "" "")
13342 (match_operand:SI 1 "" ""))
13344 (plus:SI (reg:SI 7)
13345 (match_operand:SI 3 "" "")))])]
13348 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3]);
13352 (define_insn "*call_pop_0"
13353 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13354 (match_operand:SI 1 "" ""))
13355 (set (reg:SI 7) (plus:SI (reg:SI 7)
13356 (match_operand:SI 2 "immediate_operand" "")))]
13359 if (SIBLING_CALL_P (insn))
13362 return "call\t%P0";
13364 [(set_attr "type" "call")])
13366 (define_insn "*call_pop_1"
13367 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13368 (match_operand:SI 1 "" ""))
13369 (set (reg:SI 7) (plus:SI (reg:SI 7)
13370 (match_operand:SI 2 "immediate_operand" "i")))]
13373 if (constant_call_address_operand (operands[0], Pmode))
13375 if (SIBLING_CALL_P (insn))
13378 return "call\t%P0";
13380 if (SIBLING_CALL_P (insn))
13383 return "call\t%A0";
13385 [(set_attr "type" "call")])
13387 (define_expand "call"
13388 [(call (match_operand:QI 0 "" "")
13389 (match_operand 1 "" ""))
13390 (use (match_operand 2 "" ""))]
13393 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL);
13397 (define_insn "*call_0"
13398 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13399 (match_operand 1 "" ""))]
13402 if (SIBLING_CALL_P (insn))
13405 return "call\t%P0";
13407 [(set_attr "type" "call")])
13409 (define_insn "*call_1"
13410 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13411 (match_operand 1 "" ""))]
13414 if (constant_call_address_operand (operands[0], QImode))
13416 if (SIBLING_CALL_P (insn))
13419 return "call\t%P0";
13421 if (SIBLING_CALL_P (insn))
13424 return "call\t%A0";
13426 [(set_attr "type" "call")])
13428 (define_insn "*call_1_rex64"
13429 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13430 (match_operand 1 "" ""))]
13433 if (constant_call_address_operand (operands[0], QImode))
13435 if (SIBLING_CALL_P (insn))
13438 return "call\t%P0";
13440 if (SIBLING_CALL_P (insn))
13443 return "call\t%A0";
13445 [(set_attr "type" "call")])
13447 ;; Call subroutine, returning value in operand 0
13449 (define_expand "call_value_pop"
13450 [(parallel [(set (match_operand 0 "" "")
13451 (call (match_operand:QI 1 "" "")
13452 (match_operand:SI 2 "" "")))
13454 (plus:SI (reg:SI 7)
13455 (match_operand:SI 4 "" "")))])]
13458 ix86_expand_call (operands[0], operands[1], operands[2],
13459 operands[3], operands[4]);
13463 (define_expand "call_value"
13464 [(set (match_operand 0 "" "")
13465 (call (match_operand:QI 1 "" "")
13466 (match_operand:SI 2 "" "")))
13467 (use (match_operand:SI 3 "" ""))]
13468 ;; Operand 2 not used on the i386.
13471 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL);
13475 ;; Call subroutine returning any type.
13477 (define_expand "untyped_call"
13478 [(parallel [(call (match_operand 0 "" "")
13480 (match_operand 1 "" "")
13481 (match_operand 2 "" "")])]
13486 /* In order to give reg-stack an easier job in validating two
13487 coprocessor registers as containing a possible return value,
13488 simply pretend the untyped call returns a complex long double
13491 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13492 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13493 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13496 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13498 rtx set = XVECEXP (operands[2], 0, i);
13499 emit_move_insn (SET_DEST (set), SET_SRC (set));
13502 /* The optimizer does not know that the call sets the function value
13503 registers we stored in the result block. We avoid problems by
13504 claiming that all hard registers are used and clobbered at this
13506 emit_insn (gen_blockage (const0_rtx));
13511 ;; Prologue and epilogue instructions
13513 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13514 ;; all of memory. This blocks insns from being moved across this point.
13516 (define_insn "blockage"
13517 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13520 [(set_attr "length" "0")])
13522 ;; Insn emitted into the body of a function to return from a function.
13523 ;; This is only done if the function's epilogue is known to be simple.
13524 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13526 (define_expand "return"
13528 "ix86_can_use_return_insn_p ()"
13530 if (current_function_pops_args)
13532 rtx popc = GEN_INT (current_function_pops_args);
13533 emit_jump_insn (gen_return_pop_internal (popc));
13538 (define_insn "return_internal"
13542 [(set_attr "length" "1")
13543 (set_attr "length_immediate" "0")
13544 (set_attr "modrm" "0")])
13546 (define_insn "return_pop_internal"
13548 (use (match_operand:SI 0 "const_int_operand" ""))]
13551 [(set_attr "length" "3")
13552 (set_attr "length_immediate" "2")
13553 (set_attr "modrm" "0")])
13555 (define_insn "return_indirect_internal"
13557 (use (match_operand:SI 0 "register_operand" "r"))]
13560 [(set_attr "type" "ibr")
13561 (set_attr "length_immediate" "0")])
13567 [(set_attr "length" "1")
13568 (set_attr "length_immediate" "0")
13569 (set_attr "modrm" "0")
13570 (set_attr "ppro_uops" "one")])
13572 (define_expand "prologue"
13575 "ix86_expand_prologue (); DONE;")
13577 (define_insn "set_got"
13578 [(set (match_operand:SI 0 "register_operand" "=r")
13579 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13580 (clobber (reg:CC 17))]
13582 { return output_set_got (operands[0]); }
13583 [(set_attr "type" "multi")
13584 (set_attr "length" "12")])
13586 (define_expand "epilogue"
13589 "ix86_expand_epilogue (1); DONE;")
13591 (define_expand "sibcall_epilogue"
13594 "ix86_expand_epilogue (0); DONE;")
13596 (define_expand "eh_return"
13597 [(use (match_operand 0 "register_operand" ""))
13598 (use (match_operand 1 "register_operand" ""))]
13601 rtx tmp, sa = operands[0], ra = operands[1];
13603 /* Tricky bit: we write the address of the handler to which we will
13604 be returning into someone else's stack frame, one word below the
13605 stack address we wish to restore. */
13606 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13607 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13608 tmp = gen_rtx_MEM (Pmode, tmp);
13609 emit_move_insn (tmp, ra);
13611 if (Pmode == SImode)
13612 emit_insn (gen_eh_return_si (sa));
13614 emit_insn (gen_eh_return_di (sa));
13619 (define_insn_and_split "eh_return_si"
13620 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
13621 UNSPECV_EH_RETURN)]
13626 "ix86_expand_epilogue (2); DONE;")
13628 (define_insn_and_split "eh_return_di"
13629 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
13630 UNSPECV_EH_RETURN)]
13635 "ix86_expand_epilogue (2); DONE;")
13637 (define_insn "leave"
13638 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
13639 (set (reg:SI 6) (mem:SI (reg:SI 6)))
13640 (clobber (mem:BLK (scratch)))]
13643 [(set_attr "length_immediate" "0")
13644 (set_attr "length" "1")
13645 (set_attr "modrm" "0")
13646 (set_attr "athlon_decode" "vector")
13647 (set_attr "ppro_uops" "few")])
13649 (define_insn "leave_rex64"
13650 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
13651 (set (reg:DI 6) (mem:DI (reg:DI 6)))
13652 (clobber (mem:BLK (scratch)))]
13655 [(set_attr "length_immediate" "0")
13656 (set_attr "length" "1")
13657 (set_attr "modrm" "0")
13658 (set_attr "athlon_decode" "vector")
13659 (set_attr "ppro_uops" "few")])
13661 (define_expand "ffssi2"
13662 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13663 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13666 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13667 rtx in = operands[1];
13671 emit_move_insn (tmp, constm1_rtx);
13672 emit_insn (gen_ffssi_1 (out, in));
13673 emit_insn (gen_rtx_SET (VOIDmode, out,
13674 gen_rtx_IF_THEN_ELSE (SImode,
13675 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13679 emit_insn (gen_addsi3 (out, out, const1_rtx));
13680 emit_move_insn (operands[0], out);
13683 /* Pentium bsf instruction is extremly slow. The following code is
13684 recommended by the Intel Optimizing Manual as a reasonable replacement:
13688 MOV DWORD PTR [TEMP+4],ECX
13691 MOV DWORD PTR [TEMP],EAX
13692 FILD QWORD PTR [TEMP]
13693 FSTP QWORD PTR [TEMP]
13694 WAIT ; WAIT only needed for compatibility with
13695 ; earlier processors
13696 MOV ECX, DWORD PTR [TEMP+4]
13699 TEST EAX,EAX ; clear zero flag
13701 Following piece of code expand ffs to similar beast.
13704 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13706 rtx label = gen_label_rtx ();
13708 rtx mem = assign_386_stack_local (DImode, 0);
13709 rtx fptmp = gen_reg_rtx (DFmode);
13710 split_di (&mem, 1, &lo, &hi);
13712 emit_move_insn (out, const0_rtx);
13714 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label);
13716 emit_move_insn (hi, out);
13717 emit_insn (gen_subsi3 (out, out, in));
13718 emit_insn (gen_andsi3 (out, out, in));
13719 emit_move_insn (lo, out);
13720 emit_insn (gen_floatdidf2 (fptmp,mem));
13721 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13722 emit_move_insn (out, hi);
13723 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13724 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13726 emit_label (label);
13727 LABEL_NUSES (label) = 1;
13729 emit_move_insn (operands[0], out);
13733 emit_move_insn (tmp, const0_rtx);
13734 emit_insn (gen_ffssi_1 (out, in));
13735 emit_insn (gen_rtx_SET (VOIDmode,
13736 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13737 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13739 emit_insn (gen_negsi2 (tmp, tmp));
13740 emit_insn (gen_iorsi3 (out, out, tmp));
13741 emit_insn (gen_addsi3 (out, out, const1_rtx));
13742 emit_move_insn (operands[0], out);
13747 (define_insn "ffssi_1"
13749 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13751 (set (match_operand:SI 0 "register_operand" "=r")
13752 (unspec:SI [(match_dup 1)] UNSPEC_BSF))]
13754 "bsf{l}\t{%1, %0|%0, %1}"
13755 [(set_attr "prefix_0f" "1")
13756 (set_attr "ppro_uops" "few")])
13758 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13759 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13761 ;; Thread-local storage patterns for ELF.
13763 ;; Note that these code sequences must appear exactly as shown
13764 ;; in order to allow linker relaxation.
13766 (define_insn "*tls_global_dynamic_gnu"
13767 [(set (match_operand:SI 0 "register_operand" "=a")
13768 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13769 (match_operand:SI 2 "tls_symbolic_operand" "")
13770 (match_operand:SI 3 "call_insn_operand" "")]
13772 (clobber (match_scratch:SI 4 "=d"))
13773 (clobber (match_scratch:SI 5 "=c"))
13774 (clobber (reg:CC 17))]
13776 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
13777 [(set_attr "type" "multi")
13778 (set_attr "length" "12")])
13780 (define_insn "*tls_global_dynamic_sun"
13781 [(set (match_operand:SI 0 "register_operand" "=a")
13782 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13783 (match_operand:SI 2 "tls_symbolic_operand" "")
13784 (match_operand:SI 3 "call_insn_operand" "")]
13786 (clobber (match_scratch:SI 4 "=d"))
13787 (clobber (match_scratch:SI 5 "=c"))
13788 (clobber (reg:CC 17))]
13790 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
13791 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
13792 [(set_attr "type" "multi")
13793 (set_attr "length" "14")])
13795 (define_expand "tls_global_dynamic"
13796 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13799 (match_operand:SI 1 "tls_symbolic_operand" "")
13802 (clobber (match_scratch:SI 4 ""))
13803 (clobber (match_scratch:SI 5 ""))
13804 (clobber (reg:CC 17))])]
13809 operands[2] = pic_offset_table_rtx;
13810 operands[3] = ix86_tls_get_addr ();
13813 (define_insn "*tls_local_dynamic_base_gnu"
13814 [(set (match_operand:SI 0 "register_operand" "=a")
13815 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13816 (match_operand:SI 2 "call_insn_operand" "")]
13817 UNSPEC_TLS_LD_BASE))
13818 (clobber (match_scratch:SI 3 "=d"))
13819 (clobber (match_scratch:SI 4 "=c"))
13820 (clobber (reg:CC 17))]
13822 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
13823 [(set_attr "type" "multi")
13824 (set_attr "length" "11")])
13826 (define_insn "*tls_local_dynamic_base_sun"
13827 [(set (match_operand:SI 0 "register_operand" "=a")
13828 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13829 (match_operand:SI 2 "call_insn_operand" "")]
13830 UNSPEC_TLS_LD_BASE))
13831 (clobber (match_scratch:SI 3 "=d"))
13832 (clobber (match_scratch:SI 4 "=c"))
13833 (clobber (reg:CC 17))]
13835 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
13836 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
13837 [(set_attr "type" "multi")
13838 (set_attr "length" "13")])
13840 (define_expand "tls_local_dynamic_base"
13841 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13842 (unspec:SI [(match_dup 1) (match_dup 2)]
13843 UNSPEC_TLS_LD_BASE))
13844 (clobber (match_scratch:SI 3 ""))
13845 (clobber (match_scratch:SI 4 ""))
13846 (clobber (reg:CC 17))])]
13851 operands[1] = pic_offset_table_rtx;
13852 operands[2] = ix86_tls_get_addr ();
13855 ;; Local dynamic of a single variable is a lose. Show combine how
13856 ;; to convert that back to global dynamic.
13858 (define_insn_and_split "*tls_local_dynamic_once"
13859 [(set (match_operand:SI 0 "register_operand" "=a")
13860 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13861 (match_operand:SI 2 "call_insn_operand" "")]
13862 UNSPEC_TLS_LD_BASE)
13863 (const:SI (unspec:SI
13864 [(match_operand:SI 3 "tls_symbolic_operand" "")]
13866 (clobber (match_scratch:SI 4 "=d"))
13867 (clobber (match_scratch:SI 5 "=c"))
13868 (clobber (reg:CC 17))]
13872 [(parallel [(set (match_dup 0)
13873 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
13875 (clobber (match_dup 4))
13876 (clobber (match_dup 5))
13877 (clobber (reg:CC 17))])]
13880 ;; These patterns match the binary 387 instructions for addM3, subM3,
13881 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13882 ;; SFmode. The first is the normal insn, the second the same insn but
13883 ;; with one operand a conversion, and the third the same insn but with
13884 ;; the other operand a conversion. The conversion may be SFmode or
13885 ;; SImode if the target mode DFmode, but only SImode if the target mode
13888 ;; Gcc is slightly more smart about handling normal two address instructions
13889 ;; so use special patterns for add and mull.
13890 (define_insn "*fop_sf_comm_nosse"
13891 [(set (match_operand:SF 0 "register_operand" "=f")
13892 (match_operator:SF 3 "binary_fp_operator"
13893 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13894 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
13895 "TARGET_80387 && !TARGET_SSE_MATH
13896 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13897 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13898 "* return output_387_binary_op (insn, operands);"
13899 [(set (attr "type")
13900 (if_then_else (match_operand:SF 3 "mult_operator" "")
13901 (const_string "fmul")
13902 (const_string "fop")))
13903 (set_attr "mode" "SF")])
13905 (define_insn "*fop_sf_comm"
13906 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13907 (match_operator:SF 3 "binary_fp_operator"
13908 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
13909 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13910 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13911 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13912 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13913 "* return output_387_binary_op (insn, operands);"
13914 [(set (attr "type")
13915 (if_then_else (eq_attr "alternative" "1")
13916 (if_then_else (match_operand:SF 3 "mult_operator" "")
13917 (const_string "ssemul")
13918 (const_string "sseadd"))
13919 (if_then_else (match_operand:SF 3 "mult_operator" "")
13920 (const_string "fmul")
13921 (const_string "fop"))))
13922 (set_attr "mode" "SF")])
13924 (define_insn "*fop_sf_comm_sse"
13925 [(set (match_operand:SF 0 "register_operand" "=x")
13926 (match_operator:SF 3 "binary_fp_operator"
13927 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13928 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13929 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13930 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13931 "* return output_387_binary_op (insn, operands);"
13932 [(set (attr "type")
13933 (if_then_else (match_operand:SF 3 "mult_operator" "")
13934 (const_string "ssemul")
13935 (const_string "sseadd")))
13936 (set_attr "mode" "SF")])
13938 (define_insn "*fop_df_comm_nosse"
13939 [(set (match_operand:DF 0 "register_operand" "=f")
13940 (match_operator:DF 3 "binary_fp_operator"
13941 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13942 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
13943 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
13944 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13945 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13946 "* return output_387_binary_op (insn, operands);"
13947 [(set (attr "type")
13948 (if_then_else (match_operand:SF 3 "mult_operator" "")
13949 (const_string "fmul")
13950 (const_string "fop")))
13951 (set_attr "mode" "DF")])
13953 (define_insn "*fop_df_comm"
13954 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13955 (match_operator:DF 3 "binary_fp_operator"
13956 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
13957 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13958 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
13959 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13960 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13961 "* return output_387_binary_op (insn, operands);"
13962 [(set (attr "type")
13963 (if_then_else (eq_attr "alternative" "1")
13964 (if_then_else (match_operand:SF 3 "mult_operator" "")
13965 (const_string "ssemul")
13966 (const_string "sseadd"))
13967 (if_then_else (match_operand:SF 3 "mult_operator" "")
13968 (const_string "fmul")
13969 (const_string "fop"))))
13970 (set_attr "mode" "DF")])
13972 (define_insn "*fop_df_comm_sse"
13973 [(set (match_operand:DF 0 "register_operand" "=Y")
13974 (match_operator:DF 3 "binary_fp_operator"
13975 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13976 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13977 "TARGET_SSE2 && TARGET_SSE_MATH
13978 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13979 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13980 "* return output_387_binary_op (insn, operands);"
13981 [(set (attr "type")
13982 (if_then_else (match_operand:SF 3 "mult_operator" "")
13983 (const_string "ssemul")
13984 (const_string "sseadd")))
13985 (set_attr "mode" "DF")])
13987 (define_insn "*fop_xf_comm"
13988 [(set (match_operand:XF 0 "register_operand" "=f")
13989 (match_operator:XF 3 "binary_fp_operator"
13990 [(match_operand:XF 1 "register_operand" "%0")
13991 (match_operand:XF 2 "register_operand" "f")]))]
13992 "!TARGET_64BIT && TARGET_80387
13993 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13994 "* return output_387_binary_op (insn, operands);"
13995 [(set (attr "type")
13996 (if_then_else (match_operand:XF 3 "mult_operator" "")
13997 (const_string "fmul")
13998 (const_string "fop")))
13999 (set_attr "mode" "XF")])
14001 (define_insn "*fop_tf_comm"
14002 [(set (match_operand:TF 0 "register_operand" "=f")
14003 (match_operator:TF 3 "binary_fp_operator"
14004 [(match_operand:TF 1 "register_operand" "%0")
14005 (match_operand:TF 2 "register_operand" "f")]))]
14006 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14007 "* return output_387_binary_op (insn, operands);"
14008 [(set (attr "type")
14009 (if_then_else (match_operand:TF 3 "mult_operator" "")
14010 (const_string "fmul")
14011 (const_string "fop")))
14012 (set_attr "mode" "XF")])
14014 (define_insn "*fop_sf_1_nosse"
14015 [(set (match_operand:SF 0 "register_operand" "=f,f")
14016 (match_operator:SF 3 "binary_fp_operator"
14017 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14018 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14019 "TARGET_80387 && !TARGET_SSE_MATH
14020 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14021 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14022 "* return output_387_binary_op (insn, operands);"
14023 [(set (attr "type")
14024 (cond [(match_operand:SF 3 "mult_operator" "")
14025 (const_string "fmul")
14026 (match_operand:SF 3 "div_operator" "")
14027 (const_string "fdiv")
14029 (const_string "fop")))
14030 (set_attr "mode" "SF")])
14032 (define_insn "*fop_sf_1"
14033 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14034 (match_operator:SF 3 "binary_fp_operator"
14035 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14036 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14037 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14038 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14039 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14040 "* return output_387_binary_op (insn, operands);"
14041 [(set (attr "type")
14042 (cond [(and (eq_attr "alternative" "2")
14043 (match_operand:SF 3 "mult_operator" ""))
14044 (const_string "ssemul")
14045 (and (eq_attr "alternative" "2")
14046 (match_operand:SF 3 "div_operator" ""))
14047 (const_string "ssediv")
14048 (eq_attr "alternative" "2")
14049 (const_string "sseadd")
14050 (match_operand:SF 3 "mult_operator" "")
14051 (const_string "fmul")
14052 (match_operand:SF 3 "div_operator" "")
14053 (const_string "fdiv")
14055 (const_string "fop")))
14056 (set_attr "mode" "SF")])
14058 (define_insn "*fop_sf_1_sse"
14059 [(set (match_operand:SF 0 "register_operand" "=x")
14060 (match_operator:SF 3 "binary_fp_operator"
14061 [(match_operand:SF 1 "register_operand" "0")
14062 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14064 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14065 "* return output_387_binary_op (insn, operands);"
14066 [(set (attr "type")
14067 (cond [(match_operand:SF 3 "mult_operator" "")
14068 (const_string "ssemul")
14069 (match_operand:SF 3 "div_operator" "")
14070 (const_string "ssediv")
14072 (const_string "sseadd")))
14073 (set_attr "mode" "SF")])
14075 ;; ??? Add SSE splitters for these!
14076 (define_insn "*fop_sf_2"
14077 [(set (match_operand:SF 0 "register_operand" "=f,f")
14078 (match_operator:SF 3 "binary_fp_operator"
14079 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14080 (match_operand:SF 2 "register_operand" "0,0")]))]
14081 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14082 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14083 [(set (attr "type")
14084 (cond [(match_operand:SF 3 "mult_operator" "")
14085 (const_string "fmul")
14086 (match_operand:SF 3 "div_operator" "")
14087 (const_string "fdiv")
14089 (const_string "fop")))
14090 (set_attr "fp_int_src" "true")
14091 (set_attr "ppro_uops" "many")
14092 (set_attr "mode" "SI")])
14094 (define_insn "*fop_sf_3"
14095 [(set (match_operand:SF 0 "register_operand" "=f,f")
14096 (match_operator:SF 3 "binary_fp_operator"
14097 [(match_operand:SF 1 "register_operand" "0,0")
14098 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14099 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14100 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14101 [(set (attr "type")
14102 (cond [(match_operand:SF 3 "mult_operator" "")
14103 (const_string "fmul")
14104 (match_operand:SF 3 "div_operator" "")
14105 (const_string "fdiv")
14107 (const_string "fop")))
14108 (set_attr "fp_int_src" "true")
14109 (set_attr "ppro_uops" "many")
14110 (set_attr "mode" "SI")])
14112 (define_insn "*fop_df_1_nosse"
14113 [(set (match_operand:DF 0 "register_operand" "=f,f")
14114 (match_operator:DF 3 "binary_fp_operator"
14115 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14116 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14117 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14118 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14119 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14120 "* return output_387_binary_op (insn, operands);"
14121 [(set (attr "type")
14122 (cond [(match_operand:DF 3 "mult_operator" "")
14123 (const_string "fmul")
14124 (match_operand:DF 3 "div_operator" "")
14125 (const_string "fdiv")
14127 (const_string "fop")))
14128 (set_attr "mode" "DF")])
14131 (define_insn "*fop_df_1"
14132 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14133 (match_operator:DF 3 "binary_fp_operator"
14134 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14135 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14136 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14137 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14138 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14139 "* return output_387_binary_op (insn, operands);"
14140 [(set (attr "type")
14141 (cond [(and (eq_attr "alternative" "2")
14142 (match_operand:SF 3 "mult_operator" ""))
14143 (const_string "ssemul")
14144 (and (eq_attr "alternative" "2")
14145 (match_operand:SF 3 "div_operator" ""))
14146 (const_string "ssediv")
14147 (eq_attr "alternative" "2")
14148 (const_string "sseadd")
14149 (match_operand:DF 3 "mult_operator" "")
14150 (const_string "fmul")
14151 (match_operand:DF 3 "div_operator" "")
14152 (const_string "fdiv")
14154 (const_string "fop")))
14155 (set_attr "mode" "DF")])
14157 (define_insn "*fop_df_1_sse"
14158 [(set (match_operand:DF 0 "register_operand" "=Y")
14159 (match_operator:DF 3 "binary_fp_operator"
14160 [(match_operand:DF 1 "register_operand" "0")
14161 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14162 "TARGET_SSE2 && TARGET_SSE_MATH
14163 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14164 "* return output_387_binary_op (insn, operands);"
14165 [(set_attr "mode" "DF")
14167 (cond [(match_operand:SF 3 "mult_operator" "")
14168 (const_string "ssemul")
14169 (match_operand:SF 3 "div_operator" "")
14170 (const_string "ssediv")
14172 (const_string "sseadd")))])
14174 ;; ??? Add SSE splitters for these!
14175 (define_insn "*fop_df_2"
14176 [(set (match_operand:DF 0 "register_operand" "=f,f")
14177 (match_operator:DF 3 "binary_fp_operator"
14178 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14179 (match_operand:DF 2 "register_operand" "0,0")]))]
14180 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14181 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14182 [(set (attr "type")
14183 (cond [(match_operand:DF 3 "mult_operator" "")
14184 (const_string "fmul")
14185 (match_operand:DF 3 "div_operator" "")
14186 (const_string "fdiv")
14188 (const_string "fop")))
14189 (set_attr "fp_int_src" "true")
14190 (set_attr "ppro_uops" "many")
14191 (set_attr "mode" "SI")])
14193 (define_insn "*fop_df_3"
14194 [(set (match_operand:DF 0 "register_operand" "=f,f")
14195 (match_operator:DF 3 "binary_fp_operator"
14196 [(match_operand:DF 1 "register_operand" "0,0")
14197 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14198 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14199 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14200 [(set (attr "type")
14201 (cond [(match_operand:DF 3 "mult_operator" "")
14202 (const_string "fmul")
14203 (match_operand:DF 3 "div_operator" "")
14204 (const_string "fdiv")
14206 (const_string "fop")))
14207 (set_attr "fp_int_src" "true")
14208 (set_attr "ppro_uops" "many")
14209 (set_attr "mode" "SI")])
14211 (define_insn "*fop_df_4"
14212 [(set (match_operand:DF 0 "register_operand" "=f,f")
14213 (match_operator:DF 3 "binary_fp_operator"
14214 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14215 (match_operand:DF 2 "register_operand" "0,f")]))]
14216 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14217 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14218 "* return output_387_binary_op (insn, operands);"
14219 [(set (attr "type")
14220 (cond [(match_operand:DF 3 "mult_operator" "")
14221 (const_string "fmul")
14222 (match_operand:DF 3 "div_operator" "")
14223 (const_string "fdiv")
14225 (const_string "fop")))
14226 (set_attr "mode" "SF")])
14228 (define_insn "*fop_df_5"
14229 [(set (match_operand:DF 0 "register_operand" "=f,f")
14230 (match_operator:DF 3 "binary_fp_operator"
14231 [(match_operand:DF 1 "register_operand" "0,f")
14233 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14234 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14235 "* return output_387_binary_op (insn, operands);"
14236 [(set (attr "type")
14237 (cond [(match_operand:DF 3 "mult_operator" "")
14238 (const_string "fmul")
14239 (match_operand:DF 3 "div_operator" "")
14240 (const_string "fdiv")
14242 (const_string "fop")))
14243 (set_attr "mode" "SF")])
14245 (define_insn "*fop_xf_1"
14246 [(set (match_operand:XF 0 "register_operand" "=f,f")
14247 (match_operator:XF 3 "binary_fp_operator"
14248 [(match_operand:XF 1 "register_operand" "0,f")
14249 (match_operand:XF 2 "register_operand" "f,0")]))]
14250 "!TARGET_64BIT && TARGET_80387
14251 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14252 "* return output_387_binary_op (insn, operands);"
14253 [(set (attr "type")
14254 (cond [(match_operand:XF 3 "mult_operator" "")
14255 (const_string "fmul")
14256 (match_operand:XF 3 "div_operator" "")
14257 (const_string "fdiv")
14259 (const_string "fop")))
14260 (set_attr "mode" "XF")])
14262 (define_insn "*fop_tf_1"
14263 [(set (match_operand:TF 0 "register_operand" "=f,f")
14264 (match_operator:TF 3 "binary_fp_operator"
14265 [(match_operand:TF 1 "register_operand" "0,f")
14266 (match_operand:TF 2 "register_operand" "f,0")]))]
14268 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14269 "* return output_387_binary_op (insn, operands);"
14270 [(set (attr "type")
14271 (cond [(match_operand:TF 3 "mult_operator" "")
14272 (const_string "fmul")
14273 (match_operand:TF 3 "div_operator" "")
14274 (const_string "fdiv")
14276 (const_string "fop")))
14277 (set_attr "mode" "XF")])
14279 (define_insn "*fop_xf_2"
14280 [(set (match_operand:XF 0 "register_operand" "=f,f")
14281 (match_operator:XF 3 "binary_fp_operator"
14282 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14283 (match_operand:XF 2 "register_operand" "0,0")]))]
14284 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
14285 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14286 [(set (attr "type")
14287 (cond [(match_operand:XF 3 "mult_operator" "")
14288 (const_string "fmul")
14289 (match_operand:XF 3 "div_operator" "")
14290 (const_string "fdiv")
14292 (const_string "fop")))
14293 (set_attr "fp_int_src" "true")
14294 (set_attr "mode" "SI")
14295 (set_attr "ppro_uops" "many")])
14297 (define_insn "*fop_tf_2"
14298 [(set (match_operand:TF 0 "register_operand" "=f,f")
14299 (match_operator:TF 3 "binary_fp_operator"
14300 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14301 (match_operand:TF 2 "register_operand" "0,0")]))]
14302 "TARGET_80387 && TARGET_USE_FIOP"
14303 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14304 [(set (attr "type")
14305 (cond [(match_operand:TF 3 "mult_operator" "")
14306 (const_string "fmul")
14307 (match_operand:TF 3 "div_operator" "")
14308 (const_string "fdiv")
14310 (const_string "fop")))
14311 (set_attr "fp_int_src" "true")
14312 (set_attr "mode" "SI")
14313 (set_attr "ppro_uops" "many")])
14315 (define_insn "*fop_xf_3"
14316 [(set (match_operand:XF 0 "register_operand" "=f,f")
14317 (match_operator:XF 3 "binary_fp_operator"
14318 [(match_operand:XF 1 "register_operand" "0,0")
14319 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14320 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
14321 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14322 [(set (attr "type")
14323 (cond [(match_operand:XF 3 "mult_operator" "")
14324 (const_string "fmul")
14325 (match_operand:XF 3 "div_operator" "")
14326 (const_string "fdiv")
14328 (const_string "fop")))
14329 (set_attr "fp_int_src" "true")
14330 (set_attr "mode" "SI")
14331 (set_attr "ppro_uops" "many")])
14333 (define_insn "*fop_tf_3"
14334 [(set (match_operand:TF 0 "register_operand" "=f,f")
14335 (match_operator:TF 3 "binary_fp_operator"
14336 [(match_operand:TF 1 "register_operand" "0,0")
14337 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14338 "TARGET_80387 && TARGET_USE_FIOP"
14339 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14340 [(set (attr "type")
14341 (cond [(match_operand:TF 3 "mult_operator" "")
14342 (const_string "fmul")
14343 (match_operand:TF 3 "div_operator" "")
14344 (const_string "fdiv")
14346 (const_string "fop")))
14347 (set_attr "fp_int_src" "true")
14348 (set_attr "mode" "SI")
14349 (set_attr "ppro_uops" "many")])
14351 (define_insn "*fop_xf_4"
14352 [(set (match_operand:XF 0 "register_operand" "=f,f")
14353 (match_operator:XF 3 "binary_fp_operator"
14354 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14355 (match_operand:XF 2 "register_operand" "0,f")]))]
14356 "!TARGET_64BIT && TARGET_80387"
14357 "* return output_387_binary_op (insn, operands);"
14358 [(set (attr "type")
14359 (cond [(match_operand:XF 3 "mult_operator" "")
14360 (const_string "fmul")
14361 (match_operand:XF 3 "div_operator" "")
14362 (const_string "fdiv")
14364 (const_string "fop")))
14365 (set_attr "mode" "SF")])
14367 (define_insn "*fop_tf_4"
14368 [(set (match_operand:TF 0 "register_operand" "=f,f")
14369 (match_operator:TF 3 "binary_fp_operator"
14370 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14371 (match_operand:TF 2 "register_operand" "0,f")]))]
14373 "* return output_387_binary_op (insn, operands);"
14374 [(set (attr "type")
14375 (cond [(match_operand:TF 3 "mult_operator" "")
14376 (const_string "fmul")
14377 (match_operand:TF 3 "div_operator" "")
14378 (const_string "fdiv")
14380 (const_string "fop")))
14381 (set_attr "mode" "SF")])
14383 (define_insn "*fop_xf_5"
14384 [(set (match_operand:XF 0 "register_operand" "=f,f")
14385 (match_operator:XF 3 "binary_fp_operator"
14386 [(match_operand:XF 1 "register_operand" "0,f")
14388 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14389 "!TARGET_64BIT && TARGET_80387"
14390 "* return output_387_binary_op (insn, operands);"
14391 [(set (attr "type")
14392 (cond [(match_operand:XF 3 "mult_operator" "")
14393 (const_string "fmul")
14394 (match_operand:XF 3 "div_operator" "")
14395 (const_string "fdiv")
14397 (const_string "fop")))
14398 (set_attr "mode" "SF")])
14400 (define_insn "*fop_tf_5"
14401 [(set (match_operand:TF 0 "register_operand" "=f,f")
14402 (match_operator:TF 3 "binary_fp_operator"
14403 [(match_operand:TF 1 "register_operand" "0,f")
14405 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14407 "* return output_387_binary_op (insn, operands);"
14408 [(set (attr "type")
14409 (cond [(match_operand:TF 3 "mult_operator" "")
14410 (const_string "fmul")
14411 (match_operand:TF 3 "div_operator" "")
14412 (const_string "fdiv")
14414 (const_string "fop")))
14415 (set_attr "mode" "SF")])
14417 (define_insn "*fop_xf_6"
14418 [(set (match_operand:XF 0 "register_operand" "=f,f")
14419 (match_operator:XF 3 "binary_fp_operator"
14420 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14421 (match_operand:XF 2 "register_operand" "0,f")]))]
14422 "!TARGET_64BIT && TARGET_80387"
14423 "* return output_387_binary_op (insn, operands);"
14424 [(set (attr "type")
14425 (cond [(match_operand:XF 3 "mult_operator" "")
14426 (const_string "fmul")
14427 (match_operand:XF 3 "div_operator" "")
14428 (const_string "fdiv")
14430 (const_string "fop")))
14431 (set_attr "mode" "DF")])
14433 (define_insn "*fop_tf_6"
14434 [(set (match_operand:TF 0 "register_operand" "=f,f")
14435 (match_operator:TF 3 "binary_fp_operator"
14436 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14437 (match_operand:TF 2 "register_operand" "0,f")]))]
14439 "* return output_387_binary_op (insn, operands);"
14440 [(set (attr "type")
14441 (cond [(match_operand:TF 3 "mult_operator" "")
14442 (const_string "fmul")
14443 (match_operand:TF 3 "div_operator" "")
14444 (const_string "fdiv")
14446 (const_string "fop")))
14447 (set_attr "mode" "DF")])
14449 (define_insn "*fop_xf_7"
14450 [(set (match_operand:XF 0 "register_operand" "=f,f")
14451 (match_operator:XF 3 "binary_fp_operator"
14452 [(match_operand:XF 1 "register_operand" "0,f")
14454 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14455 "!TARGET_64BIT && TARGET_80387"
14456 "* return output_387_binary_op (insn, operands);"
14457 [(set (attr "type")
14458 (cond [(match_operand:XF 3 "mult_operator" "")
14459 (const_string "fmul")
14460 (match_operand:XF 3 "div_operator" "")
14461 (const_string "fdiv")
14463 (const_string "fop")))
14464 (set_attr "mode" "DF")])
14466 (define_insn "*fop_tf_7"
14467 [(set (match_operand:TF 0 "register_operand" "=f,f")
14468 (match_operator:TF 3 "binary_fp_operator"
14469 [(match_operand:TF 1 "register_operand" "0,f")
14471 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14473 "* return output_387_binary_op (insn, operands);"
14474 [(set (attr "type")
14475 (cond [(match_operand:TF 3 "mult_operator" "")
14476 (const_string "fmul")
14477 (match_operand:TF 3 "div_operator" "")
14478 (const_string "fdiv")
14480 (const_string "fop")))
14481 (set_attr "mode" "DF")])
14484 [(set (match_operand 0 "register_operand" "")
14485 (match_operator 3 "binary_fp_operator"
14486 [(float (match_operand:SI 1 "register_operand" ""))
14487 (match_operand 2 "register_operand" "")]))]
14488 "TARGET_80387 && reload_completed
14489 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14492 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14493 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14494 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14495 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14496 GET_MODE (operands[3]),
14499 ix86_free_from_memory (GET_MODE (operands[1]));
14504 [(set (match_operand 0 "register_operand" "")
14505 (match_operator 3 "binary_fp_operator"
14506 [(match_operand 1 "register_operand" "")
14507 (float (match_operand:SI 2 "register_operand" ""))]))]
14508 "TARGET_80387 && reload_completed
14509 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14512 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14513 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14514 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14515 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14516 GET_MODE (operands[3]),
14519 ix86_free_from_memory (GET_MODE (operands[2]));
14523 ;; FPU special functions.
14525 (define_expand "sqrtsf2"
14526 [(set (match_operand:SF 0 "register_operand" "")
14527 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14528 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
14530 if (!TARGET_SSE_MATH)
14531 operands[1] = force_reg (SFmode, operands[1]);
14534 (define_insn "sqrtsf2_1"
14535 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14536 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14537 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14538 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14541 sqrtss\t{%1, %0|%0, %1}"
14542 [(set_attr "type" "fpspc,sse")
14543 (set_attr "mode" "SF,SF")
14544 (set_attr "athlon_decode" "direct,*")])
14546 (define_insn "sqrtsf2_1_sse_only"
14547 [(set (match_operand:SF 0 "register_operand" "=x")
14548 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14549 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14550 "sqrtss\t{%1, %0|%0, %1}"
14551 [(set_attr "type" "sse")
14552 (set_attr "mode" "SF")
14553 (set_attr "athlon_decode" "*")])
14555 (define_insn "sqrtsf2_i387"
14556 [(set (match_operand:SF 0 "register_operand" "=f")
14557 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14558 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14559 && !TARGET_SSE_MATH"
14561 [(set_attr "type" "fpspc")
14562 (set_attr "mode" "SF")
14563 (set_attr "athlon_decode" "direct")])
14565 (define_expand "sqrtdf2"
14566 [(set (match_operand:DF 0 "register_operand" "")
14567 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14568 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
14569 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14571 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
14572 operands[1] = force_reg (DFmode, operands[1]);
14575 (define_insn "sqrtdf2_1"
14576 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14577 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14578 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14579 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14582 sqrtsd\t{%1, %0|%0, %1}"
14583 [(set_attr "type" "fpspc,sse")
14584 (set_attr "mode" "DF,DF")
14585 (set_attr "athlon_decode" "direct,*")])
14587 (define_insn "sqrtdf2_1_sse_only"
14588 [(set (match_operand:DF 0 "register_operand" "=Y")
14589 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14590 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14591 "sqrtsd\t{%1, %0|%0, %1}"
14592 [(set_attr "type" "sse")
14593 (set_attr "mode" "DF")
14594 (set_attr "athlon_decode" "*")])
14596 (define_insn "sqrtdf2_i387"
14597 [(set (match_operand:DF 0 "register_operand" "=f")
14598 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14599 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14600 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
14602 [(set_attr "type" "fpspc")
14603 (set_attr "mode" "DF")
14604 (set_attr "athlon_decode" "direct")])
14606 (define_insn "*sqrtextendsfdf2"
14607 [(set (match_operand:DF 0 "register_operand" "=f")
14608 (sqrt:DF (float_extend:DF
14609 (match_operand:SF 1 "register_operand" "0"))))]
14610 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14611 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14613 [(set_attr "type" "fpspc")
14614 (set_attr "mode" "DF")
14615 (set_attr "athlon_decode" "direct")])
14617 (define_insn "sqrtxf2"
14618 [(set (match_operand:XF 0 "register_operand" "=f")
14619 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14620 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14621 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14623 [(set_attr "type" "fpspc")
14624 (set_attr "mode" "XF")
14625 (set_attr "athlon_decode" "direct")])
14627 (define_insn "sqrttf2"
14628 [(set (match_operand:TF 0 "register_operand" "=f")
14629 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
14630 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14631 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14633 [(set_attr "type" "fpspc")
14634 (set_attr "mode" "XF")
14635 (set_attr "athlon_decode" "direct")])
14637 (define_insn "*sqrtextenddfxf2"
14638 [(set (match_operand:XF 0 "register_operand" "=f")
14639 (sqrt:XF (float_extend:XF
14640 (match_operand:DF 1 "register_operand" "0"))))]
14641 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14643 [(set_attr "type" "fpspc")
14644 (set_attr "mode" "XF")
14645 (set_attr "athlon_decode" "direct")])
14647 (define_insn "*sqrtextenddftf2"
14648 [(set (match_operand:TF 0 "register_operand" "=f")
14649 (sqrt:TF (float_extend:TF
14650 (match_operand:DF 1 "register_operand" "0"))))]
14651 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14653 [(set_attr "type" "fpspc")
14654 (set_attr "mode" "XF")
14655 (set_attr "athlon_decode" "direct")])
14657 (define_insn "*sqrtextendsfxf2"
14658 [(set (match_operand:XF 0 "register_operand" "=f")
14659 (sqrt:XF (float_extend:XF
14660 (match_operand:SF 1 "register_operand" "0"))))]
14661 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14663 [(set_attr "type" "fpspc")
14664 (set_attr "mode" "XF")
14665 (set_attr "athlon_decode" "direct")])
14667 (define_insn "*sqrtextendsftf2"
14668 [(set (match_operand:TF 0 "register_operand" "=f")
14669 (sqrt:TF (float_extend:TF
14670 (match_operand:SF 1 "register_operand" "0"))))]
14671 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14673 [(set_attr "type" "fpspc")
14674 (set_attr "mode" "XF")
14675 (set_attr "athlon_decode" "direct")])
14677 (define_insn "sindf2"
14678 [(set (match_operand:DF 0 "register_operand" "=f")
14679 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14680 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14681 && flag_unsafe_math_optimizations"
14683 [(set_attr "type" "fpspc")
14684 (set_attr "mode" "DF")])
14686 (define_insn "sinsf2"
14687 [(set (match_operand:SF 0 "register_operand" "=f")
14688 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14689 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14690 && flag_unsafe_math_optimizations"
14692 [(set_attr "type" "fpspc")
14693 (set_attr "mode" "SF")])
14695 (define_insn "*sinextendsfdf2"
14696 [(set (match_operand:DF 0 "register_operand" "=f")
14697 (unspec:DF [(float_extend:DF
14698 (match_operand:SF 1 "register_operand" "0"))]
14700 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14701 && flag_unsafe_math_optimizations"
14703 [(set_attr "type" "fpspc")
14704 (set_attr "mode" "DF")])
14706 (define_insn "sinxf2"
14707 [(set (match_operand:XF 0 "register_operand" "=f")
14708 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14709 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14710 && flag_unsafe_math_optimizations"
14712 [(set_attr "type" "fpspc")
14713 (set_attr "mode" "XF")])
14715 (define_insn "sintf2"
14716 [(set (match_operand:TF 0 "register_operand" "=f")
14717 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
14718 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14719 && flag_unsafe_math_optimizations"
14721 [(set_attr "type" "fpspc")
14722 (set_attr "mode" "XF")])
14724 (define_insn "cosdf2"
14725 [(set (match_operand:DF 0 "register_operand" "=f")
14726 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14727 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14728 && flag_unsafe_math_optimizations"
14730 [(set_attr "type" "fpspc")
14731 (set_attr "mode" "DF")])
14733 (define_insn "cossf2"
14734 [(set (match_operand:SF 0 "register_operand" "=f")
14735 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14736 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14737 && flag_unsafe_math_optimizations"
14739 [(set_attr "type" "fpspc")
14740 (set_attr "mode" "SF")])
14742 (define_insn "*cosextendsfdf2"
14743 [(set (match_operand:DF 0 "register_operand" "=f")
14744 (unspec:DF [(float_extend:DF
14745 (match_operand:SF 1 "register_operand" "0"))]
14747 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14748 && flag_unsafe_math_optimizations"
14750 [(set_attr "type" "fpspc")
14751 (set_attr "mode" "DF")])
14753 (define_insn "cosxf2"
14754 [(set (match_operand:XF 0 "register_operand" "=f")
14755 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14756 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14757 && flag_unsafe_math_optimizations"
14759 [(set_attr "type" "fpspc")
14760 (set_attr "mode" "XF")])
14762 (define_insn "costf2"
14763 [(set (match_operand:TF 0 "register_operand" "=f")
14764 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
14765 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14766 && flag_unsafe_math_optimizations"
14768 [(set_attr "type" "fpspc")
14769 (set_attr "mode" "XF")])
14771 ;; Block operation instructions
14774 [(set (reg:SI 19) (const_int 0))]
14777 [(set_attr "type" "cld")])
14779 (define_expand "movstrsi"
14780 [(use (match_operand:BLK 0 "memory_operand" ""))
14781 (use (match_operand:BLK 1 "memory_operand" ""))
14782 (use (match_operand:SI 2 "nonmemory_operand" ""))
14783 (use (match_operand:SI 3 "const_int_operand" ""))]
14786 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14792 (define_expand "movstrdi"
14793 [(use (match_operand:BLK 0 "memory_operand" ""))
14794 (use (match_operand:BLK 1 "memory_operand" ""))
14795 (use (match_operand:DI 2 "nonmemory_operand" ""))
14796 (use (match_operand:DI 3 "const_int_operand" ""))]
14799 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14805 ;; Most CPUs don't like single string operations
14806 ;; Handle this case here to simplify previous expander.
14808 (define_expand "strmovdi_rex64"
14809 [(set (match_dup 2)
14810 (mem:DI (match_operand:DI 1 "register_operand" "")))
14811 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14813 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14814 (clobber (reg:CC 17))])
14815 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14816 (clobber (reg:CC 17))])]
14819 if (TARGET_SINGLE_STRINGOP || optimize_size)
14821 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14826 operands[2] = gen_reg_rtx (DImode);
14830 (define_expand "strmovsi"
14831 [(set (match_dup 2)
14832 (mem:SI (match_operand:SI 1 "register_operand" "")))
14833 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14835 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14836 (clobber (reg:CC 17))])
14837 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14838 (clobber (reg:CC 17))])]
14843 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14846 if (TARGET_SINGLE_STRINGOP || optimize_size)
14848 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14853 operands[2] = gen_reg_rtx (SImode);
14856 (define_expand "strmovsi_rex64"
14857 [(set (match_dup 2)
14858 (mem:SI (match_operand:DI 1 "register_operand" "")))
14859 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14861 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14862 (clobber (reg:CC 17))])
14863 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14864 (clobber (reg:CC 17))])]
14867 if (TARGET_SINGLE_STRINGOP || optimize_size)
14869 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14874 operands[2] = gen_reg_rtx (SImode);
14877 (define_expand "strmovhi"
14878 [(set (match_dup 2)
14879 (mem:HI (match_operand:SI 1 "register_operand" "")))
14880 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14882 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14883 (clobber (reg:CC 17))])
14884 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14885 (clobber (reg:CC 17))])]
14890 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14893 if (TARGET_SINGLE_STRINGOP || optimize_size)
14895 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14900 operands[2] = gen_reg_rtx (HImode);
14903 (define_expand "strmovhi_rex64"
14904 [(set (match_dup 2)
14905 (mem:HI (match_operand:DI 1 "register_operand" "")))
14906 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14908 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14909 (clobber (reg:CC 17))])
14910 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14911 (clobber (reg:CC 17))])]
14914 if (TARGET_SINGLE_STRINGOP || optimize_size)
14916 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14921 operands[2] = gen_reg_rtx (HImode);
14924 (define_expand "strmovqi"
14925 [(set (match_dup 2)
14926 (mem:QI (match_operand:SI 1 "register_operand" "")))
14927 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14929 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14930 (clobber (reg:CC 17))])
14931 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14932 (clobber (reg:CC 17))])]
14937 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14940 if (TARGET_SINGLE_STRINGOP || optimize_size)
14942 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14947 operands[2] = gen_reg_rtx (QImode);
14950 (define_expand "strmovqi_rex64"
14951 [(set (match_dup 2)
14952 (mem:QI (match_operand:DI 1 "register_operand" "")))
14953 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14955 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14956 (clobber (reg:CC 17))])
14957 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14958 (clobber (reg:CC 17))])]
14961 if (TARGET_SINGLE_STRINGOP || optimize_size)
14963 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14968 operands[2] = gen_reg_rtx (QImode);
14971 (define_insn "strmovdi_rex_1"
14972 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14973 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14974 (set (match_operand:DI 0 "register_operand" "=D")
14975 (plus:DI (match_dup 2)
14977 (set (match_operand:DI 1 "register_operand" "=S")
14978 (plus:DI (match_dup 3)
14981 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14983 [(set_attr "type" "str")
14984 (set_attr "mode" "DI")
14985 (set_attr "memory" "both")])
14987 (define_insn "strmovsi_1"
14988 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
14989 (mem:SI (match_operand:SI 3 "register_operand" "1")))
14990 (set (match_operand:SI 0 "register_operand" "=D")
14991 (plus:SI (match_dup 2)
14993 (set (match_operand:SI 1 "register_operand" "=S")
14994 (plus:SI (match_dup 3)
14997 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14999 [(set_attr "type" "str")
15000 (set_attr "mode" "SI")
15001 (set_attr "memory" "both")])
15003 (define_insn "strmovsi_rex_1"
15004 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
15005 (mem:SI (match_operand:DI 3 "register_operand" "1")))
15006 (set (match_operand:DI 0 "register_operand" "=D")
15007 (plus:DI (match_dup 2)
15009 (set (match_operand:DI 1 "register_operand" "=S")
15010 (plus:DI (match_dup 3)
15013 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15015 [(set_attr "type" "str")
15016 (set_attr "mode" "SI")
15017 (set_attr "memory" "both")])
15019 (define_insn "strmovhi_1"
15020 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
15021 (mem:HI (match_operand:SI 3 "register_operand" "1")))
15022 (set (match_operand:SI 0 "register_operand" "=D")
15023 (plus:SI (match_dup 2)
15025 (set (match_operand:SI 1 "register_operand" "=S")
15026 (plus:SI (match_dup 3)
15029 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15031 [(set_attr "type" "str")
15032 (set_attr "memory" "both")
15033 (set_attr "mode" "HI")])
15035 (define_insn "strmovhi_rex_1"
15036 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
15037 (mem:HI (match_operand:DI 3 "register_operand" "1")))
15038 (set (match_operand:DI 0 "register_operand" "=D")
15039 (plus:DI (match_dup 2)
15041 (set (match_operand:DI 1 "register_operand" "=S")
15042 (plus:DI (match_dup 3)
15045 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15047 [(set_attr "type" "str")
15048 (set_attr "memory" "both")
15049 (set_attr "mode" "HI")])
15051 (define_insn "strmovqi_1"
15052 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
15053 (mem:QI (match_operand:SI 3 "register_operand" "1")))
15054 (set (match_operand:SI 0 "register_operand" "=D")
15055 (plus:SI (match_dup 2)
15057 (set (match_operand:SI 1 "register_operand" "=S")
15058 (plus:SI (match_dup 3)
15061 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15063 [(set_attr "type" "str")
15064 (set_attr "memory" "both")
15065 (set_attr "mode" "QI")])
15067 (define_insn "strmovqi_rex_1"
15068 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
15069 (mem:QI (match_operand:DI 3 "register_operand" "1")))
15070 (set (match_operand:DI 0 "register_operand" "=D")
15071 (plus:DI (match_dup 2)
15073 (set (match_operand:DI 1 "register_operand" "=S")
15074 (plus:DI (match_dup 3)
15077 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15079 [(set_attr "type" "str")
15080 (set_attr "memory" "both")
15081 (set_attr "mode" "QI")])
15083 (define_insn "rep_movdi_rex64"
15084 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15085 (set (match_operand:DI 0 "register_operand" "=D")
15086 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15088 (match_operand:DI 3 "register_operand" "0")))
15089 (set (match_operand:DI 1 "register_operand" "=S")
15090 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15091 (match_operand:DI 4 "register_operand" "1")))
15092 (set (mem:BLK (match_dup 3))
15093 (mem:BLK (match_dup 4)))
15094 (use (match_dup 5))
15097 "{rep\;movsq|rep movsq}"
15098 [(set_attr "type" "str")
15099 (set_attr "prefix_rep" "1")
15100 (set_attr "memory" "both")
15101 (set_attr "mode" "DI")])
15103 (define_insn "rep_movsi"
15104 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15105 (set (match_operand:SI 0 "register_operand" "=D")
15106 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
15108 (match_operand:SI 3 "register_operand" "0")))
15109 (set (match_operand:SI 1 "register_operand" "=S")
15110 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
15111 (match_operand:SI 4 "register_operand" "1")))
15112 (set (mem:BLK (match_dup 3))
15113 (mem:BLK (match_dup 4)))
15114 (use (match_dup 5))
15117 "{rep\;movsl|rep movsd}"
15118 [(set_attr "type" "str")
15119 (set_attr "prefix_rep" "1")
15120 (set_attr "memory" "both")
15121 (set_attr "mode" "SI")])
15123 (define_insn "rep_movsi_rex64"
15124 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15125 (set (match_operand:DI 0 "register_operand" "=D")
15126 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15128 (match_operand:DI 3 "register_operand" "0")))
15129 (set (match_operand:DI 1 "register_operand" "=S")
15130 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
15131 (match_operand:DI 4 "register_operand" "1")))
15132 (set (mem:BLK (match_dup 3))
15133 (mem:BLK (match_dup 4)))
15134 (use (match_dup 5))
15137 "{rep\;movsl|rep movsd}"
15138 [(set_attr "type" "str")
15139 (set_attr "prefix_rep" "1")
15140 (set_attr "memory" "both")
15141 (set_attr "mode" "SI")])
15143 (define_insn "rep_movqi"
15144 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15145 (set (match_operand:SI 0 "register_operand" "=D")
15146 (plus:SI (match_operand:SI 3 "register_operand" "0")
15147 (match_operand:SI 5 "register_operand" "2")))
15148 (set (match_operand:SI 1 "register_operand" "=S")
15149 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
15150 (set (mem:BLK (match_dup 3))
15151 (mem:BLK (match_dup 4)))
15152 (use (match_dup 5))
15155 "{rep\;movsb|rep movsb}"
15156 [(set_attr "type" "str")
15157 (set_attr "prefix_rep" "1")
15158 (set_attr "memory" "both")
15159 (set_attr "mode" "SI")])
15161 (define_insn "rep_movqi_rex64"
15162 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15163 (set (match_operand:DI 0 "register_operand" "=D")
15164 (plus:DI (match_operand:DI 3 "register_operand" "0")
15165 (match_operand:DI 5 "register_operand" "2")))
15166 (set (match_operand:DI 1 "register_operand" "=S")
15167 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
15168 (set (mem:BLK (match_dup 3))
15169 (mem:BLK (match_dup 4)))
15170 (use (match_dup 5))
15173 "{rep\;movsb|rep movsb}"
15174 [(set_attr "type" "str")
15175 (set_attr "prefix_rep" "1")
15176 (set_attr "memory" "both")
15177 (set_attr "mode" "SI")])
15179 (define_expand "clrstrsi"
15180 [(use (match_operand:BLK 0 "memory_operand" ""))
15181 (use (match_operand:SI 1 "nonmemory_operand" ""))
15182 (use (match_operand 2 "const_int_operand" ""))]
15185 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15191 (define_expand "clrstrdi"
15192 [(use (match_operand:BLK 0 "memory_operand" ""))
15193 (use (match_operand:DI 1 "nonmemory_operand" ""))
15194 (use (match_operand 2 "const_int_operand" ""))]
15197 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15203 ;; Most CPUs don't like single string operations
15204 ;; Handle this case here to simplify previous expander.
15206 (define_expand "strsetdi_rex64"
15207 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
15208 (match_operand:DI 1 "register_operand" ""))
15209 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15210 (clobber (reg:CC 17))])]
15213 if (TARGET_SINGLE_STRINGOP || optimize_size)
15215 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
15220 (define_expand "strsetsi"
15221 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
15222 (match_operand:SI 1 "register_operand" ""))
15223 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15224 (clobber (reg:CC 17))])]
15229 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
15232 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15234 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
15239 (define_expand "strsetsi_rex64"
15240 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
15241 (match_operand:SI 1 "register_operand" ""))
15242 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15243 (clobber (reg:CC 17))])]
15246 if (TARGET_SINGLE_STRINGOP || optimize_size)
15248 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
15253 (define_expand "strsethi"
15254 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
15255 (match_operand:HI 1 "register_operand" ""))
15256 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15257 (clobber (reg:CC 17))])]
15262 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
15265 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15267 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
15272 (define_expand "strsethi_rex64"
15273 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
15274 (match_operand:HI 1 "register_operand" ""))
15275 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15276 (clobber (reg:CC 17))])]
15279 if (TARGET_SINGLE_STRINGOP || optimize_size)
15281 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
15286 (define_expand "strsetqi"
15287 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
15288 (match_operand:QI 1 "register_operand" ""))
15289 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15290 (clobber (reg:CC 17))])]
15295 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
15298 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15300 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
15305 (define_expand "strsetqi_rex64"
15306 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
15307 (match_operand:QI 1 "register_operand" ""))
15308 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15309 (clobber (reg:CC 17))])]
15312 if (TARGET_SINGLE_STRINGOP || optimize_size)
15314 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
15319 (define_insn "strsetdi_rex_1"
15320 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15321 (match_operand:SI 2 "register_operand" "a"))
15322 (set (match_operand:DI 0 "register_operand" "=D")
15323 (plus:DI (match_dup 1)
15326 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15328 [(set_attr "type" "str")
15329 (set_attr "memory" "store")
15330 (set_attr "mode" "DI")])
15332 (define_insn "strsetsi_1"
15333 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15334 (match_operand:SI 2 "register_operand" "a"))
15335 (set (match_operand:SI 0 "register_operand" "=D")
15336 (plus:SI (match_dup 1)
15339 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15341 [(set_attr "type" "str")
15342 (set_attr "memory" "store")
15343 (set_attr "mode" "SI")])
15345 (define_insn "strsetsi_rex_1"
15346 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15347 (match_operand:SI 2 "register_operand" "a"))
15348 (set (match_operand:DI 0 "register_operand" "=D")
15349 (plus:DI (match_dup 1)
15352 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15354 [(set_attr "type" "str")
15355 (set_attr "memory" "store")
15356 (set_attr "mode" "SI")])
15358 (define_insn "strsethi_1"
15359 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15360 (match_operand:HI 2 "register_operand" "a"))
15361 (set (match_operand:SI 0 "register_operand" "=D")
15362 (plus:SI (match_dup 1)
15365 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15367 [(set_attr "type" "str")
15368 (set_attr "memory" "store")
15369 (set_attr "mode" "HI")])
15371 (define_insn "strsethi_rex_1"
15372 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15373 (match_operand:HI 2 "register_operand" "a"))
15374 (set (match_operand:DI 0 "register_operand" "=D")
15375 (plus:DI (match_dup 1)
15378 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15380 [(set_attr "type" "str")
15381 (set_attr "memory" "store")
15382 (set_attr "mode" "HI")])
15384 (define_insn "strsetqi_1"
15385 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15386 (match_operand:QI 2 "register_operand" "a"))
15387 (set (match_operand:SI 0 "register_operand" "=D")
15388 (plus:SI (match_dup 1)
15391 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15393 [(set_attr "type" "str")
15394 (set_attr "memory" "store")
15395 (set_attr "mode" "QI")])
15397 (define_insn "strsetqi_rex_1"
15398 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15399 (match_operand:QI 2 "register_operand" "a"))
15400 (set (match_operand:DI 0 "register_operand" "=D")
15401 (plus:DI (match_dup 1)
15404 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15406 [(set_attr "type" "str")
15407 (set_attr "memory" "store")
15408 (set_attr "mode" "QI")])
15410 (define_insn "rep_stosdi_rex64"
15411 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15412 (set (match_operand:DI 0 "register_operand" "=D")
15413 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15415 (match_operand:DI 3 "register_operand" "0")))
15416 (set (mem:BLK (match_dup 3))
15418 (use (match_operand:DI 2 "register_operand" "a"))
15419 (use (match_dup 4))
15422 "{rep\;stosq|rep stosq}"
15423 [(set_attr "type" "str")
15424 (set_attr "prefix_rep" "1")
15425 (set_attr "memory" "store")
15426 (set_attr "mode" "DI")])
15428 (define_insn "rep_stossi"
15429 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15430 (set (match_operand:SI 0 "register_operand" "=D")
15431 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15433 (match_operand:SI 3 "register_operand" "0")))
15434 (set (mem:BLK (match_dup 3))
15436 (use (match_operand:SI 2 "register_operand" "a"))
15437 (use (match_dup 4))
15440 "{rep\;stosl|rep stosd}"
15441 [(set_attr "type" "str")
15442 (set_attr "prefix_rep" "1")
15443 (set_attr "memory" "store")
15444 (set_attr "mode" "SI")])
15446 (define_insn "rep_stossi_rex64"
15447 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15448 (set (match_operand:DI 0 "register_operand" "=D")
15449 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15451 (match_operand:DI 3 "register_operand" "0")))
15452 (set (mem:BLK (match_dup 3))
15454 (use (match_operand:SI 2 "register_operand" "a"))
15455 (use (match_dup 4))
15458 "{rep\;stosl|rep stosd}"
15459 [(set_attr "type" "str")
15460 (set_attr "prefix_rep" "1")
15461 (set_attr "memory" "store")
15462 (set_attr "mode" "SI")])
15464 (define_insn "rep_stosqi"
15465 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15466 (set (match_operand:SI 0 "register_operand" "=D")
15467 (plus:SI (match_operand:SI 3 "register_operand" "0")
15468 (match_operand:SI 4 "register_operand" "1")))
15469 (set (mem:BLK (match_dup 3))
15471 (use (match_operand:QI 2 "register_operand" "a"))
15472 (use (match_dup 4))
15475 "{rep\;stosb|rep stosb}"
15476 [(set_attr "type" "str")
15477 (set_attr "prefix_rep" "1")
15478 (set_attr "memory" "store")
15479 (set_attr "mode" "QI")])
15481 (define_insn "rep_stosqi_rex64"
15482 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15483 (set (match_operand:DI 0 "register_operand" "=D")
15484 (plus:DI (match_operand:DI 3 "register_operand" "0")
15485 (match_operand:DI 4 "register_operand" "1")))
15486 (set (mem:BLK (match_dup 3))
15488 (use (match_operand:QI 2 "register_operand" "a"))
15489 (use (match_dup 4))
15492 "{rep\;stosb|rep stosb}"
15493 [(set_attr "type" "str")
15494 (set_attr "prefix_rep" "1")
15495 (set_attr "memory" "store")
15496 (set_attr "mode" "QI")])
15498 (define_expand "cmpstrsi"
15499 [(set (match_operand:SI 0 "register_operand" "")
15500 (compare:SI (match_operand:BLK 1 "general_operand" "")
15501 (match_operand:BLK 2 "general_operand" "")))
15502 (use (match_operand 3 "general_operand" ""))
15503 (use (match_operand 4 "immediate_operand" ""))]
15506 rtx addr1, addr2, out, outlow, count, countreg, align;
15509 if (GET_CODE (out) != REG)
15510 out = gen_reg_rtx (SImode);
15512 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15513 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15515 count = operands[3];
15516 countreg = ix86_zero_extend_to_Pmode (count);
15518 /* %%% Iff we are testing strict equality, we can use known alignment
15519 to good advantage. This may be possible with combine, particularly
15520 once cc0 is dead. */
15521 align = operands[4];
15523 emit_insn (gen_cld ());
15524 if (GET_CODE (count) == CONST_INT)
15526 if (INTVAL (count) == 0)
15528 emit_move_insn (operands[0], const0_rtx);
15532 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
15533 addr1, addr2, countreg));
15535 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15536 addr1, addr2, countreg));
15542 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15543 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
15544 addr1, addr2, countreg));
15548 emit_insn (gen_cmpsi_1 (countreg, countreg));
15549 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15550 addr1, addr2, countreg));
15554 outlow = gen_lowpart (QImode, out);
15555 emit_insn (gen_cmpintqi (outlow));
15556 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15558 if (operands[0] != out)
15559 emit_move_insn (operands[0], out);
15564 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15566 (define_expand "cmpintqi"
15567 [(set (match_dup 1)
15568 (gtu:QI (reg:CC 17) (const_int 0)))
15570 (ltu:QI (reg:CC 17) (const_int 0)))
15571 (parallel [(set (match_operand:QI 0 "register_operand" "")
15572 (minus:QI (match_dup 1)
15574 (clobber (reg:CC 17))])]
15576 "operands[1] = gen_reg_rtx (QImode);
15577 operands[2] = gen_reg_rtx (QImode);")
15579 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15580 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15582 (define_insn "cmpstrqi_nz_1"
15584 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15585 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15586 (use (match_operand:SI 6 "register_operand" "2"))
15587 (use (match_operand:SI 3 "immediate_operand" "i"))
15589 (clobber (match_operand:SI 0 "register_operand" "=S"))
15590 (clobber (match_operand:SI 1 "register_operand" "=D"))
15591 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15594 [(set_attr "type" "str")
15595 (set_attr "mode" "QI")
15596 (set_attr "prefix_rep" "1")])
15598 (define_insn "cmpstrqi_nz_rex_1"
15600 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15601 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15602 (use (match_operand:DI 6 "register_operand" "2"))
15603 (use (match_operand:SI 3 "immediate_operand" "i"))
15605 (clobber (match_operand:DI 0 "register_operand" "=S"))
15606 (clobber (match_operand:DI 1 "register_operand" "=D"))
15607 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15610 [(set_attr "type" "str")
15611 (set_attr "mode" "QI")
15612 (set_attr "prefix_rep" "1")])
15614 ;; The same, but the count is not known to not be zero.
15616 (define_insn "cmpstrqi_1"
15618 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
15620 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15621 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
15623 (use (match_operand:SI 3 "immediate_operand" "i"))
15626 (clobber (match_operand:SI 0 "register_operand" "=S"))
15627 (clobber (match_operand:SI 1 "register_operand" "=D"))
15628 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15631 [(set_attr "type" "str")
15632 (set_attr "mode" "QI")
15633 (set_attr "prefix_rep" "1")])
15635 (define_insn "cmpstrqi_rex_1"
15637 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
15639 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15640 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
15642 (use (match_operand:SI 3 "immediate_operand" "i"))
15645 (clobber (match_operand:DI 0 "register_operand" "=S"))
15646 (clobber (match_operand:DI 1 "register_operand" "=D"))
15647 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15650 [(set_attr "type" "str")
15651 (set_attr "mode" "QI")
15652 (set_attr "prefix_rep" "1")])
15654 (define_expand "strlensi"
15655 [(set (match_operand:SI 0 "register_operand" "")
15656 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15657 (match_operand:QI 2 "immediate_operand" "")
15658 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
15661 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15667 (define_expand "strlendi"
15668 [(set (match_operand:DI 0 "register_operand" "")
15669 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15670 (match_operand:QI 2 "immediate_operand" "")
15671 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
15674 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15680 (define_insn "strlenqi_1"
15681 [(set (match_operand:SI 0 "register_operand" "=&c")
15682 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15683 (match_operand:QI 2 "register_operand" "a")
15684 (match_operand:SI 3 "immediate_operand" "i")
15685 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
15687 (clobber (match_operand:SI 1 "register_operand" "=D"))
15688 (clobber (reg:CC 17))]
15691 [(set_attr "type" "str")
15692 (set_attr "mode" "QI")
15693 (set_attr "prefix_rep" "1")])
15695 (define_insn "strlenqi_rex_1"
15696 [(set (match_operand:DI 0 "register_operand" "=&c")
15697 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15698 (match_operand:QI 2 "register_operand" "a")
15699 (match_operand:DI 3 "immediate_operand" "i")
15700 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
15702 (clobber (match_operand:DI 1 "register_operand" "=D"))
15703 (clobber (reg:CC 17))]
15706 [(set_attr "type" "str")
15707 (set_attr "mode" "QI")
15708 (set_attr "prefix_rep" "1")])
15710 ;; Peephole optimizations to clean up after cmpstr*. This should be
15711 ;; handled in combine, but it is not currently up to the task.
15712 ;; When used for their truth value, the cmpstr* expanders generate
15721 ;; The intermediate three instructions are unnecessary.
15723 ;; This one handles cmpstr*_nz_1...
15727 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15728 (mem:BLK (match_operand 5 "register_operand" ""))))
15729 (use (match_operand 6 "register_operand" ""))
15730 (use (match_operand:SI 3 "immediate_operand" ""))
15732 (clobber (match_operand 0 "register_operand" ""))
15733 (clobber (match_operand 1 "register_operand" ""))
15734 (clobber (match_operand 2 "register_operand" ""))])
15735 (set (match_operand:QI 7 "register_operand" "")
15736 (gtu:QI (reg:CC 17) (const_int 0)))
15737 (set (match_operand:QI 8 "register_operand" "")
15738 (ltu:QI (reg:CC 17) (const_int 0)))
15740 (compare (match_dup 7) (match_dup 8)))
15742 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15745 (compare:CC (mem:BLK (match_dup 4))
15746 (mem:BLK (match_dup 5))))
15747 (use (match_dup 6))
15748 (use (match_dup 3))
15750 (clobber (match_dup 0))
15751 (clobber (match_dup 1))
15752 (clobber (match_dup 2))])]
15755 ;; ...and this one handles cmpstr*_1.
15759 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
15761 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15762 (mem:BLK (match_operand 5 "register_operand" "")))
15764 (use (match_operand:SI 3 "immediate_operand" ""))
15767 (clobber (match_operand 0 "register_operand" ""))
15768 (clobber (match_operand 1 "register_operand" ""))
15769 (clobber (match_operand 2 "register_operand" ""))])
15770 (set (match_operand:QI 7 "register_operand" "")
15771 (gtu:QI (reg:CC 17) (const_int 0)))
15772 (set (match_operand:QI 8 "register_operand" "")
15773 (ltu:QI (reg:CC 17) (const_int 0)))
15775 (compare (match_dup 7) (match_dup 8)))
15777 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15780 (if_then_else:CC (ne (match_dup 6)
15782 (compare:CC (mem:BLK (match_dup 4))
15783 (mem:BLK (match_dup 5)))
15785 (use (match_dup 3))
15788 (clobber (match_dup 0))
15789 (clobber (match_dup 1))
15790 (clobber (match_dup 2))])]
15795 ;; Conditional move instructions.
15797 (define_expand "movdicc"
15798 [(set (match_operand:DI 0 "register_operand" "")
15799 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15800 (match_operand:DI 2 "general_operand" "")
15801 (match_operand:DI 3 "general_operand" "")))]
15803 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15805 (define_insn "x86_movdicc_0_m1_rex64"
15806 [(set (match_operand:DI 0 "register_operand" "=r")
15807 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15810 (clobber (reg:CC 17))]
15813 ; Since we don't have the proper number of operands for an alu insn,
15814 ; fill in all the blanks.
15815 [(set_attr "type" "alu")
15816 (set_attr "pent_pair" "pu")
15817 (set_attr "memory" "none")
15818 (set_attr "imm_disp" "false")
15819 (set_attr "mode" "DI")
15820 (set_attr "length_immediate" "0")])
15822 (define_insn "*movdicc_c_rex64"
15823 [(set (match_operand:DI 0 "register_operand" "=r,r")
15824 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15825 [(reg 17) (const_int 0)])
15826 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15827 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15828 "TARGET_64BIT && TARGET_CMOVE
15829 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15831 cmov%O2%C1\t{%2, %0|%0, %2}
15832 cmov%O2%c1\t{%3, %0|%0, %3}"
15833 [(set_attr "type" "icmov")
15834 (set_attr "mode" "DI")])
15836 (define_expand "movsicc"
15837 [(set (match_operand:SI 0 "register_operand" "")
15838 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15839 (match_operand:SI 2 "general_operand" "")
15840 (match_operand:SI 3 "general_operand" "")))]
15842 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15844 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15845 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15846 ;; So just document what we're doing explicitly.
15848 (define_insn "x86_movsicc_0_m1"
15849 [(set (match_operand:SI 0 "register_operand" "=r")
15850 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15853 (clobber (reg:CC 17))]
15856 ; Since we don't have the proper number of operands for an alu insn,
15857 ; fill in all the blanks.
15858 [(set_attr "type" "alu")
15859 (set_attr "pent_pair" "pu")
15860 (set_attr "memory" "none")
15861 (set_attr "imm_disp" "false")
15862 (set_attr "mode" "SI")
15863 (set_attr "length_immediate" "0")])
15865 (define_insn "*movsicc_noc"
15866 [(set (match_operand:SI 0 "register_operand" "=r,r")
15867 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15868 [(reg 17) (const_int 0)])
15869 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15870 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15872 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15874 cmov%O2%C1\t{%2, %0|%0, %2}
15875 cmov%O2%c1\t{%3, %0|%0, %3}"
15876 [(set_attr "type" "icmov")
15877 (set_attr "mode" "SI")])
15879 (define_expand "movhicc"
15880 [(set (match_operand:HI 0 "register_operand" "")
15881 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15882 (match_operand:HI 2 "nonimmediate_operand" "")
15883 (match_operand:HI 3 "nonimmediate_operand" "")))]
15884 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15885 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15887 (define_insn "*movhicc_noc"
15888 [(set (match_operand:HI 0 "register_operand" "=r,r")
15889 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15890 [(reg 17) (const_int 0)])
15891 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15892 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15894 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15896 cmov%O2%C1\t{%2, %0|%0, %2}
15897 cmov%O2%c1\t{%3, %0|%0, %3}"
15898 [(set_attr "type" "icmov")
15899 (set_attr "mode" "HI")])
15901 (define_expand "movsfcc"
15902 [(set (match_operand:SF 0 "register_operand" "")
15903 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15904 (match_operand:SF 2 "register_operand" "")
15905 (match_operand:SF 3 "register_operand" "")))]
15907 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15909 (define_insn "*movsfcc_1"
15910 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15911 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15912 [(reg 17) (const_int 0)])
15913 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15914 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15916 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15918 fcmov%F1\t{%2, %0|%0, %2}
15919 fcmov%f1\t{%3, %0|%0, %3}
15920 cmov%O2%C1\t{%2, %0|%0, %2}
15921 cmov%O2%c1\t{%3, %0|%0, %3}"
15922 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15923 (set_attr "mode" "SF,SF,SI,SI")])
15925 (define_expand "movdfcc"
15926 [(set (match_operand:DF 0 "register_operand" "")
15927 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15928 (match_operand:DF 2 "register_operand" "")
15929 (match_operand:DF 3 "register_operand" "")))]
15931 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15933 (define_insn "*movdfcc_1"
15934 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15935 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15936 [(reg 17) (const_int 0)])
15937 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15938 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15939 "!TARGET_64BIT && TARGET_CMOVE
15940 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15942 fcmov%F1\t{%2, %0|%0, %2}
15943 fcmov%f1\t{%3, %0|%0, %3}
15946 [(set_attr "type" "fcmov,fcmov,multi,multi")
15947 (set_attr "mode" "DF")])
15949 (define_insn "*movdfcc_1_rex64"
15950 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15951 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15952 [(reg 17) (const_int 0)])
15953 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15954 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15955 "TARGET_64BIT && TARGET_CMOVE
15956 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15958 fcmov%F1\t{%2, %0|%0, %2}
15959 fcmov%f1\t{%3, %0|%0, %3}
15960 cmov%O2%C1\t{%2, %0|%0, %2}
15961 cmov%O2%c1\t{%3, %0|%0, %3}"
15962 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15963 (set_attr "mode" "DF")])
15966 [(set (match_operand:DF 0 "register_operand" "")
15967 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15968 [(match_operand 4 "" "") (const_int 0)])
15969 (match_operand:DF 2 "nonimmediate_operand" "")
15970 (match_operand:DF 3 "nonimmediate_operand" "")))]
15971 "!TARGET_64BIT && !ANY_FP_REG_P (operands[0]) && reload_completed"
15972 [(set (match_dup 2)
15973 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15977 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15980 "split_di (operands+2, 1, operands+5, operands+6);
15981 split_di (operands+3, 1, operands+7, operands+8);
15982 split_di (operands, 1, operands+2, operands+3);")
15984 (define_expand "movxfcc"
15985 [(set (match_operand:XF 0 "register_operand" "")
15986 (if_then_else:XF (match_operand 1 "comparison_operator" "")
15987 (match_operand:XF 2 "register_operand" "")
15988 (match_operand:XF 3 "register_operand" "")))]
15989 "!TARGET_64BIT && TARGET_CMOVE"
15990 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15992 (define_expand "movtfcc"
15993 [(set (match_operand:TF 0 "register_operand" "")
15994 (if_then_else:TF (match_operand 1 "comparison_operator" "")
15995 (match_operand:TF 2 "register_operand" "")
15996 (match_operand:TF 3 "register_operand" "")))]
15998 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16000 (define_insn "*movxfcc_1"
16001 [(set (match_operand:XF 0 "register_operand" "=f,f")
16002 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16003 [(reg 17) (const_int 0)])
16004 (match_operand:XF 2 "register_operand" "f,0")
16005 (match_operand:XF 3 "register_operand" "0,f")))]
16006 "!TARGET_64BIT && TARGET_CMOVE"
16008 fcmov%F1\t{%2, %0|%0, %2}
16009 fcmov%f1\t{%3, %0|%0, %3}"
16010 [(set_attr "type" "fcmov")
16011 (set_attr "mode" "XF")])
16013 (define_insn "*movtfcc_1"
16014 [(set (match_operand:TF 0 "register_operand" "=f,f")
16015 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
16016 [(reg 17) (const_int 0)])
16017 (match_operand:TF 2 "register_operand" "f,0")
16018 (match_operand:TF 3 "register_operand" "0,f")))]
16021 fcmov%F1\t{%2, %0|%0, %2}
16022 fcmov%f1\t{%3, %0|%0, %3}"
16023 [(set_attr "type" "fcmov")
16024 (set_attr "mode" "XF")])
16026 (define_expand "minsf3"
16028 (set (match_operand:SF 0 "register_operand" "")
16029 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16030 (match_operand:SF 2 "nonimmediate_operand" ""))
16033 (clobber (reg:CC 17))])]
16037 (define_insn "*minsf"
16038 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16039 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
16040 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16043 (clobber (reg:CC 17))]
16044 "TARGET_SSE && TARGET_IEEE_FP"
16047 (define_insn "*minsf_nonieee"
16048 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16049 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16050 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16053 (clobber (reg:CC 17))]
16054 "TARGET_SSE && !TARGET_IEEE_FP
16055 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16059 [(set (match_operand:SF 0 "register_operand" "")
16060 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16061 (match_operand:SF 2 "nonimmediate_operand" ""))
16062 (match_operand:SF 3 "register_operand" "")
16063 (match_operand:SF 4 "nonimmediate_operand" "")))
16064 (clobber (reg:CC 17))]
16065 "SSE_REG_P (operands[0]) && reload_completed
16066 && ((operands_match_p (operands[1], operands[3])
16067 && operands_match_p (operands[2], operands[4]))
16068 || (operands_match_p (operands[1], operands[4])
16069 && operands_match_p (operands[2], operands[3])))"
16070 [(set (match_dup 0)
16071 (if_then_else:SF (lt (match_dup 1)
16076 ;; We can't represent the LT test directly. Do this by swapping the operands.
16079 [(set (match_operand:SF 0 "register_operand" "")
16080 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16081 (match_operand:SF 2 "register_operand" ""))
16082 (match_operand:SF 3 "register_operand" "")
16083 (match_operand:SF 4 "register_operand" "")))
16084 (clobber (reg:CC 17))]
16085 "FP_REG_P (operands[0]) && reload_completed
16086 && ((operands_match_p (operands[1], operands[3])
16087 && operands_match_p (operands[2], operands[4]))
16088 || (operands_match_p (operands[1], operands[4])
16089 && operands_match_p (operands[2], operands[3])))"
16090 [(set (reg:CCFP 17)
16091 (compare:CCFP (match_dup 2)
16094 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
16098 (define_insn "*minsf_sse"
16099 [(set (match_operand:SF 0 "register_operand" "=x")
16100 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
16101 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16104 "TARGET_SSE && reload_completed"
16105 "minss\t{%2, %0|%0, %2}"
16106 [(set_attr "type" "sse")
16107 (set_attr "mode" "SF")])
16109 (define_expand "mindf3"
16111 (set (match_operand:DF 0 "register_operand" "")
16112 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16113 (match_operand:DF 2 "nonimmediate_operand" ""))
16116 (clobber (reg:CC 17))])]
16117 "TARGET_SSE2 && TARGET_SSE_MATH"
16120 (define_insn "*mindf"
16121 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16122 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16123 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16126 (clobber (reg:CC 17))]
16127 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16130 (define_insn "*mindf_nonieee"
16131 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16132 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16133 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16136 (clobber (reg:CC 17))]
16137 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16138 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16142 [(set (match_operand:DF 0 "register_operand" "")
16143 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16144 (match_operand:DF 2 "nonimmediate_operand" ""))
16145 (match_operand:DF 3 "register_operand" "")
16146 (match_operand:DF 4 "nonimmediate_operand" "")))
16147 (clobber (reg:CC 17))]
16148 "SSE_REG_P (operands[0]) && reload_completed
16149 && ((operands_match_p (operands[1], operands[3])
16150 && operands_match_p (operands[2], operands[4]))
16151 || (operands_match_p (operands[1], operands[4])
16152 && operands_match_p (operands[2], operands[3])))"
16153 [(set (match_dup 0)
16154 (if_then_else:DF (lt (match_dup 1)
16159 ;; We can't represent the LT test directly. Do this by swapping the operands.
16161 [(set (match_operand:DF 0 "register_operand" "")
16162 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16163 (match_operand:DF 2 "register_operand" ""))
16164 (match_operand:DF 3 "register_operand" "")
16165 (match_operand:DF 4 "register_operand" "")))
16166 (clobber (reg:CC 17))]
16167 "FP_REG_P (operands[0]) && reload_completed
16168 && ((operands_match_p (operands[1], operands[3])
16169 && operands_match_p (operands[2], operands[4]))
16170 || (operands_match_p (operands[1], operands[4])
16171 && operands_match_p (operands[2], operands[3])))"
16172 [(set (reg:CCFP 17)
16173 (compare:CCFP (match_dup 2)
16176 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
16180 (define_insn "*mindf_sse"
16181 [(set (match_operand:DF 0 "register_operand" "=Y")
16182 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
16183 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16186 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16187 "minsd\t{%2, %0|%0, %2}"
16188 [(set_attr "type" "sse")
16189 (set_attr "mode" "DF")])
16191 (define_expand "maxsf3"
16193 (set (match_operand:SF 0 "register_operand" "")
16194 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16195 (match_operand:SF 2 "nonimmediate_operand" ""))
16198 (clobber (reg:CC 17))])]
16202 (define_insn "*maxsf"
16203 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16204 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
16205 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16208 (clobber (reg:CC 17))]
16209 "TARGET_SSE && TARGET_IEEE_FP"
16212 (define_insn "*maxsf_nonieee"
16213 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16214 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16215 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16218 (clobber (reg:CC 17))]
16219 "TARGET_SSE && !TARGET_IEEE_FP
16220 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16224 [(set (match_operand:SF 0 "register_operand" "")
16225 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16226 (match_operand:SF 2 "nonimmediate_operand" ""))
16227 (match_operand:SF 3 "register_operand" "")
16228 (match_operand:SF 4 "nonimmediate_operand" "")))
16229 (clobber (reg:CC 17))]
16230 "SSE_REG_P (operands[0]) && reload_completed
16231 && ((operands_match_p (operands[1], operands[3])
16232 && operands_match_p (operands[2], operands[4]))
16233 || (operands_match_p (operands[1], operands[4])
16234 && operands_match_p (operands[2], operands[3])))"
16235 [(set (match_dup 0)
16236 (if_then_else:SF (gt (match_dup 1)
16242 [(set (match_operand:SF 0 "register_operand" "")
16243 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16244 (match_operand:SF 2 "register_operand" ""))
16245 (match_operand:SF 3 "register_operand" "")
16246 (match_operand:SF 4 "register_operand" "")))
16247 (clobber (reg:CC 17))]
16248 "FP_REG_P (operands[0]) && reload_completed
16249 && ((operands_match_p (operands[1], operands[3])
16250 && operands_match_p (operands[2], operands[4]))
16251 || (operands_match_p (operands[1], operands[4])
16252 && operands_match_p (operands[2], operands[3])))"
16253 [(set (reg:CCFP 17)
16254 (compare:CCFP (match_dup 1)
16257 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
16261 (define_insn "*maxsf_sse"
16262 [(set (match_operand:SF 0 "register_operand" "=x")
16263 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
16264 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16267 "TARGET_SSE && reload_completed"
16268 "maxss\t{%2, %0|%0, %2}"
16269 [(set_attr "type" "sse")
16270 (set_attr "mode" "SF")])
16272 (define_expand "maxdf3"
16274 (set (match_operand:DF 0 "register_operand" "")
16275 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16276 (match_operand:DF 2 "nonimmediate_operand" ""))
16279 (clobber (reg:CC 17))])]
16280 "TARGET_SSE2 && TARGET_SSE_MATH"
16283 (define_insn "*maxdf"
16284 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16285 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16286 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16289 (clobber (reg:CC 17))]
16290 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16293 (define_insn "*maxdf_nonieee"
16294 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16295 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16296 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16299 (clobber (reg:CC 17))]
16300 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16301 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16305 [(set (match_operand:DF 0 "register_operand" "")
16306 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16307 (match_operand:DF 2 "nonimmediate_operand" ""))
16308 (match_operand:DF 3 "register_operand" "")
16309 (match_operand:DF 4 "nonimmediate_operand" "")))
16310 (clobber (reg:CC 17))]
16311 "SSE_REG_P (operands[0]) && reload_completed
16312 && ((operands_match_p (operands[1], operands[3])
16313 && operands_match_p (operands[2], operands[4]))
16314 || (operands_match_p (operands[1], operands[4])
16315 && operands_match_p (operands[2], operands[3])))"
16316 [(set (match_dup 0)
16317 (if_then_else:DF (gt (match_dup 1)
16323 [(set (match_operand:DF 0 "register_operand" "")
16324 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16325 (match_operand:DF 2 "register_operand" ""))
16326 (match_operand:DF 3 "register_operand" "")
16327 (match_operand:DF 4 "register_operand" "")))
16328 (clobber (reg:CC 17))]
16329 "FP_REG_P (operands[0]) && reload_completed
16330 && ((operands_match_p (operands[1], operands[3])
16331 && operands_match_p (operands[2], operands[4]))
16332 || (operands_match_p (operands[1], operands[4])
16333 && operands_match_p (operands[2], operands[3])))"
16334 [(set (reg:CCFP 17)
16335 (compare:CCFP (match_dup 1)
16338 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16342 (define_insn "*maxdf_sse"
16343 [(set (match_operand:DF 0 "register_operand" "=Y")
16344 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16345 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16348 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16349 "maxsd\t{%2, %0|%0, %2}"
16350 [(set_attr "type" "sse")
16351 (set_attr "mode" "DF")])
16353 ;; Misc patterns (?)
16355 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
16356 ;; Otherwise there will be nothing to keep
16358 ;; [(set (reg ebp) (reg esp))]
16359 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16360 ;; (clobber (eflags)]
16361 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16363 ;; in proper program order.
16364 (define_expand "pro_epilogue_adjust_stack"
16365 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
16366 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16367 (match_operand:SI 2 "immediate_operand" "i,i")))
16368 (clobber (reg:CC 17))
16369 (clobber (mem:BLK (scratch)))])]
16374 emit_insn (gen_pro_epilogue_adjust_stack_rex64
16375 (operands[0], operands[1], operands[2]));
16380 (define_insn "*pro_epilogue_adjust_stack_1"
16381 [(set (match_operand:SI 0 "register_operand" "=r,r")
16382 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16383 (match_operand:SI 2 "immediate_operand" "i,i")))
16384 (clobber (reg:CC 17))
16385 (clobber (mem:BLK (scratch)))]
16388 switch (get_attr_type (insn))
16391 return "mov{l}\t{%1, %0|%0, %1}";
16394 if (GET_CODE (operands[2]) == CONST_INT
16395 && (INTVAL (operands[2]) == 128
16396 || (INTVAL (operands[2]) < 0
16397 && INTVAL (operands[2]) != -128)))
16399 operands[2] = GEN_INT (-INTVAL (operands[2]));
16400 return "sub{l}\t{%2, %0|%0, %2}";
16402 return "add{l}\t{%2, %0|%0, %2}";
16405 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16406 return "lea{l}\t{%a2, %0|%0, %a2}";
16412 [(set (attr "type")
16413 (cond [(eq_attr "alternative" "0")
16414 (const_string "alu")
16415 (match_operand:SI 2 "const0_operand" "")
16416 (const_string "imov")
16418 (const_string "lea")))
16419 (set_attr "mode" "SI")])
16421 (define_insn "pro_epilogue_adjust_stack_rex64"
16422 [(set (match_operand:DI 0 "register_operand" "=r,r")
16423 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16424 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16425 (clobber (reg:CC 17))
16426 (clobber (mem:BLK (scratch)))]
16429 switch (get_attr_type (insn))
16432 return "mov{q}\t{%1, %0|%0, %1}";
16435 if (GET_CODE (operands[2]) == CONST_INT
16436 && (INTVAL (operands[2]) == 128
16437 || (INTVAL (operands[2]) < 0
16438 && INTVAL (operands[2]) != -128)))
16440 operands[2] = GEN_INT (-INTVAL (operands[2]));
16441 return "sub{q}\t{%2, %0|%0, %2}";
16443 return "add{q}\t{%2, %0|%0, %2}";
16446 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16447 return "lea{q}\t{%a2, %0|%0, %a2}";
16453 [(set (attr "type")
16454 (cond [(eq_attr "alternative" "0")
16455 (const_string "alu")
16456 (match_operand:DI 2 "const0_operand" "")
16457 (const_string "imov")
16459 (const_string "lea")))
16460 (set_attr "mode" "DI")])
16463 ;; Placeholder for the conditional moves. This one is split either to SSE
16464 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16465 ;; fact is that compares supported by the cmp??ss instructions are exactly
16466 ;; swapped of those supported by cmove sequence.
16467 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16468 ;; supported by i387 comparisons and we do need to emit two conditional moves
16471 (define_insn "sse_movsfcc"
16472 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16473 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16474 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16475 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16476 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16477 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16478 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16479 (clobber (reg:CC 17))]
16481 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16482 && (!TARGET_IEEE_FP
16483 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16486 (define_insn "sse_movsfcc_eq"
16487 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16488 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16489 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16490 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16491 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16492 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16493 (clobber (reg:CC 17))]
16495 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16498 (define_insn "sse_movdfcc"
16499 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
16500 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16501 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
16502 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
16503 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
16504 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
16505 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16506 (clobber (reg:CC 17))]
16508 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16509 && (!TARGET_IEEE_FP
16510 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16513 (define_insn "sse_movdfcc_eq"
16514 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
16515 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
16516 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
16517 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
16518 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
16519 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16520 (clobber (reg:CC 17))]
16522 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16525 ;; For non-sse moves just expand the usual cmove sequence.
16527 [(set (match_operand 0 "register_operand" "")
16528 (if_then_else (match_operator 1 "comparison_operator"
16529 [(match_operand 4 "nonimmediate_operand" "")
16530 (match_operand 5 "register_operand" "")])
16531 (match_operand 2 "nonimmediate_operand" "")
16532 (match_operand 3 "nonimmediate_operand" "")))
16533 (clobber (match_operand 6 "" ""))
16534 (clobber (reg:CC 17))]
16535 "!SSE_REG_P (operands[0]) && reload_completed
16536 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
16539 ix86_compare_op0 = operands[5];
16540 ix86_compare_op1 = operands[4];
16541 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
16542 VOIDmode, operands[5], operands[4]);
16543 ix86_expand_fp_movcc (operands);
16547 ;; Split SSE based conditional move into seqence:
16548 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16549 ;; and op2, op0 - zero op2 if comparison was false
16550 ;; nand op0, op3 - load op3 to op0 if comparison was false
16551 ;; or op2, op0 - get the non-zero one into the result.
16553 [(set (match_operand 0 "register_operand" "")
16554 (if_then_else (match_operator 1 "sse_comparison_operator"
16555 [(match_operand 4 "register_operand" "")
16556 (match_operand 5 "nonimmediate_operand" "")])
16557 (match_operand 2 "register_operand" "")
16558 (match_operand 3 "register_operand" "")))
16559 (clobber (match_operand 6 "" ""))
16560 (clobber (reg:CC 17))]
16561 "SSE_REG_P (operands[0]) && reload_completed"
16562 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
16563 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
16564 (subreg:TI (match_dup 4) 0)))
16565 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
16566 (subreg:TI (match_dup 3) 0)))
16567 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
16568 (subreg:TI (match_dup 7) 0)))]
16570 /* If op2 == op3, op3 will be clobbered before it is used.
16571 This should be optimized out though. */
16572 if (operands_match_p (operands[2], operands[3]))
16574 PUT_MODE (operands[1], GET_MODE (operands[0]));
16575 if (operands_match_p (operands[0], operands[4]))
16576 operands[6] = operands[4], operands[7] = operands[2];
16578 operands[6] = operands[2], operands[7] = operands[4];
16581 ;; Special case of conditional move we can handle effectivly.
16582 ;; Do not brother with the integer/floating point case, since these are
16583 ;; bot considerably slower, unlike in the generic case.
16584 (define_insn "*sse_movsfcc_const0_1"
16585 [(set (match_operand:SF 0 "register_operand" "=&x")
16586 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16587 [(match_operand:SF 4 "register_operand" "0")
16588 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16589 (match_operand:SF 2 "register_operand" "x")
16590 (match_operand:SF 3 "const0_operand" "X")))]
16594 (define_insn "*sse_movsfcc_const0_2"
16595 [(set (match_operand:SF 0 "register_operand" "=&x")
16596 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16597 [(match_operand:SF 4 "register_operand" "0")
16598 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16599 (match_operand:SF 2 "const0_operand" "X")
16600 (match_operand:SF 3 "register_operand" "x")))]
16604 (define_insn "*sse_movsfcc_const0_3"
16605 [(set (match_operand:SF 0 "register_operand" "=&x")
16606 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16607 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16608 (match_operand:SF 5 "register_operand" "0")])
16609 (match_operand:SF 2 "register_operand" "x")
16610 (match_operand:SF 3 "const0_operand" "X")))]
16614 (define_insn "*sse_movsfcc_const0_4"
16615 [(set (match_operand:SF 0 "register_operand" "=&x")
16616 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16617 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16618 (match_operand:SF 5 "register_operand" "0")])
16619 (match_operand:SF 2 "const0_operand" "X")
16620 (match_operand:SF 3 "register_operand" "x")))]
16624 (define_insn "*sse_movdfcc_const0_1"
16625 [(set (match_operand:DF 0 "register_operand" "=&Y")
16626 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16627 [(match_operand:DF 4 "register_operand" "0")
16628 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
16629 (match_operand:DF 2 "register_operand" "Y")
16630 (match_operand:DF 3 "const0_operand" "X")))]
16634 (define_insn "*sse_movdfcc_const0_2"
16635 [(set (match_operand:DF 0 "register_operand" "=&Y")
16636 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16637 [(match_operand:DF 4 "register_operand" "0")
16638 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
16639 (match_operand:DF 2 "const0_operand" "X")
16640 (match_operand:DF 3 "register_operand" "Y")))]
16644 (define_insn "*sse_movdfcc_const0_3"
16645 [(set (match_operand:DF 0 "register_operand" "=&Y")
16646 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16647 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
16648 (match_operand:DF 5 "register_operand" "0")])
16649 (match_operand:DF 2 "register_operand" "Y")
16650 (match_operand:DF 3 "const0_operand" "X")))]
16654 (define_insn "*sse_movdfcc_const0_4"
16655 [(set (match_operand:DF 0 "register_operand" "=&Y")
16656 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16657 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
16658 (match_operand:DF 5 "register_operand" "0")])
16659 (match_operand:DF 2 "const0_operand" "X")
16660 (match_operand:DF 3 "register_operand" "Y")))]
16665 [(set (match_operand 0 "register_operand" "")
16666 (if_then_else (match_operator 1 "comparison_operator"
16667 [(match_operand 4 "register_operand" "")
16668 (match_operand 5 "nonimmediate_operand" "")])
16669 (match_operand 2 "nonmemory_operand" "")
16670 (match_operand 3 "nonmemory_operand" "")))]
16671 "SSE_REG_P (operands[0]) && reload_completed
16672 && (const0_operand (operands[2], GET_MODE (operands[0]))
16673 || const0_operand (operands[3], GET_MODE (operands[0])))"
16674 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16675 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16676 (subreg:TI (match_dup 7) 0)))]
16678 PUT_MODE (operands[1], GET_MODE (operands[0]));
16679 if (!sse_comparison_operator (operands[1], VOIDmode))
16681 rtx tmp = operands[5];
16682 operands[5] = operands[4];
16684 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16686 if (const0_operand (operands[2], GET_MODE (operands[0])))
16688 operands[7] = operands[3];
16689 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16694 operands[7] = operands[2];
16695 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
16699 (define_expand "allocate_stack_worker"
16700 [(match_operand:SI 0 "register_operand" "")]
16701 "TARGET_STACK_PROBE"
16704 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16706 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16710 (define_insn "allocate_stack_worker_1"
16711 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
16712 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16713 (clobber (match_dup 0))
16714 (clobber (reg:CC 17))]
16715 "!TARGET_64BIT && TARGET_STACK_PROBE"
16717 [(set_attr "type" "multi")
16718 (set_attr "length" "5")])
16720 (define_insn "allocate_stack_worker_rex64"
16721 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
16722 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16723 (clobber (match_dup 0))
16724 (clobber (reg:CC 17))]
16725 "TARGET_64BIT && TARGET_STACK_PROBE"
16727 [(set_attr "type" "multi")
16728 (set_attr "length" "5")])
16730 (define_expand "allocate_stack"
16731 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
16732 (minus:SI (reg:SI 7)
16733 (match_operand:SI 1 "general_operand" "")))
16734 (clobber (reg:CC 17))])
16735 (parallel [(set (reg:SI 7)
16736 (minus:SI (reg:SI 7) (match_dup 1)))
16737 (clobber (reg:CC 17))])]
16738 "TARGET_STACK_PROBE"
16740 #ifdef CHECK_STACK_LIMIT
16741 if (GET_CODE (operands[1]) == CONST_INT
16742 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16743 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
16747 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
16750 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16754 (define_expand "builtin_setjmp_receiver"
16755 [(label_ref (match_operand 0 "" ""))]
16756 "!TARGET_64BIT && flag_pic"
16758 emit_insn (gen_set_got (pic_offset_table_rtx));
16762 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16765 [(set (match_operand 0 "register_operand" "")
16766 (match_operator 3 "promotable_binary_operator"
16767 [(match_operand 1 "register_operand" "")
16768 (match_operand 2 "aligned_operand" "")]))
16769 (clobber (reg:CC 17))]
16770 "! TARGET_PARTIAL_REG_STALL && reload_completed
16771 && ((GET_MODE (operands[0]) == HImode
16772 && ((!optimize_size && !TARGET_FAST_PREFIX)
16773 || GET_CODE (operands[2]) != CONST_INT
16774 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16775 || (GET_MODE (operands[0]) == QImode
16776 && (TARGET_PROMOTE_QImode || optimize_size)))"
16777 [(parallel [(set (match_dup 0)
16778 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16779 (clobber (reg:CC 17))])]
16780 "operands[0] = gen_lowpart (SImode, operands[0]);
16781 operands[1] = gen_lowpart (SImode, operands[1]);
16782 if (GET_CODE (operands[3]) != ASHIFT)
16783 operands[2] = gen_lowpart (SImode, operands[2]);
16784 PUT_MODE (operands[3], SImode);")
16788 (compare (and (match_operand 1 "aligned_operand" "")
16789 (match_operand 2 "const_int_operand" ""))
16791 (set (match_operand 0 "register_operand" "")
16792 (and (match_dup 1) (match_dup 2)))]
16793 "! TARGET_PARTIAL_REG_STALL && reload_completed
16794 && ix86_match_ccmode (insn, CCNOmode)
16795 && (GET_MODE (operands[0]) == HImode
16796 || (GET_MODE (operands[0]) == QImode
16797 /* Ensure that the operand will remain sign extended immedaite. */
16798 && INTVAL (operands[2]) >= 0
16799 && (TARGET_PROMOTE_QImode || optimize_size)))"
16800 [(parallel [(set (reg:CCNO 17)
16801 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16804 (and:SI (match_dup 1) (match_dup 2)))])]
16806 = gen_int_mode (INTVAL (operands[2])
16807 & GET_MODE_MASK (GET_MODE (operands[0])),
16809 operands[0] = gen_lowpart (SImode, operands[0]);
16810 operands[1] = gen_lowpart (SImode, operands[1]);")
16812 ; Don't promote the QImode tests, as i386 don't have encoding of
16813 ; the test instruction with 32bit sign extended immediate and thus
16817 (compare (and (match_operand:HI 0 "aligned_operand" "")
16818 (match_operand:HI 1 "const_int_operand" ""))
16820 "! TARGET_PARTIAL_REG_STALL && reload_completed
16821 && ix86_match_ccmode (insn, CCNOmode)
16822 && GET_MODE (operands[0]) == HImode"
16823 [(set (reg:CCNO 17)
16824 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16827 = gen_int_mode (INTVAL (operands[1])
16828 & GET_MODE_MASK (GET_MODE (operands[0])),
16830 operands[0] = gen_lowpart (SImode, operands[0]);")
16833 [(set (match_operand 0 "register_operand" "")
16834 (neg (match_operand 1 "register_operand" "")))
16835 (clobber (reg:CC 17))]
16836 "! TARGET_PARTIAL_REG_STALL && reload_completed
16837 && (GET_MODE (operands[0]) == HImode
16838 || (GET_MODE (operands[0]) == QImode
16839 && (TARGET_PROMOTE_QImode || optimize_size)))"
16840 [(parallel [(set (match_dup 0)
16841 (neg:SI (match_dup 1)))
16842 (clobber (reg:CC 17))])]
16843 "operands[0] = gen_lowpart (SImode, operands[0]);
16844 operands[1] = gen_lowpart (SImode, operands[1]);")
16847 [(set (match_operand 0 "register_operand" "")
16848 (not (match_operand 1 "register_operand" "")))]
16849 "! TARGET_PARTIAL_REG_STALL && reload_completed
16850 && (GET_MODE (operands[0]) == HImode
16851 || (GET_MODE (operands[0]) == QImode
16852 && (TARGET_PROMOTE_QImode || optimize_size)))"
16853 [(set (match_dup 0)
16854 (not:SI (match_dup 1)))]
16855 "operands[0] = gen_lowpart (SImode, operands[0]);
16856 operands[1] = gen_lowpart (SImode, operands[1]);")
16859 [(set (match_operand 0 "register_operand" "")
16860 (if_then_else (match_operator 1 "comparison_operator"
16861 [(reg 17) (const_int 0)])
16862 (match_operand 2 "register_operand" "")
16863 (match_operand 3 "register_operand" "")))]
16864 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16865 && (GET_MODE (operands[0]) == HImode
16866 || (GET_MODE (operands[0]) == QImode
16867 && (TARGET_PROMOTE_QImode || optimize_size)))"
16868 [(set (match_dup 0)
16869 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16870 "operands[0] = gen_lowpart (SImode, operands[0]);
16871 operands[2] = gen_lowpart (SImode, operands[2]);
16872 operands[3] = gen_lowpart (SImode, operands[3]);")
16875 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16876 ;; transform a complex memory operation into two memory to register operations.
16878 ;; Don't push memory operands
16880 [(set (match_operand:SI 0 "push_operand" "")
16881 (match_operand:SI 1 "memory_operand" ""))
16882 (match_scratch:SI 2 "r")]
16883 "! optimize_size && ! TARGET_PUSH_MEMORY"
16884 [(set (match_dup 2) (match_dup 1))
16885 (set (match_dup 0) (match_dup 2))]
16889 [(set (match_operand:DI 0 "push_operand" "")
16890 (match_operand:DI 1 "memory_operand" ""))
16891 (match_scratch:DI 2 "r")]
16892 "! optimize_size && ! TARGET_PUSH_MEMORY"
16893 [(set (match_dup 2) (match_dup 1))
16894 (set (match_dup 0) (match_dup 2))]
16897 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16900 [(set (match_operand:SF 0 "push_operand" "")
16901 (match_operand:SF 1 "memory_operand" ""))
16902 (match_scratch:SF 2 "r")]
16903 "! optimize_size && ! TARGET_PUSH_MEMORY"
16904 [(set (match_dup 2) (match_dup 1))
16905 (set (match_dup 0) (match_dup 2))]
16909 [(set (match_operand:HI 0 "push_operand" "")
16910 (match_operand:HI 1 "memory_operand" ""))
16911 (match_scratch:HI 2 "r")]
16912 "! optimize_size && ! TARGET_PUSH_MEMORY"
16913 [(set (match_dup 2) (match_dup 1))
16914 (set (match_dup 0) (match_dup 2))]
16918 [(set (match_operand:QI 0 "push_operand" "")
16919 (match_operand:QI 1 "memory_operand" ""))
16920 (match_scratch:QI 2 "q")]
16921 "! optimize_size && ! TARGET_PUSH_MEMORY"
16922 [(set (match_dup 2) (match_dup 1))
16923 (set (match_dup 0) (match_dup 2))]
16926 ;; Don't move an immediate directly to memory when the instruction
16929 [(match_scratch:SI 1 "r")
16930 (set (match_operand:SI 0 "memory_operand" "")
16933 && ! TARGET_USE_MOV0
16934 && TARGET_SPLIT_LONG_MOVES
16935 && get_attr_length (insn) >= ix86_cost->large_insn
16936 && peep2_regno_dead_p (0, FLAGS_REG)"
16937 [(parallel [(set (match_dup 1) (const_int 0))
16938 (clobber (reg:CC 17))])
16939 (set (match_dup 0) (match_dup 1))]
16943 [(match_scratch:HI 1 "r")
16944 (set (match_operand:HI 0 "memory_operand" "")
16947 && ! TARGET_USE_MOV0
16948 && TARGET_SPLIT_LONG_MOVES
16949 && get_attr_length (insn) >= ix86_cost->large_insn
16950 && peep2_regno_dead_p (0, FLAGS_REG)"
16951 [(parallel [(set (match_dup 2) (const_int 0))
16952 (clobber (reg:CC 17))])
16953 (set (match_dup 0) (match_dup 1))]
16954 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16957 [(match_scratch:QI 1 "q")
16958 (set (match_operand:QI 0 "memory_operand" "")
16961 && ! TARGET_USE_MOV0
16962 && TARGET_SPLIT_LONG_MOVES
16963 && get_attr_length (insn) >= ix86_cost->large_insn
16964 && peep2_regno_dead_p (0, FLAGS_REG)"
16965 [(parallel [(set (match_dup 2) (const_int 0))
16966 (clobber (reg:CC 17))])
16967 (set (match_dup 0) (match_dup 1))]
16968 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16971 [(match_scratch:SI 2 "r")
16972 (set (match_operand:SI 0 "memory_operand" "")
16973 (match_operand:SI 1 "immediate_operand" ""))]
16975 && get_attr_length (insn) >= ix86_cost->large_insn
16976 && TARGET_SPLIT_LONG_MOVES"
16977 [(set (match_dup 2) (match_dup 1))
16978 (set (match_dup 0) (match_dup 2))]
16982 [(match_scratch:HI 2 "r")
16983 (set (match_operand:HI 0 "memory_operand" "")
16984 (match_operand:HI 1 "immediate_operand" ""))]
16985 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16986 && TARGET_SPLIT_LONG_MOVES"
16987 [(set (match_dup 2) (match_dup 1))
16988 (set (match_dup 0) (match_dup 2))]
16992 [(match_scratch:QI 2 "q")
16993 (set (match_operand:QI 0 "memory_operand" "")
16994 (match_operand:QI 1 "immediate_operand" ""))]
16995 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16996 && TARGET_SPLIT_LONG_MOVES"
16997 [(set (match_dup 2) (match_dup 1))
16998 (set (match_dup 0) (match_dup 2))]
17001 ;; Don't compare memory with zero, load and use a test instead.
17004 (compare (match_operand:SI 0 "memory_operand" "")
17006 (match_scratch:SI 3 "r")]
17007 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17008 [(set (match_dup 3) (match_dup 0))
17009 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
17012 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17013 ;; Don't split NOTs with a displacement operand, because resulting XOR
17014 ;; will not be pariable anyway.
17016 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
17017 ;; represented using a modRM byte. The XOR replacement is long decoded,
17018 ;; so this split helps here as well.
17020 ;; Note: Can't do this as a regular split because we can't get proper
17021 ;; lifetime information then.
17024 [(set (match_operand:SI 0 "nonimmediate_operand" "")
17025 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
17027 && peep2_regno_dead_p (0, FLAGS_REG)
17028 && ((TARGET_PENTIUM
17029 && (GET_CODE (operands[0]) != MEM
17030 || !memory_displacement_operand (operands[0], SImode)))
17031 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
17032 [(parallel [(set (match_dup 0)
17033 (xor:SI (match_dup 1) (const_int -1)))
17034 (clobber (reg:CC 17))])]
17038 [(set (match_operand:HI 0 "nonimmediate_operand" "")
17039 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
17041 && peep2_regno_dead_p (0, FLAGS_REG)
17042 && ((TARGET_PENTIUM
17043 && (GET_CODE (operands[0]) != MEM
17044 || !memory_displacement_operand (operands[0], HImode)))
17045 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
17046 [(parallel [(set (match_dup 0)
17047 (xor:HI (match_dup 1) (const_int -1)))
17048 (clobber (reg:CC 17))])]
17052 [(set (match_operand:QI 0 "nonimmediate_operand" "")
17053 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
17055 && peep2_regno_dead_p (0, FLAGS_REG)
17056 && ((TARGET_PENTIUM
17057 && (GET_CODE (operands[0]) != MEM
17058 || !memory_displacement_operand (operands[0], QImode)))
17059 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
17060 [(parallel [(set (match_dup 0)
17061 (xor:QI (match_dup 1) (const_int -1)))
17062 (clobber (reg:CC 17))])]
17065 ;; Non pairable "test imm, reg" instructions can be translated to
17066 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17067 ;; byte opcode instead of two, have a short form for byte operands),
17068 ;; so do it for other CPUs as well. Given that the value was dead,
17069 ;; this should not create any new dependencies. Pass on the sub-word
17070 ;; versions if we're concerned about partial register stalls.
17074 (compare (and:SI (match_operand:SI 0 "register_operand" "")
17075 (match_operand:SI 1 "immediate_operand" ""))
17077 "ix86_match_ccmode (insn, CCNOmode)
17078 && (true_regnum (operands[0]) != 0
17079 || (GET_CODE (operands[1]) == CONST_INT
17080 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
17081 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17083 [(set (reg:CCNO 17)
17084 (compare:CCNO (and:SI (match_dup 0)
17088 (and:SI (match_dup 0) (match_dup 1)))])]
17091 ;; We don't need to handle HImode case, because it will be promoted to SImode
17092 ;; on ! TARGET_PARTIAL_REG_STALL
17096 (compare (and:QI (match_operand:QI 0 "register_operand" "")
17097 (match_operand:QI 1 "immediate_operand" ""))
17099 "! TARGET_PARTIAL_REG_STALL
17100 && ix86_match_ccmode (insn, CCNOmode)
17101 && true_regnum (operands[0]) != 0
17102 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17104 [(set (reg:CCNO 17)
17105 (compare:CCNO (and:QI (match_dup 0)
17109 (and:QI (match_dup 0) (match_dup 1)))])]
17117 (match_operand 0 "ext_register_operand" "")
17120 (match_operand 1 "const_int_operand" ""))
17122 "! TARGET_PARTIAL_REG_STALL
17123 && ix86_match_ccmode (insn, CCNOmode)
17124 && true_regnum (operands[0]) != 0
17125 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17126 [(parallel [(set (reg:CCNO 17)
17135 (set (zero_extract:SI (match_dup 0)
17146 ;; Don't do logical operations with memory inputs.
17148 [(match_scratch:SI 2 "r")
17149 (parallel [(set (match_operand:SI 0 "register_operand" "")
17150 (match_operator:SI 3 "arith_or_logical_operator"
17152 (match_operand:SI 1 "memory_operand" "")]))
17153 (clobber (reg:CC 17))])]
17154 "! optimize_size && ! TARGET_READ_MODIFY"
17155 [(set (match_dup 2) (match_dup 1))
17156 (parallel [(set (match_dup 0)
17157 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
17158 (clobber (reg:CC 17))])]
17162 [(match_scratch:SI 2 "r")
17163 (parallel [(set (match_operand:SI 0 "register_operand" "")
17164 (match_operator:SI 3 "arith_or_logical_operator"
17165 [(match_operand:SI 1 "memory_operand" "")
17167 (clobber (reg:CC 17))])]
17168 "! optimize_size && ! TARGET_READ_MODIFY"
17169 [(set (match_dup 2) (match_dup 1))
17170 (parallel [(set (match_dup 0)
17171 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
17172 (clobber (reg:CC 17))])]
17175 ; Don't do logical operations with memory outputs
17177 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
17178 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
17179 ; the same decoder scheduling characteristics as the original.
17182 [(match_scratch:SI 2 "r")
17183 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17184 (match_operator:SI 3 "arith_or_logical_operator"
17186 (match_operand:SI 1 "nonmemory_operand" "")]))
17187 (clobber (reg:CC 17))])]
17188 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17189 [(set (match_dup 2) (match_dup 0))
17190 (parallel [(set (match_dup 2)
17191 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
17192 (clobber (reg:CC 17))])
17193 (set (match_dup 0) (match_dup 2))]
17197 [(match_scratch:SI 2 "r")
17198 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17199 (match_operator:SI 3 "arith_or_logical_operator"
17200 [(match_operand:SI 1 "nonmemory_operand" "")
17202 (clobber (reg:CC 17))])]
17203 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17204 [(set (match_dup 2) (match_dup 0))
17205 (parallel [(set (match_dup 2)
17206 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17207 (clobber (reg:CC 17))])
17208 (set (match_dup 0) (match_dup 2))]
17211 ;; Attempt to always use XOR for zeroing registers.
17213 [(set (match_operand 0 "register_operand" "")
17215 "(GET_MODE (operands[0]) == QImode
17216 || GET_MODE (operands[0]) == HImode
17217 || GET_MODE (operands[0]) == SImode
17218 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17219 && (! TARGET_USE_MOV0 || optimize_size)
17220 && peep2_regno_dead_p (0, FLAGS_REG)"
17221 [(parallel [(set (match_dup 0) (const_int 0))
17222 (clobber (reg:CC 17))])]
17223 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17224 true_regnum (operands[0]));")
17227 [(set (strict_low_part (match_operand 0 "register_operand" ""))
17229 "(GET_MODE (operands[0]) == QImode
17230 || GET_MODE (operands[0]) == HImode)
17231 && (! TARGET_USE_MOV0 || optimize_size)
17232 && peep2_regno_dead_p (0, FLAGS_REG)"
17233 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
17234 (clobber (reg:CC 17))])])
17236 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
17238 [(set (match_operand 0 "register_operand" "")
17240 "(GET_MODE (operands[0]) == HImode
17241 || GET_MODE (operands[0]) == SImode
17242 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17243 && (optimize_size || TARGET_PENTIUM)
17244 && peep2_regno_dead_p (0, FLAGS_REG)"
17245 [(parallel [(set (match_dup 0) (const_int -1))
17246 (clobber (reg:CC 17))])]
17247 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17248 true_regnum (operands[0]));")
17250 ;; Attempt to convert simple leas to adds. These can be created by
17253 [(set (match_operand:SI 0 "register_operand" "")
17254 (plus:SI (match_dup 0)
17255 (match_operand:SI 1 "nonmemory_operand" "")))]
17256 "peep2_regno_dead_p (0, FLAGS_REG)"
17257 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
17258 (clobber (reg:CC 17))])]
17262 [(set (match_operand:SI 0 "register_operand" "")
17263 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
17264 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
17265 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
17266 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
17267 (clobber (reg:CC 17))])]
17268 "operands[2] = gen_lowpart (SImode, operands[2]);")
17271 [(set (match_operand:DI 0 "register_operand" "")
17272 (plus:DI (match_dup 0)
17273 (match_operand:DI 1 "x86_64_general_operand" "")))]
17274 "peep2_regno_dead_p (0, FLAGS_REG)"
17275 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
17276 (clobber (reg:CC 17))])]
17280 [(set (match_operand:SI 0 "register_operand" "")
17281 (mult:SI (match_dup 0)
17282 (match_operand:SI 1 "const_int_operand" "")))]
17283 "exact_log2 (INTVAL (operands[1])) >= 0
17284 && peep2_regno_dead_p (0, FLAGS_REG)"
17285 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17286 (clobber (reg:CC 17))])]
17287 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17290 [(set (match_operand:DI 0 "register_operand" "")
17291 (mult:DI (match_dup 0)
17292 (match_operand:DI 1 "const_int_operand" "")))]
17293 "exact_log2 (INTVAL (operands[1])) >= 0
17294 && peep2_regno_dead_p (0, FLAGS_REG)"
17295 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17296 (clobber (reg:CC 17))])]
17297 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17300 [(set (match_operand:SI 0 "register_operand" "")
17301 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17302 (match_operand:DI 2 "const_int_operand" "")) 0))]
17303 "exact_log2 (INTVAL (operands[1])) >= 0
17304 && REGNO (operands[0]) == REGNO (operands[1])
17305 && peep2_regno_dead_p (0, FLAGS_REG)"
17306 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17307 (clobber (reg:CC 17))])]
17308 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17310 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17311 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17312 ;; many CPUs it is also faster, since special hardware to avoid esp
17313 ;; dependencies is present.
17315 ;; While some of these conversions may be done using splitters, we use peepholes
17316 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17318 ;; Convert prologue esp subtractions to push.
17319 ;; We need register to push. In order to keep verify_flow_info happy we have
17321 ;; - use scratch and clobber it in order to avoid dependencies
17322 ;; - use already live register
17323 ;; We can't use the second way right now, since there is no reliable way how to
17324 ;; verify that given register is live. First choice will also most likely in
17325 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17326 ;; call clobbered registers are dead. We may want to use base pointer as an
17327 ;; alternative when no register is available later.
17330 [(match_scratch:SI 0 "r")
17331 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17332 (clobber (reg:CC 17))
17333 (clobber (mem:BLK (scratch)))])]
17334 "optimize_size || !TARGET_SUB_ESP_4"
17335 [(clobber (match_dup 0))
17336 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17337 (clobber (mem:BLK (scratch)))])])
17340 [(match_scratch:SI 0 "r")
17341 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17342 (clobber (reg:CC 17))
17343 (clobber (mem:BLK (scratch)))])]
17344 "optimize_size || !TARGET_SUB_ESP_8"
17345 [(clobber (match_dup 0))
17346 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17347 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17348 (clobber (mem:BLK (scratch)))])])
17350 ;; Convert esp subtractions to push.
17352 [(match_scratch:SI 0 "r")
17353 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17354 (clobber (reg:CC 17))])]
17355 "optimize_size || !TARGET_SUB_ESP_4"
17356 [(clobber (match_dup 0))
17357 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17360 [(match_scratch:SI 0 "r")
17361 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17362 (clobber (reg:CC 17))])]
17363 "optimize_size || !TARGET_SUB_ESP_8"
17364 [(clobber (match_dup 0))
17365 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17366 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17368 ;; Convert epilogue deallocator to pop.
17370 [(match_scratch:SI 0 "r")
17371 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17372 (clobber (reg:CC 17))
17373 (clobber (mem:BLK (scratch)))])]
17374 "optimize_size || !TARGET_ADD_ESP_4"
17375 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17376 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17377 (clobber (mem:BLK (scratch)))])]
17380 ;; Two pops case is tricky, since pop causes dependency on destination register.
17381 ;; We use two registers if available.
17383 [(match_scratch:SI 0 "r")
17384 (match_scratch:SI 1 "r")
17385 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17386 (clobber (reg:CC 17))
17387 (clobber (mem:BLK (scratch)))])]
17388 "optimize_size || !TARGET_ADD_ESP_8"
17389 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17390 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17391 (clobber (mem:BLK (scratch)))])
17392 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17393 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17397 [(match_scratch:SI 0 "r")
17398 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17399 (clobber (reg:CC 17))
17400 (clobber (mem:BLK (scratch)))])]
17402 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17403 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17404 (clobber (mem:BLK (scratch)))])
17405 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17406 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17409 ;; Convert esp additions to pop.
17411 [(match_scratch:SI 0 "r")
17412 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17413 (clobber (reg:CC 17))])]
17415 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17416 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17419 ;; Two pops case is tricky, since pop causes dependency on destination register.
17420 ;; We use two registers if available.
17422 [(match_scratch:SI 0 "r")
17423 (match_scratch:SI 1 "r")
17424 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17425 (clobber (reg:CC 17))])]
17427 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17428 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17429 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17430 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17434 [(match_scratch:SI 0 "r")
17435 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17436 (clobber (reg:CC 17))])]
17438 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17439 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17440 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17441 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17444 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17445 ;; required and register dies.
17448 (compare (match_operand:SI 0 "register_operand" "")
17449 (match_operand:SI 1 "incdec_operand" "")))]
17450 "ix86_match_ccmode (insn, CCGCmode)
17451 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17452 [(parallel [(set (reg:CCGC 17)
17453 (compare:CCGC (match_dup 0)
17455 (clobber (match_dup 0))])]
17460 (compare (match_operand:HI 0 "register_operand" "")
17461 (match_operand:HI 1 "incdec_operand" "")))]
17462 "ix86_match_ccmode (insn, CCGCmode)
17463 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17464 [(parallel [(set (reg:CCGC 17)
17465 (compare:CCGC (match_dup 0)
17467 (clobber (match_dup 0))])]
17472 (compare (match_operand:QI 0 "register_operand" "")
17473 (match_operand:QI 1 "incdec_operand" "")))]
17474 "ix86_match_ccmode (insn, CCGCmode)
17475 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17476 [(parallel [(set (reg:CCGC 17)
17477 (compare:CCGC (match_dup 0)
17479 (clobber (match_dup 0))])]
17482 ;; Convert compares with 128 to shorter add -128
17485 (compare (match_operand:SI 0 "register_operand" "")
17487 "ix86_match_ccmode (insn, CCGCmode)
17488 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17489 [(parallel [(set (reg:CCGC 17)
17490 (compare:CCGC (match_dup 0)
17492 (clobber (match_dup 0))])]
17497 (compare (match_operand:HI 0 "register_operand" "")
17499 "ix86_match_ccmode (insn, CCGCmode)
17500 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17501 [(parallel [(set (reg:CCGC 17)
17502 (compare:CCGC (match_dup 0)
17504 (clobber (match_dup 0))])]
17508 [(match_scratch:DI 0 "r")
17509 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17510 (clobber (reg:CC 17))
17511 (clobber (mem:BLK (scratch)))])]
17512 "optimize_size || !TARGET_SUB_ESP_4"
17513 [(clobber (match_dup 0))
17514 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17515 (clobber (mem:BLK (scratch)))])])
17518 [(match_scratch:DI 0 "r")
17519 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17520 (clobber (reg:CC 17))
17521 (clobber (mem:BLK (scratch)))])]
17522 "optimize_size || !TARGET_SUB_ESP_8"
17523 [(clobber (match_dup 0))
17524 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17525 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17526 (clobber (mem:BLK (scratch)))])])
17528 ;; Convert esp subtractions to push.
17530 [(match_scratch:DI 0 "r")
17531 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17532 (clobber (reg:CC 17))])]
17533 "optimize_size || !TARGET_SUB_ESP_4"
17534 [(clobber (match_dup 0))
17535 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17538 [(match_scratch:DI 0 "r")
17539 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17540 (clobber (reg:CC 17))])]
17541 "optimize_size || !TARGET_SUB_ESP_8"
17542 [(clobber (match_dup 0))
17543 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17544 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17546 ;; Convert epilogue deallocator to pop.
17548 [(match_scratch:DI 0 "r")
17549 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17550 (clobber (reg:CC 17))
17551 (clobber (mem:BLK (scratch)))])]
17552 "optimize_size || !TARGET_ADD_ESP_4"
17553 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17554 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17555 (clobber (mem:BLK (scratch)))])]
17558 ;; Two pops case is tricky, since pop causes dependency on destination register.
17559 ;; We use two registers if available.
17561 [(match_scratch:DI 0 "r")
17562 (match_scratch:DI 1 "r")
17563 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17564 (clobber (reg:CC 17))
17565 (clobber (mem:BLK (scratch)))])]
17566 "optimize_size || !TARGET_ADD_ESP_8"
17567 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17568 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17569 (clobber (mem:BLK (scratch)))])
17570 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17571 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17575 [(match_scratch:DI 0 "r")
17576 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17577 (clobber (reg:CC 17))
17578 (clobber (mem:BLK (scratch)))])]
17580 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17581 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17582 (clobber (mem:BLK (scratch)))])
17583 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17584 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17587 ;; Convert esp additions to pop.
17589 [(match_scratch:DI 0 "r")
17590 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17591 (clobber (reg:CC 17))])]
17593 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17594 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17597 ;; Two pops case is tricky, since pop causes dependency on destination register.
17598 ;; We use two registers if available.
17600 [(match_scratch:DI 0 "r")
17601 (match_scratch:DI 1 "r")
17602 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17603 (clobber (reg:CC 17))])]
17605 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17606 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17607 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17608 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17612 [(match_scratch:DI 0 "r")
17613 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17614 (clobber (reg:CC 17))])]
17616 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17617 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17618 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17619 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17622 ;; Call-value patterns last so that the wildcard operand does not
17623 ;; disrupt insn-recog's switch tables.
17625 (define_insn "*call_value_pop_0"
17626 [(set (match_operand 0 "" "")
17627 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17628 (match_operand:SI 2 "" "")))
17629 (set (reg:SI 7) (plus:SI (reg:SI 7)
17630 (match_operand:SI 3 "immediate_operand" "")))]
17633 if (SIBLING_CALL_P (insn))
17636 return "call\t%P1";
17638 [(set_attr "type" "callv")])
17640 (define_insn "*call_value_pop_1"
17641 [(set (match_operand 0 "" "")
17642 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17643 (match_operand:SI 2 "" "")))
17644 (set (reg:SI 7) (plus:SI (reg:SI 7)
17645 (match_operand:SI 3 "immediate_operand" "i")))]
17648 if (constant_call_address_operand (operands[1], QImode))
17650 if (SIBLING_CALL_P (insn))
17653 return "call\t%P1";
17655 if (SIBLING_CALL_P (insn))
17658 return "call\t%A1";
17660 [(set_attr "type" "callv")])
17662 (define_insn "*call_value_0"
17663 [(set (match_operand 0 "" "")
17664 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17665 (match_operand:SI 2 "" "")))]
17668 if (SIBLING_CALL_P (insn))
17671 return "call\t%P1";
17673 [(set_attr "type" "callv")])
17675 (define_insn "*call_value_0_rex64"
17676 [(set (match_operand 0 "" "")
17677 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
17678 (match_operand:DI 2 "const_int_operand" "")))]
17681 if (SIBLING_CALL_P (insn))
17684 return "call\t%P1";
17686 [(set_attr "type" "callv")])
17688 (define_insn "*call_value_1"
17689 [(set (match_operand 0 "" "")
17690 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17691 (match_operand:SI 2 "" "")))]
17694 if (constant_call_address_operand (operands[1], QImode))
17696 if (SIBLING_CALL_P (insn))
17699 return "call\t%P1";
17701 if (SIBLING_CALL_P (insn))
17702 return "jmp\t%*%1";
17704 return "call\t%*%1";
17706 [(set_attr "type" "callv")])
17708 (define_insn "*call_value_1_rex64"
17709 [(set (match_operand 0 "" "")
17710 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
17711 (match_operand:DI 2 "" "")))]
17714 if (constant_call_address_operand (operands[1], QImode))
17716 if (SIBLING_CALL_P (insn))
17719 return "call\t%P1";
17721 if (SIBLING_CALL_P (insn))
17724 return "call\t%A1";
17726 [(set_attr "type" "callv")])
17728 (define_insn "trap"
17729 [(trap_if (const_int 1) (const_int 5))]
17733 ;;; ix86 doesn't have conditional trap instructions, but we fake them
17734 ;;; for the sake of bounds checking. By emitting bounds checks as
17735 ;;; conditional traps rather than as conditional jumps around
17736 ;;; unconditional traps we avoid introducing spurious basic-block
17737 ;;; boundaries and facilitate elimination of redundant checks. In
17738 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
17741 ;;; FIXME: Static branch prediction rules for ix86 are such that
17742 ;;; forward conditional branches predict as untaken. As implemented
17743 ;;; below, pseudo conditional traps violate that rule. We should use
17744 ;;; .pushsection/.popsection to place all of the `int 5's in a special
17745 ;;; section loaded at the end of the text segment and branch forward
17746 ;;; there on bounds-failure, and then jump back immediately (in case
17747 ;;; the system chooses to ignore bounds violations, or to report
17748 ;;; violations and continue execution).
17750 (define_expand "conditional_trap"
17751 [(trap_if (match_operator 0 "comparison_operator"
17752 [(match_dup 2) (const_int 0)])
17753 (match_operand 1 "const_int_operand" ""))]
17756 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
17757 ix86_expand_compare (GET_CODE (operands[0]),
17763 (define_insn "*conditional_trap_1"
17764 [(trap_if (match_operator 0 "comparison_operator"
17765 [(reg 17) (const_int 0)])
17766 (match_operand 1 "const_int_operand" ""))]
17769 operands[2] = gen_label_rtx ();
17770 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
17771 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
17772 CODE_LABEL_NUMBER (operands[2]));
17776 ;; Pentium III SIMD instructions.
17778 ;; Moves for SSE/MMX regs.
17780 (define_insn "movv4sf_internal"
17781 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17782 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x"))]
17784 ;; @@@ let's try to use movaps here.
17785 "movaps\t{%1, %0|%0, %1}"
17786 [(set_attr "type" "ssemov")
17787 (set_attr "mode" "V4SF")])
17789 (define_insn "movv4si_internal"
17790 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17791 (match_operand:V4SI 1 "nonimmediate_operand" "xm,x"))]
17793 ;; @@@ let's try to use movaps here.
17794 "movaps\t{%1, %0|%0, %1}"
17795 [(set_attr "type" "ssemov")
17796 (set_attr "mode" "V4SF")])
17798 (define_insn "movv8qi_internal"
17799 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17800 (match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
17802 "movq\t{%1, %0|%0, %1}"
17803 [(set_attr "type" "mmxmov")
17804 (set_attr "mode" "DI")])
17806 (define_insn "movv4hi_internal"
17807 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17808 (match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
17810 "movq\t{%1, %0|%0, %1}"
17811 [(set_attr "type" "mmxmov")
17812 (set_attr "mode" "DI")])
17814 (define_insn "movv2si_internal"
17815 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17816 (match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
17818 "movq\t{%1, %0|%0, %1}"
17819 [(set_attr "type" "mmxcvt")
17820 (set_attr "mode" "DI")])
17822 (define_insn "movv2sf_internal"
17823 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
17824 (match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
17826 "movq\\t{%1, %0|%0, %1}"
17827 [(set_attr "type" "mmxcvt")
17828 (set_attr "mode" "DI")])
17830 (define_expand "movti"
17831 [(set (match_operand:TI 0 "general_operand" "")
17832 (match_operand:TI 1 "general_operand" ""))]
17833 "TARGET_SSE || TARGET_64BIT"
17836 ix86_expand_move (TImode, operands);
17838 ix86_expand_vector_move (TImode, operands);
17842 (define_insn "movv2df_internal"
17843 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
17844 (match_operand:V2DF 1 "general_operand" "xm,x"))]
17846 ;; @@@ let's try to use movaps here.
17847 "movapd\t{%1, %0|%0, %1}"
17848 [(set_attr "type" "ssemov")
17849 (set_attr "mode" "V2DF")])
17851 (define_insn "movv8hi_internal"
17852 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
17853 (match_operand:V8HI 1 "general_operand" "xm,x"))]
17855 ;; @@@ let's try to use movaps here.
17856 "movaps\t{%1, %0|%0, %1}"
17857 [(set_attr "type" "ssemov")
17858 (set_attr "mode" "V4SF")])
17860 (define_insn "movv16qi_internal"
17861 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
17862 (match_operand:V16QI 1 "general_operand" "xm,x"))]
17864 ;; @@@ let's try to use movaps here.
17865 "movaps\t{%1, %0|%0, %1}"
17866 [(set_attr "type" "ssemov")
17867 (set_attr "mode" "V4SF")])
17869 (define_expand "movv2df"
17870 [(set (match_operand:V2DF 0 "general_operand" "")
17871 (match_operand:V2DF 1 "general_operand" ""))]
17874 ix86_expand_vector_move (V2DFmode, operands);
17878 (define_expand "movv8hi"
17879 [(set (match_operand:V8HI 0 "general_operand" "")
17880 (match_operand:V8HI 1 "general_operand" ""))]
17883 ix86_expand_vector_move (V8HImode, operands);
17887 (define_expand "movv16qi"
17888 [(set (match_operand:V16QI 0 "general_operand" "")
17889 (match_operand:V16QI 1 "general_operand" ""))]
17892 ix86_expand_vector_move (V16QImode, operands);
17896 (define_expand "movv4sf"
17897 [(set (match_operand:V4SF 0 "general_operand" "")
17898 (match_operand:V4SF 1 "general_operand" ""))]
17901 ix86_expand_vector_move (V4SFmode, operands);
17905 (define_expand "movv4si"
17906 [(set (match_operand:V4SI 0 "general_operand" "")
17907 (match_operand:V4SI 1 "general_operand" ""))]
17910 ix86_expand_vector_move (V4SImode, operands);
17914 (define_expand "movv2si"
17915 [(set (match_operand:V2SI 0 "general_operand" "")
17916 (match_operand:V2SI 1 "general_operand" ""))]
17919 ix86_expand_vector_move (V2SImode, operands);
17923 (define_expand "movv4hi"
17924 [(set (match_operand:V4HI 0 "general_operand" "")
17925 (match_operand:V4HI 1 "general_operand" ""))]
17928 ix86_expand_vector_move (V4HImode, operands);
17932 (define_expand "movv8qi"
17933 [(set (match_operand:V8QI 0 "general_operand" "")
17934 (match_operand:V8QI 1 "general_operand" ""))]
17937 ix86_expand_vector_move (V8QImode, operands);
17941 (define_expand "movv2sf"
17942 [(set (match_operand:V2SF 0 "general_operand" "")
17943 (match_operand:V2SF 1 "general_operand" ""))]
17946 ix86_expand_vector_move (V2SFmode, operands);
17950 (define_insn_and_split "*pushti"
17951 [(set (match_operand:TI 0 "push_operand" "=<")
17952 (match_operand:TI 1 "nonmemory_operand" "x"))]
17956 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17957 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17959 [(set_attr "type" "multi")])
17961 (define_insn_and_split "*pushv2df"
17962 [(set (match_operand:V2DF 0 "push_operand" "=<")
17963 (match_operand:V2DF 1 "nonmemory_operand" "x"))]
17967 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17968 (set (mem:V2DF (reg:SI 7)) (match_dup 1))]
17970 [(set_attr "type" "multi")])
17972 (define_insn_and_split "*pushv8hi"
17973 [(set (match_operand:V8HI 0 "push_operand" "=<")
17974 (match_operand:V8HI 1 "nonmemory_operand" "x"))]
17978 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17979 (set (mem:V8HI (reg:SI 7)) (match_dup 1))]
17981 [(set_attr "type" "multi")])
17983 (define_insn_and_split "*pushv16qi"
17984 [(set (match_operand:V16QI 0 "push_operand" "=<")
17985 (match_operand:V16QI 1 "nonmemory_operand" "x"))]
17989 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17990 (set (mem:V16QI (reg:SI 7)) (match_dup 1))]
17992 [(set_attr "type" "multi")])
17994 (define_insn_and_split "*pushv4sf"
17995 [(set (match_operand:V4SF 0 "push_operand" "=<")
17996 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
18000 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18001 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
18003 [(set_attr "type" "multi")])
18005 (define_insn_and_split "*pushv4si"
18006 [(set (match_operand:V4SI 0 "push_operand" "=<")
18007 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
18011 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18012 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
18014 [(set_attr "type" "multi")])
18016 (define_insn_and_split "*pushv2si"
18017 [(set (match_operand:V2SI 0 "push_operand" "=<")
18018 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
18022 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18023 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
18025 [(set_attr "type" "mmx")])
18027 (define_insn_and_split "*pushv4hi"
18028 [(set (match_operand:V4HI 0 "push_operand" "=<")
18029 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
18033 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18034 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
18036 [(set_attr "type" "mmx")])
18038 (define_insn_and_split "*pushv8qi"
18039 [(set (match_operand:V8QI 0 "push_operand" "=<")
18040 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
18044 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18045 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
18047 [(set_attr "type" "mmx")])
18049 (define_insn_and_split "*pushv2sf"
18050 [(set (match_operand:V2SF 0 "push_operand" "=<")
18051 (match_operand:V2SF 1 "nonmemory_operand" "y"))]
18055 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18056 (set (mem:V2SF (reg:SI 7)) (match_dup 1))]
18058 [(set_attr "type" "mmx")])
18060 (define_insn "movti_internal"
18061 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
18062 (match_operand:TI 1 "general_operand" "O,xm,x"))]
18063 "TARGET_SSE && !TARGET_64BIT"
18066 movaps\t{%1, %0|%0, %1}
18067 movaps\t{%1, %0|%0, %1}"
18068 [(set_attr "type" "ssemov,ssemov,ssemov")
18069 (set_attr "mode" "V4SF")])
18071 (define_insn "*movti_rex64"
18072 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x")
18073 (match_operand:TI 1 "general_operand" "riFo,riF,O,x,m"))]
18075 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18080 movaps\\t{%1, %0|%0, %1}
18081 movaps\\t{%1, %0|%0, %1}"
18082 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
18083 (set_attr "mode" "V4SF")])
18086 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18087 (match_operand:TI 1 "general_operand" ""))]
18088 "reload_completed && !SSE_REG_P (operands[0])
18089 && !SSE_REG_P (operands[1])"
18091 "ix86_split_long_move (operands); DONE;")
18093 ;; These two patterns are useful for specifying exactly whether to use
18094 ;; movaps or movups
18095 (define_insn "sse_movaps"
18096 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18097 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
18101 movaps\t{%1, %0|%0, %1}
18102 movaps\t{%1, %0|%0, %1}"
18103 [(set_attr "type" "ssemov,ssemov")
18104 (set_attr "mode" "V4SF")])
18106 (define_insn "sse_movups"
18107 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18108 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
18112 movups\t{%1, %0|%0, %1}
18113 movups\t{%1, %0|%0, %1}"
18114 [(set_attr "type" "ssecvt,ssecvt")
18115 (set_attr "mode" "V4SF")])
18118 ;; SSE Strange Moves.
18120 (define_insn "sse_movmskps"
18121 [(set (match_operand:SI 0 "register_operand" "=r")
18122 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
18125 "movmskps\t{%1, %0|%0, %1}"
18126 [(set_attr "type" "ssecvt")
18127 (set_attr "mode" "V4SF")])
18129 (define_insn "mmx_pmovmskb"
18130 [(set (match_operand:SI 0 "register_operand" "=r")
18131 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
18133 "TARGET_SSE || TARGET_3DNOW_A"
18134 "pmovmskb\t{%1, %0|%0, %1}"
18135 [(set_attr "type" "ssecvt")
18136 (set_attr "mode" "V4SF")])
18139 (define_insn "mmx_maskmovq"
18140 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
18141 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18142 (match_operand:V8QI 2 "register_operand" "y")]
18144 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
18145 ;; @@@ check ordering of operands in intel/nonintel syntax
18146 "maskmovq\t{%2, %1|%1, %2}"
18147 [(set_attr "type" "mmxcvt")
18148 (set_attr "mode" "DI")])
18150 (define_insn "mmx_maskmovq_rex"
18151 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
18152 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18153 (match_operand:V8QI 2 "register_operand" "y")]
18155 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
18156 ;; @@@ check ordering of operands in intel/nonintel syntax
18157 "maskmovq\t{%2, %1|%1, %2}"
18158 [(set_attr "type" "mmxcvt")
18159 (set_attr "mode" "DI")])
18161 (define_insn "sse_movntv4sf"
18162 [(set (match_operand:V4SF 0 "memory_operand" "=m")
18163 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
18166 "movntps\t{%1, %0|%0, %1}"
18167 [(set_attr "type" "ssemov")
18168 (set_attr "mode" "V4SF")])
18170 (define_insn "sse_movntdi"
18171 [(set (match_operand:DI 0 "memory_operand" "=m")
18172 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
18174 "TARGET_SSE || TARGET_3DNOW_A"
18175 "movntq\t{%1, %0|%0, %1}"
18176 [(set_attr "type" "mmxmov")
18177 (set_attr "mode" "DI")])
18179 (define_insn "sse_movhlps"
18180 [(set (match_operand:V4SF 0 "register_operand" "=x")
18182 (match_operand:V4SF 1 "register_operand" "0")
18183 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18184 (parallel [(const_int 2)
18190 "movhlps\t{%2, %0|%0, %2}"
18191 [(set_attr "type" "ssecvt")
18192 (set_attr "mode" "V4SF")])
18194 (define_insn "sse_movlhps"
18195 [(set (match_operand:V4SF 0 "register_operand" "=x")
18197 (match_operand:V4SF 1 "register_operand" "0")
18198 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18199 (parallel [(const_int 2)
18205 "movlhps\t{%2, %0|%0, %2}"
18206 [(set_attr "type" "ssecvt")
18207 (set_attr "mode" "V4SF")])
18209 (define_insn "sse_movhps"
18210 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18212 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
18213 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
18216 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
18217 "movhps\t{%2, %0|%0, %2}"
18218 [(set_attr "type" "ssecvt")
18219 (set_attr "mode" "V4SF")])
18221 (define_insn "sse_movlps"
18222 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18224 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
18225 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
18228 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
18229 "movlps\t{%2, %0|%0, %2}"
18230 [(set_attr "type" "ssecvt")
18231 (set_attr "mode" "V4SF")])
18233 (define_insn "sse_loadss"
18234 [(set (match_operand:V4SF 0 "register_operand" "=x")
18236 (match_operand:V4SF 1 "memory_operand" "m")
18237 (vec_duplicate:V4SF (float:SF (const_int 0)))
18240 "movss\t{%1, %0|%0, %1}"
18241 [(set_attr "type" "ssemov")
18242 (set_attr "mode" "SF")])
18244 (define_insn "sse_movss"
18245 [(set (match_operand:V4SF 0 "register_operand" "=x")
18247 (match_operand:V4SF 1 "register_operand" "0")
18248 (match_operand:V4SF 2 "register_operand" "x")
18251 "movss\t{%2, %0|%0, %2}"
18252 [(set_attr "type" "ssemov")
18253 (set_attr "mode" "SF")])
18255 (define_insn "sse_storess"
18256 [(set (match_operand:SF 0 "memory_operand" "=m")
18258 (match_operand:V4SF 1 "register_operand" "x")
18259 (parallel [(const_int 0)])))]
18261 "movss\t{%1, %0|%0, %1}"
18262 [(set_attr "type" "ssemov")
18263 (set_attr "mode" "SF")])
18265 (define_insn "sse_shufps"
18266 [(set (match_operand:V4SF 0 "register_operand" "=x")
18267 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
18268 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
18269 (match_operand:SI 3 "immediate_operand" "i")]
18272 ;; @@@ check operand order for intel/nonintel syntax
18273 "shufps\t{%3, %2, %0|%0, %2, %3}"
18274 [(set_attr "type" "ssecvt")
18275 (set_attr "mode" "V4SF")])
18280 (define_insn "addv4sf3"
18281 [(set (match_operand:V4SF 0 "register_operand" "=x")
18282 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18283 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18285 "addps\t{%2, %0|%0, %2}"
18286 [(set_attr "type" "sseadd")
18287 (set_attr "mode" "V4SF")])
18289 (define_insn "vmaddv4sf3"
18290 [(set (match_operand:V4SF 0 "register_operand" "=x")
18292 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18293 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18297 "addss\t{%2, %0|%0, %2}"
18298 [(set_attr "type" "sseadd")
18299 (set_attr "mode" "SF")])
18301 (define_insn "subv4sf3"
18302 [(set (match_operand:V4SF 0 "register_operand" "=x")
18303 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18304 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18306 "subps\t{%2, %0|%0, %2}"
18307 [(set_attr "type" "sseadd")
18308 (set_attr "mode" "V4SF")])
18310 (define_insn "vmsubv4sf3"
18311 [(set (match_operand:V4SF 0 "register_operand" "=x")
18313 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18314 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18318 "subss\t{%2, %0|%0, %2}"
18319 [(set_attr "type" "sseadd")
18320 (set_attr "mode" "SF")])
18322 (define_insn "mulv4sf3"
18323 [(set (match_operand:V4SF 0 "register_operand" "=x")
18324 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18325 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18327 "mulps\t{%2, %0|%0, %2}"
18328 [(set_attr "type" "ssemul")
18329 (set_attr "mode" "V4SF")])
18331 (define_insn "vmmulv4sf3"
18332 [(set (match_operand:V4SF 0 "register_operand" "=x")
18334 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18335 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18339 "mulss\t{%2, %0|%0, %2}"
18340 [(set_attr "type" "ssemul")
18341 (set_attr "mode" "SF")])
18343 (define_insn "divv4sf3"
18344 [(set (match_operand:V4SF 0 "register_operand" "=x")
18345 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18346 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18348 "divps\t{%2, %0|%0, %2}"
18349 [(set_attr "type" "ssediv")
18350 (set_attr "mode" "V4SF")])
18352 (define_insn "vmdivv4sf3"
18353 [(set (match_operand:V4SF 0 "register_operand" "=x")
18355 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18356 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18360 "divss\t{%2, %0|%0, %2}"
18361 [(set_attr "type" "ssediv")
18362 (set_attr "mode" "SF")])
18365 ;; SSE square root/reciprocal
18367 (define_insn "rcpv4sf2"
18368 [(set (match_operand:V4SF 0 "register_operand" "=x")
18370 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
18372 "rcpps\t{%1, %0|%0, %1}"
18373 [(set_attr "type" "sse")
18374 (set_attr "mode" "V4SF")])
18376 (define_insn "vmrcpv4sf2"
18377 [(set (match_operand:V4SF 0 "register_operand" "=x")
18379 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18381 (match_operand:V4SF 2 "register_operand" "0")
18384 "rcpss\t{%1, %0|%0, %1}"
18385 [(set_attr "type" "sse")
18386 (set_attr "mode" "SF")])
18388 (define_insn "rsqrtv4sf2"
18389 [(set (match_operand:V4SF 0 "register_operand" "=x")
18391 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
18393 "rsqrtps\t{%1, %0|%0, %1}"
18394 [(set_attr "type" "sse")
18395 (set_attr "mode" "V4SF")])
18397 (define_insn "vmrsqrtv4sf2"
18398 [(set (match_operand:V4SF 0 "register_operand" "=x")
18400 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18402 (match_operand:V4SF 2 "register_operand" "0")
18405 "rsqrtss\t{%1, %0|%0, %1}"
18406 [(set_attr "type" "sse")
18407 (set_attr "mode" "SF")])
18409 (define_insn "sqrtv4sf2"
18410 [(set (match_operand:V4SF 0 "register_operand" "=x")
18411 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
18413 "sqrtps\t{%1, %0|%0, %1}"
18414 [(set_attr "type" "sse")
18415 (set_attr "mode" "V4SF")])
18417 (define_insn "vmsqrtv4sf2"
18418 [(set (match_operand:V4SF 0 "register_operand" "=x")
18420 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18421 (match_operand:V4SF 2 "register_operand" "0")
18424 "sqrtss\t{%1, %0|%0, %1}"
18425 [(set_attr "type" "sse")
18426 (set_attr "mode" "SF")])
18428 ;; SSE logical operations.
18430 ;; These are not called andti3 etc. because we really really don't want
18431 ;; the compiler to widen DImode ands to TImode ands and then try to move
18432 ;; into DImode subregs of SSE registers, and them together, and move out
18433 ;; of DImode subregs again!
18435 (define_insn "*sse_andti3_df_1"
18436 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18437 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18438 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18440 "andpd\t{%2, %0|%0, %2}"
18441 [(set_attr "type" "sselog")
18442 (set_attr "mode" "V2DF")])
18444 (define_insn "*sse_andti3_df_2"
18445 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18446 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18447 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18449 "andpd\t{%2, %0|%0, %2}"
18450 [(set_attr "type" "sselog")
18451 (set_attr "mode" "V2DF")])
18453 (define_insn "*sse_andti3_sf_1"
18454 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18455 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18456 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18458 "andps\t{%2, %0|%0, %2}"
18459 [(set_attr "type" "sselog")
18460 (set_attr "mode" "V4SF")])
18462 (define_insn "*sse_andti3_sf_2"
18463 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18464 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18465 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18467 "andps\t{%2, %0|%0, %2}"
18468 [(set_attr "type" "sselog")
18469 (set_attr "mode" "V4SF")])
18471 (define_insn "sse_andti3"
18472 [(set (match_operand:TI 0 "register_operand" "=x")
18473 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18474 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18475 "TARGET_SSE && !TARGET_SSE2
18476 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18477 "andps\t{%2, %0|%0, %2}"
18478 [(set_attr "type" "sselog")
18479 (set_attr "mode" "V4SF")])
18481 (define_insn "sse2_andti3"
18482 [(set (match_operand:TI 0 "register_operand" "=x")
18483 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18484 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18486 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18487 "pand\t{%2, %0|%0, %2}"
18488 [(set_attr "type" "sselog")
18489 (set_attr "mode" "TI")])
18491 (define_insn "sse2_andv2di3"
18492 [(set (match_operand:V2DI 0 "register_operand" "=x")
18493 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18494 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18496 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18497 "pand\t{%2, %0|%0, %2}"
18498 [(set_attr "type" "sselog")
18499 (set_attr "mode" "TI")])
18501 (define_insn "*sse_nandti3_df"
18502 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18503 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18504 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18506 "andnpd\t{%2, %0|%0, %2}"
18507 [(set_attr "type" "sselog")
18508 (set_attr "mode" "V2DF")])
18510 (define_insn "*sse_nandti3_sf"
18511 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18512 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18513 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18515 "andnps\t{%2, %0|%0, %2}"
18516 [(set_attr "type" "sselog")
18517 (set_attr "mode" "V4SF")])
18519 (define_insn "sse_nandti3"
18520 [(set (match_operand:TI 0 "register_operand" "=x")
18521 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18522 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18523 "TARGET_SSE && !TARGET_SSE2"
18524 "andnps\t{%2, %0|%0, %2}"
18525 [(set_attr "type" "sselog")
18526 (set_attr "mode" "V4SF")])
18528 (define_insn "sse2_nandti3"
18529 [(set (match_operand:TI 0 "register_operand" "=x")
18530 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18531 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18533 "pandn\t{%2, %0|%0, %2}"
18534 [(set_attr "type" "sselog")
18535 (set_attr "mode" "TI")])
18537 (define_insn "sse2_nandv2di3"
18538 [(set (match_operand:V2DI 0 "register_operand" "=x")
18539 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0"))
18540 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18542 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18543 "pandn\t{%2, %0|%0, %2}"
18544 [(set_attr "type" "sselog")
18545 (set_attr "mode" "TI")])
18547 (define_insn "*sse_iorti3_df_1"
18548 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18549 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18550 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18552 "orpd\t{%2, %0|%0, %2}"
18553 [(set_attr "type" "sselog")
18554 (set_attr "mode" "V2DF")])
18556 (define_insn "*sse_iorti3_df_2"
18557 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18558 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18559 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18561 "orpd\t{%2, %0|%0, %2}"
18562 [(set_attr "type" "sselog")
18563 (set_attr "mode" "V2DF")])
18565 (define_insn "*sse_iorti3_sf_1"
18566 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18567 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18568 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18570 "orps\t{%2, %0|%0, %2}"
18571 [(set_attr "type" "sselog")
18572 (set_attr "mode" "V4SF")])
18574 (define_insn "*sse_iorti3_sf_2"
18575 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18576 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18577 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18579 "orps\t{%2, %0|%0, %2}"
18580 [(set_attr "type" "sselog")
18581 (set_attr "mode" "V4SF")])
18583 (define_insn "sse_iorti3"
18584 [(set (match_operand:TI 0 "register_operand" "=x")
18585 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18586 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18587 "TARGET_SSE && !TARGET_SSE2
18588 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18589 "orps\t{%2, %0|%0, %2}"
18590 [(set_attr "type" "sselog")
18591 (set_attr "mode" "V4SF")])
18593 (define_insn "sse2_iorti3"
18594 [(set (match_operand:TI 0 "register_operand" "=x")
18595 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18596 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18598 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18599 "por\t{%2, %0|%0, %2}"
18600 [(set_attr "type" "sselog")
18601 (set_attr "mode" "TI")])
18603 (define_insn "sse2_iorv2di3"
18604 [(set (match_operand:V2DI 0 "register_operand" "=x")
18605 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18606 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18608 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18609 "por\t{%2, %0|%0, %2}"
18610 [(set_attr "type" "sselog")
18611 (set_attr "mode" "TI")])
18613 (define_insn "*sse_xorti3_df_1"
18614 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18615 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18616 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18618 "xorpd\t{%2, %0|%0, %2}"
18619 [(set_attr "type" "sselog")
18620 (set_attr "mode" "V2DF")])
18622 (define_insn "*sse_xorti3_df_2"
18623 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18624 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18625 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18627 "xorpd\t{%2, %0|%0, %2}"
18628 [(set_attr "type" "sselog")
18629 (set_attr "mode" "V2DF")])
18631 (define_insn "*sse_xorti3_sf_1"
18632 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18633 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18634 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18636 "xorps\t{%2, %0|%0, %2}"
18637 [(set_attr "type" "sselog")
18638 (set_attr "mode" "V4SF")])
18640 (define_insn "*sse_xorti3_sf_2"
18641 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18642 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18643 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18645 "xorps\t{%2, %0|%0, %2}"
18646 [(set_attr "type" "sselog")
18647 (set_attr "mode" "V4SF")])
18649 (define_insn "sse_xorti3"
18650 [(set (match_operand:TI 0 "register_operand" "=x")
18651 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18652 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18653 "TARGET_SSE && !TARGET_SSE2
18654 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18655 "xorps\t{%2, %0|%0, %2}"
18656 [(set_attr "type" "sselog")
18657 (set_attr "mode" "V4SF")])
18659 (define_insn "sse2_xorti3"
18660 [(set (match_operand:TI 0 "register_operand" "=x")
18661 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18662 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18664 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18665 "pxor\t{%2, %0|%0, %2}"
18666 [(set_attr "type" "sselog")
18667 (set_attr "mode" "TI")])
18669 (define_insn "sse2_xorv2di3"
18670 [(set (match_operand:V2DI 0 "register_operand" "=x")
18671 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18672 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18674 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18675 "pxor\t{%2, %0|%0, %2}"
18676 [(set_attr "type" "sselog")
18677 (set_attr "mode" "TI")])
18679 ;; Use xor, but don't show input operands so they aren't live before
18681 (define_insn "sse_clrv4sf"
18682 [(set (match_operand:V4SF 0 "register_operand" "=x")
18683 (unspec:V4SF [(const_int 0)] UNSPEC_NOP))]
18685 "xorps\t{%0, %0|%0, %0}"
18686 [(set_attr "type" "sselog")
18687 (set_attr "memory" "none")
18688 (set_attr "mode" "V4SF")])
18690 ;; SSE mask-generating compares
18692 (define_insn "maskcmpv4sf3"
18693 [(set (match_operand:V4SI 0 "register_operand" "=x")
18694 (match_operator:V4SI 3 "sse_comparison_operator"
18695 [(match_operand:V4SF 1 "register_operand" "0")
18696 (match_operand:V4SF 2 "register_operand" "x")]))]
18698 "cmp%D3ps\t{%2, %0|%0, %2}"
18699 [(set_attr "type" "ssecmp")
18700 (set_attr "mode" "V4SF")])
18702 (define_insn "maskncmpv4sf3"
18703 [(set (match_operand:V4SI 0 "register_operand" "=x")
18705 (match_operator:V4SI 3 "sse_comparison_operator"
18706 [(match_operand:V4SF 1 "register_operand" "0")
18707 (match_operand:V4SF 2 "register_operand" "x")])))]
18710 if (GET_CODE (operands[3]) == UNORDERED)
18711 return "cmpordps\t{%2, %0|%0, %2}";
18713 return "cmpn%D3ps\t{%2, %0|%0, %2}";
18715 [(set_attr "type" "ssecmp")
18716 (set_attr "mode" "V4SF")])
18718 (define_insn "vmmaskcmpv4sf3"
18719 [(set (match_operand:V4SI 0 "register_operand" "=x")
18721 (match_operator:V4SI 3 "sse_comparison_operator"
18722 [(match_operand:V4SF 1 "register_operand" "0")
18723 (match_operand:V4SF 2 "register_operand" "x")])
18727 "cmp%D3ss\t{%2, %0|%0, %2}"
18728 [(set_attr "type" "ssecmp")
18729 (set_attr "mode" "SF")])
18731 (define_insn "vmmaskncmpv4sf3"
18732 [(set (match_operand:V4SI 0 "register_operand" "=x")
18735 (match_operator:V4SI 3 "sse_comparison_operator"
18736 [(match_operand:V4SF 1 "register_operand" "0")
18737 (match_operand:V4SF 2 "register_operand" "x")]))
18738 (subreg:V4SI (match_dup 1) 0)
18742 if (GET_CODE (operands[3]) == UNORDERED)
18743 return "cmpordss\t{%2, %0|%0, %2}";
18745 return "cmpn%D3ss\t{%2, %0|%0, %2}";
18747 [(set_attr "type" "ssecmp")
18748 (set_attr "mode" "SF")])
18750 (define_insn "sse_comi"
18751 [(set (reg:CCFP 17)
18752 (match_operator:CCFP 2 "sse_comparison_operator"
18754 (match_operand:V4SF 0 "register_operand" "x")
18755 (parallel [(const_int 0)]))
18757 (match_operand:V4SF 1 "register_operand" "x")
18758 (parallel [(const_int 0)]))]))]
18760 "comiss\t{%1, %0|%0, %1}"
18761 [(set_attr "type" "ssecmp")
18762 (set_attr "mode" "SF")])
18764 (define_insn "sse_ucomi"
18765 [(set (reg:CCFPU 17)
18766 (match_operator:CCFPU 2 "sse_comparison_operator"
18768 (match_operand:V4SF 0 "register_operand" "x")
18769 (parallel [(const_int 0)]))
18771 (match_operand:V4SF 1 "register_operand" "x")
18772 (parallel [(const_int 0)]))]))]
18774 "ucomiss\t{%1, %0|%0, %1}"
18775 [(set_attr "type" "ssecmp")
18776 (set_attr "mode" "SF")])
18781 (define_insn "sse_unpckhps"
18782 [(set (match_operand:V4SF 0 "register_operand" "=x")
18784 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18785 (parallel [(const_int 2)
18789 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18790 (parallel [(const_int 0)
18796 "unpckhps\t{%2, %0|%0, %2}"
18797 [(set_attr "type" "ssecvt")
18798 (set_attr "mode" "V4SF")])
18800 (define_insn "sse_unpcklps"
18801 [(set (match_operand:V4SF 0 "register_operand" "=x")
18803 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18804 (parallel [(const_int 0)
18808 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18809 (parallel [(const_int 2)
18815 "unpcklps\t{%2, %0|%0, %2}"
18816 [(set_attr "type" "ssecvt")
18817 (set_attr "mode" "V4SF")])
18822 (define_insn "smaxv4sf3"
18823 [(set (match_operand:V4SF 0 "register_operand" "=x")
18824 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18825 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18827 "maxps\t{%2, %0|%0, %2}"
18828 [(set_attr "type" "sse")
18829 (set_attr "mode" "V4SF")])
18831 (define_insn "vmsmaxv4sf3"
18832 [(set (match_operand:V4SF 0 "register_operand" "=x")
18834 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18835 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18839 "maxss\t{%2, %0|%0, %2}"
18840 [(set_attr "type" "sse")
18841 (set_attr "mode" "SF")])
18843 (define_insn "sminv4sf3"
18844 [(set (match_operand:V4SF 0 "register_operand" "=x")
18845 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18846 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18848 "minps\t{%2, %0|%0, %2}"
18849 [(set_attr "type" "sse")
18850 (set_attr "mode" "V4SF")])
18852 (define_insn "vmsminv4sf3"
18853 [(set (match_operand:V4SF 0 "register_operand" "=x")
18855 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18856 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18860 "minss\t{%2, %0|%0, %2}"
18861 [(set_attr "type" "sse")
18862 (set_attr "mode" "SF")])
18865 ;; SSE <-> integer/MMX conversions
18867 (define_insn "cvtpi2ps"
18868 [(set (match_operand:V4SF 0 "register_operand" "=x")
18870 (match_operand:V4SF 1 "register_operand" "0")
18871 (vec_duplicate:V4SF
18872 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
18875 "cvtpi2ps\t{%2, %0|%0, %2}"
18876 [(set_attr "type" "ssecvt")
18877 (set_attr "mode" "V4SF")])
18879 (define_insn "cvtps2pi"
18880 [(set (match_operand:V2SI 0 "register_operand" "=y")
18882 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18883 (parallel [(const_int 0) (const_int 1)])))]
18885 "cvtps2pi\t{%1, %0|%0, %1}"
18886 [(set_attr "type" "ssecvt")
18887 (set_attr "mode" "V4SF")])
18889 (define_insn "cvttps2pi"
18890 [(set (match_operand:V2SI 0 "register_operand" "=y")
18892 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18894 (parallel [(const_int 0) (const_int 1)])))]
18896 "cvttps2pi\t{%1, %0|%0, %1}"
18897 [(set_attr "type" "ssecvt")
18898 (set_attr "mode" "SF")])
18900 (define_insn "cvtsi2ss"
18901 [(set (match_operand:V4SF 0 "register_operand" "=x")
18903 (match_operand:V4SF 1 "register_operand" "0")
18904 (vec_duplicate:V4SF
18905 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm")))
18908 "cvtsi2ss\t{%2, %0|%0, %2}"
18909 [(set_attr "type" "ssecvt")
18910 (set_attr "mode" "SF")])
18912 (define_insn "cvtss2si"
18913 [(set (match_operand:SI 0 "register_operand" "=r")
18915 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18916 (parallel [(const_int 0)])))]
18918 "cvtss2si\t{%1, %0|%0, %1}"
18919 [(set_attr "type" "ssecvt")
18920 (set_attr "mode" "SF")])
18922 (define_insn "cvttss2si"
18923 [(set (match_operand:SI 0 "register_operand" "=r")
18925 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18927 (parallel [(const_int 0)])))]
18929 "cvttss2si\t{%1, %0|%0, %1}"
18930 [(set_attr "type" "ssecvt")
18931 (set_attr "mode" "SF")])
18938 (define_insn "addv8qi3"
18939 [(set (match_operand:V8QI 0 "register_operand" "=y")
18940 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18941 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18943 "paddb\t{%2, %0|%0, %2}"
18944 [(set_attr "type" "mmxadd")
18945 (set_attr "mode" "DI")])
18947 (define_insn "addv4hi3"
18948 [(set (match_operand:V4HI 0 "register_operand" "=y")
18949 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18950 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18952 "paddw\t{%2, %0|%0, %2}"
18953 [(set_attr "type" "mmxadd")
18954 (set_attr "mode" "DI")])
18956 (define_insn "addv2si3"
18957 [(set (match_operand:V2SI 0 "register_operand" "=y")
18958 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18959 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18961 "paddd\t{%2, %0|%0, %2}"
18962 [(set_attr "type" "mmxadd")
18963 (set_attr "mode" "DI")])
18965 (define_insn "ssaddv8qi3"
18966 [(set (match_operand:V8QI 0 "register_operand" "=y")
18967 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18968 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18970 "paddsb\t{%2, %0|%0, %2}"
18971 [(set_attr "type" "mmxadd")
18972 (set_attr "mode" "DI")])
18974 (define_insn "ssaddv4hi3"
18975 [(set (match_operand:V4HI 0 "register_operand" "=y")
18976 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18977 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18979 "paddsw\t{%2, %0|%0, %2}"
18980 [(set_attr "type" "mmxadd")
18981 (set_attr "mode" "DI")])
18983 (define_insn "usaddv8qi3"
18984 [(set (match_operand:V8QI 0 "register_operand" "=y")
18985 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18986 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18988 "paddusb\t{%2, %0|%0, %2}"
18989 [(set_attr "type" "mmxadd")
18990 (set_attr "mode" "DI")])
18992 (define_insn "usaddv4hi3"
18993 [(set (match_operand:V4HI 0 "register_operand" "=y")
18994 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18995 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18997 "paddusw\t{%2, %0|%0, %2}"
18998 [(set_attr "type" "mmxadd")
18999 (set_attr "mode" "DI")])
19001 (define_insn "subv8qi3"
19002 [(set (match_operand:V8QI 0 "register_operand" "=y")
19003 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19004 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19006 "psubb\t{%2, %0|%0, %2}"
19007 [(set_attr "type" "mmxadd")
19008 (set_attr "mode" "DI")])
19010 (define_insn "subv4hi3"
19011 [(set (match_operand:V4HI 0 "register_operand" "=y")
19012 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19013 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19015 "psubw\t{%2, %0|%0, %2}"
19016 [(set_attr "type" "mmxadd")
19017 (set_attr "mode" "DI")])
19019 (define_insn "subv2si3"
19020 [(set (match_operand:V2SI 0 "register_operand" "=y")
19021 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
19022 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19024 "psubd\t{%2, %0|%0, %2}"
19025 [(set_attr "type" "mmxadd")
19026 (set_attr "mode" "DI")])
19028 (define_insn "sssubv8qi3"
19029 [(set (match_operand:V8QI 0 "register_operand" "=y")
19030 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19031 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19033 "psubsb\t{%2, %0|%0, %2}"
19034 [(set_attr "type" "mmxadd")
19035 (set_attr "mode" "DI")])
19037 (define_insn "sssubv4hi3"
19038 [(set (match_operand:V4HI 0 "register_operand" "=y")
19039 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19040 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19042 "psubsw\t{%2, %0|%0, %2}"
19043 [(set_attr "type" "mmxadd")
19044 (set_attr "mode" "DI")])
19046 (define_insn "ussubv8qi3"
19047 [(set (match_operand:V8QI 0 "register_operand" "=y")
19048 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19049 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19051 "psubusb\t{%2, %0|%0, %2}"
19052 [(set_attr "type" "mmxadd")
19053 (set_attr "mode" "DI")])
19055 (define_insn "ussubv4hi3"
19056 [(set (match_operand:V4HI 0 "register_operand" "=y")
19057 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19058 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19060 "psubusw\t{%2, %0|%0, %2}"
19061 [(set_attr "type" "mmxadd")
19062 (set_attr "mode" "DI")])
19064 (define_insn "mulv4hi3"
19065 [(set (match_operand:V4HI 0 "register_operand" "=y")
19066 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
19067 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19069 "pmullw\t{%2, %0|%0, %2}"
19070 [(set_attr "type" "mmxmul")
19071 (set_attr "mode" "DI")])
19073 (define_insn "smulv4hi3_highpart"
19074 [(set (match_operand:V4HI 0 "register_operand" "=y")
19077 (mult:V4SI (sign_extend:V4SI
19078 (match_operand:V4HI 1 "register_operand" "0"))
19080 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19083 "pmulhw\t{%2, %0|%0, %2}"
19084 [(set_attr "type" "mmxmul")
19085 (set_attr "mode" "DI")])
19087 (define_insn "umulv4hi3_highpart"
19088 [(set (match_operand:V4HI 0 "register_operand" "=y")
19091 (mult:V4SI (zero_extend:V4SI
19092 (match_operand:V4HI 1 "register_operand" "0"))
19094 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19096 "TARGET_SSE || TARGET_3DNOW_A"
19097 "pmulhuw\t{%2, %0|%0, %2}"
19098 [(set_attr "type" "mmxmul")
19099 (set_attr "mode" "DI")])
19101 (define_insn "mmx_pmaddwd"
19102 [(set (match_operand:V2SI 0 "register_operand" "=y")
19106 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
19107 (parallel [(const_int 0) (const_int 2)])))
19109 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
19110 (parallel [(const_int 0) (const_int 2)]))))
19112 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
19113 (parallel [(const_int 1)
19115 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
19116 (parallel [(const_int 1)
19117 (const_int 3)]))))))]
19119 "pmaddwd\t{%2, %0|%0, %2}"
19120 [(set_attr "type" "mmxmul")
19121 (set_attr "mode" "DI")])
19124 ;; MMX logical operations
19125 ;; Note we don't want to declare these as regular iordi3 insns to prevent
19126 ;; normal code that also wants to use the FPU from getting broken.
19127 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
19128 (define_insn "mmx_iordi3"
19129 [(set (match_operand:DI 0 "register_operand" "=y")
19131 [(ior:DI (match_operand:DI 1 "register_operand" "0")
19132 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19135 "por\t{%2, %0|%0, %2}"
19136 [(set_attr "type" "mmxadd")
19137 (set_attr "mode" "DI")])
19139 (define_insn "mmx_xordi3"
19140 [(set (match_operand:DI 0 "register_operand" "=y")
19142 [(xor:DI (match_operand:DI 1 "register_operand" "0")
19143 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19146 "pxor\t{%2, %0|%0, %2}"
19147 [(set_attr "type" "mmxadd")
19148 (set_attr "mode" "DI")
19149 (set_attr "memory" "none")])
19151 ;; Same as pxor, but don't show input operands so that we don't think
19153 (define_insn "mmx_clrdi"
19154 [(set (match_operand:DI 0 "register_operand" "=y")
19155 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
19157 "pxor\t{%0, %0|%0, %0}"
19158 [(set_attr "type" "mmxadd")
19159 (set_attr "mode" "DI")
19160 (set_attr "memory" "none")])
19162 (define_insn "mmx_anddi3"
19163 [(set (match_operand:DI 0 "register_operand" "=y")
19165 [(and:DI (match_operand:DI 1 "register_operand" "0")
19166 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19169 "pand\t{%2, %0|%0, %2}"
19170 [(set_attr "type" "mmxadd")
19171 (set_attr "mode" "DI")])
19173 (define_insn "mmx_nanddi3"
19174 [(set (match_operand:DI 0 "register_operand" "=y")
19176 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
19177 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19180 "pandn\t{%2, %0|%0, %2}"
19181 [(set_attr "type" "mmxadd")
19182 (set_attr "mode" "DI")])
19185 ;; MMX unsigned averages/sum of absolute differences
19187 (define_insn "mmx_uavgv8qi3"
19188 [(set (match_operand:V8QI 0 "register_operand" "=y")
19190 (plus:V8QI (plus:V8QI
19191 (match_operand:V8QI 1 "register_operand" "0")
19192 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
19193 (const_vector:V8QI [(const_int 1)
19202 "TARGET_SSE || TARGET_3DNOW_A"
19203 "pavgb\t{%2, %0|%0, %2}"
19204 [(set_attr "type" "mmxshft")
19205 (set_attr "mode" "DI")])
19207 (define_insn "mmx_uavgv4hi3"
19208 [(set (match_operand:V4HI 0 "register_operand" "=y")
19210 (plus:V4HI (plus:V4HI
19211 (match_operand:V4HI 1 "register_operand" "0")
19212 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
19213 (const_vector:V4HI [(const_int 1)
19218 "TARGET_SSE || TARGET_3DNOW_A"
19219 "pavgw\t{%2, %0|%0, %2}"
19220 [(set_attr "type" "mmxshft")
19221 (set_attr "mode" "DI")])
19223 (define_insn "mmx_psadbw"
19224 [(set (match_operand:DI 0 "register_operand" "=y")
19225 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
19226 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
19228 "TARGET_SSE || TARGET_3DNOW_A"
19229 "psadbw\t{%2, %0|%0, %2}"
19230 [(set_attr "type" "mmxshft")
19231 (set_attr "mode" "DI")])
19234 ;; MMX insert/extract/shuffle
19236 (define_insn "mmx_pinsrw"
19237 [(set (match_operand:V4HI 0 "register_operand" "=y")
19238 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
19239 (vec_duplicate:V4HI
19240 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
19241 (match_operand:SI 3 "immediate_operand" "i")))]
19242 "TARGET_SSE || TARGET_3DNOW_A"
19243 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
19244 [(set_attr "type" "mmxcvt")
19245 (set_attr "mode" "DI")])
19247 (define_insn "mmx_pextrw"
19248 [(set (match_operand:SI 0 "register_operand" "=r")
19249 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
19251 [(match_operand:SI 2 "immediate_operand" "i")]))))]
19252 "TARGET_SSE || TARGET_3DNOW_A"
19253 "pextrw\t{%2, %1, %0|%0, %1, %2}"
19254 [(set_attr "type" "mmxcvt")
19255 (set_attr "mode" "DI")])
19257 (define_insn "mmx_pshufw"
19258 [(set (match_operand:V4HI 0 "register_operand" "=y")
19259 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
19260 (match_operand:SI 2 "immediate_operand" "i")]
19262 "TARGET_SSE || TARGET_3DNOW_A"
19263 "pshufw\t{%2, %1, %0|%0, %1, %2}"
19264 [(set_attr "type" "mmxcvt")
19265 (set_attr "mode" "DI")])
19268 ;; MMX mask-generating comparisons
19270 (define_insn "eqv8qi3"
19271 [(set (match_operand:V8QI 0 "register_operand" "=y")
19272 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
19273 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19275 "pcmpeqb\t{%2, %0|%0, %2}"
19276 [(set_attr "type" "mmxcmp")
19277 (set_attr "mode" "DI")])
19279 (define_insn "eqv4hi3"
19280 [(set (match_operand:V4HI 0 "register_operand" "=y")
19281 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
19282 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19284 "pcmpeqw\t{%2, %0|%0, %2}"
19285 [(set_attr "type" "mmxcmp")
19286 (set_attr "mode" "DI")])
19288 (define_insn "eqv2si3"
19289 [(set (match_operand:V2SI 0 "register_operand" "=y")
19290 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
19291 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19293 "pcmpeqd\t{%2, %0|%0, %2}"
19294 [(set_attr "type" "mmxcmp")
19295 (set_attr "mode" "DI")])
19297 (define_insn "gtv8qi3"
19298 [(set (match_operand:V8QI 0 "register_operand" "=y")
19299 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
19300 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19302 "pcmpgtb\t{%2, %0|%0, %2}"
19303 [(set_attr "type" "mmxcmp")
19304 (set_attr "mode" "DI")])
19306 (define_insn "gtv4hi3"
19307 [(set (match_operand:V4HI 0 "register_operand" "=y")
19308 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19309 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19311 "pcmpgtw\t{%2, %0|%0, %2}"
19312 [(set_attr "type" "mmxcmp")
19313 (set_attr "mode" "DI")])
19315 (define_insn "gtv2si3"
19316 [(set (match_operand:V2SI 0 "register_operand" "=y")
19317 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19318 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19320 "pcmpgtd\t{%2, %0|%0, %2}"
19321 [(set_attr "type" "mmxcmp")
19322 (set_attr "mode" "DI")])
19325 ;; MMX max/min insns
19327 (define_insn "umaxv8qi3"
19328 [(set (match_operand:V8QI 0 "register_operand" "=y")
19329 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
19330 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19331 "TARGET_SSE || TARGET_3DNOW_A"
19332 "pmaxub\t{%2, %0|%0, %2}"
19333 [(set_attr "type" "mmxadd")
19334 (set_attr "mode" "DI")])
19336 (define_insn "smaxv4hi3"
19337 [(set (match_operand:V4HI 0 "register_operand" "=y")
19338 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
19339 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19340 "TARGET_SSE || TARGET_3DNOW_A"
19341 "pmaxsw\t{%2, %0|%0, %2}"
19342 [(set_attr "type" "mmxadd")
19343 (set_attr "mode" "DI")])
19345 (define_insn "uminv8qi3"
19346 [(set (match_operand:V8QI 0 "register_operand" "=y")
19347 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
19348 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19349 "TARGET_SSE || TARGET_3DNOW_A"
19350 "pminub\t{%2, %0|%0, %2}"
19351 [(set_attr "type" "mmxadd")
19352 (set_attr "mode" "DI")])
19354 (define_insn "sminv4hi3"
19355 [(set (match_operand:V4HI 0 "register_operand" "=y")
19356 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
19357 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19358 "TARGET_SSE || TARGET_3DNOW_A"
19359 "pminsw\t{%2, %0|%0, %2}"
19360 [(set_attr "type" "mmxadd")
19361 (set_attr "mode" "DI")])
19366 (define_insn "ashrv4hi3"
19367 [(set (match_operand:V4HI 0 "register_operand" "=y")
19368 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19369 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19371 "psraw\t{%2, %0|%0, %2}"
19372 [(set_attr "type" "mmxshft")
19373 (set_attr "mode" "DI")])
19375 (define_insn "ashrv2si3"
19376 [(set (match_operand:V2SI 0 "register_operand" "=y")
19377 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19378 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19380 "psrad\t{%2, %0|%0, %2}"
19381 [(set_attr "type" "mmxshft")
19382 (set_attr "mode" "DI")])
19384 (define_insn "lshrv4hi3"
19385 [(set (match_operand:V4HI 0 "register_operand" "=y")
19386 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19387 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19389 "psrlw\t{%2, %0|%0, %2}"
19390 [(set_attr "type" "mmxshft")
19391 (set_attr "mode" "DI")])
19393 (define_insn "lshrv2si3"
19394 [(set (match_operand:V2SI 0 "register_operand" "=y")
19395 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19396 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19398 "psrld\t{%2, %0|%0, %2}"
19399 [(set_attr "type" "mmxshft")
19400 (set_attr "mode" "DI")])
19402 ;; See logical MMX insns.
19403 (define_insn "mmx_lshrdi3"
19404 [(set (match_operand:DI 0 "register_operand" "=y")
19406 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
19407 (match_operand:DI 2 "nonmemory_operand" "yi"))]
19410 "psrlq\t{%2, %0|%0, %2}"
19411 [(set_attr "type" "mmxshft")
19412 (set_attr "mode" "DI")])
19414 (define_insn "ashlv4hi3"
19415 [(set (match_operand:V4HI 0 "register_operand" "=y")
19416 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
19417 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19419 "psllw\t{%2, %0|%0, %2}"
19420 [(set_attr "type" "mmxshft")
19421 (set_attr "mode" "DI")])
19423 (define_insn "ashlv2si3"
19424 [(set (match_operand:V2SI 0 "register_operand" "=y")
19425 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
19426 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19428 "pslld\t{%2, %0|%0, %2}"
19429 [(set_attr "type" "mmxshft")
19430 (set_attr "mode" "DI")])
19432 ;; See logical MMX insns.
19433 (define_insn "mmx_ashldi3"
19434 [(set (match_operand:DI 0 "register_operand" "=y")
19436 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
19437 (match_operand:DI 2 "nonmemory_operand" "yi"))]
19440 "psllq\t{%2, %0|%0, %2}"
19441 [(set_attr "type" "mmxshft")
19442 (set_attr "mode" "DI")])
19445 ;; MMX pack/unpack insns.
19447 (define_insn "mmx_packsswb"
19448 [(set (match_operand:V8QI 0 "register_operand" "=y")
19450 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19451 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19453 "packsswb\t{%2, %0|%0, %2}"
19454 [(set_attr "type" "mmxshft")
19455 (set_attr "mode" "DI")])
19457 (define_insn "mmx_packssdw"
19458 [(set (match_operand:V4HI 0 "register_operand" "=y")
19460 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
19461 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
19463 "packssdw\t{%2, %0|%0, %2}"
19464 [(set_attr "type" "mmxshft")
19465 (set_attr "mode" "DI")])
19467 (define_insn "mmx_packuswb"
19468 [(set (match_operand:V8QI 0 "register_operand" "=y")
19470 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19471 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19473 "packuswb\t{%2, %0|%0, %2}"
19474 [(set_attr "type" "mmxshft")
19475 (set_attr "mode" "DI")])
19477 (define_insn "mmx_punpckhbw"
19478 [(set (match_operand:V8QI 0 "register_operand" "=y")
19480 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19481 (parallel [(const_int 4)
19489 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19490 (parallel [(const_int 0)
19500 "punpckhbw\t{%2, %0|%0, %2}"
19501 [(set_attr "type" "mmxcvt")
19502 (set_attr "mode" "DI")])
19504 (define_insn "mmx_punpckhwd"
19505 [(set (match_operand:V4HI 0 "register_operand" "=y")
19507 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19508 (parallel [(const_int 0)
19512 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19513 (parallel [(const_int 2)
19519 "punpckhwd\t{%2, %0|%0, %2}"
19520 [(set_attr "type" "mmxcvt")
19521 (set_attr "mode" "DI")])
19523 (define_insn "mmx_punpckhdq"
19524 [(set (match_operand:V2SI 0 "register_operand" "=y")
19526 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19527 (parallel [(const_int 0)
19529 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19530 (parallel [(const_int 1)
19534 "punpckhdq\t{%2, %0|%0, %2}"
19535 [(set_attr "type" "mmxcvt")
19536 (set_attr "mode" "DI")])
19538 (define_insn "mmx_punpcklbw"
19539 [(set (match_operand:V8QI 0 "register_operand" "=y")
19541 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19542 (parallel [(const_int 0)
19550 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19551 (parallel [(const_int 4)
19561 "punpcklbw\t{%2, %0|%0, %2}"
19562 [(set_attr "type" "mmxcvt")
19563 (set_attr "mode" "DI")])
19565 (define_insn "mmx_punpcklwd"
19566 [(set (match_operand:V4HI 0 "register_operand" "=y")
19568 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19569 (parallel [(const_int 2)
19573 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19574 (parallel [(const_int 0)
19580 "punpcklwd\t{%2, %0|%0, %2}"
19581 [(set_attr "type" "mmxcvt")
19582 (set_attr "mode" "DI")])
19584 (define_insn "mmx_punpckldq"
19585 [(set (match_operand:V2SI 0 "register_operand" "=y")
19587 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19588 (parallel [(const_int 1)
19590 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19591 (parallel [(const_int 0)
19595 "punpckldq\t{%2, %0|%0, %2}"
19596 [(set_attr "type" "mmxcvt")
19597 (set_attr "mode" "DI")])
19600 ;; Miscellaneous stuff
19602 (define_insn "emms"
19603 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
19604 (clobber (reg:XF 8))
19605 (clobber (reg:XF 9))
19606 (clobber (reg:XF 10))
19607 (clobber (reg:XF 11))
19608 (clobber (reg:XF 12))
19609 (clobber (reg:XF 13))
19610 (clobber (reg:XF 14))
19611 (clobber (reg:XF 15))
19612 (clobber (reg:DI 29))
19613 (clobber (reg:DI 30))
19614 (clobber (reg:DI 31))
19615 (clobber (reg:DI 32))
19616 (clobber (reg:DI 33))
19617 (clobber (reg:DI 34))
19618 (clobber (reg:DI 35))
19619 (clobber (reg:DI 36))]
19622 [(set_attr "type" "mmx")
19623 (set_attr "memory" "unknown")])
19625 (define_insn "ldmxcsr"
19626 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
19630 [(set_attr "type" "mmx")
19631 (set_attr "memory" "load")])
19633 (define_insn "stmxcsr"
19634 [(set (match_operand:SI 0 "memory_operand" "=m")
19635 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
19638 [(set_attr "type" "mmx")
19639 (set_attr "memory" "store")])
19641 (define_expand "sfence"
19642 [(set (match_dup 0)
19643 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
19644 "TARGET_SSE || TARGET_3DNOW_A"
19646 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
19647 MEM_VOLATILE_P (operands[0]) = 1;
19650 (define_insn "*sfence_insn"
19651 [(set (match_operand:BLK 0 "" "")
19652 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
19653 "TARGET_SSE || TARGET_3DNOW_A"
19655 [(set_attr "type" "sse")
19656 (set_attr "memory" "unknown")])
19658 (define_expand "sse_prologue_save"
19659 [(parallel [(set (match_operand:BLK 0 "" "")
19660 (unspec:BLK [(reg:DI 21)
19667 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
19668 (use (match_operand:DI 1 "register_operand" ""))
19669 (use (match_operand:DI 2 "immediate_operand" ""))
19670 (use (label_ref:DI (match_operand 3 "" "")))])]
19674 (define_insn "*sse_prologue_save_insn"
19675 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
19676 (match_operand:DI 4 "const_int_operand" "n")))
19677 (unspec:BLK [(reg:DI 21)
19684 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
19685 (use (match_operand:DI 1 "register_operand" "r"))
19686 (use (match_operand:DI 2 "const_int_operand" "i"))
19687 (use (label_ref:DI (match_operand 3 "" "X")))]
19689 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
19690 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
19694 operands[0] = gen_rtx_MEM (Pmode,
19695 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
19696 output_asm_insn (\"jmp\\t%A1\", operands);
19697 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
19699 operands[4] = adjust_address (operands[0], DImode, i*16);
19700 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
19701 PUT_MODE (operands[4], TImode);
19702 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
19703 output_asm_insn (\"rex\", operands);
19704 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
19706 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
19707 CODE_LABEL_NUMBER (operands[3]));
19711 [(set_attr "type" "other")
19712 (set_attr "length_immediate" "0")
19713 (set_attr "length_address" "0")
19714 (set_attr "length" "135")
19715 (set_attr "memory" "store")
19716 (set_attr "modrm" "0")
19717 (set_attr "mode" "DI")])
19719 ;; 3Dnow! instructions
19721 (define_insn "addv2sf3"
19722 [(set (match_operand:V2SF 0 "register_operand" "=y")
19723 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
19724 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19726 "pfadd\\t{%2, %0|%0, %2}"
19727 [(set_attr "type" "mmxadd")
19728 (set_attr "mode" "V2SF")])
19730 (define_insn "subv2sf3"
19731 [(set (match_operand:V2SF 0 "register_operand" "=y")
19732 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
19733 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19735 "pfsub\\t{%2, %0|%0, %2}"
19736 [(set_attr "type" "mmxadd")
19737 (set_attr "mode" "V2SF")])
19739 (define_insn "subrv2sf3"
19740 [(set (match_operand:V2SF 0 "register_operand" "=y")
19741 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
19742 (match_operand:V2SF 1 "register_operand" "0")))]
19744 "pfsubr\\t{%2, %0|%0, %2}"
19745 [(set_attr "type" "mmxadd")
19746 (set_attr "mode" "V2SF")])
19748 (define_insn "gtv2sf3"
19749 [(set (match_operand:V2SI 0 "register_operand" "=y")
19750 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
19751 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19753 "pfcmpgt\\t{%2, %0|%0, %2}"
19754 [(set_attr "type" "mmxcmp")
19755 (set_attr "mode" "V2SF")])
19757 (define_insn "gev2sf3"
19758 [(set (match_operand:V2SI 0 "register_operand" "=y")
19759 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
19760 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19762 "pfcmpge\\t{%2, %0|%0, %2}"
19763 [(set_attr "type" "mmxcmp")
19764 (set_attr "mode" "V2SF")])
19766 (define_insn "eqv2sf3"
19767 [(set (match_operand:V2SI 0 "register_operand" "=y")
19768 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
19769 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19771 "pfcmpeq\\t{%2, %0|%0, %2}"
19772 [(set_attr "type" "mmxcmp")
19773 (set_attr "mode" "V2SF")])
19775 (define_insn "pfmaxv2sf3"
19776 [(set (match_operand:V2SF 0 "register_operand" "=y")
19777 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
19778 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19780 "pfmax\\t{%2, %0|%0, %2}"
19781 [(set_attr "type" "mmxadd")
19782 (set_attr "mode" "V2SF")])
19784 (define_insn "pfminv2sf3"
19785 [(set (match_operand:V2SF 0 "register_operand" "=y")
19786 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
19787 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19789 "pfmin\\t{%2, %0|%0, %2}"
19790 [(set_attr "type" "mmxadd")
19791 (set_attr "mode" "V2SF")])
19793 (define_insn "mulv2sf3"
19794 [(set (match_operand:V2SF 0 "register_operand" "=y")
19795 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
19796 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19798 "pfmul\\t{%2, %0|%0, %2}"
19799 [(set_attr "type" "mmxmul")
19800 (set_attr "mode" "V2SF")])
19802 (define_insn "femms"
19803 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
19804 (clobber (reg:XF 8))
19805 (clobber (reg:XF 9))
19806 (clobber (reg:XF 10))
19807 (clobber (reg:XF 11))
19808 (clobber (reg:XF 12))
19809 (clobber (reg:XF 13))
19810 (clobber (reg:XF 14))
19811 (clobber (reg:XF 15))
19812 (clobber (reg:DI 29))
19813 (clobber (reg:DI 30))
19814 (clobber (reg:DI 31))
19815 (clobber (reg:DI 32))
19816 (clobber (reg:DI 33))
19817 (clobber (reg:DI 34))
19818 (clobber (reg:DI 35))
19819 (clobber (reg:DI 36))]
19822 [(set_attr "type" "mmx")])
19824 (define_insn "pf2id"
19825 [(set (match_operand:V2SI 0 "register_operand" "=y")
19826 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
19828 "pf2id\\t{%1, %0|%0, %1}"
19829 [(set_attr "type" "mmxcvt")
19830 (set_attr "mode" "V2SF")])
19832 (define_insn "pf2iw"
19833 [(set (match_operand:V2SI 0 "register_operand" "=y")
19836 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
19838 "pf2iw\\t{%1, %0|%0, %1}"
19839 [(set_attr "type" "mmxcvt")
19840 (set_attr "mode" "V2SF")])
19842 (define_insn "pfacc"
19843 [(set (match_operand:V2SF 0 "register_operand" "=y")
19846 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19847 (parallel [(const_int 0)]))
19848 (vec_select:SF (match_dup 1)
19849 (parallel [(const_int 1)])))
19851 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19852 (parallel [(const_int 0)]))
19853 (vec_select:SF (match_dup 2)
19854 (parallel [(const_int 1)])))))]
19856 "pfacc\\t{%2, %0|%0, %2}"
19857 [(set_attr "type" "mmxadd")
19858 (set_attr "mode" "V2SF")])
19860 (define_insn "pfnacc"
19861 [(set (match_operand:V2SF 0 "register_operand" "=y")
19864 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19865 (parallel [(const_int 0)]))
19866 (vec_select:SF (match_dup 1)
19867 (parallel [(const_int 1)])))
19869 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19870 (parallel [(const_int 0)]))
19871 (vec_select:SF (match_dup 2)
19872 (parallel [(const_int 1)])))))]
19874 "pfnacc\\t{%2, %0|%0, %2}"
19875 [(set_attr "type" "mmxadd")
19876 (set_attr "mode" "V2SF")])
19878 (define_insn "pfpnacc"
19879 [(set (match_operand:V2SF 0 "register_operand" "=y")
19882 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19883 (parallel [(const_int 0)]))
19884 (vec_select:SF (match_dup 1)
19885 (parallel [(const_int 1)])))
19887 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19888 (parallel [(const_int 0)]))
19889 (vec_select:SF (match_dup 2)
19890 (parallel [(const_int 1)])))))]
19892 "pfpnacc\\t{%2, %0|%0, %2}"
19893 [(set_attr "type" "mmxadd")
19894 (set_attr "mode" "V2SF")])
19896 (define_insn "pi2fw"
19897 [(set (match_operand:V2SF 0 "register_operand" "=y")
19902 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19903 (parallel [(const_int 0)]))))
19906 (vec_select:SI (match_dup 1)
19907 (parallel [(const_int 1)])))))))]
19909 "pi2fw\\t{%1, %0|%0, %1}"
19910 [(set_attr "type" "mmxcvt")
19911 (set_attr "mode" "V2SF")])
19913 (define_insn "floatv2si2"
19914 [(set (match_operand:V2SF 0 "register_operand" "=y")
19915 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
19917 "pi2fd\\t{%1, %0|%0, %1}"
19918 [(set_attr "type" "mmxcvt")
19919 (set_attr "mode" "V2SF")])
19921 ;; This insn is identical to pavgb in operation, but the opcode is
19922 ;; different. To avoid accidentally matching pavgb, use an unspec.
19924 (define_insn "pavgusb"
19925 [(set (match_operand:V8QI 0 "register_operand" "=y")
19927 [(match_operand:V8QI 1 "register_operand" "0")
19928 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
19931 "pavgusb\\t{%2, %0|%0, %2}"
19932 [(set_attr "type" "mmxshft")
19933 (set_attr "mode" "TI")])
19935 ;; 3DNow reciprical and sqrt
19937 (define_insn "pfrcpv2sf2"
19938 [(set (match_operand:V2SF 0 "register_operand" "=y")
19939 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
19942 "pfrcp\\t{%1, %0|%0, %1}"
19943 [(set_attr "type" "mmx")
19944 (set_attr "mode" "TI")])
19946 (define_insn "pfrcpit1v2sf3"
19947 [(set (match_operand:V2SF 0 "register_operand" "=y")
19948 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19949 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
19952 "pfrcpit1\\t{%2, %0|%0, %2}"
19953 [(set_attr "type" "mmx")
19954 (set_attr "mode" "TI")])
19956 (define_insn "pfrcpit2v2sf3"
19957 [(set (match_operand:V2SF 0 "register_operand" "=y")
19958 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19959 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
19962 "pfrcpit2\\t{%2, %0|%0, %2}"
19963 [(set_attr "type" "mmx")
19964 (set_attr "mode" "TI")])
19966 (define_insn "pfrsqrtv2sf2"
19967 [(set (match_operand:V2SF 0 "register_operand" "=y")
19968 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
19971 "pfrsqrt\\t{%1, %0|%0, %1}"
19972 [(set_attr "type" "mmx")
19973 (set_attr "mode" "TI")])
19975 (define_insn "pfrsqit1v2sf3"
19976 [(set (match_operand:V2SF 0 "register_operand" "=y")
19977 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19978 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
19981 "pfrsqit1\\t{%2, %0|%0, %2}"
19982 [(set_attr "type" "mmx")
19983 (set_attr "mode" "TI")])
19985 (define_insn "pmulhrwv4hi3"
19986 [(set (match_operand:V4HI 0 "register_operand" "=y")
19992 (match_operand:V4HI 1 "register_operand" "0"))
19994 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19995 (const_vector:V4SI [(const_int 32768)
19998 (const_int 32768)]))
20001 "pmulhrw\\t{%2, %0|%0, %2}"
20002 [(set_attr "type" "mmxmul")
20003 (set_attr "mode" "TI")])
20005 (define_insn "pswapdv2si2"
20006 [(set (match_operand:V2SI 0 "register_operand" "=y")
20007 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
20008 (parallel [(const_int 1) (const_int 0)])))]
20010 "pswapd\\t{%1, %0|%0, %1}"
20011 [(set_attr "type" "mmxcvt")
20012 (set_attr "mode" "TI")])
20014 (define_insn "pswapdv2sf2"
20015 [(set (match_operand:V2SF 0 "register_operand" "=y")
20016 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
20017 (parallel [(const_int 1) (const_int 0)])))]
20019 "pswapd\\t{%1, %0|%0, %1}"
20020 [(set_attr "type" "mmxcvt")
20021 (set_attr "mode" "TI")])
20023 (define_expand "prefetch"
20024 [(prefetch (match_operand 0 "address_operand" "")
20025 (match_operand:SI 1 "const_int_operand" "")
20026 (match_operand:SI 2 "const_int_operand" ""))]
20027 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
20029 int rw = INTVAL (operands[1]);
20030 int locality = INTVAL (operands[2]);
20032 if (rw != 0 && rw != 1)
20034 if (locality < 0 || locality > 3)
20036 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
20039 /* Use 3dNOW prefetch in case we are asking for write prefetch not
20040 suported by SSE counterpart or the SSE prefetch is not available
20041 (K6 machines). Otherwise use SSE prefetch as it allows specifying
20043 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
20044 operands[2] = GEN_INT (3);
20046 operands[1] = const0_rtx;
20049 (define_insn "*prefetch_sse"
20050 [(prefetch (match_operand:SI 0 "address_operand" "p")
20052 (match_operand:SI 1 "const_int_operand" ""))]
20053 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
20055 static const char * const patterns[4] = {
20056 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
20059 int locality = INTVAL (operands[1]);
20060 if (locality < 0 || locality > 3)
20063 return patterns[locality];
20065 [(set_attr "type" "sse")
20066 (set_attr "memory" "none")])
20068 (define_insn "*prefetch_sse_rex"
20069 [(prefetch (match_operand:DI 0 "address_operand" "p")
20071 (match_operand:SI 1 "const_int_operand" ""))]
20072 "TARGET_PREFETCH_SSE && TARGET_64BIT"
20074 static const char * const patterns[4] = {
20075 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
20078 int locality = INTVAL (operands[1]);
20079 if (locality < 0 || locality > 3)
20082 return patterns[locality];
20084 [(set_attr "type" "sse")
20085 (set_attr "memory" "none")])
20087 (define_insn "*prefetch_3dnow"
20088 [(prefetch (match_operand:SI 0 "address_operand" "p")
20089 (match_operand:SI 1 "const_int_operand" "n")
20091 "TARGET_3DNOW && !TARGET_64BIT"
20093 if (INTVAL (operands[1]) == 0)
20094 return "prefetch\t%a0";
20096 return "prefetchw\t%a0";
20098 [(set_attr "type" "mmx")
20099 (set_attr "memory" "none")])
20101 (define_insn "*prefetch_3dnow_rex"
20102 [(prefetch (match_operand:DI 0 "address_operand" "p")
20103 (match_operand:SI 1 "const_int_operand" "n")
20105 "TARGET_3DNOW && TARGET_64BIT"
20107 if (INTVAL (operands[1]) == 0)
20108 return "prefetch\t%a0";
20110 return "prefetchw\t%a0";
20112 [(set_attr "type" "mmx")
20113 (set_attr "memory" "none")])
20117 (define_insn "addv2df3"
20118 [(set (match_operand:V2DF 0 "register_operand" "=x")
20119 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20120 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20122 "addpd\t{%2, %0|%0, %2}"
20123 [(set_attr "type" "sseadd")
20124 (set_attr "mode" "V2DF")])
20126 (define_insn "vmaddv2df3"
20127 [(set (match_operand:V2DF 0 "register_operand" "=x")
20128 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20129 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20133 "addsd\t{%2, %0|%0, %2}"
20134 [(set_attr "type" "sseadd")
20135 (set_attr "mode" "DF")])
20137 (define_insn "subv2df3"
20138 [(set (match_operand:V2DF 0 "register_operand" "=x")
20139 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20140 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20142 "subpd\t{%2, %0|%0, %2}"
20143 [(set_attr "type" "sseadd")
20144 (set_attr "mode" "V2DF")])
20146 (define_insn "vmsubv2df3"
20147 [(set (match_operand:V2DF 0 "register_operand" "=x")
20148 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20149 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20153 "subsd\t{%2, %0|%0, %2}"
20154 [(set_attr "type" "sseadd")
20155 (set_attr "mode" "DF")])
20157 (define_insn "mulv2df3"
20158 [(set (match_operand:V2DF 0 "register_operand" "=x")
20159 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
20160 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20162 "mulpd\t{%2, %0|%0, %2}"
20163 [(set_attr "type" "ssemul")
20164 (set_attr "mode" "V2DF")])
20166 (define_insn "vmmulv2df3"
20167 [(set (match_operand:V2DF 0 "register_operand" "=x")
20168 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
20169 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20173 "mulsd\t{%2, %0|%0, %2}"
20174 [(set_attr "type" "ssemul")
20175 (set_attr "mode" "DF")])
20177 (define_insn "divv2df3"
20178 [(set (match_operand:V2DF 0 "register_operand" "=x")
20179 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
20180 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20182 "divpd\t{%2, %0|%0, %2}"
20183 [(set_attr "type" "ssediv")
20184 (set_attr "mode" "V2DF")])
20186 (define_insn "vmdivv2df3"
20187 [(set (match_operand:V2DF 0 "register_operand" "=x")
20188 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
20189 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20193 "divsd\t{%2, %0|%0, %2}"
20194 [(set_attr "type" "ssediv")
20195 (set_attr "mode" "DF")])
20199 (define_insn "smaxv2df3"
20200 [(set (match_operand:V2DF 0 "register_operand" "=x")
20201 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
20202 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20204 "maxpd\t{%2, %0|%0, %2}"
20205 [(set_attr "type" "sseadd")
20206 (set_attr "mode" "V2DF")])
20208 (define_insn "vmsmaxv2df3"
20209 [(set (match_operand:V2DF 0 "register_operand" "=x")
20210 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
20211 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20215 "maxsd\t{%2, %0|%0, %2}"
20216 [(set_attr "type" "sseadd")
20217 (set_attr "mode" "DF")])
20219 (define_insn "sminv2df3"
20220 [(set (match_operand:V2DF 0 "register_operand" "=x")
20221 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
20222 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20224 "minpd\t{%2, %0|%0, %2}"
20225 [(set_attr "type" "sseadd")
20226 (set_attr "mode" "V2DF")])
20228 (define_insn "vmsminv2df3"
20229 [(set (match_operand:V2DF 0 "register_operand" "=x")
20230 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
20231 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20235 "minsd\t{%2, %0|%0, %2}"
20236 [(set_attr "type" "sseadd")
20237 (set_attr "mode" "DF")])
20239 (define_insn "sse2_anddf3"
20240 [(set (match_operand:V2DF 0 "register_operand" "=x")
20241 (subreg:V2DF (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
20242 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
20244 "andpd\t{%2, %0|%0, %2}"
20245 [(set_attr "type" "sselog")
20246 (set_attr "mode" "V2DF")])
20248 (define_insn "sse2_nanddf3"
20249 [(set (match_operand:V2DF 0 "register_operand" "=x")
20250 (subreg:V2DF (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "0") 0))
20251 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
20253 "andnpd\t{%2, %0|%0, %2}"
20254 [(set_attr "type" "sselog")
20255 (set_attr "mode" "V2DF")])
20257 (define_insn "sse2_iordf3"
20258 [(set (match_operand:V2DF 0 "register_operand" "=x")
20259 (subreg:V2DF (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
20260 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
20262 "orpd\t{%2, %0|%0, %2}"
20263 [(set_attr "type" "sselog")
20264 (set_attr "mode" "V2DF")])
20266 (define_insn "sse2_xordf3"
20267 [(set (match_operand:V2DF 0 "register_operand" "=x")
20268 (subreg:V2DF (xor:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
20269 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
20271 "xorpd\t{%2, %0|%0, %2}"
20272 [(set_attr "type" "sselog")
20273 (set_attr "mode" "V2DF")])
20274 ;; SSE2 square root. There doesn't appear to be an extension for the
20275 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
20277 (define_insn "sqrtv2df2"
20278 [(set (match_operand:V2DF 0 "register_operand" "=x")
20279 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
20281 "sqrtpd\t{%1, %0|%0, %1}"
20282 [(set_attr "type" "sse")
20283 (set_attr "mode" "V2DF")])
20285 (define_insn "vmsqrtv2df2"
20286 [(set (match_operand:V2DF 0 "register_operand" "=x")
20287 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
20288 (match_operand:V2DF 2 "register_operand" "0")
20291 "sqrtsd\t{%1, %0|%0, %1}"
20292 [(set_attr "type" "sse")
20293 (set_attr "mode" "SF")])
20295 ;; SSE mask-generating compares
20297 (define_insn "maskcmpv2df3"
20298 [(set (match_operand:V2DI 0 "register_operand" "=x")
20299 (match_operator:V2DI 3 "sse_comparison_operator"
20300 [(match_operand:V2DF 1 "register_operand" "0")
20301 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
20303 "cmp%D3pd\t{%2, %0|%0, %2}"
20304 [(set_attr "type" "ssecmp")
20305 (set_attr "mode" "V2DF")])
20307 (define_insn "maskncmpv2df3"
20308 [(set (match_operand:V2DI 0 "register_operand" "=x")
20310 (match_operator:V2DI 3 "sse_comparison_operator"
20311 [(match_operand:V2DF 1 "register_operand" "0")
20312 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
20314 "cmpn%D3pd\t{%2, %0|%0, %2}"
20315 [(set_attr "type" "ssecmp")
20316 (set_attr "mode" "V2DF")])
20318 (define_insn "vmmaskcmpv2df3"
20319 [(set (match_operand:V2DI 0 "register_operand" "=x")
20321 (match_operator:V2DI 3 "sse_comparison_operator"
20322 [(match_operand:V2DF 1 "register_operand" "0")
20323 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
20327 "cmp%D3sd\t{%2, %0|%0, %2}"
20328 [(set_attr "type" "ssecmp")
20329 (set_attr "mode" "DF")])
20331 (define_insn "vmmaskncmpv2df3"
20332 [(set (match_operand:V2DI 0 "register_operand" "=x")
20335 (match_operator:V2DI 3 "sse_comparison_operator"
20336 [(match_operand:V2DF 1 "register_operand" "0")
20337 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
20338 (subreg:V2DI (match_dup 1) 0)
20341 "cmp%D3sd\t{%2, %0|%0, %2}"
20342 [(set_attr "type" "ssecmp")
20343 (set_attr "mode" "DF")])
20345 (define_insn "sse2_comi"
20346 [(set (reg:CCFP 17)
20347 (match_operator:CCFP 2 "sse_comparison_operator"
20349 (match_operand:V2DF 0 "register_operand" "x")
20350 (parallel [(const_int 0)]))
20352 (match_operand:V2DF 1 "register_operand" "x")
20353 (parallel [(const_int 0)]))]))]
20355 "comisd\t{%1, %0|%0, %1}"
20356 [(set_attr "type" "ssecmp")
20357 (set_attr "mode" "DF")])
20359 (define_insn "sse2_ucomi"
20360 [(set (reg:CCFPU 17)
20361 (match_operator:CCFPU 2 "sse_comparison_operator"
20363 (match_operand:V2DF 0 "register_operand" "x")
20364 (parallel [(const_int 0)]))
20366 (match_operand:V2DF 1 "register_operand" "x")
20367 (parallel [(const_int 0)]))]))]
20369 "ucomisd\t{%1, %0|%0, %1}"
20370 [(set_attr "type" "ssecmp")
20371 (set_attr "mode" "DF")])
20373 ;; SSE Strange Moves.
20375 (define_insn "sse2_movmskpd"
20376 [(set (match_operand:SI 0 "register_operand" "=r")
20377 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
20380 "movmskpd\t{%1, %0|%0, %1}"
20381 [(set_attr "type" "ssecvt")
20382 (set_attr "mode" "V2DF")])
20384 (define_insn "sse2_pmovmskb"
20385 [(set (match_operand:SI 0 "register_operand" "=r")
20386 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
20389 "pmovmskb\t{%1, %0|%0, %1}"
20390 [(set_attr "type" "ssecvt")
20391 (set_attr "mode" "V2DF")])
20393 (define_insn "sse2_maskmovdqu"
20394 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
20395 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
20396 (match_operand:V16QI 2 "register_operand" "x")]
20399 ;; @@@ check ordering of operands in intel/nonintel syntax
20400 "maskmovdqu\t{%2, %1|%1, %2}"
20401 [(set_attr "type" "ssecvt")
20402 (set_attr "mode" "TI")])
20404 (define_insn "sse2_movntv2df"
20405 [(set (match_operand:V2DF 0 "memory_operand" "=m")
20406 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
20409 "movntpd\t{%1, %0|%0, %1}"
20410 [(set_attr "type" "ssecvt")
20411 (set_attr "mode" "V2DF")])
20413 (define_insn "sse2_movntv2di"
20414 [(set (match_operand:V2DI 0 "memory_operand" "=m")
20415 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
20418 "movntdq\t{%1, %0|%0, %1}"
20419 [(set_attr "type" "ssecvt")
20420 (set_attr "mode" "TI")])
20422 (define_insn "sse2_movntsi"
20423 [(set (match_operand:SI 0 "memory_operand" "=m")
20424 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
20427 "movnti\t{%1, %0|%0, %1}"
20428 [(set_attr "type" "ssecvt")
20429 (set_attr "mode" "V2DF")])
20431 ;; SSE <-> integer/MMX conversions
20433 ;; Conversions between SI and SF
20435 (define_insn "cvtdq2ps"
20436 [(set (match_operand:V4SF 0 "register_operand" "=x")
20437 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
20439 "cvtdq2ps\t{%1, %0|%0, %1}"
20440 [(set_attr "type" "ssecvt")
20441 (set_attr "mode" "V2DF")])
20443 (define_insn "cvtps2dq"
20444 [(set (match_operand:V4SI 0 "register_operand" "=x")
20445 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
20447 "cvtps2dq\t{%1, %0|%0, %1}"
20448 [(set_attr "type" "ssecvt")
20449 (set_attr "mode" "TI")])
20451 (define_insn "cvttps2dq"
20452 [(set (match_operand:V4SI 0 "register_operand" "=x")
20453 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20456 "cvttps2dq\t{%1, %0|%0, %1}"
20457 [(set_attr "type" "ssecvt")
20458 (set_attr "mode" "TI")])
20460 ;; Conversions between SI and DF
20462 (define_insn "cvtdq2pd"
20463 [(set (match_operand:V2DF 0 "register_operand" "=x")
20464 (float:V2DF (vec_select:V2SI
20465 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
20468 (const_int 1)]))))]
20470 "cvtdq2pd\t{%1, %0|%0, %1}"
20471 [(set_attr "type" "ssecvt")
20472 (set_attr "mode" "V2DF")])
20474 (define_insn "cvtpd2dq"
20475 [(set (match_operand:V4SI 0 "register_operand" "=x")
20477 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
20478 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
20480 "cvtpd2dq\t{%1, %0|%0, %1}"
20481 [(set_attr "type" "ssecvt")
20482 (set_attr "mode" "TI")])
20484 (define_insn "cvttpd2dq"
20485 [(set (match_operand:V4SI 0 "register_operand" "=x")
20487 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
20489 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
20491 "cvttpd2dq\t{%1, %0|%0, %1}"
20492 [(set_attr "type" "ssecvt")
20493 (set_attr "mode" "TI")])
20495 (define_insn "cvtpd2pi"
20496 [(set (match_operand:V2SI 0 "register_operand" "=y")
20497 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
20499 "cvtpd2pi\t{%1, %0|%0, %1}"
20500 [(set_attr "type" "ssecvt")
20501 (set_attr "mode" "TI")])
20503 (define_insn "cvttpd2pi"
20504 [(set (match_operand:V2SI 0 "register_operand" "=y")
20505 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
20508 "cvttpd2pi\t{%1, %0|%0, %1}"
20509 [(set_attr "type" "ssecvt")
20510 (set_attr "mode" "TI")])
20512 (define_insn "cvtpi2pd"
20513 [(set (match_operand:V2DF 0 "register_operand" "=x")
20514 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
20516 "cvtpi2pd\t{%1, %0|%0, %1}"
20517 [(set_attr "type" "ssecvt")
20518 (set_attr "mode" "TI")])
20520 ;; Conversions between SI and DF
20522 (define_insn "cvtsd2si"
20523 [(set (match_operand:SI 0 "register_operand" "=r")
20524 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20525 (parallel [(const_int 0)]))))]
20527 "cvtsd2si\t{%1, %0|%0, %1}"
20528 [(set_attr "type" "ssecvt")
20529 (set_attr "mode" "SI")])
20531 (define_insn "cvttsd2si"
20532 [(set (match_operand:SI 0 "register_operand" "=r")
20533 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20534 (parallel [(const_int 0)]))] UNSPEC_FIX))]
20536 "cvttsd2si\t{%1, %0|%0, %1}"
20537 [(set_attr "type" "ssecvt")
20538 (set_attr "mode" "SI")])
20540 (define_insn "cvtsi2sd"
20541 [(set (match_operand:V2DF 0 "register_operand" "=x")
20542 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
20543 (vec_duplicate:V2DF
20545 (match_operand:SI 2 "nonimmediate_operand" "rm")))
20548 "cvtsd2si\t{%2, %0|%0, %2}"
20549 [(set_attr "type" "ssecvt")
20550 (set_attr "mode" "DF")])
20552 ;; Conversions between SF and DF
20554 (define_insn "cvtsd2ss"
20555 [(set (match_operand:V4SF 0 "register_operand" "=x")
20556 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
20557 (vec_duplicate:V4SF
20558 (float_truncate:V2SF
20559 (match_operand:V2DF 2 "register_operand" "xm")))
20562 "cvtsd2ss\t{%2, %0|%0, %2}"
20563 [(set_attr "type" "ssecvt")
20564 (set_attr "mode" "SF")])
20566 (define_insn "cvtss2sd"
20567 [(set (match_operand:V2DF 0 "register_operand" "=x")
20568 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
20571 (match_operand:V4SF 2 "register_operand" "xm")
20572 (parallel [(const_int 0)
20576 "cvtss2sd\t{%2, %0|%0, %2}"
20577 [(set_attr "type" "ssecvt")
20578 (set_attr "mode" "DF")])
20580 (define_insn "cvtpd2ps"
20581 [(set (match_operand:V4SF 0 "register_operand" "=x")
20584 (subreg:V2SI (float_truncate:V2SF
20585 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
20586 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
20588 "cvtpd2ps\t{%1, %0|%0, %1}"
20589 [(set_attr "type" "ssecvt")
20590 (set_attr "mode" "V4SF")])
20592 (define_insn "cvtps2pd"
20593 [(set (match_operand:V2DF 0 "register_operand" "=x")
20595 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
20596 (parallel [(const_int 0)
20597 (const_int 1)]))))]
20599 "cvtps2pd\t{%1, %0|%0, %1}"
20600 [(set_attr "type" "ssecvt")
20601 (set_attr "mode" "V2DF")])
20603 ;; SSE2 variants of MMX insns
20607 (define_insn "addv16qi3"
20608 [(set (match_operand:V16QI 0 "register_operand" "=x")
20609 (plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20610 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20612 "paddb\t{%2, %0|%0, %2}"
20613 [(set_attr "type" "sseiadd")
20614 (set_attr "mode" "TI")])
20616 (define_insn "addv8hi3"
20617 [(set (match_operand:V8HI 0 "register_operand" "=x")
20618 (plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20619 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20621 "paddw\t{%2, %0|%0, %2}"
20622 [(set_attr "type" "sseiadd")
20623 (set_attr "mode" "TI")])
20625 (define_insn "addv4si3"
20626 [(set (match_operand:V4SI 0 "register_operand" "=x")
20627 (plus:V4SI (match_operand:V4SI 1 "register_operand" "0")
20628 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20630 "paddd\t{%2, %0|%0, %2}"
20631 [(set_attr "type" "sseiadd")
20632 (set_attr "mode" "TI")])
20634 (define_insn "addv2di3"
20635 [(set (match_operand:V2DI 0 "register_operand" "=x")
20636 (plus:V2DI (match_operand:V2DI 1 "register_operand" "0")
20637 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20639 "paddq\t{%2, %0|%0, %2}"
20640 [(set_attr "type" "sseiadd")
20641 (set_attr "mode" "TI")])
20643 (define_insn "ssaddv16qi3"
20644 [(set (match_operand:V16QI 0 "register_operand" "=x")
20645 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20646 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20648 "paddsb\t{%2, %0|%0, %2}"
20649 [(set_attr "type" "sseiadd")
20650 (set_attr "mode" "TI")])
20652 (define_insn "ssaddv8hi3"
20653 [(set (match_operand:V8HI 0 "register_operand" "=x")
20654 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20655 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20657 "paddsw\t{%2, %0|%0, %2}"
20658 [(set_attr "type" "sseiadd")
20659 (set_attr "mode" "TI")])
20661 (define_insn "usaddv16qi3"
20662 [(set (match_operand:V16QI 0 "register_operand" "=x")
20663 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20664 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20666 "paddusb\t{%2, %0|%0, %2}"
20667 [(set_attr "type" "sseiadd")
20668 (set_attr "mode" "TI")])
20670 (define_insn "usaddv8hi3"
20671 [(set (match_operand:V8HI 0 "register_operand" "=x")
20672 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20673 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20675 "paddusw\t{%2, %0|%0, %2}"
20676 [(set_attr "type" "sseiadd")
20677 (set_attr "mode" "TI")])
20679 (define_insn "subv16qi3"
20680 [(set (match_operand:V16QI 0 "register_operand" "=x")
20681 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20682 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20684 "psubb\t{%2, %0|%0, %2}"
20685 [(set_attr "type" "sseiadd")
20686 (set_attr "mode" "TI")])
20688 (define_insn "subv8hi3"
20689 [(set (match_operand:V8HI 0 "register_operand" "=x")
20690 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20691 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20693 "psubw\t{%2, %0|%0, %2}"
20694 [(set_attr "type" "sseiadd")
20695 (set_attr "mode" "TI")])
20697 (define_insn "subv4si3"
20698 [(set (match_operand:V4SI 0 "register_operand" "=x")
20699 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
20700 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20702 "psubd\t{%2, %0|%0, %2}"
20703 [(set_attr "type" "sseiadd")
20704 (set_attr "mode" "TI")])
20706 (define_insn "subv2di3"
20707 [(set (match_operand:V2DI 0 "register_operand" "=x")
20708 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
20709 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20711 "psubq\t{%2, %0|%0, %2}"
20712 [(set_attr "type" "sseiadd")
20713 (set_attr "mode" "TI")])
20715 (define_insn "sssubv16qi3"
20716 [(set (match_operand:V16QI 0 "register_operand" "=x")
20717 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20718 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20720 "psubsb\t{%2, %0|%0, %2}"
20721 [(set_attr "type" "sseiadd")
20722 (set_attr "mode" "TI")])
20724 (define_insn "sssubv8hi3"
20725 [(set (match_operand:V8HI 0 "register_operand" "=x")
20726 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20727 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20729 "psubsw\t{%2, %0|%0, %2}"
20730 [(set_attr "type" "sseiadd")
20731 (set_attr "mode" "TI")])
20733 (define_insn "ussubv16qi3"
20734 [(set (match_operand:V16QI 0 "register_operand" "=x")
20735 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20736 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20738 "psubusb\t{%2, %0|%0, %2}"
20739 [(set_attr "type" "sseiadd")
20740 (set_attr "mode" "TI")])
20742 (define_insn "ussubv8hi3"
20743 [(set (match_operand:V8HI 0 "register_operand" "=x")
20744 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20745 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20747 "psubusw\t{%2, %0|%0, %2}"
20748 [(set_attr "type" "sseiadd")
20749 (set_attr "mode" "TI")])
20751 (define_insn "mulv8hi3"
20752 [(set (match_operand:V8HI 0 "register_operand" "=x")
20753 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
20754 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20756 "pmullw\t{%2, %0|%0, %2}"
20757 [(set_attr "type" "sseimul")
20758 (set_attr "mode" "TI")])
20760 (define_insn "smulv8hi3_highpart"
20761 [(set (match_operand:V8HI 0 "register_operand" "=x")
20764 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
20765 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
20768 "pmulhw\t{%2, %0|%0, %2}"
20769 [(set_attr "type" "sseimul")
20770 (set_attr "mode" "TI")])
20772 (define_insn "umulv8hi3_highpart"
20773 [(set (match_operand:V8HI 0 "register_operand" "=x")
20776 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
20777 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
20780 "pmulhuw\t{%2, %0|%0, %2}"
20781 [(set_attr "type" "sseimul")
20782 (set_attr "mode" "TI")])
20784 (define_insn "sse2_umulsidi3"
20785 [(set (match_operand:DI 0 "register_operand" "=y")
20786 (mult:DI (zero_extend:DI (vec_select:SI
20787 (match_operand:V2SI 1 "register_operand" "0")
20788 (parallel [(const_int 0)])))
20789 (zero_extend:DI (vec_select:SI
20790 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
20791 (parallel [(const_int 0)])))))]
20793 "pmuludq\t{%2, %0|%0, %2}"
20794 [(set_attr "type" "sseimul")
20795 (set_attr "mode" "TI")])
20797 (define_insn "sse2_umulv2siv2di3"
20798 [(set (match_operand:V2DI 0 "register_operand" "=y")
20799 (mult:V2DI (zero_extend:V2DI
20801 (match_operand:V4SI 1 "register_operand" "0")
20802 (parallel [(const_int 0) (const_int 2)])))
20805 (match_operand:V4SI 2 "nonimmediate_operand" "ym")
20806 (parallel [(const_int 0) (const_int 2)])))))]
20808 "pmuludq\t{%2, %0|%0, %2}"
20809 [(set_attr "type" "sseimul")
20810 (set_attr "mode" "TI")])
20812 (define_insn "sse2_pmaddwd"
20813 [(set (match_operand:V4SI 0 "register_operand" "=x")
20816 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
20817 (parallel [(const_int 0)
20821 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
20822 (parallel [(const_int 0)
20827 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
20828 (parallel [(const_int 1)
20832 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
20833 (parallel [(const_int 1)
20836 (const_int 7)]))))))]
20838 "pmaddwd\t{%2, %0|%0, %2}"
20839 [(set_attr "type" "sseiadd")
20840 (set_attr "mode" "TI")])
20842 ;; Same as pxor, but don't show input operands so that we don't think
20844 (define_insn "sse2_clrti"
20845 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
20847 "pxor\t{%0, %0|%0, %0}"
20848 [(set_attr "type" "sseiadd")
20849 (set_attr "memory" "none")
20850 (set_attr "mode" "TI")])
20852 ;; MMX unsigned averages/sum of absolute differences
20854 (define_insn "sse2_uavgv16qi3"
20855 [(set (match_operand:V16QI 0 "register_operand" "=x")
20857 (plus:V16QI (plus:V16QI
20858 (match_operand:V16QI 1 "register_operand" "0")
20859 (match_operand:V16QI 2 "nonimmediate_operand" "ym"))
20860 (const_vector:V16QI [(const_int 1) (const_int 1)
20861 (const_int 1) (const_int 1)
20862 (const_int 1) (const_int 1)
20863 (const_int 1) (const_int 1)
20864 (const_int 1) (const_int 1)
20865 (const_int 1) (const_int 1)
20866 (const_int 1) (const_int 1)
20867 (const_int 1) (const_int 1)]))
20870 "pavgb\t{%2, %0|%0, %2}"
20871 [(set_attr "type" "sseiadd")
20872 (set_attr "mode" "TI")])
20874 (define_insn "sse2_uavgv8hi3"
20875 [(set (match_operand:V8HI 0 "register_operand" "=x")
20877 (plus:V8HI (plus:V8HI
20878 (match_operand:V8HI 1 "register_operand" "0")
20879 (match_operand:V8HI 2 "nonimmediate_operand" "ym"))
20880 (const_vector:V8HI [(const_int 1) (const_int 1)
20881 (const_int 1) (const_int 1)
20882 (const_int 1) (const_int 1)
20883 (const_int 1) (const_int 1)]))
20886 "pavgw\t{%2, %0|%0, %2}"
20887 [(set_attr "type" "sseiadd")
20888 (set_attr "mode" "TI")])
20890 ;; @@@ this isn't the right representation.
20891 (define_insn "sse2_psadbw"
20892 [(set (match_operand:V2DI 0 "register_operand" "=x")
20893 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
20894 (match_operand:V16QI 2 "nonimmediate_operand" "ym")]
20897 "psadbw\t{%2, %0|%0, %2}"
20898 [(set_attr "type" "sseiadd")
20899 (set_attr "mode" "TI")])
20902 ;; MMX insert/extract/shuffle
20904 (define_insn "sse2_pinsrw"
20905 [(set (match_operand:V8HI 0 "register_operand" "=x")
20906 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
20907 (vec_duplicate:V8HI
20908 (match_operand:SI 2 "nonimmediate_operand" "rm"))
20909 (match_operand:SI 3 "immediate_operand" "i")))]
20911 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20912 [(set_attr "type" "ssecvt")
20913 (set_attr "mode" "TI")])
20915 (define_insn "sse2_pextrw"
20916 [(set (match_operand:SI 0 "register_operand" "=r")
20918 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
20920 [(match_operand:SI 2 "immediate_operand" "i")]))))]
20922 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20923 [(set_attr "type" "ssecvt")
20924 (set_attr "mode" "TI")])
20926 (define_insn "sse2_pshufd"
20927 [(set (match_operand:V4SI 0 "register_operand" "=x")
20928 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
20929 (match_operand:SI 2 "immediate_operand" "i")]
20932 "pshufd\t{%2, %1, %0|%0, %1, %2}"
20933 [(set_attr "type" "ssecvt")
20934 (set_attr "mode" "TI")])
20936 (define_insn "sse2_pshuflw"
20937 [(set (match_operand:V8HI 0 "register_operand" "=x")
20938 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
20939 (match_operand:SI 2 "immediate_operand" "i")]
20942 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
20943 [(set_attr "type" "ssecvt")
20944 (set_attr "mode" "TI")])
20946 (define_insn "sse2_pshufhw"
20947 [(set (match_operand:V8HI 0 "register_operand" "=x")
20948 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
20949 (match_operand:SI 2 "immediate_operand" "i")]
20952 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
20953 [(set_attr "type" "ssecvt")
20954 (set_attr "mode" "TI")])
20956 ;; MMX mask-generating comparisons
20958 (define_insn "eqv16qi3"
20959 [(set (match_operand:V16QI 0 "register_operand" "=x")
20960 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
20961 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20963 "pcmpeqb\t{%2, %0|%0, %2}"
20964 [(set_attr "type" "ssecmp")
20965 (set_attr "mode" "TI")])
20967 (define_insn "eqv8hi3"
20968 [(set (match_operand:V8HI 0 "register_operand" "=x")
20969 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
20970 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20972 "pcmpeqw\t{%2, %0|%0, %2}"
20973 [(set_attr "type" "ssecmp")
20974 (set_attr "mode" "TI")])
20976 (define_insn "eqv4si3"
20977 [(set (match_operand:V4SI 0 "register_operand" "=x")
20978 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
20979 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20981 "pcmpeqd\t{%2, %0|%0, %2}"
20982 [(set_attr "type" "ssecmp")
20983 (set_attr "mode" "TI")])
20985 (define_insn "gtv16qi3"
20986 [(set (match_operand:V16QI 0 "register_operand" "=x")
20987 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
20988 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20990 "pcmpgtb\t{%2, %0|%0, %2}"
20991 [(set_attr "type" "ssecmp")
20992 (set_attr "mode" "TI")])
20994 (define_insn "gtv8hi3"
20995 [(set (match_operand:V8HI 0 "register_operand" "=x")
20996 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
20997 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20999 "pcmpgtw\t{%2, %0|%0, %2}"
21000 [(set_attr "type" "ssecmp")
21001 (set_attr "mode" "TI")])
21003 (define_insn "gtv4si3"
21004 [(set (match_operand:V4SI 0 "register_operand" "=x")
21005 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21006 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21008 "pcmpgtd\t{%2, %0|%0, %2}"
21009 [(set_attr "type" "ssecmp")
21010 (set_attr "mode" "TI")])
21013 ;; MMX max/min insns
21015 (define_insn "umaxv16qi3"
21016 [(set (match_operand:V16QI 0 "register_operand" "=x")
21017 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
21018 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21020 "pmaxub\t{%2, %0|%0, %2}"
21021 [(set_attr "type" "sseiadd")
21022 (set_attr "mode" "TI")])
21024 (define_insn "smaxv8hi3"
21025 [(set (match_operand:V8HI 0 "register_operand" "=x")
21026 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
21027 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21029 "pmaxsw\t{%2, %0|%0, %2}"
21030 [(set_attr "type" "sseiadd")
21031 (set_attr "mode" "TI")])
21033 (define_insn "uminv16qi3"
21034 [(set (match_operand:V16QI 0 "register_operand" "=x")
21035 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
21036 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21038 "pminub\t{%2, %0|%0, %2}"
21039 [(set_attr "type" "sseiadd")
21040 (set_attr "mode" "TI")])
21042 (define_insn "sminv8hi3"
21043 [(set (match_operand:V8HI 0 "register_operand" "=x")
21044 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
21045 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21047 "pminsw\t{%2, %0|%0, %2}"
21048 [(set_attr "type" "sseiadd")
21049 (set_attr "mode" "TI")])
21054 (define_insn "ashrv8hi3"
21055 [(set (match_operand:V8HI 0 "register_operand" "=x")
21056 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21057 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21059 "psraw\t{%2, %0|%0, %2}"
21060 [(set_attr "type" "sseishft")
21061 (set_attr "mode" "TI")])
21063 (define_insn "ashrv4si3"
21064 [(set (match_operand:V4SI 0 "register_operand" "=x")
21065 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21066 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21068 "psrad\t{%2, %0|%0, %2}"
21069 [(set_attr "type" "sseishft")
21070 (set_attr "mode" "TI")])
21072 (define_insn "lshrv8hi3"
21073 [(set (match_operand:V8HI 0 "register_operand" "=x")
21074 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21075 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21077 "psrlw\t{%2, %0|%0, %2}"
21078 [(set_attr "type" "sseishft")
21079 (set_attr "mode" "TI")])
21081 (define_insn "lshrv4si3"
21082 [(set (match_operand:V4SI 0 "register_operand" "=x")
21083 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21084 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21086 "psrld\t{%2, %0|%0, %2}"
21087 [(set_attr "type" "sseishft")
21088 (set_attr "mode" "TI")])
21090 (define_insn "lshrv2di3"
21091 [(set (match_operand:V2DI 0 "register_operand" "=x")
21092 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
21093 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21095 "psrlq\t{%2, %0|%0, %2}"
21096 [(set_attr "type" "sseishft")
21097 (set_attr "mode" "TI")])
21099 (define_insn "ashlv8hi3"
21100 [(set (match_operand:V8HI 0 "register_operand" "=x")
21101 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
21102 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21104 "psllw\t{%2, %0|%0, %2}"
21105 [(set_attr "type" "sseishft")
21106 (set_attr "mode" "TI")])
21108 (define_insn "ashlv4si3"
21109 [(set (match_operand:V4SI 0 "register_operand" "=x")
21110 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
21111 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21113 "pslld\t{%2, %0|%0, %2}"
21114 [(set_attr "type" "sseishft")
21115 (set_attr "mode" "TI")])
21117 (define_insn "ashlv2di3"
21118 [(set (match_operand:V2DI 0 "register_operand" "=x")
21119 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
21120 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21122 "psllq\t{%2, %0|%0, %2}"
21123 [(set_attr "type" "sseishft")
21124 (set_attr "mode" "TI")])
21126 (define_insn "ashrv8hi3_ti"
21127 [(set (match_operand:V8HI 0 "register_operand" "=x")
21128 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21129 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21131 "psraw\t{%2, %0|%0, %2}"
21132 [(set_attr "type" "sseishft")
21133 (set_attr "mode" "TI")])
21135 (define_insn "ashrv4si3_ti"
21136 [(set (match_operand:V4SI 0 "register_operand" "=x")
21137 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21138 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21140 "psrad\t{%2, %0|%0, %2}"
21141 [(set_attr "type" "sseishft")
21142 (set_attr "mode" "TI")])
21144 (define_insn "lshrv8hi3_ti"
21145 [(set (match_operand:V8HI 0 "register_operand" "=x")
21146 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21147 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21149 "psrlw\t{%2, %0|%0, %2}"
21150 [(set_attr "type" "sseishft")
21151 (set_attr "mode" "TI")])
21153 (define_insn "lshrv4si3_ti"
21154 [(set (match_operand:V4SI 0 "register_operand" "=x")
21155 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21156 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21158 "psrld\t{%2, %0|%0, %2}"
21159 [(set_attr "type" "sseishft")
21160 (set_attr "mode" "TI")])
21162 (define_insn "lshrv2di3_ti"
21163 [(set (match_operand:V2DI 0 "register_operand" "=x")
21164 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
21165 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21167 "psrlq\t{%2, %0|%0, %2}"
21168 [(set_attr "type" "sseishft")
21169 (set_attr "mode" "TI")])
21171 (define_insn "ashlv8hi3_ti"
21172 [(set (match_operand:V8HI 0 "register_operand" "=x")
21173 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
21174 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21176 "psllw\t{%2, %0|%0, %2}"
21177 [(set_attr "type" "sseishft")
21178 (set_attr "mode" "TI")])
21180 (define_insn "ashlv4si3_ti"
21181 [(set (match_operand:V4SI 0 "register_operand" "=x")
21182 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
21183 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21185 "pslld\t{%2, %0|%0, %2}"
21186 [(set_attr "type" "sseishft")
21187 (set_attr "mode" "TI")])
21189 (define_insn "ashlv2di3_ti"
21190 [(set (match_operand:V2DI 0 "register_operand" "=x")
21191 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
21192 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21194 "psllq\t{%2, %0|%0, %2}"
21195 [(set_attr "type" "sseishft")
21196 (set_attr "mode" "TI")])
21198 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
21199 ;; we wouldn't need here it since we never generate TImode arithmetic.
21201 ;; There has to be some kind of prize for the weirdest new instruction...
21202 (define_insn "sse2_ashlti3"
21203 [(set (match_operand:TI 0 "register_operand" "=x")
21205 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
21206 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
21207 (const_int 8)))] UNSPEC_NOP))]
21209 "pslldq\t{%2, %0|%0, %2}"
21210 [(set_attr "type" "sseishft")
21211 (set_attr "mode" "TI")])
21213 (define_insn "sse2_lshrti3"
21214 [(set (match_operand:TI 0 "register_operand" "=x")
21216 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
21217 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
21218 (const_int 8)))] UNSPEC_NOP))]
21220 "pslrdq\t{%2, %0|%0, %2}"
21221 [(set_attr "type" "sseishft")
21222 (set_attr "mode" "TI")])
21226 (define_insn "sse2_unpckhpd"
21227 [(set (match_operand:V2DF 0 "register_operand" "=x")
21229 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0")
21230 (parallel [(const_int 1)]))
21231 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x")
21232 (parallel [(const_int 0)]))))]
21234 "unpckhpd\t{%2, %0|%0, %2}"
21235 [(set_attr "type" "ssecvt")
21236 (set_attr "mode" "TI")])
21238 (define_insn "sse2_unpcklpd"
21239 [(set (match_operand:V2DF 0 "register_operand" "=x")
21241 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0")
21242 (parallel [(const_int 0)]))
21243 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x")
21244 (parallel [(const_int 1)]))))]
21246 "unpcklpd\t{%2, %0|%0, %2}"
21247 [(set_attr "type" "ssecvt")
21248 (set_attr "mode" "TI")])
21250 ;; MMX pack/unpack insns.
21252 (define_insn "sse2_packsswb"
21253 [(set (match_operand:V16QI 0 "register_operand" "=x")
21255 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
21256 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
21258 "packsswb\t{%2, %0|%0, %2}"
21259 [(set_attr "type" "ssecvt")
21260 (set_attr "mode" "TI")])
21262 (define_insn "sse2_packssdw"
21263 [(set (match_operand:V8HI 0 "register_operand" "=x")
21265 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
21266 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
21268 "packssdw\t{%2, %0|%0, %2}"
21269 [(set_attr "type" "ssecvt")
21270 (set_attr "mode" "TI")])
21272 (define_insn "sse2_packuswb"
21273 [(set (match_operand:V16QI 0 "register_operand" "=x")
21275 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
21276 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
21278 "packuswb\t{%2, %0|%0, %2}"
21279 [(set_attr "type" "ssecvt")
21280 (set_attr "mode" "TI")])
21282 (define_insn "sse2_punpckhbw"
21283 [(set (match_operand:V16QI 0 "register_operand" "=x")
21285 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
21286 (parallel [(const_int 8) (const_int 0)
21287 (const_int 9) (const_int 1)
21288 (const_int 10) (const_int 2)
21289 (const_int 11) (const_int 3)
21290 (const_int 12) (const_int 4)
21291 (const_int 13) (const_int 5)
21292 (const_int 14) (const_int 6)
21293 (const_int 15) (const_int 7)]))
21294 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
21295 (parallel [(const_int 0) (const_int 8)
21296 (const_int 1) (const_int 9)
21297 (const_int 2) (const_int 10)
21298 (const_int 3) (const_int 11)
21299 (const_int 4) (const_int 12)
21300 (const_int 5) (const_int 13)
21301 (const_int 6) (const_int 14)
21302 (const_int 7) (const_int 15)]))
21303 (const_int 21845)))]
21305 "punpckhbw\t{%2, %0|%0, %2}"
21306 [(set_attr "type" "ssecvt")
21307 (set_attr "mode" "TI")])
21309 (define_insn "sse2_punpckhwd"
21310 [(set (match_operand:V8HI 0 "register_operand" "=x")
21312 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
21313 (parallel [(const_int 4) (const_int 0)
21314 (const_int 5) (const_int 1)
21315 (const_int 6) (const_int 2)
21316 (const_int 7) (const_int 3)]))
21317 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
21318 (parallel [(const_int 0) (const_int 4)
21319 (const_int 1) (const_int 5)
21320 (const_int 2) (const_int 6)
21321 (const_int 3) (const_int 7)]))
21324 "punpckhwd\t{%2, %0|%0, %2}"
21325 [(set_attr "type" "ssecvt")
21326 (set_attr "mode" "TI")])
21328 (define_insn "sse2_punpckhdq"
21329 [(set (match_operand:V4SI 0 "register_operand" "=x")
21331 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
21332 (parallel [(const_int 2) (const_int 0)
21333 (const_int 3) (const_int 1)]))
21334 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
21335 (parallel [(const_int 0) (const_int 2)
21336 (const_int 1) (const_int 3)]))
21339 "punpckhdq\t{%2, %0|%0, %2}"
21340 [(set_attr "type" "ssecvt")
21341 (set_attr "mode" "TI")])
21343 (define_insn "sse2_punpcklbw"
21344 [(set (match_operand:V16QI 0 "register_operand" "=x")
21346 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
21347 (parallel [(const_int 0) (const_int 8)
21348 (const_int 1) (const_int 9)
21349 (const_int 2) (const_int 10)
21350 (const_int 3) (const_int 11)
21351 (const_int 4) (const_int 12)
21352 (const_int 5) (const_int 13)
21353 (const_int 6) (const_int 14)
21354 (const_int 7) (const_int 15)]))
21355 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
21356 (parallel [(const_int 8) (const_int 0)
21357 (const_int 9) (const_int 1)
21358 (const_int 10) (const_int 2)
21359 (const_int 11) (const_int 3)
21360 (const_int 12) (const_int 4)
21361 (const_int 13) (const_int 5)
21362 (const_int 14) (const_int 6)
21363 (const_int 15) (const_int 7)]))
21364 (const_int 21845)))]
21366 "punpcklbw\t{%2, %0|%0, %2}"
21367 [(set_attr "type" "ssecvt")
21368 (set_attr "mode" "TI")])
21370 (define_insn "sse2_punpcklwd"
21371 [(set (match_operand:V8HI 0 "register_operand" "=x")
21373 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
21374 (parallel [(const_int 0) (const_int 4)
21375 (const_int 1) (const_int 5)
21376 (const_int 2) (const_int 6)
21377 (const_int 3) (const_int 7)]))
21378 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
21379 (parallel [(const_int 4) (const_int 0)
21380 (const_int 5) (const_int 1)
21381 (const_int 6) (const_int 2)
21382 (const_int 7) (const_int 3)]))
21385 "punpcklwd\t{%2, %0|%0, %2}"
21386 [(set_attr "type" "ssecvt")
21387 (set_attr "mode" "TI")])
21389 (define_insn "sse2_punpckldq"
21390 [(set (match_operand:V4SI 0 "register_operand" "=x")
21392 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
21393 (parallel [(const_int 0) (const_int 2)
21394 (const_int 1) (const_int 3)]))
21395 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
21396 (parallel [(const_int 2) (const_int 0)
21397 (const_int 3) (const_int 1)]))
21400 "punpckldq\t{%2, %0|%0, %2}"
21401 [(set_attr "type" "ssecvt")
21402 (set_attr "mode" "TI")])
21406 (define_insn "sse2_movapd"
21407 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21408 (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
21412 movapd\t{%1, %0|%0, %1}
21413 movapd\t{%1, %0|%0, %1}"
21414 [(set_attr "type" "ssemov")
21415 (set_attr "mode" "V2DF")])
21417 (define_insn "sse2_movupd"
21418 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21419 (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
21423 movupd\t{%1, %0|%0, %1}
21424 movupd\t{%1, %0|%0, %1}"
21425 [(set_attr "type" "ssecvt")
21426 (set_attr "mode" "V2DF")])
21428 (define_insn "sse2_movdqa"
21429 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
21430 (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
21434 movdqa\t{%1, %0|%0, %1}
21435 movdqa\t{%1, %0|%0, %1}"
21436 [(set_attr "type" "ssemov")
21437 (set_attr "mode" "TI")])
21439 (define_insn "sse2_movdqu"
21440 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
21441 (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
21445 movdqu\t{%1, %0|%0, %1}
21446 movdqu\t{%1, %0|%0, %1}"
21447 [(set_attr "type" "ssecvt")
21448 (set_attr "mode" "TI")])
21450 (define_insn "sse2_movdq2q"
21451 [(set (match_operand:DI 0 "nonimmediate_operand" "=y")
21452 (vec_select:DI (match_operand:V2DI 1 "general_operand" "x")
21453 (parallel [(const_int 0)])))]
21455 "movdq2q\t{%1, %0|%0, %1}"
21456 [(set_attr "type" "ssecvt")
21457 (set_attr "mode" "TI")])
21459 (define_insn "sse2_movq2dq"
21460 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x")
21461 (vec_concat:V2DI (match_operand:DI 1 "general_operand" "y")
21462 (const_vector:DI [(const_int 0)])))]
21464 "movq2dq\t{%1, %0|%0, %1}"
21465 [(set_attr "type" "ssecvt")
21466 (set_attr "mode" "TI")])
21468 (define_insn "sse2_movhpd"
21469 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21471 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
21472 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
21474 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
21475 "movhpd\t{%2, %0|%0, %2}"
21476 [(set_attr "type" "ssecvt")
21477 (set_attr "mode" "V2DF")])
21479 (define_insn "sse2_movlpd"
21480 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21482 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
21483 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
21485 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
21486 "movlpd\t{%2, %0|%0, %2}"
21487 [(set_attr "type" "ssecvt")
21488 (set_attr "mode" "V2DF")])
21490 (define_insn "sse2_loadsd"
21491 [(set (match_operand:V2DF 0 "register_operand" "=x")
21493 (match_operand:DF 1 "memory_operand" "m")
21494 (vec_duplicate:DF (float:DF (const_int 0)))
21497 "movsd\t{%1, %0|%0, %1}"
21498 [(set_attr "type" "ssecvt")
21499 (set_attr "mode" "DF")])
21501 (define_insn "sse2_movsd"
21502 [(set (match_operand:V2DF 0 "register_operand" "=x")
21504 (match_operand:V2DF 1 "register_operand" "0")
21505 (match_operand:V2DF 2 "register_operand" "x")
21508 "movsd\t{%2, %0|%0, %2}"
21509 [(set_attr "type" "ssecvt")
21510 (set_attr "mode" "DF")])
21512 (define_insn "sse2_storesd"
21513 [(set (match_operand:DF 0 "memory_operand" "=m")
21515 (match_operand:V2DF 1 "register_operand" "x")
21516 (parallel [(const_int 0)])))]
21518 "movsd\t{%1, %0|%0, %1}"
21519 [(set_attr "type" "ssecvt")
21520 (set_attr "mode" "DF")])
21522 (define_insn "sse2_shufpd"
21523 [(set (match_operand:V2DF 0 "register_operand" "=x")
21524 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
21525 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
21526 (match_operand:SI 3 "immediate_operand" "i")]
21529 ;; @@@ check operand order for intel/nonintel syntax
21530 "shufpd\t{%3, %2, %0|%0, %2, %3}"
21531 [(set_attr "type" "ssecvt")
21532 (set_attr "mode" "V2DF")])
21534 (define_insn "sse2_clflush"
21535 [(unspec_volatile [(match_operand:SI 0 "address_operand" "p")]
21539 [(set_attr "type" "sse")
21540 (set_attr "memory" "unknown")])
21542 (define_expand "sse2_mfence"
21543 [(set (match_dup 0)
21544 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
21547 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21548 MEM_VOLATILE_P (operands[0]) = 1;
21551 (define_insn "*mfence_insn"
21552 [(set (match_operand:BLK 0 "" "")
21553 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
21556 [(set_attr "type" "sse")
21557 (set_attr "memory" "unknown")])
21559 (define_expand "sse2_lfence"
21560 [(set (match_dup 0)
21561 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
21564 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21565 MEM_VOLATILE_P (operands[0]) = 1;
21568 (define_insn "*lfence_insn"
21569 [(set (match_operand:BLK 0 "" "")
21570 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
21573 [(set_attr "type" "sse")
21574 (set_attr "memory" "unknown")])