1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; The special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
39 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
40 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
41 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
42 ;; 'J' Print the appropriate jump operand.
44 ;; 'b' Print the QImode name of the register for the indicated operand.
45 ;; %b0 would print %al if operands[0] is reg 0.
46 ;; 'w' Likewise, print the HImode name of the register.
47 ;; 'k' Likewise, print the SImode name of the register.
48 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
49 ;; 'y' Print "st(0)" instead of "st" as a register.
54 [; Relocation specifiers
66 (UNSPEC_STACK_ALLOC 11)
68 (UNSPEC_SSE_PROLOGUE_SAVE 13)
73 (UNSPEC_TLS_LD_BASE 17)
75 ; Other random patterns
85 ; For SSE/MMX support:
87 (UNSPEC_FIX_NOTRUNC 31)
97 (UNSPEC_NOP 45) ; prevents combiner cleverness
124 ; x87 Double output FP
125 (UNSPEC_SINCOS_COS 80)
126 (UNSPEC_SINCOS_SIN 81)
129 (UNSPEC_XTRACT_FRACT 84)
130 (UNSPEC_XTRACT_EXP 85)
131 (UNSPEC_FSCALE_FRACT 86)
132 (UNSPEC_FSCALE_EXP 87)
139 (UNSPEC_FRNDINT_FLOOR 96)
140 (UNSPEC_FRNDINT_CEIL 97)
141 (UNSPEC_FRNDINT_TRUNC 98)
142 (UNSPEC_FRNDINT_MASK_PM 99)
147 (UNSPEC_EH_RETURN 76)
151 [(UNSPECV_BLOCKAGE 0)
152 (UNSPECV_STACK_PROBE 10)
163 ;; Registers by name.
172 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
175 ;; In C guard expressions, put expressions which may be compile-time
176 ;; constants first. This allows for better optimization. For
177 ;; example, write "TARGET_64BIT && reload_completed", not
178 ;; "reload_completed && TARGET_64BIT".
181 ;; Processor type. This attribute must exactly match the processor_type
182 ;; enumeration in i386.h.
183 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona"
184 (const (symbol_ref "ix86_tune")))
186 ;; A basic instruction type. Refinements due to arguments to be
187 ;; provided in other attributes.
190 alu,alu1,negnot,imov,imovx,lea,
191 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
192 icmp,test,ibr,setcc,icmov,
193 push,pop,call,callv,leave,
195 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint,
196 sselog,sselog1,sseiadd,sseishft,sseimul,
197 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
198 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
199 (const_string "other"))
201 ;; Main data type used by the insn
203 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF"
204 (const_string "unknown"))
206 ;; The CPU unit operations uses.
207 (define_attr "unit" "integer,i387,sse,mmx,unknown"
208 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint")
209 (const_string "i387")
210 (eq_attr "type" "sselog,sselog1,sseiadd,sseishft,sseimul,
211 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
213 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
215 (eq_attr "type" "other")
216 (const_string "unknown")]
217 (const_string "integer")))
219 ;; The (bounding maximum) length of an instruction immediate.
220 (define_attr "length_immediate" ""
221 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
223 (eq_attr "unit" "i387,sse,mmx")
225 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
227 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
228 (eq_attr "type" "imov,test")
229 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
230 (eq_attr "type" "call")
231 (if_then_else (match_operand 0 "constant_call_address_operand" "")
234 (eq_attr "type" "callv")
235 (if_then_else (match_operand 1 "constant_call_address_operand" "")
238 ;; We don't know the size before shorten_branches. Expect
239 ;; the instruction to fit for better scheduling.
240 (eq_attr "type" "ibr")
243 (symbol_ref "/* Update immediate_length and other attributes! */
246 ;; The (bounding maximum) length of an instruction address.
247 (define_attr "length_address" ""
248 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
250 (and (eq_attr "type" "call")
251 (match_operand 0 "constant_call_address_operand" ""))
253 (and (eq_attr "type" "callv")
254 (match_operand 1 "constant_call_address_operand" ""))
257 (symbol_ref "ix86_attr_length_address_default (insn)")))
259 ;; Set when length prefix is used.
260 (define_attr "prefix_data16" ""
261 (if_then_else (ior (eq_attr "mode" "HI")
262 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
266 ;; Set when string REP prefix is used.
267 (define_attr "prefix_rep" ""
268 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
272 ;; Set when 0f opcode prefix is used.
273 (define_attr "prefix_0f" ""
275 (ior (eq_attr "type" "imovx,setcc,icmov")
276 (eq_attr "unit" "sse,mmx"))
280 ;; Set when REX opcode prefix is used.
281 (define_attr "prefix_rex" ""
282 (cond [(and (eq_attr "mode" "DI")
283 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
285 (and (eq_attr "mode" "QI")
286 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
289 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
295 ;; Set when modrm byte is used.
296 (define_attr "modrm" ""
297 (cond [(eq_attr "type" "str,cld,leave")
299 (eq_attr "unit" "i387")
301 (and (eq_attr "type" "incdec")
302 (ior (match_operand:SI 1 "register_operand" "")
303 (match_operand:HI 1 "register_operand" "")))
305 (and (eq_attr "type" "push")
306 (not (match_operand 1 "memory_operand" "")))
308 (and (eq_attr "type" "pop")
309 (not (match_operand 0 "memory_operand" "")))
311 (and (eq_attr "type" "imov")
312 (and (match_operand 0 "register_operand" "")
313 (match_operand 1 "immediate_operand" "")))
315 (and (eq_attr "type" "call")
316 (match_operand 0 "constant_call_address_operand" ""))
318 (and (eq_attr "type" "callv")
319 (match_operand 1 "constant_call_address_operand" ""))
324 ;; The (bounding maximum) length of an instruction in bytes.
325 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
326 ;; Later we may want to split them and compute proper length as for
328 (define_attr "length" ""
329 (cond [(eq_attr "type" "other,multi,fistp,frndint")
331 (eq_attr "type" "fcmp")
333 (eq_attr "unit" "i387")
335 (plus (attr "prefix_data16")
336 (attr "length_address")))]
337 (plus (plus (attr "modrm")
338 (plus (attr "prefix_0f")
339 (plus (attr "prefix_rex")
341 (plus (attr "prefix_rep")
342 (plus (attr "prefix_data16")
343 (plus (attr "length_immediate")
344 (attr "length_address")))))))
346 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
347 ;; `store' if there is a simple memory reference therein, or `unknown'
348 ;; if the instruction is complex.
350 (define_attr "memory" "none,load,store,both,unknown"
351 (cond [(eq_attr "type" "other,multi,str")
352 (const_string "unknown")
353 (eq_attr "type" "lea,fcmov,fpspc,cld")
354 (const_string "none")
355 (eq_attr "type" "fistp,leave")
356 (const_string "both")
357 (eq_attr "type" "frndint")
358 (const_string "load")
359 (eq_attr "type" "push")
360 (if_then_else (match_operand 1 "memory_operand" "")
361 (const_string "both")
362 (const_string "store"))
363 (eq_attr "type" "pop")
364 (if_then_else (match_operand 0 "memory_operand" "")
365 (const_string "both")
366 (const_string "load"))
367 (eq_attr "type" "setcc")
368 (if_then_else (match_operand 0 "memory_operand" "")
369 (const_string "store")
370 (const_string "none"))
371 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
372 (if_then_else (ior (match_operand 0 "memory_operand" "")
373 (match_operand 1 "memory_operand" ""))
374 (const_string "load")
375 (const_string "none"))
376 (eq_attr "type" "ibr")
377 (if_then_else (match_operand 0 "memory_operand" "")
378 (const_string "load")
379 (const_string "none"))
380 (eq_attr "type" "call")
381 (if_then_else (match_operand 0 "constant_call_address_operand" "")
382 (const_string "none")
383 (const_string "load"))
384 (eq_attr "type" "callv")
385 (if_then_else (match_operand 1 "constant_call_address_operand" "")
386 (const_string "none")
387 (const_string "load"))
388 (and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
389 (match_operand 1 "memory_operand" ""))
390 (const_string "both")
391 (and (match_operand 0 "memory_operand" "")
392 (match_operand 1 "memory_operand" ""))
393 (const_string "both")
394 (match_operand 0 "memory_operand" "")
395 (const_string "store")
396 (match_operand 1 "memory_operand" "")
397 (const_string "load")
399 "!alu1,negnot,ishift1,
400 imov,imovx,icmp,test,
402 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,sselog1,
403 mmx,mmxmov,mmxcmp,mmxcvt")
404 (match_operand 2 "memory_operand" ""))
405 (const_string "load")
406 (and (eq_attr "type" "icmov")
407 (match_operand 3 "memory_operand" ""))
408 (const_string "load")
410 (const_string "none")))
412 ;; Indicates if an instruction has both an immediate and a displacement.
414 (define_attr "imm_disp" "false,true,unknown"
415 (cond [(eq_attr "type" "other,multi")
416 (const_string "unknown")
417 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
418 (and (match_operand 0 "memory_displacement_operand" "")
419 (match_operand 1 "immediate_operand" "")))
420 (const_string "true")
421 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
422 (and (match_operand 0 "memory_displacement_operand" "")
423 (match_operand 2 "immediate_operand" "")))
424 (const_string "true")
426 (const_string "false")))
428 ;; Indicates if an FP operation has an integer source.
430 (define_attr "fp_int_src" "false,true"
431 (const_string "false"))
433 ;; Defines rounding mode of an FP operation.
435 (define_attr "i387_cw" "floor,ceil,trunc,mask_pm,uninitialized,any"
436 (const_string "any"))
438 ;; Describe a user's asm statement.
439 (define_asm_attributes
440 [(set_attr "length" "128")
441 (set_attr "type" "multi")])
443 ;; Scheduling descriptions
445 (include "pentium.md")
448 (include "athlon.md")
451 ;; Operand and operator predicates
453 (include "predicates.md")
456 ;; Compare instructions.
458 ;; All compare insns have expanders that save the operands away without
459 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
460 ;; after the cmp) will actually emit the cmpM.
462 (define_expand "cmpdi"
463 [(set (reg:CC FLAGS_REG)
464 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
465 (match_operand:DI 1 "x86_64_general_operand" "")))]
468 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
469 operands[0] = force_reg (DImode, operands[0]);
470 ix86_compare_op0 = operands[0];
471 ix86_compare_op1 = operands[1];
475 (define_expand "cmpsi"
476 [(set (reg:CC FLAGS_REG)
477 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
478 (match_operand:SI 1 "general_operand" "")))]
481 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
482 operands[0] = force_reg (SImode, operands[0]);
483 ix86_compare_op0 = operands[0];
484 ix86_compare_op1 = operands[1];
488 (define_expand "cmphi"
489 [(set (reg:CC FLAGS_REG)
490 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
491 (match_operand:HI 1 "general_operand" "")))]
494 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
495 operands[0] = force_reg (HImode, operands[0]);
496 ix86_compare_op0 = operands[0];
497 ix86_compare_op1 = operands[1];
501 (define_expand "cmpqi"
502 [(set (reg:CC FLAGS_REG)
503 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
504 (match_operand:QI 1 "general_operand" "")))]
507 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
508 operands[0] = force_reg (QImode, operands[0]);
509 ix86_compare_op0 = operands[0];
510 ix86_compare_op1 = operands[1];
514 (define_insn "cmpdi_ccno_1_rex64"
515 [(set (reg FLAGS_REG)
516 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
517 (match_operand:DI 1 "const0_operand" "n,n")))]
518 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
520 test{q}\t{%0, %0|%0, %0}
521 cmp{q}\t{%1, %0|%0, %1}"
522 [(set_attr "type" "test,icmp")
523 (set_attr "length_immediate" "0,1")
524 (set_attr "mode" "DI")])
526 (define_insn "*cmpdi_minus_1_rex64"
527 [(set (reg FLAGS_REG)
528 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
529 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
531 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
532 "cmp{q}\t{%1, %0|%0, %1}"
533 [(set_attr "type" "icmp")
534 (set_attr "mode" "DI")])
536 (define_expand "cmpdi_1_rex64"
537 [(set (reg:CC FLAGS_REG)
538 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
539 (match_operand:DI 1 "general_operand" "")))]
543 (define_insn "cmpdi_1_insn_rex64"
544 [(set (reg FLAGS_REG)
545 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
546 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
547 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
548 "cmp{q}\t{%1, %0|%0, %1}"
549 [(set_attr "type" "icmp")
550 (set_attr "mode" "DI")])
553 (define_insn "*cmpsi_ccno_1"
554 [(set (reg FLAGS_REG)
555 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
556 (match_operand:SI 1 "const0_operand" "n,n")))]
557 "ix86_match_ccmode (insn, CCNOmode)"
559 test{l}\t{%0, %0|%0, %0}
560 cmp{l}\t{%1, %0|%0, %1}"
561 [(set_attr "type" "test,icmp")
562 (set_attr "length_immediate" "0,1")
563 (set_attr "mode" "SI")])
565 (define_insn "*cmpsi_minus_1"
566 [(set (reg FLAGS_REG)
567 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
568 (match_operand:SI 1 "general_operand" "ri,mr"))
570 "ix86_match_ccmode (insn, CCGOCmode)"
571 "cmp{l}\t{%1, %0|%0, %1}"
572 [(set_attr "type" "icmp")
573 (set_attr "mode" "SI")])
575 (define_expand "cmpsi_1"
576 [(set (reg:CC FLAGS_REG)
577 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
578 (match_operand:SI 1 "general_operand" "ri,mr")))]
582 (define_insn "*cmpsi_1_insn"
583 [(set (reg FLAGS_REG)
584 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
585 (match_operand:SI 1 "general_operand" "ri,mr")))]
586 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
587 && ix86_match_ccmode (insn, CCmode)"
588 "cmp{l}\t{%1, %0|%0, %1}"
589 [(set_attr "type" "icmp")
590 (set_attr "mode" "SI")])
592 (define_insn "*cmphi_ccno_1"
593 [(set (reg FLAGS_REG)
594 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
595 (match_operand:HI 1 "const0_operand" "n,n")))]
596 "ix86_match_ccmode (insn, CCNOmode)"
598 test{w}\t{%0, %0|%0, %0}
599 cmp{w}\t{%1, %0|%0, %1}"
600 [(set_attr "type" "test,icmp")
601 (set_attr "length_immediate" "0,1")
602 (set_attr "mode" "HI")])
604 (define_insn "*cmphi_minus_1"
605 [(set (reg FLAGS_REG)
606 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
607 (match_operand:HI 1 "general_operand" "ri,mr"))
609 "ix86_match_ccmode (insn, CCGOCmode)"
610 "cmp{w}\t{%1, %0|%0, %1}"
611 [(set_attr "type" "icmp")
612 (set_attr "mode" "HI")])
614 (define_insn "*cmphi_1"
615 [(set (reg FLAGS_REG)
616 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
617 (match_operand:HI 1 "general_operand" "ri,mr")))]
618 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
619 && ix86_match_ccmode (insn, CCmode)"
620 "cmp{w}\t{%1, %0|%0, %1}"
621 [(set_attr "type" "icmp")
622 (set_attr "mode" "HI")])
624 (define_insn "*cmpqi_ccno_1"
625 [(set (reg FLAGS_REG)
626 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
627 (match_operand:QI 1 "const0_operand" "n,n")))]
628 "ix86_match_ccmode (insn, CCNOmode)"
630 test{b}\t{%0, %0|%0, %0}
631 cmp{b}\t{$0, %0|%0, 0}"
632 [(set_attr "type" "test,icmp")
633 (set_attr "length_immediate" "0,1")
634 (set_attr "mode" "QI")])
636 (define_insn "*cmpqi_1"
637 [(set (reg FLAGS_REG)
638 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
639 (match_operand:QI 1 "general_operand" "qi,mq")))]
640 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
641 && ix86_match_ccmode (insn, CCmode)"
642 "cmp{b}\t{%1, %0|%0, %1}"
643 [(set_attr "type" "icmp")
644 (set_attr "mode" "QI")])
646 (define_insn "*cmpqi_minus_1"
647 [(set (reg FLAGS_REG)
648 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
649 (match_operand:QI 1 "general_operand" "qi,mq"))
651 "ix86_match_ccmode (insn, CCGOCmode)"
652 "cmp{b}\t{%1, %0|%0, %1}"
653 [(set_attr "type" "icmp")
654 (set_attr "mode" "QI")])
656 (define_insn "*cmpqi_ext_1"
657 [(set (reg FLAGS_REG)
659 (match_operand:QI 0 "general_operand" "Qm")
662 (match_operand 1 "ext_register_operand" "Q")
665 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
666 "cmp{b}\t{%h1, %0|%0, %h1}"
667 [(set_attr "type" "icmp")
668 (set_attr "mode" "QI")])
670 (define_insn "*cmpqi_ext_1_rex64"
671 [(set (reg FLAGS_REG)
673 (match_operand:QI 0 "register_operand" "Q")
676 (match_operand 1 "ext_register_operand" "Q")
679 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
680 "cmp{b}\t{%h1, %0|%0, %h1}"
681 [(set_attr "type" "icmp")
682 (set_attr "mode" "QI")])
684 (define_insn "*cmpqi_ext_2"
685 [(set (reg FLAGS_REG)
689 (match_operand 0 "ext_register_operand" "Q")
692 (match_operand:QI 1 "const0_operand" "n")))]
693 "ix86_match_ccmode (insn, CCNOmode)"
695 [(set_attr "type" "test")
696 (set_attr "length_immediate" "0")
697 (set_attr "mode" "QI")])
699 (define_expand "cmpqi_ext_3"
700 [(set (reg:CC FLAGS_REG)
704 (match_operand 0 "ext_register_operand" "")
707 (match_operand:QI 1 "general_operand" "")))]
711 (define_insn "cmpqi_ext_3_insn"
712 [(set (reg FLAGS_REG)
716 (match_operand 0 "ext_register_operand" "Q")
719 (match_operand:QI 1 "general_operand" "Qmn")))]
720 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
721 "cmp{b}\t{%1, %h0|%h0, %1}"
722 [(set_attr "type" "icmp")
723 (set_attr "mode" "QI")])
725 (define_insn "cmpqi_ext_3_insn_rex64"
726 [(set (reg FLAGS_REG)
730 (match_operand 0 "ext_register_operand" "Q")
733 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
734 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
735 "cmp{b}\t{%1, %h0|%h0, %1}"
736 [(set_attr "type" "icmp")
737 (set_attr "mode" "QI")])
739 (define_insn "*cmpqi_ext_4"
740 [(set (reg FLAGS_REG)
744 (match_operand 0 "ext_register_operand" "Q")
749 (match_operand 1 "ext_register_operand" "Q")
752 "ix86_match_ccmode (insn, CCmode)"
753 "cmp{b}\t{%h1, %h0|%h0, %h1}"
754 [(set_attr "type" "icmp")
755 (set_attr "mode" "QI")])
757 ;; These implement float point compares.
758 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
759 ;; which would allow mix and match FP modes on the compares. Which is what
760 ;; the old patterns did, but with many more of them.
762 (define_expand "cmpxf"
763 [(set (reg:CC FLAGS_REG)
764 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
765 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
768 ix86_compare_op0 = operands[0];
769 ix86_compare_op1 = operands[1];
773 (define_expand "cmpdf"
774 [(set (reg:CC FLAGS_REG)
775 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
776 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
777 "TARGET_80387 || TARGET_SSE2"
779 ix86_compare_op0 = operands[0];
780 ix86_compare_op1 = operands[1];
784 (define_expand "cmpsf"
785 [(set (reg:CC FLAGS_REG)
786 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
787 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
788 "TARGET_80387 || TARGET_SSE"
790 ix86_compare_op0 = operands[0];
791 ix86_compare_op1 = operands[1];
795 ;; FP compares, step 1:
796 ;; Set the FP condition codes.
798 ;; CCFPmode compare with exceptions
799 ;; CCFPUmode compare with no exceptions
801 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
802 ;; used to manage the reg stack popping would not be preserved.
804 (define_insn "*cmpfp_0_sf"
805 [(set (match_operand:HI 0 "register_operand" "=a")
808 (match_operand:SF 1 "register_operand" "f")
809 (match_operand:SF 2 "const0_operand" "X"))]
812 "* return output_fp_compare (insn, operands, 0, 0);"
813 [(set_attr "type" "multi")
814 (set_attr "mode" "SF")])
816 (define_insn "*cmpfp_0_df"
817 [(set (match_operand:HI 0 "register_operand" "=a")
820 (match_operand:DF 1 "register_operand" "f")
821 (match_operand:DF 2 "const0_operand" "X"))]
824 "* return output_fp_compare (insn, operands, 0, 0);"
825 [(set_attr "type" "multi")
826 (set_attr "mode" "DF")])
828 (define_insn "*cmpfp_0_xf"
829 [(set (match_operand:HI 0 "register_operand" "=a")
832 (match_operand:XF 1 "register_operand" "f")
833 (match_operand:XF 2 "const0_operand" "X"))]
836 "* return output_fp_compare (insn, operands, 0, 0);"
837 [(set_attr "type" "multi")
838 (set_attr "mode" "XF")])
840 (define_insn "*cmpfp_sf"
841 [(set (match_operand:HI 0 "register_operand" "=a")
844 (match_operand:SF 1 "register_operand" "f")
845 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
848 "* return output_fp_compare (insn, operands, 0, 0);"
849 [(set_attr "type" "multi")
850 (set_attr "mode" "SF")])
852 (define_insn "*cmpfp_df"
853 [(set (match_operand:HI 0 "register_operand" "=a")
856 (match_operand:DF 1 "register_operand" "f")
857 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
860 "* return output_fp_compare (insn, operands, 0, 0);"
861 [(set_attr "type" "multi")
862 (set_attr "mode" "DF")])
864 (define_insn "*cmpfp_xf"
865 [(set (match_operand:HI 0 "register_operand" "=a")
868 (match_operand:XF 1 "register_operand" "f")
869 (match_operand:XF 2 "register_operand" "f"))]
872 "* return output_fp_compare (insn, operands, 0, 0);"
873 [(set_attr "type" "multi")
874 (set_attr "mode" "XF")])
876 (define_insn "*cmpfp_u"
877 [(set (match_operand:HI 0 "register_operand" "=a")
880 (match_operand 1 "register_operand" "f")
881 (match_operand 2 "register_operand" "f"))]
884 && FLOAT_MODE_P (GET_MODE (operands[1]))
885 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
886 "* return output_fp_compare (insn, operands, 0, 1);"
887 [(set_attr "type" "multi")
889 (cond [(match_operand:SF 1 "" "")
891 (match_operand:DF 1 "" "")
894 (const_string "XF")))])
896 (define_insn "*cmpfp_si"
897 [(set (match_operand:HI 0 "register_operand" "=a")
900 (match_operand 1 "register_operand" "f")
901 (match_operator 3 "float_operator"
902 [(match_operand:SI 2 "memory_operand" "m")]))]
904 "TARGET_80387 && TARGET_USE_FIOP
905 && FLOAT_MODE_P (GET_MODE (operands[1]))
906 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
907 "* return output_fp_compare (insn, operands, 0, 0);"
908 [(set_attr "type" "multi")
909 (set_attr "fp_int_src" "true")
910 (set_attr "mode" "SI")])
912 ;; FP compares, step 2
913 ;; Move the fpsw to ax.
915 (define_insn "x86_fnstsw_1"
916 [(set (match_operand:HI 0 "register_operand" "=a")
917 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
920 [(set_attr "length" "2")
921 (set_attr "mode" "SI")
922 (set_attr "unit" "i387")])
924 ;; FP compares, step 3
925 ;; Get ax into flags, general case.
927 (define_insn "x86_sahf_1"
928 [(set (reg:CC FLAGS_REG)
929 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
932 [(set_attr "length" "1")
933 (set_attr "athlon_decode" "vector")
934 (set_attr "mode" "SI")])
936 ;; Pentium Pro can do steps 1 through 3 in one go.
938 (define_insn "*cmpfp_i"
939 [(set (reg:CCFP FLAGS_REG)
940 (compare:CCFP (match_operand 0 "register_operand" "f")
941 (match_operand 1 "register_operand" "f")))]
942 "TARGET_80387 && TARGET_CMOVE
943 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
944 && FLOAT_MODE_P (GET_MODE (operands[0]))
945 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
946 "* return output_fp_compare (insn, operands, 1, 0);"
947 [(set_attr "type" "fcmp")
949 (cond [(match_operand:SF 1 "" "")
951 (match_operand:DF 1 "" "")
954 (const_string "XF")))
955 (set_attr "athlon_decode" "vector")])
957 (define_insn "*cmpfp_i_sse"
958 [(set (reg:CCFP FLAGS_REG)
959 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
960 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
962 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
963 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
964 "* return output_fp_compare (insn, operands, 1, 0);"
965 [(set_attr "type" "fcmp,ssecomi")
967 (if_then_else (match_operand:SF 1 "" "")
969 (const_string "DF")))
970 (set_attr "athlon_decode" "vector")])
972 (define_insn "*cmpfp_i_sse_only"
973 [(set (reg:CCFP FLAGS_REG)
974 (compare:CCFP (match_operand 0 "register_operand" "x")
975 (match_operand 1 "nonimmediate_operand" "xm")))]
976 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
977 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
978 "* return output_fp_compare (insn, operands, 1, 0);"
979 [(set_attr "type" "ssecomi")
981 (if_then_else (match_operand:SF 1 "" "")
983 (const_string "DF")))
984 (set_attr "athlon_decode" "vector")])
986 (define_insn "*cmpfp_iu"
987 [(set (reg:CCFPU FLAGS_REG)
988 (compare:CCFPU (match_operand 0 "register_operand" "f")
989 (match_operand 1 "register_operand" "f")))]
990 "TARGET_80387 && TARGET_CMOVE
991 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
992 && FLOAT_MODE_P (GET_MODE (operands[0]))
993 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
994 "* return output_fp_compare (insn, operands, 1, 1);"
995 [(set_attr "type" "fcmp")
997 (cond [(match_operand:SF 1 "" "")
999 (match_operand:DF 1 "" "")
1002 (const_string "XF")))
1003 (set_attr "athlon_decode" "vector")])
1005 (define_insn "*cmpfp_iu_sse"
1006 [(set (reg:CCFPU FLAGS_REG)
1007 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1008 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1010 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1011 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1012 "* return output_fp_compare (insn, operands, 1, 1);"
1013 [(set_attr "type" "fcmp,ssecomi")
1015 (if_then_else (match_operand:SF 1 "" "")
1017 (const_string "DF")))
1018 (set_attr "athlon_decode" "vector")])
1020 (define_insn "*cmpfp_iu_sse_only"
1021 [(set (reg:CCFPU FLAGS_REG)
1022 (compare:CCFPU (match_operand 0 "register_operand" "x")
1023 (match_operand 1 "nonimmediate_operand" "xm")))]
1024 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1025 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1026 "* return output_fp_compare (insn, operands, 1, 1);"
1027 [(set_attr "type" "ssecomi")
1029 (if_then_else (match_operand:SF 1 "" "")
1031 (const_string "DF")))
1032 (set_attr "athlon_decode" "vector")])
1034 ;; Move instructions.
1036 ;; General case of fullword move.
1038 (define_expand "movsi"
1039 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1040 (match_operand:SI 1 "general_operand" ""))]
1042 "ix86_expand_move (SImode, operands); DONE;")
1044 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1047 ;; %%% We don't use a post-inc memory reference because x86 is not a
1048 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1049 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1050 ;; targets without our curiosities, and it is just as easy to represent
1051 ;; this differently.
1053 (define_insn "*pushsi2"
1054 [(set (match_operand:SI 0 "push_operand" "=<")
1055 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1058 [(set_attr "type" "push")
1059 (set_attr "mode" "SI")])
1061 ;; For 64BIT abi we always round up to 8 bytes.
1062 (define_insn "*pushsi2_rex64"
1063 [(set (match_operand:SI 0 "push_operand" "=X")
1064 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1067 [(set_attr "type" "push")
1068 (set_attr "mode" "SI")])
1070 (define_insn "*pushsi2_prologue"
1071 [(set (match_operand:SI 0 "push_operand" "=<")
1072 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1073 (clobber (mem:BLK (scratch)))]
1076 [(set_attr "type" "push")
1077 (set_attr "mode" "SI")])
1079 (define_insn "*popsi1_epilogue"
1080 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1081 (mem:SI (reg:SI SP_REG)))
1082 (set (reg:SI SP_REG)
1083 (plus:SI (reg:SI SP_REG) (const_int 4)))
1084 (clobber (mem:BLK (scratch)))]
1087 [(set_attr "type" "pop")
1088 (set_attr "mode" "SI")])
1090 (define_insn "popsi1"
1091 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1092 (mem:SI (reg:SI SP_REG)))
1093 (set (reg:SI SP_REG)
1094 (plus:SI (reg:SI SP_REG) (const_int 4)))]
1097 [(set_attr "type" "pop")
1098 (set_attr "mode" "SI")])
1100 (define_insn "*movsi_xor"
1101 [(set (match_operand:SI 0 "register_operand" "=r")
1102 (match_operand:SI 1 "const0_operand" "i"))
1103 (clobber (reg:CC FLAGS_REG))]
1104 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1105 "xor{l}\t{%0, %0|%0, %0}"
1106 [(set_attr "type" "alu1")
1107 (set_attr "mode" "SI")
1108 (set_attr "length_immediate" "0")])
1110 (define_insn "*movsi_or"
1111 [(set (match_operand:SI 0 "register_operand" "=r")
1112 (match_operand:SI 1 "immediate_operand" "i"))
1113 (clobber (reg:CC FLAGS_REG))]
1115 && operands[1] == constm1_rtx
1116 && (TARGET_PENTIUM || optimize_size)"
1118 operands[1] = constm1_rtx;
1119 return "or{l}\t{%1, %0|%0, %1}";
1121 [(set_attr "type" "alu1")
1122 (set_attr "mode" "SI")
1123 (set_attr "length_immediate" "1")])
1125 (define_insn "*movsi_1"
1126 [(set (match_operand:SI 0 "nonimmediate_operand"
1127 "=r ,m ,!*y,!rm,!*y,!*x,!rm,!*x")
1128 (match_operand:SI 1 "general_operand"
1129 "rinm,rin,*y ,*y ,rm ,*x ,*x ,rm"))]
1130 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1131 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1133 switch (get_attr_type (insn))
1136 if (get_attr_mode (insn) == MODE_TI)
1137 return "movdqa\t{%1, %0|%0, %1}";
1138 return "movd\t{%1, %0|%0, %1}";
1141 if (get_attr_mode (insn) == MODE_DI)
1142 return "movq\t{%1, %0|%0, %1}";
1143 return "movd\t{%1, %0|%0, %1}";
1146 return "lea{l}\t{%1, %0|%0, %1}";
1149 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1151 return "mov{l}\t{%1, %0|%0, %1}";
1155 (cond [(eq_attr "alternative" "2,3,4")
1156 (const_string "mmxmov")
1157 (eq_attr "alternative" "5,6,7")
1158 (const_string "ssemov")
1159 (and (ne (symbol_ref "flag_pic") (const_int 0))
1160 (match_operand:SI 1 "symbolic_operand" ""))
1161 (const_string "lea")
1163 (const_string "imov")))
1164 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1166 (define_insn "*movsi_1_nointernunit"
1167 [(set (match_operand:SI 0 "nonimmediate_operand"
1168 "=r ,m ,!*y,!m,!*y,!*x,!m,!*x")
1169 (match_operand:SI 1 "general_operand"
1170 "rinm,rin,*y ,*y,m ,*x ,*x,m"))]
1171 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1172 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1174 switch (get_attr_type (insn))
1177 if (get_attr_mode (insn) == MODE_TI)
1178 return "movdqa\t{%1, %0|%0, %1}";
1179 return "movd\t{%1, %0|%0, %1}";
1182 if (get_attr_mode (insn) == MODE_DI)
1183 return "movq\t{%1, %0|%0, %1}";
1184 return "movd\t{%1, %0|%0, %1}";
1187 return "lea{l}\t{%1, %0|%0, %1}";
1190 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1192 return "mov{l}\t{%1, %0|%0, %1}";
1196 (cond [(eq_attr "alternative" "2,3,4")
1197 (const_string "mmxmov")
1198 (eq_attr "alternative" "5,6,7")
1199 (const_string "ssemov")
1200 (and (ne (symbol_ref "flag_pic") (const_int 0))
1201 (match_operand:SI 1 "symbolic_operand" ""))
1202 (const_string "lea")
1204 (const_string "imov")))
1205 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1207 ;; Stores and loads of ax to arbitrary constant address.
1208 ;; We fake an second form of instruction to force reload to load address
1209 ;; into register when rax is not available
1210 (define_insn "*movabssi_1_rex64"
1211 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1212 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1213 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1215 movabs{l}\t{%1, %P0|%P0, %1}
1216 mov{l}\t{%1, %a0|%a0, %1}"
1217 [(set_attr "type" "imov")
1218 (set_attr "modrm" "0,*")
1219 (set_attr "length_address" "8,0")
1220 (set_attr "length_immediate" "0,*")
1221 (set_attr "memory" "store")
1222 (set_attr "mode" "SI")])
1224 (define_insn "*movabssi_2_rex64"
1225 [(set (match_operand:SI 0 "register_operand" "=a,r")
1226 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1227 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1229 movabs{l}\t{%P1, %0|%0, %P1}
1230 mov{l}\t{%a1, %0|%0, %a1}"
1231 [(set_attr "type" "imov")
1232 (set_attr "modrm" "0,*")
1233 (set_attr "length_address" "8,0")
1234 (set_attr "length_immediate" "0")
1235 (set_attr "memory" "load")
1236 (set_attr "mode" "SI")])
1238 (define_insn "*swapsi"
1239 [(set (match_operand:SI 0 "register_operand" "+r")
1240 (match_operand:SI 1 "register_operand" "+r"))
1245 [(set_attr "type" "imov")
1246 (set_attr "mode" "SI")
1247 (set_attr "pent_pair" "np")
1248 (set_attr "athlon_decode" "vector")])
1250 (define_expand "movhi"
1251 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1252 (match_operand:HI 1 "general_operand" ""))]
1254 "ix86_expand_move (HImode, operands); DONE;")
1256 (define_insn "*pushhi2"
1257 [(set (match_operand:HI 0 "push_operand" "=<,<")
1258 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1261 push{w}\t{|WORD PTR }%1
1263 [(set_attr "type" "push")
1264 (set_attr "mode" "HI")])
1266 ;; For 64BIT abi we always round up to 8 bytes.
1267 (define_insn "*pushhi2_rex64"
1268 [(set (match_operand:HI 0 "push_operand" "=X")
1269 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1272 [(set_attr "type" "push")
1273 (set_attr "mode" "QI")])
1275 (define_insn "*movhi_1"
1276 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1277 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1278 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1280 switch (get_attr_type (insn))
1283 /* movzwl is faster than movw on p2 due to partial word stalls,
1284 though not as fast as an aligned movl. */
1285 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1287 if (get_attr_mode (insn) == MODE_SI)
1288 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1290 return "mov{w}\t{%1, %0|%0, %1}";
1294 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1295 (const_string "imov")
1296 (and (eq_attr "alternative" "0")
1297 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1299 (eq (symbol_ref "TARGET_HIMODE_MATH")
1301 (const_string "imov")
1302 (and (eq_attr "alternative" "1,2")
1303 (match_operand:HI 1 "aligned_operand" ""))
1304 (const_string "imov")
1305 (and (ne (symbol_ref "TARGET_MOVX")
1307 (eq_attr "alternative" "0,2"))
1308 (const_string "imovx")
1310 (const_string "imov")))
1312 (cond [(eq_attr "type" "imovx")
1314 (and (eq_attr "alternative" "1,2")
1315 (match_operand:HI 1 "aligned_operand" ""))
1317 (and (eq_attr "alternative" "0")
1318 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1320 (eq (symbol_ref "TARGET_HIMODE_MATH")
1324 (const_string "HI")))])
1326 ;; Stores and loads of ax to arbitrary constant address.
1327 ;; We fake an second form of instruction to force reload to load address
1328 ;; into register when rax is not available
1329 (define_insn "*movabshi_1_rex64"
1330 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1331 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1332 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1334 movabs{w}\t{%1, %P0|%P0, %1}
1335 mov{w}\t{%1, %a0|%a0, %1}"
1336 [(set_attr "type" "imov")
1337 (set_attr "modrm" "0,*")
1338 (set_attr "length_address" "8,0")
1339 (set_attr "length_immediate" "0,*")
1340 (set_attr "memory" "store")
1341 (set_attr "mode" "HI")])
1343 (define_insn "*movabshi_2_rex64"
1344 [(set (match_operand:HI 0 "register_operand" "=a,r")
1345 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1346 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1348 movabs{w}\t{%P1, %0|%0, %P1}
1349 mov{w}\t{%a1, %0|%0, %a1}"
1350 [(set_attr "type" "imov")
1351 (set_attr "modrm" "0,*")
1352 (set_attr "length_address" "8,0")
1353 (set_attr "length_immediate" "0")
1354 (set_attr "memory" "load")
1355 (set_attr "mode" "HI")])
1357 (define_insn "*swaphi_1"
1358 [(set (match_operand:HI 0 "register_operand" "+r")
1359 (match_operand:HI 1 "register_operand" "+r"))
1362 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1364 [(set_attr "type" "imov")
1365 (set_attr "mode" "SI")
1366 (set_attr "pent_pair" "np")
1367 (set_attr "athlon_decode" "vector")])
1369 (define_insn "*swaphi_2"
1370 [(set (match_operand:HI 0 "register_operand" "+r")
1371 (match_operand:HI 1 "register_operand" "+r"))
1374 "TARGET_PARTIAL_REG_STALL"
1376 [(set_attr "type" "imov")
1377 (set_attr "mode" "HI")
1378 (set_attr "pent_pair" "np")
1379 (set_attr "athlon_decode" "vector")])
1381 (define_expand "movstricthi"
1382 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1383 (match_operand:HI 1 "general_operand" ""))]
1384 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1386 /* Don't generate memory->memory moves, go through a register */
1387 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1388 operands[1] = force_reg (HImode, operands[1]);
1391 (define_insn "*movstricthi_1"
1392 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1393 (match_operand:HI 1 "general_operand" "rn,m"))]
1394 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1395 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1396 "mov{w}\t{%1, %0|%0, %1}"
1397 [(set_attr "type" "imov")
1398 (set_attr "mode" "HI")])
1400 (define_insn "*movstricthi_xor"
1401 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1402 (match_operand:HI 1 "const0_operand" "i"))
1403 (clobber (reg:CC FLAGS_REG))]
1405 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1406 "xor{w}\t{%0, %0|%0, %0}"
1407 [(set_attr "type" "alu1")
1408 (set_attr "mode" "HI")
1409 (set_attr "length_immediate" "0")])
1411 (define_expand "movqi"
1412 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1413 (match_operand:QI 1 "general_operand" ""))]
1415 "ix86_expand_move (QImode, operands); DONE;")
1417 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1418 ;; "push a byte". But actually we use pushw, which has the effect
1419 ;; of rounding the amount pushed up to a halfword.
1421 (define_insn "*pushqi2"
1422 [(set (match_operand:QI 0 "push_operand" "=X,X")
1423 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1426 push{w}\t{|word ptr }%1
1428 [(set_attr "type" "push")
1429 (set_attr "mode" "HI")])
1431 ;; For 64BIT abi we always round up to 8 bytes.
1432 (define_insn "*pushqi2_rex64"
1433 [(set (match_operand:QI 0 "push_operand" "=X")
1434 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1437 [(set_attr "type" "push")
1438 (set_attr "mode" "QI")])
1440 ;; Situation is quite tricky about when to choose full sized (SImode) move
1441 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1442 ;; partial register dependency machines (such as AMD Athlon), where QImode
1443 ;; moves issue extra dependency and for partial register stalls machines
1444 ;; that don't use QImode patterns (and QImode move cause stall on the next
1447 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1448 ;; register stall machines with, where we use QImode instructions, since
1449 ;; partial register stall can be caused there. Then we use movzx.
1450 (define_insn "*movqi_1"
1451 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1452 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1453 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1455 switch (get_attr_type (insn))
1458 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1460 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1462 if (get_attr_mode (insn) == MODE_SI)
1463 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1465 return "mov{b}\t{%1, %0|%0, %1}";
1469 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1470 (const_string "imov")
1471 (and (eq_attr "alternative" "3")
1472 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1474 (eq (symbol_ref "TARGET_QIMODE_MATH")
1476 (const_string "imov")
1477 (eq_attr "alternative" "3,5")
1478 (const_string "imovx")
1479 (and (ne (symbol_ref "TARGET_MOVX")
1481 (eq_attr "alternative" "2"))
1482 (const_string "imovx")
1484 (const_string "imov")))
1486 (cond [(eq_attr "alternative" "3,4,5")
1488 (eq_attr "alternative" "6")
1490 (eq_attr "type" "imovx")
1492 (and (eq_attr "type" "imov")
1493 (and (eq_attr "alternative" "0,1")
1494 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1497 ;; Avoid partial register stalls when not using QImode arithmetic
1498 (and (eq_attr "type" "imov")
1499 (and (eq_attr "alternative" "0,1")
1500 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1502 (eq (symbol_ref "TARGET_QIMODE_MATH")
1506 (const_string "QI")))])
1508 (define_expand "reload_outqi"
1509 [(parallel [(match_operand:QI 0 "" "=m")
1510 (match_operand:QI 1 "register_operand" "r")
1511 (match_operand:QI 2 "register_operand" "=&q")])]
1515 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1517 if (reg_overlap_mentioned_p (op2, op0))
1519 if (! q_regs_operand (op1, QImode))
1521 emit_insn (gen_movqi (op2, op1));
1524 emit_insn (gen_movqi (op0, op1));
1528 (define_insn "*swapqi_1"
1529 [(set (match_operand:QI 0 "register_operand" "+r")
1530 (match_operand:QI 1 "register_operand" "+r"))
1533 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1535 [(set_attr "type" "imov")
1536 (set_attr "mode" "SI")
1537 (set_attr "pent_pair" "np")
1538 (set_attr "athlon_decode" "vector")])
1540 (define_insn "*swapqi_2"
1541 [(set (match_operand:QI 0 "register_operand" "+q")
1542 (match_operand:QI 1 "register_operand" "+q"))
1545 "TARGET_PARTIAL_REG_STALL"
1547 [(set_attr "type" "imov")
1548 (set_attr "mode" "QI")
1549 (set_attr "pent_pair" "np")
1550 (set_attr "athlon_decode" "vector")])
1552 (define_expand "movstrictqi"
1553 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1554 (match_operand:QI 1 "general_operand" ""))]
1555 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1557 /* Don't generate memory->memory moves, go through a register. */
1558 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1559 operands[1] = force_reg (QImode, operands[1]);
1562 (define_insn "*movstrictqi_1"
1563 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1564 (match_operand:QI 1 "general_operand" "*qn,m"))]
1565 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1566 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1567 "mov{b}\t{%1, %0|%0, %1}"
1568 [(set_attr "type" "imov")
1569 (set_attr "mode" "QI")])
1571 (define_insn "*movstrictqi_xor"
1572 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1573 (match_operand:QI 1 "const0_operand" "i"))
1574 (clobber (reg:CC FLAGS_REG))]
1575 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1576 "xor{b}\t{%0, %0|%0, %0}"
1577 [(set_attr "type" "alu1")
1578 (set_attr "mode" "QI")
1579 (set_attr "length_immediate" "0")])
1581 (define_insn "*movsi_extv_1"
1582 [(set (match_operand:SI 0 "register_operand" "=R")
1583 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1587 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1588 [(set_attr "type" "imovx")
1589 (set_attr "mode" "SI")])
1591 (define_insn "*movhi_extv_1"
1592 [(set (match_operand:HI 0 "register_operand" "=R")
1593 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1597 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1598 [(set_attr "type" "imovx")
1599 (set_attr "mode" "SI")])
1601 (define_insn "*movqi_extv_1"
1602 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1603 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1608 switch (get_attr_type (insn))
1611 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1613 return "mov{b}\t{%h1, %0|%0, %h1}";
1617 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1618 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1619 (ne (symbol_ref "TARGET_MOVX")
1621 (const_string "imovx")
1622 (const_string "imov")))
1624 (if_then_else (eq_attr "type" "imovx")
1626 (const_string "QI")))])
1628 (define_insn "*movqi_extv_1_rex64"
1629 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1630 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1635 switch (get_attr_type (insn))
1638 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1640 return "mov{b}\t{%h1, %0|%0, %h1}";
1644 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1645 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1646 (ne (symbol_ref "TARGET_MOVX")
1648 (const_string "imovx")
1649 (const_string "imov")))
1651 (if_then_else (eq_attr "type" "imovx")
1653 (const_string "QI")))])
1655 ;; Stores and loads of ax to arbitrary constant address.
1656 ;; We fake an second form of instruction to force reload to load address
1657 ;; into register when rax is not available
1658 (define_insn "*movabsqi_1_rex64"
1659 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1660 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1661 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1663 movabs{b}\t{%1, %P0|%P0, %1}
1664 mov{b}\t{%1, %a0|%a0, %1}"
1665 [(set_attr "type" "imov")
1666 (set_attr "modrm" "0,*")
1667 (set_attr "length_address" "8,0")
1668 (set_attr "length_immediate" "0,*")
1669 (set_attr "memory" "store")
1670 (set_attr "mode" "QI")])
1672 (define_insn "*movabsqi_2_rex64"
1673 [(set (match_operand:QI 0 "register_operand" "=a,r")
1674 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1675 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1677 movabs{b}\t{%P1, %0|%0, %P1}
1678 mov{b}\t{%a1, %0|%0, %a1}"
1679 [(set_attr "type" "imov")
1680 (set_attr "modrm" "0,*")
1681 (set_attr "length_address" "8,0")
1682 (set_attr "length_immediate" "0")
1683 (set_attr "memory" "load")
1684 (set_attr "mode" "QI")])
1686 (define_insn "*movsi_extzv_1"
1687 [(set (match_operand:SI 0 "register_operand" "=R")
1688 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1692 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1693 [(set_attr "type" "imovx")
1694 (set_attr "mode" "SI")])
1696 (define_insn "*movqi_extzv_2"
1697 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1698 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1703 switch (get_attr_type (insn))
1706 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1708 return "mov{b}\t{%h1, %0|%0, %h1}";
1712 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1713 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1714 (ne (symbol_ref "TARGET_MOVX")
1716 (const_string "imovx")
1717 (const_string "imov")))
1719 (if_then_else (eq_attr "type" "imovx")
1721 (const_string "QI")))])
1723 (define_insn "*movqi_extzv_2_rex64"
1724 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1725 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1730 switch (get_attr_type (insn))
1733 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1735 return "mov{b}\t{%h1, %0|%0, %h1}";
1739 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1740 (ne (symbol_ref "TARGET_MOVX")
1742 (const_string "imovx")
1743 (const_string "imov")))
1745 (if_then_else (eq_attr "type" "imovx")
1747 (const_string "QI")))])
1749 (define_insn "movsi_insv_1"
1750 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1753 (match_operand:SI 1 "general_operand" "Qmn"))]
1755 "mov{b}\t{%b1, %h0|%h0, %b1}"
1756 [(set_attr "type" "imov")
1757 (set_attr "mode" "QI")])
1759 (define_insn "movdi_insv_1_rex64"
1760 [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
1763 (match_operand:DI 1 "nonmemory_operand" "Qn"))]
1765 "mov{b}\t{%b1, %h0|%h0, %b1}"
1766 [(set_attr "type" "imov")
1767 (set_attr "mode" "QI")])
1769 (define_insn "*movqi_insv_2"
1770 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1773 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1776 "mov{b}\t{%h1, %h0|%h0, %h1}"
1777 [(set_attr "type" "imov")
1778 (set_attr "mode" "QI")])
1780 (define_expand "movdi"
1781 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1782 (match_operand:DI 1 "general_operand" ""))]
1784 "ix86_expand_move (DImode, operands); DONE;")
1786 (define_insn "*pushdi"
1787 [(set (match_operand:DI 0 "push_operand" "=<")
1788 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1792 (define_insn "*pushdi2_rex64"
1793 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1794 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1799 [(set_attr "type" "push,multi")
1800 (set_attr "mode" "DI")])
1802 ;; Convert impossible pushes of immediate to existing instructions.
1803 ;; First try to get scratch register and go through it. In case this
1804 ;; fails, push sign extended lower part first and then overwrite
1805 ;; upper part by 32bit move.
1807 [(match_scratch:DI 2 "r")
1808 (set (match_operand:DI 0 "push_operand" "")
1809 (match_operand:DI 1 "immediate_operand" ""))]
1810 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1811 && !x86_64_immediate_operand (operands[1], DImode)"
1812 [(set (match_dup 2) (match_dup 1))
1813 (set (match_dup 0) (match_dup 2))]
1816 ;; We need to define this as both peepholer and splitter for case
1817 ;; peephole2 pass is not run.
1818 ;; "&& 1" is needed to keep it from matching the previous pattern.
1820 [(set (match_operand:DI 0 "push_operand" "")
1821 (match_operand:DI 1 "immediate_operand" ""))]
1822 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1823 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1824 [(set (match_dup 0) (match_dup 1))
1825 (set (match_dup 2) (match_dup 3))]
1826 "split_di (operands + 1, 1, operands + 2, operands + 3);
1827 operands[1] = gen_lowpart (DImode, operands[2]);
1828 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1833 [(set (match_operand:DI 0 "push_operand" "")
1834 (match_operand:DI 1 "immediate_operand" ""))]
1835 "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
1836 && !symbolic_operand (operands[1], DImode)
1837 && !x86_64_immediate_operand (operands[1], DImode)"
1838 [(set (match_dup 0) (match_dup 1))
1839 (set (match_dup 2) (match_dup 3))]
1840 "split_di (operands + 1, 1, operands + 2, operands + 3);
1841 operands[1] = gen_lowpart (DImode, operands[2]);
1842 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1846 (define_insn "*pushdi2_prologue_rex64"
1847 [(set (match_operand:DI 0 "push_operand" "=<")
1848 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1849 (clobber (mem:BLK (scratch)))]
1852 [(set_attr "type" "push")
1853 (set_attr "mode" "DI")])
1855 (define_insn "*popdi1_epilogue_rex64"
1856 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1857 (mem:DI (reg:DI SP_REG)))
1858 (set (reg:DI SP_REG)
1859 (plus:DI (reg:DI SP_REG) (const_int 8)))
1860 (clobber (mem:BLK (scratch)))]
1863 [(set_attr "type" "pop")
1864 (set_attr "mode" "DI")])
1866 (define_insn "popdi1"
1867 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1868 (mem:DI (reg:DI SP_REG)))
1869 (set (reg:DI SP_REG)
1870 (plus:DI (reg:DI SP_REG) (const_int 8)))]
1873 [(set_attr "type" "pop")
1874 (set_attr "mode" "DI")])
1876 (define_insn "*movdi_xor_rex64"
1877 [(set (match_operand:DI 0 "register_operand" "=r")
1878 (match_operand:DI 1 "const0_operand" "i"))
1879 (clobber (reg:CC FLAGS_REG))]
1880 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1881 && reload_completed"
1882 "xor{l}\t{%k0, %k0|%k0, %k0}"
1883 [(set_attr "type" "alu1")
1884 (set_attr "mode" "SI")
1885 (set_attr "length_immediate" "0")])
1887 (define_insn "*movdi_or_rex64"
1888 [(set (match_operand:DI 0 "register_operand" "=r")
1889 (match_operand:DI 1 "const_int_operand" "i"))
1890 (clobber (reg:CC FLAGS_REG))]
1891 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1893 && operands[1] == constm1_rtx"
1895 operands[1] = constm1_rtx;
1896 return "or{q}\t{%1, %0|%0, %1}";
1898 [(set_attr "type" "alu1")
1899 (set_attr "mode" "DI")
1900 (set_attr "length_immediate" "1")])
1902 (define_insn "*movdi_2"
1903 [(set (match_operand:DI 0 "nonimmediate_operand"
1904 "=r ,o ,m*y,*y,m ,*Y,*Y,m ,*x,*x")
1905 (match_operand:DI 1 "general_operand"
1906 "riFo,riF,*y ,m ,*Y,*Y,m ,*x,*x,m "))]
1908 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1912 movq\t{%1, %0|%0, %1}
1913 movq\t{%1, %0|%0, %1}
1914 movq\t{%1, %0|%0, %1}
1915 movdqa\t{%1, %0|%0, %1}
1916 movq\t{%1, %0|%0, %1}
1917 movlps\t{%1, %0|%0, %1}
1918 movaps\t{%1, %0|%0, %1}
1919 movlps\t{%1, %0|%0, %1}"
1920 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov")
1921 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,V2SF,V4SF,V2SF")])
1924 [(set (match_operand:DI 0 "push_operand" "")
1925 (match_operand:DI 1 "general_operand" ""))]
1926 "!TARGET_64BIT && reload_completed
1927 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1929 "ix86_split_long_move (operands); DONE;")
1931 ;; %%% This multiword shite has got to go.
1933 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1934 (match_operand:DI 1 "general_operand" ""))]
1935 "!TARGET_64BIT && reload_completed
1936 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1937 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1939 "ix86_split_long_move (operands); DONE;")
1941 (define_insn "*movdi_1_rex64"
1942 [(set (match_operand:DI 0 "nonimmediate_operand"
1943 "=r,r ,r,mr,!mr,!*y,!rm,!*y,!*x,!rm,!*x,!*x,!*y")
1944 (match_operand:DI 1 "general_operand"
1945 "Z ,rem,i,re,n ,*y ,*y ,rm ,*x ,*x ,rm ,*y ,*x"))]
1947 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1948 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1950 switch (get_attr_type (insn))
1953 if (which_alternative == 11)
1954 return "movq2dq\t{%1, %0|%0, %1}";
1956 return "movdq2q\t{%1, %0|%0, %1}";
1958 if (get_attr_mode (insn) == MODE_TI)
1959 return "movdqa\t{%1, %0|%0, %1}";
1962 /* Moves from and into integer register is done using movd opcode with
1964 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1965 return "movd\t{%1, %0|%0, %1}";
1966 return "movq\t{%1, %0|%0, %1}";
1970 return "lea{q}\t{%a1, %0|%0, %a1}";
1972 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1974 if (get_attr_mode (insn) == MODE_SI)
1975 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1976 else if (which_alternative == 2)
1977 return "movabs{q}\t{%1, %0|%0, %1}";
1979 return "mov{q}\t{%1, %0|%0, %1}";
1983 (cond [(eq_attr "alternative" "5,6,7")
1984 (const_string "mmxmov")
1985 (eq_attr "alternative" "8,9,10")
1986 (const_string "ssemov")
1987 (eq_attr "alternative" "11,12")
1988 (const_string "ssecvt")
1989 (eq_attr "alternative" "4")
1990 (const_string "multi")
1991 (and (ne (symbol_ref "flag_pic") (const_int 0))
1992 (match_operand:DI 1 "symbolic_operand" ""))
1993 (const_string "lea")
1995 (const_string "imov")))
1996 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*")
1997 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*")
1998 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI,DI,DI")])
2000 (define_insn "*movdi_1_rex64_nointerunit"
2001 [(set (match_operand:DI 0 "nonimmediate_operand"
2002 "=r,r ,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
2003 (match_operand:DI 1 "general_operand"
2004 "Z,rem,i,re,n ,*y ,*y,m ,*Y ,*Y,m"))]
2006 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2007 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2009 switch (get_attr_type (insn))
2012 if (get_attr_mode (insn) == MODE_TI)
2013 return "movdqa\t{%1, %0|%0, %1}";
2016 return "movq\t{%1, %0|%0, %1}";
2020 return "lea{q}\t{%a1, %0|%0, %a1}";
2022 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2024 if (get_attr_mode (insn) == MODE_SI)
2025 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2026 else if (which_alternative == 2)
2027 return "movabs{q}\t{%1, %0|%0, %1}";
2029 return "mov{q}\t{%1, %0|%0, %1}";
2033 (cond [(eq_attr "alternative" "5,6,7")
2034 (const_string "mmxmov")
2035 (eq_attr "alternative" "8,9,10")
2036 (const_string "ssemov")
2037 (eq_attr "alternative" "4")
2038 (const_string "multi")
2039 (and (ne (symbol_ref "flag_pic") (const_int 0))
2040 (match_operand:DI 1 "symbolic_operand" ""))
2041 (const_string "lea")
2043 (const_string "imov")))
2044 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2045 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2046 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2048 ;; Stores and loads of ax to arbitrary constant address.
2049 ;; We fake an second form of instruction to force reload to load address
2050 ;; into register when rax is not available
2051 (define_insn "*movabsdi_1_rex64"
2052 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2053 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2054 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2056 movabs{q}\t{%1, %P0|%P0, %1}
2057 mov{q}\t{%1, %a0|%a0, %1}"
2058 [(set_attr "type" "imov")
2059 (set_attr "modrm" "0,*")
2060 (set_attr "length_address" "8,0")
2061 (set_attr "length_immediate" "0,*")
2062 (set_attr "memory" "store")
2063 (set_attr "mode" "DI")])
2065 (define_insn "*movabsdi_2_rex64"
2066 [(set (match_operand:DI 0 "register_operand" "=a,r")
2067 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2068 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2070 movabs{q}\t{%P1, %0|%0, %P1}
2071 mov{q}\t{%a1, %0|%0, %a1}"
2072 [(set_attr "type" "imov")
2073 (set_attr "modrm" "0,*")
2074 (set_attr "length_address" "8,0")
2075 (set_attr "length_immediate" "0")
2076 (set_attr "memory" "load")
2077 (set_attr "mode" "DI")])
2079 ;; Convert impossible stores of immediate to existing instructions.
2080 ;; First try to get scratch register and go through it. In case this
2081 ;; fails, move by 32bit parts.
2083 [(match_scratch:DI 2 "r")
2084 (set (match_operand:DI 0 "memory_operand" "")
2085 (match_operand:DI 1 "immediate_operand" ""))]
2086 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2087 && !x86_64_immediate_operand (operands[1], DImode)"
2088 [(set (match_dup 2) (match_dup 1))
2089 (set (match_dup 0) (match_dup 2))]
2092 ;; We need to define this as both peepholer and splitter for case
2093 ;; peephole2 pass is not run.
2094 ;; "&& 1" is needed to keep it from matching the previous pattern.
2096 [(set (match_operand:DI 0 "memory_operand" "")
2097 (match_operand:DI 1 "immediate_operand" ""))]
2098 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2099 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2100 [(set (match_dup 2) (match_dup 3))
2101 (set (match_dup 4) (match_dup 5))]
2102 "split_di (operands, 2, operands + 2, operands + 4);")
2105 [(set (match_operand:DI 0 "memory_operand" "")
2106 (match_operand:DI 1 "immediate_operand" ""))]
2107 "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
2108 && !symbolic_operand (operands[1], DImode)
2109 && !x86_64_immediate_operand (operands[1], DImode)"
2110 [(set (match_dup 2) (match_dup 3))
2111 (set (match_dup 4) (match_dup 5))]
2112 "split_di (operands, 2, operands + 2, operands + 4);")
2114 (define_insn "*swapdi_rex64"
2115 [(set (match_operand:DI 0 "register_operand" "+r")
2116 (match_operand:DI 1 "register_operand" "+r"))
2121 [(set_attr "type" "imov")
2122 (set_attr "mode" "DI")
2123 (set_attr "pent_pair" "np")
2124 (set_attr "athlon_decode" "vector")])
2126 (define_expand "movti"
2127 [(set (match_operand:TI 0 "nonimmediate_operand" "")
2128 (match_operand:TI 1 "nonimmediate_operand" ""))]
2129 "TARGET_SSE || TARGET_64BIT"
2132 ix86_expand_move (TImode, operands);
2134 ix86_expand_vector_move (TImode, operands);
2138 (define_insn "*movti_internal"
2139 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
2140 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
2141 "TARGET_SSE && !TARGET_64BIT
2142 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2144 switch (which_alternative)
2147 if (get_attr_mode (insn) == MODE_V4SF)
2148 return "xorps\t%0, %0";
2150 return "pxor\t%0, %0";
2153 if (get_attr_mode (insn) == MODE_V4SF)
2154 return "movaps\t{%1, %0|%0, %1}";
2156 return "movdqa\t{%1, %0|%0, %1}";
2161 [(set_attr "type" "ssemov,ssemov,ssemov")
2163 (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
2164 (const_string "V4SF")
2166 (eq_attr "alternative" "0,1")
2168 (ne (symbol_ref "optimize_size")
2170 (const_string "V4SF")
2171 (const_string "TI"))
2172 (eq_attr "alternative" "2")
2174 (ne (symbol_ref "optimize_size")
2176 (const_string "V4SF")
2177 (const_string "TI"))]
2178 (const_string "TI")))])
2180 (define_insn "*movti_rex64"
2181 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
2182 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
2184 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2186 switch (which_alternative)
2192 if (get_attr_mode (insn) == MODE_V4SF)
2193 return "xorps\t%0, %0";
2195 return "pxor\t%0, %0";
2198 if (get_attr_mode (insn) == MODE_V4SF)
2199 return "movaps\t{%1, %0|%0, %1}";
2201 return "movdqa\t{%1, %0|%0, %1}";
2206 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
2208 (cond [(eq_attr "alternative" "2,3")
2210 (ne (symbol_ref "optimize_size")
2212 (const_string "V4SF")
2213 (const_string "TI"))
2214 (eq_attr "alternative" "4")
2216 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
2218 (ne (symbol_ref "optimize_size")
2220 (const_string "V4SF")
2221 (const_string "TI"))]
2222 (const_string "DI")))])
2225 [(set (match_operand:TI 0 "nonimmediate_operand" "")
2226 (match_operand:TI 1 "general_operand" ""))]
2227 "reload_completed && !SSE_REG_P (operands[0])
2228 && !SSE_REG_P (operands[1])"
2230 "ix86_split_long_move (operands); DONE;")
2232 (define_expand "movsf"
2233 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2234 (match_operand:SF 1 "general_operand" ""))]
2236 "ix86_expand_move (SFmode, operands); DONE;")
2238 (define_insn "*pushsf"
2239 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2240 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2243 switch (which_alternative)
2246 return "push{l}\t%1";
2249 /* This insn should be already split before reg-stack. */
2253 [(set_attr "type" "multi,push,multi")
2254 (set_attr "mode" "SF,SI,SF")])
2256 (define_insn "*pushsf_rex64"
2257 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2258 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2261 switch (which_alternative)
2264 return "push{q}\t%q1";
2267 /* This insn should be already split before reg-stack. */
2271 [(set_attr "type" "multi,push,multi")
2272 (set_attr "mode" "SF,DI,SF")])
2275 [(set (match_operand:SF 0 "push_operand" "")
2276 (match_operand:SF 1 "memory_operand" ""))]
2278 && GET_CODE (operands[1]) == MEM
2279 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2280 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2283 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2286 ;; %%% Kill this when call knows how to work this out.
2288 [(set (match_operand:SF 0 "push_operand" "")
2289 (match_operand:SF 1 "any_fp_register_operand" ""))]
2291 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
2292 (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])
2295 [(set (match_operand:SF 0 "push_operand" "")
2296 (match_operand:SF 1 "any_fp_register_operand" ""))]
2298 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2299 (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
2301 (define_insn "*movsf_1"
2302 [(set (match_operand:SF 0 "nonimmediate_operand"
2303 "=f#xr,m ,f#xr,r#xf ,m ,x#rf,x#rf,x#rf ,m ,!*y,!rm,!*y")
2304 (match_operand:SF 1 "general_operand"
2305 "fm#rx,f#rx,G ,rmF#fx,Fr#fx,C ,x ,xm#rf,x#rf,rm ,*y ,*y"))]
2306 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2307 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2308 && (reload_in_progress || reload_completed
2309 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2310 || GET_CODE (operands[1]) != CONST_DOUBLE
2311 || memory_operand (operands[0], SFmode))"
2313 switch (which_alternative)
2316 return output_387_reg_move (insn, operands);
2319 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2320 return "fstp%z0\t%y0";
2322 return "fst%z0\t%y0";
2325 return standard_80387_constant_opcode (operands[1]);
2329 return "mov{l}\t{%1, %0|%0, %1}";
2331 if (get_attr_mode (insn) == MODE_TI)
2332 return "pxor\t%0, %0";
2334 return "xorps\t%0, %0";
2336 if (get_attr_mode (insn) == MODE_V4SF)
2337 return "movaps\t{%1, %0|%0, %1}";
2339 return "movss\t{%1, %0|%0, %1}";
2342 return "movss\t{%1, %0|%0, %1}";
2346 return "movd\t{%1, %0|%0, %1}";
2349 return "movq\t{%1, %0|%0, %1}";
2355 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2357 (cond [(eq_attr "alternative" "3,4,9,10")
2359 (eq_attr "alternative" "5")
2361 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2363 (ne (symbol_ref "TARGET_SSE2")
2365 (eq (symbol_ref "optimize_size")
2368 (const_string "V4SF"))
2369 /* For architectures resolving dependencies on
2370 whole SSE registers use APS move to break dependency
2371 chains, otherwise use short move to avoid extra work.
2373 Do the same for architectures resolving dependencies on
2374 the parts. While in DF mode it is better to always handle
2375 just register parts, the SF mode is different due to lack
2376 of instructions to load just part of the register. It is
2377 better to maintain the whole registers in single format
2378 to avoid problems on using packed logical operations. */
2379 (eq_attr "alternative" "6")
2381 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2383 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2385 (const_string "V4SF")
2386 (const_string "SF"))
2387 (eq_attr "alternative" "11")
2388 (const_string "DI")]
2389 (const_string "SF")))])
2391 (define_insn "*movsf_1_nointerunit"
2392 [(set (match_operand:SF 0 "nonimmediate_operand"
2393 "=f#xr,m ,f#xr,r#xf ,m ,x#rf,x#rf,x#rf ,m ,!*y,!m,!*y")
2394 (match_operand:SF 1 "general_operand"
2395 "fm#rx,f#rx,G ,rmF#fx,Fr#fx,C ,x ,xm#rf,x#rf,m ,*y,*y"))]
2396 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2397 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2398 && (reload_in_progress || reload_completed
2399 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2400 || GET_CODE (operands[1]) != CONST_DOUBLE
2401 || memory_operand (operands[0], SFmode))"
2403 switch (which_alternative)
2406 return output_387_reg_move (insn, operands);
2409 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2410 return "fstp%z0\t%y0";
2412 return "fst%z0\t%y0";
2415 return standard_80387_constant_opcode (operands[1]);
2419 return "mov{l}\t{%1, %0|%0, %1}";
2421 if (get_attr_mode (insn) == MODE_TI)
2422 return "pxor\t%0, %0";
2424 return "xorps\t%0, %0";
2426 if (get_attr_mode (insn) == MODE_V4SF)
2427 return "movaps\t{%1, %0|%0, %1}";
2429 return "movss\t{%1, %0|%0, %1}";
2432 return "movss\t{%1, %0|%0, %1}";
2436 return "movd\t{%1, %0|%0, %1}";
2439 return "movq\t{%1, %0|%0, %1}";
2445 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2447 (cond [(eq_attr "alternative" "3,4,9,10")
2449 (eq_attr "alternative" "5")
2451 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2453 (ne (symbol_ref "TARGET_SSE2")
2455 (eq (symbol_ref "optimize_size")
2458 (const_string "V4SF"))
2459 /* For architectures resolving dependencies on
2460 whole SSE registers use APS move to break dependency
2461 chains, otherwise use short move to avoid extra work.
2463 Do the same for architectures resolving dependencies on
2464 the parts. While in DF mode it is better to always handle
2465 just register parts, the SF mode is different due to lack
2466 of instructions to load just part of the register. It is
2467 better to maintain the whole registers in single format
2468 to avoid problems on using packed logical operations. */
2469 (eq_attr "alternative" "6")
2471 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2473 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2475 (const_string "V4SF")
2476 (const_string "SF"))
2477 (eq_attr "alternative" "11")
2478 (const_string "DI")]
2479 (const_string "SF")))])
2481 (define_insn "*swapsf"
2482 [(set (match_operand:SF 0 "fp_register_operand" "+f")
2483 (match_operand:SF 1 "fp_register_operand" "+f"))
2486 "reload_completed || TARGET_80387"
2488 if (STACK_TOP_P (operands[0]))
2493 [(set_attr "type" "fxch")
2494 (set_attr "mode" "SF")])
2496 (define_expand "movdf"
2497 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2498 (match_operand:DF 1 "general_operand" ""))]
2500 "ix86_expand_move (DFmode, operands); DONE;")
2502 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2503 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2504 ;; On the average, pushdf using integers can be still shorter. Allow this
2505 ;; pattern for optimize_size too.
2507 (define_insn "*pushdf_nointeger"
2508 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2509 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2510 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2512 /* This insn should be already split before reg-stack. */
2515 [(set_attr "type" "multi")
2516 (set_attr "mode" "DF,SI,SI,DF")])
2518 (define_insn "*pushdf_integer"
2519 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2520 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2521 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2523 /* This insn should be already split before reg-stack. */
2526 [(set_attr "type" "multi")
2527 (set_attr "mode" "DF,SI,DF")])
2529 ;; %%% Kill this when call knows how to work this out.
2531 [(set (match_operand:DF 0 "push_operand" "")
2532 (match_operand:DF 1 "any_fp_register_operand" ""))]
2533 "!TARGET_64BIT && reload_completed"
2534 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
2535 (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
2539 [(set (match_operand:DF 0 "push_operand" "")
2540 (match_operand:DF 1 "any_fp_register_operand" ""))]
2541 "TARGET_64BIT && reload_completed"
2542 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2543 (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
2547 [(set (match_operand:DF 0 "push_operand" "")
2548 (match_operand:DF 1 "general_operand" ""))]
2551 "ix86_split_long_move (operands); DONE;")
2553 ;; Moving is usually shorter when only FP registers are used. This separate
2554 ;; movdf pattern avoids the use of integer registers for FP operations
2555 ;; when optimizing for size.
2557 (define_insn "*movdf_nointeger"
2558 [(set (match_operand:DF 0 "nonimmediate_operand"
2559 "=f#Y,m ,f#Y,*r ,o ,Y#f*x,Y#f*x,Y#f*x ,m ")
2560 (match_operand:DF 1 "general_operand"
2561 "fm#Y,f#Y,G ,*roF,F*r,C ,Y#f*x,HmY#f*x,Y#f*x"))]
2562 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2563 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2564 && (reload_in_progress || reload_completed
2565 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2566 || GET_CODE (operands[1]) != CONST_DOUBLE
2567 || memory_operand (operands[0], DFmode))"
2569 switch (which_alternative)
2572 return output_387_reg_move (insn, operands);
2575 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2576 return "fstp%z0\t%y0";
2578 return "fst%z0\t%y0";
2581 return standard_80387_constant_opcode (operands[1]);
2587 switch (get_attr_mode (insn))
2590 return "xorps\t%0, %0";
2592 return "xorpd\t%0, %0";
2594 return "pxor\t%0, %0";
2601 switch (get_attr_mode (insn))
2604 return "movaps\t{%1, %0|%0, %1}";
2606 return "movapd\t{%1, %0|%0, %1}";
2608 return "movdqa\t{%1, %0|%0, %1}";
2610 return "movq\t{%1, %0|%0, %1}";
2612 return "movsd\t{%1, %0|%0, %1}";
2614 return "movlpd\t{%1, %0|%0, %1}";
2616 return "movlps\t{%1, %0|%0, %1}";
2625 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2627 (cond [(eq_attr "alternative" "0,1,2")
2629 (eq_attr "alternative" "3,4")
2632 /* For SSE1, we have many fewer alternatives. */
2633 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2634 (cond [(eq_attr "alternative" "5,6")
2635 (const_string "V4SF")
2637 (const_string "V2SF"))
2639 /* xorps is one byte shorter. */
2640 (eq_attr "alternative" "5")
2641 (cond [(ne (symbol_ref "optimize_size")
2643 (const_string "V4SF")
2644 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2648 (const_string "V2DF"))
2650 /* For architectures resolving dependencies on
2651 whole SSE registers use APD move to break dependency
2652 chains, otherwise use short move to avoid extra work.
2654 movaps encodes one byte shorter. */
2655 (eq_attr "alternative" "6")
2657 [(ne (symbol_ref "optimize_size")
2659 (const_string "V4SF")
2660 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2662 (const_string "V2DF")
2664 (const_string "DF"))
2665 /* For architectures resolving dependencies on register
2666 parts we may avoid extra work to zero out upper part
2668 (eq_attr "alternative" "7")
2670 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2672 (const_string "V1DF")
2673 (const_string "DF"))
2675 (const_string "DF")))])
2677 (define_insn "*movdf_integer"
2678 [(set (match_operand:DF 0 "nonimmediate_operand"
2679 "=f#Yr,m ,f#Yr,r#Yf ,o ,Y#rf*x,Y#rf*x,Y#rf*x,m")
2680 (match_operand:DF 1 "general_operand"
2681 "fm#Yr,f#Yr,G ,roF#Yf,Fr#Yf,C ,Y#rf*x,m ,Y#rf*x"))]
2682 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2683 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2684 && (reload_in_progress || reload_completed
2685 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2686 || GET_CODE (operands[1]) != CONST_DOUBLE
2687 || memory_operand (operands[0], DFmode))"
2689 switch (which_alternative)
2692 return output_387_reg_move (insn, operands);
2695 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2696 return "fstp%z0\t%y0";
2698 return "fst%z0\t%y0";
2701 return standard_80387_constant_opcode (operands[1]);
2708 switch (get_attr_mode (insn))
2711 return "xorps\t%0, %0";
2713 return "xorpd\t%0, %0";
2715 return "pxor\t%0, %0";
2722 switch (get_attr_mode (insn))
2725 return "movaps\t{%1, %0|%0, %1}";
2727 return "movapd\t{%1, %0|%0, %1}";
2729 return "movdqa\t{%1, %0|%0, %1}";
2731 return "movq\t{%1, %0|%0, %1}";
2733 return "movsd\t{%1, %0|%0, %1}";
2735 return "movlpd\t{%1, %0|%0, %1}";
2737 return "movlps\t{%1, %0|%0, %1}";
2746 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2748 (cond [(eq_attr "alternative" "0,1,2")
2750 (eq_attr "alternative" "3,4")
2753 /* For SSE1, we have many fewer alternatives. */
2754 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2755 (cond [(eq_attr "alternative" "5,6")
2756 (const_string "V4SF")
2758 (const_string "V2SF"))
2760 /* xorps is one byte shorter. */
2761 (eq_attr "alternative" "5")
2762 (cond [(ne (symbol_ref "optimize_size")
2764 (const_string "V4SF")
2765 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2769 (const_string "V2DF"))
2771 /* For architectures resolving dependencies on
2772 whole SSE registers use APD move to break dependency
2773 chains, otherwise use short move to avoid extra work.
2775 movaps encodes one byte shorter. */
2776 (eq_attr "alternative" "6")
2778 [(ne (symbol_ref "optimize_size")
2780 (const_string "V4SF")
2781 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2783 (const_string "V2DF")
2785 (const_string "DF"))
2786 /* For architectures resolving dependencies on register
2787 parts we may avoid extra work to zero out upper part
2789 (eq_attr "alternative" "7")
2791 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2793 (const_string "V1DF")
2794 (const_string "DF"))
2796 (const_string "DF")))])
2799 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2800 (match_operand:DF 1 "general_operand" ""))]
2802 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2803 && ! (ANY_FP_REG_P (operands[0]) ||
2804 (GET_CODE (operands[0]) == SUBREG
2805 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2806 && ! (ANY_FP_REG_P (operands[1]) ||
2807 (GET_CODE (operands[1]) == SUBREG
2808 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2810 "ix86_split_long_move (operands); DONE;")
2812 (define_insn "*swapdf"
2813 [(set (match_operand:DF 0 "fp_register_operand" "+f")
2814 (match_operand:DF 1 "fp_register_operand" "+f"))
2817 "reload_completed || TARGET_80387"
2819 if (STACK_TOP_P (operands[0]))
2824 [(set_attr "type" "fxch")
2825 (set_attr "mode" "DF")])
2827 (define_expand "movxf"
2828 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2829 (match_operand:XF 1 "general_operand" ""))]
2831 "ix86_expand_move (XFmode, operands); DONE;")
2833 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2834 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2835 ;; Pushing using integer instructions is longer except for constants
2836 ;; and direct memory references.
2837 ;; (assuming that any given constant is pushed only once, but this ought to be
2838 ;; handled elsewhere).
2840 (define_insn "*pushxf_nointeger"
2841 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2842 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2845 /* This insn should be already split before reg-stack. */
2848 [(set_attr "type" "multi")
2849 (set_attr "mode" "XF,SI,SI")])
2851 (define_insn "*pushxf_integer"
2852 [(set (match_operand:XF 0 "push_operand" "=<,<")
2853 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2856 /* This insn should be already split before reg-stack. */
2859 [(set_attr "type" "multi")
2860 (set_attr "mode" "XF,SI")])
2863 [(set (match_operand 0 "push_operand" "")
2864 (match_operand 1 "general_operand" ""))]
2866 && (GET_MODE (operands[0]) == XFmode
2867 || GET_MODE (operands[0]) == DFmode)
2868 && !ANY_FP_REG_P (operands[1])"
2870 "ix86_split_long_move (operands); DONE;")
2873 [(set (match_operand:XF 0 "push_operand" "")
2874 (match_operand:XF 1 "any_fp_register_operand" ""))]
2876 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
2877 (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
2878 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2881 [(set (match_operand:XF 0 "push_operand" "")
2882 (match_operand:XF 1 "any_fp_register_operand" ""))]
2884 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
2885 (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
2886 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2888 ;; Do not use integer registers when optimizing for size
2889 (define_insn "*movxf_nointeger"
2890 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2891 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2893 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2894 && (reload_in_progress || reload_completed
2895 || GET_CODE (operands[1]) != CONST_DOUBLE
2896 || memory_operand (operands[0], XFmode))"
2898 switch (which_alternative)
2901 return output_387_reg_move (insn, operands);
2904 /* There is no non-popping store to memory for XFmode. So if
2905 we need one, follow the store with a load. */
2906 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2907 return "fstp%z0\t%y0\;fld%z0\t%y0";
2909 return "fstp%z0\t%y0";
2912 return standard_80387_constant_opcode (operands[1]);
2919 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2920 (set_attr "mode" "XF,XF,XF,SI,SI")])
2922 (define_insn "*movxf_integer"
2923 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2924 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2926 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2927 && (reload_in_progress || reload_completed
2928 || GET_CODE (operands[1]) != CONST_DOUBLE
2929 || memory_operand (operands[0], XFmode))"
2931 switch (which_alternative)
2934 return output_387_reg_move (insn, operands);
2937 /* There is no non-popping store to memory for XFmode. So if
2938 we need one, follow the store with a load. */
2939 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2940 return "fstp%z0\t%y0\;fld%z0\t%y0";
2942 return "fstp%z0\t%y0";
2945 return standard_80387_constant_opcode (operands[1]);
2952 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2953 (set_attr "mode" "XF,XF,XF,SI,SI")])
2956 [(set (match_operand 0 "nonimmediate_operand" "")
2957 (match_operand 1 "general_operand" ""))]
2959 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2960 && GET_MODE (operands[0]) == XFmode
2961 && ! (ANY_FP_REG_P (operands[0]) ||
2962 (GET_CODE (operands[0]) == SUBREG
2963 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2964 && ! (ANY_FP_REG_P (operands[1]) ||
2965 (GET_CODE (operands[1]) == SUBREG
2966 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2968 "ix86_split_long_move (operands); DONE;")
2971 [(set (match_operand 0 "register_operand" "")
2972 (match_operand 1 "memory_operand" ""))]
2974 && GET_CODE (operands[1]) == MEM
2975 && (GET_MODE (operands[0]) == XFmode
2976 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2977 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2978 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2979 [(set (match_dup 0) (match_dup 1))]
2981 rtx c = get_pool_constant (XEXP (operands[1], 0));
2982 rtx r = operands[0];
2984 if (GET_CODE (r) == SUBREG)
2989 if (!standard_sse_constant_p (c))
2992 else if (FP_REG_P (r))
2994 if (!standard_80387_constant_p (c))
2997 else if (MMX_REG_P (r))
3003 (define_insn "swapxf"
3004 [(set (match_operand:XF 0 "register_operand" "+f")
3005 (match_operand:XF 1 "register_operand" "+f"))
3010 if (STACK_TOP_P (operands[0]))
3015 [(set_attr "type" "fxch")
3016 (set_attr "mode" "XF")])
3018 (define_expand "movtf"
3019 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3020 (match_operand:TF 1 "nonimmediate_operand" ""))]
3023 ix86_expand_move (TFmode, operands);
3027 (define_insn "*movtf_internal"
3028 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
3029 (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
3031 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3033 switch (which_alternative)
3039 if (get_attr_mode (insn) == MODE_V4SF)
3040 return "xorps\t%0, %0";
3042 return "pxor\t%0, %0";
3045 if (get_attr_mode (insn) == MODE_V4SF)
3046 return "movaps\t{%1, %0|%0, %1}";
3048 return "movdqa\t{%1, %0|%0, %1}";
3053 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
3055 (cond [(eq_attr "alternative" "2,3")
3057 (ne (symbol_ref "optimize_size")
3059 (const_string "V4SF")
3060 (const_string "TI"))
3061 (eq_attr "alternative" "4")
3063 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
3065 (ne (symbol_ref "optimize_size")
3067 (const_string "V4SF")
3068 (const_string "TI"))]
3069 (const_string "DI")))])
3072 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3073 (match_operand:TF 1 "general_operand" ""))]
3074 "reload_completed && !SSE_REG_P (operands[0])
3075 && !SSE_REG_P (operands[1])"
3077 "ix86_split_long_move (operands); DONE;")
3079 ;; Zero extension instructions
3081 (define_expand "zero_extendhisi2"
3082 [(set (match_operand:SI 0 "register_operand" "")
3083 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3086 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3088 operands[1] = force_reg (HImode, operands[1]);
3089 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3094 (define_insn "zero_extendhisi2_and"
3095 [(set (match_operand:SI 0 "register_operand" "=r")
3096 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3097 (clobber (reg:CC FLAGS_REG))]
3098 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3100 [(set_attr "type" "alu1")
3101 (set_attr "mode" "SI")])
3104 [(set (match_operand:SI 0 "register_operand" "")
3105 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3106 (clobber (reg:CC FLAGS_REG))]
3107 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3108 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3109 (clobber (reg:CC FLAGS_REG))])]
3112 (define_insn "*zero_extendhisi2_movzwl"
3113 [(set (match_operand:SI 0 "register_operand" "=r")
3114 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3115 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3116 "movz{wl|x}\t{%1, %0|%0, %1}"
3117 [(set_attr "type" "imovx")
3118 (set_attr "mode" "SI")])
3120 (define_expand "zero_extendqihi2"
3122 [(set (match_operand:HI 0 "register_operand" "")
3123 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3124 (clobber (reg:CC FLAGS_REG))])]
3128 (define_insn "*zero_extendqihi2_and"
3129 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3130 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3131 (clobber (reg:CC FLAGS_REG))]
3132 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3134 [(set_attr "type" "alu1")
3135 (set_attr "mode" "HI")])
3137 (define_insn "*zero_extendqihi2_movzbw_and"
3138 [(set (match_operand:HI 0 "register_operand" "=r,r")
3139 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3140 (clobber (reg:CC FLAGS_REG))]
3141 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3143 [(set_attr "type" "imovx,alu1")
3144 (set_attr "mode" "HI")])
3146 (define_insn "*zero_extendqihi2_movzbw"
3147 [(set (match_operand:HI 0 "register_operand" "=r")
3148 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3149 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3150 "movz{bw|x}\t{%1, %0|%0, %1}"
3151 [(set_attr "type" "imovx")
3152 (set_attr "mode" "HI")])
3154 ;; For the movzbw case strip only the clobber
3156 [(set (match_operand:HI 0 "register_operand" "")
3157 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3158 (clobber (reg:CC FLAGS_REG))]
3160 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3161 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3162 [(set (match_operand:HI 0 "register_operand" "")
3163 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3165 ;; When source and destination does not overlap, clear destination
3166 ;; first and then do the movb
3168 [(set (match_operand:HI 0 "register_operand" "")
3169 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3170 (clobber (reg:CC FLAGS_REG))]
3172 && ANY_QI_REG_P (operands[0])
3173 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3174 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3175 [(set (match_dup 0) (const_int 0))
3176 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3177 "operands[2] = gen_lowpart (QImode, operands[0]);")
3179 ;; Rest is handled by single and.
3181 [(set (match_operand:HI 0 "register_operand" "")
3182 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3183 (clobber (reg:CC FLAGS_REG))]
3185 && true_regnum (operands[0]) == true_regnum (operands[1])"
3186 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3187 (clobber (reg:CC FLAGS_REG))])]
3190 (define_expand "zero_extendqisi2"
3192 [(set (match_operand:SI 0 "register_operand" "")
3193 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3194 (clobber (reg:CC FLAGS_REG))])]
3198 (define_insn "*zero_extendqisi2_and"
3199 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3200 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3201 (clobber (reg:CC FLAGS_REG))]
3202 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3204 [(set_attr "type" "alu1")
3205 (set_attr "mode" "SI")])
3207 (define_insn "*zero_extendqisi2_movzbw_and"
3208 [(set (match_operand:SI 0 "register_operand" "=r,r")
3209 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3210 (clobber (reg:CC FLAGS_REG))]
3211 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3213 [(set_attr "type" "imovx,alu1")
3214 (set_attr "mode" "SI")])
3216 (define_insn "*zero_extendqisi2_movzbw"
3217 [(set (match_operand:SI 0 "register_operand" "=r")
3218 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3219 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3220 "movz{bl|x}\t{%1, %0|%0, %1}"
3221 [(set_attr "type" "imovx")
3222 (set_attr "mode" "SI")])
3224 ;; For the movzbl case strip only the clobber
3226 [(set (match_operand:SI 0 "register_operand" "")
3227 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3228 (clobber (reg:CC FLAGS_REG))]
3230 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3231 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3233 (zero_extend:SI (match_dup 1)))])
3235 ;; When source and destination does not overlap, clear destination
3236 ;; first and then do the movb
3238 [(set (match_operand:SI 0 "register_operand" "")
3239 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3240 (clobber (reg:CC FLAGS_REG))]
3242 && ANY_QI_REG_P (operands[0])
3243 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3244 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3245 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3246 [(set (match_dup 0) (const_int 0))
3247 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3248 "operands[2] = gen_lowpart (QImode, operands[0]);")
3250 ;; Rest is handled by single and.
3252 [(set (match_operand:SI 0 "register_operand" "")
3253 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3254 (clobber (reg:CC FLAGS_REG))]
3256 && true_regnum (operands[0]) == true_regnum (operands[1])"
3257 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3258 (clobber (reg:CC FLAGS_REG))])]
3261 ;; %%% Kill me once multi-word ops are sane.
3262 (define_expand "zero_extendsidi2"
3263 [(set (match_operand:DI 0 "register_operand" "=r")
3264 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3268 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3273 (define_insn "zero_extendsidi2_32"
3274 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3275 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
3276 (clobber (reg:CC FLAGS_REG))]
3277 "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3282 movd\t{%1, %0|%0, %1}
3283 movd\t{%1, %0|%0, %1}"
3284 [(set_attr "mode" "SI,SI,SI,DI,TI")
3285 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3287 (define_insn "*zero_extendsidi2_32_1"
3288 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3289 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
3290 (clobber (reg:CC FLAGS_REG))]
3291 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3296 movd\t{%1, %0|%0, %1}
3297 movd\t{%1, %0|%0, %1}"
3298 [(set_attr "mode" "SI,SI,SI,DI,TI")
3299 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3301 (define_insn "zero_extendsidi2_rex64"
3302 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
3303 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
3304 "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3306 mov\t{%k1, %k0|%k0, %k1}
3308 movd\t{%1, %0|%0, %1}
3309 movd\t{%1, %0|%0, %1}"
3310 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3311 (set_attr "mode" "SI,DI,DI,TI")])
3313 (define_insn "*zero_extendsidi2_rex64_1"
3314 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
3315 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
3316 "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3318 mov\t{%k1, %k0|%k0, %k1}
3320 movd\t{%1, %0|%0, %1}
3321 movd\t{%1, %0|%0, %1}"
3322 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3323 (set_attr "mode" "SI,DI,SI,SI")])
3326 [(set (match_operand:DI 0 "memory_operand" "")
3327 (zero_extend:DI (match_dup 0)))]
3329 [(set (match_dup 4) (const_int 0))]
3330 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3333 [(set (match_operand:DI 0 "register_operand" "")
3334 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3335 (clobber (reg:CC FLAGS_REG))]
3336 "!TARGET_64BIT && reload_completed
3337 && true_regnum (operands[0]) == true_regnum (operands[1])"
3338 [(set (match_dup 4) (const_int 0))]
3339 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3342 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3343 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3344 (clobber (reg:CC FLAGS_REG))]
3345 "!TARGET_64BIT && reload_completed
3346 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3347 [(set (match_dup 3) (match_dup 1))
3348 (set (match_dup 4) (const_int 0))]
3349 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3351 (define_insn "zero_extendhidi2"
3352 [(set (match_operand:DI 0 "register_operand" "=r,r")
3353 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3356 movz{wl|x}\t{%1, %k0|%k0, %1}
3357 movz{wq|x}\t{%1, %0|%0, %1}"
3358 [(set_attr "type" "imovx")
3359 (set_attr "mode" "SI,DI")])
3361 (define_insn "zero_extendqidi2"
3362 [(set (match_operand:DI 0 "register_operand" "=r,r")
3363 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3366 movz{bl|x}\t{%1, %k0|%k0, %1}
3367 movz{bq|x}\t{%1, %0|%0, %1}"
3368 [(set_attr "type" "imovx")
3369 (set_attr "mode" "SI,DI")])
3371 ;; Sign extension instructions
3373 (define_expand "extendsidi2"
3374 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3375 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3376 (clobber (reg:CC FLAGS_REG))
3377 (clobber (match_scratch:SI 2 ""))])]
3382 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3387 (define_insn "*extendsidi2_1"
3388 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3389 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3390 (clobber (reg:CC FLAGS_REG))
3391 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3395 (define_insn "extendsidi2_rex64"
3396 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3397 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3401 movs{lq|x}\t{%1,%0|%0, %1}"
3402 [(set_attr "type" "imovx")
3403 (set_attr "mode" "DI")
3404 (set_attr "prefix_0f" "0")
3405 (set_attr "modrm" "0,1")])
3407 (define_insn "extendhidi2"
3408 [(set (match_operand:DI 0 "register_operand" "=r")
3409 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3411 "movs{wq|x}\t{%1,%0|%0, %1}"
3412 [(set_attr "type" "imovx")
3413 (set_attr "mode" "DI")])
3415 (define_insn "extendqidi2"
3416 [(set (match_operand:DI 0 "register_operand" "=r")
3417 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3419 "movs{bq|x}\t{%1,%0|%0, %1}"
3420 [(set_attr "type" "imovx")
3421 (set_attr "mode" "DI")])
3423 ;; Extend to memory case when source register does die.
3425 [(set (match_operand:DI 0 "memory_operand" "")
3426 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3427 (clobber (reg:CC FLAGS_REG))
3428 (clobber (match_operand:SI 2 "register_operand" ""))]
3430 && dead_or_set_p (insn, operands[1])
3431 && !reg_mentioned_p (operands[1], operands[0]))"
3432 [(set (match_dup 3) (match_dup 1))
3433 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3434 (clobber (reg:CC FLAGS_REG))])
3435 (set (match_dup 4) (match_dup 1))]
3436 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3438 ;; Extend to memory case when source register does not die.
3440 [(set (match_operand:DI 0 "memory_operand" "")
3441 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3442 (clobber (reg:CC FLAGS_REG))
3443 (clobber (match_operand:SI 2 "register_operand" ""))]
3447 split_di (&operands[0], 1, &operands[3], &operands[4]);
3449 emit_move_insn (operands[3], operands[1]);
3451 /* Generate a cltd if possible and doing so it profitable. */
3452 if (true_regnum (operands[1]) == 0
3453 && true_regnum (operands[2]) == 1
3454 && (optimize_size || TARGET_USE_CLTD))
3456 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3460 emit_move_insn (operands[2], operands[1]);
3461 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3463 emit_move_insn (operands[4], operands[2]);
3467 ;; Extend to register case. Optimize case where source and destination
3468 ;; registers match and cases where we can use cltd.
3470 [(set (match_operand:DI 0 "register_operand" "")
3471 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3472 (clobber (reg:CC FLAGS_REG))
3473 (clobber (match_scratch:SI 2 ""))]
3477 split_di (&operands[0], 1, &operands[3], &operands[4]);
3479 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3480 emit_move_insn (operands[3], operands[1]);
3482 /* Generate a cltd if possible and doing so it profitable. */
3483 if (true_regnum (operands[3]) == 0
3484 && (optimize_size || TARGET_USE_CLTD))
3486 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3490 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3491 emit_move_insn (operands[4], operands[1]);
3493 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3497 (define_insn "extendhisi2"
3498 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3499 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3502 switch (get_attr_prefix_0f (insn))
3505 return "{cwtl|cwde}";
3507 return "movs{wl|x}\t{%1,%0|%0, %1}";
3510 [(set_attr "type" "imovx")
3511 (set_attr "mode" "SI")
3512 (set (attr "prefix_0f")
3513 ;; movsx is short decodable while cwtl is vector decoded.
3514 (if_then_else (and (eq_attr "cpu" "!k6")
3515 (eq_attr "alternative" "0"))
3517 (const_string "1")))
3519 (if_then_else (eq_attr "prefix_0f" "0")
3521 (const_string "1")))])
3523 (define_insn "*extendhisi2_zext"
3524 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3526 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3529 switch (get_attr_prefix_0f (insn))
3532 return "{cwtl|cwde}";
3534 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3537 [(set_attr "type" "imovx")
3538 (set_attr "mode" "SI")
3539 (set (attr "prefix_0f")
3540 ;; movsx is short decodable while cwtl is vector decoded.
3541 (if_then_else (and (eq_attr "cpu" "!k6")
3542 (eq_attr "alternative" "0"))
3544 (const_string "1")))
3546 (if_then_else (eq_attr "prefix_0f" "0")
3548 (const_string "1")))])
3550 (define_insn "extendqihi2"
3551 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3552 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3555 switch (get_attr_prefix_0f (insn))
3558 return "{cbtw|cbw}";
3560 return "movs{bw|x}\t{%1,%0|%0, %1}";
3563 [(set_attr "type" "imovx")
3564 (set_attr "mode" "HI")
3565 (set (attr "prefix_0f")
3566 ;; movsx is short decodable while cwtl is vector decoded.
3567 (if_then_else (and (eq_attr "cpu" "!k6")
3568 (eq_attr "alternative" "0"))
3570 (const_string "1")))
3572 (if_then_else (eq_attr "prefix_0f" "0")
3574 (const_string "1")))])
3576 (define_insn "extendqisi2"
3577 [(set (match_operand:SI 0 "register_operand" "=r")
3578 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3580 "movs{bl|x}\t{%1,%0|%0, %1}"
3581 [(set_attr "type" "imovx")
3582 (set_attr "mode" "SI")])
3584 (define_insn "*extendqisi2_zext"
3585 [(set (match_operand:DI 0 "register_operand" "=r")
3587 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3589 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3590 [(set_attr "type" "imovx")
3591 (set_attr "mode" "SI")])
3593 ;; Conversions between float and double.
3595 ;; These are all no-ops in the model used for the 80387. So just
3598 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3599 (define_insn "*dummy_extendsfdf2"
3600 [(set (match_operand:DF 0 "push_operand" "=<")
3601 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3606 [(set (match_operand:DF 0 "push_operand" "")
3607 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3609 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
3610 (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
3613 [(set (match_operand:DF 0 "push_operand" "")
3614 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3616 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
3617 (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
3619 (define_insn "*dummy_extendsfxf2"
3620 [(set (match_operand:XF 0 "push_operand" "=<")
3621 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3626 [(set (match_operand:XF 0 "push_operand" "")
3627 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3629 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3630 (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3631 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3634 [(set (match_operand:XF 0 "push_operand" "")
3635 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3637 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3638 (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3639 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3642 [(set (match_operand:XF 0 "push_operand" "")
3643 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3645 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3646 (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3647 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3650 [(set (match_operand:XF 0 "push_operand" "")
3651 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3653 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3654 (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3655 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3657 (define_expand "extendsfdf2"
3658 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3659 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3660 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
3662 /* ??? Needed for compress_float_constant since all fp constants
3663 are LEGITIMATE_CONSTANT_P. */
3664 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3665 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3666 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3667 operands[1] = force_reg (SFmode, operands[1]);
3670 (define_insn "*extendsfdf2_mixed"
3671 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m#fY,Y#f")
3672 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3673 "TARGET_SSE2 && TARGET_MIX_SSE_I387
3674 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3676 switch (which_alternative)
3679 return output_387_reg_move (insn, operands);
3682 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3683 return "fstp%z0\t%y0";
3685 return "fst%z0\t%y0";
3688 return "cvtss2sd\t{%1, %0|%0, %1}";
3694 [(set_attr "type" "fmov,fmov,ssecvt")
3695 (set_attr "mode" "SF,XF,DF")])
3697 (define_insn "*extendsfdf2_sse"
3698 [(set (match_operand:DF 0 "register_operand" "=Y")
3699 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3700 "TARGET_SSE2 && TARGET_SSE_MATH
3701 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3702 "cvtss2sd\t{%1, %0|%0, %1}"
3703 [(set_attr "type" "ssecvt")
3704 (set_attr "mode" "DF")])
3706 (define_insn "*extendsfdf2_i387"
3707 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m")
3708 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3710 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3712 switch (which_alternative)
3715 return output_387_reg_move (insn, operands);
3718 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3719 return "fstp%z0\t%y0";
3721 return "fst%z0\t%y0";
3727 [(set_attr "type" "fmov")
3728 (set_attr "mode" "SF,XF")])
3730 (define_expand "extendsfxf2"
3731 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3732 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3735 /* ??? Needed for compress_float_constant since all fp constants
3736 are LEGITIMATE_CONSTANT_P. */
3737 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3738 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3739 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3740 operands[1] = force_reg (SFmode, operands[1]);
3743 (define_insn "*extendsfxf2_i387"
3744 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3745 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3747 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3749 switch (which_alternative)
3752 return output_387_reg_move (insn, operands);
3755 /* There is no non-popping store to memory for XFmode. So if
3756 we need one, follow the store with a load. */
3757 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3758 return "fstp%z0\t%y0";
3760 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3766 [(set_attr "type" "fmov")
3767 (set_attr "mode" "SF,XF")])
3769 (define_expand "extenddfxf2"
3770 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3771 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3774 /* ??? Needed for compress_float_constant since all fp constants
3775 are LEGITIMATE_CONSTANT_P. */
3776 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3777 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3778 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3779 operands[1] = force_reg (DFmode, operands[1]);
3782 (define_insn "*extenddfxf2_i387"
3783 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3784 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3786 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3788 switch (which_alternative)
3791 return output_387_reg_move (insn, operands);
3794 /* There is no non-popping store to memory for XFmode. So if
3795 we need one, follow the store with a load. */
3796 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3797 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3799 return "fstp%z0\t%y0";
3805 [(set_attr "type" "fmov")
3806 (set_attr "mode" "DF,XF")])
3808 ;; %%% This seems bad bad news.
3809 ;; This cannot output into an f-reg because there is no way to be sure
3810 ;; of truncating in that case. Otherwise this is just like a simple move
3811 ;; insn. So we pretend we can output to a reg in order to get better
3812 ;; register preferencing, but we really use a stack slot.
3814 ;; Conversion from DFmode to SFmode.
3816 (define_expand "truncdfsf2"
3817 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3819 (match_operand:DF 1 "nonimmediate_operand" "")))]
3820 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
3822 if (MEM_P (operands[0]) && MEM_P (operands[1]))
3823 operands[1] = force_reg (DFmode, operands[1]);
3825 if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)
3827 else if (flag_unsafe_math_optimizations)
3831 rtx temp = assign_386_stack_local (SFmode, 0);
3832 emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
3837 (define_expand "truncdfsf2_with_temp"
3838 [(parallel [(set (match_operand:SF 0 "" "")
3839 (float_truncate:SF (match_operand:DF 1 "" "")))
3840 (clobber (match_operand:SF 2 "" ""))])]
3843 (define_insn "*truncdfsf_fast_mixed"
3844 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f,Y")
3846 (match_operand:DF 1 "nonimmediate_operand" "f ,f,Ym")))]
3847 "TARGET_SSE2 && TARGET_MIX_SSE_I387 && flag_unsafe_math_optimizations"
3849 switch (which_alternative)
3852 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3853 return "fstp%z0\t%y0";
3855 return "fst%z0\t%y0";
3857 return output_387_reg_move (insn, operands);
3859 return "cvtsd2ss\t{%1, %0|%0, %1}";
3864 [(set_attr "type" "fmov,fmov,ssecvt")
3865 (set_attr "mode" "SF")])
3867 ;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
3868 ;; because nothing we do here is unsafe.
3869 (define_insn "*truncdfsf_fast_sse"
3870 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y")
3872 (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
3873 "TARGET_SSE2 && TARGET_SSE_MATH"
3874 "cvtsd2ss\t{%1, %0|%0, %1}"
3875 [(set_attr "type" "ssecvt")
3876 (set_attr "mode" "SF")])
3878 (define_insn "*truncdfsf_fast_i387"
3879 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
3881 (match_operand:DF 1 "nonimmediate_operand" "f")))]
3882 "TARGET_80387 && flag_unsafe_math_optimizations"
3883 "* return output_387_reg_move (insn, operands);"
3884 [(set_attr "type" "fmov")
3885 (set_attr "mode" "SF")])
3887 (define_insn "*truncdfsf_mixed"
3888 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Y")
3890 (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Ym")))
3891 (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))]
3892 "TARGET_MIX_SSE_I387"
3894 switch (which_alternative)
3897 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3898 return "fstp%z0\t%y0";
3900 return "fst%z0\t%y0";
3904 return "cvtsd2ss\t{%1, %0|%0, %1}";
3909 [(set_attr "type" "fmov,multi,ssecvt")
3910 (set_attr "mode" "SF")])
3912 (define_insn "*truncdfsf_i387"
3913 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
3915 (match_operand:DF 1 "nonimmediate_operand" "f,f")))
3916 (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
3919 switch (which_alternative)
3922 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3923 return "fstp%z0\t%y0";
3925 return "fst%z0\t%y0";
3932 [(set_attr "type" "fmov,multi")
3933 (set_attr "mode" "SF")])
3936 [(set (match_operand:SF 0 "register_operand" "")
3938 (match_operand:DF 1 "fp_register_operand" "")))
3939 (clobber (match_operand 2 "" ""))]
3941 [(set (match_dup 2) (match_dup 1))
3942 (set (match_dup 0) (match_dup 2))]
3944 operands[1] = gen_rtx_REG (SFmode, true_regnum (operands[1]));
3947 ;; Conversion from XFmode to SFmode.
3949 (define_expand "truncxfsf2"
3950 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3952 (match_operand:XF 1 "register_operand" "")))
3953 (clobber (match_dup 2))])]
3956 if (flag_unsafe_math_optimizations)
3958 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3959 emit_insn (gen_truncxfsf2_i387_noop (reg, operands[1]));
3960 if (reg != operands[0])
3961 emit_move_insn (operands[0], reg);
3965 operands[2] = assign_386_stack_local (SFmode, 0);
3968 (define_insn "*truncxfsf2_mixed"
3969 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3971 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3972 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3973 "TARGET_MIX_SSE_I387"
3975 switch (which_alternative)
3978 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3979 return "fstp%z0\t%y0";
3981 return "fst%z0\t%y0";
3986 [(set_attr "type" "fmov,multi,multi,multi")
3987 (set_attr "mode" "SF")])
3989 (define_insn "truncxfsf2_i387_noop"
3990 [(set (match_operand:SF 0 "register_operand" "=f")
3991 (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
3992 "TARGET_80387 && flag_unsafe_math_optimizations"
3994 return output_387_reg_move (insn, operands);
3996 [(set_attr "type" "fmov")
3997 (set_attr "mode" "SF")])
3999 (define_insn "*truncxfsf2_i387"
4000 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#r,?r#f")
4002 (match_operand:XF 1 "register_operand" "f,f,f")))
4003 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m"))]
4006 switch (which_alternative)
4009 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4010 return "fstp%z0\t%y0";
4012 return "fst%z0\t%y0";
4017 [(set_attr "type" "fmov,multi,multi")
4018 (set_attr "mode" "SF")])
4020 (define_insn "*truncxfsf2_i387_1"
4021 [(set (match_operand:SF 0 "memory_operand" "=m")
4023 (match_operand:XF 1 "register_operand" "f")))]
4026 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4027 return "fstp%z0\t%y0";
4029 return "fst%z0\t%y0";
4031 [(set_attr "type" "fmov")
4032 (set_attr "mode" "SF")])
4035 [(set (match_operand:SF 0 "register_operand" "")
4037 (match_operand:XF 1 "register_operand" "")))
4038 (clobber (match_operand:SF 2 "memory_operand" ""))]
4039 "TARGET_80387 && reload_completed"
4040 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4041 (set (match_dup 0) (match_dup 2))]
4045 [(set (match_operand:SF 0 "memory_operand" "")
4047 (match_operand:XF 1 "register_operand" "")))
4048 (clobber (match_operand:SF 2 "memory_operand" ""))]
4050 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4053 ;; Conversion from XFmode to DFmode.
4055 (define_expand "truncxfdf2"
4056 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4058 (match_operand:XF 1 "register_operand" "")))
4059 (clobber (match_dup 2))])]
4062 if (flag_unsafe_math_optimizations)
4064 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DFmode);
4065 emit_insn (gen_truncxfdf2_i387_noop (reg, operands[1]));
4066 if (reg != operands[0])
4067 emit_move_insn (operands[0], reg);
4071 operands[2] = assign_386_stack_local (DFmode, 0);
4074 (define_insn "*truncxfdf2_mixed"
4075 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4077 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4078 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4079 "TARGET_SSE2 && TARGET_MIX_SSE_I387"
4081 switch (which_alternative)
4084 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4085 return "fstp%z0\t%y0";
4087 return "fst%z0\t%y0";
4093 [(set_attr "type" "fmov,multi,multi,multi")
4094 (set_attr "mode" "DF")])
4096 (define_insn "truncxfdf2_i387_noop"
4097 [(set (match_operand:DF 0 "register_operand" "=f")
4098 (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
4099 "TARGET_80387 && flag_unsafe_math_optimizations"
4101 return output_387_reg_move (insn, operands);
4103 [(set_attr "type" "fmov")
4104 (set_attr "mode" "DF")])
4106 (define_insn "*truncxfdf2_i387"
4107 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#r,?r#f")
4109 (match_operand:XF 1 "register_operand" "f,f,f")))
4110 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m"))]
4113 switch (which_alternative)
4116 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4117 return "fstp%z0\t%y0";
4119 return "fst%z0\t%y0";
4124 [(set_attr "type" "fmov,multi,multi")
4125 (set_attr "mode" "DF")])
4127 (define_insn "*truncxfdf2_i387_1"
4128 [(set (match_operand:DF 0 "memory_operand" "=m")
4130 (match_operand:XF 1 "register_operand" "f")))]
4133 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4134 return "fstp%z0\t%y0";
4136 return "fst%z0\t%y0";
4138 [(set_attr "type" "fmov")
4139 (set_attr "mode" "DF")])
4142 [(set (match_operand:DF 0 "register_operand" "")
4144 (match_operand:XF 1 "register_operand" "")))
4145 (clobber (match_operand:DF 2 "memory_operand" ""))]
4146 "TARGET_80387 && reload_completed"
4147 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4148 (set (match_dup 0) (match_dup 2))]
4152 [(set (match_operand:DF 0 "memory_operand" "")
4154 (match_operand:XF 1 "register_operand" "")))
4155 (clobber (match_operand:DF 2 "memory_operand" ""))]
4157 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4160 ;; %%% Break up all these bad boys.
4162 ;; Signed conversion to DImode.
4164 (define_expand "fix_truncxfdi2"
4165 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4166 (fix:DI (match_operand:XF 1 "register_operand" "")))
4167 (clobber (reg:CC FLAGS_REG))])]
4171 (define_expand "fix_truncdfdi2"
4172 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4173 (fix:DI (match_operand:DF 1 "register_operand" "")))
4174 (clobber (reg:CC FLAGS_REG))])]
4175 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2)"
4177 if (TARGET_64BIT && TARGET_SSE2)
4179 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4180 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4181 if (out != operands[0])
4182 emit_move_insn (operands[0], out);
4187 (define_expand "fix_truncsfdi2"
4188 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4189 (fix:DI (match_operand:SF 1 "register_operand" "")))
4190 (clobber (reg:CC FLAGS_REG))])]
4191 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE)"
4193 if (TARGET_64BIT && TARGET_SSE)
4195 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4196 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4197 if (out != operands[0])
4198 emit_move_insn (operands[0], out);
4203 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4204 ;; of the machinery.
4205 (define_insn_and_split "*fix_truncdi_i387"
4206 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4207 (fix:DI (match_operand 1 "register_operand" "f,f")))
4208 (clobber (reg:CC FLAGS_REG))]
4209 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4210 && !reload_completed && !reload_in_progress
4211 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4216 ix86_optimize_mode_switching = 1;
4217 operands[2] = assign_386_stack_local (HImode, 1);
4218 operands[3] = assign_386_stack_local (HImode, 2);
4219 if (memory_operand (operands[0], VOIDmode))
4220 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4221 operands[2], operands[3]));
4224 operands[4] = assign_386_stack_local (DImode, 0);
4225 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4226 operands[2], operands[3],
4231 [(set_attr "type" "fistp")
4232 (set_attr "i387_cw" "trunc")
4233 (set_attr "mode" "DI")])
4235 (define_insn "fix_truncdi_nomemory"
4236 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4237 (fix:DI (match_operand 1 "register_operand" "f,f")))
4238 (use (match_operand:HI 2 "memory_operand" "m,m"))
4239 (use (match_operand:HI 3 "memory_operand" "m,m"))
4240 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4241 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4242 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4243 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4245 [(set_attr "type" "fistp")
4246 (set_attr "i387_cw" "trunc")
4247 (set_attr "mode" "DI")])
4249 (define_insn "fix_truncdi_memory"
4250 [(set (match_operand:DI 0 "memory_operand" "=m")
4251 (fix:DI (match_operand 1 "register_operand" "f")))
4252 (use (match_operand:HI 2 "memory_operand" "m"))
4253 (use (match_operand:HI 3 "memory_operand" "m"))
4254 (clobber (match_scratch:DF 4 "=&1f"))]
4255 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4256 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4257 "* return output_fix_trunc (insn, operands);"
4258 [(set_attr "type" "fistp")
4259 (set_attr "i387_cw" "trunc")
4260 (set_attr "mode" "DI")])
4263 [(set (match_operand:DI 0 "register_operand" "")
4264 (fix:DI (match_operand 1 "register_operand" "")))
4265 (use (match_operand:HI 2 "memory_operand" ""))
4266 (use (match_operand:HI 3 "memory_operand" ""))
4267 (clobber (match_operand:DI 4 "memory_operand" ""))
4268 (clobber (match_scratch 5 ""))]
4270 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4273 (clobber (match_dup 5))])
4274 (set (match_dup 0) (match_dup 4))]
4278 [(set (match_operand:DI 0 "memory_operand" "")
4279 (fix:DI (match_operand 1 "register_operand" "")))
4280 (use (match_operand:HI 2 "memory_operand" ""))
4281 (use (match_operand:HI 3 "memory_operand" ""))
4282 (clobber (match_operand:DI 4 "memory_operand" ""))
4283 (clobber (match_scratch 5 ""))]
4285 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4288 (clobber (match_dup 5))])]
4291 ;; When SSE available, it is always faster to use it!
4292 (define_insn "fix_truncsfdi_sse"
4293 [(set (match_operand:DI 0 "register_operand" "=r,r")
4294 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4295 "TARGET_64BIT && TARGET_SSE"
4296 "cvttss2si{q}\t{%1, %0|%0, %1}"
4297 [(set_attr "type" "sseicvt")
4298 (set_attr "mode" "SF")
4299 (set_attr "athlon_decode" "double,vector")])
4301 ;; Avoid vector decoded form of the instruction.
4303 [(match_scratch:SF 2 "x")
4304 (set (match_operand:DI 0 "register_operand" "")
4305 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4306 "TARGET_K8 && !optimize_size"
4307 [(set (match_dup 2) (match_dup 1))
4308 (set (match_dup 0) (fix:DI (match_dup 2)))]
4311 (define_insn "fix_truncdfdi_sse"
4312 [(set (match_operand:DI 0 "register_operand" "=r,r")
4313 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4314 "TARGET_64BIT && TARGET_SSE2"
4315 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4316 [(set_attr "type" "sseicvt,sseicvt")
4317 (set_attr "mode" "DF")
4318 (set_attr "athlon_decode" "double,vector")])
4320 ;; Avoid vector decoded form of the instruction.
4322 [(match_scratch:DF 2 "Y")
4323 (set (match_operand:DI 0 "register_operand" "")
4324 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4325 "TARGET_K8 && !optimize_size"
4326 [(set (match_dup 2) (match_dup 1))
4327 (set (match_dup 0) (fix:DI (match_dup 2)))]
4330 ;; Signed conversion to SImode.
4332 (define_expand "fix_truncxfsi2"
4333 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4334 (fix:SI (match_operand:XF 1 "register_operand" "")))
4335 (clobber (reg:CC FLAGS_REG))])]
4339 (define_expand "fix_truncdfsi2"
4340 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4341 (fix:SI (match_operand:DF 1 "register_operand" "")))
4342 (clobber (reg:CC FLAGS_REG))])]
4343 "TARGET_80387 || TARGET_SSE2"
4347 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4348 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4349 if (out != operands[0])
4350 emit_move_insn (operands[0], out);
4355 (define_expand "fix_truncsfsi2"
4356 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4357 (fix:SI (match_operand:SF 1 "register_operand" "")))
4358 (clobber (reg:CC FLAGS_REG))])]
4359 "TARGET_80387 || TARGET_SSE"
4363 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4364 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4365 if (out != operands[0])
4366 emit_move_insn (operands[0], out);
4371 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4372 ;; of the machinery.
4373 (define_insn_and_split "*fix_truncsi_i387"
4374 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4375 (fix:SI (match_operand 1 "register_operand" "f,f")))
4376 (clobber (reg:CC FLAGS_REG))]
4377 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4378 && !reload_completed && !reload_in_progress
4379 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4384 ix86_optimize_mode_switching = 1;
4385 operands[2] = assign_386_stack_local (HImode, 1);
4386 operands[3] = assign_386_stack_local (HImode, 2);
4387 if (memory_operand (operands[0], VOIDmode))
4388 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4389 operands[2], operands[3]));
4392 operands[4] = assign_386_stack_local (SImode, 0);
4393 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4394 operands[2], operands[3],
4399 [(set_attr "type" "fistp")
4400 (set_attr "i387_cw" "trunc")
4401 (set_attr "mode" "SI")])
4403 (define_insn "fix_truncsi_nomemory"
4404 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4405 (fix:SI (match_operand 1 "register_operand" "f,f")))
4406 (use (match_operand:HI 2 "memory_operand" "m,m"))
4407 (use (match_operand:HI 3 "memory_operand" "m,m"))
4408 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4409 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4410 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4412 [(set_attr "type" "fistp")
4413 (set_attr "i387_cw" "trunc")
4414 (set_attr "mode" "SI")])
4416 (define_insn "fix_truncsi_memory"
4417 [(set (match_operand:SI 0 "memory_operand" "=m")
4418 (fix:SI (match_operand 1 "register_operand" "f")))
4419 (use (match_operand:HI 2 "memory_operand" "m"))
4420 (use (match_operand:HI 3 "memory_operand" "m"))]
4421 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4422 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4423 "* return output_fix_trunc (insn, operands);"
4424 [(set_attr "type" "fistp")
4425 (set_attr "i387_cw" "trunc")
4426 (set_attr "mode" "SI")])
4428 ;; When SSE available, it is always faster to use it!
4429 (define_insn "fix_truncsfsi_sse"
4430 [(set (match_operand:SI 0 "register_operand" "=r,r")
4431 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4433 "cvttss2si\t{%1, %0|%0, %1}"
4434 [(set_attr "type" "sseicvt")
4435 (set_attr "mode" "DF")
4436 (set_attr "athlon_decode" "double,vector")])
4438 ;; Avoid vector decoded form of the instruction.
4440 [(match_scratch:SF 2 "x")
4441 (set (match_operand:SI 0 "register_operand" "")
4442 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4443 "TARGET_K8 && !optimize_size"
4444 [(set (match_dup 2) (match_dup 1))
4445 (set (match_dup 0) (fix:SI (match_dup 2)))]
4448 (define_insn "fix_truncdfsi_sse"
4449 [(set (match_operand:SI 0 "register_operand" "=r,r")
4450 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4452 "cvttsd2si\t{%1, %0|%0, %1}"
4453 [(set_attr "type" "sseicvt")
4454 (set_attr "mode" "DF")
4455 (set_attr "athlon_decode" "double,vector")])
4457 ;; Avoid vector decoded form of the instruction.
4459 [(match_scratch:DF 2 "Y")
4460 (set (match_operand:SI 0 "register_operand" "")
4461 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4462 "TARGET_K8 && !optimize_size"
4463 [(set (match_dup 2) (match_dup 1))
4464 (set (match_dup 0) (fix:SI (match_dup 2)))]
4468 [(set (match_operand:SI 0 "register_operand" "")
4469 (fix:SI (match_operand 1 "register_operand" "")))
4470 (use (match_operand:HI 2 "memory_operand" ""))
4471 (use (match_operand:HI 3 "memory_operand" ""))
4472 (clobber (match_operand:SI 4 "memory_operand" ""))]
4474 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4476 (use (match_dup 3))])
4477 (set (match_dup 0) (match_dup 4))]
4481 [(set (match_operand:SI 0 "memory_operand" "")
4482 (fix:SI (match_operand 1 "register_operand" "")))
4483 (use (match_operand:HI 2 "memory_operand" ""))
4484 (use (match_operand:HI 3 "memory_operand" ""))
4485 (clobber (match_operand:SI 4 "memory_operand" ""))]
4487 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4489 (use (match_dup 3))])]
4492 ;; Signed conversion to HImode.
4494 (define_expand "fix_truncxfhi2"
4495 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4496 (fix:HI (match_operand:XF 1 "register_operand" "")))
4497 (clobber (reg:CC FLAGS_REG))])]
4501 (define_expand "fix_truncdfhi2"
4502 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4503 (fix:HI (match_operand:DF 1 "register_operand" "")))
4504 (clobber (reg:CC FLAGS_REG))])]
4505 "TARGET_80387 && !TARGET_SSE2"
4508 (define_expand "fix_truncsfhi2"
4509 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4510 (fix:HI (match_operand:SF 1 "register_operand" "")))
4511 (clobber (reg:CC FLAGS_REG))])]
4512 "TARGET_80387 && !TARGET_SSE"
4515 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4516 ;; of the machinery.
4517 (define_insn_and_split "*fix_trunchi_i387"
4518 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4519 (fix:HI (match_operand 1 "register_operand" "f,f")))
4520 (clobber (reg:CC FLAGS_REG))]
4521 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4522 && !reload_completed && !reload_in_progress
4523 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4528 ix86_optimize_mode_switching = 1;
4529 operands[2] = assign_386_stack_local (HImode, 1);
4530 operands[3] = assign_386_stack_local (HImode, 2);
4531 if (memory_operand (operands[0], VOIDmode))
4532 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4533 operands[2], operands[3]));
4536 operands[4] = assign_386_stack_local (HImode, 0);
4537 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4538 operands[2], operands[3],
4543 [(set_attr "type" "fistp")
4544 (set_attr "i387_cw" "trunc")
4545 (set_attr "mode" "HI")])
4547 (define_insn "fix_trunchi_nomemory"
4548 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4549 (fix:HI (match_operand 1 "register_operand" "f,f")))
4550 (use (match_operand:HI 2 "memory_operand" "m,m"))
4551 (use (match_operand:HI 3 "memory_operand" "m,m"))
4552 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4553 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4554 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4556 [(set_attr "type" "fistp")
4557 (set_attr "i387_cw" "trunc")
4558 (set_attr "mode" "HI")])
4560 (define_insn "fix_trunchi_memory"
4561 [(set (match_operand:HI 0 "memory_operand" "=m")
4562 (fix:HI (match_operand 1 "register_operand" "f")))
4563 (use (match_operand:HI 2 "memory_operand" "m"))
4564 (use (match_operand:HI 3 "memory_operand" "m"))]
4565 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4566 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4567 "* return output_fix_trunc (insn, operands);"
4568 [(set_attr "type" "fistp")
4569 (set_attr "i387_cw" "trunc")
4570 (set_attr "mode" "HI")])
4573 [(set (match_operand:HI 0 "memory_operand" "")
4574 (fix:HI (match_operand 1 "register_operand" "")))
4575 (use (match_operand:HI 2 "memory_operand" ""))
4576 (use (match_operand:HI 3 "memory_operand" ""))
4577 (clobber (match_operand:HI 4 "memory_operand" ""))]
4579 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4581 (use (match_dup 3))])]
4585 [(set (match_operand:HI 0 "register_operand" "")
4586 (fix:HI (match_operand 1 "register_operand" "")))
4587 (use (match_operand:HI 2 "memory_operand" ""))
4588 (use (match_operand:HI 3 "memory_operand" ""))
4589 (clobber (match_operand:HI 4 "memory_operand" ""))]
4591 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4594 (clobber (match_dup 4))])
4595 (set (match_dup 0) (match_dup 4))]
4598 (define_insn "x86_fnstcw_1"
4599 [(set (match_operand:HI 0 "memory_operand" "=m")
4600 (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
4603 [(set_attr "length" "2")
4604 (set_attr "mode" "HI")
4605 (set_attr "unit" "i387")])
4607 (define_insn "x86_fldcw_1"
4608 [(set (reg:HI FPSR_REG)
4609 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4612 [(set_attr "length" "2")
4613 (set_attr "mode" "HI")
4614 (set_attr "unit" "i387")
4615 (set_attr "athlon_decode" "vector")])
4617 ;; Conversion between fixed point and floating point.
4619 ;; Even though we only accept memory inputs, the backend _really_
4620 ;; wants to be able to do this between registers.
4622 (define_expand "floathisf2"
4623 [(set (match_operand:SF 0 "register_operand" "")
4624 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4625 "TARGET_80387 || TARGET_SSE_MATH"
4627 if (TARGET_SSE_MATH)
4629 emit_insn (gen_floatsisf2 (operands[0],
4630 convert_to_mode (SImode, operands[1], 0)));
4635 (define_insn "*floathisf2_i387"
4636 [(set (match_operand:SF 0 "register_operand" "=f,f")
4637 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4638 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
4642 [(set_attr "type" "fmov,multi")
4643 (set_attr "mode" "SF")
4644 (set_attr "fp_int_src" "true")])
4646 (define_expand "floatsisf2"
4647 [(set (match_operand:SF 0 "register_operand" "")
4648 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4649 "TARGET_80387 || TARGET_SSE_MATH"
4652 (define_insn "*floatsisf2_mixed"
4653 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4654 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4655 "TARGET_MIX_SSE_I387"
4659 cvtsi2ss\t{%1, %0|%0, %1}
4660 cvtsi2ss\t{%1, %0|%0, %1}"
4661 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4662 (set_attr "mode" "SF")
4663 (set_attr "athlon_decode" "*,*,vector,double")
4664 (set_attr "fp_int_src" "true")])
4666 (define_insn "*floatsisf2_sse"
4667 [(set (match_operand:SF 0 "register_operand" "=x,x")
4668 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4670 "cvtsi2ss\t{%1, %0|%0, %1}"
4671 [(set_attr "type" "sseicvt")
4672 (set_attr "mode" "SF")
4673 (set_attr "athlon_decode" "vector,double")
4674 (set_attr "fp_int_src" "true")])
4676 (define_insn "*floatsisf2_i387"
4677 [(set (match_operand:SF 0 "register_operand" "=f,f")
4678 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4683 [(set_attr "type" "fmov,multi")
4684 (set_attr "mode" "SF")
4685 (set_attr "fp_int_src" "true")])
4687 (define_expand "floatdisf2"
4688 [(set (match_operand:SF 0 "register_operand" "")
4689 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4690 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
4693 (define_insn "*floatdisf2_mixed"
4694 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4695 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4696 "TARGET_64BIT && TARGET_MIX_SSE_I387"
4700 cvtsi2ss{q}\t{%1, %0|%0, %1}
4701 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4702 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4703 (set_attr "mode" "SF")
4704 (set_attr "athlon_decode" "*,*,vector,double")
4705 (set_attr "fp_int_src" "true")])
4707 (define_insn "*floatdisf2_sse"
4708 [(set (match_operand:SF 0 "register_operand" "=x,x")
4709 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4710 "TARGET_64BIT && TARGET_SSE_MATH"
4711 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4712 [(set_attr "type" "sseicvt")
4713 (set_attr "mode" "SF")
4714 (set_attr "athlon_decode" "vector,double")
4715 (set_attr "fp_int_src" "true")])
4717 (define_insn "*floatdisf2_i387"
4718 [(set (match_operand:SF 0 "register_operand" "=f,f")
4719 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4724 [(set_attr "type" "fmov,multi")
4725 (set_attr "mode" "SF")
4726 (set_attr "fp_int_src" "true")])
4728 (define_expand "floathidf2"
4729 [(set (match_operand:DF 0 "register_operand" "")
4730 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4731 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4733 if (TARGET_SSE2 && TARGET_SSE_MATH)
4735 emit_insn (gen_floatsidf2 (operands[0],
4736 convert_to_mode (SImode, operands[1], 0)));
4741 (define_insn "*floathidf2_i387"
4742 [(set (match_operand:DF 0 "register_operand" "=f,f")
4743 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4744 "TARGET_80387 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
4748 [(set_attr "type" "fmov,multi")
4749 (set_attr "mode" "DF")
4750 (set_attr "fp_int_src" "true")])
4752 (define_expand "floatsidf2"
4753 [(set (match_operand:DF 0 "register_operand" "")
4754 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4755 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4758 (define_insn "*floatsidf2_mixed"
4759 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4760 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4761 "TARGET_SSE2 && TARGET_MIX_SSE_I387"
4765 cvtsi2sd\t{%1, %0|%0, %1}
4766 cvtsi2sd\t{%1, %0|%0, %1}"
4767 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4768 (set_attr "mode" "DF")
4769 (set_attr "athlon_decode" "*,*,double,direct")
4770 (set_attr "fp_int_src" "true")])
4772 (define_insn "*floatsidf2_sse"
4773 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4774 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4775 "TARGET_SSE2 && TARGET_SSE_MATH"
4776 "cvtsi2sd\t{%1, %0|%0, %1}"
4777 [(set_attr "type" "sseicvt")
4778 (set_attr "mode" "DF")
4779 (set_attr "athlon_decode" "double,direct")
4780 (set_attr "fp_int_src" "true")])
4782 (define_insn "*floatsidf2_i387"
4783 [(set (match_operand:DF 0 "register_operand" "=f,f")
4784 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4789 [(set_attr "type" "fmov,multi")
4790 (set_attr "mode" "DF")
4791 (set_attr "fp_int_src" "true")])
4793 (define_expand "floatdidf2"
4794 [(set (match_operand:DF 0 "register_operand" "")
4795 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4796 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
4799 (define_insn "*floatdidf2_mixed"
4800 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4801 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4802 "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
4806 cvtsi2sd{q}\t{%1, %0|%0, %1}
4807 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4808 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4809 (set_attr "mode" "DF")
4810 (set_attr "athlon_decode" "*,*,double,direct")
4811 (set_attr "fp_int_src" "true")])
4813 (define_insn "*floatdidf2_sse"
4814 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4815 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4816 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
4817 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4818 [(set_attr "type" "sseicvt")
4819 (set_attr "mode" "DF")
4820 (set_attr "athlon_decode" "double,direct")
4821 (set_attr "fp_int_src" "true")])
4823 (define_insn "*floatdidf2_i387"
4824 [(set (match_operand:DF 0 "register_operand" "=f,f")
4825 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4830 [(set_attr "type" "fmov,multi")
4831 (set_attr "mode" "DF")
4832 (set_attr "fp_int_src" "true")])
4834 (define_insn "floathixf2"
4835 [(set (match_operand:XF 0 "register_operand" "=f,f")
4836 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4841 [(set_attr "type" "fmov,multi")
4842 (set_attr "mode" "XF")
4843 (set_attr "fp_int_src" "true")])
4845 (define_insn "floatsixf2"
4846 [(set (match_operand:XF 0 "register_operand" "=f,f")
4847 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4852 [(set_attr "type" "fmov,multi")
4853 (set_attr "mode" "XF")
4854 (set_attr "fp_int_src" "true")])
4856 (define_insn "floatdixf2"
4857 [(set (match_operand:XF 0 "register_operand" "=f,f")
4858 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4863 [(set_attr "type" "fmov,multi")
4864 (set_attr "mode" "XF")
4865 (set_attr "fp_int_src" "true")])
4867 ;; %%% Kill these when reload knows how to do it.
4869 [(set (match_operand 0 "fp_register_operand" "")
4870 (float (match_operand 1 "register_operand" "")))]
4873 && FLOAT_MODE_P (GET_MODE (operands[0]))"
4876 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4877 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4878 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4879 ix86_free_from_memory (GET_MODE (operands[1]));
4883 (define_expand "floatunssisf2"
4884 [(use (match_operand:SF 0 "register_operand" ""))
4885 (use (match_operand:SI 1 "register_operand" ""))]
4886 "!TARGET_64BIT && TARGET_SSE_MATH"
4887 "x86_emit_floatuns (operands); DONE;")
4889 (define_expand "floatunsdisf2"
4890 [(use (match_operand:SF 0 "register_operand" ""))
4891 (use (match_operand:DI 1 "register_operand" ""))]
4892 "TARGET_64BIT && TARGET_SSE_MATH"
4893 "x86_emit_floatuns (operands); DONE;")
4895 (define_expand "floatunsdidf2"
4896 [(use (match_operand:DF 0 "register_operand" ""))
4897 (use (match_operand:DI 1 "register_operand" ""))]
4898 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
4899 "x86_emit_floatuns (operands); DONE;")
4901 ;; SSE extract/set expanders
4906 ;; %%% splits for addsidi3
4907 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4908 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4909 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4911 (define_expand "adddi3"
4912 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4913 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4914 (match_operand:DI 2 "x86_64_general_operand" "")))
4915 (clobber (reg:CC FLAGS_REG))]
4917 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4919 (define_insn "*adddi3_1"
4920 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4921 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4922 (match_operand:DI 2 "general_operand" "roiF,riF")))
4923 (clobber (reg:CC FLAGS_REG))]
4924 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4928 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4929 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4930 (match_operand:DI 2 "general_operand" "")))
4931 (clobber (reg:CC FLAGS_REG))]
4932 "!TARGET_64BIT && reload_completed"
4933 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
4935 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4936 (parallel [(set (match_dup 3)
4937 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
4940 (clobber (reg:CC FLAGS_REG))])]
4941 "split_di (operands+0, 1, operands+0, operands+3);
4942 split_di (operands+1, 1, operands+1, operands+4);
4943 split_di (operands+2, 1, operands+2, operands+5);")
4945 (define_insn "adddi3_carry_rex64"
4946 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4947 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
4948 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4949 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4950 (clobber (reg:CC FLAGS_REG))]
4951 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4952 "adc{q}\t{%2, %0|%0, %2}"
4953 [(set_attr "type" "alu")
4954 (set_attr "pent_pair" "pu")
4955 (set_attr "mode" "DI")])
4957 (define_insn "*adddi3_cc_rex64"
4958 [(set (reg:CC FLAGS_REG)
4959 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4960 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4962 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4963 (plus:DI (match_dup 1) (match_dup 2)))]
4964 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4965 "add{q}\t{%2, %0|%0, %2}"
4966 [(set_attr "type" "alu")
4967 (set_attr "mode" "DI")])
4969 (define_insn "addqi3_carry"
4970 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4971 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
4972 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
4973 (match_operand:QI 2 "general_operand" "qi,qm")))
4974 (clobber (reg:CC FLAGS_REG))]
4975 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4976 "adc{b}\t{%2, %0|%0, %2}"
4977 [(set_attr "type" "alu")
4978 (set_attr "pent_pair" "pu")
4979 (set_attr "mode" "QI")])
4981 (define_insn "addhi3_carry"
4982 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4983 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
4984 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
4985 (match_operand:HI 2 "general_operand" "ri,rm")))
4986 (clobber (reg:CC FLAGS_REG))]
4987 "ix86_binary_operator_ok (PLUS, HImode, operands)"
4988 "adc{w}\t{%2, %0|%0, %2}"
4989 [(set_attr "type" "alu")
4990 (set_attr "pent_pair" "pu")
4991 (set_attr "mode" "HI")])
4993 (define_insn "addsi3_carry"
4994 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4995 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
4996 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
4997 (match_operand:SI 2 "general_operand" "ri,rm")))
4998 (clobber (reg:CC FLAGS_REG))]
4999 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5000 "adc{l}\t{%2, %0|%0, %2}"
5001 [(set_attr "type" "alu")
5002 (set_attr "pent_pair" "pu")
5003 (set_attr "mode" "SI")])
5005 (define_insn "*addsi3_carry_zext"
5006 [(set (match_operand:DI 0 "register_operand" "=r")
5008 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5009 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5010 (match_operand:SI 2 "general_operand" "rim"))))
5011 (clobber (reg:CC FLAGS_REG))]
5012 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5013 "adc{l}\t{%2, %k0|%k0, %2}"
5014 [(set_attr "type" "alu")
5015 (set_attr "pent_pair" "pu")
5016 (set_attr "mode" "SI")])
5018 (define_insn "*addsi3_cc"
5019 [(set (reg:CC FLAGS_REG)
5020 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5021 (match_operand:SI 2 "general_operand" "ri,rm")]
5023 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5024 (plus:SI (match_dup 1) (match_dup 2)))]
5025 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5026 "add{l}\t{%2, %0|%0, %2}"
5027 [(set_attr "type" "alu")
5028 (set_attr "mode" "SI")])
5030 (define_insn "addqi3_cc"
5031 [(set (reg:CC FLAGS_REG)
5032 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5033 (match_operand:QI 2 "general_operand" "qi,qm")]
5035 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5036 (plus:QI (match_dup 1) (match_dup 2)))]
5037 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5038 "add{b}\t{%2, %0|%0, %2}"
5039 [(set_attr "type" "alu")
5040 (set_attr "mode" "QI")])
5042 (define_expand "addsi3"
5043 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5044 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5045 (match_operand:SI 2 "general_operand" "")))
5046 (clobber (reg:CC FLAGS_REG))])]
5048 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5050 (define_insn "*lea_1"
5051 [(set (match_operand:SI 0 "register_operand" "=r")
5052 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5054 "lea{l}\t{%a1, %0|%0, %a1}"
5055 [(set_attr "type" "lea")
5056 (set_attr "mode" "SI")])
5058 (define_insn "*lea_1_rex64"
5059 [(set (match_operand:SI 0 "register_operand" "=r")
5060 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5062 "lea{l}\t{%a1, %0|%0, %a1}"
5063 [(set_attr "type" "lea")
5064 (set_attr "mode" "SI")])
5066 (define_insn "*lea_1_zext"
5067 [(set (match_operand:DI 0 "register_operand" "=r")
5069 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5071 "lea{l}\t{%a1, %k0|%k0, %a1}"
5072 [(set_attr "type" "lea")
5073 (set_attr "mode" "SI")])
5075 (define_insn "*lea_2_rex64"
5076 [(set (match_operand:DI 0 "register_operand" "=r")
5077 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5079 "lea{q}\t{%a1, %0|%0, %a1}"
5080 [(set_attr "type" "lea")
5081 (set_attr "mode" "DI")])
5083 ;; The lea patterns for non-Pmodes needs to be matched by several
5084 ;; insns converted to real lea by splitters.
5086 (define_insn_and_split "*lea_general_1"
5087 [(set (match_operand 0 "register_operand" "=r")
5088 (plus (plus (match_operand 1 "index_register_operand" "l")
5089 (match_operand 2 "register_operand" "r"))
5090 (match_operand 3 "immediate_operand" "i")))]
5091 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5092 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5093 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5094 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5095 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5096 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5097 || GET_MODE (operands[3]) == VOIDmode)"
5099 "&& reload_completed"
5103 operands[0] = gen_lowpart (SImode, operands[0]);
5104 operands[1] = gen_lowpart (Pmode, operands[1]);
5105 operands[2] = gen_lowpart (Pmode, operands[2]);
5106 operands[3] = gen_lowpart (Pmode, operands[3]);
5107 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5109 if (Pmode != SImode)
5110 pat = gen_rtx_SUBREG (SImode, pat, 0);
5111 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5114 [(set_attr "type" "lea")
5115 (set_attr "mode" "SI")])
5117 (define_insn_and_split "*lea_general_1_zext"
5118 [(set (match_operand:DI 0 "register_operand" "=r")
5120 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l")
5121 (match_operand:SI 2 "register_operand" "r"))
5122 (match_operand:SI 3 "immediate_operand" "i"))))]
5125 "&& reload_completed"
5127 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5129 (match_dup 3)) 0)))]
5131 operands[1] = gen_lowpart (Pmode, operands[1]);
5132 operands[2] = gen_lowpart (Pmode, operands[2]);
5133 operands[3] = gen_lowpart (Pmode, operands[3]);
5135 [(set_attr "type" "lea")
5136 (set_attr "mode" "SI")])
5138 (define_insn_and_split "*lea_general_2"
5139 [(set (match_operand 0 "register_operand" "=r")
5140 (plus (mult (match_operand 1 "index_register_operand" "l")
5141 (match_operand 2 "const248_operand" "i"))
5142 (match_operand 3 "nonmemory_operand" "ri")))]
5143 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5144 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5145 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5146 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5147 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5148 || GET_MODE (operands[3]) == VOIDmode)"
5150 "&& reload_completed"
5154 operands[0] = gen_lowpart (SImode, operands[0]);
5155 operands[1] = gen_lowpart (Pmode, operands[1]);
5156 operands[3] = gen_lowpart (Pmode, operands[3]);
5157 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5159 if (Pmode != SImode)
5160 pat = gen_rtx_SUBREG (SImode, pat, 0);
5161 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5164 [(set_attr "type" "lea")
5165 (set_attr "mode" "SI")])
5167 (define_insn_and_split "*lea_general_2_zext"
5168 [(set (match_operand:DI 0 "register_operand" "=r")
5170 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l")
5171 (match_operand:SI 2 "const248_operand" "n"))
5172 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5175 "&& reload_completed"
5177 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5179 (match_dup 3)) 0)))]
5181 operands[1] = gen_lowpart (Pmode, operands[1]);
5182 operands[3] = gen_lowpart (Pmode, operands[3]);
5184 [(set_attr "type" "lea")
5185 (set_attr "mode" "SI")])
5187 (define_insn_and_split "*lea_general_3"
5188 [(set (match_operand 0 "register_operand" "=r")
5189 (plus (plus (mult (match_operand 1 "index_register_operand" "l")
5190 (match_operand 2 "const248_operand" "i"))
5191 (match_operand 3 "register_operand" "r"))
5192 (match_operand 4 "immediate_operand" "i")))]
5193 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5194 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5195 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5196 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5197 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5199 "&& reload_completed"
5203 operands[0] = gen_lowpart (SImode, operands[0]);
5204 operands[1] = gen_lowpart (Pmode, operands[1]);
5205 operands[3] = gen_lowpart (Pmode, operands[3]);
5206 operands[4] = gen_lowpart (Pmode, operands[4]);
5207 pat = gen_rtx_PLUS (Pmode,
5208 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5212 if (Pmode != SImode)
5213 pat = gen_rtx_SUBREG (SImode, pat, 0);
5214 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5217 [(set_attr "type" "lea")
5218 (set_attr "mode" "SI")])
5220 (define_insn_and_split "*lea_general_3_zext"
5221 [(set (match_operand:DI 0 "register_operand" "=r")
5223 (plus:SI (plus:SI (mult:SI
5224 (match_operand:SI 1 "index_register_operand" "l")
5225 (match_operand:SI 2 "const248_operand" "n"))
5226 (match_operand:SI 3 "register_operand" "r"))
5227 (match_operand:SI 4 "immediate_operand" "i"))))]
5230 "&& reload_completed"
5232 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5235 (match_dup 4)) 0)))]
5237 operands[1] = gen_lowpart (Pmode, operands[1]);
5238 operands[3] = gen_lowpart (Pmode, operands[3]);
5239 operands[4] = gen_lowpart (Pmode, operands[4]);
5241 [(set_attr "type" "lea")
5242 (set_attr "mode" "SI")])
5244 (define_insn "*adddi_1_rex64"
5245 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5246 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5247 (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
5248 (clobber (reg:CC FLAGS_REG))]
5249 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5251 switch (get_attr_type (insn))
5254 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5255 return "lea{q}\t{%a2, %0|%0, %a2}";
5258 if (! rtx_equal_p (operands[0], operands[1]))
5260 if (operands[2] == const1_rtx)
5261 return "inc{q}\t%0";
5262 else if (operands[2] == constm1_rtx)
5263 return "dec{q}\t%0";
5268 if (! rtx_equal_p (operands[0], operands[1]))
5271 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5272 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5273 if (GET_CODE (operands[2]) == CONST_INT
5274 /* Avoid overflows. */
5275 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5276 && (INTVAL (operands[2]) == 128
5277 || (INTVAL (operands[2]) < 0
5278 && INTVAL (operands[2]) != -128)))
5280 operands[2] = GEN_INT (-INTVAL (operands[2]));
5281 return "sub{q}\t{%2, %0|%0, %2}";
5283 return "add{q}\t{%2, %0|%0, %2}";
5287 (cond [(eq_attr "alternative" "2")
5288 (const_string "lea")
5289 ; Current assemblers are broken and do not allow @GOTOFF in
5290 ; ought but a memory context.
5291 (match_operand:DI 2 "pic_symbolic_operand" "")
5292 (const_string "lea")
5293 (match_operand:DI 2 "incdec_operand" "")
5294 (const_string "incdec")
5296 (const_string "alu")))
5297 (set_attr "mode" "DI")])
5299 ;; Convert lea to the lea pattern to avoid flags dependency.
5301 [(set (match_operand:DI 0 "register_operand" "")
5302 (plus:DI (match_operand:DI 1 "register_operand" "")
5303 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5304 (clobber (reg:CC FLAGS_REG))]
5305 "TARGET_64BIT && reload_completed
5306 && true_regnum (operands[0]) != true_regnum (operands[1])"
5308 (plus:DI (match_dup 1)
5312 (define_insn "*adddi_2_rex64"
5313 [(set (reg FLAGS_REG)
5315 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5316 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5318 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5319 (plus:DI (match_dup 1) (match_dup 2)))]
5320 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5321 && ix86_binary_operator_ok (PLUS, DImode, operands)
5322 /* Current assemblers are broken and do not allow @GOTOFF in
5323 ought but a memory context. */
5324 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5326 switch (get_attr_type (insn))
5329 if (! rtx_equal_p (operands[0], operands[1]))
5331 if (operands[2] == const1_rtx)
5332 return "inc{q}\t%0";
5333 else if (operands[2] == constm1_rtx)
5334 return "dec{q}\t%0";
5339 if (! rtx_equal_p (operands[0], operands[1]))
5341 /* ???? We ought to handle there the 32bit case too
5342 - do we need new constraint? */
5343 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5344 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5345 if (GET_CODE (operands[2]) == CONST_INT
5346 /* Avoid overflows. */
5347 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5348 && (INTVAL (operands[2]) == 128
5349 || (INTVAL (operands[2]) < 0
5350 && INTVAL (operands[2]) != -128)))
5352 operands[2] = GEN_INT (-INTVAL (operands[2]));
5353 return "sub{q}\t{%2, %0|%0, %2}";
5355 return "add{q}\t{%2, %0|%0, %2}";
5359 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5360 (const_string "incdec")
5361 (const_string "alu")))
5362 (set_attr "mode" "DI")])
5364 (define_insn "*adddi_3_rex64"
5365 [(set (reg FLAGS_REG)
5366 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5367 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5368 (clobber (match_scratch:DI 0 "=r"))]
5370 && ix86_match_ccmode (insn, CCZmode)
5371 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5372 /* Current assemblers are broken and do not allow @GOTOFF in
5373 ought but a memory context. */
5374 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5376 switch (get_attr_type (insn))
5379 if (! rtx_equal_p (operands[0], operands[1]))
5381 if (operands[2] == const1_rtx)
5382 return "inc{q}\t%0";
5383 else if (operands[2] == constm1_rtx)
5384 return "dec{q}\t%0";
5389 if (! rtx_equal_p (operands[0], operands[1]))
5391 /* ???? We ought to handle there the 32bit case too
5392 - do we need new constraint? */
5393 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5394 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5395 if (GET_CODE (operands[2]) == CONST_INT
5396 /* Avoid overflows. */
5397 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5398 && (INTVAL (operands[2]) == 128
5399 || (INTVAL (operands[2]) < 0
5400 && INTVAL (operands[2]) != -128)))
5402 operands[2] = GEN_INT (-INTVAL (operands[2]));
5403 return "sub{q}\t{%2, %0|%0, %2}";
5405 return "add{q}\t{%2, %0|%0, %2}";
5409 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5410 (const_string "incdec")
5411 (const_string "alu")))
5412 (set_attr "mode" "DI")])
5414 ; For comparisons against 1, -1 and 128, we may generate better code
5415 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5416 ; is matched then. We can't accept general immediate, because for
5417 ; case of overflows, the result is messed up.
5418 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5420 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5421 ; only for comparisons not depending on it.
5422 (define_insn "*adddi_4_rex64"
5423 [(set (reg FLAGS_REG)
5424 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5425 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5426 (clobber (match_scratch:DI 0 "=rm"))]
5428 && ix86_match_ccmode (insn, CCGCmode)"
5430 switch (get_attr_type (insn))
5433 if (operands[2] == constm1_rtx)
5434 return "inc{q}\t%0";
5435 else if (operands[2] == const1_rtx)
5436 return "dec{q}\t%0";
5441 if (! rtx_equal_p (operands[0], operands[1]))
5443 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5444 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5445 if ((INTVAL (operands[2]) == -128
5446 || (INTVAL (operands[2]) > 0
5447 && INTVAL (operands[2]) != 128))
5448 /* Avoid overflows. */
5449 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5450 return "sub{q}\t{%2, %0|%0, %2}";
5451 operands[2] = GEN_INT (-INTVAL (operands[2]));
5452 return "add{q}\t{%2, %0|%0, %2}";
5456 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5457 (const_string "incdec")
5458 (const_string "alu")))
5459 (set_attr "mode" "DI")])
5461 (define_insn "*adddi_5_rex64"
5462 [(set (reg FLAGS_REG)
5464 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5465 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5467 (clobber (match_scratch:DI 0 "=r"))]
5469 && ix86_match_ccmode (insn, CCGOCmode)
5470 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5471 /* Current assemblers are broken and do not allow @GOTOFF in
5472 ought but a memory context. */
5473 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5475 switch (get_attr_type (insn))
5478 if (! rtx_equal_p (operands[0], operands[1]))
5480 if (operands[2] == const1_rtx)
5481 return "inc{q}\t%0";
5482 else if (operands[2] == constm1_rtx)
5483 return "dec{q}\t%0";
5488 if (! rtx_equal_p (operands[0], operands[1]))
5490 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5491 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5492 if (GET_CODE (operands[2]) == CONST_INT
5493 /* Avoid overflows. */
5494 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5495 && (INTVAL (operands[2]) == 128
5496 || (INTVAL (operands[2]) < 0
5497 && INTVAL (operands[2]) != -128)))
5499 operands[2] = GEN_INT (-INTVAL (operands[2]));
5500 return "sub{q}\t{%2, %0|%0, %2}";
5502 return "add{q}\t{%2, %0|%0, %2}";
5506 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5507 (const_string "incdec")
5508 (const_string "alu")))
5509 (set_attr "mode" "DI")])
5512 (define_insn "*addsi_1"
5513 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5514 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5515 (match_operand:SI 2 "general_operand" "rmni,rni,lni")))
5516 (clobber (reg:CC FLAGS_REG))]
5517 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5519 switch (get_attr_type (insn))
5522 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5523 return "lea{l}\t{%a2, %0|%0, %a2}";
5526 if (! rtx_equal_p (operands[0], operands[1]))
5528 if (operands[2] == const1_rtx)
5529 return "inc{l}\t%0";
5530 else if (operands[2] == constm1_rtx)
5531 return "dec{l}\t%0";
5536 if (! rtx_equal_p (operands[0], operands[1]))
5539 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5540 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5541 if (GET_CODE (operands[2]) == CONST_INT
5542 && (INTVAL (operands[2]) == 128
5543 || (INTVAL (operands[2]) < 0
5544 && INTVAL (operands[2]) != -128)))
5546 operands[2] = GEN_INT (-INTVAL (operands[2]));
5547 return "sub{l}\t{%2, %0|%0, %2}";
5549 return "add{l}\t{%2, %0|%0, %2}";
5553 (cond [(eq_attr "alternative" "2")
5554 (const_string "lea")
5555 ; Current assemblers are broken and do not allow @GOTOFF in
5556 ; ought but a memory context.
5557 (match_operand:SI 2 "pic_symbolic_operand" "")
5558 (const_string "lea")
5559 (match_operand:SI 2 "incdec_operand" "")
5560 (const_string "incdec")
5562 (const_string "alu")))
5563 (set_attr "mode" "SI")])
5565 ;; Convert lea to the lea pattern to avoid flags dependency.
5567 [(set (match_operand 0 "register_operand" "")
5568 (plus (match_operand 1 "register_operand" "")
5569 (match_operand 2 "nonmemory_operand" "")))
5570 (clobber (reg:CC FLAGS_REG))]
5572 && true_regnum (operands[0]) != true_regnum (operands[1])"
5576 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5577 may confuse gen_lowpart. */
5578 if (GET_MODE (operands[0]) != Pmode)
5580 operands[1] = gen_lowpart (Pmode, operands[1]);
5581 operands[2] = gen_lowpart (Pmode, operands[2]);
5583 operands[0] = gen_lowpart (SImode, operands[0]);
5584 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5585 if (Pmode != SImode)
5586 pat = gen_rtx_SUBREG (SImode, pat, 0);
5587 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5591 ;; It may seem that nonimmediate operand is proper one for operand 1.
5592 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5593 ;; we take care in ix86_binary_operator_ok to not allow two memory
5594 ;; operands so proper swapping will be done in reload. This allow
5595 ;; patterns constructed from addsi_1 to match.
5596 (define_insn "addsi_1_zext"
5597 [(set (match_operand:DI 0 "register_operand" "=r,r")
5599 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5600 (match_operand:SI 2 "general_operand" "rmni,lni"))))
5601 (clobber (reg:CC FLAGS_REG))]
5602 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5604 switch (get_attr_type (insn))
5607 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5608 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5611 if (operands[2] == const1_rtx)
5612 return "inc{l}\t%k0";
5613 else if (operands[2] == constm1_rtx)
5614 return "dec{l}\t%k0";
5619 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5620 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5621 if (GET_CODE (operands[2]) == CONST_INT
5622 && (INTVAL (operands[2]) == 128
5623 || (INTVAL (operands[2]) < 0
5624 && INTVAL (operands[2]) != -128)))
5626 operands[2] = GEN_INT (-INTVAL (operands[2]));
5627 return "sub{l}\t{%2, %k0|%k0, %2}";
5629 return "add{l}\t{%2, %k0|%k0, %2}";
5633 (cond [(eq_attr "alternative" "1")
5634 (const_string "lea")
5635 ; Current assemblers are broken and do not allow @GOTOFF in
5636 ; ought but a memory context.
5637 (match_operand:SI 2 "pic_symbolic_operand" "")
5638 (const_string "lea")
5639 (match_operand:SI 2 "incdec_operand" "")
5640 (const_string "incdec")
5642 (const_string "alu")))
5643 (set_attr "mode" "SI")])
5645 ;; Convert lea to the lea pattern to avoid flags dependency.
5647 [(set (match_operand:DI 0 "register_operand" "")
5649 (plus:SI (match_operand:SI 1 "register_operand" "")
5650 (match_operand:SI 2 "nonmemory_operand" ""))))
5651 (clobber (reg:CC FLAGS_REG))]
5652 "TARGET_64BIT && reload_completed
5653 && true_regnum (operands[0]) != true_regnum (operands[1])"
5655 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5657 operands[1] = gen_lowpart (Pmode, operands[1]);
5658 operands[2] = gen_lowpart (Pmode, operands[2]);
5661 (define_insn "*addsi_2"
5662 [(set (reg FLAGS_REG)
5664 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5665 (match_operand:SI 2 "general_operand" "rmni,rni"))
5667 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5668 (plus:SI (match_dup 1) (match_dup 2)))]
5669 "ix86_match_ccmode (insn, CCGOCmode)
5670 && ix86_binary_operator_ok (PLUS, SImode, operands)
5671 /* Current assemblers are broken and do not allow @GOTOFF in
5672 ought but a memory context. */
5673 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5675 switch (get_attr_type (insn))
5678 if (! rtx_equal_p (operands[0], operands[1]))
5680 if (operands[2] == const1_rtx)
5681 return "inc{l}\t%0";
5682 else if (operands[2] == constm1_rtx)
5683 return "dec{l}\t%0";
5688 if (! rtx_equal_p (operands[0], operands[1]))
5690 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5691 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5692 if (GET_CODE (operands[2]) == CONST_INT
5693 && (INTVAL (operands[2]) == 128
5694 || (INTVAL (operands[2]) < 0
5695 && INTVAL (operands[2]) != -128)))
5697 operands[2] = GEN_INT (-INTVAL (operands[2]));
5698 return "sub{l}\t{%2, %0|%0, %2}";
5700 return "add{l}\t{%2, %0|%0, %2}";
5704 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5705 (const_string "incdec")
5706 (const_string "alu")))
5707 (set_attr "mode" "SI")])
5709 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5710 (define_insn "*addsi_2_zext"
5711 [(set (reg FLAGS_REG)
5713 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5714 (match_operand:SI 2 "general_operand" "rmni"))
5716 (set (match_operand:DI 0 "register_operand" "=r")
5717 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5718 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5719 && ix86_binary_operator_ok (PLUS, SImode, operands)
5720 /* Current assemblers are broken and do not allow @GOTOFF in
5721 ought but a memory context. */
5722 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5724 switch (get_attr_type (insn))
5727 if (operands[2] == const1_rtx)
5728 return "inc{l}\t%k0";
5729 else if (operands[2] == constm1_rtx)
5730 return "dec{l}\t%k0";
5735 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5736 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5737 if (GET_CODE (operands[2]) == CONST_INT
5738 && (INTVAL (operands[2]) == 128
5739 || (INTVAL (operands[2]) < 0
5740 && INTVAL (operands[2]) != -128)))
5742 operands[2] = GEN_INT (-INTVAL (operands[2]));
5743 return "sub{l}\t{%2, %k0|%k0, %2}";
5745 return "add{l}\t{%2, %k0|%k0, %2}";
5749 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5750 (const_string "incdec")
5751 (const_string "alu")))
5752 (set_attr "mode" "SI")])
5754 (define_insn "*addsi_3"
5755 [(set (reg FLAGS_REG)
5756 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5757 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5758 (clobber (match_scratch:SI 0 "=r"))]
5759 "ix86_match_ccmode (insn, CCZmode)
5760 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5761 /* Current assemblers are broken and do not allow @GOTOFF in
5762 ought but a memory context. */
5763 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5765 switch (get_attr_type (insn))
5768 if (! rtx_equal_p (operands[0], operands[1]))
5770 if (operands[2] == const1_rtx)
5771 return "inc{l}\t%0";
5772 else if (operands[2] == constm1_rtx)
5773 return "dec{l}\t%0";
5778 if (! rtx_equal_p (operands[0], operands[1]))
5780 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5781 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5782 if (GET_CODE (operands[2]) == CONST_INT
5783 && (INTVAL (operands[2]) == 128
5784 || (INTVAL (operands[2]) < 0
5785 && INTVAL (operands[2]) != -128)))
5787 operands[2] = GEN_INT (-INTVAL (operands[2]));
5788 return "sub{l}\t{%2, %0|%0, %2}";
5790 return "add{l}\t{%2, %0|%0, %2}";
5794 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5795 (const_string "incdec")
5796 (const_string "alu")))
5797 (set_attr "mode" "SI")])
5799 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5800 (define_insn "*addsi_3_zext"
5801 [(set (reg FLAGS_REG)
5802 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5803 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5804 (set (match_operand:DI 0 "register_operand" "=r")
5805 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5806 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5807 && ix86_binary_operator_ok (PLUS, SImode, operands)
5808 /* Current assemblers are broken and do not allow @GOTOFF in
5809 ought but a memory context. */
5810 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5812 switch (get_attr_type (insn))
5815 if (operands[2] == const1_rtx)
5816 return "inc{l}\t%k0";
5817 else if (operands[2] == constm1_rtx)
5818 return "dec{l}\t%k0";
5823 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5824 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5825 if (GET_CODE (operands[2]) == CONST_INT
5826 && (INTVAL (operands[2]) == 128
5827 || (INTVAL (operands[2]) < 0
5828 && INTVAL (operands[2]) != -128)))
5830 operands[2] = GEN_INT (-INTVAL (operands[2]));
5831 return "sub{l}\t{%2, %k0|%k0, %2}";
5833 return "add{l}\t{%2, %k0|%k0, %2}";
5837 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5838 (const_string "incdec")
5839 (const_string "alu")))
5840 (set_attr "mode" "SI")])
5842 ; For comparisons against 1, -1 and 128, we may generate better code
5843 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5844 ; is matched then. We can't accept general immediate, because for
5845 ; case of overflows, the result is messed up.
5846 ; This pattern also don't hold of 0x80000000, since the value overflows
5848 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5849 ; only for comparisons not depending on it.
5850 (define_insn "*addsi_4"
5851 [(set (reg FLAGS_REG)
5852 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5853 (match_operand:SI 2 "const_int_operand" "n")))
5854 (clobber (match_scratch:SI 0 "=rm"))]
5855 "ix86_match_ccmode (insn, CCGCmode)
5856 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5858 switch (get_attr_type (insn))
5861 if (operands[2] == constm1_rtx)
5862 return "inc{l}\t%0";
5863 else if (operands[2] == const1_rtx)
5864 return "dec{l}\t%0";
5869 if (! rtx_equal_p (operands[0], operands[1]))
5871 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5872 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5873 if ((INTVAL (operands[2]) == -128
5874 || (INTVAL (operands[2]) > 0
5875 && INTVAL (operands[2]) != 128)))
5876 return "sub{l}\t{%2, %0|%0, %2}";
5877 operands[2] = GEN_INT (-INTVAL (operands[2]));
5878 return "add{l}\t{%2, %0|%0, %2}";
5882 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5883 (const_string "incdec")
5884 (const_string "alu")))
5885 (set_attr "mode" "SI")])
5887 (define_insn "*addsi_5"
5888 [(set (reg FLAGS_REG)
5890 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5891 (match_operand:SI 2 "general_operand" "rmni"))
5893 (clobber (match_scratch:SI 0 "=r"))]
5894 "ix86_match_ccmode (insn, CCGOCmode)
5895 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5896 /* Current assemblers are broken and do not allow @GOTOFF in
5897 ought but a memory context. */
5898 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5900 switch (get_attr_type (insn))
5903 if (! rtx_equal_p (operands[0], operands[1]))
5905 if (operands[2] == const1_rtx)
5906 return "inc{l}\t%0";
5907 else if (operands[2] == constm1_rtx)
5908 return "dec{l}\t%0";
5913 if (! rtx_equal_p (operands[0], operands[1]))
5915 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5916 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5917 if (GET_CODE (operands[2]) == CONST_INT
5918 && (INTVAL (operands[2]) == 128
5919 || (INTVAL (operands[2]) < 0
5920 && INTVAL (operands[2]) != -128)))
5922 operands[2] = GEN_INT (-INTVAL (operands[2]));
5923 return "sub{l}\t{%2, %0|%0, %2}";
5925 return "add{l}\t{%2, %0|%0, %2}";
5929 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5930 (const_string "incdec")
5931 (const_string "alu")))
5932 (set_attr "mode" "SI")])
5934 (define_expand "addhi3"
5935 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5936 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5937 (match_operand:HI 2 "general_operand" "")))
5938 (clobber (reg:CC FLAGS_REG))])]
5939 "TARGET_HIMODE_MATH"
5940 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5942 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5943 ;; type optimizations enabled by define-splits. This is not important
5944 ;; for PII, and in fact harmful because of partial register stalls.
5946 (define_insn "*addhi_1_lea"
5947 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5948 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5949 (match_operand:HI 2 "general_operand" "ri,rm,lni")))
5950 (clobber (reg:CC FLAGS_REG))]
5951 "!TARGET_PARTIAL_REG_STALL
5952 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5954 switch (get_attr_type (insn))
5959 if (operands[2] == const1_rtx)
5960 return "inc{w}\t%0";
5961 else if (operands[2] == constm1_rtx)
5962 return "dec{w}\t%0";
5966 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5967 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5968 if (GET_CODE (operands[2]) == CONST_INT
5969 && (INTVAL (operands[2]) == 128
5970 || (INTVAL (operands[2]) < 0
5971 && INTVAL (operands[2]) != -128)))
5973 operands[2] = GEN_INT (-INTVAL (operands[2]));
5974 return "sub{w}\t{%2, %0|%0, %2}";
5976 return "add{w}\t{%2, %0|%0, %2}";
5980 (if_then_else (eq_attr "alternative" "2")
5981 (const_string "lea")
5982 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5983 (const_string "incdec")
5984 (const_string "alu"))))
5985 (set_attr "mode" "HI,HI,SI")])
5987 (define_insn "*addhi_1"
5988 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5989 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5990 (match_operand:HI 2 "general_operand" "ri,rm")))
5991 (clobber (reg:CC FLAGS_REG))]
5992 "TARGET_PARTIAL_REG_STALL
5993 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5995 switch (get_attr_type (insn))
5998 if (operands[2] == const1_rtx)
5999 return "inc{w}\t%0";
6000 else if (operands[2] == constm1_rtx)
6001 return "dec{w}\t%0";
6005 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6006 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6007 if (GET_CODE (operands[2]) == CONST_INT
6008 && (INTVAL (operands[2]) == 128
6009 || (INTVAL (operands[2]) < 0
6010 && INTVAL (operands[2]) != -128)))
6012 operands[2] = GEN_INT (-INTVAL (operands[2]));
6013 return "sub{w}\t{%2, %0|%0, %2}";
6015 return "add{w}\t{%2, %0|%0, %2}";
6019 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6020 (const_string "incdec")
6021 (const_string "alu")))
6022 (set_attr "mode" "HI")])
6024 (define_insn "*addhi_2"
6025 [(set (reg FLAGS_REG)
6027 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6028 (match_operand:HI 2 "general_operand" "rmni,rni"))
6030 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6031 (plus:HI (match_dup 1) (match_dup 2)))]
6032 "ix86_match_ccmode (insn, CCGOCmode)
6033 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6035 switch (get_attr_type (insn))
6038 if (operands[2] == const1_rtx)
6039 return "inc{w}\t%0";
6040 else if (operands[2] == constm1_rtx)
6041 return "dec{w}\t%0";
6045 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6046 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6047 if (GET_CODE (operands[2]) == CONST_INT
6048 && (INTVAL (operands[2]) == 128
6049 || (INTVAL (operands[2]) < 0
6050 && INTVAL (operands[2]) != -128)))
6052 operands[2] = GEN_INT (-INTVAL (operands[2]));
6053 return "sub{w}\t{%2, %0|%0, %2}";
6055 return "add{w}\t{%2, %0|%0, %2}";
6059 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6060 (const_string "incdec")
6061 (const_string "alu")))
6062 (set_attr "mode" "HI")])
6064 (define_insn "*addhi_3"
6065 [(set (reg FLAGS_REG)
6066 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6067 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6068 (clobber (match_scratch:HI 0 "=r"))]
6069 "ix86_match_ccmode (insn, CCZmode)
6070 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6072 switch (get_attr_type (insn))
6075 if (operands[2] == const1_rtx)
6076 return "inc{w}\t%0";
6077 else if (operands[2] == constm1_rtx)
6078 return "dec{w}\t%0";
6082 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6083 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6084 if (GET_CODE (operands[2]) == CONST_INT
6085 && (INTVAL (operands[2]) == 128
6086 || (INTVAL (operands[2]) < 0
6087 && INTVAL (operands[2]) != -128)))
6089 operands[2] = GEN_INT (-INTVAL (operands[2]));
6090 return "sub{w}\t{%2, %0|%0, %2}";
6092 return "add{w}\t{%2, %0|%0, %2}";
6096 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6097 (const_string "incdec")
6098 (const_string "alu")))
6099 (set_attr "mode" "HI")])
6101 ; See comments above addsi_4 for details.
6102 (define_insn "*addhi_4"
6103 [(set (reg FLAGS_REG)
6104 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6105 (match_operand:HI 2 "const_int_operand" "n")))
6106 (clobber (match_scratch:HI 0 "=rm"))]
6107 "ix86_match_ccmode (insn, CCGCmode)
6108 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6110 switch (get_attr_type (insn))
6113 if (operands[2] == constm1_rtx)
6114 return "inc{w}\t%0";
6115 else if (operands[2] == const1_rtx)
6116 return "dec{w}\t%0";
6121 if (! rtx_equal_p (operands[0], operands[1]))
6123 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6124 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6125 if ((INTVAL (operands[2]) == -128
6126 || (INTVAL (operands[2]) > 0
6127 && INTVAL (operands[2]) != 128)))
6128 return "sub{w}\t{%2, %0|%0, %2}";
6129 operands[2] = GEN_INT (-INTVAL (operands[2]));
6130 return "add{w}\t{%2, %0|%0, %2}";
6134 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6135 (const_string "incdec")
6136 (const_string "alu")))
6137 (set_attr "mode" "SI")])
6140 (define_insn "*addhi_5"
6141 [(set (reg FLAGS_REG)
6143 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6144 (match_operand:HI 2 "general_operand" "rmni"))
6146 (clobber (match_scratch:HI 0 "=r"))]
6147 "ix86_match_ccmode (insn, CCGOCmode)
6148 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6150 switch (get_attr_type (insn))
6153 if (operands[2] == const1_rtx)
6154 return "inc{w}\t%0";
6155 else if (operands[2] == constm1_rtx)
6156 return "dec{w}\t%0";
6160 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6161 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6162 if (GET_CODE (operands[2]) == CONST_INT
6163 && (INTVAL (operands[2]) == 128
6164 || (INTVAL (operands[2]) < 0
6165 && INTVAL (operands[2]) != -128)))
6167 operands[2] = GEN_INT (-INTVAL (operands[2]));
6168 return "sub{w}\t{%2, %0|%0, %2}";
6170 return "add{w}\t{%2, %0|%0, %2}";
6174 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6175 (const_string "incdec")
6176 (const_string "alu")))
6177 (set_attr "mode" "HI")])
6179 (define_expand "addqi3"
6180 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6181 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6182 (match_operand:QI 2 "general_operand" "")))
6183 (clobber (reg:CC FLAGS_REG))])]
6184 "TARGET_QIMODE_MATH"
6185 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6187 ;; %%% Potential partial reg stall on alternative 2. What to do?
6188 (define_insn "*addqi_1_lea"
6189 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6190 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6191 (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
6192 (clobber (reg:CC FLAGS_REG))]
6193 "!TARGET_PARTIAL_REG_STALL
6194 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6196 int widen = (which_alternative == 2);
6197 switch (get_attr_type (insn))
6202 if (operands[2] == const1_rtx)
6203 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6204 else if (operands[2] == constm1_rtx)
6205 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6209 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6210 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6211 if (GET_CODE (operands[2]) == CONST_INT
6212 && (INTVAL (operands[2]) == 128
6213 || (INTVAL (operands[2]) < 0
6214 && INTVAL (operands[2]) != -128)))
6216 operands[2] = GEN_INT (-INTVAL (operands[2]));
6218 return "sub{l}\t{%2, %k0|%k0, %2}";
6220 return "sub{b}\t{%2, %0|%0, %2}";
6223 return "add{l}\t{%k2, %k0|%k0, %k2}";
6225 return "add{b}\t{%2, %0|%0, %2}";
6229 (if_then_else (eq_attr "alternative" "3")
6230 (const_string "lea")
6231 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6232 (const_string "incdec")
6233 (const_string "alu"))))
6234 (set_attr "mode" "QI,QI,SI,SI")])
6236 (define_insn "*addqi_1"
6237 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6238 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6239 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6240 (clobber (reg:CC FLAGS_REG))]
6241 "TARGET_PARTIAL_REG_STALL
6242 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6244 int widen = (which_alternative == 2);
6245 switch (get_attr_type (insn))
6248 if (operands[2] == const1_rtx)
6249 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6250 else if (operands[2] == constm1_rtx)
6251 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6255 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6256 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6257 if (GET_CODE (operands[2]) == CONST_INT
6258 && (INTVAL (operands[2]) == 128
6259 || (INTVAL (operands[2]) < 0
6260 && INTVAL (operands[2]) != -128)))
6262 operands[2] = GEN_INT (-INTVAL (operands[2]));
6264 return "sub{l}\t{%2, %k0|%k0, %2}";
6266 return "sub{b}\t{%2, %0|%0, %2}";
6269 return "add{l}\t{%k2, %k0|%k0, %k2}";
6271 return "add{b}\t{%2, %0|%0, %2}";
6275 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6276 (const_string "incdec")
6277 (const_string "alu")))
6278 (set_attr "mode" "QI,QI,SI")])
6280 (define_insn "*addqi_1_slp"
6281 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6282 (plus:QI (match_dup 0)
6283 (match_operand:QI 1 "general_operand" "qn,qnm")))
6284 (clobber (reg:CC FLAGS_REG))]
6285 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6286 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6288 switch (get_attr_type (insn))
6291 if (operands[1] == const1_rtx)
6292 return "inc{b}\t%0";
6293 else if (operands[1] == constm1_rtx)
6294 return "dec{b}\t%0";
6298 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6299 if (GET_CODE (operands[1]) == CONST_INT
6300 && INTVAL (operands[1]) < 0)
6302 operands[1] = GEN_INT (-INTVAL (operands[1]));
6303 return "sub{b}\t{%1, %0|%0, %1}";
6305 return "add{b}\t{%1, %0|%0, %1}";
6309 (if_then_else (match_operand:QI 1 "incdec_operand" "")
6310 (const_string "incdec")
6311 (const_string "alu1")))
6312 (set (attr "memory")
6313 (if_then_else (match_operand 1 "memory_operand" "")
6314 (const_string "load")
6315 (const_string "none")))
6316 (set_attr "mode" "QI")])
6318 (define_insn "*addqi_2"
6319 [(set (reg FLAGS_REG)
6321 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6322 (match_operand:QI 2 "general_operand" "qmni,qni"))
6324 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6325 (plus:QI (match_dup 1) (match_dup 2)))]
6326 "ix86_match_ccmode (insn, CCGOCmode)
6327 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6329 switch (get_attr_type (insn))
6332 if (operands[2] == const1_rtx)
6333 return "inc{b}\t%0";
6334 else if (operands[2] == constm1_rtx
6335 || (GET_CODE (operands[2]) == CONST_INT
6336 && INTVAL (operands[2]) == 255))
6337 return "dec{b}\t%0";
6341 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6342 if (GET_CODE (operands[2]) == CONST_INT
6343 && INTVAL (operands[2]) < 0)
6345 operands[2] = GEN_INT (-INTVAL (operands[2]));
6346 return "sub{b}\t{%2, %0|%0, %2}";
6348 return "add{b}\t{%2, %0|%0, %2}";
6352 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6353 (const_string "incdec")
6354 (const_string "alu")))
6355 (set_attr "mode" "QI")])
6357 (define_insn "*addqi_3"
6358 [(set (reg FLAGS_REG)
6359 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6360 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6361 (clobber (match_scratch:QI 0 "=q"))]
6362 "ix86_match_ccmode (insn, CCZmode)
6363 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6365 switch (get_attr_type (insn))
6368 if (operands[2] == const1_rtx)
6369 return "inc{b}\t%0";
6370 else if (operands[2] == constm1_rtx
6371 || (GET_CODE (operands[2]) == CONST_INT
6372 && INTVAL (operands[2]) == 255))
6373 return "dec{b}\t%0";
6377 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6378 if (GET_CODE (operands[2]) == CONST_INT
6379 && INTVAL (operands[2]) < 0)
6381 operands[2] = GEN_INT (-INTVAL (operands[2]));
6382 return "sub{b}\t{%2, %0|%0, %2}";
6384 return "add{b}\t{%2, %0|%0, %2}";
6388 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6389 (const_string "incdec")
6390 (const_string "alu")))
6391 (set_attr "mode" "QI")])
6393 ; See comments above addsi_4 for details.
6394 (define_insn "*addqi_4"
6395 [(set (reg FLAGS_REG)
6396 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6397 (match_operand:QI 2 "const_int_operand" "n")))
6398 (clobber (match_scratch:QI 0 "=qm"))]
6399 "ix86_match_ccmode (insn, CCGCmode)
6400 && (INTVAL (operands[2]) & 0xff) != 0x80"
6402 switch (get_attr_type (insn))
6405 if (operands[2] == constm1_rtx
6406 || (GET_CODE (operands[2]) == CONST_INT
6407 && INTVAL (operands[2]) == 255))
6408 return "inc{b}\t%0";
6409 else if (operands[2] == const1_rtx)
6410 return "dec{b}\t%0";
6415 if (! rtx_equal_p (operands[0], operands[1]))
6417 if (INTVAL (operands[2]) < 0)
6419 operands[2] = GEN_INT (-INTVAL (operands[2]));
6420 return "add{b}\t{%2, %0|%0, %2}";
6422 return "sub{b}\t{%2, %0|%0, %2}";
6426 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6427 (const_string "incdec")
6428 (const_string "alu")))
6429 (set_attr "mode" "QI")])
6432 (define_insn "*addqi_5"
6433 [(set (reg FLAGS_REG)
6435 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6436 (match_operand:QI 2 "general_operand" "qmni"))
6438 (clobber (match_scratch:QI 0 "=q"))]
6439 "ix86_match_ccmode (insn, CCGOCmode)
6440 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6442 switch (get_attr_type (insn))
6445 if (operands[2] == const1_rtx)
6446 return "inc{b}\t%0";
6447 else if (operands[2] == constm1_rtx
6448 || (GET_CODE (operands[2]) == CONST_INT
6449 && INTVAL (operands[2]) == 255))
6450 return "dec{b}\t%0";
6454 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6455 if (GET_CODE (operands[2]) == CONST_INT
6456 && INTVAL (operands[2]) < 0)
6458 operands[2] = GEN_INT (-INTVAL (operands[2]));
6459 return "sub{b}\t{%2, %0|%0, %2}";
6461 return "add{b}\t{%2, %0|%0, %2}";
6465 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6466 (const_string "incdec")
6467 (const_string "alu")))
6468 (set_attr "mode" "QI")])
6471 (define_insn "addqi_ext_1"
6472 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6477 (match_operand 1 "ext_register_operand" "0")
6480 (match_operand:QI 2 "general_operand" "Qmn")))
6481 (clobber (reg:CC FLAGS_REG))]
6484 switch (get_attr_type (insn))
6487 if (operands[2] == const1_rtx)
6488 return "inc{b}\t%h0";
6489 else if (operands[2] == constm1_rtx
6490 || (GET_CODE (operands[2]) == CONST_INT
6491 && INTVAL (operands[2]) == 255))
6492 return "dec{b}\t%h0";
6496 return "add{b}\t{%2, %h0|%h0, %2}";
6500 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6501 (const_string "incdec")
6502 (const_string "alu")))
6503 (set_attr "mode" "QI")])
6505 (define_insn "*addqi_ext_1_rex64"
6506 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6511 (match_operand 1 "ext_register_operand" "0")
6514 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6515 (clobber (reg:CC FLAGS_REG))]
6518 switch (get_attr_type (insn))
6521 if (operands[2] == const1_rtx)
6522 return "inc{b}\t%h0";
6523 else if (operands[2] == constm1_rtx
6524 || (GET_CODE (operands[2]) == CONST_INT
6525 && INTVAL (operands[2]) == 255))
6526 return "dec{b}\t%h0";
6530 return "add{b}\t{%2, %h0|%h0, %2}";
6534 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6535 (const_string "incdec")
6536 (const_string "alu")))
6537 (set_attr "mode" "QI")])
6539 (define_insn "*addqi_ext_2"
6540 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6545 (match_operand 1 "ext_register_operand" "%0")
6549 (match_operand 2 "ext_register_operand" "Q")
6552 (clobber (reg:CC FLAGS_REG))]
6554 "add{b}\t{%h2, %h0|%h0, %h2}"
6555 [(set_attr "type" "alu")
6556 (set_attr "mode" "QI")])
6558 ;; The patterns that match these are at the end of this file.
6560 (define_expand "addxf3"
6561 [(set (match_operand:XF 0 "register_operand" "")
6562 (plus:XF (match_operand:XF 1 "register_operand" "")
6563 (match_operand:XF 2 "register_operand" "")))]
6567 (define_expand "adddf3"
6568 [(set (match_operand:DF 0 "register_operand" "")
6569 (plus:DF (match_operand:DF 1 "register_operand" "")
6570 (match_operand:DF 2 "nonimmediate_operand" "")))]
6571 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6574 (define_expand "addsf3"
6575 [(set (match_operand:SF 0 "register_operand" "")
6576 (plus:SF (match_operand:SF 1 "register_operand" "")
6577 (match_operand:SF 2 "nonimmediate_operand" "")))]
6578 "TARGET_80387 || TARGET_SSE_MATH"
6581 ;; Subtract instructions
6583 ;; %%% splits for subsidi3
6585 (define_expand "subdi3"
6586 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6587 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6588 (match_operand:DI 2 "x86_64_general_operand" "")))
6589 (clobber (reg:CC FLAGS_REG))])]
6591 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6593 (define_insn "*subdi3_1"
6594 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6595 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6596 (match_operand:DI 2 "general_operand" "roiF,riF")))
6597 (clobber (reg:CC FLAGS_REG))]
6598 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6602 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6603 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6604 (match_operand:DI 2 "general_operand" "")))
6605 (clobber (reg:CC FLAGS_REG))]
6606 "!TARGET_64BIT && reload_completed"
6607 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
6608 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6609 (parallel [(set (match_dup 3)
6610 (minus:SI (match_dup 4)
6611 (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
6613 (clobber (reg:CC FLAGS_REG))])]
6614 "split_di (operands+0, 1, operands+0, operands+3);
6615 split_di (operands+1, 1, operands+1, operands+4);
6616 split_di (operands+2, 1, operands+2, operands+5);")
6618 (define_insn "subdi3_carry_rex64"
6619 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6620 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6621 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6622 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6623 (clobber (reg:CC FLAGS_REG))]
6624 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6625 "sbb{q}\t{%2, %0|%0, %2}"
6626 [(set_attr "type" "alu")
6627 (set_attr "pent_pair" "pu")
6628 (set_attr "mode" "DI")])
6630 (define_insn "*subdi_1_rex64"
6631 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6632 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6633 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6634 (clobber (reg:CC FLAGS_REG))]
6635 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6636 "sub{q}\t{%2, %0|%0, %2}"
6637 [(set_attr "type" "alu")
6638 (set_attr "mode" "DI")])
6640 (define_insn "*subdi_2_rex64"
6641 [(set (reg FLAGS_REG)
6643 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6644 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6646 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6647 (minus:DI (match_dup 1) (match_dup 2)))]
6648 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6649 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6650 "sub{q}\t{%2, %0|%0, %2}"
6651 [(set_attr "type" "alu")
6652 (set_attr "mode" "DI")])
6654 (define_insn "*subdi_3_rex63"
6655 [(set (reg FLAGS_REG)
6656 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6657 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6658 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6659 (minus:DI (match_dup 1) (match_dup 2)))]
6660 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6661 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6662 "sub{q}\t{%2, %0|%0, %2}"
6663 [(set_attr "type" "alu")
6664 (set_attr "mode" "DI")])
6666 (define_insn "subqi3_carry"
6667 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6668 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6669 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6670 (match_operand:QI 2 "general_operand" "qi,qm"))))
6671 (clobber (reg:CC FLAGS_REG))]
6672 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6673 "sbb{b}\t{%2, %0|%0, %2}"
6674 [(set_attr "type" "alu")
6675 (set_attr "pent_pair" "pu")
6676 (set_attr "mode" "QI")])
6678 (define_insn "subhi3_carry"
6679 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6680 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6681 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6682 (match_operand:HI 2 "general_operand" "ri,rm"))))
6683 (clobber (reg:CC FLAGS_REG))]
6684 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6685 "sbb{w}\t{%2, %0|%0, %2}"
6686 [(set_attr "type" "alu")
6687 (set_attr "pent_pair" "pu")
6688 (set_attr "mode" "HI")])
6690 (define_insn "subsi3_carry"
6691 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6692 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6693 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6694 (match_operand:SI 2 "general_operand" "ri,rm"))))
6695 (clobber (reg:CC FLAGS_REG))]
6696 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6697 "sbb{l}\t{%2, %0|%0, %2}"
6698 [(set_attr "type" "alu")
6699 (set_attr "pent_pair" "pu")
6700 (set_attr "mode" "SI")])
6702 (define_insn "subsi3_carry_zext"
6703 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6705 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6706 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6707 (match_operand:SI 2 "general_operand" "ri,rm")))))
6708 (clobber (reg:CC FLAGS_REG))]
6709 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6710 "sbb{l}\t{%2, %k0|%k0, %2}"
6711 [(set_attr "type" "alu")
6712 (set_attr "pent_pair" "pu")
6713 (set_attr "mode" "SI")])
6715 (define_expand "subsi3"
6716 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6717 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6718 (match_operand:SI 2 "general_operand" "")))
6719 (clobber (reg:CC FLAGS_REG))])]
6721 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6723 (define_insn "*subsi_1"
6724 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6725 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6726 (match_operand:SI 2 "general_operand" "ri,rm")))
6727 (clobber (reg:CC FLAGS_REG))]
6728 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6729 "sub{l}\t{%2, %0|%0, %2}"
6730 [(set_attr "type" "alu")
6731 (set_attr "mode" "SI")])
6733 (define_insn "*subsi_1_zext"
6734 [(set (match_operand:DI 0 "register_operand" "=r")
6736 (minus:SI (match_operand:SI 1 "register_operand" "0")
6737 (match_operand:SI 2 "general_operand" "rim"))))
6738 (clobber (reg:CC FLAGS_REG))]
6739 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6740 "sub{l}\t{%2, %k0|%k0, %2}"
6741 [(set_attr "type" "alu")
6742 (set_attr "mode" "SI")])
6744 (define_insn "*subsi_2"
6745 [(set (reg FLAGS_REG)
6747 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6748 (match_operand:SI 2 "general_operand" "ri,rm"))
6750 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6751 (minus:SI (match_dup 1) (match_dup 2)))]
6752 "ix86_match_ccmode (insn, CCGOCmode)
6753 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6754 "sub{l}\t{%2, %0|%0, %2}"
6755 [(set_attr "type" "alu")
6756 (set_attr "mode" "SI")])
6758 (define_insn "*subsi_2_zext"
6759 [(set (reg FLAGS_REG)
6761 (minus:SI (match_operand:SI 1 "register_operand" "0")
6762 (match_operand:SI 2 "general_operand" "rim"))
6764 (set (match_operand:DI 0 "register_operand" "=r")
6766 (minus:SI (match_dup 1)
6768 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6769 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6770 "sub{l}\t{%2, %k0|%k0, %2}"
6771 [(set_attr "type" "alu")
6772 (set_attr "mode" "SI")])
6774 (define_insn "*subsi_3"
6775 [(set (reg FLAGS_REG)
6776 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6777 (match_operand:SI 2 "general_operand" "ri,rm")))
6778 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6779 (minus:SI (match_dup 1) (match_dup 2)))]
6780 "ix86_match_ccmode (insn, CCmode)
6781 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6782 "sub{l}\t{%2, %0|%0, %2}"
6783 [(set_attr "type" "alu")
6784 (set_attr "mode" "SI")])
6786 (define_insn "*subsi_3_zext"
6787 [(set (reg FLAGS_REG)
6788 (compare (match_operand:SI 1 "register_operand" "0")
6789 (match_operand:SI 2 "general_operand" "rim")))
6790 (set (match_operand:DI 0 "register_operand" "=r")
6792 (minus:SI (match_dup 1)
6794 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6795 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6796 "sub{q}\t{%2, %0|%0, %2}"
6797 [(set_attr "type" "alu")
6798 (set_attr "mode" "DI")])
6800 (define_expand "subhi3"
6801 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6802 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6803 (match_operand:HI 2 "general_operand" "")))
6804 (clobber (reg:CC FLAGS_REG))])]
6805 "TARGET_HIMODE_MATH"
6806 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6808 (define_insn "*subhi_1"
6809 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6810 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6811 (match_operand:HI 2 "general_operand" "ri,rm")))
6812 (clobber (reg:CC FLAGS_REG))]
6813 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6814 "sub{w}\t{%2, %0|%0, %2}"
6815 [(set_attr "type" "alu")
6816 (set_attr "mode" "HI")])
6818 (define_insn "*subhi_2"
6819 [(set (reg FLAGS_REG)
6821 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6822 (match_operand:HI 2 "general_operand" "ri,rm"))
6824 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6825 (minus:HI (match_dup 1) (match_dup 2)))]
6826 "ix86_match_ccmode (insn, CCGOCmode)
6827 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6828 "sub{w}\t{%2, %0|%0, %2}"
6829 [(set_attr "type" "alu")
6830 (set_attr "mode" "HI")])
6832 (define_insn "*subhi_3"
6833 [(set (reg FLAGS_REG)
6834 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6835 (match_operand:HI 2 "general_operand" "ri,rm")))
6836 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6837 (minus:HI (match_dup 1) (match_dup 2)))]
6838 "ix86_match_ccmode (insn, CCmode)
6839 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6840 "sub{w}\t{%2, %0|%0, %2}"
6841 [(set_attr "type" "alu")
6842 (set_attr "mode" "HI")])
6844 (define_expand "subqi3"
6845 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6846 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6847 (match_operand:QI 2 "general_operand" "")))
6848 (clobber (reg:CC FLAGS_REG))])]
6849 "TARGET_QIMODE_MATH"
6850 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6852 (define_insn "*subqi_1"
6853 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6854 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6855 (match_operand:QI 2 "general_operand" "qn,qmn")))
6856 (clobber (reg:CC FLAGS_REG))]
6857 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6858 "sub{b}\t{%2, %0|%0, %2}"
6859 [(set_attr "type" "alu")
6860 (set_attr "mode" "QI")])
6862 (define_insn "*subqi_1_slp"
6863 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6864 (minus:QI (match_dup 0)
6865 (match_operand:QI 1 "general_operand" "qn,qmn")))
6866 (clobber (reg:CC FLAGS_REG))]
6867 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6868 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6869 "sub{b}\t{%1, %0|%0, %1}"
6870 [(set_attr "type" "alu1")
6871 (set_attr "mode" "QI")])
6873 (define_insn "*subqi_2"
6874 [(set (reg FLAGS_REG)
6876 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6877 (match_operand:QI 2 "general_operand" "qi,qm"))
6879 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6880 (minus:HI (match_dup 1) (match_dup 2)))]
6881 "ix86_match_ccmode (insn, CCGOCmode)
6882 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6883 "sub{b}\t{%2, %0|%0, %2}"
6884 [(set_attr "type" "alu")
6885 (set_attr "mode" "QI")])
6887 (define_insn "*subqi_3"
6888 [(set (reg FLAGS_REG)
6889 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6890 (match_operand:QI 2 "general_operand" "qi,qm")))
6891 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6892 (minus:HI (match_dup 1) (match_dup 2)))]
6893 "ix86_match_ccmode (insn, CCmode)
6894 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6895 "sub{b}\t{%2, %0|%0, %2}"
6896 [(set_attr "type" "alu")
6897 (set_attr "mode" "QI")])
6899 ;; The patterns that match these are at the end of this file.
6901 (define_expand "subxf3"
6902 [(set (match_operand:XF 0 "register_operand" "")
6903 (minus:XF (match_operand:XF 1 "register_operand" "")
6904 (match_operand:XF 2 "register_operand" "")))]
6908 (define_expand "subdf3"
6909 [(set (match_operand:DF 0 "register_operand" "")
6910 (minus:DF (match_operand:DF 1 "register_operand" "")
6911 (match_operand:DF 2 "nonimmediate_operand" "")))]
6912 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6915 (define_expand "subsf3"
6916 [(set (match_operand:SF 0 "register_operand" "")
6917 (minus:SF (match_operand:SF 1 "register_operand" "")
6918 (match_operand:SF 2 "nonimmediate_operand" "")))]
6919 "TARGET_80387 || TARGET_SSE_MATH"
6922 ;; Multiply instructions
6924 (define_expand "muldi3"
6925 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6926 (mult:DI (match_operand:DI 1 "register_operand" "")
6927 (match_operand:DI 2 "x86_64_general_operand" "")))
6928 (clobber (reg:CC FLAGS_REG))])]
6932 (define_insn "*muldi3_1_rex64"
6933 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6934 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6935 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6936 (clobber (reg:CC FLAGS_REG))]
6938 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6940 imul{q}\t{%2, %1, %0|%0, %1, %2}
6941 imul{q}\t{%2, %1, %0|%0, %1, %2}
6942 imul{q}\t{%2, %0|%0, %2}"
6943 [(set_attr "type" "imul")
6944 (set_attr "prefix_0f" "0,0,1")
6945 (set (attr "athlon_decode")
6946 (cond [(eq_attr "cpu" "athlon")
6947 (const_string "vector")
6948 (eq_attr "alternative" "1")
6949 (const_string "vector")
6950 (and (eq_attr "alternative" "2")
6951 (match_operand 1 "memory_operand" ""))
6952 (const_string "vector")]
6953 (const_string "direct")))
6954 (set_attr "mode" "DI")])
6956 (define_expand "mulsi3"
6957 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6958 (mult:SI (match_operand:SI 1 "register_operand" "")
6959 (match_operand:SI 2 "general_operand" "")))
6960 (clobber (reg:CC FLAGS_REG))])]
6964 (define_insn "*mulsi3_1"
6965 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6966 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6967 (match_operand:SI 2 "general_operand" "K,i,mr")))
6968 (clobber (reg:CC FLAGS_REG))]
6969 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6971 imul{l}\t{%2, %1, %0|%0, %1, %2}
6972 imul{l}\t{%2, %1, %0|%0, %1, %2}
6973 imul{l}\t{%2, %0|%0, %2}"
6974 [(set_attr "type" "imul")
6975 (set_attr "prefix_0f" "0,0,1")
6976 (set (attr "athlon_decode")
6977 (cond [(eq_attr "cpu" "athlon")
6978 (const_string "vector")
6979 (eq_attr "alternative" "1")
6980 (const_string "vector")
6981 (and (eq_attr "alternative" "2")
6982 (match_operand 1 "memory_operand" ""))
6983 (const_string "vector")]
6984 (const_string "direct")))
6985 (set_attr "mode" "SI")])
6987 (define_insn "*mulsi3_1_zext"
6988 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6990 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6991 (match_operand:SI 2 "general_operand" "K,i,mr"))))
6992 (clobber (reg:CC FLAGS_REG))]
6994 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6996 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6997 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6998 imul{l}\t{%2, %k0|%k0, %2}"
6999 [(set_attr "type" "imul")
7000 (set_attr "prefix_0f" "0,0,1")
7001 (set (attr "athlon_decode")
7002 (cond [(eq_attr "cpu" "athlon")
7003 (const_string "vector")
7004 (eq_attr "alternative" "1")
7005 (const_string "vector")
7006 (and (eq_attr "alternative" "2")
7007 (match_operand 1 "memory_operand" ""))
7008 (const_string "vector")]
7009 (const_string "direct")))
7010 (set_attr "mode" "SI")])
7012 (define_expand "mulhi3"
7013 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7014 (mult:HI (match_operand:HI 1 "register_operand" "")
7015 (match_operand:HI 2 "general_operand" "")))
7016 (clobber (reg:CC FLAGS_REG))])]
7017 "TARGET_HIMODE_MATH"
7020 (define_insn "*mulhi3_1"
7021 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7022 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7023 (match_operand:HI 2 "general_operand" "K,i,mr")))
7024 (clobber (reg:CC FLAGS_REG))]
7025 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7027 imul{w}\t{%2, %1, %0|%0, %1, %2}
7028 imul{w}\t{%2, %1, %0|%0, %1, %2}
7029 imul{w}\t{%2, %0|%0, %2}"
7030 [(set_attr "type" "imul")
7031 (set_attr "prefix_0f" "0,0,1")
7032 (set (attr "athlon_decode")
7033 (cond [(eq_attr "cpu" "athlon")
7034 (const_string "vector")
7035 (eq_attr "alternative" "1,2")
7036 (const_string "vector")]
7037 (const_string "direct")))
7038 (set_attr "mode" "HI")])
7040 (define_expand "mulqi3"
7041 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7042 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7043 (match_operand:QI 2 "register_operand" "")))
7044 (clobber (reg:CC FLAGS_REG))])]
7045 "TARGET_QIMODE_MATH"
7048 (define_insn "*mulqi3_1"
7049 [(set (match_operand:QI 0 "register_operand" "=a")
7050 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7051 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7052 (clobber (reg:CC FLAGS_REG))]
7054 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7056 [(set_attr "type" "imul")
7057 (set_attr "length_immediate" "0")
7058 (set (attr "athlon_decode")
7059 (if_then_else (eq_attr "cpu" "athlon")
7060 (const_string "vector")
7061 (const_string "direct")))
7062 (set_attr "mode" "QI")])
7064 (define_expand "umulqihi3"
7065 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7066 (mult:HI (zero_extend:HI
7067 (match_operand:QI 1 "nonimmediate_operand" ""))
7069 (match_operand:QI 2 "register_operand" ""))))
7070 (clobber (reg:CC FLAGS_REG))])]
7071 "TARGET_QIMODE_MATH"
7074 (define_insn "*umulqihi3_1"
7075 [(set (match_operand:HI 0 "register_operand" "=a")
7076 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7077 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7078 (clobber (reg:CC FLAGS_REG))]
7080 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7082 [(set_attr "type" "imul")
7083 (set_attr "length_immediate" "0")
7084 (set (attr "athlon_decode")
7085 (if_then_else (eq_attr "cpu" "athlon")
7086 (const_string "vector")
7087 (const_string "direct")))
7088 (set_attr "mode" "QI")])
7090 (define_expand "mulqihi3"
7091 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7092 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7093 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7094 (clobber (reg:CC FLAGS_REG))])]
7095 "TARGET_QIMODE_MATH"
7098 (define_insn "*mulqihi3_insn"
7099 [(set (match_operand:HI 0 "register_operand" "=a")
7100 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7101 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7102 (clobber (reg:CC FLAGS_REG))]
7104 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7106 [(set_attr "type" "imul")
7107 (set_attr "length_immediate" "0")
7108 (set (attr "athlon_decode")
7109 (if_then_else (eq_attr "cpu" "athlon")
7110 (const_string "vector")
7111 (const_string "direct")))
7112 (set_attr "mode" "QI")])
7114 (define_expand "umulditi3"
7115 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7116 (mult:TI (zero_extend:TI
7117 (match_operand:DI 1 "nonimmediate_operand" ""))
7119 (match_operand:DI 2 "register_operand" ""))))
7120 (clobber (reg:CC FLAGS_REG))])]
7124 (define_insn "*umulditi3_insn"
7125 [(set (match_operand:TI 0 "register_operand" "=A")
7126 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7127 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7128 (clobber (reg:CC FLAGS_REG))]
7130 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7132 [(set_attr "type" "imul")
7133 (set_attr "length_immediate" "0")
7134 (set (attr "athlon_decode")
7135 (if_then_else (eq_attr "cpu" "athlon")
7136 (const_string "vector")
7137 (const_string "double")))
7138 (set_attr "mode" "DI")])
7140 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7141 (define_expand "umulsidi3"
7142 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7143 (mult:DI (zero_extend:DI
7144 (match_operand:SI 1 "nonimmediate_operand" ""))
7146 (match_operand:SI 2 "register_operand" ""))))
7147 (clobber (reg:CC FLAGS_REG))])]
7151 (define_insn "*umulsidi3_insn"
7152 [(set (match_operand:DI 0 "register_operand" "=A")
7153 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7154 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7155 (clobber (reg:CC FLAGS_REG))]
7157 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7159 [(set_attr "type" "imul")
7160 (set_attr "length_immediate" "0")
7161 (set (attr "athlon_decode")
7162 (if_then_else (eq_attr "cpu" "athlon")
7163 (const_string "vector")
7164 (const_string "double")))
7165 (set_attr "mode" "SI")])
7167 (define_expand "mulditi3"
7168 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7169 (mult:TI (sign_extend:TI
7170 (match_operand:DI 1 "nonimmediate_operand" ""))
7172 (match_operand:DI 2 "register_operand" ""))))
7173 (clobber (reg:CC FLAGS_REG))])]
7177 (define_insn "*mulditi3_insn"
7178 [(set (match_operand:TI 0 "register_operand" "=A")
7179 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7180 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7181 (clobber (reg:CC FLAGS_REG))]
7183 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7185 [(set_attr "type" "imul")
7186 (set_attr "length_immediate" "0")
7187 (set (attr "athlon_decode")
7188 (if_then_else (eq_attr "cpu" "athlon")
7189 (const_string "vector")
7190 (const_string "double")))
7191 (set_attr "mode" "DI")])
7193 (define_expand "mulsidi3"
7194 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7195 (mult:DI (sign_extend:DI
7196 (match_operand:SI 1 "nonimmediate_operand" ""))
7198 (match_operand:SI 2 "register_operand" ""))))
7199 (clobber (reg:CC FLAGS_REG))])]
7203 (define_insn "*mulsidi3_insn"
7204 [(set (match_operand:DI 0 "register_operand" "=A")
7205 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7206 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7207 (clobber (reg:CC FLAGS_REG))]
7209 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7211 [(set_attr "type" "imul")
7212 (set_attr "length_immediate" "0")
7213 (set (attr "athlon_decode")
7214 (if_then_else (eq_attr "cpu" "athlon")
7215 (const_string "vector")
7216 (const_string "double")))
7217 (set_attr "mode" "SI")])
7219 (define_expand "umuldi3_highpart"
7220 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7223 (mult:TI (zero_extend:TI
7224 (match_operand:DI 1 "nonimmediate_operand" ""))
7226 (match_operand:DI 2 "register_operand" "")))
7228 (clobber (match_scratch:DI 3 ""))
7229 (clobber (reg:CC FLAGS_REG))])]
7233 (define_insn "*umuldi3_highpart_rex64"
7234 [(set (match_operand:DI 0 "register_operand" "=d")
7237 (mult:TI (zero_extend:TI
7238 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7240 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7242 (clobber (match_scratch:DI 3 "=1"))
7243 (clobber (reg:CC FLAGS_REG))]
7245 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7247 [(set_attr "type" "imul")
7248 (set_attr "length_immediate" "0")
7249 (set (attr "athlon_decode")
7250 (if_then_else (eq_attr "cpu" "athlon")
7251 (const_string "vector")
7252 (const_string "double")))
7253 (set_attr "mode" "DI")])
7255 (define_expand "umulsi3_highpart"
7256 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7259 (mult:DI (zero_extend:DI
7260 (match_operand:SI 1 "nonimmediate_operand" ""))
7262 (match_operand:SI 2 "register_operand" "")))
7264 (clobber (match_scratch:SI 3 ""))
7265 (clobber (reg:CC FLAGS_REG))])]
7269 (define_insn "*umulsi3_highpart_insn"
7270 [(set (match_operand:SI 0 "register_operand" "=d")
7273 (mult:DI (zero_extend:DI
7274 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7276 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7278 (clobber (match_scratch:SI 3 "=1"))
7279 (clobber (reg:CC FLAGS_REG))]
7280 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7282 [(set_attr "type" "imul")
7283 (set_attr "length_immediate" "0")
7284 (set (attr "athlon_decode")
7285 (if_then_else (eq_attr "cpu" "athlon")
7286 (const_string "vector")
7287 (const_string "double")))
7288 (set_attr "mode" "SI")])
7290 (define_insn "*umulsi3_highpart_zext"
7291 [(set (match_operand:DI 0 "register_operand" "=d")
7292 (zero_extend:DI (truncate:SI
7294 (mult:DI (zero_extend:DI
7295 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7297 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7299 (clobber (match_scratch:SI 3 "=1"))
7300 (clobber (reg:CC FLAGS_REG))]
7302 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7304 [(set_attr "type" "imul")
7305 (set_attr "length_immediate" "0")
7306 (set (attr "athlon_decode")
7307 (if_then_else (eq_attr "cpu" "athlon")
7308 (const_string "vector")
7309 (const_string "double")))
7310 (set_attr "mode" "SI")])
7312 (define_expand "smuldi3_highpart"
7313 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7316 (mult:TI (sign_extend:TI
7317 (match_operand:DI 1 "nonimmediate_operand" ""))
7319 (match_operand:DI 2 "register_operand" "")))
7321 (clobber (match_scratch:DI 3 ""))
7322 (clobber (reg:CC FLAGS_REG))])]
7326 (define_insn "*smuldi3_highpart_rex64"
7327 [(set (match_operand:DI 0 "register_operand" "=d")
7330 (mult:TI (sign_extend:TI
7331 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7333 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7335 (clobber (match_scratch:DI 3 "=1"))
7336 (clobber (reg:CC FLAGS_REG))]
7338 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7340 [(set_attr "type" "imul")
7341 (set (attr "athlon_decode")
7342 (if_then_else (eq_attr "cpu" "athlon")
7343 (const_string "vector")
7344 (const_string "double")))
7345 (set_attr "mode" "DI")])
7347 (define_expand "smulsi3_highpart"
7348 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7351 (mult:DI (sign_extend:DI
7352 (match_operand:SI 1 "nonimmediate_operand" ""))
7354 (match_operand:SI 2 "register_operand" "")))
7356 (clobber (match_scratch:SI 3 ""))
7357 (clobber (reg:CC FLAGS_REG))])]
7361 (define_insn "*smulsi3_highpart_insn"
7362 [(set (match_operand:SI 0 "register_operand" "=d")
7365 (mult:DI (sign_extend:DI
7366 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7368 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7370 (clobber (match_scratch:SI 3 "=1"))
7371 (clobber (reg:CC FLAGS_REG))]
7372 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7374 [(set_attr "type" "imul")
7375 (set (attr "athlon_decode")
7376 (if_then_else (eq_attr "cpu" "athlon")
7377 (const_string "vector")
7378 (const_string "double")))
7379 (set_attr "mode" "SI")])
7381 (define_insn "*smulsi3_highpart_zext"
7382 [(set (match_operand:DI 0 "register_operand" "=d")
7383 (zero_extend:DI (truncate:SI
7385 (mult:DI (sign_extend:DI
7386 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7388 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7390 (clobber (match_scratch:SI 3 "=1"))
7391 (clobber (reg:CC FLAGS_REG))]
7393 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7395 [(set_attr "type" "imul")
7396 (set (attr "athlon_decode")
7397 (if_then_else (eq_attr "cpu" "athlon")
7398 (const_string "vector")
7399 (const_string "double")))
7400 (set_attr "mode" "SI")])
7402 ;; The patterns that match these are at the end of this file.
7404 (define_expand "mulxf3"
7405 [(set (match_operand:XF 0 "register_operand" "")
7406 (mult:XF (match_operand:XF 1 "register_operand" "")
7407 (match_operand:XF 2 "register_operand" "")))]
7411 (define_expand "muldf3"
7412 [(set (match_operand:DF 0 "register_operand" "")
7413 (mult:DF (match_operand:DF 1 "register_operand" "")
7414 (match_operand:DF 2 "nonimmediate_operand" "")))]
7415 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7418 (define_expand "mulsf3"
7419 [(set (match_operand:SF 0 "register_operand" "")
7420 (mult:SF (match_operand:SF 1 "register_operand" "")
7421 (match_operand:SF 2 "nonimmediate_operand" "")))]
7422 "TARGET_80387 || TARGET_SSE_MATH"
7425 ;; Divide instructions
7427 (define_insn "divqi3"
7428 [(set (match_operand:QI 0 "register_operand" "=a")
7429 (div:QI (match_operand:HI 1 "register_operand" "0")
7430 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7431 (clobber (reg:CC FLAGS_REG))]
7432 "TARGET_QIMODE_MATH"
7434 [(set_attr "type" "idiv")
7435 (set_attr "mode" "QI")])
7437 (define_insn "udivqi3"
7438 [(set (match_operand:QI 0 "register_operand" "=a")
7439 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7440 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7441 (clobber (reg:CC FLAGS_REG))]
7442 "TARGET_QIMODE_MATH"
7444 [(set_attr "type" "idiv")
7445 (set_attr "mode" "QI")])
7447 ;; The patterns that match these are at the end of this file.
7449 (define_expand "divxf3"
7450 [(set (match_operand:XF 0 "register_operand" "")
7451 (div:XF (match_operand:XF 1 "register_operand" "")
7452 (match_operand:XF 2 "register_operand" "")))]
7456 (define_expand "divdf3"
7457 [(set (match_operand:DF 0 "register_operand" "")
7458 (div:DF (match_operand:DF 1 "register_operand" "")
7459 (match_operand:DF 2 "nonimmediate_operand" "")))]
7460 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7463 (define_expand "divsf3"
7464 [(set (match_operand:SF 0 "register_operand" "")
7465 (div:SF (match_operand:SF 1 "register_operand" "")
7466 (match_operand:SF 2 "nonimmediate_operand" "")))]
7467 "TARGET_80387 || TARGET_SSE_MATH"
7470 ;; Remainder instructions.
7472 (define_expand "divmoddi4"
7473 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7474 (div:DI (match_operand:DI 1 "register_operand" "")
7475 (match_operand:DI 2 "nonimmediate_operand" "")))
7476 (set (match_operand:DI 3 "register_operand" "")
7477 (mod:DI (match_dup 1) (match_dup 2)))
7478 (clobber (reg:CC FLAGS_REG))])]
7482 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7483 ;; Penalize eax case slightly because it results in worse scheduling
7485 (define_insn "*divmoddi4_nocltd_rex64"
7486 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7487 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7488 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7489 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7490 (mod:DI (match_dup 2) (match_dup 3)))
7491 (clobber (reg:CC FLAGS_REG))]
7492 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7494 [(set_attr "type" "multi")])
7496 (define_insn "*divmoddi4_cltd_rex64"
7497 [(set (match_operand:DI 0 "register_operand" "=a")
7498 (div:DI (match_operand:DI 2 "register_operand" "a")
7499 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7500 (set (match_operand:DI 1 "register_operand" "=&d")
7501 (mod:DI (match_dup 2) (match_dup 3)))
7502 (clobber (reg:CC FLAGS_REG))]
7503 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7505 [(set_attr "type" "multi")])
7507 (define_insn "*divmoddi_noext_rex64"
7508 [(set (match_operand:DI 0 "register_operand" "=a")
7509 (div:DI (match_operand:DI 1 "register_operand" "0")
7510 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7511 (set (match_operand:DI 3 "register_operand" "=d")
7512 (mod:DI (match_dup 1) (match_dup 2)))
7513 (use (match_operand:DI 4 "register_operand" "3"))
7514 (clobber (reg:CC FLAGS_REG))]
7517 [(set_attr "type" "idiv")
7518 (set_attr "mode" "DI")])
7521 [(set (match_operand:DI 0 "register_operand" "")
7522 (div:DI (match_operand:DI 1 "register_operand" "")
7523 (match_operand:DI 2 "nonimmediate_operand" "")))
7524 (set (match_operand:DI 3 "register_operand" "")
7525 (mod:DI (match_dup 1) (match_dup 2)))
7526 (clobber (reg:CC FLAGS_REG))]
7527 "TARGET_64BIT && reload_completed"
7528 [(parallel [(set (match_dup 3)
7529 (ashiftrt:DI (match_dup 4) (const_int 63)))
7530 (clobber (reg:CC FLAGS_REG))])
7531 (parallel [(set (match_dup 0)
7532 (div:DI (reg:DI 0) (match_dup 2)))
7534 (mod:DI (reg:DI 0) (match_dup 2)))
7536 (clobber (reg:CC FLAGS_REG))])]
7538 /* Avoid use of cltd in favor of a mov+shift. */
7539 if (!TARGET_USE_CLTD && !optimize_size)
7541 if (true_regnum (operands[1]))
7542 emit_move_insn (operands[0], operands[1]);
7544 emit_move_insn (operands[3], operands[1]);
7545 operands[4] = operands[3];
7549 if (true_regnum (operands[1]))
7551 operands[4] = operands[1];
7556 (define_expand "divmodsi4"
7557 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7558 (div:SI (match_operand:SI 1 "register_operand" "")
7559 (match_operand:SI 2 "nonimmediate_operand" "")))
7560 (set (match_operand:SI 3 "register_operand" "")
7561 (mod:SI (match_dup 1) (match_dup 2)))
7562 (clobber (reg:CC FLAGS_REG))])]
7566 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7567 ;; Penalize eax case slightly because it results in worse scheduling
7569 (define_insn "*divmodsi4_nocltd"
7570 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7571 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7572 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7573 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7574 (mod:SI (match_dup 2) (match_dup 3)))
7575 (clobber (reg:CC FLAGS_REG))]
7576 "!optimize_size && !TARGET_USE_CLTD"
7578 [(set_attr "type" "multi")])
7580 (define_insn "*divmodsi4_cltd"
7581 [(set (match_operand:SI 0 "register_operand" "=a")
7582 (div:SI (match_operand:SI 2 "register_operand" "a")
7583 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7584 (set (match_operand:SI 1 "register_operand" "=&d")
7585 (mod:SI (match_dup 2) (match_dup 3)))
7586 (clobber (reg:CC FLAGS_REG))]
7587 "optimize_size || TARGET_USE_CLTD"
7589 [(set_attr "type" "multi")])
7591 (define_insn "*divmodsi_noext"
7592 [(set (match_operand:SI 0 "register_operand" "=a")
7593 (div:SI (match_operand:SI 1 "register_operand" "0")
7594 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7595 (set (match_operand:SI 3 "register_operand" "=d")
7596 (mod:SI (match_dup 1) (match_dup 2)))
7597 (use (match_operand:SI 4 "register_operand" "3"))
7598 (clobber (reg:CC FLAGS_REG))]
7601 [(set_attr "type" "idiv")
7602 (set_attr "mode" "SI")])
7605 [(set (match_operand:SI 0 "register_operand" "")
7606 (div:SI (match_operand:SI 1 "register_operand" "")
7607 (match_operand:SI 2 "nonimmediate_operand" "")))
7608 (set (match_operand:SI 3 "register_operand" "")
7609 (mod:SI (match_dup 1) (match_dup 2)))
7610 (clobber (reg:CC FLAGS_REG))]
7612 [(parallel [(set (match_dup 3)
7613 (ashiftrt:SI (match_dup 4) (const_int 31)))
7614 (clobber (reg:CC FLAGS_REG))])
7615 (parallel [(set (match_dup 0)
7616 (div:SI (reg:SI 0) (match_dup 2)))
7618 (mod:SI (reg:SI 0) (match_dup 2)))
7620 (clobber (reg:CC FLAGS_REG))])]
7622 /* Avoid use of cltd in favor of a mov+shift. */
7623 if (!TARGET_USE_CLTD && !optimize_size)
7625 if (true_regnum (operands[1]))
7626 emit_move_insn (operands[0], operands[1]);
7628 emit_move_insn (operands[3], operands[1]);
7629 operands[4] = operands[3];
7633 if (true_regnum (operands[1]))
7635 operands[4] = operands[1];
7639 (define_insn "divmodhi4"
7640 [(set (match_operand:HI 0 "register_operand" "=a")
7641 (div:HI (match_operand:HI 1 "register_operand" "0")
7642 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7643 (set (match_operand:HI 3 "register_operand" "=&d")
7644 (mod:HI (match_dup 1) (match_dup 2)))
7645 (clobber (reg:CC FLAGS_REG))]
7646 "TARGET_HIMODE_MATH"
7648 [(set_attr "type" "multi")
7649 (set_attr "length_immediate" "0")
7650 (set_attr "mode" "SI")])
7652 (define_insn "udivmoddi4"
7653 [(set (match_operand:DI 0 "register_operand" "=a")
7654 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7655 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7656 (set (match_operand:DI 3 "register_operand" "=&d")
7657 (umod:DI (match_dup 1) (match_dup 2)))
7658 (clobber (reg:CC FLAGS_REG))]
7660 "xor{q}\t%3, %3\;div{q}\t%2"
7661 [(set_attr "type" "multi")
7662 (set_attr "length_immediate" "0")
7663 (set_attr "mode" "DI")])
7665 (define_insn "*udivmoddi4_noext"
7666 [(set (match_operand:DI 0 "register_operand" "=a")
7667 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7668 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7669 (set (match_operand:DI 3 "register_operand" "=d")
7670 (umod:DI (match_dup 1) (match_dup 2)))
7672 (clobber (reg:CC FLAGS_REG))]
7675 [(set_attr "type" "idiv")
7676 (set_attr "mode" "DI")])
7679 [(set (match_operand:DI 0 "register_operand" "")
7680 (udiv:DI (match_operand:DI 1 "register_operand" "")
7681 (match_operand:DI 2 "nonimmediate_operand" "")))
7682 (set (match_operand:DI 3 "register_operand" "")
7683 (umod:DI (match_dup 1) (match_dup 2)))
7684 (clobber (reg:CC FLAGS_REG))]
7685 "TARGET_64BIT && reload_completed"
7686 [(set (match_dup 3) (const_int 0))
7687 (parallel [(set (match_dup 0)
7688 (udiv:DI (match_dup 1) (match_dup 2)))
7690 (umod:DI (match_dup 1) (match_dup 2)))
7692 (clobber (reg:CC FLAGS_REG))])]
7695 (define_insn "udivmodsi4"
7696 [(set (match_operand:SI 0 "register_operand" "=a")
7697 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7698 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7699 (set (match_operand:SI 3 "register_operand" "=&d")
7700 (umod:SI (match_dup 1) (match_dup 2)))
7701 (clobber (reg:CC FLAGS_REG))]
7703 "xor{l}\t%3, %3\;div{l}\t%2"
7704 [(set_attr "type" "multi")
7705 (set_attr "length_immediate" "0")
7706 (set_attr "mode" "SI")])
7708 (define_insn "*udivmodsi4_noext"
7709 [(set (match_operand:SI 0 "register_operand" "=a")
7710 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7711 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7712 (set (match_operand:SI 3 "register_operand" "=d")
7713 (umod:SI (match_dup 1) (match_dup 2)))
7715 (clobber (reg:CC FLAGS_REG))]
7718 [(set_attr "type" "idiv")
7719 (set_attr "mode" "SI")])
7722 [(set (match_operand:SI 0 "register_operand" "")
7723 (udiv:SI (match_operand:SI 1 "register_operand" "")
7724 (match_operand:SI 2 "nonimmediate_operand" "")))
7725 (set (match_operand:SI 3 "register_operand" "")
7726 (umod:SI (match_dup 1) (match_dup 2)))
7727 (clobber (reg:CC FLAGS_REG))]
7729 [(set (match_dup 3) (const_int 0))
7730 (parallel [(set (match_dup 0)
7731 (udiv:SI (match_dup 1) (match_dup 2)))
7733 (umod:SI (match_dup 1) (match_dup 2)))
7735 (clobber (reg:CC FLAGS_REG))])]
7738 (define_expand "udivmodhi4"
7739 [(set (match_dup 4) (const_int 0))
7740 (parallel [(set (match_operand:HI 0 "register_operand" "")
7741 (udiv:HI (match_operand:HI 1 "register_operand" "")
7742 (match_operand:HI 2 "nonimmediate_operand" "")))
7743 (set (match_operand:HI 3 "register_operand" "")
7744 (umod:HI (match_dup 1) (match_dup 2)))
7746 (clobber (reg:CC FLAGS_REG))])]
7747 "TARGET_HIMODE_MATH"
7748 "operands[4] = gen_reg_rtx (HImode);")
7750 (define_insn "*udivmodhi_noext"
7751 [(set (match_operand:HI 0 "register_operand" "=a")
7752 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7753 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7754 (set (match_operand:HI 3 "register_operand" "=d")
7755 (umod:HI (match_dup 1) (match_dup 2)))
7756 (use (match_operand:HI 4 "register_operand" "3"))
7757 (clobber (reg:CC FLAGS_REG))]
7760 [(set_attr "type" "idiv")
7761 (set_attr "mode" "HI")])
7763 ;; We cannot use div/idiv for double division, because it causes
7764 ;; "division by zero" on the overflow and that's not what we expect
7765 ;; from truncate. Because true (non truncating) double division is
7766 ;; never generated, we can't create this insn anyway.
7769 ; [(set (match_operand:SI 0 "register_operand" "=a")
7771 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7773 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7774 ; (set (match_operand:SI 3 "register_operand" "=d")
7776 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7777 ; (clobber (reg:CC FLAGS_REG))]
7779 ; "div{l}\t{%2, %0|%0, %2}"
7780 ; [(set_attr "type" "idiv")])
7782 ;;- Logical AND instructions
7784 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7785 ;; Note that this excludes ah.
7787 (define_insn "*testdi_1_rex64"
7788 [(set (reg FLAGS_REG)
7790 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7791 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7793 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7794 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7796 test{l}\t{%k1, %k0|%k0, %k1}
7797 test{l}\t{%k1, %k0|%k0, %k1}
7798 test{q}\t{%1, %0|%0, %1}
7799 test{q}\t{%1, %0|%0, %1}
7800 test{q}\t{%1, %0|%0, %1}"
7801 [(set_attr "type" "test")
7802 (set_attr "modrm" "0,1,0,1,1")
7803 (set_attr "mode" "SI,SI,DI,DI,DI")
7804 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7806 (define_insn "testsi_1"
7807 [(set (reg FLAGS_REG)
7809 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
7810 (match_operand:SI 1 "general_operand" "in,in,rin"))
7812 "ix86_match_ccmode (insn, CCNOmode)
7813 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7814 "test{l}\t{%1, %0|%0, %1}"
7815 [(set_attr "type" "test")
7816 (set_attr "modrm" "0,1,1")
7817 (set_attr "mode" "SI")
7818 (set_attr "pent_pair" "uv,np,uv")])
7820 (define_expand "testsi_ccno_1"
7821 [(set (reg:CCNO FLAGS_REG)
7823 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7824 (match_operand:SI 1 "nonmemory_operand" ""))
7829 (define_insn "*testhi_1"
7830 [(set (reg FLAGS_REG)
7831 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
7832 (match_operand:HI 1 "general_operand" "n,n,rn"))
7834 "ix86_match_ccmode (insn, CCNOmode)
7835 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7836 "test{w}\t{%1, %0|%0, %1}"
7837 [(set_attr "type" "test")
7838 (set_attr "modrm" "0,1,1")
7839 (set_attr "mode" "HI")
7840 (set_attr "pent_pair" "uv,np,uv")])
7842 (define_expand "testqi_ccz_1"
7843 [(set (reg:CCZ FLAGS_REG)
7844 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7845 (match_operand:QI 1 "nonmemory_operand" ""))
7850 (define_insn "*testqi_1_maybe_si"
7851 [(set (reg FLAGS_REG)
7854 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7855 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7857 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7858 && ix86_match_ccmode (insn,
7859 GET_CODE (operands[1]) == CONST_INT
7860 && INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)"
7862 if (which_alternative == 3)
7864 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
7865 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7866 return "test{l}\t{%1, %k0|%k0, %1}";
7868 return "test{b}\t{%1, %0|%0, %1}";
7870 [(set_attr "type" "test")
7871 (set_attr "modrm" "0,1,1,1")
7872 (set_attr "mode" "QI,QI,QI,SI")
7873 (set_attr "pent_pair" "uv,np,uv,np")])
7875 (define_insn "*testqi_1"
7876 [(set (reg FLAGS_REG)
7879 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm")
7880 (match_operand:QI 1 "general_operand" "n,n,qn"))
7882 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7883 && ix86_match_ccmode (insn, CCNOmode)"
7884 "test{b}\t{%1, %0|%0, %1}"
7885 [(set_attr "type" "test")
7886 (set_attr "modrm" "0,1,1")
7887 (set_attr "mode" "QI")
7888 (set_attr "pent_pair" "uv,np,uv")])
7890 (define_expand "testqi_ext_ccno_0"
7891 [(set (reg:CCNO FLAGS_REG)
7895 (match_operand 0 "ext_register_operand" "")
7898 (match_operand 1 "const_int_operand" ""))
7903 (define_insn "*testqi_ext_0"
7904 [(set (reg FLAGS_REG)
7908 (match_operand 0 "ext_register_operand" "Q")
7911 (match_operand 1 "const_int_operand" "n"))
7913 "ix86_match_ccmode (insn, CCNOmode)"
7914 "test{b}\t{%1, %h0|%h0, %1}"
7915 [(set_attr "type" "test")
7916 (set_attr "mode" "QI")
7917 (set_attr "length_immediate" "1")
7918 (set_attr "pent_pair" "np")])
7920 (define_insn "*testqi_ext_1"
7921 [(set (reg FLAGS_REG)
7925 (match_operand 0 "ext_register_operand" "Q")
7929 (match_operand:QI 1 "general_operand" "Qm")))
7931 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7932 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7933 "test{b}\t{%1, %h0|%h0, %1}"
7934 [(set_attr "type" "test")
7935 (set_attr "mode" "QI")])
7937 (define_insn "*testqi_ext_1_rex64"
7938 [(set (reg FLAGS_REG)
7942 (match_operand 0 "ext_register_operand" "Q")
7946 (match_operand:QI 1 "register_operand" "Q")))
7948 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7949 "test{b}\t{%1, %h0|%h0, %1}"
7950 [(set_attr "type" "test")
7951 (set_attr "mode" "QI")])
7953 (define_insn "*testqi_ext_2"
7954 [(set (reg FLAGS_REG)
7958 (match_operand 0 "ext_register_operand" "Q")
7962 (match_operand 1 "ext_register_operand" "Q")
7966 "ix86_match_ccmode (insn, CCNOmode)"
7967 "test{b}\t{%h1, %h0|%h0, %h1}"
7968 [(set_attr "type" "test")
7969 (set_attr "mode" "QI")])
7971 ;; Combine likes to form bit extractions for some tests. Humor it.
7972 (define_insn "*testqi_ext_3"
7973 [(set (reg FLAGS_REG)
7974 (compare (zero_extract:SI
7975 (match_operand 0 "nonimmediate_operand" "rm")
7976 (match_operand:SI 1 "const_int_operand" "")
7977 (match_operand:SI 2 "const_int_operand" ""))
7979 "ix86_match_ccmode (insn, CCNOmode)
7980 && (GET_MODE (operands[0]) == SImode
7981 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7982 || GET_MODE (operands[0]) == HImode
7983 || GET_MODE (operands[0]) == QImode)"
7986 (define_insn "*testqi_ext_3_rex64"
7987 [(set (reg FLAGS_REG)
7988 (compare (zero_extract:DI
7989 (match_operand 0 "nonimmediate_operand" "rm")
7990 (match_operand:DI 1 "const_int_operand" "")
7991 (match_operand:DI 2 "const_int_operand" ""))
7994 && ix86_match_ccmode (insn, CCNOmode)
7995 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
7996 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
7997 /* Ensure that resulting mask is zero or sign extended operand. */
7998 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7999 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8000 && INTVAL (operands[1]) > 32))
8001 && (GET_MODE (operands[0]) == SImode
8002 || GET_MODE (operands[0]) == DImode
8003 || GET_MODE (operands[0]) == HImode
8004 || GET_MODE (operands[0]) == QImode)"
8008 [(set (match_operand 0 "flags_reg_operand" "")
8009 (match_operator 1 "compare_operator"
8011 (match_operand 2 "nonimmediate_operand" "")
8012 (match_operand 3 "const_int_operand" "")
8013 (match_operand 4 "const_int_operand" ""))
8015 "ix86_match_ccmode (insn, CCNOmode)"
8016 [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
8018 rtx val = operands[2];
8019 HOST_WIDE_INT len = INTVAL (operands[3]);
8020 HOST_WIDE_INT pos = INTVAL (operands[4]);
8022 enum machine_mode mode, submode;
8024 mode = GET_MODE (val);
8025 if (GET_CODE (val) == MEM)
8027 /* ??? Combine likes to put non-volatile mem extractions in QImode
8028 no matter the size of the test. So find a mode that works. */
8029 if (! MEM_VOLATILE_P (val))
8031 mode = smallest_mode_for_size (pos + len, MODE_INT);
8032 val = adjust_address (val, mode, 0);
8035 else if (GET_CODE (val) == SUBREG
8036 && (submode = GET_MODE (SUBREG_REG (val)),
8037 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8038 && pos + len <= GET_MODE_BITSIZE (submode))
8040 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8042 val = SUBREG_REG (val);
8044 else if (mode == HImode && pos + len <= 8)
8046 /* Small HImode tests can be converted to QImode. */
8048 val = gen_lowpart (QImode, val);
8051 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8052 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8054 operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
8057 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8058 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8059 ;; this is relatively important trick.
8060 ;; Do the conversion only post-reload to avoid limiting of the register class
8063 [(set (match_operand 0 "flags_reg_operand" "")
8064 (match_operator 1 "compare_operator"
8065 [(and (match_operand 2 "register_operand" "")
8066 (match_operand 3 "const_int_operand" ""))
8069 && QI_REG_P (operands[2])
8070 && GET_MODE (operands[2]) != QImode
8071 && ((ix86_match_ccmode (insn, CCZmode)
8072 && !(INTVAL (operands[3]) & ~(255 << 8)))
8073 || (ix86_match_ccmode (insn, CCNOmode)
8074 && !(INTVAL (operands[3]) & ~(127 << 8))))"
8077 [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
8080 "operands[2] = gen_lowpart (SImode, operands[2]);
8081 operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
8084 [(set (match_operand 0 "flags_reg_operand" "")
8085 (match_operator 1 "compare_operator"
8086 [(and (match_operand 2 "nonimmediate_operand" "")
8087 (match_operand 3 "const_int_operand" ""))
8090 && GET_MODE (operands[2]) != QImode
8091 && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2]))
8092 && ((ix86_match_ccmode (insn, CCZmode)
8093 && !(INTVAL (operands[3]) & ~255))
8094 || (ix86_match_ccmode (insn, CCNOmode)
8095 && !(INTVAL (operands[3]) & ~127)))"
8097 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
8099 "operands[2] = gen_lowpart (QImode, operands[2]);
8100 operands[3] = gen_lowpart (QImode, operands[3]);")
8103 ;; %%% This used to optimize known byte-wide and operations to memory,
8104 ;; and sometimes to QImode registers. If this is considered useful,
8105 ;; it should be done with splitters.
8107 (define_expand "anddi3"
8108 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8109 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8110 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8111 (clobber (reg:CC FLAGS_REG))]
8113 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8115 (define_insn "*anddi_1_rex64"
8116 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8117 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8118 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8119 (clobber (reg:CC FLAGS_REG))]
8120 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8122 switch (get_attr_type (insn))
8126 enum machine_mode mode;
8128 if (GET_CODE (operands[2]) != CONST_INT)
8130 if (INTVAL (operands[2]) == 0xff)
8132 else if (INTVAL (operands[2]) == 0xffff)
8137 operands[1] = gen_lowpart (mode, operands[1]);
8139 return "movz{bq|x}\t{%1,%0|%0, %1}";
8141 return "movz{wq|x}\t{%1,%0|%0, %1}";
8145 if (! rtx_equal_p (operands[0], operands[1]))
8147 if (get_attr_mode (insn) == MODE_SI)
8148 return "and{l}\t{%k2, %k0|%k0, %k2}";
8150 return "and{q}\t{%2, %0|%0, %2}";
8153 [(set_attr "type" "alu,alu,alu,imovx")
8154 (set_attr "length_immediate" "*,*,*,0")
8155 (set_attr "mode" "SI,DI,DI,DI")])
8157 (define_insn "*anddi_2"
8158 [(set (reg FLAGS_REG)
8159 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8160 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8162 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8163 (and:DI (match_dup 1) (match_dup 2)))]
8164 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8165 && ix86_binary_operator_ok (AND, DImode, operands)"
8167 and{l}\t{%k2, %k0|%k0, %k2}
8168 and{q}\t{%2, %0|%0, %2}
8169 and{q}\t{%2, %0|%0, %2}"
8170 [(set_attr "type" "alu")
8171 (set_attr "mode" "SI,DI,DI")])
8173 (define_expand "andsi3"
8174 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8175 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8176 (match_operand:SI 2 "general_operand" "")))
8177 (clobber (reg:CC FLAGS_REG))]
8179 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8181 (define_insn "*andsi_1"
8182 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8183 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8184 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8185 (clobber (reg:CC FLAGS_REG))]
8186 "ix86_binary_operator_ok (AND, SImode, operands)"
8188 switch (get_attr_type (insn))
8192 enum machine_mode mode;
8194 if (GET_CODE (operands[2]) != CONST_INT)
8196 if (INTVAL (operands[2]) == 0xff)
8198 else if (INTVAL (operands[2]) == 0xffff)
8203 operands[1] = gen_lowpart (mode, operands[1]);
8205 return "movz{bl|x}\t{%1,%0|%0, %1}";
8207 return "movz{wl|x}\t{%1,%0|%0, %1}";
8211 if (! rtx_equal_p (operands[0], operands[1]))
8213 return "and{l}\t{%2, %0|%0, %2}";
8216 [(set_attr "type" "alu,alu,imovx")
8217 (set_attr "length_immediate" "*,*,0")
8218 (set_attr "mode" "SI")])
8221 [(set (match_operand 0 "register_operand" "")
8223 (const_int -65536)))
8224 (clobber (reg:CC FLAGS_REG))]
8225 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8226 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8227 "operands[1] = gen_lowpart (HImode, operands[0]);")
8230 [(set (match_operand 0 "ext_register_operand" "")
8233 (clobber (reg:CC FLAGS_REG))]
8234 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8235 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8236 "operands[1] = gen_lowpart (QImode, operands[0]);")
8239 [(set (match_operand 0 "ext_register_operand" "")
8241 (const_int -65281)))
8242 (clobber (reg:CC FLAGS_REG))]
8243 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8244 [(parallel [(set (zero_extract:SI (match_dup 0)
8248 (zero_extract:SI (match_dup 0)
8251 (zero_extract:SI (match_dup 0)
8254 (clobber (reg:CC FLAGS_REG))])]
8255 "operands[0] = gen_lowpart (SImode, operands[0]);")
8257 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8258 (define_insn "*andsi_1_zext"
8259 [(set (match_operand:DI 0 "register_operand" "=r")
8261 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8262 (match_operand:SI 2 "general_operand" "rim"))))
8263 (clobber (reg:CC FLAGS_REG))]
8264 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8265 "and{l}\t{%2, %k0|%k0, %2}"
8266 [(set_attr "type" "alu")
8267 (set_attr "mode" "SI")])
8269 (define_insn "*andsi_2"
8270 [(set (reg FLAGS_REG)
8271 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8272 (match_operand:SI 2 "general_operand" "rim,ri"))
8274 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8275 (and:SI (match_dup 1) (match_dup 2)))]
8276 "ix86_match_ccmode (insn, CCNOmode)
8277 && ix86_binary_operator_ok (AND, SImode, operands)"
8278 "and{l}\t{%2, %0|%0, %2}"
8279 [(set_attr "type" "alu")
8280 (set_attr "mode" "SI")])
8282 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8283 (define_insn "*andsi_2_zext"
8284 [(set (reg FLAGS_REG)
8285 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8286 (match_operand:SI 2 "general_operand" "rim"))
8288 (set (match_operand:DI 0 "register_operand" "=r")
8289 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8290 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8291 && ix86_binary_operator_ok (AND, SImode, operands)"
8292 "and{l}\t{%2, %k0|%k0, %2}"
8293 [(set_attr "type" "alu")
8294 (set_attr "mode" "SI")])
8296 (define_expand "andhi3"
8297 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8298 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8299 (match_operand:HI 2 "general_operand" "")))
8300 (clobber (reg:CC FLAGS_REG))]
8301 "TARGET_HIMODE_MATH"
8302 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8304 (define_insn "*andhi_1"
8305 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8306 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8307 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8308 (clobber (reg:CC FLAGS_REG))]
8309 "ix86_binary_operator_ok (AND, HImode, operands)"
8311 switch (get_attr_type (insn))
8314 if (GET_CODE (operands[2]) != CONST_INT)
8316 if (INTVAL (operands[2]) == 0xff)
8317 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8321 if (! rtx_equal_p (operands[0], operands[1]))
8324 return "and{w}\t{%2, %0|%0, %2}";
8327 [(set_attr "type" "alu,alu,imovx")
8328 (set_attr "length_immediate" "*,*,0")
8329 (set_attr "mode" "HI,HI,SI")])
8331 (define_insn "*andhi_2"
8332 [(set (reg FLAGS_REG)
8333 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8334 (match_operand:HI 2 "general_operand" "rim,ri"))
8336 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8337 (and:HI (match_dup 1) (match_dup 2)))]
8338 "ix86_match_ccmode (insn, CCNOmode)
8339 && ix86_binary_operator_ok (AND, HImode, operands)"
8340 "and{w}\t{%2, %0|%0, %2}"
8341 [(set_attr "type" "alu")
8342 (set_attr "mode" "HI")])
8344 (define_expand "andqi3"
8345 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8346 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8347 (match_operand:QI 2 "general_operand" "")))
8348 (clobber (reg:CC FLAGS_REG))]
8349 "TARGET_QIMODE_MATH"
8350 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8352 ;; %%% Potential partial reg stall on alternative 2. What to do?
8353 (define_insn "*andqi_1"
8354 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8355 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8356 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8357 (clobber (reg:CC FLAGS_REG))]
8358 "ix86_binary_operator_ok (AND, QImode, operands)"
8360 and{b}\t{%2, %0|%0, %2}
8361 and{b}\t{%2, %0|%0, %2}
8362 and{l}\t{%k2, %k0|%k0, %k2}"
8363 [(set_attr "type" "alu")
8364 (set_attr "mode" "QI,QI,SI")])
8366 (define_insn "*andqi_1_slp"
8367 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8368 (and:QI (match_dup 0)
8369 (match_operand:QI 1 "general_operand" "qi,qmi")))
8370 (clobber (reg:CC FLAGS_REG))]
8371 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8372 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8373 "and{b}\t{%1, %0|%0, %1}"
8374 [(set_attr "type" "alu1")
8375 (set_attr "mode" "QI")])
8377 (define_insn "*andqi_2_maybe_si"
8378 [(set (reg FLAGS_REG)
8380 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8381 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8383 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8384 (and:QI (match_dup 1) (match_dup 2)))]
8385 "ix86_binary_operator_ok (AND, QImode, operands)
8386 && ix86_match_ccmode (insn,
8387 GET_CODE (operands[2]) == CONST_INT
8388 && INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)"
8390 if (which_alternative == 2)
8392 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8393 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8394 return "and{l}\t{%2, %k0|%k0, %2}";
8396 return "and{b}\t{%2, %0|%0, %2}";
8398 [(set_attr "type" "alu")
8399 (set_attr "mode" "QI,QI,SI")])
8401 (define_insn "*andqi_2"
8402 [(set (reg FLAGS_REG)
8404 (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8405 (match_operand:QI 2 "general_operand" "qim,qi"))
8407 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8408 (and:QI (match_dup 1) (match_dup 2)))]
8409 "ix86_match_ccmode (insn, CCNOmode)
8410 && ix86_binary_operator_ok (AND, QImode, operands)"
8411 "and{b}\t{%2, %0|%0, %2}"
8412 [(set_attr "type" "alu")
8413 (set_attr "mode" "QI")])
8415 (define_insn "*andqi_2_slp"
8416 [(set (reg FLAGS_REG)
8418 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8419 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8421 (set (strict_low_part (match_dup 0))
8422 (and:QI (match_dup 0) (match_dup 1)))]
8423 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8424 && ix86_match_ccmode (insn, CCNOmode)
8425 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8426 "and{b}\t{%1, %0|%0, %1}"
8427 [(set_attr "type" "alu1")
8428 (set_attr "mode" "QI")])
8430 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8431 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8432 ;; for a QImode operand, which of course failed.
8434 (define_insn "andqi_ext_0"
8435 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8440 (match_operand 1 "ext_register_operand" "0")
8443 (match_operand 2 "const_int_operand" "n")))
8444 (clobber (reg:CC FLAGS_REG))]
8446 "and{b}\t{%2, %h0|%h0, %2}"
8447 [(set_attr "type" "alu")
8448 (set_attr "length_immediate" "1")
8449 (set_attr "mode" "QI")])
8451 ;; Generated by peephole translating test to and. This shows up
8452 ;; often in fp comparisons.
8454 (define_insn "*andqi_ext_0_cc"
8455 [(set (reg FLAGS_REG)
8459 (match_operand 1 "ext_register_operand" "0")
8462 (match_operand 2 "const_int_operand" "n"))
8464 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8473 "ix86_match_ccmode (insn, CCNOmode)"
8474 "and{b}\t{%2, %h0|%h0, %2}"
8475 [(set_attr "type" "alu")
8476 (set_attr "length_immediate" "1")
8477 (set_attr "mode" "QI")])
8479 (define_insn "*andqi_ext_1"
8480 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8485 (match_operand 1 "ext_register_operand" "0")
8489 (match_operand:QI 2 "general_operand" "Qm"))))
8490 (clobber (reg:CC FLAGS_REG))]
8492 "and{b}\t{%2, %h0|%h0, %2}"
8493 [(set_attr "type" "alu")
8494 (set_attr "length_immediate" "0")
8495 (set_attr "mode" "QI")])
8497 (define_insn "*andqi_ext_1_rex64"
8498 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8503 (match_operand 1 "ext_register_operand" "0")
8507 (match_operand 2 "ext_register_operand" "Q"))))
8508 (clobber (reg:CC FLAGS_REG))]
8510 "and{b}\t{%2, %h0|%h0, %2}"
8511 [(set_attr "type" "alu")
8512 (set_attr "length_immediate" "0")
8513 (set_attr "mode" "QI")])
8515 (define_insn "*andqi_ext_2"
8516 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8521 (match_operand 1 "ext_register_operand" "%0")
8525 (match_operand 2 "ext_register_operand" "Q")
8528 (clobber (reg:CC FLAGS_REG))]
8530 "and{b}\t{%h2, %h0|%h0, %h2}"
8531 [(set_attr "type" "alu")
8532 (set_attr "length_immediate" "0")
8533 (set_attr "mode" "QI")])
8535 ;; Convert wide AND instructions with immediate operand to shorter QImode
8536 ;; equivalents when possible.
8537 ;; Don't do the splitting with memory operands, since it introduces risk
8538 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8539 ;; for size, but that can (should?) be handled by generic code instead.
8541 [(set (match_operand 0 "register_operand" "")
8542 (and (match_operand 1 "register_operand" "")
8543 (match_operand 2 "const_int_operand" "")))
8544 (clobber (reg:CC FLAGS_REG))]
8546 && QI_REG_P (operands[0])
8547 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8548 && !(~INTVAL (operands[2]) & ~(255 << 8))
8549 && GET_MODE (operands[0]) != QImode"
8550 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8551 (and:SI (zero_extract:SI (match_dup 1)
8552 (const_int 8) (const_int 8))
8554 (clobber (reg:CC FLAGS_REG))])]
8555 "operands[0] = gen_lowpart (SImode, operands[0]);
8556 operands[1] = gen_lowpart (SImode, operands[1]);
8557 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8559 ;; Since AND can be encoded with sign extended immediate, this is only
8560 ;; profitable when 7th bit is not set.
8562 [(set (match_operand 0 "register_operand" "")
8563 (and (match_operand 1 "general_operand" "")
8564 (match_operand 2 "const_int_operand" "")))
8565 (clobber (reg:CC FLAGS_REG))]
8567 && ANY_QI_REG_P (operands[0])
8568 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8569 && !(~INTVAL (operands[2]) & ~255)
8570 && !(INTVAL (operands[2]) & 128)
8571 && GET_MODE (operands[0]) != QImode"
8572 [(parallel [(set (strict_low_part (match_dup 0))
8573 (and:QI (match_dup 1)
8575 (clobber (reg:CC FLAGS_REG))])]
8576 "operands[0] = gen_lowpart (QImode, operands[0]);
8577 operands[1] = gen_lowpart (QImode, operands[1]);
8578 operands[2] = gen_lowpart (QImode, operands[2]);")
8580 ;; Logical inclusive OR instructions
8582 ;; %%% This used to optimize known byte-wide and operations to memory.
8583 ;; If this is considered useful, it should be done with splitters.
8585 (define_expand "iordi3"
8586 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8587 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8588 (match_operand:DI 2 "x86_64_general_operand" "")))
8589 (clobber (reg:CC FLAGS_REG))]
8591 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8593 (define_insn "*iordi_1_rex64"
8594 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8595 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8596 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8597 (clobber (reg:CC FLAGS_REG))]
8599 && ix86_binary_operator_ok (IOR, DImode, operands)"
8600 "or{q}\t{%2, %0|%0, %2}"
8601 [(set_attr "type" "alu")
8602 (set_attr "mode" "DI")])
8604 (define_insn "*iordi_2_rex64"
8605 [(set (reg FLAGS_REG)
8606 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8607 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8609 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8610 (ior:DI (match_dup 1) (match_dup 2)))]
8612 && ix86_match_ccmode (insn, CCNOmode)
8613 && ix86_binary_operator_ok (IOR, DImode, operands)"
8614 "or{q}\t{%2, %0|%0, %2}"
8615 [(set_attr "type" "alu")
8616 (set_attr "mode" "DI")])
8618 (define_insn "*iordi_3_rex64"
8619 [(set (reg FLAGS_REG)
8620 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8621 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8623 (clobber (match_scratch:DI 0 "=r"))]
8625 && ix86_match_ccmode (insn, CCNOmode)
8626 && ix86_binary_operator_ok (IOR, DImode, operands)"
8627 "or{q}\t{%2, %0|%0, %2}"
8628 [(set_attr "type" "alu")
8629 (set_attr "mode" "DI")])
8632 (define_expand "iorsi3"
8633 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8634 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8635 (match_operand:SI 2 "general_operand" "")))
8636 (clobber (reg:CC FLAGS_REG))]
8638 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8640 (define_insn "*iorsi_1"
8641 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8642 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8643 (match_operand:SI 2 "general_operand" "ri,rmi")))
8644 (clobber (reg:CC FLAGS_REG))]
8645 "ix86_binary_operator_ok (IOR, SImode, operands)"
8646 "or{l}\t{%2, %0|%0, %2}"
8647 [(set_attr "type" "alu")
8648 (set_attr "mode" "SI")])
8650 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8651 (define_insn "*iorsi_1_zext"
8652 [(set (match_operand:DI 0 "register_operand" "=rm")
8654 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8655 (match_operand:SI 2 "general_operand" "rim"))))
8656 (clobber (reg:CC FLAGS_REG))]
8657 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8658 "or{l}\t{%2, %k0|%k0, %2}"
8659 [(set_attr "type" "alu")
8660 (set_attr "mode" "SI")])
8662 (define_insn "*iorsi_1_zext_imm"
8663 [(set (match_operand:DI 0 "register_operand" "=rm")
8664 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8665 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8666 (clobber (reg:CC FLAGS_REG))]
8668 "or{l}\t{%2, %k0|%k0, %2}"
8669 [(set_attr "type" "alu")
8670 (set_attr "mode" "SI")])
8672 (define_insn "*iorsi_2"
8673 [(set (reg FLAGS_REG)
8674 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8675 (match_operand:SI 2 "general_operand" "rim,ri"))
8677 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8678 (ior:SI (match_dup 1) (match_dup 2)))]
8679 "ix86_match_ccmode (insn, CCNOmode)
8680 && ix86_binary_operator_ok (IOR, SImode, operands)"
8681 "or{l}\t{%2, %0|%0, %2}"
8682 [(set_attr "type" "alu")
8683 (set_attr "mode" "SI")])
8685 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8686 ;; ??? Special case for immediate operand is missing - it is tricky.
8687 (define_insn "*iorsi_2_zext"
8688 [(set (reg FLAGS_REG)
8689 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8690 (match_operand:SI 2 "general_operand" "rim"))
8692 (set (match_operand:DI 0 "register_operand" "=r")
8693 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8694 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8695 && ix86_binary_operator_ok (IOR, SImode, operands)"
8696 "or{l}\t{%2, %k0|%k0, %2}"
8697 [(set_attr "type" "alu")
8698 (set_attr "mode" "SI")])
8700 (define_insn "*iorsi_2_zext_imm"
8701 [(set (reg FLAGS_REG)
8702 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8703 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8705 (set (match_operand:DI 0 "register_operand" "=r")
8706 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8707 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8708 && ix86_binary_operator_ok (IOR, SImode, operands)"
8709 "or{l}\t{%2, %k0|%k0, %2}"
8710 [(set_attr "type" "alu")
8711 (set_attr "mode" "SI")])
8713 (define_insn "*iorsi_3"
8714 [(set (reg FLAGS_REG)
8715 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8716 (match_operand:SI 2 "general_operand" "rim"))
8718 (clobber (match_scratch:SI 0 "=r"))]
8719 "ix86_match_ccmode (insn, CCNOmode)
8720 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8721 "or{l}\t{%2, %0|%0, %2}"
8722 [(set_attr "type" "alu")
8723 (set_attr "mode" "SI")])
8725 (define_expand "iorhi3"
8726 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8727 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8728 (match_operand:HI 2 "general_operand" "")))
8729 (clobber (reg:CC FLAGS_REG))]
8730 "TARGET_HIMODE_MATH"
8731 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8733 (define_insn "*iorhi_1"
8734 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8735 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8736 (match_operand:HI 2 "general_operand" "rmi,ri")))
8737 (clobber (reg:CC FLAGS_REG))]
8738 "ix86_binary_operator_ok (IOR, HImode, operands)"
8739 "or{w}\t{%2, %0|%0, %2}"
8740 [(set_attr "type" "alu")
8741 (set_attr "mode" "HI")])
8743 (define_insn "*iorhi_2"
8744 [(set (reg FLAGS_REG)
8745 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8746 (match_operand:HI 2 "general_operand" "rim,ri"))
8748 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8749 (ior:HI (match_dup 1) (match_dup 2)))]
8750 "ix86_match_ccmode (insn, CCNOmode)
8751 && ix86_binary_operator_ok (IOR, HImode, operands)"
8752 "or{w}\t{%2, %0|%0, %2}"
8753 [(set_attr "type" "alu")
8754 (set_attr "mode" "HI")])
8756 (define_insn "*iorhi_3"
8757 [(set (reg FLAGS_REG)
8758 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8759 (match_operand:HI 2 "general_operand" "rim"))
8761 (clobber (match_scratch:HI 0 "=r"))]
8762 "ix86_match_ccmode (insn, CCNOmode)
8763 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8764 "or{w}\t{%2, %0|%0, %2}"
8765 [(set_attr "type" "alu")
8766 (set_attr "mode" "HI")])
8768 (define_expand "iorqi3"
8769 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8770 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8771 (match_operand:QI 2 "general_operand" "")))
8772 (clobber (reg:CC FLAGS_REG))]
8773 "TARGET_QIMODE_MATH"
8774 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8776 ;; %%% Potential partial reg stall on alternative 2. What to do?
8777 (define_insn "*iorqi_1"
8778 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8779 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8780 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8781 (clobber (reg:CC FLAGS_REG))]
8782 "ix86_binary_operator_ok (IOR, QImode, operands)"
8784 or{b}\t{%2, %0|%0, %2}
8785 or{b}\t{%2, %0|%0, %2}
8786 or{l}\t{%k2, %k0|%k0, %k2}"
8787 [(set_attr "type" "alu")
8788 (set_attr "mode" "QI,QI,SI")])
8790 (define_insn "*iorqi_1_slp"
8791 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8792 (ior:QI (match_dup 0)
8793 (match_operand:QI 1 "general_operand" "qmi,qi")))
8794 (clobber (reg:CC FLAGS_REG))]
8795 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8796 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8797 "or{b}\t{%1, %0|%0, %1}"
8798 [(set_attr "type" "alu1")
8799 (set_attr "mode" "QI")])
8801 (define_insn "*iorqi_2"
8802 [(set (reg FLAGS_REG)
8803 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8804 (match_operand:QI 2 "general_operand" "qim,qi"))
8806 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8807 (ior:QI (match_dup 1) (match_dup 2)))]
8808 "ix86_match_ccmode (insn, CCNOmode)
8809 && ix86_binary_operator_ok (IOR, QImode, operands)"
8810 "or{b}\t{%2, %0|%0, %2}"
8811 [(set_attr "type" "alu")
8812 (set_attr "mode" "QI")])
8814 (define_insn "*iorqi_2_slp"
8815 [(set (reg FLAGS_REG)
8816 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8817 (match_operand:QI 1 "general_operand" "qim,qi"))
8819 (set (strict_low_part (match_dup 0))
8820 (ior:QI (match_dup 0) (match_dup 1)))]
8821 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8822 && ix86_match_ccmode (insn, CCNOmode)
8823 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8824 "or{b}\t{%1, %0|%0, %1}"
8825 [(set_attr "type" "alu1")
8826 (set_attr "mode" "QI")])
8828 (define_insn "*iorqi_3"
8829 [(set (reg FLAGS_REG)
8830 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8831 (match_operand:QI 2 "general_operand" "qim"))
8833 (clobber (match_scratch:QI 0 "=q"))]
8834 "ix86_match_ccmode (insn, CCNOmode)
8835 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8836 "or{b}\t{%2, %0|%0, %2}"
8837 [(set_attr "type" "alu")
8838 (set_attr "mode" "QI")])
8840 (define_insn "iorqi_ext_0"
8841 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8846 (match_operand 1 "ext_register_operand" "0")
8849 (match_operand 2 "const_int_operand" "n")))
8850 (clobber (reg:CC FLAGS_REG))]
8851 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8852 "or{b}\t{%2, %h0|%h0, %2}"
8853 [(set_attr "type" "alu")
8854 (set_attr "length_immediate" "1")
8855 (set_attr "mode" "QI")])
8857 (define_insn "*iorqi_ext_1"
8858 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8863 (match_operand 1 "ext_register_operand" "0")
8867 (match_operand:QI 2 "general_operand" "Qm"))))
8868 (clobber (reg:CC FLAGS_REG))]
8870 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8871 "or{b}\t{%2, %h0|%h0, %2}"
8872 [(set_attr "type" "alu")
8873 (set_attr "length_immediate" "0")
8874 (set_attr "mode" "QI")])
8876 (define_insn "*iorqi_ext_1_rex64"
8877 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8882 (match_operand 1 "ext_register_operand" "0")
8886 (match_operand 2 "ext_register_operand" "Q"))))
8887 (clobber (reg:CC FLAGS_REG))]
8889 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8890 "or{b}\t{%2, %h0|%h0, %2}"
8891 [(set_attr "type" "alu")
8892 (set_attr "length_immediate" "0")
8893 (set_attr "mode" "QI")])
8895 (define_insn "*iorqi_ext_2"
8896 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8900 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8903 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8906 (clobber (reg:CC FLAGS_REG))]
8907 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8908 "ior{b}\t{%h2, %h0|%h0, %h2}"
8909 [(set_attr "type" "alu")
8910 (set_attr "length_immediate" "0")
8911 (set_attr "mode" "QI")])
8914 [(set (match_operand 0 "register_operand" "")
8915 (ior (match_operand 1 "register_operand" "")
8916 (match_operand 2 "const_int_operand" "")))
8917 (clobber (reg:CC FLAGS_REG))]
8919 && QI_REG_P (operands[0])
8920 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8921 && !(INTVAL (operands[2]) & ~(255 << 8))
8922 && GET_MODE (operands[0]) != QImode"
8923 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8924 (ior:SI (zero_extract:SI (match_dup 1)
8925 (const_int 8) (const_int 8))
8927 (clobber (reg:CC FLAGS_REG))])]
8928 "operands[0] = gen_lowpart (SImode, operands[0]);
8929 operands[1] = gen_lowpart (SImode, operands[1]);
8930 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8932 ;; Since OR can be encoded with sign extended immediate, this is only
8933 ;; profitable when 7th bit is set.
8935 [(set (match_operand 0 "register_operand" "")
8936 (ior (match_operand 1 "general_operand" "")
8937 (match_operand 2 "const_int_operand" "")))
8938 (clobber (reg:CC FLAGS_REG))]
8940 && ANY_QI_REG_P (operands[0])
8941 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8942 && !(INTVAL (operands[2]) & ~255)
8943 && (INTVAL (operands[2]) & 128)
8944 && GET_MODE (operands[0]) != QImode"
8945 [(parallel [(set (strict_low_part (match_dup 0))
8946 (ior:QI (match_dup 1)
8948 (clobber (reg:CC FLAGS_REG))])]
8949 "operands[0] = gen_lowpart (QImode, operands[0]);
8950 operands[1] = gen_lowpart (QImode, operands[1]);
8951 operands[2] = gen_lowpart (QImode, operands[2]);")
8953 ;; Logical XOR instructions
8955 ;; %%% This used to optimize known byte-wide and operations to memory.
8956 ;; If this is considered useful, it should be done with splitters.
8958 (define_expand "xordi3"
8959 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8960 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8961 (match_operand:DI 2 "x86_64_general_operand" "")))
8962 (clobber (reg:CC FLAGS_REG))]
8964 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8966 (define_insn "*xordi_1_rex64"
8967 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8968 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8969 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8970 (clobber (reg:CC FLAGS_REG))]
8972 && ix86_binary_operator_ok (XOR, DImode, operands)"
8974 xor{q}\t{%2, %0|%0, %2}
8975 xor{q}\t{%2, %0|%0, %2}"
8976 [(set_attr "type" "alu")
8977 (set_attr "mode" "DI,DI")])
8979 (define_insn "*xordi_2_rex64"
8980 [(set (reg FLAGS_REG)
8981 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8982 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8984 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8985 (xor:DI (match_dup 1) (match_dup 2)))]
8987 && ix86_match_ccmode (insn, CCNOmode)
8988 && ix86_binary_operator_ok (XOR, DImode, operands)"
8990 xor{q}\t{%2, %0|%0, %2}
8991 xor{q}\t{%2, %0|%0, %2}"
8992 [(set_attr "type" "alu")
8993 (set_attr "mode" "DI,DI")])
8995 (define_insn "*xordi_3_rex64"
8996 [(set (reg FLAGS_REG)
8997 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8998 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9000 (clobber (match_scratch:DI 0 "=r"))]
9002 && ix86_match_ccmode (insn, CCNOmode)
9003 && ix86_binary_operator_ok (XOR, DImode, operands)"
9004 "xor{q}\t{%2, %0|%0, %2}"
9005 [(set_attr "type" "alu")
9006 (set_attr "mode" "DI")])
9008 (define_expand "xorsi3"
9009 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9010 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9011 (match_operand:SI 2 "general_operand" "")))
9012 (clobber (reg:CC FLAGS_REG))]
9014 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9016 (define_insn "*xorsi_1"
9017 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9018 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9019 (match_operand:SI 2 "general_operand" "ri,rm")))
9020 (clobber (reg:CC FLAGS_REG))]
9021 "ix86_binary_operator_ok (XOR, SImode, operands)"
9022 "xor{l}\t{%2, %0|%0, %2}"
9023 [(set_attr "type" "alu")
9024 (set_attr "mode" "SI")])
9026 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9027 ;; Add speccase for immediates
9028 (define_insn "*xorsi_1_zext"
9029 [(set (match_operand:DI 0 "register_operand" "=r")
9031 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9032 (match_operand:SI 2 "general_operand" "rim"))))
9033 (clobber (reg:CC FLAGS_REG))]
9034 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9035 "xor{l}\t{%2, %k0|%k0, %2}"
9036 [(set_attr "type" "alu")
9037 (set_attr "mode" "SI")])
9039 (define_insn "*xorsi_1_zext_imm"
9040 [(set (match_operand:DI 0 "register_operand" "=r")
9041 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9042 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9043 (clobber (reg:CC FLAGS_REG))]
9044 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9045 "xor{l}\t{%2, %k0|%k0, %2}"
9046 [(set_attr "type" "alu")
9047 (set_attr "mode" "SI")])
9049 (define_insn "*xorsi_2"
9050 [(set (reg FLAGS_REG)
9051 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9052 (match_operand:SI 2 "general_operand" "rim,ri"))
9054 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9055 (xor:SI (match_dup 1) (match_dup 2)))]
9056 "ix86_match_ccmode (insn, CCNOmode)
9057 && ix86_binary_operator_ok (XOR, SImode, operands)"
9058 "xor{l}\t{%2, %0|%0, %2}"
9059 [(set_attr "type" "alu")
9060 (set_attr "mode" "SI")])
9062 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9063 ;; ??? Special case for immediate operand is missing - it is tricky.
9064 (define_insn "*xorsi_2_zext"
9065 [(set (reg FLAGS_REG)
9066 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9067 (match_operand:SI 2 "general_operand" "rim"))
9069 (set (match_operand:DI 0 "register_operand" "=r")
9070 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9071 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9072 && ix86_binary_operator_ok (XOR, SImode, operands)"
9073 "xor{l}\t{%2, %k0|%k0, %2}"
9074 [(set_attr "type" "alu")
9075 (set_attr "mode" "SI")])
9077 (define_insn "*xorsi_2_zext_imm"
9078 [(set (reg FLAGS_REG)
9079 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9080 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9082 (set (match_operand:DI 0 "register_operand" "=r")
9083 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9084 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9085 && ix86_binary_operator_ok (XOR, SImode, operands)"
9086 "xor{l}\t{%2, %k0|%k0, %2}"
9087 [(set_attr "type" "alu")
9088 (set_attr "mode" "SI")])
9090 (define_insn "*xorsi_3"
9091 [(set (reg FLAGS_REG)
9092 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9093 (match_operand:SI 2 "general_operand" "rim"))
9095 (clobber (match_scratch:SI 0 "=r"))]
9096 "ix86_match_ccmode (insn, CCNOmode)
9097 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9098 "xor{l}\t{%2, %0|%0, %2}"
9099 [(set_attr "type" "alu")
9100 (set_attr "mode" "SI")])
9102 (define_expand "xorhi3"
9103 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9104 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9105 (match_operand:HI 2 "general_operand" "")))
9106 (clobber (reg:CC FLAGS_REG))]
9107 "TARGET_HIMODE_MATH"
9108 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9110 (define_insn "*xorhi_1"
9111 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9112 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9113 (match_operand:HI 2 "general_operand" "rmi,ri")))
9114 (clobber (reg:CC FLAGS_REG))]
9115 "ix86_binary_operator_ok (XOR, HImode, operands)"
9116 "xor{w}\t{%2, %0|%0, %2}"
9117 [(set_attr "type" "alu")
9118 (set_attr "mode" "HI")])
9120 (define_insn "*xorhi_2"
9121 [(set (reg FLAGS_REG)
9122 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9123 (match_operand:HI 2 "general_operand" "rim,ri"))
9125 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9126 (xor:HI (match_dup 1) (match_dup 2)))]
9127 "ix86_match_ccmode (insn, CCNOmode)
9128 && ix86_binary_operator_ok (XOR, HImode, operands)"
9129 "xor{w}\t{%2, %0|%0, %2}"
9130 [(set_attr "type" "alu")
9131 (set_attr "mode" "HI")])
9133 (define_insn "*xorhi_3"
9134 [(set (reg FLAGS_REG)
9135 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9136 (match_operand:HI 2 "general_operand" "rim"))
9138 (clobber (match_scratch:HI 0 "=r"))]
9139 "ix86_match_ccmode (insn, CCNOmode)
9140 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9141 "xor{w}\t{%2, %0|%0, %2}"
9142 [(set_attr "type" "alu")
9143 (set_attr "mode" "HI")])
9145 (define_expand "xorqi3"
9146 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9147 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9148 (match_operand:QI 2 "general_operand" "")))
9149 (clobber (reg:CC FLAGS_REG))]
9150 "TARGET_QIMODE_MATH"
9151 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9153 ;; %%% Potential partial reg stall on alternative 2. What to do?
9154 (define_insn "*xorqi_1"
9155 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9156 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9157 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9158 (clobber (reg:CC FLAGS_REG))]
9159 "ix86_binary_operator_ok (XOR, QImode, operands)"
9161 xor{b}\t{%2, %0|%0, %2}
9162 xor{b}\t{%2, %0|%0, %2}
9163 xor{l}\t{%k2, %k0|%k0, %k2}"
9164 [(set_attr "type" "alu")
9165 (set_attr "mode" "QI,QI,SI")])
9167 (define_insn "*xorqi_1_slp"
9168 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9169 (xor:QI (match_dup 0)
9170 (match_operand:QI 1 "general_operand" "qi,qmi")))
9171 (clobber (reg:CC FLAGS_REG))]
9172 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9173 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9174 "xor{b}\t{%1, %0|%0, %1}"
9175 [(set_attr "type" "alu1")
9176 (set_attr "mode" "QI")])
9178 (define_insn "xorqi_ext_0"
9179 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9184 (match_operand 1 "ext_register_operand" "0")
9187 (match_operand 2 "const_int_operand" "n")))
9188 (clobber (reg:CC FLAGS_REG))]
9189 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9190 "xor{b}\t{%2, %h0|%h0, %2}"
9191 [(set_attr "type" "alu")
9192 (set_attr "length_immediate" "1")
9193 (set_attr "mode" "QI")])
9195 (define_insn "*xorqi_ext_1"
9196 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9201 (match_operand 1 "ext_register_operand" "0")
9205 (match_operand:QI 2 "general_operand" "Qm"))))
9206 (clobber (reg:CC FLAGS_REG))]
9208 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9209 "xor{b}\t{%2, %h0|%h0, %2}"
9210 [(set_attr "type" "alu")
9211 (set_attr "length_immediate" "0")
9212 (set_attr "mode" "QI")])
9214 (define_insn "*xorqi_ext_1_rex64"
9215 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9220 (match_operand 1 "ext_register_operand" "0")
9224 (match_operand 2 "ext_register_operand" "Q"))))
9225 (clobber (reg:CC FLAGS_REG))]
9227 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9228 "xor{b}\t{%2, %h0|%h0, %2}"
9229 [(set_attr "type" "alu")
9230 (set_attr "length_immediate" "0")
9231 (set_attr "mode" "QI")])
9233 (define_insn "*xorqi_ext_2"
9234 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9238 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9241 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9244 (clobber (reg:CC FLAGS_REG))]
9245 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9246 "xor{b}\t{%h2, %h0|%h0, %h2}"
9247 [(set_attr "type" "alu")
9248 (set_attr "length_immediate" "0")
9249 (set_attr "mode" "QI")])
9251 (define_insn "*xorqi_cc_1"
9252 [(set (reg FLAGS_REG)
9254 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9255 (match_operand:QI 2 "general_operand" "qim,qi"))
9257 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9258 (xor:QI (match_dup 1) (match_dup 2)))]
9259 "ix86_match_ccmode (insn, CCNOmode)
9260 && ix86_binary_operator_ok (XOR, QImode, operands)"
9261 "xor{b}\t{%2, %0|%0, %2}"
9262 [(set_attr "type" "alu")
9263 (set_attr "mode" "QI")])
9265 (define_insn "*xorqi_2_slp"
9266 [(set (reg FLAGS_REG)
9267 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9268 (match_operand:QI 1 "general_operand" "qim,qi"))
9270 (set (strict_low_part (match_dup 0))
9271 (xor:QI (match_dup 0) (match_dup 1)))]
9272 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9273 && ix86_match_ccmode (insn, CCNOmode)
9274 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9275 "xor{b}\t{%1, %0|%0, %1}"
9276 [(set_attr "type" "alu1")
9277 (set_attr "mode" "QI")])
9279 (define_insn "*xorqi_cc_2"
9280 [(set (reg FLAGS_REG)
9282 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9283 (match_operand:QI 2 "general_operand" "qim"))
9285 (clobber (match_scratch:QI 0 "=q"))]
9286 "ix86_match_ccmode (insn, CCNOmode)
9287 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9288 "xor{b}\t{%2, %0|%0, %2}"
9289 [(set_attr "type" "alu")
9290 (set_attr "mode" "QI")])
9292 (define_insn "*xorqi_cc_ext_1"
9293 [(set (reg FLAGS_REG)
9297 (match_operand 1 "ext_register_operand" "0")
9300 (match_operand:QI 2 "general_operand" "qmn"))
9302 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9306 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9308 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9309 "xor{b}\t{%2, %h0|%h0, %2}"
9310 [(set_attr "type" "alu")
9311 (set_attr "mode" "QI")])
9313 (define_insn "*xorqi_cc_ext_1_rex64"
9314 [(set (reg FLAGS_REG)
9318 (match_operand 1 "ext_register_operand" "0")
9321 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9323 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9327 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9329 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9330 "xor{b}\t{%2, %h0|%h0, %2}"
9331 [(set_attr "type" "alu")
9332 (set_attr "mode" "QI")])
9334 (define_expand "xorqi_cc_ext_1"
9336 (set (reg:CCNO FLAGS_REG)
9340 (match_operand 1 "ext_register_operand" "")
9343 (match_operand:QI 2 "general_operand" ""))
9345 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9349 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9355 [(set (match_operand 0 "register_operand" "")
9356 (xor (match_operand 1 "register_operand" "")
9357 (match_operand 2 "const_int_operand" "")))
9358 (clobber (reg:CC FLAGS_REG))]
9360 && QI_REG_P (operands[0])
9361 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9362 && !(INTVAL (operands[2]) & ~(255 << 8))
9363 && GET_MODE (operands[0]) != QImode"
9364 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9365 (xor:SI (zero_extract:SI (match_dup 1)
9366 (const_int 8) (const_int 8))
9368 (clobber (reg:CC FLAGS_REG))])]
9369 "operands[0] = gen_lowpart (SImode, operands[0]);
9370 operands[1] = gen_lowpart (SImode, operands[1]);
9371 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9373 ;; Since XOR can be encoded with sign extended immediate, this is only
9374 ;; profitable when 7th bit is set.
9376 [(set (match_operand 0 "register_operand" "")
9377 (xor (match_operand 1 "general_operand" "")
9378 (match_operand 2 "const_int_operand" "")))
9379 (clobber (reg:CC FLAGS_REG))]
9381 && ANY_QI_REG_P (operands[0])
9382 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9383 && !(INTVAL (operands[2]) & ~255)
9384 && (INTVAL (operands[2]) & 128)
9385 && GET_MODE (operands[0]) != QImode"
9386 [(parallel [(set (strict_low_part (match_dup 0))
9387 (xor:QI (match_dup 1)
9389 (clobber (reg:CC FLAGS_REG))])]
9390 "operands[0] = gen_lowpart (QImode, operands[0]);
9391 operands[1] = gen_lowpart (QImode, operands[1]);
9392 operands[2] = gen_lowpart (QImode, operands[2]);")
9394 ;; Negation instructions
9396 (define_expand "negdi2"
9397 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9398 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9399 (clobber (reg:CC FLAGS_REG))])]
9401 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9403 (define_insn "*negdi2_1"
9404 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9405 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9406 (clobber (reg:CC FLAGS_REG))]
9408 && ix86_unary_operator_ok (NEG, DImode, operands)"
9412 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9413 (neg:DI (match_operand:DI 1 "general_operand" "")))
9414 (clobber (reg:CC FLAGS_REG))]
9415 "!TARGET_64BIT && reload_completed"
9417 [(set (reg:CCZ FLAGS_REG)
9418 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9419 (set (match_dup 0) (neg:SI (match_dup 2)))])
9422 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
9425 (clobber (reg:CC FLAGS_REG))])
9428 (neg:SI (match_dup 1)))
9429 (clobber (reg:CC FLAGS_REG))])]
9430 "split_di (operands+1, 1, operands+2, operands+3);
9431 split_di (operands+0, 1, operands+0, operands+1);")
9433 (define_insn "*negdi2_1_rex64"
9434 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9435 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9436 (clobber (reg:CC FLAGS_REG))]
9437 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9439 [(set_attr "type" "negnot")
9440 (set_attr "mode" "DI")])
9442 ;; The problem with neg is that it does not perform (compare x 0),
9443 ;; it really performs (compare 0 x), which leaves us with the zero
9444 ;; flag being the only useful item.
9446 (define_insn "*negdi2_cmpz_rex64"
9447 [(set (reg:CCZ FLAGS_REG)
9448 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9450 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9451 (neg:DI (match_dup 1)))]
9452 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9454 [(set_attr "type" "negnot")
9455 (set_attr "mode" "DI")])
9458 (define_expand "negsi2"
9459 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9460 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9461 (clobber (reg:CC FLAGS_REG))])]
9463 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9465 (define_insn "*negsi2_1"
9466 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9467 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9468 (clobber (reg:CC FLAGS_REG))]
9469 "ix86_unary_operator_ok (NEG, SImode, operands)"
9471 [(set_attr "type" "negnot")
9472 (set_attr "mode" "SI")])
9474 ;; Combine is quite creative about this pattern.
9475 (define_insn "*negsi2_1_zext"
9476 [(set (match_operand:DI 0 "register_operand" "=r")
9477 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9480 (clobber (reg:CC FLAGS_REG))]
9481 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9483 [(set_attr "type" "negnot")
9484 (set_attr "mode" "SI")])
9486 ;; The problem with neg is that it does not perform (compare x 0),
9487 ;; it really performs (compare 0 x), which leaves us with the zero
9488 ;; flag being the only useful item.
9490 (define_insn "*negsi2_cmpz"
9491 [(set (reg:CCZ FLAGS_REG)
9492 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9494 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9495 (neg:SI (match_dup 1)))]
9496 "ix86_unary_operator_ok (NEG, SImode, operands)"
9498 [(set_attr "type" "negnot")
9499 (set_attr "mode" "SI")])
9501 (define_insn "*negsi2_cmpz_zext"
9502 [(set (reg:CCZ FLAGS_REG)
9503 (compare:CCZ (lshiftrt:DI
9505 (match_operand:DI 1 "register_operand" "0")
9509 (set (match_operand:DI 0 "register_operand" "=r")
9510 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9513 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9515 [(set_attr "type" "negnot")
9516 (set_attr "mode" "SI")])
9518 (define_expand "neghi2"
9519 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9520 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9521 (clobber (reg:CC FLAGS_REG))])]
9522 "TARGET_HIMODE_MATH"
9523 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9525 (define_insn "*neghi2_1"
9526 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9527 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9528 (clobber (reg:CC FLAGS_REG))]
9529 "ix86_unary_operator_ok (NEG, HImode, operands)"
9531 [(set_attr "type" "negnot")
9532 (set_attr "mode" "HI")])
9534 (define_insn "*neghi2_cmpz"
9535 [(set (reg:CCZ FLAGS_REG)
9536 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9538 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9539 (neg:HI (match_dup 1)))]
9540 "ix86_unary_operator_ok (NEG, HImode, operands)"
9542 [(set_attr "type" "negnot")
9543 (set_attr "mode" "HI")])
9545 (define_expand "negqi2"
9546 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9547 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9548 (clobber (reg:CC FLAGS_REG))])]
9549 "TARGET_QIMODE_MATH"
9550 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9552 (define_insn "*negqi2_1"
9553 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9554 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9555 (clobber (reg:CC FLAGS_REG))]
9556 "ix86_unary_operator_ok (NEG, QImode, operands)"
9558 [(set_attr "type" "negnot")
9559 (set_attr "mode" "QI")])
9561 (define_insn "*negqi2_cmpz"
9562 [(set (reg:CCZ FLAGS_REG)
9563 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9565 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9566 (neg:QI (match_dup 1)))]
9567 "ix86_unary_operator_ok (NEG, QImode, operands)"
9569 [(set_attr "type" "negnot")
9570 (set_attr "mode" "QI")])
9572 ;; Changing of sign for FP values is doable using integer unit too.
9574 (define_expand "negsf2"
9575 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9576 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
9577 "TARGET_80387 || TARGET_SSE_MATH"
9578 "ix86_expand_fp_absneg_operator (NEG, SFmode, operands); DONE;")
9580 (define_expand "abssf2"
9581 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9582 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
9583 "TARGET_80387 || TARGET_SSE_MATH"
9584 "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
9586 (define_insn "*absnegsf2_mixed"
9587 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9588 (match_operator:SF 3 "absneg_operator"
9589 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#fr,0 ,0")]))
9590 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X ,X"))
9591 (clobber (reg:CC FLAGS_REG))]
9592 "TARGET_SSE_MATH && TARGET_MIX_SSE_I387
9593 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9596 (define_insn "*absnegsf2_sse"
9597 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#r,x#r,rm#x")
9598 (match_operator:SF 3 "absneg_operator"
9599 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#r,0")]))
9600 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X"))
9601 (clobber (reg:CC FLAGS_REG))]
9603 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9606 (define_insn "*absnegsf2_i387"
9607 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9608 (match_operator:SF 3 "absneg_operator"
9609 [(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
9610 (use (match_operand 2 "" ""))
9611 (clobber (reg:CC FLAGS_REG))]
9612 "TARGET_80387 && !TARGET_SSE_MATH
9613 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9616 (define_expand "negdf2"
9617 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9618 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
9619 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9620 "ix86_expand_fp_absneg_operator (NEG, DFmode, operands); DONE;")
9622 (define_expand "absdf2"
9623 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9624 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
9625 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9626 "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
9628 (define_insn "*absnegdf2_mixed"
9629 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9630 (match_operator:DF 3 "absneg_operator"
9631 [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#fr,0 ,0")]))
9632 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X ,X"))
9633 (clobber (reg:CC FLAGS_REG))]
9634 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
9635 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9638 (define_insn "*absnegdf2_sse"
9639 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#r,Y#r,rm#Y")
9640 (match_operator:DF 3 "absneg_operator"
9641 [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#r,0")]))
9642 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X"))
9643 (clobber (reg:CC FLAGS_REG))]
9644 "TARGET_SSE2 && TARGET_SSE_MATH
9645 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9648 (define_insn "*absnegdf2_i387"
9649 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9650 (match_operator:DF 3 "absneg_operator"
9651 [(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
9652 (use (match_operand 2 "" ""))
9653 (clobber (reg:CC FLAGS_REG))]
9654 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
9655 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9658 (define_expand "negxf2"
9659 [(set (match_operand:XF 0 "nonimmediate_operand" "")
9660 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
9662 "ix86_expand_fp_absneg_operator (NEG, XFmode, operands); DONE;")
9664 (define_expand "absxf2"
9665 [(set (match_operand:XF 0 "nonimmediate_operand" "")
9666 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
9668 "ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
9670 (define_insn "*absnegxf2_i387"
9671 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9672 (match_operator:XF 3 "absneg_operator"
9673 [(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
9674 (use (match_operand 2 "" ""))
9675 (clobber (reg:CC FLAGS_REG))]
9677 && ix86_unary_operator_ok (GET_CODE (operands[3]), XFmode, operands)"
9680 ;; Splitters for fp abs and neg.
9683 [(set (match_operand 0 "fp_register_operand" "")
9684 (match_operator 1 "absneg_operator" [(match_dup 0)]))
9685 (use (match_operand 2 "" ""))
9686 (clobber (reg:CC FLAGS_REG))]
9688 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
9691 [(set (match_operand 0 "register_operand" "")
9692 (match_operator 3 "absneg_operator"
9693 [(match_operand 1 "register_operand" "")]))
9694 (use (match_operand 2 "nonimmediate_operand" ""))
9695 (clobber (reg:CC FLAGS_REG))]
9696 "reload_completed && SSE_REG_P (operands[0])"
9697 [(set (match_dup 0) (match_dup 3))]
9699 enum machine_mode mode = GET_MODE (operands[0]);
9700 enum machine_mode vmode = GET_MODE (operands[2]);
9703 operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
9704 operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
9705 if (operands_match_p (operands[0], operands[2]))
9708 operands[1] = operands[2];
9711 if (GET_CODE (operands[3]) == ABS)
9712 tmp = gen_rtx_AND (vmode, operands[1], operands[2]);
9714 tmp = gen_rtx_XOR (vmode, operands[1], operands[2]);
9719 [(set (match_operand:SF 0 "register_operand" "")
9720 (match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
9721 (use (match_operand:V4SF 2 "" ""))
9722 (clobber (reg:CC FLAGS_REG))]
9724 [(parallel [(set (match_dup 0) (match_dup 1))
9725 (clobber (reg:CC FLAGS_REG))])]
9728 operands[0] = gen_lowpart (SImode, operands[0]);
9729 if (GET_CODE (operands[1]) == ABS)
9731 tmp = gen_int_mode (0x7fffffff, SImode);
9732 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9736 tmp = gen_int_mode (0x80000000, SImode);
9737 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9743 [(set (match_operand:DF 0 "register_operand" "")
9744 (match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
9745 (use (match_operand 2 "" ""))
9746 (clobber (reg:CC FLAGS_REG))]
9748 [(parallel [(set (match_dup 0) (match_dup 1))
9749 (clobber (reg:CC FLAGS_REG))])]
9754 tmp = gen_lowpart (DImode, operands[0]);
9755 tmp = gen_rtx_ZERO_EXTRACT (DImode, tmp, const1_rtx, GEN_INT (63));
9758 if (GET_CODE (operands[1]) == ABS)
9761 tmp = gen_rtx_NOT (DImode, tmp);
9765 operands[0] = gen_highpart (SImode, operands[0]);
9766 if (GET_CODE (operands[1]) == ABS)
9768 tmp = gen_int_mode (0x7fffffff, SImode);
9769 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9773 tmp = gen_int_mode (0x80000000, SImode);
9774 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9781 [(set (match_operand:XF 0 "register_operand" "")
9782 (match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
9783 (use (match_operand 2 "" ""))
9784 (clobber (reg:CC FLAGS_REG))]
9786 [(parallel [(set (match_dup 0) (match_dup 1))
9787 (clobber (reg:CC FLAGS_REG))])]
9790 operands[0] = gen_rtx_REG (SImode,
9791 true_regnum (operands[0])
9792 + (TARGET_64BIT ? 1 : 2));
9793 if (GET_CODE (operands[1]) == ABS)
9795 tmp = GEN_INT (0x7fff);
9796 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9800 tmp = GEN_INT (0x8000);
9801 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9807 [(set (match_operand 0 "memory_operand" "")
9808 (match_operator 1 "absneg_operator" [(match_dup 0)]))
9809 (use (match_operand 2 "" ""))
9810 (clobber (reg:CC FLAGS_REG))]
9812 [(parallel [(set (match_dup 0) (match_dup 1))
9813 (clobber (reg:CC FLAGS_REG))])]
9815 enum machine_mode mode = GET_MODE (operands[0]);
9816 int size = mode == XFmode ? 10 : GET_MODE_SIZE (mode);
9819 operands[0] = adjust_address (operands[0], QImode, size - 1);
9820 if (GET_CODE (operands[1]) == ABS)
9822 tmp = gen_int_mode (0x7f, QImode);
9823 tmp = gen_rtx_AND (QImode, operands[0], tmp);
9827 tmp = gen_int_mode (0x80, QImode);
9828 tmp = gen_rtx_XOR (QImode, operands[0], tmp);
9833 ;; Conditionalize these after reload. If they match before reload, we
9834 ;; lose the clobber and ability to use integer instructions.
9836 (define_insn "*negsf2_1"
9837 [(set (match_operand:SF 0 "register_operand" "=f")
9838 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9839 "TARGET_80387 && reload_completed"
9841 [(set_attr "type" "fsgn")
9842 (set_attr "mode" "SF")])
9844 (define_insn "*negdf2_1"
9845 [(set (match_operand:DF 0 "register_operand" "=f")
9846 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9847 "TARGET_80387 && reload_completed"
9849 [(set_attr "type" "fsgn")
9850 (set_attr "mode" "DF")])
9852 (define_insn "*negxf2_1"
9853 [(set (match_operand:XF 0 "register_operand" "=f")
9854 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9855 "TARGET_80387 && reload_completed"
9857 [(set_attr "type" "fsgn")
9858 (set_attr "mode" "XF")])
9860 (define_insn "*abssf2_1"
9861 [(set (match_operand:SF 0 "register_operand" "=f")
9862 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
9863 "TARGET_80387 && reload_completed"
9865 [(set_attr "type" "fsgn")
9866 (set_attr "mode" "SF")])
9868 (define_insn "*absdf2_1"
9869 [(set (match_operand:DF 0 "register_operand" "=f")
9870 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
9871 "TARGET_80387 && reload_completed"
9873 [(set_attr "type" "fsgn")
9874 (set_attr "mode" "DF")])
9876 (define_insn "*absxf2_1"
9877 [(set (match_operand:XF 0 "register_operand" "=f")
9878 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
9879 "TARGET_80387 && reload_completed"
9881 [(set_attr "type" "fsgn")
9882 (set_attr "mode" "DF")])
9884 (define_insn "*negextendsfdf2"
9885 [(set (match_operand:DF 0 "register_operand" "=f")
9886 (neg:DF (float_extend:DF
9887 (match_operand:SF 1 "register_operand" "0"))))]
9888 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9890 [(set_attr "type" "fsgn")
9891 (set_attr "mode" "DF")])
9893 (define_insn "*negextenddfxf2"
9894 [(set (match_operand:XF 0 "register_operand" "=f")
9895 (neg:XF (float_extend:XF
9896 (match_operand:DF 1 "register_operand" "0"))))]
9899 [(set_attr "type" "fsgn")
9900 (set_attr "mode" "XF")])
9902 (define_insn "*negextendsfxf2"
9903 [(set (match_operand:XF 0 "register_operand" "=f")
9904 (neg:XF (float_extend:XF
9905 (match_operand:SF 1 "register_operand" "0"))))]
9908 [(set_attr "type" "fsgn")
9909 (set_attr "mode" "XF")])
9911 (define_insn "*absextendsfdf2"
9912 [(set (match_operand:DF 0 "register_operand" "=f")
9913 (abs:DF (float_extend:DF
9914 (match_operand:SF 1 "register_operand" "0"))))]
9915 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9917 [(set_attr "type" "fsgn")
9918 (set_attr "mode" "DF")])
9920 (define_insn "*absextenddfxf2"
9921 [(set (match_operand:XF 0 "register_operand" "=f")
9922 (abs:XF (float_extend:XF
9923 (match_operand:DF 1 "register_operand" "0"))))]
9926 [(set_attr "type" "fsgn")
9927 (set_attr "mode" "XF")])
9929 (define_insn "*absextendsfxf2"
9930 [(set (match_operand:XF 0 "register_operand" "=f")
9931 (abs:XF (float_extend:XF
9932 (match_operand:SF 1 "register_operand" "0"))))]
9935 [(set_attr "type" "fsgn")
9936 (set_attr "mode" "XF")])
9938 ;; One complement instructions
9940 (define_expand "one_cmpldi2"
9941 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9942 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
9944 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
9946 (define_insn "*one_cmpldi2_1_rex64"
9947 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9948 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
9949 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
9951 [(set_attr "type" "negnot")
9952 (set_attr "mode" "DI")])
9954 (define_insn "*one_cmpldi2_2_rex64"
9955 [(set (reg FLAGS_REG)
9956 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9958 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9959 (not:DI (match_dup 1)))]
9960 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9961 && ix86_unary_operator_ok (NOT, DImode, operands)"
9963 [(set_attr "type" "alu1")
9964 (set_attr "mode" "DI")])
9967 [(set (match_operand 0 "flags_reg_operand" "")
9968 (match_operator 2 "compare_operator"
9969 [(not:DI (match_operand:DI 3 "nonimmediate_operand" ""))
9971 (set (match_operand:DI 1 "nonimmediate_operand" "")
9972 (not:DI (match_dup 3)))]
9973 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9974 [(parallel [(set (match_dup 0)
9976 [(xor:DI (match_dup 3) (const_int -1))
9979 (xor:DI (match_dup 3) (const_int -1)))])]
9982 (define_expand "one_cmplsi2"
9983 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9984 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
9986 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
9988 (define_insn "*one_cmplsi2_1"
9989 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9990 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
9991 "ix86_unary_operator_ok (NOT, SImode, operands)"
9993 [(set_attr "type" "negnot")
9994 (set_attr "mode" "SI")])
9996 ;; ??? Currently never generated - xor is used instead.
9997 (define_insn "*one_cmplsi2_1_zext"
9998 [(set (match_operand:DI 0 "register_operand" "=r")
9999 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10000 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10002 [(set_attr "type" "negnot")
10003 (set_attr "mode" "SI")])
10005 (define_insn "*one_cmplsi2_2"
10006 [(set (reg FLAGS_REG)
10007 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10009 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10010 (not:SI (match_dup 1)))]
10011 "ix86_match_ccmode (insn, CCNOmode)
10012 && ix86_unary_operator_ok (NOT, SImode, operands)"
10014 [(set_attr "type" "alu1")
10015 (set_attr "mode" "SI")])
10018 [(set (match_operand 0 "flags_reg_operand" "")
10019 (match_operator 2 "compare_operator"
10020 [(not:SI (match_operand:SI 3 "nonimmediate_operand" ""))
10022 (set (match_operand:SI 1 "nonimmediate_operand" "")
10023 (not:SI (match_dup 3)))]
10024 "ix86_match_ccmode (insn, CCNOmode)"
10025 [(parallel [(set (match_dup 0)
10026 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10029 (xor:SI (match_dup 3) (const_int -1)))])]
10032 ;; ??? Currently never generated - xor is used instead.
10033 (define_insn "*one_cmplsi2_2_zext"
10034 [(set (reg FLAGS_REG)
10035 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10037 (set (match_operand:DI 0 "register_operand" "=r")
10038 (zero_extend:DI (not:SI (match_dup 1))))]
10039 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10040 && ix86_unary_operator_ok (NOT, SImode, operands)"
10042 [(set_attr "type" "alu1")
10043 (set_attr "mode" "SI")])
10046 [(set (match_operand 0 "flags_reg_operand" "")
10047 (match_operator 2 "compare_operator"
10048 [(not:SI (match_operand:SI 3 "register_operand" ""))
10050 (set (match_operand:DI 1 "register_operand" "")
10051 (zero_extend:DI (not:SI (match_dup 3))))]
10052 "ix86_match_ccmode (insn, CCNOmode)"
10053 [(parallel [(set (match_dup 0)
10054 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10057 (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
10060 (define_expand "one_cmplhi2"
10061 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10062 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10063 "TARGET_HIMODE_MATH"
10064 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10066 (define_insn "*one_cmplhi2_1"
10067 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10068 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10069 "ix86_unary_operator_ok (NOT, HImode, operands)"
10071 [(set_attr "type" "negnot")
10072 (set_attr "mode" "HI")])
10074 (define_insn "*one_cmplhi2_2"
10075 [(set (reg FLAGS_REG)
10076 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10078 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10079 (not:HI (match_dup 1)))]
10080 "ix86_match_ccmode (insn, CCNOmode)
10081 && ix86_unary_operator_ok (NEG, HImode, operands)"
10083 [(set_attr "type" "alu1")
10084 (set_attr "mode" "HI")])
10087 [(set (match_operand 0 "flags_reg_operand" "")
10088 (match_operator 2 "compare_operator"
10089 [(not:HI (match_operand:HI 3 "nonimmediate_operand" ""))
10091 (set (match_operand:HI 1 "nonimmediate_operand" "")
10092 (not:HI (match_dup 3)))]
10093 "ix86_match_ccmode (insn, CCNOmode)"
10094 [(parallel [(set (match_dup 0)
10095 (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1))
10098 (xor:HI (match_dup 3) (const_int -1)))])]
10101 ;; %%% Potential partial reg stall on alternative 1. What to do?
10102 (define_expand "one_cmplqi2"
10103 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10104 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10105 "TARGET_QIMODE_MATH"
10106 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10108 (define_insn "*one_cmplqi2_1"
10109 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10110 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10111 "ix86_unary_operator_ok (NOT, QImode, operands)"
10115 [(set_attr "type" "negnot")
10116 (set_attr "mode" "QI,SI")])
10118 (define_insn "*one_cmplqi2_2"
10119 [(set (reg FLAGS_REG)
10120 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10122 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10123 (not:QI (match_dup 1)))]
10124 "ix86_match_ccmode (insn, CCNOmode)
10125 && ix86_unary_operator_ok (NOT, QImode, operands)"
10127 [(set_attr "type" "alu1")
10128 (set_attr "mode" "QI")])
10131 [(set (match_operand 0 "flags_reg_operand" "")
10132 (match_operator 2 "compare_operator"
10133 [(not:QI (match_operand:QI 3 "nonimmediate_operand" ""))
10135 (set (match_operand:QI 1 "nonimmediate_operand" "")
10136 (not:QI (match_dup 3)))]
10137 "ix86_match_ccmode (insn, CCNOmode)"
10138 [(parallel [(set (match_dup 0)
10139 (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1))
10142 (xor:QI (match_dup 3) (const_int -1)))])]
10145 ;; Arithmetic shift instructions
10147 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10148 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10149 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10150 ;; from the assembler input.
10152 ;; This instruction shifts the target reg/mem as usual, but instead of
10153 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10154 ;; is a left shift double, bits are taken from the high order bits of
10155 ;; reg, else if the insn is a shift right double, bits are taken from the
10156 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10157 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10159 ;; Since sh[lr]d does not change the `reg' operand, that is done
10160 ;; separately, making all shifts emit pairs of shift double and normal
10161 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10162 ;; support a 63 bit shift, each shift where the count is in a reg expands
10163 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10165 ;; If the shift count is a constant, we need never emit more than one
10166 ;; shift pair, instead using moves and sign extension for counts greater
10169 (define_expand "ashldi3"
10170 [(set (match_operand:DI 0 "shiftdi_operand" "")
10171 (ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
10172 (match_operand:QI 2 "nonmemory_operand" "")))]
10174 "ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;")
10176 (define_insn "*ashldi3_1_rex64"
10177 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10178 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,l")
10179 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10180 (clobber (reg:CC FLAGS_REG))]
10181 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10183 switch (get_attr_type (insn))
10186 if (operands[2] != const1_rtx)
10188 if (!rtx_equal_p (operands[0], operands[1]))
10190 return "add{q}\t{%0, %0|%0, %0}";
10193 if (GET_CODE (operands[2]) != CONST_INT
10194 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10196 operands[1] = gen_rtx_MULT (DImode, operands[1],
10197 GEN_INT (1 << INTVAL (operands[2])));
10198 return "lea{q}\t{%a1, %0|%0, %a1}";
10201 if (REG_P (operands[2]))
10202 return "sal{q}\t{%b2, %0|%0, %b2}";
10203 else if (operands[2] == const1_rtx
10204 && (TARGET_SHIFT1 || optimize_size))
10205 return "sal{q}\t%0";
10207 return "sal{q}\t{%2, %0|%0, %2}";
10210 [(set (attr "type")
10211 (cond [(eq_attr "alternative" "1")
10212 (const_string "lea")
10213 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10215 (match_operand 0 "register_operand" ""))
10216 (match_operand 2 "const1_operand" ""))
10217 (const_string "alu")
10219 (const_string "ishift")))
10220 (set_attr "mode" "DI")])
10222 ;; Convert lea to the lea pattern to avoid flags dependency.
10224 [(set (match_operand:DI 0 "register_operand" "")
10225 (ashift:DI (match_operand:DI 1 "index_register_operand" "")
10226 (match_operand:QI 2 "immediate_operand" "")))
10227 (clobber (reg:CC FLAGS_REG))]
10228 "TARGET_64BIT && reload_completed
10229 && true_regnum (operands[0]) != true_regnum (operands[1])"
10230 [(set (match_dup 0)
10231 (mult:DI (match_dup 1)
10233 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10235 ;; This pattern can't accept a variable shift count, since shifts by
10236 ;; zero don't affect the flags. We assume that shifts by constant
10237 ;; zero are optimized away.
10238 (define_insn "*ashldi3_cmp_rex64"
10239 [(set (reg FLAGS_REG)
10241 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10242 (match_operand:QI 2 "immediate_operand" "e"))
10244 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10245 (ashift:DI (match_dup 1) (match_dup 2)))]
10246 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10247 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10249 switch (get_attr_type (insn))
10252 if (operands[2] != const1_rtx)
10254 return "add{q}\t{%0, %0|%0, %0}";
10257 if (REG_P (operands[2]))
10258 return "sal{q}\t{%b2, %0|%0, %b2}";
10259 else if (operands[2] == const1_rtx
10260 && (TARGET_SHIFT1 || optimize_size))
10261 return "sal{q}\t%0";
10263 return "sal{q}\t{%2, %0|%0, %2}";
10266 [(set (attr "type")
10267 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10269 (match_operand 0 "register_operand" ""))
10270 (match_operand 2 "const1_operand" ""))
10271 (const_string "alu")
10273 (const_string "ishift")))
10274 (set_attr "mode" "DI")])
10276 (define_insn "*ashldi3_1"
10277 [(set (match_operand:DI 0 "register_operand" "=&r,r")
10278 (ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
10279 (match_operand:QI 2 "nonmemory_operand" "Jc,Jc")))
10280 (clobber (reg:CC FLAGS_REG))]
10283 [(set_attr "type" "multi")])
10285 ;; By default we don't ask for a scratch register, because when DImode
10286 ;; values are manipulated, registers are already at a premium. But if
10287 ;; we have one handy, we won't turn it away.
10289 [(match_scratch:SI 3 "r")
10290 (parallel [(set (match_operand:DI 0 "register_operand" "")
10291 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10292 (match_operand:QI 2 "nonmemory_operand" "")))
10293 (clobber (reg:CC FLAGS_REG))])
10295 "!TARGET_64BIT && TARGET_CMOVE"
10297 "ix86_split_ashldi (operands, operands[3]); DONE;")
10300 [(set (match_operand:DI 0 "register_operand" "")
10301 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10302 (match_operand:QI 2 "nonmemory_operand" "")))
10303 (clobber (reg:CC FLAGS_REG))]
10304 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
10306 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10308 (define_insn "x86_shld_1"
10309 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10310 (ior:SI (ashift:SI (match_dup 0)
10311 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10312 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10313 (minus:QI (const_int 32) (match_dup 2)))))
10314 (clobber (reg:CC FLAGS_REG))]
10317 shld{l}\t{%2, %1, %0|%0, %1, %2}
10318 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10319 [(set_attr "type" "ishift")
10320 (set_attr "prefix_0f" "1")
10321 (set_attr "mode" "SI")
10322 (set_attr "pent_pair" "np")
10323 (set_attr "athlon_decode" "vector")])
10325 (define_expand "x86_shift_adj_1"
10326 [(set (reg:CCZ FLAGS_REG)
10327 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10330 (set (match_operand:SI 0 "register_operand" "")
10331 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10332 (match_operand:SI 1 "register_operand" "")
10335 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10336 (match_operand:SI 3 "register_operand" "r")
10341 (define_expand "x86_shift_adj_2"
10342 [(use (match_operand:SI 0 "register_operand" ""))
10343 (use (match_operand:SI 1 "register_operand" ""))
10344 (use (match_operand:QI 2 "register_operand" ""))]
10347 rtx label = gen_label_rtx ();
10350 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10352 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10353 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10354 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10355 gen_rtx_LABEL_REF (VOIDmode, label),
10357 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10358 JUMP_LABEL (tmp) = label;
10360 emit_move_insn (operands[0], operands[1]);
10361 ix86_expand_clear (operands[1]);
10363 emit_label (label);
10364 LABEL_NUSES (label) = 1;
10369 (define_expand "ashlsi3"
10370 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10371 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10372 (match_operand:QI 2 "nonmemory_operand" "")))
10373 (clobber (reg:CC FLAGS_REG))]
10375 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10377 (define_insn "*ashlsi3_1"
10378 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10379 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l")
10380 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10381 (clobber (reg:CC FLAGS_REG))]
10382 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10384 switch (get_attr_type (insn))
10387 if (operands[2] != const1_rtx)
10389 if (!rtx_equal_p (operands[0], operands[1]))
10391 return "add{l}\t{%0, %0|%0, %0}";
10397 if (REG_P (operands[2]))
10398 return "sal{l}\t{%b2, %0|%0, %b2}";
10399 else if (operands[2] == const1_rtx
10400 && (TARGET_SHIFT1 || optimize_size))
10401 return "sal{l}\t%0";
10403 return "sal{l}\t{%2, %0|%0, %2}";
10406 [(set (attr "type")
10407 (cond [(eq_attr "alternative" "1")
10408 (const_string "lea")
10409 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10411 (match_operand 0 "register_operand" ""))
10412 (match_operand 2 "const1_operand" ""))
10413 (const_string "alu")
10415 (const_string "ishift")))
10416 (set_attr "mode" "SI")])
10418 ;; Convert lea to the lea pattern to avoid flags dependency.
10420 [(set (match_operand 0 "register_operand" "")
10421 (ashift (match_operand 1 "index_register_operand" "")
10422 (match_operand:QI 2 "const_int_operand" "")))
10423 (clobber (reg:CC FLAGS_REG))]
10425 && true_regnum (operands[0]) != true_regnum (operands[1])
10426 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 4"
10430 enum machine_mode mode = GET_MODE (operands[0]);
10432 if (GET_MODE_SIZE (mode) < 4)
10433 operands[0] = gen_lowpart (SImode, operands[0]);
10435 operands[1] = gen_lowpart (Pmode, operands[1]);
10436 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10438 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10439 if (Pmode != SImode)
10440 pat = gen_rtx_SUBREG (SImode, pat, 0);
10441 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10445 ;; Rare case of shifting RSP is handled by generating move and shift
10447 [(set (match_operand 0 "register_operand" "")
10448 (ashift (match_operand 1 "register_operand" "")
10449 (match_operand:QI 2 "const_int_operand" "")))
10450 (clobber (reg:CC FLAGS_REG))]
10452 && true_regnum (operands[0]) != true_regnum (operands[1])"
10456 emit_move_insn (operands[1], operands[0]);
10457 pat = gen_rtx_SET (VOIDmode, operands[0],
10458 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10459 operands[0], operands[2]));
10460 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10461 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10465 (define_insn "*ashlsi3_1_zext"
10466 [(set (match_operand:DI 0 "register_operand" "=r,r")
10467 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,l")
10468 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10469 (clobber (reg:CC FLAGS_REG))]
10470 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10472 switch (get_attr_type (insn))
10475 if (operands[2] != const1_rtx)
10477 return "add{l}\t{%k0, %k0|%k0, %k0}";
10483 if (REG_P (operands[2]))
10484 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10485 else if (operands[2] == const1_rtx
10486 && (TARGET_SHIFT1 || optimize_size))
10487 return "sal{l}\t%k0";
10489 return "sal{l}\t{%2, %k0|%k0, %2}";
10492 [(set (attr "type")
10493 (cond [(eq_attr "alternative" "1")
10494 (const_string "lea")
10495 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10497 (match_operand 2 "const1_operand" ""))
10498 (const_string "alu")
10500 (const_string "ishift")))
10501 (set_attr "mode" "SI")])
10503 ;; Convert lea to the lea pattern to avoid flags dependency.
10505 [(set (match_operand:DI 0 "register_operand" "")
10506 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10507 (match_operand:QI 2 "const_int_operand" ""))))
10508 (clobber (reg:CC FLAGS_REG))]
10509 "TARGET_64BIT && reload_completed
10510 && true_regnum (operands[0]) != true_regnum (operands[1])"
10511 [(set (match_dup 0) (zero_extend:DI
10512 (subreg:SI (mult:SI (match_dup 1)
10513 (match_dup 2)) 0)))]
10515 operands[1] = gen_lowpart (Pmode, operands[1]);
10516 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10519 ;; This pattern can't accept a variable shift count, since shifts by
10520 ;; zero don't affect the flags. We assume that shifts by constant
10521 ;; zero are optimized away.
10522 (define_insn "*ashlsi3_cmp"
10523 [(set (reg FLAGS_REG)
10525 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10526 (match_operand:QI 2 "const_1_to_31_operand" "I"))
10528 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10529 (ashift:SI (match_dup 1) (match_dup 2)))]
10530 "ix86_match_ccmode (insn, CCGOCmode)
10531 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10533 switch (get_attr_type (insn))
10536 if (operands[2] != const1_rtx)
10538 return "add{l}\t{%0, %0|%0, %0}";
10541 if (REG_P (operands[2]))
10542 return "sal{l}\t{%b2, %0|%0, %b2}";
10543 else if (operands[2] == const1_rtx
10544 && (TARGET_SHIFT1 || optimize_size))
10545 return "sal{l}\t%0";
10547 return "sal{l}\t{%2, %0|%0, %2}";
10550 [(set (attr "type")
10551 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10553 (match_operand 0 "register_operand" ""))
10554 (match_operand 2 "const1_operand" ""))
10555 (const_string "alu")
10557 (const_string "ishift")))
10558 (set_attr "mode" "SI")])
10560 (define_insn "*ashlsi3_cmp_zext"
10561 [(set (reg FLAGS_REG)
10563 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10564 (match_operand:QI 2 "const_1_to_31_operand" "I"))
10566 (set (match_operand:DI 0 "register_operand" "=r")
10567 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10568 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10569 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10571 switch (get_attr_type (insn))
10574 if (operands[2] != const1_rtx)
10576 return "add{l}\t{%k0, %k0|%k0, %k0}";
10579 if (REG_P (operands[2]))
10580 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10581 else if (operands[2] == const1_rtx
10582 && (TARGET_SHIFT1 || optimize_size))
10583 return "sal{l}\t%k0";
10585 return "sal{l}\t{%2, %k0|%k0, %2}";
10588 [(set (attr "type")
10589 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10591 (match_operand 2 "const1_operand" ""))
10592 (const_string "alu")
10594 (const_string "ishift")))
10595 (set_attr "mode" "SI")])
10597 (define_expand "ashlhi3"
10598 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10599 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10600 (match_operand:QI 2 "nonmemory_operand" "")))
10601 (clobber (reg:CC FLAGS_REG))]
10602 "TARGET_HIMODE_MATH"
10603 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10605 (define_insn "*ashlhi3_1_lea"
10606 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10607 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l")
10608 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10609 (clobber (reg:CC FLAGS_REG))]
10610 "!TARGET_PARTIAL_REG_STALL
10611 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10613 switch (get_attr_type (insn))
10618 if (operands[2] != const1_rtx)
10620 return "add{w}\t{%0, %0|%0, %0}";
10623 if (REG_P (operands[2]))
10624 return "sal{w}\t{%b2, %0|%0, %b2}";
10625 else if (operands[2] == const1_rtx
10626 && (TARGET_SHIFT1 || optimize_size))
10627 return "sal{w}\t%0";
10629 return "sal{w}\t{%2, %0|%0, %2}";
10632 [(set (attr "type")
10633 (cond [(eq_attr "alternative" "1")
10634 (const_string "lea")
10635 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10637 (match_operand 0 "register_operand" ""))
10638 (match_operand 2 "const1_operand" ""))
10639 (const_string "alu")
10641 (const_string "ishift")))
10642 (set_attr "mode" "HI,SI")])
10644 (define_insn "*ashlhi3_1"
10645 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10646 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10647 (match_operand:QI 2 "nonmemory_operand" "cI")))
10648 (clobber (reg:CC FLAGS_REG))]
10649 "TARGET_PARTIAL_REG_STALL
10650 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10652 switch (get_attr_type (insn))
10655 if (operands[2] != const1_rtx)
10657 return "add{w}\t{%0, %0|%0, %0}";
10660 if (REG_P (operands[2]))
10661 return "sal{w}\t{%b2, %0|%0, %b2}";
10662 else if (operands[2] == const1_rtx
10663 && (TARGET_SHIFT1 || optimize_size))
10664 return "sal{w}\t%0";
10666 return "sal{w}\t{%2, %0|%0, %2}";
10669 [(set (attr "type")
10670 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10672 (match_operand 0 "register_operand" ""))
10673 (match_operand 2 "const1_operand" ""))
10674 (const_string "alu")
10676 (const_string "ishift")))
10677 (set_attr "mode" "HI")])
10679 ;; This pattern can't accept a variable shift count, since shifts by
10680 ;; zero don't affect the flags. We assume that shifts by constant
10681 ;; zero are optimized away.
10682 (define_insn "*ashlhi3_cmp"
10683 [(set (reg FLAGS_REG)
10685 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10686 (match_operand:QI 2 "const_1_to_31_operand" "I"))
10688 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10689 (ashift:HI (match_dup 1) (match_dup 2)))]
10690 "ix86_match_ccmode (insn, CCGOCmode)
10691 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10693 switch (get_attr_type (insn))
10696 if (operands[2] != const1_rtx)
10698 return "add{w}\t{%0, %0|%0, %0}";
10701 if (REG_P (operands[2]))
10702 return "sal{w}\t{%b2, %0|%0, %b2}";
10703 else if (operands[2] == const1_rtx
10704 && (TARGET_SHIFT1 || optimize_size))
10705 return "sal{w}\t%0";
10707 return "sal{w}\t{%2, %0|%0, %2}";
10710 [(set (attr "type")
10711 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10713 (match_operand 0 "register_operand" ""))
10714 (match_operand 2 "const1_operand" ""))
10715 (const_string "alu")
10717 (const_string "ishift")))
10718 (set_attr "mode" "HI")])
10720 (define_expand "ashlqi3"
10721 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10722 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10723 (match_operand:QI 2 "nonmemory_operand" "")))
10724 (clobber (reg:CC FLAGS_REG))]
10725 "TARGET_QIMODE_MATH"
10726 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10728 ;; %%% Potential partial reg stall on alternative 2. What to do?
10730 (define_insn "*ashlqi3_1_lea"
10731 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10732 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l")
10733 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10734 (clobber (reg:CC FLAGS_REG))]
10735 "!TARGET_PARTIAL_REG_STALL
10736 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10738 switch (get_attr_type (insn))
10743 if (operands[2] != const1_rtx)
10745 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10746 return "add{l}\t{%k0, %k0|%k0, %k0}";
10748 return "add{b}\t{%0, %0|%0, %0}";
10751 if (REG_P (operands[2]))
10753 if (get_attr_mode (insn) == MODE_SI)
10754 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10756 return "sal{b}\t{%b2, %0|%0, %b2}";
10758 else if (operands[2] == const1_rtx
10759 && (TARGET_SHIFT1 || optimize_size))
10761 if (get_attr_mode (insn) == MODE_SI)
10762 return "sal{l}\t%0";
10764 return "sal{b}\t%0";
10768 if (get_attr_mode (insn) == MODE_SI)
10769 return "sal{l}\t{%2, %k0|%k0, %2}";
10771 return "sal{b}\t{%2, %0|%0, %2}";
10775 [(set (attr "type")
10776 (cond [(eq_attr "alternative" "2")
10777 (const_string "lea")
10778 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10780 (match_operand 0 "register_operand" ""))
10781 (match_operand 2 "const1_operand" ""))
10782 (const_string "alu")
10784 (const_string "ishift")))
10785 (set_attr "mode" "QI,SI,SI")])
10787 (define_insn "*ashlqi3_1"
10788 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10789 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
10790 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
10791 (clobber (reg:CC FLAGS_REG))]
10792 "TARGET_PARTIAL_REG_STALL
10793 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10795 switch (get_attr_type (insn))
10798 if (operands[2] != const1_rtx)
10800 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10801 return "add{l}\t{%k0, %k0|%k0, %k0}";
10803 return "add{b}\t{%0, %0|%0, %0}";
10806 if (REG_P (operands[2]))
10808 if (get_attr_mode (insn) == MODE_SI)
10809 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10811 return "sal{b}\t{%b2, %0|%0, %b2}";
10813 else if (operands[2] == const1_rtx
10814 && (TARGET_SHIFT1 || optimize_size))
10816 if (get_attr_mode (insn) == MODE_SI)
10817 return "sal{l}\t%0";
10819 return "sal{b}\t%0";
10823 if (get_attr_mode (insn) == MODE_SI)
10824 return "sal{l}\t{%2, %k0|%k0, %2}";
10826 return "sal{b}\t{%2, %0|%0, %2}";
10830 [(set (attr "type")
10831 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10833 (match_operand 0 "register_operand" ""))
10834 (match_operand 2 "const1_operand" ""))
10835 (const_string "alu")
10837 (const_string "ishift")))
10838 (set_attr "mode" "QI,SI")])
10840 ;; This pattern can't accept a variable shift count, since shifts by
10841 ;; zero don't affect the flags. We assume that shifts by constant
10842 ;; zero are optimized away.
10843 (define_insn "*ashlqi3_cmp"
10844 [(set (reg FLAGS_REG)
10846 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
10847 (match_operand:QI 2 "const_1_to_31_operand" "I"))
10849 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10850 (ashift:QI (match_dup 1) (match_dup 2)))]
10851 "ix86_match_ccmode (insn, CCGOCmode)
10852 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10854 switch (get_attr_type (insn))
10857 if (operands[2] != const1_rtx)
10859 return "add{b}\t{%0, %0|%0, %0}";
10862 if (REG_P (operands[2]))
10863 return "sal{b}\t{%b2, %0|%0, %b2}";
10864 else if (operands[2] == const1_rtx
10865 && (TARGET_SHIFT1 || optimize_size))
10866 return "sal{b}\t%0";
10868 return "sal{b}\t{%2, %0|%0, %2}";
10871 [(set (attr "type")
10872 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10874 (match_operand 0 "register_operand" ""))
10875 (match_operand 2 "const1_operand" ""))
10876 (const_string "alu")
10878 (const_string "ishift")))
10879 (set_attr "mode" "QI")])
10881 ;; See comment above `ashldi3' about how this works.
10883 (define_expand "ashrdi3"
10884 [(set (match_operand:DI 0 "shiftdi_operand" "")
10885 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
10886 (match_operand:QI 2 "nonmemory_operand" "")))]
10888 "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
10890 (define_insn "*ashrdi3_63_rex64"
10891 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
10892 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
10893 (match_operand:DI 2 "const_int_operand" "i,i")))
10894 (clobber (reg:CC FLAGS_REG))]
10895 "TARGET_64BIT && INTVAL (operands[2]) == 63
10896 && (TARGET_USE_CLTD || optimize_size)
10897 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10900 sar{q}\t{%2, %0|%0, %2}"
10901 [(set_attr "type" "imovx,ishift")
10902 (set_attr "prefix_0f" "0,*")
10903 (set_attr "length_immediate" "0,*")
10904 (set_attr "modrm" "0,1")
10905 (set_attr "mode" "DI")])
10907 (define_insn "*ashrdi3_1_one_bit_rex64"
10908 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10909 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10910 (match_operand:QI 2 "const1_operand" "")))
10911 (clobber (reg:CC FLAGS_REG))]
10912 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
10913 && (TARGET_SHIFT1 || optimize_size)"
10915 [(set_attr "type" "ishift")
10916 (set (attr "length")
10917 (if_then_else (match_operand:DI 0 "register_operand" "")
10919 (const_string "*")))])
10921 (define_insn "*ashrdi3_1_rex64"
10922 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
10923 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
10924 (match_operand:QI 2 "nonmemory_operand" "J,c")))
10925 (clobber (reg:CC FLAGS_REG))]
10926 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10928 sar{q}\t{%2, %0|%0, %2}
10929 sar{q}\t{%b2, %0|%0, %b2}"
10930 [(set_attr "type" "ishift")
10931 (set_attr "mode" "DI")])
10933 ;; This pattern can't accept a variable shift count, since shifts by
10934 ;; zero don't affect the flags. We assume that shifts by constant
10935 ;; zero are optimized away.
10936 (define_insn "*ashrdi3_one_bit_cmp_rex64"
10937 [(set (reg FLAGS_REG)
10939 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10940 (match_operand:QI 2 "const1_operand" ""))
10942 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10943 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10944 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10945 && (TARGET_SHIFT1 || optimize_size)
10946 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10948 [(set_attr "type" "ishift")
10949 (set (attr "length")
10950 (if_then_else (match_operand:DI 0 "register_operand" "")
10952 (const_string "*")))])
10954 ;; This pattern can't accept a variable shift count, since shifts by
10955 ;; zero don't affect the flags. We assume that shifts by constant
10956 ;; zero are optimized away.
10957 (define_insn "*ashrdi3_cmp_rex64"
10958 [(set (reg FLAGS_REG)
10960 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10961 (match_operand:QI 2 "const_int_operand" "n"))
10963 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10964 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10965 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10966 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10967 "sar{q}\t{%2, %0|%0, %2}"
10968 [(set_attr "type" "ishift")
10969 (set_attr "mode" "DI")])
10971 (define_insn "*ashrdi3_1"
10972 [(set (match_operand:DI 0 "register_operand" "=r")
10973 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
10974 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10975 (clobber (reg:CC FLAGS_REG))]
10978 [(set_attr "type" "multi")])
10980 ;; By default we don't ask for a scratch register, because when DImode
10981 ;; values are manipulated, registers are already at a premium. But if
10982 ;; we have one handy, we won't turn it away.
10984 [(match_scratch:SI 3 "r")
10985 (parallel [(set (match_operand:DI 0 "register_operand" "")
10986 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10987 (match_operand:QI 2 "nonmemory_operand" "")))
10988 (clobber (reg:CC FLAGS_REG))])
10990 "!TARGET_64BIT && TARGET_CMOVE"
10992 "ix86_split_ashrdi (operands, operands[3]); DONE;")
10995 [(set (match_operand:DI 0 "register_operand" "")
10996 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10997 (match_operand:QI 2 "nonmemory_operand" "")))
10998 (clobber (reg:CC FLAGS_REG))]
10999 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
11001 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11003 (define_insn "x86_shrd_1"
11004 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11005 (ior:SI (ashiftrt:SI (match_dup 0)
11006 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11007 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11008 (minus:QI (const_int 32) (match_dup 2)))))
11009 (clobber (reg:CC FLAGS_REG))]
11012 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11013 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11014 [(set_attr "type" "ishift")
11015 (set_attr "prefix_0f" "1")
11016 (set_attr "pent_pair" "np")
11017 (set_attr "mode" "SI")])
11019 (define_expand "x86_shift_adj_3"
11020 [(use (match_operand:SI 0 "register_operand" ""))
11021 (use (match_operand:SI 1 "register_operand" ""))
11022 (use (match_operand:QI 2 "register_operand" ""))]
11025 rtx label = gen_label_rtx ();
11028 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11030 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11031 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11032 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11033 gen_rtx_LABEL_REF (VOIDmode, label),
11035 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11036 JUMP_LABEL (tmp) = label;
11038 emit_move_insn (operands[0], operands[1]);
11039 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11041 emit_label (label);
11042 LABEL_NUSES (label) = 1;
11047 (define_insn "ashrsi3_31"
11048 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11049 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11050 (match_operand:SI 2 "const_int_operand" "i,i")))
11051 (clobber (reg:CC FLAGS_REG))]
11052 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11053 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11056 sar{l}\t{%2, %0|%0, %2}"
11057 [(set_attr "type" "imovx,ishift")
11058 (set_attr "prefix_0f" "0,*")
11059 (set_attr "length_immediate" "0,*")
11060 (set_attr "modrm" "0,1")
11061 (set_attr "mode" "SI")])
11063 (define_insn "*ashrsi3_31_zext"
11064 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11065 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11066 (match_operand:SI 2 "const_int_operand" "i,i"))))
11067 (clobber (reg:CC FLAGS_REG))]
11068 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11069 && INTVAL (operands[2]) == 31
11070 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11073 sar{l}\t{%2, %k0|%k0, %2}"
11074 [(set_attr "type" "imovx,ishift")
11075 (set_attr "prefix_0f" "0,*")
11076 (set_attr "length_immediate" "0,*")
11077 (set_attr "modrm" "0,1")
11078 (set_attr "mode" "SI")])
11080 (define_expand "ashrsi3"
11081 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11082 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11083 (match_operand:QI 2 "nonmemory_operand" "")))
11084 (clobber (reg:CC FLAGS_REG))]
11086 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11088 (define_insn "*ashrsi3_1_one_bit"
11089 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11090 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11091 (match_operand:QI 2 "const1_operand" "")))
11092 (clobber (reg:CC FLAGS_REG))]
11093 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11094 && (TARGET_SHIFT1 || optimize_size)"
11096 [(set_attr "type" "ishift")
11097 (set (attr "length")
11098 (if_then_else (match_operand:SI 0 "register_operand" "")
11100 (const_string "*")))])
11102 (define_insn "*ashrsi3_1_one_bit_zext"
11103 [(set (match_operand:DI 0 "register_operand" "=r")
11104 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11105 (match_operand:QI 2 "const1_operand" ""))))
11106 (clobber (reg:CC FLAGS_REG))]
11107 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11108 && (TARGET_SHIFT1 || optimize_size)"
11110 [(set_attr "type" "ishift")
11111 (set_attr "length" "2")])
11113 (define_insn "*ashrsi3_1"
11114 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11115 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11116 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11117 (clobber (reg:CC FLAGS_REG))]
11118 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11120 sar{l}\t{%2, %0|%0, %2}
11121 sar{l}\t{%b2, %0|%0, %b2}"
11122 [(set_attr "type" "ishift")
11123 (set_attr "mode" "SI")])
11125 (define_insn "*ashrsi3_1_zext"
11126 [(set (match_operand:DI 0 "register_operand" "=r,r")
11127 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11128 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11129 (clobber (reg:CC FLAGS_REG))]
11130 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11132 sar{l}\t{%2, %k0|%k0, %2}
11133 sar{l}\t{%b2, %k0|%k0, %b2}"
11134 [(set_attr "type" "ishift")
11135 (set_attr "mode" "SI")])
11137 ;; This pattern can't accept a variable shift count, since shifts by
11138 ;; zero don't affect the flags. We assume that shifts by constant
11139 ;; zero are optimized away.
11140 (define_insn "*ashrsi3_one_bit_cmp"
11141 [(set (reg FLAGS_REG)
11143 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11144 (match_operand:QI 2 "const1_operand" ""))
11146 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11147 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11148 "ix86_match_ccmode (insn, CCGOCmode)
11149 && (TARGET_SHIFT1 || optimize_size)
11150 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11152 [(set_attr "type" "ishift")
11153 (set (attr "length")
11154 (if_then_else (match_operand:SI 0 "register_operand" "")
11156 (const_string "*")))])
11158 (define_insn "*ashrsi3_one_bit_cmp_zext"
11159 [(set (reg FLAGS_REG)
11161 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11162 (match_operand:QI 2 "const1_operand" ""))
11164 (set (match_operand:DI 0 "register_operand" "=r")
11165 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11166 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11167 && (TARGET_SHIFT1 || optimize_size)
11168 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11170 [(set_attr "type" "ishift")
11171 (set_attr "length" "2")])
11173 ;; This pattern can't accept a variable shift count, since shifts by
11174 ;; zero don't affect the flags. We assume that shifts by constant
11175 ;; zero are optimized away.
11176 (define_insn "*ashrsi3_cmp"
11177 [(set (reg FLAGS_REG)
11179 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11180 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11182 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11183 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11184 "ix86_match_ccmode (insn, CCGOCmode)
11185 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11186 "sar{l}\t{%2, %0|%0, %2}"
11187 [(set_attr "type" "ishift")
11188 (set_attr "mode" "SI")])
11190 (define_insn "*ashrsi3_cmp_zext"
11191 [(set (reg FLAGS_REG)
11193 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11194 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11196 (set (match_operand:DI 0 "register_operand" "=r")
11197 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11198 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11199 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11200 "sar{l}\t{%2, %k0|%k0, %2}"
11201 [(set_attr "type" "ishift")
11202 (set_attr "mode" "SI")])
11204 (define_expand "ashrhi3"
11205 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11206 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11207 (match_operand:QI 2 "nonmemory_operand" "")))
11208 (clobber (reg:CC FLAGS_REG))]
11209 "TARGET_HIMODE_MATH"
11210 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11212 (define_insn "*ashrhi3_1_one_bit"
11213 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11214 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11215 (match_operand:QI 2 "const1_operand" "")))
11216 (clobber (reg:CC FLAGS_REG))]
11217 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11218 && (TARGET_SHIFT1 || optimize_size)"
11220 [(set_attr "type" "ishift")
11221 (set (attr "length")
11222 (if_then_else (match_operand 0 "register_operand" "")
11224 (const_string "*")))])
11226 (define_insn "*ashrhi3_1"
11227 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11228 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11229 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11230 (clobber (reg:CC FLAGS_REG))]
11231 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11233 sar{w}\t{%2, %0|%0, %2}
11234 sar{w}\t{%b2, %0|%0, %b2}"
11235 [(set_attr "type" "ishift")
11236 (set_attr "mode" "HI")])
11238 ;; This pattern can't accept a variable shift count, since shifts by
11239 ;; zero don't affect the flags. We assume that shifts by constant
11240 ;; zero are optimized away.
11241 (define_insn "*ashrhi3_one_bit_cmp"
11242 [(set (reg FLAGS_REG)
11244 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11245 (match_operand:QI 2 "const1_operand" ""))
11247 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11248 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11249 "ix86_match_ccmode (insn, CCGOCmode)
11250 && (TARGET_SHIFT1 || optimize_size)
11251 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11253 [(set_attr "type" "ishift")
11254 (set (attr "length")
11255 (if_then_else (match_operand 0 "register_operand" "")
11257 (const_string "*")))])
11259 ;; This pattern can't accept a variable shift count, since shifts by
11260 ;; zero don't affect the flags. We assume that shifts by constant
11261 ;; zero are optimized away.
11262 (define_insn "*ashrhi3_cmp"
11263 [(set (reg FLAGS_REG)
11265 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11266 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11268 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11269 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11270 "ix86_match_ccmode (insn, CCGOCmode)
11271 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11272 "sar{w}\t{%2, %0|%0, %2}"
11273 [(set_attr "type" "ishift")
11274 (set_attr "mode" "HI")])
11276 (define_expand "ashrqi3"
11277 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11278 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11279 (match_operand:QI 2 "nonmemory_operand" "")))
11280 (clobber (reg:CC FLAGS_REG))]
11281 "TARGET_QIMODE_MATH"
11282 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11284 (define_insn "*ashrqi3_1_one_bit"
11285 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11286 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11287 (match_operand:QI 2 "const1_operand" "")))
11288 (clobber (reg:CC FLAGS_REG))]
11289 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11290 && (TARGET_SHIFT1 || optimize_size)"
11292 [(set_attr "type" "ishift")
11293 (set (attr "length")
11294 (if_then_else (match_operand 0 "register_operand" "")
11296 (const_string "*")))])
11298 (define_insn "*ashrqi3_1_one_bit_slp"
11299 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11300 (ashiftrt:QI (match_dup 0)
11301 (match_operand:QI 1 "const1_operand" "")))
11302 (clobber (reg:CC FLAGS_REG))]
11303 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11304 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11305 && (TARGET_SHIFT1 || optimize_size)"
11307 [(set_attr "type" "ishift1")
11308 (set (attr "length")
11309 (if_then_else (match_operand 0 "register_operand" "")
11311 (const_string "*")))])
11313 (define_insn "*ashrqi3_1"
11314 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11315 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11316 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11317 (clobber (reg:CC FLAGS_REG))]
11318 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11320 sar{b}\t{%2, %0|%0, %2}
11321 sar{b}\t{%b2, %0|%0, %b2}"
11322 [(set_attr "type" "ishift")
11323 (set_attr "mode" "QI")])
11325 (define_insn "*ashrqi3_1_slp"
11326 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11327 (ashiftrt:QI (match_dup 0)
11328 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11329 (clobber (reg:CC FLAGS_REG))]
11330 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11331 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11333 sar{b}\t{%1, %0|%0, %1}
11334 sar{b}\t{%b1, %0|%0, %b1}"
11335 [(set_attr "type" "ishift1")
11336 (set_attr "mode" "QI")])
11338 ;; This pattern can't accept a variable shift count, since shifts by
11339 ;; zero don't affect the flags. We assume that shifts by constant
11340 ;; zero are optimized away.
11341 (define_insn "*ashrqi3_one_bit_cmp"
11342 [(set (reg FLAGS_REG)
11344 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11345 (match_operand:QI 2 "const1_operand" "I"))
11347 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11348 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11349 "ix86_match_ccmode (insn, CCGOCmode)
11350 && (TARGET_SHIFT1 || optimize_size)
11351 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11353 [(set_attr "type" "ishift")
11354 (set (attr "length")
11355 (if_then_else (match_operand 0 "register_operand" "")
11357 (const_string "*")))])
11359 ;; This pattern can't accept a variable shift count, since shifts by
11360 ;; zero don't affect the flags. We assume that shifts by constant
11361 ;; zero are optimized away.
11362 (define_insn "*ashrqi3_cmp"
11363 [(set (reg FLAGS_REG)
11365 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11366 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11368 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11369 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11370 "ix86_match_ccmode (insn, CCGOCmode)
11371 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11372 "sar{b}\t{%2, %0|%0, %2}"
11373 [(set_attr "type" "ishift")
11374 (set_attr "mode" "QI")])
11376 ;; Logical shift instructions
11378 ;; See comment above `ashldi3' about how this works.
11380 (define_expand "lshrdi3"
11381 [(set (match_operand:DI 0 "shiftdi_operand" "")
11382 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11383 (match_operand:QI 2 "nonmemory_operand" "")))]
11385 "ix86_expand_binary_operator (LSHIFTRT, DImode, operands); DONE;")
11387 (define_insn "*lshrdi3_1_one_bit_rex64"
11388 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11389 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11390 (match_operand:QI 2 "const1_operand" "")))
11391 (clobber (reg:CC FLAGS_REG))]
11392 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11393 && (TARGET_SHIFT1 || optimize_size)"
11395 [(set_attr "type" "ishift")
11396 (set (attr "length")
11397 (if_then_else (match_operand:DI 0 "register_operand" "")
11399 (const_string "*")))])
11401 (define_insn "*lshrdi3_1_rex64"
11402 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11403 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11404 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11405 (clobber (reg:CC FLAGS_REG))]
11406 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11408 shr{q}\t{%2, %0|%0, %2}
11409 shr{q}\t{%b2, %0|%0, %b2}"
11410 [(set_attr "type" "ishift")
11411 (set_attr "mode" "DI")])
11413 ;; This pattern can't accept a variable shift count, since shifts by
11414 ;; zero don't affect the flags. We assume that shifts by constant
11415 ;; zero are optimized away.
11416 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11417 [(set (reg FLAGS_REG)
11419 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11420 (match_operand:QI 2 "const1_operand" ""))
11422 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11423 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11424 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11425 && (TARGET_SHIFT1 || optimize_size)
11426 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11428 [(set_attr "type" "ishift")
11429 (set (attr "length")
11430 (if_then_else (match_operand:DI 0 "register_operand" "")
11432 (const_string "*")))])
11434 ;; This pattern can't accept a variable shift count, since shifts by
11435 ;; zero don't affect the flags. We assume that shifts by constant
11436 ;; zero are optimized away.
11437 (define_insn "*lshrdi3_cmp_rex64"
11438 [(set (reg FLAGS_REG)
11440 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11441 (match_operand:QI 2 "const_int_operand" "e"))
11443 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11444 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11445 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11446 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11447 "shr{q}\t{%2, %0|%0, %2}"
11448 [(set_attr "type" "ishift")
11449 (set_attr "mode" "DI")])
11451 (define_insn "*lshrdi3_1"
11452 [(set (match_operand:DI 0 "register_operand" "=r")
11453 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11454 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11455 (clobber (reg:CC FLAGS_REG))]
11458 [(set_attr "type" "multi")])
11460 ;; By default we don't ask for a scratch register, because when DImode
11461 ;; values are manipulated, registers are already at a premium. But if
11462 ;; we have one handy, we won't turn it away.
11464 [(match_scratch:SI 3 "r")
11465 (parallel [(set (match_operand:DI 0 "register_operand" "")
11466 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11467 (match_operand:QI 2 "nonmemory_operand" "")))
11468 (clobber (reg:CC FLAGS_REG))])
11470 "!TARGET_64BIT && TARGET_CMOVE"
11472 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11475 [(set (match_operand:DI 0 "register_operand" "")
11476 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11477 (match_operand:QI 2 "nonmemory_operand" "")))
11478 (clobber (reg:CC FLAGS_REG))]
11479 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
11481 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11483 (define_expand "lshrsi3"
11484 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11485 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11486 (match_operand:QI 2 "nonmemory_operand" "")))
11487 (clobber (reg:CC FLAGS_REG))]
11489 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11491 (define_insn "*lshrsi3_1_one_bit"
11492 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11493 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11494 (match_operand:QI 2 "const1_operand" "")))
11495 (clobber (reg:CC FLAGS_REG))]
11496 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11497 && (TARGET_SHIFT1 || optimize_size)"
11499 [(set_attr "type" "ishift")
11500 (set (attr "length")
11501 (if_then_else (match_operand:SI 0 "register_operand" "")
11503 (const_string "*")))])
11505 (define_insn "*lshrsi3_1_one_bit_zext"
11506 [(set (match_operand:DI 0 "register_operand" "=r")
11507 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11508 (match_operand:QI 2 "const1_operand" "")))
11509 (clobber (reg:CC FLAGS_REG))]
11510 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11511 && (TARGET_SHIFT1 || optimize_size)"
11513 [(set_attr "type" "ishift")
11514 (set_attr "length" "2")])
11516 (define_insn "*lshrsi3_1"
11517 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11518 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11519 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11520 (clobber (reg:CC FLAGS_REG))]
11521 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11523 shr{l}\t{%2, %0|%0, %2}
11524 shr{l}\t{%b2, %0|%0, %b2}"
11525 [(set_attr "type" "ishift")
11526 (set_attr "mode" "SI")])
11528 (define_insn "*lshrsi3_1_zext"
11529 [(set (match_operand:DI 0 "register_operand" "=r,r")
11531 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11532 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11533 (clobber (reg:CC FLAGS_REG))]
11534 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11536 shr{l}\t{%2, %k0|%k0, %2}
11537 shr{l}\t{%b2, %k0|%k0, %b2}"
11538 [(set_attr "type" "ishift")
11539 (set_attr "mode" "SI")])
11541 ;; This pattern can't accept a variable shift count, since shifts by
11542 ;; zero don't affect the flags. We assume that shifts by constant
11543 ;; zero are optimized away.
11544 (define_insn "*lshrsi3_one_bit_cmp"
11545 [(set (reg FLAGS_REG)
11547 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11548 (match_operand:QI 2 "const1_operand" ""))
11550 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11551 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11552 "ix86_match_ccmode (insn, CCGOCmode)
11553 && (TARGET_SHIFT1 || optimize_size)
11554 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11556 [(set_attr "type" "ishift")
11557 (set (attr "length")
11558 (if_then_else (match_operand:SI 0 "register_operand" "")
11560 (const_string "*")))])
11562 (define_insn "*lshrsi3_cmp_one_bit_zext"
11563 [(set (reg FLAGS_REG)
11565 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11566 (match_operand:QI 2 "const1_operand" ""))
11568 (set (match_operand:DI 0 "register_operand" "=r")
11569 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11570 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11571 && (TARGET_SHIFT1 || optimize_size)
11572 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11574 [(set_attr "type" "ishift")
11575 (set_attr "length" "2")])
11577 ;; This pattern can't accept a variable shift count, since shifts by
11578 ;; zero don't affect the flags. We assume that shifts by constant
11579 ;; zero are optimized away.
11580 (define_insn "*lshrsi3_cmp"
11581 [(set (reg FLAGS_REG)
11583 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11584 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11586 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11587 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11588 "ix86_match_ccmode (insn, CCGOCmode)
11589 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11590 "shr{l}\t{%2, %0|%0, %2}"
11591 [(set_attr "type" "ishift")
11592 (set_attr "mode" "SI")])
11594 (define_insn "*lshrsi3_cmp_zext"
11595 [(set (reg FLAGS_REG)
11597 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11598 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11600 (set (match_operand:DI 0 "register_operand" "=r")
11601 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11602 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11603 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11604 "shr{l}\t{%2, %k0|%k0, %2}"
11605 [(set_attr "type" "ishift")
11606 (set_attr "mode" "SI")])
11608 (define_expand "lshrhi3"
11609 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11610 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11611 (match_operand:QI 2 "nonmemory_operand" "")))
11612 (clobber (reg:CC FLAGS_REG))]
11613 "TARGET_HIMODE_MATH"
11614 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11616 (define_insn "*lshrhi3_1_one_bit"
11617 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11618 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11619 (match_operand:QI 2 "const1_operand" "")))
11620 (clobber (reg:CC FLAGS_REG))]
11621 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11622 && (TARGET_SHIFT1 || optimize_size)"
11624 [(set_attr "type" "ishift")
11625 (set (attr "length")
11626 (if_then_else (match_operand 0 "register_operand" "")
11628 (const_string "*")))])
11630 (define_insn "*lshrhi3_1"
11631 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11632 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11633 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11634 (clobber (reg:CC FLAGS_REG))]
11635 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11637 shr{w}\t{%2, %0|%0, %2}
11638 shr{w}\t{%b2, %0|%0, %b2}"
11639 [(set_attr "type" "ishift")
11640 (set_attr "mode" "HI")])
11642 ;; This pattern can't accept a variable shift count, since shifts by
11643 ;; zero don't affect the flags. We assume that shifts by constant
11644 ;; zero are optimized away.
11645 (define_insn "*lshrhi3_one_bit_cmp"
11646 [(set (reg FLAGS_REG)
11648 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11649 (match_operand:QI 2 "const1_operand" ""))
11651 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11652 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11653 "ix86_match_ccmode (insn, CCGOCmode)
11654 && (TARGET_SHIFT1 || optimize_size)
11655 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11657 [(set_attr "type" "ishift")
11658 (set (attr "length")
11659 (if_then_else (match_operand:SI 0 "register_operand" "")
11661 (const_string "*")))])
11663 ;; This pattern can't accept a variable shift count, since shifts by
11664 ;; zero don't affect the flags. We assume that shifts by constant
11665 ;; zero are optimized away.
11666 (define_insn "*lshrhi3_cmp"
11667 [(set (reg FLAGS_REG)
11669 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11670 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11672 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11673 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11674 "ix86_match_ccmode (insn, CCGOCmode)
11675 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11676 "shr{w}\t{%2, %0|%0, %2}"
11677 [(set_attr "type" "ishift")
11678 (set_attr "mode" "HI")])
11680 (define_expand "lshrqi3"
11681 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11682 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11683 (match_operand:QI 2 "nonmemory_operand" "")))
11684 (clobber (reg:CC FLAGS_REG))]
11685 "TARGET_QIMODE_MATH"
11686 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11688 (define_insn "*lshrqi3_1_one_bit"
11689 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11690 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11691 (match_operand:QI 2 "const1_operand" "")))
11692 (clobber (reg:CC FLAGS_REG))]
11693 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11694 && (TARGET_SHIFT1 || optimize_size)"
11696 [(set_attr "type" "ishift")
11697 (set (attr "length")
11698 (if_then_else (match_operand 0 "register_operand" "")
11700 (const_string "*")))])
11702 (define_insn "*lshrqi3_1_one_bit_slp"
11703 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11704 (lshiftrt:QI (match_dup 0)
11705 (match_operand:QI 1 "const1_operand" "")))
11706 (clobber (reg:CC FLAGS_REG))]
11707 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11708 && (TARGET_SHIFT1 || optimize_size)"
11710 [(set_attr "type" "ishift1")
11711 (set (attr "length")
11712 (if_then_else (match_operand 0 "register_operand" "")
11714 (const_string "*")))])
11716 (define_insn "*lshrqi3_1"
11717 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11718 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11719 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11720 (clobber (reg:CC FLAGS_REG))]
11721 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11723 shr{b}\t{%2, %0|%0, %2}
11724 shr{b}\t{%b2, %0|%0, %b2}"
11725 [(set_attr "type" "ishift")
11726 (set_attr "mode" "QI")])
11728 (define_insn "*lshrqi3_1_slp"
11729 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11730 (lshiftrt:QI (match_dup 0)
11731 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11732 (clobber (reg:CC FLAGS_REG))]
11733 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11734 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11736 shr{b}\t{%1, %0|%0, %1}
11737 shr{b}\t{%b1, %0|%0, %b1}"
11738 [(set_attr "type" "ishift1")
11739 (set_attr "mode" "QI")])
11741 ;; This pattern can't accept a variable shift count, since shifts by
11742 ;; zero don't affect the flags. We assume that shifts by constant
11743 ;; zero are optimized away.
11744 (define_insn "*lshrqi2_one_bit_cmp"
11745 [(set (reg FLAGS_REG)
11747 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11748 (match_operand:QI 2 "const1_operand" ""))
11750 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11751 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11752 "ix86_match_ccmode (insn, CCGOCmode)
11753 && (TARGET_SHIFT1 || optimize_size)
11754 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11756 [(set_attr "type" "ishift")
11757 (set (attr "length")
11758 (if_then_else (match_operand:SI 0 "register_operand" "")
11760 (const_string "*")))])
11762 ;; This pattern can't accept a variable shift count, since shifts by
11763 ;; zero don't affect the flags. We assume that shifts by constant
11764 ;; zero are optimized away.
11765 (define_insn "*lshrqi2_cmp"
11766 [(set (reg FLAGS_REG)
11768 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11769 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11771 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11772 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11773 "ix86_match_ccmode (insn, CCGOCmode)
11774 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11775 "shr{b}\t{%2, %0|%0, %2}"
11776 [(set_attr "type" "ishift")
11777 (set_attr "mode" "QI")])
11779 ;; Rotate instructions
11781 (define_expand "rotldi3"
11782 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11783 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
11784 (match_operand:QI 2 "nonmemory_operand" "")))
11785 (clobber (reg:CC FLAGS_REG))]
11787 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
11789 (define_insn "*rotlsi3_1_one_bit_rex64"
11790 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11791 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11792 (match_operand:QI 2 "const1_operand" "")))
11793 (clobber (reg:CC FLAGS_REG))]
11794 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
11795 && (TARGET_SHIFT1 || optimize_size)"
11797 [(set_attr "type" "rotate")
11798 (set (attr "length")
11799 (if_then_else (match_operand:DI 0 "register_operand" "")
11801 (const_string "*")))])
11803 (define_insn "*rotldi3_1_rex64"
11804 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11805 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11806 (match_operand:QI 2 "nonmemory_operand" "e,c")))
11807 (clobber (reg:CC FLAGS_REG))]
11808 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
11810 rol{q}\t{%2, %0|%0, %2}
11811 rol{q}\t{%b2, %0|%0, %b2}"
11812 [(set_attr "type" "rotate")
11813 (set_attr "mode" "DI")])
11815 (define_expand "rotlsi3"
11816 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11817 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
11818 (match_operand:QI 2 "nonmemory_operand" "")))
11819 (clobber (reg:CC FLAGS_REG))]
11821 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
11823 (define_insn "*rotlsi3_1_one_bit"
11824 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11825 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11826 (match_operand:QI 2 "const1_operand" "")))
11827 (clobber (reg:CC FLAGS_REG))]
11828 "ix86_binary_operator_ok (ROTATE, SImode, operands)
11829 && (TARGET_SHIFT1 || optimize_size)"
11831 [(set_attr "type" "rotate")
11832 (set (attr "length")
11833 (if_then_else (match_operand:SI 0 "register_operand" "")
11835 (const_string "*")))])
11837 (define_insn "*rotlsi3_1_one_bit_zext"
11838 [(set (match_operand:DI 0 "register_operand" "=r")
11840 (rotate:SI (match_operand:SI 1 "register_operand" "0")
11841 (match_operand:QI 2 "const1_operand" ""))))
11842 (clobber (reg:CC FLAGS_REG))]
11843 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
11844 && (TARGET_SHIFT1 || optimize_size)"
11846 [(set_attr "type" "rotate")
11847 (set_attr "length" "2")])
11849 (define_insn "*rotlsi3_1"
11850 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11851 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11852 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11853 (clobber (reg:CC FLAGS_REG))]
11854 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
11856 rol{l}\t{%2, %0|%0, %2}
11857 rol{l}\t{%b2, %0|%0, %b2}"
11858 [(set_attr "type" "rotate")
11859 (set_attr "mode" "SI")])
11861 (define_insn "*rotlsi3_1_zext"
11862 [(set (match_operand:DI 0 "register_operand" "=r,r")
11864 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
11865 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11866 (clobber (reg:CC FLAGS_REG))]
11867 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
11869 rol{l}\t{%2, %k0|%k0, %2}
11870 rol{l}\t{%b2, %k0|%k0, %b2}"
11871 [(set_attr "type" "rotate")
11872 (set_attr "mode" "SI")])
11874 (define_expand "rotlhi3"
11875 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11876 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
11877 (match_operand:QI 2 "nonmemory_operand" "")))
11878 (clobber (reg:CC FLAGS_REG))]
11879 "TARGET_HIMODE_MATH"
11880 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
11882 (define_insn "*rotlhi3_1_one_bit"
11883 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11884 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11885 (match_operand:QI 2 "const1_operand" "")))
11886 (clobber (reg:CC FLAGS_REG))]
11887 "ix86_binary_operator_ok (ROTATE, HImode, operands)
11888 && (TARGET_SHIFT1 || optimize_size)"
11890 [(set_attr "type" "rotate")
11891 (set (attr "length")
11892 (if_then_else (match_operand 0 "register_operand" "")
11894 (const_string "*")))])
11896 (define_insn "*rotlhi3_1"
11897 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11898 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11899 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11900 (clobber (reg:CC FLAGS_REG))]
11901 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
11903 rol{w}\t{%2, %0|%0, %2}
11904 rol{w}\t{%b2, %0|%0, %b2}"
11905 [(set_attr "type" "rotate")
11906 (set_attr "mode" "HI")])
11908 (define_expand "rotlqi3"
11909 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11910 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
11911 (match_operand:QI 2 "nonmemory_operand" "")))
11912 (clobber (reg:CC FLAGS_REG))]
11913 "TARGET_QIMODE_MATH"
11914 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
11916 (define_insn "*rotlqi3_1_one_bit_slp"
11917 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11918 (rotate:QI (match_dup 0)
11919 (match_operand:QI 1 "const1_operand" "")))
11920 (clobber (reg:CC FLAGS_REG))]
11921 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11922 && (TARGET_SHIFT1 || optimize_size)"
11924 [(set_attr "type" "rotate1")
11925 (set (attr "length")
11926 (if_then_else (match_operand 0 "register_operand" "")
11928 (const_string "*")))])
11930 (define_insn "*rotlqi3_1_one_bit"
11931 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11932 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11933 (match_operand:QI 2 "const1_operand" "")))
11934 (clobber (reg:CC FLAGS_REG))]
11935 "ix86_binary_operator_ok (ROTATE, QImode, operands)
11936 && (TARGET_SHIFT1 || optimize_size)"
11938 [(set_attr "type" "rotate")
11939 (set (attr "length")
11940 (if_then_else (match_operand 0 "register_operand" "")
11942 (const_string "*")))])
11944 (define_insn "*rotlqi3_1_slp"
11945 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11946 (rotate:QI (match_dup 0)
11947 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11948 (clobber (reg:CC FLAGS_REG))]
11949 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11950 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11952 rol{b}\t{%1, %0|%0, %1}
11953 rol{b}\t{%b1, %0|%0, %b1}"
11954 [(set_attr "type" "rotate1")
11955 (set_attr "mode" "QI")])
11957 (define_insn "*rotlqi3_1"
11958 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11959 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11960 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11961 (clobber (reg:CC FLAGS_REG))]
11962 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
11964 rol{b}\t{%2, %0|%0, %2}
11965 rol{b}\t{%b2, %0|%0, %b2}"
11966 [(set_attr "type" "rotate")
11967 (set_attr "mode" "QI")])
11969 (define_expand "rotrdi3"
11970 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11971 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
11972 (match_operand:QI 2 "nonmemory_operand" "")))
11973 (clobber (reg:CC FLAGS_REG))]
11975 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
11977 (define_insn "*rotrdi3_1_one_bit_rex64"
11978 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11979 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11980 (match_operand:QI 2 "const1_operand" "")))
11981 (clobber (reg:CC FLAGS_REG))]
11982 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
11983 && (TARGET_SHIFT1 || optimize_size)"
11985 [(set_attr "type" "rotate")
11986 (set (attr "length")
11987 (if_then_else (match_operand:DI 0 "register_operand" "")
11989 (const_string "*")))])
11991 (define_insn "*rotrdi3_1_rex64"
11992 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11993 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11994 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11995 (clobber (reg:CC FLAGS_REG))]
11996 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
11998 ror{q}\t{%2, %0|%0, %2}
11999 ror{q}\t{%b2, %0|%0, %b2}"
12000 [(set_attr "type" "rotate")
12001 (set_attr "mode" "DI")])
12003 (define_expand "rotrsi3"
12004 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12005 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12006 (match_operand:QI 2 "nonmemory_operand" "")))
12007 (clobber (reg:CC FLAGS_REG))]
12009 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12011 (define_insn "*rotrsi3_1_one_bit"
12012 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12013 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12014 (match_operand:QI 2 "const1_operand" "")))
12015 (clobber (reg:CC FLAGS_REG))]
12016 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12017 && (TARGET_SHIFT1 || optimize_size)"
12019 [(set_attr "type" "rotate")
12020 (set (attr "length")
12021 (if_then_else (match_operand:SI 0 "register_operand" "")
12023 (const_string "*")))])
12025 (define_insn "*rotrsi3_1_one_bit_zext"
12026 [(set (match_operand:DI 0 "register_operand" "=r")
12028 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12029 (match_operand:QI 2 "const1_operand" ""))))
12030 (clobber (reg:CC FLAGS_REG))]
12031 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12032 && (TARGET_SHIFT1 || optimize_size)"
12034 [(set_attr "type" "rotate")
12035 (set (attr "length")
12036 (if_then_else (match_operand:SI 0 "register_operand" "")
12038 (const_string "*")))])
12040 (define_insn "*rotrsi3_1"
12041 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12042 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12043 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12044 (clobber (reg:CC FLAGS_REG))]
12045 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12047 ror{l}\t{%2, %0|%0, %2}
12048 ror{l}\t{%b2, %0|%0, %b2}"
12049 [(set_attr "type" "rotate")
12050 (set_attr "mode" "SI")])
12052 (define_insn "*rotrsi3_1_zext"
12053 [(set (match_operand:DI 0 "register_operand" "=r,r")
12055 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12056 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12057 (clobber (reg:CC FLAGS_REG))]
12058 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12060 ror{l}\t{%2, %k0|%k0, %2}
12061 ror{l}\t{%b2, %k0|%k0, %b2}"
12062 [(set_attr "type" "rotate")
12063 (set_attr "mode" "SI")])
12065 (define_expand "rotrhi3"
12066 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12067 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12068 (match_operand:QI 2 "nonmemory_operand" "")))
12069 (clobber (reg:CC FLAGS_REG))]
12070 "TARGET_HIMODE_MATH"
12071 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12073 (define_insn "*rotrhi3_one_bit"
12074 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12075 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12076 (match_operand:QI 2 "const1_operand" "")))
12077 (clobber (reg:CC FLAGS_REG))]
12078 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12079 && (TARGET_SHIFT1 || optimize_size)"
12081 [(set_attr "type" "rotate")
12082 (set (attr "length")
12083 (if_then_else (match_operand 0 "register_operand" "")
12085 (const_string "*")))])
12087 (define_insn "*rotrhi3"
12088 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12089 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12090 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12091 (clobber (reg:CC FLAGS_REG))]
12092 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12094 ror{w}\t{%2, %0|%0, %2}
12095 ror{w}\t{%b2, %0|%0, %b2}"
12096 [(set_attr "type" "rotate")
12097 (set_attr "mode" "HI")])
12099 (define_expand "rotrqi3"
12100 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12101 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12102 (match_operand:QI 2 "nonmemory_operand" "")))
12103 (clobber (reg:CC FLAGS_REG))]
12104 "TARGET_QIMODE_MATH"
12105 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12107 (define_insn "*rotrqi3_1_one_bit"
12108 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12109 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12110 (match_operand:QI 2 "const1_operand" "")))
12111 (clobber (reg:CC FLAGS_REG))]
12112 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12113 && (TARGET_SHIFT1 || optimize_size)"
12115 [(set_attr "type" "rotate")
12116 (set (attr "length")
12117 (if_then_else (match_operand 0 "register_operand" "")
12119 (const_string "*")))])
12121 (define_insn "*rotrqi3_1_one_bit_slp"
12122 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12123 (rotatert:QI (match_dup 0)
12124 (match_operand:QI 1 "const1_operand" "")))
12125 (clobber (reg:CC FLAGS_REG))]
12126 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12127 && (TARGET_SHIFT1 || optimize_size)"
12129 [(set_attr "type" "rotate1")
12130 (set (attr "length")
12131 (if_then_else (match_operand 0 "register_operand" "")
12133 (const_string "*")))])
12135 (define_insn "*rotrqi3_1"
12136 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12137 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12138 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12139 (clobber (reg:CC FLAGS_REG))]
12140 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12142 ror{b}\t{%2, %0|%0, %2}
12143 ror{b}\t{%b2, %0|%0, %b2}"
12144 [(set_attr "type" "rotate")
12145 (set_attr "mode" "QI")])
12147 (define_insn "*rotrqi3_1_slp"
12148 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12149 (rotatert:QI (match_dup 0)
12150 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12151 (clobber (reg:CC FLAGS_REG))]
12152 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12153 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12155 ror{b}\t{%1, %0|%0, %1}
12156 ror{b}\t{%b1, %0|%0, %b1}"
12157 [(set_attr "type" "rotate1")
12158 (set_attr "mode" "QI")])
12160 ;; Bit set / bit test instructions
12162 (define_expand "extv"
12163 [(set (match_operand:SI 0 "register_operand" "")
12164 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12165 (match_operand:SI 2 "immediate_operand" "")
12166 (match_operand:SI 3 "immediate_operand" "")))]
12169 /* Handle extractions from %ah et al. */
12170 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12173 /* From mips.md: extract_bit_field doesn't verify that our source
12174 matches the predicate, so check it again here. */
12175 if (! ext_register_operand (operands[1], VOIDmode))
12179 (define_expand "extzv"
12180 [(set (match_operand:SI 0 "register_operand" "")
12181 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12182 (match_operand:SI 2 "immediate_operand" "")
12183 (match_operand:SI 3 "immediate_operand" "")))]
12186 /* Handle extractions from %ah et al. */
12187 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12190 /* From mips.md: extract_bit_field doesn't verify that our source
12191 matches the predicate, so check it again here. */
12192 if (! ext_register_operand (operands[1], VOIDmode))
12196 (define_expand "insv"
12197 [(set (zero_extract (match_operand 0 "ext_register_operand" "")
12198 (match_operand 1 "immediate_operand" "")
12199 (match_operand 2 "immediate_operand" ""))
12200 (match_operand 3 "register_operand" ""))]
12203 /* Handle extractions from %ah et al. */
12204 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12207 /* From mips.md: insert_bit_field doesn't verify that our source
12208 matches the predicate, so check it again here. */
12209 if (! ext_register_operand (operands[0], VOIDmode))
12213 emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
12215 emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
12220 ;; %%% bts, btr, btc, bt.
12221 ;; In general these instructions are *slow* when applied to memory,
12222 ;; since they enforce atomic operation. When applied to registers,
12223 ;; it depends on the cpu implementation. They're never faster than
12224 ;; the corresponding and/ior/xor operations, so with 32-bit there's
12225 ;; no point. But in 64-bit, we can't hold the relevant immediates
12226 ;; within the instruction itself, so operating on bits in the high
12227 ;; 32-bits of a register becomes easier.
12229 ;; These are slow on Nocona, but fast on Athlon64. We do require the use
12230 ;; of btrq and btcq for corner cases of post-reload expansion of absdf and
12231 ;; negdf respectively, so they can never be disabled entirely.
12233 (define_insn "*btsq"
12234 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12236 (match_operand:DI 1 "const_0_to_63_operand" ""))
12238 (clobber (reg:CC FLAGS_REG))]
12239 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12241 [(set_attr "type" "alu1")])
12243 (define_insn "*btrq"
12244 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12246 (match_operand:DI 1 "const_0_to_63_operand" ""))
12248 (clobber (reg:CC FLAGS_REG))]
12249 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12251 [(set_attr "type" "alu1")])
12253 (define_insn "*btcq"
12254 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12256 (match_operand:DI 1 "const_0_to_63_operand" ""))
12257 (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
12258 (clobber (reg:CC FLAGS_REG))]
12259 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12261 [(set_attr "type" "alu1")])
12263 ;; Allow Nocona to avoid these instructions if a register is available.
12266 [(match_scratch:DI 2 "r")
12267 (parallel [(set (zero_extract:DI
12268 (match_operand:DI 0 "register_operand" "")
12270 (match_operand:DI 1 "const_0_to_63_operand" ""))
12272 (clobber (reg:CC FLAGS_REG))])]
12273 "TARGET_64BIT && !TARGET_USE_BT"
12276 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12279 if (HOST_BITS_PER_WIDE_INT >= 64)
12280 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12281 else if (i < HOST_BITS_PER_WIDE_INT)
12282 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12284 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12286 op1 = immed_double_const (lo, hi, DImode);
12289 emit_move_insn (operands[2], op1);
12293 emit_insn (gen_iordi3 (operands[0], operands[0], op1));
12298 [(match_scratch:DI 2 "r")
12299 (parallel [(set (zero_extract:DI
12300 (match_operand:DI 0 "register_operand" "")
12302 (match_operand:DI 1 "const_0_to_63_operand" ""))
12304 (clobber (reg:CC FLAGS_REG))])]
12305 "TARGET_64BIT && !TARGET_USE_BT"
12308 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12311 if (HOST_BITS_PER_WIDE_INT >= 64)
12312 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12313 else if (i < HOST_BITS_PER_WIDE_INT)
12314 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12316 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12318 op1 = immed_double_const (~lo, ~hi, DImode);
12321 emit_move_insn (operands[2], op1);
12325 emit_insn (gen_anddi3 (operands[0], operands[0], op1));
12330 [(match_scratch:DI 2 "r")
12331 (parallel [(set (zero_extract:DI
12332 (match_operand:DI 0 "register_operand" "")
12334 (match_operand:DI 1 "const_0_to_63_operand" ""))
12335 (not:DI (zero_extract:DI
12336 (match_dup 0) (const_int 1) (match_dup 1))))
12337 (clobber (reg:CC FLAGS_REG))])]
12338 "TARGET_64BIT && !TARGET_USE_BT"
12341 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12344 if (HOST_BITS_PER_WIDE_INT >= 64)
12345 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12346 else if (i < HOST_BITS_PER_WIDE_INT)
12347 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12349 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12351 op1 = immed_double_const (lo, hi, DImode);
12354 emit_move_insn (operands[2], op1);
12358 emit_insn (gen_xordi3 (operands[0], operands[0], op1));
12362 ;; Store-flag instructions.
12364 ;; For all sCOND expanders, also expand the compare or test insn that
12365 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12367 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12368 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12369 ;; way, which can later delete the movzx if only QImode is needed.
12371 (define_expand "seq"
12372 [(set (match_operand:QI 0 "register_operand" "")
12373 (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12375 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12377 (define_expand "sne"
12378 [(set (match_operand:QI 0 "register_operand" "")
12379 (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
12381 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12383 (define_expand "sgt"
12384 [(set (match_operand:QI 0 "register_operand" "")
12385 (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12387 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12389 (define_expand "sgtu"
12390 [(set (match_operand:QI 0 "register_operand" "")
12391 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12393 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12395 (define_expand "slt"
12396 [(set (match_operand:QI 0 "register_operand" "")
12397 (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12399 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12401 (define_expand "sltu"
12402 [(set (match_operand:QI 0 "register_operand" "")
12403 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12405 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12407 (define_expand "sge"
12408 [(set (match_operand:QI 0 "register_operand" "")
12409 (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12411 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12413 (define_expand "sgeu"
12414 [(set (match_operand:QI 0 "register_operand" "")
12415 (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12417 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12419 (define_expand "sle"
12420 [(set (match_operand:QI 0 "register_operand" "")
12421 (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
12423 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12425 (define_expand "sleu"
12426 [(set (match_operand:QI 0 "register_operand" "")
12427 (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12429 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12431 (define_expand "sunordered"
12432 [(set (match_operand:QI 0 "register_operand" "")
12433 (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12434 "TARGET_80387 || TARGET_SSE"
12435 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12437 (define_expand "sordered"
12438 [(set (match_operand:QI 0 "register_operand" "")
12439 (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12441 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12443 (define_expand "suneq"
12444 [(set (match_operand:QI 0 "register_operand" "")
12445 (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12446 "TARGET_80387 || TARGET_SSE"
12447 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12449 (define_expand "sunge"
12450 [(set (match_operand:QI 0 "register_operand" "")
12451 (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12452 "TARGET_80387 || TARGET_SSE"
12453 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12455 (define_expand "sungt"
12456 [(set (match_operand:QI 0 "register_operand" "")
12457 (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12458 "TARGET_80387 || TARGET_SSE"
12459 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12461 (define_expand "sunle"
12462 [(set (match_operand:QI 0 "register_operand" "")
12463 (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
12464 "TARGET_80387 || TARGET_SSE"
12465 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12467 (define_expand "sunlt"
12468 [(set (match_operand:QI 0 "register_operand" "")
12469 (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12470 "TARGET_80387 || TARGET_SSE"
12471 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12473 (define_expand "sltgt"
12474 [(set (match_operand:QI 0 "register_operand" "")
12475 (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12476 "TARGET_80387 || TARGET_SSE"
12477 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12479 (define_insn "*setcc_1"
12480 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12481 (match_operator:QI 1 "ix86_comparison_operator"
12482 [(reg FLAGS_REG) (const_int 0)]))]
12485 [(set_attr "type" "setcc")
12486 (set_attr "mode" "QI")])
12488 (define_insn "*setcc_2"
12489 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12490 (match_operator:QI 1 "ix86_comparison_operator"
12491 [(reg FLAGS_REG) (const_int 0)]))]
12494 [(set_attr "type" "setcc")
12495 (set_attr "mode" "QI")])
12497 ;; In general it is not safe to assume too much about CCmode registers,
12498 ;; so simplify-rtx stops when it sees a second one. Under certain
12499 ;; conditions this is safe on x86, so help combine not create
12506 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12507 (ne:QI (match_operator 1 "ix86_comparison_operator"
12508 [(reg FLAGS_REG) (const_int 0)])
12511 [(set (match_dup 0) (match_dup 1))]
12513 PUT_MODE (operands[1], QImode);
12517 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12518 (ne:QI (match_operator 1 "ix86_comparison_operator"
12519 [(reg FLAGS_REG) (const_int 0)])
12522 [(set (match_dup 0) (match_dup 1))]
12524 PUT_MODE (operands[1], QImode);
12528 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12529 (eq:QI (match_operator 1 "ix86_comparison_operator"
12530 [(reg FLAGS_REG) (const_int 0)])
12533 [(set (match_dup 0) (match_dup 1))]
12535 rtx new_op1 = copy_rtx (operands[1]);
12536 operands[1] = new_op1;
12537 PUT_MODE (new_op1, QImode);
12538 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12539 GET_MODE (XEXP (new_op1, 0))));
12541 /* Make sure that (a) the CCmode we have for the flags is strong
12542 enough for the reversed compare or (b) we have a valid FP compare. */
12543 if (! ix86_comparison_operator (new_op1, VOIDmode))
12548 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12549 (eq:QI (match_operator 1 "ix86_comparison_operator"
12550 [(reg FLAGS_REG) (const_int 0)])
12553 [(set (match_dup 0) (match_dup 1))]
12555 rtx new_op1 = copy_rtx (operands[1]);
12556 operands[1] = new_op1;
12557 PUT_MODE (new_op1, QImode);
12558 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12559 GET_MODE (XEXP (new_op1, 0))));
12561 /* Make sure that (a) the CCmode we have for the flags is strong
12562 enough for the reversed compare or (b) we have a valid FP compare. */
12563 if (! ix86_comparison_operator (new_op1, VOIDmode))
12567 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12568 ;; subsequent logical operations are used to imitate conditional moves.
12569 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12570 ;; it directly. Further holding this value in pseudo register might bring
12571 ;; problem in implicit normalization in spill code.
12572 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12573 ;; instructions after reload by splitting the conditional move patterns.
12575 (define_insn "*sse_setccsf"
12576 [(set (match_operand:SF 0 "register_operand" "=x")
12577 (match_operator:SF 1 "sse_comparison_operator"
12578 [(match_operand:SF 2 "register_operand" "0")
12579 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12580 "TARGET_SSE && reload_completed"
12581 "cmp%D1ss\t{%3, %0|%0, %3}"
12582 [(set_attr "type" "ssecmp")
12583 (set_attr "mode" "SF")])
12585 (define_insn "*sse_setccdf"
12586 [(set (match_operand:DF 0 "register_operand" "=Y")
12587 (match_operator:DF 1 "sse_comparison_operator"
12588 [(match_operand:DF 2 "register_operand" "0")
12589 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12590 "TARGET_SSE2 && reload_completed"
12591 "cmp%D1sd\t{%3, %0|%0, %3}"
12592 [(set_attr "type" "ssecmp")
12593 (set_attr "mode" "DF")])
12595 ;; Basic conditional jump instructions.
12596 ;; We ignore the overflow flag for signed branch instructions.
12598 ;; For all bCOND expanders, also expand the compare or test insn that
12599 ;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
12601 (define_expand "beq"
12603 (if_then_else (match_dup 1)
12604 (label_ref (match_operand 0 "" ""))
12607 "ix86_expand_branch (EQ, operands[0]); DONE;")
12609 (define_expand "bne"
12611 (if_then_else (match_dup 1)
12612 (label_ref (match_operand 0 "" ""))
12615 "ix86_expand_branch (NE, operands[0]); DONE;")
12617 (define_expand "bgt"
12619 (if_then_else (match_dup 1)
12620 (label_ref (match_operand 0 "" ""))
12623 "ix86_expand_branch (GT, operands[0]); DONE;")
12625 (define_expand "bgtu"
12627 (if_then_else (match_dup 1)
12628 (label_ref (match_operand 0 "" ""))
12631 "ix86_expand_branch (GTU, operands[0]); DONE;")
12633 (define_expand "blt"
12635 (if_then_else (match_dup 1)
12636 (label_ref (match_operand 0 "" ""))
12639 "ix86_expand_branch (LT, operands[0]); DONE;")
12641 (define_expand "bltu"
12643 (if_then_else (match_dup 1)
12644 (label_ref (match_operand 0 "" ""))
12647 "ix86_expand_branch (LTU, operands[0]); DONE;")
12649 (define_expand "bge"
12651 (if_then_else (match_dup 1)
12652 (label_ref (match_operand 0 "" ""))
12655 "ix86_expand_branch (GE, operands[0]); DONE;")
12657 (define_expand "bgeu"
12659 (if_then_else (match_dup 1)
12660 (label_ref (match_operand 0 "" ""))
12663 "ix86_expand_branch (GEU, operands[0]); DONE;")
12665 (define_expand "ble"
12667 (if_then_else (match_dup 1)
12668 (label_ref (match_operand 0 "" ""))
12671 "ix86_expand_branch (LE, operands[0]); DONE;")
12673 (define_expand "bleu"
12675 (if_then_else (match_dup 1)
12676 (label_ref (match_operand 0 "" ""))
12679 "ix86_expand_branch (LEU, operands[0]); DONE;")
12681 (define_expand "bunordered"
12683 (if_then_else (match_dup 1)
12684 (label_ref (match_operand 0 "" ""))
12686 "TARGET_80387 || TARGET_SSE"
12687 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12689 (define_expand "bordered"
12691 (if_then_else (match_dup 1)
12692 (label_ref (match_operand 0 "" ""))
12694 "TARGET_80387 || TARGET_SSE"
12695 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12697 (define_expand "buneq"
12699 (if_then_else (match_dup 1)
12700 (label_ref (match_operand 0 "" ""))
12702 "TARGET_80387 || TARGET_SSE"
12703 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12705 (define_expand "bunge"
12707 (if_then_else (match_dup 1)
12708 (label_ref (match_operand 0 "" ""))
12710 "TARGET_80387 || TARGET_SSE"
12711 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12713 (define_expand "bungt"
12715 (if_then_else (match_dup 1)
12716 (label_ref (match_operand 0 "" ""))
12718 "TARGET_80387 || TARGET_SSE"
12719 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12721 (define_expand "bunle"
12723 (if_then_else (match_dup 1)
12724 (label_ref (match_operand 0 "" ""))
12726 "TARGET_80387 || TARGET_SSE"
12727 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12729 (define_expand "bunlt"
12731 (if_then_else (match_dup 1)
12732 (label_ref (match_operand 0 "" ""))
12734 "TARGET_80387 || TARGET_SSE"
12735 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12737 (define_expand "bltgt"
12739 (if_then_else (match_dup 1)
12740 (label_ref (match_operand 0 "" ""))
12742 "TARGET_80387 || TARGET_SSE"
12743 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12745 (define_insn "*jcc_1"
12747 (if_then_else (match_operator 1 "ix86_comparison_operator"
12748 [(reg FLAGS_REG) (const_int 0)])
12749 (label_ref (match_operand 0 "" ""))
12753 [(set_attr "type" "ibr")
12754 (set_attr "modrm" "0")
12755 (set (attr "length")
12756 (if_then_else (and (ge (minus (match_dup 0) (pc))
12758 (lt (minus (match_dup 0) (pc))
12763 (define_insn "*jcc_2"
12765 (if_then_else (match_operator 1 "ix86_comparison_operator"
12766 [(reg FLAGS_REG) (const_int 0)])
12768 (label_ref (match_operand 0 "" ""))))]
12771 [(set_attr "type" "ibr")
12772 (set_attr "modrm" "0")
12773 (set (attr "length")
12774 (if_then_else (and (ge (minus (match_dup 0) (pc))
12776 (lt (minus (match_dup 0) (pc))
12781 ;; In general it is not safe to assume too much about CCmode registers,
12782 ;; so simplify-rtx stops when it sees a second one. Under certain
12783 ;; conditions this is safe on x86, so help combine not create
12791 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
12792 [(reg FLAGS_REG) (const_int 0)])
12794 (label_ref (match_operand 1 "" ""))
12798 (if_then_else (match_dup 0)
12799 (label_ref (match_dup 1))
12802 PUT_MODE (operands[0], VOIDmode);
12807 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
12808 [(reg FLAGS_REG) (const_int 0)])
12810 (label_ref (match_operand 1 "" ""))
12814 (if_then_else (match_dup 0)
12815 (label_ref (match_dup 1))
12818 rtx new_op0 = copy_rtx (operands[0]);
12819 operands[0] = new_op0;
12820 PUT_MODE (new_op0, VOIDmode);
12821 PUT_CODE (new_op0, ix86_reverse_condition (GET_CODE (new_op0),
12822 GET_MODE (XEXP (new_op0, 0))));
12824 /* Make sure that (a) the CCmode we have for the flags is strong
12825 enough for the reversed compare or (b) we have a valid FP compare. */
12826 if (! ix86_comparison_operator (new_op0, VOIDmode))
12830 ;; Define combination compare-and-branch fp compare instructions to use
12831 ;; during early optimization. Splitting the operation apart early makes
12832 ;; for bad code when we want to reverse the operation.
12834 (define_insn "*fp_jcc_1"
12836 (if_then_else (match_operator 0 "comparison_operator"
12837 [(match_operand 1 "register_operand" "f")
12838 (match_operand 2 "register_operand" "f")])
12839 (label_ref (match_operand 3 "" ""))
12841 (clobber (reg:CCFP FPSR_REG))
12842 (clobber (reg:CCFP FLAGS_REG))]
12843 "TARGET_CMOVE && TARGET_80387
12844 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12845 && FLOAT_MODE_P (GET_MODE (operands[1]))
12846 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12847 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12850 (define_insn "*fp_jcc_1_sse"
12852 (if_then_else (match_operator 0 "comparison_operator"
12853 [(match_operand 1 "register_operand" "f#x,x#f")
12854 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12855 (label_ref (match_operand 3 "" ""))
12857 (clobber (reg:CCFP FPSR_REG))
12858 (clobber (reg:CCFP FLAGS_REG))]
12860 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12861 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12862 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12865 (define_insn "*fp_jcc_1_sse_only"
12867 (if_then_else (match_operator 0 "comparison_operator"
12868 [(match_operand 1 "register_operand" "x")
12869 (match_operand 2 "nonimmediate_operand" "xm")])
12870 (label_ref (match_operand 3 "" ""))
12872 (clobber (reg:CCFP FPSR_REG))
12873 (clobber (reg:CCFP FLAGS_REG))]
12874 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12875 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12876 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12879 (define_insn "*fp_jcc_2"
12881 (if_then_else (match_operator 0 "comparison_operator"
12882 [(match_operand 1 "register_operand" "f")
12883 (match_operand 2 "register_operand" "f")])
12885 (label_ref (match_operand 3 "" ""))))
12886 (clobber (reg:CCFP FPSR_REG))
12887 (clobber (reg:CCFP FLAGS_REG))]
12888 "TARGET_CMOVE && TARGET_80387
12889 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12890 && FLOAT_MODE_P (GET_MODE (operands[1]))
12891 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12892 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12895 (define_insn "*fp_jcc_2_sse"
12897 (if_then_else (match_operator 0 "comparison_operator"
12898 [(match_operand 1 "register_operand" "f#x,x#f")
12899 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12901 (label_ref (match_operand 3 "" ""))))
12902 (clobber (reg:CCFP FPSR_REG))
12903 (clobber (reg:CCFP FLAGS_REG))]
12905 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12906 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12907 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12910 (define_insn "*fp_jcc_2_sse_only"
12912 (if_then_else (match_operator 0 "comparison_operator"
12913 [(match_operand 1 "register_operand" "x")
12914 (match_operand 2 "nonimmediate_operand" "xm")])
12916 (label_ref (match_operand 3 "" ""))))
12917 (clobber (reg:CCFP FPSR_REG))
12918 (clobber (reg:CCFP FLAGS_REG))]
12919 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12920 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12921 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12924 (define_insn "*fp_jcc_3"
12926 (if_then_else (match_operator 0 "comparison_operator"
12927 [(match_operand 1 "register_operand" "f")
12928 (match_operand 2 "nonimmediate_operand" "fm")])
12929 (label_ref (match_operand 3 "" ""))
12931 (clobber (reg:CCFP FPSR_REG))
12932 (clobber (reg:CCFP FLAGS_REG))
12933 (clobber (match_scratch:HI 4 "=a"))]
12935 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12936 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12937 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12938 && SELECT_CC_MODE (GET_CODE (operands[0]),
12939 operands[1], operands[2]) == CCFPmode
12940 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12943 (define_insn "*fp_jcc_4"
12945 (if_then_else (match_operator 0 "comparison_operator"
12946 [(match_operand 1 "register_operand" "f")
12947 (match_operand 2 "nonimmediate_operand" "fm")])
12949 (label_ref (match_operand 3 "" ""))))
12950 (clobber (reg:CCFP FPSR_REG))
12951 (clobber (reg:CCFP FLAGS_REG))
12952 (clobber (match_scratch:HI 4 "=a"))]
12954 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12955 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12956 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12957 && SELECT_CC_MODE (GET_CODE (operands[0]),
12958 operands[1], operands[2]) == CCFPmode
12959 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12962 (define_insn "*fp_jcc_5"
12964 (if_then_else (match_operator 0 "comparison_operator"
12965 [(match_operand 1 "register_operand" "f")
12966 (match_operand 2 "register_operand" "f")])
12967 (label_ref (match_operand 3 "" ""))
12969 (clobber (reg:CCFP FPSR_REG))
12970 (clobber (reg:CCFP FLAGS_REG))
12971 (clobber (match_scratch:HI 4 "=a"))]
12973 && FLOAT_MODE_P (GET_MODE (operands[1]))
12974 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12975 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12978 (define_insn "*fp_jcc_6"
12980 (if_then_else (match_operator 0 "comparison_operator"
12981 [(match_operand 1 "register_operand" "f")
12982 (match_operand 2 "register_operand" "f")])
12984 (label_ref (match_operand 3 "" ""))))
12985 (clobber (reg:CCFP FPSR_REG))
12986 (clobber (reg:CCFP FLAGS_REG))
12987 (clobber (match_scratch:HI 4 "=a"))]
12989 && FLOAT_MODE_P (GET_MODE (operands[1]))
12990 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12991 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12994 (define_insn "*fp_jcc_7"
12996 (if_then_else (match_operator 0 "comparison_operator"
12997 [(match_operand 1 "register_operand" "f")
12998 (match_operand 2 "const_double_operand" "C")])
12999 (label_ref (match_operand 3 "" ""))
13001 (clobber (reg:CCFP FPSR_REG))
13002 (clobber (reg:CCFP FLAGS_REG))
13003 (clobber (match_scratch:HI 4 "=a"))]
13005 && FLOAT_MODE_P (GET_MODE (operands[1]))
13006 && operands[2] == CONST0_RTX (GET_MODE (operands[1]))
13007 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13008 && SELECT_CC_MODE (GET_CODE (operands[0]),
13009 operands[1], operands[2]) == CCFPmode
13010 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13013 ;; The order of operands in *fp_jcc_8 is forced by combine in
13014 ;; simplify_comparison () function. Float operator is treated as RTX_OBJ
13015 ;; with a precedence over other operators and is always put in the first
13016 ;; place. Swap condition and operands to match ficom instruction.
13018 (define_insn "*fp_jcc_8"
13020 (if_then_else (match_operator 0 "comparison_operator"
13021 [(match_operator 1 "float_operator"
13022 [(match_operand:SI 2 "nonimmediate_operand" "m,?r")])
13023 (match_operand 3 "register_operand" "f,f")])
13024 (label_ref (match_operand 4 "" ""))
13026 (clobber (reg:CCFP FPSR_REG))
13027 (clobber (reg:CCFP FLAGS_REG))
13028 (clobber (match_scratch:HI 5 "=a,a"))]
13029 "TARGET_80387 && TARGET_USE_FIOP
13030 && FLOAT_MODE_P (GET_MODE (operands[3]))
13031 && GET_MODE (operands[1]) == GET_MODE (operands[3])
13032 && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
13033 && ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
13034 && ix86_fp_jump_nontrivial_p (swap_condition (GET_CODE (operands[0])))"
13039 (if_then_else (match_operator 0 "comparison_operator"
13040 [(match_operand 1 "register_operand" "")
13041 (match_operand 2 "nonimmediate_operand" "")])
13042 (match_operand 3 "" "")
13043 (match_operand 4 "" "")))
13044 (clobber (reg:CCFP FPSR_REG))
13045 (clobber (reg:CCFP FLAGS_REG))]
13049 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13050 operands[3], operands[4], NULL_RTX, NULL_RTX);
13056 (if_then_else (match_operator 0 "comparison_operator"
13057 [(match_operand 1 "register_operand" "")
13058 (match_operand 2 "general_operand" "")])
13059 (match_operand 3 "" "")
13060 (match_operand 4 "" "")))
13061 (clobber (reg:CCFP FPSR_REG))
13062 (clobber (reg:CCFP FLAGS_REG))
13063 (clobber (match_scratch:HI 5 "=a"))]
13067 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13068 operands[3], operands[4], operands[5], NULL_RTX);
13074 (if_then_else (match_operator 0 "comparison_operator"
13075 [(match_operator 1 "float_operator"
13076 [(match_operand:SI 2 "memory_operand" "")])
13077 (match_operand 3 "register_operand" "")])
13078 (match_operand 4 "" "")
13079 (match_operand 5 "" "")))
13080 (clobber (reg:CCFP FPSR_REG))
13081 (clobber (reg:CCFP FLAGS_REG))
13082 (clobber (match_scratch:HI 6 "=a"))]
13086 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);
13087 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
13088 operands[3], operands[7],
13089 operands[4], operands[5], operands[6], NULL_RTX);
13093 ;; %%% Kill this when reload knows how to do it.
13096 (if_then_else (match_operator 0 "comparison_operator"
13097 [(match_operator 1 "float_operator"
13098 [(match_operand:SI 2 "register_operand" "")])
13099 (match_operand 3 "register_operand" "")])
13100 (match_operand 4 "" "")
13101 (match_operand 5 "" "")))
13102 (clobber (reg:CCFP FPSR_REG))
13103 (clobber (reg:CCFP FLAGS_REG))
13104 (clobber (match_scratch:HI 6 "=a"))]
13108 operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
13109 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);
13110 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
13111 operands[3], operands[7],
13112 operands[4], operands[5], operands[6], operands[2]);
13116 ;; Unconditional and other jump instructions
13118 (define_insn "jump"
13120 (label_ref (match_operand 0 "" "")))]
13123 [(set_attr "type" "ibr")
13124 (set (attr "length")
13125 (if_then_else (and (ge (minus (match_dup 0) (pc))
13127 (lt (minus (match_dup 0) (pc))
13131 (set_attr "modrm" "0")])
13133 (define_expand "indirect_jump"
13134 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13138 (define_insn "*indirect_jump"
13139 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13142 [(set_attr "type" "ibr")
13143 (set_attr "length_immediate" "0")])
13145 (define_insn "*indirect_jump_rtx64"
13146 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13149 [(set_attr "type" "ibr")
13150 (set_attr "length_immediate" "0")])
13152 (define_expand "tablejump"
13153 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13154 (use (label_ref (match_operand 1 "" "")))])]
13157 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13158 relative. Convert the relative address to an absolute address. */
13162 enum rtx_code code;
13168 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13170 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13174 op1 = pic_offset_table_rtx;
13179 op0 = pic_offset_table_rtx;
13183 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13188 (define_insn "*tablejump_1"
13189 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13190 (use (label_ref (match_operand 1 "" "")))]
13193 [(set_attr "type" "ibr")
13194 (set_attr "length_immediate" "0")])
13196 (define_insn "*tablejump_1_rtx64"
13197 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13198 (use (label_ref (match_operand 1 "" "")))]
13201 [(set_attr "type" "ibr")
13202 (set_attr "length_immediate" "0")])
13204 ;; Loop instruction
13206 ;; This is all complicated by the fact that since this is a jump insn
13207 ;; we must handle our own reloads.
13209 (define_expand "doloop_end"
13210 [(use (match_operand 0 "" "")) ; loop pseudo
13211 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13212 (use (match_operand 2 "" "")) ; max iterations
13213 (use (match_operand 3 "" "")) ; loop level
13214 (use (match_operand 4 "" ""))] ; label
13215 "!TARGET_64BIT && TARGET_USE_LOOP"
13218 /* Only use cloop on innermost loops. */
13219 if (INTVAL (operands[3]) > 1)
13221 if (GET_MODE (operands[0]) != SImode)
13223 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13228 (define_insn "doloop_end_internal"
13230 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13232 (label_ref (match_operand 0 "" ""))
13234 (set (match_operand:SI 2 "nonimmediate_operand" "=1,1,*m*r")
13235 (plus:SI (match_dup 1)
13237 (clobber (match_scratch:SI 3 "=X,X,r"))
13238 (clobber (reg:CC FLAGS_REG))]
13239 "!TARGET_64BIT && TARGET_USE_LOOP
13240 && (reload_in_progress || reload_completed
13241 || register_operand (operands[2], VOIDmode))"
13243 if (which_alternative != 0)
13245 if (get_attr_length (insn) == 2)
13246 return "%+loop\t%l0";
13248 return "dec{l}\t%1\;%+jne\t%l0";
13250 [(set (attr "length")
13251 (if_then_else (and (eq_attr "alternative" "0")
13252 (and (ge (minus (match_dup 0) (pc))
13254 (lt (minus (match_dup 0) (pc))
13258 ;; We don't know the type before shorten branches. Optimistically expect
13259 ;; the loop instruction to match.
13260 (set (attr "type") (const_string "ibr"))])
13264 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13266 (match_operand 0 "" "")
13269 (plus:SI (match_dup 1)
13271 (clobber (match_scratch:SI 2 ""))
13272 (clobber (reg:CC FLAGS_REG))]
13273 "!TARGET_64BIT && TARGET_USE_LOOP
13274 && reload_completed
13275 && REGNO (operands[1]) != 2"
13276 [(parallel [(set (reg:CCZ FLAGS_REG)
13277 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13279 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13280 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13287 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13289 (match_operand 0 "" "")
13291 (set (match_operand:SI 2 "nonimmediate_operand" "")
13292 (plus:SI (match_dup 1)
13294 (clobber (match_scratch:SI 3 ""))
13295 (clobber (reg:CC FLAGS_REG))]
13296 "!TARGET_64BIT && TARGET_USE_LOOP
13297 && reload_completed
13298 && (! REG_P (operands[2])
13299 || ! rtx_equal_p (operands[1], operands[2]))"
13300 [(set (match_dup 3) (match_dup 1))
13301 (parallel [(set (reg:CCZ FLAGS_REG)
13302 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13304 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13305 (set (match_dup 2) (match_dup 3))
13306 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13311 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13314 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
13315 (set (match_operand:QI 1 "register_operand" "")
13316 (match_operator:QI 2 "ix86_comparison_operator"
13317 [(reg FLAGS_REG) (const_int 0)]))
13318 (set (match_operand 3 "q_regs_operand" "")
13319 (zero_extend (match_dup 1)))]
13320 "(peep2_reg_dead_p (3, operands[1])
13321 || operands_match_p (operands[1], operands[3]))
13322 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13323 [(set (match_dup 4) (match_dup 0))
13324 (set (strict_low_part (match_dup 5))
13327 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13328 operands[5] = gen_lowpart (QImode, operands[3]);
13329 ix86_expand_clear (operands[3]);
13332 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13335 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
13336 (set (match_operand:QI 1 "register_operand" "")
13337 (match_operator:QI 2 "ix86_comparison_operator"
13338 [(reg FLAGS_REG) (const_int 0)]))
13339 (parallel [(set (match_operand 3 "q_regs_operand" "")
13340 (zero_extend (match_dup 1)))
13341 (clobber (reg:CC FLAGS_REG))])]
13342 "(peep2_reg_dead_p (3, operands[1])
13343 || operands_match_p (operands[1], operands[3]))
13344 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13345 [(set (match_dup 4) (match_dup 0))
13346 (set (strict_low_part (match_dup 5))
13349 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13350 operands[5] = gen_lowpart (QImode, operands[3]);
13351 ix86_expand_clear (operands[3]);
13354 ;; Call instructions.
13356 ;; The predicates normally associated with named expanders are not properly
13357 ;; checked for calls. This is a bug in the generic code, but it isn't that
13358 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13360 ;; Call subroutine returning no value.
13362 (define_expand "call_pop"
13363 [(parallel [(call (match_operand:QI 0 "" "")
13364 (match_operand:SI 1 "" ""))
13365 (set (reg:SI SP_REG)
13366 (plus:SI (reg:SI SP_REG)
13367 (match_operand:SI 3 "" "")))])]
13370 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13374 (define_insn "*call_pop_0"
13375 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13376 (match_operand:SI 1 "" ""))
13377 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13378 (match_operand:SI 2 "immediate_operand" "")))]
13381 if (SIBLING_CALL_P (insn))
13384 return "call\t%P0";
13386 [(set_attr "type" "call")])
13388 (define_insn "*call_pop_1"
13389 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13390 (match_operand:SI 1 "" ""))
13391 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13392 (match_operand:SI 2 "immediate_operand" "i")))]
13395 if (constant_call_address_operand (operands[0], Pmode))
13397 if (SIBLING_CALL_P (insn))
13400 return "call\t%P0";
13402 if (SIBLING_CALL_P (insn))
13405 return "call\t%A0";
13407 [(set_attr "type" "call")])
13409 (define_expand "call"
13410 [(call (match_operand:QI 0 "" "")
13411 (match_operand 1 "" ""))
13412 (use (match_operand 2 "" ""))]
13415 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13419 (define_expand "sibcall"
13420 [(call (match_operand:QI 0 "" "")
13421 (match_operand 1 "" ""))
13422 (use (match_operand 2 "" ""))]
13425 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13429 (define_insn "*call_0"
13430 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13431 (match_operand 1 "" ""))]
13434 if (SIBLING_CALL_P (insn))
13437 return "call\t%P0";
13439 [(set_attr "type" "call")])
13441 (define_insn "*call_1"
13442 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13443 (match_operand 1 "" ""))]
13444 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13446 if (constant_call_address_operand (operands[0], Pmode))
13447 return "call\t%P0";
13448 return "call\t%A0";
13450 [(set_attr "type" "call")])
13452 (define_insn "*sibcall_1"
13453 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13454 (match_operand 1 "" ""))]
13455 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13457 if (constant_call_address_operand (operands[0], Pmode))
13461 [(set_attr "type" "call")])
13463 (define_insn "*call_1_rex64"
13464 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13465 (match_operand 1 "" ""))]
13466 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13468 if (constant_call_address_operand (operands[0], Pmode))
13469 return "call\t%P0";
13470 return "call\t%A0";
13472 [(set_attr "type" "call")])
13474 (define_insn "*sibcall_1_rex64"
13475 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13476 (match_operand 1 "" ""))]
13477 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13479 [(set_attr "type" "call")])
13481 (define_insn "*sibcall_1_rex64_v"
13482 [(call (mem:QI (reg:DI 40))
13483 (match_operand 0 "" ""))]
13484 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13486 [(set_attr "type" "call")])
13489 ;; Call subroutine, returning value in operand 0
13491 (define_expand "call_value_pop"
13492 [(parallel [(set (match_operand 0 "" "")
13493 (call (match_operand:QI 1 "" "")
13494 (match_operand:SI 2 "" "")))
13495 (set (reg:SI SP_REG)
13496 (plus:SI (reg:SI SP_REG)
13497 (match_operand:SI 4 "" "")))])]
13500 ix86_expand_call (operands[0], operands[1], operands[2],
13501 operands[3], operands[4], 0);
13505 (define_expand "call_value"
13506 [(set (match_operand 0 "" "")
13507 (call (match_operand:QI 1 "" "")
13508 (match_operand:SI 2 "" "")))
13509 (use (match_operand:SI 3 "" ""))]
13510 ;; Operand 2 not used on the i386.
13513 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13517 (define_expand "sibcall_value"
13518 [(set (match_operand 0 "" "")
13519 (call (match_operand:QI 1 "" "")
13520 (match_operand:SI 2 "" "")))
13521 (use (match_operand:SI 3 "" ""))]
13522 ;; Operand 2 not used on the i386.
13525 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13529 ;; Call subroutine returning any type.
13531 (define_expand "untyped_call"
13532 [(parallel [(call (match_operand 0 "" "")
13534 (match_operand 1 "" "")
13535 (match_operand 2 "" "")])]
13540 /* In order to give reg-stack an easier job in validating two
13541 coprocessor registers as containing a possible return value,
13542 simply pretend the untyped call returns a complex long double
13545 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13546 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13547 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13550 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13552 rtx set = XVECEXP (operands[2], 0, i);
13553 emit_move_insn (SET_DEST (set), SET_SRC (set));
13556 /* The optimizer does not know that the call sets the function value
13557 registers we stored in the result block. We avoid problems by
13558 claiming that all hard registers are used and clobbered at this
13560 emit_insn (gen_blockage (const0_rtx));
13565 ;; Prologue and epilogue instructions
13567 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13568 ;; all of memory. This blocks insns from being moved across this point.
13570 (define_insn "blockage"
13571 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13574 [(set_attr "length" "0")])
13576 ;; Insn emitted into the body of a function to return from a function.
13577 ;; This is only done if the function's epilogue is known to be simple.
13578 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13580 (define_expand "return"
13582 "ix86_can_use_return_insn_p ()"
13584 if (current_function_pops_args)
13586 rtx popc = GEN_INT (current_function_pops_args);
13587 emit_jump_insn (gen_return_pop_internal (popc));
13592 (define_insn "return_internal"
13596 [(set_attr "length" "1")
13597 (set_attr "length_immediate" "0")
13598 (set_attr "modrm" "0")])
13600 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
13601 ;; instruction Athlon and K8 have.
13603 (define_insn "return_internal_long"
13605 (unspec [(const_int 0)] UNSPEC_REP)]
13608 [(set_attr "length" "1")
13609 (set_attr "length_immediate" "0")
13610 (set_attr "prefix_rep" "1")
13611 (set_attr "modrm" "0")])
13613 (define_insn "return_pop_internal"
13615 (use (match_operand:SI 0 "const_int_operand" ""))]
13618 [(set_attr "length" "3")
13619 (set_attr "length_immediate" "2")
13620 (set_attr "modrm" "0")])
13622 (define_insn "return_indirect_internal"
13624 (use (match_operand:SI 0 "register_operand" "r"))]
13627 [(set_attr "type" "ibr")
13628 (set_attr "length_immediate" "0")])
13634 [(set_attr "length" "1")
13635 (set_attr "length_immediate" "0")
13636 (set_attr "modrm" "0")])
13638 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
13639 ;; branch prediction penalty for the third jump in a 16-byte
13642 (define_insn "align"
13643 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
13646 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
13647 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
13649 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
13650 The align insn is used to avoid 3 jump instructions in the row to improve
13651 branch prediction and the benefits hardly outweight the cost of extra 8
13652 nops on the average inserted by full alignment pseudo operation. */
13656 [(set_attr "length" "16")])
13658 (define_expand "prologue"
13661 "ix86_expand_prologue (); DONE;")
13663 (define_insn "set_got"
13664 [(set (match_operand:SI 0 "register_operand" "=r")
13665 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13666 (clobber (reg:CC FLAGS_REG))]
13668 { return output_set_got (operands[0]); }
13669 [(set_attr "type" "multi")
13670 (set_attr "length" "12")])
13672 (define_expand "epilogue"
13675 "ix86_expand_epilogue (1); DONE;")
13677 (define_expand "sibcall_epilogue"
13680 "ix86_expand_epilogue (0); DONE;")
13682 (define_expand "eh_return"
13683 [(use (match_operand 0 "register_operand" ""))]
13686 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13688 /* Tricky bit: we write the address of the handler to which we will
13689 be returning into someone else's stack frame, one word below the
13690 stack address we wish to restore. */
13691 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13692 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13693 tmp = gen_rtx_MEM (Pmode, tmp);
13694 emit_move_insn (tmp, ra);
13696 if (Pmode == SImode)
13697 emit_jump_insn (gen_eh_return_si (sa));
13699 emit_jump_insn (gen_eh_return_di (sa));
13704 (define_insn_and_split "eh_return_si"
13706 (unspec [(match_operand:SI 0 "register_operand" "c")]
13707 UNSPEC_EH_RETURN))]
13712 "ix86_expand_epilogue (2); DONE;")
13714 (define_insn_and_split "eh_return_di"
13716 (unspec [(match_operand:DI 0 "register_operand" "c")]
13717 UNSPEC_EH_RETURN))]
13722 "ix86_expand_epilogue (2); DONE;")
13724 (define_insn "leave"
13725 [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
13726 (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
13727 (clobber (mem:BLK (scratch)))]
13730 [(set_attr "type" "leave")])
13732 (define_insn "leave_rex64"
13733 [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
13734 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
13735 (clobber (mem:BLK (scratch)))]
13738 [(set_attr "type" "leave")])
13740 (define_expand "ffssi2"
13742 [(set (match_operand:SI 0 "register_operand" "")
13743 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
13744 (clobber (match_scratch:SI 2 ""))
13745 (clobber (reg:CC FLAGS_REG))])]
13749 (define_insn_and_split "*ffs_cmove"
13750 [(set (match_operand:SI 0 "register_operand" "=r")
13751 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13752 (clobber (match_scratch:SI 2 "=&r"))
13753 (clobber (reg:CC FLAGS_REG))]
13756 "&& reload_completed"
13757 [(set (match_dup 2) (const_int -1))
13758 (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13759 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13760 (set (match_dup 0) (if_then_else:SI
13761 (eq (reg:CCZ FLAGS_REG) (const_int 0))
13764 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13765 (clobber (reg:CC FLAGS_REG))])]
13768 (define_insn_and_split "*ffs_no_cmove"
13769 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
13770 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13771 (clobber (match_scratch:SI 2 "=&q"))
13772 (clobber (reg:CC FLAGS_REG))]
13776 [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13777 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13778 (set (strict_low_part (match_dup 3))
13779 (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
13780 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
13781 (clobber (reg:CC FLAGS_REG))])
13782 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
13783 (clobber (reg:CC FLAGS_REG))])
13784 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13785 (clobber (reg:CC FLAGS_REG))])]
13787 operands[3] = gen_lowpart (QImode, operands[2]);
13788 ix86_expand_clear (operands[2]);
13791 (define_insn "*ffssi_1"
13792 [(set (reg:CCZ FLAGS_REG)
13793 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13795 (set (match_operand:SI 0 "register_operand" "=r")
13796 (ctz:SI (match_dup 1)))]
13798 "bsf{l}\t{%1, %0|%0, %1}"
13799 [(set_attr "prefix_0f" "1")])
13801 (define_expand "ffsdi2"
13803 [(set (match_operand:DI 0 "register_operand" "")
13804 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
13805 (clobber (match_scratch:DI 2 ""))
13806 (clobber (reg:CC FLAGS_REG))])]
13807 "TARGET_64BIT && TARGET_CMOVE"
13810 (define_insn_and_split "*ffs_rex64"
13811 [(set (match_operand:DI 0 "register_operand" "=r")
13812 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
13813 (clobber (match_scratch:DI 2 "=&r"))
13814 (clobber (reg:CC FLAGS_REG))]
13815 "TARGET_64BIT && TARGET_CMOVE"
13817 "&& reload_completed"
13818 [(set (match_dup 2) (const_int -1))
13819 (parallel [(set (reg:CCZ FLAGS_REG)
13820 (compare:CCZ (match_dup 1) (const_int 0)))
13821 (set (match_dup 0) (ctz:DI (match_dup 1)))])
13822 (set (match_dup 0) (if_then_else:DI
13823 (eq (reg:CCZ FLAGS_REG) (const_int 0))
13826 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
13827 (clobber (reg:CC FLAGS_REG))])]
13830 (define_insn "*ffsdi_1"
13831 [(set (reg:CCZ FLAGS_REG)
13832 (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
13834 (set (match_operand:DI 0 "register_operand" "=r")
13835 (ctz:DI (match_dup 1)))]
13837 "bsf{q}\t{%1, %0|%0, %1}"
13838 [(set_attr "prefix_0f" "1")])
13840 (define_insn "ctzsi2"
13841 [(set (match_operand:SI 0 "register_operand" "=r")
13842 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13843 (clobber (reg:CC FLAGS_REG))]
13845 "bsf{l}\t{%1, %0|%0, %1}"
13846 [(set_attr "prefix_0f" "1")])
13848 (define_insn "ctzdi2"
13849 [(set (match_operand:DI 0 "register_operand" "=r")
13850 (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
13851 (clobber (reg:CC FLAGS_REG))]
13853 "bsf{q}\t{%1, %0|%0, %1}"
13854 [(set_attr "prefix_0f" "1")])
13856 (define_expand "clzsi2"
13858 [(set (match_operand:SI 0 "register_operand" "")
13859 (minus:SI (const_int 31)
13860 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
13861 (clobber (reg:CC FLAGS_REG))])
13863 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
13864 (clobber (reg:CC FLAGS_REG))])]
13868 (define_insn "*bsr"
13869 [(set (match_operand:SI 0 "register_operand" "=r")
13870 (minus:SI (const_int 31)
13871 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
13872 (clobber (reg:CC FLAGS_REG))]
13874 "bsr{l}\t{%1, %0|%0, %1}"
13875 [(set_attr "prefix_0f" "1")])
13877 (define_expand "clzdi2"
13879 [(set (match_operand:DI 0 "register_operand" "")
13880 (minus:DI (const_int 63)
13881 (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
13882 (clobber (reg:CC FLAGS_REG))])
13884 [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
13885 (clobber (reg:CC FLAGS_REG))])]
13889 (define_insn "*bsr_rex64"
13890 [(set (match_operand:DI 0 "register_operand" "=r")
13891 (minus:DI (const_int 63)
13892 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
13893 (clobber (reg:CC FLAGS_REG))]
13895 "bsr{q}\t{%1, %0|%0, %1}"
13896 [(set_attr "prefix_0f" "1")])
13898 ;; Thread-local storage patterns for ELF.
13900 ;; Note that these code sequences must appear exactly as shown
13901 ;; in order to allow linker relaxation.
13903 (define_insn "*tls_global_dynamic_32_gnu"
13904 [(set (match_operand:SI 0 "register_operand" "=a")
13905 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13906 (match_operand:SI 2 "tls_symbolic_operand" "")
13907 (match_operand:SI 3 "call_insn_operand" "")]
13909 (clobber (match_scratch:SI 4 "=d"))
13910 (clobber (match_scratch:SI 5 "=c"))
13911 (clobber (reg:CC FLAGS_REG))]
13912 "!TARGET_64BIT && TARGET_GNU_TLS"
13913 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
13914 [(set_attr "type" "multi")
13915 (set_attr "length" "12")])
13917 (define_insn "*tls_global_dynamic_32_sun"
13918 [(set (match_operand:SI 0 "register_operand" "=a")
13919 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13920 (match_operand:SI 2 "tls_symbolic_operand" "")
13921 (match_operand:SI 3 "call_insn_operand" "")]
13923 (clobber (match_scratch:SI 4 "=d"))
13924 (clobber (match_scratch:SI 5 "=c"))
13925 (clobber (reg:CC FLAGS_REG))]
13926 "!TARGET_64BIT && TARGET_SUN_TLS"
13927 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
13928 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
13929 [(set_attr "type" "multi")
13930 (set_attr "length" "14")])
13932 (define_expand "tls_global_dynamic_32"
13933 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13936 (match_operand:SI 1 "tls_symbolic_operand" "")
13939 (clobber (match_scratch:SI 4 ""))
13940 (clobber (match_scratch:SI 5 ""))
13941 (clobber (reg:CC FLAGS_REG))])]
13945 operands[2] = pic_offset_table_rtx;
13948 operands[2] = gen_reg_rtx (Pmode);
13949 emit_insn (gen_set_got (operands[2]));
13951 operands[3] = ix86_tls_get_addr ();
13954 (define_insn "*tls_global_dynamic_64"
13955 [(set (match_operand:DI 0 "register_operand" "=a")
13956 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
13957 (match_operand:DI 3 "" "")))
13958 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
13961 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
13962 [(set_attr "type" "multi")
13963 (set_attr "length" "16")])
13965 (define_expand "tls_global_dynamic_64"
13966 [(parallel [(set (match_operand:DI 0 "register_operand" "")
13967 (call (mem:QI (match_dup 2)) (const_int 0)))
13968 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
13972 operands[2] = ix86_tls_get_addr ();
13975 (define_insn "*tls_local_dynamic_base_32_gnu"
13976 [(set (match_operand:SI 0 "register_operand" "=a")
13977 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13978 (match_operand:SI 2 "call_insn_operand" "")]
13979 UNSPEC_TLS_LD_BASE))
13980 (clobber (match_scratch:SI 3 "=d"))
13981 (clobber (match_scratch:SI 4 "=c"))
13982 (clobber (reg:CC FLAGS_REG))]
13983 "!TARGET_64BIT && TARGET_GNU_TLS"
13984 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
13985 [(set_attr "type" "multi")
13986 (set_attr "length" "11")])
13988 (define_insn "*tls_local_dynamic_base_32_sun"
13989 [(set (match_operand:SI 0 "register_operand" "=a")
13990 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13991 (match_operand:SI 2 "call_insn_operand" "")]
13992 UNSPEC_TLS_LD_BASE))
13993 (clobber (match_scratch:SI 3 "=d"))
13994 (clobber (match_scratch:SI 4 "=c"))
13995 (clobber (reg:CC FLAGS_REG))]
13996 "!TARGET_64BIT && TARGET_SUN_TLS"
13997 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
13998 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
13999 [(set_attr "type" "multi")
14000 (set_attr "length" "13")])
14002 (define_expand "tls_local_dynamic_base_32"
14003 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14004 (unspec:SI [(match_dup 1) (match_dup 2)]
14005 UNSPEC_TLS_LD_BASE))
14006 (clobber (match_scratch:SI 3 ""))
14007 (clobber (match_scratch:SI 4 ""))
14008 (clobber (reg:CC FLAGS_REG))])]
14012 operands[1] = pic_offset_table_rtx;
14015 operands[1] = gen_reg_rtx (Pmode);
14016 emit_insn (gen_set_got (operands[1]));
14018 operands[2] = ix86_tls_get_addr ();
14021 (define_insn "*tls_local_dynamic_base_64"
14022 [(set (match_operand:DI 0 "register_operand" "=a")
14023 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14024 (match_operand:DI 2 "" "")))
14025 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14027 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14028 [(set_attr "type" "multi")
14029 (set_attr "length" "12")])
14031 (define_expand "tls_local_dynamic_base_64"
14032 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14033 (call (mem:QI (match_dup 1)) (const_int 0)))
14034 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14037 operands[1] = ix86_tls_get_addr ();
14040 ;; Local dynamic of a single variable is a lose. Show combine how
14041 ;; to convert that back to global dynamic.
14043 (define_insn_and_split "*tls_local_dynamic_32_once"
14044 [(set (match_operand:SI 0 "register_operand" "=a")
14045 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14046 (match_operand:SI 2 "call_insn_operand" "")]
14047 UNSPEC_TLS_LD_BASE)
14048 (const:SI (unspec:SI
14049 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14051 (clobber (match_scratch:SI 4 "=d"))
14052 (clobber (match_scratch:SI 5 "=c"))
14053 (clobber (reg:CC FLAGS_REG))]
14057 [(parallel [(set (match_dup 0)
14058 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14060 (clobber (match_dup 4))
14061 (clobber (match_dup 5))
14062 (clobber (reg:CC FLAGS_REG))])]
14065 ;; Load and add the thread base pointer from %gs:0.
14067 (define_insn "*load_tp_si"
14068 [(set (match_operand:SI 0 "register_operand" "=r")
14069 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14071 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14072 [(set_attr "type" "imov")
14073 (set_attr "modrm" "0")
14074 (set_attr "length" "7")
14075 (set_attr "memory" "load")
14076 (set_attr "imm_disp" "false")])
14078 (define_insn "*add_tp_si"
14079 [(set (match_operand:SI 0 "register_operand" "=r")
14080 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14081 (match_operand:SI 1 "register_operand" "0")))
14082 (clobber (reg:CC FLAGS_REG))]
14084 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14085 [(set_attr "type" "alu")
14086 (set_attr "modrm" "0")
14087 (set_attr "length" "7")
14088 (set_attr "memory" "load")
14089 (set_attr "imm_disp" "false")])
14091 (define_insn "*load_tp_di"
14092 [(set (match_operand:DI 0 "register_operand" "=r")
14093 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14095 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14096 [(set_attr "type" "imov")
14097 (set_attr "modrm" "0")
14098 (set_attr "length" "7")
14099 (set_attr "memory" "load")
14100 (set_attr "imm_disp" "false")])
14102 (define_insn "*add_tp_di"
14103 [(set (match_operand:DI 0 "register_operand" "=r")
14104 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14105 (match_operand:DI 1 "register_operand" "0")))
14106 (clobber (reg:CC FLAGS_REG))]
14108 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14109 [(set_attr "type" "alu")
14110 (set_attr "modrm" "0")
14111 (set_attr "length" "7")
14112 (set_attr "memory" "load")
14113 (set_attr "imm_disp" "false")])
14115 ;; These patterns match the binary 387 instructions for addM3, subM3,
14116 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14117 ;; SFmode. The first is the normal insn, the second the same insn but
14118 ;; with one operand a conversion, and the third the same insn but with
14119 ;; the other operand a conversion. The conversion may be SFmode or
14120 ;; SImode if the target mode DFmode, but only SImode if the target mode
14123 ;; Gcc is slightly more smart about handling normal two address instructions
14124 ;; so use special patterns for add and mull.
14126 (define_insn "*fop_sf_comm_mixed"
14127 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14128 (match_operator:SF 3 "binary_fp_operator"
14129 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14130 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14131 "TARGET_MIX_SSE_I387
14132 && COMMUTATIVE_ARITH_P (operands[3])
14133 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14134 "* return output_387_binary_op (insn, operands);"
14135 [(set (attr "type")
14136 (if_then_else (eq_attr "alternative" "1")
14137 (if_then_else (match_operand:SF 3 "mult_operator" "")
14138 (const_string "ssemul")
14139 (const_string "sseadd"))
14140 (if_then_else (match_operand:SF 3 "mult_operator" "")
14141 (const_string "fmul")
14142 (const_string "fop"))))
14143 (set_attr "mode" "SF")])
14145 (define_insn "*fop_sf_comm_sse"
14146 [(set (match_operand:SF 0 "register_operand" "=x")
14147 (match_operator:SF 3 "binary_fp_operator"
14148 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14149 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14151 && COMMUTATIVE_ARITH_P (operands[3])
14152 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14153 "* return output_387_binary_op (insn, operands);"
14154 [(set (attr "type")
14155 (if_then_else (match_operand:SF 3 "mult_operator" "")
14156 (const_string "ssemul")
14157 (const_string "sseadd")))
14158 (set_attr "mode" "SF")])
14160 (define_insn "*fop_sf_comm_i387"
14161 [(set (match_operand:SF 0 "register_operand" "=f")
14162 (match_operator:SF 3 "binary_fp_operator"
14163 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14164 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14166 && COMMUTATIVE_ARITH_P (operands[3])
14167 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14168 "* return output_387_binary_op (insn, operands);"
14169 [(set (attr "type")
14170 (if_then_else (match_operand:SF 3 "mult_operator" "")
14171 (const_string "fmul")
14172 (const_string "fop")))
14173 (set_attr "mode" "SF")])
14175 (define_insn "*fop_sf_1_mixed"
14176 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14177 (match_operator:SF 3 "binary_fp_operator"
14178 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14179 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14180 "TARGET_MIX_SSE_I387
14181 && !COMMUTATIVE_ARITH_P (operands[3])
14182 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14183 "* return output_387_binary_op (insn, operands);"
14184 [(set (attr "type")
14185 (cond [(and (eq_attr "alternative" "2")
14186 (match_operand:SF 3 "mult_operator" ""))
14187 (const_string "ssemul")
14188 (and (eq_attr "alternative" "2")
14189 (match_operand:SF 3 "div_operator" ""))
14190 (const_string "ssediv")
14191 (eq_attr "alternative" "2")
14192 (const_string "sseadd")
14193 (match_operand:SF 3 "mult_operator" "")
14194 (const_string "fmul")
14195 (match_operand:SF 3 "div_operator" "")
14196 (const_string "fdiv")
14198 (const_string "fop")))
14199 (set_attr "mode" "SF")])
14201 (define_insn "*fop_sf_1_sse"
14202 [(set (match_operand:SF 0 "register_operand" "=x")
14203 (match_operator:SF 3 "binary_fp_operator"
14204 [(match_operand:SF 1 "register_operand" "0")
14205 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14207 && !COMMUTATIVE_ARITH_P (operands[3])"
14208 "* return output_387_binary_op (insn, operands);"
14209 [(set (attr "type")
14210 (cond [(match_operand:SF 3 "mult_operator" "")
14211 (const_string "ssemul")
14212 (match_operand:SF 3 "div_operator" "")
14213 (const_string "ssediv")
14215 (const_string "sseadd")))
14216 (set_attr "mode" "SF")])
14218 ;; This pattern is not fully shadowed by the pattern above.
14219 (define_insn "*fop_sf_1_i387"
14220 [(set (match_operand:SF 0 "register_operand" "=f,f")
14221 (match_operator:SF 3 "binary_fp_operator"
14222 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14223 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14224 "TARGET_80387 && !TARGET_SSE_MATH
14225 && !COMMUTATIVE_ARITH_P (operands[3])
14226 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14227 "* return output_387_binary_op (insn, operands);"
14228 [(set (attr "type")
14229 (cond [(match_operand:SF 3 "mult_operator" "")
14230 (const_string "fmul")
14231 (match_operand:SF 3 "div_operator" "")
14232 (const_string "fdiv")
14234 (const_string "fop")))
14235 (set_attr "mode" "SF")])
14238 ;; ??? Add SSE splitters for these!
14239 (define_insn "*fop_sf_2_i387"
14240 [(set (match_operand:SF 0 "register_operand" "=f,f")
14241 (match_operator:SF 3 "binary_fp_operator"
14242 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14243 (match_operand:SF 2 "register_operand" "0,0")]))]
14244 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14245 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14246 [(set (attr "type")
14247 (cond [(match_operand:SF 3 "mult_operator" "")
14248 (const_string "fmul")
14249 (match_operand:SF 3 "div_operator" "")
14250 (const_string "fdiv")
14252 (const_string "fop")))
14253 (set_attr "fp_int_src" "true")
14254 (set_attr "mode" "SI")])
14256 (define_insn "*fop_sf_3_i387"
14257 [(set (match_operand:SF 0 "register_operand" "=f,f")
14258 (match_operator:SF 3 "binary_fp_operator"
14259 [(match_operand:SF 1 "register_operand" "0,0")
14260 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14261 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14262 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14263 [(set (attr "type")
14264 (cond [(match_operand:SF 3 "mult_operator" "")
14265 (const_string "fmul")
14266 (match_operand:SF 3 "div_operator" "")
14267 (const_string "fdiv")
14269 (const_string "fop")))
14270 (set_attr "fp_int_src" "true")
14271 (set_attr "mode" "SI")])
14273 (define_insn "*fop_df_comm_mixed"
14274 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14275 (match_operator:DF 3 "binary_fp_operator"
14276 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14277 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14278 "TARGET_SSE2 && TARGET_MIX_SSE_I387
14279 && COMMUTATIVE_ARITH_P (operands[3])
14280 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14281 "* return output_387_binary_op (insn, operands);"
14282 [(set (attr "type")
14283 (if_then_else (eq_attr "alternative" "1")
14284 (if_then_else (match_operand:SF 3 "mult_operator" "")
14285 (const_string "ssemul")
14286 (const_string "sseadd"))
14287 (if_then_else (match_operand:SF 3 "mult_operator" "")
14288 (const_string "fmul")
14289 (const_string "fop"))))
14290 (set_attr "mode" "DF")])
14292 (define_insn "*fop_df_comm_sse"
14293 [(set (match_operand:DF 0 "register_operand" "=Y")
14294 (match_operator:DF 3 "binary_fp_operator"
14295 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14296 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14297 "TARGET_SSE2 && TARGET_SSE_MATH
14298 && COMMUTATIVE_ARITH_P (operands[3])
14299 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14300 "* return output_387_binary_op (insn, operands);"
14301 [(set (attr "type")
14302 (if_then_else (match_operand:SF 3 "mult_operator" "")
14303 (const_string "ssemul")
14304 (const_string "sseadd")))
14305 (set_attr "mode" "DF")])
14307 (define_insn "*fop_df_comm_i387"
14308 [(set (match_operand:DF 0 "register_operand" "=f")
14309 (match_operator:DF 3 "binary_fp_operator"
14310 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14311 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14313 && COMMUTATIVE_ARITH_P (operands[3])
14314 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14315 "* return output_387_binary_op (insn, operands);"
14316 [(set (attr "type")
14317 (if_then_else (match_operand:SF 3 "mult_operator" "")
14318 (const_string "fmul")
14319 (const_string "fop")))
14320 (set_attr "mode" "DF")])
14322 (define_insn "*fop_df_1_mixed"
14323 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14324 (match_operator:DF 3 "binary_fp_operator"
14325 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14326 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14327 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14328 && !COMMUTATIVE_ARITH_P (operands[3])
14329 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14330 "* return output_387_binary_op (insn, operands);"
14331 [(set (attr "type")
14332 (cond [(and (eq_attr "alternative" "2")
14333 (match_operand:SF 3 "mult_operator" ""))
14334 (const_string "ssemul")
14335 (and (eq_attr "alternative" "2")
14336 (match_operand:SF 3 "div_operator" ""))
14337 (const_string "ssediv")
14338 (eq_attr "alternative" "2")
14339 (const_string "sseadd")
14340 (match_operand:DF 3 "mult_operator" "")
14341 (const_string "fmul")
14342 (match_operand:DF 3 "div_operator" "")
14343 (const_string "fdiv")
14345 (const_string "fop")))
14346 (set_attr "mode" "DF")])
14348 (define_insn "*fop_df_1_sse"
14349 [(set (match_operand:DF 0 "register_operand" "=Y")
14350 (match_operator:DF 3 "binary_fp_operator"
14351 [(match_operand:DF 1 "register_operand" "0")
14352 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14353 "TARGET_SSE2 && TARGET_SSE_MATH
14354 && !COMMUTATIVE_ARITH_P (operands[3])"
14355 "* return output_387_binary_op (insn, operands);"
14356 [(set_attr "mode" "DF")
14358 (cond [(match_operand:SF 3 "mult_operator" "")
14359 (const_string "ssemul")
14360 (match_operand:SF 3 "div_operator" "")
14361 (const_string "ssediv")
14363 (const_string "sseadd")))])
14365 ;; This pattern is not fully shadowed by the pattern above.
14366 (define_insn "*fop_df_1_i387"
14367 [(set (match_operand:DF 0 "register_operand" "=f,f")
14368 (match_operator:DF 3 "binary_fp_operator"
14369 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14370 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14371 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
14372 && !COMMUTATIVE_ARITH_P (operands[3])
14373 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14374 "* return output_387_binary_op (insn, operands);"
14375 [(set (attr "type")
14376 (cond [(match_operand:DF 3 "mult_operator" "")
14377 (const_string "fmul")
14378 (match_operand:DF 3 "div_operator" "")
14379 (const_string "fdiv")
14381 (const_string "fop")))
14382 (set_attr "mode" "DF")])
14384 ;; ??? Add SSE splitters for these!
14385 (define_insn "*fop_df_2_i387"
14386 [(set (match_operand:DF 0 "register_operand" "=f,f")
14387 (match_operator:DF 3 "binary_fp_operator"
14388 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14389 (match_operand:DF 2 "register_operand" "0,0")]))]
14390 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14391 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14392 [(set (attr "type")
14393 (cond [(match_operand:DF 3 "mult_operator" "")
14394 (const_string "fmul")
14395 (match_operand:DF 3 "div_operator" "")
14396 (const_string "fdiv")
14398 (const_string "fop")))
14399 (set_attr "fp_int_src" "true")
14400 (set_attr "mode" "SI")])
14402 (define_insn "*fop_df_3_i387"
14403 [(set (match_operand:DF 0 "register_operand" "=f,f")
14404 (match_operator:DF 3 "binary_fp_operator"
14405 [(match_operand:DF 1 "register_operand" "0,0")
14406 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14407 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14408 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14409 [(set (attr "type")
14410 (cond [(match_operand:DF 3 "mult_operator" "")
14411 (const_string "fmul")
14412 (match_operand:DF 3 "div_operator" "")
14413 (const_string "fdiv")
14415 (const_string "fop")))
14416 (set_attr "fp_int_src" "true")
14417 (set_attr "mode" "SI")])
14419 (define_insn "*fop_df_4_i387"
14420 [(set (match_operand:DF 0 "register_operand" "=f,f")
14421 (match_operator:DF 3 "binary_fp_operator"
14422 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14423 (match_operand:DF 2 "register_operand" "0,f")]))]
14424 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
14425 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14426 "* return output_387_binary_op (insn, operands);"
14427 [(set (attr "type")
14428 (cond [(match_operand:DF 3 "mult_operator" "")
14429 (const_string "fmul")
14430 (match_operand:DF 3 "div_operator" "")
14431 (const_string "fdiv")
14433 (const_string "fop")))
14434 (set_attr "mode" "SF")])
14436 (define_insn "*fop_df_5_i387"
14437 [(set (match_operand:DF 0 "register_operand" "=f,f")
14438 (match_operator:DF 3 "binary_fp_operator"
14439 [(match_operand:DF 1 "register_operand" "0,f")
14441 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14442 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14443 "* return output_387_binary_op (insn, operands);"
14444 [(set (attr "type")
14445 (cond [(match_operand:DF 3 "mult_operator" "")
14446 (const_string "fmul")
14447 (match_operand:DF 3 "div_operator" "")
14448 (const_string "fdiv")
14450 (const_string "fop")))
14451 (set_attr "mode" "SF")])
14453 (define_insn "*fop_df_6_i387"
14454 [(set (match_operand:DF 0 "register_operand" "=f,f")
14455 (match_operator:DF 3 "binary_fp_operator"
14457 (match_operand:SF 1 "register_operand" "0,f"))
14459 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14460 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14461 "* return output_387_binary_op (insn, operands);"
14462 [(set (attr "type")
14463 (cond [(match_operand:DF 3 "mult_operator" "")
14464 (const_string "fmul")
14465 (match_operand:DF 3 "div_operator" "")
14466 (const_string "fdiv")
14468 (const_string "fop")))
14469 (set_attr "mode" "SF")])
14471 (define_insn "*fop_xf_comm_i387"
14472 [(set (match_operand:XF 0 "register_operand" "=f")
14473 (match_operator:XF 3 "binary_fp_operator"
14474 [(match_operand:XF 1 "register_operand" "%0")
14475 (match_operand:XF 2 "register_operand" "f")]))]
14477 && COMMUTATIVE_ARITH_P (operands[3])"
14478 "* return output_387_binary_op (insn, operands);"
14479 [(set (attr "type")
14480 (if_then_else (match_operand:XF 3 "mult_operator" "")
14481 (const_string "fmul")
14482 (const_string "fop")))
14483 (set_attr "mode" "XF")])
14485 (define_insn "*fop_xf_1_i387"
14486 [(set (match_operand:XF 0 "register_operand" "=f,f")
14487 (match_operator:XF 3 "binary_fp_operator"
14488 [(match_operand:XF 1 "register_operand" "0,f")
14489 (match_operand:XF 2 "register_operand" "f,0")]))]
14491 && !COMMUTATIVE_ARITH_P (operands[3])"
14492 "* return output_387_binary_op (insn, operands);"
14493 [(set (attr "type")
14494 (cond [(match_operand:XF 3 "mult_operator" "")
14495 (const_string "fmul")
14496 (match_operand:XF 3 "div_operator" "")
14497 (const_string "fdiv")
14499 (const_string "fop")))
14500 (set_attr "mode" "XF")])
14502 (define_insn "*fop_xf_2_i387"
14503 [(set (match_operand:XF 0 "register_operand" "=f,f")
14504 (match_operator:XF 3 "binary_fp_operator"
14505 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14506 (match_operand:XF 2 "register_operand" "0,0")]))]
14507 "TARGET_80387 && TARGET_USE_FIOP"
14508 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14509 [(set (attr "type")
14510 (cond [(match_operand:XF 3 "mult_operator" "")
14511 (const_string "fmul")
14512 (match_operand:XF 3 "div_operator" "")
14513 (const_string "fdiv")
14515 (const_string "fop")))
14516 (set_attr "fp_int_src" "true")
14517 (set_attr "mode" "SI")])
14519 (define_insn "*fop_xf_3_i387"
14520 [(set (match_operand:XF 0 "register_operand" "=f,f")
14521 (match_operator:XF 3 "binary_fp_operator"
14522 [(match_operand:XF 1 "register_operand" "0,0")
14523 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14524 "TARGET_80387 && TARGET_USE_FIOP"
14525 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14526 [(set (attr "type")
14527 (cond [(match_operand:XF 3 "mult_operator" "")
14528 (const_string "fmul")
14529 (match_operand:XF 3 "div_operator" "")
14530 (const_string "fdiv")
14532 (const_string "fop")))
14533 (set_attr "fp_int_src" "true")
14534 (set_attr "mode" "SI")])
14536 (define_insn "*fop_xf_4_i387"
14537 [(set (match_operand:XF 0 "register_operand" "=f,f")
14538 (match_operator:XF 3 "binary_fp_operator"
14539 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14540 (match_operand:XF 2 "register_operand" "0,f")]))]
14542 "* return output_387_binary_op (insn, operands);"
14543 [(set (attr "type")
14544 (cond [(match_operand:XF 3 "mult_operator" "")
14545 (const_string "fmul")
14546 (match_operand:XF 3 "div_operator" "")
14547 (const_string "fdiv")
14549 (const_string "fop")))
14550 (set_attr "mode" "SF")])
14552 (define_insn "*fop_xf_5_i387"
14553 [(set (match_operand:XF 0 "register_operand" "=f,f")
14554 (match_operator:XF 3 "binary_fp_operator"
14555 [(match_operand:XF 1 "register_operand" "0,f")
14557 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14559 "* return output_387_binary_op (insn, operands);"
14560 [(set (attr "type")
14561 (cond [(match_operand:XF 3 "mult_operator" "")
14562 (const_string "fmul")
14563 (match_operand:XF 3 "div_operator" "")
14564 (const_string "fdiv")
14566 (const_string "fop")))
14567 (set_attr "mode" "SF")])
14569 (define_insn "*fop_xf_6_i387"
14570 [(set (match_operand:XF 0 "register_operand" "=f,f")
14571 (match_operator:XF 3 "binary_fp_operator"
14573 (match_operand 1 "register_operand" "0,f"))
14575 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14577 "* return output_387_binary_op (insn, operands);"
14578 [(set (attr "type")
14579 (cond [(match_operand:XF 3 "mult_operator" "")
14580 (const_string "fmul")
14581 (match_operand:XF 3 "div_operator" "")
14582 (const_string "fdiv")
14584 (const_string "fop")))
14585 (set_attr "mode" "SF")])
14588 [(set (match_operand 0 "register_operand" "")
14589 (match_operator 3 "binary_fp_operator"
14590 [(float (match_operand:SI 1 "register_operand" ""))
14591 (match_operand 2 "register_operand" "")]))]
14592 "TARGET_80387 && reload_completed
14593 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14596 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14597 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14598 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14599 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14600 GET_MODE (operands[3]),
14603 ix86_free_from_memory (GET_MODE (operands[1]));
14608 [(set (match_operand 0 "register_operand" "")
14609 (match_operator 3 "binary_fp_operator"
14610 [(match_operand 1 "register_operand" "")
14611 (float (match_operand:SI 2 "register_operand" ""))]))]
14612 "TARGET_80387 && reload_completed
14613 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14616 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14617 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14618 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14619 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14620 GET_MODE (operands[3]),
14623 ix86_free_from_memory (GET_MODE (operands[2]));
14627 ;; FPU special functions.
14629 (define_expand "sqrtsf2"
14630 [(set (match_operand:SF 0 "register_operand" "")
14631 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14632 "TARGET_USE_FANCY_MATH_387 || TARGET_SSE_MATH"
14634 if (!TARGET_SSE_MATH)
14635 operands[1] = force_reg (SFmode, operands[1]);
14638 (define_insn "*sqrtsf2_mixed"
14639 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14640 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14641 "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387"
14644 sqrtss\t{%1, %0|%0, %1}"
14645 [(set_attr "type" "fpspc,sse")
14646 (set_attr "mode" "SF,SF")
14647 (set_attr "athlon_decode" "direct,*")])
14649 (define_insn "*sqrtsf2_sse"
14650 [(set (match_operand:SF 0 "register_operand" "=x")
14651 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14653 "sqrtss\t{%1, %0|%0, %1}"
14654 [(set_attr "type" "sse")
14655 (set_attr "mode" "SF")
14656 (set_attr "athlon_decode" "*")])
14658 (define_insn "*sqrtsf2_i387"
14659 [(set (match_operand:SF 0 "register_operand" "=f")
14660 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14661 "TARGET_USE_FANCY_MATH_387"
14663 [(set_attr "type" "fpspc")
14664 (set_attr "mode" "SF")
14665 (set_attr "athlon_decode" "direct")])
14667 (define_expand "sqrtdf2"
14668 [(set (match_operand:DF 0 "register_operand" "")
14669 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14670 "TARGET_USE_FANCY_MATH_387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14672 if (!(TARGET_SSE2 && TARGET_SSE_MATH))
14673 operands[1] = force_reg (DFmode, operands[1]);
14676 (define_insn "*sqrtdf2_mixed"
14677 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14678 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14679 "TARGET_USE_FANCY_MATH_387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"
14682 sqrtsd\t{%1, %0|%0, %1}"
14683 [(set_attr "type" "fpspc,sse")
14684 (set_attr "mode" "DF,DF")
14685 (set_attr "athlon_decode" "direct,*")])
14687 (define_insn "*sqrtdf2_sse"
14688 [(set (match_operand:DF 0 "register_operand" "=Y")
14689 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14690 "TARGET_SSE2 && TARGET_SSE_MATH"
14691 "sqrtsd\t{%1, %0|%0, %1}"
14692 [(set_attr "type" "sse")
14693 (set_attr "mode" "DF")
14694 (set_attr "athlon_decode" "*")])
14696 (define_insn "*sqrtdf2_i387"
14697 [(set (match_operand:DF 0 "register_operand" "=f")
14698 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14699 "TARGET_USE_FANCY_MATH_387"
14701 [(set_attr "type" "fpspc")
14702 (set_attr "mode" "DF")
14703 (set_attr "athlon_decode" "direct")])
14705 (define_insn "*sqrtextendsfdf2_i387"
14706 [(set (match_operand:DF 0 "register_operand" "=f")
14707 (sqrt:DF (float_extend:DF
14708 (match_operand:SF 1 "register_operand" "0"))))]
14709 "TARGET_USE_FANCY_MATH_387
14710 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
14712 [(set_attr "type" "fpspc")
14713 (set_attr "mode" "DF")
14714 (set_attr "athlon_decode" "direct")])
14716 (define_insn "sqrtxf2"
14717 [(set (match_operand:XF 0 "register_operand" "=f")
14718 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14719 "TARGET_USE_FANCY_MATH_387
14720 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14722 [(set_attr "type" "fpspc")
14723 (set_attr "mode" "XF")
14724 (set_attr "athlon_decode" "direct")])
14726 (define_insn "*sqrtextendsfxf2_i387"
14727 [(set (match_operand:XF 0 "register_operand" "=f")
14728 (sqrt:XF (float_extend:XF
14729 (match_operand:SF 1 "register_operand" "0"))))]
14730 "TARGET_USE_FANCY_MATH_387"
14732 [(set_attr "type" "fpspc")
14733 (set_attr "mode" "XF")
14734 (set_attr "athlon_decode" "direct")])
14736 (define_insn "*sqrtextenddfxf2_i387"
14737 [(set (match_operand:XF 0 "register_operand" "=f")
14738 (sqrt:XF (float_extend:XF
14739 (match_operand:DF 1 "register_operand" "0"))))]
14740 "TARGET_USE_FANCY_MATH_387"
14742 [(set_attr "type" "fpspc")
14743 (set_attr "mode" "XF")
14744 (set_attr "athlon_decode" "direct")])
14746 (define_insn "fpremxf4"
14747 [(set (match_operand:XF 0 "register_operand" "=f")
14748 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14749 (match_operand:XF 3 "register_operand" "1")]
14751 (set (match_operand:XF 1 "register_operand" "=u")
14752 (unspec:XF [(match_dup 2) (match_dup 3)]
14754 (set (reg:CCFP FPSR_REG)
14755 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
14756 "TARGET_USE_FANCY_MATH_387
14757 && flag_unsafe_math_optimizations"
14759 [(set_attr "type" "fpspc")
14760 (set_attr "mode" "XF")])
14762 (define_expand "fmodsf3"
14763 [(use (match_operand:SF 0 "register_operand" ""))
14764 (use (match_operand:SF 1 "register_operand" ""))
14765 (use (match_operand:SF 2 "register_operand" ""))]
14766 "TARGET_USE_FANCY_MATH_387
14767 && flag_unsafe_math_optimizations"
14769 rtx label = gen_label_rtx ();
14771 rtx op1 = gen_reg_rtx (XFmode);
14772 rtx op2 = gen_reg_rtx (XFmode);
14774 emit_insn(gen_extendsfxf2 (op1, operands[1]));
14775 emit_insn(gen_extendsfxf2 (op2, operands[2]));
14777 emit_label (label);
14779 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
14780 ix86_emit_fp_unordered_jump (label);
14782 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op1));
14786 (define_expand "fmoddf3"
14787 [(use (match_operand:DF 0 "register_operand" ""))
14788 (use (match_operand:DF 1 "register_operand" ""))
14789 (use (match_operand:DF 2 "register_operand" ""))]
14790 "TARGET_USE_FANCY_MATH_387
14791 && flag_unsafe_math_optimizations"
14793 rtx label = gen_label_rtx ();
14795 rtx op1 = gen_reg_rtx (XFmode);
14796 rtx op2 = gen_reg_rtx (XFmode);
14798 emit_insn (gen_extenddfxf2 (op1, operands[1]));
14799 emit_insn (gen_extenddfxf2 (op2, operands[2]));
14801 emit_label (label);
14803 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
14804 ix86_emit_fp_unordered_jump (label);
14806 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op1));
14810 (define_expand "fmodxf3"
14811 [(use (match_operand:XF 0 "register_operand" ""))
14812 (use (match_operand:XF 1 "register_operand" ""))
14813 (use (match_operand:XF 2 "register_operand" ""))]
14814 "TARGET_USE_FANCY_MATH_387
14815 && flag_unsafe_math_optimizations"
14817 rtx label = gen_label_rtx ();
14819 emit_label (label);
14821 emit_insn (gen_fpremxf4 (operands[1], operands[2],
14822 operands[1], operands[2]));
14823 ix86_emit_fp_unordered_jump (label);
14825 emit_move_insn (operands[0], operands[1]);
14829 (define_insn "fprem1xf4"
14830 [(set (match_operand:XF 0 "register_operand" "=f")
14831 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14832 (match_operand:XF 3 "register_operand" "1")]
14834 (set (match_operand:XF 1 "register_operand" "=u")
14835 (unspec:XF [(match_dup 2) (match_dup 3)]
14837 (set (reg:CCFP FPSR_REG)
14838 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
14839 "TARGET_USE_FANCY_MATH_387
14840 && flag_unsafe_math_optimizations"
14842 [(set_attr "type" "fpspc")
14843 (set_attr "mode" "XF")])
14845 (define_expand "dremsf3"
14846 [(use (match_operand:SF 0 "register_operand" ""))
14847 (use (match_operand:SF 1 "register_operand" ""))
14848 (use (match_operand:SF 2 "register_operand" ""))]
14849 "TARGET_USE_FANCY_MATH_387
14850 && flag_unsafe_math_optimizations"
14852 rtx label = gen_label_rtx ();
14854 rtx op1 = gen_reg_rtx (XFmode);
14855 rtx op2 = gen_reg_rtx (XFmode);
14857 emit_insn(gen_extendsfxf2 (op1, operands[1]));
14858 emit_insn(gen_extendsfxf2 (op2, operands[2]));
14860 emit_label (label);
14862 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
14863 ix86_emit_fp_unordered_jump (label);
14865 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op1));
14869 (define_expand "dremdf3"
14870 [(use (match_operand:DF 0 "register_operand" ""))
14871 (use (match_operand:DF 1 "register_operand" ""))
14872 (use (match_operand:DF 2 "register_operand" ""))]
14873 "TARGET_USE_FANCY_MATH_387
14874 && flag_unsafe_math_optimizations"
14876 rtx label = gen_label_rtx ();
14878 rtx op1 = gen_reg_rtx (XFmode);
14879 rtx op2 = gen_reg_rtx (XFmode);
14881 emit_insn (gen_extenddfxf2 (op1, operands[1]));
14882 emit_insn (gen_extenddfxf2 (op2, operands[2]));
14884 emit_label (label);
14886 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
14887 ix86_emit_fp_unordered_jump (label);
14889 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op1));
14893 (define_expand "dremxf3"
14894 [(use (match_operand:XF 0 "register_operand" ""))
14895 (use (match_operand:XF 1 "register_operand" ""))
14896 (use (match_operand:XF 2 "register_operand" ""))]
14897 "TARGET_USE_FANCY_MATH_387
14898 && flag_unsafe_math_optimizations"
14900 rtx label = gen_label_rtx ();
14902 emit_label (label);
14904 emit_insn (gen_fprem1xf4 (operands[1], operands[2],
14905 operands[1], operands[2]));
14906 ix86_emit_fp_unordered_jump (label);
14908 emit_move_insn (operands[0], operands[1]);
14912 (define_insn "*sindf2"
14913 [(set (match_operand:DF 0 "register_operand" "=f")
14914 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14915 "TARGET_USE_FANCY_MATH_387
14916 && flag_unsafe_math_optimizations"
14918 [(set_attr "type" "fpspc")
14919 (set_attr "mode" "DF")])
14921 (define_insn "*sinsf2"
14922 [(set (match_operand:SF 0 "register_operand" "=f")
14923 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14924 "TARGET_USE_FANCY_MATH_387
14925 && flag_unsafe_math_optimizations"
14927 [(set_attr "type" "fpspc")
14928 (set_attr "mode" "SF")])
14930 (define_insn "*sinextendsfdf2"
14931 [(set (match_operand:DF 0 "register_operand" "=f")
14932 (unspec:DF [(float_extend:DF
14933 (match_operand:SF 1 "register_operand" "0"))]
14935 "TARGET_USE_FANCY_MATH_387
14936 && flag_unsafe_math_optimizations"
14938 [(set_attr "type" "fpspc")
14939 (set_attr "mode" "DF")])
14941 (define_insn "*sinxf2"
14942 [(set (match_operand:XF 0 "register_operand" "=f")
14943 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14944 "TARGET_USE_FANCY_MATH_387
14945 && flag_unsafe_math_optimizations"
14947 [(set_attr "type" "fpspc")
14948 (set_attr "mode" "XF")])
14950 (define_insn "*cosdf2"
14951 [(set (match_operand:DF 0 "register_operand" "=f")
14952 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14953 "TARGET_USE_FANCY_MATH_387
14954 && flag_unsafe_math_optimizations"
14956 [(set_attr "type" "fpspc")
14957 (set_attr "mode" "DF")])
14959 (define_insn "*cossf2"
14960 [(set (match_operand:SF 0 "register_operand" "=f")
14961 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14962 "TARGET_USE_FANCY_MATH_387
14963 && flag_unsafe_math_optimizations"
14965 [(set_attr "type" "fpspc")
14966 (set_attr "mode" "SF")])
14968 (define_insn "*cosextendsfdf2"
14969 [(set (match_operand:DF 0 "register_operand" "=f")
14970 (unspec:DF [(float_extend:DF
14971 (match_operand:SF 1 "register_operand" "0"))]
14973 "TARGET_USE_FANCY_MATH_387
14974 && flag_unsafe_math_optimizations"
14976 [(set_attr "type" "fpspc")
14977 (set_attr "mode" "DF")])
14979 (define_insn "*cosxf2"
14980 [(set (match_operand:XF 0 "register_operand" "=f")
14981 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14982 "TARGET_USE_FANCY_MATH_387
14983 && flag_unsafe_math_optimizations"
14985 [(set_attr "type" "fpspc")
14986 (set_attr "mode" "XF")])
14988 ;; With sincos pattern defined, sin and cos builtin function will be
14989 ;; expanded to sincos pattern with one of its outputs left unused.
14990 ;; Cse pass will detected, if two sincos patterns can be combined,
14991 ;; otherwise sincos pattern will be split back to sin or cos pattern,
14992 ;; depending on the unused output.
14994 (define_insn "sincosdf3"
14995 [(set (match_operand:DF 0 "register_operand" "=f")
14996 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
14997 UNSPEC_SINCOS_COS))
14998 (set (match_operand:DF 1 "register_operand" "=u")
14999 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15000 "TARGET_USE_FANCY_MATH_387
15001 && flag_unsafe_math_optimizations"
15003 [(set_attr "type" "fpspc")
15004 (set_attr "mode" "DF")])
15007 [(set (match_operand:DF 0 "register_operand" "")
15008 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15009 UNSPEC_SINCOS_COS))
15010 (set (match_operand:DF 1 "register_operand" "")
15011 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15012 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15013 && !reload_completed && !reload_in_progress"
15014 [(set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_SIN))]
15018 [(set (match_operand:DF 0 "register_operand" "")
15019 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15020 UNSPEC_SINCOS_COS))
15021 (set (match_operand:DF 1 "register_operand" "")
15022 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15023 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15024 && !reload_completed && !reload_in_progress"
15025 [(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_COS))]
15028 (define_insn "sincossf3"
15029 [(set (match_operand:SF 0 "register_operand" "=f")
15030 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15031 UNSPEC_SINCOS_COS))
15032 (set (match_operand:SF 1 "register_operand" "=u")
15033 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15034 "TARGET_USE_FANCY_MATH_387
15035 && flag_unsafe_math_optimizations"
15037 [(set_attr "type" "fpspc")
15038 (set_attr "mode" "SF")])
15041 [(set (match_operand:SF 0 "register_operand" "")
15042 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15043 UNSPEC_SINCOS_COS))
15044 (set (match_operand:SF 1 "register_operand" "")
15045 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15046 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15047 && !reload_completed && !reload_in_progress"
15048 [(set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_SIN))]
15052 [(set (match_operand:SF 0 "register_operand" "")
15053 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15054 UNSPEC_SINCOS_COS))
15055 (set (match_operand:SF 1 "register_operand" "")
15056 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15057 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15058 && !reload_completed && !reload_in_progress"
15059 [(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_COS))]
15062 (define_insn "*sincosextendsfdf3"
15063 [(set (match_operand:DF 0 "register_operand" "=f")
15064 (unspec:DF [(float_extend:DF
15065 (match_operand:SF 2 "register_operand" "0"))]
15066 UNSPEC_SINCOS_COS))
15067 (set (match_operand:DF 1 "register_operand" "=u")
15068 (unspec:DF [(float_extend:DF
15069 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15070 "TARGET_USE_FANCY_MATH_387
15071 && flag_unsafe_math_optimizations"
15073 [(set_attr "type" "fpspc")
15074 (set_attr "mode" "DF")])
15077 [(set (match_operand:DF 0 "register_operand" "")
15078 (unspec:DF [(float_extend:DF
15079 (match_operand:SF 2 "register_operand" ""))]
15080 UNSPEC_SINCOS_COS))
15081 (set (match_operand:DF 1 "register_operand" "")
15082 (unspec:DF [(float_extend:DF
15083 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15084 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15085 && !reload_completed && !reload_in_progress"
15086 [(set (match_dup 1) (unspec:DF [(float_extend:DF
15087 (match_dup 2))] UNSPEC_SIN))]
15091 [(set (match_operand:DF 0 "register_operand" "")
15092 (unspec:DF [(float_extend:DF
15093 (match_operand:SF 2 "register_operand" ""))]
15094 UNSPEC_SINCOS_COS))
15095 (set (match_operand:DF 1 "register_operand" "")
15096 (unspec:DF [(float_extend:DF
15097 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15098 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15099 && !reload_completed && !reload_in_progress"
15100 [(set (match_dup 0) (unspec:DF [(float_extend:DF
15101 (match_dup 2))] UNSPEC_COS))]
15104 (define_insn "sincosxf3"
15105 [(set (match_operand:XF 0 "register_operand" "=f")
15106 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15107 UNSPEC_SINCOS_COS))
15108 (set (match_operand:XF 1 "register_operand" "=u")
15109 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15110 "TARGET_USE_FANCY_MATH_387
15111 && flag_unsafe_math_optimizations"
15113 [(set_attr "type" "fpspc")
15114 (set_attr "mode" "XF")])
15117 [(set (match_operand:XF 0 "register_operand" "")
15118 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15119 UNSPEC_SINCOS_COS))
15120 (set (match_operand:XF 1 "register_operand" "")
15121 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15122 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15123 && !reload_completed && !reload_in_progress"
15124 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
15128 [(set (match_operand:XF 0 "register_operand" "")
15129 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15130 UNSPEC_SINCOS_COS))
15131 (set (match_operand:XF 1 "register_operand" "")
15132 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15133 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15134 && !reload_completed && !reload_in_progress"
15135 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
15138 (define_insn "*tandf3_1"
15139 [(set (match_operand:DF 0 "register_operand" "=f")
15140 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15142 (set (match_operand:DF 1 "register_operand" "=u")
15143 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
15144 "TARGET_USE_FANCY_MATH_387
15145 && flag_unsafe_math_optimizations"
15147 [(set_attr "type" "fpspc")
15148 (set_attr "mode" "DF")])
15150 ;; optimize sequence: fptan
15153 ;; into fptan insn.
15156 [(parallel[(set (match_operand:DF 0 "register_operand" "")
15157 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15159 (set (match_operand:DF 1 "register_operand" "")
15160 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])
15162 (match_operand:DF 3 "immediate_operand" ""))]
15163 "standard_80387_constant_p (operands[3]) == 2"
15164 [(parallel[(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_TAN_ONE))
15165 (set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15168 (define_expand "tandf2"
15169 [(parallel [(set (match_dup 2)
15170 (unspec:DF [(match_operand:DF 1 "register_operand" "")]
15172 (set (match_operand:DF 0 "register_operand" "")
15173 (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15174 "TARGET_USE_FANCY_MATH_387
15175 && flag_unsafe_math_optimizations"
15177 operands[2] = gen_reg_rtx (DFmode);
15180 (define_insn "*tansf3_1"
15181 [(set (match_operand:SF 0 "register_operand" "=f")
15182 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15184 (set (match_operand:SF 1 "register_operand" "=u")
15185 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
15186 "TARGET_USE_FANCY_MATH_387
15187 && flag_unsafe_math_optimizations"
15189 [(set_attr "type" "fpspc")
15190 (set_attr "mode" "SF")])
15192 ;; optimize sequence: fptan
15195 ;; into fptan insn.
15198 [(parallel[(set (match_operand:SF 0 "register_operand" "")
15199 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15201 (set (match_operand:SF 1 "register_operand" "")
15202 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])
15204 (match_operand:SF 3 "immediate_operand" ""))]
15205 "standard_80387_constant_p (operands[3]) == 2"
15206 [(parallel[(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_TAN_ONE))
15207 (set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15210 (define_expand "tansf2"
15211 [(parallel [(set (match_dup 2)
15212 (unspec:SF [(match_operand:SF 1 "register_operand" "")]
15214 (set (match_operand:SF 0 "register_operand" "")
15215 (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15216 "TARGET_USE_FANCY_MATH_387
15217 && flag_unsafe_math_optimizations"
15219 operands[2] = gen_reg_rtx (SFmode);
15222 (define_insn "*tanxf3_1"
15223 [(set (match_operand:XF 0 "register_operand" "=f")
15224 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15226 (set (match_operand:XF 1 "register_operand" "=u")
15227 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
15228 "TARGET_USE_FANCY_MATH_387
15229 && flag_unsafe_math_optimizations"
15231 [(set_attr "type" "fpspc")
15232 (set_attr "mode" "XF")])
15234 ;; optimize sequence: fptan
15237 ;; into fptan insn.
15240 [(parallel[(set (match_operand:XF 0 "register_operand" "")
15241 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15243 (set (match_operand:XF 1 "register_operand" "")
15244 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])
15246 (match_operand:XF 3 "immediate_operand" ""))]
15247 "standard_80387_constant_p (operands[3]) == 2"
15248 [(parallel[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_TAN_ONE))
15249 (set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15252 (define_expand "tanxf2"
15253 [(parallel [(set (match_dup 2)
15254 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15256 (set (match_operand:XF 0 "register_operand" "")
15257 (unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15258 "TARGET_USE_FANCY_MATH_387
15259 && flag_unsafe_math_optimizations"
15261 operands[2] = gen_reg_rtx (XFmode);
15264 (define_insn "atan2df3_1"
15265 [(set (match_operand:DF 0 "register_operand" "=f")
15266 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15267 (match_operand:DF 1 "register_operand" "u")]
15269 (clobber (match_scratch:DF 3 "=1"))]
15270 "TARGET_USE_FANCY_MATH_387
15271 && flag_unsafe_math_optimizations"
15273 [(set_attr "type" "fpspc")
15274 (set_attr "mode" "DF")])
15276 (define_expand "atan2df3"
15277 [(use (match_operand:DF 0 "register_operand" "=f"))
15278 (use (match_operand:DF 2 "register_operand" "0"))
15279 (use (match_operand:DF 1 "register_operand" "u"))]
15280 "TARGET_USE_FANCY_MATH_387
15281 && flag_unsafe_math_optimizations"
15283 rtx copy = gen_reg_rtx (DFmode);
15284 emit_move_insn (copy, operands[1]);
15285 emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
15289 (define_expand "atandf2"
15290 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15291 (unspec:DF [(match_dup 2)
15292 (match_operand:DF 1 "register_operand" "")]
15294 (clobber (match_scratch:DF 3 ""))])]
15295 "TARGET_USE_FANCY_MATH_387
15296 && flag_unsafe_math_optimizations"
15298 operands[2] = gen_reg_rtx (DFmode);
15299 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15302 (define_insn "atan2sf3_1"
15303 [(set (match_operand:SF 0 "register_operand" "=f")
15304 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15305 (match_operand:SF 1 "register_operand" "u")]
15307 (clobber (match_scratch:SF 3 "=1"))]
15308 "TARGET_USE_FANCY_MATH_387
15309 && flag_unsafe_math_optimizations"
15311 [(set_attr "type" "fpspc")
15312 (set_attr "mode" "SF")])
15314 (define_expand "atan2sf3"
15315 [(use (match_operand:SF 0 "register_operand" "=f"))
15316 (use (match_operand:SF 2 "register_operand" "0"))
15317 (use (match_operand:SF 1 "register_operand" "u"))]
15318 "TARGET_USE_FANCY_MATH_387
15319 && flag_unsafe_math_optimizations"
15321 rtx copy = gen_reg_rtx (SFmode);
15322 emit_move_insn (copy, operands[1]);
15323 emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
15327 (define_expand "atansf2"
15328 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15329 (unspec:SF [(match_dup 2)
15330 (match_operand:SF 1 "register_operand" "")]
15332 (clobber (match_scratch:SF 3 ""))])]
15333 "TARGET_USE_FANCY_MATH_387
15334 && flag_unsafe_math_optimizations"
15336 operands[2] = gen_reg_rtx (SFmode);
15337 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15340 (define_insn "atan2xf3_1"
15341 [(set (match_operand:XF 0 "register_operand" "=f")
15342 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15343 (match_operand:XF 1 "register_operand" "u")]
15345 (clobber (match_scratch:XF 3 "=1"))]
15346 "TARGET_USE_FANCY_MATH_387
15347 && flag_unsafe_math_optimizations"
15349 [(set_attr "type" "fpspc")
15350 (set_attr "mode" "XF")])
15352 (define_expand "atan2xf3"
15353 [(use (match_operand:XF 0 "register_operand" "=f"))
15354 (use (match_operand:XF 2 "register_operand" "0"))
15355 (use (match_operand:XF 1 "register_operand" "u"))]
15356 "TARGET_USE_FANCY_MATH_387
15357 && flag_unsafe_math_optimizations"
15359 rtx copy = gen_reg_rtx (XFmode);
15360 emit_move_insn (copy, operands[1]);
15361 emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
15365 (define_expand "atanxf2"
15366 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15367 (unspec:XF [(match_dup 2)
15368 (match_operand:XF 1 "register_operand" "")]
15370 (clobber (match_scratch:XF 3 ""))])]
15371 "TARGET_USE_FANCY_MATH_387
15372 && flag_unsafe_math_optimizations"
15374 operands[2] = gen_reg_rtx (XFmode);
15375 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15378 (define_expand "asindf2"
15379 [(set (match_dup 2)
15380 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15381 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15382 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15383 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15384 (parallel [(set (match_dup 7)
15385 (unspec:XF [(match_dup 6) (match_dup 2)]
15387 (clobber (match_scratch:XF 8 ""))])
15388 (set (match_operand:DF 0 "register_operand" "")
15389 (float_truncate:DF (match_dup 7)))]
15390 "TARGET_USE_FANCY_MATH_387
15391 && flag_unsafe_math_optimizations"
15395 for (i=2; i<8; i++)
15396 operands[i] = gen_reg_rtx (XFmode);
15398 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15401 (define_expand "asinsf2"
15402 [(set (match_dup 2)
15403 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15404 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15405 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15406 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15407 (parallel [(set (match_dup 7)
15408 (unspec:XF [(match_dup 6) (match_dup 2)]
15410 (clobber (match_scratch:XF 8 ""))])
15411 (set (match_operand:SF 0 "register_operand" "")
15412 (float_truncate:SF (match_dup 7)))]
15413 "TARGET_USE_FANCY_MATH_387
15414 && flag_unsafe_math_optimizations"
15418 for (i=2; i<8; i++)
15419 operands[i] = gen_reg_rtx (XFmode);
15421 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15424 (define_expand "asinxf2"
15425 [(set (match_dup 2)
15426 (mult:XF (match_operand:XF 1 "register_operand" "")
15428 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15429 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15430 (parallel [(set (match_operand:XF 0 "register_operand" "")
15431 (unspec:XF [(match_dup 5) (match_dup 1)]
15433 (clobber (match_scratch:XF 6 ""))])]
15434 "TARGET_USE_FANCY_MATH_387
15435 && flag_unsafe_math_optimizations"
15439 for (i=2; i<6; i++)
15440 operands[i] = gen_reg_rtx (XFmode);
15442 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15445 (define_expand "acosdf2"
15446 [(set (match_dup 2)
15447 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15448 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15449 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15450 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15451 (parallel [(set (match_dup 7)
15452 (unspec:XF [(match_dup 2) (match_dup 6)]
15454 (clobber (match_scratch:XF 8 ""))])
15455 (set (match_operand:DF 0 "register_operand" "")
15456 (float_truncate:DF (match_dup 7)))]
15457 "TARGET_USE_FANCY_MATH_387
15458 && flag_unsafe_math_optimizations"
15462 for (i=2; i<8; i++)
15463 operands[i] = gen_reg_rtx (XFmode);
15465 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15468 (define_expand "acossf2"
15469 [(set (match_dup 2)
15470 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15471 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15472 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15473 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15474 (parallel [(set (match_dup 7)
15475 (unspec:XF [(match_dup 2) (match_dup 6)]
15477 (clobber (match_scratch:XF 8 ""))])
15478 (set (match_operand:SF 0 "register_operand" "")
15479 (float_truncate:SF (match_dup 7)))]
15480 "TARGET_USE_FANCY_MATH_387
15481 && flag_unsafe_math_optimizations"
15485 for (i=2; i<8; i++)
15486 operands[i] = gen_reg_rtx (XFmode);
15488 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15491 (define_expand "acosxf2"
15492 [(set (match_dup 2)
15493 (mult:XF (match_operand:XF 1 "register_operand" "")
15495 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15496 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15497 (parallel [(set (match_operand:XF 0 "register_operand" "")
15498 (unspec:XF [(match_dup 1) (match_dup 5)]
15500 (clobber (match_scratch:XF 6 ""))])]
15501 "TARGET_USE_FANCY_MATH_387
15502 && flag_unsafe_math_optimizations"
15506 for (i=2; i<6; i++)
15507 operands[i] = gen_reg_rtx (XFmode);
15509 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15512 (define_insn "fyl2x_xf3"
15513 [(set (match_operand:XF 0 "register_operand" "=f")
15514 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15515 (match_operand:XF 1 "register_operand" "u")]
15517 (clobber (match_scratch:XF 3 "=1"))]
15518 "TARGET_USE_FANCY_MATH_387
15519 && flag_unsafe_math_optimizations"
15521 [(set_attr "type" "fpspc")
15522 (set_attr "mode" "XF")])
15524 (define_expand "logsf2"
15525 [(set (match_dup 2)
15526 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15527 (parallel [(set (match_dup 4)
15528 (unspec:XF [(match_dup 2)
15529 (match_dup 3)] UNSPEC_FYL2X))
15530 (clobber (match_scratch:XF 5 ""))])
15531 (set (match_operand:SF 0 "register_operand" "")
15532 (float_truncate:SF (match_dup 4)))]
15533 "TARGET_USE_FANCY_MATH_387
15534 && flag_unsafe_math_optimizations"
15538 operands[2] = gen_reg_rtx (XFmode);
15539 operands[3] = gen_reg_rtx (XFmode);
15540 operands[4] = gen_reg_rtx (XFmode);
15542 temp = standard_80387_constant_rtx (4); /* fldln2 */
15543 emit_move_insn (operands[3], temp);
15546 (define_expand "logdf2"
15547 [(set (match_dup 2)
15548 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15549 (parallel [(set (match_dup 4)
15550 (unspec:XF [(match_dup 2)
15551 (match_dup 3)] UNSPEC_FYL2X))
15552 (clobber (match_scratch:XF 5 ""))])
15553 (set (match_operand:DF 0 "register_operand" "")
15554 (float_truncate:DF (match_dup 4)))]
15555 "TARGET_USE_FANCY_MATH_387
15556 && flag_unsafe_math_optimizations"
15560 operands[2] = gen_reg_rtx (XFmode);
15561 operands[3] = gen_reg_rtx (XFmode);
15562 operands[4] = gen_reg_rtx (XFmode);
15564 temp = standard_80387_constant_rtx (4); /* fldln2 */
15565 emit_move_insn (operands[3], temp);
15568 (define_expand "logxf2"
15569 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15570 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15571 (match_dup 2)] UNSPEC_FYL2X))
15572 (clobber (match_scratch:XF 3 ""))])]
15573 "TARGET_USE_FANCY_MATH_387
15574 && flag_unsafe_math_optimizations"
15578 operands[2] = gen_reg_rtx (XFmode);
15579 temp = standard_80387_constant_rtx (4); /* fldln2 */
15580 emit_move_insn (operands[2], temp);
15583 (define_expand "log10sf2"
15584 [(set (match_dup 2)
15585 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15586 (parallel [(set (match_dup 4)
15587 (unspec:XF [(match_dup 2)
15588 (match_dup 3)] UNSPEC_FYL2X))
15589 (clobber (match_scratch:XF 5 ""))])
15590 (set (match_operand:SF 0 "register_operand" "")
15591 (float_truncate:SF (match_dup 4)))]
15592 "TARGET_USE_FANCY_MATH_387
15593 && flag_unsafe_math_optimizations"
15597 operands[2] = gen_reg_rtx (XFmode);
15598 operands[3] = gen_reg_rtx (XFmode);
15599 operands[4] = gen_reg_rtx (XFmode);
15601 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15602 emit_move_insn (operands[3], temp);
15605 (define_expand "log10df2"
15606 [(set (match_dup 2)
15607 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15608 (parallel [(set (match_dup 4)
15609 (unspec:XF [(match_dup 2)
15610 (match_dup 3)] UNSPEC_FYL2X))
15611 (clobber (match_scratch:XF 5 ""))])
15612 (set (match_operand:DF 0 "register_operand" "")
15613 (float_truncate:DF (match_dup 4)))]
15614 "TARGET_USE_FANCY_MATH_387
15615 && flag_unsafe_math_optimizations"
15619 operands[2] = gen_reg_rtx (XFmode);
15620 operands[3] = gen_reg_rtx (XFmode);
15621 operands[4] = gen_reg_rtx (XFmode);
15623 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15624 emit_move_insn (operands[3], temp);
15627 (define_expand "log10xf2"
15628 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15629 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15630 (match_dup 2)] UNSPEC_FYL2X))
15631 (clobber (match_scratch:XF 3 ""))])]
15632 "TARGET_USE_FANCY_MATH_387
15633 && flag_unsafe_math_optimizations"
15637 operands[2] = gen_reg_rtx (XFmode);
15638 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15639 emit_move_insn (operands[2], temp);
15642 (define_expand "log2sf2"
15643 [(set (match_dup 2)
15644 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15645 (parallel [(set (match_dup 4)
15646 (unspec:XF [(match_dup 2)
15647 (match_dup 3)] UNSPEC_FYL2X))
15648 (clobber (match_scratch:XF 5 ""))])
15649 (set (match_operand:SF 0 "register_operand" "")
15650 (float_truncate:SF (match_dup 4)))]
15651 "TARGET_USE_FANCY_MATH_387
15652 && flag_unsafe_math_optimizations"
15654 operands[2] = gen_reg_rtx (XFmode);
15655 operands[3] = gen_reg_rtx (XFmode);
15656 operands[4] = gen_reg_rtx (XFmode);
15658 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15661 (define_expand "log2df2"
15662 [(set (match_dup 2)
15663 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15664 (parallel [(set (match_dup 4)
15665 (unspec:XF [(match_dup 2)
15666 (match_dup 3)] UNSPEC_FYL2X))
15667 (clobber (match_scratch:XF 5 ""))])
15668 (set (match_operand:DF 0 "register_operand" "")
15669 (float_truncate:DF (match_dup 4)))]
15670 "TARGET_USE_FANCY_MATH_387
15671 && flag_unsafe_math_optimizations"
15673 operands[2] = gen_reg_rtx (XFmode);
15674 operands[3] = gen_reg_rtx (XFmode);
15675 operands[4] = gen_reg_rtx (XFmode);
15677 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15680 (define_expand "log2xf2"
15681 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15682 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15683 (match_dup 2)] UNSPEC_FYL2X))
15684 (clobber (match_scratch:XF 3 ""))])]
15685 "TARGET_USE_FANCY_MATH_387
15686 && flag_unsafe_math_optimizations"
15688 operands[2] = gen_reg_rtx (XFmode);
15689 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15692 (define_insn "fyl2xp1_xf3"
15693 [(set (match_operand:XF 0 "register_operand" "=f")
15694 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15695 (match_operand:XF 1 "register_operand" "u")]
15697 (clobber (match_scratch:XF 3 "=1"))]
15698 "TARGET_USE_FANCY_MATH_387
15699 && flag_unsafe_math_optimizations"
15701 [(set_attr "type" "fpspc")
15702 (set_attr "mode" "XF")])
15704 (define_expand "log1psf2"
15705 [(use (match_operand:SF 0 "register_operand" ""))
15706 (use (match_operand:SF 1 "register_operand" ""))]
15707 "TARGET_USE_FANCY_MATH_387
15708 && flag_unsafe_math_optimizations"
15710 rtx op0 = gen_reg_rtx (XFmode);
15711 rtx op1 = gen_reg_rtx (XFmode);
15713 emit_insn (gen_extendsfxf2 (op1, operands[1]));
15714 ix86_emit_i387_log1p (op0, op1);
15715 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
15719 (define_expand "log1pdf2"
15720 [(use (match_operand:DF 0 "register_operand" ""))
15721 (use (match_operand:DF 1 "register_operand" ""))]
15722 "TARGET_USE_FANCY_MATH_387
15723 && flag_unsafe_math_optimizations"
15725 rtx op0 = gen_reg_rtx (XFmode);
15726 rtx op1 = gen_reg_rtx (XFmode);
15728 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15729 ix86_emit_i387_log1p (op0, op1);
15730 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
15734 (define_expand "log1pxf2"
15735 [(use (match_operand:XF 0 "register_operand" ""))
15736 (use (match_operand:XF 1 "register_operand" ""))]
15737 "TARGET_USE_FANCY_MATH_387
15738 && flag_unsafe_math_optimizations"
15740 ix86_emit_i387_log1p (operands[0], operands[1]);
15744 (define_insn "*fxtractxf3"
15745 [(set (match_operand:XF 0 "register_operand" "=f")
15746 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15747 UNSPEC_XTRACT_FRACT))
15748 (set (match_operand:XF 1 "register_operand" "=u")
15749 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
15750 "TARGET_USE_FANCY_MATH_387
15751 && flag_unsafe_math_optimizations"
15753 [(set_attr "type" "fpspc")
15754 (set_attr "mode" "XF")])
15756 (define_expand "logbsf2"
15757 [(set (match_dup 2)
15758 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15759 (parallel [(set (match_dup 3)
15760 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
15762 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
15763 (set (match_operand:SF 0 "register_operand" "")
15764 (float_truncate:SF (match_dup 4)))]
15765 "TARGET_USE_FANCY_MATH_387
15766 && flag_unsafe_math_optimizations"
15768 operands[2] = gen_reg_rtx (XFmode);
15769 operands[3] = gen_reg_rtx (XFmode);
15770 operands[4] = gen_reg_rtx (XFmode);
15773 (define_expand "logbdf2"
15774 [(set (match_dup 2)
15775 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15776 (parallel [(set (match_dup 3)
15777 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
15779 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
15780 (set (match_operand:DF 0 "register_operand" "")
15781 (float_truncate:DF (match_dup 4)))]
15782 "TARGET_USE_FANCY_MATH_387
15783 && flag_unsafe_math_optimizations"
15785 operands[2] = gen_reg_rtx (XFmode);
15786 operands[3] = gen_reg_rtx (XFmode);
15787 operands[4] = gen_reg_rtx (XFmode);
15790 (define_expand "logbxf2"
15791 [(parallel [(set (match_dup 2)
15792 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15793 UNSPEC_XTRACT_FRACT))
15794 (set (match_operand:XF 0 "register_operand" "")
15795 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
15796 "TARGET_USE_FANCY_MATH_387
15797 && flag_unsafe_math_optimizations"
15799 operands[2] = gen_reg_rtx (XFmode);
15802 (define_expand "ilogbsi2"
15803 [(parallel [(set (match_dup 2)
15804 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15805 UNSPEC_XTRACT_FRACT))
15806 (set (match_operand:XF 3 "register_operand" "")
15807 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])
15808 (parallel [(set (match_operand:SI 0 "register_operand" "")
15809 (fix:SI (match_dup 3)))
15810 (clobber (reg:CC FLAGS_REG))])]
15811 "TARGET_USE_FANCY_MATH_387
15812 && flag_unsafe_math_optimizations"
15814 operands[2] = gen_reg_rtx (XFmode);
15815 operands[3] = gen_reg_rtx (XFmode);
15818 (define_insn "*f2xm1xf2"
15819 [(set (match_operand:XF 0 "register_operand" "=f")
15820 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15822 "TARGET_USE_FANCY_MATH_387
15823 && flag_unsafe_math_optimizations"
15825 [(set_attr "type" "fpspc")
15826 (set_attr "mode" "XF")])
15828 (define_insn "*fscalexf4"
15829 [(set (match_operand:XF 0 "register_operand" "=f")
15830 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15831 (match_operand:XF 3 "register_operand" "1")]
15832 UNSPEC_FSCALE_FRACT))
15833 (set (match_operand:XF 1 "register_operand" "=u")
15834 (unspec:XF [(match_dup 2) (match_dup 3)]
15835 UNSPEC_FSCALE_EXP))]
15836 "TARGET_USE_FANCY_MATH_387
15837 && flag_unsafe_math_optimizations"
15839 [(set_attr "type" "fpspc")
15840 (set_attr "mode" "XF")])
15842 (define_expand "expsf2"
15843 [(set (match_dup 2)
15844 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15845 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15846 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15847 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15848 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15849 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15850 (parallel [(set (match_dup 10)
15851 (unspec:XF [(match_dup 9) (match_dup 5)]
15852 UNSPEC_FSCALE_FRACT))
15853 (set (match_dup 11)
15854 (unspec:XF [(match_dup 9) (match_dup 5)]
15855 UNSPEC_FSCALE_EXP))])
15856 (set (match_operand:SF 0 "register_operand" "")
15857 (float_truncate:SF (match_dup 10)))]
15858 "TARGET_USE_FANCY_MATH_387
15859 && flag_unsafe_math_optimizations"
15864 for (i=2; i<12; i++)
15865 operands[i] = gen_reg_rtx (XFmode);
15866 temp = standard_80387_constant_rtx (5); /* fldl2e */
15867 emit_move_insn (operands[3], temp);
15868 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15871 (define_expand "expdf2"
15872 [(set (match_dup 2)
15873 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15874 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15875 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15876 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15877 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15878 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15879 (parallel [(set (match_dup 10)
15880 (unspec:XF [(match_dup 9) (match_dup 5)]
15881 UNSPEC_FSCALE_FRACT))
15882 (set (match_dup 11)
15883 (unspec:XF [(match_dup 9) (match_dup 5)]
15884 UNSPEC_FSCALE_EXP))])
15885 (set (match_operand:DF 0 "register_operand" "")
15886 (float_truncate:DF (match_dup 10)))]
15887 "TARGET_USE_FANCY_MATH_387
15888 && flag_unsafe_math_optimizations"
15893 for (i=2; i<12; i++)
15894 operands[i] = gen_reg_rtx (XFmode);
15895 temp = standard_80387_constant_rtx (5); /* fldl2e */
15896 emit_move_insn (operands[3], temp);
15897 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15900 (define_expand "expxf2"
15901 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15903 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15904 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15905 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15906 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15907 (parallel [(set (match_operand:XF 0 "register_operand" "")
15908 (unspec:XF [(match_dup 8) (match_dup 4)]
15909 UNSPEC_FSCALE_FRACT))
15911 (unspec:XF [(match_dup 8) (match_dup 4)]
15912 UNSPEC_FSCALE_EXP))])]
15913 "TARGET_USE_FANCY_MATH_387
15914 && flag_unsafe_math_optimizations"
15919 for (i=2; i<10; i++)
15920 operands[i] = gen_reg_rtx (XFmode);
15921 temp = standard_80387_constant_rtx (5); /* fldl2e */
15922 emit_move_insn (operands[2], temp);
15923 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
15926 (define_expand "exp10sf2"
15927 [(set (match_dup 2)
15928 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15929 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15930 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15931 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15932 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15933 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15934 (parallel [(set (match_dup 10)
15935 (unspec:XF [(match_dup 9) (match_dup 5)]
15936 UNSPEC_FSCALE_FRACT))
15937 (set (match_dup 11)
15938 (unspec:XF [(match_dup 9) (match_dup 5)]
15939 UNSPEC_FSCALE_EXP))])
15940 (set (match_operand:SF 0 "register_operand" "")
15941 (float_truncate:SF (match_dup 10)))]
15942 "TARGET_USE_FANCY_MATH_387
15943 && flag_unsafe_math_optimizations"
15948 for (i=2; i<12; i++)
15949 operands[i] = gen_reg_rtx (XFmode);
15950 temp = standard_80387_constant_rtx (6); /* fldl2t */
15951 emit_move_insn (operands[3], temp);
15952 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15955 (define_expand "exp10df2"
15956 [(set (match_dup 2)
15957 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15958 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15959 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15960 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15961 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15962 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15963 (parallel [(set (match_dup 10)
15964 (unspec:XF [(match_dup 9) (match_dup 5)]
15965 UNSPEC_FSCALE_FRACT))
15966 (set (match_dup 11)
15967 (unspec:XF [(match_dup 9) (match_dup 5)]
15968 UNSPEC_FSCALE_EXP))])
15969 (set (match_operand:DF 0 "register_operand" "")
15970 (float_truncate:DF (match_dup 10)))]
15971 "TARGET_USE_FANCY_MATH_387
15972 && flag_unsafe_math_optimizations"
15977 for (i=2; i<12; i++)
15978 operands[i] = gen_reg_rtx (XFmode);
15979 temp = standard_80387_constant_rtx (6); /* fldl2t */
15980 emit_move_insn (operands[3], temp);
15981 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15984 (define_expand "exp10xf2"
15985 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15987 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15988 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15989 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15990 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15991 (parallel [(set (match_operand:XF 0 "register_operand" "")
15992 (unspec:XF [(match_dup 8) (match_dup 4)]
15993 UNSPEC_FSCALE_FRACT))
15995 (unspec:XF [(match_dup 8) (match_dup 4)]
15996 UNSPEC_FSCALE_EXP))])]
15997 "TARGET_USE_FANCY_MATH_387
15998 && flag_unsafe_math_optimizations"
16003 for (i=2; i<10; i++)
16004 operands[i] = gen_reg_rtx (XFmode);
16005 temp = standard_80387_constant_rtx (6); /* fldl2t */
16006 emit_move_insn (operands[2], temp);
16007 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
16010 (define_expand "exp2sf2"
16011 [(set (match_dup 2)
16012 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16013 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16014 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16015 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16016 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16017 (parallel [(set (match_dup 8)
16018 (unspec:XF [(match_dup 7) (match_dup 3)]
16019 UNSPEC_FSCALE_FRACT))
16021 (unspec:XF [(match_dup 7) (match_dup 3)]
16022 UNSPEC_FSCALE_EXP))])
16023 (set (match_operand:SF 0 "register_operand" "")
16024 (float_truncate:SF (match_dup 8)))]
16025 "TARGET_USE_FANCY_MATH_387
16026 && flag_unsafe_math_optimizations"
16030 for (i=2; i<10; i++)
16031 operands[i] = gen_reg_rtx (XFmode);
16032 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16035 (define_expand "exp2df2"
16036 [(set (match_dup 2)
16037 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16038 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16039 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16040 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16041 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16042 (parallel [(set (match_dup 8)
16043 (unspec:XF [(match_dup 7) (match_dup 3)]
16044 UNSPEC_FSCALE_FRACT))
16046 (unspec:XF [(match_dup 7) (match_dup 3)]
16047 UNSPEC_FSCALE_EXP))])
16048 (set (match_operand:DF 0 "register_operand" "")
16049 (float_truncate:DF (match_dup 8)))]
16050 "TARGET_USE_FANCY_MATH_387
16051 && flag_unsafe_math_optimizations"
16055 for (i=2; i<10; i++)
16056 operands[i] = gen_reg_rtx (XFmode);
16057 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16060 (define_expand "exp2xf2"
16061 [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
16062 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16063 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16064 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16065 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16066 (parallel [(set (match_operand:XF 0 "register_operand" "")
16067 (unspec:XF [(match_dup 7) (match_dup 3)]
16068 UNSPEC_FSCALE_FRACT))
16070 (unspec:XF [(match_dup 7) (match_dup 3)]
16071 UNSPEC_FSCALE_EXP))])]
16072 "TARGET_USE_FANCY_MATH_387
16073 && flag_unsafe_math_optimizations"
16077 for (i=2; i<9; i++)
16078 operands[i] = gen_reg_rtx (XFmode);
16079 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16082 (define_expand "expm1df2"
16083 [(set (match_dup 2)
16084 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16085 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16086 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16087 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16088 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16089 (parallel [(set (match_dup 8)
16090 (unspec:XF [(match_dup 7) (match_dup 5)]
16091 UNSPEC_FSCALE_FRACT))
16093 (unspec:XF [(match_dup 7) (match_dup 5)]
16094 UNSPEC_FSCALE_EXP))])
16095 (parallel [(set (match_dup 11)
16096 (unspec:XF [(match_dup 10) (match_dup 9)]
16097 UNSPEC_FSCALE_FRACT))
16098 (set (match_dup 12)
16099 (unspec:XF [(match_dup 10) (match_dup 9)]
16100 UNSPEC_FSCALE_EXP))])
16101 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16102 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16103 (set (match_operand:DF 0 "register_operand" "")
16104 (float_truncate:DF (match_dup 14)))]
16105 "TARGET_USE_FANCY_MATH_387
16106 && flag_unsafe_math_optimizations"
16111 for (i=2; i<15; i++)
16112 operands[i] = gen_reg_rtx (XFmode);
16113 temp = standard_80387_constant_rtx (5); /* fldl2e */
16114 emit_move_insn (operands[3], temp);
16115 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16118 (define_expand "expm1sf2"
16119 [(set (match_dup 2)
16120 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16121 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16122 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16123 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16124 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16125 (parallel [(set (match_dup 8)
16126 (unspec:XF [(match_dup 7) (match_dup 5)]
16127 UNSPEC_FSCALE_FRACT))
16129 (unspec:XF [(match_dup 7) (match_dup 5)]
16130 UNSPEC_FSCALE_EXP))])
16131 (parallel [(set (match_dup 11)
16132 (unspec:XF [(match_dup 10) (match_dup 9)]
16133 UNSPEC_FSCALE_FRACT))
16134 (set (match_dup 12)
16135 (unspec:XF [(match_dup 10) (match_dup 9)]
16136 UNSPEC_FSCALE_EXP))])
16137 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16138 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16139 (set (match_operand:SF 0 "register_operand" "")
16140 (float_truncate:SF (match_dup 14)))]
16141 "TARGET_USE_FANCY_MATH_387
16142 && flag_unsafe_math_optimizations"
16147 for (i=2; i<15; i++)
16148 operands[i] = gen_reg_rtx (XFmode);
16149 temp = standard_80387_constant_rtx (5); /* fldl2e */
16150 emit_move_insn (operands[3], temp);
16151 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16154 (define_expand "expm1xf2"
16155 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16157 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16158 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16159 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16160 (parallel [(set (match_dup 7)
16161 (unspec:XF [(match_dup 6) (match_dup 4)]
16162 UNSPEC_FSCALE_FRACT))
16164 (unspec:XF [(match_dup 6) (match_dup 4)]
16165 UNSPEC_FSCALE_EXP))])
16166 (parallel [(set (match_dup 10)
16167 (unspec:XF [(match_dup 9) (match_dup 8)]
16168 UNSPEC_FSCALE_FRACT))
16169 (set (match_dup 11)
16170 (unspec:XF [(match_dup 9) (match_dup 8)]
16171 UNSPEC_FSCALE_EXP))])
16172 (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
16173 (set (match_operand:XF 0 "register_operand" "")
16174 (plus:XF (match_dup 12) (match_dup 7)))]
16175 "TARGET_USE_FANCY_MATH_387
16176 && flag_unsafe_math_optimizations"
16181 for (i=2; i<13; i++)
16182 operands[i] = gen_reg_rtx (XFmode);
16183 temp = standard_80387_constant_rtx (5); /* fldl2e */
16184 emit_move_insn (operands[2], temp);
16185 emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
16189 (define_insn "frndintxf2"
16190 [(set (match_operand:XF 0 "register_operand" "=f")
16191 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16193 "TARGET_USE_FANCY_MATH_387
16194 && flag_unsafe_math_optimizations"
16196 [(set_attr "type" "fpspc")
16197 (set_attr "mode" "XF")])
16199 (define_expand "rintdf2"
16200 [(use (match_operand:DF 0 "register_operand" ""))
16201 (use (match_operand:DF 1 "register_operand" ""))]
16202 "TARGET_USE_FANCY_MATH_387
16203 && flag_unsafe_math_optimizations"
16205 rtx op0 = gen_reg_rtx (XFmode);
16206 rtx op1 = gen_reg_rtx (XFmode);
16208 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16209 emit_insn (gen_frndintxf2 (op0, op1));
16211 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16215 (define_expand "rintsf2"
16216 [(use (match_operand:SF 0 "register_operand" ""))
16217 (use (match_operand:SF 1 "register_operand" ""))]
16218 "TARGET_USE_FANCY_MATH_387
16219 && flag_unsafe_math_optimizations"
16221 rtx op0 = gen_reg_rtx (XFmode);
16222 rtx op1 = gen_reg_rtx (XFmode);
16224 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16225 emit_insn (gen_frndintxf2 (op0, op1));
16227 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16231 (define_expand "rintxf2"
16232 [(use (match_operand:XF 0 "register_operand" ""))
16233 (use (match_operand:XF 1 "register_operand" ""))]
16234 "TARGET_USE_FANCY_MATH_387
16235 && flag_unsafe_math_optimizations"
16237 emit_insn (gen_frndintxf2 (operands[0], operands[1]));
16241 (define_insn "frndintxf2_floor"
16242 [(set (match_operand:XF 0 "register_operand" "=f")
16243 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16244 UNSPEC_FRNDINT_FLOOR))
16245 (use (match_operand:HI 2 "memory_operand" "m"))
16246 (use (match_operand:HI 3 "memory_operand" "m"))]
16247 "TARGET_USE_FANCY_MATH_387
16248 && flag_unsafe_math_optimizations"
16249 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16250 [(set_attr "type" "frndint")
16251 (set_attr "i387_cw" "floor")
16252 (set_attr "mode" "XF")])
16254 (define_expand "floordf2"
16255 [(use (match_operand:DF 0 "register_operand" ""))
16256 (use (match_operand:DF 1 "register_operand" ""))]
16257 "TARGET_USE_FANCY_MATH_387
16258 && flag_unsafe_math_optimizations"
16260 rtx op0 = gen_reg_rtx (XFmode);
16261 rtx op1 = gen_reg_rtx (XFmode);
16262 rtx op2 = assign_386_stack_local (HImode, 1);
16263 rtx op3 = assign_386_stack_local (HImode, 2);
16265 ix86_optimize_mode_switching = 1;
16267 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16268 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16270 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16274 (define_expand "floorsf2"
16275 [(use (match_operand:SF 0 "register_operand" ""))
16276 (use (match_operand:SF 1 "register_operand" ""))]
16277 "TARGET_USE_FANCY_MATH_387
16278 && flag_unsafe_math_optimizations"
16280 rtx op0 = gen_reg_rtx (XFmode);
16281 rtx op1 = gen_reg_rtx (XFmode);
16282 rtx op2 = assign_386_stack_local (HImode, 1);
16283 rtx op3 = assign_386_stack_local (HImode, 2);
16285 ix86_optimize_mode_switching = 1;
16287 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16288 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16290 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16294 (define_expand "floorxf2"
16295 [(use (match_operand:XF 0 "register_operand" ""))
16296 (use (match_operand:XF 1 "register_operand" ""))]
16297 "TARGET_USE_FANCY_MATH_387
16298 && flag_unsafe_math_optimizations"
16300 rtx op2 = assign_386_stack_local (HImode, 1);
16301 rtx op3 = assign_386_stack_local (HImode, 2);
16303 ix86_optimize_mode_switching = 1;
16305 emit_insn (gen_frndintxf2_floor (operands[0], operands[1], op2, op3));
16309 (define_insn "frndintxf2_ceil"
16310 [(set (match_operand:XF 0 "register_operand" "=f")
16311 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16312 UNSPEC_FRNDINT_CEIL))
16313 (use (match_operand:HI 2 "memory_operand" "m"))
16314 (use (match_operand:HI 3 "memory_operand" "m"))]
16315 "TARGET_USE_FANCY_MATH_387
16316 && flag_unsafe_math_optimizations"
16317 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16318 [(set_attr "type" "frndint")
16319 (set_attr "i387_cw" "ceil")
16320 (set_attr "mode" "XF")])
16322 (define_expand "ceildf2"
16323 [(use (match_operand:DF 0 "register_operand" ""))
16324 (use (match_operand:DF 1 "register_operand" ""))]
16325 "TARGET_USE_FANCY_MATH_387
16326 && flag_unsafe_math_optimizations"
16328 rtx op0 = gen_reg_rtx (XFmode);
16329 rtx op1 = gen_reg_rtx (XFmode);
16330 rtx op2 = assign_386_stack_local (HImode, 1);
16331 rtx op3 = assign_386_stack_local (HImode, 2);
16333 ix86_optimize_mode_switching = 1;
16335 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16336 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16338 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16342 (define_expand "ceilsf2"
16343 [(use (match_operand:SF 0 "register_operand" ""))
16344 (use (match_operand:SF 1 "register_operand" ""))]
16345 "TARGET_USE_FANCY_MATH_387
16346 && flag_unsafe_math_optimizations"
16348 rtx op0 = gen_reg_rtx (XFmode);
16349 rtx op1 = gen_reg_rtx (XFmode);
16350 rtx op2 = assign_386_stack_local (HImode, 1);
16351 rtx op3 = assign_386_stack_local (HImode, 2);
16353 ix86_optimize_mode_switching = 1;
16355 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16356 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16358 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16362 (define_expand "ceilxf2"
16363 [(use (match_operand:XF 0 "register_operand" ""))
16364 (use (match_operand:XF 1 "register_operand" ""))]
16365 "TARGET_USE_FANCY_MATH_387
16366 && flag_unsafe_math_optimizations"
16368 rtx op2 = assign_386_stack_local (HImode, 1);
16369 rtx op3 = assign_386_stack_local (HImode, 2);
16371 ix86_optimize_mode_switching = 1;
16373 emit_insn (gen_frndintxf2_ceil (operands[0], operands[1], op2, op3));
16377 (define_insn "frndintxf2_trunc"
16378 [(set (match_operand:XF 0 "register_operand" "=f")
16379 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16380 UNSPEC_FRNDINT_TRUNC))
16381 (use (match_operand:HI 2 "memory_operand" "m"))
16382 (use (match_operand:HI 3 "memory_operand" "m"))]
16383 "TARGET_USE_FANCY_MATH_387
16384 && flag_unsafe_math_optimizations"
16385 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16386 [(set_attr "type" "frndint")
16387 (set_attr "i387_cw" "trunc")
16388 (set_attr "mode" "XF")])
16390 (define_expand "btruncdf2"
16391 [(use (match_operand:DF 0 "register_operand" ""))
16392 (use (match_operand:DF 1 "register_operand" ""))]
16393 "TARGET_USE_FANCY_MATH_387
16394 && flag_unsafe_math_optimizations"
16396 rtx op0 = gen_reg_rtx (XFmode);
16397 rtx op1 = gen_reg_rtx (XFmode);
16398 rtx op2 = assign_386_stack_local (HImode, 1);
16399 rtx op3 = assign_386_stack_local (HImode, 2);
16401 ix86_optimize_mode_switching = 1;
16403 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16404 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16406 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16410 (define_expand "btruncsf2"
16411 [(use (match_operand:SF 0 "register_operand" ""))
16412 (use (match_operand:SF 1 "register_operand" ""))]
16413 "TARGET_USE_FANCY_MATH_387
16414 && flag_unsafe_math_optimizations"
16416 rtx op0 = gen_reg_rtx (XFmode);
16417 rtx op1 = gen_reg_rtx (XFmode);
16418 rtx op2 = assign_386_stack_local (HImode, 1);
16419 rtx op3 = assign_386_stack_local (HImode, 2);
16421 ix86_optimize_mode_switching = 1;
16423 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16424 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16426 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16430 (define_expand "btruncxf2"
16431 [(use (match_operand:XF 0 "register_operand" ""))
16432 (use (match_operand:XF 1 "register_operand" ""))]
16433 "TARGET_USE_FANCY_MATH_387
16434 && flag_unsafe_math_optimizations"
16436 rtx op2 = assign_386_stack_local (HImode, 1);
16437 rtx op3 = assign_386_stack_local (HImode, 2);
16439 ix86_optimize_mode_switching = 1;
16441 emit_insn (gen_frndintxf2_trunc (operands[0], operands[1], op2, op3));
16445 (define_insn "frndintxf2_mask_pm"
16446 [(set (match_operand:XF 0 "register_operand" "=f")
16447 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16448 UNSPEC_FRNDINT_MASK_PM))
16449 (use (match_operand:HI 2 "memory_operand" "m"))
16450 (use (match_operand:HI 3 "memory_operand" "m"))]
16451 "TARGET_USE_FANCY_MATH_387
16452 && flag_unsafe_math_optimizations"
16453 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
16454 [(set_attr "type" "frndint")
16455 (set_attr "i387_cw" "mask_pm")
16456 (set_attr "mode" "XF")])
16458 (define_expand "nearbyintdf2"
16459 [(use (match_operand:DF 0 "register_operand" ""))
16460 (use (match_operand:DF 1 "register_operand" ""))]
16461 "TARGET_USE_FANCY_MATH_387
16462 && flag_unsafe_math_optimizations"
16464 rtx op0 = gen_reg_rtx (XFmode);
16465 rtx op1 = gen_reg_rtx (XFmode);
16466 rtx op2 = assign_386_stack_local (HImode, 1);
16467 rtx op3 = assign_386_stack_local (HImode, 2);
16469 ix86_optimize_mode_switching = 1;
16471 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16472 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16474 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16478 (define_expand "nearbyintsf2"
16479 [(use (match_operand:SF 0 "register_operand" ""))
16480 (use (match_operand:SF 1 "register_operand" ""))]
16481 "TARGET_USE_FANCY_MATH_387
16482 && flag_unsafe_math_optimizations"
16484 rtx op0 = gen_reg_rtx (XFmode);
16485 rtx op1 = gen_reg_rtx (XFmode);
16486 rtx op2 = assign_386_stack_local (HImode, 1);
16487 rtx op3 = assign_386_stack_local (HImode, 2);
16489 ix86_optimize_mode_switching = 1;
16491 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16492 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16494 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16498 (define_expand "nearbyintxf2"
16499 [(use (match_operand:XF 0 "register_operand" ""))
16500 (use (match_operand:XF 1 "register_operand" ""))]
16501 "TARGET_USE_FANCY_MATH_387
16502 && flag_unsafe_math_optimizations"
16504 rtx op2 = assign_386_stack_local (HImode, 1);
16505 rtx op3 = assign_386_stack_local (HImode, 2);
16507 ix86_optimize_mode_switching = 1;
16509 emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1],
16515 ;; Block operation instructions
16518 [(set (reg:SI DIRFLAG_REG) (const_int 0))]
16521 [(set_attr "type" "cld")])
16523 (define_expand "movmemsi"
16524 [(use (match_operand:BLK 0 "memory_operand" ""))
16525 (use (match_operand:BLK 1 "memory_operand" ""))
16526 (use (match_operand:SI 2 "nonmemory_operand" ""))
16527 (use (match_operand:SI 3 "const_int_operand" ""))]
16530 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16536 (define_expand "movmemdi"
16537 [(use (match_operand:BLK 0 "memory_operand" ""))
16538 (use (match_operand:BLK 1 "memory_operand" ""))
16539 (use (match_operand:DI 2 "nonmemory_operand" ""))
16540 (use (match_operand:DI 3 "const_int_operand" ""))]
16543 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16549 ;; Most CPUs don't like single string operations
16550 ;; Handle this case here to simplify previous expander.
16552 (define_expand "strmov"
16553 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
16554 (set (match_operand 1 "memory_operand" "") (match_dup 4))
16555 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
16556 (clobber (reg:CC FLAGS_REG))])
16557 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
16558 (clobber (reg:CC FLAGS_REG))])]
16561 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
16563 /* If .md ever supports :P for Pmode, these can be directly
16564 in the pattern above. */
16565 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
16566 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
16568 if (TARGET_SINGLE_STRINGOP || optimize_size)
16570 emit_insn (gen_strmov_singleop (operands[0], operands[1],
16571 operands[2], operands[3],
16572 operands[5], operands[6]));
16576 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
16579 (define_expand "strmov_singleop"
16580 [(parallel [(set (match_operand 1 "memory_operand" "")
16581 (match_operand 3 "memory_operand" ""))
16582 (set (match_operand 0 "register_operand" "")
16583 (match_operand 4 "" ""))
16584 (set (match_operand 2 "register_operand" "")
16585 (match_operand 5 "" ""))
16586 (use (reg:SI DIRFLAG_REG))])]
16587 "TARGET_SINGLE_STRINGOP || optimize_size"
16590 (define_insn "*strmovdi_rex_1"
16591 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
16592 (mem:DI (match_operand:DI 3 "register_operand" "1")))
16593 (set (match_operand:DI 0 "register_operand" "=D")
16594 (plus:DI (match_dup 2)
16596 (set (match_operand:DI 1 "register_operand" "=S")
16597 (plus:DI (match_dup 3)
16599 (use (reg:SI DIRFLAG_REG))]
16600 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16602 [(set_attr "type" "str")
16603 (set_attr "mode" "DI")
16604 (set_attr "memory" "both")])
16606 (define_insn "*strmovsi_1"
16607 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
16608 (mem:SI (match_operand:SI 3 "register_operand" "1")))
16609 (set (match_operand:SI 0 "register_operand" "=D")
16610 (plus:SI (match_dup 2)
16612 (set (match_operand:SI 1 "register_operand" "=S")
16613 (plus:SI (match_dup 3)
16615 (use (reg:SI DIRFLAG_REG))]
16616 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16618 [(set_attr "type" "str")
16619 (set_attr "mode" "SI")
16620 (set_attr "memory" "both")])
16622 (define_insn "*strmovsi_rex_1"
16623 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
16624 (mem:SI (match_operand:DI 3 "register_operand" "1")))
16625 (set (match_operand:DI 0 "register_operand" "=D")
16626 (plus:DI (match_dup 2)
16628 (set (match_operand:DI 1 "register_operand" "=S")
16629 (plus:DI (match_dup 3)
16631 (use (reg:SI DIRFLAG_REG))]
16632 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16634 [(set_attr "type" "str")
16635 (set_attr "mode" "SI")
16636 (set_attr "memory" "both")])
16638 (define_insn "*strmovhi_1"
16639 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
16640 (mem:HI (match_operand:SI 3 "register_operand" "1")))
16641 (set (match_operand:SI 0 "register_operand" "=D")
16642 (plus:SI (match_dup 2)
16644 (set (match_operand:SI 1 "register_operand" "=S")
16645 (plus:SI (match_dup 3)
16647 (use (reg:SI DIRFLAG_REG))]
16648 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16650 [(set_attr "type" "str")
16651 (set_attr "memory" "both")
16652 (set_attr "mode" "HI")])
16654 (define_insn "*strmovhi_rex_1"
16655 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
16656 (mem:HI (match_operand:DI 3 "register_operand" "1")))
16657 (set (match_operand:DI 0 "register_operand" "=D")
16658 (plus:DI (match_dup 2)
16660 (set (match_operand:DI 1 "register_operand" "=S")
16661 (plus:DI (match_dup 3)
16663 (use (reg:SI DIRFLAG_REG))]
16664 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16666 [(set_attr "type" "str")
16667 (set_attr "memory" "both")
16668 (set_attr "mode" "HI")])
16670 (define_insn "*strmovqi_1"
16671 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
16672 (mem:QI (match_operand:SI 3 "register_operand" "1")))
16673 (set (match_operand:SI 0 "register_operand" "=D")
16674 (plus:SI (match_dup 2)
16676 (set (match_operand:SI 1 "register_operand" "=S")
16677 (plus:SI (match_dup 3)
16679 (use (reg:SI DIRFLAG_REG))]
16680 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16682 [(set_attr "type" "str")
16683 (set_attr "memory" "both")
16684 (set_attr "mode" "QI")])
16686 (define_insn "*strmovqi_rex_1"
16687 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
16688 (mem:QI (match_operand:DI 3 "register_operand" "1")))
16689 (set (match_operand:DI 0 "register_operand" "=D")
16690 (plus:DI (match_dup 2)
16692 (set (match_operand:DI 1 "register_operand" "=S")
16693 (plus:DI (match_dup 3)
16695 (use (reg:SI DIRFLAG_REG))]
16696 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16698 [(set_attr "type" "str")
16699 (set_attr "memory" "both")
16700 (set_attr "mode" "QI")])
16702 (define_expand "rep_mov"
16703 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
16704 (set (match_operand 0 "register_operand" "")
16705 (match_operand 5 "" ""))
16706 (set (match_operand 2 "register_operand" "")
16707 (match_operand 6 "" ""))
16708 (set (match_operand 1 "memory_operand" "")
16709 (match_operand 3 "memory_operand" ""))
16710 (use (match_dup 4))
16711 (use (reg:SI DIRFLAG_REG))])]
16715 (define_insn "*rep_movdi_rex64"
16716 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16717 (set (match_operand:DI 0 "register_operand" "=D")
16718 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16720 (match_operand:DI 3 "register_operand" "0")))
16721 (set (match_operand:DI 1 "register_operand" "=S")
16722 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
16723 (match_operand:DI 4 "register_operand" "1")))
16724 (set (mem:BLK (match_dup 3))
16725 (mem:BLK (match_dup 4)))
16726 (use (match_dup 5))
16727 (use (reg:SI DIRFLAG_REG))]
16729 "{rep\;movsq|rep movsq}"
16730 [(set_attr "type" "str")
16731 (set_attr "prefix_rep" "1")
16732 (set_attr "memory" "both")
16733 (set_attr "mode" "DI")])
16735 (define_insn "*rep_movsi"
16736 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16737 (set (match_operand:SI 0 "register_operand" "=D")
16738 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
16740 (match_operand:SI 3 "register_operand" "0")))
16741 (set (match_operand:SI 1 "register_operand" "=S")
16742 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
16743 (match_operand:SI 4 "register_operand" "1")))
16744 (set (mem:BLK (match_dup 3))
16745 (mem:BLK (match_dup 4)))
16746 (use (match_dup 5))
16747 (use (reg:SI DIRFLAG_REG))]
16749 "{rep\;movsl|rep movsd}"
16750 [(set_attr "type" "str")
16751 (set_attr "prefix_rep" "1")
16752 (set_attr "memory" "both")
16753 (set_attr "mode" "SI")])
16755 (define_insn "*rep_movsi_rex64"
16756 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16757 (set (match_operand:DI 0 "register_operand" "=D")
16758 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16760 (match_operand:DI 3 "register_operand" "0")))
16761 (set (match_operand:DI 1 "register_operand" "=S")
16762 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
16763 (match_operand:DI 4 "register_operand" "1")))
16764 (set (mem:BLK (match_dup 3))
16765 (mem:BLK (match_dup 4)))
16766 (use (match_dup 5))
16767 (use (reg:SI DIRFLAG_REG))]
16769 "{rep\;movsl|rep movsd}"
16770 [(set_attr "type" "str")
16771 (set_attr "prefix_rep" "1")
16772 (set_attr "memory" "both")
16773 (set_attr "mode" "SI")])
16775 (define_insn "*rep_movqi"
16776 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16777 (set (match_operand:SI 0 "register_operand" "=D")
16778 (plus:SI (match_operand:SI 3 "register_operand" "0")
16779 (match_operand:SI 5 "register_operand" "2")))
16780 (set (match_operand:SI 1 "register_operand" "=S")
16781 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
16782 (set (mem:BLK (match_dup 3))
16783 (mem:BLK (match_dup 4)))
16784 (use (match_dup 5))
16785 (use (reg:SI DIRFLAG_REG))]
16787 "{rep\;movsb|rep movsb}"
16788 [(set_attr "type" "str")
16789 (set_attr "prefix_rep" "1")
16790 (set_attr "memory" "both")
16791 (set_attr "mode" "SI")])
16793 (define_insn "*rep_movqi_rex64"
16794 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16795 (set (match_operand:DI 0 "register_operand" "=D")
16796 (plus:DI (match_operand:DI 3 "register_operand" "0")
16797 (match_operand:DI 5 "register_operand" "2")))
16798 (set (match_operand:DI 1 "register_operand" "=S")
16799 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
16800 (set (mem:BLK (match_dup 3))
16801 (mem:BLK (match_dup 4)))
16802 (use (match_dup 5))
16803 (use (reg:SI DIRFLAG_REG))]
16805 "{rep\;movsb|rep movsb}"
16806 [(set_attr "type" "str")
16807 (set_attr "prefix_rep" "1")
16808 (set_attr "memory" "both")
16809 (set_attr "mode" "SI")])
16811 (define_expand "clrmemsi"
16812 [(use (match_operand:BLK 0 "memory_operand" ""))
16813 (use (match_operand:SI 1 "nonmemory_operand" ""))
16814 (use (match_operand 2 "const_int_operand" ""))]
16817 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
16823 (define_expand "clrmemdi"
16824 [(use (match_operand:BLK 0 "memory_operand" ""))
16825 (use (match_operand:DI 1 "nonmemory_operand" ""))
16826 (use (match_operand 2 "const_int_operand" ""))]
16829 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
16835 ;; Most CPUs don't like single string operations
16836 ;; Handle this case here to simplify previous expander.
16838 (define_expand "strset"
16839 [(set (match_operand 1 "memory_operand" "")
16840 (match_operand 2 "register_operand" ""))
16841 (parallel [(set (match_operand 0 "register_operand" "")
16843 (clobber (reg:CC FLAGS_REG))])]
16846 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
16847 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
16849 /* If .md ever supports :P for Pmode, this can be directly
16850 in the pattern above. */
16851 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
16852 GEN_INT (GET_MODE_SIZE (GET_MODE
16854 if (TARGET_SINGLE_STRINGOP || optimize_size)
16856 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
16862 (define_expand "strset_singleop"
16863 [(parallel [(set (match_operand 1 "memory_operand" "")
16864 (match_operand 2 "register_operand" ""))
16865 (set (match_operand 0 "register_operand" "")
16866 (match_operand 3 "" ""))
16867 (use (reg:SI DIRFLAG_REG))])]
16868 "TARGET_SINGLE_STRINGOP || optimize_size"
16871 (define_insn "*strsetdi_rex_1"
16872 [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
16873 (match_operand:DI 2 "register_operand" "a"))
16874 (set (match_operand:DI 0 "register_operand" "=D")
16875 (plus:DI (match_dup 1)
16877 (use (reg:SI DIRFLAG_REG))]
16878 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16880 [(set_attr "type" "str")
16881 (set_attr "memory" "store")
16882 (set_attr "mode" "DI")])
16884 (define_insn "*strsetsi_1"
16885 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
16886 (match_operand:SI 2 "register_operand" "a"))
16887 (set (match_operand:SI 0 "register_operand" "=D")
16888 (plus:SI (match_dup 1)
16890 (use (reg:SI DIRFLAG_REG))]
16891 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16893 [(set_attr "type" "str")
16894 (set_attr "memory" "store")
16895 (set_attr "mode" "SI")])
16897 (define_insn "*strsetsi_rex_1"
16898 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16899 (match_operand:SI 2 "register_operand" "a"))
16900 (set (match_operand:DI 0 "register_operand" "=D")
16901 (plus:DI (match_dup 1)
16903 (use (reg:SI DIRFLAG_REG))]
16904 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16906 [(set_attr "type" "str")
16907 (set_attr "memory" "store")
16908 (set_attr "mode" "SI")])
16910 (define_insn "*strsethi_1"
16911 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
16912 (match_operand:HI 2 "register_operand" "a"))
16913 (set (match_operand:SI 0 "register_operand" "=D")
16914 (plus:SI (match_dup 1)
16916 (use (reg:SI DIRFLAG_REG))]
16917 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16919 [(set_attr "type" "str")
16920 (set_attr "memory" "store")
16921 (set_attr "mode" "HI")])
16923 (define_insn "*strsethi_rex_1"
16924 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
16925 (match_operand:HI 2 "register_operand" "a"))
16926 (set (match_operand:DI 0 "register_operand" "=D")
16927 (plus:DI (match_dup 1)
16929 (use (reg:SI DIRFLAG_REG))]
16930 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16932 [(set_attr "type" "str")
16933 (set_attr "memory" "store")
16934 (set_attr "mode" "HI")])
16936 (define_insn "*strsetqi_1"
16937 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
16938 (match_operand:QI 2 "register_operand" "a"))
16939 (set (match_operand:SI 0 "register_operand" "=D")
16940 (plus:SI (match_dup 1)
16942 (use (reg:SI DIRFLAG_REG))]
16943 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16945 [(set_attr "type" "str")
16946 (set_attr "memory" "store")
16947 (set_attr "mode" "QI")])
16949 (define_insn "*strsetqi_rex_1"
16950 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
16951 (match_operand:QI 2 "register_operand" "a"))
16952 (set (match_operand:DI 0 "register_operand" "=D")
16953 (plus:DI (match_dup 1)
16955 (use (reg:SI DIRFLAG_REG))]
16956 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16958 [(set_attr "type" "str")
16959 (set_attr "memory" "store")
16960 (set_attr "mode" "QI")])
16962 (define_expand "rep_stos"
16963 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
16964 (set (match_operand 0 "register_operand" "")
16965 (match_operand 4 "" ""))
16966 (set (match_operand 2 "memory_operand" "") (const_int 0))
16967 (use (match_operand 3 "register_operand" ""))
16968 (use (match_dup 1))
16969 (use (reg:SI DIRFLAG_REG))])]
16973 (define_insn "*rep_stosdi_rex64"
16974 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16975 (set (match_operand:DI 0 "register_operand" "=D")
16976 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16978 (match_operand:DI 3 "register_operand" "0")))
16979 (set (mem:BLK (match_dup 3))
16981 (use (match_operand:DI 2 "register_operand" "a"))
16982 (use (match_dup 4))
16983 (use (reg:SI DIRFLAG_REG))]
16985 "{rep\;stosq|rep stosq}"
16986 [(set_attr "type" "str")
16987 (set_attr "prefix_rep" "1")
16988 (set_attr "memory" "store")
16989 (set_attr "mode" "DI")])
16991 (define_insn "*rep_stossi"
16992 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16993 (set (match_operand:SI 0 "register_operand" "=D")
16994 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
16996 (match_operand:SI 3 "register_operand" "0")))
16997 (set (mem:BLK (match_dup 3))
16999 (use (match_operand:SI 2 "register_operand" "a"))
17000 (use (match_dup 4))
17001 (use (reg:SI DIRFLAG_REG))]
17003 "{rep\;stosl|rep stosd}"
17004 [(set_attr "type" "str")
17005 (set_attr "prefix_rep" "1")
17006 (set_attr "memory" "store")
17007 (set_attr "mode" "SI")])
17009 (define_insn "*rep_stossi_rex64"
17010 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17011 (set (match_operand:DI 0 "register_operand" "=D")
17012 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
17014 (match_operand:DI 3 "register_operand" "0")))
17015 (set (mem:BLK (match_dup 3))
17017 (use (match_operand:SI 2 "register_operand" "a"))
17018 (use (match_dup 4))
17019 (use (reg:SI DIRFLAG_REG))]
17021 "{rep\;stosl|rep stosd}"
17022 [(set_attr "type" "str")
17023 (set_attr "prefix_rep" "1")
17024 (set_attr "memory" "store")
17025 (set_attr "mode" "SI")])
17027 (define_insn "*rep_stosqi"
17028 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17029 (set (match_operand:SI 0 "register_operand" "=D")
17030 (plus:SI (match_operand:SI 3 "register_operand" "0")
17031 (match_operand:SI 4 "register_operand" "1")))
17032 (set (mem:BLK (match_dup 3))
17034 (use (match_operand:QI 2 "register_operand" "a"))
17035 (use (match_dup 4))
17036 (use (reg:SI DIRFLAG_REG))]
17038 "{rep\;stosb|rep stosb}"
17039 [(set_attr "type" "str")
17040 (set_attr "prefix_rep" "1")
17041 (set_attr "memory" "store")
17042 (set_attr "mode" "QI")])
17044 (define_insn "*rep_stosqi_rex64"
17045 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17046 (set (match_operand:DI 0 "register_operand" "=D")
17047 (plus:DI (match_operand:DI 3 "register_operand" "0")
17048 (match_operand:DI 4 "register_operand" "1")))
17049 (set (mem:BLK (match_dup 3))
17051 (use (match_operand:QI 2 "register_operand" "a"))
17052 (use (match_dup 4))
17053 (use (reg:SI DIRFLAG_REG))]
17055 "{rep\;stosb|rep stosb}"
17056 [(set_attr "type" "str")
17057 (set_attr "prefix_rep" "1")
17058 (set_attr "memory" "store")
17059 (set_attr "mode" "QI")])
17061 (define_expand "cmpstrsi"
17062 [(set (match_operand:SI 0 "register_operand" "")
17063 (compare:SI (match_operand:BLK 1 "general_operand" "")
17064 (match_operand:BLK 2 "general_operand" "")))
17065 (use (match_operand 3 "general_operand" ""))
17066 (use (match_operand 4 "immediate_operand" ""))]
17067 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
17069 rtx addr1, addr2, out, outlow, count, countreg, align;
17071 /* Can't use this if the user has appropriated esi or edi. */
17072 if (global_regs[4] || global_regs[5])
17076 if (GET_CODE (out) != REG)
17077 out = gen_reg_rtx (SImode);
17079 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
17080 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
17081 if (addr1 != XEXP (operands[1], 0))
17082 operands[1] = replace_equiv_address_nv (operands[1], addr1);
17083 if (addr2 != XEXP (operands[2], 0))
17084 operands[2] = replace_equiv_address_nv (operands[2], addr2);
17086 count = operands[3];
17087 countreg = ix86_zero_extend_to_Pmode (count);
17089 /* %%% Iff we are testing strict equality, we can use known alignment
17090 to good advantage. This may be possible with combine, particularly
17091 once cc0 is dead. */
17092 align = operands[4];
17094 emit_insn (gen_cld ());
17095 if (GET_CODE (count) == CONST_INT)
17097 if (INTVAL (count) == 0)
17099 emit_move_insn (operands[0], const0_rtx);
17102 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
17103 operands[1], operands[2]));
17108 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
17110 emit_insn (gen_cmpsi_1 (countreg, countreg));
17111 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
17112 operands[1], operands[2]));
17115 outlow = gen_lowpart (QImode, out);
17116 emit_insn (gen_cmpintqi (outlow));
17117 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
17119 if (operands[0] != out)
17120 emit_move_insn (operands[0], out);
17125 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
17127 (define_expand "cmpintqi"
17128 [(set (match_dup 1)
17129 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17131 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17132 (parallel [(set (match_operand:QI 0 "register_operand" "")
17133 (minus:QI (match_dup 1)
17135 (clobber (reg:CC FLAGS_REG))])]
17137 "operands[1] = gen_reg_rtx (QImode);
17138 operands[2] = gen_reg_rtx (QImode);")
17140 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
17141 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
17143 (define_expand "cmpstrqi_nz_1"
17144 [(parallel [(set (reg:CC FLAGS_REG)
17145 (compare:CC (match_operand 4 "memory_operand" "")
17146 (match_operand 5 "memory_operand" "")))
17147 (use (match_operand 2 "register_operand" ""))
17148 (use (match_operand:SI 3 "immediate_operand" ""))
17149 (use (reg:SI DIRFLAG_REG))
17150 (clobber (match_operand 0 "register_operand" ""))
17151 (clobber (match_operand 1 "register_operand" ""))
17152 (clobber (match_dup 2))])]
17156 (define_insn "*cmpstrqi_nz_1"
17157 [(set (reg:CC FLAGS_REG)
17158 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17159 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
17160 (use (match_operand:SI 6 "register_operand" "2"))
17161 (use (match_operand:SI 3 "immediate_operand" "i"))
17162 (use (reg:SI DIRFLAG_REG))
17163 (clobber (match_operand:SI 0 "register_operand" "=S"))
17164 (clobber (match_operand:SI 1 "register_operand" "=D"))
17165 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17168 [(set_attr "type" "str")
17169 (set_attr "mode" "QI")
17170 (set_attr "prefix_rep" "1")])
17172 (define_insn "*cmpstrqi_nz_rex_1"
17173 [(set (reg:CC FLAGS_REG)
17174 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17175 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
17176 (use (match_operand:DI 6 "register_operand" "2"))
17177 (use (match_operand:SI 3 "immediate_operand" "i"))
17178 (use (reg:SI DIRFLAG_REG))
17179 (clobber (match_operand:DI 0 "register_operand" "=S"))
17180 (clobber (match_operand:DI 1 "register_operand" "=D"))
17181 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17184 [(set_attr "type" "str")
17185 (set_attr "mode" "QI")
17186 (set_attr "prefix_rep" "1")])
17188 ;; The same, but the count is not known to not be zero.
17190 (define_expand "cmpstrqi_1"
17191 [(parallel [(set (reg:CC FLAGS_REG)
17192 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
17194 (compare:CC (match_operand 4 "memory_operand" "")
17195 (match_operand 5 "memory_operand" ""))
17197 (use (match_operand:SI 3 "immediate_operand" ""))
17198 (use (reg:CC FLAGS_REG))
17199 (use (reg:SI DIRFLAG_REG))
17200 (clobber (match_operand 0 "register_operand" ""))
17201 (clobber (match_operand 1 "register_operand" ""))
17202 (clobber (match_dup 2))])]
17206 (define_insn "*cmpstrqi_1"
17207 [(set (reg:CC FLAGS_REG)
17208 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
17210 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17211 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
17213 (use (match_operand:SI 3 "immediate_operand" "i"))
17214 (use (reg:CC FLAGS_REG))
17215 (use (reg:SI DIRFLAG_REG))
17216 (clobber (match_operand:SI 0 "register_operand" "=S"))
17217 (clobber (match_operand:SI 1 "register_operand" "=D"))
17218 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17221 [(set_attr "type" "str")
17222 (set_attr "mode" "QI")
17223 (set_attr "prefix_rep" "1")])
17225 (define_insn "*cmpstrqi_rex_1"
17226 [(set (reg:CC FLAGS_REG)
17227 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
17229 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17230 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
17232 (use (match_operand:SI 3 "immediate_operand" "i"))
17233 (use (reg:CC FLAGS_REG))
17234 (use (reg:SI DIRFLAG_REG))
17235 (clobber (match_operand:DI 0 "register_operand" "=S"))
17236 (clobber (match_operand:DI 1 "register_operand" "=D"))
17237 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17240 [(set_attr "type" "str")
17241 (set_attr "mode" "QI")
17242 (set_attr "prefix_rep" "1")])
17244 (define_expand "strlensi"
17245 [(set (match_operand:SI 0 "register_operand" "")
17246 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
17247 (match_operand:QI 2 "immediate_operand" "")
17248 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17251 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17257 (define_expand "strlendi"
17258 [(set (match_operand:DI 0 "register_operand" "")
17259 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
17260 (match_operand:QI 2 "immediate_operand" "")
17261 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17264 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17270 (define_expand "strlenqi_1"
17271 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
17272 (use (reg:SI DIRFLAG_REG))
17273 (clobber (match_operand 1 "register_operand" ""))
17274 (clobber (reg:CC FLAGS_REG))])]
17278 (define_insn "*strlenqi_1"
17279 [(set (match_operand:SI 0 "register_operand" "=&c")
17280 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
17281 (match_operand:QI 2 "register_operand" "a")
17282 (match_operand:SI 3 "immediate_operand" "i")
17283 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
17284 (use (reg:SI DIRFLAG_REG))
17285 (clobber (match_operand:SI 1 "register_operand" "=D"))
17286 (clobber (reg:CC FLAGS_REG))]
17289 [(set_attr "type" "str")
17290 (set_attr "mode" "QI")
17291 (set_attr "prefix_rep" "1")])
17293 (define_insn "*strlenqi_rex_1"
17294 [(set (match_operand:DI 0 "register_operand" "=&c")
17295 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
17296 (match_operand:QI 2 "register_operand" "a")
17297 (match_operand:DI 3 "immediate_operand" "i")
17298 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
17299 (use (reg:SI DIRFLAG_REG))
17300 (clobber (match_operand:DI 1 "register_operand" "=D"))
17301 (clobber (reg:CC FLAGS_REG))]
17304 [(set_attr "type" "str")
17305 (set_attr "mode" "QI")
17306 (set_attr "prefix_rep" "1")])
17308 ;; Peephole optimizations to clean up after cmpstr*. This should be
17309 ;; handled in combine, but it is not currently up to the task.
17310 ;; When used for their truth value, the cmpstr* expanders generate
17319 ;; The intermediate three instructions are unnecessary.
17321 ;; This one handles cmpstr*_nz_1...
17324 (set (reg:CC FLAGS_REG)
17325 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17326 (mem:BLK (match_operand 5 "register_operand" ""))))
17327 (use (match_operand 6 "register_operand" ""))
17328 (use (match_operand:SI 3 "immediate_operand" ""))
17329 (use (reg:SI DIRFLAG_REG))
17330 (clobber (match_operand 0 "register_operand" ""))
17331 (clobber (match_operand 1 "register_operand" ""))
17332 (clobber (match_operand 2 "register_operand" ""))])
17333 (set (match_operand:QI 7 "register_operand" "")
17334 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17335 (set (match_operand:QI 8 "register_operand" "")
17336 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17337 (set (reg FLAGS_REG)
17338 (compare (match_dup 7) (match_dup 8)))
17340 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17342 (set (reg:CC FLAGS_REG)
17343 (compare:CC (mem:BLK (match_dup 4))
17344 (mem:BLK (match_dup 5))))
17345 (use (match_dup 6))
17346 (use (match_dup 3))
17347 (use (reg:SI DIRFLAG_REG))
17348 (clobber (match_dup 0))
17349 (clobber (match_dup 1))
17350 (clobber (match_dup 2))])]
17353 ;; ...and this one handles cmpstr*_1.
17356 (set (reg:CC FLAGS_REG)
17357 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
17359 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17360 (mem:BLK (match_operand 5 "register_operand" "")))
17362 (use (match_operand:SI 3 "immediate_operand" ""))
17363 (use (reg:CC FLAGS_REG))
17364 (use (reg:SI DIRFLAG_REG))
17365 (clobber (match_operand 0 "register_operand" ""))
17366 (clobber (match_operand 1 "register_operand" ""))
17367 (clobber (match_operand 2 "register_operand" ""))])
17368 (set (match_operand:QI 7 "register_operand" "")
17369 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17370 (set (match_operand:QI 8 "register_operand" "")
17371 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17372 (set (reg FLAGS_REG)
17373 (compare (match_dup 7) (match_dup 8)))
17375 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17377 (set (reg:CC FLAGS_REG)
17378 (if_then_else:CC (ne (match_dup 6)
17380 (compare:CC (mem:BLK (match_dup 4))
17381 (mem:BLK (match_dup 5)))
17383 (use (match_dup 3))
17384 (use (reg:CC FLAGS_REG))
17385 (use (reg:SI DIRFLAG_REG))
17386 (clobber (match_dup 0))
17387 (clobber (match_dup 1))
17388 (clobber (match_dup 2))])]
17393 ;; Conditional move instructions.
17395 (define_expand "movdicc"
17396 [(set (match_operand:DI 0 "register_operand" "")
17397 (if_then_else:DI (match_operand 1 "comparison_operator" "")
17398 (match_operand:DI 2 "general_operand" "")
17399 (match_operand:DI 3 "general_operand" "")))]
17401 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17403 (define_insn "x86_movdicc_0_m1_rex64"
17404 [(set (match_operand:DI 0 "register_operand" "=r")
17405 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
17408 (clobber (reg:CC FLAGS_REG))]
17411 ; Since we don't have the proper number of operands for an alu insn,
17412 ; fill in all the blanks.
17413 [(set_attr "type" "alu")
17414 (set_attr "pent_pair" "pu")
17415 (set_attr "memory" "none")
17416 (set_attr "imm_disp" "false")
17417 (set_attr "mode" "DI")
17418 (set_attr "length_immediate" "0")])
17420 (define_insn "movdicc_c_rex64"
17421 [(set (match_operand:DI 0 "register_operand" "=r,r")
17422 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
17423 [(reg FLAGS_REG) (const_int 0)])
17424 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
17425 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
17426 "TARGET_64BIT && TARGET_CMOVE
17427 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17429 cmov%O2%C1\t{%2, %0|%0, %2}
17430 cmov%O2%c1\t{%3, %0|%0, %3}"
17431 [(set_attr "type" "icmov")
17432 (set_attr "mode" "DI")])
17434 (define_expand "movsicc"
17435 [(set (match_operand:SI 0 "register_operand" "")
17436 (if_then_else:SI (match_operand 1 "comparison_operator" "")
17437 (match_operand:SI 2 "general_operand" "")
17438 (match_operand:SI 3 "general_operand" "")))]
17440 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17442 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
17443 ;; the register first winds up with `sbbl $0,reg', which is also weird.
17444 ;; So just document what we're doing explicitly.
17446 (define_insn "x86_movsicc_0_m1"
17447 [(set (match_operand:SI 0 "register_operand" "=r")
17448 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
17451 (clobber (reg:CC FLAGS_REG))]
17454 ; Since we don't have the proper number of operands for an alu insn,
17455 ; fill in all the blanks.
17456 [(set_attr "type" "alu")
17457 (set_attr "pent_pair" "pu")
17458 (set_attr "memory" "none")
17459 (set_attr "imm_disp" "false")
17460 (set_attr "mode" "SI")
17461 (set_attr "length_immediate" "0")])
17463 (define_insn "*movsicc_noc"
17464 [(set (match_operand:SI 0 "register_operand" "=r,r")
17465 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
17466 [(reg FLAGS_REG) (const_int 0)])
17467 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
17468 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
17470 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17472 cmov%O2%C1\t{%2, %0|%0, %2}
17473 cmov%O2%c1\t{%3, %0|%0, %3}"
17474 [(set_attr "type" "icmov")
17475 (set_attr "mode" "SI")])
17477 (define_expand "movhicc"
17478 [(set (match_operand:HI 0 "register_operand" "")
17479 (if_then_else:HI (match_operand 1 "comparison_operator" "")
17480 (match_operand:HI 2 "general_operand" "")
17481 (match_operand:HI 3 "general_operand" "")))]
17482 "TARGET_HIMODE_MATH"
17483 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17485 (define_insn "*movhicc_noc"
17486 [(set (match_operand:HI 0 "register_operand" "=r,r")
17487 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
17488 [(reg FLAGS_REG) (const_int 0)])
17489 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
17490 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
17492 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17494 cmov%O2%C1\t{%2, %0|%0, %2}
17495 cmov%O2%c1\t{%3, %0|%0, %3}"
17496 [(set_attr "type" "icmov")
17497 (set_attr "mode" "HI")])
17499 (define_expand "movqicc"
17500 [(set (match_operand:QI 0 "register_operand" "")
17501 (if_then_else:QI (match_operand 1 "comparison_operator" "")
17502 (match_operand:QI 2 "general_operand" "")
17503 (match_operand:QI 3 "general_operand" "")))]
17504 "TARGET_QIMODE_MATH"
17505 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17507 (define_insn_and_split "*movqicc_noc"
17508 [(set (match_operand:QI 0 "register_operand" "=r,r")
17509 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
17510 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17511 (match_operand:QI 2 "register_operand" "r,0")
17512 (match_operand:QI 3 "register_operand" "0,r")))]
17513 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
17515 "&& reload_completed"
17516 [(set (match_dup 0)
17517 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17520 "operands[0] = gen_lowpart (SImode, operands[0]);
17521 operands[2] = gen_lowpart (SImode, operands[2]);
17522 operands[3] = gen_lowpart (SImode, operands[3]);"
17523 [(set_attr "type" "icmov")
17524 (set_attr "mode" "SI")])
17526 (define_expand "movsfcc"
17527 [(set (match_operand:SF 0 "register_operand" "")
17528 (if_then_else:SF (match_operand 1 "comparison_operator" "")
17529 (match_operand:SF 2 "register_operand" "")
17530 (match_operand:SF 3 "register_operand" "")))]
17532 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17534 (define_insn "*movsfcc_1"
17535 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17536 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17537 [(reg FLAGS_REG) (const_int 0)])
17538 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17539 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17541 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17543 fcmov%F1\t{%2, %0|%0, %2}
17544 fcmov%f1\t{%3, %0|%0, %3}
17545 cmov%O2%C1\t{%2, %0|%0, %2}
17546 cmov%O2%c1\t{%3, %0|%0, %3}"
17547 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17548 (set_attr "mode" "SF,SF,SI,SI")])
17550 (define_expand "movdfcc"
17551 [(set (match_operand:DF 0 "register_operand" "")
17552 (if_then_else:DF (match_operand 1 "comparison_operator" "")
17553 (match_operand:DF 2 "register_operand" "")
17554 (match_operand:DF 3 "register_operand" "")))]
17556 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17558 (define_insn "*movdfcc_1"
17559 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
17560 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17561 [(reg FLAGS_REG) (const_int 0)])
17562 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17563 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17564 "!TARGET_64BIT && TARGET_CMOVE
17565 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17567 fcmov%F1\t{%2, %0|%0, %2}
17568 fcmov%f1\t{%3, %0|%0, %3}
17571 [(set_attr "type" "fcmov,fcmov,multi,multi")
17572 (set_attr "mode" "DF")])
17574 (define_insn "*movdfcc_1_rex64"
17575 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17576 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17577 [(reg FLAGS_REG) (const_int 0)])
17578 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
17579 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
17580 "TARGET_64BIT && TARGET_CMOVE
17581 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17583 fcmov%F1\t{%2, %0|%0, %2}
17584 fcmov%f1\t{%3, %0|%0, %3}
17585 cmov%O2%C1\t{%2, %0|%0, %2}
17586 cmov%O2%c1\t{%3, %0|%0, %3}"
17587 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17588 (set_attr "mode" "DF")])
17591 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
17592 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17593 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17594 (match_operand:DF 2 "nonimmediate_operand" "")
17595 (match_operand:DF 3 "nonimmediate_operand" "")))]
17596 "!TARGET_64BIT && reload_completed"
17597 [(set (match_dup 2)
17598 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17602 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17605 "split_di (operands+2, 1, operands+5, operands+6);
17606 split_di (operands+3, 1, operands+7, operands+8);
17607 split_di (operands, 1, operands+2, operands+3);")
17609 (define_expand "movxfcc"
17610 [(set (match_operand:XF 0 "register_operand" "")
17611 (if_then_else:XF (match_operand 1 "comparison_operator" "")
17612 (match_operand:XF 2 "register_operand" "")
17613 (match_operand:XF 3 "register_operand" "")))]
17615 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17617 (define_insn "*movxfcc_1"
17618 [(set (match_operand:XF 0 "register_operand" "=f,f")
17619 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
17620 [(reg FLAGS_REG) (const_int 0)])
17621 (match_operand:XF 2 "register_operand" "f,0")
17622 (match_operand:XF 3 "register_operand" "0,f")))]
17625 fcmov%F1\t{%2, %0|%0, %2}
17626 fcmov%f1\t{%3, %0|%0, %3}"
17627 [(set_attr "type" "fcmov")
17628 (set_attr "mode" "XF")])
17630 (define_expand "minsf3"
17632 (set (match_operand:SF 0 "register_operand" "")
17633 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17634 (match_operand:SF 2 "nonimmediate_operand" ""))
17637 (clobber (reg:CC FLAGS_REG))])]
17641 (define_insn "*minsf"
17642 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17643 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
17644 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17647 (clobber (reg:CC FLAGS_REG))]
17648 "TARGET_SSE && TARGET_IEEE_FP"
17651 (define_insn "*minsf_nonieee"
17652 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17653 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17654 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17657 (clobber (reg:CC FLAGS_REG))]
17658 "TARGET_SSE && !TARGET_IEEE_FP
17659 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17663 [(set (match_operand:SF 0 "register_operand" "")
17664 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17665 (match_operand:SF 2 "nonimmediate_operand" ""))
17666 (match_operand:SF 3 "register_operand" "")
17667 (match_operand:SF 4 "nonimmediate_operand" "")))
17668 (clobber (reg:CC FLAGS_REG))]
17669 "SSE_REG_P (operands[0]) && reload_completed
17670 && ((operands_match_p (operands[1], operands[3])
17671 && operands_match_p (operands[2], operands[4]))
17672 || (operands_match_p (operands[1], operands[4])
17673 && operands_match_p (operands[2], operands[3])))"
17674 [(set (match_dup 0)
17675 (if_then_else:SF (lt (match_dup 1)
17680 ;; Conditional addition patterns
17681 (define_expand "addqicc"
17682 [(match_operand:QI 0 "register_operand" "")
17683 (match_operand 1 "comparison_operator" "")
17684 (match_operand:QI 2 "register_operand" "")
17685 (match_operand:QI 3 "const_int_operand" "")]
17687 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17689 (define_expand "addhicc"
17690 [(match_operand:HI 0 "register_operand" "")
17691 (match_operand 1 "comparison_operator" "")
17692 (match_operand:HI 2 "register_operand" "")
17693 (match_operand:HI 3 "const_int_operand" "")]
17695 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17697 (define_expand "addsicc"
17698 [(match_operand:SI 0 "register_operand" "")
17699 (match_operand 1 "comparison_operator" "")
17700 (match_operand:SI 2 "register_operand" "")
17701 (match_operand:SI 3 "const_int_operand" "")]
17703 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17705 (define_expand "adddicc"
17706 [(match_operand:DI 0 "register_operand" "")
17707 (match_operand 1 "comparison_operator" "")
17708 (match_operand:DI 2 "register_operand" "")
17709 (match_operand:DI 3 "const_int_operand" "")]
17711 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17713 ;; We can't represent the LT test directly. Do this by swapping the operands.
17716 [(set (match_operand:SF 0 "fp_register_operand" "")
17717 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17718 (match_operand:SF 2 "register_operand" ""))
17719 (match_operand:SF 3 "register_operand" "")
17720 (match_operand:SF 4 "register_operand" "")))
17721 (clobber (reg:CC FLAGS_REG))]
17723 && ((operands_match_p (operands[1], operands[3])
17724 && operands_match_p (operands[2], operands[4]))
17725 || (operands_match_p (operands[1], operands[4])
17726 && operands_match_p (operands[2], operands[3])))"
17727 [(set (reg:CCFP FLAGS_REG)
17728 (compare:CCFP (match_dup 2)
17731 (if_then_else:SF (ge (reg:CCFP FLAGS_REG) (const_int 0))
17735 (define_insn "*minsf_sse"
17736 [(set (match_operand:SF 0 "register_operand" "=x")
17737 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
17738 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17741 "TARGET_SSE && reload_completed"
17742 "minss\t{%2, %0|%0, %2}"
17743 [(set_attr "type" "sse")
17744 (set_attr "mode" "SF")])
17746 (define_expand "mindf3"
17748 (set (match_operand:DF 0 "register_operand" "")
17749 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17750 (match_operand:DF 2 "nonimmediate_operand" ""))
17753 (clobber (reg:CC FLAGS_REG))])]
17754 "TARGET_SSE2 && TARGET_SSE_MATH"
17757 (define_insn "*mindf"
17758 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17759 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17760 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17763 (clobber (reg:CC FLAGS_REG))]
17764 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
17767 (define_insn "*mindf_nonieee"
17768 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17769 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17770 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17773 (clobber (reg:CC FLAGS_REG))]
17774 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17775 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17779 [(set (match_operand:DF 0 "register_operand" "")
17780 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17781 (match_operand:DF 2 "nonimmediate_operand" ""))
17782 (match_operand:DF 3 "register_operand" "")
17783 (match_operand:DF 4 "nonimmediate_operand" "")))
17784 (clobber (reg:CC FLAGS_REG))]
17785 "SSE_REG_P (operands[0]) && reload_completed
17786 && ((operands_match_p (operands[1], operands[3])
17787 && operands_match_p (operands[2], operands[4]))
17788 || (operands_match_p (operands[1], operands[4])
17789 && operands_match_p (operands[2], operands[3])))"
17790 [(set (match_dup 0)
17791 (if_then_else:DF (lt (match_dup 1)
17796 ;; We can't represent the LT test directly. Do this by swapping the operands.
17798 [(set (match_operand:DF 0 "fp_register_operand" "")
17799 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17800 (match_operand:DF 2 "register_operand" ""))
17801 (match_operand:DF 3 "register_operand" "")
17802 (match_operand:DF 4 "register_operand" "")))
17803 (clobber (reg:CC FLAGS_REG))]
17805 && ((operands_match_p (operands[1], operands[3])
17806 && operands_match_p (operands[2], operands[4]))
17807 || (operands_match_p (operands[1], operands[4])
17808 && operands_match_p (operands[2], operands[3])))"
17809 [(set (reg:CCFP FLAGS_REG)
17810 (compare:CCFP (match_dup 2)
17813 (if_then_else:DF (ge (reg:CCFP FLAGS_REG) (const_int 0))
17817 (define_insn "*mindf_sse"
17818 [(set (match_operand:DF 0 "register_operand" "=Y")
17819 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
17820 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17823 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17824 "minsd\t{%2, %0|%0, %2}"
17825 [(set_attr "type" "sse")
17826 (set_attr "mode" "DF")])
17828 (define_expand "maxsf3"
17830 (set (match_operand:SF 0 "register_operand" "")
17831 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17832 (match_operand:SF 2 "nonimmediate_operand" ""))
17835 (clobber (reg:CC FLAGS_REG))])]
17839 (define_insn "*maxsf"
17840 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17841 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
17842 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17845 (clobber (reg:CC FLAGS_REG))]
17846 "TARGET_SSE && TARGET_IEEE_FP"
17849 (define_insn "*maxsf_nonieee"
17850 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17851 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17852 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17855 (clobber (reg:CC FLAGS_REG))]
17856 "TARGET_SSE && !TARGET_IEEE_FP
17857 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17861 [(set (match_operand:SF 0 "register_operand" "")
17862 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17863 (match_operand:SF 2 "nonimmediate_operand" ""))
17864 (match_operand:SF 3 "register_operand" "")
17865 (match_operand:SF 4 "nonimmediate_operand" "")))
17866 (clobber (reg:CC FLAGS_REG))]
17867 "SSE_REG_P (operands[0]) && reload_completed
17868 && ((operands_match_p (operands[1], operands[3])
17869 && operands_match_p (operands[2], operands[4]))
17870 || (operands_match_p (operands[1], operands[4])
17871 && operands_match_p (operands[2], operands[3])))"
17872 [(set (match_dup 0)
17873 (if_then_else:SF (gt (match_dup 1)
17879 [(set (match_operand:SF 0 "fp_register_operand" "")
17880 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17881 (match_operand:SF 2 "register_operand" ""))
17882 (match_operand:SF 3 "register_operand" "")
17883 (match_operand:SF 4 "register_operand" "")))
17884 (clobber (reg:CC FLAGS_REG))]
17886 && ((operands_match_p (operands[1], operands[3])
17887 && operands_match_p (operands[2], operands[4]))
17888 || (operands_match_p (operands[1], operands[4])
17889 && operands_match_p (operands[2], operands[3])))"
17890 [(set (reg:CCFP FLAGS_REG)
17891 (compare:CCFP (match_dup 1)
17894 (if_then_else:SF (gt (reg:CCFP FLAGS_REG) (const_int 0))
17898 (define_insn "*maxsf_sse"
17899 [(set (match_operand:SF 0 "register_operand" "=x")
17900 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
17901 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17904 "TARGET_SSE && reload_completed"
17905 "maxss\t{%2, %0|%0, %2}"
17906 [(set_attr "type" "sse")
17907 (set_attr "mode" "SF")])
17909 (define_expand "maxdf3"
17911 (set (match_operand:DF 0 "register_operand" "")
17912 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17913 (match_operand:DF 2 "nonimmediate_operand" ""))
17916 (clobber (reg:CC FLAGS_REG))])]
17917 "TARGET_SSE2 && TARGET_SSE_MATH"
17920 (define_insn "*maxdf"
17921 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17922 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17923 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17926 (clobber (reg:CC FLAGS_REG))]
17927 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
17930 (define_insn "*maxdf_nonieee"
17931 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17932 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17933 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17936 (clobber (reg:CC FLAGS_REG))]
17937 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17938 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17942 [(set (match_operand:DF 0 "register_operand" "")
17943 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17944 (match_operand:DF 2 "nonimmediate_operand" ""))
17945 (match_operand:DF 3 "register_operand" "")
17946 (match_operand:DF 4 "nonimmediate_operand" "")))
17947 (clobber (reg:CC FLAGS_REG))]
17948 "SSE_REG_P (operands[0]) && reload_completed
17949 && ((operands_match_p (operands[1], operands[3])
17950 && operands_match_p (operands[2], operands[4]))
17951 || (operands_match_p (operands[1], operands[4])
17952 && operands_match_p (operands[2], operands[3])))"
17953 [(set (match_dup 0)
17954 (if_then_else:DF (gt (match_dup 1)
17960 [(set (match_operand:DF 0 "fp_register_operand" "")
17961 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17962 (match_operand:DF 2 "register_operand" ""))
17963 (match_operand:DF 3 "register_operand" "")
17964 (match_operand:DF 4 "register_operand" "")))
17965 (clobber (reg:CC FLAGS_REG))]
17967 && ((operands_match_p (operands[1], operands[3])
17968 && operands_match_p (operands[2], operands[4]))
17969 || (operands_match_p (operands[1], operands[4])
17970 && operands_match_p (operands[2], operands[3])))"
17971 [(set (reg:CCFP FLAGS_REG)
17972 (compare:CCFP (match_dup 1)
17975 (if_then_else:DF (gt (reg:CCFP FLAGS_REG) (const_int 0))
17979 (define_insn "*maxdf_sse"
17980 [(set (match_operand:DF 0 "register_operand" "=Y")
17981 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
17982 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17985 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17986 "maxsd\t{%2, %0|%0, %2}"
17987 [(set_attr "type" "sse")
17988 (set_attr "mode" "DF")])
17990 ;; Misc patterns (?)
17992 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
17993 ;; Otherwise there will be nothing to keep
17995 ;; [(set (reg ebp) (reg esp))]
17996 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
17997 ;; (clobber (eflags)]
17998 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
18000 ;; in proper program order.
18001 (define_insn "pro_epilogue_adjust_stack_1"
18002 [(set (match_operand:SI 0 "register_operand" "=r,r")
18003 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
18004 (match_operand:SI 2 "immediate_operand" "i,i")))
18005 (clobber (reg:CC FLAGS_REG))
18006 (clobber (mem:BLK (scratch)))]
18009 switch (get_attr_type (insn))
18012 return "mov{l}\t{%1, %0|%0, %1}";
18015 if (GET_CODE (operands[2]) == CONST_INT
18016 && (INTVAL (operands[2]) == 128
18017 || (INTVAL (operands[2]) < 0
18018 && INTVAL (operands[2]) != -128)))
18020 operands[2] = GEN_INT (-INTVAL (operands[2]));
18021 return "sub{l}\t{%2, %0|%0, %2}";
18023 return "add{l}\t{%2, %0|%0, %2}";
18026 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18027 return "lea{l}\t{%a2, %0|%0, %a2}";
18033 [(set (attr "type")
18034 (cond [(eq_attr "alternative" "0")
18035 (const_string "alu")
18036 (match_operand:SI 2 "const0_operand" "")
18037 (const_string "imov")
18039 (const_string "lea")))
18040 (set_attr "mode" "SI")])
18042 (define_insn "pro_epilogue_adjust_stack_rex64"
18043 [(set (match_operand:DI 0 "register_operand" "=r,r")
18044 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18045 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
18046 (clobber (reg:CC FLAGS_REG))
18047 (clobber (mem:BLK (scratch)))]
18050 switch (get_attr_type (insn))
18053 return "mov{q}\t{%1, %0|%0, %1}";
18056 if (GET_CODE (operands[2]) == CONST_INT
18057 /* Avoid overflows. */
18058 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
18059 && (INTVAL (operands[2]) == 128
18060 || (INTVAL (operands[2]) < 0
18061 && INTVAL (operands[2]) != -128)))
18063 operands[2] = GEN_INT (-INTVAL (operands[2]));
18064 return "sub{q}\t{%2, %0|%0, %2}";
18066 return "add{q}\t{%2, %0|%0, %2}";
18069 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18070 return "lea{q}\t{%a2, %0|%0, %a2}";
18076 [(set (attr "type")
18077 (cond [(eq_attr "alternative" "0")
18078 (const_string "alu")
18079 (match_operand:DI 2 "const0_operand" "")
18080 (const_string "imov")
18082 (const_string "lea")))
18083 (set_attr "mode" "DI")])
18085 (define_insn "pro_epilogue_adjust_stack_rex64_2"
18086 [(set (match_operand:DI 0 "register_operand" "=r,r")
18087 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18088 (match_operand:DI 3 "immediate_operand" "i,i")))
18089 (use (match_operand:DI 2 "register_operand" "r,r"))
18090 (clobber (reg:CC FLAGS_REG))
18091 (clobber (mem:BLK (scratch)))]
18094 switch (get_attr_type (insn))
18097 return "add{q}\t{%2, %0|%0, %2}";
18100 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
18101 return "lea{q}\t{%a2, %0|%0, %a2}";
18107 [(set_attr "type" "alu,lea")
18108 (set_attr "mode" "DI")])
18110 ;; Placeholder for the conditional moves. This one is split either to SSE
18111 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
18112 ;; fact is that compares supported by the cmp??ss instructions are exactly
18113 ;; swapped of those supported by cmove sequence.
18114 ;; The EQ/NE comparisons also needs bit care, since they are not directly
18115 ;; supported by i387 comparisons and we do need to emit two conditional moves
18118 (define_insn "sse_movsfcc"
18119 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
18120 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18121 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
18122 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
18123 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
18124 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
18125 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18126 (clobber (reg:CC FLAGS_REG))]
18128 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18129 /* Avoid combine from being smart and converting min/max
18130 instruction patterns into conditional moves. */
18131 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18132 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18133 || !rtx_equal_p (operands[4], operands[2])
18134 || !rtx_equal_p (operands[5], operands[3]))
18135 && (!TARGET_IEEE_FP
18136 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18139 (define_insn "sse_movsfcc_eq"
18140 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
18141 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
18142 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
18143 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
18144 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
18145 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
18146 (clobber (reg:CC FLAGS_REG))]
18148 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18151 (define_insn "sse_movdfcc"
18152 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
18153 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18154 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
18155 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
18156 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
18157 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
18158 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18159 (clobber (reg:CC FLAGS_REG))]
18161 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18162 /* Avoid combine from being smart and converting min/max
18163 instruction patterns into conditional moves. */
18164 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18165 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18166 || !rtx_equal_p (operands[4], operands[2])
18167 || !rtx_equal_p (operands[5], operands[3]))
18168 && (!TARGET_IEEE_FP
18169 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18172 (define_insn "sse_movdfcc_eq"
18173 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
18174 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
18175 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
18176 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
18177 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
18178 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
18179 (clobber (reg:CC FLAGS_REG))]
18181 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18184 ;; For non-sse moves just expand the usual cmove sequence.
18186 [(set (match_operand 0 "register_operand" "")
18187 (if_then_else (match_operator 1 "comparison_operator"
18188 [(match_operand 4 "nonimmediate_operand" "")
18189 (match_operand 5 "register_operand" "")])
18190 (match_operand 2 "nonimmediate_operand" "")
18191 (match_operand 3 "nonimmediate_operand" "")))
18192 (clobber (match_operand 6 "" ""))
18193 (clobber (reg:CC FLAGS_REG))]
18194 "!SSE_REG_P (operands[0]) && reload_completed
18195 && (GET_MODE (operands[0]) == SFmode
18196 || (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))"
18199 ix86_compare_op0 = operands[5];
18200 ix86_compare_op1 = operands[4];
18201 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
18202 VOIDmode, operands[5], operands[4]);
18203 ix86_expand_fp_movcc (operands);
18207 ;; Split SSE based conditional move into sequence:
18208 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
18209 ;; and op2, op0 - zero op2 if comparison was false
18210 ;; nand op0, op3 - load op3 to op0 if comparison was false
18211 ;; or op2, op0 - get the nonzero one into the result.
18213 [(set (match_operand:SF 0 "register_operand" "")
18214 (if_then_else:SF (match_operator:SF 1 "sse_comparison_operator"
18215 [(match_operand:SF 4 "register_operand" "")
18216 (match_operand:SF 5 "nonimmediate_operand" "")])
18217 (match_operand:SF 2 "register_operand" "")
18218 (match_operand:SF 3 "register_operand" "")))
18219 (clobber (match_operand 6 "" ""))
18220 (clobber (reg:CC FLAGS_REG))]
18221 "SSE_REG_P (operands[0]) && reload_completed"
18222 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18223 (set (match_dup 2) (and:V4SF (match_dup 2)
18225 (set (match_dup 8) (and:V4SF (not:V4SF (match_dup 8))
18227 (set (match_dup 0) (ior:V4SF (match_dup 6)
18230 /* If op2 == op3, op3 would be clobbered before it is used. */
18231 if (operands_match_p (operands[2], operands[3]))
18233 emit_move_insn (operands[0], operands[2]);
18237 PUT_MODE (operands[1], GET_MODE (operands[0]));
18238 if (operands_match_p (operands[0], operands[4]))
18239 operands[6] = operands[4], operands[7] = operands[2];
18241 operands[6] = operands[2], operands[7] = operands[4];
18242 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18243 operands[2] = simplify_gen_subreg (V4SFmode, operands[2], SFmode, 0);
18244 operands[3] = simplify_gen_subreg (V4SFmode, operands[3], SFmode, 0);
18245 operands[8] = simplify_gen_subreg (V4SFmode, operands[4], SFmode, 0);
18246 operands[6] = simplify_gen_subreg (V4SFmode, operands[6], SFmode, 0);
18247 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18251 [(set (match_operand:DF 0 "register_operand" "")
18252 (if_then_else:DF (match_operator:DF 1 "sse_comparison_operator"
18253 [(match_operand:DF 4 "register_operand" "")
18254 (match_operand:DF 5 "nonimmediate_operand" "")])
18255 (match_operand:DF 2 "register_operand" "")
18256 (match_operand:DF 3 "register_operand" "")))
18257 (clobber (match_operand 6 "" ""))
18258 (clobber (reg:CC FLAGS_REG))]
18259 "SSE_REG_P (operands[0]) && reload_completed"
18260 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18261 (set (match_dup 2) (and:V2DF (match_dup 2)
18263 (set (match_dup 8) (and:V2DF (not:V2DF (match_dup 8))
18265 (set (match_dup 0) (ior:V2DF (match_dup 6)
18268 if (TARGET_SSE_SPLIT_REGS && !optimize_size)
18270 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18271 emit_insn (gen_sse2_unpcklpd (op, op, op));
18272 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18273 emit_insn (gen_sse2_unpcklpd (op, op, op));
18276 /* If op2 == op3, op3 would be clobbered before it is used. */
18277 if (operands_match_p (operands[2], operands[3]))
18279 emit_move_insn (operands[0], operands[2]);
18283 PUT_MODE (operands[1], GET_MODE (operands[0]));
18284 if (operands_match_p (operands[0], operands[4]))
18285 operands[6] = operands[4], operands[7] = operands[2];
18287 operands[6] = operands[2], operands[7] = operands[4];
18288 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18289 operands[2] = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18290 operands[3] = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18291 operands[8] = simplify_gen_subreg (V2DFmode, operands[4], DFmode, 0);
18292 operands[6] = simplify_gen_subreg (V2DFmode, operands[6], DFmode, 0);
18293 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18296 ;; Special case of conditional move we can handle effectively.
18297 ;; Do not brother with the integer/floating point case, since these are
18298 ;; bot considerably slower, unlike in the generic case.
18299 (define_insn "*sse_movsfcc_const0_1"
18300 [(set (match_operand:SF 0 "register_operand" "=&x")
18301 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18302 [(match_operand:SF 4 "register_operand" "0")
18303 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18304 (match_operand:SF 2 "register_operand" "x")
18305 (match_operand:SF 3 "const0_operand" "X")))]
18309 (define_insn "*sse_movsfcc_const0_2"
18310 [(set (match_operand:SF 0 "register_operand" "=&x")
18311 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18312 [(match_operand:SF 4 "register_operand" "0")
18313 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18314 (match_operand:SF 2 "const0_operand" "X")
18315 (match_operand:SF 3 "register_operand" "x")))]
18319 (define_insn "*sse_movsfcc_const0_3"
18320 [(set (match_operand:SF 0 "register_operand" "=&x")
18321 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18322 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18323 (match_operand:SF 5 "register_operand" "0")])
18324 (match_operand:SF 2 "register_operand" "x")
18325 (match_operand:SF 3 "const0_operand" "X")))]
18329 (define_insn "*sse_movsfcc_const0_4"
18330 [(set (match_operand:SF 0 "register_operand" "=&x")
18331 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18332 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18333 (match_operand:SF 5 "register_operand" "0")])
18334 (match_operand:SF 2 "const0_operand" "X")
18335 (match_operand:SF 3 "register_operand" "x")))]
18339 (define_insn "*sse_movdfcc_const0_1"
18340 [(set (match_operand:DF 0 "register_operand" "=&Y")
18341 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18342 [(match_operand:DF 4 "register_operand" "0")
18343 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18344 (match_operand:DF 2 "register_operand" "Y")
18345 (match_operand:DF 3 "const0_operand" "X")))]
18349 (define_insn "*sse_movdfcc_const0_2"
18350 [(set (match_operand:DF 0 "register_operand" "=&Y")
18351 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18352 [(match_operand:DF 4 "register_operand" "0")
18353 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18354 (match_operand:DF 2 "const0_operand" "X")
18355 (match_operand:DF 3 "register_operand" "Y")))]
18359 (define_insn "*sse_movdfcc_const0_3"
18360 [(set (match_operand:DF 0 "register_operand" "=&Y")
18361 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18362 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18363 (match_operand:DF 5 "register_operand" "0")])
18364 (match_operand:DF 2 "register_operand" "Y")
18365 (match_operand:DF 3 "const0_operand" "X")))]
18369 (define_insn "*sse_movdfcc_const0_4"
18370 [(set (match_operand:DF 0 "register_operand" "=&Y")
18371 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18372 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18373 (match_operand:DF 5 "register_operand" "0")])
18374 (match_operand:DF 2 "const0_operand" "X")
18375 (match_operand:DF 3 "register_operand" "Y")))]
18380 [(set (match_operand:SF 0 "register_operand" "")
18381 (if_then_else:SF (match_operator 1 "comparison_operator"
18382 [(match_operand:SF 4 "nonimmediate_operand" "")
18383 (match_operand:SF 5 "nonimmediate_operand" "")])
18384 (match_operand:SF 2 "nonmemory_operand" "")
18385 (match_operand:SF 3 "nonmemory_operand" "")))]
18386 "SSE_REG_P (operands[0]) && reload_completed
18387 && (const0_operand (operands[2], GET_MODE (operands[0]))
18388 || const0_operand (operands[3], GET_MODE (operands[0])))"
18389 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18390 (set (match_dup 8) (and:V4SF (match_dup 6) (match_dup 7)))]
18392 PUT_MODE (operands[1], GET_MODE (operands[0]));
18393 if (!sse_comparison_operator (operands[1], VOIDmode)
18394 || !rtx_equal_p (operands[0], operands[4]))
18396 rtx tmp = operands[5];
18397 operands[5] = operands[4];
18399 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18401 if (!rtx_equal_p (operands[0], operands[4]))
18403 operands[8] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18404 if (const0_operand (operands[2], GET_MODE (operands[2])))
18406 operands[7] = operands[3];
18407 operands[6] = gen_rtx_NOT (V4SFmode, operands[8]);
18411 operands[7] = operands[2];
18412 operands[6] = operands[8];
18414 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18418 [(set (match_operand:DF 0 "register_operand" "")
18419 (if_then_else:DF (match_operator 1 "comparison_operator"
18420 [(match_operand:DF 4 "nonimmediate_operand" "")
18421 (match_operand:DF 5 "nonimmediate_operand" "")])
18422 (match_operand:DF 2 "nonmemory_operand" "")
18423 (match_operand:DF 3 "nonmemory_operand" "")))]
18424 "SSE_REG_P (operands[0]) && reload_completed
18425 && (const0_operand (operands[2], GET_MODE (operands[0]))
18426 || const0_operand (operands[3], GET_MODE (operands[0])))"
18427 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18428 (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))]
18430 if (TARGET_SSE_SPLIT_REGS && !optimize_size)
18432 if (REG_P (operands[2]))
18434 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18435 emit_insn (gen_sse2_unpcklpd (op, op, op));
18437 if (REG_P (operands[3]))
18439 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18440 emit_insn (gen_sse2_unpcklpd (op, op, op));
18443 PUT_MODE (operands[1], GET_MODE (operands[0]));
18444 if (!sse_comparison_operator (operands[1], VOIDmode)
18445 || !rtx_equal_p (operands[0], operands[4]))
18447 rtx tmp = operands[5];
18448 operands[5] = operands[4];
18450 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18452 if (!rtx_equal_p (operands[0], operands[4]))
18454 operands[8] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18455 if (const0_operand (operands[2], GET_MODE (operands[2])))
18457 operands[7] = operands[3];
18458 operands[6] = gen_rtx_NOT (V2DFmode, operands[8]);
18462 operands[7] = operands[2];
18463 operands[6] = operands[8];
18465 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18468 (define_expand "allocate_stack_worker"
18469 [(match_operand:SI 0 "register_operand" "")]
18470 "TARGET_STACK_PROBE"
18472 if (reload_completed)
18475 emit_insn (gen_allocate_stack_worker_rex64_postreload (operands[0]));
18477 emit_insn (gen_allocate_stack_worker_postreload (operands[0]));
18482 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
18484 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
18489 (define_insn "allocate_stack_worker_1"
18490 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18491 UNSPECV_STACK_PROBE)
18492 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18493 (clobber (match_scratch:SI 1 "=0"))
18494 (clobber (reg:CC FLAGS_REG))]
18495 "!TARGET_64BIT && TARGET_STACK_PROBE"
18497 [(set_attr "type" "multi")
18498 (set_attr "length" "5")])
18500 (define_expand "allocate_stack_worker_postreload"
18501 [(parallel [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18502 UNSPECV_STACK_PROBE)
18503 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18504 (clobber (match_dup 0))
18505 (clobber (reg:CC FLAGS_REG))])]
18509 (define_insn "allocate_stack_worker_rex64"
18510 [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18511 UNSPECV_STACK_PROBE)
18512 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18513 (clobber (match_scratch:DI 1 "=0"))
18514 (clobber (reg:CC FLAGS_REG))]
18515 "TARGET_64BIT && TARGET_STACK_PROBE"
18517 [(set_attr "type" "multi")
18518 (set_attr "length" "5")])
18520 (define_expand "allocate_stack_worker_rex64_postreload"
18521 [(parallel [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18522 UNSPECV_STACK_PROBE)
18523 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18524 (clobber (match_dup 0))
18525 (clobber (reg:CC FLAGS_REG))])]
18529 (define_expand "allocate_stack"
18530 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
18531 (minus:SI (reg:SI SP_REG)
18532 (match_operand:SI 1 "general_operand" "")))
18533 (clobber (reg:CC FLAGS_REG))])
18534 (parallel [(set (reg:SI SP_REG)
18535 (minus:SI (reg:SI SP_REG) (match_dup 1)))
18536 (clobber (reg:CC FLAGS_REG))])]
18537 "TARGET_STACK_PROBE"
18539 #ifdef CHECK_STACK_LIMIT
18540 if (GET_CODE (operands[1]) == CONST_INT
18541 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
18542 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
18546 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
18549 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
18553 (define_expand "builtin_setjmp_receiver"
18554 [(label_ref (match_operand 0 "" ""))]
18555 "!TARGET_64BIT && flag_pic"
18557 emit_insn (gen_set_got (pic_offset_table_rtx));
18561 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
18564 [(set (match_operand 0 "register_operand" "")
18565 (match_operator 3 "promotable_binary_operator"
18566 [(match_operand 1 "register_operand" "")
18567 (match_operand 2 "aligned_operand" "")]))
18568 (clobber (reg:CC FLAGS_REG))]
18569 "! TARGET_PARTIAL_REG_STALL && reload_completed
18570 && ((GET_MODE (operands[0]) == HImode
18571 && ((!optimize_size && !TARGET_FAST_PREFIX)
18572 || GET_CODE (operands[2]) != CONST_INT
18573 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
18574 || (GET_MODE (operands[0]) == QImode
18575 && (TARGET_PROMOTE_QImode || optimize_size)))"
18576 [(parallel [(set (match_dup 0)
18577 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18578 (clobber (reg:CC FLAGS_REG))])]
18579 "operands[0] = gen_lowpart (SImode, operands[0]);
18580 operands[1] = gen_lowpart (SImode, operands[1]);
18581 if (GET_CODE (operands[3]) != ASHIFT)
18582 operands[2] = gen_lowpart (SImode, operands[2]);
18583 PUT_MODE (operands[3], SImode);")
18585 ; Promote the QImode tests, as i386 has encoding of the AND
18586 ; instruction with 32-bit sign-extended immediate and thus the
18587 ; instruction size is unchanged, except in the %eax case for
18588 ; which it is increased by one byte, hence the ! optimize_size.
18590 [(set (match_operand 0 "flags_reg_operand" "")
18591 (match_operator 2 "compare_operator"
18592 [(and (match_operand 3 "aligned_operand" "")
18593 (match_operand 4 "const_int_operand" ""))
18595 (set (match_operand 1 "register_operand" "")
18596 (and (match_dup 3) (match_dup 4)))]
18597 "! TARGET_PARTIAL_REG_STALL && reload_completed
18598 /* Ensure that the operand will remain sign-extended immediate. */
18599 && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode)
18601 && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
18602 || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))"
18603 [(parallel [(set (match_dup 0)
18604 (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4))
18607 (and:SI (match_dup 3) (match_dup 4)))])]
18610 = gen_int_mode (INTVAL (operands[4])
18611 & GET_MODE_MASK (GET_MODE (operands[1])), SImode);
18612 operands[1] = gen_lowpart (SImode, operands[1]);
18613 operands[3] = gen_lowpart (SImode, operands[3]);
18616 ; Don't promote the QImode tests, as i386 doesn't have encoding of
18617 ; the TEST instruction with 32-bit sign-extended immediate and thus
18618 ; the instruction size would at least double, which is not what we
18619 ; want even with ! optimize_size.
18621 [(set (match_operand 0 "flags_reg_operand" "")
18622 (match_operator 1 "compare_operator"
18623 [(and (match_operand:HI 2 "aligned_operand" "")
18624 (match_operand:HI 3 "const_int_operand" ""))
18626 "! TARGET_PARTIAL_REG_STALL && reload_completed
18627 /* Ensure that the operand will remain sign-extended immediate. */
18628 && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)
18629 && ! TARGET_FAST_PREFIX
18630 && ! optimize_size"
18631 [(set (match_dup 0)
18632 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
18636 = gen_int_mode (INTVAL (operands[3])
18637 & GET_MODE_MASK (GET_MODE (operands[2])), SImode);
18638 operands[2] = gen_lowpart (SImode, operands[2]);
18642 [(set (match_operand 0 "register_operand" "")
18643 (neg (match_operand 1 "register_operand" "")))
18644 (clobber (reg:CC FLAGS_REG))]
18645 "! TARGET_PARTIAL_REG_STALL && reload_completed
18646 && (GET_MODE (operands[0]) == HImode
18647 || (GET_MODE (operands[0]) == QImode
18648 && (TARGET_PROMOTE_QImode || optimize_size)))"
18649 [(parallel [(set (match_dup 0)
18650 (neg:SI (match_dup 1)))
18651 (clobber (reg:CC FLAGS_REG))])]
18652 "operands[0] = gen_lowpart (SImode, operands[0]);
18653 operands[1] = gen_lowpart (SImode, operands[1]);")
18656 [(set (match_operand 0 "register_operand" "")
18657 (not (match_operand 1 "register_operand" "")))]
18658 "! TARGET_PARTIAL_REG_STALL && reload_completed
18659 && (GET_MODE (operands[0]) == HImode
18660 || (GET_MODE (operands[0]) == QImode
18661 && (TARGET_PROMOTE_QImode || optimize_size)))"
18662 [(set (match_dup 0)
18663 (not:SI (match_dup 1)))]
18664 "operands[0] = gen_lowpart (SImode, operands[0]);
18665 operands[1] = gen_lowpart (SImode, operands[1]);")
18668 [(set (match_operand 0 "register_operand" "")
18669 (if_then_else (match_operator 1 "comparison_operator"
18670 [(reg FLAGS_REG) (const_int 0)])
18671 (match_operand 2 "register_operand" "")
18672 (match_operand 3 "register_operand" "")))]
18673 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
18674 && (GET_MODE (operands[0]) == HImode
18675 || (GET_MODE (operands[0]) == QImode
18676 && (TARGET_PROMOTE_QImode || optimize_size)))"
18677 [(set (match_dup 0)
18678 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
18679 "operands[0] = gen_lowpart (SImode, operands[0]);
18680 operands[2] = gen_lowpart (SImode, operands[2]);
18681 operands[3] = gen_lowpart (SImode, operands[3]);")
18684 ;; RTL Peephole optimizations, run before sched2. These primarily look to
18685 ;; transform a complex memory operation into two memory to register operations.
18687 ;; Don't push memory operands
18689 [(set (match_operand:SI 0 "push_operand" "")
18690 (match_operand:SI 1 "memory_operand" ""))
18691 (match_scratch:SI 2 "r")]
18692 "! optimize_size && ! TARGET_PUSH_MEMORY"
18693 [(set (match_dup 2) (match_dup 1))
18694 (set (match_dup 0) (match_dup 2))]
18698 [(set (match_operand:DI 0 "push_operand" "")
18699 (match_operand:DI 1 "memory_operand" ""))
18700 (match_scratch:DI 2 "r")]
18701 "! optimize_size && ! TARGET_PUSH_MEMORY"
18702 [(set (match_dup 2) (match_dup 1))
18703 (set (match_dup 0) (match_dup 2))]
18706 ;; We need to handle SFmode only, because DFmode and XFmode is split to
18709 [(set (match_operand:SF 0 "push_operand" "")
18710 (match_operand:SF 1 "memory_operand" ""))
18711 (match_scratch:SF 2 "r")]
18712 "! optimize_size && ! TARGET_PUSH_MEMORY"
18713 [(set (match_dup 2) (match_dup 1))
18714 (set (match_dup 0) (match_dup 2))]
18718 [(set (match_operand:HI 0 "push_operand" "")
18719 (match_operand:HI 1 "memory_operand" ""))
18720 (match_scratch:HI 2 "r")]
18721 "! optimize_size && ! TARGET_PUSH_MEMORY"
18722 [(set (match_dup 2) (match_dup 1))
18723 (set (match_dup 0) (match_dup 2))]
18727 [(set (match_operand:QI 0 "push_operand" "")
18728 (match_operand:QI 1 "memory_operand" ""))
18729 (match_scratch:QI 2 "q")]
18730 "! optimize_size && ! TARGET_PUSH_MEMORY"
18731 [(set (match_dup 2) (match_dup 1))
18732 (set (match_dup 0) (match_dup 2))]
18735 ;; Don't move an immediate directly to memory when the instruction
18738 [(match_scratch:SI 1 "r")
18739 (set (match_operand:SI 0 "memory_operand" "")
18742 && ! TARGET_USE_MOV0
18743 && TARGET_SPLIT_LONG_MOVES
18744 && get_attr_length (insn) >= ix86_cost->large_insn
18745 && peep2_regno_dead_p (0, FLAGS_REG)"
18746 [(parallel [(set (match_dup 1) (const_int 0))
18747 (clobber (reg:CC FLAGS_REG))])
18748 (set (match_dup 0) (match_dup 1))]
18752 [(match_scratch:HI 1 "r")
18753 (set (match_operand:HI 0 "memory_operand" "")
18756 && ! TARGET_USE_MOV0
18757 && TARGET_SPLIT_LONG_MOVES
18758 && get_attr_length (insn) >= ix86_cost->large_insn
18759 && peep2_regno_dead_p (0, FLAGS_REG)"
18760 [(parallel [(set (match_dup 2) (const_int 0))
18761 (clobber (reg:CC FLAGS_REG))])
18762 (set (match_dup 0) (match_dup 1))]
18763 "operands[2] = gen_lowpart (SImode, operands[1]);")
18766 [(match_scratch:QI 1 "q")
18767 (set (match_operand:QI 0 "memory_operand" "")
18770 && ! TARGET_USE_MOV0
18771 && TARGET_SPLIT_LONG_MOVES
18772 && get_attr_length (insn) >= ix86_cost->large_insn
18773 && peep2_regno_dead_p (0, FLAGS_REG)"
18774 [(parallel [(set (match_dup 2) (const_int 0))
18775 (clobber (reg:CC FLAGS_REG))])
18776 (set (match_dup 0) (match_dup 1))]
18777 "operands[2] = gen_lowpart (SImode, operands[1]);")
18780 [(match_scratch:SI 2 "r")
18781 (set (match_operand:SI 0 "memory_operand" "")
18782 (match_operand:SI 1 "immediate_operand" ""))]
18784 && get_attr_length (insn) >= ix86_cost->large_insn
18785 && TARGET_SPLIT_LONG_MOVES"
18786 [(set (match_dup 2) (match_dup 1))
18787 (set (match_dup 0) (match_dup 2))]
18791 [(match_scratch:HI 2 "r")
18792 (set (match_operand:HI 0 "memory_operand" "")
18793 (match_operand:HI 1 "immediate_operand" ""))]
18794 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18795 && TARGET_SPLIT_LONG_MOVES"
18796 [(set (match_dup 2) (match_dup 1))
18797 (set (match_dup 0) (match_dup 2))]
18801 [(match_scratch:QI 2 "q")
18802 (set (match_operand:QI 0 "memory_operand" "")
18803 (match_operand:QI 1 "immediate_operand" ""))]
18804 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18805 && TARGET_SPLIT_LONG_MOVES"
18806 [(set (match_dup 2) (match_dup 1))
18807 (set (match_dup 0) (match_dup 2))]
18810 ;; Don't compare memory with zero, load and use a test instead.
18812 [(set (match_operand 0 "flags_reg_operand" "")
18813 (match_operator 1 "compare_operator"
18814 [(match_operand:SI 2 "memory_operand" "")
18816 (match_scratch:SI 3 "r")]
18817 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
18818 [(set (match_dup 3) (match_dup 2))
18819 (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
18822 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
18823 ;; Don't split NOTs with a displacement operand, because resulting XOR
18824 ;; will not be pairable anyway.
18826 ;; On AMD K6, NOT is vector decoded with memory operand that cannot be
18827 ;; represented using a modRM byte. The XOR replacement is long decoded,
18828 ;; so this split helps here as well.
18830 ;; Note: Can't do this as a regular split because we can't get proper
18831 ;; lifetime information then.
18834 [(set (match_operand:SI 0 "nonimmediate_operand" "")
18835 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
18837 && peep2_regno_dead_p (0, FLAGS_REG)
18838 && ((TARGET_PENTIUM
18839 && (GET_CODE (operands[0]) != MEM
18840 || !memory_displacement_operand (operands[0], SImode)))
18841 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
18842 [(parallel [(set (match_dup 0)
18843 (xor:SI (match_dup 1) (const_int -1)))
18844 (clobber (reg:CC FLAGS_REG))])]
18848 [(set (match_operand:HI 0 "nonimmediate_operand" "")
18849 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
18851 && peep2_regno_dead_p (0, FLAGS_REG)
18852 && ((TARGET_PENTIUM
18853 && (GET_CODE (operands[0]) != MEM
18854 || !memory_displacement_operand (operands[0], HImode)))
18855 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
18856 [(parallel [(set (match_dup 0)
18857 (xor:HI (match_dup 1) (const_int -1)))
18858 (clobber (reg:CC FLAGS_REG))])]
18862 [(set (match_operand:QI 0 "nonimmediate_operand" "")
18863 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
18865 && peep2_regno_dead_p (0, FLAGS_REG)
18866 && ((TARGET_PENTIUM
18867 && (GET_CODE (operands[0]) != MEM
18868 || !memory_displacement_operand (operands[0], QImode)))
18869 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
18870 [(parallel [(set (match_dup 0)
18871 (xor:QI (match_dup 1) (const_int -1)))
18872 (clobber (reg:CC FLAGS_REG))])]
18875 ;; Non pairable "test imm, reg" instructions can be translated to
18876 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
18877 ;; byte opcode instead of two, have a short form for byte operands),
18878 ;; so do it for other CPUs as well. Given that the value was dead,
18879 ;; this should not create any new dependencies. Pass on the sub-word
18880 ;; versions if we're concerned about partial register stalls.
18883 [(set (match_operand 0 "flags_reg_operand" "")
18884 (match_operator 1 "compare_operator"
18885 [(and:SI (match_operand:SI 2 "register_operand" "")
18886 (match_operand:SI 3 "immediate_operand" ""))
18888 "ix86_match_ccmode (insn, CCNOmode)
18889 && (true_regnum (operands[2]) != 0
18890 || (GET_CODE (operands[3]) == CONST_INT
18891 && CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'K')))
18892 && peep2_reg_dead_p (1, operands[2])"
18894 [(set (match_dup 0)
18895 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
18898 (and:SI (match_dup 2) (match_dup 3)))])]
18901 ;; We don't need to handle HImode case, because it will be promoted to SImode
18902 ;; on ! TARGET_PARTIAL_REG_STALL
18905 [(set (match_operand 0 "flags_reg_operand" "")
18906 (match_operator 1 "compare_operator"
18907 [(and:QI (match_operand:QI 2 "register_operand" "")
18908 (match_operand:QI 3 "immediate_operand" ""))
18910 "! TARGET_PARTIAL_REG_STALL
18911 && ix86_match_ccmode (insn, CCNOmode)
18912 && true_regnum (operands[2]) != 0
18913 && peep2_reg_dead_p (1, operands[2])"
18915 [(set (match_dup 0)
18916 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
18919 (and:QI (match_dup 2) (match_dup 3)))])]
18923 [(set (match_operand 0 "flags_reg_operand" "")
18924 (match_operator 1 "compare_operator"
18927 (match_operand 2 "ext_register_operand" "")
18930 (match_operand 3 "const_int_operand" ""))
18932 "! TARGET_PARTIAL_REG_STALL
18933 && ix86_match_ccmode (insn, CCNOmode)
18934 && true_regnum (operands[2]) != 0
18935 && peep2_reg_dead_p (1, operands[2])"
18936 [(parallel [(set (match_dup 0)
18945 (set (zero_extract:SI (match_dup 2)
18956 ;; Don't do logical operations with memory inputs.
18958 [(match_scratch:SI 2 "r")
18959 (parallel [(set (match_operand:SI 0 "register_operand" "")
18960 (match_operator:SI 3 "arith_or_logical_operator"
18962 (match_operand:SI 1 "memory_operand" "")]))
18963 (clobber (reg:CC FLAGS_REG))])]
18964 "! optimize_size && ! TARGET_READ_MODIFY"
18965 [(set (match_dup 2) (match_dup 1))
18966 (parallel [(set (match_dup 0)
18967 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
18968 (clobber (reg:CC FLAGS_REG))])]
18972 [(match_scratch:SI 2 "r")
18973 (parallel [(set (match_operand:SI 0 "register_operand" "")
18974 (match_operator:SI 3 "arith_or_logical_operator"
18975 [(match_operand:SI 1 "memory_operand" "")
18977 (clobber (reg:CC FLAGS_REG))])]
18978 "! optimize_size && ! TARGET_READ_MODIFY"
18979 [(set (match_dup 2) (match_dup 1))
18980 (parallel [(set (match_dup 0)
18981 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
18982 (clobber (reg:CC FLAGS_REG))])]
18985 ; Don't do logical operations with memory outputs
18987 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
18988 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
18989 ; the same decoder scheduling characteristics as the original.
18992 [(match_scratch:SI 2 "r")
18993 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18994 (match_operator:SI 3 "arith_or_logical_operator"
18996 (match_operand:SI 1 "nonmemory_operand" "")]))
18997 (clobber (reg:CC FLAGS_REG))])]
18998 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18999 [(set (match_dup 2) (match_dup 0))
19000 (parallel [(set (match_dup 2)
19001 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
19002 (clobber (reg:CC FLAGS_REG))])
19003 (set (match_dup 0) (match_dup 2))]
19007 [(match_scratch:SI 2 "r")
19008 (parallel [(set (match_operand:SI 0 "memory_operand" "")
19009 (match_operator:SI 3 "arith_or_logical_operator"
19010 [(match_operand:SI 1 "nonmemory_operand" "")
19012 (clobber (reg:CC FLAGS_REG))])]
19013 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
19014 [(set (match_dup 2) (match_dup 0))
19015 (parallel [(set (match_dup 2)
19016 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
19017 (clobber (reg:CC FLAGS_REG))])
19018 (set (match_dup 0) (match_dup 2))]
19021 ;; Attempt to always use XOR for zeroing registers.
19023 [(set (match_operand 0 "register_operand" "")
19025 "(GET_MODE (operands[0]) == QImode
19026 || GET_MODE (operands[0]) == HImode
19027 || GET_MODE (operands[0]) == SImode
19028 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19029 && (! TARGET_USE_MOV0 || optimize_size)
19030 && peep2_regno_dead_p (0, FLAGS_REG)"
19031 [(parallel [(set (match_dup 0) (const_int 0))
19032 (clobber (reg:CC FLAGS_REG))])]
19033 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19037 [(set (strict_low_part (match_operand 0 "register_operand" ""))
19039 "(GET_MODE (operands[0]) == QImode
19040 || GET_MODE (operands[0]) == HImode)
19041 && (! TARGET_USE_MOV0 || optimize_size)
19042 && peep2_regno_dead_p (0, FLAGS_REG)"
19043 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
19044 (clobber (reg:CC FLAGS_REG))])])
19046 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
19048 [(set (match_operand 0 "register_operand" "")
19050 "(GET_MODE (operands[0]) == HImode
19051 || GET_MODE (operands[0]) == SImode
19052 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19053 && (optimize_size || TARGET_PENTIUM)
19054 && peep2_regno_dead_p (0, FLAGS_REG)"
19055 [(parallel [(set (match_dup 0) (const_int -1))
19056 (clobber (reg:CC FLAGS_REG))])]
19057 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19060 ;; Attempt to convert simple leas to adds. These can be created by
19063 [(set (match_operand:SI 0 "register_operand" "")
19064 (plus:SI (match_dup 0)
19065 (match_operand:SI 1 "nonmemory_operand" "")))]
19066 "peep2_regno_dead_p (0, FLAGS_REG)"
19067 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
19068 (clobber (reg:CC FLAGS_REG))])]
19072 [(set (match_operand:SI 0 "register_operand" "")
19073 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
19074 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
19075 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
19076 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
19077 (clobber (reg:CC FLAGS_REG))])]
19078 "operands[2] = gen_lowpart (SImode, operands[2]);")
19081 [(set (match_operand:DI 0 "register_operand" "")
19082 (plus:DI (match_dup 0)
19083 (match_operand:DI 1 "x86_64_general_operand" "")))]
19084 "peep2_regno_dead_p (0, FLAGS_REG)"
19085 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
19086 (clobber (reg:CC FLAGS_REG))])]
19090 [(set (match_operand:SI 0 "register_operand" "")
19091 (mult:SI (match_dup 0)
19092 (match_operand:SI 1 "const_int_operand" "")))]
19093 "exact_log2 (INTVAL (operands[1])) >= 0
19094 && peep2_regno_dead_p (0, FLAGS_REG)"
19095 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19096 (clobber (reg:CC FLAGS_REG))])]
19097 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19100 [(set (match_operand:DI 0 "register_operand" "")
19101 (mult:DI (match_dup 0)
19102 (match_operand:DI 1 "const_int_operand" "")))]
19103 "exact_log2 (INTVAL (operands[1])) >= 0
19104 && peep2_regno_dead_p (0, FLAGS_REG)"
19105 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
19106 (clobber (reg:CC FLAGS_REG))])]
19107 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19110 [(set (match_operand:SI 0 "register_operand" "")
19111 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
19112 (match_operand:DI 2 "const_int_operand" "")) 0))]
19113 "exact_log2 (INTVAL (operands[2])) >= 0
19114 && REGNO (operands[0]) == REGNO (operands[1])
19115 && peep2_regno_dead_p (0, FLAGS_REG)"
19116 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19117 (clobber (reg:CC FLAGS_REG))])]
19118 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
19120 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
19121 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
19122 ;; many CPUs it is also faster, since special hardware to avoid esp
19123 ;; dependencies is present.
19125 ;; While some of these conversions may be done using splitters, we use peepholes
19126 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
19128 ;; Convert prologue esp subtractions to push.
19129 ;; We need register to push. In order to keep verify_flow_info happy we have
19131 ;; - use scratch and clobber it in order to avoid dependencies
19132 ;; - use already live register
19133 ;; We can't use the second way right now, since there is no reliable way how to
19134 ;; verify that given register is live. First choice will also most likely in
19135 ;; fewer dependencies. On the place of esp adjustments it is very likely that
19136 ;; call clobbered registers are dead. We may want to use base pointer as an
19137 ;; alternative when no register is available later.
19140 [(match_scratch:SI 0 "r")
19141 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19142 (clobber (reg:CC FLAGS_REG))
19143 (clobber (mem:BLK (scratch)))])]
19144 "optimize_size || !TARGET_SUB_ESP_4"
19145 [(clobber (match_dup 0))
19146 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19147 (clobber (mem:BLK (scratch)))])])
19150 [(match_scratch:SI 0 "r")
19151 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19152 (clobber (reg:CC FLAGS_REG))
19153 (clobber (mem:BLK (scratch)))])]
19154 "optimize_size || !TARGET_SUB_ESP_8"
19155 [(clobber (match_dup 0))
19156 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19157 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19158 (clobber (mem:BLK (scratch)))])])
19160 ;; Convert esp subtractions to push.
19162 [(match_scratch:SI 0 "r")
19163 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19164 (clobber (reg:CC FLAGS_REG))])]
19165 "optimize_size || !TARGET_SUB_ESP_4"
19166 [(clobber (match_dup 0))
19167 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19170 [(match_scratch:SI 0 "r")
19171 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19172 (clobber (reg:CC FLAGS_REG))])]
19173 "optimize_size || !TARGET_SUB_ESP_8"
19174 [(clobber (match_dup 0))
19175 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19176 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19178 ;; Convert epilogue deallocator to pop.
19180 [(match_scratch:SI 0 "r")
19181 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19182 (clobber (reg:CC FLAGS_REG))
19183 (clobber (mem:BLK (scratch)))])]
19184 "optimize_size || !TARGET_ADD_ESP_4"
19185 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19186 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19187 (clobber (mem:BLK (scratch)))])]
19190 ;; Two pops case is tricky, since pop causes dependency on destination register.
19191 ;; We use two registers if available.
19193 [(match_scratch:SI 0 "r")
19194 (match_scratch:SI 1 "r")
19195 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19196 (clobber (reg:CC FLAGS_REG))
19197 (clobber (mem:BLK (scratch)))])]
19198 "optimize_size || !TARGET_ADD_ESP_8"
19199 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19200 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19201 (clobber (mem:BLK (scratch)))])
19202 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19203 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19207 [(match_scratch:SI 0 "r")
19208 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19209 (clobber (reg:CC FLAGS_REG))
19210 (clobber (mem:BLK (scratch)))])]
19212 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19213 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19214 (clobber (mem:BLK (scratch)))])
19215 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19216 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19219 ;; Convert esp additions to pop.
19221 [(match_scratch:SI 0 "r")
19222 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19223 (clobber (reg:CC FLAGS_REG))])]
19225 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19226 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19229 ;; Two pops case is tricky, since pop causes dependency on destination register.
19230 ;; We use two registers if available.
19232 [(match_scratch:SI 0 "r")
19233 (match_scratch:SI 1 "r")
19234 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19235 (clobber (reg:CC FLAGS_REG))])]
19237 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19238 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19239 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19240 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19244 [(match_scratch:SI 0 "r")
19245 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19246 (clobber (reg:CC FLAGS_REG))])]
19248 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19249 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19250 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19251 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19254 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
19255 ;; required and register dies. Similarly for 128 to plus -128.
19257 [(set (match_operand 0 "flags_reg_operand" "")
19258 (match_operator 1 "compare_operator"
19259 [(match_operand 2 "register_operand" "")
19260 (match_operand 3 "const_int_operand" "")]))]
19261 "(INTVAL (operands[3]) == -1
19262 || INTVAL (operands[3]) == 1
19263 || INTVAL (operands[3]) == 128)
19264 && ix86_match_ccmode (insn, CCGCmode)
19265 && peep2_reg_dead_p (1, operands[2])"
19266 [(parallel [(set (match_dup 0)
19267 (match_op_dup 1 [(match_dup 2) (match_dup 3)]))
19268 (clobber (match_dup 2))])]
19272 [(match_scratch:DI 0 "r")
19273 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19274 (clobber (reg:CC FLAGS_REG))
19275 (clobber (mem:BLK (scratch)))])]
19276 "optimize_size || !TARGET_SUB_ESP_4"
19277 [(clobber (match_dup 0))
19278 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19279 (clobber (mem:BLK (scratch)))])])
19282 [(match_scratch:DI 0 "r")
19283 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19284 (clobber (reg:CC FLAGS_REG))
19285 (clobber (mem:BLK (scratch)))])]
19286 "optimize_size || !TARGET_SUB_ESP_8"
19287 [(clobber (match_dup 0))
19288 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19289 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19290 (clobber (mem:BLK (scratch)))])])
19292 ;; Convert esp subtractions to push.
19294 [(match_scratch:DI 0 "r")
19295 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19296 (clobber (reg:CC FLAGS_REG))])]
19297 "optimize_size || !TARGET_SUB_ESP_4"
19298 [(clobber (match_dup 0))
19299 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19302 [(match_scratch:DI 0 "r")
19303 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19304 (clobber (reg:CC FLAGS_REG))])]
19305 "optimize_size || !TARGET_SUB_ESP_8"
19306 [(clobber (match_dup 0))
19307 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19308 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19310 ;; Convert epilogue deallocator to pop.
19312 [(match_scratch:DI 0 "r")
19313 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19314 (clobber (reg:CC FLAGS_REG))
19315 (clobber (mem:BLK (scratch)))])]
19316 "optimize_size || !TARGET_ADD_ESP_4"
19317 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19318 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19319 (clobber (mem:BLK (scratch)))])]
19322 ;; Two pops case is tricky, since pop causes dependency on destination register.
19323 ;; We use two registers if available.
19325 [(match_scratch:DI 0 "r")
19326 (match_scratch:DI 1 "r")
19327 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19328 (clobber (reg:CC FLAGS_REG))
19329 (clobber (mem:BLK (scratch)))])]
19330 "optimize_size || !TARGET_ADD_ESP_8"
19331 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19332 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19333 (clobber (mem:BLK (scratch)))])
19334 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19335 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19339 [(match_scratch:DI 0 "r")
19340 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19341 (clobber (reg:CC FLAGS_REG))
19342 (clobber (mem:BLK (scratch)))])]
19344 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19345 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19346 (clobber (mem:BLK (scratch)))])
19347 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19348 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19351 ;; Convert esp additions to pop.
19353 [(match_scratch:DI 0 "r")
19354 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19355 (clobber (reg:CC FLAGS_REG))])]
19357 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19358 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19361 ;; Two pops case is tricky, since pop causes dependency on destination register.
19362 ;; We use two registers if available.
19364 [(match_scratch:DI 0 "r")
19365 (match_scratch:DI 1 "r")
19366 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19367 (clobber (reg:CC FLAGS_REG))])]
19369 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19370 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19371 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19372 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19376 [(match_scratch:DI 0 "r")
19377 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19378 (clobber (reg:CC FLAGS_REG))])]
19380 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19381 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19382 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19383 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19386 ;; Convert imul by three, five and nine into lea
19389 [(set (match_operand:SI 0 "register_operand" "")
19390 (mult:SI (match_operand:SI 1 "register_operand" "")
19391 (match_operand:SI 2 "const_int_operand" "")))
19392 (clobber (reg:CC FLAGS_REG))])]
19393 "INTVAL (operands[2]) == 3
19394 || INTVAL (operands[2]) == 5
19395 || INTVAL (operands[2]) == 9"
19396 [(set (match_dup 0)
19397 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
19399 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19403 [(set (match_operand:SI 0 "register_operand" "")
19404 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19405 (match_operand:SI 2 "const_int_operand" "")))
19406 (clobber (reg:CC FLAGS_REG))])]
19408 && (INTVAL (operands[2]) == 3
19409 || INTVAL (operands[2]) == 5
19410 || INTVAL (operands[2]) == 9)"
19411 [(set (match_dup 0) (match_dup 1))
19413 (plus:SI (mult:SI (match_dup 0) (match_dup 2))
19415 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19419 [(set (match_operand:DI 0 "register_operand" "")
19420 (mult:DI (match_operand:DI 1 "register_operand" "")
19421 (match_operand:DI 2 "const_int_operand" "")))
19422 (clobber (reg:CC FLAGS_REG))])]
19424 && (INTVAL (operands[2]) == 3
19425 || INTVAL (operands[2]) == 5
19426 || INTVAL (operands[2]) == 9)"
19427 [(set (match_dup 0)
19428 (plus:DI (mult:DI (match_dup 1) (match_dup 2))
19430 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19434 [(set (match_operand:DI 0 "register_operand" "")
19435 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19436 (match_operand:DI 2 "const_int_operand" "")))
19437 (clobber (reg:CC FLAGS_REG))])]
19440 && (INTVAL (operands[2]) == 3
19441 || INTVAL (operands[2]) == 5
19442 || INTVAL (operands[2]) == 9)"
19443 [(set (match_dup 0) (match_dup 1))
19445 (plus:DI (mult:DI (match_dup 0) (match_dup 2))
19447 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19449 ;; Imul $32bit_imm, mem, reg is vector decoded, while
19450 ;; imul $32bit_imm, reg, reg is direct decoded.
19452 [(match_scratch:DI 3 "r")
19453 (parallel [(set (match_operand:DI 0 "register_operand" "")
19454 (mult:DI (match_operand:DI 1 "memory_operand" "")
19455 (match_operand:DI 2 "immediate_operand" "")))
19456 (clobber (reg:CC FLAGS_REG))])]
19457 "TARGET_K8 && !optimize_size
19458 && (GET_CODE (operands[2]) != CONST_INT
19459 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19460 [(set (match_dup 3) (match_dup 1))
19461 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
19462 (clobber (reg:CC FLAGS_REG))])]
19466 [(match_scratch:SI 3 "r")
19467 (parallel [(set (match_operand:SI 0 "register_operand" "")
19468 (mult:SI (match_operand:SI 1 "memory_operand" "")
19469 (match_operand:SI 2 "immediate_operand" "")))
19470 (clobber (reg:CC FLAGS_REG))])]
19471 "TARGET_K8 && !optimize_size
19472 && (GET_CODE (operands[2]) != CONST_INT
19473 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19474 [(set (match_dup 3) (match_dup 1))
19475 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
19476 (clobber (reg:CC FLAGS_REG))])]
19480 [(match_scratch:SI 3 "r")
19481 (parallel [(set (match_operand:DI 0 "register_operand" "")
19483 (mult:SI (match_operand:SI 1 "memory_operand" "")
19484 (match_operand:SI 2 "immediate_operand" ""))))
19485 (clobber (reg:CC FLAGS_REG))])]
19486 "TARGET_K8 && !optimize_size
19487 && (GET_CODE (operands[2]) != CONST_INT
19488 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19489 [(set (match_dup 3) (match_dup 1))
19490 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
19491 (clobber (reg:CC FLAGS_REG))])]
19494 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
19495 ;; Convert it into imul reg, reg
19496 ;; It would be better to force assembler to encode instruction using long
19497 ;; immediate, but there is apparently no way to do so.
19499 [(parallel [(set (match_operand:DI 0 "register_operand" "")
19500 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19501 (match_operand:DI 2 "const_int_operand" "")))
19502 (clobber (reg:CC FLAGS_REG))])
19503 (match_scratch:DI 3 "r")]
19504 "TARGET_K8 && !optimize_size
19505 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19506 [(set (match_dup 3) (match_dup 2))
19507 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
19508 (clobber (reg:CC FLAGS_REG))])]
19510 if (!rtx_equal_p (operands[0], operands[1]))
19511 emit_move_insn (operands[0], operands[1]);
19515 [(parallel [(set (match_operand:SI 0 "register_operand" "")
19516 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19517 (match_operand:SI 2 "const_int_operand" "")))
19518 (clobber (reg:CC FLAGS_REG))])
19519 (match_scratch:SI 3 "r")]
19520 "TARGET_K8 && !optimize_size
19521 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19522 [(set (match_dup 3) (match_dup 2))
19523 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
19524 (clobber (reg:CC FLAGS_REG))])]
19526 if (!rtx_equal_p (operands[0], operands[1]))
19527 emit_move_insn (operands[0], operands[1]);
19531 [(parallel [(set (match_operand:HI 0 "register_operand" "")
19532 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
19533 (match_operand:HI 2 "immediate_operand" "")))
19534 (clobber (reg:CC FLAGS_REG))])
19535 (match_scratch:HI 3 "r")]
19536 "TARGET_K8 && !optimize_size"
19537 [(set (match_dup 3) (match_dup 2))
19538 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
19539 (clobber (reg:CC FLAGS_REG))])]
19541 if (!rtx_equal_p (operands[0], operands[1]))
19542 emit_move_insn (operands[0], operands[1]);
19545 ;; Call-value patterns last so that the wildcard operand does not
19546 ;; disrupt insn-recog's switch tables.
19548 (define_insn "*call_value_pop_0"
19549 [(set (match_operand 0 "" "")
19550 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19551 (match_operand:SI 2 "" "")))
19552 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19553 (match_operand:SI 3 "immediate_operand" "")))]
19556 if (SIBLING_CALL_P (insn))
19559 return "call\t%P1";
19561 [(set_attr "type" "callv")])
19563 (define_insn "*call_value_pop_1"
19564 [(set (match_operand 0 "" "")
19565 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19566 (match_operand:SI 2 "" "")))
19567 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19568 (match_operand:SI 3 "immediate_operand" "i")))]
19571 if (constant_call_address_operand (operands[1], Pmode))
19573 if (SIBLING_CALL_P (insn))
19576 return "call\t%P1";
19578 if (SIBLING_CALL_P (insn))
19581 return "call\t%A1";
19583 [(set_attr "type" "callv")])
19585 (define_insn "*call_value_0"
19586 [(set (match_operand 0 "" "")
19587 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19588 (match_operand:SI 2 "" "")))]
19591 if (SIBLING_CALL_P (insn))
19594 return "call\t%P1";
19596 [(set_attr "type" "callv")])
19598 (define_insn "*call_value_0_rex64"
19599 [(set (match_operand 0 "" "")
19600 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19601 (match_operand:DI 2 "const_int_operand" "")))]
19604 if (SIBLING_CALL_P (insn))
19607 return "call\t%P1";
19609 [(set_attr "type" "callv")])
19611 (define_insn "*call_value_1"
19612 [(set (match_operand 0 "" "")
19613 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19614 (match_operand:SI 2 "" "")))]
19615 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
19617 if (constant_call_address_operand (operands[1], Pmode))
19618 return "call\t%P1";
19619 return "call\t%A1";
19621 [(set_attr "type" "callv")])
19623 (define_insn "*sibcall_value_1"
19624 [(set (match_operand 0 "" "")
19625 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
19626 (match_operand:SI 2 "" "")))]
19627 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
19629 if (constant_call_address_operand (operands[1], Pmode))
19633 [(set_attr "type" "callv")])
19635 (define_insn "*call_value_1_rex64"
19636 [(set (match_operand 0 "" "")
19637 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
19638 (match_operand:DI 2 "" "")))]
19639 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
19641 if (constant_call_address_operand (operands[1], Pmode))
19642 return "call\t%P1";
19643 return "call\t%A1";
19645 [(set_attr "type" "callv")])
19647 (define_insn "*sibcall_value_1_rex64"
19648 [(set (match_operand 0 "" "")
19649 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19650 (match_operand:DI 2 "" "")))]
19651 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19653 [(set_attr "type" "callv")])
19655 (define_insn "*sibcall_value_1_rex64_v"
19656 [(set (match_operand 0 "" "")
19657 (call (mem:QI (reg:DI 40))
19658 (match_operand:DI 1 "" "")))]
19659 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19661 [(set_attr "type" "callv")])
19663 (define_insn "trap"
19664 [(trap_if (const_int 1) (const_int 5))]
19668 ;;; ix86 doesn't have conditional trap instructions, but we fake them
19669 ;;; for the sake of bounds checking. By emitting bounds checks as
19670 ;;; conditional traps rather than as conditional jumps around
19671 ;;; unconditional traps we avoid introducing spurious basic-block
19672 ;;; boundaries and facilitate elimination of redundant checks. In
19673 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
19676 ;;; FIXME: Static branch prediction rules for ix86 are such that
19677 ;;; forward conditional branches predict as untaken. As implemented
19678 ;;; below, pseudo conditional traps violate that rule. We should use
19679 ;;; .pushsection/.popsection to place all of the `int 5's in a special
19680 ;;; section loaded at the end of the text segment and branch forward
19681 ;;; there on bounds-failure, and then jump back immediately (in case
19682 ;;; the system chooses to ignore bounds violations, or to report
19683 ;;; violations and continue execution).
19685 (define_expand "conditional_trap"
19686 [(trap_if (match_operator 0 "comparison_operator"
19687 [(match_dup 2) (const_int 0)])
19688 (match_operand 1 "const_int_operand" ""))]
19691 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
19692 ix86_expand_compare (GET_CODE (operands[0]),
19698 (define_insn "*conditional_trap_1"
19699 [(trap_if (match_operator 0 "comparison_operator"
19700 [(reg FLAGS_REG) (const_int 0)])
19701 (match_operand 1 "const_int_operand" ""))]
19704 operands[2] = gen_label_rtx ();
19705 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
19706 (*targetm.asm_out.internal_label) (asm_out_file, "L",
19707 CODE_LABEL_NUMBER (operands[2]));
19711 ;; Pentium III SIMD instructions.
19713 ;; Moves for SSE/MMX regs.
19715 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
19716 (define_mode_macro MMXMODEI [V8QI V4HI V2SI])
19718 (define_expand "mov<mode>"
19719 [(set (match_operand:MMXMODEI 0 "nonimmediate_operand" "")
19720 (match_operand:MMXMODEI 1 "nonimmediate_operand" ""))]
19723 ix86_expand_vector_move (<MODE>mode, operands);
19727 (define_insn "*mov<mode>_internal_rex64"
19728 [(set (match_operand:MMXMODEI 0 "nonimmediate_operand"
19729 "=rm,r,*y,*y ,m ,*y,Y ,x,x ,m,r,x")
19730 (match_operand:MMXMODEI 1 "vector_move_operand"
19731 "Cr ,m,C ,*ym,*y,Y ,*y,C,xm,x,x,r"))]
19732 "TARGET_64BIT && TARGET_MMX
19733 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19735 movq\t{%1, %0|%0, %1}
19736 movq\t{%1, %0|%0, %1}
19738 movq\t{%1, %0|%0, %1}
19739 movq\t{%1, %0|%0, %1}
19740 movdq2q\t{%1, %0|%0, %1}
19741 movq2dq\t{%1, %0|%0, %1}
19743 movq\t{%1, %0|%0, %1}
19744 movq\t{%1, %0|%0, %1}
19745 movd\t{%1, %0|%0, %1}
19746 movd\t{%1, %0|%0, %1}"
19747 [(set_attr "type" "imov,imov,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov,ssemov,ssemov")
19748 (set_attr "mode" "DI")])
19750 (define_insn "*mov<mode>_internal"
19751 [(set (match_operand:MMXMODEI 0 "nonimmediate_operand"
19752 "=*y,*y ,m ,*y,*Y,*Y,*Y ,m ,*x,*x,*x,m")
19753 (match_operand:MMXMODEI 1 "vector_move_operand"
19754 "C ,*ym,*y,*Y,*y,C ,*Ym,*Y,C ,*x,m ,*x"))]
19756 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19759 movq\t{%1, %0|%0, %1}
19760 movq\t{%1, %0|%0, %1}
19761 movdq2q\t{%1, %0|%0, %1}
19762 movq2dq\t{%1, %0|%0, %1}
19764 movq\t{%1, %0|%0, %1}
19765 movq\t{%1, %0|%0, %1}
19767 movaps\t{%1, %0|%0, %1}
19768 movlps\t{%1, %0|%0, %1}
19769 movlps\t{%1, %0|%0, %1}"
19770 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov")
19771 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF")])
19773 (define_expand "movv2sf"
19774 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
19775 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
19778 ix86_expand_vector_move (V2SFmode, operands);
19782 (define_insn "*movv2sf_internal_rex64"
19783 [(set (match_operand:V2SF 0 "nonimmediate_operand"
19784 "=rm,r,*y ,*y ,m ,*y,Y ,x,x ,m,r,x")
19785 (match_operand:V2SF 1 "vector_move_operand"
19786 "Cr ,m ,C ,*ym,*y,Y ,*y,C,xm,x,x,r"))]
19787 "TARGET_64BIT && TARGET_MMX
19788 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19790 movq\t{%1, %0|%0, %1}
19791 movq\t{%1, %0|%0, %1}
19793 movq\t{%1, %0|%0, %1}
19794 movq\t{%1, %0|%0, %1}
19795 movdq2q\t{%1, %0|%0, %1}
19796 movq2dq\t{%1, %0|%0, %1}
19798 movlps\t{%1, %0|%0, %1}
19799 movlps\t{%1, %0|%0, %1}
19800 movd\t{%1, %0|%0, %1}
19801 movd\t{%1, %0|%0, %1}"
19802 [(set_attr "type" "imov,imov,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov,ssemov,ssemov")
19803 (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V2SF,V2SF,DI,DI")])
19805 (define_insn "*movv2sf_internal"
19806 [(set (match_operand:V2SF 0 "nonimmediate_operand"
19807 "=*y,*y ,m,*y,*Y,*x,*x ,m")
19808 (match_operand:V2SF 1 "vector_move_operand"
19809 "C ,*ym,*y,*Y,*y,C ,*xm,*x"))]
19811 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19814 movq\t{%1, %0|%0, %1}
19815 movq\t{%1, %0|%0, %1}
19816 movdq2q\t{%1, %0|%0, %1}
19817 movq2dq\t{%1, %0|%0, %1}
19819 movlps\t{%1, %0|%0, %1}
19820 movlps\t{%1, %0|%0, %1}"
19821 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
19822 (set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V2SF,V2SF")])
19824 ;; All 8-byte vector modes handled by MMX
19825 (define_mode_macro MMXMODE [V8QI V4HI V2SI V2SF])
19827 (define_expand "movmisalign<mode>"
19828 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
19829 (match_operand:MMXMODE 1 "nonimmediate_operand" ""))]
19832 ix86_expand_vector_move (<MODE>mode, operands);
19836 ;; SSE Strange Moves.
19838 (define_insn "mmx_pmovmskb"
19839 [(set (match_operand:SI 0 "register_operand" "=r")
19840 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
19842 "TARGET_SSE || TARGET_3DNOW_A"
19843 "pmovmskb\t{%1, %0|%0, %1}"
19844 [(set_attr "type" "ssecvt")
19845 (set_attr "mode" "V4SF")])
19848 (define_insn "mmx_maskmovq"
19849 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
19850 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19851 (match_operand:V8QI 2 "register_operand" "y")]
19853 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
19854 ;; @@@ check ordering of operands in intel/nonintel syntax
19855 "maskmovq\t{%2, %1|%1, %2}"
19856 [(set_attr "type" "mmxcvt")
19857 (set_attr "mode" "DI")])
19859 (define_insn "mmx_maskmovq_rex"
19860 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
19861 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19862 (match_operand:V8QI 2 "register_operand" "y")]
19864 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
19865 ;; @@@ check ordering of operands in intel/nonintel syntax
19866 "maskmovq\t{%2, %1|%1, %2}"
19867 [(set_attr "type" "mmxcvt")
19868 (set_attr "mode" "DI")])
19870 (define_insn "sse_movntdi"
19871 [(set (match_operand:DI 0 "memory_operand" "=m")
19872 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
19874 "TARGET_SSE || TARGET_3DNOW_A"
19875 "movntq\t{%1, %0|%0, %1}"
19876 [(set_attr "type" "mmxmov")
19877 (set_attr "mode" "DI")])
19883 (define_insn "addv8qi3"
19884 [(set (match_operand:V8QI 0 "register_operand" "=y")
19885 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
19886 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19888 "paddb\t{%2, %0|%0, %2}"
19889 [(set_attr "type" "mmxadd")
19890 (set_attr "mode" "DI")])
19892 (define_insn "addv4hi3"
19893 [(set (match_operand:V4HI 0 "register_operand" "=y")
19894 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
19895 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19897 "paddw\t{%2, %0|%0, %2}"
19898 [(set_attr "type" "mmxadd")
19899 (set_attr "mode" "DI")])
19901 (define_insn "addv2si3"
19902 [(set (match_operand:V2SI 0 "register_operand" "=y")
19903 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
19904 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19906 "paddd\t{%2, %0|%0, %2}"
19907 [(set_attr "type" "mmxadd")
19908 (set_attr "mode" "DI")])
19910 (define_insn "mmx_adddi3"
19911 [(set (match_operand:DI 0 "register_operand" "=y")
19913 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
19914 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19917 "paddq\t{%2, %0|%0, %2}"
19918 [(set_attr "type" "mmxadd")
19919 (set_attr "mode" "DI")])
19921 (define_insn "ssaddv8qi3"
19922 [(set (match_operand:V8QI 0 "register_operand" "=y")
19923 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
19924 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19926 "paddsb\t{%2, %0|%0, %2}"
19927 [(set_attr "type" "mmxadd")
19928 (set_attr "mode" "DI")])
19930 (define_insn "ssaddv4hi3"
19931 [(set (match_operand:V4HI 0 "register_operand" "=y")
19932 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
19933 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19935 "paddsw\t{%2, %0|%0, %2}"
19936 [(set_attr "type" "mmxadd")
19937 (set_attr "mode" "DI")])
19939 (define_insn "usaddv8qi3"
19940 [(set (match_operand:V8QI 0 "register_operand" "=y")
19941 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
19942 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19944 "paddusb\t{%2, %0|%0, %2}"
19945 [(set_attr "type" "mmxadd")
19946 (set_attr "mode" "DI")])
19948 (define_insn "usaddv4hi3"
19949 [(set (match_operand:V4HI 0 "register_operand" "=y")
19950 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
19951 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19953 "paddusw\t{%2, %0|%0, %2}"
19954 [(set_attr "type" "mmxadd")
19955 (set_attr "mode" "DI")])
19957 (define_insn "subv8qi3"
19958 [(set (match_operand:V8QI 0 "register_operand" "=y")
19959 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19960 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19962 "psubb\t{%2, %0|%0, %2}"
19963 [(set_attr "type" "mmxadd")
19964 (set_attr "mode" "DI")])
19966 (define_insn "subv4hi3"
19967 [(set (match_operand:V4HI 0 "register_operand" "=y")
19968 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19969 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19971 "psubw\t{%2, %0|%0, %2}"
19972 [(set_attr "type" "mmxadd")
19973 (set_attr "mode" "DI")])
19975 (define_insn "subv2si3"
19976 [(set (match_operand:V2SI 0 "register_operand" "=y")
19977 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
19978 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19980 "psubd\t{%2, %0|%0, %2}"
19981 [(set_attr "type" "mmxadd")
19982 (set_attr "mode" "DI")])
19984 (define_insn "mmx_subdi3"
19985 [(set (match_operand:DI 0 "register_operand" "=y")
19987 [(minus:DI (match_operand:DI 1 "register_operand" "0")
19988 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19991 "psubq\t{%2, %0|%0, %2}"
19992 [(set_attr "type" "mmxadd")
19993 (set_attr "mode" "DI")])
19995 (define_insn "sssubv8qi3"
19996 [(set (match_operand:V8QI 0 "register_operand" "=y")
19997 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19998 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20000 "psubsb\t{%2, %0|%0, %2}"
20001 [(set_attr "type" "mmxadd")
20002 (set_attr "mode" "DI")])
20004 (define_insn "sssubv4hi3"
20005 [(set (match_operand:V4HI 0 "register_operand" "=y")
20006 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20007 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20009 "psubsw\t{%2, %0|%0, %2}"
20010 [(set_attr "type" "mmxadd")
20011 (set_attr "mode" "DI")])
20013 (define_insn "ussubv8qi3"
20014 [(set (match_operand:V8QI 0 "register_operand" "=y")
20015 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20016 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20018 "psubusb\t{%2, %0|%0, %2}"
20019 [(set_attr "type" "mmxadd")
20020 (set_attr "mode" "DI")])
20022 (define_insn "ussubv4hi3"
20023 [(set (match_operand:V4HI 0 "register_operand" "=y")
20024 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20025 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20027 "psubusw\t{%2, %0|%0, %2}"
20028 [(set_attr "type" "mmxadd")
20029 (set_attr "mode" "DI")])
20031 (define_insn "mulv4hi3"
20032 [(set (match_operand:V4HI 0 "register_operand" "=y")
20033 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
20034 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20036 "pmullw\t{%2, %0|%0, %2}"
20037 [(set_attr "type" "mmxmul")
20038 (set_attr "mode" "DI")])
20040 (define_insn "smulv4hi3_highpart"
20041 [(set (match_operand:V4HI 0 "register_operand" "=y")
20044 (mult:V4SI (sign_extend:V4SI
20045 (match_operand:V4HI 1 "register_operand" "0"))
20047 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20050 "pmulhw\t{%2, %0|%0, %2}"
20051 [(set_attr "type" "mmxmul")
20052 (set_attr "mode" "DI")])
20054 (define_insn "umulv4hi3_highpart"
20055 [(set (match_operand:V4HI 0 "register_operand" "=y")
20058 (mult:V4SI (zero_extend:V4SI
20059 (match_operand:V4HI 1 "register_operand" "0"))
20061 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20063 "TARGET_SSE || TARGET_3DNOW_A"
20064 "pmulhuw\t{%2, %0|%0, %2}"
20065 [(set_attr "type" "mmxmul")
20066 (set_attr "mode" "DI")])
20068 (define_insn "mmx_pmaddwd"
20069 [(set (match_operand:V2SI 0 "register_operand" "=y")
20073 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
20074 (parallel [(const_int 0) (const_int 2)])))
20076 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
20077 (parallel [(const_int 0) (const_int 2)]))))
20079 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
20080 (parallel [(const_int 1)
20082 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
20083 (parallel [(const_int 1)
20084 (const_int 3)]))))))]
20086 "pmaddwd\t{%2, %0|%0, %2}"
20087 [(set_attr "type" "mmxmul")
20088 (set_attr "mode" "DI")])
20090 (define_insn "sse2_umulsidi3"
20091 [(set (match_operand:DI 0 "register_operand" "=y")
20095 (match_operand:V2SI 1 "register_operand" "0")
20096 (parallel [(const_int 0)])))
20099 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
20100 (parallel [(const_int 0)])))))]
20102 "pmuludq\t{%2, %0|%0, %2}"
20103 [(set_attr "type" "mmxmul")
20104 (set_attr "mode" "DI")])
20107 ;; MMX logical operations
20108 ;; Note we don't want to declare these as regular iordi3 insns to prevent
20109 ;; normal code that also wants to use the FPU from getting broken.
20110 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
20111 (define_insn "mmx_iordi3"
20112 [(set (match_operand:DI 0 "register_operand" "=y")
20114 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
20115 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20118 "por\t{%2, %0|%0, %2}"
20119 [(set_attr "type" "mmxadd")
20120 (set_attr "mode" "DI")])
20122 (define_insn "mmx_xordi3"
20123 [(set (match_operand:DI 0 "register_operand" "=y")
20125 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
20126 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20129 "pxor\t{%2, %0|%0, %2}"
20130 [(set_attr "type" "mmxadd")
20131 (set_attr "mode" "DI")
20132 (set_attr "memory" "none")])
20134 ;; Same as pxor, but don't show input operands so that we don't think
20136 (define_insn "mmx_clrdi"
20137 [(set (match_operand:DI 0 "register_operand" "=y")
20138 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
20140 "pxor\t{%0, %0|%0, %0}"
20141 [(set_attr "type" "mmxadd")
20142 (set_attr "mode" "DI")
20143 (set_attr "memory" "none")])
20145 (define_insn "mmx_anddi3"
20146 [(set (match_operand:DI 0 "register_operand" "=y")
20148 [(and:DI (match_operand:DI 1 "register_operand" "%0")
20149 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20152 "pand\t{%2, %0|%0, %2}"
20153 [(set_attr "type" "mmxadd")
20154 (set_attr "mode" "DI")])
20156 (define_insn "mmx_nanddi3"
20157 [(set (match_operand:DI 0 "register_operand" "=y")
20159 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
20160 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20163 "pandn\t{%2, %0|%0, %2}"
20164 [(set_attr "type" "mmxadd")
20165 (set_attr "mode" "DI")])
20168 ;; MMX unsigned averages/sum of absolute differences
20170 (define_insn "mmx_uavgv8qi3"
20171 [(set (match_operand:V8QI 0 "register_operand" "=y")
20173 (plus:V8QI (plus:V8QI
20174 (match_operand:V8QI 1 "register_operand" "0")
20175 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
20176 (const_vector:V8QI [(const_int 1)
20185 "TARGET_SSE || TARGET_3DNOW_A"
20186 "pavgb\t{%2, %0|%0, %2}"
20187 [(set_attr "type" "mmxshft")
20188 (set_attr "mode" "DI")])
20190 (define_insn "mmx_uavgv4hi3"
20191 [(set (match_operand:V4HI 0 "register_operand" "=y")
20193 (plus:V4HI (plus:V4HI
20194 (match_operand:V4HI 1 "register_operand" "0")
20195 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
20196 (const_vector:V4HI [(const_int 1)
20201 "TARGET_SSE || TARGET_3DNOW_A"
20202 "pavgw\t{%2, %0|%0, %2}"
20203 [(set_attr "type" "mmxshft")
20204 (set_attr "mode" "DI")])
20206 (define_insn "mmx_psadbw"
20207 [(set (match_operand:DI 0 "register_operand" "=y")
20208 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
20209 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20211 "TARGET_SSE || TARGET_3DNOW_A"
20212 "psadbw\t{%2, %0|%0, %2}"
20213 [(set_attr "type" "mmxshft")
20214 (set_attr "mode" "DI")])
20217 ;; MMX insert/extract/shuffle
20219 (define_expand "mmx_pinsrw"
20220 [(set (match_operand:V4HI 0 "register_operand" "")
20222 (match_operand:V4HI 1 "register_operand" "")
20223 (vec_duplicate:V4HI
20224 (match_operand:SI 2 "nonimmediate_operand" ""))
20225 (match_operand:SI 3 "const_0_to_3_operand" "")))]
20226 "TARGET_SSE || TARGET_3DNOW_A"
20228 operands[2] = gen_lowpart (HImode, operands[2]);
20229 operands[3] = GEN_INT (1 << INTVAL (operands[3]));
20232 (define_insn "*mmx_pinsrw"
20233 [(set (match_operand:V4HI 0 "register_operand" "=y")
20235 (match_operand:V4HI 1 "register_operand" "0")
20236 (vec_duplicate:V4HI
20237 (match_operand:HI 2 "nonimmediate_operand" "rm"))
20238 (match_operand:SI 3 "const_pow2_1_to_8_operand" "N")))]
20239 "TARGET_SSE || TARGET_3DNOW_A"
20241 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
20242 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
20244 [(set_attr "type" "mmxcvt")
20245 (set_attr "mode" "DI")])
20247 (define_insn "mmx_pextrw"
20248 [(set (match_operand:SI 0 "register_operand" "=r")
20249 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
20251 [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
20252 "TARGET_SSE || TARGET_3DNOW_A"
20253 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20254 [(set_attr "type" "mmxcvt")
20255 (set_attr "mode" "DI")])
20257 (define_insn "mmx_pshufw"
20258 [(set (match_operand:V4HI 0 "register_operand" "=y")
20259 (unspec:V4HI [(match_operand:V4HI 1 "nonimmediate_operand" "ym")
20260 (match_operand:SI 2 "immediate_operand" "i")]
20262 "TARGET_SSE || TARGET_3DNOW_A"
20263 "pshufw\t{%2, %1, %0|%0, %1, %2}"
20264 [(set_attr "type" "mmxcvt")
20265 (set_attr "mode" "DI")])
20268 ;; MMX mask-generating comparisons
20270 (define_insn "eqv8qi3"
20271 [(set (match_operand:V8QI 0 "register_operand" "=y")
20272 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
20273 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20275 "pcmpeqb\t{%2, %0|%0, %2}"
20276 [(set_attr "type" "mmxcmp")
20277 (set_attr "mode" "DI")])
20279 (define_insn "eqv4hi3"
20280 [(set (match_operand:V4HI 0 "register_operand" "=y")
20281 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
20282 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20284 "pcmpeqw\t{%2, %0|%0, %2}"
20285 [(set_attr "type" "mmxcmp")
20286 (set_attr "mode" "DI")])
20288 (define_insn "eqv2si3"
20289 [(set (match_operand:V2SI 0 "register_operand" "=y")
20290 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
20291 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20293 "pcmpeqd\t{%2, %0|%0, %2}"
20294 [(set_attr "type" "mmxcmp")
20295 (set_attr "mode" "DI")])
20297 (define_insn "gtv8qi3"
20298 [(set (match_operand:V8QI 0 "register_operand" "=y")
20299 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
20300 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20302 "pcmpgtb\t{%2, %0|%0, %2}"
20303 [(set_attr "type" "mmxcmp")
20304 (set_attr "mode" "DI")])
20306 (define_insn "gtv4hi3"
20307 [(set (match_operand:V4HI 0 "register_operand" "=y")
20308 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20309 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20311 "pcmpgtw\t{%2, %0|%0, %2}"
20312 [(set_attr "type" "mmxcmp")
20313 (set_attr "mode" "DI")])
20315 (define_insn "gtv2si3"
20316 [(set (match_operand:V2SI 0 "register_operand" "=y")
20317 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20318 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20320 "pcmpgtd\t{%2, %0|%0, %2}"
20321 [(set_attr "type" "mmxcmp")
20322 (set_attr "mode" "DI")])
20325 ;; MMX max/min insns
20327 (define_insn "umaxv8qi3"
20328 [(set (match_operand:V8QI 0 "register_operand" "=y")
20329 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
20330 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20331 "TARGET_SSE || TARGET_3DNOW_A"
20332 "pmaxub\t{%2, %0|%0, %2}"
20333 [(set_attr "type" "mmxadd")
20334 (set_attr "mode" "DI")])
20336 (define_insn "smaxv4hi3"
20337 [(set (match_operand:V4HI 0 "register_operand" "=y")
20338 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
20339 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20340 "TARGET_SSE || TARGET_3DNOW_A"
20341 "pmaxsw\t{%2, %0|%0, %2}"
20342 [(set_attr "type" "mmxadd")
20343 (set_attr "mode" "DI")])
20345 (define_insn "uminv8qi3"
20346 [(set (match_operand:V8QI 0 "register_operand" "=y")
20347 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
20348 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20349 "TARGET_SSE || TARGET_3DNOW_A"
20350 "pminub\t{%2, %0|%0, %2}"
20351 [(set_attr "type" "mmxadd")
20352 (set_attr "mode" "DI")])
20354 (define_insn "sminv4hi3"
20355 [(set (match_operand:V4HI 0 "register_operand" "=y")
20356 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
20357 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20358 "TARGET_SSE || TARGET_3DNOW_A"
20359 "pminsw\t{%2, %0|%0, %2}"
20360 [(set_attr "type" "mmxadd")
20361 (set_attr "mode" "DI")])
20366 (define_insn "ashrv4hi3"
20367 [(set (match_operand:V4HI 0 "register_operand" "=y")
20368 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20369 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20371 "psraw\t{%2, %0|%0, %2}"
20372 [(set_attr "type" "mmxshft")
20373 (set_attr "mode" "DI")])
20375 (define_insn "ashrv2si3"
20376 [(set (match_operand:V2SI 0 "register_operand" "=y")
20377 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20378 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20380 "psrad\t{%2, %0|%0, %2}"
20381 [(set_attr "type" "mmxshft")
20382 (set_attr "mode" "DI")])
20384 (define_insn "lshrv4hi3"
20385 [(set (match_operand:V4HI 0 "register_operand" "=y")
20386 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20387 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20389 "psrlw\t{%2, %0|%0, %2}"
20390 [(set_attr "type" "mmxshft")
20391 (set_attr "mode" "DI")])
20393 (define_insn "lshrv2si3"
20394 [(set (match_operand:V2SI 0 "register_operand" "=y")
20395 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20396 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20398 "psrld\t{%2, %0|%0, %2}"
20399 [(set_attr "type" "mmxshft")
20400 (set_attr "mode" "DI")])
20402 ;; See logical MMX insns.
20403 (define_insn "mmx_lshrdi3"
20404 [(set (match_operand:DI 0 "register_operand" "=y")
20406 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
20407 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20410 "psrlq\t{%2, %0|%0, %2}"
20411 [(set_attr "type" "mmxshft")
20412 (set_attr "mode" "DI")])
20414 (define_insn "ashlv4hi3"
20415 [(set (match_operand:V4HI 0 "register_operand" "=y")
20416 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
20417 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20419 "psllw\t{%2, %0|%0, %2}"
20420 [(set_attr "type" "mmxshft")
20421 (set_attr "mode" "DI")])
20423 (define_insn "ashlv2si3"
20424 [(set (match_operand:V2SI 0 "register_operand" "=y")
20425 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
20426 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20428 "pslld\t{%2, %0|%0, %2}"
20429 [(set_attr "type" "mmxshft")
20430 (set_attr "mode" "DI")])
20432 ;; See logical MMX insns.
20433 (define_insn "mmx_ashldi3"
20434 [(set (match_operand:DI 0 "register_operand" "=y")
20436 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
20437 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20440 "psllq\t{%2, %0|%0, %2}"
20441 [(set_attr "type" "mmxshft")
20442 (set_attr "mode" "DI")])
20445 ;; MMX pack/unpack insns.
20447 (define_insn "mmx_packsswb"
20448 [(set (match_operand:V8QI 0 "register_operand" "=y")
20450 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20451 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20453 "packsswb\t{%2, %0|%0, %2}"
20454 [(set_attr "type" "mmxshft")
20455 (set_attr "mode" "DI")])
20457 (define_insn "mmx_packssdw"
20458 [(set (match_operand:V4HI 0 "register_operand" "=y")
20460 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
20461 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
20463 "packssdw\t{%2, %0|%0, %2}"
20464 [(set_attr "type" "mmxshft")
20465 (set_attr "mode" "DI")])
20467 (define_insn "mmx_packuswb"
20468 [(set (match_operand:V8QI 0 "register_operand" "=y")
20470 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20471 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20473 "packuswb\t{%2, %0|%0, %2}"
20474 [(set_attr "type" "mmxshft")
20475 (set_attr "mode" "DI")])
20477 (define_insn "mmx_punpckhbw"
20478 [(set (match_operand:V8QI 0 "register_operand" "=y")
20480 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20481 (parallel [(const_int 4)
20489 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20490 (parallel [(const_int 0)
20500 "punpckhbw\t{%2, %0|%0, %2}"
20501 [(set_attr "type" "mmxcvt")
20502 (set_attr "mode" "DI")])
20504 (define_insn "mmx_punpckhwd"
20505 [(set (match_operand:V4HI 0 "register_operand" "=y")
20507 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20508 (parallel [(const_int 0)
20512 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20513 (parallel [(const_int 2)
20519 "punpckhwd\t{%2, %0|%0, %2}"
20520 [(set_attr "type" "mmxcvt")
20521 (set_attr "mode" "DI")])
20523 (define_insn "mmx_punpckhdq"
20524 [(set (match_operand:V2SI 0 "register_operand" "=y")
20526 (match_operand:V2SI 1 "register_operand" "0")
20527 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
20528 (parallel [(const_int 1)
20532 "punpckhdq\t{%2, %0|%0, %2}"
20533 [(set_attr "type" "mmxcvt")
20534 (set_attr "mode" "DI")])
20536 (define_insn "mmx_punpcklbw"
20537 [(set (match_operand:V8QI 0 "register_operand" "=y")
20539 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20540 (parallel [(const_int 0)
20548 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20549 (parallel [(const_int 4)
20559 "punpcklbw\t{%2, %0|%0, %2}"
20560 [(set_attr "type" "mmxcvt")
20561 (set_attr "mode" "DI")])
20563 (define_insn "mmx_punpcklwd"
20564 [(set (match_operand:V4HI 0 "register_operand" "=y")
20566 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20567 (parallel [(const_int 2)
20571 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20572 (parallel [(const_int 0)
20578 "punpcklwd\t{%2, %0|%0, %2}"
20579 [(set_attr "type" "mmxcvt")
20580 (set_attr "mode" "DI")])
20582 (define_insn "mmx_punpckldq"
20583 [(set (match_operand:V2SI 0 "register_operand" "=y")
20585 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
20586 (parallel [(const_int 1)
20588 (match_operand:V2SI 2 "register_operand" "y")
20591 "punpckldq\t{%2, %0|%0, %2}"
20592 [(set_attr "type" "mmxcvt")
20593 (set_attr "mode" "DI")])
20596 ;; Miscellaneous stuff
20598 (define_insn "emms"
20599 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
20600 (clobber (reg:XF 8))
20601 (clobber (reg:XF 9))
20602 (clobber (reg:XF 10))
20603 (clobber (reg:XF 11))
20604 (clobber (reg:XF 12))
20605 (clobber (reg:XF 13))
20606 (clobber (reg:XF 14))
20607 (clobber (reg:XF 15))
20608 (clobber (reg:DI 29))
20609 (clobber (reg:DI 30))
20610 (clobber (reg:DI 31))
20611 (clobber (reg:DI 32))
20612 (clobber (reg:DI 33))
20613 (clobber (reg:DI 34))
20614 (clobber (reg:DI 35))
20615 (clobber (reg:DI 36))]
20618 [(set_attr "type" "mmx")
20619 (set_attr "memory" "unknown")])
20621 (define_insn "ldmxcsr"
20622 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
20626 [(set_attr "type" "sse")
20627 (set_attr "memory" "load")])
20629 (define_insn "stmxcsr"
20630 [(set (match_operand:SI 0 "memory_operand" "=m")
20631 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
20634 [(set_attr "type" "sse")
20635 (set_attr "memory" "store")])
20637 (define_expand "sfence"
20638 [(set (match_dup 0)
20639 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20640 "TARGET_SSE || TARGET_3DNOW_A"
20642 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
20643 MEM_VOLATILE_P (operands[0]) = 1;
20646 (define_insn "*sfence_insn"
20647 [(set (match_operand:BLK 0 "" "")
20648 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20649 "TARGET_SSE || TARGET_3DNOW_A"
20651 [(set_attr "type" "sse")
20652 (set_attr "memory" "unknown")])
20654 (define_expand "sse_prologue_save"
20655 [(parallel [(set (match_operand:BLK 0 "" "")
20656 (unspec:BLK [(reg:DI 21)
20663 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20664 (use (match_operand:DI 1 "register_operand" ""))
20665 (use (match_operand:DI 2 "immediate_operand" ""))
20666 (use (label_ref:DI (match_operand 3 "" "")))])]
20670 (define_insn "*sse_prologue_save_insn"
20671 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
20672 (match_operand:DI 4 "const_int_operand" "n")))
20673 (unspec:BLK [(reg:DI 21)
20680 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20681 (use (match_operand:DI 1 "register_operand" "r"))
20682 (use (match_operand:DI 2 "const_int_operand" "i"))
20683 (use (label_ref:DI (match_operand 3 "" "X")))]
20685 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
20686 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
20690 operands[0] = gen_rtx_MEM (Pmode,
20691 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
20692 output_asm_insn (\"jmp\\t%A1\", operands);
20693 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
20695 operands[4] = adjust_address (operands[0], DImode, i*16);
20696 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
20697 PUT_MODE (operands[4], TImode);
20698 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
20699 output_asm_insn (\"rex\", operands);
20700 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
20702 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
20703 CODE_LABEL_NUMBER (operands[3]));
20707 [(set_attr "type" "other")
20708 (set_attr "length_immediate" "0")
20709 (set_attr "length_address" "0")
20710 (set_attr "length" "135")
20711 (set_attr "memory" "store")
20712 (set_attr "modrm" "0")
20713 (set_attr "mode" "DI")])
20715 ;; 3Dnow! instructions
20717 (define_insn "addv2sf3"
20718 [(set (match_operand:V2SF 0 "register_operand" "=y")
20719 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20720 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20722 "pfadd\\t{%2, %0|%0, %2}"
20723 [(set_attr "type" "mmxadd")
20724 (set_attr "mode" "V2SF")])
20726 (define_insn "subv2sf3"
20727 [(set (match_operand:V2SF 0 "register_operand" "=y")
20728 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20729 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20731 "pfsub\\t{%2, %0|%0, %2}"
20732 [(set_attr "type" "mmxadd")
20733 (set_attr "mode" "V2SF")])
20735 (define_insn "subrv2sf3"
20736 [(set (match_operand:V2SF 0 "register_operand" "=y")
20737 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
20738 (match_operand:V2SF 1 "register_operand" "0")))]
20740 "pfsubr\\t{%2, %0|%0, %2}"
20741 [(set_attr "type" "mmxadd")
20742 (set_attr "mode" "V2SF")])
20744 (define_insn "gtv2sf3"
20745 [(set (match_operand:V2SI 0 "register_operand" "=y")
20746 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
20747 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20749 "pfcmpgt\\t{%2, %0|%0, %2}"
20750 [(set_attr "type" "mmxcmp")
20751 (set_attr "mode" "V2SF")])
20753 (define_insn "gev2sf3"
20754 [(set (match_operand:V2SI 0 "register_operand" "=y")
20755 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
20756 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20758 "pfcmpge\\t{%2, %0|%0, %2}"
20759 [(set_attr "type" "mmxcmp")
20760 (set_attr "mode" "V2SF")])
20762 (define_insn "eqv2sf3"
20763 [(set (match_operand:V2SI 0 "register_operand" "=y")
20764 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
20765 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20767 "pfcmpeq\\t{%2, %0|%0, %2}"
20768 [(set_attr "type" "mmxcmp")
20769 (set_attr "mode" "V2SF")])
20771 (define_insn "pfmaxv2sf3"
20772 [(set (match_operand:V2SF 0 "register_operand" "=y")
20773 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
20774 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20776 "pfmax\\t{%2, %0|%0, %2}"
20777 [(set_attr "type" "mmxadd")
20778 (set_attr "mode" "V2SF")])
20780 (define_insn "pfminv2sf3"
20781 [(set (match_operand:V2SF 0 "register_operand" "=y")
20782 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
20783 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20785 "pfmin\\t{%2, %0|%0, %2}"
20786 [(set_attr "type" "mmxadd")
20787 (set_attr "mode" "V2SF")])
20789 (define_insn "mulv2sf3"
20790 [(set (match_operand:V2SF 0 "register_operand" "=y")
20791 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
20792 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20794 "pfmul\\t{%2, %0|%0, %2}"
20795 [(set_attr "type" "mmxmul")
20796 (set_attr "mode" "V2SF")])
20798 (define_insn "femms"
20799 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
20800 (clobber (reg:XF 8))
20801 (clobber (reg:XF 9))
20802 (clobber (reg:XF 10))
20803 (clobber (reg:XF 11))
20804 (clobber (reg:XF 12))
20805 (clobber (reg:XF 13))
20806 (clobber (reg:XF 14))
20807 (clobber (reg:XF 15))
20808 (clobber (reg:DI 29))
20809 (clobber (reg:DI 30))
20810 (clobber (reg:DI 31))
20811 (clobber (reg:DI 32))
20812 (clobber (reg:DI 33))
20813 (clobber (reg:DI 34))
20814 (clobber (reg:DI 35))
20815 (clobber (reg:DI 36))]
20818 [(set_attr "type" "mmx")
20819 (set_attr "memory" "none")])
20821 (define_insn "pf2id"
20822 [(set (match_operand:V2SI 0 "register_operand" "=y")
20823 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
20825 "pf2id\\t{%1, %0|%0, %1}"
20826 [(set_attr "type" "mmxcvt")
20827 (set_attr "mode" "V2SF")])
20829 (define_insn "pf2iw"
20830 [(set (match_operand:V2SI 0 "register_operand" "=y")
20833 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
20835 "pf2iw\\t{%1, %0|%0, %1}"
20836 [(set_attr "type" "mmxcvt")
20837 (set_attr "mode" "V2SF")])
20839 (define_insn "pfacc"
20840 [(set (match_operand:V2SF 0 "register_operand" "=y")
20843 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20844 (parallel [(const_int 0)]))
20845 (vec_select:SF (match_dup 1)
20846 (parallel [(const_int 1)])))
20848 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20849 (parallel [(const_int 0)]))
20850 (vec_select:SF (match_dup 2)
20851 (parallel [(const_int 1)])))))]
20853 "pfacc\\t{%2, %0|%0, %2}"
20854 [(set_attr "type" "mmxadd")
20855 (set_attr "mode" "V2SF")])
20857 (define_insn "pfnacc"
20858 [(set (match_operand:V2SF 0 "register_operand" "=y")
20861 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20862 (parallel [(const_int 0)]))
20863 (vec_select:SF (match_dup 1)
20864 (parallel [(const_int 1)])))
20866 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20867 (parallel [(const_int 0)]))
20868 (vec_select:SF (match_dup 2)
20869 (parallel [(const_int 1)])))))]
20871 "pfnacc\\t{%2, %0|%0, %2}"
20872 [(set_attr "type" "mmxadd")
20873 (set_attr "mode" "V2SF")])
20875 (define_insn "pfpnacc"
20876 [(set (match_operand:V2SF 0 "register_operand" "=y")
20879 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
20880 (parallel [(const_int 0)]))
20881 (vec_select:SF (match_dup 1)
20882 (parallel [(const_int 1)])))
20884 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
20885 (parallel [(const_int 0)]))
20886 (vec_select:SF (match_dup 2)
20887 (parallel [(const_int 1)])))))]
20889 "pfpnacc\\t{%2, %0|%0, %2}"
20890 [(set_attr "type" "mmxadd")
20891 (set_attr "mode" "V2SF")])
20893 (define_insn "pi2fw"
20894 [(set (match_operand:V2SF 0 "register_operand" "=y")
20899 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
20900 (parallel [(const_int 0)]))))
20903 (vec_select:SI (match_dup 1)
20904 (parallel [(const_int 1)])))))))]
20906 "pi2fw\\t{%1, %0|%0, %1}"
20907 [(set_attr "type" "mmxcvt")
20908 (set_attr "mode" "V2SF")])
20910 (define_insn "floatv2si2"
20911 [(set (match_operand:V2SF 0 "register_operand" "=y")
20912 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
20914 "pi2fd\\t{%1, %0|%0, %1}"
20915 [(set_attr "type" "mmxcvt")
20916 (set_attr "mode" "V2SF")])
20918 ;; This insn is identical to pavgb in operation, but the opcode is
20919 ;; different. To avoid accidentally matching pavgb, use an unspec.
20921 (define_insn "pavgusb"
20922 [(set (match_operand:V8QI 0 "register_operand" "=y")
20924 [(match_operand:V8QI 1 "register_operand" "0")
20925 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20928 "pavgusb\\t{%2, %0|%0, %2}"
20929 [(set_attr "type" "mmxshft")
20930 (set_attr "mode" "TI")])
20932 ;; 3DNow reciprocal and sqrt
20934 (define_insn "pfrcpv2sf2"
20935 [(set (match_operand:V2SF 0 "register_operand" "=y")
20936 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
20939 "pfrcp\\t{%1, %0|%0, %1}"
20940 [(set_attr "type" "mmx")
20941 (set_attr "mode" "TI")])
20943 (define_insn "pfrcpit1v2sf3"
20944 [(set (match_operand:V2SF 0 "register_operand" "=y")
20945 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
20946 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20949 "pfrcpit1\\t{%2, %0|%0, %2}"
20950 [(set_attr "type" "mmx")
20951 (set_attr "mode" "TI")])
20953 (define_insn "pfrcpit2v2sf3"
20954 [(set (match_operand:V2SF 0 "register_operand" "=y")
20955 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
20956 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20959 "pfrcpit2\\t{%2, %0|%0, %2}"
20960 [(set_attr "type" "mmx")
20961 (set_attr "mode" "TI")])
20963 (define_insn "pfrsqrtv2sf2"
20964 [(set (match_operand:V2SF 0 "register_operand" "=y")
20965 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
20968 "pfrsqrt\\t{%1, %0|%0, %1}"
20969 [(set_attr "type" "mmx")
20970 (set_attr "mode" "TI")])
20972 (define_insn "pfrsqit1v2sf3"
20973 [(set (match_operand:V2SF 0 "register_operand" "=y")
20974 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
20975 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20978 "pfrsqit1\\t{%2, %0|%0, %2}"
20979 [(set_attr "type" "mmx")
20980 (set_attr "mode" "TI")])
20982 (define_insn "pmulhrwv4hi3"
20983 [(set (match_operand:V4HI 0 "register_operand" "=y")
20989 (match_operand:V4HI 1 "register_operand" "0"))
20991 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20992 (const_vector:V4SI [(const_int 32768)
20995 (const_int 32768)]))
20998 "pmulhrw\\t{%2, %0|%0, %2}"
20999 [(set_attr "type" "mmxmul")
21000 (set_attr "mode" "TI")])
21002 (define_insn "pswapdv2si2"
21003 [(set (match_operand:V2SI 0 "register_operand" "=y")
21004 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21005 (parallel [(const_int 1) (const_int 0)])))]
21007 "pswapd\\t{%1, %0|%0, %1}"
21008 [(set_attr "type" "mmxcvt")
21009 (set_attr "mode" "TI")])
21011 (define_insn "pswapdv2sf2"
21012 [(set (match_operand:V2SF 0 "register_operand" "=y")
21013 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
21014 (parallel [(const_int 1) (const_int 0)])))]
21016 "pswapd\\t{%1, %0|%0, %1}"
21017 [(set_attr "type" "mmxcvt")
21018 (set_attr "mode" "TI")])
21020 (define_expand "prefetch"
21021 [(prefetch (match_operand 0 "address_operand" "")
21022 (match_operand:SI 1 "const_int_operand" "")
21023 (match_operand:SI 2 "const_int_operand" ""))]
21024 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21026 int rw = INTVAL (operands[1]);
21027 int locality = INTVAL (operands[2]);
21029 if (rw != 0 && rw != 1)
21031 if (locality < 0 || locality > 3)
21033 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
21036 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21037 suported by SSE counterpart or the SSE prefetch is not available
21038 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21040 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21041 operands[2] = GEN_INT (3);
21043 operands[1] = const0_rtx;
21046 (define_insn "*prefetch_sse"
21047 [(prefetch (match_operand:SI 0 "address_operand" "p")
21049 (match_operand:SI 1 "const_int_operand" ""))]
21050 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21052 static const char * const patterns[4] = {
21053 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21056 int locality = INTVAL (operands[1]);
21057 if (locality < 0 || locality > 3)
21060 return patterns[locality];
21062 [(set_attr "type" "sse")
21063 (set_attr "memory" "none")])
21065 (define_insn "*prefetch_sse_rex"
21066 [(prefetch (match_operand:DI 0 "address_operand" "p")
21068 (match_operand:SI 1 "const_int_operand" ""))]
21069 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21071 static const char * const patterns[4] = {
21072 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21075 int locality = INTVAL (operands[1]);
21076 if (locality < 0 || locality > 3)
21079 return patterns[locality];
21081 [(set_attr "type" "sse")
21082 (set_attr "memory" "none")])
21084 (define_insn "*prefetch_3dnow"
21085 [(prefetch (match_operand:SI 0 "address_operand" "p")
21086 (match_operand:SI 1 "const_int_operand" "n")
21088 "TARGET_3DNOW && !TARGET_64BIT"
21090 if (INTVAL (operands[1]) == 0)
21091 return "prefetch\t%a0";
21093 return "prefetchw\t%a0";
21095 [(set_attr "type" "mmx")
21096 (set_attr "memory" "none")])
21098 (define_insn "*prefetch_3dnow_rex"
21099 [(prefetch (match_operand:DI 0 "address_operand" "p")
21100 (match_operand:SI 1 "const_int_operand" "n")
21102 "TARGET_3DNOW && TARGET_64BIT"
21104 if (INTVAL (operands[1]) == 0)
21105 return "prefetch\t%a0";
21107 return "prefetchw\t%a0";
21109 [(set_attr "type" "mmx")
21110 (set_attr "memory" "none")])