1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
54 ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
55 ;; operand 0 is the memory address to scan.
56 ;; operand 1 is a register containing the value to scan for. The mode
57 ;; of the scas opcode will be the same as the mode of this operand.
58 ;; operand 2 is the known alignment of operand 0.
59 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
60 ;; operand 0 is the argument for `sin'.
61 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
62 ;; operand 0 is the argument for `cos'.
63 ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
64 ;; always SImode. operand 0 is the size of the stack allocation.
65 ;; 4 This is the source of a fake SET of the frame pointer which is used to
66 ;; prevent insns referencing it being scheduled across the initial
67 ;; decrement of the stack pointer.
68 ;; 5 This is a `bsf' operation.
69 ;; 6 This is the @GOT offset of a PIC address.
70 ;; 7 This is the @GOTOFF offset of a PIC address.
71 ;; 8 This is a reference to a symbol's @PLT address.
72 ;; 9 This is an `fnstsw' operation.
73 ;; 10 This is a `sahf' operation.
74 ;; 11 This is a `fstcw' operation
75 ;; 12 This is behaviour of add when setting carry flag.
76 ;; 13 This is a `eh_return' placeholder.
78 ;; For SSE/MMX support:
79 ;; 30 This is `fix', guaranteed to be truncating.
80 ;; 31 This is a `emms' operation.
81 ;; 32 This is a `maskmov' operation.
82 ;; 33 This is a `movmsk' operation.
83 ;; 34 This is a `non-temporal' move.
84 ;; 35 This is a `prefetch' operation.
85 ;; 36 This is used to distinguish COMISS from UCOMISS.
86 ;; 37 This is a `ldmxcsr' operation.
87 ;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
88 ;; 39 This is a forced `movups' instruction (rather than whatever movti does)
89 ;; 40 This is a `stmxcsr' operation.
90 ;; 41 This is a `shuffle' operation.
91 ;; 42 This is a `rcp' operation.
92 ;; 43 This is a `rsqsrt' operation.
93 ;; 44 This is a `sfence' operation.
94 ;; 45 This is a noop to prevent excessive combiner cleverness.
96 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
100 ;; Processor type. This attribute must exactly match the processor_type
101 ;; enumeration in i386.h.
102 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
103 (const (symbol_ref "ix86_cpu")))
105 ;; A basic instruction type. Refinements due to arguments to be
106 ;; provided in other attributes.
108 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx"
109 (const_string "other"))
111 ;; Main data type used by the insn
112 (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
113 (const_string "unknown"))
115 ;; Set for i387 operations.
116 (define_attr "i387" ""
117 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch")
121 ;; The (bounding maximum) length of an instruction immediate.
122 (define_attr "length_immediate" ""
123 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
127 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
128 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
129 (eq_attr "type" "imov,test")
130 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
131 (eq_attr "type" "call")
132 (if_then_else (match_operand 0 "constant_call_address_operand" "")
135 (eq_attr "type" "callv")
136 (if_then_else (match_operand 1 "constant_call_address_operand" "")
139 (eq_attr "type" "ibr")
140 (if_then_else (and (ge (minus (match_dup 0) (pc))
142 (lt (minus (match_dup 0) (pc))
147 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
149 ;; The (bounding maximum) length of an instruction address.
150 (define_attr "length_address" ""
151 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
153 (and (eq_attr "type" "call")
154 (match_operand 1 "constant_call_address_operand" ""))
156 (and (eq_attr "type" "callv")
157 (match_operand 1 "constant_call_address_operand" ""))
160 (symbol_ref "ix86_attr_length_address_default (insn)")))
162 ;; Set when length prefix is used.
163 (define_attr "prefix_data16" ""
164 (if_then_else (eq_attr "mode" "HI")
168 ;; Set when string REP prefix is used.
169 (define_attr "prefix_rep" "" (const_int 0))
171 ;; Set when 0f opcode prefix is used.
172 (define_attr "prefix_0f" ""
173 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
177 ;; Set when modrm byte is used.
178 (define_attr "modrm" ""
179 (cond [(eq_attr "type" "str,cld")
183 (and (eq_attr "type" "incdec")
184 (ior (match_operand:SI 1 "register_operand" "")
185 (match_operand:HI 1 "register_operand" "")))
187 (and (eq_attr "type" "push")
188 (not (match_operand 1 "memory_operand" "")))
190 (and (eq_attr "type" "pop")
191 (not (match_operand 0 "memory_operand" "")))
193 (and (eq_attr "type" "imov")
194 (and (match_operand 0 "register_operand" "")
195 (match_operand 1 "immediate_operand" "")))
200 ;; The (bounding maximum) length of an instruction in bytes.
201 (define_attr "length" ""
202 (cond [(eq_attr "type" "other,multi")
205 (plus (plus (attr "modrm")
206 (plus (attr "prefix_0f")
209 (plus (attr "prefix_rep")
210 (plus (attr "prefix_data16")
211 (plus (attr "length_immediate")
212 (attr "length_address")))))))
214 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
215 ;; `store' if there is a simple memory reference therein, or `unknown'
216 ;; if the instruction is complex.
218 (define_attr "memory" "none,load,store,both,unknown"
219 (cond [(eq_attr "type" "other,multi,str")
220 (const_string "unknown")
221 (eq_attr "type" "lea,fcmov,fpspc,cld")
222 (const_string "none")
223 (eq_attr "type" "push")
224 (if_then_else (match_operand 1 "memory_operand" "")
225 (const_string "both")
226 (const_string "store"))
227 (eq_attr "type" "pop,setcc")
228 (if_then_else (match_operand 0 "memory_operand" "")
229 (const_string "both")
230 (const_string "load"))
231 (eq_attr "type" "icmp,test")
232 (if_then_else (ior (match_operand 0 "memory_operand" "")
233 (match_operand 1 "memory_operand" ""))
234 (const_string "load")
235 (const_string "none"))
236 (eq_attr "type" "ibr")
237 (if_then_else (match_operand 0 "memory_operand" "")
238 (const_string "load")
239 (const_string "none"))
240 (eq_attr "type" "call")
241 (if_then_else (match_operand 0 "constant_call_address_operand" "")
242 (const_string "none")
243 (const_string "load"))
244 (eq_attr "type" "callv")
245 (if_then_else (match_operand 1 "constant_call_address_operand" "")
246 (const_string "none")
247 (const_string "load"))
248 (and (eq_attr "type" "alu1,negnot")
249 (match_operand 1 "memory_operand" ""))
250 (const_string "both")
251 (and (match_operand 0 "memory_operand" "")
252 (match_operand 1 "memory_operand" ""))
253 (const_string "both")
254 (match_operand 0 "memory_operand" "")
255 (const_string "store")
256 (match_operand 1 "memory_operand" "")
257 (const_string "load")
258 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
259 (match_operand 2 "memory_operand" ""))
260 (const_string "load")
261 (and (eq_attr "type" "icmov")
262 (match_operand 3 "memory_operand" ""))
263 (const_string "load")
265 (const_string "none")))
267 ;; Indicates if an instruction has both an immediate and a displacement.
269 (define_attr "imm_disp" "false,true,unknown"
270 (cond [(eq_attr "type" "other,multi")
271 (const_string "unknown")
272 (and (eq_attr "type" "icmp,test,imov")
273 (and (match_operand 0 "memory_displacement_operand" "")
274 (match_operand 1 "immediate_operand" "")))
275 (const_string "true")
276 (and (eq_attr "type" "alu,ishift,imul,idiv")
277 (and (match_operand 0 "memory_displacement_operand" "")
278 (match_operand 2 "immediate_operand" "")))
279 (const_string "true")
281 (const_string "false")))
283 ;; Indicates if an FP operation has an integer source.
285 (define_attr "fp_int_src" "false,true"
286 (const_string "false"))
288 ;; Describe a user's asm statement.
289 (define_asm_attributes
290 [(set_attr "length" "128")
291 (set_attr "type" "multi")])
293 ;; Pentium Scheduling
295 ;; The Pentium is an in-order core with two integer pipelines.
297 ;; True for insns that behave like prefixed insns on the Pentium.
298 (define_attr "pent_prefix" "false,true"
299 (if_then_else (ior (eq_attr "prefix_0f" "1")
300 (ior (eq_attr "prefix_data16" "1")
301 (eq_attr "prefix_rep" "1")))
302 (const_string "true")
303 (const_string "false")))
305 ;; Categorize how an instruction slots.
307 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
308 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
309 ;; rules, because it results in noticeably better code on non-MMX Pentium
310 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
311 ;; common, so the scheduler usualy has a non-prefixed insn to pair).
313 (define_attr "pent_pair" "uv,pu,pv,np"
314 (cond [(eq_attr "imm_disp" "true")
316 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
317 (and (eq_attr "type" "pop,push")
318 (eq_attr "memory" "!both")))
319 (if_then_else (eq_attr "pent_prefix" "true")
322 (eq_attr "type" "ibr")
324 (and (eq_attr "type" "ishift")
325 (match_operand 2 "const_int_operand" ""))
327 (and (eq_attr "type" "call")
328 (match_operand 0 "constant_call_address_operand" ""))
330 (and (eq_attr "type" "callv")
331 (match_operand 1 "constant_call_address_operand" ""))
334 (const_string "np")))
336 ;; Rough readiness numbers. Fine tuning happens in i386.c.
338 ;; u describes pipe U
339 ;; v describes pipe V
340 ;; uv describes either pipe U or V for those that can issue to either
341 ;; np describes not paring
343 ;; fpm describes fp insns of different types are not pipelined.
345 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
347 (define_function_unit "pent_np" 1 0
348 (and (eq_attr "cpu" "pentium")
349 (eq_attr "type" "imul"))
352 (define_function_unit "pent_mul" 1 1
353 (and (eq_attr "cpu" "pentium")
354 (eq_attr "type" "imul"))
357 ;; Rep movs takes minimally 12 cycles.
358 (define_function_unit "pent_np" 1 0
359 (and (eq_attr "cpu" "pentium")
360 (eq_attr "type" "str"))
363 ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
364 (define_function_unit "pent_np" 1 0
365 (and (eq_attr "cpu" "pentium")
366 (eq_attr "type" "idiv"))
369 ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
370 ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
371 ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
372 ; The integer <-> fp conversion is not modeled correctly. Fild behaves
373 ; like normal fp operation and fist takes 6 cycles.
375 (define_function_unit "fpu" 1 0
376 (and (eq_attr "cpu" "pentium")
377 (and (eq_attr "type" "fmov")
378 (and (eq_attr "memory" "load,store")
379 (eq_attr "mode" "XF"))))
382 (define_function_unit "pent_np" 1 0
383 (and (eq_attr "cpu" "pentium")
384 (and (eq_attr "type" "fmov")
385 (and (eq_attr "memory" "load,store")
386 (eq_attr "mode" "XF"))))
389 (define_function_unit "fpu" 1 0
390 (and (eq_attr "cpu" "pentium")
391 (and (eq_attr "type" "fmov")
392 (ior (match_operand 1 "immediate_operand" "")
393 (eq_attr "memory" "store"))))
396 (define_function_unit "pent_np" 1 0
397 (and (eq_attr "cpu" "pentium")
398 (and (eq_attr "type" "fmov")
399 (ior (match_operand 1 "immediate_operand" "")
400 (eq_attr "memory" "store"))))
403 (define_function_unit "pent_np" 1 0
404 (and (eq_attr "cpu" "pentium")
405 (eq_attr "type" "cld"))
408 (define_function_unit "fpu" 1 0
409 (and (eq_attr "cpu" "pentium")
410 (and (eq_attr "type" "fmov")
411 (eq_attr "memory" "none,load")))
414 ; Read/Modify/Write instructions usually take 3 cycles.
415 (define_function_unit "pent_u" 1 0
416 (and (eq_attr "cpu" "pentium")
417 (and (eq_attr "type" "alu,alu1,ishift")
418 (and (eq_attr "pent_pair" "pu")
419 (eq_attr "memory" "both"))))
422 (define_function_unit "pent_uv" 2 0
423 (and (eq_attr "cpu" "pentium")
424 (and (eq_attr "type" "alu,alu1,ishift")
425 (and (eq_attr "pent_pair" "!np")
426 (eq_attr "memory" "both"))))
429 (define_function_unit "pent_np" 1 0
430 (and (eq_attr "cpu" "pentium")
431 (and (eq_attr "type" "alu,alu1,negnot,ishift")
432 (and (eq_attr "pent_pair" "np")
433 (eq_attr "memory" "both"))))
436 ; Read/Modify or Modify/Write instructions usually take 2 cycles.
437 (define_function_unit "pent_u" 1 0
438 (and (eq_attr "cpu" "pentium")
439 (and (eq_attr "type" "alu,ishift")
440 (and (eq_attr "pent_pair" "pu")
441 (eq_attr "memory" "load,store"))))
444 (define_function_unit "pent_uv" 2 0
445 (and (eq_attr "cpu" "pentium")
446 (and (eq_attr "type" "alu,ishift")
447 (and (eq_attr "pent_pair" "!np")
448 (eq_attr "memory" "load,store"))))
451 (define_function_unit "pent_np" 1 0
452 (and (eq_attr "cpu" "pentium")
453 (and (eq_attr "type" "alu,ishift")
454 (and (eq_attr "pent_pair" "np")
455 (eq_attr "memory" "load,store"))))
458 ; Insns w/o memory operands and move instructions usually take one cycle.
459 (define_function_unit "pent_u" 1 0
460 (and (eq_attr "cpu" "pentium")
461 (eq_attr "pent_pair" "pu"))
464 (define_function_unit "pent_v" 1 0
465 (and (eq_attr "cpu" "pentium")
466 (eq_attr "pent_pair" "pv"))
469 (define_function_unit "pent_uv" 2 0
470 (and (eq_attr "cpu" "pentium")
471 (eq_attr "pent_pair" "!np"))
474 (define_function_unit "pent_np" 1 0
475 (and (eq_attr "cpu" "pentium")
476 (eq_attr "pent_pair" "np"))
479 ; Pairable insns only conflict with other non-pairable insns.
480 (define_function_unit "pent_np" 1 0
481 (and (eq_attr "cpu" "pentium")
482 (and (eq_attr "type" "alu,alu1,ishift")
483 (and (eq_attr "pent_pair" "!np")
484 (eq_attr "memory" "both"))))
486 [(eq_attr "pent_pair" "np")])
488 (define_function_unit "pent_np" 1 0
489 (and (eq_attr "cpu" "pentium")
490 (and (eq_attr "type" "alu,alu1,ishift")
491 (and (eq_attr "pent_pair" "!np")
492 (eq_attr "memory" "load,store"))))
494 [(eq_attr "pent_pair" "np")])
496 (define_function_unit "pent_np" 1 0
497 (and (eq_attr "cpu" "pentium")
498 (eq_attr "pent_pair" "!np"))
500 [(eq_attr "pent_pair" "np")])
502 ; Floating point instructions usually blocks cycle longer when combined with
503 ; integer instructions, because of the inpaired fxch instruction.
504 (define_function_unit "pent_np" 1 0
505 (and (eq_attr "cpu" "pentium")
506 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp"))
508 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp")])
510 (define_function_unit "fpu" 1 0
511 (and (eq_attr "cpu" "pentium")
512 (eq_attr "type" "fcmp,fxch,fsgn"))
515 ; Addition takes 3 cycles; assume other random cruft does as well.
516 ; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
517 (define_function_unit "fpu" 1 0
518 (and (eq_attr "cpu" "pentium")
519 (eq_attr "type" "fop,fop1"))
522 ; Multiplication takes 3 cycles and is only half pipelined.
523 (define_function_unit "fpu" 1 0
524 (and (eq_attr "cpu" "pentium")
525 (eq_attr "type" "fmul"))
528 (define_function_unit "pent_mul" 1 1
529 (and (eq_attr "cpu" "pentium")
530 (eq_attr "type" "fmul"))
533 ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
534 ; They can overlap with integer insns. Only the last two cycles can overlap
535 ; with other fp insns. Only fsin/fcos can overlap with multiplies.
536 ; Only last two cycles of fsin/fcos can overlap with other instructions.
537 (define_function_unit "fpu" 1 0
538 (and (eq_attr "cpu" "pentium")
539 (eq_attr "type" "fdiv"))
542 (define_function_unit "pent_mul" 1 1
543 (and (eq_attr "cpu" "pentium")
544 (eq_attr "type" "fdiv"))
547 (define_function_unit "fpu" 1 0
548 (and (eq_attr "cpu" "pentium")
549 (eq_attr "type" "fpspc"))
552 (define_function_unit "pent_mul" 1 1
553 (and (eq_attr "cpu" "pentium")
554 (eq_attr "type" "fpspc"))
557 ;; Pentium Pro/PII Scheduling
559 ;; The PPro has an out-of-order core, but the instruction decoders are
560 ;; naturally in-order and asymmetric. We get best performance by scheduling
561 ;; for the decoders, for in doing so we give the oo execution unit the
564 ;; Categorize how many uops an ia32 instruction evaluates to:
565 ;; one -- an instruction with 1 uop can be decoded by any of the
567 ;; few -- an instruction with 1 to 4 uops can be decoded only by
569 ;; many -- a complex instruction may take an unspecified number of
570 ;; cycles to decode in decoder 0.
572 (define_attr "ppro_uops" "one,few,many"
573 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
574 (const_string "many")
575 (eq_attr "type" "icmov,fcmov,str,cld")
577 (eq_attr "type" "imov")
578 (if_then_else (eq_attr "memory" "store,both")
580 (const_string "one"))
581 (eq_attr "memory" "!none")
584 (const_string "one")))
586 ;; Rough readiness numbers. Fine tuning happens in i386.c.
588 ;; p0 describes port 0.
589 ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
590 ;; p2 describes port 2 for loads.
591 ;; p34 describes ports 3 and 4 for stores.
592 ;; fpu describes the fpu accessed via port 0.
593 ;; ??? It is less than clear if there are separate fadd and fmul units
594 ;; that could operate in parallel.
596 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
598 (define_function_unit "ppro_p0" 1 0
599 (and (eq_attr "cpu" "pentiumpro")
600 (eq_attr "type" "ishift,lea,ibr,cld"))
603 (define_function_unit "ppro_p0" 1 0
604 (and (eq_attr "cpu" "pentiumpro")
605 (eq_attr "type" "imul"))
608 ;; ??? Does the divider lock out the pipe while it works,
609 ;; or is there a disconnected unit?
610 (define_function_unit "ppro_p0" 1 0
611 (and (eq_attr "cpu" "pentiumpro")
612 (eq_attr "type" "idiv"))
615 (define_function_unit "ppro_p0" 1 0
616 (and (eq_attr "cpu" "pentiumpro")
617 (eq_attr "type" "fop,fop1,fsgn"))
620 (define_function_unit "ppro_p0" 1 0
621 (and (eq_attr "cpu" "pentiumpro")
622 (eq_attr "type" "fcmov"))
625 (define_function_unit "ppro_p0" 1 0
626 (and (eq_attr "cpu" "pentiumpro")
627 (eq_attr "type" "fcmp"))
630 (define_function_unit "ppro_p0" 1 0
631 (and (eq_attr "cpu" "pentiumpro")
632 (eq_attr "type" "fmov"))
635 (define_function_unit "ppro_p0" 1 0
636 (and (eq_attr "cpu" "pentiumpro")
637 (eq_attr "type" "fmul"))
640 (define_function_unit "ppro_p0" 1 0
641 (and (eq_attr "cpu" "pentiumpro")
642 (eq_attr "type" "fdiv,fpspc"))
645 (define_function_unit "ppro_p01" 2 0
646 (and (eq_attr "cpu" "pentiumpro")
647 (eq_attr "type" "!imov,fmov"))
650 (define_function_unit "ppro_p01" 2 0
651 (and (and (eq_attr "cpu" "pentiumpro")
652 (eq_attr "type" "imov,fmov"))
653 (eq_attr "memory" "none"))
656 (define_function_unit "ppro_p2" 1 0
657 (and (eq_attr "cpu" "pentiumpro")
658 (ior (eq_attr "type" "pop")
659 (eq_attr "memory" "load,both")))
662 (define_function_unit "ppro_p34" 1 0
663 (and (eq_attr "cpu" "pentiumpro")
664 (ior (eq_attr "type" "push")
665 (eq_attr "memory" "store,both")))
668 (define_function_unit "fpu" 1 0
669 (and (eq_attr "cpu" "pentiumpro")
670 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov"))
673 (define_function_unit "fpu" 1 0
674 (and (eq_attr "cpu" "pentiumpro")
675 (eq_attr "type" "fmul"))
678 (define_function_unit "fpu" 1 0
679 (and (eq_attr "cpu" "pentiumpro")
680 (eq_attr "type" "fdiv,fpspc"))
683 ;; imul uses the fpu. ??? does it have the same throughput as fmul?
684 (define_function_unit "fpu" 1 0
685 (and (eq_attr "cpu" "pentiumpro")
686 (eq_attr "type" "imul"))
689 ;; AMD K6/K6-2 Scheduling
691 ;; The K6 has similar architecture to PPro. Important difference is, that
692 ;; there are only two decoders and they seems to be much slower than execution
693 ;; units. So we have to pay much more attention to proper decoding for
694 ;; schedulers. We share most of scheduler code for PPro in i386.c
696 ;; The fp unit is not pipelined and do one operation per two cycles including
699 ;; alu describes both ALU units (ALU-X and ALU-Y).
700 ;; alux describes X alu unit
701 ;; fpu describes FPU unit
702 ;; load describes load unit.
703 ;; branch describes branch unit.
704 ;; store decsribes store unit. This unit is not modelled completely and only
705 ;; used to model lea operation. Otherwise it lie outside of the critical
708 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
710 ;; The decoder specification is in the PPro section above!
712 ;; Shift instructions and certain arithmetic are issued only to X pipe.
713 (define_function_unit "k6_alux" 1 0
714 (and (eq_attr "cpu" "k6")
715 (eq_attr "type" "ishift,alu1,negnot,cld"))
718 ;; The QI mode arithmetic is issued to X pipe only.
719 (define_function_unit "k6_alux" 1 0
720 (and (eq_attr "cpu" "k6")
721 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
722 (match_operand:QI 0 "general_operand" "")))
725 (define_function_unit "k6_alu" 2 0
726 (and (eq_attr "cpu" "k6")
727 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
730 (define_function_unit "k6_alu" 2 0
731 (and (eq_attr "cpu" "k6")
732 (and (eq_attr "type" "imov")
733 (eq_attr "memory" "none")))
736 (define_function_unit "k6_branch" 1 0
737 (and (eq_attr "cpu" "k6")
738 (eq_attr "type" "call,callv,ibr"))
741 ;; Load unit have two cycle latency, but we take care for it in adjust_cost
742 (define_function_unit "k6_load" 1 0
743 (and (eq_attr "cpu" "k6")
744 (ior (eq_attr "type" "pop")
745 (eq_attr "memory" "load,both")))
748 (define_function_unit "k6_load" 1 0
749 (and (eq_attr "cpu" "k6")
750 (and (eq_attr "type" "str")
751 (eq_attr "memory" "load,both")))
754 ;; Lea have two instructions, so latency is probably 2
755 (define_function_unit "k6_store" 1 0
756 (and (eq_attr "cpu" "k6")
757 (eq_attr "type" "lea"))
760 (define_function_unit "k6_store" 1 0
761 (and (eq_attr "cpu" "k6")
762 (eq_attr "type" "str"))
765 (define_function_unit "k6_store" 1 0
766 (and (eq_attr "cpu" "k6")
767 (ior (eq_attr "type" "push")
768 (eq_attr "memory" "store,both")))
771 (define_function_unit "k6_fpu" 1 1
772 (and (eq_attr "cpu" "k6")
773 (eq_attr "type" "fop,fop1,fmov,fcmp"))
776 (define_function_unit "k6_fpu" 1 1
777 (and (eq_attr "cpu" "k6")
778 (eq_attr "type" "fmul"))
782 (define_function_unit "k6_fpu" 1 1
783 (and (eq_attr "cpu" "k6")
784 (eq_attr "type" "fdiv,fpspc"))
787 (define_function_unit "k6_alu" 2 0
788 (and (eq_attr "cpu" "k6")
789 (eq_attr "type" "imul"))
792 (define_function_unit "k6_alux" 1 0
793 (and (eq_attr "cpu" "k6")
794 (eq_attr "type" "imul"))
798 (define_function_unit "k6_alu" 2 0
799 (and (eq_attr "cpu" "k6")
800 (eq_attr "type" "idiv"))
803 (define_function_unit "k6_alux" 1 0
804 (and (eq_attr "cpu" "k6")
805 (eq_attr "type" "idiv"))
808 ;; AMD Athlon Scheduling
810 ;; The Athlon does contain three pipelined FP units, three integer units and
811 ;; three address generation units.
813 ;; The predecode logic is determining boundaries of instructions in the 64
814 ;; byte cache line. So the cache line straddling problem of K6 might be issue
815 ;; here as well, but it is not noted in the documentation.
817 ;; Three DirectPath instructions decoders and only one VectorPath decoder
818 ;; is available. They can decode three DirectPath instructions or one VectorPath
819 ;; instruction per cycle.
820 ;; Decoded macro instructions are then passed to 72 entry instruction control
822 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
824 ;; The load/store queue unit is not attached to the schedulers but
825 ;; communicates with all the execution units seperately instead.
827 (define_attr "athlon_decode" "direct,vector"
828 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
829 (const_string "vector")
830 (and (eq_attr "type" "push")
831 (match_operand 1 "memory_operand" ""))
832 (const_string "vector")
833 (and (eq_attr "type" "fmov")
834 (and (eq_attr "memory" "load,store")
835 (eq_attr "mode" "XF")))
836 (const_string "vector")]
837 (const_string "direct")))
839 (define_function_unit "athlon_vectordec" 1 0
840 (and (eq_attr "cpu" "athlon")
841 (eq_attr "athlon_decode" "vector"))
844 (define_function_unit "athlon_directdec" 3 0
845 (and (eq_attr "cpu" "athlon")
846 (eq_attr "athlon_decode" "direct"))
849 (define_function_unit "athlon_vectordec" 1 0
850 (and (eq_attr "cpu" "athlon")
851 (eq_attr "athlon_decode" "direct"))
852 1 1 [(eq_attr "athlon_decode" "vector")])
854 (define_function_unit "athlon_ieu" 3 0
855 (and (eq_attr "cpu" "athlon")
856 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
859 (define_function_unit "athlon_ieu" 3 0
860 (and (eq_attr "cpu" "athlon")
861 (eq_attr "type" "str"))
864 (define_function_unit "athlon_ieu" 3 0
865 (and (eq_attr "cpu" "athlon")
866 (eq_attr "type" "imul"))
869 (define_function_unit "athlon_ieu" 3 0
870 (and (eq_attr "cpu" "athlon")
871 (eq_attr "type" "idiv"))
874 (define_function_unit "athlon_muldiv" 1 0
875 (and (eq_attr "cpu" "athlon")
876 (eq_attr "type" "imul"))
879 (define_function_unit "athlon_muldiv" 1 0
880 (and (eq_attr "cpu" "athlon")
881 (eq_attr "type" "idiv"))
884 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
885 (cond [(eq_attr "type" "fop,fop1,fcmp")
887 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
889 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
890 (const_string "store")
891 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
893 (and (eq_attr "type" "fmov")
894 (ior (match_operand:SI 1 "register_operand" "")
895 (match_operand 1 "immediate_operand" "")))
896 (const_string "store")
897 (eq_attr "type" "fmov")
898 (const_string "muladd")]
899 (const_string "none")))
901 ;; We use latencies 1 for definitions. This is OK to model colisions
902 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
904 ;; fsin, fcos: 96-192
906 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
907 (define_function_unit "athlon_fp" 3 0
908 (and (eq_attr "cpu" "athlon")
909 (eq_attr "type" "fpspc"))
912 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
913 (define_function_unit "athlon_fp" 3 0
914 (and (eq_attr "cpu" "athlon")
915 (eq_attr "type" "fdiv"))
918 (define_function_unit "athlon_fp" 3 0
919 (and (eq_attr "cpu" "athlon")
920 (eq_attr "type" "fop,fop1,fmul"))
923 ;; XFmode loads are slow.
924 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
925 ;; there are no dependent instructions.
927 (define_function_unit "athlon_fp" 3 0
928 (and (eq_attr "cpu" "athlon")
929 (and (eq_attr "type" "fmov")
930 (and (eq_attr "memory" "load")
931 (eq_attr "mode" "XF"))))
934 (define_function_unit "athlon_fp" 3 0
935 (and (eq_attr "cpu" "athlon")
936 (eq_attr "type" "fmov,fsgn"))
939 ;; fcmp and ftst instructions
940 (define_function_unit "athlon_fp" 3 0
941 (and (eq_attr "cpu" "athlon")
942 (and (eq_attr "type" "fcmp")
943 (eq_attr "athlon_decode" "direct")))
946 ;; fcmpi instructions.
947 (define_function_unit "athlon_fp" 3 0
948 (and (eq_attr "cpu" "athlon")
949 (and (eq_attr "type" "fcmp")
950 (eq_attr "athlon_decode" "vector")))
953 (define_function_unit "athlon_fp" 3 0
954 (and (eq_attr "cpu" "athlon")
955 (eq_attr "type" "fcmov"))
958 (define_function_unit "athlon_fp_mul" 1 0
959 (and (eq_attr "cpu" "athlon")
960 (eq_attr "athlon_fpunits" "mul"))
963 (define_function_unit "athlon_fp_add" 1 0
964 (and (eq_attr "cpu" "athlon")
965 (eq_attr "athlon_fpunits" "add"))
968 (define_function_unit "athlon_fp_muladd" 2 0
969 (and (eq_attr "cpu" "athlon")
970 (eq_attr "athlon_fpunits" "muladd,mul,add"))
973 (define_function_unit "athlon_fp_store" 1 0
974 (and (eq_attr "cpu" "athlon")
975 (eq_attr "athlon_fpunits" "store"))
978 ;; We don't need to model the Adress Generation Unit, since we don't model
979 ;; the re-order buffer yet and thus we never schedule more than three operations
980 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
981 ;; decoders independently on the functional units.
983 ;(define_function_unit "athlon_agu" 3 0
984 ; (and (eq_attr "cpu" "athlon")
985 ; (and (eq_attr "memory" "!none")
986 ; (eq_attr "athlon_fpunits" "none")))
989 ;; Model load unit to avoid too long sequences of loads. We don't need to
990 ;; model store queue, since it is hardly going to be bottleneck.
992 (define_function_unit "athlon_load" 2 0
993 (and (eq_attr "cpu" "athlon")
994 (eq_attr "memory" "load,both"))
998 ;; Compare instructions.
1000 ;; All compare insns have expanders that save the operands away without
1001 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
1002 ;; after the cmp) will actually emit the cmpM.
1004 (define_expand "cmpdi"
1006 (compare:CC (match_operand:DI 0 "x86_64_general_operand" "")
1007 (match_operand:DI 1 "x86_64_general_operand" "")))]
1011 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1012 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1013 operands[0] = force_reg (DImode, operands[0]);
1014 ix86_compare_op0 = operands[0];
1015 ix86_compare_op1 = operands[1];
1019 (define_expand "cmpsi"
1021 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
1022 (match_operand:SI 1 "general_operand" "")))]
1026 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1027 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1028 operands[0] = force_reg (SImode, operands[0]);
1029 ix86_compare_op0 = operands[0];
1030 ix86_compare_op1 = operands[1];
1034 (define_expand "cmphi"
1036 (compare:CC (match_operand:HI 0 "general_operand" "")
1037 (match_operand:HI 1 "general_operand" "")))]
1041 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1042 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1043 operands[0] = force_reg (HImode, operands[0]);
1044 ix86_compare_op0 = operands[0];
1045 ix86_compare_op1 = operands[1];
1049 (define_expand "cmpqi"
1051 (compare:CC (match_operand:QI 0 "general_operand" "")
1052 (match_operand:QI 1 "general_operand" "")))]
1053 "TARGET_QIMODE_MATH"
1056 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1057 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1058 operands[0] = force_reg (QImode, operands[0]);
1059 ix86_compare_op0 = operands[0];
1060 ix86_compare_op1 = operands[1];
1064 (define_insn "cmpdi_ccno_1_rex64"
1066 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
1067 (match_operand:DI 1 "const0_operand" "n,n")))]
1068 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
1070 test{q}\\t{%0, %0|%0, %0}
1071 cmp{q}\\t{%1, %0|%0, %1}"
1072 [(set_attr "type" "test,icmp")
1073 (set_attr "length_immediate" "0,1")
1074 (set_attr "mode" "DI")])
1076 (define_insn "*cmpdi_minus_1_rex64"
1078 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
1079 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
1081 "ix86_match_ccmode (insn, CCGOCmode)"
1082 "cmp{q}\\t{%1, %0|%0, %1}"
1083 [(set_attr "type" "icmp")
1084 (set_attr "mode" "DI")])
1086 (define_expand "cmpdi_1_rex64"
1088 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
1089 (match_operand:DI 1 "general_operand" "")))]
1093 (define_insn "cmpdi_1_insn_rex64"
1095 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
1096 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
1097 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1098 "cmp{q}\\t{%1, %0|%0, %1}"
1099 [(set_attr "type" "icmp")
1100 (set_attr "mode" "DI")])
1103 (define_insn "*cmpsi_ccno_1"
1105 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
1106 (match_operand:SI 1 "const0_operand" "n,n")))]
1107 "ix86_match_ccmode (insn, CCNOmode)"
1109 test{l}\\t{%0, %0|%0, %0}
1110 cmp{l}\\t{%1, %0|%0, %1}"
1111 [(set_attr "type" "test,icmp")
1112 (set_attr "length_immediate" "0,1")
1113 (set_attr "mode" "SI")])
1115 (define_insn "*cmpsi_minus_1"
1117 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1118 (match_operand:SI 1 "general_operand" "ri,mr"))
1120 "ix86_match_ccmode (insn, CCGOCmode)"
1121 "cmp{l}\\t{%1, %0|%0, %1}"
1122 [(set_attr "type" "icmp")
1123 (set_attr "mode" "SI")])
1125 (define_expand "cmpsi_1"
1127 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1128 (match_operand:SI 1 "general_operand" "ri,mr")))]
1132 (define_insn "*cmpsi_1_insn"
1134 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1135 (match_operand:SI 1 "general_operand" "ri,mr")))]
1136 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1137 && ix86_match_ccmode (insn, CCmode)"
1138 "cmp{l}\\t{%1, %0|%0, %1}"
1139 [(set_attr "type" "icmp")
1140 (set_attr "mode" "SI")])
1142 (define_insn "*cmphi_ccno_1"
1144 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
1145 (match_operand:HI 1 "const0_operand" "n,n")))]
1146 "ix86_match_ccmode (insn, CCNOmode)"
1148 test{w}\\t{%0, %0|%0, %0}
1149 cmp{w}\\t{%1, %0|%0, %1}"
1150 [(set_attr "type" "test,icmp")
1151 (set_attr "length_immediate" "0,1")
1152 (set_attr "mode" "HI")])
1154 (define_insn "*cmphi_minus_1"
1156 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1157 (match_operand:HI 1 "general_operand" "ri,mr"))
1159 "ix86_match_ccmode (insn, CCGOCmode)"
1160 "cmp{w}\\t{%1, %0|%0, %1}"
1161 [(set_attr "type" "icmp")
1162 (set_attr "mode" "HI")])
1164 (define_insn "*cmphi_1"
1166 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1167 (match_operand:HI 1 "general_operand" "ri,mr")))]
1168 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1169 && ix86_match_ccmode (insn, CCmode)"
1170 "cmp{w}\\t{%1, %0|%0, %1}"
1171 [(set_attr "type" "icmp")
1172 (set_attr "mode" "HI")])
1174 (define_insn "*cmpqi_ccno_1"
1176 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
1177 (match_operand:QI 1 "const0_operand" "n,n")))]
1178 "ix86_match_ccmode (insn, CCNOmode)"
1180 test{b}\\t{%0, %0|%0, %0}
1181 cmp{b}\\t{$0, %0|%0, 0}"
1182 [(set_attr "type" "test,icmp")
1183 (set_attr "length_immediate" "0,1")
1184 (set_attr "mode" "QI")])
1186 (define_insn "*cmpqi_1"
1188 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1189 (match_operand:QI 1 "general_operand" "qi,mq")))]
1190 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1191 && ix86_match_ccmode (insn, CCmode)"
1192 "cmp{b}\\t{%1, %0|%0, %1}"
1193 [(set_attr "type" "icmp")
1194 (set_attr "mode" "QI")])
1196 (define_insn "*cmpqi_minus_1"
1198 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1199 (match_operand:QI 1 "general_operand" "qi,mq"))
1201 "ix86_match_ccmode (insn, CCGOCmode)"
1202 "cmp{b}\\t{%1, %0|%0, %1}"
1203 [(set_attr "type" "icmp")
1204 (set_attr "mode" "QI")])
1206 (define_insn "*cmpqi_ext_1"
1209 (match_operand:QI 0 "general_operand" "Qm")
1212 (match_operand 1 "ext_register_operand" "Q")
1214 (const_int 8)) 0)))]
1215 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1216 "cmp{b}\\t{%h1, %0|%0, %h1}"
1217 [(set_attr "type" "icmp")
1218 (set_attr "mode" "QI")])
1220 (define_insn "*cmpqi_ext_1_rex64"
1223 (match_operand:QI 0 "ext_register_operand" "Q")
1226 (match_operand 1 "ext_register_operand" "Q")
1228 (const_int 8)) 0)))]
1229 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1230 "cmp{b}\\t{%h1, %0|%0, %h1}"
1231 [(set_attr "type" "icmp")
1232 (set_attr "mode" "QI")])
1234 (define_insn "*cmpqi_ext_2"
1239 (match_operand 0 "ext_register_operand" "Q")
1242 (match_operand:QI 1 "const0_operand" "n")))]
1243 "ix86_match_ccmode (insn, CCNOmode)"
1244 "test{b}\\t%h0, %h0"
1245 [(set_attr "type" "test")
1246 (set_attr "length_immediate" "0")
1247 (set_attr "mode" "QI")])
1249 (define_expand "cmpqi_ext_3"
1254 (match_operand 0 "ext_register_operand" "")
1257 (match_operand:QI 1 "general_operand" "")))]
1261 (define_insn "cmpqi_ext_3_insn"
1266 (match_operand 0 "ext_register_operand" "Q")
1269 (match_operand:QI 1 "general_operand" "Qmn")))]
1270 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1271 "cmp{b}\\t{%1, %h0|%h0, %1}"
1272 [(set_attr "type" "icmp")
1273 (set_attr "mode" "QI")])
1275 (define_insn "cmpqi_ext_3_insn_rex64"
1280 (match_operand 0 "ext_register_operand" "Q")
1283 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1284 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1285 "cmp{b}\\t{%1, %h0|%h0, %1}"
1286 [(set_attr "type" "icmp")
1287 (set_attr "mode" "QI")])
1289 (define_insn "*cmpqi_ext_4"
1294 (match_operand 0 "ext_register_operand" "Q")
1299 (match_operand 1 "ext_register_operand" "Q")
1301 (const_int 8)) 0)))]
1302 "ix86_match_ccmode (insn, CCmode)"
1303 "cmp{b}\\t{%h1, %h0|%h0, %h1}"
1304 [(set_attr "type" "icmp")
1305 (set_attr "mode" "QI")])
1307 ;; These implement float point compares.
1308 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1309 ;; which would allow mix and match FP modes on the compares. Which is what
1310 ;; the old patterns did, but with many more of them.
1312 (define_expand "cmpxf"
1314 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
1315 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
1316 "TARGET_80387 && !TARGET_64BIT"
1319 ix86_compare_op0 = operands[0];
1320 ix86_compare_op1 = operands[1];
1324 (define_expand "cmptf"
1326 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
1327 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
1331 ix86_compare_op0 = operands[0];
1332 ix86_compare_op1 = operands[1];
1336 (define_expand "cmpdf"
1338 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
1339 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
1340 "TARGET_80387 || TARGET_SSE2"
1343 ix86_compare_op0 = operands[0];
1344 ix86_compare_op1 = operands[1];
1348 (define_expand "cmpsf"
1350 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
1351 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
1352 "TARGET_80387 || TARGET_SSE"
1355 ix86_compare_op0 = operands[0];
1356 ix86_compare_op1 = operands[1];
1360 ;; FP compares, step 1:
1361 ;; Set the FP condition codes.
1363 ;; CCFPmode compare with exceptions
1364 ;; CCFPUmode compare with no exceptions
1366 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
1367 ;; and that fp moves clobber the condition codes, and that there is
1368 ;; currently no way to describe this fact to reg-stack. So there are
1369 ;; no splitters yet for this.
1371 ;; %%% YIKES! This scheme does not retain a strong connection between
1372 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
1373 ;; work! Only allow tos/mem with tos in op 0.
1375 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
1376 ;; things aren't as bad as they sound...
1378 (define_insn "*cmpfp_0"
1379 [(set (match_operand:HI 0 "register_operand" "=a")
1381 [(compare:CCFP (match_operand 1 "register_operand" "f")
1382 (match_operand 2 "const0_operand" "X"))] 9))]
1384 && FLOAT_MODE_P (GET_MODE (operands[1]))
1385 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1388 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1389 return \"ftst\;fnstsw\\t%0\;fstp\\t%y0\";
1391 return \"ftst\;fnstsw\\t%0\";
1393 [(set_attr "type" "multi")
1394 (set_attr "mode" "unknownfp")])
1396 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1397 ;; used to manage the reg stack popping would not be preserved.
1399 (define_insn "*cmpfp_2_sf"
1402 (match_operand:SF 0 "register_operand" "f")
1403 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
1405 "* return output_fp_compare (insn, operands, 0, 0);"
1406 [(set_attr "type" "fcmp")
1407 (set_attr "mode" "SF")])
1409 (define_insn "*cmpfp_2_sf_1"
1410 [(set (match_operand:HI 0 "register_operand" "=a")
1413 (match_operand:SF 1 "register_operand" "f")
1414 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
1416 "* return output_fp_compare (insn, operands, 2, 0);"
1417 [(set_attr "type" "fcmp")
1418 (set_attr "mode" "SF")])
1420 (define_insn "*cmpfp_2_df"
1423 (match_operand:DF 0 "register_operand" "f")
1424 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
1426 "* return output_fp_compare (insn, operands, 0, 0);"
1427 [(set_attr "type" "fcmp")
1428 (set_attr "mode" "DF")])
1430 (define_insn "*cmpfp_2_df_1"
1431 [(set (match_operand:HI 0 "register_operand" "=a")
1434 (match_operand:DF 1 "register_operand" "f")
1435 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
1437 "* return output_fp_compare (insn, operands, 2, 0);"
1438 [(set_attr "type" "multi")
1439 (set_attr "mode" "DF")])
1441 (define_insn "*cmpfp_2_xf"
1444 (match_operand:XF 0 "register_operand" "f")
1445 (match_operand:XF 1 "register_operand" "f")))]
1446 "TARGET_80387 && !TARGET_64BIT"
1447 "* return output_fp_compare (insn, operands, 0, 0);"
1448 [(set_attr "type" "fcmp")
1449 (set_attr "mode" "XF")])
1451 (define_insn "*cmpfp_2_tf"
1454 (match_operand:TF 0 "register_operand" "f")
1455 (match_operand:TF 1 "register_operand" "f")))]
1457 "* return output_fp_compare (insn, operands, 0, 0);"
1458 [(set_attr "type" "fcmp")
1459 (set_attr "mode" "XF")])
1461 (define_insn "*cmpfp_2_xf_1"
1462 [(set (match_operand:HI 0 "register_operand" "=a")
1465 (match_operand:XF 1 "register_operand" "f")
1466 (match_operand:XF 2 "register_operand" "f"))] 9))]
1467 "TARGET_80387 && !TARGET_64BIT"
1468 "* return output_fp_compare (insn, operands, 2, 0);"
1469 [(set_attr "type" "multi")
1470 (set_attr "mode" "XF")])
1472 (define_insn "*cmpfp_2_tf_1"
1473 [(set (match_operand:HI 0 "register_operand" "=a")
1476 (match_operand:TF 1 "register_operand" "f")
1477 (match_operand:TF 2 "register_operand" "f"))] 9))]
1479 "* return output_fp_compare (insn, operands, 2, 0);"
1480 [(set_attr "type" "multi")
1481 (set_attr "mode" "XF")])
1483 (define_insn "*cmpfp_2u"
1484 [(set (reg:CCFPU 18)
1486 (match_operand 0 "register_operand" "f")
1487 (match_operand 1 "register_operand" "f")))]
1489 && FLOAT_MODE_P (GET_MODE (operands[0]))
1490 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1491 "* return output_fp_compare (insn, operands, 0, 1);"
1492 [(set_attr "type" "fcmp")
1493 (set_attr "mode" "unknownfp")])
1495 (define_insn "*cmpfp_2u_1"
1496 [(set (match_operand:HI 0 "register_operand" "=a")
1499 (match_operand 1 "register_operand" "f")
1500 (match_operand 2 "register_operand" "f"))] 9))]
1502 && FLOAT_MODE_P (GET_MODE (operands[1]))
1503 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1504 "* return output_fp_compare (insn, operands, 2, 1);"
1505 [(set_attr "type" "multi")
1506 (set_attr "mode" "unknownfp")])
1508 ;; Patterns to match the SImode-in-memory ficom instructions.
1510 ;; %%% Play games with accepting gp registers, as otherwise we have to
1511 ;; force them to memory during rtl generation, which is no good. We
1512 ;; can get rid of this once we teach reload to do memory input reloads
1515 (define_insn "*ficom_1"
1518 (match_operand 0 "register_operand" "f,f")
1519 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
1520 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
1521 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
1524 ;; Split the not-really-implemented gp register case into a
1525 ;; push-op-pop sequence.
1527 ;; %%% This is most efficient, but am I gonna get in trouble
1528 ;; for separating cc0_setter and cc0_user?
1533 (match_operand:SF 0 "register_operand" "")
1534 (float (match_operand:SI 1 "register_operand" ""))))]
1535 "0 && TARGET_80387 && reload_completed"
1536 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
1537 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
1538 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
1539 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
1540 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1541 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
1543 ;; FP compares, step 2
1544 ;; Move the fpsw to ax.
1546 (define_insn "x86_fnstsw_1"
1547 [(set (match_operand:HI 0 "register_operand" "=a")
1548 (unspec:HI [(reg 18)] 9))]
1551 [(set_attr "length" "2")
1552 (set_attr "mode" "SI")
1553 (set_attr "i387" "1")
1554 (set_attr "ppro_uops" "few")])
1556 ;; FP compares, step 3
1557 ;; Get ax into flags, general case.
1559 (define_insn "x86_sahf_1"
1561 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
1564 [(set_attr "length" "1")
1565 (set_attr "athlon_decode" "vector")
1566 (set_attr "mode" "SI")
1567 (set_attr "ppro_uops" "one")])
1569 ;; Pentium Pro can do steps 1 through 3 in one go.
1571 (define_insn "*cmpfp_i"
1573 (compare:CCFP (match_operand 0 "register_operand" "f")
1574 (match_operand 1 "register_operand" "f")))]
1575 "TARGET_80387 && TARGET_CMOVE
1576 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1577 && FLOAT_MODE_P (GET_MODE (operands[0]))
1578 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1579 "* return output_fp_compare (insn, operands, 1, 0);"
1580 [(set_attr "type" "fcmp")
1581 (set_attr "mode" "unknownfp")
1582 (set_attr "athlon_decode" "vector")])
1584 (define_insn "*cmpfp_i_sse"
1586 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1587 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1589 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1590 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1591 "* return output_fp_compare (insn, operands, 1, 0);"
1592 [(set_attr "type" "fcmp,sse")
1593 (set_attr "mode" "unknownfp")
1594 (set_attr "athlon_decode" "vector")])
1596 (define_insn "*cmpfp_i_sse_only"
1598 (compare:CCFP (match_operand 0 "register_operand" "x")
1599 (match_operand 1 "nonimmediate_operand" "xm")))]
1600 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1601 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1602 "* return output_fp_compare (insn, operands, 1, 0);"
1603 [(set_attr "type" "sse")
1604 (set_attr "mode" "unknownfp")
1605 (set_attr "athlon_decode" "vector")])
1607 (define_insn "*cmpfp_iu"
1608 [(set (reg:CCFPU 17)
1609 (compare:CCFPU (match_operand 0 "register_operand" "f")
1610 (match_operand 1 "register_operand" "f")))]
1611 "TARGET_80387 && TARGET_CMOVE
1612 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1613 && FLOAT_MODE_P (GET_MODE (operands[0]))
1614 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1615 "* return output_fp_compare (insn, operands, 1, 1);"
1616 [(set_attr "type" "fcmp")
1617 (set_attr "mode" "unknownfp")
1618 (set_attr "athlon_decode" "vector")])
1620 (define_insn "*cmpfp_iu_sse"
1621 [(set (reg:CCFPU 17)
1622 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1623 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1625 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1626 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1627 "* return output_fp_compare (insn, operands, 1, 1);"
1628 [(set_attr "type" "fcmp,sse")
1629 (set_attr "mode" "unknownfp")
1630 (set_attr "athlon_decode" "vector")])
1632 (define_insn "*cmpfp_iu_sse_only"
1633 [(set (reg:CCFPU 17)
1634 (compare:CCFPU (match_operand 0 "register_operand" "x")
1635 (match_operand 1 "nonimmediate_operand" "xm")))]
1636 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1637 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1638 "* return output_fp_compare (insn, operands, 1, 1);"
1639 [(set_attr "type" "sse")
1640 (set_attr "mode" "unknownfp")
1641 (set_attr "athlon_decode" "vector")])
1643 ;; Move instructions.
1645 ;; General case of fullword move.
1647 (define_expand "movsi"
1648 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1649 (match_operand:SI 1 "general_operand" ""))]
1651 "ix86_expand_move (SImode, operands); DONE;")
1653 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1656 ;; %%% We don't use a post-inc memory reference because x86 is not a
1657 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1658 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1659 ;; targets without our curiosities, and it is just as easy to represent
1660 ;; this differently.
1662 (define_insn "*pushsi2"
1663 [(set (match_operand:SI 0 "push_operand" "=<")
1664 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1667 [(set_attr "type" "push")
1668 (set_attr "mode" "SI")])
1670 ;; For 64BIT abi we always round up to 8 bytes.
1671 (define_insn "*pushsi2_rex64"
1672 [(set (match_operand:SI 0 "push_operand" "=X")
1673 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1676 [(set_attr "type" "push")
1677 (set_attr "mode" "SI")])
1679 (define_insn "*pushsi2_prologue"
1680 [(set (match_operand:SI 0 "push_operand" "=<")
1681 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1682 (set (reg:SI 6) (reg:SI 6))]
1685 [(set_attr "type" "push")
1686 (set_attr "mode" "SI")])
1688 (define_insn "*popsi1_epilogue"
1689 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1690 (mem:SI (reg:SI 7)))
1692 (plus:SI (reg:SI 7) (const_int 4)))
1693 (set (reg:SI 6) (reg:SI 6))]
1696 [(set_attr "type" "pop")
1697 (set_attr "mode" "SI")])
1699 (define_insn "popsi1"
1700 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1701 (mem:SI (reg:SI 7)))
1703 (plus:SI (reg:SI 7) (const_int 4)))]
1706 [(set_attr "type" "pop")
1707 (set_attr "mode" "SI")])
1709 (define_insn "*movsi_xor"
1710 [(set (match_operand:SI 0 "register_operand" "=r")
1711 (match_operand:SI 1 "const0_operand" "i"))
1712 (clobber (reg:CC 17))]
1713 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1714 "xor{l}\\t{%0, %0|%0, %0}"
1715 [(set_attr "type" "alu1")
1716 (set_attr "mode" "SI")
1717 (set_attr "length_immediate" "0")])
1719 (define_insn "*movsi_or"
1720 [(set (match_operand:SI 0 "register_operand" "=r")
1721 (match_operand:SI 1 "immediate_operand" "i"))
1722 (clobber (reg:CC 17))]
1723 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1724 && INTVAL (operands[1]) == -1
1725 && (TARGET_PENTIUM || optimize_size)"
1728 operands[1] = constm1_rtx;
1729 return \"or{l}\\t{%1, %0|%0, %1}\";
1731 [(set_attr "type" "alu1")
1732 (set_attr "mode" "SI")
1733 (set_attr "length_immediate" "1")])
1735 (define_insn "*movsi_1"
1736 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y")
1737 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))]
1738 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1741 switch (get_attr_type (insn))
1744 if (get_attr_mode (insn) == TImode)
1745 return \"movdqa\\t{%1, %0|%0, %1}\";
1746 return \"movd\\t{%1, %0|%0, %1}\";
1749 return \"movd\\t{%1, %0|%0, %1}\";
1752 return \"lea{l}\\t{%1, %0|%0, %1}\";
1755 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1757 return \"mov{l}\\t{%1, %0|%0, %1}\";
1761 (cond [(eq_attr "alternative" "4,5")
1762 (const_string "mmx")
1763 (eq_attr "alternative" "6,7,8")
1764 (const_string "sse")
1765 (and (ne (symbol_ref "flag_pic") (const_int 0))
1766 (match_operand:SI 1 "symbolic_operand" ""))
1767 (const_string "lea")
1769 (const_string "imov")))
1770 (set_attr "modrm" "0,*,0,*,*,*,*,*,*")
1771 (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")])
1773 ;; Stores and loads of ax to arbitary constant address.
1774 ;; We fake an second form of instruction to force reload to load address
1775 ;; into register when rax is not available
1776 (define_insn "*movabssi_1_rex64"
1777 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1778 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1781 movabs{l}\\t{%1, %P0|%P0, %1}
1782 mov{l}\\t{%1, %a0|%a0, %1}
1783 movabs{l}\\t{%1, %a0|%a0, %1}"
1784 [(set_attr "type" "imov")
1785 (set_attr "modrm" "0,*,*")
1786 (set_attr "length_address" "8,0,0")
1787 (set_attr "length_immediate" "0,*,*")
1788 (set_attr "memory" "store")
1789 (set_attr "mode" "SI")])
1791 (define_insn "*movabssi_2_rex64"
1792 [(set (match_operand:SI 0 "register_operand" "=a,r")
1793 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1796 movabs{l}\\t{%P1, %0|%0, %P1}
1797 mov{l}\\t{%a1, %0|%0, %a1}"
1798 [(set_attr "type" "imov")
1799 (set_attr "modrm" "0,*")
1800 (set_attr "length_address" "8,0")
1801 (set_attr "length_immediate" "0")
1802 (set_attr "memory" "load")
1803 (set_attr "mode" "SI")])
1805 (define_insn "*swapsi"
1806 [(set (match_operand:SI 0 "register_operand" "+r")
1807 (match_operand:SI 1 "register_operand" "+r"))
1812 [(set_attr "type" "imov")
1813 (set_attr "pent_pair" "np")
1814 (set_attr "athlon_decode" "vector")
1815 (set_attr "mode" "SI")
1816 (set_attr "modrm" "0")
1817 (set_attr "ppro_uops" "few")])
1819 (define_expand "movhi"
1820 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1821 (match_operand:HI 1 "general_operand" ""))]
1823 "ix86_expand_move (HImode, operands); DONE;")
1825 (define_insn "*pushhi2"
1826 [(set (match_operand:HI 0 "push_operand" "=<,<")
1827 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1830 push{w}\\t{|WORD PTR }%1
1832 [(set_attr "type" "push")
1833 (set_attr "mode" "HI")])
1835 ;; For 64BIT abi we always round up to 8 bytes.
1836 (define_insn "*pushhi2_rex64"
1837 [(set (match_operand:HI 0 "push_operand" "=X")
1838 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1841 [(set_attr "type" "push")
1842 (set_attr "mode" "QI")])
1844 (define_insn "*movhi_1"
1845 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1846 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1847 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1850 switch (get_attr_type (insn))
1853 /* movzwl is faster than movw on p2 due to partial word stalls,
1854 though not as fast as an aligned movl. */
1855 return \"movz{wl|x}\\t{%1, %k0|%k0, %1}\";
1857 if (get_attr_mode (insn) == MODE_SI)
1858 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
1860 return \"mov{w}\\t{%1, %0|%0, %1}\";
1864 (cond [(and (eq_attr "alternative" "0,1")
1865 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1867 (eq (symbol_ref "TARGET_HIMODE_MATH")
1869 (const_string "imov")
1870 (and (eq_attr "alternative" "2,3,4")
1871 (match_operand:HI 1 "aligned_operand" ""))
1872 (const_string "imov")
1873 (and (ne (symbol_ref "TARGET_MOVX")
1875 (eq_attr "alternative" "0,1,3,4"))
1876 (const_string "imovx")
1878 (const_string "imov")))
1880 (cond [(eq_attr "type" "imovx")
1882 (and (eq_attr "alternative" "2,3,4")
1883 (match_operand:HI 1 "aligned_operand" ""))
1885 (and (eq_attr "alternative" "0,1")
1886 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1888 (eq (symbol_ref "TARGET_HIMODE_MATH")
1892 (const_string "HI")))
1893 (set_attr "modrm" "0,*,*,0,*,*")])
1895 ;; Stores and loads of ax to arbitary constant address.
1896 ;; We fake an second form of instruction to force reload to load address
1897 ;; into register when rax is not available
1898 (define_insn "*movabshi_1_rex64"
1899 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1900 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1903 movabs{w}\\t{%1, %P0|%P0, %1}
1904 mov{w}\\t{%1, %a0|%a0, %1}
1905 movabs{w}\\t{%1, %a0|%a0, %1}"
1906 [(set_attr "type" "imov")
1907 (set_attr "modrm" "0,*,*")
1908 (set_attr "length_address" "8,0,0")
1909 (set_attr "length_immediate" "0,*,*")
1910 (set_attr "memory" "store")
1911 (set_attr "mode" "HI")])
1913 (define_insn "*movabshi_2_rex64"
1914 [(set (match_operand:HI 0 "register_operand" "=a,r")
1915 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1918 movabs{w}\\t{%P1, %0|%0, %P1}
1919 mov{w}\\t{%a1, %0|%0, %a1}"
1920 [(set_attr "type" "imov")
1921 (set_attr "modrm" "0,*")
1922 (set_attr "length_address" "8,0")
1923 (set_attr "length_immediate" "0")
1924 (set_attr "memory" "load")
1925 (set_attr "mode" "HI")])
1927 (define_insn "*swaphi_1"
1928 [(set (match_operand:HI 0 "register_operand" "+r")
1929 (match_operand:HI 1 "register_operand" "+r"))
1932 "TARGET_PARTIAL_REG_STALL"
1934 [(set_attr "type" "imov")
1935 (set_attr "pent_pair" "np")
1936 (set_attr "mode" "HI")
1937 (set_attr "modrm" "0")
1938 (set_attr "ppro_uops" "few")])
1940 (define_insn "*swaphi_2"
1941 [(set (match_operand:HI 0 "register_operand" "+r")
1942 (match_operand:HI 1 "register_operand" "+r"))
1945 "! TARGET_PARTIAL_REG_STALL"
1946 "xchg{l}\\t%k1, %k0"
1947 [(set_attr "type" "imov")
1948 (set_attr "pent_pair" "np")
1949 (set_attr "mode" "SI")
1950 (set_attr "modrm" "0")
1951 (set_attr "ppro_uops" "few")])
1953 (define_expand "movstricthi"
1954 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1955 (match_operand:HI 1 "general_operand" ""))]
1956 "! TARGET_PARTIAL_REG_STALL"
1959 /* Don't generate memory->memory moves, go through a register */
1960 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1961 operands[1] = force_reg (HImode, operands[1]);
1964 (define_insn "*movstricthi_1"
1965 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1966 (match_operand:HI 1 "general_operand" "rn,m"))]
1967 "! TARGET_PARTIAL_REG_STALL
1968 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1969 "mov{w}\\t{%1, %0|%0, %1}"
1970 [(set_attr "type" "imov")
1971 (set_attr "mode" "HI")])
1973 (define_insn "*movstricthi_xor"
1974 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1975 (match_operand:HI 1 "const0_operand" "i"))
1976 (clobber (reg:CC 17))]
1977 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1978 "xor{w}\\t{%0, %0|%0, %0}"
1979 [(set_attr "type" "alu1")
1980 (set_attr "mode" "HI")
1981 (set_attr "length_immediate" "0")])
1983 (define_expand "movqi"
1984 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1985 (match_operand:QI 1 "general_operand" ""))]
1987 "ix86_expand_move (QImode, operands); DONE;")
1989 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1990 ;; "push a byte". But actually we use pushw, which has the effect
1991 ;; of rounding the amount pushed up to a halfword.
1993 (define_insn "*pushqi2"
1994 [(set (match_operand:QI 0 "push_operand" "=X,X")
1995 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1998 push{w}\\t{|word ptr }%1
2000 [(set_attr "type" "push")
2001 (set_attr "mode" "HI")])
2003 ;; For 64BIT abi we always round up to 8 bytes.
2004 (define_insn "*pushqi2_rex64"
2005 [(set (match_operand:QI 0 "push_operand" "=X")
2006 (match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
2009 [(set_attr "type" "push")
2010 (set_attr "mode" "QI")])
2012 ;; Situation is quite tricky about when to choose full sized (SImode) move
2013 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
2014 ;; partial register dependency machines (such as AMD Athlon), where QImode
2015 ;; moves issue extra dependency and for partial register stalls machines
2016 ;; that don't use QImode patterns (and QImode move cause stall on the next
2019 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
2020 ;; register stall machines with, where we use QImode instructions, since
2021 ;; partial register stall can be caused there. Then we use movzx.
2022 (define_insn "*movqi_1"
2023 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
2024 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
2025 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
2028 switch (get_attr_type (insn))
2031 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
2033 return \"movz{bl|x}\\t{%1, %k0|%k0, %1}\";
2035 if (get_attr_mode (insn) == MODE_SI)
2036 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2038 return \"mov{b}\\t{%1, %0|%0, %1}\";
2042 (cond [(and (eq_attr "alternative" "3")
2043 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
2045 (eq (symbol_ref "TARGET_QIMODE_MATH")
2047 (const_string "imov")
2048 (eq_attr "alternative" "3,5")
2049 (const_string "imovx")
2050 (and (ne (symbol_ref "TARGET_MOVX")
2052 (eq_attr "alternative" "2"))
2053 (const_string "imovx")
2055 (const_string "imov")))
2057 (cond [(eq_attr "alternative" "3,4,5")
2059 (eq_attr "alternative" "6")
2061 (eq_attr "type" "imovx")
2063 (and (eq_attr "type" "imov")
2064 (and (eq_attr "alternative" "0,1,2")
2065 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
2068 ;; Avoid partial register stalls when not using QImode arithmetic
2069 (and (eq_attr "type" "imov")
2070 (and (eq_attr "alternative" "0,1,2")
2071 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
2073 (eq (symbol_ref "TARGET_QIMODE_MATH")
2077 (const_string "QI")))])
2079 (define_expand "reload_outqi"
2080 [(parallel [(match_operand:QI 0 "" "=m")
2081 (match_operand:QI 1 "register_operand" "r")
2082 (match_operand:QI 2 "register_operand" "=&q")])]
2087 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
2089 if (reg_overlap_mentioned_p (op2, op0))
2091 if (! q_regs_operand (op1, QImode))
2093 emit_insn (gen_movqi (op2, op1));
2096 emit_insn (gen_movqi (op0, op1));
2100 (define_insn "*swapqi"
2101 [(set (match_operand:QI 0 "register_operand" "+r")
2102 (match_operand:QI 1 "register_operand" "+r"))
2107 [(set_attr "type" "imov")
2108 (set_attr "pent_pair" "np")
2109 (set_attr "mode" "QI")
2110 (set_attr "modrm" "0")
2111 (set_attr "ppro_uops" "few")])
2113 (define_expand "movstrictqi"
2114 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
2115 (match_operand:QI 1 "general_operand" ""))]
2116 "! TARGET_PARTIAL_REG_STALL"
2119 /* Don't generate memory->memory moves, go through a register */
2120 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2121 operands[1] = force_reg (QImode, operands[1]);
2124 (define_insn "*movstrictqi_1"
2125 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
2126 (match_operand:QI 1 "general_operand" "*qn,m"))]
2127 "! TARGET_PARTIAL_REG_STALL
2128 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2129 "mov{b}\\t{%1, %0|%0, %1}"
2130 [(set_attr "type" "imov")
2131 (set_attr "mode" "QI")])
2133 (define_insn "*movstrictqi_xor"
2134 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
2135 (match_operand:QI 1 "const0_operand" "i"))
2136 (clobber (reg:CC 17))]
2137 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
2138 "xor{b}\\t{%0, %0|%0, %0}"
2139 [(set_attr "type" "alu1")
2140 (set_attr "mode" "QI")
2141 (set_attr "length_immediate" "0")])
2143 (define_insn "*movsi_extv_1"
2144 [(set (match_operand:SI 0 "register_operand" "=R")
2145 (sign_extract:SI (match_operand:SI 1 "ext_register_operand" "Q")
2149 "movs{bl|x}\\t{%h1, %0|%0, %h1}"
2150 [(set_attr "type" "imovx")
2151 (set_attr "mode" "SI")])
2153 (define_insn "*movhi_extv_1"
2154 [(set (match_operand:HI 0 "register_operand" "=R")
2155 (sign_extract:HI (match_operand:SI 1 "ext_register_operand" "Q")
2159 "movs{bl|x}\\t{%h1, %k0|%k0, %h1}"
2160 [(set_attr "type" "imovx")
2161 (set_attr "mode" "SI")])
2163 (define_insn "*movqi_extv_1"
2164 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2165 (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
2171 switch (get_attr_type (insn))
2174 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2176 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2180 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2181 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2182 (ne (symbol_ref "TARGET_MOVX")
2184 (const_string "imovx")
2185 (const_string "imov")))
2187 (if_then_else (eq_attr "type" "imovx")
2189 (const_string "QI")))])
2191 (define_insn "*movqi_extv_1_rex64"
2192 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2193 (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
2199 switch (get_attr_type (insn))
2202 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2204 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2208 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2209 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2210 (ne (symbol_ref "TARGET_MOVX")
2212 (const_string "imovx")
2213 (const_string "imov")))
2215 (if_then_else (eq_attr "type" "imovx")
2217 (const_string "QI")))])
2219 ;; Stores and loads of ax to arbitary constant address.
2220 ;; We fake an second form of instruction to force reload to load address
2221 ;; into register when rax is not available
2222 (define_insn "*movabsqi_1_rex64"
2223 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2224 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
2227 movabs{q}\\t{%1, %P0|%P0, %1}
2228 mov{q}\\t{%1, %a0|%a0, %1}
2229 movabs{q}\\t{%1, %a0|%a0, %1}"
2230 [(set_attr "type" "imov")
2231 (set_attr "modrm" "0,*,*")
2232 (set_attr "length_address" "8,0,0")
2233 (set_attr "length_immediate" "0,*,*")
2234 (set_attr "memory" "store")
2235 (set_attr "mode" "QI")])
2237 (define_insn "*movabsqi_2_rex64"
2238 [(set (match_operand:QI 0 "register_operand" "=a,r")
2239 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2242 movabs{q}\\t{%P1, %0|%0, %P1}
2243 mov{q}\\t{%a1, %0|%0, %a1}"
2244 [(set_attr "type" "imov")
2245 (set_attr "modrm" "0,*")
2246 (set_attr "length_address" "8,0")
2247 (set_attr "length_immediate" "0")
2248 (set_attr "memory" "load")
2249 (set_attr "mode" "QI")])
2251 (define_insn "*movsi_extzv_1"
2252 [(set (match_operand:SI 0 "register_operand" "=R")
2253 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
2257 "movz{bl|x}\\t{%h1, %0|%0, %h1}"
2258 [(set_attr "type" "imovx")
2259 (set_attr "mode" "SI")])
2261 (define_insn "*movqi_extzv_2"
2262 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2263 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2269 switch (get_attr_type (insn))
2272 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2274 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2278 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2279 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2280 (ne (symbol_ref "TARGET_MOVX")
2282 (const_string "imovx")
2283 (const_string "imov")))
2285 (if_then_else (eq_attr "type" "imovx")
2287 (const_string "QI")))])
2289 (define_insn "*movqi_extzv_2_rex64"
2290 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2291 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2297 switch (get_attr_type (insn))
2300 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2302 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2306 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2307 (ne (symbol_ref "TARGET_MOVX")
2309 (const_string "imovx")
2310 (const_string "imov")))
2312 (if_then_else (eq_attr "type" "imovx")
2314 (const_string "QI")))])
2316 (define_insn "*movsi_insv_1"
2317 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2320 (match_operand:SI 1 "nonimmediate_operand" "Qm"))]
2322 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2323 [(set_attr "type" "imov")
2324 (set_attr "mode" "QI")])
2326 (define_insn "*movsi_insv_1_rex64"
2327 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2330 (match_operand:SI 1 "ext_register_operand" "Q"))]
2332 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2333 [(set_attr "type" "imov")
2334 (set_attr "mode" "QI")])
2336 (define_insn "*movqi_insv_2"
2337 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2340 (and:SI (lshiftrt:SI (match_operand:SI 1 "ext_register_operand" "Q")
2344 "mov{b}\\t{%h1, %h0|%h0, %h1}"
2345 [(set_attr "type" "imov")
2346 (set_attr "mode" "QI")])
2348 (define_expand "movdi"
2349 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2350 (match_operand:DI 1 "general_operand" ""))]
2352 "ix86_expand_move (DImode, operands); DONE;")
2354 (define_insn "*pushdi"
2355 [(set (match_operand:DI 0 "push_operand" "=<")
2356 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2360 (define_insn "pushdi2_rex64"
2361 [(set (match_operand:DI 0 "push_operand" "=<,!<")
2362 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
2367 [(set_attr "type" "push,multi")
2368 (set_attr "mode" "DI")])
2370 ;; Convert impossible pushes of immediate to existing instructions.
2371 ;; First try to get scratch register and go trought it. In case this
2372 ;; fails, push sign extended lower part first and then overwrite
2373 ;; upper part by 32bit move.
2375 [(match_scratch:DI 2 "r")
2376 (set (match_operand:DI 0 "push_operand" "")
2377 (match_operand:DI 1 "immediate_operand" ""))]
2378 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2379 && !x86_64_immediate_operand (operands[1], DImode)"
2380 [(set (match_dup 2) (match_dup 1))
2381 (set (match_dup 0) (match_dup 2))]
2384 ;; We need to define this as both peepholer and splitter for case
2385 ;; peephole2 pass is not run.
2387 [(set (match_operand:DI 0 "push_operand" "")
2388 (match_operand:DI 1 "immediate_operand" ""))]
2389 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2390 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2391 [(set (match_dup 0) (match_dup 1))
2392 (set (match_dup 2) (match_dup 3))]
2393 "split_di (operands + 1, 1, operands + 2, operands + 3);
2394 operands[1] = gen_lowpart (DImode, operands[2]);
2395 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2400 [(set (match_operand:DI 0 "push_operand" "")
2401 (match_operand:DI 1 "immediate_operand" ""))]
2402 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2403 && !symbolic_operand (operands[1], DImode)
2404 && !x86_64_immediate_operand (operands[1], DImode)"
2405 [(set (match_dup 0) (match_dup 1))
2406 (set (match_dup 2) (match_dup 3))]
2407 "split_di (operands + 1, 1, operands + 2, operands + 3);
2408 operands[1] = gen_lowpart (DImode, operands[2]);
2409 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2413 (define_insn "*pushdi2_prologue_rex64"
2414 [(set (match_operand:DI 0 "push_operand" "=<")
2415 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
2416 (set (reg:DI 6) (reg:DI 6))]
2419 [(set_attr "type" "push")
2420 (set_attr "mode" "DI")])
2422 (define_insn "*popdi1_epilogue_rex64"
2423 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2424 (mem:DI (reg:DI 7)))
2426 (plus:DI (reg:DI 7) (const_int 8)))
2427 (set (reg:DI 6) (reg:DI 6))]
2430 [(set_attr "type" "pop")
2431 (set_attr "mode" "DI")])
2433 (define_insn "popdi1"
2434 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2435 (mem:DI (reg:DI 7)))
2437 (plus:DI (reg:DI 7) (const_int 8)))]
2440 [(set_attr "type" "pop")
2441 (set_attr "mode" "DI")])
2443 (define_insn "*movdi_xor_rex64"
2444 [(set (match_operand:DI 0 "register_operand" "=r")
2445 (match_operand:DI 1 "const0_operand" "i"))
2446 (clobber (reg:CC 17))]
2447 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)
2449 "xor{l}\\t{%k0, %k0|%k0, %k0}"
2450 [(set_attr "type" "alu1")
2451 (set_attr "mode" "SI")
2452 (set_attr "length_immediate" "0")])
2454 (define_insn "*movdi_or_rex64"
2455 [(set (match_operand:DI 0 "register_operand" "=r")
2456 (match_operand:DI 1 "const_int_operand" "i"))
2457 (clobber (reg:CC 17))]
2458 "reload_completed && GET_CODE (operands[1]) == CONST_INT
2460 && INTVAL (operands[1]) == -1
2461 && (TARGET_PENTIUM || optimize_size)"
2464 operands[1] = constm1_rtx;
2465 return \"or{q}\\t{%1, %0|%0, %1}\";
2467 [(set_attr "type" "alu1")
2468 (set_attr "mode" "DI")
2469 (set_attr "length_immediate" "1")])
2471 (define_insn "*movdi_2"
2472 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y")
2473 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
2475 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2479 movq\\t{%1, %0|%0, %1}
2480 movq\\t{%1, %0|%0, %1}
2481 movq\\t{%1, %0|%0, %1}
2482 movdqa\\t{%1, %0|%0, %1}
2483 movq\\t{%1, %0|%0, %1}"
2484 [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
2485 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
2488 [(set (match_operand:DI 0 "push_operand" "")
2489 (match_operand:DI 1 "general_operand" ""))]
2490 "!TARGET_64BIT && reload_completed
2491 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2493 "ix86_split_long_move (operands); DONE;")
2495 ;; %%% This multiword shite has got to go.
2497 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2498 (match_operand:DI 1 "general_operand" ""))]
2499 "!TARGET_64BIT && reload_completed
2500 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
2501 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2503 "ix86_split_long_move (operands); DONE;")
2505 (define_insn "*movdi_1_rex64"
2506 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
2507 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
2508 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2512 switch (get_attr_type (insn))
2515 if (register_operand (operands[0], DImode)
2516 && register_operand (operands[1], DImode))
2517 return \"movdqa\\t{%1, %0|%0, %1}\";
2520 return \"movq\\t{%1, %0|%0, %1}\";
2524 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
2526 if (flag_pic && SYMBOLIC_CONST (operands[1]))
2528 if (get_attr_mode (insn) == MODE_SI)
2529 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2530 else if (which_alternative == 2)
2531 return \"movabs{q}\\t{%1, %0|%0, %1}\";
2533 return \"mov{q}\\t{%1, %0|%0, %1}\";
2537 (cond [(eq_attr "alternative" "5,6")
2538 (const_string "mmx")
2539 (eq_attr "alternative" "7,8")
2540 (const_string "sse")
2541 (eq_attr "alternative" "4")
2542 (const_string "multi")
2543 (and (ne (symbol_ref "flag_pic") (const_int 0))
2544 (match_operand:DI 1 "symbolic_operand" ""))
2545 (const_string "lea")
2547 (const_string "imov")))
2548 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
2549 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
2550 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
2552 ;; Stores and loads of ax to arbitary constant address.
2553 ;; We fake an second form of instruction to force reload to load address
2554 ;; into register when rax is not available
2555 (define_insn "*movabsdi_1_rex64"
2556 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2557 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2560 movabs{q}\\t{%1, %P0|%P0, %1}
2561 mov{q}\\t{%1, %a0|%a0, %1}
2562 movabs{q}\\t{%1, %a0|%a0, %1}"
2563 [(set_attr "type" "imov")
2564 (set_attr "modrm" "0,*,*")
2565 (set_attr "length_address" "8,0,0")
2566 (set_attr "length_immediate" "0,*,*")
2567 (set_attr "memory" "store")
2568 (set_attr "mode" "DI")])
2570 (define_insn "*movabsdi_2_rex64"
2571 [(set (match_operand:DI 0 "register_operand" "=a,r")
2572 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2575 movabs{q}\\t{%P1, %0|%0, %P1}
2576 mov{q}\\t{%a1, %0|%0, %a1}"
2577 [(set_attr "type" "imov")
2578 (set_attr "modrm" "0,*")
2579 (set_attr "length_address" "8,0")
2580 (set_attr "length_immediate" "0")
2581 (set_attr "memory" "load")
2582 (set_attr "mode" "DI")])
2584 ;; Convert impossible stores of immediate to existing instructions.
2585 ;; First try to get scratch register and go trought it. In case this
2586 ;; fails, move by 32bit parts.
2588 [(match_scratch:DI 2 "r")
2589 (set (match_operand:DI 0 "memory_operand" "")
2590 (match_operand:DI 1 "immediate_operand" ""))]
2591 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2592 && !x86_64_immediate_operand (operands[1], DImode)"
2593 [(set (match_dup 2) (match_dup 1))
2594 (set (match_dup 0) (match_dup 2))]
2597 ;; We need to define this as both peepholer and splitter for case
2598 ;; peephole2 pass is not run.
2600 [(set (match_operand:DI 0 "memory_operand" "")
2601 (match_operand:DI 1 "immediate_operand" ""))]
2602 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2603 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2604 [(set (match_dup 2) (match_dup 3))
2605 (set (match_dup 4) (match_dup 5))]
2606 "split_di (operands, 2, operands + 2, operands + 4);")
2609 [(set (match_operand:DI 0 "memory_operand" "")
2610 (match_operand:DI 1 "immediate_operand" ""))]
2611 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2612 && !symbolic_operand (operands[1], DImode)
2613 && !x86_64_immediate_operand (operands[1], DImode)"
2614 [(set (match_dup 2) (match_dup 3))
2615 (set (match_dup 4) (match_dup 5))]
2616 "split_di (operands, 2, operands + 2, operands + 4);")
2618 (define_insn "*swapdi_rex64"
2619 [(set (match_operand:DI 0 "register_operand" "+r")
2620 (match_operand:DI 1 "register_operand" "+r"))
2625 [(set_attr "type" "imov")
2626 (set_attr "pent_pair" "np")
2627 (set_attr "athlon_decode" "vector")
2628 (set_attr "mode" "DI")
2629 (set_attr "modrm" "0")
2630 (set_attr "ppro_uops" "few")])
2633 (define_expand "movsf"
2634 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2635 (match_operand:SF 1 "general_operand" ""))]
2637 "ix86_expand_move (SFmode, operands); DONE;")
2639 (define_insn "*pushsf"
2640 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2641 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2645 switch (which_alternative)
2648 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2649 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2650 operands[2] = stack_pointer_rtx;
2651 operands[3] = GEN_INT (4);
2652 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2653 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2655 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2658 return \"push{l}\\t%1\";
2666 [(set_attr "type" "multi,push,multi")
2667 (set_attr "mode" "SF,SI,SF")])
2669 (define_insn "*pushsf_rex64"
2670 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2671 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2675 switch (which_alternative)
2678 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2679 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2680 operands[2] = stack_pointer_rtx;
2681 operands[3] = GEN_INT (8);
2682 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2683 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2685 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2688 return \"push{q}\\t%q1\";
2697 [(set_attr "type" "multi,push,multi")
2698 (set_attr "mode" "SF,DI,SF")])
2701 [(set (match_operand:SF 0 "push_operand" "")
2702 (match_operand:SF 1 "memory_operand" ""))]
2704 && GET_CODE (operands[1]) == MEM
2705 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2706 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2709 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2712 ;; %%% Kill this when call knows how to work this out.
2714 [(set (match_operand:SF 0 "push_operand" "")
2715 (match_operand:SF 1 "register_operand" ""))]
2716 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2717 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2718 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2721 [(set (match_operand:SF 0 "push_operand" "")
2722 (match_operand:SF 1 "register_operand" ""))]
2723 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2724 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2725 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2727 (define_insn "*movsf_1"
2728 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2729 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2730 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2731 && (reload_in_progress || reload_completed
2732 || GET_CODE (operands[1]) != CONST_DOUBLE
2733 || memory_operand (operands[0], SFmode))"
2736 switch (which_alternative)
2739 if (REG_P (operands[1])
2740 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2741 return \"fstp\\t%y0\";
2742 else if (STACK_TOP_P (operands[0]))
2743 return \"fld%z1\\t%y1\";
2745 return \"fst\\t%y0\";
2748 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2749 return \"fstp%z0\\t%y0\";
2751 return \"fst%z0\\t%y0\";
2754 switch (standard_80387_constant_p (operands[1]))
2765 return \"mov{l}\\t{%1, %0|%0, %1}\";
2767 return \"pxor\\t%0, %0\";
2769 if (TARGET_PARTIAL_REG_DEPENDENCY)
2770 return \"movaps\\t{%1, %0|%0, %1}\";
2772 return \"movss\\t{%1, %0|%0, %1}\";
2775 return \"movss\\t{%1, %0|%0, %1}\";
2781 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2782 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2784 (define_insn "*swapsf"
2785 [(set (match_operand:SF 0 "register_operand" "+f")
2786 (match_operand:SF 1 "register_operand" "+f"))
2789 "reload_completed || !TARGET_SSE2"
2792 if (STACK_TOP_P (operands[0]))
2793 return \"fxch\\t%1\";
2795 return \"fxch\\t%0\";
2797 [(set_attr "type" "fxch")
2798 (set_attr "mode" "SF")])
2800 (define_expand "movdf"
2801 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2802 (match_operand:DF 1 "general_operand" ""))]
2804 "ix86_expand_move (DFmode, operands); DONE;")
2806 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2807 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2808 ;; On the average, pushdf using integers can be still shorter. Allow this
2809 ;; pattern for optimize_size too.
2811 (define_insn "*pushdf_nointeger"
2812 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2813 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2814 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2817 switch (which_alternative)
2820 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2821 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2822 operands[2] = stack_pointer_rtx;
2823 operands[3] = GEN_INT (8);
2824 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2825 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2827 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2838 [(set_attr "type" "multi")
2839 (set_attr "mode" "DF,SI,SI,DF")])
2841 (define_insn "*pushdf_integer"
2842 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2843 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2844 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2847 switch (which_alternative)
2850 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2851 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2852 operands[2] = stack_pointer_rtx;
2853 operands[3] = GEN_INT (8);
2855 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2856 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2858 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2860 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2861 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2863 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2874 [(set_attr "type" "multi")
2875 (set_attr "mode" "DF,SI,DF")])
2877 ;; %%% Kill this when call knows how to work this out.
2879 [(set (match_operand:DF 0 "push_operand" "")
2880 (match_operand:DF 1 "register_operand" ""))]
2881 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2882 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2883 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2887 [(set (match_operand:DF 0 "push_operand" "")
2888 (match_operand:DF 1 "register_operand" ""))]
2889 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2890 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2891 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2895 [(set (match_operand:DF 0 "push_operand" "")
2896 (match_operand:DF 1 "general_operand" ""))]
2899 "ix86_split_long_move (operands); DONE;")
2901 ;; Moving is usually shorter when only FP registers are used. This separate
2902 ;; movdf pattern avoids the use of integer registers for FP operations
2903 ;; when optimizing for size.
2905 (define_insn "*movdf_nointeger"
2906 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2907 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2908 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2909 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2910 && (reload_in_progress || reload_completed
2911 || GET_CODE (operands[1]) != CONST_DOUBLE
2912 || memory_operand (operands[0], DFmode))"
2915 switch (which_alternative)
2918 if (REG_P (operands[1])
2919 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2920 return \"fstp\\t%y0\";
2921 else if (STACK_TOP_P (operands[0]))
2922 return \"fld%z1\\t%y1\";
2924 return \"fst\\t%y0\";
2927 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2928 return \"fstp%z0\\t%y0\";
2930 return \"fst%z0\\t%y0\";
2933 switch (standard_80387_constant_p (operands[1]))
2946 return \"pxor\\t%0, %0\";
2948 if (TARGET_PARTIAL_REG_DEPENDENCY)
2949 return \"movapd\\t{%1, %0|%0, %1}\";
2951 return \"movsd\\t{%1, %0|%0, %1}\";
2954 return \"movsd\\t{%1, %0|%0, %1}\";
2960 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2961 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2963 (define_insn "*movdf_integer"
2964 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2965 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2966 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2967 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2968 && (reload_in_progress || reload_completed
2969 || GET_CODE (operands[1]) != CONST_DOUBLE
2970 || memory_operand (operands[0], DFmode))"
2973 switch (which_alternative)
2976 if (REG_P (operands[1])
2977 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2978 return \"fstp\\t%y0\";
2979 else if (STACK_TOP_P (operands[0]))
2980 return \"fld%z1\\t%y1\";
2982 return \"fst\\t%y0\";
2985 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2986 return \"fstp%z0\\t%y0\";
2988 return \"fst%z0\\t%y0\";
2991 switch (standard_80387_constant_p (operands[1]))
3005 return \"pxor\\t%0, %0\";
3007 if (TARGET_PARTIAL_REG_DEPENDENCY)
3008 return \"movapd\\t{%1, %0|%0, %1}\";
3010 return \"movsd\\t{%1, %0|%0, %1}\";
3013 return \"movsd\\t{%1, %0|%0, %1}\";
3019 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
3020 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
3023 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3024 (match_operand:DF 1 "general_operand" ""))]
3026 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3027 && ! (ANY_FP_REG_P (operands[0]) ||
3028 (GET_CODE (operands[0]) == SUBREG
3029 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3030 && ! (ANY_FP_REG_P (operands[1]) ||
3031 (GET_CODE (operands[1]) == SUBREG
3032 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3034 "ix86_split_long_move (operands); DONE;")
3036 (define_insn "*swapdf"
3037 [(set (match_operand:DF 0 "register_operand" "+f")
3038 (match_operand:DF 1 "register_operand" "+f"))
3041 "reload_completed || !TARGET_SSE2"
3044 if (STACK_TOP_P (operands[0]))
3045 return \"fxch\\t%1\";
3047 return \"fxch\\t%0\";
3049 [(set_attr "type" "fxch")
3050 (set_attr "mode" "DF")])
3052 (define_expand "movxf"
3053 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3054 (match_operand:XF 1 "general_operand" ""))]
3056 "ix86_expand_move (XFmode, operands); DONE;")
3058 (define_expand "movtf"
3059 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3060 (match_operand:TF 1 "general_operand" ""))]
3062 "ix86_expand_move (TFmode, operands); DONE;")
3064 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
3065 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
3066 ;; Pushing using integer instructions is longer except for constants
3067 ;; and direct memory references.
3068 ;; (assuming that any given constant is pushed only once, but this ought to be
3069 ;; handled elsewhere).
3071 (define_insn "*pushxf_nointeger"
3072 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
3073 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
3074 "optimize_size && !TARGET_64BIT"
3077 switch (which_alternative)
3080 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3081 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3082 operands[2] = stack_pointer_rtx;
3083 operands[3] = GEN_INT (12);
3084 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3085 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3087 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3097 [(set_attr "type" "multi")
3098 (set_attr "mode" "XF,SI,SI")])
3100 (define_insn "*pushtf_nointeger"
3101 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
3102 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
3106 switch (which_alternative)
3109 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3110 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3111 operands[2] = stack_pointer_rtx;
3112 operands[3] = GEN_INT (16);
3113 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3114 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3116 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3126 [(set_attr "type" "multi")
3127 (set_attr "mode" "XF,SI,SI")])
3129 (define_insn "*pushxf_integer"
3130 [(set (match_operand:XF 0 "push_operand" "=<,<")
3131 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
3132 "!optimize_size && !TARGET_64BIT"
3135 switch (which_alternative)
3138 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3139 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3140 operands[2] = stack_pointer_rtx;
3141 operands[3] = GEN_INT (12);
3142 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3143 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3145 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3154 [(set_attr "type" "multi")
3155 (set_attr "mode" "XF,SI")])
3157 (define_insn "*pushtf_integer"
3158 [(set (match_operand:TF 0 "push_operand" "=<,<")
3159 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
3163 switch (which_alternative)
3166 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3167 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3168 operands[2] = stack_pointer_rtx;
3169 operands[3] = GEN_INT (16);
3171 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3172 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3174 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3176 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3177 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3179 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3188 [(set_attr "type" "multi")
3189 (set_attr "mode" "XF,SI")])
3192 [(set (match_operand 0 "push_operand" "")
3193 (match_operand 1 "general_operand" ""))]
3195 && (GET_MODE (operands[0]) == XFmode
3196 || GET_MODE (operands[0]) == TFmode
3197 || GET_MODE (operands[0]) == DFmode)
3198 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
3200 "ix86_split_long_move (operands); DONE;")
3203 [(set (match_operand:XF 0 "push_operand" "")
3204 (match_operand:XF 1 "register_operand" ""))]
3205 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3206 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3207 (set (mem:XF (reg:SI 7)) (match_dup 1))])
3210 [(set (match_operand:TF 0 "push_operand" "")
3211 (match_operand:TF 1 "register_operand" ""))]
3212 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3213 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3214 (set (mem:TF (reg:SI 7)) (match_dup 1))])
3217 [(set (match_operand:TF 0 "push_operand" "")
3218 (match_operand:TF 1 "register_operand" ""))]
3219 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3220 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3221 (set (mem:TF (reg:DI 7)) (match_dup 1))])
3223 ;; Do not use integer registers when optimizing for size
3224 (define_insn "*movxf_nointeger"
3225 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3226 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3227 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3230 && (reload_in_progress || reload_completed
3231 || GET_CODE (operands[1]) != CONST_DOUBLE
3232 || memory_operand (operands[0], XFmode))"
3235 switch (which_alternative)
3238 if (REG_P (operands[1])
3239 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3240 return \"fstp\\t%y0\";
3241 else if (STACK_TOP_P (operands[0]))
3242 return \"fld%z1\\t%y1\";
3244 return \"fst\\t%y0\";
3247 /* There is no non-popping store to memory for XFmode. So if
3248 we need one, follow the store with a load. */
3249 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3250 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3252 return \"fstp%z0\\t%y0\";
3255 switch (standard_80387_constant_p (operands[1]))
3269 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3270 (set_attr "mode" "XF,XF,XF,SI,SI")])
3272 (define_insn "*movtf_nointeger"
3273 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3274 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3275 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3277 && (reload_in_progress || reload_completed
3278 || GET_CODE (operands[1]) != CONST_DOUBLE
3279 || memory_operand (operands[0], TFmode))"
3282 switch (which_alternative)
3285 if (REG_P (operands[1])
3286 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3287 return \"fstp\\t%y0\";
3288 else if (STACK_TOP_P (operands[0]))
3289 return \"fld%z1\\t%y1\";
3291 return \"fst\\t%y0\";
3294 /* There is no non-popping store to memory for XFmode. So if
3295 we need one, follow the store with a load. */
3296 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3297 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3299 return \"fstp%z0\\t%y0\";
3302 switch (standard_80387_constant_p (operands[1]))
3316 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3317 (set_attr "mode" "XF,XF,XF,SI,SI")])
3319 (define_insn "*movxf_integer"
3320 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3321 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3322 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3325 && (reload_in_progress || reload_completed
3326 || GET_CODE (operands[1]) != CONST_DOUBLE
3327 || memory_operand (operands[0], XFmode))"
3330 switch (which_alternative)
3333 if (REG_P (operands[1])
3334 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3335 return \"fstp\\t%y0\";
3336 else if (STACK_TOP_P (operands[0]))
3337 return \"fld%z1\\t%y1\";
3339 return \"fst\\t%y0\";
3342 /* There is no non-popping store to memory for XFmode. So if
3343 we need one, follow the store with a load. */
3344 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3345 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3347 return \"fstp%z0\\t%y0\";
3350 switch (standard_80387_constant_p (operands[1]))
3364 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3365 (set_attr "mode" "XF,XF,XF,SI,SI")])
3367 (define_insn "*movtf_integer"
3368 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3369 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3370 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3372 && (reload_in_progress || reload_completed
3373 || GET_CODE (operands[1]) != CONST_DOUBLE
3374 || memory_operand (operands[0], TFmode))"
3377 switch (which_alternative)
3380 if (REG_P (operands[1])
3381 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3382 return \"fstp\\t%y0\";
3383 else if (STACK_TOP_P (operands[0]))
3384 return \"fld%z1\\t%y1\";
3386 return \"fst\\t%y0\";
3389 /* There is no non-popping store to memory for XFmode. So if
3390 we need one, follow the store with a load. */
3391 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3392 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3394 return \"fstp%z0\\t%y0\";
3397 switch (standard_80387_constant_p (operands[1]))
3411 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3412 (set_attr "mode" "XF,XF,XF,SI,SI")])
3415 [(set (match_operand 0 "nonimmediate_operand" "")
3416 (match_operand 1 "general_operand" ""))]
3418 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3419 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3420 && ! (ANY_FP_REG_P (operands[0]) ||
3421 (GET_CODE (operands[0]) == SUBREG
3422 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3423 && ! (ANY_FP_REG_P (operands[1]) ||
3424 (GET_CODE (operands[1]) == SUBREG
3425 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3427 "ix86_split_long_move (operands); DONE;")
3430 [(set (match_operand 0 "register_operand" "")
3431 (match_operand 1 "memory_operand" ""))]
3433 && GET_CODE (operands[1]) == MEM
3434 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3435 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3436 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3437 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3438 && (!(SSE_REG_P (operands[0]) ||
3439 (GET_CODE (operands[0]) == SUBREG
3440 && SSE_REG_P (SUBREG_REG (operands[0]))))
3441 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3442 && (!(FP_REG_P (operands[0]) ||
3443 (GET_CODE (operands[0]) == SUBREG
3444 && FP_REG_P (SUBREG_REG (operands[0]))))
3445 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3448 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3450 (define_insn "swapxf"
3451 [(set (match_operand:XF 0 "register_operand" "+f")
3452 (match_operand:XF 1 "register_operand" "+f"))
3458 if (STACK_TOP_P (operands[0]))
3459 return \"fxch\\t%1\";
3461 return \"fxch\\t%0\";
3463 [(set_attr "type" "fxch")
3464 (set_attr "mode" "XF")])
3466 (define_insn "swaptf"
3467 [(set (match_operand:TF 0 "register_operand" "+f")
3468 (match_operand:TF 1 "register_operand" "+f"))
3474 if (STACK_TOP_P (operands[0]))
3475 return \"fxch\\t%1\";
3477 return \"fxch\\t%0\";
3479 [(set_attr "type" "fxch")
3480 (set_attr "mode" "XF")])
3482 ;; Zero extension instructions
3484 (define_expand "zero_extendhisi2"
3485 [(set (match_operand:SI 0 "register_operand" "")
3486 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3490 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3492 operands[1] = force_reg (HImode, operands[1]);
3493 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3498 (define_insn "zero_extendhisi2_and"
3499 [(set (match_operand:SI 0 "register_operand" "=r")
3500 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3501 (clobber (reg:CC 17))]
3502 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3504 [(set_attr "type" "alu1")
3505 (set_attr "mode" "SI")])
3508 [(set (match_operand:SI 0 "register_operand" "")
3509 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3510 (clobber (reg:CC 17))]
3511 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3512 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3513 (clobber (reg:CC 17))])]
3516 (define_insn "*zero_extendhisi2_movzwl"
3517 [(set (match_operand:SI 0 "register_operand" "=r")
3518 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3519 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3520 "movz{wl|x}\\t{%1, %0|%0, %1}"
3521 [(set_attr "type" "imovx")
3522 (set_attr "mode" "SI")])
3524 (define_expand "zero_extendqihi2"
3526 [(set (match_operand:HI 0 "register_operand" "")
3527 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3528 (clobber (reg:CC 17))])]
3532 (define_insn "*zero_extendqihi2_and"
3533 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3534 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3535 (clobber (reg:CC 17))]
3536 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3538 [(set_attr "type" "alu1")
3539 (set_attr "mode" "HI")])
3541 (define_insn "*zero_extendqihi2_movzbw_and"
3542 [(set (match_operand:HI 0 "register_operand" "=r,r")
3543 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3544 (clobber (reg:CC 17))]
3545 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3547 [(set_attr "type" "imovx,alu1")
3548 (set_attr "mode" "HI")])
3550 (define_insn "*zero_extendqihi2_movzbw"
3551 [(set (match_operand:HI 0 "register_operand" "=r")
3552 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3553 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3554 "movz{bw|x}\\t{%1, %0|%0, %1}"
3555 [(set_attr "type" "imovx")
3556 (set_attr "mode" "HI")])
3558 ;; For the movzbw case strip only the clobber
3560 [(set (match_operand:HI 0 "register_operand" "")
3561 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3562 (clobber (reg:CC 17))]
3564 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3565 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3566 [(set (match_operand:HI 0 "register_operand" "")
3567 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3569 ;; When source and destination does not overlap, clear destination
3570 ;; first and then do the movb
3572 [(set (match_operand:HI 0 "register_operand" "")
3573 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3574 (clobber (reg:CC 17))]
3576 && ANY_QI_REG_P (operands[0])
3577 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3578 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3579 [(set (match_dup 0) (const_int 0))
3580 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3581 "operands[2] = gen_lowpart (QImode, operands[0]);")
3583 ;; Rest is handled by single and.
3585 [(set (match_operand:HI 0 "register_operand" "")
3586 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3587 (clobber (reg:CC 17))]
3589 && true_regnum (operands[0]) == true_regnum (operands[1])"
3590 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3591 (clobber (reg:CC 17))])]
3594 (define_expand "zero_extendqisi2"
3596 [(set (match_operand:SI 0 "register_operand" "")
3597 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3598 (clobber (reg:CC 17))])]
3602 (define_insn "*zero_extendqisi2_and"
3603 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3604 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3605 (clobber (reg:CC 17))]
3606 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3608 [(set_attr "type" "alu1")
3609 (set_attr "mode" "SI")])
3611 (define_insn "*zero_extendqisi2_movzbw_and"
3612 [(set (match_operand:SI 0 "register_operand" "=r,r")
3613 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3614 (clobber (reg:CC 17))]
3615 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3617 [(set_attr "type" "imovx,alu1")
3618 (set_attr "mode" "SI")])
3620 (define_insn "*zero_extendqisi2_movzbw"
3621 [(set (match_operand:SI 0 "register_operand" "=r")
3622 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3623 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3624 "movz{bl|x}\\t{%1, %0|%0, %1}"
3625 [(set_attr "type" "imovx")
3626 (set_attr "mode" "SI")])
3628 ;; For the movzbl case strip only the clobber
3630 [(set (match_operand:SI 0 "register_operand" "")
3631 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3632 (clobber (reg:CC 17))]
3634 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3635 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3637 (zero_extend:SI (match_dup 1)))])
3639 ;; When source and destination does not overlap, clear destination
3640 ;; first and then do the movb
3642 [(set (match_operand:SI 0 "register_operand" "")
3643 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3644 (clobber (reg:CC 17))]
3646 && ANY_QI_REG_P (operands[0])
3647 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3648 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3649 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3650 [(set (match_dup 0) (const_int 0))
3651 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3652 "operands[2] = gen_lowpart (QImode, operands[0]);")
3654 ;; Rest is handled by single and.
3656 [(set (match_operand:SI 0 "register_operand" "")
3657 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3658 (clobber (reg:CC 17))]
3660 && true_regnum (operands[0]) == true_regnum (operands[1])"
3661 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3662 (clobber (reg:CC 17))])]
3665 ;; %%% Kill me once multi-word ops are sane.
3666 (define_expand "zero_extendsidi2"
3667 [(set (match_operand:DI 0 "register_operand" "=r")
3668 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3672 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3677 (define_insn "zero_extendsidi2_32"
3678 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3679 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3680 (clobber (reg:CC 17))]
3683 [(set_attr "mode" "SI")])
3685 (define_insn "zero_extendsidi2_rex64"
3686 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3687 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3690 mov\\t{%k1, %k0|%k0, %k1}
3692 [(set_attr "type" "imovx,imov")
3693 (set_attr "mode" "SI,DI")])
3696 [(set (match_operand:DI 0 "memory_operand" "")
3697 (zero_extend:DI (match_dup 0)))]
3699 [(set (match_dup 4) (const_int 0))]
3700 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3703 [(set (match_operand:DI 0 "register_operand" "")
3704 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3705 (clobber (reg:CC 17))]
3706 "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])
3708 [(set (match_dup 4) (const_int 0))]
3709 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3712 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3713 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3714 (clobber (reg:CC 17))]
3715 "reload_completed && !TARGET_64BIT"
3716 [(set (match_dup 3) (match_dup 1))
3717 (set (match_dup 4) (const_int 0))]
3718 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3720 (define_insn "zero_extendhidi2"
3721 [(set (match_operand:DI 0 "register_operand" "=r,r")
3722 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3725 movz{wl|x}\\t{%1, %k0|%k0, %1}
3726 movz{wq|x}\\t{%1, %0|%0, %1}"
3727 [(set_attr "type" "imovx")
3728 (set_attr "mode" "SI,DI")])
3730 (define_insn "zero_extendqidi2"
3731 [(set (match_operand:DI 0 "register_operand" "=r,r")
3732 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3735 movz{bl|x}\\t{%1, %k0|%k0, %1}
3736 movz{bq|x}\\t{%1, %0|%0, %1}"
3737 [(set_attr "type" "imovx")
3738 (set_attr "mode" "SI,DI")])
3740 ;; Sign extension instructions
3742 (define_expand "extendsidi2"
3743 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3744 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3745 (clobber (reg:CC 17))
3746 (clobber (match_scratch:SI 2 ""))])]
3752 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3757 (define_insn "*extendsidi2_1"
3758 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3759 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3760 (clobber (reg:CC 17))
3761 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3765 (define_insn "extendsidi2_rex64"
3766 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3767 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3771 movs{lq|x}\\t{%1,%0|%0, %1}"
3772 [(set_attr "type" "imovx")
3773 (set_attr "mode" "DI")
3774 (set_attr "prefix_0f" "0")
3775 (set_attr "modrm" "0,1")])
3777 (define_insn "extendhidi2"
3778 [(set (match_operand:DI 0 "register_operand" "=r")
3779 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3781 "movs{wq|x}\\t{%1,%0|%0, %1}"
3782 [(set_attr "type" "imovx")
3783 (set_attr "mode" "DI")])
3785 (define_insn "extendqidi2"
3786 [(set (match_operand:DI 0 "register_operand" "=r")
3787 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3789 "movs{bq|x}\\t{%1,%0|%0, %1}"
3790 [(set_attr "type" "imovx")
3791 (set_attr "mode" "DI")])
3793 ;; Extend to memory case when source register does die.
3795 [(set (match_operand:DI 0 "memory_operand" "")
3796 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3797 (clobber (reg:CC 17))
3798 (clobber (match_operand:SI 2 "register_operand" ""))]
3800 && dead_or_set_p (insn, operands[1])
3801 && !reg_mentioned_p (operands[1], operands[0]))"
3802 [(set (match_dup 3) (match_dup 1))
3803 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3804 (clobber (reg:CC 17))])
3805 (set (match_dup 4) (match_dup 1))]
3806 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3808 ;; Extend to memory case when source register does not die.
3810 [(set (match_operand:DI 0 "memory_operand" "")
3811 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3812 (clobber (reg:CC 17))
3813 (clobber (match_operand:SI 2 "register_operand" ""))]
3818 split_di (&operands[0], 1, &operands[3], &operands[4]);
3820 emit_move_insn (operands[3], operands[1]);
3822 /* Generate a cltd if possible and doing so it profitable. */
3823 if (true_regnum (operands[1]) == 0
3824 && true_regnum (operands[2]) == 1
3825 && (optimize_size || TARGET_USE_CLTD))
3827 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3831 emit_move_insn (operands[2], operands[1]);
3832 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3834 emit_move_insn (operands[4], operands[2]);
3838 ;; Extend to register case. Optimize case where source and destination
3839 ;; registers match and cases where we can use cltd.
3841 [(set (match_operand:DI 0 "register_operand" "")
3842 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3843 (clobber (reg:CC 17))
3844 (clobber (match_scratch:SI 2 ""))]
3849 split_di (&operands[0], 1, &operands[3], &operands[4]);
3851 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3852 emit_move_insn (operands[3], operands[1]);
3854 /* Generate a cltd if possible and doing so it profitable. */
3855 if (true_regnum (operands[3]) == 0
3856 && (optimize_size || TARGET_USE_CLTD))
3858 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3862 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3863 emit_move_insn (operands[4], operands[1]);
3865 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3869 (define_insn "extendhisi2"
3870 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3871 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3875 switch (get_attr_prefix_0f (insn))
3878 return \"{cwtl|cwde}\";
3880 return \"movs{wl|x}\\t{%1,%0|%0, %1}\";
3883 [(set_attr "type" "imovx")
3884 (set_attr "mode" "SI")
3885 (set (attr "prefix_0f")
3886 ;; movsx is short decodable while cwtl is vector decoded.
3887 (if_then_else (and (eq_attr "cpu" "!k6")
3888 (eq_attr "alternative" "0"))
3890 (const_string "1")))
3892 (if_then_else (eq_attr "prefix_0f" "0")
3894 (const_string "1")))])
3896 (define_insn "*extendhisi2_zext"
3897 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3899 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3903 switch (get_attr_prefix_0f (insn))
3906 return \"{cwtl|cwde}\";
3908 return \"movs{wl|x}\\t{%1,%k0|%k0, %1}\";
3911 [(set_attr "type" "imovx")
3912 (set_attr "mode" "SI")
3913 (set (attr "prefix_0f")
3914 ;; movsx is short decodable while cwtl is vector decoded.
3915 (if_then_else (and (eq_attr "cpu" "!k6")
3916 (eq_attr "alternative" "0"))
3918 (const_string "1")))
3920 (if_then_else (eq_attr "prefix_0f" "0")
3922 (const_string "1")))])
3924 (define_insn "extendqihi2"
3925 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3926 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3930 switch (get_attr_prefix_0f (insn))
3933 return \"{cbtw|cbw}\";
3935 return \"movs{bw|x}\\t{%1,%0|%0, %1}\";
3938 [(set_attr "type" "imovx")
3939 (set_attr "mode" "HI")
3940 (set (attr "prefix_0f")
3941 ;; movsx is short decodable while cwtl is vector decoded.
3942 (if_then_else (and (eq_attr "cpu" "!k6")
3943 (eq_attr "alternative" "0"))
3945 (const_string "1")))
3947 (if_then_else (eq_attr "prefix_0f" "0")
3949 (const_string "1")))])
3951 (define_insn "extendqisi2"
3952 [(set (match_operand:SI 0 "register_operand" "=r")
3953 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3955 "movs{bl|x}\\t{%1,%0|%0, %1}"
3956 [(set_attr "type" "imovx")
3957 (set_attr "mode" "SI")])
3959 (define_insn "*extendqisi2_zext"
3960 [(set (match_operand:DI 0 "register_operand" "=r")
3962 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3964 "movs{bl|x}\\t{%1,%k0|%k0, %1}"
3965 [(set_attr "type" "imovx")
3966 (set_attr "mode" "SI")])
3968 ;; Conversions between float and double.
3970 ;; These are all no-ops in the model used for the 80387. So just
3973 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3974 (define_insn "*dummy_extendsfdf2"
3975 [(set (match_operand:DF 0 "push_operand" "=<")
3976 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3981 [(set (match_operand:DF 0 "push_operand" "")
3982 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3983 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3984 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3985 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3988 [(set (match_operand:DF 0 "push_operand" "")
3989 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3990 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3991 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3992 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3994 (define_insn "*dummy_extendsfxf2"
3995 [(set (match_operand:XF 0 "push_operand" "=<")
3996 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
4001 [(set (match_operand:XF 0 "push_operand" "")
4002 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
4003 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4004 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
4005 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4007 (define_insn "*dummy_extendsftf2"
4008 [(set (match_operand:TF 0 "push_operand" "=<")
4009 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
4014 [(set (match_operand:TF 0 "push_operand" "")
4015 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
4016 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4017 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4018 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
4021 [(set (match_operand:TF 0 "push_operand" "")
4022 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
4023 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
4024 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4025 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
4027 (define_insn "*dummy_extenddfxf2"
4028 [(set (match_operand:XF 0 "push_operand" "=<")
4029 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4034 [(set (match_operand:XF 0 "push_operand" "")
4035 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
4036 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4037 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
4038 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4040 (define_insn "*dummy_extenddftf2"
4041 [(set (match_operand:TF 0 "push_operand" "=<")
4042 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4047 [(set (match_operand:TF 0 "push_operand" "")
4048 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4049 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4050 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4051 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4054 [(set (match_operand:TF 0 "push_operand" "")
4055 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4056 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
4057 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4058 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
4060 (define_expand "extendsfdf2"
4061 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4062 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
4063 "TARGET_80387 || TARGET_SSE2"
4066 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4067 operands[1] = force_reg (SFmode, operands[1]);
4070 (define_insn "*extendsfdf2_1"
4071 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
4072 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
4073 "(TARGET_80387 || TARGET_SSE2)
4074 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4077 switch (which_alternative)
4080 if (REG_P (operands[1])
4081 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4082 return \"fstp\\t%y0\";
4083 else if (STACK_TOP_P (operands[0]))
4084 return \"fld%z1\\t%y1\";
4086 return \"fst\\t%y0\";
4089 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4090 return \"fstp%z0\\t%y0\";
4093 return \"fst%z0\\t%y0\";
4095 return \"cvtss2sd\\t{%1, %0|%0, %1}\";
4101 [(set_attr "type" "fmov,fmov,sse")
4102 (set_attr "mode" "SF,XF,DF")])
4104 (define_insn "*extendsfdf2_1_sse_only"
4105 [(set (match_operand:DF 0 "register_operand" "=Y")
4106 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
4107 "!TARGET_80387 && TARGET_SSE2
4108 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4109 "cvtss2sd\\t{%1, %0|%0, %1}"
4110 [(set_attr "type" "sse")
4111 (set_attr "mode" "DF")])
4113 (define_expand "extendsfxf2"
4114 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4115 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
4116 "TARGET_80387 && !TARGET_64BIT"
4119 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4120 operands[1] = force_reg (SFmode, operands[1]);
4123 (define_insn "*extendsfxf2_1"
4124 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4125 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4126 "TARGET_80387 && !TARGET_64BIT
4127 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4130 switch (which_alternative)
4133 if (REG_P (operands[1])
4134 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4135 return \"fstp\\t%y0\";
4136 else if (STACK_TOP_P (operands[0]))
4137 return \"fld%z1\\t%y1\";
4139 return \"fst\\t%y0\";
4142 /* There is no non-popping store to memory for XFmode. So if
4143 we need one, follow the store with a load. */
4144 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4145 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4147 return \"fstp%z0\\t%y0\";
4153 [(set_attr "type" "fmov")
4154 (set_attr "mode" "SF,XF")])
4156 (define_expand "extendsftf2"
4157 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4158 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
4162 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4163 operands[1] = force_reg (SFmode, operands[1]);
4166 (define_insn "*extendsftf2_1"
4167 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4168 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4170 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4173 switch (which_alternative)
4176 if (REG_P (operands[1])
4177 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4178 return \"fstp\\t%y0\";
4179 else if (STACK_TOP_P (operands[0]))
4180 return \"fld%z1\\t%y1\";
4182 return \"fst\\t%y0\";
4185 /* There is no non-popping store to memory for XFmode. So if
4186 we need one, follow the store with a load. */
4187 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4188 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4190 return \"fstp%z0\\t%y0\";
4196 [(set_attr "type" "fmov")
4197 (set_attr "mode" "SF,XF")])
4199 (define_expand "extenddfxf2"
4200 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4201 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
4202 "TARGET_80387 && !TARGET_64BIT"
4205 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4206 operands[1] = force_reg (DFmode, operands[1]);
4209 (define_insn "*extenddfxf2_1"
4210 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4211 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4212 "TARGET_80387 && !TARGET_64BIT
4213 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4216 switch (which_alternative)
4219 if (REG_P (operands[1])
4220 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4221 return \"fstp\\t%y0\";
4222 else if (STACK_TOP_P (operands[0]))
4223 return \"fld%z1\\t%y1\";
4225 return \"fst\\t%y0\";
4228 /* There is no non-popping store to memory for XFmode. So if
4229 we need one, follow the store with a load. */
4230 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4231 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4233 return \"fstp%z0\\t%y0\";
4239 [(set_attr "type" "fmov")
4240 (set_attr "mode" "DF,XF")])
4242 (define_expand "extenddftf2"
4243 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4244 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
4248 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4249 operands[1] = force_reg (DFmode, operands[1]);
4252 (define_insn "*extenddftf2_1"
4253 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4254 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4256 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4259 switch (which_alternative)
4262 if (REG_P (operands[1])
4263 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4264 return \"fstp\\t%y0\";
4265 else if (STACK_TOP_P (operands[0]))
4266 return \"fld%z1\\t%y1\";
4268 return \"fst\\t%y0\";
4271 /* There is no non-popping store to memory for XFmode. So if
4272 we need one, follow the store with a load. */
4273 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4274 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4276 return \"fstp%z0\\t%y0\";
4282 [(set_attr "type" "fmov")
4283 (set_attr "mode" "DF,XF")])
4285 ;; %%% This seems bad bad news.
4286 ;; This cannot output into an f-reg because there is no way to be sure
4287 ;; of truncating in that case. Otherwise this is just like a simple move
4288 ;; insn. So we pretend we can output to a reg in order to get better
4289 ;; register preferencing, but we really use a stack slot.
4291 (define_expand "truncdfsf2"
4292 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4294 (match_operand:DF 1 "register_operand" "")))
4295 (clobber (match_dup 2))])]
4296 "TARGET_80387 || TARGET_SSE2"
4299 operands[2] = assign_386_stack_local (SFmode, 0);
4302 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4307 (define_insn "*truncdfsf2_1"
4308 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4310 (match_operand:DF 1 "register_operand" "f,f,f,f")))
4311 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4312 "TARGET_80387 && !TARGET_SSE2"
4315 switch (which_alternative)
4318 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4319 return \"fstp%z0\\t%y0\";
4321 return \"fst%z0\\t%y0\";
4326 [(set_attr "type" "fmov,multi,multi,multi")
4327 (set_attr "mode" "SF,SF,SF,SF")])
4329 (define_insn "*truncdfsf2_1_sse"
4330 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y")
4332 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
4333 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
4334 "TARGET_80387 && TARGET_SSE2"
4337 switch (which_alternative)
4340 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4341 return \"fstp%z0\\t%y0\";
4343 return \"fst%z0\\t%y0\";
4345 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4350 [(set_attr "type" "fmov,multi,multi,multi,sse")
4351 (set_attr "mode" "SF,SF,SF,SF,DF")])
4353 (define_insn "*truncdfsf2_2"
4354 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
4356 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4357 "TARGET_80387 && TARGET_SSE2
4358 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4361 switch (which_alternative)
4364 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4366 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4367 return \"fstp%z0\\t%y0\";
4369 return \"fst%z0\\t%y0\";
4372 [(set_attr "type" "sse,fmov")
4373 (set_attr "mode" "DF,SF")])
4375 (define_insn "truncdfsf2_3"
4376 [(set (match_operand:SF 0 "memory_operand" "=m")
4378 (match_operand:DF 1 "register_operand" "f")))]
4382 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4383 return \"fstp%z0\\t%y0\";
4385 return \"fst%z0\\t%y0\";
4387 [(set_attr "type" "fmov")
4388 (set_attr "mode" "SF")])
4390 (define_insn "truncdfsf2_sse_only"
4391 [(set (match_operand:SF 0 "register_operand" "=Y")
4393 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4394 "!TARGET_80387 && TARGET_SSE2"
4395 "cvtsd2ss\\t{%1, %0|%0, %1}"
4396 [(set_attr "type" "sse")
4397 (set_attr "mode" "DF")])
4400 [(set (match_operand:SF 0 "memory_operand" "")
4402 (match_operand:DF 1 "register_operand" "")))
4403 (clobber (match_operand:SF 2 "memory_operand" ""))]
4405 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4409 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4411 (match_operand:DF 1 "nonimmediate_operand" "")))
4412 (clobber (match_operand 2 "" ""))]
4413 "TARGET_80387 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
4414 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4418 [(set (match_operand:SF 0 "register_operand" "")
4420 (match_operand:DF 1 "register_operand" "")))
4421 (clobber (match_operand:SF 2 "memory_operand" ""))]
4422 "TARGET_80387 && reload_completed
4423 && FP_REG_P (operands[1])"
4424 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4425 (set (match_dup 0) (match_dup 2))]
4428 (define_expand "truncxfsf2"
4429 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4431 (match_operand:XF 1 "register_operand" "")))
4432 (clobber (match_dup 2))])]
4433 "TARGET_80387 && !TARGET_64BIT"
4434 "operands[2] = assign_386_stack_local (SFmode, 0);")
4436 (define_insn "*truncxfsf2_1"
4437 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4439 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4440 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4441 "TARGET_80387 && !TARGET_64BIT"
4444 switch (which_alternative)
4447 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4448 return \"fstp%z0\\t%y0\";
4450 return \"fst%z0\\t%y0\";
4455 [(set_attr "type" "fmov,multi,multi,multi")
4456 (set_attr "mode" "SF")])
4458 (define_insn "*truncxfsf2_2"
4459 [(set (match_operand:SF 0 "memory_operand" "=m")
4461 (match_operand:XF 1 "register_operand" "f")))]
4462 "TARGET_80387 && !TARGET_64BIT"
4465 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4466 return \"fstp%z0\\t%y0\";
4468 return \"fst%z0\\t%y0\";
4470 [(set_attr "type" "fmov")
4471 (set_attr "mode" "SF")])
4474 [(set (match_operand:SF 0 "memory_operand" "")
4476 (match_operand:XF 1 "register_operand" "")))
4477 (clobber (match_operand:SF 2 "memory_operand" ""))]
4479 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4483 [(set (match_operand:SF 0 "register_operand" "")
4485 (match_operand:XF 1 "register_operand" "")))
4486 (clobber (match_operand:SF 2 "memory_operand" ""))]
4487 "TARGET_80387 && reload_completed"
4488 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4489 (set (match_dup 0) (match_dup 2))]
4492 (define_expand "trunctfsf2"
4493 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4495 (match_operand:TF 1 "register_operand" "")))
4496 (clobber (match_dup 2))])]
4498 "operands[2] = assign_386_stack_local (SFmode, 0);")
4500 (define_insn "*trunctfsf2_1"
4501 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4503 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4504 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4508 switch (which_alternative)
4511 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4512 return \"fstp%z0\\t%y0\";
4514 return \"fst%z0\\t%y0\";
4519 [(set_attr "type" "fmov,multi,multi,multi")
4520 (set_attr "mode" "SF")])
4522 (define_insn "*trunctfsf2_2"
4523 [(set (match_operand:SF 0 "memory_operand" "=m")
4525 (match_operand:TF 1 "register_operand" "f")))]
4529 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4530 return \"fstp%z0\\t%y0\";
4532 return \"fst%z0\\t%y0\";
4534 [(set_attr "type" "fmov")
4535 (set_attr "mode" "SF")])
4538 [(set (match_operand:SF 0 "memory_operand" "")
4540 (match_operand:TF 1 "register_operand" "")))
4541 (clobber (match_operand:SF 2 "memory_operand" ""))]
4543 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4547 [(set (match_operand:SF 0 "register_operand" "")
4549 (match_operand:TF 1 "register_operand" "")))
4550 (clobber (match_operand:SF 2 "memory_operand" ""))]
4551 "TARGET_80387 && reload_completed"
4552 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4553 (set (match_dup 0) (match_dup 2))]
4557 (define_expand "truncxfdf2"
4558 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4560 (match_operand:XF 1 "register_operand" "")))
4561 (clobber (match_dup 2))])]
4562 "TARGET_80387 && !TARGET_64BIT"
4563 "operands[2] = assign_386_stack_local (DFmode, 0);")
4565 (define_insn "*truncxfdf2_1"
4566 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4568 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4569 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4570 "TARGET_80387 && !TARGET_64BIT"
4573 switch (which_alternative)
4576 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4577 return \"fstp%z0\\t%y0\";
4579 return \"fst%z0\\t%y0\";
4585 [(set_attr "type" "fmov,multi,multi,multi")
4586 (set_attr "mode" "DF")])
4588 (define_insn "*truncxfdf2_2"
4589 [(set (match_operand:DF 0 "memory_operand" "=m")
4591 (match_operand:XF 1 "register_operand" "f")))]
4592 "TARGET_80387 && !TARGET_64BIT"
4595 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4596 return \"fstp%z0\\t%y0\";
4598 return \"fst%z0\\t%y0\";
4600 [(set_attr "type" "fmov")
4601 (set_attr "mode" "DF")])
4604 [(set (match_operand:DF 0 "memory_operand" "")
4606 (match_operand:XF 1 "register_operand" "")))
4607 (clobber (match_operand:DF 2 "memory_operand" ""))]
4609 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4613 [(set (match_operand:DF 0 "register_operand" "")
4615 (match_operand:XF 1 "register_operand" "")))
4616 (clobber (match_operand:DF 2 "memory_operand" ""))]
4617 "TARGET_80387 && reload_completed"
4618 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4619 (set (match_dup 0) (match_dup 2))]
4622 (define_expand "trunctfdf2"
4623 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4625 (match_operand:TF 1 "register_operand" "")))
4626 (clobber (match_dup 2))])]
4628 "operands[2] = assign_386_stack_local (DFmode, 0);")
4630 (define_insn "*trunctfdf2_1"
4631 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4633 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4634 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4638 switch (which_alternative)
4641 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4642 return \"fstp%z0\\t%y0\";
4644 return \"fst%z0\\t%y0\";
4650 [(set_attr "type" "fmov,multi,multi,multi")
4651 (set_attr "mode" "DF")])
4653 (define_insn "*trunctfdf2_2"
4654 [(set (match_operand:DF 0 "memory_operand" "=m")
4656 (match_operand:TF 1 "register_operand" "f")))]
4660 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4661 return \"fstp%z0\\t%y0\";
4663 return \"fst%z0\\t%y0\";
4665 [(set_attr "type" "fmov")
4666 (set_attr "mode" "DF")])
4669 [(set (match_operand:DF 0 "memory_operand" "")
4671 (match_operand:TF 1 "register_operand" "")))
4672 (clobber (match_operand:DF 2 "memory_operand" ""))]
4674 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4678 [(set (match_operand:DF 0 "register_operand" "")
4680 (match_operand:TF 1 "register_operand" "")))
4681 (clobber (match_operand:DF 2 "memory_operand" ""))]
4682 "TARGET_80387 && reload_completed"
4683 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4684 (set (match_dup 0) (match_dup 2))]
4688 ;; %%% Break up all these bad boys.
4690 ;; Signed conversion to DImode.
4692 (define_expand "fix_truncxfdi2"
4693 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4694 (fix:DI (match_operand:XF 1 "register_operand" "")))
4695 (clobber (match_dup 2))
4696 (clobber (match_dup 3))
4697 (clobber (match_scratch:SI 4 ""))
4698 (clobber (match_scratch:XF 5 ""))])]
4699 "TARGET_80387 && !TARGET_64BIT"
4700 "operands[2] = assign_386_stack_local (SImode, 0);
4701 operands[3] = assign_386_stack_local (DImode, 1);")
4703 (define_expand "fix_trunctfdi2"
4704 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4705 (fix:DI (match_operand:TF 1 "register_operand" "")))
4706 (clobber (match_dup 2))
4707 (clobber (match_dup 3))
4708 (clobber (match_scratch:SI 4 ""))
4709 (clobber (match_scratch:TF 5 ""))])]
4711 "operands[2] = assign_386_stack_local (SImode, 0);
4712 operands[3] = assign_386_stack_local (DImode, 1);")
4714 (define_expand "fix_truncdfdi2"
4715 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4716 (fix:DI (match_operand:DF 1 "register_operand" "")))
4717 (clobber (match_dup 2))
4718 (clobber (match_dup 3))
4719 (clobber (match_scratch:SI 4 ""))
4720 (clobber (match_scratch:DF 5 ""))])]
4721 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4726 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4727 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4728 if (out != operands[0])
4729 emit_move_insn (operands[0], out);
4734 operands[2] = assign_386_stack_local (SImode, 0);
4735 operands[3] = assign_386_stack_local (DImode, 1);
4739 (define_expand "fix_truncsfdi2"
4740 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4741 (fix:DI (match_operand:SF 1 "register_operand" "")))
4742 (clobber (match_dup 2))
4743 (clobber (match_dup 3))
4744 (clobber (match_scratch:SI 4 ""))
4745 (clobber (match_scratch:SF 5 ""))])]
4746 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4751 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4752 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4753 if (out != operands[0])
4754 emit_move_insn (operands[0], out);
4759 operands[2] = assign_386_stack_local (SImode, 0);
4760 operands[3] = assign_386_stack_local (DImode, 1);
4764 (define_insn "*fix_truncdi_1"
4765 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4766 (fix:DI (match_operand 1 "register_operand" "f,f")))
4767 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4768 (clobber (match_operand:DI 3 "memory_operand" "=m,m"))
4769 (clobber (match_scratch:SI 4 "=&r,&r"))
4770 (clobber (match_scratch 5 "=&f,&f"))]
4771 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4772 && (!TARGET_SSE2 || !TARGET_64BIT
4773 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4774 "* return output_fix_trunc (insn, operands);"
4775 [(set_attr "type" "multi")])
4778 [(set (match_operand:DI 0 "register_operand" "")
4779 (fix:DI (match_operand 1 "register_operand" "")))
4780 (clobber (match_operand:SI 2 "memory_operand" ""))
4781 (clobber (match_operand:DI 3 "memory_operand" ""))
4782 (clobber (match_scratch:SI 4 ""))
4783 (clobber (match_scratch 5 ""))]
4784 "reload_completed && !reg_overlap_mentioned_p (operands[4], operands[3])"
4785 [(parallel [(set (match_dup 3) (fix:DI (match_dup 1)))
4786 (clobber (match_dup 2))
4787 (clobber (match_dup 3))
4788 (clobber (match_dup 4))
4789 (clobber (match_dup 5))])
4790 (set (match_dup 0) (match_dup 3))]
4793 ;; When SSE available, it is always faster to use it!
4794 (define_insn "fix_truncsfdi_sse"
4795 [(set (match_operand:DI 0 "register_operand" "=r")
4796 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4797 "TARGET_SSE && TARGET_64BIT"
4798 "cvttss2si{q}\\t{%1, %0|%0, %1}"
4799 [(set_attr "type" "sse")])
4801 (define_insn "fix_truncdfdi_sse"
4802 [(set (match_operand:DI 0 "register_operand" "=r")
4803 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4804 "TARGET_SSE2 && TARGET_64BIT"
4805 "cvttsd2si{q}\\t{%1, %0|%0, %1}"
4806 [(set_attr "type" "sse")])
4808 ;; Signed conversion to SImode.
4810 (define_expand "fix_truncxfsi2"
4811 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4812 (fix:SI (match_operand:XF 1 "register_operand" "")))
4813 (clobber (match_dup 2))
4814 (clobber (match_dup 3))
4815 (clobber (match_scratch:SI 4 ""))])]
4816 "TARGET_80387 && !TARGET_64BIT"
4817 "operands[2] = assign_386_stack_local (SImode, 0);
4818 operands[3] = assign_386_stack_local (SImode, 1);")
4820 (define_expand "fix_trunctfsi2"
4821 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4822 (fix:SI (match_operand:TF 1 "register_operand" "")))
4823 (clobber (match_dup 2))
4824 (clobber (match_dup 3))
4825 (clobber (match_scratch:SI 4 ""))])]
4827 "operands[2] = assign_386_stack_local (SImode, 0);
4828 operands[3] = assign_386_stack_local (SImode, 1);")
4830 (define_expand "fix_truncdfsi2"
4831 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4832 (fix:SI (match_operand:DF 1 "register_operand" "")))
4833 (clobber (match_dup 2))
4834 (clobber (match_dup 3))
4835 (clobber (match_scratch:SI 4 ""))])]
4836 "TARGET_80387 || TARGET_SSE2"
4841 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4842 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4843 if (out != operands[0])
4844 emit_move_insn (operands[0], out);
4849 operands[2] = assign_386_stack_local (SImode, 0);
4850 operands[3] = assign_386_stack_local (SImode, 1);
4854 (define_expand "fix_truncsfsi2"
4855 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4856 (fix:SI (match_operand:SF 1 "register_operand" "")))
4857 (clobber (match_dup 2))
4858 (clobber (match_dup 3))
4859 (clobber (match_scratch:SI 4 ""))])]
4860 "TARGET_80387 || TARGET_SSE"
4865 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4866 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4867 if (out != operands[0])
4868 emit_move_insn (operands[0], out);
4873 operands[2] = assign_386_stack_local (SImode, 0);
4874 operands[3] = assign_386_stack_local (SImode, 1);
4878 (define_insn "*fix_truncsi_1"
4879 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4880 (fix:SI (match_operand 1 "register_operand" "f,f")))
4881 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4882 (clobber (match_operand:SI 3 "memory_operand" "=m,m"))
4883 (clobber (match_scratch:SI 4 "=&r,r"))]
4884 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4885 && (!TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4886 "* return output_fix_trunc (insn, operands);"
4887 [(set_attr "type" "multi")])
4889 ;; When SSE available, it is always faster to use it!
4890 (define_insn "fix_truncsfsi_sse"
4891 [(set (match_operand:SI 0 "register_operand" "=r")
4892 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4894 "cvttss2si\\t{%1, %0|%0, %1}"
4895 [(set_attr "type" "sse")])
4897 (define_insn "fix_truncdfsi_sse"
4898 [(set (match_operand:SI 0 "register_operand" "=r")
4899 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4901 "cvttsd2si\\t{%1, %0|%0, %1}"
4902 [(set_attr "type" "sse")])
4905 [(set (match_operand:SI 0 "register_operand" "")
4906 (fix:SI (match_operand 1 "register_operand" "")))
4907 (clobber (match_operand:SI 2 "memory_operand" ""))
4908 (clobber (match_operand:SI 3 "memory_operand" ""))
4909 (clobber (match_scratch:SI 4 ""))]
4911 [(parallel [(set (match_dup 3) (fix:SI (match_dup 1)))
4912 (clobber (match_dup 2))
4913 (clobber (match_dup 3))
4914 (clobber (match_dup 4))])
4915 (set (match_dup 0) (match_dup 3))]
4918 ;; Signed conversion to HImode.
4920 (define_expand "fix_truncxfhi2"
4921 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4922 (fix:HI (match_operand:XF 1 "register_operand" "")))
4923 (clobber (match_dup 2))
4924 (clobber (match_dup 3))
4925 (clobber (match_scratch:SI 4 ""))])]
4926 "TARGET_80387 && !TARGET_64BIT"
4927 "operands[2] = assign_386_stack_local (SImode, 0);
4928 operands[3] = assign_386_stack_local (HImode, 1);")
4930 (define_expand "fix_trunctfhi2"
4931 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4932 (fix:HI (match_operand:TF 1 "register_operand" "")))
4933 (clobber (match_dup 2))
4934 (clobber (match_dup 3))
4935 (clobber (match_scratch:SI 4 ""))])]
4937 "operands[2] = assign_386_stack_local (SImode, 0);
4938 operands[3] = assign_386_stack_local (HImode, 1);")
4940 (define_expand "fix_truncdfhi2"
4941 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4942 (fix:HI (match_operand:DF 1 "register_operand" "")))
4943 (clobber (match_dup 2))
4944 (clobber (match_dup 3))
4945 (clobber (match_scratch:SI 4 ""))])]
4946 "TARGET_80387 && !TARGET_SSE2"
4947 "operands[2] = assign_386_stack_local (SImode, 0);
4948 operands[3] = assign_386_stack_local (HImode, 1);")
4950 (define_expand "fix_truncsfhi2"
4951 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4952 (fix:HI (match_operand:SF 1 "register_operand" "")))
4953 (clobber (match_dup 2))
4954 (clobber (match_dup 3))
4955 (clobber (match_scratch:SI 4 ""))])]
4956 "TARGET_80387 && !TARGET_SSE"
4957 "operands[2] = assign_386_stack_local (SImode, 0);
4958 operands[3] = assign_386_stack_local (HImode, 1);")
4960 (define_insn "*fix_trunchi_1"
4961 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4962 (fix:HI (match_operand 1 "register_operand" "f,f")))
4963 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4964 (clobber (match_operand:HI 3 "memory_operand" "=m,m"))
4965 (clobber (match_scratch:SI 4 "=&r,r"))]
4966 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4967 && (TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4968 "* return output_fix_trunc (insn, operands);"
4969 [(set_attr "type" "multi")])
4972 [(set (match_operand:HI 0 "register_operand" "")
4973 (fix:HI (match_operand 1 "register_operand" "")))
4974 (clobber (match_operand:SI 2 "memory_operand" ""))
4975 (clobber (match_operand:HI 3 "memory_operand" ""))
4976 (clobber (match_scratch:SI 4 ""))]
4978 [(parallel [(set (match_dup 3) (fix:HI (match_dup 1)))
4979 (clobber (match_dup 2))
4980 (clobber (match_dup 3))
4981 (clobber (match_dup 4))])
4982 (set (match_dup 0) (match_dup 3))]
4985 ;; %%% Kill these when reload knows how to do it.
4987 [(set (match_operand 0 "register_operand" "")
4988 (fix (match_operand 1 "register_operand" "")))]
4989 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[1]))
4990 && FP_REG_P (operands[1])"
4994 operands[2] = ix86_force_to_memory (GET_MODE (operands[0]), operands[0]);
4995 operands[2] = gen_rtx_FIX (GET_MODE (operands[2]), operands[1]);
4996 emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1]));
4997 emit_move_insn (operands[0], operands[2]);
4998 ix86_free_from_memory (GET_MODE (operands[0]));
5003 (define_insn "x86_fnstcw_1"
5004 [(set (match_operand:HI 0 "memory_operand" "=m")
5005 (unspec:HI [(reg:HI 18)] 11))]
5008 [(set_attr "length" "2")
5009 (set_attr "mode" "HI")
5010 (set_attr "i387" "1")
5011 (set_attr "ppro_uops" "few")])
5013 (define_insn "x86_fldcw_1"
5015 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
5018 [(set_attr "length" "2")
5019 (set_attr "mode" "HI")
5020 (set_attr "i387" "1")
5021 (set_attr "athlon_decode" "vector")
5022 (set_attr "ppro_uops" "few")])
5024 ;; Conversion between fixed point and floating point.
5026 ;; Even though we only accept memory inputs, the backend _really_
5027 ;; wants to be able to do this between registers.
5029 (define_insn "floathisf2"
5030 [(set (match_operand:SF 0 "register_operand" "=f,f")
5031 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5032 "TARGET_80387 && !TARGET_SSE"
5036 [(set_attr "type" "fmov,multi")
5037 (set_attr "mode" "SF")
5038 (set_attr "fp_int_src" "true")])
5040 (define_expand "floatsisf2"
5041 [(set (match_operand:SF 0 "register_operand" "")
5042 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5043 "TARGET_SSE || TARGET_80387"
5046 (define_insn "*floatsisf2_i387"
5047 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5048 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5049 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
5053 cvtsi2ss\\t{%1, %0|%0, %1}"
5054 [(set_attr "type" "fmov,multi,sse")
5055 (set_attr "mode" "SF")
5056 (set_attr "fp_int_src" "true")])
5058 (define_insn "*floatsisf2_sse"
5059 [(set (match_operand:SF 0 "register_operand" "=x")
5060 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5062 "cvtsi2ss\\t{%1, %0|%0, %1}"
5063 [(set_attr "type" "sse")
5064 (set_attr "mode" "SF")
5065 (set_attr "fp_int_src" "true")])
5067 (define_expand "floatdisf2"
5068 [(set (match_operand:SF 0 "register_operand" "")
5069 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
5070 "(TARGET_SSE && TARGET_64BIT) || TARGET_80387"
5073 (define_insn "*floatdisf2_i387"
5074 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
5075 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5076 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
5080 cvtsi2ss{q}\\t{%1, %0|%0, %1}"
5081 [(set_attr "type" "fmov,multi,sse")
5082 (set_attr "mode" "SF")
5083 (set_attr "fp_int_src" "true")])
5085 (define_insn "*floatdisf2_sse"
5086 [(set (match_operand:SF 0 "register_operand" "=x")
5087 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5088 "TARGET_SSE && TARGET_64BIT"
5089 "cvtsi2ss{q}\\t{%1, %0|%0, %1}"
5090 [(set_attr "type" "sse")
5091 (set_attr "mode" "SF")
5092 (set_attr "fp_int_src" "true")])
5094 (define_insn "floathidf2"
5095 [(set (match_operand:DF 0 "register_operand" "=f,f")
5096 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5097 "TARGET_80387 && !TARGET_SSE2"
5101 [(set_attr "type" "fmov,multi")
5102 (set_attr "mode" "DF")
5103 (set_attr "fp_int_src" "true")])
5105 (define_expand "floatsidf2"
5106 [(set (match_operand:DF 0 "register_operand" "")
5107 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5111 (define_insn "*floatsidf2_i387"
5112 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5113 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5114 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5118 cvtsi2sd\\t{%1, %0|%0, %1}"
5119 [(set_attr "type" "fmov,multi,sse")
5120 (set_attr "mode" "DF")
5121 (set_attr "fp_int_src" "true")])
5123 (define_insn "*floatsidf2_sse"
5124 [(set (match_operand:DF 0 "register_operand" "=Y")
5125 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5127 "cvtsi2sd\\t{%1, %0|%0, %1}"
5128 [(set_attr "type" "sse")
5129 (set_attr "mode" "DF")
5130 (set_attr "fp_int_src" "true")])
5132 (define_expand "floatdidf2"
5133 [(set (match_operand:DF 0 "register_operand" "")
5134 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5135 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
5138 (define_insn "*floatdidf2_i387"
5139 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5140 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
5141 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
5145 cvtsi2sd{q}\\t{%1, %0|%0, %1}"
5146 [(set_attr "type" "fmov,multi,sse")
5147 (set_attr "mode" "DF")
5148 (set_attr "fp_int_src" "true")])
5150 (define_insn "*floatdidf2_sse"
5151 [(set (match_operand:DF 0 "register_operand" "=Y")
5152 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
5154 "cvtsi2sd{q}\\t{%1, %0|%0, %1}"
5155 [(set_attr "type" "sse")
5156 (set_attr "mode" "DF")
5157 (set_attr "fp_int_src" "true")])
5159 (define_insn "floathixf2"
5160 [(set (match_operand:XF 0 "register_operand" "=f,f")
5161 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5162 "TARGET_80387 && !TARGET_64BIT"
5166 [(set_attr "type" "fmov,multi")
5167 (set_attr "mode" "XF")
5168 (set_attr "fp_int_src" "true")])
5170 (define_insn "floathitf2"
5171 [(set (match_operand:TF 0 "register_operand" "=f,f")
5172 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5177 [(set_attr "type" "fmov,multi")
5178 (set_attr "mode" "XF")
5179 (set_attr "fp_int_src" "true")])
5181 (define_insn "floatsixf2"
5182 [(set (match_operand:XF 0 "register_operand" "=f,f")
5183 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5184 "TARGET_80387 && !TARGET_64BIT"
5188 [(set_attr "type" "fmov,multi")
5189 (set_attr "mode" "XF")
5190 (set_attr "fp_int_src" "true")])
5192 (define_insn "floatsitf2"
5193 [(set (match_operand:TF 0 "register_operand" "=f,f")
5194 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5199 [(set_attr "type" "fmov,multi")
5200 (set_attr "mode" "XF")
5201 (set_attr "fp_int_src" "true")])
5203 (define_insn "floatdixf2"
5204 [(set (match_operand:XF 0 "register_operand" "=f,f")
5205 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5206 "TARGET_80387 && !TARGET_64BIT"
5210 [(set_attr "type" "fmov,multi")
5211 (set_attr "mode" "XF")
5212 (set_attr "fp_int_src" "true")])
5214 (define_insn "floatditf2"
5215 [(set (match_operand:TF 0 "register_operand" "=f,f")
5216 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5221 [(set_attr "type" "fmov,multi")
5222 (set_attr "mode" "XF")
5223 (set_attr "fp_int_src" "true")])
5225 ;; %%% Kill these when reload knows how to do it.
5227 [(set (match_operand 0 "register_operand" "")
5228 (float (match_operand 1 "register_operand" "")))]
5229 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
5230 && FP_REG_P (operands[0])"
5234 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5235 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5236 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5237 ix86_free_from_memory (GET_MODE (operands[1]));
5243 ;; %%% splits for addsidi3
5244 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5245 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5246 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5248 (define_expand "adddi3"
5249 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5250 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5251 (match_operand:DI 2 "x86_64_general_operand" "")))
5252 (clobber (reg:CC 17))]
5254 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5256 (define_insn "*adddi3_1"
5257 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5258 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5259 (match_operand:DI 2 "general_operand" "roiF,riF")))
5260 (clobber (reg:CC 17))]
5265 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5266 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5267 (match_operand:DI 2 "general_operand" "")))
5268 (clobber (reg:CC 17))]
5269 "reload_completed && !TARGET_64BIT"
5270 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
5271 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5272 (parallel [(set (match_dup 3)
5273 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5276 (clobber (reg:CC 17))])]
5277 "split_di (operands+0, 1, operands+0, operands+3);
5278 split_di (operands+1, 1, operands+1, operands+4);
5279 split_di (operands+2, 1, operands+2, operands+5);")
5281 (define_insn "*adddi3_carry_rex64"
5282 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5283 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
5284 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5285 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5286 (clobber (reg:CC 17))]
5287 "ix86_binary_operator_ok (PLUS, DImode, operands)"
5288 "adc{q}\\t{%2, %0|%0, %2}"
5289 [(set_attr "type" "alu")
5290 (set_attr "pent_pair" "pu")
5291 (set_attr "mode" "DI")
5292 (set_attr "ppro_uops" "few")])
5294 (define_insn "*adddi3_cc_rex64"
5295 [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5296 (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12))
5297 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5298 (plus:DI (match_dup 1) (match_dup 2)))]
5299 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5300 "add{q}\\t{%2, %0|%0, %2}"
5301 [(set_attr "type" "alu")
5302 (set_attr "mode" "DI")])
5304 (define_insn "*addsi3_carry"
5305 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5306 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5307 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5308 (match_operand:SI 2 "general_operand" "ri,rm")))
5309 (clobber (reg:CC 17))]
5310 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5311 "adc{l}\\t{%2, %0|%0, %2}"
5312 [(set_attr "type" "alu")
5313 (set_attr "pent_pair" "pu")
5314 (set_attr "mode" "SI")
5315 (set_attr "ppro_uops" "few")])
5317 (define_insn "*addsi3_carry_zext"
5318 [(set (match_operand:DI 0 "register_operand" "=r")
5320 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5321 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5322 (match_operand:SI 2 "general_operand" "rim"))))
5323 (clobber (reg:CC 17))]
5324 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5325 "adc{l}\\t{%2, %k0|%k0, %2}"
5326 [(set_attr "type" "alu")
5327 (set_attr "pent_pair" "pu")
5328 (set_attr "mode" "SI")
5329 (set_attr "ppro_uops" "few")])
5331 (define_insn "*addsi3_cc"
5332 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5333 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
5334 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5335 (plus:SI (match_dup 1) (match_dup 2)))]
5336 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5337 "add{l}\\t{%2, %0|%0, %2}"
5338 [(set_attr "type" "alu")
5339 (set_attr "mode" "SI")])
5341 (define_insn "addqi3_cc"
5342 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5343 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
5344 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5345 (plus:QI (match_dup 1) (match_dup 2)))]
5346 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5347 "add{b}\\t{%2, %0|%0, %2}"
5348 [(set_attr "type" "alu")
5349 (set_attr "mode" "QI")])
5351 (define_expand "addsi3"
5352 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5353 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5354 (match_operand:SI 2 "general_operand" "")))
5355 (clobber (reg:CC 17))])]
5357 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5359 (define_insn "*lea_1"
5360 [(set (match_operand:SI 0 "register_operand" "=r")
5361 (match_operand:SI 1 "address_operand" "p"))]
5363 "lea{l}\\t{%a1, %0|%0, %a1}"
5364 [(set_attr "type" "lea")
5365 (set_attr "mode" "SI")])
5367 (define_insn "*lea_1_rex64"
5368 [(set (match_operand:SI 0 "register_operand" "=r")
5369 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5371 "lea{l}\\t{%a1, %0|%0, %a1}"
5372 [(set_attr "type" "lea")
5373 (set_attr "mode" "SI")])
5375 (define_insn "*lea_1_zext"
5376 [(set (match_operand:DI 0 "register_operand" "=r")
5377 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5379 "lea{l}\\t{%a1, %k0|%k0, %a1}"
5380 [(set_attr "type" "lea")
5381 (set_attr "mode" "SI")])
5383 (define_insn "*lea_2_rex64"
5384 [(set (match_operand:DI 0 "register_operand" "=r")
5385 (match_operand:DI 1 "address_operand" "p"))]
5387 "lea{q}\\t{%a1, %0|%0, %a1}"
5388 [(set_attr "type" "lea")
5389 (set_attr "mode" "DI")])
5391 ;; The lea patterns for non-Pmodes needs to be matched by several
5392 ;; insns converted to real lea by splitters.
5394 (define_insn_and_split "*lea_general_1"
5395 [(set (match_operand 0 "register_operand" "=r")
5396 (plus (plus (match_operand 1 "register_operand" "r")
5397 (match_operand 2 "register_operand" "r"))
5398 (match_operand 3 "immediate_operand" "i")))]
5399 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5400 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5401 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5402 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5403 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5404 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5405 || GET_MODE (operands[3]) == VOIDmode)"
5407 "&& reload_completed"
5412 operands[0] = gen_lowpart (SImode, operands[0]);
5413 operands[1] = gen_lowpart (Pmode, operands[1]);
5414 operands[2] = gen_lowpart (Pmode, operands[2]);
5415 operands[3] = gen_lowpart (Pmode, operands[3]);
5416 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5418 if (Pmode != SImode)
5419 pat = gen_rtx_SUBREG (SImode, pat, 0);
5420 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5423 [(set_attr "type" "lea")
5424 (set_attr "mode" "SI")])
5426 (define_insn_and_split "*lea_general_1_zext"
5427 [(set (match_operand:DI 0 "register_operand" "=r")
5429 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
5430 (match_operand:SI 2 "register_operand" "r"))
5431 (match_operand:SI 3 "immediate_operand" "i"))))]
5434 "&& reload_completed"
5436 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5438 (match_dup 3)) 0)))]
5441 operands[1] = gen_lowpart (Pmode, operands[1]);
5442 operands[2] = gen_lowpart (Pmode, operands[2]);
5443 operands[3] = gen_lowpart (Pmode, operands[3]);
5445 [(set_attr "type" "lea")
5446 (set_attr "mode" "SI")])
5448 (define_insn_and_split "*lea_general_2"
5449 [(set (match_operand 0 "register_operand" "=r")
5450 (plus (mult (match_operand 1 "register_operand" "r")
5451 (match_operand 2 "const248_operand" "i"))
5452 (match_operand 3 "nonmemory_operand" "ri")))]
5453 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5454 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5455 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5456 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5457 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5458 || GET_MODE (operands[3]) == VOIDmode)"
5460 "&& reload_completed"
5465 operands[0] = gen_lowpart (SImode, operands[0]);
5466 operands[1] = gen_lowpart (Pmode, operands[1]);
5467 operands[3] = gen_lowpart (Pmode, operands[3]);
5468 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5470 if (Pmode != SImode)
5471 pat = gen_rtx_SUBREG (SImode, pat, 0);
5472 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5475 [(set_attr "type" "lea")
5476 (set_attr "mode" "SI")])
5478 (define_insn_and_split "*lea_general_2_zext"
5479 [(set (match_operand:DI 0 "register_operand" "=r")
5481 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5482 (match_operand:SI 2 "const248_operand" "n"))
5483 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5486 "&& reload_completed"
5488 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5490 (match_dup 3)) 0)))]
5493 operands[1] = gen_lowpart (Pmode, operands[1]);
5494 operands[3] = gen_lowpart (Pmode, operands[3]);
5496 [(set_attr "type" "lea")
5497 (set_attr "mode" "SI")])
5499 (define_insn_and_split "*lea_general_3"
5500 [(set (match_operand 0 "register_operand" "=r")
5501 (plus (plus (mult (match_operand 1 "register_operand" "r")
5502 (match_operand 2 "const248_operand" "i"))
5503 (match_operand 3 "register_operand" "r"))
5504 (match_operand 4 "immediate_operand" "i")))]
5505 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5506 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5507 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5508 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5509 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5511 "&& reload_completed"
5516 operands[0] = gen_lowpart (SImode, operands[0]);
5517 operands[1] = gen_lowpart (Pmode, operands[1]);
5518 operands[3] = gen_lowpart (Pmode, operands[3]);
5519 operands[4] = gen_lowpart (Pmode, operands[4]);
5520 pat = gen_rtx_PLUS (Pmode,
5521 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5525 if (Pmode != SImode)
5526 pat = gen_rtx_SUBREG (SImode, pat, 0);
5527 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5530 [(set_attr "type" "lea")
5531 (set_attr "mode" "SI")])
5533 (define_insn_and_split "*lea_general_3_zext"
5534 [(set (match_operand:DI 0 "register_operand" "=r")
5536 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
5537 (match_operand:SI 2 "const248_operand" "n"))
5538 (match_operand:SI 3 "register_operand" "r"))
5539 (match_operand:SI 4 "immediate_operand" "i"))))]
5542 "&& reload_completed"
5544 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5547 (match_dup 4)) 0)))]
5550 operands[1] = gen_lowpart (Pmode, operands[1]);
5551 operands[3] = gen_lowpart (Pmode, operands[3]);
5552 operands[4] = gen_lowpart (Pmode, operands[4]);
5554 [(set_attr "type" "lea")
5555 (set_attr "mode" "SI")])
5557 (define_insn "*adddi_1_rex64"
5558 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5559 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5560 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5561 (clobber (reg:CC 17))]
5562 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5565 switch (get_attr_type (insn))
5568 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5569 return \"lea{q}\\t{%a2, %0|%0, %a2}\";
5572 if (! rtx_equal_p (operands[0], operands[1]))
5574 if (operands[2] == const1_rtx)
5575 return \"inc{q}\\t%0\";
5576 else if (operands[2] == constm1_rtx)
5577 return \"dec{q}\\t%0\";
5582 if (! rtx_equal_p (operands[0], operands[1]))
5585 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5586 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5587 if (GET_CODE (operands[2]) == CONST_INT
5588 && (INTVAL (operands[2]) == 128
5589 || (INTVAL (operands[2]) < 0
5590 && INTVAL (operands[2]) != -128)))
5592 operands[2] = GEN_INT (-INTVAL (operands[2]));
5593 return \"sub{q}\\t{%2, %0|%0, %2}\";
5595 return \"add{q}\\t{%2, %0|%0, %2}\";
5599 (cond [(eq_attr "alternative" "2")
5600 (const_string "lea")
5601 ; Current assemblers are broken and do not allow @GOTOFF in
5602 ; ought but a memory context.
5603 (match_operand:DI 2 "pic_symbolic_operand" "")
5604 (const_string "lea")
5605 (match_operand:DI 2 "incdec_operand" "")
5606 (const_string "incdec")
5608 (const_string "alu")))
5609 (set_attr "mode" "DI")])
5611 ;; Convert lea to the lea pattern to avoid flags dependency.
5613 [(set (match_operand:DI 0 "register_operand" "")
5614 (plus:DI (match_operand:DI 1 "register_operand" "")
5615 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5616 (clobber (reg:CC 17))]
5617 "reload_completed && TARGET_64BIT
5618 && true_regnum (operands[0]) != true_regnum (operands[1])"
5620 (plus:DI (match_dup 1)
5624 (define_insn "*adddi_2_rex64"
5627 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5628 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5630 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5631 (plus:DI (match_dup 1) (match_dup 2)))]
5632 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5633 && ix86_binary_operator_ok (PLUS, DImode, operands)
5634 /* Current assemblers are broken and do not allow @GOTOFF in
5635 ought but a memory context. */
5636 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5639 switch (get_attr_type (insn))
5642 if (! rtx_equal_p (operands[0], operands[1]))
5644 if (operands[2] == const1_rtx)
5645 return \"inc{q}\\t%0\";
5646 else if (operands[2] == constm1_rtx)
5647 return \"dec{q}\\t%0\";
5652 if (! rtx_equal_p (operands[0], operands[1]))
5654 /* ???? We ought to handle there the 32bit case too
5655 - do we need new constrant? */
5656 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5657 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5658 if (GET_CODE (operands[2]) == CONST_INT
5659 && (INTVAL (operands[2]) == 128
5660 || (INTVAL (operands[2]) < 0
5661 && INTVAL (operands[2]) != -128)))
5663 operands[2] = GEN_INT (-INTVAL (operands[2]));
5664 return \"sub{q}\\t{%2, %0|%0, %2}\";
5666 return \"add{q}\\t{%2, %0|%0, %2}\";
5670 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5671 (const_string "incdec")
5672 (const_string "alu")))
5673 (set_attr "mode" "DI")])
5675 (define_insn "*adddi_3_rex64"
5677 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5678 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5679 (clobber (match_scratch:DI 0 "=r"))]
5681 && ix86_match_ccmode (insn, CCZmode)
5682 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5683 /* Current assemblers are broken and do not allow @GOTOFF in
5684 ought but a memory context. */
5685 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5688 switch (get_attr_type (insn))
5691 if (! rtx_equal_p (operands[0], operands[1]))
5693 if (operands[2] == const1_rtx)
5694 return \"inc{q}\\t%0\";
5695 else if (operands[2] == constm1_rtx)
5696 return \"dec{q}\\t%0\";
5701 if (! rtx_equal_p (operands[0], operands[1]))
5703 /* ???? We ought to handle there the 32bit case too
5704 - do we need new constrant? */
5705 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5706 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5707 if (GET_CODE (operands[2]) == CONST_INT
5708 && (INTVAL (operands[2]) == 128
5709 || (INTVAL (operands[2]) < 0
5710 && INTVAL (operands[2]) != -128)))
5712 operands[2] = GEN_INT (-INTVAL (operands[2]));
5713 return \"sub{q}\\t{%2, %0|%0, %2}\";
5715 return \"add{q}\\t{%2, %0|%0, %2}\";
5719 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5720 (const_string "incdec")
5721 (const_string "alu")))
5722 (set_attr "mode" "DI")])
5724 ; For comparisons against 1, -1 and 128, we may generate better code
5725 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5726 ; is matched then. We can't accept general immediate, because for
5727 ; case of overflows, the result is messed up.
5728 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5730 ; Also carry flag is reversed compared to cmp, so this converison is valid
5731 ; only for comparisons not depending on it.
5732 (define_insn "*adddi_4_rex64"
5734 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5735 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5736 (clobber (match_scratch:DI 0 "=rm"))]
5738 && ix86_match_ccmode (insn, CCGCmode)"
5741 switch (get_attr_type (insn))
5744 if (operands[2] == constm1_rtx)
5745 return \"inc{q}\\t%0\";
5746 else if (operands[2] == const1_rtx)
5747 return \"dec{q}\\t%0\";
5752 if (! rtx_equal_p (operands[0], operands[1]))
5754 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5755 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5756 if ((INTVAL (operands[2]) == -128
5757 || (INTVAL (operands[2]) > 0
5758 && INTVAL (operands[2]) != 128)))
5759 return \"sub{q}\\t{%2, %0|%0, %2}\";
5760 operands[2] = GEN_INT (-INTVAL (operands[2]));
5761 return \"add{q}\\t{%2, %0|%0, %2}\";
5765 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5766 (const_string "incdec")
5767 (const_string "alu")))
5768 (set_attr "mode" "DI")])
5770 (define_insn "*adddi_5_rex64"
5773 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5774 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5776 (clobber (match_scratch:DI 0 "=r"))]
5778 && ix86_match_ccmode (insn, CCGOCmode)
5779 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5780 /* Current assemblers are broken and do not allow @GOTOFF in
5781 ought but a memory context. */
5782 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5785 switch (get_attr_type (insn))
5788 if (! rtx_equal_p (operands[0], operands[1]))
5790 if (operands[2] == const1_rtx)
5791 return \"inc{q}\\t%0\";
5792 else if (operands[2] == constm1_rtx)
5793 return \"dec{q}\\t%0\";
5798 if (! rtx_equal_p (operands[0], operands[1]))
5800 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5801 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5802 if (GET_CODE (operands[2]) == CONST_INT
5803 && (INTVAL (operands[2]) == 128
5804 || (INTVAL (operands[2]) < 0
5805 && INTVAL (operands[2]) != -128)))
5807 operands[2] = GEN_INT (-INTVAL (operands[2]));
5808 return \"sub{q}\\t{%2, %0|%0, %2}\";
5810 return \"add{q}\\t{%2, %0|%0, %2}\";
5814 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5815 (const_string "incdec")
5816 (const_string "alu")))
5817 (set_attr "mode" "DI")])
5820 (define_insn "*addsi_1"
5821 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5822 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5823 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5824 (clobber (reg:CC 17))]
5825 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5828 switch (get_attr_type (insn))
5831 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5832 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
5835 if (! rtx_equal_p (operands[0], operands[1]))
5837 if (operands[2] == const1_rtx)
5838 return \"inc{l}\\t%0\";
5839 else if (operands[2] == constm1_rtx)
5840 return \"dec{l}\\t%0\";
5845 if (! rtx_equal_p (operands[0], operands[1]))
5848 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5849 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5850 if (GET_CODE (operands[2]) == CONST_INT
5851 && (INTVAL (operands[2]) == 128
5852 || (INTVAL (operands[2]) < 0
5853 && INTVAL (operands[2]) != -128)))
5855 operands[2] = GEN_INT (-INTVAL (operands[2]));
5856 return \"sub{l}\\t{%2, %0|%0, %2}\";
5858 return \"add{l}\\t{%2, %0|%0, %2}\";
5862 (cond [(eq_attr "alternative" "2")
5863 (const_string "lea")
5864 ; Current assemblers are broken and do not allow @GOTOFF in
5865 ; ought but a memory context.
5866 (match_operand:SI 2 "pic_symbolic_operand" "")
5867 (const_string "lea")
5868 (match_operand:SI 2 "incdec_operand" "")
5869 (const_string "incdec")
5871 (const_string "alu")))
5872 (set_attr "mode" "SI")])
5874 ;; Convert lea to the lea pattern to avoid flags dependency.
5876 [(set (match_operand 0 "register_operand" "")
5877 (plus (match_operand 1 "register_operand" "")
5878 (match_operand 2 "nonmemory_operand" "")))
5879 (clobber (reg:CC 17))]
5881 && true_regnum (operands[0]) != true_regnum (operands[1])"
5886 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5887 may confuse gen_lowpart. */
5888 if (GET_MODE (operands[0]) != Pmode)
5890 operands[1] = gen_lowpart (Pmode, operands[1]);
5891 operands[2] = gen_lowpart (Pmode, operands[2]);
5893 operands[0] = gen_lowpart (SImode, operands[0]);
5894 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5895 if (Pmode != SImode)
5896 pat = gen_rtx_SUBREG (SImode, pat, 0);
5897 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5901 ;; It may seem that nonimmediate operand is proper one for operand 1.
5902 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5903 ;; we take care in ix86_binary_operator_ok to not allow two memory
5904 ;; operands so proper swapping will be done in reload. This allow
5905 ;; patterns constructed from addsi_1 to match.
5906 (define_insn "addsi_1_zext"
5907 [(set (match_operand:DI 0 "register_operand" "=r,r")
5909 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5910 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5911 (clobber (reg:CC 17))]
5912 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5915 switch (get_attr_type (insn))
5918 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5919 return \"lea{l}\\t{%a2, %k0|%k0, %a2}\";
5922 if (operands[2] == const1_rtx)
5923 return \"inc{l}\\t%k0\";
5924 else if (operands[2] == constm1_rtx)
5925 return \"dec{l}\\t%k0\";
5930 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5931 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5932 if (GET_CODE (operands[2]) == CONST_INT
5933 && (INTVAL (operands[2]) == 128
5934 || (INTVAL (operands[2]) < 0
5935 && INTVAL (operands[2]) != -128)))
5937 operands[2] = GEN_INT (-INTVAL (operands[2]));
5938 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5940 return \"add{l}\\t{%2, %k0|%k0, %2}\";
5944 (cond [(eq_attr "alternative" "1")
5945 (const_string "lea")
5946 ; Current assemblers are broken and do not allow @GOTOFF in
5947 ; ought but a memory context.
5948 (match_operand:SI 2 "pic_symbolic_operand" "")
5949 (const_string "lea")
5950 (match_operand:SI 2 "incdec_operand" "")
5951 (const_string "incdec")
5953 (const_string "alu")))
5954 (set_attr "mode" "SI")])
5956 ;; Convert lea to the lea pattern to avoid flags dependency.
5958 [(set (match_operand:DI 0 "register_operand" "")
5960 (plus:SI (match_operand:SI 1 "register_operand" "")
5961 (match_operand:SI 2 "nonmemory_operand" ""))))
5962 (clobber (reg:CC 17))]
5964 && true_regnum (operands[0]) != true_regnum (operands[1])"
5966 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5969 operands[1] = gen_lowpart (Pmode, operands[1]);
5970 operands[2] = gen_lowpart (Pmode, operands[2]);
5973 (define_insn "*addsi_2"
5976 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5977 (match_operand:SI 2 "general_operand" "rmni,rni"))
5979 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5980 (plus:SI (match_dup 1) (match_dup 2)))]
5981 "ix86_match_ccmode (insn, CCGOCmode)
5982 && ix86_binary_operator_ok (PLUS, SImode, operands)
5983 /* Current assemblers are broken and do not allow @GOTOFF in
5984 ought but a memory context. */
5985 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5988 switch (get_attr_type (insn))
5991 if (! rtx_equal_p (operands[0], operands[1]))
5993 if (operands[2] == const1_rtx)
5994 return \"inc{l}\\t%0\";
5995 else if (operands[2] == constm1_rtx)
5996 return \"dec{l}\\t%0\";
6001 if (! rtx_equal_p (operands[0], operands[1]))
6003 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6004 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6005 if (GET_CODE (operands[2]) == CONST_INT
6006 && (INTVAL (operands[2]) == 128
6007 || (INTVAL (operands[2]) < 0
6008 && INTVAL (operands[2]) != -128)))
6010 operands[2] = GEN_INT (-INTVAL (operands[2]));
6011 return \"sub{l}\\t{%2, %0|%0, %2}\";
6013 return \"add{l}\\t{%2, %0|%0, %2}\";
6017 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6018 (const_string "incdec")
6019 (const_string "alu")))
6020 (set_attr "mode" "SI")])
6022 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6023 (define_insn "*addsi_2_zext"
6026 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6027 (match_operand:SI 2 "general_operand" "rmni"))
6029 (set (match_operand:DI 0 "register_operand" "=r")
6030 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6031 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6032 && ix86_binary_operator_ok (PLUS, SImode, operands)
6033 /* Current assemblers are broken and do not allow @GOTOFF in
6034 ought but a memory context. */
6035 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6038 switch (get_attr_type (insn))
6041 if (operands[2] == const1_rtx)
6042 return \"inc{l}\\t%k0\";
6043 else if (operands[2] == constm1_rtx)
6044 return \"dec{l}\\t%k0\";
6049 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6050 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6051 if (GET_CODE (operands[2]) == CONST_INT
6052 && (INTVAL (operands[2]) == 128
6053 || (INTVAL (operands[2]) < 0
6054 && INTVAL (operands[2]) != -128)))
6056 operands[2] = GEN_INT (-INTVAL (operands[2]));
6057 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6059 return \"add{l}\\t{%2, %k0|%k0, %2}\";
6063 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6064 (const_string "incdec")
6065 (const_string "alu")))
6066 (set_attr "mode" "SI")])
6068 (define_insn "*addsi_3"
6070 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6071 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6072 (clobber (match_scratch:SI 0 "=r"))]
6073 "ix86_match_ccmode (insn, CCZmode)
6074 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6075 /* Current assemblers are broken and do not allow @GOTOFF in
6076 ought but a memory context. */
6077 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6080 switch (get_attr_type (insn))
6083 if (! rtx_equal_p (operands[0], operands[1]))
6085 if (operands[2] == const1_rtx)
6086 return \"inc{l}\\t%0\";
6087 else if (operands[2] == constm1_rtx)
6088 return \"dec{l}\\t%0\";
6093 if (! rtx_equal_p (operands[0], operands[1]))
6095 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6096 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6097 if (GET_CODE (operands[2]) == CONST_INT
6098 && (INTVAL (operands[2]) == 128
6099 || (INTVAL (operands[2]) < 0
6100 && INTVAL (operands[2]) != -128)))
6102 operands[2] = GEN_INT (-INTVAL (operands[2]));
6103 return \"sub{l}\\t{%2, %0|%0, %2}\";
6105 return \"add{l}\\t{%2, %0|%0, %2}\";
6109 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6110 (const_string "incdec")
6111 (const_string "alu")))
6112 (set_attr "mode" "SI")])
6114 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6115 (define_insn "*addsi_3_zext"
6117 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6118 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6119 (set (match_operand:DI 0 "register_operand" "=r")
6120 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6121 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6122 && ix86_binary_operator_ok (PLUS, SImode, operands)
6123 /* Current assemblers are broken and do not allow @GOTOFF in
6124 ought but a memory context. */
6125 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6128 switch (get_attr_type (insn))
6131 if (operands[2] == const1_rtx)
6132 return \"inc{l}\\t%k0\";
6133 else if (operands[2] == constm1_rtx)
6134 return \"dec{l}\\t%k0\";
6139 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6140 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6141 if (GET_CODE (operands[2]) == CONST_INT
6142 && (INTVAL (operands[2]) == 128
6143 || (INTVAL (operands[2]) < 0
6144 && INTVAL (operands[2]) != -128)))
6146 operands[2] = GEN_INT (-INTVAL (operands[2]));
6147 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6149 return \"add{l}\\t{%2, %k0|%k0, %2}\";
6153 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6154 (const_string "incdec")
6155 (const_string "alu")))
6156 (set_attr "mode" "SI")])
6158 ; For comparisons agains 1, -1 and 128, we may generate better code
6159 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6160 ; is matched then. We can't accept general immediate, because for
6161 ; case of overflows, the result is messed up.
6162 ; This pattern also don't hold of 0x80000000, since the value overflows
6164 ; Also carry flag is reversed compared to cmp, so this converison is valid
6165 ; only for comparisons not depending on it.
6166 (define_insn "*addsi_4"
6168 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6169 (match_operand:SI 2 "const_int_operand" "n")))
6170 (clobber (match_scratch:SI 0 "=rm"))]
6171 "ix86_match_ccmode (insn, CCGCmode)
6172 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6175 switch (get_attr_type (insn))
6178 if (operands[2] == constm1_rtx)
6179 return \"inc{l}\\t%0\";
6180 else if (operands[2] == const1_rtx)
6181 return \"dec{l}\\t%0\";
6186 if (! rtx_equal_p (operands[0], operands[1]))
6188 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6189 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6190 if ((INTVAL (operands[2]) == -128
6191 || (INTVAL (operands[2]) > 0
6192 && INTVAL (operands[2]) != 128)))
6193 return \"sub{l}\\t{%2, %0|%0, %2}\";
6194 operands[2] = GEN_INT (-INTVAL (operands[2]));
6195 return \"add{l}\\t{%2, %0|%0, %2}\";
6199 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6200 (const_string "incdec")
6201 (const_string "alu")))
6202 (set_attr "mode" "SI")])
6204 (define_insn "*addsi_5"
6207 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6208 (match_operand:SI 2 "general_operand" "rmni"))
6210 (clobber (match_scratch:SI 0 "=r"))]
6211 "ix86_match_ccmode (insn, CCGOCmode)
6212 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6213 /* Current assemblers are broken and do not allow @GOTOFF in
6214 ought but a memory context. */
6215 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6218 switch (get_attr_type (insn))
6221 if (! rtx_equal_p (operands[0], operands[1]))
6223 if (operands[2] == const1_rtx)
6224 return \"inc{l}\\t%0\";
6225 else if (operands[2] == constm1_rtx)
6226 return \"dec{l}\\t%0\";
6231 if (! rtx_equal_p (operands[0], operands[1]))
6233 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6234 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6235 if (GET_CODE (operands[2]) == CONST_INT
6236 && (INTVAL (operands[2]) == 128
6237 || (INTVAL (operands[2]) < 0
6238 && INTVAL (operands[2]) != -128)))
6240 operands[2] = GEN_INT (-INTVAL (operands[2]));
6241 return \"sub{l}\\t{%2, %0|%0, %2}\";
6243 return \"add{l}\\t{%2, %0|%0, %2}\";
6247 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6248 (const_string "incdec")
6249 (const_string "alu")))
6250 (set_attr "mode" "SI")])
6252 (define_expand "addhi3"
6253 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6254 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6255 (match_operand:HI 2 "general_operand" "")))
6256 (clobber (reg:CC 17))])]
6257 "TARGET_HIMODE_MATH"
6258 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6260 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6261 ;; type optimizations enabled by define-splits. This is not important
6262 ;; for PII, and in fact harmful because of partial register stalls.
6264 (define_insn "*addhi_1_lea"
6265 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6266 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6267 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6268 (clobber (reg:CC 17))]
6269 "!TARGET_PARTIAL_REG_STALL
6270 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6273 switch (get_attr_type (insn))
6278 if (operands[2] == const1_rtx)
6279 return \"inc{w}\\t%0\";
6280 else if (operands[2] == constm1_rtx
6281 || (GET_CODE (operands[2]) == CONST_INT
6282 && INTVAL (operands[2]) == 65535))
6283 return \"dec{w}\\t%0\";
6287 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6288 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6289 if (GET_CODE (operands[2]) == CONST_INT
6290 && (INTVAL (operands[2]) == 128
6291 || (INTVAL (operands[2]) < 0
6292 && INTVAL (operands[2]) != -128)))
6294 operands[2] = GEN_INT (-INTVAL (operands[2]));
6295 return \"sub{w}\\t{%2, %0|%0, %2}\";
6297 return \"add{w}\\t{%2, %0|%0, %2}\";
6301 (if_then_else (eq_attr "alternative" "2")
6302 (const_string "lea")
6303 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6304 (const_string "incdec")
6305 (const_string "alu"))))
6306 (set_attr "mode" "HI,HI,SI")])
6308 (define_insn "*addhi_1"
6309 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6310 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6311 (match_operand:HI 2 "general_operand" "ri,rm")))
6312 (clobber (reg:CC 17))]
6313 "TARGET_PARTIAL_REG_STALL
6314 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6317 switch (get_attr_type (insn))
6320 if (operands[2] == const1_rtx)
6321 return \"inc{w}\\t%0\";
6322 else if (operands[2] == constm1_rtx
6323 || (GET_CODE (operands[2]) == CONST_INT
6324 && INTVAL (operands[2]) == 65535))
6325 return \"dec{w}\\t%0\";
6329 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6330 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6331 if (GET_CODE (operands[2]) == CONST_INT
6332 && (INTVAL (operands[2]) == 128
6333 || (INTVAL (operands[2]) < 0
6334 && INTVAL (operands[2]) != -128)))
6336 operands[2] = GEN_INT (-INTVAL (operands[2]));
6337 return \"sub{w}\\t{%2, %0|%0, %2}\";
6339 return \"add{w}\\t{%2, %0|%0, %2}\";
6343 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6344 (const_string "incdec")
6345 (const_string "alu")))
6346 (set_attr "mode" "HI")])
6348 (define_insn "*addhi_2"
6351 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6352 (match_operand:HI 2 "general_operand" "rmni,rni"))
6354 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6355 (plus:HI (match_dup 1) (match_dup 2)))]
6356 "ix86_match_ccmode (insn, CCGOCmode)
6357 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6360 switch (get_attr_type (insn))
6363 if (operands[2] == const1_rtx)
6364 return \"inc{w}\\t%0\";
6365 else if (operands[2] == constm1_rtx
6366 || (GET_CODE (operands[2]) == CONST_INT
6367 && INTVAL (operands[2]) == 65535))
6368 return \"dec{w}\\t%0\";
6372 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6373 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6374 if (GET_CODE (operands[2]) == CONST_INT
6375 && (INTVAL (operands[2]) == 128
6376 || (INTVAL (operands[2]) < 0
6377 && INTVAL (operands[2]) != -128)))
6379 operands[2] = GEN_INT (-INTVAL (operands[2]));
6380 return \"sub{w}\\t{%2, %0|%0, %2}\";
6382 return \"add{w}\\t{%2, %0|%0, %2}\";
6386 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6387 (const_string "incdec")
6388 (const_string "alu")))
6389 (set_attr "mode" "HI")])
6391 (define_insn "*addhi_3"
6393 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6394 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6395 (clobber (match_scratch:HI 0 "=r"))]
6396 "ix86_match_ccmode (insn, CCZmode)
6397 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6400 switch (get_attr_type (insn))
6403 if (operands[2] == const1_rtx)
6404 return \"inc{w}\\t%0\";
6405 else if (operands[2] == constm1_rtx
6406 || (GET_CODE (operands[2]) == CONST_INT
6407 && INTVAL (operands[2]) == 65535))
6408 return \"dec{w}\\t%0\";
6412 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6413 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6414 if (GET_CODE (operands[2]) == CONST_INT
6415 && (INTVAL (operands[2]) == 128
6416 || (INTVAL (operands[2]) < 0
6417 && INTVAL (operands[2]) != -128)))
6419 operands[2] = GEN_INT (-INTVAL (operands[2]));
6420 return \"sub{w}\\t{%2, %0|%0, %2}\";
6422 return \"add{w}\\t{%2, %0|%0, %2}\";
6426 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6427 (const_string "incdec")
6428 (const_string "alu")))
6429 (set_attr "mode" "HI")])
6431 ; See comments above addsi_3_imm for details.
6432 (define_insn "*addhi_4"
6434 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6435 (match_operand:HI 2 "const_int_operand" "n")))
6436 (clobber (match_scratch:HI 0 "=rm"))]
6437 "ix86_match_ccmode (insn, CCGCmode)
6438 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6441 switch (get_attr_type (insn))
6444 if (operands[2] == constm1_rtx
6445 || (GET_CODE (operands[2]) == CONST_INT
6446 && INTVAL (operands[2]) == 65535))
6447 return \"inc{w}\\t%0\";
6448 else if (operands[2] == const1_rtx)
6449 return \"dec{w}\\t%0\";
6454 if (! rtx_equal_p (operands[0], operands[1]))
6456 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6457 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6458 if ((INTVAL (operands[2]) == -128
6459 || (INTVAL (operands[2]) > 0
6460 && INTVAL (operands[2]) != 128)))
6461 return \"sub{w}\\t{%2, %0|%0, %2}\";
6462 operands[2] = GEN_INT (-INTVAL (operands[2]));
6463 return \"add{w}\\t{%2, %0|%0, %2}\";
6467 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6468 (const_string "incdec")
6469 (const_string "alu")))
6470 (set_attr "mode" "SI")])
6473 (define_insn "*addhi_5"
6476 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6477 (match_operand:HI 2 "general_operand" "rmni"))
6479 (clobber (match_scratch:HI 0 "=r"))]
6480 "ix86_match_ccmode (insn, CCGOCmode)
6481 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6484 switch (get_attr_type (insn))
6487 if (operands[2] == const1_rtx)
6488 return \"inc{w}\\t%0\";
6489 else if (operands[2] == constm1_rtx
6490 || (GET_CODE (operands[2]) == CONST_INT
6491 && INTVAL (operands[2]) == 65535))
6492 return \"dec{w}\\t%0\";
6496 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6497 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6498 if (GET_CODE (operands[2]) == CONST_INT
6499 && (INTVAL (operands[2]) == 128
6500 || (INTVAL (operands[2]) < 0
6501 && INTVAL (operands[2]) != -128)))
6503 operands[2] = GEN_INT (-INTVAL (operands[2]));
6504 return \"sub{w}\\t{%2, %0|%0, %2}\";
6506 return \"add{w}\\t{%2, %0|%0, %2}\";
6510 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6511 (const_string "incdec")
6512 (const_string "alu")))
6513 (set_attr "mode" "HI")])
6515 (define_expand "addqi3"
6516 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6517 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6518 (match_operand:QI 2 "general_operand" "")))
6519 (clobber (reg:CC 17))])]
6520 "TARGET_QIMODE_MATH"
6521 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6523 ;; %%% Potential partial reg stall on alternative 2. What to do?
6524 (define_insn "*addqi_1_lea"
6525 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6526 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6527 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6528 (clobber (reg:CC 17))]
6529 "!TARGET_PARTIAL_REG_STALL
6530 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6533 int widen = (which_alternative == 2);
6534 switch (get_attr_type (insn))
6539 if (operands[2] == const1_rtx)
6540 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
6541 else if (operands[2] == constm1_rtx
6542 || (GET_CODE (operands[2]) == CONST_INT
6543 && INTVAL (operands[2]) == 255))
6544 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
6548 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6549 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6550 if (GET_CODE (operands[2]) == CONST_INT
6551 && (INTVAL (operands[2]) == 128
6552 || (INTVAL (operands[2]) < 0
6553 && INTVAL (operands[2]) != -128)))
6555 operands[2] = GEN_INT (-INTVAL (operands[2]));
6557 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6559 return \"sub{b}\\t{%2, %0|%0, %2}\";
6562 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
6564 return \"add{b}\\t{%2, %0|%0, %2}\";
6568 (if_then_else (eq_attr "alternative" "3")
6569 (const_string "lea")
6570 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6571 (const_string "incdec")
6572 (const_string "alu"))))
6573 (set_attr "mode" "QI,QI,SI,SI")])
6575 (define_insn "*addqi_1"
6576 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6577 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6578 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6579 (clobber (reg:CC 17))]
6580 "TARGET_PARTIAL_REG_STALL
6581 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6584 int widen = (which_alternative == 2);
6585 switch (get_attr_type (insn))
6588 if (operands[2] == const1_rtx)
6589 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
6590 else if (operands[2] == constm1_rtx
6591 || (GET_CODE (operands[2]) == CONST_INT
6592 && INTVAL (operands[2]) == 255))
6593 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
6597 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6598 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6599 if (GET_CODE (operands[2]) == CONST_INT
6600 && (INTVAL (operands[2]) == 128
6601 || (INTVAL (operands[2]) < 0
6602 && INTVAL (operands[2]) != -128)))
6604 operands[2] = GEN_INT (-INTVAL (operands[2]));
6606 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6608 return \"sub{b}\\t{%2, %0|%0, %2}\";
6611 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
6613 return \"add{b}\\t{%2, %0|%0, %2}\";
6617 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6618 (const_string "incdec")
6619 (const_string "alu")))
6620 (set_attr "mode" "QI,QI,SI")])
6622 (define_insn "*addqi_2"
6625 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6626 (match_operand:QI 2 "general_operand" "qmni,qni"))
6628 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6629 (plus:QI (match_dup 1) (match_dup 2)))]
6630 "ix86_match_ccmode (insn, CCGOCmode)
6631 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6634 switch (get_attr_type (insn))
6637 if (operands[2] == const1_rtx)
6638 return \"inc{b}\\t%0\";
6639 else if (operands[2] == constm1_rtx
6640 || (GET_CODE (operands[2]) == CONST_INT
6641 && INTVAL (operands[2]) == 255))
6642 return \"dec{b}\\t%0\";
6646 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6647 if (GET_CODE (operands[2]) == CONST_INT
6648 && INTVAL (operands[2]) < 0)
6650 operands[2] = GEN_INT (-INTVAL (operands[2]));
6651 return \"sub{b}\\t{%2, %0|%0, %2}\";
6653 return \"add{b}\\t{%2, %0|%0, %2}\";
6657 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6658 (const_string "incdec")
6659 (const_string "alu")))
6660 (set_attr "mode" "QI")])
6662 (define_insn "*addqi_3"
6664 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6665 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6666 (clobber (match_scratch:QI 0 "=q"))]
6667 "ix86_match_ccmode (insn, CCZmode)
6668 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6671 switch (get_attr_type (insn))
6674 if (operands[2] == const1_rtx)
6675 return \"inc{b}\\t%0\";
6676 else if (operands[2] == constm1_rtx
6677 || (GET_CODE (operands[2]) == CONST_INT
6678 && INTVAL (operands[2]) == 255))
6679 return \"dec{b}\\t%0\";
6683 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6684 if (GET_CODE (operands[2]) == CONST_INT
6685 && INTVAL (operands[2]) < 0)
6687 operands[2] = GEN_INT (-INTVAL (operands[2]));
6688 return \"sub{b}\\t{%2, %0|%0, %2}\";
6690 return \"add{b}\\t{%2, %0|%0, %2}\";
6694 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6695 (const_string "incdec")
6696 (const_string "alu")))
6697 (set_attr "mode" "QI")])
6699 ; See comments above addsi_3_imm for details.
6700 (define_insn "*addqi_4"
6702 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6703 (match_operand:QI 2 "const_int_operand" "n")))
6704 (clobber (match_scratch:QI 0 "=qm"))]
6705 "ix86_match_ccmode (insn, CCGCmode)
6706 && (INTVAL (operands[2]) & 0xff) != 0x80"
6709 switch (get_attr_type (insn))
6712 if (operands[2] == constm1_rtx
6713 || (GET_CODE (operands[2]) == CONST_INT
6714 && INTVAL (operands[2]) == 255))
6715 return \"inc{b}\\t%0\";
6716 else if (operands[2] == const1_rtx)
6717 return \"dec{b}\\t%0\";
6722 if (! rtx_equal_p (operands[0], operands[1]))
6724 if (INTVAL (operands[2]) < 0)
6726 operands[2] = GEN_INT (-INTVAL (operands[2]));
6727 return \"add{b}\\t{%2, %0|%0, %2}\";
6729 return \"sub{b}\\t{%2, %0|%0, %2}\";
6733 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6734 (const_string "incdec")
6735 (const_string "alu")))
6736 (set_attr "mode" "QI")])
6739 (define_insn "*addqi_5"
6742 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6743 (match_operand:QI 2 "general_operand" "qmni"))
6745 (clobber (match_scratch:QI 0 "=q"))]
6746 "ix86_match_ccmode (insn, CCGOCmode)
6747 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6750 switch (get_attr_type (insn))
6753 if (operands[2] == const1_rtx)
6754 return \"inc{b}\\t%0\";
6755 else if (operands[2] == constm1_rtx
6756 || (GET_CODE (operands[2]) == CONST_INT
6757 && INTVAL (operands[2]) == 255))
6758 return \"dec{b}\\t%0\";
6762 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6763 if (GET_CODE (operands[2]) == CONST_INT
6764 && INTVAL (operands[2]) < 0)
6766 operands[2] = GEN_INT (-INTVAL (operands[2]));
6767 return \"sub{b}\\t{%2, %0|%0, %2}\";
6769 return \"add{b}\\t{%2, %0|%0, %2}\";
6773 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6774 (const_string "incdec")
6775 (const_string "alu")))
6776 (set_attr "mode" "QI")])
6779 (define_insn "addqi_ext_1"
6780 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6785 (match_operand 1 "ext_register_operand" "0")
6788 (match_operand:QI 2 "general_operand" "qmn")))
6789 (clobber (reg:CC 17))]
6793 switch (get_attr_type (insn))
6796 if (operands[2] == const1_rtx)
6797 return \"inc{b}\\t%h0\";
6798 else if (operands[2] == constm1_rtx
6799 || (GET_CODE (operands[2]) == CONST_INT
6800 && INTVAL (operands[2]) == 255))
6801 return \"dec{b}\\t%h0\";
6805 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6809 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6810 (const_string "incdec")
6811 (const_string "alu")))
6812 (set_attr "mode" "QI")])
6814 (define_insn "*addqi_ext_1_rex64"
6815 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6820 (match_operand 1 "ext_register_operand" "0")
6823 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6824 (clobber (reg:CC 17))]
6828 switch (get_attr_type (insn))
6831 if (operands[2] == const1_rtx)
6832 return \"inc{b}\\t%h0\";
6833 else if (operands[2] == constm1_rtx
6834 || (GET_CODE (operands[2]) == CONST_INT
6835 && INTVAL (operands[2]) == 255))
6836 return \"dec{b}\\t%h0\";
6840 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6844 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6845 (const_string "incdec")
6846 (const_string "alu")))
6847 (set_attr "mode" "QI")])
6849 (define_insn "*addqi_ext_2"
6850 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6855 (match_operand 1 "ext_register_operand" "%0")
6859 (match_operand 2 "ext_register_operand" "Q")
6862 (clobber (reg:CC 17))]
6864 "add{b}\\t{%h2, %h0|%h0, %h2}"
6865 [(set_attr "type" "alu")
6866 (set_attr "mode" "QI")])
6868 ;; The patterns that match these are at the end of this file.
6870 (define_expand "addxf3"
6871 [(set (match_operand:XF 0 "register_operand" "")
6872 (plus:XF (match_operand:XF 1 "register_operand" "")
6873 (match_operand:XF 2 "register_operand" "")))]
6874 "TARGET_80387 && !TARGET_64BIT"
6877 (define_expand "addtf3"
6878 [(set (match_operand:TF 0 "register_operand" "")
6879 (plus:TF (match_operand:TF 1 "register_operand" "")
6880 (match_operand:TF 2 "register_operand" "")))]
6884 (define_expand "adddf3"
6885 [(set (match_operand:DF 0 "register_operand" "")
6886 (plus:DF (match_operand:DF 1 "register_operand" "")
6887 (match_operand:DF 2 "nonimmediate_operand" "")))]
6888 "TARGET_80387 || TARGET_SSE2"
6891 (define_expand "addsf3"
6892 [(set (match_operand:SF 0 "register_operand" "")
6893 (plus:SF (match_operand:SF 1 "register_operand" "")
6894 (match_operand:SF 2 "nonimmediate_operand" "")))]
6895 "TARGET_80387 || TARGET_SSE"
6898 ;; Subtract instructions
6900 ;; %%% splits for subsidi3
6902 (define_expand "subdi3"
6903 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6904 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6905 (match_operand:DI 2 "x86_64_general_operand" "")))
6906 (clobber (reg:CC 17))])]
6908 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6910 (define_insn "*subdi3_1"
6911 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6912 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6913 (match_operand:DI 2 "general_operand" "roiF,riF")))
6914 (clobber (reg:CC 17))]
6919 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6920 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6921 (match_operand:DI 2 "general_operand" "")))
6922 (clobber (reg:CC 17))]
6923 "reload_completed && !TARGET_64BIT"
6924 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6925 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6926 (parallel [(set (match_dup 3)
6927 (minus:SI (match_dup 4)
6928 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6930 (clobber (reg:CC 17))])]
6931 "split_di (operands+0, 1, operands+0, operands+3);
6932 split_di (operands+1, 1, operands+1, operands+4);
6933 split_di (operands+2, 1, operands+2, operands+5);")
6935 (define_insn "subdi3_carry_rex64"
6936 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6937 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6938 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6939 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6940 (clobber (reg:CC 17))]
6941 "ix86_binary_operator_ok (MINUS, DImode, operands)"
6942 "sbb{q}\\t{%2, %0|%0, %2}"
6943 [(set_attr "type" "alu")
6944 (set_attr "pent_pair" "pu")
6945 (set_attr "ppro_uops" "few")
6946 (set_attr "mode" "DI")])
6948 (define_insn "*subdi_1_rex64"
6949 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6950 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6951 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6952 (clobber (reg:CC 17))]
6953 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6954 "sub{q}\\t{%2, %0|%0, %2}"
6955 [(set_attr "type" "alu")
6956 (set_attr "mode" "DI")])
6958 (define_insn "*subdi_2_rex64"
6961 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6962 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6964 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6965 (minus:DI (match_dup 1) (match_dup 2)))]
6966 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6967 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6968 "sub{q}\\t{%2, %0|%0, %2}"
6969 [(set_attr "type" "alu")
6970 (set_attr "mode" "DI")])
6972 (define_insn "*subdi_3_rex63"
6974 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6975 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6976 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6977 (minus:DI (match_dup 1) (match_dup 2)))]
6978 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6979 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6980 "sub{q}\\t{%2, %0|%0, %2}"
6981 [(set_attr "type" "alu")
6982 (set_attr "mode" "DI")])
6985 (define_insn "subsi3_carry"
6986 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6987 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6988 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6989 (match_operand:SI 2 "general_operand" "ri,rm"))))
6990 (clobber (reg:CC 17))]
6991 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6992 "sbb{l}\\t{%2, %0|%0, %2}"
6993 [(set_attr "type" "alu")
6994 (set_attr "pent_pair" "pu")
6995 (set_attr "ppro_uops" "few")
6996 (set_attr "mode" "SI")])
6998 (define_insn "subsi3_carry_zext"
6999 [(set (match_operand:DI 0 "register_operand" "=rm,r")
7001 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
7002 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
7003 (match_operand:SI 2 "general_operand" "ri,rm")))))
7004 (clobber (reg:CC 17))]
7005 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7006 "sbb{l}\\t{%2, %k0|%k0, %2}"
7007 [(set_attr "type" "alu")
7008 (set_attr "pent_pair" "pu")
7009 (set_attr "ppro_uops" "few")
7010 (set_attr "mode" "SI")])
7012 (define_expand "subsi3"
7013 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
7014 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
7015 (match_operand:SI 2 "general_operand" "")))
7016 (clobber (reg:CC 17))])]
7018 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
7020 (define_insn "*subsi_1"
7021 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7022 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7023 (match_operand:SI 2 "general_operand" "ri,rm")))
7024 (clobber (reg:CC 17))]
7025 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7026 "sub{l}\\t{%2, %0|%0, %2}"
7027 [(set_attr "type" "alu")
7028 (set_attr "mode" "SI")])
7030 (define_insn "*subsi_1_zext"
7031 [(set (match_operand:DI 0 "register_operand" "=r")
7033 (minus:SI (match_operand:SI 1 "register_operand" "0")
7034 (match_operand:SI 2 "general_operand" "rim"))))
7035 (clobber (reg:CC 17))]
7036 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7037 "sub{l}\\t{%2, %k0|%k0, %2}"
7038 [(set_attr "type" "alu")
7039 (set_attr "mode" "SI")])
7041 (define_insn "*subsi_2"
7044 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7045 (match_operand:SI 2 "general_operand" "ri,rm"))
7047 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7048 (minus:SI (match_dup 1) (match_dup 2)))]
7049 "ix86_match_ccmode (insn, CCGOCmode)
7050 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7051 "sub{l}\\t{%2, %0|%0, %2}"
7052 [(set_attr "type" "alu")
7053 (set_attr "mode" "SI")])
7055 (define_insn "*subsi_2_zext"
7058 (minus:SI (match_operand:SI 1 "register_operand" "0")
7059 (match_operand:SI 2 "general_operand" "rim"))
7061 (set (match_operand:DI 0 "register_operand" "=r")
7063 (minus:SI (match_dup 1)
7065 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7066 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7067 "sub{l}\\t{%2, %k0|%k0, %2}"
7068 [(set_attr "type" "alu")
7069 (set_attr "mode" "SI")])
7071 (define_insn "*subsi_3"
7073 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7074 (match_operand:SI 2 "general_operand" "ri,rm")))
7075 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7076 (minus:SI (match_dup 1) (match_dup 2)))]
7077 "ix86_match_ccmode (insn, CCmode)
7078 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7079 "sub{l}\\t{%2, %0|%0, %2}"
7080 [(set_attr "type" "alu")
7081 (set_attr "mode" "SI")])
7083 (define_insn "*subsi_3_zext"
7085 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
7086 (match_operand:SI 2 "general_operand" "rim")))
7087 (set (match_operand:DI 0 "register_operand" "=r")
7089 (minus:SI (match_dup 1)
7091 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7092 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7093 "sub{q}\\t{%2, %0|%0, %2}"
7094 [(set_attr "type" "alu")
7095 (set_attr "mode" "DI")])
7097 (define_expand "subhi3"
7098 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7099 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7100 (match_operand:HI 2 "general_operand" "")))
7101 (clobber (reg:CC 17))])]
7102 "TARGET_HIMODE_MATH"
7103 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7105 (define_insn "*subhi_1"
7106 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7107 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7108 (match_operand:HI 2 "general_operand" "ri,rm")))
7109 (clobber (reg:CC 17))]
7110 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7111 "sub{w}\\t{%2, %0|%0, %2}"
7112 [(set_attr "type" "alu")
7113 (set_attr "mode" "HI")])
7115 (define_insn "*subhi_2"
7118 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7119 (match_operand:HI 2 "general_operand" "ri,rm"))
7121 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7122 (minus:HI (match_dup 1) (match_dup 2)))]
7123 "ix86_match_ccmode (insn, CCGOCmode)
7124 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7125 "sub{w}\\t{%2, %0|%0, %2}"
7126 [(set_attr "type" "alu")
7127 (set_attr "mode" "HI")])
7129 (define_insn "*subhi_3"
7131 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7132 (match_operand:HI 2 "general_operand" "ri,rm")))
7133 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7134 (minus:HI (match_dup 1) (match_dup 2)))]
7135 "ix86_match_ccmode (insn, CCmode)
7136 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7137 "sub{w}\\t{%2, %0|%0, %2}"
7138 [(set_attr "type" "alu")
7139 (set_attr "mode" "HI")])
7141 (define_expand "subqi3"
7142 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7143 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7144 (match_operand:QI 2 "general_operand" "")))
7145 (clobber (reg:CC 17))])]
7146 "TARGET_QIMODE_MATH"
7147 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7149 (define_insn "*subqi_1"
7150 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7151 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7152 (match_operand:QI 2 "general_operand" "qn,qmn")))
7153 (clobber (reg:CC 17))]
7154 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7155 "sub{b}\\t{%2, %0|%0, %2}"
7156 [(set_attr "type" "alu")
7157 (set_attr "mode" "QI")])
7159 (define_insn "*subqi_2"
7162 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7163 (match_operand:QI 2 "general_operand" "qi,qm"))
7165 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7166 (minus:HI (match_dup 1) (match_dup 2)))]
7167 "ix86_match_ccmode (insn, CCGOCmode)
7168 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7169 "sub{b}\\t{%2, %0|%0, %2}"
7170 [(set_attr "type" "alu")
7171 (set_attr "mode" "QI")])
7173 (define_insn "*subqi_3"
7175 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7176 (match_operand:QI 2 "general_operand" "qi,qm")))
7177 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7178 (minus:HI (match_dup 1) (match_dup 2)))]
7179 "ix86_match_ccmode (insn, CCmode)
7180 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7181 "sub{b}\\t{%2, %0|%0, %2}"
7182 [(set_attr "type" "alu")
7183 (set_attr "mode" "QI")])
7185 ;; The patterns that match these are at the end of this file.
7187 (define_expand "subxf3"
7188 [(set (match_operand:XF 0 "register_operand" "")
7189 (minus:XF (match_operand:XF 1 "register_operand" "")
7190 (match_operand:XF 2 "register_operand" "")))]
7191 "TARGET_80387 && !TARGET_64BIT"
7194 (define_expand "subtf3"
7195 [(set (match_operand:TF 0 "register_operand" "")
7196 (minus:TF (match_operand:TF 1 "register_operand" "")
7197 (match_operand:TF 2 "register_operand" "")))]
7201 (define_expand "subdf3"
7202 [(set (match_operand:DF 0 "register_operand" "")
7203 (minus:DF (match_operand:DF 1 "register_operand" "")
7204 (match_operand:DF 2 "nonimmediate_operand" "")))]
7205 "TARGET_80387 || TARGET_SSE2"
7208 (define_expand "subsf3"
7209 [(set (match_operand:SF 0 "register_operand" "")
7210 (minus:SF (match_operand:SF 1 "register_operand" "")
7211 (match_operand:SF 2 "nonimmediate_operand" "")))]
7212 "TARGET_80387 || TARGET_SSE"
7215 ;; Multiply instructions
7217 (define_expand "muldi3"
7218 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7219 (mult:DI (match_operand:DI 1 "register_operand" "")
7220 (match_operand:DI 2 "x86_64_general_operand" "")))
7221 (clobber (reg:CC 17))])]
7225 (define_insn "*muldi3_1_rex64"
7226 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7227 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
7228 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7229 (clobber (reg:CC 17))]
7230 "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
7233 imul{q}\\t{%2, %1, %0|%0, %1, %2}
7234 imul{q}\\t{%2, %1, %0|%0, %1, %2}
7235 imul{q}\\t{%2, %0|%0, %2}"
7236 [(set_attr "type" "imul")
7237 (set_attr "prefix_0f" "0,0,1")
7238 (set_attr "mode" "DI")])
7240 (define_expand "mulsi3"
7241 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7242 (mult:SI (match_operand:SI 1 "register_operand" "")
7243 (match_operand:SI 2 "general_operand" "")))
7244 (clobber (reg:CC 17))])]
7248 (define_insn "*mulsi3_1"
7249 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7250 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7251 (match_operand:SI 2 "general_operand" "K,i,mr")))
7252 (clobber (reg:CC 17))]
7253 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7254 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7255 ; there are two ways of writing the exact same machine instruction
7256 ; in assembly language. One, for example, is:
7260 ; while the other is:
7262 ; imul $12, %eax, %eax
7264 ; The first is simply short-hand for the latter. But, some assemblers,
7265 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7267 imul{l}\\t{%2, %1, %0|%0, %1, %2}
7268 imul{l}\\t{%2, %1, %0|%0, %1, %2}
7269 imul{l}\\t{%2, %0|%0, %2}"
7270 [(set_attr "type" "imul")
7271 (set_attr "prefix_0f" "0,0,1")
7272 (set_attr "mode" "SI")])
7274 (define_insn "*mulsi3_1_zext"
7275 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7277 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7278 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7279 (clobber (reg:CC 17))]
7281 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7282 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7283 ; there are two ways of writing the exact same machine instruction
7284 ; in assembly language. One, for example, is:
7288 ; while the other is:
7290 ; imul $12, %eax, %eax
7292 ; The first is simply short-hand for the latter. But, some assemblers,
7293 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7295 imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
7296 imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
7297 imul{l}\\t{%2, %k0|%k0, %2}"
7298 [(set_attr "type" "imul")
7299 (set_attr "prefix_0f" "0,0,1")
7300 (set_attr "mode" "SI")])
7302 (define_expand "mulhi3"
7303 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7304 (mult:HI (match_operand:HI 1 "register_operand" "")
7305 (match_operand:HI 2 "general_operand" "")))
7306 (clobber (reg:CC 17))])]
7307 "TARGET_HIMODE_MATH"
7310 (define_insn "*mulhi3_1"
7311 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7312 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
7313 (match_operand:HI 2 "general_operand" "K,i,mr")))
7314 (clobber (reg:CC 17))]
7315 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7316 ; %%% There was a note about "Assembler has weird restrictions",
7317 ; concerning alternative 1 when op1 == op0. True?
7319 imul{w}\\t{%2, %1, %0|%0, %1, %2}
7320 imul{w}\\t{%2, %1, %0|%0, %1, %2}
7321 imul{w}\\t{%2, %0|%0, %2}"
7322 [(set_attr "type" "imul")
7323 (set_attr "prefix_0f" "0,0,1")
7324 (set_attr "mode" "HI")])
7326 (define_insn "mulqi3"
7327 [(set (match_operand:QI 0 "register_operand" "=a")
7328 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7329 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7330 (clobber (reg:CC 17))]
7331 "TARGET_QIMODE_MATH"
7333 [(set_attr "type" "imul")
7334 (set_attr "length_immediate" "0")
7335 (set_attr "mode" "QI")])
7337 (define_insn "umulqihi3"
7338 [(set (match_operand:HI 0 "register_operand" "=a")
7339 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7340 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7341 (clobber (reg:CC 17))]
7342 "TARGET_QIMODE_MATH"
7344 [(set_attr "type" "imul")
7345 (set_attr "length_immediate" "0")
7346 (set_attr "mode" "QI")])
7348 (define_insn "mulqihi3"
7349 [(set (match_operand:HI 0 "register_operand" "=a")
7350 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7351 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7352 (clobber (reg:CC 17))]
7353 "TARGET_QIMODE_MATH"
7355 [(set_attr "type" "imul")
7356 (set_attr "length_immediate" "0")
7357 (set_attr "mode" "QI")])
7359 (define_insn "umulditi3"
7360 [(set (match_operand:TI 0 "register_operand" "=A")
7361 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7362 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7363 (clobber (reg:CC 17))]
7366 [(set_attr "type" "imul")
7367 (set_attr "ppro_uops" "few")
7368 (set_attr "length_immediate" "0")
7369 (set_attr "mode" "DI")])
7371 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7372 (define_insn "umulsidi3"
7373 [(set (match_operand:DI 0 "register_operand" "=A")
7374 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7375 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7376 (clobber (reg:CC 17))]
7379 [(set_attr "type" "imul")
7380 (set_attr "ppro_uops" "few")
7381 (set_attr "length_immediate" "0")
7382 (set_attr "mode" "SI")])
7384 (define_insn "mulditi3"
7385 [(set (match_operand:TI 0 "register_operand" "=A")
7386 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7387 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7388 (clobber (reg:CC 17))]
7391 [(set_attr "type" "imul")
7392 (set_attr "length_immediate" "0")
7393 (set_attr "mode" "DI")])
7395 (define_insn "mulsidi3"
7396 [(set (match_operand:DI 0 "register_operand" "=A")
7397 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7398 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7399 (clobber (reg:CC 17))]
7402 [(set_attr "type" "imul")
7403 (set_attr "length_immediate" "0")
7404 (set_attr "mode" "SI")])
7406 (define_insn "*umuldi3_highpart_rex64"
7407 [(set (match_operand:DI 0 "register_operand" "=d")
7410 (mult:TI (zero_extend:TI
7411 (match_operand:DI 1 "register_operand" "%a"))
7413 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7415 (clobber (match_scratch:DI 3 "=a"))
7416 (clobber (reg:CC 17))]
7419 [(set_attr "type" "imul")
7420 (set_attr "ppro_uops" "few")
7421 (set_attr "length_immediate" "0")
7422 (set_attr "mode" "DI")])
7424 (define_insn "umulsi3_highpart"
7425 [(set (match_operand:SI 0 "register_operand" "=d")
7428 (mult:DI (zero_extend:DI
7429 (match_operand:SI 1 "register_operand" "%a"))
7431 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7433 (clobber (match_scratch:SI 3 "=a"))
7434 (clobber (reg:CC 17))]
7437 [(set_attr "type" "imul")
7438 (set_attr "ppro_uops" "few")
7439 (set_attr "length_immediate" "0")
7440 (set_attr "mode" "SI")])
7442 (define_insn "*umulsi3_highpart_zext"
7443 [(set (match_operand:DI 0 "register_operand" "=d")
7444 (zero_extend:DI (truncate:SI
7446 (mult:DI (zero_extend:DI
7447 (match_operand:SI 1 "register_operand" "%a"))
7449 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7451 (clobber (match_scratch:SI 3 "=a"))
7452 (clobber (reg:CC 17))]
7455 [(set_attr "type" "imul")
7456 (set_attr "ppro_uops" "few")
7457 (set_attr "length_immediate" "0")
7458 (set_attr "mode" "SI")])
7460 (define_insn "*smuldi3_highpart_rex64"
7461 [(set (match_operand:DI 0 "register_operand" "=d")
7464 (mult:TI (sign_extend:TI
7465 (match_operand:DI 1 "register_operand" "%a"))
7467 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7469 (clobber (match_scratch:DI 3 "=a"))
7470 (clobber (reg:CC 17))]
7473 [(set_attr "type" "imul")
7474 (set_attr "ppro_uops" "few")
7475 (set_attr "mode" "DI")])
7477 (define_insn "smulsi3_highpart"
7478 [(set (match_operand:SI 0 "register_operand" "=d")
7481 (mult:DI (sign_extend:DI
7482 (match_operand:SI 1 "register_operand" "%a"))
7484 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7486 (clobber (match_scratch:SI 3 "=a"))
7487 (clobber (reg:CC 17))]
7490 [(set_attr "type" "imul")
7491 (set_attr "ppro_uops" "few")
7492 (set_attr "mode" "SI")])
7494 (define_insn "*smulsi3_highpart_zext"
7495 [(set (match_operand:DI 0 "register_operand" "=d")
7496 (zero_extend:DI (truncate:SI
7498 (mult:DI (sign_extend:DI
7499 (match_operand:SI 1 "register_operand" "%a"))
7501 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7503 (clobber (match_scratch:SI 3 "=a"))
7504 (clobber (reg:CC 17))]
7507 [(set_attr "type" "imul")
7508 (set_attr "ppro_uops" "few")
7509 (set_attr "mode" "SI")])
7511 ;; The patterns that match these are at the end of this file.
7513 (define_expand "mulxf3"
7514 [(set (match_operand:XF 0 "register_operand" "")
7515 (mult:XF (match_operand:XF 1 "register_operand" "")
7516 (match_operand:XF 2 "register_operand" "")))]
7517 "TARGET_80387 && !TARGET_64BIT"
7520 (define_expand "multf3"
7521 [(set (match_operand:TF 0 "register_operand" "")
7522 (mult:TF (match_operand:TF 1 "register_operand" "")
7523 (match_operand:TF 2 "register_operand" "")))]
7527 (define_expand "muldf3"
7528 [(set (match_operand:DF 0 "register_operand" "")
7529 (mult:DF (match_operand:DF 1 "register_operand" "")
7530 (match_operand:DF 2 "nonimmediate_operand" "")))]
7531 "TARGET_80387 || TARGET_SSE2"
7534 (define_expand "mulsf3"
7535 [(set (match_operand:SF 0 "register_operand" "")
7536 (mult:SF (match_operand:SF 1 "register_operand" "")
7537 (match_operand:SF 2 "nonimmediate_operand" "")))]
7538 "TARGET_80387 || TARGET_SSE"
7541 ;; Divide instructions
7543 (define_insn "divqi3"
7544 [(set (match_operand:QI 0 "register_operand" "=a")
7545 (div:QI (match_operand:HI 1 "register_operand" "0")
7546 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7547 (clobber (reg:CC 17))]
7548 "TARGET_QIMODE_MATH"
7550 [(set_attr "type" "idiv")
7551 (set_attr "mode" "QI")
7552 (set_attr "ppro_uops" "few")])
7554 (define_insn "udivqi3"
7555 [(set (match_operand:QI 0 "register_operand" "=a")
7556 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7557 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7558 (clobber (reg:CC 17))]
7559 "TARGET_QIMODE_MATH"
7561 [(set_attr "type" "idiv")
7562 (set_attr "mode" "QI")
7563 (set_attr "ppro_uops" "few")])
7565 ;; The patterns that match these are at the end of this file.
7567 (define_expand "divxf3"
7568 [(set (match_operand:XF 0 "register_operand" "")
7569 (div:XF (match_operand:XF 1 "register_operand" "")
7570 (match_operand:XF 2 "register_operand" "")))]
7571 "TARGET_80387 && !TARGET_64BIT"
7574 (define_expand "divtf3"
7575 [(set (match_operand:TF 0 "register_operand" "")
7576 (div:TF (match_operand:TF 1 "register_operand" "")
7577 (match_operand:TF 2 "register_operand" "")))]
7581 (define_expand "divdf3"
7582 [(set (match_operand:DF 0 "register_operand" "")
7583 (div:DF (match_operand:DF 1 "register_operand" "")
7584 (match_operand:DF 2 "nonimmediate_operand" "")))]
7585 "TARGET_80387 || TARGET_SSE2"
7588 (define_expand "divsf3"
7589 [(set (match_operand:SF 0 "register_operand" "")
7590 (div:SF (match_operand:SF 1 "register_operand" "")
7591 (match_operand:SF 2 "nonimmediate_operand" "")))]
7592 "TARGET_80387 || TARGET_SSE"
7595 ;; Remainder instructions.
7597 (define_expand "divmoddi4"
7598 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7599 (div:DI (match_operand:DI 1 "register_operand" "")
7600 (match_operand:DI 2 "nonimmediate_operand" "")))
7601 (set (match_operand:DI 3 "register_operand" "")
7602 (mod:DI (match_dup 1) (match_dup 2)))
7603 (clobber (reg:CC 17))])]
7607 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7608 ;; Penalize eax case sligthly because it results in worse scheduling
7610 (define_insn "*divmoddi4_nocltd_rex64"
7611 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7612 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7613 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7614 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7615 (mod:DI (match_dup 2) (match_dup 3)))
7616 (clobber (reg:CC 17))]
7617 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7619 [(set_attr "type" "multi")])
7621 (define_insn "*divmoddi4_cltd_rex64"
7622 [(set (match_operand:DI 0 "register_operand" "=a")
7623 (div:DI (match_operand:DI 2 "register_operand" "a")
7624 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7625 (set (match_operand:DI 1 "register_operand" "=&d")
7626 (mod:DI (match_dup 2) (match_dup 3)))
7627 (clobber (reg:CC 17))]
7628 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7630 [(set_attr "type" "multi")])
7632 (define_insn "*divmoddi_noext_rex64"
7633 [(set (match_operand:DI 0 "register_operand" "=a")
7634 (div:DI (match_operand:DI 1 "register_operand" "0")
7635 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7636 (set (match_operand:DI 3 "register_operand" "=d")
7637 (mod:DI (match_dup 1) (match_dup 2)))
7638 (use (match_operand:DI 4 "register_operand" "3"))
7639 (clobber (reg:CC 17))]
7642 [(set_attr "type" "idiv")
7643 (set_attr "mode" "DI")
7644 (set_attr "ppro_uops" "few")])
7647 [(set (match_operand:DI 0 "register_operand" "")
7648 (div:DI (match_operand:DI 1 "register_operand" "")
7649 (match_operand:DI 2 "nonimmediate_operand" "")))
7650 (set (match_operand:DI 3 "register_operand" "")
7651 (mod:DI (match_dup 1) (match_dup 2)))
7652 (clobber (reg:CC 17))]
7653 "TARGET_64BIT && reload_completed"
7654 [(parallel [(set (match_dup 3)
7655 (ashiftrt:DI (match_dup 4) (const_int 63)))
7656 (clobber (reg:CC 17))])
7657 (parallel [(set (match_dup 0)
7658 (div:DI (reg:DI 0) (match_dup 2)))
7660 (mod:DI (reg:DI 0) (match_dup 2)))
7662 (clobber (reg:CC 17))])]
7665 /* Avoid use of cltd in favour of a mov+shift. */
7666 if (!TARGET_USE_CLTD && !optimize_size)
7668 if (true_regnum (operands[1]))
7669 emit_move_insn (operands[0], operands[1]);
7671 emit_move_insn (operands[3], operands[1]);
7672 operands[4] = operands[3];
7676 if (true_regnum (operands[1]))
7678 operands[4] = operands[1];
7683 (define_expand "divmodsi4"
7684 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7685 (div:SI (match_operand:SI 1 "register_operand" "")
7686 (match_operand:SI 2 "nonimmediate_operand" "")))
7687 (set (match_operand:SI 3 "register_operand" "")
7688 (mod:SI (match_dup 1) (match_dup 2)))
7689 (clobber (reg:CC 17))])]
7693 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7694 ;; Penalize eax case sligthly because it results in worse scheduling
7696 (define_insn "*divmodsi4_nocltd"
7697 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7698 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7699 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7700 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7701 (mod:SI (match_dup 2) (match_dup 3)))
7702 (clobber (reg:CC 17))]
7703 "!optimize_size && !TARGET_USE_CLTD"
7705 [(set_attr "type" "multi")])
7707 (define_insn "*divmodsi4_cltd"
7708 [(set (match_operand:SI 0 "register_operand" "=a")
7709 (div:SI (match_operand:SI 2 "register_operand" "a")
7710 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7711 (set (match_operand:SI 1 "register_operand" "=&d")
7712 (mod:SI (match_dup 2) (match_dup 3)))
7713 (clobber (reg:CC 17))]
7714 "optimize_size || TARGET_USE_CLTD"
7716 [(set_attr "type" "multi")])
7718 (define_insn "*divmodsi_noext"
7719 [(set (match_operand:SI 0 "register_operand" "=a")
7720 (div:SI (match_operand:SI 1 "register_operand" "0")
7721 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7722 (set (match_operand:SI 3 "register_operand" "=d")
7723 (mod:SI (match_dup 1) (match_dup 2)))
7724 (use (match_operand:SI 4 "register_operand" "3"))
7725 (clobber (reg:CC 17))]
7728 [(set_attr "type" "idiv")
7729 (set_attr "mode" "SI")
7730 (set_attr "ppro_uops" "few")])
7733 [(set (match_operand:SI 0 "register_operand" "")
7734 (div:SI (match_operand:SI 1 "register_operand" "")
7735 (match_operand:SI 2 "nonimmediate_operand" "")))
7736 (set (match_operand:SI 3 "register_operand" "")
7737 (mod:SI (match_dup 1) (match_dup 2)))
7738 (clobber (reg:CC 17))]
7740 [(parallel [(set (match_dup 3)
7741 (ashiftrt:SI (match_dup 4) (const_int 31)))
7742 (clobber (reg:CC 17))])
7743 (parallel [(set (match_dup 0)
7744 (div:SI (reg:SI 0) (match_dup 2)))
7746 (mod:SI (reg:SI 0) (match_dup 2)))
7748 (clobber (reg:CC 17))])]
7751 /* Avoid use of cltd in favour of a mov+shift. */
7752 if (!TARGET_USE_CLTD && !optimize_size)
7754 if (true_regnum (operands[1]))
7755 emit_move_insn (operands[0], operands[1]);
7757 emit_move_insn (operands[3], operands[1]);
7758 operands[4] = operands[3];
7762 if (true_regnum (operands[1]))
7764 operands[4] = operands[1];
7768 (define_insn "divmodhi4"
7769 [(set (match_operand:HI 0 "register_operand" "=a")
7770 (div:HI (match_operand:HI 1 "register_operand" "0")
7771 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7772 (set (match_operand:HI 3 "register_operand" "=&d")
7773 (mod:HI (match_dup 1) (match_dup 2)))
7774 (clobber (reg:CC 17))]
7775 "TARGET_HIMODE_MATH"
7776 "cwtd\;idiv{w}\\t%2"
7777 [(set_attr "type" "multi")
7778 (set_attr "length_immediate" "0")
7779 (set_attr "mode" "SI")])
7781 (define_insn "udivmoddi4"
7782 [(set (match_operand:DI 0 "register_operand" "=a")
7783 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7784 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7785 (set (match_operand:DI 3 "register_operand" "=&d")
7786 (umod:DI (match_dup 1) (match_dup 2)))
7787 (clobber (reg:CC 17))]
7789 "xor{q}\\t%3, %3\;div{q}\\t%2"
7790 [(set_attr "type" "multi")
7791 (set_attr "length_immediate" "0")
7792 (set_attr "mode" "DI")])
7794 (define_insn "*udivmoddi4_noext"
7795 [(set (match_operand:DI 0 "register_operand" "=a")
7796 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7797 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7798 (set (match_operand:DI 3 "register_operand" "=d")
7799 (umod:DI (match_dup 1) (match_dup 2)))
7801 (clobber (reg:CC 17))]
7804 [(set_attr "type" "idiv")
7805 (set_attr "ppro_uops" "few")
7806 (set_attr "mode" "DI")])
7809 [(set (match_operand:DI 0 "register_operand" "")
7810 (udiv:DI (match_operand:DI 1 "register_operand" "")
7811 (match_operand:DI 2 "nonimmediate_operand" "")))
7812 (set (match_operand:DI 3 "register_operand" "")
7813 (umod:DI (match_dup 1) (match_dup 2)))
7814 (clobber (reg:CC 17))]
7815 "reload_completed && TARGET_64BIT"
7816 [(set (match_dup 3) (const_int 0))
7817 (parallel [(set (match_dup 0)
7818 (udiv:DI (match_dup 1) (match_dup 2)))
7820 (umod:DI (match_dup 1) (match_dup 2)))
7822 (clobber (reg:CC 17))])]
7825 (define_insn "udivmodsi4"
7826 [(set (match_operand:SI 0 "register_operand" "=a")
7827 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7828 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7829 (set (match_operand:SI 3 "register_operand" "=&d")
7830 (umod:SI (match_dup 1) (match_dup 2)))
7831 (clobber (reg:CC 17))]
7833 "xor{l}\\t%3, %3\;div{l}\\t%2"
7834 [(set_attr "type" "multi")
7835 (set_attr "length_immediate" "0")
7836 (set_attr "mode" "SI")])
7838 (define_insn "*udivmodsi4_noext"
7839 [(set (match_operand:SI 0 "register_operand" "=a")
7840 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7841 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7842 (set (match_operand:SI 3 "register_operand" "=d")
7843 (umod:SI (match_dup 1) (match_dup 2)))
7845 (clobber (reg:CC 17))]
7848 [(set_attr "type" "idiv")
7849 (set_attr "ppro_uops" "few")
7850 (set_attr "mode" "SI")])
7853 [(set (match_operand:SI 0 "register_operand" "")
7854 (udiv:SI (match_operand:SI 1 "register_operand" "")
7855 (match_operand:SI 2 "nonimmediate_operand" "")))
7856 (set (match_operand:SI 3 "register_operand" "")
7857 (umod:SI (match_dup 1) (match_dup 2)))
7858 (clobber (reg:CC 17))]
7860 [(set (match_dup 3) (const_int 0))
7861 (parallel [(set (match_dup 0)
7862 (udiv:SI (match_dup 1) (match_dup 2)))
7864 (umod:SI (match_dup 1) (match_dup 2)))
7866 (clobber (reg:CC 17))])]
7869 (define_expand "udivmodhi4"
7870 [(set (match_dup 4) (const_int 0))
7871 (parallel [(set (match_operand:HI 0 "register_operand" "")
7872 (udiv:HI (match_operand:HI 1 "register_operand" "")
7873 (match_operand:HI 2 "nonimmediate_operand" "")))
7874 (set (match_operand:HI 3 "register_operand" "")
7875 (umod:HI (match_dup 1) (match_dup 2)))
7877 (clobber (reg:CC 17))])]
7878 "TARGET_HIMODE_MATH"
7879 "operands[4] = gen_reg_rtx (HImode);")
7881 (define_insn "*udivmodhi_noext"
7882 [(set (match_operand:HI 0 "register_operand" "=a")
7883 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7884 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7885 (set (match_operand:HI 3 "register_operand" "=d")
7886 (umod:HI (match_dup 1) (match_dup 2)))
7887 (use (match_operand:HI 4 "register_operand" "3"))
7888 (clobber (reg:CC 17))]
7891 [(set_attr "type" "idiv")
7892 (set_attr "mode" "HI")
7893 (set_attr "ppro_uops" "few")])
7895 ;; We can not use div/idiv for double division, because it causes
7896 ;; "division by zero" on the overflow and that's not what we expect
7897 ;; from truncate. Because true (non truncating) double division is
7898 ;; never generated, we can't create this insn anyway.
7901 ; [(set (match_operand:SI 0 "register_operand" "=a")
7903 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7905 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7906 ; (set (match_operand:SI 3 "register_operand" "=d")
7908 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7909 ; (clobber (reg:CC 17))]
7911 ; "div{l}\\t{%2, %0|%0, %2}"
7912 ; [(set_attr "type" "idiv")
7913 ; (set_attr "ppro_uops" "few")])
7915 ;;- Logical AND instructions
7917 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7918 ;; Note that this excludes ah.
7920 (define_insn "*testdi_1_rex64"
7923 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7924 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7926 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7928 test{l}\\t{%k1, %k0|%k0, %k1}
7929 test{l}\\t{%k1, %k0|%k0, %k1}
7930 test{q}\\t{%1, %0|%0, %1}
7931 test{q}\\t{%1, %0|%0, %1}
7932 test{q}\\t{%1, %0|%0, %1}"
7933 [(set_attr "type" "test")
7934 (set_attr "modrm" "0,1,0,1,1")
7935 (set_attr "mode" "SI,SI,DI,DI,DI")
7936 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7938 (define_insn "testsi_1"
7941 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7942 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7944 "ix86_match_ccmode (insn, CCNOmode)"
7945 "test{l}\\t{%1, %0|%0, %1}"
7946 [(set_attr "type" "test")
7947 (set_attr "modrm" "0,1,1")
7948 (set_attr "mode" "SI")
7949 (set_attr "pent_pair" "uv,np,uv")])
7951 (define_expand "testsi_ccno_1"
7954 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7955 (match_operand:SI 1 "nonmemory_operand" ""))
7960 (define_insn "*testhi_1"
7962 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7963 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7965 "ix86_match_ccmode (insn, CCNOmode)"
7966 "test{w}\\t{%1, %0|%0, %1}"
7967 [(set_attr "type" "test")
7968 (set_attr "modrm" "0,1,1")
7969 (set_attr "mode" "HI")
7970 (set_attr "pent_pair" "uv,np,uv")])
7972 (define_expand "testqi_ccz_1"
7974 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7975 (match_operand:QI 1 "nonmemory_operand" ""))
7980 (define_insn "*testqi_1"
7982 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7983 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7985 "ix86_match_ccmode (insn, CCNOmode)"
7988 if (which_alternative == 3)
7990 if (GET_CODE (operands[1]) == CONST_INT
7991 && (INTVAL (operands[1]) & 0xffffff00))
7992 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7993 return \"test{l}\\t{%1, %k0|%k0, %1}\";
7995 return \"test{b}\\t{%1, %0|%0, %1}\";
7997 [(set_attr "type" "test")
7998 (set_attr "modrm" "0,1,1,1")
7999 (set_attr "mode" "QI,QI,QI,SI")
8000 (set_attr "pent_pair" "uv,np,uv,np")])
8002 (define_expand "testqi_ext_ccno_0"
8007 (match_operand 0 "ext_register_operand" "")
8010 (match_operand 1 "const_int_operand" ""))
8015 (define_insn "*testqi_ext_0"
8020 (match_operand 0 "ext_register_operand" "Q")
8023 (match_operand 1 "const_int_operand" "n"))
8025 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
8026 && ix86_match_ccmode (insn, CCNOmode)"
8027 "test{b}\\t{%1, %h0|%h0, %1}"
8028 [(set_attr "type" "test")
8029 (set_attr "mode" "QI")
8030 (set_attr "length_immediate" "1")
8031 (set_attr "pent_pair" "np")])
8033 (define_insn "*testqi_ext_1"
8038 (match_operand 0 "ext_register_operand" "Q")
8042 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
8044 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8045 "test{b}\\t{%1, %h0|%h0, %1}"
8046 [(set_attr "type" "test")
8047 (set_attr "mode" "QI")])
8049 (define_insn "*testqi_ext_1_rex64"
8054 (match_operand 0 "ext_register_operand" "Q")
8058 (match_operand:QI 1 "ext_register_operand" "Q")))
8060 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8061 "test{b}\\t{%1, %h0|%h0, %1}"
8062 [(set_attr "type" "test")
8063 (set_attr "mode" "QI")])
8065 (define_insn "*testqi_ext_2"
8070 (match_operand 0 "ext_register_operand" "Q")
8074 (match_operand 1 "ext_register_operand" "Q")
8078 "ix86_match_ccmode (insn, CCNOmode)"
8079 "test{b}\\t{%h1, %h0|%h0, %h1}"
8080 [(set_attr "type" "test")
8081 (set_attr "mode" "QI")])
8083 ;; Combine likes to form bit extractions for some tests. Humor it.
8084 (define_insn "*testqi_ext_3"
8086 (compare (zero_extract:SI
8087 (match_operand 0 "nonimmediate_operand" "rm")
8088 (match_operand:SI 1 "const_int_operand" "")
8089 (match_operand:SI 2 "const_int_operand" ""))
8091 "ix86_match_ccmode (insn, CCNOmode)
8092 && (GET_MODE (operands[0]) == SImode
8093 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8094 || GET_MODE (operands[0]) == HImode
8095 || GET_MODE (operands[0]) == QImode)"
8098 (define_insn "*testqi_ext_3_rex64"
8100 (compare (zero_extract:DI
8101 (match_operand 0 "nonimmediate_operand" "rm")
8102 (match_operand:DI 1 "const_int_operand" "")
8103 (match_operand:DI 2 "const_int_operand" ""))
8105 "ix86_match_ccmode (insn, CCNOmode)
8107 && (GET_MODE (operands[0]) == SImode
8108 || GET_MODE (operands[0]) == DImode
8109 || GET_MODE (operands[0]) == HImode
8110 || GET_MODE (operands[0]) == QImode)"
8115 (compare (zero_extract
8116 (match_operand 0 "nonimmediate_operand" "rm")
8117 (match_operand 1 "const_int_operand" "")
8118 (match_operand 2 "const_int_operand" ""))
8120 "ix86_match_ccmode (insn, CCNOmode)"
8121 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8124 HOST_WIDE_INT len = INTVAL (operands[1]);
8125 HOST_WIDE_INT pos = INTVAL (operands[2]);
8127 enum machine_mode mode;
8129 mode = GET_MODE (operands[0]);
8130 if (GET_CODE (operands[0]) == MEM)
8132 /* ??? Combine likes to put non-volatile mem extractions in QImode
8133 no matter the size of the test. So find a mode that works. */
8134 if (! MEM_VOLATILE_P (operands[0]))
8136 mode = smallest_mode_for_size (pos + len, MODE_INT);
8137 operands[0] = change_address (operands[0], mode, NULL_RTX);
8140 else if (mode == HImode && pos + len <= 8)
8142 /* Small HImode tests can be converted to QImode. */
8144 operands[0] = gen_lowpart (QImode, operands[0]);
8147 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8148 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8150 operands[3] = gen_rtx_AND (mode, operands[0],
8151 GEN_INT (trunc_int_for_mode (mask, mode)));
8154 ;; %%% This used to optimize known byte-wide and operations to memory,
8155 ;; and sometimes to QImode registers. If this is considered useful,
8156 ;; it should be done with splitters.
8158 (define_expand "anddi3"
8159 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8160 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8161 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8162 (clobber (reg:CC 17))]
8164 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8166 (define_insn "*anddi_1_rex64"
8167 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8168 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8169 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8170 (clobber (reg:CC 17))]
8171 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8174 switch (get_attr_type (insn))
8178 enum machine_mode mode;
8180 if (GET_CODE (operands[2]) != CONST_INT)
8182 if (INTVAL (operands[2]) == 0xff)
8184 else if (INTVAL (operands[2]) == 0xffff)
8189 operands[1] = gen_lowpart (mode, operands[1]);
8191 return \"movz{bq|x}\\t{%1,%0|%0, %1}\";
8193 return \"movz{wq|x}\\t{%1,%0|%0, %1}\";
8197 if (! rtx_equal_p (operands[0], operands[1]))
8199 if (get_attr_mode (insn) == MODE_SI)
8200 return \"and{l}\\t{%k2, %k0|%k0, %k2}\";
8202 return \"and{q}\\t{%2, %0|%0, %2}\";
8205 [(set_attr "type" "alu,alu,alu,imovx")
8206 (set_attr "length_immediate" "*,*,*,0")
8207 (set_attr "mode" "SI,DI,DI,DI")])
8209 (define_insn "*anddi_2"
8211 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8212 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8214 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8215 (and:DI (match_dup 1) (match_dup 2)))]
8216 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8217 && ix86_binary_operator_ok (AND, DImode, operands)"
8219 and{l}\\t{%k2, %k0|%k0, %k2}
8220 and{q}\\t{%2, %0|%0, %2}
8221 and{q}\\t{%2, %0|%0, %2}"
8222 [(set_attr "type" "alu")
8223 (set_attr "mode" "SI,DI,DI")])
8225 (define_expand "andsi3"
8226 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8227 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8228 (match_operand:SI 2 "general_operand" "")))
8229 (clobber (reg:CC 17))]
8231 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8233 (define_insn "*andsi_1"
8234 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8235 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8236 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8237 (clobber (reg:CC 17))]
8238 "ix86_binary_operator_ok (AND, SImode, operands)"
8241 switch (get_attr_type (insn))
8245 enum machine_mode mode;
8247 if (GET_CODE (operands[2]) != CONST_INT)
8249 if (INTVAL (operands[2]) == 0xff)
8251 else if (INTVAL (operands[2]) == 0xffff)
8256 operands[1] = gen_lowpart (mode, operands[1]);
8258 return \"movz{bl|x}\\t{%1,%0|%0, %1}\";
8260 return \"movz{wl|x}\\t{%1,%0|%0, %1}\";
8264 if (! rtx_equal_p (operands[0], operands[1]))
8266 return \"and{l}\\t{%2, %0|%0, %2}\";
8269 [(set_attr "type" "alu,alu,imovx")
8270 (set_attr "length_immediate" "*,*,0")
8271 (set_attr "mode" "SI")])
8274 [(set (match_operand 0 "register_operand" "")
8276 (const_int -65536)))
8277 (clobber (reg:CC 17))]
8279 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8280 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))"
8281 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8282 "operands[1] = gen_lowpart (HImode, operands[0]);")
8285 [(set (match_operand 0 "q_regs_operand" "")
8288 (clobber (reg:CC 17))]
8289 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
8290 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8291 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))"
8292 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8293 "operands[1] = gen_lowpart (QImode, operands[0]);")
8296 [(set (match_operand 0 "register_operand" "")
8298 (const_int -65281)))
8299 (clobber (reg:CC 17))]
8300 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
8301 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8302 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
8303 && (! reload_completed || ANY_QI_REG_P (operands[0]))"
8304 [(parallel [(set (zero_extract:SI (match_dup 0)
8308 (zero_extract:SI (match_dup 0)
8311 (zero_extract:SI (match_dup 0)
8314 (clobber (reg:CC 17))])]
8315 "operands[0] = gen_lowpart (SImode, operands[0]);")
8317 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8318 (define_insn "*andsi_1_zext"
8319 [(set (match_operand:DI 0 "register_operand" "=r")
8321 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8322 (match_operand:SI 2 "general_operand" "rim"))))
8323 (clobber (reg:CC 17))]
8324 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8325 "and{l}\\t{%2, %k0|%k0, %2}"
8326 [(set_attr "type" "alu")
8327 (set_attr "mode" "SI")])
8329 (define_insn "*andsi_2"
8331 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8332 (match_operand:SI 2 "general_operand" "rim,ri"))
8334 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8335 (and:SI (match_dup 1) (match_dup 2)))]
8336 "ix86_match_ccmode (insn, CCNOmode)
8337 && ix86_binary_operator_ok (AND, SImode, operands)"
8338 "and{l}\\t{%2, %0|%0, %2}"
8339 [(set_attr "type" "alu")
8340 (set_attr "mode" "SI")])
8342 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8343 (define_insn "*andsi_2_zext"
8345 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8346 (match_operand:SI 2 "general_operand" "rim"))
8348 (set (match_operand:DI 0 "register_operand" "=r")
8349 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8350 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8351 && ix86_binary_operator_ok (AND, SImode, operands)"
8352 "and{l}\\t{%2, %k0|%k0, %2}"
8353 [(set_attr "type" "alu")
8354 (set_attr "mode" "SI")])
8356 (define_expand "andhi3"
8357 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8358 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8359 (match_operand:HI 2 "general_operand" "")))
8360 (clobber (reg:CC 17))]
8361 "TARGET_HIMODE_MATH"
8362 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8364 (define_insn "*andhi_1"
8365 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8366 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8367 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8368 (clobber (reg:CC 17))]
8369 "ix86_binary_operator_ok (AND, HImode, operands)"
8372 switch (get_attr_type (insn))
8375 if (GET_CODE (operands[2]) != CONST_INT)
8377 if (INTVAL (operands[2]) == 0xff)
8378 return \"movz{bl|x}\\t{%b1, %k0|%k0, %b1}\";
8382 if (! rtx_equal_p (operands[0], operands[1]))
8385 return \"and{w}\\t{%2, %0|%0, %2}\";
8388 [(set_attr "type" "alu,alu,imovx")
8389 (set_attr "length_immediate" "*,*,0")
8390 (set_attr "mode" "HI,HI,SI")])
8392 (define_insn "*andhi_2"
8394 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8395 (match_operand:HI 2 "general_operand" "rim,ri"))
8397 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8398 (and:HI (match_dup 1) (match_dup 2)))]
8399 "ix86_match_ccmode (insn, CCNOmode)
8400 && ix86_binary_operator_ok (AND, HImode, operands)"
8401 "and{w}\\t{%2, %0|%0, %2}"
8402 [(set_attr "type" "alu")
8403 (set_attr "mode" "HI")])
8405 (define_expand "andqi3"
8406 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8407 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8408 (match_operand:QI 2 "general_operand" "")))
8409 (clobber (reg:CC 17))]
8410 "TARGET_QIMODE_MATH"
8411 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8413 ;; %%% Potential partial reg stall on alternative 2. What to do?
8414 (define_insn "*andqi_1"
8415 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8416 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8417 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8418 (clobber (reg:CC 17))]
8419 "ix86_binary_operator_ok (AND, QImode, operands)"
8421 and{b}\\t{%2, %0|%0, %2}
8422 and{b}\\t{%2, %0|%0, %2}
8423 and{l}\\t{%k2, %k0|%k0, %k2}"
8424 [(set_attr "type" "alu")
8425 (set_attr "mode" "QI,QI,SI")])
8427 (define_insn "*andqi_1_slp"
8428 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8429 (and:QI (match_dup 0)
8430 (match_operand:QI 1 "general_operand" "qi,qmi")))
8431 (clobber (reg:CC 17))]
8433 "and{b}\\t{%1, %0|%0, %1}"
8434 [(set_attr "type" "alu1")
8435 (set_attr "mode" "QI")])
8437 (define_insn "*andqi_2"
8440 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8441 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8443 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8444 (and:QI (match_dup 1) (match_dup 2)))]
8445 "ix86_match_ccmode (insn, CCNOmode)
8446 && ix86_binary_operator_ok (AND, QImode, operands)"
8449 if (which_alternative == 2)
8451 if (GET_CODE (operands[2]) == CONST_INT
8452 && (INTVAL (operands[2]) & 0xffffff00))
8453 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8454 return \"and{l}\\t{%2, %k0|%k0, %2}\";
8456 return \"and{b}\\t{%2, %0|%0, %2}\";
8458 [(set_attr "type" "alu")
8459 (set_attr "mode" "QI,QI,SI")])
8461 (define_insn "*andqi_2_slp"
8464 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8465 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8467 (set (strict_low_part (match_dup 0))
8468 (and:QI (match_dup 0) (match_dup 1)))]
8469 "ix86_match_ccmode (insn, CCNOmode)"
8470 "and{b}\\t{%1, %0|%0, %1}"
8471 [(set_attr "type" "alu1")
8472 (set_attr "mode" "QI")])
8474 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8475 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8476 ;; for a QImode operand, which of course failed.
8478 (define_insn "andqi_ext_0"
8479 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8484 (match_operand 1 "ext_register_operand" "0")
8487 (match_operand 2 "const_int_operand" "n")))
8488 (clobber (reg:CC 17))]
8489 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8490 "and{b}\\t{%2, %h0|%h0, %2}"
8491 [(set_attr "type" "alu")
8492 (set_attr "length_immediate" "1")
8493 (set_attr "mode" "QI")])
8495 ;; Generated by peephole translating test to and. This shows up
8496 ;; often in fp comparisons.
8498 (define_insn "*andqi_ext_0_cc"
8503 (match_operand 1 "ext_register_operand" "0")
8506 (match_operand 2 "const_int_operand" "n"))
8508 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8517 "ix86_match_ccmode (insn, CCNOmode)
8518 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8519 "and{b}\\t{%2, %h0|%h0, %2}"
8520 [(set_attr "type" "alu")
8521 (set_attr "length_immediate" "1")
8522 (set_attr "mode" "QI")])
8524 (define_insn "*andqi_ext_1"
8525 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8530 (match_operand 1 "ext_register_operand" "0")
8534 (match_operand:QI 2 "general_operand" "Qm"))))
8535 (clobber (reg:CC 17))]
8537 "and{b}\\t{%2, %h0|%h0, %2}"
8538 [(set_attr "type" "alu")
8539 (set_attr "length_immediate" "0")
8540 (set_attr "mode" "QI")])
8542 (define_insn "*andqi_ext_1_rex64"
8543 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8548 (match_operand 1 "ext_register_operand" "0")
8552 (match_operand:QI 2 "ext_register_operand" "Q"))))
8553 (clobber (reg:CC 17))]
8555 "and{b}\\t{%2, %h0|%h0, %2}"
8556 [(set_attr "type" "alu")
8557 (set_attr "length_immediate" "0")
8558 (set_attr "mode" "QI")])
8560 (define_insn "*andqi_ext_2"
8561 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8566 (match_operand 1 "ext_register_operand" "%0")
8570 (match_operand 2 "ext_register_operand" "Q")
8573 (clobber (reg:CC 17))]
8575 "and{b}\\t{%h2, %h0|%h0, %h2}"
8576 [(set_attr "type" "alu")
8577 (set_attr "length_immediate" "0")
8578 (set_attr "mode" "QI")])
8580 ;; Logical inclusive OR instructions
8582 ;; %%% This used to optimize known byte-wide and operations to memory.
8583 ;; If this is considered useful, it should be done with splitters.
8585 (define_expand "iordi3"
8586 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8587 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8588 (match_operand:DI 2 "x86_64_general_operand" "")))
8589 (clobber (reg:CC 17))]
8591 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8593 (define_insn "*iordi_1_rex64"
8594 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8595 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8596 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8597 (clobber (reg:CC 17))]
8599 && ix86_binary_operator_ok (IOR, DImode, operands)"
8600 "or{q}\\t{%2, %0|%0, %2}"
8601 [(set_attr "type" "alu")
8602 (set_attr "mode" "DI")])
8604 (define_insn "*iordi_2_rex64"
8606 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8607 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8609 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8610 (ior:DI (match_dup 1) (match_dup 2)))]
8612 && ix86_match_ccmode (insn, CCNOmode)
8613 && ix86_binary_operator_ok (IOR, DImode, operands)"
8614 "or{q}\\t{%2, %0|%0, %2}"
8615 [(set_attr "type" "alu")
8616 (set_attr "mode" "DI")])
8618 (define_insn "*iordi_3_rex64"
8620 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8621 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8623 (clobber (match_scratch:DI 0 "=r"))]
8625 && ix86_match_ccmode (insn, CCNOmode)
8626 && ix86_binary_operator_ok (IOR, DImode, operands)"
8627 "or{q}\\t{%2, %0|%0, %2}"
8628 [(set_attr "type" "alu")
8629 (set_attr "mode" "DI")])
8632 (define_expand "iorsi3"
8633 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8634 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8635 (match_operand:SI 2 "general_operand" "")))
8636 (clobber (reg:CC 17))]
8638 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8640 (define_insn "*iorsi_1"
8641 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8642 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8643 (match_operand:SI 2 "general_operand" "ri,rmi")))
8644 (clobber (reg:CC 17))]
8645 "ix86_binary_operator_ok (IOR, SImode, operands)"
8646 "or{l}\\t{%2, %0|%0, %2}"
8647 [(set_attr "type" "alu")
8648 (set_attr "mode" "SI")])
8650 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8651 (define_insn "*iorsi_1_zext"
8652 [(set (match_operand:DI 0 "register_operand" "=rm")
8654 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8655 (match_operand:SI 2 "general_operand" "rim"))))
8656 (clobber (reg:CC 17))]
8657 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8658 "or{l}\\t{%2, %k0|%k0, %2}"
8659 [(set_attr "type" "alu")
8660 (set_attr "mode" "SI")])
8662 (define_insn "*iorsi_1_zext_imm"
8663 [(set (match_operand:DI 0 "register_operand" "=rm")
8664 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8665 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8666 (clobber (reg:CC 17))]
8668 "or{l}\\t{%2, %k0|%k0, %2}"
8669 [(set_attr "type" "alu")
8670 (set_attr "mode" "SI")])
8672 (define_insn "*iorsi_2"
8674 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8675 (match_operand:SI 2 "general_operand" "rim,ri"))
8677 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8678 (ior:SI (match_dup 1) (match_dup 2)))]
8679 "ix86_match_ccmode (insn, CCNOmode)
8680 && ix86_binary_operator_ok (IOR, SImode, operands)"
8681 "or{l}\\t{%2, %0|%0, %2}"
8682 [(set_attr "type" "alu")
8683 (set_attr "mode" "SI")])
8685 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8686 ;; ??? Special case for immediate operand is missing - it is tricky.
8687 (define_insn "*iorsi_2_zext"
8689 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8690 (match_operand:SI 2 "general_operand" "rim"))
8692 (set (match_operand:DI 0 "register_operand" "=r")
8693 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8694 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8695 && ix86_binary_operator_ok (IOR, SImode, operands)"
8696 "or{l}\\t{%2, %k0|%k0, %2}"
8697 [(set_attr "type" "alu")
8698 (set_attr "mode" "SI")])
8700 (define_insn "*iorsi_2_zext_imm"
8702 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8703 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8705 (set (match_operand:DI 0 "register_operand" "=r")
8706 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8707 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8708 && ix86_binary_operator_ok (IOR, SImode, operands)"
8709 "or{l}\\t{%2, %k0|%k0, %2}"
8710 [(set_attr "type" "alu")
8711 (set_attr "mode" "SI")])
8713 (define_insn "*iorsi_3"
8715 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8716 (match_operand:SI 2 "general_operand" "rim"))
8718 (clobber (match_scratch:SI 0 "=r"))]
8719 "ix86_match_ccmode (insn, CCNOmode)
8720 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8721 "or{l}\\t{%2, %0|%0, %2}"
8722 [(set_attr "type" "alu")
8723 (set_attr "mode" "SI")])
8725 (define_expand "iorhi3"
8726 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8727 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8728 (match_operand:HI 2 "general_operand" "")))
8729 (clobber (reg:CC 17))]
8730 "TARGET_HIMODE_MATH"
8731 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8733 (define_insn "*iorhi_1"
8734 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8735 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8736 (match_operand:HI 2 "general_operand" "rmi,ri")))
8737 (clobber (reg:CC 17))]
8738 "ix86_binary_operator_ok (IOR, HImode, operands)"
8739 "or{w}\\t{%2, %0|%0, %2}"
8740 [(set_attr "type" "alu")
8741 (set_attr "mode" "HI")])
8743 (define_insn "*iorhi_2"
8745 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8746 (match_operand:HI 2 "general_operand" "rim,ri"))
8748 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8749 (ior:HI (match_dup 1) (match_dup 2)))]
8750 "ix86_match_ccmode (insn, CCNOmode)
8751 && ix86_binary_operator_ok (IOR, HImode, operands)"
8752 "or{w}\\t{%2, %0|%0, %2}"
8753 [(set_attr "type" "alu")
8754 (set_attr "mode" "HI")])
8756 (define_insn "*iorhi_3"
8758 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8759 (match_operand:HI 2 "general_operand" "rim"))
8761 (clobber (match_scratch:HI 0 "=r"))]
8762 "ix86_match_ccmode (insn, CCNOmode)
8763 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8764 "or{w}\\t{%2, %0|%0, %2}"
8765 [(set_attr "type" "alu")
8766 (set_attr "mode" "HI")])
8768 (define_expand "iorqi3"
8769 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8770 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8771 (match_operand:QI 2 "general_operand" "")))
8772 (clobber (reg:CC 17))]
8773 "TARGET_QIMODE_MATH"
8774 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8776 ;; %%% Potential partial reg stall on alternative 2. What to do?
8777 (define_insn "*iorqi_1"
8778 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8779 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8780 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8781 (clobber (reg:CC 17))]
8782 "ix86_binary_operator_ok (IOR, QImode, operands)"
8784 or{b}\\t{%2, %0|%0, %2}
8785 or{b}\\t{%2, %0|%0, %2}
8786 or{l}\\t{%k2, %k0|%k0, %k2}"
8787 [(set_attr "type" "alu")
8788 (set_attr "mode" "QI,QI,SI")])
8790 (define_insn "*iorqi_1_slp"
8791 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8792 (ior:QI (match_dup 0)
8793 (match_operand:QI 1 "general_operand" "qmi,qi")))
8794 (clobber (reg:CC 17))]
8796 "or{b}\\t{%1, %0|%0, %1}"
8797 [(set_attr "type" "alu1")
8798 (set_attr "mode" "QI")])
8800 (define_insn "*iorqi_2"
8802 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8803 (match_operand:QI 2 "general_operand" "qim,qi"))
8805 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8806 (ior:QI (match_dup 1) (match_dup 2)))]
8807 "ix86_match_ccmode (insn, CCNOmode)
8808 && ix86_binary_operator_ok (IOR, QImode, operands)"
8809 "or{b}\\t{%2, %0|%0, %2}"
8810 [(set_attr "type" "alu")
8811 (set_attr "mode" "QI")])
8813 (define_insn "*iorqi_2_slp"
8815 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8816 (match_operand:QI 1 "general_operand" "qim,qi"))
8818 (set (strict_low_part (match_dup 0))
8819 (ior:QI (match_dup 0) (match_dup 1)))]
8820 "ix86_match_ccmode (insn, CCNOmode)"
8821 "or{b}\\t{%1, %0|%0, %1}"
8822 [(set_attr "type" "alu1")
8823 (set_attr "mode" "QI")])
8825 (define_insn "*iorqi_3"
8827 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8828 (match_operand:QI 2 "general_operand" "qim"))
8830 (clobber (match_scratch:QI 0 "=q"))]
8831 "ix86_match_ccmode (insn, CCNOmode)
8832 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8833 "or{b}\\t{%2, %0|%0, %2}"
8834 [(set_attr "type" "alu")
8835 (set_attr "mode" "QI")])
8838 ;; Logical XOR instructions
8840 ;; %%% This used to optimize known byte-wide and operations to memory.
8841 ;; If this is considered useful, it should be done with splitters.
8843 (define_expand "xordi3"
8844 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8845 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8846 (match_operand:DI 2 "x86_64_general_operand" "")))
8847 (clobber (reg:CC 17))]
8849 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8851 (define_insn "*xordi_1_rex64"
8852 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8853 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8854 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8855 (clobber (reg:CC 17))]
8857 && ix86_binary_operator_ok (XOR, DImode, operands)"
8859 xor{q}\\t{%2, %0|%0, %2}
8860 xor{q}\\t{%2, %0|%0, %2}"
8861 [(set_attr "type" "alu")
8862 (set_attr "mode" "DI,DI")])
8864 (define_insn "*xordi_2_rex64"
8866 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8867 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8869 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8870 (xor:DI (match_dup 1) (match_dup 2)))]
8872 && ix86_match_ccmode (insn, CCNOmode)
8873 && ix86_binary_operator_ok (XOR, DImode, operands)"
8875 xor{q}\\t{%2, %0|%0, %2}
8876 xor{q}\\t{%2, %0|%0, %2}"
8877 [(set_attr "type" "alu")
8878 (set_attr "mode" "DI,DI")])
8880 (define_insn "*xordi_3_rex64"
8882 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8883 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8885 (clobber (match_scratch:DI 0 "=r"))]
8887 && ix86_match_ccmode (insn, CCNOmode)
8888 && ix86_binary_operator_ok (XOR, DImode, operands)"
8889 "xor{q}\\t{%2, %0|%0, %2}"
8890 [(set_attr "type" "alu")
8891 (set_attr "mode" "DI")])
8893 (define_expand "xorsi3"
8894 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8895 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8896 (match_operand:SI 2 "general_operand" "")))
8897 (clobber (reg:CC 17))]
8899 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8901 (define_insn "*xorsi_1"
8902 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8903 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8904 (match_operand:SI 2 "general_operand" "ri,rm")))
8905 (clobber (reg:CC 17))]
8906 "ix86_binary_operator_ok (XOR, SImode, operands)"
8907 "xor{l}\\t{%2, %0|%0, %2}"
8908 [(set_attr "type" "alu")
8909 (set_attr "mode" "SI")])
8911 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8912 ;; Add speccase for immediates
8913 (define_insn "*xorsi_1_zext"
8914 [(set (match_operand:DI 0 "register_operand" "=r")
8916 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8917 (match_operand:SI 2 "general_operand" "rim"))))
8918 (clobber (reg:CC 17))]
8919 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8920 "xor{l}\\t{%2, %k0|%k0, %2}"
8921 [(set_attr "type" "alu")
8922 (set_attr "mode" "SI")])
8924 (define_insn "*xorsi_1_zext_imm"
8925 [(set (match_operand:DI 0 "register_operand" "=r")
8926 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8927 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8928 (clobber (reg:CC 17))]
8929 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8930 "xor{l}\\t{%2, %k0|%k0, %2}"
8931 [(set_attr "type" "alu")
8932 (set_attr "mode" "SI")])
8934 (define_insn "*xorsi_2"
8936 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8937 (match_operand:SI 2 "general_operand" "rim,ri"))
8939 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8940 (xor:SI (match_dup 1) (match_dup 2)))]
8941 "ix86_match_ccmode (insn, CCNOmode)
8942 && ix86_binary_operator_ok (XOR, SImode, operands)"
8943 "xor{l}\\t{%2, %0|%0, %2}"
8944 [(set_attr "type" "alu")
8945 (set_attr "mode" "SI")])
8947 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8948 ;; ??? Special case for immediate operand is missing - it is tricky.
8949 (define_insn "*xorsi_2_zext"
8951 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8952 (match_operand:SI 2 "general_operand" "rim"))
8954 (set (match_operand:DI 0 "register_operand" "=r")
8955 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8956 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8957 && ix86_binary_operator_ok (XOR, SImode, operands)"
8958 "xor{l}\\t{%2, %k0|%k0, %2}"
8959 [(set_attr "type" "alu")
8960 (set_attr "mode" "SI")])
8962 (define_insn "*xorsi_2_zext_imm"
8964 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8965 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8967 (set (match_operand:DI 0 "register_operand" "=r")
8968 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8969 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8970 && ix86_binary_operator_ok (XOR, SImode, operands)"
8971 "xor{l}\\t{%2, %k0|%k0, %2}"
8972 [(set_attr "type" "alu")
8973 (set_attr "mode" "SI")])
8975 (define_insn "*xorsi_3"
8977 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8978 (match_operand:SI 2 "general_operand" "rim"))
8980 (clobber (match_scratch:SI 0 "=r"))]
8981 "ix86_match_ccmode (insn, CCNOmode)
8982 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8983 "xor{l}\\t{%2, %0|%0, %2}"
8984 [(set_attr "type" "alu")
8985 (set_attr "mode" "SI")])
8987 (define_expand "xorhi3"
8988 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8989 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
8990 (match_operand:HI 2 "general_operand" "")))
8991 (clobber (reg:CC 17))]
8992 "TARGET_HIMODE_MATH"
8993 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
8995 (define_insn "*xorhi_1"
8996 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8997 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8998 (match_operand:HI 2 "general_operand" "rmi,ri")))
8999 (clobber (reg:CC 17))]
9000 "ix86_binary_operator_ok (XOR, HImode, operands)"
9001 "xor{w}\\t{%2, %0|%0, %2}"
9002 [(set_attr "type" "alu")
9003 (set_attr "mode" "HI")])
9005 (define_insn "*xorhi_2"
9007 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9008 (match_operand:HI 2 "general_operand" "rim,ri"))
9010 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9011 (xor:HI (match_dup 1) (match_dup 2)))]
9012 "ix86_match_ccmode (insn, CCNOmode)
9013 && ix86_binary_operator_ok (XOR, HImode, operands)"
9014 "xor{w}\\t{%2, %0|%0, %2}"
9015 [(set_attr "type" "alu")
9016 (set_attr "mode" "HI")])
9018 (define_insn "*xorhi_3"
9020 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9021 (match_operand:HI 2 "general_operand" "rim"))
9023 (clobber (match_scratch:HI 0 "=r"))]
9024 "ix86_match_ccmode (insn, CCNOmode)
9025 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9026 "xor{w}\\t{%2, %0|%0, %2}"
9027 [(set_attr "type" "alu")
9028 (set_attr "mode" "HI")])
9030 (define_expand "xorqi3"
9031 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9032 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9033 (match_operand:QI 2 "general_operand" "")))
9034 (clobber (reg:CC 17))]
9035 "TARGET_QIMODE_MATH"
9036 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9038 ;; %%% Potential partial reg stall on alternative 2. What to do?
9039 (define_insn "*xorqi_1"
9040 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9041 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9042 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9043 (clobber (reg:CC 17))]
9044 "ix86_binary_operator_ok (XOR, QImode, operands)"
9046 xor{b}\\t{%2, %0|%0, %2}
9047 xor{b}\\t{%2, %0|%0, %2}
9048 xor{l}\\t{%k2, %k0|%k0, %k2}"
9049 [(set_attr "type" "alu")
9050 (set_attr "mode" "QI,QI,SI")])
9052 (define_insn "*xorqi_ext_1"
9053 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9057 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9060 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9063 (clobber (reg:CC 17))]
9065 "xor{b}\\t{%h2, %h0|%h0, %h2}"
9066 [(set_attr "type" "alu")
9067 (set_attr "length_immediate" "0")
9068 (set_attr "mode" "QI")])
9070 (define_insn "*xorqi_cc_1"
9073 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9074 (match_operand:QI 2 "general_operand" "qim,qi"))
9076 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9077 (xor:QI (match_dup 1) (match_dup 2)))]
9078 "ix86_match_ccmode (insn, CCNOmode)
9079 && ix86_binary_operator_ok (XOR, QImode, operands)"
9080 "xor{b}\\t{%2, %0|%0, %2}"
9081 [(set_attr "type" "alu")
9082 (set_attr "mode" "QI")])
9084 (define_insn "*xorqi_cc_2"
9087 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9088 (match_operand:QI 2 "general_operand" "qim"))
9090 (clobber (match_scratch:QI 0 "=q"))]
9091 "ix86_match_ccmode (insn, CCNOmode)
9092 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9093 "xor{b}\\t{%2, %0|%0, %2}"
9094 [(set_attr "type" "alu")
9095 (set_attr "mode" "QI")])
9097 (define_insn "*xorqi_cc_ext_1"
9102 (match_operand 1 "ext_register_operand" "0")
9105 (match_operand:QI 2 "general_operand" "qmn"))
9107 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9111 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9113 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9114 "xor{b}\\t{%2, %h0|%h0, %2}"
9115 [(set_attr "type" "alu")
9116 (set_attr "mode" "QI")])
9118 (define_insn "*xorqi_cc_ext_1_rex64"
9123 (match_operand 1 "ext_register_operand" "0")
9126 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9128 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9132 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9134 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9135 "xor{b}\\t{%2, %h0|%h0, %2}"
9136 [(set_attr "type" "alu")
9137 (set_attr "mode" "QI")])
9139 (define_expand "xorqi_cc_ext_1"
9145 (match_operand 1 "ext_register_operand" "")
9148 (match_operand:QI 2 "general_operand" ""))
9150 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9154 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9159 ;; Negation instructions
9161 (define_expand "negdi2"
9162 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9163 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9164 (clobber (reg:CC 17))])]
9166 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9168 (define_insn "*negdi2_1"
9169 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9170 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9171 (clobber (reg:CC 17))]
9173 && ix86_unary_operator_ok (NEG, DImode, operands)"
9177 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9178 (neg:DI (match_operand:DI 1 "general_operand" "")))
9179 (clobber (reg:CC 17))]
9184 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9185 (set (match_dup 0) (neg:SI (match_dup 2)))])
9188 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9191 (clobber (reg:CC 17))])
9194 (neg:SI (match_dup 1)))
9195 (clobber (reg:CC 17))])]
9196 "split_di (operands+1, 1, operands+2, operands+3);
9197 split_di (operands+0, 1, operands+0, operands+1);")
9199 (define_insn "*negdi2_1_rex64"
9200 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9201 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9202 (clobber (reg:CC 17))]
9203 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9205 [(set_attr "type" "negnot")
9206 (set_attr "mode" "DI")])
9208 ;; The problem with neg is that it does not perform (compare x 0),
9209 ;; it really performs (compare 0 x), which leaves us with the zero
9210 ;; flag being the only useful item.
9212 (define_insn "*negdi2_cmpz_rex64"
9214 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9216 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9217 (neg:DI (match_dup 1)))]
9218 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9220 [(set_attr "type" "negnot")
9221 (set_attr "mode" "DI")])
9224 (define_expand "negsi2"
9225 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9226 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9227 (clobber (reg:CC 17))])]
9229 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9231 (define_insn "*negsi2_1"
9232 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9233 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9234 (clobber (reg:CC 17))]
9235 "ix86_unary_operator_ok (NEG, SImode, operands)"
9237 [(set_attr "type" "negnot")
9238 (set_attr "mode" "SI")])
9240 ;; Combine is quite creative about this pattern.
9241 (define_insn "*negsi2_1_zext"
9242 [(set (match_operand:DI 0 "register_operand" "=r")
9243 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9246 (clobber (reg:CC 17))]
9247 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9249 [(set_attr "type" "negnot")
9250 (set_attr "mode" "SI")])
9252 ;; The problem with neg is that it does not perform (compare x 0),
9253 ;; it really performs (compare 0 x), which leaves us with the zero
9254 ;; flag being the only useful item.
9256 (define_insn "*negsi2_cmpz"
9258 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9260 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9261 (neg:SI (match_dup 1)))]
9262 "ix86_unary_operator_ok (NEG, SImode, operands)"
9264 [(set_attr "type" "negnot")
9265 (set_attr "mode" "SI")])
9267 (define_insn "*negsi2_cmpz_zext"
9269 (compare:CCZ (lshiftrt:DI
9271 (match_operand:DI 1 "register_operand" "0")
9275 (set (match_operand:DI 0 "register_operand" "=r")
9276 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9279 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9281 [(set_attr "type" "negnot")
9282 (set_attr "mode" "SI")])
9284 (define_expand "neghi2"
9285 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9286 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9287 (clobber (reg:CC 17))])]
9288 "TARGET_HIMODE_MATH"
9289 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9291 (define_insn "*neghi2_1"
9292 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9293 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9294 (clobber (reg:CC 17))]
9295 "ix86_unary_operator_ok (NEG, HImode, operands)"
9297 [(set_attr "type" "negnot")
9298 (set_attr "mode" "HI")])
9300 (define_insn "*neghi2_cmpz"
9302 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9304 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9305 (neg:HI (match_dup 1)))]
9306 "ix86_unary_operator_ok (NEG, HImode, operands)"
9308 [(set_attr "type" "negnot")
9309 (set_attr "mode" "HI")])
9311 (define_expand "negqi2"
9312 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9313 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9314 (clobber (reg:CC 17))])]
9315 "TARGET_QIMODE_MATH"
9316 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9318 (define_insn "*negqi2_1"
9319 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9320 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9321 (clobber (reg:CC 17))]
9322 "ix86_unary_operator_ok (NEG, QImode, operands)"
9324 [(set_attr "type" "negnot")
9325 (set_attr "mode" "QI")])
9327 (define_insn "*negqi2_cmpz"
9329 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9331 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9332 (neg:QI (match_dup 1)))]
9333 "ix86_unary_operator_ok (NEG, QImode, operands)"
9335 [(set_attr "type" "negnot")
9336 (set_attr "mode" "QI")])
9338 ;; Changing of sign for FP values is doable using integer unit too.
9340 (define_expand "negsf2"
9341 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9342 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9343 (clobber (reg:CC 17))])]
9347 /* In case operand is in memory, we will not use SSE. */
9348 if (memory_operand (operands[0], VOIDmode)
9349 && rtx_equal_p (operands[0], operands[1]))
9350 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9353 /* Using SSE is tricky, since we need bitwise negation of -0
9355 rtx reg = gen_reg_rtx (SFmode);
9356 rtx dest = operands[0];
9358 operands[1] = force_reg (SFmode, operands[1]);
9359 operands[0] = force_reg (SFmode, operands[0]);
9360 emit_move_insn (reg,
9361 gen_lowpart (SFmode,
9362 GEN_INT (trunc_int_for_mode (0x80000000,
9364 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9365 if (dest != operands[0])
9366 emit_move_insn (dest, operands[0]);
9370 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9372 (define_insn "negsf2_memory"
9373 [(set (match_operand:SF 0 "memory_operand" "=m")
9374 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9375 (clobber (reg:CC 17))]
9376 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9379 (define_insn "negsf2_ifs"
9380 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9381 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9382 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x"))
9383 (clobber (reg:CC 17))]
9385 && (reload_in_progress || reload_completed
9386 || (register_operand (operands[0], VOIDmode)
9387 && register_operand (operands[1], VOIDmode)))"
9391 [(set (match_operand:SF 0 "memory_operand" "")
9392 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9393 (use (match_operand:SF 2 "" ""))
9394 (clobber (reg:CC 17))]
9396 [(parallel [(set (match_dup 0)
9397 (neg:SF (match_dup 1)))
9398 (clobber (reg:CC 17))])])
9401 [(set (match_operand:SF 0 "register_operand" "")
9402 (neg:SF (match_operand:SF 1 "register_operand" "")))
9403 (use (match_operand:SF 2 "" ""))
9404 (clobber (reg:CC 17))]
9405 "reload_completed && !SSE_REG_P (operands[0])"
9406 [(parallel [(set (match_dup 0)
9407 (neg:SF (match_dup 1)))
9408 (clobber (reg:CC 17))])])
9411 [(set (match_operand:SF 0 "register_operand" "")
9412 (neg:SF (match_operand:SF 1 "register_operand" "")))
9413 (use (match_operand:SF 2 "register_operand" ""))
9414 (clobber (reg:CC 17))]
9415 "reload_completed && SSE_REG_P (operands[0])"
9416 [(set (subreg:TI (match_dup 0) 0)
9417 (xor:TI (subreg:TI (match_dup 1) 0)
9418 (subreg:TI (match_dup 2) 0)))]
9421 if (operands_match_p (operands[0], operands[2]))
9425 operands[1] = operands[2];
9431 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9432 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9434 (define_insn "*negsf2_if"
9435 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9436 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9437 (clobber (reg:CC 17))]
9438 "TARGET_80387 && !TARGET_SSE
9439 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9443 [(set (match_operand:SF 0 "register_operand" "")
9444 (neg:SF (match_operand:SF 1 "register_operand" "")))
9445 (clobber (reg:CC 17))]
9446 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9448 (neg:SF (match_dup 1)))]
9452 [(set (match_operand:SF 0 "register_operand" "")
9453 (neg:SF (match_operand:SF 1 "register_operand" "")))
9454 (clobber (reg:CC 17))]
9455 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9456 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9457 (clobber (reg:CC 17))])]
9458 "operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9459 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9462 [(set (match_operand 0 "memory_operand" "")
9463 (neg (match_operand 1 "memory_operand" "")))
9464 (clobber (reg:CC 17))]
9465 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9466 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9467 (clobber (reg:CC 17))])]
9470 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9472 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9475 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
9476 operands[0] = adj_offsettable_operand (operands[0], size - 1);
9477 operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
9480 (define_expand "negdf2"
9481 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9482 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9483 (clobber (reg:CC 17))])]
9487 /* In case operand is in memory, we will not use SSE. */
9488 if (memory_operand (operands[0], VOIDmode)
9489 && rtx_equal_p (operands[0], operands[1]))
9490 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9493 /* Using SSE is tricky, since we need bitwise negation of -0
9495 rtx reg = gen_reg_rtx (DFmode);
9496 #if HOST_BITS_PER_WIDE_INT >= 64
9497 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9500 rtx imm = immed_double_const (0, 0x80000000, DImode);
9502 rtx dest = operands[0];
9504 operands[1] = force_reg (DFmode, operands[1]);
9505 operands[0] = force_reg (DFmode, operands[0]);
9506 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9507 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9508 if (dest != operands[0])
9509 emit_move_insn (dest, operands[0]);
9513 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9515 (define_insn "negdf2_memory"
9516 [(set (match_operand:DF 0 "memory_operand" "=m")
9517 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9518 (clobber (reg:CC 17))]
9519 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9522 (define_insn "negdf2_ifs"
9523 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9524 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9525 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
9526 (clobber (reg:CC 17))]
9527 "TARGET_SSE2 && !TARGET_64BIT
9528 && (reload_in_progress || reload_completed
9529 || (register_operand (operands[0], VOIDmode)
9530 && register_operand (operands[1], VOIDmode)))"
9533 (define_insn "*negdf2_ifs_rex64"
9534 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9535 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9536 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9537 (clobber (reg:CC 17))]
9538 "TARGET_SSE2 && TARGET_64BIT
9539 && (reload_in_progress || reload_completed
9540 || (register_operand (operands[0], VOIDmode)
9541 && register_operand (operands[1], VOIDmode)))"
9545 [(set (match_operand:DF 0 "memory_operand" "")
9546 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9547 (use (match_operand:DF 2 "" ""))
9548 (clobber (reg:CC 17))]
9550 [(parallel [(set (match_dup 0)
9551 (neg:DF (match_dup 1)))
9552 (clobber (reg:CC 17))])])
9555 [(set (match_operand:DF 0 "register_operand" "")
9556 (neg:DF (match_operand:DF 1 "register_operand" "")))
9557 (use (match_operand:DF 2 "" ""))
9558 (clobber (reg:CC 17))]
9559 "reload_completed && !SSE_REG_P (operands[0])
9560 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9561 [(parallel [(set (match_dup 0)
9562 (neg:DF (match_dup 1)))
9563 (clobber (reg:CC 17))])])
9566 [(set (match_operand:DF 0 "register_operand" "")
9567 (neg:DF (match_operand:DF 1 "register_operand" "")))
9568 (use (match_operand:DF 2 "" ""))
9569 (clobber (reg:CC 17))]
9570 "reload_completed && GENERAL_REG_P (operands[0]) && TARGET_64BIT"
9571 [(parallel [(set (match_dup 0)
9572 (xor:DI (match_dup 1) (match_dup 2)))
9573 (clobber (reg:CC 17))])]
9574 "operands[0] = gen_lowpart (DImode, operands[0]);
9575 operands[1] = gen_lowpart (DImode, operands[1]);
9576 operands[2] = gen_lowpart (DImode, operands[2]);")
9579 [(set (match_operand:DF 0 "register_operand" "")
9580 (neg:DF (match_operand:DF 1 "register_operand" "")))
9581 (use (match_operand:DF 2 "register_operand" ""))
9582 (clobber (reg:CC 17))]
9583 "reload_completed && SSE_REG_P (operands[0])"
9584 [(set (subreg:TI (match_dup 0) 0)
9585 (xor:TI (subreg:TI (match_dup 1) 0)
9586 (subreg:TI (match_dup 2) 0)))]
9589 if (operands_match_p (operands[0], operands[2]))
9593 operands[1] = operands[2];
9598 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9599 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9601 (define_insn "*negdf2_if"
9602 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9603 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9604 (clobber (reg:CC 17))]
9605 "TARGET_80387 && !TARGET_64BIT
9606 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9609 ;; FIXME: We should to allow integer registers here. Problem is that
9610 ;; we need another scratch register to get constant from.
9611 ;; Forcing constant to mem if no register available in peep2 should be
9612 ;; safe even for PIC mode, because of RIP relative addressing.
9613 (define_insn "*negdf2_if_rex64"
9614 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9615 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9616 (clobber (reg:CC 17))]
9617 "TARGET_80387 && TARGET_64BIT
9618 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9622 [(set (match_operand:DF 0 "register_operand" "")
9623 (neg:DF (match_operand:DF 1 "register_operand" "")))
9624 (clobber (reg:CC 17))]
9625 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9627 (neg:DF (match_dup 1)))]
9631 [(set (match_operand:DF 0 "register_operand" "")
9632 (neg:DF (match_operand:DF 1 "register_operand" "")))
9633 (clobber (reg:CC 17))]
9634 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
9636 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9637 (clobber (reg:CC 17))])]
9638 "operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
9639 split_di (operands+0, 1, operands+2, operands+3);")
9641 (define_expand "negxf2"
9642 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9643 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9644 (clobber (reg:CC 17))])]
9645 "TARGET_80387 && !TARGET_64BIT"
9646 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9648 (define_expand "negtf2"
9649 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9650 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9651 (clobber (reg:CC 17))])]
9653 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9655 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9656 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9658 (define_insn "*negxf2_if"
9659 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9660 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9661 (clobber (reg:CC 17))]
9662 "TARGET_80387 && !TARGET_64BIT
9663 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9667 [(set (match_operand:XF 0 "register_operand" "")
9668 (neg:XF (match_operand:XF 1 "register_operand" "")))
9669 (clobber (reg:CC 17))]
9670 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9672 (neg:XF (match_dup 1)))]
9676 [(set (match_operand:XF 0 "register_operand" "")
9677 (neg:XF (match_operand:XF 1 "register_operand" "")))
9678 (clobber (reg:CC 17))]
9679 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9680 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9681 (clobber (reg:CC 17))])]
9682 "operands[1] = GEN_INT (0x8000);
9683 operands[0] = gen_rtx_REG (SImode,
9684 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9686 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9687 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9689 (define_insn "*negtf2_if"
9690 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9691 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9692 (clobber (reg:CC 17))]
9693 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9697 [(set (match_operand:TF 0 "register_operand" "")
9698 (neg:TF (match_operand:TF 1 "register_operand" "")))
9699 (clobber (reg:CC 17))]
9700 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9702 (neg:TF (match_dup 1)))]
9706 [(set (match_operand:TF 0 "register_operand" "")
9707 (neg:TF (match_operand:TF 1 "register_operand" "")))
9708 (clobber (reg:CC 17))]
9709 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9710 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9711 (clobber (reg:CC 17))])]
9712 "operands[1] = GEN_INT (0x8000);
9713 operands[0] = gen_rtx_REG (SImode,
9714 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9716 ;; Conditionize these after reload. If they matches before reload, we
9717 ;; lose the clobber and ability to use integer instructions.
9719 (define_insn "*negsf2_1"
9720 [(set (match_operand:SF 0 "register_operand" "=f")
9721 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9722 "TARGET_80387 && reload_completed"
9724 [(set_attr "type" "fsgn")
9725 (set_attr "mode" "SF")
9726 (set_attr "ppro_uops" "few")])
9728 (define_insn "*negdf2_1"
9729 [(set (match_operand:DF 0 "register_operand" "=f")
9730 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9731 "TARGET_80387 && reload_completed"
9733 [(set_attr "type" "fsgn")
9734 (set_attr "mode" "DF")
9735 (set_attr "ppro_uops" "few")])
9737 (define_insn "*negextendsfdf2"
9738 [(set (match_operand:DF 0 "register_operand" "=f")
9739 (neg:DF (float_extend:DF
9740 (match_operand:SF 1 "register_operand" "0"))))]
9743 [(set_attr "type" "fsgn")
9744 (set_attr "mode" "DF")
9745 (set_attr "ppro_uops" "few")])
9747 (define_insn "*negxf2_1"
9748 [(set (match_operand:XF 0 "register_operand" "=f")
9749 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9750 "TARGET_80387 && !TARGET_64BIT && reload_completed"
9752 [(set_attr "type" "fsgn")
9753 (set_attr "mode" "XF")
9754 (set_attr "ppro_uops" "few")])
9756 (define_insn "*negextenddfxf2"
9757 [(set (match_operand:XF 0 "register_operand" "=f")
9758 (neg:XF (float_extend:XF
9759 (match_operand:DF 1 "register_operand" "0"))))]
9760 "TARGET_80387 && !TARGET_64BIT"
9762 [(set_attr "type" "fsgn")
9763 (set_attr "mode" "XF")
9764 (set_attr "ppro_uops" "few")])
9766 (define_insn "*negextendsfxf2"
9767 [(set (match_operand:XF 0 "register_operand" "=f")
9768 (neg:XF (float_extend:XF
9769 (match_operand:SF 1 "register_operand" "0"))))]
9770 "TARGET_80387 && !TARGET_64BIT"
9772 [(set_attr "type" "fsgn")
9773 (set_attr "mode" "XF")
9774 (set_attr "ppro_uops" "few")])
9776 (define_insn "*negtf2_1"
9777 [(set (match_operand:TF 0 "register_operand" "=f")
9778 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9779 "TARGET_80387 && reload_completed"
9781 [(set_attr "type" "fsgn")
9782 (set_attr "mode" "XF")
9783 (set_attr "ppro_uops" "few")])
9785 (define_insn "*negextenddftf2"
9786 [(set (match_operand:TF 0 "register_operand" "=f")
9787 (neg:TF (float_extend:TF
9788 (match_operand:DF 1 "register_operand" "0"))))]
9791 [(set_attr "type" "fsgn")
9792 (set_attr "mode" "XF")
9793 (set_attr "ppro_uops" "few")])
9795 (define_insn "*negextendsftf2"
9796 [(set (match_operand:TF 0 "register_operand" "=f")
9797 (neg:TF (float_extend:TF
9798 (match_operand:SF 1 "register_operand" "0"))))]
9801 [(set_attr "type" "fsgn")
9802 (set_attr "mode" "XF")
9803 (set_attr "ppro_uops" "few")])
9805 ;; Absolute value instructions
9807 (define_expand "abssf2"
9808 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9809 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9810 (clobber (reg:CC 17))])]
9814 /* In case operand is in memory, we will not use SSE. */
9815 if (memory_operand (operands[0], VOIDmode)
9816 && rtx_equal_p (operands[0], operands[1]))
9817 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9820 /* Using SSE is tricky, since we need bitwise negation of -0
9822 rtx reg = gen_reg_rtx (SFmode);
9823 rtx dest = operands[0];
9825 operands[1] = force_reg (SFmode, operands[1]);
9826 operands[0] = force_reg (SFmode, operands[0]);
9827 emit_move_insn (reg,
9828 gen_lowpart (SFmode,
9829 GEN_INT (trunc_int_for_mode (0x80000000,
9831 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9832 if (dest != operands[0])
9833 emit_move_insn (dest, operands[0]);
9837 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9839 (define_insn "abssf2_memory"
9840 [(set (match_operand:SF 0 "memory_operand" "=m")
9841 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9842 (clobber (reg:CC 17))]
9843 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9846 (define_insn "abssf2_ifs"
9847 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf")
9848 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9849 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x"))
9850 (clobber (reg:CC 17))]
9852 && (reload_in_progress || reload_completed
9853 || (register_operand (operands[0], VOIDmode)
9854 && register_operand (operands[1], VOIDmode)))"
9858 [(set (match_operand:SF 0 "memory_operand" "")
9859 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9860 (use (match_operand:SF 2 "" ""))
9861 (clobber (reg:CC 17))]
9863 [(parallel [(set (match_dup 0)
9864 (abs:SF (match_dup 1)))
9865 (clobber (reg:CC 17))])])
9868 [(set (match_operand:SF 0 "register_operand" "")
9869 (abs:SF (match_operand:SF 1 "register_operand" "")))
9870 (use (match_operand:SF 2 "" ""))
9871 (clobber (reg:CC 17))]
9872 "reload_completed && !SSE_REG_P (operands[0])"
9873 [(parallel [(set (match_dup 0)
9874 (abs:SF (match_dup 1)))
9875 (clobber (reg:CC 17))])])
9878 [(set (match_operand:SF 0 "register_operand" "")
9879 (abs:SF (match_operand:SF 1 "register_operand" "")))
9880 (use (match_operand:SF 2 "register_operand" ""))
9881 (clobber (reg:CC 17))]
9882 "reload_completed && SSE_REG_P (operands[0])"
9883 [(set (subreg:TI (match_dup 0) 0)
9884 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9885 (subreg:TI (match_dup 1) 0)))])
9887 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9888 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9890 (define_insn "*abssf2_if"
9891 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9892 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9893 (clobber (reg:CC 17))]
9894 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9898 [(set (match_operand:SF 0 "register_operand" "")
9899 (abs:SF (match_operand:SF 1 "register_operand" "")))
9900 (clobber (reg:CC 17))]
9901 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9903 (abs:SF (match_dup 1)))]
9907 [(set (match_operand:SF 0 "register_operand" "")
9908 (abs:SF (match_operand:SF 1 "register_operand" "")))
9909 (clobber (reg:CC 17))]
9910 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9911 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9912 (clobber (reg:CC 17))])]
9913 "operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
9914 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9917 [(set (match_operand 0 "memory_operand" "")
9918 (abs (match_operand 1 "memory_operand" "")))
9919 (clobber (reg:CC 17))]
9920 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9921 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9922 (clobber (reg:CC 17))])]
9925 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9927 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9930 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
9931 operands[0] = adj_offsettable_operand (operands[0], size - 1);
9932 operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
9935 (define_expand "absdf2"
9936 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9937 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9938 (clobber (reg:CC 17))])]
9942 /* In case operand is in memory, we will not use SSE. */
9943 if (memory_operand (operands[0], VOIDmode)
9944 && rtx_equal_p (operands[0], operands[1]))
9945 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9948 /* Using SSE is tricky, since we need bitwise negation of -0
9950 rtx reg = gen_reg_rtx (DFmode);
9951 #if HOST_BITS_PER_WIDE_INT >= 64
9952 rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
9955 rtx imm = immed_double_const (0, 0x80000000, DImode);
9957 rtx dest = operands[0];
9959 operands[1] = force_reg (DFmode, operands[1]);
9960 operands[0] = force_reg (DFmode, operands[0]);
9961 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9962 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9963 if (dest != operands[0])
9964 emit_move_insn (dest, operands[0]);
9968 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9970 (define_insn "absdf2_memory"
9971 [(set (match_operand:DF 0 "memory_operand" "=m")
9972 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9973 (clobber (reg:CC 17))]
9974 "ix86_unary_operator_ok (ABS, DFmode, operands)"
9977 (define_insn "absdf2_ifs"
9978 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf")
9979 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
9980 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
9981 (clobber (reg:CC 17))]
9982 "TARGET_SSE2 && !TARGET_64BIT
9983 && (reload_in_progress || reload_completed
9984 || (register_operand (operands[0], VOIDmode)
9985 && register_operand (operands[1], VOIDmode)))"
9988 (define_insn "*absdf2_ifs_rex64"
9989 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr")
9990 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
9991 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
9992 (clobber (reg:CC 17))]
9993 "TARGET_SSE2 && TARGET_64BIT
9994 && (reload_in_progress || reload_completed
9995 || (register_operand (operands[0], VOIDmode)
9996 && register_operand (operands[1], VOIDmode)))"
10000 [(set (match_operand:DF 0 "memory_operand" "")
10001 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10002 (use (match_operand:DF 2 "" ""))
10003 (clobber (reg:CC 17))]
10005 [(parallel [(set (match_dup 0)
10006 (abs:DF (match_dup 1)))
10007 (clobber (reg:CC 17))])])
10010 [(set (match_operand:DF 0 "register_operand" "")
10011 (abs:DF (match_operand:DF 1 "register_operand" "")))
10012 (use (match_operand:DF 2 "" ""))
10013 (clobber (reg:CC 17))]
10014 "reload_completed && !SSE_REG_P (operands[0])"
10015 [(parallel [(set (match_dup 0)
10016 (abs:DF (match_dup 1)))
10017 (clobber (reg:CC 17))])])
10020 [(set (match_operand:DF 0 "register_operand" "")
10021 (abs:DF (match_operand:DF 1 "register_operand" "")))
10022 (use (match_operand:DF 2 "register_operand" ""))
10023 (clobber (reg:CC 17))]
10024 "reload_completed && SSE_REG_P (operands[0])"
10025 [(set (subreg:TI (match_dup 0) 0)
10026 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
10027 (subreg:TI (match_dup 1) 0)))])
10030 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10031 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10033 (define_insn "*absdf2_if"
10034 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10035 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10036 (clobber (reg:CC 17))]
10037 "TARGET_80387 && !TARGET_64BIT
10038 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10041 ;; FIXME: We should to allow integer registers here. Problem is that
10042 ;; we need another scratch register to get constant from.
10043 ;; Forcing constant to mem if no register available in peep2 should be
10044 ;; safe even for PIC mode, because of RIP relative addressing.
10045 (define_insn "*absdf2_if_rex64"
10046 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10047 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10048 (clobber (reg:CC 17))]
10049 "TARGET_80387 && TARGET_64BIT
10050 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10054 [(set (match_operand:DF 0 "register_operand" "")
10055 (abs:DF (match_operand:DF 1 "register_operand" "")))
10056 (clobber (reg:CC 17))]
10057 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10058 [(set (match_dup 0)
10059 (abs:DF (match_dup 1)))]
10063 [(set (match_operand:DF 0 "register_operand" "")
10064 (abs:DF (match_operand:DF 1 "register_operand" "")))
10065 (clobber (reg:CC 17))]
10066 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
10068 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10069 (clobber (reg:CC 17))])]
10070 "operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
10071 split_di (operands+0, 1, operands+2, operands+3);")
10073 (define_expand "absxf2"
10074 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10075 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10076 (clobber (reg:CC 17))])]
10077 "TARGET_80387 && !TARGET_64BIT"
10078 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10080 (define_expand "abstf2"
10081 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10082 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10083 (clobber (reg:CC 17))])]
10085 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10087 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10088 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10090 (define_insn "*absxf2_if"
10091 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10092 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10093 (clobber (reg:CC 17))]
10094 "TARGET_80387 && !TARGET_64BIT
10095 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10099 [(set (match_operand:XF 0 "register_operand" "")
10100 (abs:XF (match_operand:XF 1 "register_operand" "")))
10101 (clobber (reg:CC 17))]
10102 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10103 [(set (match_dup 0)
10104 (abs:XF (match_dup 1)))]
10108 [(set (match_operand:XF 0 "register_operand" "")
10109 (abs:XF (match_operand:XF 1 "register_operand" "")))
10110 (clobber (reg:CC 17))]
10111 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10112 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10113 (clobber (reg:CC 17))])]
10114 "operands[1] = GEN_INT (~0x8000);
10115 operands[0] = gen_rtx_REG (SImode,
10116 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10118 (define_insn "*abstf2_if"
10119 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10120 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10121 (clobber (reg:CC 17))]
10122 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10126 [(set (match_operand:TF 0 "register_operand" "")
10127 (abs:TF (match_operand:TF 1 "register_operand" "")))
10128 (clobber (reg:CC 17))]
10129 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
10130 [(set (match_dup 0)
10131 (abs:TF (match_dup 1)))]
10135 [(set (match_operand:TF 0 "register_operand" "")
10136 (abs:TF (match_operand:TF 1 "register_operand" "")))
10137 (clobber (reg:CC 17))]
10138 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
10139 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10140 (clobber (reg:CC 17))])]
10141 "operands[1] = GEN_INT (~0x8000);
10142 operands[0] = gen_rtx_REG (SImode,
10143 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10145 (define_insn "*abssf2_1"
10146 [(set (match_operand:SF 0 "register_operand" "=f")
10147 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10148 "TARGET_80387 && reload_completed"
10150 [(set_attr "type" "fsgn")
10151 (set_attr "mode" "SF")])
10153 (define_insn "*absdf2_1"
10154 [(set (match_operand:DF 0 "register_operand" "=f")
10155 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10156 "TARGET_80387 && reload_completed"
10158 [(set_attr "type" "fsgn")
10159 (set_attr "mode" "DF")])
10161 (define_insn "*absextendsfdf2"
10162 [(set (match_operand:DF 0 "register_operand" "=f")
10163 (abs:DF (float_extend:DF
10164 (match_operand:SF 1 "register_operand" "0"))))]
10167 [(set_attr "type" "fsgn")
10168 (set_attr "mode" "DF")])
10170 (define_insn "*absxf2_1"
10171 [(set (match_operand:XF 0 "register_operand" "=f")
10172 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10173 "TARGET_80387 && !TARGET_64BIT && reload_completed"
10175 [(set_attr "type" "fsgn")
10176 (set_attr "mode" "DF")])
10178 (define_insn "*absextenddfxf2"
10179 [(set (match_operand:XF 0 "register_operand" "=f")
10180 (abs:XF (float_extend:XF
10181 (match_operand:DF 1 "register_operand" "0"))))]
10182 "TARGET_80387 && !TARGET_64BIT"
10184 [(set_attr "type" "fsgn")
10185 (set_attr "mode" "XF")])
10187 (define_insn "*absextendsfxf2"
10188 [(set (match_operand:XF 0 "register_operand" "=f")
10189 (abs:XF (float_extend:XF
10190 (match_operand:SF 1 "register_operand" "0"))))]
10191 "TARGET_80387 && !TARGET_64BIT"
10193 [(set_attr "type" "fsgn")
10194 (set_attr "mode" "XF")])
10196 (define_insn "*abstf2_1"
10197 [(set (match_operand:TF 0 "register_operand" "=f")
10198 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10199 "TARGET_80387 && reload_completed"
10201 [(set_attr "type" "fsgn")
10202 (set_attr "mode" "DF")])
10204 (define_insn "*absextenddftf2"
10205 [(set (match_operand:TF 0 "register_operand" "=f")
10206 (abs:TF (float_extend:TF
10207 (match_operand:DF 1 "register_operand" "0"))))]
10210 [(set_attr "type" "fsgn")
10211 (set_attr "mode" "XF")])
10213 (define_insn "*absextendsftf2"
10214 [(set (match_operand:TF 0 "register_operand" "=f")
10215 (abs:TF (float_extend:TF
10216 (match_operand:SF 1 "register_operand" "0"))))]
10219 [(set_attr "type" "fsgn")
10220 (set_attr "mode" "XF")])
10222 ;; One complement instructions
10224 (define_expand "one_cmpldi2"
10225 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10226 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10228 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10230 (define_insn "*one_cmpldi2_1_rex64"
10231 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10232 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10233 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10235 [(set_attr "type" "negnot")
10236 (set_attr "mode" "DI")])
10238 (define_insn "*one_cmpldi2_2_rex64"
10240 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10242 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10243 (not:DI (match_dup 1)))]
10244 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10245 && ix86_unary_operator_ok (NOT, DImode, operands)"
10247 [(set_attr "type" "alu1")
10248 (set_attr "mode" "DI")])
10252 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10254 (set (match_operand:DI 0 "nonimmediate_operand" "")
10255 (not:DI (match_dup 1)))]
10256 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10257 [(parallel [(set (reg:CCNO 17)
10258 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10261 (xor:DI (match_dup 1) (const_int -1)))])]
10264 (define_expand "one_cmplsi2"
10265 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10266 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10268 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10270 (define_insn "*one_cmplsi2_1"
10271 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10272 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10273 "ix86_unary_operator_ok (NOT, SImode, operands)"
10275 [(set_attr "type" "negnot")
10276 (set_attr "mode" "SI")])
10278 ;; ??? Currently never generated - xor is used instead.
10279 (define_insn "*one_cmplsi2_1_zext"
10280 [(set (match_operand:DI 0 "register_operand" "=r")
10281 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10282 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10284 [(set_attr "type" "negnot")
10285 (set_attr "mode" "SI")])
10287 (define_insn "*one_cmplsi2_2"
10289 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10291 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10292 (not:SI (match_dup 1)))]
10293 "ix86_match_ccmode (insn, CCNOmode)
10294 && ix86_unary_operator_ok (NOT, SImode, operands)"
10296 [(set_attr "type" "alu1")
10297 (set_attr "mode" "SI")])
10301 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10303 (set (match_operand:SI 0 "nonimmediate_operand" "")
10304 (not:SI (match_dup 1)))]
10305 "ix86_match_ccmode (insn, CCNOmode)"
10306 [(parallel [(set (reg:CCNO 17)
10307 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10310 (xor:SI (match_dup 1) (const_int -1)))])]
10313 ;; ??? Currently never generated - xor is used instead.
10314 (define_insn "*one_cmplsi2_2_zext"
10316 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10318 (set (match_operand:DI 0 "register_operand" "=r")
10319 (zero_extend:DI (not:SI (match_dup 1))))]
10320 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10321 && ix86_unary_operator_ok (NOT, SImode, operands)"
10323 [(set_attr "type" "alu1")
10324 (set_attr "mode" "SI")])
10328 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10330 (set (match_operand:DI 0 "register_operand" "")
10331 (zero_extend:DI (not:SI (match_dup 1))))]
10332 "ix86_match_ccmode (insn, CCNOmode)"
10333 [(parallel [(set (reg:CCNO 17)
10334 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10337 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10340 (define_expand "one_cmplhi2"
10341 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10342 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10343 "TARGET_HIMODE_MATH"
10344 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10346 (define_insn "*one_cmplhi2_1"
10347 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10348 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10349 "ix86_unary_operator_ok (NOT, HImode, operands)"
10351 [(set_attr "type" "negnot")
10352 (set_attr "mode" "HI")])
10354 (define_insn "*one_cmplhi2_2"
10356 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10358 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10359 (not:HI (match_dup 1)))]
10360 "ix86_match_ccmode (insn, CCNOmode)
10361 && ix86_unary_operator_ok (NEG, HImode, operands)"
10363 [(set_attr "type" "alu1")
10364 (set_attr "mode" "HI")])
10368 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10370 (set (match_operand:HI 0 "nonimmediate_operand" "")
10371 (not:HI (match_dup 1)))]
10372 "ix86_match_ccmode (insn, CCNOmode)"
10373 [(parallel [(set (reg:CCNO 17)
10374 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10377 (xor:HI (match_dup 1) (const_int -1)))])]
10380 ;; %%% Potential partial reg stall on alternative 1. What to do?
10381 (define_expand "one_cmplqi2"
10382 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10383 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10384 "TARGET_QIMODE_MATH"
10385 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10387 (define_insn "*one_cmplqi2_1"
10388 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10389 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10390 "ix86_unary_operator_ok (NOT, QImode, operands)"
10394 [(set_attr "type" "negnot")
10395 (set_attr "mode" "QI,SI")])
10397 (define_insn "*one_cmplqi2_2"
10399 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10401 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10402 (not:QI (match_dup 1)))]
10403 "ix86_match_ccmode (insn, CCNOmode)
10404 && ix86_unary_operator_ok (NOT, QImode, operands)"
10406 [(set_attr "type" "alu1")
10407 (set_attr "mode" "QI")])
10411 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10413 (set (match_operand:QI 0 "nonimmediate_operand" "")
10414 (not:QI (match_dup 1)))]
10415 "ix86_match_ccmode (insn, CCNOmode)"
10416 [(parallel [(set (reg:CCNO 17)
10417 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10420 (xor:QI (match_dup 1) (const_int -1)))])]
10423 ;; Arithmetic shift instructions
10425 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10426 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10427 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10428 ;; from the assembler input.
10430 ;; This instruction shifts the target reg/mem as usual, but instead of
10431 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10432 ;; is a left shift double, bits are taken from the high order bits of
10433 ;; reg, else if the insn is a shift right double, bits are taken from the
10434 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10435 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10437 ;; Since sh[lr]d does not change the `reg' operand, that is done
10438 ;; separately, making all shifts emit pairs of shift double and normal
10439 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10440 ;; support a 63 bit shift, each shift where the count is in a reg expands
10441 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10443 ;; If the shift count is a constant, we need never emit more than one
10444 ;; shift pair, instead using moves and sign extension for counts greater
10447 (define_expand "ashldi3"
10448 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10449 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10450 (match_operand:QI 2 "nonmemory_operand" "")))
10451 (clobber (reg:CC 17))])]
10455 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10457 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10460 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10464 (define_insn "*ashldi3_1_rex64"
10465 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10466 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10467 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10468 (clobber (reg:CC 17))]
10469 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10472 switch (get_attr_type (insn))
10475 if (operands[2] != const1_rtx)
10477 if (!rtx_equal_p (operands[0], operands[1]))
10479 return \"add{q}\\t{%0, %0|%0, %0}\";
10482 if (GET_CODE (operands[2]) != CONST_INT
10483 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10485 operands[1] = gen_rtx_MULT (DImode, operands[1],
10486 GEN_INT (1 << INTVAL (operands[2])));
10487 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
10490 if (REG_P (operands[2]))
10491 return \"sal{q}\\t{%b2, %0|%0, %b2}\";
10492 else if (GET_CODE (operands[2]) == CONST_INT
10493 && INTVAL (operands[2]) == 1
10494 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10495 return \"sal{q}\\t%0\";
10497 return \"sal{q}\\t{%2, %0|%0, %2}\";
10500 [(set (attr "type")
10501 (cond [(eq_attr "alternative" "1")
10502 (const_string "lea")
10503 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10505 (match_operand 0 "register_operand" ""))
10506 (match_operand 2 "const1_operand" ""))
10507 (const_string "alu")
10509 (const_string "ishift")))
10510 (set_attr "mode" "DI")])
10512 ;; Convert lea to the lea pattern to avoid flags dependency.
10514 [(set (match_operand:DI 0 "register_operand" "")
10515 (ashift:DI (match_operand:DI 1 "register_operand" "")
10516 (match_operand:QI 2 "immediate_operand" "")))
10517 (clobber (reg:CC 17))]
10520 && true_regnum (operands[0]) != true_regnum (operands[1])"
10521 [(set (match_dup 0)
10522 (mult:DI (match_dup 1)
10524 "operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10527 ;; This pattern can't accept a variable shift count, since shifts by
10528 ;; zero don't affect the flags. We assume that shifts by constant
10529 ;; zero are optimized away.
10530 (define_insn "*ashldi3_cmp_rex64"
10533 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10534 (match_operand:QI 2 "immediate_operand" "e"))
10536 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10537 (ashift:DI (match_dup 1) (match_dup 2)))]
10538 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10539 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10542 switch (get_attr_type (insn))
10545 if (operands[2] != const1_rtx)
10547 return \"add{q}\\t{%0, %0|%0, %0}\";
10550 if (REG_P (operands[2]))
10551 return \"sal{q}\\t{%b2, %0|%0, %b2}\";
10552 else if (GET_CODE (operands[2]) == CONST_INT
10553 && INTVAL (operands[2]) == 1
10554 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10555 return \"sal{q}\\t%0\";
10557 return \"sal{q}\\t{%2, %0|%0, %2}\";
10560 [(set (attr "type")
10561 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10563 (match_operand 0 "register_operand" ""))
10564 (match_operand 2 "const1_operand" ""))
10565 (const_string "alu")
10567 (const_string "ishift")))
10568 (set_attr "mode" "DI")])
10570 (define_insn "ashldi3_1"
10571 [(set (match_operand:DI 0 "register_operand" "=r")
10572 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10573 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10574 (clobber (match_scratch:SI 3 "=&r"))
10575 (clobber (reg:CC 17))]
10576 "!TARGET_64BIT && TARGET_CMOVE"
10578 [(set_attr "type" "multi")])
10580 (define_insn "*ashldi3_2"
10581 [(set (match_operand:DI 0 "register_operand" "=r")
10582 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10583 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10584 (clobber (reg:CC 17))]
10587 [(set_attr "type" "multi")])
10590 [(set (match_operand:DI 0 "register_operand" "")
10591 (ashift:DI (match_operand:DI 1 "register_operand" "")
10592 (match_operand:QI 2 "nonmemory_operand" "")))
10593 (clobber (match_scratch:SI 3 ""))
10594 (clobber (reg:CC 17))]
10595 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10597 "ix86_split_ashldi (operands, operands[3]); DONE;")
10600 [(set (match_operand:DI 0 "register_operand" "")
10601 (ashift:DI (match_operand:DI 1 "register_operand" "")
10602 (match_operand:QI 2 "nonmemory_operand" "")))
10603 (clobber (reg:CC 17))]
10604 "!TARGET_64BIT && reload_completed"
10606 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10608 (define_insn "x86_shld_1"
10609 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10610 (ior:SI (ashift:SI (match_dup 0)
10611 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10612 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10613 (minus:QI (const_int 32) (match_dup 2)))))
10614 (clobber (reg:CC 17))]
10617 shld{l}\\t{%2, %1, %0|%0, %1, %2}
10618 shld{l}\\t{%s2%1, %0|%0, %1, %2}"
10619 [(set_attr "type" "ishift")
10620 (set_attr "prefix_0f" "1")
10621 (set_attr "mode" "SI")
10622 (set_attr "pent_pair" "np")
10623 (set_attr "athlon_decode" "vector")
10624 (set_attr "ppro_uops" "few")])
10626 (define_expand "x86_shift_adj_1"
10628 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10631 (set (match_operand:SI 0 "register_operand" "")
10632 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10633 (match_operand:SI 1 "register_operand" "")
10636 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10637 (match_operand:SI 3 "register_operand" "r")
10642 (define_expand "x86_shift_adj_2"
10643 [(use (match_operand:SI 0 "register_operand" ""))
10644 (use (match_operand:SI 1 "register_operand" ""))
10645 (use (match_operand:QI 2 "register_operand" ""))]
10649 rtx label = gen_label_rtx ();
10652 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10654 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10655 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10656 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10657 gen_rtx_LABEL_REF (VOIDmode, label),
10659 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10660 JUMP_LABEL (tmp) = label;
10662 emit_move_insn (operands[0], operands[1]);
10663 emit_move_insn (operands[1], const0_rtx);
10665 emit_label (label);
10666 LABEL_NUSES (label) = 1;
10671 (define_expand "ashlsi3"
10672 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10673 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10674 (match_operand:QI 2 "nonmemory_operand" "")))
10675 (clobber (reg:CC 17))]
10677 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10679 (define_insn "*ashlsi3_1"
10680 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10681 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10682 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10683 (clobber (reg:CC 17))]
10684 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10687 switch (get_attr_type (insn))
10690 if (operands[2] != const1_rtx)
10692 if (!rtx_equal_p (operands[0], operands[1]))
10694 return \"add{l}\\t{%0, %0|%0, %0}\";
10700 if (REG_P (operands[2]))
10701 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
10702 else if (GET_CODE (operands[2]) == CONST_INT
10703 && INTVAL (operands[2]) == 1
10704 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10705 return \"sal{l}\\t%0\";
10707 return \"sal{l}\\t{%2, %0|%0, %2}\";
10710 [(set (attr "type")
10711 (cond [(eq_attr "alternative" "1")
10712 (const_string "lea")
10713 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10715 (match_operand 0 "register_operand" ""))
10716 (match_operand 2 "const1_operand" ""))
10717 (const_string "alu")
10719 (const_string "ishift")))
10720 (set_attr "mode" "SI")])
10722 ;; Convert lea to the lea pattern to avoid flags dependency.
10724 [(set (match_operand 0 "register_operand" "")
10725 (ashift (match_operand 1 "register_operand" "")
10726 (match_operand:QI 2 "const_int_operand" "")))
10727 (clobber (reg:CC 17))]
10729 && true_regnum (operands[0]) != true_regnum (operands[1])"
10734 operands[0] = gen_lowpart (SImode, operands[0]);
10735 operands[1] = gen_lowpart (Pmode, operands[1]);
10736 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10738 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10739 if (Pmode != SImode)
10740 pat = gen_rtx_SUBREG (SImode, pat, 0);
10741 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10745 (define_insn "*ashlsi3_1_zext"
10746 [(set (match_operand:DI 0 "register_operand" "=r,r")
10747 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10748 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10749 (clobber (reg:CC 17))]
10750 "ix86_binary_operator_ok (ASHIFT, SImode, operands) && TARGET_64BIT"
10753 switch (get_attr_type (insn))
10756 if (operands[2] != const1_rtx)
10758 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10764 if (REG_P (operands[2]))
10765 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10766 else if (GET_CODE (operands[2]) == CONST_INT
10767 && INTVAL (operands[2]) == 1
10768 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10769 return \"sal{l}\\t%k0\";
10771 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10774 [(set (attr "type")
10775 (cond [(eq_attr "alternative" "1")
10776 (const_string "lea")
10777 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10779 (match_operand 2 "const1_operand" ""))
10780 (const_string "alu")
10782 (const_string "ishift")))
10783 (set_attr "mode" "SI")])
10785 ;; Convert lea to the lea pattern to avoid flags dependency.
10787 [(set (match_operand:DI 0 "register_operand" "")
10788 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10789 (match_operand:QI 2 "const_int_operand" ""))))
10790 (clobber (reg:CC 17))]
10792 && true_regnum (operands[0]) != true_regnum (operands[1])"
10793 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10796 operands[1] = gen_lowpart (Pmode, operands[1]);
10797 operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
10801 ;; This pattern can't accept a variable shift count, since shifts by
10802 ;; zero don't affect the flags. We assume that shifts by constant
10803 ;; zero are optimized away.
10804 (define_insn "*ashlsi3_cmp"
10807 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10808 (match_operand:QI 2 "immediate_operand" "I"))
10810 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10811 (ashift:SI (match_dup 1) (match_dup 2)))]
10812 "ix86_match_ccmode (insn, CCGOCmode)
10813 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10816 switch (get_attr_type (insn))
10819 if (operands[2] != const1_rtx)
10821 return \"add{l}\\t{%0, %0|%0, %0}\";
10824 if (REG_P (operands[2]))
10825 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
10826 else if (GET_CODE (operands[2]) == CONST_INT
10827 && INTVAL (operands[2]) == 1
10828 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10829 return \"sal{l}\\t%0\";
10831 return \"sal{l}\\t{%2, %0|%0, %2}\";
10834 [(set (attr "type")
10835 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10837 (match_operand 0 "register_operand" ""))
10838 (match_operand 2 "const1_operand" ""))
10839 (const_string "alu")
10841 (const_string "ishift")))
10842 (set_attr "mode" "SI")])
10844 (define_insn "*ashlsi3_cmp_zext"
10847 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10848 (match_operand:QI 2 "immediate_operand" "I"))
10850 (set (match_operand:DI 0 "register_operand" "=r")
10851 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10852 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10853 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10856 switch (get_attr_type (insn))
10859 if (operands[2] != const1_rtx)
10861 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10864 if (REG_P (operands[2]))
10865 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10866 else if (GET_CODE (operands[2]) == CONST_INT
10867 && INTVAL (operands[2]) == 1
10868 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10869 return \"sal{l}\\t%k0\";
10871 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10874 [(set (attr "type")
10875 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10877 (match_operand 2 "const1_operand" ""))
10878 (const_string "alu")
10880 (const_string "ishift")))
10881 (set_attr "mode" "SI")])
10883 (define_expand "ashlhi3"
10884 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10885 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10886 (match_operand:QI 2 "nonmemory_operand" "")))
10887 (clobber (reg:CC 17))]
10888 "TARGET_HIMODE_MATH"
10889 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10891 (define_insn "*ashlhi3_1_lea"
10892 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10893 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10894 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10895 (clobber (reg:CC 17))]
10896 "!TARGET_PARTIAL_REG_STALL
10897 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10900 switch (get_attr_type (insn))
10905 if (operands[2] != const1_rtx)
10907 return \"add{w}\\t{%0, %0|%0, %0}\";
10910 if (REG_P (operands[2]))
10911 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10912 else if (GET_CODE (operands[2]) == CONST_INT
10913 && INTVAL (operands[2]) == 1
10914 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10915 return \"sal{w}\\t%0\";
10917 return \"sal{w}\\t{%2, %0|%0, %2}\";
10920 [(set (attr "type")
10921 (cond [(eq_attr "alternative" "1")
10922 (const_string "lea")
10923 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10925 (match_operand 0 "register_operand" ""))
10926 (match_operand 2 "const1_operand" ""))
10927 (const_string "alu")
10929 (const_string "ishift")))
10930 (set_attr "mode" "HI,SI")])
10932 (define_insn "*ashlhi3_1"
10933 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10934 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10935 (match_operand:QI 2 "nonmemory_operand" "cI")))
10936 (clobber (reg:CC 17))]
10937 "TARGET_PARTIAL_REG_STALL
10938 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10941 switch (get_attr_type (insn))
10944 if (operands[2] != const1_rtx)
10946 return \"add{w}\\t{%0, %0|%0, %0}\";
10949 if (REG_P (operands[2]))
10950 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10951 else if (GET_CODE (operands[2]) == CONST_INT
10952 && INTVAL (operands[2]) == 1
10953 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10954 return \"sal{w}\\t%0\";
10956 return \"sal{w}\\t{%2, %0|%0, %2}\";
10959 [(set (attr "type")
10960 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10962 (match_operand 0 "register_operand" ""))
10963 (match_operand 2 "const1_operand" ""))
10964 (const_string "alu")
10966 (const_string "ishift")))
10967 (set_attr "mode" "HI")])
10969 ;; This pattern can't accept a variable shift count, since shifts by
10970 ;; zero don't affect the flags. We assume that shifts by constant
10971 ;; zero are optimized away.
10972 (define_insn "*ashlhi3_cmp"
10975 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10976 (match_operand:QI 2 "immediate_operand" "I"))
10978 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10979 (ashift:HI (match_dup 1) (match_dup 2)))]
10980 "ix86_match_ccmode (insn, CCGOCmode)
10981 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10984 switch (get_attr_type (insn))
10987 if (operands[2] != const1_rtx)
10989 return \"add{w}\\t{%0, %0|%0, %0}\";
10992 if (REG_P (operands[2]))
10993 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10994 else if (GET_CODE (operands[2]) == CONST_INT
10995 && INTVAL (operands[2]) == 1
10996 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10997 return \"sal{w}\\t%0\";
10999 return \"sal{w}\\t{%2, %0|%0, %2}\";
11002 [(set (attr "type")
11003 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11005 (match_operand 0 "register_operand" ""))
11006 (match_operand 2 "const1_operand" ""))
11007 (const_string "alu")
11009 (const_string "ishift")))
11010 (set_attr "mode" "HI")])
11012 (define_expand "ashlqi3"
11013 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11014 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11015 (match_operand:QI 2 "nonmemory_operand" "")))
11016 (clobber (reg:CC 17))]
11017 "TARGET_QIMODE_MATH"
11018 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11020 ;; %%% Potential partial reg stall on alternative 2. What to do?
11022 (define_insn "*ashlqi3_1_lea"
11023 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11024 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11025 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11026 (clobber (reg:CC 17))]
11027 "!TARGET_PARTIAL_REG_STALL
11028 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11031 switch (get_attr_type (insn))
11036 if (operands[2] != const1_rtx)
11038 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11039 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
11041 return \"add{b}\\t{%0, %0|%0, %0}\";
11044 if (REG_P (operands[2]))
11046 if (get_attr_mode (insn) == MODE_SI)
11047 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
11049 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11051 else if (GET_CODE (operands[2]) == CONST_INT
11052 && INTVAL (operands[2]) == 1
11053 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11055 if (get_attr_mode (insn) == MODE_SI)
11056 return \"sal{l}\\t%0\";
11058 return \"sal{b}\\t%0\";
11062 if (get_attr_mode (insn) == MODE_SI)
11063 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
11065 return \"sal{b}\\t{%2, %0|%0, %2}\";
11069 [(set (attr "type")
11070 (cond [(eq_attr "alternative" "2")
11071 (const_string "lea")
11072 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11074 (match_operand 0 "register_operand" ""))
11075 (match_operand 2 "const1_operand" ""))
11076 (const_string "alu")
11078 (const_string "ishift")))
11079 (set_attr "mode" "QI,SI,SI")])
11081 (define_insn "*ashlqi3_1"
11082 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11083 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11084 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11085 (clobber (reg:CC 17))]
11086 "TARGET_PARTIAL_REG_STALL
11087 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11090 switch (get_attr_type (insn))
11093 if (operands[2] != const1_rtx)
11095 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11096 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
11098 return \"add{b}\\t{%0, %0|%0, %0}\";
11101 if (REG_P (operands[2]))
11103 if (get_attr_mode (insn) == MODE_SI)
11104 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
11106 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11108 else if (GET_CODE (operands[2]) == CONST_INT
11109 && INTVAL (operands[2]) == 1
11110 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11112 if (get_attr_mode (insn) == MODE_SI)
11113 return \"sal{l}\\t%0\";
11115 return \"sal{b}\\t%0\";
11119 if (get_attr_mode (insn) == MODE_SI)
11120 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
11122 return \"sal{b}\\t{%2, %0|%0, %2}\";
11126 [(set (attr "type")
11127 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11129 (match_operand 0 "register_operand" ""))
11130 (match_operand 2 "const1_operand" ""))
11131 (const_string "alu")
11133 (const_string "ishift")))
11134 (set_attr "mode" "QI,SI")])
11136 ;; This pattern can't accept a variable shift count, since shifts by
11137 ;; zero don't affect the flags. We assume that shifts by constant
11138 ;; zero are optimized away.
11139 (define_insn "*ashlqi3_cmp"
11142 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11143 (match_operand:QI 2 "immediate_operand" "I"))
11145 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11146 (ashift:QI (match_dup 1) (match_dup 2)))]
11147 "ix86_match_ccmode (insn, CCGOCmode)
11148 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11151 switch (get_attr_type (insn))
11154 if (operands[2] != const1_rtx)
11156 return \"add{b}\\t{%0, %0|%0, %0}\";
11159 if (REG_P (operands[2]))
11160 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
11161 else if (GET_CODE (operands[2]) == CONST_INT
11162 && INTVAL (operands[2]) == 1
11163 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
11164 return \"sal{b}\\t%0\";
11166 return \"sal{b}\\t{%2, %0|%0, %2}\";
11169 [(set (attr "type")
11170 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11172 (match_operand 0 "register_operand" ""))
11173 (match_operand 2 "const1_operand" ""))
11174 (const_string "alu")
11176 (const_string "ishift")))
11177 (set_attr "mode" "QI")])
11179 ;; See comment above `ashldi3' about how this works.
11181 (define_expand "ashrdi3"
11182 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11183 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11184 (match_operand:QI 2 "nonmemory_operand" "")))
11185 (clobber (reg:CC 17))])]
11189 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11191 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11194 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11198 (define_insn "ashrdi3_63_rex64"
11199 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11200 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11201 (match_operand:DI 2 "const_int_operand" "i,i")))
11202 (clobber (reg:CC 17))]
11203 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11204 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11207 sar{q}\\t{%2, %0|%0, %2}"
11208 [(set_attr "type" "imovx,ishift")
11209 (set_attr "prefix_0f" "0,*")
11210 (set_attr "length_immediate" "0,*")
11211 (set_attr "modrm" "0,1")
11212 (set_attr "mode" "DI")])
11214 (define_insn "*ashrdi3_1_one_bit_rex64"
11215 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11216 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11217 (match_operand:QI 2 "const_int_1_operand" "")))
11218 (clobber (reg:CC 17))]
11219 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11220 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11222 [(set_attr "type" "ishift")
11223 (set (attr "length")
11224 (if_then_else (match_operand:DI 0 "register_operand" "")
11226 (const_string "*")))])
11228 (define_insn "*ashrdi3_1_rex64"
11229 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11230 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11231 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11232 (clobber (reg:CC 17))]
11233 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11235 sar{q}\\t{%2, %0|%0, %2}
11236 sar{q}\\t{%b2, %0|%0, %b2}"
11237 [(set_attr "type" "ishift")
11238 (set_attr "mode" "DI")])
11240 ;; This pattern can't accept a variable shift count, since shifts by
11241 ;; zero don't affect the flags. We assume that shifts by constant
11242 ;; zero are optimized away.
11243 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11246 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11247 (match_operand:QI 2 "const_int_1_operand" ""))
11249 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11250 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11251 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11252 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11253 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11255 [(set_attr "type" "ishift")
11256 (set (attr "length")
11257 (if_then_else (match_operand:DI 0 "register_operand" "")
11259 (const_string "*")))])
11261 ;; This pattern can't accept a variable shift count, since shifts by
11262 ;; zero don't affect the flags. We assume that shifts by constant
11263 ;; zero are optimized away.
11264 (define_insn "*ashrdi3_cmp_rex64"
11267 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11268 (match_operand:QI 2 "const_int_operand" "n"))
11270 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11271 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11272 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11273 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11274 "sar{q}\\t{%2, %0|%0, %2}"
11275 [(set_attr "type" "ishift")
11276 (set_attr "mode" "DI")])
11279 (define_insn "ashrdi3_1"
11280 [(set (match_operand:DI 0 "register_operand" "=r")
11281 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11282 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11283 (clobber (match_scratch:SI 3 "=&r"))
11284 (clobber (reg:CC 17))]
11285 "!TARGET_64BIT && TARGET_CMOVE"
11287 [(set_attr "type" "multi")])
11289 (define_insn "*ashrdi3_2"
11290 [(set (match_operand:DI 0 "register_operand" "=r")
11291 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11292 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11293 (clobber (reg:CC 17))]
11296 [(set_attr "type" "multi")])
11299 [(set (match_operand:DI 0 "register_operand" "")
11300 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11301 (match_operand:QI 2 "nonmemory_operand" "")))
11302 (clobber (match_scratch:SI 3 ""))
11303 (clobber (reg:CC 17))]
11304 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11306 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11309 [(set (match_operand:DI 0 "register_operand" "")
11310 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11311 (match_operand:QI 2 "nonmemory_operand" "")))
11312 (clobber (reg:CC 17))]
11313 "!TARGET_64BIT && reload_completed"
11315 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11317 (define_insn "x86_shrd_1"
11318 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11319 (ior:SI (ashiftrt:SI (match_dup 0)
11320 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11321 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11322 (minus:QI (const_int 32) (match_dup 2)))))
11323 (clobber (reg:CC 17))]
11326 shrd{l}\\t{%2, %1, %0|%0, %1, %2}
11327 shrd{l}\\t{%s2%1, %0|%0, %1, %2}"
11328 [(set_attr "type" "ishift")
11329 (set_attr "prefix_0f" "1")
11330 (set_attr "pent_pair" "np")
11331 (set_attr "ppro_uops" "few")
11332 (set_attr "mode" "SI")])
11334 (define_expand "x86_shift_adj_3"
11335 [(use (match_operand:SI 0 "register_operand" ""))
11336 (use (match_operand:SI 1 "register_operand" ""))
11337 (use (match_operand:QI 2 "register_operand" ""))]
11341 rtx label = gen_label_rtx ();
11344 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11346 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11347 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11348 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11349 gen_rtx_LABEL_REF (VOIDmode, label),
11351 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11352 JUMP_LABEL (tmp) = label;
11354 emit_move_insn (operands[0], operands[1]);
11355 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11357 emit_label (label);
11358 LABEL_NUSES (label) = 1;
11363 (define_insn "ashrsi3_31"
11364 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11365 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11366 (match_operand:SI 2 "const_int_operand" "i,i")))
11367 (clobber (reg:CC 17))]
11368 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11369 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11372 sar{l}\\t{%2, %0|%0, %2}"
11373 [(set_attr "type" "imovx,ishift")
11374 (set_attr "prefix_0f" "0,*")
11375 (set_attr "length_immediate" "0,*")
11376 (set_attr "modrm" "0,1")
11377 (set_attr "mode" "SI")])
11379 (define_insn "*ashrsi3_31_zext"
11380 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11381 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11382 (match_operand:SI 2 "const_int_operand" "i,i"))))
11383 (clobber (reg:CC 17))]
11384 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11385 && TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11388 sar{l}\\t{%2, %k0|%k0, %2}"
11389 [(set_attr "type" "imovx,ishift")
11390 (set_attr "prefix_0f" "0,*")
11391 (set_attr "length_immediate" "0,*")
11392 (set_attr "modrm" "0,1")
11393 (set_attr "mode" "SI")])
11395 (define_expand "ashrsi3"
11396 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11397 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11398 (match_operand:QI 2 "nonmemory_operand" "")))
11399 (clobber (reg:CC 17))]
11401 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11403 (define_insn "*ashrsi3_1_one_bit"
11404 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11405 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11406 (match_operand:QI 2 "const_int_1_operand" "")))
11407 (clobber (reg:CC 17))]
11408 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11409 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11411 [(set_attr "type" "ishift")
11412 (set (attr "length")
11413 (if_then_else (match_operand:SI 0 "register_operand" "")
11415 (const_string "*")))])
11417 (define_insn "*ashrsi3_1_one_bit_zext"
11418 [(set (match_operand:DI 0 "register_operand" "=r")
11419 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11420 (match_operand:QI 2 "const_int_1_operand" ""))))
11421 (clobber (reg:CC 17))]
11422 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11423 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11425 [(set_attr "type" "ishift")
11426 (set_attr "length" "2")])
11428 (define_insn "*ashrsi3_1"
11429 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11430 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11431 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11432 (clobber (reg:CC 17))]
11433 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11435 sar{l}\\t{%2, %0|%0, %2}
11436 sar{l}\\t{%b2, %0|%0, %b2}"
11437 [(set_attr "type" "ishift")
11438 (set_attr "mode" "SI")])
11440 (define_insn "*ashrsi3_1_zext"
11441 [(set (match_operand:DI 0 "register_operand" "=r,r")
11442 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11443 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11444 (clobber (reg:CC 17))]
11445 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11447 sar{l}\\t{%2, %k0|%k0, %2}
11448 sar{l}\\t{%b2, %k0|%k0, %b2}"
11449 [(set_attr "type" "ishift")
11450 (set_attr "mode" "SI")])
11452 ;; This pattern can't accept a variable shift count, since shifts by
11453 ;; zero don't affect the flags. We assume that shifts by constant
11454 ;; zero are optimized away.
11455 (define_insn "*ashrsi3_one_bit_cmp"
11458 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11459 (match_operand:QI 2 "const_int_1_operand" ""))
11461 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11462 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11463 "ix86_match_ccmode (insn, CCGOCmode)
11464 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11465 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11467 [(set_attr "type" "ishift")
11468 (set (attr "length")
11469 (if_then_else (match_operand:SI 0 "register_operand" "")
11471 (const_string "*")))])
11473 (define_insn "*ashrsi3_one_bit_cmp_zext"
11476 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11477 (match_operand:QI 2 "const_int_1_operand" ""))
11479 (set (match_operand:DI 0 "register_operand" "=r")
11480 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11481 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11482 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11483 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11485 [(set_attr "type" "ishift")
11486 (set_attr "length" "2")])
11488 ;; This pattern can't accept a variable shift count, since shifts by
11489 ;; zero don't affect the flags. We assume that shifts by constant
11490 ;; zero are optimized away.
11491 (define_insn "*ashrsi3_cmp"
11494 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11495 (match_operand:QI 2 "immediate_operand" "I"))
11497 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11498 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11499 "ix86_match_ccmode (insn, CCGOCmode)
11500 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11501 "sar{l}\\t{%2, %0|%0, %2}"
11502 [(set_attr "type" "ishift")
11503 (set_attr "mode" "SI")])
11505 (define_insn "*ashrsi3_cmp_zext"
11508 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11509 (match_operand:QI 2 "immediate_operand" "I"))
11511 (set (match_operand:DI 0 "register_operand" "=r")
11512 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11513 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11514 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11515 "sar{l}\\t{%2, %k0|%k0, %2}"
11516 [(set_attr "type" "ishift")
11517 (set_attr "mode" "SI")])
11519 (define_expand "ashrhi3"
11520 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11521 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11522 (match_operand:QI 2 "nonmemory_operand" "")))
11523 (clobber (reg:CC 17))]
11524 "TARGET_HIMODE_MATH"
11525 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11527 (define_insn "*ashrhi3_1_one_bit"
11528 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11529 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11530 (match_operand:QI 2 "const_int_1_operand" "")))
11531 (clobber (reg:CC 17))]
11532 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11533 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11535 [(set_attr "type" "ishift")
11536 (set (attr "length")
11537 (if_then_else (match_operand 0 "register_operand" "")
11539 (const_string "*")))])
11541 (define_insn "*ashrhi3_1"
11542 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11543 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11544 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11545 (clobber (reg:CC 17))]
11546 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11548 sar{w}\\t{%2, %0|%0, %2}
11549 sar{w}\\t{%b2, %0|%0, %b2}"
11550 [(set_attr "type" "ishift")
11551 (set_attr "mode" "HI")])
11553 ;; This pattern can't accept a variable shift count, since shifts by
11554 ;; zero don't affect the flags. We assume that shifts by constant
11555 ;; zero are optimized away.
11556 (define_insn "*ashrhi3_one_bit_cmp"
11559 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11560 (match_operand:QI 2 "const_int_1_operand" ""))
11562 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11563 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11564 "ix86_match_ccmode (insn, CCGOCmode)
11565 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11566 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11568 [(set_attr "type" "ishift")
11569 (set (attr "length")
11570 (if_then_else (match_operand 0 "register_operand" "")
11572 (const_string "*")))])
11574 ;; This pattern can't accept a variable shift count, since shifts by
11575 ;; zero don't affect the flags. We assume that shifts by constant
11576 ;; zero are optimized away.
11577 (define_insn "*ashrhi3_cmp"
11580 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11581 (match_operand:QI 2 "immediate_operand" "I"))
11583 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11584 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11585 "ix86_match_ccmode (insn, CCGOCmode)
11586 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11587 "sar{w}\\t{%2, %0|%0, %2}"
11588 [(set_attr "type" "ishift")
11589 (set_attr "mode" "HI")])
11591 (define_expand "ashrqi3"
11592 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11593 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11594 (match_operand:QI 2 "nonmemory_operand" "")))
11595 (clobber (reg:CC 17))]
11596 "TARGET_QIMODE_MATH"
11597 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11599 (define_insn "*ashrqi3_1_one_bit"
11600 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11601 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11602 (match_operand:QI 2 "const_int_1_operand" "")))
11603 (clobber (reg:CC 17))]
11604 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11605 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11607 [(set_attr "type" "ishift")
11608 (set (attr "length")
11609 (if_then_else (match_operand 0 "register_operand" "")
11611 (const_string "*")))])
11613 (define_insn "*ashrqi3_1"
11614 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11615 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11616 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11617 (clobber (reg:CC 17))]
11618 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11620 sar{b}\\t{%2, %0|%0, %2}
11621 sar{b}\\t{%b2, %0|%0, %b2}"
11622 [(set_attr "type" "ishift")
11623 (set_attr "mode" "QI")])
11625 ;; This pattern can't accept a variable shift count, since shifts by
11626 ;; zero don't affect the flags. We assume that shifts by constant
11627 ;; zero are optimized away.
11628 (define_insn "*ashrqi3_one_bit_cmp"
11631 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11632 (match_operand:QI 2 "const_int_1_operand" "I"))
11634 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11635 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11636 "ix86_match_ccmode (insn, CCGOCmode)
11637 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11638 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11640 [(set_attr "type" "ishift")
11641 (set (attr "length")
11642 (if_then_else (match_operand 0 "register_operand" "")
11644 (const_string "*")))])
11646 ;; This pattern can't accept a variable shift count, since shifts by
11647 ;; zero don't affect the flags. We assume that shifts by constant
11648 ;; zero are optimized away.
11649 (define_insn "*ashrqi3_cmp"
11652 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11653 (match_operand:QI 2 "immediate_operand" "I"))
11655 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11656 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11657 "ix86_match_ccmode (insn, CCGOCmode)
11658 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11659 "sar{b}\\t{%2, %0|%0, %2}"
11660 [(set_attr "type" "ishift")
11661 (set_attr "mode" "QI")])
11663 ;; Logical shift instructions
11665 ;; See comment above `ashldi3' about how this works.
11667 (define_expand "lshrdi3"
11668 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11669 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11670 (match_operand:QI 2 "nonmemory_operand" "")))
11671 (clobber (reg:CC 17))])]
11675 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11677 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11680 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11684 (define_insn "*lshrdi3_1_one_bit_rex64"
11685 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11686 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11687 (match_operand:QI 2 "const_int_1_operand" "")))
11688 (clobber (reg:CC 17))]
11689 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11690 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11692 [(set_attr "type" "ishift")
11693 (set (attr "length")
11694 (if_then_else (match_operand:DI 0 "register_operand" "")
11696 (const_string "*")))])
11698 (define_insn "*lshrdi3_1_rex64"
11699 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11700 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11701 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11702 (clobber (reg:CC 17))]
11703 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11705 shr{q}\\t{%2, %0|%0, %2}
11706 shr{q}\\t{%b2, %0|%0, %b2}"
11707 [(set_attr "type" "ishift")
11708 (set_attr "mode" "DI")])
11710 ;; This pattern can't accept a variable shift count, since shifts by
11711 ;; zero don't affect the flags. We assume that shifts by constant
11712 ;; zero are optimized away.
11713 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11716 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11717 (match_operand:QI 2 "const_int_1_operand" ""))
11719 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11720 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11721 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11722 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11723 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11725 [(set_attr "type" "ishift")
11726 (set (attr "length")
11727 (if_then_else (match_operand:DI 0 "register_operand" "")
11729 (const_string "*")))])
11731 ;; This pattern can't accept a variable shift count, since shifts by
11732 ;; zero don't affect the flags. We assume that shifts by constant
11733 ;; zero are optimized away.
11734 (define_insn "*lshrdi3_cmp_rex64"
11737 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11738 (match_operand:QI 2 "const_int_operand" "e"))
11740 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11741 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11742 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11743 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11744 "shr{q}\\t{%2, %0|%0, %2}"
11745 [(set_attr "type" "ishift")
11746 (set_attr "mode" "DI")])
11748 (define_insn "lshrdi3_1"
11749 [(set (match_operand:DI 0 "register_operand" "=r")
11750 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11751 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11752 (clobber (match_scratch:SI 3 "=&r"))
11753 (clobber (reg:CC 17))]
11754 "!TARGET_64BIT && TARGET_CMOVE"
11756 [(set_attr "type" "multi")])
11758 (define_insn "*lshrdi3_2"
11759 [(set (match_operand:DI 0 "register_operand" "=r")
11760 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11761 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11762 (clobber (reg:CC 17))]
11765 [(set_attr "type" "multi")])
11768 [(set (match_operand:DI 0 "register_operand" "")
11769 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11770 (match_operand:QI 2 "nonmemory_operand" "")))
11771 (clobber (match_scratch:SI 3 ""))
11772 (clobber (reg:CC 17))]
11773 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11775 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11778 [(set (match_operand:DI 0 "register_operand" "")
11779 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11780 (match_operand:QI 2 "nonmemory_operand" "")))
11781 (clobber (reg:CC 17))]
11782 "!TARGET_64BIT && reload_completed"
11784 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11786 (define_expand "lshrsi3"
11787 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11788 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11789 (match_operand:QI 2 "nonmemory_operand" "")))
11790 (clobber (reg:CC 17))]
11792 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11794 (define_insn "*lshrsi3_1_one_bit"
11795 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11796 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11797 (match_operand:QI 2 "const_int_1_operand" "")))
11798 (clobber (reg:CC 17))]
11799 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11800 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11802 [(set_attr "type" "ishift")
11803 (set (attr "length")
11804 (if_then_else (match_operand:SI 0 "register_operand" "")
11806 (const_string "*")))])
11808 (define_insn "*lshrsi3_1_one_bit_zext"
11809 [(set (match_operand:DI 0 "register_operand" "=r")
11810 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11811 (match_operand:QI 2 "const_int_1_operand" "")))
11812 (clobber (reg:CC 17))]
11813 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11814 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11816 [(set_attr "type" "ishift")
11817 (set_attr "length" "2")])
11819 (define_insn "*lshrsi3_1"
11820 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11821 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11822 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11823 (clobber (reg:CC 17))]
11824 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11826 shr{l}\\t{%2, %0|%0, %2}
11827 shr{l}\\t{%b2, %0|%0, %b2}"
11828 [(set_attr "type" "ishift")
11829 (set_attr "mode" "SI")])
11831 (define_insn "*lshrsi3_1_zext"
11832 [(set (match_operand:DI 0 "register_operand" "=r,r")
11834 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11835 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11836 (clobber (reg:CC 17))]
11837 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11839 shr{l}\\t{%2, %k0|%k0, %2}
11840 shr{l}\\t{%b2, %k0|%k0, %b2}"
11841 [(set_attr "type" "ishift")
11842 (set_attr "mode" "SI")])
11844 ;; This pattern can't accept a variable shift count, since shifts by
11845 ;; zero don't affect the flags. We assume that shifts by constant
11846 ;; zero are optimized away.
11847 (define_insn "*lshrsi3_one_bit_cmp"
11850 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11851 (match_operand:QI 2 "const_int_1_operand" ""))
11853 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11854 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11855 "ix86_match_ccmode (insn, CCGOCmode)
11856 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11857 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11859 [(set_attr "type" "ishift")
11860 (set (attr "length")
11861 (if_then_else (match_operand:SI 0 "register_operand" "")
11863 (const_string "*")))])
11865 (define_insn "*lshrsi3_cmp_one_bit_zext"
11868 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11869 (match_operand:QI 2 "const_int_1_operand" ""))
11871 (set (match_operand:DI 0 "register_operand" "=r")
11872 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11873 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11874 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11875 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11877 [(set_attr "type" "ishift")
11878 (set_attr "length" "2")])
11880 ;; This pattern can't accept a variable shift count, since shifts by
11881 ;; zero don't affect the flags. We assume that shifts by constant
11882 ;; zero are optimized away.
11883 (define_insn "*lshrsi3_cmp"
11886 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11887 (match_operand:QI 2 "immediate_operand" "I"))
11889 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11890 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11891 "ix86_match_ccmode (insn, CCGOCmode)
11892 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11893 "shr{l}\\t{%2, %0|%0, %2}"
11894 [(set_attr "type" "ishift")
11895 (set_attr "mode" "SI")])
11897 (define_insn "*lshrsi3_cmp_zext"
11900 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11901 (match_operand:QI 2 "immediate_operand" "I"))
11903 (set (match_operand:DI 0 "register_operand" "=r")
11904 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11905 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11906 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11907 "shr{l}\\t{%2, %k0|%k0, %2}"
11908 [(set_attr "type" "ishift")
11909 (set_attr "mode" "SI")])
11911 (define_expand "lshrhi3"
11912 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11913 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11914 (match_operand:QI 2 "nonmemory_operand" "")))
11915 (clobber (reg:CC 17))]
11916 "TARGET_HIMODE_MATH"
11917 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11919 (define_insn "*lshrhi3_1_one_bit"
11920 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11921 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11922 (match_operand:QI 2 "const_int_1_operand" "")))
11923 (clobber (reg:CC 17))]
11924 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11925 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11927 [(set_attr "type" "ishift")
11928 (set (attr "length")
11929 (if_then_else (match_operand 0 "register_operand" "")
11931 (const_string "*")))])
11933 (define_insn "*lshrhi3_1"
11934 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11935 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11936 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11937 (clobber (reg:CC 17))]
11938 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11940 shr{w}\\t{%2, %0|%0, %2}
11941 shr{w}\\t{%b2, %0|%0, %b2}"
11942 [(set_attr "type" "ishift")
11943 (set_attr "mode" "HI")])
11945 ;; This pattern can't accept a variable shift count, since shifts by
11946 ;; zero don't affect the flags. We assume that shifts by constant
11947 ;; zero are optimized away.
11948 (define_insn "*lshrhi3_one_bit_cmp"
11951 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11952 (match_operand:QI 2 "const_int_1_operand" ""))
11954 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11955 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11956 "ix86_match_ccmode (insn, CCGOCmode)
11957 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11958 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11960 [(set_attr "type" "ishift")
11961 (set (attr "length")
11962 (if_then_else (match_operand:SI 0 "register_operand" "")
11964 (const_string "*")))])
11966 ;; This pattern can't accept a variable shift count, since shifts by
11967 ;; zero don't affect the flags. We assume that shifts by constant
11968 ;; zero are optimized away.
11969 (define_insn "*lshrhi3_cmp"
11972 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11973 (match_operand:QI 2 "immediate_operand" "I"))
11975 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11976 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11977 "ix86_match_ccmode (insn, CCGOCmode)
11978 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11979 "shr{w}\\t{%2, %0|%0, %2}"
11980 [(set_attr "type" "ishift")
11981 (set_attr "mode" "HI")])
11983 (define_expand "lshrqi3"
11984 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11985 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11986 (match_operand:QI 2 "nonmemory_operand" "")))
11987 (clobber (reg:CC 17))]
11988 "TARGET_QIMODE_MATH"
11989 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11991 (define_insn "*lshrqi3_1_one_bit"
11992 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11993 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11994 (match_operand:QI 2 "const_int_1_operand" "")))
11995 (clobber (reg:CC 17))]
11996 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11997 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11999 [(set_attr "type" "ishift")
12000 (set (attr "length")
12001 (if_then_else (match_operand 0 "register_operand" "")
12003 (const_string "*")))])
12005 (define_insn "*lshrqi3_1"
12006 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12007 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12008 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12009 (clobber (reg:CC 17))]
12010 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12012 shr{b}\\t{%2, %0|%0, %2}
12013 shr{b}\\t{%b2, %0|%0, %b2}"
12014 [(set_attr "type" "ishift")
12015 (set_attr "mode" "QI")])
12017 ;; This pattern can't accept a variable shift count, since shifts by
12018 ;; zero don't affect the flags. We assume that shifts by constant
12019 ;; zero are optimized away.
12020 (define_insn "*lshrqi2_one_bit_cmp"
12023 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12024 (match_operand:QI 2 "const_int_1_operand" ""))
12026 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12027 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12028 "ix86_match_ccmode (insn, CCGOCmode)
12029 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
12030 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12032 [(set_attr "type" "ishift")
12033 (set (attr "length")
12034 (if_then_else (match_operand:SI 0 "register_operand" "")
12036 (const_string "*")))])
12038 ;; This pattern can't accept a variable shift count, since shifts by
12039 ;; zero don't affect the flags. We assume that shifts by constant
12040 ;; zero are optimized away.
12041 (define_insn "*lshrqi2_cmp"
12044 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12045 (match_operand:QI 2 "immediate_operand" "I"))
12047 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12048 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12049 "ix86_match_ccmode (insn, CCGOCmode)
12050 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12051 "shr{b}\\t{%2, %0|%0, %2}"
12052 [(set_attr "type" "ishift")
12053 (set_attr "mode" "QI")])
12055 ;; Rotate instructions
12057 (define_expand "rotldi3"
12058 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12059 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12060 (match_operand:QI 2 "nonmemory_operand" "")))
12061 (clobber (reg:CC 17))]
12063 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12065 (define_insn "*rotlsi3_1_one_bit_rex64"
12066 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12067 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12068 (match_operand:QI 2 "const_int_1_operand" "")))
12069 (clobber (reg:CC 17))]
12070 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12071 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12073 [(set_attr "type" "ishift")
12074 (set (attr "length")
12075 (if_then_else (match_operand:DI 0 "register_operand" "")
12077 (const_string "*")))])
12079 (define_insn "*rotldi3_1_rex64"
12080 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12081 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12082 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12083 (clobber (reg:CC 17))]
12084 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12086 rol{q}\\t{%2, %0|%0, %2}
12087 rol{q}\\t{%b2, %0|%0, %b2}"
12088 [(set_attr "type" "ishift")
12089 (set_attr "mode" "DI")])
12091 (define_expand "rotlsi3"
12092 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12093 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12094 (match_operand:QI 2 "nonmemory_operand" "")))
12095 (clobber (reg:CC 17))]
12097 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12099 (define_insn "*rotlsi3_1_one_bit"
12100 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12101 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12102 (match_operand:QI 2 "const_int_1_operand" "")))
12103 (clobber (reg:CC 17))]
12104 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12105 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12107 [(set_attr "type" "ishift")
12108 (set (attr "length")
12109 (if_then_else (match_operand:SI 0 "register_operand" "")
12111 (const_string "*")))])
12113 (define_insn "*rotlsi3_1_one_bit_zext"
12114 [(set (match_operand:DI 0 "register_operand" "=r")
12116 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12117 (match_operand:QI 2 "const_int_1_operand" ""))))
12118 (clobber (reg:CC 17))]
12119 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12120 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12122 [(set_attr "type" "ishift")
12123 (set_attr "length" "2")])
12125 (define_insn "*rotlsi3_1"
12126 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12127 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12128 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12129 (clobber (reg:CC 17))]
12130 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12132 rol{l}\\t{%2, %0|%0, %2}
12133 rol{l}\\t{%b2, %0|%0, %b2}"
12134 [(set_attr "type" "ishift")
12135 (set_attr "mode" "SI")])
12137 (define_insn "*rotlsi3_1_zext"
12138 [(set (match_operand:DI 0 "register_operand" "=r,r")
12140 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12141 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12142 (clobber (reg:CC 17))]
12143 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12145 rol{l}\\t{%2, %k0|%k0, %2}
12146 rol{l}\\t{%b2, %k0|%k0, %b2}"
12147 [(set_attr "type" "ishift")
12148 (set_attr "mode" "SI")])
12150 (define_expand "rotlhi3"
12151 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12152 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12153 (match_operand:QI 2 "nonmemory_operand" "")))
12154 (clobber (reg:CC 17))]
12155 "TARGET_HIMODE_MATH"
12156 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12158 (define_insn "*rotlhi3_1_one_bit"
12159 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12160 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12161 (match_operand:QI 2 "const_int_1_operand" "")))
12162 (clobber (reg:CC 17))]
12163 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12164 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12166 [(set_attr "type" "ishift")
12167 (set (attr "length")
12168 (if_then_else (match_operand 0 "register_operand" "")
12170 (const_string "*")))])
12172 (define_insn "*rotlhi3_1"
12173 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12174 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12175 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12176 (clobber (reg:CC 17))]
12177 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12179 rol{w}\\t{%2, %0|%0, %2}
12180 rol{w}\\t{%b2, %0|%0, %b2}"
12181 [(set_attr "type" "ishift")
12182 (set_attr "mode" "HI")])
12184 (define_expand "rotlqi3"
12185 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12186 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12187 (match_operand:QI 2 "nonmemory_operand" "")))
12188 (clobber (reg:CC 17))]
12189 "TARGET_QIMODE_MATH"
12190 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12192 (define_insn "*rotlqi3_1_one_bit"
12193 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12194 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12195 (match_operand:QI 2 "const_int_1_operand" "")))
12196 (clobber (reg:CC 17))]
12197 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12198 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12200 [(set_attr "type" "ishift")
12201 (set (attr "length")
12202 (if_then_else (match_operand 0 "register_operand" "")
12204 (const_string "*")))])
12206 (define_insn "*rotlqi3_1"
12207 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12208 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12209 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12210 (clobber (reg:CC 17))]
12211 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12213 rol{b}\\t{%2, %0|%0, %2}
12214 rol{b}\\t{%b2, %0|%0, %b2}"
12215 [(set_attr "type" "ishift")
12216 (set_attr "mode" "QI")])
12218 (define_expand "rotrdi3"
12219 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12220 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12221 (match_operand:QI 2 "nonmemory_operand" "")))
12222 (clobber (reg:CC 17))]
12224 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12226 (define_insn "*rotrdi3_1_one_bit_rex64"
12227 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12228 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12229 (match_operand:QI 2 "const_int_1_operand" "")))
12230 (clobber (reg:CC 17))]
12231 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12232 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12234 [(set_attr "type" "ishift")
12235 (set (attr "length")
12236 (if_then_else (match_operand:DI 0 "register_operand" "")
12238 (const_string "*")))])
12240 (define_insn "*rotrdi3_1_rex64"
12241 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12242 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12243 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12244 (clobber (reg:CC 17))]
12245 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12247 ror{q}\\t{%2, %0|%0, %2}
12248 ror{q}\\t{%b2, %0|%0, %b2}"
12249 [(set_attr "type" "ishift")
12250 (set_attr "mode" "DI")])
12252 (define_expand "rotrsi3"
12253 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12254 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12255 (match_operand:QI 2 "nonmemory_operand" "")))
12256 (clobber (reg:CC 17))]
12258 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12260 (define_insn "*rotrsi3_1_one_bit"
12261 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12262 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12263 (match_operand:QI 2 "const_int_1_operand" "")))
12264 (clobber (reg:CC 17))]
12265 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12266 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12268 [(set_attr "type" "ishift")
12269 (set (attr "length")
12270 (if_then_else (match_operand:SI 0 "register_operand" "")
12272 (const_string "*")))])
12274 (define_insn "*rotrsi3_1_one_bit_zext"
12275 [(set (match_operand:DI 0 "register_operand" "=r")
12277 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12278 (match_operand:QI 2 "const_int_1_operand" ""))))
12279 (clobber (reg:CC 17))]
12280 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12281 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12283 [(set_attr "type" "ishift")
12284 (set (attr "length")
12285 (if_then_else (match_operand:SI 0 "register_operand" "")
12287 (const_string "*")))])
12289 (define_insn "*rotrsi3_1"
12290 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12291 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12292 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12293 (clobber (reg:CC 17))]
12294 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12296 ror{l}\\t{%2, %0|%0, %2}
12297 ror{l}\\t{%b2, %0|%0, %b2}"
12298 [(set_attr "type" "ishift")
12299 (set_attr "mode" "SI")])
12301 (define_insn "*rotrsi3_1_zext"
12302 [(set (match_operand:DI 0 "register_operand" "=r,r")
12304 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12305 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12306 (clobber (reg:CC 17))]
12307 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12309 ror{l}\\t{%2, %k0|%k0, %2}
12310 ror{l}\\t{%b2, %k0|%k0, %b2}"
12311 [(set_attr "type" "ishift")
12312 (set_attr "mode" "SI")])
12314 (define_expand "rotrhi3"
12315 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12316 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12317 (match_operand:QI 2 "nonmemory_operand" "")))
12318 (clobber (reg:CC 17))]
12319 "TARGET_HIMODE_MATH"
12320 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12322 (define_insn "*rotrhi3_one_bit"
12323 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12324 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12325 (match_operand:QI 2 "const_int_1_operand" "")))
12326 (clobber (reg:CC 17))]
12327 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12328 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12330 [(set_attr "type" "ishift")
12331 (set (attr "length")
12332 (if_then_else (match_operand 0 "register_operand" "")
12334 (const_string "*")))])
12336 (define_insn "*rotrhi3"
12337 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12338 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12339 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12340 (clobber (reg:CC 17))]
12341 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12343 ror{w}\\t{%2, %0|%0, %2}
12344 ror{w}\\t{%b2, %0|%0, %b2}"
12345 [(set_attr "type" "ishift")
12346 (set_attr "mode" "HI")])
12348 (define_expand "rotrqi3"
12349 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12350 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12351 (match_operand:QI 2 "nonmemory_operand" "")))
12352 (clobber (reg:CC 17))]
12353 "TARGET_QIMODE_MATH"
12354 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12356 (define_insn "*rotrqi3_1_one_bit"
12357 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12358 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12359 (match_operand:QI 2 "const_int_1_operand" "")))
12360 (clobber (reg:CC 17))]
12361 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12362 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
12364 [(set_attr "type" "ishift")
12365 (set (attr "length")
12366 (if_then_else (match_operand 0 "register_operand" "")
12368 (const_string "*")))])
12370 (define_insn "*rotrqi3_1"
12371 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12372 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12373 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12374 (clobber (reg:CC 17))]
12375 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12377 ror{b}\\t{%2, %0|%0, %2}
12378 ror{b}\\t{%b2, %0|%0, %b2}"
12379 [(set_attr "type" "ishift")
12380 (set_attr "mode" "QI")])
12382 ;; Bit set / bit test instructions
12384 (define_expand "extv"
12385 [(set (match_operand:SI 0 "register_operand" "")
12386 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12387 (match_operand:SI 2 "immediate_operand" "")
12388 (match_operand:SI 3 "immediate_operand" "")))]
12392 /* Handle extractions from %ah et al. */
12393 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12396 /* From mips.md: extract_bit_field doesn't verify that our source
12397 matches the predicate, so check it again here. */
12398 if (! register_operand (operands[1], VOIDmode))
12402 (define_expand "extzv"
12403 [(set (match_operand:SI 0 "register_operand" "")
12404 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12405 (match_operand:SI 2 "immediate_operand" "")
12406 (match_operand:SI 3 "immediate_operand" "")))]
12410 /* Handle extractions from %ah et al. */
12411 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12414 /* From mips.md: extract_bit_field doesn't verify that our source
12415 matches the predicate, so check it again here. */
12416 if (! register_operand (operands[1], VOIDmode))
12420 (define_expand "insv"
12421 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12422 (match_operand:SI 1 "immediate_operand" "")
12423 (match_operand:SI 2 "immediate_operand" ""))
12424 (match_operand:SI 3 "register_operand" ""))]
12428 /* Handle extractions from %ah et al. */
12429 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12432 /* From mips.md: insert_bit_field doesn't verify that our source
12433 matches the predicate, so check it again here. */
12434 if (! register_operand (operands[0], VOIDmode))
12438 ;; %%% bts, btr, btc, bt.
12440 ;; Store-flag instructions.
12442 ;; For all sCOND expanders, also expand the compare or test insn that
12443 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12445 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12446 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12447 ;; way, which can later delete the movzx if only QImode is needed.
12449 (define_expand "seq"
12450 [(set (match_operand:SI 0 "register_operand" "")
12451 (eq:SI (reg:CC 17) (const_int 0)))]
12453 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12455 (define_expand "sne"
12456 [(set (match_operand:SI 0 "register_operand" "")
12457 (ne:SI (reg:CC 17) (const_int 0)))]
12459 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12461 (define_expand "sgt"
12462 [(set (match_operand:SI 0 "register_operand" "")
12463 (gt:SI (reg:CC 17) (const_int 0)))]
12465 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12467 (define_expand "sgtu"
12468 [(set (match_operand:SI 0 "register_operand" "")
12469 (gtu:SI (reg:CC 17) (const_int 0)))]
12471 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12473 (define_expand "slt"
12474 [(set (match_operand:SI 0 "register_operand" "")
12475 (lt:SI (reg:CC 17) (const_int 0)))]
12477 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12479 (define_expand "sltu"
12480 [(set (match_operand:SI 0 "register_operand" "")
12481 (ltu:SI (reg:CC 17) (const_int 0)))]
12483 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12485 (define_expand "sge"
12486 [(set (match_operand:SI 0 "register_operand" "")
12487 (ge:SI (reg:CC 17) (const_int 0)))]
12489 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12491 (define_expand "sgeu"
12492 [(set (match_operand:SI 0 "register_operand" "")
12493 (geu:SI (reg:CC 17) (const_int 0)))]
12495 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12497 (define_expand "sle"
12498 [(set (match_operand:SI 0 "register_operand" "")
12499 (le:SI (reg:CC 17) (const_int 0)))]
12501 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12503 (define_expand "sleu"
12504 [(set (match_operand:SI 0 "register_operand" "")
12505 (leu:SI (reg:CC 17) (const_int 0)))]
12507 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12509 (define_expand "sunordered"
12510 [(set (match_operand:SI 0 "register_operand" "")
12511 (unordered:SI (reg:CC 17) (const_int 0)))]
12512 "TARGET_80387 || TARGET_SSE"
12513 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12515 (define_expand "sordered"
12516 [(set (match_operand:SI 0 "register_operand" "")
12517 (ordered:SI (reg:CC 17) (const_int 0)))]
12519 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12521 (define_expand "suneq"
12522 [(set (match_operand:SI 0 "register_operand" "")
12523 (uneq:SI (reg:CC 17) (const_int 0)))]
12524 "TARGET_80387 || TARGET_SSE"
12525 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12527 (define_expand "sunge"
12528 [(set (match_operand:SI 0 "register_operand" "")
12529 (unge:SI (reg:CC 17) (const_int 0)))]
12530 "TARGET_80387 || TARGET_SSE"
12531 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12533 (define_expand "sungt"
12534 [(set (match_operand:SI 0 "register_operand" "")
12535 (ungt:SI (reg:CC 17) (const_int 0)))]
12536 "TARGET_80387 || TARGET_SSE"
12537 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12539 (define_expand "sunle"
12540 [(set (match_operand:SI 0 "register_operand" "")
12541 (unle:SI (reg:CC 17) (const_int 0)))]
12542 "TARGET_80387 || TARGET_SSE"
12543 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12545 (define_expand "sunlt"
12546 [(set (match_operand:SI 0 "register_operand" "")
12547 (unlt:SI (reg:CC 17) (const_int 0)))]
12548 "TARGET_80387 || TARGET_SSE"
12549 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12551 (define_expand "sltgt"
12552 [(set (match_operand:SI 0 "register_operand" "")
12553 (ltgt:SI (reg:CC 17) (const_int 0)))]
12554 "TARGET_80387 || TARGET_SSE"
12555 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12557 (define_insn "*setcc_1"
12558 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12559 (match_operator:QI 1 "ix86_comparison_operator"
12560 [(reg 17) (const_int 0)]))]
12563 [(set_attr "type" "setcc")
12564 (set_attr "mode" "QI")])
12566 (define_insn "setcc_2"
12567 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12568 (match_operator:QI 1 "ix86_comparison_operator"
12569 [(reg 17) (const_int 0)]))]
12572 [(set_attr "type" "setcc")
12573 (set_attr "mode" "QI")])
12575 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12576 ;; subsequent logical operations are used to imitate conditional moves.
12577 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12578 ;; it directly. Futher holding this value in pseudo register might bring
12579 ;; problem in implicit normalization in spill code.
12580 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12581 ;; instructions after reload by splitting the conditional move patterns.
12583 (define_insn "*sse_setccsf"
12584 [(set (match_operand:SF 0 "register_operand" "=x")
12585 (match_operator:SF 1 "sse_comparison_operator"
12586 [(match_operand:SF 2 "register_operand" "0")
12587 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12588 "TARGET_SSE && reload_completed"
12589 "cmp%D1ss\\t{%3, %0|%0, %3}"
12590 [(set_attr "type" "sse")
12591 (set_attr "mode" "SF")])
12593 (define_insn "*sse_setccdf"
12594 [(set (match_operand:DF 0 "register_operand" "=Y")
12595 (match_operator:DF 1 "sse_comparison_operator"
12596 [(match_operand:DF 2 "register_operand" "0")
12597 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12598 "TARGET_SSE2 && reload_completed"
12599 "cmp%D1sd\\t{%3, %0|%0, %3}"
12600 [(set_attr "type" "sse")
12601 (set_attr "mode" "DF")])
12603 ;; Basic conditional jump instructions.
12604 ;; We ignore the overflow flag for signed branch instructions.
12606 ;; For all bCOND expanders, also expand the compare or test insn that
12607 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12609 (define_expand "beq"
12611 (if_then_else (match_dup 1)
12612 (label_ref (match_operand 0 "" ""))
12615 "ix86_expand_branch (EQ, operands[0]); DONE;")
12617 (define_expand "bne"
12619 (if_then_else (match_dup 1)
12620 (label_ref (match_operand 0 "" ""))
12623 "ix86_expand_branch (NE, operands[0]); DONE;")
12625 (define_expand "bgt"
12627 (if_then_else (match_dup 1)
12628 (label_ref (match_operand 0 "" ""))
12631 "ix86_expand_branch (GT, operands[0]); DONE;")
12633 (define_expand "bgtu"
12635 (if_then_else (match_dup 1)
12636 (label_ref (match_operand 0 "" ""))
12639 "ix86_expand_branch (GTU, operands[0]); DONE;")
12641 (define_expand "blt"
12643 (if_then_else (match_dup 1)
12644 (label_ref (match_operand 0 "" ""))
12647 "ix86_expand_branch (LT, operands[0]); DONE;")
12649 (define_expand "bltu"
12651 (if_then_else (match_dup 1)
12652 (label_ref (match_operand 0 "" ""))
12655 "ix86_expand_branch (LTU, operands[0]); DONE;")
12657 (define_expand "bge"
12659 (if_then_else (match_dup 1)
12660 (label_ref (match_operand 0 "" ""))
12663 "ix86_expand_branch (GE, operands[0]); DONE;")
12665 (define_expand "bgeu"
12667 (if_then_else (match_dup 1)
12668 (label_ref (match_operand 0 "" ""))
12671 "ix86_expand_branch (GEU, operands[0]); DONE;")
12673 (define_expand "ble"
12675 (if_then_else (match_dup 1)
12676 (label_ref (match_operand 0 "" ""))
12679 "ix86_expand_branch (LE, operands[0]); DONE;")
12681 (define_expand "bleu"
12683 (if_then_else (match_dup 1)
12684 (label_ref (match_operand 0 "" ""))
12687 "ix86_expand_branch (LEU, operands[0]); DONE;")
12689 (define_expand "bunordered"
12691 (if_then_else (match_dup 1)
12692 (label_ref (match_operand 0 "" ""))
12694 "TARGET_80387 || TARGET_SSE"
12695 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12697 (define_expand "bordered"
12699 (if_then_else (match_dup 1)
12700 (label_ref (match_operand 0 "" ""))
12702 "TARGET_80387 || TARGET_SSE"
12703 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12705 (define_expand "buneq"
12707 (if_then_else (match_dup 1)
12708 (label_ref (match_operand 0 "" ""))
12710 "TARGET_80387 || TARGET_SSE"
12711 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12713 (define_expand "bunge"
12715 (if_then_else (match_dup 1)
12716 (label_ref (match_operand 0 "" ""))
12718 "TARGET_80387 || TARGET_SSE"
12719 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12721 (define_expand "bungt"
12723 (if_then_else (match_dup 1)
12724 (label_ref (match_operand 0 "" ""))
12726 "TARGET_80387 || TARGET_SSE"
12727 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12729 (define_expand "bunle"
12731 (if_then_else (match_dup 1)
12732 (label_ref (match_operand 0 "" ""))
12734 "TARGET_80387 || TARGET_SSE"
12735 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12737 (define_expand "bunlt"
12739 (if_then_else (match_dup 1)
12740 (label_ref (match_operand 0 "" ""))
12742 "TARGET_80387 || TARGET_SSE"
12743 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12745 (define_expand "bltgt"
12747 (if_then_else (match_dup 1)
12748 (label_ref (match_operand 0 "" ""))
12750 "TARGET_80387 || TARGET_SSE"
12751 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12753 (define_insn "*jcc_1"
12755 (if_then_else (match_operator 1 "ix86_comparison_operator"
12756 [(reg 17) (const_int 0)])
12757 (label_ref (match_operand 0 "" ""))
12761 [(set_attr "type" "ibr")
12762 (set (attr "prefix_0f")
12763 (if_then_else (and (ge (minus (match_dup 0) (pc))
12765 (lt (minus (match_dup 0) (pc))
12770 (define_insn "*jcc_2"
12772 (if_then_else (match_operator 1 "ix86_comparison_operator"
12773 [(reg 17) (const_int 0)])
12775 (label_ref (match_operand 0 "" ""))))]
12778 [(set_attr "type" "ibr")
12779 (set (attr "prefix_0f")
12780 (if_then_else (and (ge (minus (match_dup 0) (pc))
12782 (lt (minus (match_dup 0) (pc))
12787 ;; Define combination compare-and-branch fp compare instructions to use
12788 ;; during early optimization. Splitting the operation apart early makes
12789 ;; for bad code when we want to reverse the operation.
12791 (define_insn "*fp_jcc_1"
12793 (if_then_else (match_operator 0 "comparison_operator"
12794 [(match_operand 1 "register_operand" "f")
12795 (match_operand 2 "register_operand" "f")])
12796 (label_ref (match_operand 3 "" ""))
12798 (clobber (reg:CCFP 18))
12799 (clobber (reg:CCFP 17))]
12800 "TARGET_CMOVE && TARGET_80387
12801 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12802 && FLOAT_MODE_P (GET_MODE (operands[1]))
12803 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12806 (define_insn "*fp_jcc_1_sse"
12808 (if_then_else (match_operator 0 "comparison_operator"
12809 [(match_operand 1 "register_operand" "f#x,x#f")
12810 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12811 (label_ref (match_operand 3 "" ""))
12813 (clobber (reg:CCFP 18))
12814 (clobber (reg:CCFP 17))]
12816 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12817 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12820 (define_insn "*fp_jcc_1_sse_only"
12822 (if_then_else (match_operator 0 "comparison_operator"
12823 [(match_operand 1 "register_operand" "x")
12824 (match_operand 2 "nonimmediate_operand" "xm")])
12825 (label_ref (match_operand 3 "" ""))
12827 (clobber (reg:CCFP 18))
12828 (clobber (reg:CCFP 17))]
12829 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12830 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12833 (define_insn "*fp_jcc_2"
12835 (if_then_else (match_operator 0 "comparison_operator"
12836 [(match_operand 1 "register_operand" "f")
12837 (match_operand 2 "register_operand" "f")])
12839 (label_ref (match_operand 3 "" ""))))
12840 (clobber (reg:CCFP 18))
12841 (clobber (reg:CCFP 17))]
12842 "TARGET_CMOVE && TARGET_80387
12843 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12844 && FLOAT_MODE_P (GET_MODE (operands[1]))
12845 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12848 (define_insn "*fp_jcc_2_sse"
12850 (if_then_else (match_operator 0 "comparison_operator"
12851 [(match_operand 1 "register_operand" "f#x,x#f")
12852 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12854 (label_ref (match_operand 3 "" ""))))
12855 (clobber (reg:CCFP 18))
12856 (clobber (reg:CCFP 17))]
12858 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12859 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12862 (define_insn "*fp_jcc_2_sse_only"
12864 (if_then_else (match_operator 0 "comparison_operator"
12865 [(match_operand 1 "register_operand" "x")
12866 (match_operand 2 "nonimmediate_operand" "xm")])
12868 (label_ref (match_operand 3 "" ""))))
12869 (clobber (reg:CCFP 18))
12870 (clobber (reg:CCFP 17))]
12871 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12872 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12875 (define_insn "*fp_jcc_3"
12877 (if_then_else (match_operator 0 "comparison_operator"
12878 [(match_operand 1 "register_operand" "f")
12879 (match_operand 2 "nonimmediate_operand" "fm")])
12880 (label_ref (match_operand 3 "" ""))
12882 (clobber (reg:CCFP 18))
12883 (clobber (reg:CCFP 17))
12884 (clobber (match_scratch:HI 4 "=a"))]
12886 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12887 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12888 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12889 && SELECT_CC_MODE (GET_CODE (operands[0]),
12890 operands[1], operands[2]) == CCFPmode"
12893 (define_insn "*fp_jcc_4"
12895 (if_then_else (match_operator 0 "comparison_operator"
12896 [(match_operand 1 "register_operand" "f")
12897 (match_operand 2 "nonimmediate_operand" "fm")])
12899 (label_ref (match_operand 3 "" ""))))
12900 (clobber (reg:CCFP 18))
12901 (clobber (reg:CCFP 17))
12902 (clobber (match_scratch:HI 4 "=a"))]
12904 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12905 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12906 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12907 && SELECT_CC_MODE (GET_CODE (operands[0]),
12908 operands[1], operands[2]) == CCFPmode"
12911 (define_insn "*fp_jcc_5"
12913 (if_then_else (match_operator 0 "comparison_operator"
12914 [(match_operand 1 "register_operand" "f")
12915 (match_operand 2 "register_operand" "f")])
12916 (label_ref (match_operand 3 "" ""))
12918 (clobber (reg:CCFP 18))
12919 (clobber (reg:CCFP 17))
12920 (clobber (match_scratch:HI 4 "=a"))]
12922 && FLOAT_MODE_P (GET_MODE (operands[1]))
12923 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12926 (define_insn "*fp_jcc_6"
12928 (if_then_else (match_operator 0 "comparison_operator"
12929 [(match_operand 1 "register_operand" "f")
12930 (match_operand 2 "register_operand" "f")])
12932 (label_ref (match_operand 3 "" ""))))
12933 (clobber (reg:CCFP 18))
12934 (clobber (reg:CCFP 17))
12935 (clobber (match_scratch:HI 4 "=a"))]
12937 && FLOAT_MODE_P (GET_MODE (operands[1]))
12938 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12943 (if_then_else (match_operator 0 "comparison_operator"
12944 [(match_operand 1 "register_operand" "")
12945 (match_operand 2 "nonimmediate_operand" "")])
12946 (match_operand 3 "" "")
12947 (match_operand 4 "" "")))
12948 (clobber (reg:CCFP 18))
12949 (clobber (reg:CCFP 17))]
12954 ix86_split_fp_branch (operands[0], operands[1], operands[2],
12955 operands[3], operands[4], NULL_RTX);
12961 (if_then_else (match_operator 0 "comparison_operator"
12962 [(match_operand 1 "register_operand" "")
12963 (match_operand 2 "nonimmediate_operand" "")])
12964 (match_operand 3 "" "")
12965 (match_operand 4 "" "")))
12966 (clobber (reg:CCFP 18))
12967 (clobber (reg:CCFP 17))
12968 (clobber (match_scratch:HI 5 "=a"))]
12971 (if_then_else (match_dup 6)
12976 ix86_split_fp_branch (operands[0], operands[1], operands[2],
12977 operands[3], operands[4], operands[5]);
12981 ;; Unconditional and other jump instructions
12983 (define_insn "jump"
12985 (label_ref (match_operand 0 "" "")))]
12988 [(set_attr "type" "ibr")])
12990 (define_insn "indirect_jump"
12991 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
12994 [(set_attr "type" "ibr")
12995 (set_attr "length_immediate" "0")])
12997 (define_insn "tablejump"
12998 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
12999 (use (label_ref (match_operand 1 "" "")))]
13002 [(set_attr "type" "ibr")
13003 (set_attr "length_immediate" "0")])
13005 ;; Implement switch statements when generating PIC code. Switches are
13006 ;; implemented by `tablejump' when not using -fpic.
13008 ;; Emit code here to do the range checking and make the index zero based.
13010 ;; Each entry in the "addr_diff_vec" looks like this as the result of the
13011 ;; two rules below:
13013 ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
13015 ;; 1. An expression involving an external reference may only use the
13016 ;; addition operator, and only with an assembly-time constant.
13017 ;; The example above satisfies this because ".-.L2" is a constant.
13019 ;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
13020 ;; given the value of "GOT - .", where GOT is the actual address of
13021 ;; the Global Offset Table. Therefore, the .long above actually
13022 ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
13023 ;; expression "GOT - .L2" by itself would generate an error from as(1).
13025 ;; The pattern below emits code that looks like this:
13028 ;; subl TABLE@GOTOFF(%ebx,index,4),reg
13031 ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
13032 ;; the addr_diff_vec is known to be part of this module.
13034 ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
13035 ;; evaluates to just ".L2".
13037 (define_expand "casesi"
13038 [(set (match_dup 5)
13039 (match_operand:SI 0 "general_operand" ""))
13040 (parallel [(set (match_dup 6)
13041 (minus:SI (match_dup 5)
13042 (match_operand:SI 1 "general_operand" "")))
13043 (clobber (reg:CC 17))])
13045 (compare:CC (match_dup 6)
13046 (match_operand:SI 2 "general_operand" "")))
13048 (if_then_else (gtu (reg:CC 17)
13050 (label_ref (match_operand 4 "" ""))
13053 [(set (match_dup 7)
13054 (minus:SI (match_dup 8)
13055 (mem:SI (plus:SI (plus:SI (mult:SI (match_dup 6) (const_int 4))
13057 (const (unspec [(label_ref (match_operand 3 "" ""))] 7))))))
13058 (clobber (reg:CC 17))])
13059 (parallel [(set (pc) (match_dup 7))
13060 (use (label_ref (match_dup 3)))])]
13064 operands[5] = gen_reg_rtx (SImode);
13065 operands[6] = gen_reg_rtx (SImode);
13066 operands[7] = gen_reg_rtx (SImode);
13067 operands[8] = pic_offset_table_rtx;
13068 current_function_uses_pic_offset_table = 1;
13071 (define_insn "*tablejump_pic"
13072 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13073 (use (label_ref (match_operand 1 "" "")))]
13076 [(set_attr "type" "ibr")
13077 (set_attr "length_immediate" "0")])
13079 ;; Loop instruction
13081 ;; This is all complicated by the fact that since this is a jump insn
13082 ;; we must handle our own reloads.
13084 (define_expand "doloop_end"
13085 [(use (match_operand 0 "" "")) ; loop pseudo
13086 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13087 (use (match_operand 2 "" "")) ; max iterations
13088 (use (match_operand 3 "" "")) ; loop level
13089 (use (match_operand 4 "" ""))] ; label
13090 "TARGET_USE_LOOP && !TARGET_64BIT"
13093 /* Only use cloop on innermost loops. */
13094 if (INTVAL (operands[3]) > 1)
13096 if (GET_MODE (operands[0]) != SImode)
13098 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13103 (define_insn "doloop_end_internal"
13105 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13107 (label_ref (match_operand 0 "" ""))
13109 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13110 (plus:SI (match_dup 1)
13112 (clobber (match_scratch:SI 3 "=X,X,r"))
13113 (clobber (reg:CC 17))]
13114 "TARGET_USE_LOOP && !TARGET_64BIT"
13117 if (which_alternative != 0)
13119 if (get_attr_length (insn) == 2)
13120 return \"loop\\t%l0\";
13122 return \"dec{l}\\t%1\;jne\\t%l0\";
13124 [(set_attr "ppro_uops" "many")
13126 (if_then_else (and (eq_attr "alternative" "0")
13127 (and (ge (minus (match_dup 0) (pc))
13129 (lt (minus (match_dup 0) (pc))
13131 (const_string "ibr")
13132 (const_string "multi")))])
13136 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13138 (match_operand 0 "" "")
13141 (plus:SI (match_dup 1)
13143 (clobber (match_scratch:SI 2 ""))
13144 (clobber (reg:CC 17))]
13145 "TARGET_USE_LOOP && !TARGET_64BIT
13146 && reload_completed
13147 && REGNO (operands[1]) != 2"
13148 [(parallel [(set (reg:CCZ 17)
13149 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13151 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13152 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13159 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13161 (match_operand 0 "" "")
13163 (set (match_operand:SI 2 "nonimmediate_operand" "")
13164 (plus:SI (match_dup 1)
13166 (clobber (match_scratch:SI 3 ""))
13167 (clobber (reg:CC 17))]
13168 "TARGET_USE_LOOP && !TARGET_64BIT
13169 && reload_completed
13170 && (! REG_P (operands[2])
13171 || ! rtx_equal_p (operands[1], operands[2]))"
13172 [(set (match_dup 3) (match_dup 1))
13173 (parallel [(set (reg:CCZ 17)
13174 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13176 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13177 (set (match_dup 2) (match_dup 3))
13178 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13183 ;; Call instructions.
13185 ;; The predicates normally associated with named expanders are not properly
13186 ;; checked for calls. This is a bug in the generic code, but it isn't that
13187 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13189 ;; Call subroutine returning no value.
13191 (define_expand "call_pop"
13192 [(parallel [(call (match_operand:QI 0 "" "")
13193 (match_operand:SI 1 "" ""))
13195 (plus:SI (reg:SI 7)
13196 (match_operand:SI 3 "" "")))])]
13200 if (operands[3] == const0_rtx)
13202 emit_insn (gen_call (operands[0], operands[1], constm1_rtx));
13205 /* Static functions and indirect calls don't need
13206 current_function_uses_pic_offset_table. */
13208 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13209 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13210 current_function_uses_pic_offset_table = 1;
13211 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13212 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13217 (define_insn "*call_pop_0"
13218 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13219 (match_operand:SI 1 "" ""))
13220 (set (reg:SI 7) (plus:SI (reg:SI 7)
13221 (match_operand:SI 2 "immediate_operand" "")))]
13225 if (SIBLING_CALL_P (insn))
13226 return \"jmp\\t%P0\";
13228 return \"call\\t%P0\";
13230 [(set_attr "type" "call")])
13232 (define_insn "*call_pop_1"
13233 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13234 (match_operand:SI 1 "" ""))
13235 (set (reg:SI 7) (plus:SI (reg:SI 7)
13236 (match_operand:SI 2 "immediate_operand" "i")))]
13240 if (constant_call_address_operand (operands[0], Pmode))
13242 if (SIBLING_CALL_P (insn))
13243 return \"jmp\\t%P0\";
13245 return \"call\\t%P0\";
13247 if (SIBLING_CALL_P (insn))
13248 return \"jmp\\t%A0\";
13250 return \"call\\t%A0\";
13252 [(set_attr "type" "call")])
13254 (define_expand "call"
13255 [(call (match_operand:QI 0 "" "")
13256 (match_operand 1 "" ""))
13257 (use (match_operand 2 "" ""))]
13258 ;; Operand 1 not used on the i386.
13263 /* Static functions and indirect calls don't need
13264 current_function_uses_pic_offset_table. */
13266 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
13267 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
13268 current_function_uses_pic_offset_table = 1;
13270 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
13271 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
13272 if (TARGET_64BIT && INTVAL (operands[2]) >= 0)
13274 rtx reg = gen_rtx_REG (QImode, 0);
13275 emit_move_insn (reg, operands[2]);
13276 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13277 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13280 insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
13284 (define_expand "call_exp"
13285 [(call (match_operand:QI 0 "" "")
13286 (match_operand 1 "" ""))]
13290 (define_insn "*call_0"
13291 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13292 (match_operand 1 "" ""))]
13296 if (SIBLING_CALL_P (insn))
13297 return \"jmp\\t%P0\";
13299 return \"call\\t%P0\";
13301 [(set_attr "type" "call")])
13303 (define_insn "*call_1"
13304 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13305 (match_operand 1 "" ""))]
13309 if (constant_call_address_operand (operands[0], QImode))
13311 if (SIBLING_CALL_P (insn))
13312 return \"jmp\\t%P0\";
13314 return \"call\\t%P0\";
13316 if (SIBLING_CALL_P (insn))
13317 return \"jmp\\t%A0\";
13319 return \"call\\t%A0\";
13321 [(set_attr "type" "call")])
13323 (define_insn "*call_1_rex64"
13324 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13325 (match_operand 1 "" ""))]
13329 if (constant_call_address_operand (operands[0], QImode))
13331 if (SIBLING_CALL_P (insn))
13332 return \"jmp\\t%P0\";
13334 return \"call\\t%P0\";
13336 if (SIBLING_CALL_P (insn))
13337 return \"jmp\\t%A0\";
13339 return \"call\\t%A0\";
13341 [(set_attr "type" "call")])
13343 ;; Call subroutine, returning value in operand 0
13344 ;; (which must be a hard register).
13346 (define_expand "call_value_pop"
13347 [(parallel [(set (match_operand 0 "" "")
13348 (call (match_operand:QI 1 "" "")
13349 (match_operand:SI 2 "" "")))
13351 (plus:SI (reg:SI 7)
13352 (match_operand:SI 4 "" "")))])]
13356 if (operands[4] == const0_rtx)
13358 emit_insn (gen_call_value (operands[0], operands[1], operands[2],
13362 /* Static functions and indirect calls don't need
13363 current_function_uses_pic_offset_table. */
13365 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13366 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13367 current_function_uses_pic_offset_table = 1;
13368 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13369 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13372 (define_expand "call_value"
13373 [(set (match_operand 0 "" "")
13374 (call (match_operand:QI 1 "" "")
13375 (match_operand:SI 2 "" "")))
13376 (use (match_operand:SI 3 "" ""))]
13377 ;; Operand 2 not used on the i386.
13382 /* Static functions and indirect calls don't need
13383 current_function_uses_pic_offset_table. */
13385 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13386 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
13387 current_function_uses_pic_offset_table = 1;
13388 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
13389 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
13390 if (TARGET_64BIT && INTVAL (operands[3]) >= 0)
13392 rtx reg = gen_rtx_REG (QImode, 0);
13393 emit_move_insn (reg, operands[3]);
13394 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13396 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
13399 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
13404 (define_expand "call_value_exp"
13405 [(set (match_operand 0 "" "")
13406 (call (match_operand:QI 1 "" "")
13407 (match_operand:SI 2 "" "")))]
13411 ;; Call subroutine returning any type.
13413 (define_expand "untyped_call"
13414 [(parallel [(call (match_operand 0 "" "")
13416 (match_operand 1 "" "")
13417 (match_operand 2 "" "")])]
13423 /* In order to give reg-stack an easier job in validating two
13424 coprocessor registers as containing a possible return value,
13425 simply pretend the untyped call returns a complex long double
13428 emit_call_insn (TARGET_80387
13429 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
13430 operands[0], const0_rtx,
13431 GEN_INT (SSE_REGPARM_MAX - 1))
13432 : gen_call (operands[0], const0_rtx,
13433 GEN_INT (SSE_REGPARM_MAX - 1)));
13435 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13437 rtx set = XVECEXP (operands[2], 0, i);
13438 emit_move_insn (SET_DEST (set), SET_SRC (set));
13441 /* The optimizer does not know that the call sets the function value
13442 registers we stored in the result block. We avoid problems by
13443 claiming that all hard registers are used and clobbered at this
13445 emit_insn (gen_blockage ());
13450 ;; Prologue and epilogue instructions
13452 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13453 ;; all of memory. This blocks insns from being moved across this point.
13455 (define_insn "blockage"
13456 [(unspec_volatile [(const_int 0)] 0)]
13459 [(set_attr "length" "0")])
13461 ;; Insn emitted into the body of a function to return from a function.
13462 ;; This is only done if the function's epilogue is known to be simple.
13463 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13465 (define_expand "return"
13467 "ix86_can_use_return_insn_p ()"
13470 if (current_function_pops_args)
13472 rtx popc = GEN_INT (current_function_pops_args);
13473 emit_jump_insn (gen_return_pop_internal (popc));
13478 (define_insn "return_internal"
13482 [(set_attr "length" "1")
13483 (set_attr "length_immediate" "0")
13484 (set_attr "modrm" "0")])
13486 (define_insn "return_pop_internal"
13488 (use (match_operand:SI 0 "const_int_operand" ""))]
13491 [(set_attr "length" "3")
13492 (set_attr "length_immediate" "2")
13493 (set_attr "modrm" "0")])
13495 (define_insn "return_indirect_internal"
13497 (use (match_operand:SI 0 "register_operand" "r"))]
13500 [(set_attr "type" "ibr")
13501 (set_attr "length_immediate" "0")])
13507 [(set_attr "length" "1")
13508 (set_attr "length_immediate" "0")
13509 (set_attr "modrm" "0")
13510 (set_attr "ppro_uops" "one")])
13512 (define_expand "prologue"
13515 "ix86_expand_prologue (); DONE;")
13517 (define_insn "prologue_set_got"
13518 [(set (match_operand:SI 0 "register_operand" "=r")
13519 (unspec_volatile:SI
13520 [(plus:SI (match_dup 0)
13521 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
13522 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
13523 (clobber (reg:CC 17))]
13527 if (GET_CODE (operands[2]) == LABEL_REF)
13528 operands[2] = XEXP (operands[2], 0);
13529 if (TARGET_DEEP_BRANCH_PREDICTION)
13530 return \"add{l}\\t{%1, %0|%0, %1}\";
13532 return \"add{l}\\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}\";
13534 [(set_attr "type" "alu")
13535 ; Since this insn may have two constant operands, we must set the
13537 (set_attr "length_immediate" "4")
13538 (set_attr "mode" "SI")])
13540 (define_insn "prologue_get_pc"
13541 [(set (match_operand:SI 0 "register_operand" "=r")
13542 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
13546 if (GET_CODE (operands[1]) == LABEL_REF)
13547 operands[1] = XEXP (operands[1], 0);
13548 output_asm_insn (\"call\\t%X1\", operands);
13549 if (! TARGET_DEEP_BRANCH_PREDICTION)
13551 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
13552 CODE_LABEL_NUMBER (operands[1]));
13556 [(set_attr "type" "multi")])
13558 (define_expand "epilogue"
13561 "ix86_expand_epilogue (1); DONE;")
13563 (define_expand "sibcall_epilogue"
13566 "ix86_expand_epilogue (0); DONE;")
13568 (define_expand "eh_return"
13569 [(use (match_operand 0 "register_operand" ""))
13570 (use (match_operand 1 "register_operand" ""))]
13574 rtx tmp, sa = operands[0], ra = operands[1];
13576 /* Tricky bit: we write the address of the handler to which we will
13577 be returning into someone else's stack frame, one word below the
13578 stack address we wish to restore. */
13579 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13580 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13581 tmp = gen_rtx_MEM (Pmode, tmp);
13582 emit_move_insn (tmp, ra);
13584 emit_insn (gen_eh_return_1 (sa));
13589 (define_insn_and_split "eh_return_1"
13590 [(unspec_volatile [(match_operand 0 "register_operand" "c")] 13)]
13595 "ix86_expand_epilogue (2); DONE;")
13597 (define_insn "leave"
13598 [(set (reg:SI 7) (reg:SI 6))
13599 (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))]
13602 [(set_attr "length_immediate" "0")
13603 (set_attr "length" "1")
13604 (set_attr "modrm" "0")
13605 (set_attr "modrm" "0")
13606 (set_attr "athlon_decode" "vector")
13607 (set_attr "ppro_uops" "few")])
13609 (define_insn "leave_rex64"
13610 [(set (reg:DI 7) (reg:DI 6))
13611 (set (reg:DI 6) (mem:DI (pre_dec:DI (reg:DI 7))))]
13614 [(set_attr "length_immediate" "0")
13615 (set_attr "length" "1")
13616 (set_attr "modrm" "0")
13617 (set_attr "modrm" "0")
13618 (set_attr "athlon_decode" "vector")
13619 (set_attr "ppro_uops" "few")])
13621 (define_expand "ffssi2"
13622 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13623 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13627 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13628 rtx in = operands[1];
13632 emit_move_insn (tmp, constm1_rtx);
13633 emit_insn (gen_ffssi_1 (out, in));
13634 emit_insn (gen_rtx_SET (VOIDmode, out,
13635 gen_rtx_IF_THEN_ELSE (SImode,
13636 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13640 emit_insn (gen_addsi3 (out, out, const1_rtx));
13641 emit_move_insn (operands[0], out);
13644 /* Pentium bsf instruction is extremly slow. The following code is
13645 recommended by the Intel Optimizing Manual as a reasonable replacement:
13649 MOV DWORD PTR [TEMP+4],ECX
13652 MOV DWORD PTR [TEMP],EAX
13653 FILD QWORD PTR [TEMP]
13654 FSTP QWORD PTR [TEMP]
13655 WAIT ; WAIT only needed for compatibility with
13656 ; earlier processors
13657 MOV ECX, DWORD PTR [TEMP+4]
13660 TEST EAX,EAX ; clear zero flag
13662 Following piece of code expand ffs to similar beast.
13665 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13667 rtx label = gen_label_rtx ();
13669 rtx mem = assign_386_stack_local (DImode, 0);
13670 rtx fptmp = gen_reg_rtx (DFmode);
13671 split_di (&mem, 1, &lo, &hi);
13673 emit_move_insn (out, const0_rtx);
13675 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, 0, label);
13677 emit_move_insn (hi, out);
13678 emit_insn (gen_subsi3 (out, out, in));
13679 emit_insn (gen_andsi3 (out, out, in));
13680 emit_move_insn (lo, out);
13681 emit_insn (gen_floatdidf2 (fptmp,mem));
13682 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13683 emit_move_insn (out, hi);
13684 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13685 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13687 emit_label (label);
13688 LABEL_NUSES (label) = 1;
13690 emit_move_insn (operands[0], out);
13694 emit_move_insn (tmp, const0_rtx);
13695 emit_insn (gen_ffssi_1 (out, in));
13696 emit_insn (gen_rtx_SET (VOIDmode,
13697 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13698 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13700 emit_insn (gen_negsi2 (tmp, tmp));
13701 emit_insn (gen_iorsi3 (out, out, tmp));
13702 emit_insn (gen_addsi3 (out, out, const1_rtx));
13703 emit_move_insn (operands[0], out);
13708 (define_insn "ffssi_1"
13710 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13712 (set (match_operand:SI 0 "register_operand" "=r")
13713 (unspec:SI [(match_dup 1)] 5))]
13715 "bsf{l}\\t{%1, %0|%0, %1}"
13716 [(set_attr "prefix_0f" "1")
13717 (set_attr "ppro_uops" "few")])
13719 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13720 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13722 ;; These patterns match the binary 387 instructions for addM3, subM3,
13723 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13724 ;; SFmode. The first is the normal insn, the second the same insn but
13725 ;; with one operand a conversion, and the third the same insn but with
13726 ;; the other operand a conversion. The conversion may be SFmode or
13727 ;; SImode if the target mode DFmode, but only SImode if the target mode
13730 ;; Gcc is slightly more smart about handling normal two address instructions
13731 ;; so use special patterns for add and mull.
13732 (define_insn "*fop_sf_comm"
13733 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13734 (match_operator:SF 3 "binary_fp_operator"
13735 [(match_operand:SF 1 "register_operand" "%0,0")
13736 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13737 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13738 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13739 "* return output_387_binary_op (insn, operands);"
13740 [(set (attr "type")
13741 (if_then_else (eq_attr "alternative" "1")
13742 (const_string "sse")
13743 (if_then_else (match_operand:SF 3 "mult_operator" "")
13744 (const_string "fmul")
13745 (const_string "fop"))))
13746 (set_attr "mode" "SF")])
13748 (define_insn "*fop_sf_comm_sse"
13749 [(set (match_operand:SF 0 "register_operand" "=x")
13750 (match_operator:SF 3 "binary_fp_operator"
13751 [(match_operand:SF 1 "register_operand" "%0")
13752 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13753 "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13754 "* return output_387_binary_op (insn, operands);"
13755 [(set_attr "type" "sse")
13756 (set_attr "mode" "SF")])
13758 (define_insn "*fop_df_comm"
13759 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13760 (match_operator:DF 3 "binary_fp_operator"
13761 [(match_operand:DF 1 "register_operand" "%0,0")
13762 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13763 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13764 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13765 "* return output_387_binary_op (insn, operands);"
13766 [(set (attr "type")
13767 (if_then_else (eq_attr "alternative" "1")
13768 (const_string "sse")
13769 (if_then_else (match_operand:SF 3 "mult_operator" "")
13770 (const_string "fmul")
13771 (const_string "fop"))))
13772 (set_attr "mode" "DF")])
13774 (define_insn "*fop_df_comm_sse"
13775 [(set (match_operand:DF 0 "register_operand" "=Y")
13776 (match_operator:DF 3 "binary_fp_operator"
13777 [(match_operand:DF 1 "register_operand" "%0")
13778 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13780 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13781 "* return output_387_binary_op (insn, operands);"
13782 [(set_attr "type" "sse")
13783 (set_attr "mode" "DF")])
13785 (define_insn "*fop_xf_comm"
13786 [(set (match_operand:XF 0 "register_operand" "=f")
13787 (match_operator:XF 3 "binary_fp_operator"
13788 [(match_operand:XF 1 "register_operand" "%0")
13789 (match_operand:XF 2 "register_operand" "f")]))]
13790 "TARGET_80387 && !TARGET_64BIT
13791 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13792 "* return output_387_binary_op (insn, operands);"
13793 [(set (attr "type")
13794 (if_then_else (match_operand:XF 3 "mult_operator" "")
13795 (const_string "fmul")
13796 (const_string "fop")))
13797 (set_attr "mode" "XF")])
13799 (define_insn "*fop_tf_comm"
13800 [(set (match_operand:TF 0 "register_operand" "=f")
13801 (match_operator:TF 3 "binary_fp_operator"
13802 [(match_operand:TF 1 "register_operand" "%0")
13803 (match_operand:TF 2 "register_operand" "f")]))]
13804 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13805 "* return output_387_binary_op (insn, operands);"
13806 [(set (attr "type")
13807 (if_then_else (match_operand:TF 3 "mult_operator" "")
13808 (const_string "fmul")
13809 (const_string "fop")))
13810 (set_attr "mode" "XF")])
13812 (define_insn "*fop_sf_1"
13813 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
13814 (match_operator:SF 3 "binary_fp_operator"
13815 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
13816 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
13817 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13818 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13819 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13820 "* return output_387_binary_op (insn, operands);"
13821 [(set (attr "type")
13822 (cond [(eq_attr "alternative" "2")
13823 (const_string "sse")
13824 (match_operand:SF 3 "mult_operator" "")
13825 (const_string "fmul")
13826 (match_operand:SF 3 "div_operator" "")
13827 (const_string "fdiv")
13829 (const_string "fop")))
13830 (set_attr "mode" "SF")])
13832 (define_insn "*fop_sf_1_sse"
13833 [(set (match_operand:SF 0 "register_operand" "=x")
13834 (match_operator:SF 3 "binary_fp_operator"
13835 [(match_operand:SF 1 "register_operand" "0")
13836 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13838 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13839 "* return output_387_binary_op (insn, operands);"
13840 [(set_attr "type" "sse")
13841 (set_attr "mode" "SF")])
13843 ;; ??? Add SSE splitters for these!
13844 (define_insn "*fop_sf_2"
13845 [(set (match_operand:SF 0 "register_operand" "=f,f")
13846 (match_operator:SF 3 "binary_fp_operator"
13847 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13848 (match_operand:SF 2 "register_operand" "0,0")]))]
13849 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13850 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13851 [(set (attr "type")
13852 (cond [(match_operand:SF 3 "mult_operator" "")
13853 (const_string "fmul")
13854 (match_operand:SF 3 "div_operator" "")
13855 (const_string "fdiv")
13857 (const_string "fop")))
13858 (set_attr "fp_int_src" "true")
13859 (set_attr "ppro_uops" "many")
13860 (set_attr "mode" "SI")])
13862 (define_insn "*fop_sf_3"
13863 [(set (match_operand:SF 0 "register_operand" "=f,f")
13864 (match_operator:SF 3 "binary_fp_operator"
13865 [(match_operand:SF 1 "register_operand" "0,0")
13866 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13867 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13868 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13869 [(set (attr "type")
13870 (cond [(match_operand:SF 3 "mult_operator" "")
13871 (const_string "fmul")
13872 (match_operand:SF 3 "div_operator" "")
13873 (const_string "fdiv")
13875 (const_string "fop")))
13876 (set_attr "fp_int_src" "true")
13877 (set_attr "ppro_uops" "many")
13878 (set_attr "mode" "SI")])
13880 (define_insn "*fop_df_1"
13881 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
13882 (match_operator:DF 3 "binary_fp_operator"
13883 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
13884 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
13885 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13886 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13887 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13888 "* return output_387_binary_op (insn, operands);"
13889 [(set (attr "type")
13890 (cond [(eq_attr "alternative" "2")
13891 (const_string "sse")
13892 (match_operand:DF 3 "mult_operator" "")
13893 (const_string "fmul")
13894 (match_operand:DF 3 "div_operator" "")
13895 (const_string "fdiv")
13897 (const_string "fop")))
13898 (set_attr "mode" "DF")])
13900 (define_insn "*fop_df_1_sse"
13901 [(set (match_operand:DF 0 "register_operand" "=Y")
13902 (match_operator:DF 3 "binary_fp_operator"
13903 [(match_operand:DF 1 "register_operand" "0")
13904 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13906 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13907 "* return output_387_binary_op (insn, operands);"
13908 [(set_attr "type" "sse")])
13910 ;; ??? Add SSE splitters for these!
13911 (define_insn "*fop_df_2"
13912 [(set (match_operand:DF 0 "register_operand" "=f,f")
13913 (match_operator:DF 3 "binary_fp_operator"
13914 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13915 (match_operand:DF 2 "register_operand" "0,0")]))]
13916 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13917 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13918 [(set (attr "type")
13919 (cond [(match_operand:DF 3 "mult_operator" "")
13920 (const_string "fmul")
13921 (match_operand:DF 3 "div_operator" "")
13922 (const_string "fdiv")
13924 (const_string "fop")))
13925 (set_attr "fp_int_src" "true")
13926 (set_attr "ppro_uops" "many")
13927 (set_attr "mode" "SI")])
13929 (define_insn "*fop_df_3"
13930 [(set (match_operand:DF 0 "register_operand" "=f,f")
13931 (match_operator:DF 3 "binary_fp_operator"
13932 [(match_operand:DF 1 "register_operand" "0,0")
13933 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13934 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13935 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13936 [(set (attr "type")
13937 (cond [(match_operand:DF 3 "mult_operator" "")
13938 (const_string "fmul")
13939 (match_operand:DF 3 "div_operator" "")
13940 (const_string "fdiv")
13942 (const_string "fop")))
13943 (set_attr "fp_int_src" "true")
13944 (set_attr "ppro_uops" "many")
13945 (set_attr "mode" "SI")])
13947 (define_insn "*fop_df_4"
13948 [(set (match_operand:DF 0 "register_operand" "=f,f")
13949 (match_operator:DF 3 "binary_fp_operator"
13950 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13951 (match_operand:DF 2 "register_operand" "0,f")]))]
13953 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13954 "* return output_387_binary_op (insn, operands);"
13955 [(set (attr "type")
13956 (cond [(match_operand:DF 3 "mult_operator" "")
13957 (const_string "fmul")
13958 (match_operand:DF 3 "div_operator" "")
13959 (const_string "fdiv")
13961 (const_string "fop")))
13962 (set_attr "mode" "SF")])
13964 (define_insn "*fop_df_5"
13965 [(set (match_operand:DF 0 "register_operand" "=f,f")
13966 (match_operator:DF 3 "binary_fp_operator"
13967 [(match_operand:DF 1 "register_operand" "0,f")
13969 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13970 "TARGET_80387 && !TARGET_SSE2"
13971 "* return output_387_binary_op (insn, operands);"
13972 [(set (attr "type")
13973 (cond [(match_operand:DF 3 "mult_operator" "")
13974 (const_string "fmul")
13975 (match_operand:DF 3 "div_operator" "")
13976 (const_string "fdiv")
13978 (const_string "fop")))
13979 (set_attr "mode" "SF")])
13981 (define_insn "*fop_xf_1"
13982 [(set (match_operand:XF 0 "register_operand" "=f,f")
13983 (match_operator:XF 3 "binary_fp_operator"
13984 [(match_operand:XF 1 "register_operand" "0,f")
13985 (match_operand:XF 2 "register_operand" "f,0")]))]
13986 "TARGET_80387 && !TARGET_64BIT
13987 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13988 "* return output_387_binary_op (insn, operands);"
13989 [(set (attr "type")
13990 (cond [(match_operand:XF 3 "mult_operator" "")
13991 (const_string "fmul")
13992 (match_operand:XF 3 "div_operator" "")
13993 (const_string "fdiv")
13995 (const_string "fop")))
13996 (set_attr "mode" "XF")])
13998 (define_insn "*fop_tf_1"
13999 [(set (match_operand:TF 0 "register_operand" "=f,f")
14000 (match_operator:TF 3 "binary_fp_operator"
14001 [(match_operand:TF 1 "register_operand" "0,f")
14002 (match_operand:TF 2 "register_operand" "f,0")]))]
14004 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14005 "* return output_387_binary_op (insn, operands);"
14006 [(set (attr "type")
14007 (cond [(match_operand:TF 3 "mult_operator" "")
14008 (const_string "fmul")
14009 (match_operand:TF 3 "div_operator" "")
14010 (const_string "fdiv")
14012 (const_string "fop")))
14013 (set_attr "mode" "XF")])
14015 (define_insn "*fop_xf_2"
14016 [(set (match_operand:XF 0 "register_operand" "=f,f")
14017 (match_operator:XF 3 "binary_fp_operator"
14018 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14019 (match_operand:XF 2 "register_operand" "0,0")]))]
14020 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
14021 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14022 [(set (attr "type")
14023 (cond [(match_operand:XF 3 "mult_operator" "")
14024 (const_string "fmul")
14025 (match_operand:XF 3 "div_operator" "")
14026 (const_string "fdiv")
14028 (const_string "fop")))
14029 (set_attr "fp_int_src" "true")
14030 (set_attr "mode" "SI")
14031 (set_attr "ppro_uops" "many")])
14033 (define_insn "*fop_tf_2"
14034 [(set (match_operand:TF 0 "register_operand" "=f,f")
14035 (match_operator:TF 3 "binary_fp_operator"
14036 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14037 (match_operand:TF 2 "register_operand" "0,0")]))]
14038 "TARGET_80387 && TARGET_USE_FIOP"
14039 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14040 [(set (attr "type")
14041 (cond [(match_operand:TF 3 "mult_operator" "")
14042 (const_string "fmul")
14043 (match_operand:TF 3 "div_operator" "")
14044 (const_string "fdiv")
14046 (const_string "fop")))
14047 (set_attr "fp_int_src" "true")
14048 (set_attr "mode" "SI")
14049 (set_attr "ppro_uops" "many")])
14051 (define_insn "*fop_xf_3"
14052 [(set (match_operand:XF 0 "register_operand" "=f,f")
14053 (match_operator:XF 3 "binary_fp_operator"
14054 [(match_operand:XF 1 "register_operand" "0,0")
14055 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14056 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
14057 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14058 [(set (attr "type")
14059 (cond [(match_operand:XF 3 "mult_operator" "")
14060 (const_string "fmul")
14061 (match_operand:XF 3 "div_operator" "")
14062 (const_string "fdiv")
14064 (const_string "fop")))
14065 (set_attr "fp_int_src" "true")
14066 (set_attr "mode" "SI")
14067 (set_attr "ppro_uops" "many")])
14069 (define_insn "*fop_tf_3"
14070 [(set (match_operand:TF 0 "register_operand" "=f,f")
14071 (match_operator:TF 3 "binary_fp_operator"
14072 [(match_operand:TF 1 "register_operand" "0,0")
14073 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14074 "TARGET_80387 && TARGET_USE_FIOP"
14075 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14076 [(set (attr "type")
14077 (cond [(match_operand:TF 3 "mult_operator" "")
14078 (const_string "fmul")
14079 (match_operand:TF 3 "div_operator" "")
14080 (const_string "fdiv")
14082 (const_string "fop")))
14083 (set_attr "fp_int_src" "true")
14084 (set_attr "mode" "SI")
14085 (set_attr "ppro_uops" "many")])
14087 (define_insn "*fop_xf_4"
14088 [(set (match_operand:XF 0 "register_operand" "=f,f")
14089 (match_operator:XF 3 "binary_fp_operator"
14090 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14091 (match_operand:XF 2 "register_operand" "0,f")]))]
14092 "TARGET_80387 && !TARGET_64BIT"
14093 "* return output_387_binary_op (insn, operands);"
14094 [(set (attr "type")
14095 (cond [(match_operand:XF 3 "mult_operator" "")
14096 (const_string "fmul")
14097 (match_operand:XF 3 "div_operator" "")
14098 (const_string "fdiv")
14100 (const_string "fop")))
14101 (set_attr "mode" "SF")])
14103 (define_insn "*fop_tf_4"
14104 [(set (match_operand:TF 0 "register_operand" "=f,f")
14105 (match_operator:TF 3 "binary_fp_operator"
14106 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14107 (match_operand:TF 2 "register_operand" "0,f")]))]
14109 "* return output_387_binary_op (insn, operands);"
14110 [(set (attr "type")
14111 (cond [(match_operand:TF 3 "mult_operator" "")
14112 (const_string "fmul")
14113 (match_operand:TF 3 "div_operator" "")
14114 (const_string "fdiv")
14116 (const_string "fop")))
14117 (set_attr "mode" "SF")])
14119 (define_insn "*fop_xf_5"
14120 [(set (match_operand:XF 0 "register_operand" "=f,f")
14121 (match_operator:XF 3 "binary_fp_operator"
14122 [(match_operand:XF 1 "register_operand" "0,f")
14124 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14125 "TARGET_80387 && !TARGET_64BIT"
14126 "* return output_387_binary_op (insn, operands);"
14127 [(set (attr "type")
14128 (cond [(match_operand:XF 3 "mult_operator" "")
14129 (const_string "fmul")
14130 (match_operand:XF 3 "div_operator" "")
14131 (const_string "fdiv")
14133 (const_string "fop")))
14134 (set_attr "mode" "SF")])
14136 (define_insn "*fop_tf_5"
14137 [(set (match_operand:TF 0 "register_operand" "=f,f")
14138 (match_operator:TF 3 "binary_fp_operator"
14139 [(match_operand:TF 1 "register_operand" "0,f")
14141 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14143 "* return output_387_binary_op (insn, operands);"
14144 [(set (attr "type")
14145 (cond [(match_operand:TF 3 "mult_operator" "")
14146 (const_string "fmul")
14147 (match_operand:TF 3 "div_operator" "")
14148 (const_string "fdiv")
14150 (const_string "fop")))
14151 (set_attr "mode" "SF")])
14153 (define_insn "*fop_xf_6"
14154 [(set (match_operand:XF 0 "register_operand" "=f,f")
14155 (match_operator:XF 3 "binary_fp_operator"
14156 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14157 (match_operand:XF 2 "register_operand" "0,f")]))]
14158 "TARGET_80387 && !TARGET_64BIT"
14159 "* return output_387_binary_op (insn, operands);"
14160 [(set (attr "type")
14161 (cond [(match_operand:XF 3 "mult_operator" "")
14162 (const_string "fmul")
14163 (match_operand:XF 3 "div_operator" "")
14164 (const_string "fdiv")
14166 (const_string "fop")))
14167 (set_attr "mode" "DF")])
14169 (define_insn "*fop_tf_6"
14170 [(set (match_operand:TF 0 "register_operand" "=f,f")
14171 (match_operator:TF 3 "binary_fp_operator"
14172 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14173 (match_operand:TF 2 "register_operand" "0,f")]))]
14175 "* return output_387_binary_op (insn, operands);"
14176 [(set (attr "type")
14177 (cond [(match_operand:TF 3 "mult_operator" "")
14178 (const_string "fmul")
14179 (match_operand:TF 3 "div_operator" "")
14180 (const_string "fdiv")
14182 (const_string "fop")))
14183 (set_attr "mode" "DF")])
14185 (define_insn "*fop_xf_7"
14186 [(set (match_operand:XF 0 "register_operand" "=f,f")
14187 (match_operator:XF 3 "binary_fp_operator"
14188 [(match_operand:XF 1 "register_operand" "0,f")
14190 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14191 "TARGET_80387 && !TARGET_64BIT"
14192 "* return output_387_binary_op (insn, operands);"
14193 [(set (attr "type")
14194 (cond [(match_operand:XF 3 "mult_operator" "")
14195 (const_string "fmul")
14196 (match_operand:XF 3 "div_operator" "")
14197 (const_string "fdiv")
14199 (const_string "fop")))
14200 (set_attr "mode" "DF")])
14202 (define_insn "*fop_tf_7"
14203 [(set (match_operand:TF 0 "register_operand" "=f,f")
14204 (match_operator:TF 3 "binary_fp_operator"
14205 [(match_operand:TF 1 "register_operand" "0,f")
14207 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14209 "* return output_387_binary_op (insn, operands);"
14210 [(set (attr "type")
14211 (cond [(match_operand:TF 3 "mult_operator" "")
14212 (const_string "fmul")
14213 (match_operand:TF 3 "div_operator" "")
14214 (const_string "fdiv")
14216 (const_string "fop")))
14217 (set_attr "mode" "DF")])
14220 [(set (match_operand 0 "register_operand" "")
14221 (match_operator 3 "binary_fp_operator"
14222 [(float (match_operand:SI 1 "register_operand" ""))
14223 (match_operand 2 "register_operand" "")]))]
14224 "TARGET_80387 && reload_completed
14225 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14229 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14230 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14231 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14232 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14233 GET_MODE (operands[3]),
14236 ix86_free_from_memory (GET_MODE (operands[1]));
14241 [(set (match_operand 0 "register_operand" "")
14242 (match_operator 3 "binary_fp_operator"
14243 [(match_operand 1 "register_operand" "")
14244 (float (match_operand:SI 2 "register_operand" ""))]))]
14245 "TARGET_80387 && reload_completed
14246 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14250 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14251 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14252 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14253 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14254 GET_MODE (operands[3]),
14257 ix86_free_from_memory (GET_MODE (operands[2]));
14261 ;; FPU special functions.
14263 (define_expand "sqrtsf2"
14264 [(set (match_operand:SF 0 "register_operand" "")
14265 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14266 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
14270 operands[1] = force_reg (SFmode, operands[1]);
14273 (define_insn "sqrtsf2_1"
14274 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14275 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14276 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14277 && (TARGET_SSE && TARGET_MIX_SSE_I387)"
14280 sqrtss\\t{%1, %0|%0, %1}"
14281 [(set_attr "type" "fpspc,sse")
14282 (set_attr "mode" "SF,SF")
14283 (set_attr "athlon_decode" "direct,*")])
14285 (define_insn "sqrtsf2_1_sse_only"
14286 [(set (match_operand:SF 0 "register_operand" "=x")
14287 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14288 "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14289 "sqrtss\\t{%1, %0|%0, %1}"
14290 [(set_attr "type" "sse")
14291 (set_attr "mode" "SF")
14292 (set_attr "athlon_decode" "*")])
14294 (define_insn "sqrtsf2_i387"
14295 [(set (match_operand:SF 0 "register_operand" "=f")
14296 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14297 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14298 && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
14300 [(set_attr "type" "fpspc")
14301 (set_attr "mode" "SF")
14302 (set_attr "athlon_decode" "direct")])
14304 (define_expand "sqrtdf2"
14305 [(set (match_operand:DF 0 "register_operand" "")
14306 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14307 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
14311 operands[1] = force_reg (DFmode, operands[1]);
14314 (define_insn "sqrtdf2_1"
14315 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14316 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14317 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14318 && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
14321 sqrtsd\\t{%1, %0|%0, %1}"
14322 [(set_attr "type" "fpspc,sse")
14323 (set_attr "mode" "DF,DF")
14324 (set_attr "athlon_decode" "direct,*")])
14326 (define_insn "sqrtdf2_1_sse_only"
14327 [(set (match_operand:DF 0 "register_operand" "=Y")
14328 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14329 "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14330 "sqrtsd\\t{%1, %0|%0, %1}"
14331 [(set_attr "type" "sse")
14332 (set_attr "mode" "DF")
14333 (set_attr "athlon_decode" "*")])
14335 (define_insn "sqrtdf2_i387"
14336 [(set (match_operand:DF 0 "register_operand" "=f")
14337 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14338 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14339 && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
14341 [(set_attr "type" "fpspc")
14342 (set_attr "mode" "DF")
14343 (set_attr "athlon_decode" "direct")])
14345 (define_insn "*sqrtextendsfdf2"
14346 [(set (match_operand:DF 0 "register_operand" "=f")
14347 (sqrt:DF (float_extend:DF
14348 (match_operand:SF 1 "register_operand" "0"))))]
14349 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
14351 [(set_attr "type" "fpspc")
14352 (set_attr "mode" "DF")
14353 (set_attr "athlon_decode" "direct")])
14355 (define_insn "sqrtxf2"
14356 [(set (match_operand:XF 0 "register_operand" "=f")
14357 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14358 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
14359 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14361 [(set_attr "type" "fpspc")
14362 (set_attr "mode" "XF")
14363 (set_attr "athlon_decode" "direct")])
14365 (define_insn "sqrttf2"
14366 [(set (match_operand:TF 0 "register_operand" "=f")
14367 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
14368 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14369 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14371 [(set_attr "type" "fpspc")
14372 (set_attr "mode" "XF")
14373 (set_attr "athlon_decode" "direct")])
14375 (define_insn "*sqrtextenddfxf2"
14376 [(set (match_operand:XF 0 "register_operand" "=f")
14377 (sqrt:XF (float_extend:XF
14378 (match_operand:DF 1 "register_operand" "0"))))]
14379 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
14381 [(set_attr "type" "fpspc")
14382 (set_attr "mode" "XF")
14383 (set_attr "athlon_decode" "direct")])
14385 (define_insn "*sqrtextenddftf2"
14386 [(set (match_operand:TF 0 "register_operand" "=f")
14387 (sqrt:TF (float_extend:TF
14388 (match_operand:DF 1 "register_operand" "0"))))]
14389 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14391 [(set_attr "type" "fpspc")
14392 (set_attr "mode" "XF")
14393 (set_attr "athlon_decode" "direct")])
14395 (define_insn "*sqrtextendsfxf2"
14396 [(set (match_operand:XF 0 "register_operand" "=f")
14397 (sqrt:XF (float_extend:XF
14398 (match_operand:SF 1 "register_operand" "0"))))]
14399 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
14401 [(set_attr "type" "fpspc")
14402 (set_attr "mode" "XF")
14403 (set_attr "athlon_decode" "direct")])
14405 (define_insn "*sqrtextendsftf2"
14406 [(set (match_operand:TF 0 "register_operand" "=f")
14407 (sqrt:TF (float_extend:TF
14408 (match_operand:SF 1 "register_operand" "0"))))]
14409 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14411 [(set_attr "type" "fpspc")
14412 (set_attr "mode" "XF")
14413 (set_attr "athlon_decode" "direct")])
14415 (define_insn "sindf2"
14416 [(set (match_operand:DF 0 "register_operand" "=f")
14417 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
14418 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14419 && flag_unsafe_math_optimizations"
14421 [(set_attr "type" "fpspc")
14422 (set_attr "mode" "DF")])
14424 (define_insn "sinsf2"
14425 [(set (match_operand:SF 0 "register_operand" "=f")
14426 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
14427 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14428 && flag_unsafe_math_optimizations"
14430 [(set_attr "type" "fpspc")
14431 (set_attr "mode" "SF")])
14433 (define_insn "*sinextendsfdf2"
14434 [(set (match_operand:DF 0 "register_operand" "=f")
14435 (unspec:DF [(float_extend:DF
14436 (match_operand:SF 1 "register_operand" "0"))] 1))]
14437 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14438 && flag_unsafe_math_optimizations"
14440 [(set_attr "type" "fpspc")
14441 (set_attr "mode" "DF")])
14443 (define_insn "sinxf2"
14444 [(set (match_operand:XF 0 "register_operand" "=f")
14445 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
14446 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
14447 && flag_unsafe_math_optimizations"
14449 [(set_attr "type" "fpspc")
14450 (set_attr "mode" "XF")])
14452 (define_insn "sintf2"
14453 [(set (match_operand:TF 0 "register_operand" "=f")
14454 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
14455 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14456 && flag_unsafe_math_optimizations"
14458 [(set_attr "type" "fpspc")
14459 (set_attr "mode" "XF")])
14461 (define_insn "cosdf2"
14462 [(set (match_operand:DF 0 "register_operand" "=f")
14463 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
14464 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14465 && flag_unsafe_math_optimizations"
14467 [(set_attr "type" "fpspc")
14468 (set_attr "mode" "DF")])
14470 (define_insn "cossf2"
14471 [(set (match_operand:SF 0 "register_operand" "=f")
14472 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
14473 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14474 && flag_unsafe_math_optimizations"
14476 [(set_attr "type" "fpspc")
14477 (set_attr "mode" "SF")])
14479 (define_insn "*cosextendsfdf2"
14480 [(set (match_operand:DF 0 "register_operand" "=f")
14481 (unspec:DF [(float_extend:DF
14482 (match_operand:SF 1 "register_operand" "0"))] 2))]
14483 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14484 && flag_unsafe_math_optimizations"
14486 [(set_attr "type" "fpspc")
14487 (set_attr "mode" "DF")])
14489 (define_insn "cosxf2"
14490 [(set (match_operand:XF 0 "register_operand" "=f")
14491 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
14492 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14493 && flag_unsafe_math_optimizations"
14495 [(set_attr "type" "fpspc")
14496 (set_attr "mode" "XF")])
14498 (define_insn "costf2"
14499 [(set (match_operand:TF 0 "register_operand" "=f")
14500 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
14501 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14502 && flag_unsafe_math_optimizations"
14504 [(set_attr "type" "fpspc")
14505 (set_attr "mode" "XF")])
14507 ;; Block operation instructions
14510 [(set (reg:SI 19) (const_int 0))]
14513 [(set_attr "type" "cld")])
14515 (define_expand "movstrsi"
14516 [(use (match_operand:BLK 0 "memory_operand" ""))
14517 (use (match_operand:BLK 1 "memory_operand" ""))
14518 (use (match_operand:SI 2 "nonmemory_operand" ""))
14519 (use (match_operand:SI 3 "const_int_operand" ""))]
14523 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14529 (define_expand "movstrdi"
14530 [(use (match_operand:BLK 0 "memory_operand" ""))
14531 (use (match_operand:BLK 1 "memory_operand" ""))
14532 (use (match_operand:DI 2 "nonmemory_operand" ""))
14533 (use (match_operand:DI 3 "const_int_operand" ""))]
14537 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14543 ;; Most CPUs don't like single string operations
14544 ;; Handle this case here to simplify previous expander.
14546 (define_expand "strmovdi_rex64"
14547 [(set (match_dup 2)
14548 (mem:DI (match_operand:DI 1 "register_operand" "")))
14549 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14551 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14552 (clobber (reg:CC 17))])
14553 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14554 (clobber (reg:CC 17))])]
14558 if (TARGET_SINGLE_STRINGOP || optimize_size)
14560 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14565 operands[2] = gen_reg_rtx (DImode);
14569 (define_expand "strmovsi"
14570 [(set (match_dup 2)
14571 (mem:SI (match_operand:SI 1 "register_operand" "")))
14572 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14574 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14575 (clobber (reg:CC 17))])
14576 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14577 (clobber (reg:CC 17))])]
14583 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14586 if (TARGET_SINGLE_STRINGOP || optimize_size)
14588 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14593 operands[2] = gen_reg_rtx (SImode);
14596 (define_expand "strmovsi_rex64"
14597 [(set (match_dup 2)
14598 (mem:SI (match_operand:DI 1 "register_operand" "")))
14599 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14601 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14602 (clobber (reg:CC 17))])
14603 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14604 (clobber (reg:CC 17))])]
14608 if (TARGET_SINGLE_STRINGOP || optimize_size)
14610 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14615 operands[2] = gen_reg_rtx (SImode);
14618 (define_expand "strmovhi"
14619 [(set (match_dup 2)
14620 (mem:HI (match_operand:SI 1 "register_operand" "")))
14621 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14623 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14624 (clobber (reg:CC 17))])
14625 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14626 (clobber (reg:CC 17))])]
14632 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14635 if (TARGET_SINGLE_STRINGOP || optimize_size)
14637 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14642 operands[2] = gen_reg_rtx (HImode);
14645 (define_expand "strmovhi_rex64"
14646 [(set (match_dup 2)
14647 (mem:HI (match_operand:DI 1 "register_operand" "")))
14648 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14650 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14651 (clobber (reg:CC 17))])
14652 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14653 (clobber (reg:CC 17))])]
14657 if (TARGET_SINGLE_STRINGOP || optimize_size)
14659 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14664 operands[2] = gen_reg_rtx (HImode);
14667 (define_expand "strmovqi"
14668 [(set (match_dup 2)
14669 (mem:QI (match_operand:SI 1 "register_operand" "")))
14670 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14672 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14673 (clobber (reg:CC 17))])
14674 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14675 (clobber (reg:CC 17))])]
14681 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14684 if (TARGET_SINGLE_STRINGOP || optimize_size)
14686 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14691 operands[2] = gen_reg_rtx (QImode);
14694 (define_expand "strmovqi_rex64"
14695 [(set (match_dup 2)
14696 (mem:QI (match_operand:DI 1 "register_operand" "")))
14697 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14699 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14700 (clobber (reg:CC 17))])
14701 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14702 (clobber (reg:CC 17))])]
14706 if (TARGET_SINGLE_STRINGOP || optimize_size)
14708 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14713 operands[2] = gen_reg_rtx (QImode);
14716 (define_insn "strmovdi_rex_1"
14717 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14718 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14719 (set (match_operand:DI 0 "register_operand" "=D")
14720 (plus:DI (match_dup 2)
14722 (set (match_operand:DI 1 "register_operand" "=S")
14723 (plus:DI (match_dup 3)
14726 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14728 [(set_attr "type" "str")
14729 (set_attr "mode" "DI")
14730 (set_attr "memory" "both")])
14732 (define_insn "strmovsi_1"
14733 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
14734 (mem:SI (match_operand:SI 3 "register_operand" "1")))
14735 (set (match_operand:SI 0 "register_operand" "=D")
14736 (plus:SI (match_dup 2)
14738 (set (match_operand:SI 1 "register_operand" "=S")
14739 (plus:SI (match_dup 3)
14742 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14744 [(set_attr "type" "str")
14745 (set_attr "mode" "SI")
14746 (set_attr "memory" "both")])
14748 (define_insn "strmovsi_rex_1"
14749 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
14750 (mem:SI (match_operand:DI 3 "register_operand" "1")))
14751 (set (match_operand:DI 0 "register_operand" "=D")
14752 (plus:DI (match_dup 2)
14754 (set (match_operand:DI 1 "register_operand" "=S")
14755 (plus:DI (match_dup 3)
14758 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14760 [(set_attr "type" "str")
14761 (set_attr "mode" "SI")
14762 (set_attr "memory" "both")])
14764 (define_insn "strmovhi_1"
14765 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
14766 (mem:HI (match_operand:SI 3 "register_operand" "1")))
14767 (set (match_operand:SI 0 "register_operand" "=D")
14768 (plus:SI (match_dup 2)
14770 (set (match_operand:SI 1 "register_operand" "=S")
14771 (plus:SI (match_dup 3)
14774 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14776 [(set_attr "type" "str")
14777 (set_attr "memory" "both")
14778 (set_attr "mode" "HI")])
14780 (define_insn "strmovhi_rex_1"
14781 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
14782 (mem:HI (match_operand:DI 3 "register_operand" "1")))
14783 (set (match_operand:DI 0 "register_operand" "=D")
14784 (plus:DI (match_dup 2)
14786 (set (match_operand:DI 1 "register_operand" "=S")
14787 (plus:DI (match_dup 3)
14790 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14792 [(set_attr "type" "str")
14793 (set_attr "memory" "both")
14794 (set_attr "mode" "HI")])
14796 (define_insn "strmovqi_1"
14797 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
14798 (mem:QI (match_operand:SI 3 "register_operand" "1")))
14799 (set (match_operand:SI 0 "register_operand" "=D")
14800 (plus:SI (match_dup 2)
14802 (set (match_operand:SI 1 "register_operand" "=S")
14803 (plus:SI (match_dup 3)
14806 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14808 [(set_attr "type" "str")
14809 (set_attr "memory" "both")
14810 (set_attr "mode" "QI")])
14812 (define_insn "strmovqi_rex_1"
14813 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
14814 (mem:QI (match_operand:DI 3 "register_operand" "1")))
14815 (set (match_operand:DI 0 "register_operand" "=D")
14816 (plus:DI (match_dup 2)
14818 (set (match_operand:DI 1 "register_operand" "=S")
14819 (plus:DI (match_dup 3)
14822 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14824 [(set_attr "type" "str")
14825 (set_attr "memory" "both")
14826 (set_attr "mode" "QI")])
14828 (define_insn "rep_movdi_rex64"
14829 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14830 (set (match_operand:DI 0 "register_operand" "=D")
14831 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14833 (match_operand:DI 3 "register_operand" "0")))
14834 (set (match_operand:DI 1 "register_operand" "=S")
14835 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
14836 (match_operand:DI 4 "register_operand" "1")))
14837 (set (mem:BLK (match_dup 3))
14838 (mem:BLK (match_dup 4)))
14839 (use (match_dup 5))
14842 "rep\;movsq|rep movsq"
14843 [(set_attr "type" "str")
14844 (set_attr "prefix_rep" "1")
14845 (set_attr "memory" "both")
14846 (set_attr "mode" "DI")])
14848 (define_insn "rep_movsi"
14849 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14850 (set (match_operand:SI 0 "register_operand" "=D")
14851 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
14853 (match_operand:SI 3 "register_operand" "0")))
14854 (set (match_operand:SI 1 "register_operand" "=S")
14855 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
14856 (match_operand:SI 4 "register_operand" "1")))
14857 (set (mem:BLK (match_dup 3))
14858 (mem:BLK (match_dup 4)))
14859 (use (match_dup 5))
14862 "rep\;movsl|rep movsd"
14863 [(set_attr "type" "str")
14864 (set_attr "prefix_rep" "1")
14865 (set_attr "memory" "both")
14866 (set_attr "mode" "SI")])
14868 (define_insn "rep_movsi_rex64"
14869 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14870 (set (match_operand:DI 0 "register_operand" "=D")
14871 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14873 (match_operand:DI 3 "register_operand" "0")))
14874 (set (match_operand:DI 1 "register_operand" "=S")
14875 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
14876 (match_operand:DI 4 "register_operand" "1")))
14877 (set (mem:BLK (match_dup 3))
14878 (mem:BLK (match_dup 4)))
14879 (use (match_dup 5))
14882 "rep\;movsl|rep movsd"
14883 [(set_attr "type" "str")
14884 (set_attr "prefix_rep" "1")
14885 (set_attr "memory" "both")
14886 (set_attr "mode" "SI")])
14888 (define_insn "rep_movqi"
14889 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14890 (set (match_operand:SI 0 "register_operand" "=D")
14891 (plus:SI (match_operand:SI 3 "register_operand" "0")
14892 (match_operand:SI 5 "register_operand" "2")))
14893 (set (match_operand:SI 1 "register_operand" "=S")
14894 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
14895 (set (mem:BLK (match_dup 3))
14896 (mem:BLK (match_dup 4)))
14897 (use (match_dup 5))
14900 "rep\;movsb|rep movsb"
14901 [(set_attr "type" "str")
14902 (set_attr "prefix_rep" "1")
14903 (set_attr "memory" "both")
14904 (set_attr "mode" "SI")])
14906 (define_insn "rep_movqi_rex64"
14907 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14908 (set (match_operand:DI 0 "register_operand" "=D")
14909 (plus:DI (match_operand:DI 3 "register_operand" "0")
14910 (match_operand:DI 5 "register_operand" "2")))
14911 (set (match_operand:DI 1 "register_operand" "=S")
14912 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
14913 (set (mem:BLK (match_dup 3))
14914 (mem:BLK (match_dup 4)))
14915 (use (match_dup 5))
14918 "rep\;movsb|rep movsb"
14919 [(set_attr "type" "str")
14920 (set_attr "prefix_rep" "1")
14921 (set_attr "memory" "both")
14922 (set_attr "mode" "SI")])
14924 (define_expand "clrstrsi"
14925 [(use (match_operand:BLK 0 "memory_operand" ""))
14926 (use (match_operand:SI 1 "nonmemory_operand" ""))
14927 (use (match_operand 2 "const_int_operand" ""))]
14931 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14937 (define_expand "clrstrdi"
14938 [(use (match_operand:BLK 0 "memory_operand" ""))
14939 (use (match_operand:DI 1 "nonmemory_operand" ""))
14940 (use (match_operand 2 "const_int_operand" ""))]
14944 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14950 ;; Most CPUs don't like single string operations
14951 ;; Handle this case here to simplify previous expander.
14953 (define_expand "strsetdi_rex64"
14954 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
14955 (match_operand:DI 1 "register_operand" ""))
14956 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14957 (clobber (reg:CC 17))])]
14961 if (TARGET_SINGLE_STRINGOP || optimize_size)
14963 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
14968 (define_expand "strsetsi"
14969 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
14970 (match_operand:SI 1 "register_operand" ""))
14971 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14972 (clobber (reg:CC 17))])]
14978 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
14981 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14983 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
14988 (define_expand "strsetsi_rex64"
14989 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
14990 (match_operand:SI 1 "register_operand" ""))
14991 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14992 (clobber (reg:CC 17))])]
14996 if (TARGET_SINGLE_STRINGOP || optimize_size)
14998 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
15003 (define_expand "strsethi"
15004 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
15005 (match_operand:HI 1 "register_operand" ""))
15006 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15007 (clobber (reg:CC 17))])]
15013 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
15016 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15018 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
15023 (define_expand "strsethi_rex64"
15024 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
15025 (match_operand:HI 1 "register_operand" ""))
15026 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15027 (clobber (reg:CC 17))])]
15031 if (TARGET_SINGLE_STRINGOP || optimize_size)
15033 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
15038 (define_expand "strsetqi"
15039 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
15040 (match_operand:QI 1 "register_operand" ""))
15041 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15042 (clobber (reg:CC 17))])]
15048 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
15051 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15053 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
15058 (define_expand "strsetqi_rex64"
15059 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
15060 (match_operand:QI 1 "register_operand" ""))
15061 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15062 (clobber (reg:CC 17))])]
15066 if (TARGET_SINGLE_STRINGOP || optimize_size)
15068 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
15073 (define_insn "strsetdi_rex_1"
15074 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15075 (match_operand:SI 2 "register_operand" "a"))
15076 (set (match_operand:DI 0 "register_operand" "=D")
15077 (plus:DI (match_dup 1)
15080 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15082 [(set_attr "type" "str")
15083 (set_attr "memory" "store")
15084 (set_attr "mode" "DI")])
15086 (define_insn "strsetsi_1"
15087 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15088 (match_operand:SI 2 "register_operand" "a"))
15089 (set (match_operand:SI 0 "register_operand" "=D")
15090 (plus:SI (match_dup 1)
15093 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15095 [(set_attr "type" "str")
15096 (set_attr "memory" "store")
15097 (set_attr "mode" "SI")])
15099 (define_insn "strsetsi_rex_1"
15100 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15101 (match_operand:SI 2 "register_operand" "a"))
15102 (set (match_operand:DI 0 "register_operand" "=D")
15103 (plus:DI (match_dup 1)
15106 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15108 [(set_attr "type" "str")
15109 (set_attr "memory" "store")
15110 (set_attr "mode" "SI")])
15112 (define_insn "strsethi_1"
15113 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15114 (match_operand:HI 2 "register_operand" "a"))
15115 (set (match_operand:SI 0 "register_operand" "=D")
15116 (plus:SI (match_dup 1)
15119 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15121 [(set_attr "type" "str")
15122 (set_attr "memory" "store")
15123 (set_attr "mode" "HI")])
15125 (define_insn "strsethi_rex_1"
15126 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15127 (match_operand:HI 2 "register_operand" "a"))
15128 (set (match_operand:DI 0 "register_operand" "=D")
15129 (plus:DI (match_dup 1)
15132 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15134 [(set_attr "type" "str")
15135 (set_attr "memory" "store")
15136 (set_attr "mode" "HI")])
15138 (define_insn "strsetqi_1"
15139 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15140 (match_operand:QI 2 "register_operand" "a"))
15141 (set (match_operand:SI 0 "register_operand" "=D")
15142 (plus:SI (match_dup 1)
15145 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15147 [(set_attr "type" "str")
15148 (set_attr "memory" "store")
15149 (set_attr "mode" "QI")])
15151 (define_insn "strsetqi_rex_1"
15152 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15153 (match_operand:QI 2 "register_operand" "a"))
15154 (set (match_operand:DI 0 "register_operand" "=D")
15155 (plus:DI (match_dup 1)
15158 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15160 [(set_attr "type" "str")
15161 (set_attr "memory" "store")
15162 (set_attr "mode" "QI")])
15164 (define_insn "rep_stosdi_rex64"
15165 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15166 (set (match_operand:DI 0 "register_operand" "=D")
15167 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15169 (match_operand:DI 3 "register_operand" "0")))
15170 (set (mem:BLK (match_dup 3))
15172 (use (match_operand:DI 2 "register_operand" "a"))
15173 (use (match_dup 4))
15176 "rep\;stosq|rep stosq"
15177 [(set_attr "type" "str")
15178 (set_attr "prefix_rep" "1")
15179 (set_attr "memory" "store")
15180 (set_attr "mode" "DI")])
15182 (define_insn "rep_stossi"
15183 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15184 (set (match_operand:SI 0 "register_operand" "=D")
15185 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15187 (match_operand:SI 3 "register_operand" "0")))
15188 (set (mem:BLK (match_dup 3))
15190 (use (match_operand:SI 2 "register_operand" "a"))
15191 (use (match_dup 4))
15194 "rep\;stosl|rep stosd"
15195 [(set_attr "type" "str")
15196 (set_attr "prefix_rep" "1")
15197 (set_attr "memory" "store")
15198 (set_attr "mode" "SI")])
15200 (define_insn "rep_stossi_rex64"
15201 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15202 (set (match_operand:DI 0 "register_operand" "=D")
15203 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15205 (match_operand:DI 3 "register_operand" "0")))
15206 (set (mem:BLK (match_dup 3))
15208 (use (match_operand:SI 2 "register_operand" "a"))
15209 (use (match_dup 4))
15212 "rep\;stosl|rep stosd"
15213 [(set_attr "type" "str")
15214 (set_attr "prefix_rep" "1")
15215 (set_attr "memory" "store")
15216 (set_attr "mode" "SI")])
15218 (define_insn "rep_stosqi"
15219 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15220 (set (match_operand:SI 0 "register_operand" "=D")
15221 (plus:SI (match_operand:SI 3 "register_operand" "0")
15222 (match_operand:SI 4 "register_operand" "1")))
15223 (set (mem:BLK (match_dup 3))
15225 (use (match_operand:QI 2 "register_operand" "a"))
15226 (use (match_dup 4))
15229 "rep\;stosb|rep stosb"
15230 [(set_attr "type" "str")
15231 (set_attr "prefix_rep" "1")
15232 (set_attr "memory" "store")
15233 (set_attr "mode" "QI")])
15235 (define_insn "rep_stosqi_rex64"
15236 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15237 (set (match_operand:DI 0 "register_operand" "=D")
15238 (plus:DI (match_operand:DI 3 "register_operand" "0")
15239 (match_operand:DI 4 "register_operand" "1")))
15240 (set (mem:BLK (match_dup 3))
15242 (use (match_operand:QI 2 "register_operand" "a"))
15243 (use (match_dup 4))
15246 "rep\;stosb|rep stosb"
15247 [(set_attr "type" "str")
15248 (set_attr "prefix_rep" "1")
15249 (set_attr "memory" "store")
15250 (set_attr "mode" "QI")])
15252 (define_expand "cmpstrsi"
15253 [(set (match_operand:SI 0 "register_operand" "")
15254 (compare:SI (match_operand:BLK 1 "general_operand" "")
15255 (match_operand:BLK 2 "general_operand" "")))
15256 (use (match_operand 3 "general_operand" ""))
15257 (use (match_operand 4 "immediate_operand" ""))]
15261 rtx addr1, addr2, out, outlow, count, countreg, align;
15264 if (GET_CODE (out) != REG)
15265 out = gen_reg_rtx (SImode);
15267 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15268 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15270 count = operands[3];
15271 countreg = copy_to_mode_reg (Pmode, count);
15273 /* %%% Iff we are testing strict equality, we can use known alignment
15274 to good advantage. This may be possible with combine, particularly
15275 once cc0 is dead. */
15276 align = operands[4];
15278 emit_insn (gen_cld ());
15279 if (GET_CODE (count) == CONST_INT)
15281 if (INTVAL (count) == 0)
15283 emit_move_insn (operands[0], const0_rtx);
15287 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
15288 addr1, addr2, countreg));
15290 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15291 addr1, addr2, countreg));
15297 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15298 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
15299 addr1, addr2, countreg));
15303 emit_insn (gen_cmpsi_1 (countreg, countreg));
15304 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15305 addr1, addr2, countreg));
15309 outlow = gen_lowpart (QImode, out);
15310 emit_insn (gen_cmpintqi (outlow));
15311 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15313 if (operands[0] != out)
15314 emit_move_insn (operands[0], out);
15319 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15321 (define_expand "cmpintqi"
15322 [(set (match_dup 1)
15323 (gtu:QI (reg:CC 17) (const_int 0)))
15325 (ltu:QI (reg:CC 17) (const_int 0)))
15326 (parallel [(set (match_operand:QI 0 "register_operand" "")
15327 (minus:QI (match_dup 1)
15329 (clobber (reg:CC 17))])]
15331 "operands[1] = gen_reg_rtx (QImode);
15332 operands[2] = gen_reg_rtx (QImode);")
15334 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15335 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15337 (define_insn "cmpstrqi_nz_1"
15339 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15340 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15341 (use (match_operand:SI 6 "register_operand" "2"))
15342 (use (match_operand:SI 3 "immediate_operand" "i"))
15344 (clobber (match_operand:SI 0 "register_operand" "=S"))
15345 (clobber (match_operand:SI 1 "register_operand" "=D"))
15346 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15349 [(set_attr "type" "str")
15350 (set_attr "mode" "QI")
15351 (set_attr "prefix_rep" "1")])
15353 (define_insn "cmpstrqi_nz_rex_1"
15355 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15356 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15357 (use (match_operand:DI 6 "register_operand" "2"))
15358 (use (match_operand:SI 3 "immediate_operand" "i"))
15360 (clobber (match_operand:DI 0 "register_operand" "=S"))
15361 (clobber (match_operand:DI 1 "register_operand" "=D"))
15362 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15365 [(set_attr "type" "str")
15366 (set_attr "mode" "QI")
15367 (set_attr "prefix_rep" "1")])
15369 ;; The same, but the count is not known to not be zero.
15371 (define_insn "cmpstrqi_1"
15373 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
15375 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15376 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
15378 (use (match_operand:SI 3 "immediate_operand" "i"))
15381 (clobber (match_operand:SI 0 "register_operand" "=S"))
15382 (clobber (match_operand:SI 1 "register_operand" "=D"))
15383 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15386 [(set_attr "type" "str")
15387 (set_attr "mode" "QI")
15388 (set_attr "prefix_rep" "1")])
15390 (define_insn "cmpstrqi_rex_1"
15392 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
15394 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15395 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
15397 (use (match_operand:SI 3 "immediate_operand" "i"))
15400 (clobber (match_operand:DI 0 "register_operand" "=S"))
15401 (clobber (match_operand:DI 1 "register_operand" "=D"))
15402 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15405 [(set_attr "type" "str")
15406 (set_attr "mode" "QI")
15407 (set_attr "prefix_rep" "1")])
15409 (define_expand "strlensi"
15410 [(set (match_operand:SI 0 "register_operand" "")
15411 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15412 (match_operand:QI 2 "immediate_operand" "")
15413 (match_operand 3 "immediate_operand" "")] 0))]
15417 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15423 (define_expand "strlendi"
15424 [(set (match_operand:DI 0 "register_operand" "")
15425 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15426 (match_operand:QI 2 "immediate_operand" "")
15427 (match_operand 3 "immediate_operand" "")] 0))]
15431 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15437 (define_insn "strlenqi_1"
15438 [(set (match_operand:SI 0 "register_operand" "=&c")
15439 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15440 (match_operand:QI 2 "register_operand" "a")
15441 (match_operand:SI 3 "immediate_operand" "i")
15442 (match_operand:SI 4 "register_operand" "0")] 0))
15444 (clobber (match_operand:SI 1 "register_operand" "=D"))
15445 (clobber (reg:CC 17))]
15448 [(set_attr "type" "str")
15449 (set_attr "mode" "QI")
15450 (set_attr "prefix_rep" "1")])
15452 (define_insn "strlenqi_rex_1"
15453 [(set (match_operand:DI 0 "register_operand" "=&c")
15454 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15455 (match_operand:QI 2 "register_operand" "a")
15456 (match_operand:DI 3 "immediate_operand" "i")
15457 (match_operand:DI 4 "register_operand" "0")] 0))
15459 (clobber (match_operand:DI 1 "register_operand" "=D"))
15460 (clobber (reg:CC 17))]
15463 [(set_attr "type" "str")
15464 (set_attr "mode" "QI")
15465 (set_attr "prefix_rep" "1")])
15467 ;; Peephole optimizations to clean up after cmpstr*. This should be
15468 ;; handled in combine, but it is not currently up to the task.
15469 ;; When used for their truth value, the cmpstr* expanders generate
15478 ;; The intermediate three instructions are unnecessary.
15480 ;; This one handles cmpstr*_nz_1...
15484 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15485 (mem:BLK (match_operand 5 "register_operand" ""))))
15486 (use (match_operand 6 "register_operand" ""))
15487 (use (match_operand:SI 3 "immediate_operand" ""))
15489 (clobber (match_operand 0 "register_operand" ""))
15490 (clobber (match_operand 1 "register_operand" ""))
15491 (clobber (match_operand 2 "register_operand" ""))])
15492 (set (match_operand:QI 7 "register_operand" "")
15493 (gtu:QI (reg:CC 17) (const_int 0)))
15494 (set (match_operand:QI 8 "register_operand" "")
15495 (ltu:QI (reg:CC 17) (const_int 0)))
15497 (compare (match_dup 7) (match_dup 8)))
15502 (compare:CC (mem:BLK (match_dup 4))
15503 (mem:BLK (match_dup 5))))
15504 (use (match_dup 6))
15505 (use (match_dup 3))
15507 (clobber (match_dup 0))
15508 (clobber (match_dup 1))
15509 (clobber (match_dup 2))])]
15512 ;; ...and this one handles cmpstr*_1.
15516 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
15518 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15519 (mem:BLK (match_operand 5 "register_operand" "")))
15521 (use (match_operand:SI 3 "immediate_operand" ""))
15524 (clobber (match_operand 0 "register_operand" ""))
15525 (clobber (match_operand 1 "register_operand" ""))
15526 (clobber (match_operand 2 "register_operand" ""))])
15527 (set (match_operand:QI 7 "register_operand" "")
15528 (gtu:QI (reg:CC 17) (const_int 0)))
15529 (set (match_operand:QI 8 "register_operand" "")
15530 (ltu:QI (reg:CC 17) (const_int 0)))
15532 (compare (match_dup 7) (match_dup 8)))
15537 (if_then_else:CC (ne (match_dup 6)
15539 (compare:CC (mem:BLK (match_dup 4))
15540 (mem:BLK (match_dup 5)))
15542 (use (match_dup 3))
15545 (clobber (match_dup 0))
15546 (clobber (match_dup 1))
15547 (clobber (match_dup 2))])]
15552 ;; Conditional move instructions.
15554 (define_expand "movdicc_rex64"
15555 [(set (match_operand:DI 0 "register_operand" "")
15556 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15557 (match_operand:DI 2 "x86_64_general_operand" "")
15558 (match_operand:DI 3 "x86_64_general_operand" "")))]
15560 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15562 (define_insn "x86_movdicc_0_m1_rex64"
15563 [(set (match_operand:DI 0 "register_operand" "=r")
15564 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15567 (clobber (reg:CC 17))]
15570 ; Since we don't have the proper number of operands for an alu insn,
15571 ; fill in all the blanks.
15572 [(set_attr "type" "alu")
15573 (set_attr "memory" "none")
15574 (set_attr "imm_disp" "false")
15575 (set_attr "mode" "DI")
15576 (set_attr "length_immediate" "0")])
15578 (define_insn "*movdicc_c_rex64"
15579 [(set (match_operand:DI 0 "register_operand" "=r,r")
15580 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15581 [(reg 17) (const_int 0)])
15582 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15583 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15584 "TARGET_64BIT && TARGET_CMOVE
15585 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15587 cmov%C1\\t{%2, %0|%0, %2}
15588 cmov%c1\\t{%3, %0|%0, %3}"
15589 [(set_attr "type" "icmov")
15590 (set_attr "mode" "DI")])
15592 (define_expand "movsicc"
15593 [(set (match_operand:SI 0 "register_operand" "")
15594 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15595 (match_operand:SI 2 "general_operand" "")
15596 (match_operand:SI 3 "general_operand" "")))]
15598 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15600 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15601 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15602 ;; So just document what we're doing explicitly.
15604 (define_insn "x86_movsicc_0_m1"
15605 [(set (match_operand:SI 0 "register_operand" "=r")
15606 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15609 (clobber (reg:CC 17))]
15612 ; Since we don't have the proper number of operands for an alu insn,
15613 ; fill in all the blanks.
15614 [(set_attr "type" "alu")
15615 (set_attr "memory" "none")
15616 (set_attr "imm_disp" "false")
15617 (set_attr "mode" "SI")
15618 (set_attr "length_immediate" "0")])
15620 (define_insn "*movsicc_noc"
15621 [(set (match_operand:SI 0 "register_operand" "=r,r")
15622 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15623 [(reg 17) (const_int 0)])
15624 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15625 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15627 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15629 cmov%C1\\t{%2, %0|%0, %2}
15630 cmov%c1\\t{%3, %0|%0, %3}"
15631 [(set_attr "type" "icmov")
15632 (set_attr "mode" "SI")])
15634 (define_expand "movhicc"
15635 [(set (match_operand:HI 0 "register_operand" "")
15636 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15637 (match_operand:HI 2 "nonimmediate_operand" "")
15638 (match_operand:HI 3 "nonimmediate_operand" "")))]
15639 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15640 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15642 (define_insn "*movhicc_noc"
15643 [(set (match_operand:HI 0 "register_operand" "=r,r")
15644 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15645 [(reg 17) (const_int 0)])
15646 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15647 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15649 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15651 cmov%C1\\t{%2, %0|%0, %2}
15652 cmov%c1\\t{%3, %0|%0, %3}"
15653 [(set_attr "type" "icmov")
15654 (set_attr "mode" "HI")])
15656 (define_expand "movsfcc"
15657 [(set (match_operand:SF 0 "register_operand" "")
15658 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15659 (match_operand:SF 2 "register_operand" "")
15660 (match_operand:SF 3 "register_operand" "")))]
15662 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15664 (define_insn "*movsfcc_1"
15665 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15666 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15667 [(reg 17) (const_int 0)])
15668 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15669 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15671 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15673 fcmov%F1\\t{%2, %0|%0, %2}
15674 fcmov%f1\\t{%3, %0|%0, %3}
15675 cmov%C1\\t{%2, %0|%0, %2}
15676 cmov%c1\\t{%3, %0|%0, %3}"
15677 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15678 (set_attr "mode" "SF,SF,SI,SI")])
15680 (define_expand "movdfcc"
15681 [(set (match_operand:DF 0 "register_operand" "")
15682 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15683 (match_operand:DF 2 "register_operand" "")
15684 (match_operand:DF 3 "register_operand" "")))]
15686 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15688 (define_insn "*movdfcc_1"
15689 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15690 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15691 [(reg 17) (const_int 0)])
15692 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15693 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15694 "TARGET_CMOVE && !TARGET_64BIT
15695 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15697 fcmov%F1\\t{%2, %0|%0, %2}
15698 fcmov%f1\\t{%3, %0|%0, %3}
15701 [(set_attr "type" "fcmov,fcmov,multi,multi")
15702 (set_attr "mode" "DF")])
15704 (define_insn "*movdfcc_1_rex64"
15705 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15706 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15707 [(reg 17) (const_int 0)])
15708 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15709 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15710 "TARGET_CMOVE && TARGET_64BIT
15711 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15713 fcmov%F1\\t{%2, %0|%0, %2}
15714 fcmov%f1\\t{%3, %0|%0, %3}
15715 cmov%C1\\t{%2, %0|%0, %2}
15716 cmov%c1\\t{%3, %0|%0, %3}"
15717 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15718 (set_attr "mode" "DF")])
15721 [(set (match_operand:DF 0 "register_operand" "")
15722 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15723 [(match_operand 4 "" "") (const_int 0)])
15724 (match_operand:DF 2 "nonimmediate_operand" "")
15725 (match_operand:DF 3 "nonimmediate_operand" "")))]
15726 "!ANY_FP_REG_P (operands[0]) && reload_completed && !TARGET_64BIT"
15727 [(set (match_dup 2)
15728 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15732 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15735 "split_di (operands+2, 1, operands+5, operands+6);
15736 split_di (operands+3, 1, operands+7, operands+8);
15737 split_di (operands, 1, operands+2, operands+3);")
15739 (define_expand "movxfcc"
15740 [(set (match_operand:XF 0 "register_operand" "")
15741 (if_then_else:XF (match_operand 1 "comparison_operator" "")
15742 (match_operand:XF 2 "register_operand" "")
15743 (match_operand:XF 3 "register_operand" "")))]
15744 "TARGET_CMOVE && !TARGET_64BIT"
15745 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15747 (define_expand "movtfcc"
15748 [(set (match_operand:TF 0 "register_operand" "")
15749 (if_then_else:TF (match_operand 1 "comparison_operator" "")
15750 (match_operand:TF 2 "register_operand" "")
15751 (match_operand:TF 3 "register_operand" "")))]
15753 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15755 (define_insn "*movxfcc_1"
15756 [(set (match_operand:XF 0 "register_operand" "=f,f")
15757 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
15758 [(reg 17) (const_int 0)])
15759 (match_operand:XF 2 "register_operand" "f,0")
15760 (match_operand:XF 3 "register_operand" "0,f")))]
15761 "TARGET_CMOVE && !TARGET_64BIT"
15763 fcmov%F1\\t{%2, %0|%0, %2}
15764 fcmov%f1\\t{%3, %0|%0, %3}"
15765 [(set_attr "type" "fcmov")
15766 (set_attr "mode" "XF")])
15768 (define_insn "*movtfcc_1"
15769 [(set (match_operand:TF 0 "register_operand" "=f,f")
15770 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
15771 [(reg 17) (const_int 0)])
15772 (match_operand:TF 2 "register_operand" "f,0")
15773 (match_operand:TF 3 "register_operand" "0,f")))]
15776 fcmov%F1\\t{%2, %0|%0, %2}
15777 fcmov%f1\\t{%3, %0|%0, %3}"
15778 [(set_attr "type" "fcmov")
15779 (set_attr "mode" "XF")])
15781 (define_expand "minsf3"
15783 (set (match_operand:SF 0 "register_operand" "")
15784 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15785 (match_operand:SF 2 "nonimmediate_operand" ""))
15788 (clobber (reg:CC 17))])]
15792 (define_insn "*minsf"
15793 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15794 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
15795 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
15798 (clobber (reg:CC 17))]
15799 "TARGET_SSE && TARGET_IEEE_FP"
15802 (define_insn "*minsf_nonieee"
15803 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15804 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
15805 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15808 (clobber (reg:CC 17))]
15809 "TARGET_SSE && !TARGET_IEEE_FP"
15813 [(set (match_operand:SF 0 "register_operand" "")
15814 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15815 (match_operand:SF 2 "nonimmediate_operand" ""))
15818 (clobber (reg:CC 17))]
15819 "SSE_REG_P (operands[0]) && reload_completed"
15820 [(set (match_dup 0)
15821 (if_then_else:SF (lt (match_dup 1)
15826 ;; We can't represent the LT test directly. Do this by swapping the operands.
15828 [(set (match_operand:SF 0 "register_operand" "")
15829 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15830 (match_operand:SF 2 "register_operand" ""))
15833 (clobber (reg:CC 17))]
15834 "FP_REG_P (operands[0]) && reload_completed"
15835 [(set (reg:CCFP 17)
15836 (compare:CCFP (match_dup 2)
15839 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
15843 (define_insn "*minsf_sse"
15844 [(set (match_operand:SF 0 "register_operand" "=x")
15845 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
15846 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15849 "TARGET_SSE && reload_completed"
15850 "minss\\t{%2, %0|%0, %2}"
15851 [(set_attr "type" "sse")
15852 (set_attr "mode" "SF")])
15854 (define_expand "mindf3"
15856 (set (match_operand:DF 0 "register_operand" "")
15857 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15858 (match_operand:DF 2 "nonimmediate_operand" ""))
15861 (clobber (reg:CC 17))])]
15865 (define_insn "*mindf"
15866 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15867 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15868 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
15871 (clobber (reg:CC 17))]
15872 "TARGET_SSE2 && TARGET_IEEE_FP"
15875 (define_insn "*mindf_nonieee"
15876 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15877 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
15878 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15881 (clobber (reg:CC 17))]
15882 "TARGET_SSE2 && !TARGET_IEEE_FP"
15886 [(set (match_operand:DF 0 "register_operand" "")
15887 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15888 (match_operand:DF 2 "nonimmediate_operand" ""))
15891 (clobber (reg:CC 17))]
15892 "SSE_REG_P (operands[0]) && reload_completed"
15893 [(set (match_dup 0)
15894 (if_then_else:DF (lt (match_dup 1)
15899 ;; We can't represent the LT test directly. Do this by swapping the operands.
15901 [(set (match_operand:DF 0 "register_operand" "")
15902 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15903 (match_operand:DF 2 "register_operand" ""))
15906 (clobber (reg:CC 17))]
15907 "FP_REG_P (operands[0]) && reload_completed"
15908 [(set (reg:CCFP 17)
15909 (compare:CCFP (match_dup 2)
15912 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
15916 (define_insn "*mindf_sse"
15917 [(set (match_operand:DF 0 "register_operand" "=Y")
15918 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
15919 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15922 "TARGET_SSE2 && reload_completed"
15923 "minsd\\t{%2, %0|%0, %2}"
15924 [(set_attr "type" "sse")
15925 (set_attr "mode" "DF")])
15927 (define_expand "maxsf3"
15929 (set (match_operand:SF 0 "register_operand" "")
15930 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15931 (match_operand:SF 2 "nonimmediate_operand" ""))
15934 (clobber (reg:CC 17))])]
15938 (define_insn "*maxsf"
15939 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15940 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
15941 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x,0"))
15944 (clobber (reg:CC 17))]
15945 "TARGET_SSE && TARGET_IEEE_FP"
15948 (define_insn "*maxsf_nonieee"
15949 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15950 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
15951 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15954 (clobber (reg:CC 17))]
15955 "TARGET_SSE && !TARGET_IEEE_FP"
15959 [(set (match_operand:SF 0 "register_operand" "")
15960 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15961 (match_operand:SF 2 "nonimmediate_operand" ""))
15964 (clobber (reg:CC 17))]
15965 "SSE_REG_P (operands[0]) && reload_completed"
15966 [(set (match_dup 0)
15967 (if_then_else:SF (gt (match_dup 1)
15973 [(set (match_operand:SF 0 "register_operand" "")
15974 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15975 (match_operand:SF 2 "register_operand" ""))
15978 (clobber (reg:CC 17))]
15979 "FP_REG_P (operands[0]) && reload_completed"
15980 [(set (reg:CCFP 17)
15981 (compare:CCFP (match_dup 1)
15984 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
15988 (define_insn "*maxsf_sse"
15989 [(set (match_operand:SF 0 "register_operand" "=x")
15990 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
15991 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15994 "TARGET_SSE && reload_completed"
15995 "maxss\\t{%2, %0|%0, %2}"
15996 [(set_attr "type" "sse")
15997 (set_attr "mode" "SF")])
15999 (define_expand "maxdf3"
16001 (set (match_operand:DF 0 "register_operand" "")
16002 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16003 (match_operand:DF 2 "nonimmediate_operand" ""))
16006 (clobber (reg:CC 17))])]
16010 (define_insn "*maxdf"
16011 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16012 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16013 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y,0"))
16016 (clobber (reg:CC 17))]
16017 "TARGET_SSE2 && TARGET_IEEE_FP"
16020 (define_insn "*maxdf_nonieee"
16021 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16022 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
16023 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
16026 (clobber (reg:CC 17))]
16027 "TARGET_SSE2 && !TARGET_IEEE_FP"
16031 [(set (match_operand:DF 0 "register_operand" "")
16032 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16033 (match_operand:DF 2 "nonimmediate_operand" ""))
16036 (clobber (reg:CC 17))]
16037 "SSE_REG_P (operands[0]) && reload_completed"
16038 [(set (match_dup 0)
16039 (if_then_else:DF (gt (match_dup 1)
16045 [(set (match_operand:DF 0 "register_operand" "")
16046 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16047 (match_operand:DF 2 "register_operand" ""))
16050 (clobber (reg:CC 17))]
16051 "FP_REG_P (operands[0]) && reload_completed"
16052 [(set (reg:CCFP 17)
16053 (compare:CCFP (match_dup 1)
16056 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16060 (define_insn "*maxdf_sse"
16061 [(set (match_operand:DF 0 "register_operand" "=Y")
16062 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16063 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16066 "TARGET_SSE2 && reload_completed"
16067 "maxsd\\t{%2, %0|%0, %2}"
16068 [(set_attr "type" "sse")
16069 (set_attr "mode" "DF")])
16071 ;; Misc patterns (?)
16073 ;; This pattern exists to put a dependancy on all ebp-based memory accesses.
16074 ;; Otherwise there will be nothing to keep
16076 ;; [(set (reg ebp) (reg esp))]
16077 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16078 ;; (clobber (eflags)]
16079 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16081 ;; in proper program order.
16082 (define_expand "pro_epilogue_adjust_stack"
16083 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
16084 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16085 (match_operand:SI 2 "immediate_operand" "i,i")))
16086 (set (match_operand:SI 3 "register_operand" "+r,r")
16088 (clobber (reg:CC 17))])]
16094 emit_insn (gen_pro_epilogue_adjust_stack_rex64 (operands[0], operands[1],
16095 operands[2], operands[3]));
16100 (define_insn "*pro_epilogue_adjust_stack_1"
16101 [(set (match_operand:SI 0 "register_operand" "=r,r")
16102 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16103 (match_operand:SI 2 "immediate_operand" "i,i")))
16104 (set (match_operand:SI 3 "register_operand" "+r,r")
16106 (clobber (reg:CC 17))]
16110 switch (get_attr_type (insn))
16113 return \"mov{l}\\t{%1, %0|%0, %1}\";
16116 if (GET_CODE (operands[2]) == CONST_INT
16117 && (INTVAL (operands[2]) == 128
16118 || (INTVAL (operands[2]) < 0
16119 && INTVAL (operands[2]) != -128)))
16121 operands[2] = GEN_INT (-INTVAL (operands[2]));
16122 return \"sub{l}\\t{%2, %0|%0, %2}\";
16124 return \"add{l}\\t{%2, %0|%0, %2}\";
16127 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16128 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
16134 [(set (attr "type")
16135 (cond [(eq_attr "alternative" "0")
16136 (const_string "alu")
16137 (match_operand:SI 2 "const0_operand" "")
16138 (const_string "imov")
16140 (const_string "lea")))
16141 (set_attr "mode" "SI")])
16143 (define_insn "pro_epilogue_adjust_stack_rex64"
16144 [(set (match_operand:DI 0 "register_operand" "=r,r")
16145 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16146 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16147 (set (match_operand:DI 3 "register_operand" "+r,r")
16149 (clobber (reg:CC 17))]
16153 switch (get_attr_type (insn))
16156 return \"mov{q}\\t{%1, %0|%0, %1}\";
16159 if (GET_CODE (operands[2]) == CONST_INT
16160 && (INTVAL (operands[2]) == 128
16161 || (INTVAL (operands[2]) < 0
16162 && INTVAL (operands[2]) != -128)))
16164 operands[2] = GEN_INT (-INTVAL (operands[2]));
16165 return \"sub{q}\\t{%2, %0|%0, %2}\";
16167 return \"add{q}\\t{%2, %0|%0, %2}\";
16170 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16171 return \"lea{q}\\t{%a2, %0|%0, %a2}\";
16177 [(set (attr "type")
16178 (cond [(eq_attr "alternative" "0")
16179 (const_string "alu")
16180 (match_operand:DI 2 "const0_operand" "")
16181 (const_string "imov")
16183 (const_string "lea")))
16184 (set_attr "mode" "DI")])
16187 ;; Placeholder for the conditional moves. This one is split eighter to SSE
16188 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16189 ;; fact is that compares supported by the cmp??ss instructions are exactly
16190 ;; swapped of those supported by cmove sequence.
16191 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16192 ;; supported by i387 comparisons and we do need to emit two conditional moves
16195 (define_insn "sse_movsfcc"
16196 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16197 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16198 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16199 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16200 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16201 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16202 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16203 (clobber (reg:CC 17))]
16205 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16206 && (!TARGET_IEEE_FP
16207 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16210 (define_insn "sse_movsfcc_eq"
16211 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16212 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16213 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16214 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16215 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16216 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16217 (clobber (reg:CC 17))]
16219 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16222 (define_insn "sse_movdfcc"
16223 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16224 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16225 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16226 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16227 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16228 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16229 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16230 (clobber (reg:CC 17))]
16232 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16233 && (!TARGET_IEEE_FP
16234 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16237 (define_insn "sse_movdfcc_eq"
16238 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16239 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16240 (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16241 (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16242 (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16243 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16244 (clobber (reg:CC 17))]
16246 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16249 ;; For non-sse moves just expand the usual cmove sequence.
16251 [(set (match_operand 0 "register_operand" "")
16252 (if_then_else (match_operator 1 "comparison_operator"
16253 [(match_operand 4 "nonimmediate_operand" "")
16254 (match_operand 5 "register_operand" "")])
16255 (match_operand 2 "nonimmediate_operand" "")
16256 (match_operand 3 "nonimmediate_operand" "")))
16257 (clobber (match_operand 6 "" ""))
16258 (clobber (reg:CC 17))]
16259 "!SSE_REG_P (operands[0]) && reload_completed
16260 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
16264 ix86_compare_op0 = operands[5];
16265 ix86_compare_op1 = operands[4];
16266 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
16267 VOIDmode, operands[5], operands[4]);
16268 ix86_expand_fp_movcc (operands);
16272 ;; Split SSE based conditional move into seqence:
16273 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16274 ;; and op2, op0 - zero op2 if comparison was false
16275 ;; nand op0, op3 - load op3 to op0 if comparison was false
16276 ;; or op2, op0 - get the non-zero one into the result.
16278 [(set (match_operand 0 "register_operand" "")
16279 (if_then_else (match_operator 1 "sse_comparison_operator"
16280 [(match_operand 4 "register_operand" "")
16281 (match_operand 5 "nonimmediate_operand" "")])
16282 (match_operand 2 "register_operand" "")
16283 (match_operand 3 "register_operand" "")))
16284 (clobber (match_operand 6 "" ""))
16285 (clobber (reg:CC 17))]
16286 "SSE_REG_P (operands[0]) && reload_completed"
16287 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
16288 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
16289 (subreg:TI (match_dup 4) 0)))
16290 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
16291 (subreg:TI (match_dup 3) 0)))
16292 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
16293 (subreg:TI (match_dup 7) 0)))]
16296 PUT_MODE (operands[1], GET_MODE (operands[0]));
16297 if (operands_match_p (operands[0], operands[4]))
16298 operands[6] = operands[4], operands[7] = operands[2];
16300 operands[6] = operands[2], operands[7] = operands[4];
16303 ;; Special case of conditional move we can handle effectivly.
16304 ;; Do not brother with the integer/floating point case, since these are
16305 ;; bot considerably slower, unlike in the generic case.
16306 (define_insn "*sse_movsfcc_const0_1"
16307 [(set (match_operand:SF 0 "register_operand" "=x")
16308 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16309 [(match_operand:SF 4 "register_operand" "0")
16310 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16311 (match_operand:SF 2 "register_operand" "x")
16312 (match_operand:SF 3 "const0_operand" "X")))]
16316 (define_insn "*sse_movsfcc_const0_2"
16317 [(set (match_operand:SF 0 "register_operand" "=x")
16318 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16319 [(match_operand:SF 4 "register_operand" "0")
16320 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16321 (match_operand:SF 2 "const0_operand" "x")
16322 (match_operand:SF 3 "register_operand" "X")))]
16326 (define_insn "*sse_movsfcc_const0_3"
16327 [(set (match_operand:SF 0 "register_operand" "=x")
16328 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16329 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16330 (match_operand:SF 5 "register_operand" "0")])
16331 (match_operand:SF 2 "register_operand" "x")
16332 (match_operand:SF 3 "const0_operand" "X")))]
16336 (define_insn "*sse_movsfcc_const0_4"
16337 [(set (match_operand:SF 0 "register_operand" "=x")
16338 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16339 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16340 (match_operand:SF 5 "register_operand" "0")])
16341 (match_operand:SF 2 "const0_operand" "x")
16342 (match_operand:SF 3 "register_operand" "X")))]
16346 (define_insn "*sse_movdfcc_const0_1"
16347 [(set (match_operand:SF 0 "register_operand" "=x")
16348 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16349 [(match_operand:SF 4 "register_operand" "0")
16350 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16351 (match_operand:SF 2 "register_operand" "x")
16352 (match_operand:SF 3 "const0_operand" "X")))]
16356 (define_insn "*sse_movdfcc_const0_2"
16357 [(set (match_operand:SF 0 "register_operand" "=x")
16358 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16359 [(match_operand:SF 4 "register_operand" "0")
16360 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16361 (match_operand:SF 2 "const0_operand" "x")
16362 (match_operand:SF 3 "register_operand" "X")))]
16366 (define_insn "*sse_movdfcc_const0_3"
16367 [(set (match_operand:SF 0 "register_operand" "=x")
16368 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16369 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16370 (match_operand:SF 5 "register_operand" "0")])
16371 (match_operand:SF 2 "register_operand" "x")
16372 (match_operand:SF 3 "const0_operand" "X")))]
16376 (define_insn "*sse_movdfcc_const0_4"
16377 [(set (match_operand:SF 0 "register_operand" "=x")
16378 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16379 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16380 (match_operand:SF 5 "register_operand" "0")])
16381 (match_operand:SF 2 "const0_operand" "x")
16382 (match_operand:SF 3 "register_operand" "X")))]
16387 [(set (match_operand 0 "register_operand" "")
16388 (if_then_else (match_operator 1 "comparison_operator"
16389 [(match_operand 4 "register_operand" "")
16390 (match_operand 5 "nonimmediate_operand" "")])
16391 (match_operand 2 "nonmemory_operand" "")
16392 (match_operand 3 "nonmemory_operand" "")))]
16393 "SSE_REG_P (operands[0]) && reload_completed
16394 && (const0_operand (operands[2], GET_MODE (operands[0]))
16395 || const0_operand (operands[3], GET_MODE (operands[0])))"
16396 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16397 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16398 (subreg:TI (match_dup 7) 0)))]
16401 PUT_MODE (operands[1], GET_MODE (operands[0]));
16402 if (!sse_comparison_operator (operands[1], VOIDmode))
16404 rtx tmp = operands[5];
16405 operands[5] = operands[4];
16407 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16409 if (const0_operand (operands[2], GET_MODE (operands[0])))
16411 operands[7] = operands[3];
16412 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16417 operands[7] = operands[2];
16418 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
16422 (define_expand "allocate_stack_worker"
16423 [(match_operand:SI 0 "register_operand" "")]
16424 "TARGET_STACK_PROBE"
16428 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16430 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16434 (define_insn "allocate_stack_worker_1"
16435 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
16436 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16437 (clobber (match_dup 0))
16438 (clobber (reg:CC 17))]
16439 "TARGET_STACK_PROBE && !TARGET_64BIT"
16441 [(set_attr "type" "multi")
16442 (set_attr "length" "5")])
16444 (define_insn "allocate_stack_worker_rex64"
16445 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
16446 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16447 (clobber (match_dup 0))
16448 (clobber (reg:CC 17))]
16449 "TARGET_STACK_PROBE && TARGET_64BIT"
16451 [(set_attr "type" "multi")
16452 (set_attr "length" "5")])
16454 (define_expand "allocate_stack"
16455 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
16456 (minus:SI (reg:SI 7)
16457 (match_operand:SI 1 "general_operand" "")))
16458 (clobber (reg:CC 17))])
16459 (parallel [(set (reg:SI 7)
16460 (minus:SI (reg:SI 7) (match_dup 1)))
16461 (clobber (reg:CC 17))])]
16462 "TARGET_STACK_PROBE"
16465 #ifdef CHECK_STACK_LIMIT
16466 if (GET_CODE (operands[1]) == CONST_INT
16467 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16468 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
16472 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
16475 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16479 (define_expand "builtin_setjmp_receiver"
16480 [(label_ref (match_operand 0 "" ""))]
16481 "flag_pic && !TARGET_64BIT"
16484 load_pic_register ();
16488 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16491 [(set (match_operand 0 "register_operand" "")
16492 (match_operator 3 "promotable_binary_operator"
16493 [(match_operand 1 "register_operand" "")
16494 (match_operand 2 "aligned_operand" "")]))
16495 (clobber (reg:CC 17))]
16496 "! TARGET_PARTIAL_REG_STALL && reload_completed
16497 && ((GET_MODE (operands[0]) == HImode
16498 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
16499 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16500 || (GET_MODE (operands[0]) == QImode
16501 && (TARGET_PROMOTE_QImode || optimize_size)))"
16502 [(parallel [(set (match_dup 0)
16503 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16504 (clobber (reg:CC 17))])]
16505 "operands[0] = gen_lowpart (SImode, operands[0]);
16506 operands[1] = gen_lowpart (SImode, operands[1]);
16507 if (GET_CODE (operands[3]) != ASHIFT)
16508 operands[2] = gen_lowpart (SImode, operands[2]);
16509 PUT_MODE (operands[3], SImode);")
16513 (compare (and (match_operand 1 "aligned_operand" "")
16514 (match_operand 2 "const_int_operand" ""))
16516 (set (match_operand 0 "register_operand" "")
16517 (and (match_dup 1) (match_dup 2)))]
16518 "! TARGET_PARTIAL_REG_STALL && reload_completed
16519 && ix86_match_ccmode (insn, CCNOmode)
16520 && (GET_MODE (operands[0]) == HImode
16521 || (GET_MODE (operands[0]) == QImode
16522 && (TARGET_PROMOTE_QImode || optimize_size)))"
16523 [(parallel [(set (reg:CCNO 17)
16524 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16527 (and:SI (match_dup 1) (match_dup 2)))])]
16529 = GEN_INT (trunc_int_for_mode (INTVAL (operands[2])
16530 & GET_MODE_MASK (GET_MODE (operands[0])),
16532 operands[0] = gen_lowpart (SImode, operands[0]);
16533 operands[1] = gen_lowpart (SImode, operands[1]);")
16537 (compare (and (match_operand 0 "aligned_operand" "")
16538 (match_operand 1 "const_int_operand" ""))
16540 "! TARGET_PARTIAL_REG_STALL && reload_completed
16541 && ix86_match_ccmode (insn, CCNOmode)
16542 && (GET_MODE (operands[0]) == HImode
16543 || (GET_MODE (operands[0]) == QImode
16544 && (TARGET_PROMOTE_QImode || optimize_size)))"
16545 [(set (reg:CCNO 17)
16546 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16549 = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
16550 & GET_MODE_MASK (GET_MODE (operands[0])),
16552 operands[0] = gen_lowpart (SImode, operands[0]);")
16555 [(set (match_operand 0 "register_operand" "")
16556 (neg (match_operand 1 "register_operand" "")))
16557 (clobber (reg:CC 17))]
16558 "! TARGET_PARTIAL_REG_STALL && reload_completed
16559 && (GET_MODE (operands[0]) == HImode
16560 || (GET_MODE (operands[0]) == QImode
16561 && (TARGET_PROMOTE_QImode || optimize_size)))"
16562 [(parallel [(set (match_dup 0)
16563 (neg:SI (match_dup 1)))
16564 (clobber (reg:CC 17))])]
16565 "operands[0] = gen_lowpart (SImode, operands[0]);
16566 operands[1] = gen_lowpart (SImode, operands[1]);")
16569 [(set (match_operand 0 "register_operand" "")
16570 (not (match_operand 1 "register_operand" "")))]
16571 "! TARGET_PARTIAL_REG_STALL && reload_completed
16572 && (GET_MODE (operands[0]) == HImode
16573 || (GET_MODE (operands[0]) == QImode
16574 && (TARGET_PROMOTE_QImode || optimize_size)))"
16575 [(set (match_dup 0)
16576 (not:SI (match_dup 1)))]
16577 "operands[0] = gen_lowpart (SImode, operands[0]);
16578 operands[1] = gen_lowpart (SImode, operands[1]);")
16581 [(set (match_operand 0 "register_operand" "")
16582 (if_then_else (match_operator 1 "comparison_operator"
16583 [(reg 17) (const_int 0)])
16584 (match_operand 2 "register_operand" "")
16585 (match_operand 3 "register_operand" "")))]
16586 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16587 && (GET_MODE (operands[0]) == HImode
16588 || (GET_MODE (operands[0]) == QImode
16589 && (TARGET_PROMOTE_QImode || optimize_size)))"
16590 [(set (match_dup 0)
16591 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16592 "operands[0] = gen_lowpart (SImode, operands[0]);
16593 operands[2] = gen_lowpart (SImode, operands[2]);
16594 operands[3] = gen_lowpart (SImode, operands[3]);")
16597 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16598 ;; transform a complex memory operation into two memory to register operations.
16600 ;; Don't push memory operands
16602 [(set (match_operand:SI 0 "push_operand" "")
16603 (match_operand:SI 1 "memory_operand" ""))
16604 (match_scratch:SI 2 "r")]
16605 "! optimize_size && ! TARGET_PUSH_MEMORY"
16606 [(set (match_dup 2) (match_dup 1))
16607 (set (match_dup 0) (match_dup 2))]
16611 [(set (match_operand:DI 0 "push_operand" "")
16612 (match_operand:DI 1 "memory_operand" ""))
16613 (match_scratch:DI 2 "r")]
16614 "! optimize_size && ! TARGET_PUSH_MEMORY"
16615 [(set (match_dup 2) (match_dup 1))
16616 (set (match_dup 0) (match_dup 2))]
16619 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16622 [(set (match_operand:SF 0 "push_operand" "")
16623 (match_operand:SF 1 "memory_operand" ""))
16624 (match_scratch:SF 2 "r")]
16625 "! optimize_size && ! TARGET_PUSH_MEMORY"
16626 [(set (match_dup 2) (match_dup 1))
16627 (set (match_dup 0) (match_dup 2))]
16631 [(set (match_operand:HI 0 "push_operand" "")
16632 (match_operand:HI 1 "memory_operand" ""))
16633 (match_scratch:HI 2 "r")]
16634 "! optimize_size && ! TARGET_PUSH_MEMORY"
16635 [(set (match_dup 2) (match_dup 1))
16636 (set (match_dup 0) (match_dup 2))]
16640 [(set (match_operand:QI 0 "push_operand" "")
16641 (match_operand:QI 1 "memory_operand" ""))
16642 (match_scratch:QI 2 "q")]
16643 "! optimize_size && ! TARGET_PUSH_MEMORY"
16644 [(set (match_dup 2) (match_dup 1))
16645 (set (match_dup 0) (match_dup 2))]
16648 ;; Don't move an immediate directly to memory when the instruction
16651 [(match_scratch:SI 1 "r")
16652 (set (match_operand:SI 0 "memory_operand" "")
16655 && ! TARGET_USE_MOV0
16656 && TARGET_SPLIT_LONG_MOVES
16657 && get_attr_length (insn) >= ix86_cost->large_insn
16658 && peep2_regno_dead_p (0, FLAGS_REG)"
16659 [(parallel [(set (match_dup 1) (const_int 0))
16660 (clobber (reg:CC 17))])
16661 (set (match_dup 0) (match_dup 1))]
16665 [(match_scratch:HI 1 "r")
16666 (set (match_operand:HI 0 "memory_operand" "")
16669 && ! TARGET_USE_MOV0
16670 && TARGET_SPLIT_LONG_MOVES
16671 && get_attr_length (insn) >= ix86_cost->large_insn
16672 && peep2_regno_dead_p (0, FLAGS_REG)"
16673 [(parallel [(set (match_dup 2) (const_int 0))
16674 (clobber (reg:CC 17))])
16675 (set (match_dup 0) (match_dup 1))]
16676 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16679 [(match_scratch:QI 1 "q")
16680 (set (match_operand:QI 0 "memory_operand" "")
16683 && ! TARGET_USE_MOV0
16684 && TARGET_SPLIT_LONG_MOVES
16685 && get_attr_length (insn) >= ix86_cost->large_insn
16686 && peep2_regno_dead_p (0, FLAGS_REG)"
16687 [(parallel [(set (match_dup 2) (const_int 0))
16688 (clobber (reg:CC 17))])
16689 (set (match_dup 0) (match_dup 1))]
16690 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16693 [(match_scratch:SI 2 "r")
16694 (set (match_operand:SI 0 "memory_operand" "")
16695 (match_operand:SI 1 "immediate_operand" ""))]
16697 && get_attr_length (insn) >= ix86_cost->large_insn
16698 && TARGET_SPLIT_LONG_MOVES"
16699 [(set (match_dup 2) (match_dup 1))
16700 (set (match_dup 0) (match_dup 2))]
16704 [(match_scratch:HI 2 "r")
16705 (set (match_operand:HI 0 "memory_operand" "")
16706 (match_operand:HI 1 "immediate_operand" ""))]
16707 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16708 && TARGET_SPLIT_LONG_MOVES"
16709 [(set (match_dup 2) (match_dup 1))
16710 (set (match_dup 0) (match_dup 2))]
16714 [(match_scratch:QI 2 "q")
16715 (set (match_operand:QI 0 "memory_operand" "")
16716 (match_operand:QI 1 "immediate_operand" ""))]
16717 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16718 && TARGET_SPLIT_LONG_MOVES"
16719 [(set (match_dup 2) (match_dup 1))
16720 (set (match_dup 0) (match_dup 2))]
16723 ;; Don't compare memory with zero, load and use a test instead.
16726 (compare (match_operand:SI 0 "memory_operand" "")
16728 (match_scratch:SI 3 "r")]
16729 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
16730 [(set (match_dup 3) (match_dup 0))
16731 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
16734 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
16735 ;; Don't split NOTs with a displacement operand, because resulting XOR
16736 ;; will not be pariable anyway.
16738 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
16739 ;; represented using a modRM byte. The XOR replacement is long decoded,
16740 ;; so this split helps here as well.
16742 ;; Note: Can't do this as a regular split because we can't get proper
16743 ;; lifetime information then.
16746 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
16747 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
16749 && peep2_regno_dead_p (0, FLAGS_REG)
16750 && ((TARGET_PENTIUM
16751 && (GET_CODE (operands[0]) != MEM
16752 || !memory_displacement_operand (operands[0], SImode)))
16753 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
16754 [(parallel [(set (match_dup 0)
16755 (xor:SI (match_dup 1) (const_int -1)))
16756 (clobber (reg:CC 17))])]
16760 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
16761 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
16763 && peep2_regno_dead_p (0, FLAGS_REG)
16764 && ((TARGET_PENTIUM
16765 && (GET_CODE (operands[0]) != MEM
16766 || !memory_displacement_operand (operands[0], HImode)))
16767 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
16768 [(parallel [(set (match_dup 0)
16769 (xor:HI (match_dup 1) (const_int -1)))
16770 (clobber (reg:CC 17))])]
16774 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
16775 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
16777 && peep2_regno_dead_p (0, FLAGS_REG)
16778 && ((TARGET_PENTIUM
16779 && (GET_CODE (operands[0]) != MEM
16780 || !memory_displacement_operand (operands[0], QImode)))
16781 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
16782 [(parallel [(set (match_dup 0)
16783 (xor:QI (match_dup 1) (const_int -1)))
16784 (clobber (reg:CC 17))])]
16787 ;; Non pairable "test imm, reg" instructions can be translated to
16788 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
16789 ;; byte opcode instead of two, have a short form for byte operands),
16790 ;; so do it for other CPUs as well. Given that the value was dead,
16791 ;; this should not create any new dependancies. Pass on the sub-word
16792 ;; versions if we're concerned about partial register stalls.
16796 (compare (and:SI (match_operand:SI 0 "register_operand" "")
16797 (match_operand:SI 1 "immediate_operand" ""))
16799 "ix86_match_ccmode (insn, CCNOmode)
16800 && (true_regnum (operands[0]) != 0
16801 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
16802 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16804 [(set (reg:CCNO 17)
16805 (compare:CCNO (and:SI (match_dup 0)
16809 (and:SI (match_dup 0) (match_dup 1)))])]
16812 ;; We don't need to handle HImode case, because it will be promoted to SImode
16813 ;; on ! TARGET_PARTIAL_REG_STALL
16817 (compare (and:QI (match_operand:QI 0 "register_operand" "")
16818 (match_operand:QI 1 "immediate_operand" ""))
16820 "! TARGET_PARTIAL_REG_STALL
16821 && ix86_match_ccmode (insn, CCNOmode)
16822 && true_regnum (operands[0]) != 0
16823 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16825 [(set (reg:CCNO 17)
16826 (compare:CCNO (and:QI (match_dup 0)
16830 (and:QI (match_dup 0) (match_dup 1)))])]
16838 (match_operand 0 "ext_register_operand" "q")
16841 (match_operand 1 "const_int_operand" "n"))
16843 "! TARGET_PARTIAL_REG_STALL
16844 && ix86_match_ccmode (insn, CCNOmode)
16845 && true_regnum (operands[0]) != 0
16846 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16847 [(parallel [(set (reg:CCNO 17)
16856 (set (zero_extract:SI (match_dup 0)
16867 ;; Don't do logical operations with memory inputs.
16869 [(match_scratch:SI 2 "r")
16870 (parallel [(set (match_operand:SI 0 "register_operand" "")
16871 (match_operator:SI 3 "arith_or_logical_operator"
16873 (match_operand:SI 1 "memory_operand" "")]))
16874 (clobber (reg:CC 17))])]
16875 "! optimize_size && ! TARGET_READ_MODIFY"
16876 [(set (match_dup 2) (match_dup 1))
16877 (parallel [(set (match_dup 0)
16878 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
16879 (clobber (reg:CC 17))])]
16883 [(match_scratch:SI 2 "r")
16884 (parallel [(set (match_operand:SI 0 "register_operand" "")
16885 (match_operator:SI 3 "arith_or_logical_operator"
16886 [(match_operand:SI 1 "memory_operand" "")
16888 (clobber (reg:CC 17))])]
16889 "! optimize_size && ! TARGET_READ_MODIFY"
16890 [(set (match_dup 2) (match_dup 1))
16891 (parallel [(set (match_dup 0)
16892 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
16893 (clobber (reg:CC 17))])]
16896 ; Don't do logical operations with memory outputs
16898 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
16899 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
16900 ; the same decoder scheduling characteristics as the original.
16903 [(match_scratch:SI 2 "r")
16904 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16905 (match_operator:SI 3 "arith_or_logical_operator"
16907 (match_operand:SI 1 "nonmemory_operand" "")]))
16908 (clobber (reg:CC 17))])]
16909 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16910 [(set (match_dup 2) (match_dup 0))
16911 (parallel [(set (match_dup 2)
16912 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
16913 (clobber (reg:CC 17))])
16914 (set (match_dup 0) (match_dup 2))]
16918 [(match_scratch:SI 2 "r")
16919 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16920 (match_operator:SI 3 "arith_or_logical_operator"
16921 [(match_operand:SI 1 "nonmemory_operand" "")
16923 (clobber (reg:CC 17))])]
16924 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16925 [(set (match_dup 2) (match_dup 0))
16926 (parallel [(set (match_dup 2)
16927 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16928 (clobber (reg:CC 17))])
16929 (set (match_dup 0) (match_dup 2))]
16932 ;; Attempt to always use XOR for zeroing registers.
16934 [(set (match_operand 0 "register_operand" "")
16936 "(GET_MODE (operands[0]) == QImode
16937 || GET_MODE (operands[0]) == HImode
16938 || GET_MODE (operands[0]) == SImode
16939 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16940 && (! TARGET_USE_MOV0 || optimize_size)
16941 && peep2_regno_dead_p (0, FLAGS_REG)"
16942 [(parallel [(set (match_dup 0) (const_int 0))
16943 (clobber (reg:CC 17))])]
16944 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16945 true_regnum (operands[0]));")
16948 [(set (strict_low_part (match_operand 0 "register_operand" ""))
16950 "(GET_MODE (operands[0]) == QImode
16951 || GET_MODE (operands[0]) == HImode)
16952 && (! TARGET_USE_MOV0 || optimize_size)
16953 && peep2_regno_dead_p (0, FLAGS_REG)"
16954 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
16955 (clobber (reg:CC 17))])])
16957 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
16959 [(set (match_operand 0 "register_operand" "")
16961 "(GET_MODE (operands[0]) == HImode
16962 || GET_MODE (operands[0]) == SImode
16963 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16964 && (optimize_size || TARGET_PENTIUM)
16965 && peep2_regno_dead_p (0, FLAGS_REG)"
16966 [(parallel [(set (match_dup 0) (const_int -1))
16967 (clobber (reg:CC 17))])]
16968 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16969 true_regnum (operands[0]));")
16971 ;; Attempt to convert simple leas to adds. These can be created by
16974 [(set (match_operand:SI 0 "register_operand" "")
16975 (plus:SI (match_dup 0)
16976 (match_operand:SI 1 "nonmemory_operand" "")))]
16977 "peep2_regno_dead_p (0, FLAGS_REG)"
16978 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
16979 (clobber (reg:CC 17))])]
16983 [(set (match_operand:SI 0 "register_operand" "")
16984 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
16985 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
16986 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
16987 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
16988 (clobber (reg:CC 17))])]
16989 "operands[2] = gen_lowpart (SImode, operands[2]);")
16992 [(set (match_operand:DI 0 "register_operand" "")
16993 (plus:DI (match_dup 0)
16994 (match_operand:DI 1 "x86_64_general_operand" "")))]
16995 "peep2_regno_dead_p (0, FLAGS_REG)"
16996 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
16997 (clobber (reg:CC 17))])]
17001 [(set (match_operand:SI 0 "register_operand" "")
17002 (mult:SI (match_dup 0)
17003 (match_operand:SI 1 "const_int_operand" "")))]
17004 "exact_log2 (INTVAL (operands[1])) >= 0
17005 && peep2_regno_dead_p (0, FLAGS_REG)"
17006 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17007 (clobber (reg:CC 17))])]
17008 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17011 [(set (match_operand:DI 0 "register_operand" "")
17012 (mult:DI (match_dup 0)
17013 (match_operand:DI 1 "const_int_operand" "")))]
17014 "exact_log2 (INTVAL (operands[1])) >= 0
17015 && peep2_regno_dead_p (0, FLAGS_REG)"
17016 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17017 (clobber (reg:CC 17))])]
17018 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17021 [(set (match_operand:SI 0 "register_operand" "")
17022 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17023 (match_operand:DI 2 "const_int_operand" "")) 0))]
17024 "exact_log2 (INTVAL (operands[1])) >= 0
17025 && REGNO (operands[0]) == REGNO (operands[1])
17026 && peep2_regno_dead_p (0, FLAGS_REG)"
17027 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17028 (clobber (reg:CC 17))])]
17029 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17031 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17032 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17033 ;; many CPUs it is also faster, since special hardware to avoid esp
17034 ;; dependancies is present.
17036 ;; While some of these converisons may be done using splitters, we use peepholes
17037 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17039 ;; Convert prologue esp substractions to push.
17040 ;; We need register to push. In order to keep verify_flow_info happy we have
17042 ;; - use scratch and clobber it in order to avoid dependencies
17043 ;; - use already live register
17044 ;; We can't use the second way right now, since there is no reliable way how to
17045 ;; verify that given register is live. First choice will also most likely in
17046 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17047 ;; call clobbered registers are dead. We may want to use base pointer as an
17048 ;; alternative when no register is available later.
17051 [(match_scratch:SI 0 "r")
17052 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17053 (set (reg:SI 6) (reg:SI 6))
17054 (clobber (reg:CC 17))])]
17055 "optimize_size || !TARGET_SUB_ESP_4"
17056 [(clobber (match_dup 0))
17057 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17058 (set (reg:SI 6) (reg:SI 6))])])
17061 [(match_scratch:SI 0 "r")
17062 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17063 (set (reg:SI 6) (reg:SI 6))
17064 (clobber (reg:CC 17))])]
17065 "optimize_size || !TARGET_SUB_ESP_8"
17066 [(clobber (match_dup 0))
17067 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17068 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17069 (set (reg:SI 6) (reg:SI 6))])])
17071 ;; Convert esp substractions to push.
17073 [(match_scratch:SI 0 "r")
17074 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17075 (clobber (reg:CC 17))])]
17076 "optimize_size || !TARGET_SUB_ESP_4"
17077 [(clobber (match_dup 0))
17078 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17081 [(match_scratch:SI 0 "r")
17082 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17083 (clobber (reg:CC 17))])]
17084 "optimize_size || !TARGET_SUB_ESP_8"
17085 [(clobber (match_dup 0))
17086 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17087 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17089 ;; Convert epilogue deallocator to pop.
17091 [(match_scratch:SI 0 "r")
17092 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17093 (set (reg:SI 6) (reg:SI 6))
17094 (clobber (reg:CC 17))])]
17095 "optimize_size || !TARGET_ADD_ESP_4"
17096 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17097 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17098 (set (reg:SI 6) (reg:SI 6))])]
17101 ;; Two pops case is tricky, since pop causes dependency on destination register.
17102 ;; We use two registers if available.
17104 [(match_scratch:SI 0 "r")
17105 (match_scratch:SI 1 "r")
17106 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17107 (set (reg:SI 6) (reg:SI 6))
17108 (clobber (reg:CC 17))])]
17109 "optimize_size || !TARGET_ADD_ESP_8"
17110 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17111 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17112 (set (reg:SI 6) (reg:SI 6))])
17113 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17114 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17118 [(match_scratch:SI 0 "r")
17119 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17120 (set (reg:SI 6) (reg:SI 6))
17121 (clobber (reg:CC 17))])]
17123 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17124 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17125 (set (reg:SI 6) (reg:SI 6))])
17126 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17127 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17130 ;; Convert esp additions to pop.
17132 [(match_scratch:SI 0 "r")
17133 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17134 (clobber (reg:CC 17))])]
17136 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17137 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17140 ;; Two pops case is tricky, since pop causes dependency on destination register.
17141 ;; We use two registers if available.
17143 [(match_scratch:SI 0 "r")
17144 (match_scratch:SI 1 "r")
17145 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17146 (clobber (reg:CC 17))])]
17148 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17149 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17150 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17151 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17155 [(match_scratch:SI 0 "r")
17156 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17157 (clobber (reg:CC 17))])]
17159 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17160 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17161 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17162 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17165 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17166 ;; required and register dies.
17169 (compare (match_operand:SI 0 "register_operand" "")
17170 (match_operand:SI 1 "incdec_operand" "")))]
17171 "ix86_match_ccmode (insn, CCGCmode)
17172 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17173 [(parallel [(set (reg:CCGC 17)
17174 (compare:CCGC (match_dup 0)
17176 (clobber (match_dup 0))])]
17181 (compare (match_operand:HI 0 "register_operand" "")
17182 (match_operand:HI 1 "incdec_operand" "")))]
17183 "ix86_match_ccmode (insn, CCGCmode)
17184 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17185 [(parallel [(set (reg:CCGC 17)
17186 (compare:CCGC (match_dup 0)
17188 (clobber (match_dup 0))])]
17193 (compare (match_operand:QI 0 "register_operand" "")
17194 (match_operand:QI 1 "incdec_operand" "")))]
17195 "ix86_match_ccmode (insn, CCGCmode)
17196 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17197 [(parallel [(set (reg:CCGC 17)
17198 (compare:CCGC (match_dup 0)
17200 (clobber (match_dup 0))])]
17203 ;; Convert compares with 128 to shorter add -128
17206 (compare (match_operand:SI 0 "register_operand" "")
17208 "ix86_match_ccmode (insn, CCGCmode)
17209 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17210 [(parallel [(set (reg:CCGC 17)
17211 (compare:CCGC (match_dup 0)
17213 (clobber (match_dup 0))])]
17218 (compare (match_operand:HI 0 "register_operand" "")
17220 "ix86_match_ccmode (insn, CCGCmode)
17221 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17222 [(parallel [(set (reg:CCGC 17)
17223 (compare:CCGC (match_dup 0)
17225 (clobber (match_dup 0))])]
17229 [(match_scratch:DI 0 "r")
17230 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17231 (set (reg:DI 6) (reg:DI 6))
17232 (clobber (reg:CC 17))])]
17233 "optimize_size || !TARGET_SUB_ESP_4"
17234 [(clobber (match_dup 0))
17235 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17236 (set (reg:DI 6) (reg:DI 6))])])
17239 [(match_scratch:DI 0 "r")
17240 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17241 (set (reg:DI 6) (reg:DI 6))
17242 (clobber (reg:CC 17))])]
17243 "optimize_size || !TARGET_SUB_ESP_8"
17244 [(clobber (match_dup 0))
17245 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17246 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17247 (set (reg:DI 6) (reg:DI 6))])])
17249 ;; Convert esp substractions to push.
17251 [(match_scratch:DI 0 "r")
17252 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17253 (clobber (reg:CC 17))])]
17254 "optimize_size || !TARGET_SUB_ESP_4"
17255 [(clobber (match_dup 0))
17256 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17259 [(match_scratch:DI 0 "r")
17260 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17261 (clobber (reg:CC 17))])]
17262 "optimize_size || !TARGET_SUB_ESP_8"
17263 [(clobber (match_dup 0))
17264 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17265 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17267 ;; Convert epilogue deallocator to pop.
17269 [(match_scratch:DI 0 "r")
17270 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17271 (set (reg:DI 6) (reg:DI 6))
17272 (clobber (reg:CC 17))])]
17273 "optimize_size || !TARGET_ADD_ESP_4"
17274 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17275 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17276 (set (reg:DI 6) (reg:DI 6))])]
17279 ;; Two pops case is tricky, since pop causes dependency on destination register.
17280 ;; We use two registers if available.
17282 [(match_scratch:DI 0 "r")
17283 (match_scratch:DI 1 "r")
17284 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17285 (set (reg:DI 6) (reg:DI 6))
17286 (clobber (reg:CC 17))])]
17287 "optimize_size || !TARGET_ADD_ESP_8"
17288 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17289 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17290 (set (reg:DI 6) (reg:DI 6))])
17291 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17292 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17296 [(match_scratch:DI 0 "r")
17297 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17298 (set (reg:DI 6) (reg:DI 6))
17299 (clobber (reg:CC 17))])]
17301 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17302 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17303 (set (reg:DI 6) (reg:DI 6))])
17304 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17305 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17308 ;; Convert esp additions to pop.
17310 [(match_scratch:DI 0 "r")
17311 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17312 (clobber (reg:CC 17))])]
17314 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17315 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17318 ;; Two pops case is tricky, since pop causes dependency on destination register.
17319 ;; We use two registers if available.
17321 [(match_scratch:DI 0 "r")
17322 (match_scratch:DI 1 "r")
17323 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17324 (clobber (reg:CC 17))])]
17326 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17327 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17328 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17329 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17333 [(match_scratch:DI 0 "r")
17334 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17335 (clobber (reg:CC 17))])]
17337 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17338 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17339 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17340 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17343 ;; Call-value patterns last so that the wildcard operand does not
17344 ;; disrupt insn-recog's switch tables.
17346 (define_insn "*call_value_pop_0"
17347 [(set (match_operand 0 "" "")
17348 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17349 (match_operand:SI 2 "" "")))
17350 (set (reg:SI 7) (plus:SI (reg:SI 7)
17351 (match_operand:SI 3 "immediate_operand" "")))]
17355 if (SIBLING_CALL_P (insn))
17356 return \"jmp\\t%P1\";
17358 return \"call\\t%P1\";
17360 [(set_attr "type" "callv")])
17362 (define_insn "*call_value_pop_1"
17363 [(set (match_operand 0 "" "")
17364 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17365 (match_operand:SI 2 "" "")))
17366 (set (reg:SI 7) (plus:SI (reg:SI 7)
17367 (match_operand:SI 3 "immediate_operand" "i")))]
17371 if (constant_call_address_operand (operands[1], QImode))
17373 if (SIBLING_CALL_P (insn))
17374 return \"jmp\\t%P1\";
17376 return \"call\\t%P1\";
17378 if (SIBLING_CALL_P (insn))
17379 return \"jmp\\t%A1\";
17381 return \"call\\t%A1\";
17383 [(set_attr "type" "callv")])
17385 (define_insn "*call_value_0"
17386 [(set (match_operand 0 "" "")
17387 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17388 (match_operand:SI 2 "" "")))]
17392 if (SIBLING_CALL_P (insn))
17393 return \"jmp\\t%P1\";
17395 return \"call\\t%P1\";
17397 [(set_attr "type" "callv")])
17399 (define_insn "*call_value_0_rex64"
17400 [(set (match_operand 0 "" "")
17401 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
17402 (match_operand:DI 2 "const_int_operand" "")))]
17406 if (SIBLING_CALL_P (insn))
17407 return \"jmp\\t%P1\";
17409 return \"call\\t%P1\";
17411 [(set_attr "type" "callv")])
17413 (define_insn "*call_value_1"
17414 [(set (match_operand 0 "" "")
17415 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17416 (match_operand:SI 2 "" "")))]
17420 if (constant_call_address_operand (operands[1], QImode))
17422 if (SIBLING_CALL_P (insn))
17423 return \"jmp\\t%P1\";
17425 return \"call\\t%P1\";
17427 if (SIBLING_CALL_P (insn))
17428 return \"jmp\\t%*%1\";
17430 return \"call\\t%*%1\";
17432 [(set_attr "type" "callv")])
17434 (define_insn "*call_value_1_rex64"
17435 [(set (match_operand 0 "" "")
17436 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
17437 (match_operand:DI 2 "" "")))]
17441 if (constant_call_address_operand (operands[1], QImode))
17443 if (SIBLING_CALL_P (insn))
17444 return \"jmp\\t%P1\";
17446 return \"call\\t%P1\";
17448 if (SIBLING_CALL_P (insn))
17449 return \"jmp\\t%A1\";
17451 return \"call\\t%A1\";
17453 [(set_attr "type" "callv")])
17455 (define_insn "trap"
17456 [(trap_if (const_int 1) (const_int 5))]
17460 ;;; ix86 doesn't have conditional trap instructions, but we fake them
17461 ;;; for the sake of bounds checking. By emitting bounds checks as
17462 ;;; conditional traps rather than as conditional jumps around
17463 ;;; unconditional traps we avoid introducing spurious basic-block
17464 ;;; boundaries and facilitate elimination of redundant checks. In
17465 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
17468 ;;; FIXME: Static branch prediction rules for ix86 are such that
17469 ;;; forward conditional branches predict as untaken. As implemented
17470 ;;; below, pseudo conditional traps violate that rule. We should use
17471 ;;; .pushsection/.popsection to place all of the `int 5's in a special
17472 ;;; section loaded at the end of the text segment and branch forward
17473 ;;; there on bounds-failure, and then jump back immediately (in case
17474 ;;; the system chooses to ignore bounds violations, or to report
17475 ;;; violations and continue execution).
17477 (define_expand "conditional_trap"
17478 [(trap_if (match_operator 0 "comparison_operator"
17479 [(match_dup 2) (const_int 0)])
17480 (match_operand 1 "const_int_operand" ""))]
17484 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
17485 ix86_expand_compare (GET_CODE (operands[0]),
17492 [(trap_if (match_operator 0 "comparison_operator"
17493 [(reg 17) (const_int 0)])
17494 (match_operand 1 "const_int_operand" ""))]
17498 operands[2] = gen_label_rtx ();
17499 output_asm_insn (\"j%c0\\t%l2\; int\\t%1\", operands);
17500 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
17501 CODE_LABEL_NUMBER (operands[2]));
17505 ;; Pentium III SIMD instructions.
17507 ;; Moves for SSE/MMX regs.
17509 (define_insn "movv4sf_internal"
17510 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17511 (match_operand:V4SF 1 "general_operand" "xm,x"))]
17513 ;; @@@ let's try to use movaps here.
17514 "movaps\\t{%1, %0|%0, %1}"
17515 [(set_attr "type" "sse")])
17517 (define_insn "movv4si_internal"
17518 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17519 (match_operand:V4SI 1 "general_operand" "xm,x"))]
17521 ;; @@@ let's try to use movaps here.
17522 "movaps\\t{%1, %0|%0, %1}"
17523 [(set_attr "type" "sse")])
17525 (define_insn "movv8qi_internal"
17526 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17527 (match_operand:V8QI 1 "general_operand" "ym,y"))]
17529 "movq\\t{%1, %0|%0, %1}"
17530 [(set_attr "type" "mmx")])
17532 (define_insn "movv4hi_internal"
17533 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17534 (match_operand:V4HI 1 "general_operand" "ym,y"))]
17536 "movq\\t{%1, %0|%0, %1}"
17537 [(set_attr "type" "mmx")])
17539 (define_insn "movv2si_internal"
17540 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17541 (match_operand:V2SI 1 "general_operand" "ym,y"))]
17543 "movq\\t{%1, %0|%0, %1}"
17544 [(set_attr "type" "mmx")])
17546 (define_expand "movti"
17547 [(set (match_operand:TI 0 "general_operand" "")
17548 (match_operand:TI 1 "general_operand" ""))]
17552 /* For constants other than zero into memory. We do not know how the
17553 instructions used to build constants modify the upper 64 bits
17554 of the register, once we have that information we may be able
17555 to handle some of them more efficiently. */
17556 if ((reload_in_progress | reload_completed) == 0
17557 && register_operand (operands[0], TImode)
17558 && CONSTANT_P (operands[1]))
17560 rtx addr = gen_reg_rtx (Pmode);
17562 emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0));
17563 operands[1] = gen_rtx_MEM (TImode, addr);
17566 /* Make operand1 a register if it isn't already. */
17567 if ((reload_in_progress | reload_completed) == 0
17568 && !register_operand (operands[0], TImode)
17569 && !register_operand (operands[1], TImode)
17570 && operands[1] != CONST0_RTX (TImode))
17572 rtx temp = force_reg (TImode, operands[1]);
17573 emit_move_insn (operands[0], temp);
17578 (define_expand "movv4sf"
17579 [(set (match_operand:V4SF 0 "general_operand" "")
17580 (match_operand:V4SF 1 "general_operand" ""))]
17584 /* For constants other than zero into memory. We do not know how the
17585 instructions used to build constants modify the upper 64 bits
17586 of the register, once we have that information we may be able
17587 to handle some of them more efficiently. */
17588 if ((reload_in_progress | reload_completed) == 0
17589 && register_operand (operands[0], V4SFmode)
17590 && CONSTANT_P (operands[1]))
17592 rtx addr = gen_reg_rtx (Pmode);
17594 emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0));
17595 operands[1] = gen_rtx_MEM (V4SFmode, addr);
17598 /* Make operand1 a register if it isn't already. */
17599 if ((reload_in_progress | reload_completed) == 0
17600 && !register_operand (operands[0], V4SFmode)
17601 && !register_operand (operands[1], V4SFmode)
17602 && operands[1] != CONST0_RTX (V4SFmode))
17604 rtx temp = force_reg (V4SFmode, operands[1]);
17605 emit_move_insn (operands[0], temp);
17610 (define_expand "movv4si"
17611 [(set (match_operand:V4SI 0 "general_operand" "")
17612 (match_operand:V4SI 1 "general_operand" ""))]
17616 /* For constants other than zero into memory. We do not know how the
17617 instructions used to build constants modify the upper 64 bits
17618 of the register, once we have that information we may be able
17619 to handle some of them more efficiently. */
17620 if ((reload_in_progress | reload_completed) == 0
17621 && register_operand (operands[0], V4SImode)
17622 && CONSTANT_P (operands[1]))
17624 rtx addr = gen_reg_rtx (Pmode);
17626 emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0));
17627 operands[1] = gen_rtx_MEM (V4SImode, addr);
17630 /* Make operand1 a register if it isn't already. */
17631 if ((reload_in_progress | reload_completed) == 0
17632 && !register_operand (operands[0], V4SImode)
17633 && !register_operand (operands[1], V4SImode)
17634 && operands[1] != CONST0_RTX (V4SImode))
17636 rtx temp = force_reg (V4SImode, operands[1]);
17637 emit_move_insn (operands[0], temp);
17642 (define_expand "movv2si"
17643 [(set (match_operand:V2SI 0 "general_operand" "")
17644 (match_operand:V2SI 1 "general_operand" ""))]
17648 /* For constants other than zero into memory. We do not know how the
17649 instructions used to build constants modify the upper 64 bits
17650 of the register, once we have that information we may be able
17651 to handle some of them more efficiently. */
17652 if ((reload_in_progress | reload_completed) == 0
17653 && register_operand (operands[0], V2SImode)
17654 && CONSTANT_P (operands[1]))
17656 rtx addr = gen_reg_rtx (Pmode);
17658 emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0));
17659 operands[1] = gen_rtx_MEM (V2SImode, addr);
17662 /* Make operand1 a register if it isn't already. */
17663 if ((reload_in_progress | reload_completed) == 0
17664 && !register_operand (operands[0], V2SImode)
17665 && !register_operand (operands[1], V2SImode)
17666 && operands[1] != CONST0_RTX (V2SImode))
17668 rtx temp = force_reg (V2SImode, operands[1]);
17669 emit_move_insn (operands[0], temp);
17674 (define_expand "movv4hi"
17675 [(set (match_operand:V4HI 0 "general_operand" "")
17676 (match_operand:V4HI 1 "general_operand" ""))]
17680 /* For constants other than zero into memory. We do not know how the
17681 instructions used to build constants modify the upper 64 bits
17682 of the register, once we have that information we may be able
17683 to handle some of them more efficiently. */
17684 if ((reload_in_progress | reload_completed) == 0
17685 && register_operand (operands[0], V4HImode)
17686 && CONSTANT_P (operands[1]))
17688 rtx addr = gen_reg_rtx (Pmode);
17690 emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0));
17691 operands[1] = gen_rtx_MEM (V4HImode, addr);
17694 /* Make operand1 a register if it isn't already. */
17695 if ((reload_in_progress | reload_completed) == 0
17696 && !register_operand (operands[0], V4HImode)
17697 && !register_operand (operands[1], V4HImode)
17698 && operands[1] != CONST0_RTX (V4HImode))
17700 rtx temp = force_reg (V4HImode, operands[1]);
17701 emit_move_insn (operands[0], temp);
17706 (define_expand "movv8qi"
17707 [(set (match_operand:V8QI 0 "general_operand" "")
17708 (match_operand:V8QI 1 "general_operand" ""))]
17712 /* For constants other than zero into memory. We do not know how the
17713 instructions used to build constants modify the upper 64 bits
17714 of the register, once we have that information we may be able
17715 to handle some of them more efficiently. */
17716 if ((reload_in_progress | reload_completed) == 0
17717 && register_operand (operands[0], V8QImode)
17718 && CONSTANT_P (operands[1]))
17720 rtx addr = gen_reg_rtx (Pmode);
17722 emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0));
17723 operands[1] = gen_rtx_MEM (V8QImode, addr);
17726 /* Make operand1 a register if it isn't already. */
17727 if ((reload_in_progress | reload_completed) == 0
17728 && !register_operand (operands[0], V8QImode)
17729 && !register_operand (operands[1], V8QImode)
17730 && operands[1] != CONST0_RTX (V8QImode))
17732 rtx temp = force_reg (V8QImode, operands[1]);
17733 emit_move_insn (operands[0], temp);
17738 (define_insn_and_split "*pushti"
17739 [(set (match_operand:TI 0 "push_operand" "=<")
17740 (match_operand:TI 1 "nonmemory_operand" "x"))]
17744 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17745 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17747 [(set_attr "type" "sse")])
17749 (define_insn_and_split "*pushv4sf"
17750 [(set (match_operand:V4SF 0 "push_operand" "=<")
17751 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
17755 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17756 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
17758 [(set_attr "type" "sse")])
17760 (define_insn_and_split "*pushv4si"
17761 [(set (match_operand:V4SI 0 "push_operand" "=<")
17762 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
17766 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17767 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
17769 [(set_attr "type" "sse")])
17771 (define_insn_and_split "*pushv2si"
17772 [(set (match_operand:V2SI 0 "push_operand" "=<")
17773 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
17777 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17778 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
17780 [(set_attr "type" "mmx")])
17782 (define_insn_and_split "*pushv4hi"
17783 [(set (match_operand:V4HI 0 "push_operand" "=<")
17784 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
17788 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17789 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
17791 [(set_attr "type" "mmx")])
17793 (define_insn_and_split "*pushv8qi"
17794 [(set (match_operand:V8QI 0 "push_operand" "=<")
17795 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
17799 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17800 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
17802 [(set_attr "type" "mmx")])
17804 (define_insn "movti_internal"
17805 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
17806 (match_operand:TI 1 "general_operand" "xm,x"))]
17809 movaps\\t{%1, %0|%0, %1}
17810 movaps\\t{%1, %0|%0, %1}"
17811 [(set_attr "type" "sse")])
17813 ;; These two patterns are useful for specifying exactly whether to use
17814 ;; movaps or movups
17815 (define_insn "sse_movaps"
17816 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17817 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
17820 movaps\\t{%1, %0|%0, %1}
17821 movaps\\t{%1, %0|%0, %1}"
17822 [(set_attr "type" "sse")])
17824 (define_insn "sse_movups"
17825 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17826 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
17829 movups\\t{%1, %0|%0, %1}
17830 movups\\t{%1, %0|%0, %1}"
17831 [(set_attr "type" "sse")])
17834 ;; SSE Strange Moves.
17836 (define_insn "sse_movmskps"
17837 [(set (match_operand:SI 0 "register_operand" "=r")
17838 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
17840 "movmskps\\t{%1, %0|%0, %1}"
17841 [(set_attr "type" "sse")])
17843 (define_insn "mmx_pmovmskb"
17844 [(set (match_operand:SI 0 "register_operand" "=r")
17845 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
17847 "pmovmskb\\t{%1, %0|%0, %1}"
17848 [(set_attr "type" "sse")])
17850 (define_insn "mmx_maskmovq"
17851 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17852 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17853 (match_operand:V8QI 2 "register_operand" "y")] 32))]
17855 ;; @@@ check ordering of operands in intel/nonintel syntax
17856 "maskmovq\\t{%2, %1|%1, %2}"
17857 [(set_attr "type" "sse")])
17859 (define_insn "sse_movntv4sf"
17860 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17861 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
17863 "movntps\\t{%1, %0|%0, %1}"
17864 [(set_attr "type" "sse")])
17866 (define_insn "sse_movntdi"
17867 [(set (match_operand:DI 0 "memory_operand" "=m")
17868 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
17870 "movntq\\t{%1, %0|%0, %1}"
17871 [(set_attr "type" "sse")])
17873 (define_insn "sse_movhlps"
17874 [(set (match_operand:V4SF 0 "register_operand" "=x")
17876 (match_operand:V4SF 1 "register_operand" "0")
17877 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17878 (parallel [(const_int 2)
17884 "movhlps\\t{%2, %0|%0, %2}"
17885 [(set_attr "type" "sse")])
17887 (define_insn "sse_movlhps"
17888 [(set (match_operand:V4SF 0 "register_operand" "=x")
17890 (match_operand:V4SF 1 "register_operand" "0")
17891 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17892 (parallel [(const_int 2)
17898 "movlhps\\t{%2, %0|%0, %2}"
17899 [(set_attr "type" "sse")])
17901 (define_insn "sse_movhps"
17902 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17904 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17905 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17907 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17908 "movhps\\t{%2, %0|%0, %2}"
17909 [(set_attr "type" "sse")])
17911 (define_insn "sse_movlps"
17912 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17914 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17915 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17917 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17918 "movlps\\t{%2, %0|%0, %2}"
17919 [(set_attr "type" "sse")])
17921 (define_insn "sse_loadss"
17922 [(set (match_operand:V4SF 0 "register_operand" "=x")
17924 (match_operand:V4SF 1 "memory_operand" "m")
17925 (vec_duplicate:V4SF (float:SF (const_int 0)))
17928 "movss\\t{%1, %0|%0, %1}"
17929 [(set_attr "type" "sse")])
17931 (define_insn "sse_movss"
17932 [(set (match_operand:V4SF 0 "register_operand" "=x")
17934 (match_operand:V4SF 1 "register_operand" "0")
17935 (match_operand:V4SF 2 "register_operand" "x")
17938 "movss\\t{%2, %0|%0, %2}"
17939 [(set_attr "type" "sse")])
17941 (define_insn "sse_storess"
17942 [(set (match_operand:SF 0 "memory_operand" "=m")
17944 (match_operand:V4SF 1 "register_operand" "x")
17945 (parallel [(const_int 0)])))]
17947 "movss\\t{%1, %0|%0, %1}"
17948 [(set_attr "type" "sse")])
17950 (define_insn "sse_shufps"
17951 [(set (match_operand:V4SF 0 "register_operand" "=x")
17952 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
17953 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
17954 (match_operand:SI 3 "immediate_operand" "i")] 41))]
17956 ;; @@@ check operand order for intel/nonintel syntax
17957 "shufps\\t{%3, %2, %0|%0, %2, %3}"
17958 [(set_attr "type" "sse")])
17963 (define_insn "addv4sf3"
17964 [(set (match_operand:V4SF 0 "register_operand" "=x")
17965 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17966 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17968 "addps\\t{%2, %0|%0, %2}"
17969 [(set_attr "type" "sse")])
17971 (define_insn "vmaddv4sf3"
17972 [(set (match_operand:V4SF 0 "register_operand" "=x")
17973 (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17974 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17978 "addss\\t{%2, %0|%0, %2}"
17979 [(set_attr "type" "sse")])
17981 (define_insn "subv4sf3"
17982 [(set (match_operand:V4SF 0 "register_operand" "=x")
17983 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17984 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17986 "subps\\t{%2, %0|%0, %2}"
17987 [(set_attr "type" "sse")])
17989 (define_insn "vmsubv4sf3"
17990 [(set (match_operand:V4SF 0 "register_operand" "=x")
17991 (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17992 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17996 "subss\\t{%2, %0|%0, %2}"
17997 [(set_attr "type" "sse")])
17999 (define_insn "mulv4sf3"
18000 [(set (match_operand:V4SF 0 "register_operand" "=x")
18001 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18002 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18004 "mulps\\t{%2, %0|%0, %2}"
18005 [(set_attr "type" "sse")])
18007 (define_insn "vmmulv4sf3"
18008 [(set (match_operand:V4SF 0 "register_operand" "=x")
18009 (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18010 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18014 "mulss\\t{%2, %0|%0, %2}"
18015 [(set_attr "type" "sse")])
18017 (define_insn "divv4sf3"
18018 [(set (match_operand:V4SF 0 "register_operand" "=x")
18019 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18020 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18022 "divps\\t{%2, %0|%0, %2}"
18023 [(set_attr "type" "sse")])
18025 (define_insn "vmdivv4sf3"
18026 [(set (match_operand:V4SF 0 "register_operand" "=x")
18027 (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18028 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18032 "divss\\t{%2, %0|%0, %2}"
18033 [(set_attr "type" "sse")])
18036 ;; SSE square root/reciprocal
18038 (define_insn "rcpv4sf2"
18039 [(set (match_operand:V4SF 0 "register_operand" "=x")
18040 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
18042 "rcpps\\t{%1, %0|%0, %1}"
18043 [(set_attr "type" "sse")])
18045 (define_insn "vmrcpv4sf2"
18046 [(set (match_operand:V4SF 0 "register_operand" "=x")
18047 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42)
18048 (match_operand:V4SF 2 "register_operand" "0")
18051 "rcpss\\t{%1, %0|%0, %1}"
18052 [(set_attr "type" "sse")])
18054 (define_insn "rsqrtv4sf2"
18055 [(set (match_operand:V4SF 0 "register_operand" "=x")
18056 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
18058 "rsqrtps\\t{%1, %0|%0, %1}"
18059 [(set_attr "type" "sse")])
18061 (define_insn "vmrsqrtv4sf2"
18062 [(set (match_operand:V4SF 0 "register_operand" "=x")
18063 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43)
18064 (match_operand:V4SF 2 "register_operand" "0")
18067 "rsqrtss\\t{%1, %0|%0, %1}"
18068 [(set_attr "type" "sse")])
18070 (define_insn "sqrtv4sf2"
18071 [(set (match_operand:V4SF 0 "register_operand" "=x")
18072 (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
18074 "sqrtps\\t{%1, %0|%0, %1}"
18075 [(set_attr "type" "sse")])
18077 (define_insn "vmsqrtv4sf2"
18078 [(set (match_operand:V4SF 0 "register_operand" "=x")
18079 (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm"))
18080 (match_operand:V4SF 2 "register_operand" "0")
18083 "sqrtss\\t{%1, %0|%0, %1}"
18084 [(set_attr "type" "sse")])
18087 ;; SSE logical operations.
18089 ;; These are not called andti3 etc. because we really really don't want
18090 ;; the compiler to widen DImode ands to TImode ands and then try to move
18091 ;; into DImode subregs of SSE registers, and them together, and move out
18092 ;; of DImode subregs again!
18094 (define_insn "*sse_andti3_df_1"
18095 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18096 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18097 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18099 "andpd\\t{%2, %0|%0, %2}"
18100 [(set_attr "type" "sse")])
18102 (define_insn "*sse_andti3_df_2"
18103 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18104 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18105 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18107 "andpd\\t{%2, %0|%0, %2}"
18108 [(set_attr "type" "sse")])
18110 (define_insn "*sse_andti3_sf_1"
18111 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18112 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18113 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18115 "andps\\t{%2, %0|%0, %2}"
18116 [(set_attr "type" "sse")])
18118 (define_insn "*sse_andti3_sf_2"
18119 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18120 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18121 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18123 "andps\\t{%2, %0|%0, %2}"
18124 [(set_attr "type" "sse")])
18126 (define_insn "sse_andti3"
18127 [(set (match_operand:TI 0 "register_operand" "=x")
18128 (and:TI (match_operand:TI 1 "register_operand" "%0")
18129 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18130 "TARGET_SSE && !TARGET_SSE2"
18131 "andps\\t{%2, %0|%0, %2}"
18132 [(set_attr "type" "sse")])
18134 (define_insn "*sse_andti3_sse2"
18135 [(set (match_operand:TI 0 "register_operand" "=x")
18136 (and:TI (match_operand:TI 1 "register_operand" "%0")
18137 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18139 "pand\\t{%2, %0|%0, %2}"
18140 [(set_attr "type" "sse")])
18142 (define_insn "*sse_nandti3_df"
18143 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18144 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18145 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18147 "andnpd\\t{%2, %0|%0, %2}"
18148 [(set_attr "type" "sse")])
18150 (define_insn "*sse_nandti3_sf"
18151 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18152 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18153 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18155 "andnps\\t{%2, %0|%0, %2}"
18156 [(set_attr "type" "sse")])
18158 (define_insn "sse_nandti3"
18159 [(set (match_operand:TI 0 "register_operand" "=x")
18160 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18161 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18162 "TARGET_SSE && !TARGET_SSE2"
18163 "andnps\\t{%2, %0|%0, %2}"
18164 [(set_attr "type" "sse")])
18166 (define_insn "*sse_nandti3_sse2"
18167 [(set (match_operand:TI 0 "register_operand" "=x")
18168 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18169 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18171 "pnand\\t{%2, %0|%0, %2}"
18172 [(set_attr "type" "sse")])
18174 (define_insn "*sse_iorti3_df_1"
18175 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18176 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18177 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18179 "orpd\\t{%2, %0|%0, %2}"
18180 [(set_attr "type" "sse")])
18182 (define_insn "*sse_iorti3_df_2"
18183 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18184 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18185 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18187 "orpd\\t{%2, %0|%0, %2}"
18188 [(set_attr "type" "sse")])
18190 (define_insn "*sse_iorti3_sf_1"
18191 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18192 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18193 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18195 "orps\\t{%2, %0|%0, %2}"
18196 [(set_attr "type" "sse")])
18198 (define_insn "*sse_iorti3_sf_2"
18199 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18200 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18201 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18203 "orps\\t{%2, %0|%0, %2}"
18204 [(set_attr "type" "sse")])
18206 (define_insn "sse_iorti3"
18207 [(set (match_operand:TI 0 "register_operand" "=x")
18208 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18209 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18210 "TARGET_SSE && !TARGET_SSE2"
18211 "orps\\t{%2, %0|%0, %2}"
18212 [(set_attr "type" "sse")])
18214 (define_insn "*sse_iorti3_sse2"
18215 [(set (match_operand:TI 0 "register_operand" "=x")
18216 (ior:TI (match_operand:TI 1 "register_operand" "%0")
18217 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18219 "por\\t{%2, %0|%0, %2}"
18220 [(set_attr "type" "sse")])
18222 (define_insn "*sse_xorti3_df_1"
18223 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18224 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18225 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18227 "xorpd\\t{%2, %0|%0, %2}"
18228 [(set_attr "type" "sse")])
18230 (define_insn "*sse_xorti3_df_2"
18231 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18232 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18233 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18235 "xorpd\\t{%2, %0|%0, %2}"
18236 [(set_attr "type" "sse")])
18238 (define_insn "*sse_xorti3_sf_1"
18239 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18240 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18241 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18243 "xorps\\t{%2, %0|%0, %2}"
18244 [(set_attr "type" "sse")])
18246 (define_insn "*sse_xorti3_sf_2"
18247 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18248 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18249 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18251 "xorps\\t{%2, %0|%0, %2}"
18252 [(set_attr "type" "sse")])
18254 (define_insn "sse_xorti3"
18255 [(set (match_operand:TI 0 "register_operand" "=x")
18256 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18257 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18258 "TARGET_SSE && !TARGET_SSE2"
18259 "xorps\\t{%2, %0|%0, %2}"
18260 [(set_attr "type" "sse")])
18262 (define_insn "*sse_xorti3_sse2"
18263 [(set (match_operand:TI 0 "register_operand" "=x")
18264 (xor:TI (match_operand:TI 1 "register_operand" "%0")
18265 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18267 "pxor\\t{%2, %0|%0, %2}"
18268 [(set_attr "type" "sse")])
18270 ;; Use xor, but don't show input operands so they aren't live before
18272 (define_insn "sse_clrti"
18273 [(set (match_operand:TI 0 "register_operand" "=x")
18274 (unspec:TI [(const_int 0)] 45))]
18276 "xorps\\t{%0, %0|%0, %0}"
18277 [(set_attr "type" "sse")])
18280 ;; SSE mask-generating compares
18282 (define_insn "maskcmpv4sf3"
18283 [(set (match_operand:V4SI 0 "register_operand" "=x")
18284 (match_operator:V4SI 3 "sse_comparison_operator"
18285 [(match_operand:V4SF 1 "register_operand" "0")
18286 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
18288 "cmp%D3ps\\t{%2, %0|%0, %2}"
18289 [(set_attr "type" "sse")])
18291 (define_insn "maskncmpv4sf3"
18292 [(set (match_operand:V4SI 0 "register_operand" "=x")
18294 (match_operator:V4SI 3 "sse_comparison_operator"
18295 [(match_operand:V4SF 1 "register_operand" "0")
18296 (match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
18298 "cmpn%D3ps\\t{%2, %0|%0, %2}"
18299 [(set_attr "type" "sse")])
18301 (define_insn "vmmaskcmpv4sf3"
18302 [(set (match_operand:V4SI 0 "register_operand" "=x")
18304 (match_operator:V4SI 3 "sse_comparison_operator"
18305 [(match_operand:V4SF 1 "register_operand" "0")
18306 (match_operand:V4SF 2 "nonimmediate_operand" "x")])
18310 "cmp%D3ss\\t{%2, %0|%0, %2}"
18311 [(set_attr "type" "sse")])
18313 (define_insn "vmmaskncmpv4sf3"
18314 [(set (match_operand:V4SI 0 "register_operand" "=x")
18317 (match_operator:V4SI 3 "sse_comparison_operator"
18318 [(match_operand:V4SF 1 "register_operand" "0")
18319 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))
18320 (subreg:V4SI (match_dup 1) 0)
18323 "cmp%D3ss\\t{%2, %0|%0, %2}"
18324 [(set_attr "type" "sse")])
18326 (define_insn "sse_comi"
18327 [(set (reg:CCFP 17)
18328 (match_operator:CCFP 2 "sse_comparison_operator"
18330 (match_operand:V4SF 0 "register_operand" "x")
18331 (parallel [(const_int 0)]))
18333 (match_operand:V4SF 1 "register_operand" "x")
18334 (parallel [(const_int 0)]))]))]
18336 "comiss\\t{%2, %0|%0, %2}"
18337 [(set_attr "type" "sse")])
18339 (define_insn "sse_ucomi"
18340 [(set (reg:CCFPU 17)
18341 (match_operator:CCFPU 2 "sse_comparison_operator"
18343 (match_operand:V4SF 0 "register_operand" "x")
18344 (parallel [(const_int 0)]))
18346 (match_operand:V4SF 1 "register_operand" "x")
18347 (parallel [(const_int 0)]))]))]
18349 "ucomiss\\t{%2, %0|%0, %2}"
18350 [(set_attr "type" "sse")])
18355 (define_insn "sse_unpckhps"
18356 [(set (match_operand:V4SF 0 "register_operand" "=x")
18358 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18359 (parallel [(const_int 2)
18363 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
18364 (parallel [(const_int 0)
18370 "unpckhps\\t{%2, %0|%0, %2}"
18371 [(set_attr "type" "sse")])
18373 (define_insn "sse_unpcklps"
18374 [(set (match_operand:V4SF 0 "register_operand" "=x")
18376 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18377 (parallel [(const_int 0)
18381 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
18382 (parallel [(const_int 2)
18388 "unpcklps\\t{%2, %0|%0, %2}"
18389 [(set_attr "type" "sse")])
18394 (define_insn "smaxv4sf3"
18395 [(set (match_operand:V4SF 0 "register_operand" "=x")
18396 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18397 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18399 "maxps\\t{%2, %0|%0, %2}"
18400 [(set_attr "type" "sse")])
18402 (define_insn "vmsmaxv4sf3"
18403 [(set (match_operand:V4SF 0 "register_operand" "=x")
18404 (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18405 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18409 "maxss\\t{%2, %0|%0, %2}"
18410 [(set_attr "type" "sse")])
18412 (define_insn "sminv4sf3"
18413 [(set (match_operand:V4SF 0 "register_operand" "=x")
18414 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18415 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18417 "minps\\t{%2, %0|%0, %2}"
18418 [(set_attr "type" "sse")])
18420 (define_insn "vmsminv4sf3"
18421 [(set (match_operand:V4SF 0 "register_operand" "=x")
18422 (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18423 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18427 "minss\\t{%2, %0|%0, %2}"
18428 [(set_attr "type" "sse")])
18431 ;; SSE <-> integer/MMX conversions
18433 (define_insn "cvtpi2ps"
18434 [(set (match_operand:V4SF 0 "register_operand" "=x")
18435 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18436 (vec_duplicate:V4SF
18437 (float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
18440 "cvtpi2ps\\t{%2, %0|%0, %2}"
18441 [(set_attr "type" "sse")])
18443 (define_insn "cvtps2pi"
18444 [(set (match_operand:V2SI 0 "register_operand" "=y")
18445 (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18450 "cvtps2pi\\t{%1, %0|%0, %1}"
18451 [(set_attr "type" "sse")])
18453 (define_insn "cvttps2pi"
18454 [(set (match_operand:V2SI 0 "register_operand" "=y")
18455 (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18460 "cvttps2pi\\t{%1, %0|%0, %1}"
18461 [(set_attr "type" "sse")])
18463 (define_insn "cvtsi2ss"
18464 [(set (match_operand:V4SF 0 "register_operand" "=x")
18465 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
18466 (vec_duplicate:V4SF
18467 (float:SF (match_operand:SI 2 "register_operand" "rm")))
18470 "cvtsi2ss\\t{%2, %0|%0, %2}"
18471 [(set_attr "type" "sse")])
18473 (define_insn "cvtss2si"
18474 [(set (match_operand:SI 0 "register_operand" "=y")
18475 (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
18476 (parallel [(const_int 0)])))]
18478 "cvtss2si\\t{%1, %0|%0, %1}"
18479 [(set_attr "type" "sse")])
18481 (define_insn "cvttss2si"
18482 [(set (match_operand:SI 0 "register_operand" "=y")
18483 (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
18484 (parallel [(const_int 0)])))]
18486 "cvttss2si\\t{%1, %0|%0, %1}"
18487 [(set_attr "type" "sse")])
18494 (define_insn "addv8qi3"
18495 [(set (match_operand:V8QI 0 "register_operand" "=y")
18496 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18497 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18499 "paddb\\t{%2, %0|%0, %2}"
18500 [(set_attr "type" "mmx")])
18502 (define_insn "addv4hi3"
18503 [(set (match_operand:V4HI 0 "register_operand" "=y")
18504 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18505 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18507 "paddw\\t{%2, %0|%0, %2}"
18508 [(set_attr "type" "mmx")])
18510 (define_insn "addv2si3"
18511 [(set (match_operand:V2SI 0 "register_operand" "=y")
18512 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18513 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18515 "paddd\\t{%2, %0|%0, %2}"
18516 [(set_attr "type" "mmx")])
18518 (define_insn "ssaddv8qi3"
18519 [(set (match_operand:V8QI 0 "register_operand" "=y")
18520 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18521 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18523 "paddsb\\t{%2, %0|%0, %2}"
18524 [(set_attr "type" "mmx")])
18526 (define_insn "ssaddv4hi3"
18527 [(set (match_operand:V4HI 0 "register_operand" "=y")
18528 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18529 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18531 "paddsw\\t{%2, %0|%0, %2}"
18532 [(set_attr "type" "mmx")])
18534 (define_insn "usaddv8qi3"
18535 [(set (match_operand:V8QI 0 "register_operand" "=y")
18536 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18537 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18539 "paddusb\\t{%2, %0|%0, %2}"
18540 [(set_attr "type" "mmx")])
18542 (define_insn "usaddv4hi3"
18543 [(set (match_operand:V4HI 0 "register_operand" "=y")
18544 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18545 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18547 "paddusw\\t{%2, %0|%0, %2}"
18548 [(set_attr "type" "mmx")])
18550 (define_insn "subv8qi3"
18551 [(set (match_operand:V8QI 0 "register_operand" "=y")
18552 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18553 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18555 "psubb\\t{%2, %0|%0, %2}"
18556 [(set_attr "type" "mmx")])
18558 (define_insn "subv4hi3"
18559 [(set (match_operand:V4HI 0 "register_operand" "=y")
18560 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18561 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18563 "psubw\\t{%2, %0|%0, %2}"
18564 [(set_attr "type" "mmx")])
18566 (define_insn "subv2si3"
18567 [(set (match_operand:V2SI 0 "register_operand" "=y")
18568 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18569 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18571 "psubd\\t{%2, %0|%0, %2}"
18572 [(set_attr "type" "mmx")])
18574 (define_insn "sssubv8qi3"
18575 [(set (match_operand:V8QI 0 "register_operand" "=y")
18576 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18577 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18579 "psubsb\\t{%2, %0|%0, %2}"
18580 [(set_attr "type" "mmx")])
18582 (define_insn "sssubv4hi3"
18583 [(set (match_operand:V4HI 0 "register_operand" "=y")
18584 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18585 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18587 "psubsw\\t{%2, %0|%0, %2}"
18588 [(set_attr "type" "mmx")])
18590 (define_insn "ussubv8qi3"
18591 [(set (match_operand:V8QI 0 "register_operand" "=y")
18592 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18593 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18595 "psubusb\\t{%2, %0|%0, %2}"
18596 [(set_attr "type" "mmx")])
18598 (define_insn "ussubv4hi3"
18599 [(set (match_operand:V4HI 0 "register_operand" "=y")
18600 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18601 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18603 "psubusw\\t{%2, %0|%0, %2}"
18604 [(set_attr "type" "mmx")])
18606 (define_insn "mulv4hi3"
18607 [(set (match_operand:V4HI 0 "register_operand" "=y")
18608 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
18609 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18611 "pmullw\\t{%2, %0|%0, %2}"
18612 [(set_attr "type" "mmx")])
18614 (define_insn "smulv4hi3_highpart"
18615 [(set (match_operand:V4HI 0 "register_operand" "=y")
18618 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18619 (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18622 "pmulhw\\t{%2, %0|%0, %2}"
18623 [(set_attr "type" "mmx")])
18625 (define_insn "umulv4hi3_highpart"
18626 [(set (match_operand:V4HI 0 "register_operand" "=y")
18629 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18630 (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18633 "pmulhuw\\t{%2, %0|%0, %2}"
18634 [(set_attr "type" "mmx")])
18636 (define_insn "mmx_pmaddwd"
18637 [(set (match_operand:V2SI 0 "register_operand" "=y")
18640 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
18641 (parallel [(const_int 0)
18643 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18644 (parallel [(const_int 0)
18647 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
18648 (parallel [(const_int 1)
18650 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
18651 (parallel [(const_int 1)
18652 (const_int 3)]))))))]
18654 "pmaddwd\\t{%2, %0|%0, %2}"
18655 [(set_attr "type" "mmx")])
18658 ;; MMX logical operations
18659 ;; Note we don't want to declare these as regular iordi3 insns to prevent
18660 ;; normal code that also wants to use the FPU from getting broken.
18661 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
18662 (define_insn "mmx_iordi3"
18663 [(set (match_operand:DI 0 "register_operand" "=y")
18665 [(ior:DI (match_operand:DI 1 "register_operand" "0")
18666 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18668 "por\\t{%2, %0|%0, %2}"
18669 [(set_attr "type" "mmx")])
18671 (define_insn "mmx_xordi3"
18672 [(set (match_operand:DI 0 "register_operand" "=y")
18674 [(xor:DI (match_operand:DI 1 "register_operand" "0")
18675 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18677 "pxor\\t{%2, %0|%0, %2}"
18678 [(set_attr "type" "mmx")])
18680 ;; Same as pxor, but don't show input operands so that we don't think
18682 (define_insn "mmx_clrdi"
18683 [(set (match_operand:DI 0 "register_operand" "=y")
18684 (unspec:DI [(const_int 0)] 45))]
18686 "pxor\\t{%0, %0|%0, %0}"
18687 [(set_attr "type" "mmx")])
18689 (define_insn "mmx_anddi3"
18690 [(set (match_operand:DI 0 "register_operand" "=y")
18692 [(and:DI (match_operand:DI 1 "register_operand" "0")
18693 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18695 "pand\\t{%2, %0|%0, %2}"
18696 [(set_attr "type" "mmx")])
18698 (define_insn "mmx_nanddi3"
18699 [(set (match_operand:DI 0 "register_operand" "=y")
18701 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
18702 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18704 "pandn\\t{%2, %0|%0, %2}"
18705 [(set_attr "type" "mmx")])
18708 ;; MMX unsigned averages/sum of absolute differences
18710 (define_insn "mmx_uavgv8qi3"
18711 [(set (match_operand:V8QI 0 "register_operand" "=y")
18713 (plus:V8QI (plus:V8QI
18714 (match_operand:V8QI 1 "register_operand" "0")
18715 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18716 (vec_const:V8QI (parallel [(const_int 1)
18726 "pavgb\\t{%2, %0|%0, %2}"
18727 [(set_attr "type" "sse")])
18729 (define_insn "mmx_uavgv4hi3"
18730 [(set (match_operand:V4HI 0 "register_operand" "=y")
18732 (plus:V4HI (plus:V4HI
18733 (match_operand:V4HI 1 "register_operand" "0")
18734 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18735 (vec_const:V4HI (parallel [(const_int 1)
18741 "pavgw\\t{%2, %0|%0, %2}"
18742 [(set_attr "type" "sse")])
18744 (define_insn "mmx_psadbw"
18745 [(set (match_operand:V8QI 0 "register_operand" "=y")
18746 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18747 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
18749 "psadbw\\t{%2, %0|%0, %2}"
18750 [(set_attr "type" "sse")])
18753 ;; MMX insert/extract/shuffle
18755 (define_insn "mmx_pinsrw"
18756 [(set (match_operand:V4HI 0 "register_operand" "=y")
18757 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
18758 (vec_duplicate:V4HI
18759 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
18760 (match_operand:SI 3 "immediate_operand" "i")))]
18762 "pinsrw\\t{%3, %2, %0|%0, %2, %3}"
18763 [(set_attr "type" "sse")])
18765 (define_insn "mmx_pextrw"
18766 [(set (match_operand:SI 0 "register_operand" "=r")
18767 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
18769 [(match_operand:SI 2 "immediate_operand" "i")]))))]
18771 "pextrw\\t{%2, %1, %0|%0, %1, %2}"
18772 [(set_attr "type" "sse")])
18774 (define_insn "mmx_pshufw"
18775 [(set (match_operand:V4HI 0 "register_operand" "=y")
18776 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
18777 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18778 (match_operand:SI 3 "immediate_operand" "i")] 41))]
18780 "pshufw\\t{%3, %2, %0|%0, %2, %3}"
18781 [(set_attr "type" "sse")])
18784 ;; MMX mask-generating comparisons
18786 (define_insn "eqv8qi3"
18787 [(set (match_operand:V8QI 0 "register_operand" "=y")
18788 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
18789 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18791 "pcmpeqb\\t{%2, %0|%0, %2}"
18792 [(set_attr "type" "mmx")])
18794 (define_insn "eqv4hi3"
18795 [(set (match_operand:V4HI 0 "register_operand" "=y")
18796 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
18797 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18799 "pcmpeqw\\t{%2, %0|%0, %2}"
18800 [(set_attr "type" "mmx")])
18802 (define_insn "eqv2si3"
18803 [(set (match_operand:V2SI 0 "register_operand" "=y")
18804 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
18805 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18807 "pcmpeqd\\t{%2, %0|%0, %2}"
18808 [(set_attr "type" "mmx")])
18810 (define_insn "gtv8qi3"
18811 [(set (match_operand:V8QI 0 "register_operand" "=y")
18812 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
18813 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18815 "pcmpgtb\\t{%2, %0|%0, %2}"
18816 [(set_attr "type" "mmx")])
18818 (define_insn "gtv4hi3"
18819 [(set (match_operand:V4HI 0 "register_operand" "=y")
18820 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18821 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18823 "pcmpgtw\\t{%2, %0|%0, %2}"
18824 [(set_attr "type" "mmx")])
18826 (define_insn "gtv2si3"
18827 [(set (match_operand:V2SI 0 "register_operand" "=y")
18828 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18829 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18831 "pcmpgtd\\t{%2, %0|%0, %2}"
18832 [(set_attr "type" "mmx")])
18835 ;; MMX max/min insns
18837 (define_insn "umaxv8qi3"
18838 [(set (match_operand:V8QI 0 "register_operand" "=y")
18839 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
18840 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18842 "pmaxub\\t{%2, %0|%0, %2}"
18843 [(set_attr "type" "sse")])
18845 (define_insn "smaxv4hi3"
18846 [(set (match_operand:V4HI 0 "register_operand" "=y")
18847 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
18848 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18850 "pmaxsw\\t{%2, %0|%0, %2}"
18851 [(set_attr "type" "sse")])
18853 (define_insn "uminv8qi3"
18854 [(set (match_operand:V8QI 0 "register_operand" "=y")
18855 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
18856 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18858 "pminub\\t{%2, %0|%0, %2}"
18859 [(set_attr "type" "sse")])
18861 (define_insn "sminv4hi3"
18862 [(set (match_operand:V4HI 0 "register_operand" "=y")
18863 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
18864 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18866 "pminsw\\t{%2, %0|%0, %2}"
18867 [(set_attr "type" "sse")])
18872 (define_insn "ashrv4hi3"
18873 [(set (match_operand:V4HI 0 "register_operand" "=y")
18874 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18875 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18877 "psraw\\t{%2, %0|%0, %2}"
18878 [(set_attr "type" "mmx")])
18880 (define_insn "ashrv2si3"
18881 [(set (match_operand:V2SI 0 "register_operand" "=y")
18882 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18883 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18885 "psrad\\t{%2, %0|%0, %2}"
18886 [(set_attr "type" "mmx")])
18888 (define_insn "lshrv4hi3"
18889 [(set (match_operand:V4HI 0 "register_operand" "=y")
18890 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18891 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18893 "psrlw\\t{%2, %0|%0, %2}"
18894 [(set_attr "type" "mmx")])
18896 (define_insn "lshrv2si3"
18897 [(set (match_operand:V2SI 0 "register_operand" "=y")
18898 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18899 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18901 "psrld\\t{%2, %0|%0, %2}"
18902 [(set_attr "type" "mmx")])
18904 ;; See logical MMX insns.
18905 (define_insn "mmx_lshrdi3"
18906 [(set (match_operand:DI 0 "register_operand" "=y")
18908 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
18909 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18911 "psrlq\\t{%2, %0|%0, %2}"
18912 [(set_attr "type" "mmx")])
18914 (define_insn "ashlv4hi3"
18915 [(set (match_operand:V4HI 0 "register_operand" "=y")
18916 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
18917 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18919 "psllw\\t{%2, %0|%0, %2}"
18920 [(set_attr "type" "mmx")])
18922 (define_insn "ashlv2si3"
18923 [(set (match_operand:V2SI 0 "register_operand" "=y")
18924 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
18925 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18927 "pslld\\t{%2, %0|%0, %2}"
18928 [(set_attr "type" "mmx")])
18930 ;; See logical MMX insns.
18931 (define_insn "mmx_ashldi3"
18932 [(set (match_operand:DI 0 "register_operand" "=y")
18934 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
18935 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18937 "psllq\\t{%2, %0|%0, %2}"
18938 [(set_attr "type" "mmx")])
18941 ;; MMX pack/unpack insns.
18943 (define_insn "mmx_packsswb"
18944 [(set (match_operand:V8QI 0 "register_operand" "=y")
18946 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
18947 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
18949 "packsswb\\t{%2, %0|%0, %2}"
18950 [(set_attr "type" "mmx")])
18952 (define_insn "mmx_packssdw"
18953 [(set (match_operand:V4HI 0 "register_operand" "=y")
18955 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
18956 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
18958 "packssdw\\t{%2, %0|%0, %2}"
18959 [(set_attr "type" "mmx")])
18961 (define_insn "mmx_packuswb"
18962 [(set (match_operand:V8QI 0 "register_operand" "=y")
18964 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
18965 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
18967 "packuswb\\t{%2, %0|%0, %2}"
18968 [(set_attr "type" "mmx")])
18970 (define_insn "mmx_punpckhbw"
18971 [(set (match_operand:V8QI 0 "register_operand" "=y")
18973 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
18974 (parallel [(const_int 4)
18982 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
18983 (parallel [(const_int 0)
18993 "punpckhbw\\t{%2, %0|%0, %2}"
18994 [(set_attr "type" "mmx")])
18996 (define_insn "mmx_punpckhwd"
18997 [(set (match_operand:V4HI 0 "register_operand" "=y")
18999 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19000 (parallel [(const_int 0)
19004 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19005 (parallel [(const_int 2)
19011 "punpckhwd\\t{%2, %0|%0, %2}"
19012 [(set_attr "type" "mmx")])
19014 (define_insn "mmx_punpckhdq"
19015 [(set (match_operand:V2SI 0 "register_operand" "=y")
19017 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19018 (parallel [(const_int 0)
19020 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19021 (parallel [(const_int 1)
19025 "punpckhdq\\t{%2, %0|%0, %2}"
19026 [(set_attr "type" "mmx")])
19028 (define_insn "mmx_punpcklbw"
19029 [(set (match_operand:V8QI 0 "register_operand" "=y")
19031 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19032 (parallel [(const_int 0)
19040 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19041 (parallel [(const_int 4)
19051 "punpcklbw\\t{%2, %0|%0, %2}"
19052 [(set_attr "type" "mmx")])
19054 (define_insn "mmx_punpcklwd"
19055 [(set (match_operand:V4HI 0 "register_operand" "=y")
19057 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19058 (parallel [(const_int 2)
19062 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19063 (parallel [(const_int 0)
19069 "punpcklwd\\t{%2, %0|%0, %2}"
19070 [(set_attr "type" "mmx")])
19072 (define_insn "mmx_punpckldq"
19073 [(set (match_operand:V2SI 0 "register_operand" "=y")
19075 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19076 (parallel [(const_int 1)
19078 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19079 (parallel [(const_int 0)
19083 "punpckldq\\t{%2, %0|%0, %2}"
19084 [(set_attr "type" "mmx")])
19087 ;; Miscellaneous stuff
19089 (define_insn "emms"
19090 [(unspec_volatile [(const_int 0)] 31)
19091 (clobber (reg:XF 8))
19092 (clobber (reg:XF 9))
19093 (clobber (reg:XF 10))
19094 (clobber (reg:XF 11))
19095 (clobber (reg:XF 12))
19096 (clobber (reg:XF 13))
19097 (clobber (reg:XF 14))
19098 (clobber (reg:XF 15))
19099 (clobber (reg:DI 29))
19100 (clobber (reg:DI 30))
19101 (clobber (reg:DI 31))
19102 (clobber (reg:DI 32))
19103 (clobber (reg:DI 33))
19104 (clobber (reg:DI 34))
19105 (clobber (reg:DI 35))
19106 (clobber (reg:DI 36))]
19109 [(set_attr "type" "mmx")
19110 (set_attr "memory" "unknown")])
19112 (define_insn "ldmxcsr"
19113 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
19116 [(set_attr "type" "mmx")])
19118 (define_insn "stmxcsr"
19119 [(set (match_operand:SI 0 "memory_operand" "=m")
19120 (unspec_volatile:SI [(const_int 0)] 40))]
19123 [(set_attr "type" "mmx")])
19125 (define_expand "sfence"
19126 [(set (match_dup 0)
19127 (unspec:BLK [(match_dup 0)] 44))]
19131 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
19132 MEM_VOLATILE_P (operands[0]) = 1;
19135 (define_insn "*sfence_insn"
19136 [(set (match_operand:BLK 0 "" "")
19137 (unspec:BLK [(match_dup 0)] 44))]
19140 [(set_attr "type" "sse")
19141 (set_attr "memory" "unknown")])
19143 (define_insn "prefetch"
19144 [(unspec [(match_operand:SI 0 "address_operand" "p")
19145 (match_operand:SI 1 "immediate_operand" "n")] 35)]
19149 switch (INTVAL (operands[1]))
19152 return \"prefetchnta\\t%a0\";
19154 return \"prefetcht0\\t%a0\";
19156 return \"prefetcht1\\t%a0\";
19158 return \"prefetcht2\\t%a0\";
19163 [(set_attr "type" "sse")])