1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; The special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
39 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
40 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
41 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
42 ;; 'J' Print the appropriate jump operand.
44 ;; 'b' Print the QImode name of the register for the indicated operand.
45 ;; %b0 would print %al if operands[0] is reg 0.
46 ;; 'w' Likewise, print the HImode name of the register.
47 ;; 'k' Likewise, print the SImode name of the register.
48 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
49 ;; 'y' Print "st(0)" instead of "st" as a register.
54 [; Relocation specifiers
66 (UNSPEC_STACK_ALLOC 11)
68 (UNSPEC_SSE_PROLOGUE_SAVE 13)
73 (UNSPEC_TLS_LD_BASE 17)
75 ; Other random patterns
85 ; For SSE/MMX support:
96 (UNSPEC_NOP 45) ; prevents combiner cleverness
123 ; x87 Double output FP
124 (UNSPEC_SINCOS_COS 80)
125 (UNSPEC_SINCOS_SIN 81)
128 (UNSPEC_XTRACT_FRACT 84)
129 (UNSPEC_XTRACT_EXP 85)
130 (UNSPEC_FSCALE_FRACT 86)
131 (UNSPEC_FSCALE_EXP 87)
138 (UNSPEC_FRNDINT_FLOOR 96)
139 (UNSPEC_FRNDINT_CEIL 97)
140 (UNSPEC_FRNDINT_TRUNC 98)
141 (UNSPEC_FRNDINT_MASK_PM 99)
146 (UNSPEC_EH_RETURN 76)
150 [(UNSPECV_BLOCKAGE 0)
151 (UNSPECV_STACK_PROBE 10)
162 ;; Registers by name.
171 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
174 ;; In C guard expressions, put expressions which may be compile-time
175 ;; constants first. This allows for better optimization. For
176 ;; example, write "TARGET_64BIT && reload_completed", not
177 ;; "reload_completed && TARGET_64BIT".
180 ;; Processor type. This attribute must exactly match the processor_type
181 ;; enumeration in i386.h.
182 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona"
183 (const (symbol_ref "ix86_tune")))
185 ;; A basic instruction type. Refinements due to arguments to be
186 ;; provided in other attributes.
189 alu,alu1,negnot,imov,imovx,lea,
190 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
191 icmp,test,ibr,setcc,icmov,
192 push,pop,call,callv,leave,
194 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint,
195 sselog,sseiadd,sseishft,sseimul,
196 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
197 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
198 (const_string "other"))
200 ;; Main data type used by the insn
202 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
203 (const_string "unknown"))
205 ;; The CPU unit operations uses.
206 (define_attr "unit" "integer,i387,sse,mmx,unknown"
207 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint")
208 (const_string "i387")
209 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
210 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
212 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
214 (eq_attr "type" "other")
215 (const_string "unknown")]
216 (const_string "integer")))
218 ;; The (bounding maximum) length of an instruction immediate.
219 (define_attr "length_immediate" ""
220 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
222 (eq_attr "unit" "i387,sse,mmx")
224 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
226 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
227 (eq_attr "type" "imov,test")
228 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
229 (eq_attr "type" "call")
230 (if_then_else (match_operand 0 "constant_call_address_operand" "")
233 (eq_attr "type" "callv")
234 (if_then_else (match_operand 1 "constant_call_address_operand" "")
237 ;; We don't know the size before shorten_branches. Expect
238 ;; the instruction to fit for better scheduling.
239 (eq_attr "type" "ibr")
242 (symbol_ref "/* Update immediate_length and other attributes! */
245 ;; The (bounding maximum) length of an instruction address.
246 (define_attr "length_address" ""
247 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
249 (and (eq_attr "type" "call")
250 (match_operand 0 "constant_call_address_operand" ""))
252 (and (eq_attr "type" "callv")
253 (match_operand 1 "constant_call_address_operand" ""))
256 (symbol_ref "ix86_attr_length_address_default (insn)")))
258 ;; Set when length prefix is used.
259 (define_attr "prefix_data16" ""
260 (if_then_else (ior (eq_attr "mode" "HI")
261 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
265 ;; Set when string REP prefix is used.
266 (define_attr "prefix_rep" ""
267 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
271 ;; Set when 0f opcode prefix is used.
272 (define_attr "prefix_0f" ""
274 (ior (eq_attr "type" "imovx,setcc,icmov")
275 (eq_attr "unit" "sse,mmx"))
279 ;; Set when REX opcode prefix is used.
280 (define_attr "prefix_rex" ""
281 (cond [(and (eq_attr "mode" "DI")
282 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
284 (and (eq_attr "mode" "QI")
285 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
288 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
294 ;; Set when modrm byte is used.
295 (define_attr "modrm" ""
296 (cond [(eq_attr "type" "str,cld,leave")
298 (eq_attr "unit" "i387")
300 (and (eq_attr "type" "incdec")
301 (ior (match_operand:SI 1 "register_operand" "")
302 (match_operand:HI 1 "register_operand" "")))
304 (and (eq_attr "type" "push")
305 (not (match_operand 1 "memory_operand" "")))
307 (and (eq_attr "type" "pop")
308 (not (match_operand 0 "memory_operand" "")))
310 (and (eq_attr "type" "imov")
311 (and (match_operand 0 "register_operand" "")
312 (match_operand 1 "immediate_operand" "")))
314 (and (eq_attr "type" "call")
315 (match_operand 0 "constant_call_address_operand" ""))
317 (and (eq_attr "type" "callv")
318 (match_operand 1 "constant_call_address_operand" ""))
323 ;; The (bounding maximum) length of an instruction in bytes.
324 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
325 ;; Later we may want to split them and compute proper length as for
327 (define_attr "length" ""
328 (cond [(eq_attr "type" "other,multi,fistp,frndint")
330 (eq_attr "type" "fcmp")
332 (eq_attr "unit" "i387")
334 (plus (attr "prefix_data16")
335 (attr "length_address")))]
336 (plus (plus (attr "modrm")
337 (plus (attr "prefix_0f")
338 (plus (attr "prefix_rex")
340 (plus (attr "prefix_rep")
341 (plus (attr "prefix_data16")
342 (plus (attr "length_immediate")
343 (attr "length_address")))))))
345 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
346 ;; `store' if there is a simple memory reference therein, or `unknown'
347 ;; if the instruction is complex.
349 (define_attr "memory" "none,load,store,both,unknown"
350 (cond [(eq_attr "type" "other,multi,str")
351 (const_string "unknown")
352 (eq_attr "type" "lea,fcmov,fpspc,cld")
353 (const_string "none")
354 (eq_attr "type" "fistp,leave")
355 (const_string "both")
356 (eq_attr "type" "frndint")
357 (const_string "load")
358 (eq_attr "type" "push")
359 (if_then_else (match_operand 1 "memory_operand" "")
360 (const_string "both")
361 (const_string "store"))
362 (eq_attr "type" "pop")
363 (if_then_else (match_operand 0 "memory_operand" "")
364 (const_string "both")
365 (const_string "load"))
366 (eq_attr "type" "setcc")
367 (if_then_else (match_operand 0 "memory_operand" "")
368 (const_string "store")
369 (const_string "none"))
370 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
371 (if_then_else (ior (match_operand 0 "memory_operand" "")
372 (match_operand 1 "memory_operand" ""))
373 (const_string "load")
374 (const_string "none"))
375 (eq_attr "type" "ibr")
376 (if_then_else (match_operand 0 "memory_operand" "")
377 (const_string "load")
378 (const_string "none"))
379 (eq_attr "type" "call")
380 (if_then_else (match_operand 0 "constant_call_address_operand" "")
381 (const_string "none")
382 (const_string "load"))
383 (eq_attr "type" "callv")
384 (if_then_else (match_operand 1 "constant_call_address_operand" "")
385 (const_string "none")
386 (const_string "load"))
387 (and (eq_attr "type" "alu1,negnot,ishift1")
388 (match_operand 1 "memory_operand" ""))
389 (const_string "both")
390 (and (match_operand 0 "memory_operand" "")
391 (match_operand 1 "memory_operand" ""))
392 (const_string "both")
393 (match_operand 0 "memory_operand" "")
394 (const_string "store")
395 (match_operand 1 "memory_operand" "")
396 (const_string "load")
398 "!alu1,negnot,ishift1,
399 imov,imovx,icmp,test,
401 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
402 mmx,mmxmov,mmxcmp,mmxcvt")
403 (match_operand 2 "memory_operand" ""))
404 (const_string "load")
405 (and (eq_attr "type" "icmov")
406 (match_operand 3 "memory_operand" ""))
407 (const_string "load")
409 (const_string "none")))
411 ;; Indicates if an instruction has both an immediate and a displacement.
413 (define_attr "imm_disp" "false,true,unknown"
414 (cond [(eq_attr "type" "other,multi")
415 (const_string "unknown")
416 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
417 (and (match_operand 0 "memory_displacement_operand" "")
418 (match_operand 1 "immediate_operand" "")))
419 (const_string "true")
420 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
421 (and (match_operand 0 "memory_displacement_operand" "")
422 (match_operand 2 "immediate_operand" "")))
423 (const_string "true")
425 (const_string "false")))
427 ;; Indicates if an FP operation has an integer source.
429 (define_attr "fp_int_src" "false,true"
430 (const_string "false"))
432 ;; Defines rounding mode of an FP operation.
434 (define_attr "i387_cw" "floor,ceil,trunc,mask_pm,uninitialized,any"
435 (const_string "any"))
437 ;; Describe a user's asm statement.
438 (define_asm_attributes
439 [(set_attr "length" "128")
440 (set_attr "type" "multi")])
442 ;; Scheduling descriptions
444 (include "pentium.md")
447 (include "athlon.md")
450 ;; Operand and operator predicates
452 (include "predicates.md")
455 ;; Compare instructions.
457 ;; All compare insns have expanders that save the operands away without
458 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
459 ;; after the cmp) will actually emit the cmpM.
461 (define_expand "cmpdi"
462 [(set (reg:CC FLAGS_REG)
463 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
464 (match_operand:DI 1 "x86_64_general_operand" "")))]
467 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
468 operands[0] = force_reg (DImode, operands[0]);
469 ix86_compare_op0 = operands[0];
470 ix86_compare_op1 = operands[1];
474 (define_expand "cmpsi"
475 [(set (reg:CC FLAGS_REG)
476 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
477 (match_operand:SI 1 "general_operand" "")))]
480 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
481 operands[0] = force_reg (SImode, operands[0]);
482 ix86_compare_op0 = operands[0];
483 ix86_compare_op1 = operands[1];
487 (define_expand "cmphi"
488 [(set (reg:CC FLAGS_REG)
489 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
490 (match_operand:HI 1 "general_operand" "")))]
493 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
494 operands[0] = force_reg (HImode, operands[0]);
495 ix86_compare_op0 = operands[0];
496 ix86_compare_op1 = operands[1];
500 (define_expand "cmpqi"
501 [(set (reg:CC FLAGS_REG)
502 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
503 (match_operand:QI 1 "general_operand" "")))]
506 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
507 operands[0] = force_reg (QImode, operands[0]);
508 ix86_compare_op0 = operands[0];
509 ix86_compare_op1 = operands[1];
513 (define_insn "cmpdi_ccno_1_rex64"
514 [(set (reg FLAGS_REG)
515 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
516 (match_operand:DI 1 "const0_operand" "n,n")))]
517 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
519 test{q}\t{%0, %0|%0, %0}
520 cmp{q}\t{%1, %0|%0, %1}"
521 [(set_attr "type" "test,icmp")
522 (set_attr "length_immediate" "0,1")
523 (set_attr "mode" "DI")])
525 (define_insn "*cmpdi_minus_1_rex64"
526 [(set (reg FLAGS_REG)
527 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
528 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
530 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
531 "cmp{q}\t{%1, %0|%0, %1}"
532 [(set_attr "type" "icmp")
533 (set_attr "mode" "DI")])
535 (define_expand "cmpdi_1_rex64"
536 [(set (reg:CC FLAGS_REG)
537 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
538 (match_operand:DI 1 "general_operand" "")))]
542 (define_insn "cmpdi_1_insn_rex64"
543 [(set (reg FLAGS_REG)
544 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
545 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
546 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
547 "cmp{q}\t{%1, %0|%0, %1}"
548 [(set_attr "type" "icmp")
549 (set_attr "mode" "DI")])
552 (define_insn "*cmpsi_ccno_1"
553 [(set (reg FLAGS_REG)
554 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
555 (match_operand:SI 1 "const0_operand" "n,n")))]
556 "ix86_match_ccmode (insn, CCNOmode)"
558 test{l}\t{%0, %0|%0, %0}
559 cmp{l}\t{%1, %0|%0, %1}"
560 [(set_attr "type" "test,icmp")
561 (set_attr "length_immediate" "0,1")
562 (set_attr "mode" "SI")])
564 (define_insn "*cmpsi_minus_1"
565 [(set (reg FLAGS_REG)
566 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
567 (match_operand:SI 1 "general_operand" "ri,mr"))
569 "ix86_match_ccmode (insn, CCGOCmode)"
570 "cmp{l}\t{%1, %0|%0, %1}"
571 [(set_attr "type" "icmp")
572 (set_attr "mode" "SI")])
574 (define_expand "cmpsi_1"
575 [(set (reg:CC FLAGS_REG)
576 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
577 (match_operand:SI 1 "general_operand" "ri,mr")))]
581 (define_insn "*cmpsi_1_insn"
582 [(set (reg FLAGS_REG)
583 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
584 (match_operand:SI 1 "general_operand" "ri,mr")))]
585 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
586 && ix86_match_ccmode (insn, CCmode)"
587 "cmp{l}\t{%1, %0|%0, %1}"
588 [(set_attr "type" "icmp")
589 (set_attr "mode" "SI")])
591 (define_insn "*cmphi_ccno_1"
592 [(set (reg FLAGS_REG)
593 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
594 (match_operand:HI 1 "const0_operand" "n,n")))]
595 "ix86_match_ccmode (insn, CCNOmode)"
597 test{w}\t{%0, %0|%0, %0}
598 cmp{w}\t{%1, %0|%0, %1}"
599 [(set_attr "type" "test,icmp")
600 (set_attr "length_immediate" "0,1")
601 (set_attr "mode" "HI")])
603 (define_insn "*cmphi_minus_1"
604 [(set (reg FLAGS_REG)
605 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
606 (match_operand:HI 1 "general_operand" "ri,mr"))
608 "ix86_match_ccmode (insn, CCGOCmode)"
609 "cmp{w}\t{%1, %0|%0, %1}"
610 [(set_attr "type" "icmp")
611 (set_attr "mode" "HI")])
613 (define_insn "*cmphi_1"
614 [(set (reg FLAGS_REG)
615 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
616 (match_operand:HI 1 "general_operand" "ri,mr")))]
617 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
618 && ix86_match_ccmode (insn, CCmode)"
619 "cmp{w}\t{%1, %0|%0, %1}"
620 [(set_attr "type" "icmp")
621 (set_attr "mode" "HI")])
623 (define_insn "*cmpqi_ccno_1"
624 [(set (reg FLAGS_REG)
625 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
626 (match_operand:QI 1 "const0_operand" "n,n")))]
627 "ix86_match_ccmode (insn, CCNOmode)"
629 test{b}\t{%0, %0|%0, %0}
630 cmp{b}\t{$0, %0|%0, 0}"
631 [(set_attr "type" "test,icmp")
632 (set_attr "length_immediate" "0,1")
633 (set_attr "mode" "QI")])
635 (define_insn "*cmpqi_1"
636 [(set (reg FLAGS_REG)
637 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
638 (match_operand:QI 1 "general_operand" "qi,mq")))]
639 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
640 && ix86_match_ccmode (insn, CCmode)"
641 "cmp{b}\t{%1, %0|%0, %1}"
642 [(set_attr "type" "icmp")
643 (set_attr "mode" "QI")])
645 (define_insn "*cmpqi_minus_1"
646 [(set (reg FLAGS_REG)
647 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
648 (match_operand:QI 1 "general_operand" "qi,mq"))
650 "ix86_match_ccmode (insn, CCGOCmode)"
651 "cmp{b}\t{%1, %0|%0, %1}"
652 [(set_attr "type" "icmp")
653 (set_attr "mode" "QI")])
655 (define_insn "*cmpqi_ext_1"
656 [(set (reg FLAGS_REG)
658 (match_operand:QI 0 "general_operand" "Qm")
661 (match_operand 1 "ext_register_operand" "Q")
664 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
665 "cmp{b}\t{%h1, %0|%0, %h1}"
666 [(set_attr "type" "icmp")
667 (set_attr "mode" "QI")])
669 (define_insn "*cmpqi_ext_1_rex64"
670 [(set (reg FLAGS_REG)
672 (match_operand:QI 0 "register_operand" "Q")
675 (match_operand 1 "ext_register_operand" "Q")
678 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
679 "cmp{b}\t{%h1, %0|%0, %h1}"
680 [(set_attr "type" "icmp")
681 (set_attr "mode" "QI")])
683 (define_insn "*cmpqi_ext_2"
684 [(set (reg FLAGS_REG)
688 (match_operand 0 "ext_register_operand" "Q")
691 (match_operand:QI 1 "const0_operand" "n")))]
692 "ix86_match_ccmode (insn, CCNOmode)"
694 [(set_attr "type" "test")
695 (set_attr "length_immediate" "0")
696 (set_attr "mode" "QI")])
698 (define_expand "cmpqi_ext_3"
699 [(set (reg:CC FLAGS_REG)
703 (match_operand 0 "ext_register_operand" "")
706 (match_operand:QI 1 "general_operand" "")))]
710 (define_insn "cmpqi_ext_3_insn"
711 [(set (reg FLAGS_REG)
715 (match_operand 0 "ext_register_operand" "Q")
718 (match_operand:QI 1 "general_operand" "Qmn")))]
719 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
720 "cmp{b}\t{%1, %h0|%h0, %1}"
721 [(set_attr "type" "icmp")
722 (set_attr "mode" "QI")])
724 (define_insn "cmpqi_ext_3_insn_rex64"
725 [(set (reg FLAGS_REG)
729 (match_operand 0 "ext_register_operand" "Q")
732 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
733 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
734 "cmp{b}\t{%1, %h0|%h0, %1}"
735 [(set_attr "type" "icmp")
736 (set_attr "mode" "QI")])
738 (define_insn "*cmpqi_ext_4"
739 [(set (reg FLAGS_REG)
743 (match_operand 0 "ext_register_operand" "Q")
748 (match_operand 1 "ext_register_operand" "Q")
751 "ix86_match_ccmode (insn, CCmode)"
752 "cmp{b}\t{%h1, %h0|%h0, %h1}"
753 [(set_attr "type" "icmp")
754 (set_attr "mode" "QI")])
756 ;; These implement float point compares.
757 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
758 ;; which would allow mix and match FP modes on the compares. Which is what
759 ;; the old patterns did, but with many more of them.
761 (define_expand "cmpxf"
762 [(set (reg:CC FLAGS_REG)
763 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
764 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
767 ix86_compare_op0 = operands[0];
768 ix86_compare_op1 = operands[1];
772 (define_expand "cmpdf"
773 [(set (reg:CC FLAGS_REG)
774 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
775 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
776 "TARGET_80387 || TARGET_SSE2"
778 ix86_compare_op0 = operands[0];
779 ix86_compare_op1 = operands[1];
783 (define_expand "cmpsf"
784 [(set (reg:CC FLAGS_REG)
785 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
786 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
787 "TARGET_80387 || TARGET_SSE"
789 ix86_compare_op0 = operands[0];
790 ix86_compare_op1 = operands[1];
794 ;; FP compares, step 1:
795 ;; Set the FP condition codes.
797 ;; CCFPmode compare with exceptions
798 ;; CCFPUmode compare with no exceptions
800 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
801 ;; used to manage the reg stack popping would not be preserved.
803 (define_insn "*cmpfp_0_sf"
804 [(set (match_operand:HI 0 "register_operand" "=a")
807 (match_operand:SF 1 "register_operand" "f")
808 (match_operand:SF 2 "const0_operand" "X"))]
811 "* return output_fp_compare (insn, operands, 0, 0);"
812 [(set_attr "type" "multi")
813 (set_attr "mode" "SF")])
815 (define_insn "*cmpfp_0_df"
816 [(set (match_operand:HI 0 "register_operand" "=a")
819 (match_operand:DF 1 "register_operand" "f")
820 (match_operand:DF 2 "const0_operand" "X"))]
823 "* return output_fp_compare (insn, operands, 0, 0);"
824 [(set_attr "type" "multi")
825 (set_attr "mode" "DF")])
827 (define_insn "*cmpfp_0_xf"
828 [(set (match_operand:HI 0 "register_operand" "=a")
831 (match_operand:XF 1 "register_operand" "f")
832 (match_operand:XF 2 "const0_operand" "X"))]
835 "* return output_fp_compare (insn, operands, 0, 0);"
836 [(set_attr "type" "multi")
837 (set_attr "mode" "XF")])
839 (define_insn "*cmpfp_sf"
840 [(set (match_operand:HI 0 "register_operand" "=a")
843 (match_operand:SF 1 "register_operand" "f")
844 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
847 "* return output_fp_compare (insn, operands, 0, 0);"
848 [(set_attr "type" "multi")
849 (set_attr "mode" "SF")])
851 (define_insn "*cmpfp_df"
852 [(set (match_operand:HI 0 "register_operand" "=a")
855 (match_operand:DF 1 "register_operand" "f")
856 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
859 "* return output_fp_compare (insn, operands, 0, 0);"
860 [(set_attr "type" "multi")
861 (set_attr "mode" "DF")])
863 (define_insn "*cmpfp_xf"
864 [(set (match_operand:HI 0 "register_operand" "=a")
867 (match_operand:XF 1 "register_operand" "f")
868 (match_operand:XF 2 "register_operand" "f"))]
871 "* return output_fp_compare (insn, operands, 0, 0);"
872 [(set_attr "type" "multi")
873 (set_attr "mode" "XF")])
875 (define_insn "*cmpfp_u"
876 [(set (match_operand:HI 0 "register_operand" "=a")
879 (match_operand 1 "register_operand" "f")
880 (match_operand 2 "register_operand" "f"))]
883 && FLOAT_MODE_P (GET_MODE (operands[1]))
884 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
885 "* return output_fp_compare (insn, operands, 0, 1);"
886 [(set_attr "type" "multi")
888 (cond [(match_operand:SF 1 "" "")
890 (match_operand:DF 1 "" "")
893 (const_string "XF")))])
895 (define_insn "*cmpfp_si"
896 [(set (match_operand:HI 0 "register_operand" "=a")
899 (match_operand 1 "register_operand" "f")
900 (match_operator 3 "float_operator"
901 [(match_operand:SI 2 "memory_operand" "m")]))]
903 "TARGET_80387 && TARGET_USE_FIOP
904 && FLOAT_MODE_P (GET_MODE (operands[1]))
905 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
906 "* return output_fp_compare (insn, operands, 0, 0);"
907 [(set_attr "type" "multi")
908 (set_attr "fp_int_src" "true")
909 (set_attr "mode" "SI")])
911 ;; FP compares, step 2
912 ;; Move the fpsw to ax.
914 (define_insn "x86_fnstsw_1"
915 [(set (match_operand:HI 0 "register_operand" "=a")
916 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
919 [(set_attr "length" "2")
920 (set_attr "mode" "SI")
921 (set_attr "unit" "i387")])
923 ;; FP compares, step 3
924 ;; Get ax into flags, general case.
926 (define_insn "x86_sahf_1"
927 [(set (reg:CC FLAGS_REG)
928 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
931 [(set_attr "length" "1")
932 (set_attr "athlon_decode" "vector")
933 (set_attr "mode" "SI")])
935 ;; Pentium Pro can do steps 1 through 3 in one go.
937 (define_insn "*cmpfp_i"
938 [(set (reg:CCFP FLAGS_REG)
939 (compare:CCFP (match_operand 0 "register_operand" "f")
940 (match_operand 1 "register_operand" "f")))]
941 "TARGET_80387 && TARGET_CMOVE
942 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
943 && FLOAT_MODE_P (GET_MODE (operands[0]))
944 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
945 "* return output_fp_compare (insn, operands, 1, 0);"
946 [(set_attr "type" "fcmp")
948 (cond [(match_operand:SF 1 "" "")
950 (match_operand:DF 1 "" "")
953 (const_string "XF")))
954 (set_attr "athlon_decode" "vector")])
956 (define_insn "*cmpfp_i_sse"
957 [(set (reg:CCFP FLAGS_REG)
958 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
959 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
961 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
962 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
963 "* return output_fp_compare (insn, operands, 1, 0);"
964 [(set_attr "type" "fcmp,ssecomi")
966 (if_then_else (match_operand:SF 1 "" "")
968 (const_string "DF")))
969 (set_attr "athlon_decode" "vector")])
971 (define_insn "*cmpfp_i_sse_only"
972 [(set (reg:CCFP FLAGS_REG)
973 (compare:CCFP (match_operand 0 "register_operand" "x")
974 (match_operand 1 "nonimmediate_operand" "xm")))]
975 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
976 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
977 "* return output_fp_compare (insn, operands, 1, 0);"
978 [(set_attr "type" "ssecomi")
980 (if_then_else (match_operand:SF 1 "" "")
982 (const_string "DF")))
983 (set_attr "athlon_decode" "vector")])
985 (define_insn "*cmpfp_iu"
986 [(set (reg:CCFPU FLAGS_REG)
987 (compare:CCFPU (match_operand 0 "register_operand" "f")
988 (match_operand 1 "register_operand" "f")))]
989 "TARGET_80387 && TARGET_CMOVE
990 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
991 && FLOAT_MODE_P (GET_MODE (operands[0]))
992 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
993 "* return output_fp_compare (insn, operands, 1, 1);"
994 [(set_attr "type" "fcmp")
996 (cond [(match_operand:SF 1 "" "")
998 (match_operand:DF 1 "" "")
1001 (const_string "XF")))
1002 (set_attr "athlon_decode" "vector")])
1004 (define_insn "*cmpfp_iu_sse"
1005 [(set (reg:CCFPU FLAGS_REG)
1006 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1007 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1009 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1010 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1011 "* return output_fp_compare (insn, operands, 1, 1);"
1012 [(set_attr "type" "fcmp,ssecomi")
1014 (if_then_else (match_operand:SF 1 "" "")
1016 (const_string "DF")))
1017 (set_attr "athlon_decode" "vector")])
1019 (define_insn "*cmpfp_iu_sse_only"
1020 [(set (reg:CCFPU FLAGS_REG)
1021 (compare:CCFPU (match_operand 0 "register_operand" "x")
1022 (match_operand 1 "nonimmediate_operand" "xm")))]
1023 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1024 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1025 "* return output_fp_compare (insn, operands, 1, 1);"
1026 [(set_attr "type" "ssecomi")
1028 (if_then_else (match_operand:SF 1 "" "")
1030 (const_string "DF")))
1031 (set_attr "athlon_decode" "vector")])
1033 ;; Move instructions.
1035 ;; General case of fullword move.
1037 (define_expand "movsi"
1038 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1039 (match_operand:SI 1 "general_operand" ""))]
1041 "ix86_expand_move (SImode, operands); DONE;")
1043 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1046 ;; %%% We don't use a post-inc memory reference because x86 is not a
1047 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1048 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1049 ;; targets without our curiosities, and it is just as easy to represent
1050 ;; this differently.
1052 (define_insn "*pushsi2"
1053 [(set (match_operand:SI 0 "push_operand" "=<")
1054 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1057 [(set_attr "type" "push")
1058 (set_attr "mode" "SI")])
1060 ;; For 64BIT abi we always round up to 8 bytes.
1061 (define_insn "*pushsi2_rex64"
1062 [(set (match_operand:SI 0 "push_operand" "=X")
1063 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1066 [(set_attr "type" "push")
1067 (set_attr "mode" "SI")])
1069 (define_insn "*pushsi2_prologue"
1070 [(set (match_operand:SI 0 "push_operand" "=<")
1071 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1072 (clobber (mem:BLK (scratch)))]
1075 [(set_attr "type" "push")
1076 (set_attr "mode" "SI")])
1078 (define_insn "*popsi1_epilogue"
1079 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1080 (mem:SI (reg:SI SP_REG)))
1081 (set (reg:SI SP_REG)
1082 (plus:SI (reg:SI SP_REG) (const_int 4)))
1083 (clobber (mem:BLK (scratch)))]
1086 [(set_attr "type" "pop")
1087 (set_attr "mode" "SI")])
1089 (define_insn "popsi1"
1090 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1091 (mem:SI (reg:SI SP_REG)))
1092 (set (reg:SI SP_REG)
1093 (plus:SI (reg:SI SP_REG) (const_int 4)))]
1096 [(set_attr "type" "pop")
1097 (set_attr "mode" "SI")])
1099 (define_insn "*movsi_xor"
1100 [(set (match_operand:SI 0 "register_operand" "=r")
1101 (match_operand:SI 1 "const0_operand" "i"))
1102 (clobber (reg:CC FLAGS_REG))]
1103 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1104 "xor{l}\t{%0, %0|%0, %0}"
1105 [(set_attr "type" "alu1")
1106 (set_attr "mode" "SI")
1107 (set_attr "length_immediate" "0")])
1109 (define_insn "*movsi_or"
1110 [(set (match_operand:SI 0 "register_operand" "=r")
1111 (match_operand:SI 1 "immediate_operand" "i"))
1112 (clobber (reg:CC FLAGS_REG))]
1114 && operands[1] == constm1_rtx
1115 && (TARGET_PENTIUM || optimize_size)"
1117 operands[1] = constm1_rtx;
1118 return "or{l}\t{%1, %0|%0, %1}";
1120 [(set_attr "type" "alu1")
1121 (set_attr "mode" "SI")
1122 (set_attr "length_immediate" "1")])
1124 (define_insn "*movsi_1"
1125 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1126 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1127 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1128 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1130 switch (get_attr_type (insn))
1133 if (get_attr_mode (insn) == MODE_TI)
1134 return "movdqa\t{%1, %0|%0, %1}";
1135 return "movd\t{%1, %0|%0, %1}";
1138 if (get_attr_mode (insn) == MODE_DI)
1139 return "movq\t{%1, %0|%0, %1}";
1140 return "movd\t{%1, %0|%0, %1}";
1143 return "lea{l}\t{%1, %0|%0, %1}";
1146 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1148 return "mov{l}\t{%1, %0|%0, %1}";
1152 (cond [(eq_attr "alternative" "2,3,4")
1153 (const_string "mmxmov")
1154 (eq_attr "alternative" "5,6,7")
1155 (const_string "ssemov")
1156 (and (ne (symbol_ref "flag_pic") (const_int 0))
1157 (match_operand:SI 1 "symbolic_operand" ""))
1158 (const_string "lea")
1160 (const_string "imov")))
1161 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1163 (define_insn "*movsi_1_nointernunit"
1164 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1165 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1166 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1167 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1169 switch (get_attr_type (insn))
1172 if (get_attr_mode (insn) == MODE_TI)
1173 return "movdqa\t{%1, %0|%0, %1}";
1174 return "movd\t{%1, %0|%0, %1}";
1177 if (get_attr_mode (insn) == MODE_DI)
1178 return "movq\t{%1, %0|%0, %1}";
1179 return "movd\t{%1, %0|%0, %1}";
1182 return "lea{l}\t{%1, %0|%0, %1}";
1185 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1187 return "mov{l}\t{%1, %0|%0, %1}";
1191 (cond [(eq_attr "alternative" "2,3,4")
1192 (const_string "mmxmov")
1193 (eq_attr "alternative" "5,6,7")
1194 (const_string "ssemov")
1195 (and (ne (symbol_ref "flag_pic") (const_int 0))
1196 (match_operand:SI 1 "symbolic_operand" ""))
1197 (const_string "lea")
1199 (const_string "imov")))
1200 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1202 ;; Stores and loads of ax to arbitrary constant address.
1203 ;; We fake an second form of instruction to force reload to load address
1204 ;; into register when rax is not available
1205 (define_insn "*movabssi_1_rex64"
1206 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1207 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1208 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1210 movabs{l}\t{%1, %P0|%P0, %1}
1211 mov{l}\t{%1, %a0|%a0, %1}"
1212 [(set_attr "type" "imov")
1213 (set_attr "modrm" "0,*")
1214 (set_attr "length_address" "8,0")
1215 (set_attr "length_immediate" "0,*")
1216 (set_attr "memory" "store")
1217 (set_attr "mode" "SI")])
1219 (define_insn "*movabssi_2_rex64"
1220 [(set (match_operand:SI 0 "register_operand" "=a,r")
1221 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1222 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1224 movabs{l}\t{%P1, %0|%0, %P1}
1225 mov{l}\t{%a1, %0|%0, %a1}"
1226 [(set_attr "type" "imov")
1227 (set_attr "modrm" "0,*")
1228 (set_attr "length_address" "8,0")
1229 (set_attr "length_immediate" "0")
1230 (set_attr "memory" "load")
1231 (set_attr "mode" "SI")])
1233 (define_insn "*swapsi"
1234 [(set (match_operand:SI 0 "register_operand" "+r")
1235 (match_operand:SI 1 "register_operand" "+r"))
1240 [(set_attr "type" "imov")
1241 (set_attr "pent_pair" "np")
1242 (set_attr "athlon_decode" "vector")
1243 (set_attr "mode" "SI")
1244 (set_attr "modrm" "0")])
1246 (define_expand "movhi"
1247 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1248 (match_operand:HI 1 "general_operand" ""))]
1250 "ix86_expand_move (HImode, operands); DONE;")
1252 (define_insn "*pushhi2"
1253 [(set (match_operand:HI 0 "push_operand" "=<,<")
1254 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1257 push{w}\t{|WORD PTR }%1
1259 [(set_attr "type" "push")
1260 (set_attr "mode" "HI")])
1262 ;; For 64BIT abi we always round up to 8 bytes.
1263 (define_insn "*pushhi2_rex64"
1264 [(set (match_operand:HI 0 "push_operand" "=X")
1265 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1268 [(set_attr "type" "push")
1269 (set_attr "mode" "QI")])
1271 (define_insn "*movhi_1"
1272 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1273 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1274 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1276 switch (get_attr_type (insn))
1279 /* movzwl is faster than movw on p2 due to partial word stalls,
1280 though not as fast as an aligned movl. */
1281 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1283 if (get_attr_mode (insn) == MODE_SI)
1284 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1286 return "mov{w}\t{%1, %0|%0, %1}";
1290 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1291 (const_string "imov")
1292 (and (eq_attr "alternative" "0")
1293 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1295 (eq (symbol_ref "TARGET_HIMODE_MATH")
1297 (const_string "imov")
1298 (and (eq_attr "alternative" "1,2")
1299 (match_operand:HI 1 "aligned_operand" ""))
1300 (const_string "imov")
1301 (and (ne (symbol_ref "TARGET_MOVX")
1303 (eq_attr "alternative" "0,2"))
1304 (const_string "imovx")
1306 (const_string "imov")))
1308 (cond [(eq_attr "type" "imovx")
1310 (and (eq_attr "alternative" "1,2")
1311 (match_operand:HI 1 "aligned_operand" ""))
1313 (and (eq_attr "alternative" "0")
1314 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1316 (eq (symbol_ref "TARGET_HIMODE_MATH")
1320 (const_string "HI")))])
1322 ;; Stores and loads of ax to arbitrary constant address.
1323 ;; We fake an second form of instruction to force reload to load address
1324 ;; into register when rax is not available
1325 (define_insn "*movabshi_1_rex64"
1326 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1327 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1328 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1330 movabs{w}\t{%1, %P0|%P0, %1}
1331 mov{w}\t{%1, %a0|%a0, %1}"
1332 [(set_attr "type" "imov")
1333 (set_attr "modrm" "0,*")
1334 (set_attr "length_address" "8,0")
1335 (set_attr "length_immediate" "0,*")
1336 (set_attr "memory" "store")
1337 (set_attr "mode" "HI")])
1339 (define_insn "*movabshi_2_rex64"
1340 [(set (match_operand:HI 0 "register_operand" "=a,r")
1341 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1342 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1344 movabs{w}\t{%P1, %0|%0, %P1}
1345 mov{w}\t{%a1, %0|%0, %a1}"
1346 [(set_attr "type" "imov")
1347 (set_attr "modrm" "0,*")
1348 (set_attr "length_address" "8,0")
1349 (set_attr "length_immediate" "0")
1350 (set_attr "memory" "load")
1351 (set_attr "mode" "HI")])
1353 (define_insn "*swaphi_1"
1354 [(set (match_operand:HI 0 "register_operand" "+r")
1355 (match_operand:HI 1 "register_operand" "+r"))
1358 "TARGET_PARTIAL_REG_STALL"
1360 [(set_attr "type" "imov")
1361 (set_attr "pent_pair" "np")
1362 (set_attr "mode" "HI")
1363 (set_attr "modrm" "0")])
1365 (define_insn "*swaphi_2"
1366 [(set (match_operand:HI 0 "register_operand" "+r")
1367 (match_operand:HI 1 "register_operand" "+r"))
1370 "! TARGET_PARTIAL_REG_STALL"
1372 [(set_attr "type" "imov")
1373 (set_attr "pent_pair" "np")
1374 (set_attr "mode" "SI")
1375 (set_attr "modrm" "0")])
1377 (define_expand "movstricthi"
1378 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1379 (match_operand:HI 1 "general_operand" ""))]
1380 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1382 /* Don't generate memory->memory moves, go through a register */
1383 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1384 operands[1] = force_reg (HImode, operands[1]);
1387 (define_insn "*movstricthi_1"
1388 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1389 (match_operand:HI 1 "general_operand" "rn,m"))]
1390 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1391 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1392 "mov{w}\t{%1, %0|%0, %1}"
1393 [(set_attr "type" "imov")
1394 (set_attr "mode" "HI")])
1396 (define_insn "*movstricthi_xor"
1397 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1398 (match_operand:HI 1 "const0_operand" "i"))
1399 (clobber (reg:CC FLAGS_REG))]
1401 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1402 "xor{w}\t{%0, %0|%0, %0}"
1403 [(set_attr "type" "alu1")
1404 (set_attr "mode" "HI")
1405 (set_attr "length_immediate" "0")])
1407 (define_expand "movqi"
1408 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1409 (match_operand:QI 1 "general_operand" ""))]
1411 "ix86_expand_move (QImode, operands); DONE;")
1413 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1414 ;; "push a byte". But actually we use pushw, which has the effect
1415 ;; of rounding the amount pushed up to a halfword.
1417 (define_insn "*pushqi2"
1418 [(set (match_operand:QI 0 "push_operand" "=X,X")
1419 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1422 push{w}\t{|word ptr }%1
1424 [(set_attr "type" "push")
1425 (set_attr "mode" "HI")])
1427 ;; For 64BIT abi we always round up to 8 bytes.
1428 (define_insn "*pushqi2_rex64"
1429 [(set (match_operand:QI 0 "push_operand" "=X")
1430 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1433 [(set_attr "type" "push")
1434 (set_attr "mode" "QI")])
1436 ;; Situation is quite tricky about when to choose full sized (SImode) move
1437 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1438 ;; partial register dependency machines (such as AMD Athlon), where QImode
1439 ;; moves issue extra dependency and for partial register stalls machines
1440 ;; that don't use QImode patterns (and QImode move cause stall on the next
1443 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1444 ;; register stall machines with, where we use QImode instructions, since
1445 ;; partial register stall can be caused there. Then we use movzx.
1446 (define_insn "*movqi_1"
1447 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1448 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1449 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1451 switch (get_attr_type (insn))
1454 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1456 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1458 if (get_attr_mode (insn) == MODE_SI)
1459 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1461 return "mov{b}\t{%1, %0|%0, %1}";
1465 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1466 (const_string "imov")
1467 (and (eq_attr "alternative" "3")
1468 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1470 (eq (symbol_ref "TARGET_QIMODE_MATH")
1472 (const_string "imov")
1473 (eq_attr "alternative" "3,5")
1474 (const_string "imovx")
1475 (and (ne (symbol_ref "TARGET_MOVX")
1477 (eq_attr "alternative" "2"))
1478 (const_string "imovx")
1480 (const_string "imov")))
1482 (cond [(eq_attr "alternative" "3,4,5")
1484 (eq_attr "alternative" "6")
1486 (eq_attr "type" "imovx")
1488 (and (eq_attr "type" "imov")
1489 (and (eq_attr "alternative" "0,1,2")
1490 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1493 ;; Avoid partial register stalls when not using QImode arithmetic
1494 (and (eq_attr "type" "imov")
1495 (and (eq_attr "alternative" "0,1,2")
1496 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1498 (eq (symbol_ref "TARGET_QIMODE_MATH")
1502 (const_string "QI")))])
1504 (define_expand "reload_outqi"
1505 [(parallel [(match_operand:QI 0 "" "=m")
1506 (match_operand:QI 1 "register_operand" "r")
1507 (match_operand:QI 2 "register_operand" "=&q")])]
1511 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1513 if (reg_overlap_mentioned_p (op2, op0))
1515 if (! q_regs_operand (op1, QImode))
1517 emit_insn (gen_movqi (op2, op1));
1520 emit_insn (gen_movqi (op0, op1));
1524 (define_insn "*swapqi"
1525 [(set (match_operand:QI 0 "register_operand" "+r")
1526 (match_operand:QI 1 "register_operand" "+r"))
1531 [(set_attr "type" "imov")
1532 (set_attr "pent_pair" "np")
1533 (set_attr "mode" "QI")
1534 (set_attr "modrm" "0")])
1536 (define_expand "movstrictqi"
1537 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1538 (match_operand:QI 1 "general_operand" ""))]
1539 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1541 /* Don't generate memory->memory moves, go through a register. */
1542 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1543 operands[1] = force_reg (QImode, operands[1]);
1546 (define_insn "*movstrictqi_1"
1547 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1548 (match_operand:QI 1 "general_operand" "*qn,m"))]
1549 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1550 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1551 "mov{b}\t{%1, %0|%0, %1}"
1552 [(set_attr "type" "imov")
1553 (set_attr "mode" "QI")])
1555 (define_insn "*movstrictqi_xor"
1556 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1557 (match_operand:QI 1 "const0_operand" "i"))
1558 (clobber (reg:CC FLAGS_REG))]
1559 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1560 "xor{b}\t{%0, %0|%0, %0}"
1561 [(set_attr "type" "alu1")
1562 (set_attr "mode" "QI")
1563 (set_attr "length_immediate" "0")])
1565 (define_insn "*movsi_extv_1"
1566 [(set (match_operand:SI 0 "register_operand" "=R")
1567 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1571 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1572 [(set_attr "type" "imovx")
1573 (set_attr "mode" "SI")])
1575 (define_insn "*movhi_extv_1"
1576 [(set (match_operand:HI 0 "register_operand" "=R")
1577 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1581 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1582 [(set_attr "type" "imovx")
1583 (set_attr "mode" "SI")])
1585 (define_insn "*movqi_extv_1"
1586 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1587 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1592 switch (get_attr_type (insn))
1595 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1597 return "mov{b}\t{%h1, %0|%0, %h1}";
1601 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1602 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1603 (ne (symbol_ref "TARGET_MOVX")
1605 (const_string "imovx")
1606 (const_string "imov")))
1608 (if_then_else (eq_attr "type" "imovx")
1610 (const_string "QI")))])
1612 (define_insn "*movqi_extv_1_rex64"
1613 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1614 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1619 switch (get_attr_type (insn))
1622 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1624 return "mov{b}\t{%h1, %0|%0, %h1}";
1628 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1629 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1630 (ne (symbol_ref "TARGET_MOVX")
1632 (const_string "imovx")
1633 (const_string "imov")))
1635 (if_then_else (eq_attr "type" "imovx")
1637 (const_string "QI")))])
1639 ;; Stores and loads of ax to arbitrary constant address.
1640 ;; We fake an second form of instruction to force reload to load address
1641 ;; into register when rax is not available
1642 (define_insn "*movabsqi_1_rex64"
1643 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1644 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1645 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1647 movabs{b}\t{%1, %P0|%P0, %1}
1648 mov{b}\t{%1, %a0|%a0, %1}"
1649 [(set_attr "type" "imov")
1650 (set_attr "modrm" "0,*")
1651 (set_attr "length_address" "8,0")
1652 (set_attr "length_immediate" "0,*")
1653 (set_attr "memory" "store")
1654 (set_attr "mode" "QI")])
1656 (define_insn "*movabsqi_2_rex64"
1657 [(set (match_operand:QI 0 "register_operand" "=a,r")
1658 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1659 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1661 movabs{b}\t{%P1, %0|%0, %P1}
1662 mov{b}\t{%a1, %0|%0, %a1}"
1663 [(set_attr "type" "imov")
1664 (set_attr "modrm" "0,*")
1665 (set_attr "length_address" "8,0")
1666 (set_attr "length_immediate" "0")
1667 (set_attr "memory" "load")
1668 (set_attr "mode" "QI")])
1670 (define_insn "*movsi_extzv_1"
1671 [(set (match_operand:SI 0 "register_operand" "=R")
1672 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1676 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1677 [(set_attr "type" "imovx")
1678 (set_attr "mode" "SI")])
1680 (define_insn "*movqi_extzv_2"
1681 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1682 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1687 switch (get_attr_type (insn))
1690 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1692 return "mov{b}\t{%h1, %0|%0, %h1}";
1696 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1697 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1698 (ne (symbol_ref "TARGET_MOVX")
1700 (const_string "imovx")
1701 (const_string "imov")))
1703 (if_then_else (eq_attr "type" "imovx")
1705 (const_string "QI")))])
1707 (define_insn "*movqi_extzv_2_rex64"
1708 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1709 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1714 switch (get_attr_type (insn))
1717 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1719 return "mov{b}\t{%h1, %0|%0, %h1}";
1723 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1724 (ne (symbol_ref "TARGET_MOVX")
1726 (const_string "imovx")
1727 (const_string "imov")))
1729 (if_then_else (eq_attr "type" "imovx")
1731 (const_string "QI")))])
1733 (define_insn "movsi_insv_1"
1734 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1737 (match_operand:SI 1 "general_operand" "Qmn"))]
1739 "mov{b}\t{%b1, %h0|%h0, %b1}"
1740 [(set_attr "type" "imov")
1741 (set_attr "mode" "QI")])
1743 (define_insn "movdi_insv_1_rex64"
1744 [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
1747 (match_operand:DI 1 "nonmemory_operand" "Qn"))]
1749 "mov{b}\t{%b1, %h0|%h0, %b1}"
1750 [(set_attr "type" "imov")
1751 (set_attr "mode" "QI")])
1753 (define_insn "*movqi_insv_2"
1754 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1757 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1760 "mov{b}\t{%h1, %h0|%h0, %h1}"
1761 [(set_attr "type" "imov")
1762 (set_attr "mode" "QI")])
1764 (define_expand "movdi"
1765 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1766 (match_operand:DI 1 "general_operand" ""))]
1768 "ix86_expand_move (DImode, operands); DONE;")
1770 (define_insn "*pushdi"
1771 [(set (match_operand:DI 0 "push_operand" "=<")
1772 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1776 (define_insn "pushdi2_rex64"
1777 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1778 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1783 [(set_attr "type" "push,multi")
1784 (set_attr "mode" "DI")])
1786 ;; Convert impossible pushes of immediate to existing instructions.
1787 ;; First try to get scratch register and go through it. In case this
1788 ;; fails, push sign extended lower part first and then overwrite
1789 ;; upper part by 32bit move.
1791 [(match_scratch:DI 2 "r")
1792 (set (match_operand:DI 0 "push_operand" "")
1793 (match_operand:DI 1 "immediate_operand" ""))]
1794 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1795 && !x86_64_immediate_operand (operands[1], DImode)"
1796 [(set (match_dup 2) (match_dup 1))
1797 (set (match_dup 0) (match_dup 2))]
1800 ;; We need to define this as both peepholer and splitter for case
1801 ;; peephole2 pass is not run.
1802 ;; "&& 1" is needed to keep it from matching the previous pattern.
1804 [(set (match_operand:DI 0 "push_operand" "")
1805 (match_operand:DI 1 "immediate_operand" ""))]
1806 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1807 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1808 [(set (match_dup 0) (match_dup 1))
1809 (set (match_dup 2) (match_dup 3))]
1810 "split_di (operands + 1, 1, operands + 2, operands + 3);
1811 operands[1] = gen_lowpart (DImode, operands[2]);
1812 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1817 [(set (match_operand:DI 0 "push_operand" "")
1818 (match_operand:DI 1 "immediate_operand" ""))]
1819 "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
1820 && !symbolic_operand (operands[1], DImode)
1821 && !x86_64_immediate_operand (operands[1], DImode)"
1822 [(set (match_dup 0) (match_dup 1))
1823 (set (match_dup 2) (match_dup 3))]
1824 "split_di (operands + 1, 1, operands + 2, operands + 3);
1825 operands[1] = gen_lowpart (DImode, operands[2]);
1826 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1830 (define_insn "*pushdi2_prologue_rex64"
1831 [(set (match_operand:DI 0 "push_operand" "=<")
1832 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1833 (clobber (mem:BLK (scratch)))]
1836 [(set_attr "type" "push")
1837 (set_attr "mode" "DI")])
1839 (define_insn "*popdi1_epilogue_rex64"
1840 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1841 (mem:DI (reg:DI SP_REG)))
1842 (set (reg:DI SP_REG)
1843 (plus:DI (reg:DI SP_REG) (const_int 8)))
1844 (clobber (mem:BLK (scratch)))]
1847 [(set_attr "type" "pop")
1848 (set_attr "mode" "DI")])
1850 (define_insn "popdi1"
1851 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1852 (mem:DI (reg:DI SP_REG)))
1853 (set (reg:DI SP_REG)
1854 (plus:DI (reg:DI SP_REG) (const_int 8)))]
1857 [(set_attr "type" "pop")
1858 (set_attr "mode" "DI")])
1860 (define_insn "*movdi_xor_rex64"
1861 [(set (match_operand:DI 0 "register_operand" "=r")
1862 (match_operand:DI 1 "const0_operand" "i"))
1863 (clobber (reg:CC FLAGS_REG))]
1864 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1865 && reload_completed"
1866 "xor{l}\t{%k0, %k0|%k0, %k0}"
1867 [(set_attr "type" "alu1")
1868 (set_attr "mode" "SI")
1869 (set_attr "length_immediate" "0")])
1871 (define_insn "*movdi_or_rex64"
1872 [(set (match_operand:DI 0 "register_operand" "=r")
1873 (match_operand:DI 1 "const_int_operand" "i"))
1874 (clobber (reg:CC FLAGS_REG))]
1875 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1877 && operands[1] == constm1_rtx"
1879 operands[1] = constm1_rtx;
1880 return "or{q}\t{%1, %0|%0, %1}";
1882 [(set_attr "type" "alu1")
1883 (set_attr "mode" "DI")
1884 (set_attr "length_immediate" "1")])
1886 (define_insn "*movdi_2"
1887 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1888 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1890 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1894 movq\t{%1, %0|%0, %1}
1895 movq\t{%1, %0|%0, %1}
1896 movq\t{%1, %0|%0, %1}
1897 movdqa\t{%1, %0|%0, %1}
1898 movq\t{%1, %0|%0, %1}"
1899 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1900 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1903 [(set (match_operand:DI 0 "push_operand" "")
1904 (match_operand:DI 1 "general_operand" ""))]
1905 "!TARGET_64BIT && reload_completed
1906 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1908 "ix86_split_long_move (operands); DONE;")
1910 ;; %%% This multiword shite has got to go.
1912 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1913 (match_operand:DI 1 "general_operand" ""))]
1914 "!TARGET_64BIT && reload_completed
1915 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1916 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1918 "ix86_split_long_move (operands); DONE;")
1920 (define_insn "*movdi_1_rex64"
1921 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y,!*Y,!*y")
1922 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm,*y,*Y"))]
1924 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1925 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1927 switch (get_attr_type (insn))
1930 if (which_alternative == 11)
1931 return "movq2dq\t{%1, %0|%0, %1}";
1933 return "movdq2q\t{%1, %0|%0, %1}";
1935 if (get_attr_mode (insn) == MODE_TI)
1936 return "movdqa\t{%1, %0|%0, %1}";
1939 /* Moves from and into integer register is done using movd opcode with
1941 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1942 return "movd\t{%1, %0|%0, %1}";
1943 return "movq\t{%1, %0|%0, %1}";
1947 return "lea{q}\t{%a1, %0|%0, %a1}";
1949 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1951 if (get_attr_mode (insn) == MODE_SI)
1952 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1953 else if (which_alternative == 2)
1954 return "movabs{q}\t{%1, %0|%0, %1}";
1956 return "mov{q}\t{%1, %0|%0, %1}";
1960 (cond [(eq_attr "alternative" "5,6,7")
1961 (const_string "mmxmov")
1962 (eq_attr "alternative" "8,9,10")
1963 (const_string "ssemov")
1964 (eq_attr "alternative" "11,12")
1965 (const_string "ssecvt")
1966 (eq_attr "alternative" "4")
1967 (const_string "multi")
1968 (and (ne (symbol_ref "flag_pic") (const_int 0))
1969 (match_operand:DI 1 "symbolic_operand" ""))
1970 (const_string "lea")
1972 (const_string "imov")))
1973 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*")
1974 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*")
1975 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI,DI,DI")])
1977 (define_insn "*movdi_1_rex64_nointerunit"
1978 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
1979 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
1981 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
1982 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1984 switch (get_attr_type (insn))
1987 if (get_attr_mode (insn) == MODE_TI)
1988 return "movdqa\t{%1, %0|%0, %1}";
1991 return "movq\t{%1, %0|%0, %1}";
1995 return "lea{q}\t{%a1, %0|%0, %a1}";
1997 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1999 if (get_attr_mode (insn) == MODE_SI)
2000 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2001 else if (which_alternative == 2)
2002 return "movabs{q}\t{%1, %0|%0, %1}";
2004 return "mov{q}\t{%1, %0|%0, %1}";
2008 (cond [(eq_attr "alternative" "5,6,7")
2009 (const_string "mmxmov")
2010 (eq_attr "alternative" "8,9,10")
2011 (const_string "ssemov")
2012 (eq_attr "alternative" "4")
2013 (const_string "multi")
2014 (and (ne (symbol_ref "flag_pic") (const_int 0))
2015 (match_operand:DI 1 "symbolic_operand" ""))
2016 (const_string "lea")
2018 (const_string "imov")))
2019 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2020 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2021 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2023 ;; Stores and loads of ax to arbitrary constant address.
2024 ;; We fake an second form of instruction to force reload to load address
2025 ;; into register when rax is not available
2026 (define_insn "*movabsdi_1_rex64"
2027 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2028 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2029 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2031 movabs{q}\t{%1, %P0|%P0, %1}
2032 mov{q}\t{%1, %a0|%a0, %1}"
2033 [(set_attr "type" "imov")
2034 (set_attr "modrm" "0,*")
2035 (set_attr "length_address" "8,0")
2036 (set_attr "length_immediate" "0,*")
2037 (set_attr "memory" "store")
2038 (set_attr "mode" "DI")])
2040 (define_insn "*movabsdi_2_rex64"
2041 [(set (match_operand:DI 0 "register_operand" "=a,r")
2042 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2043 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2045 movabs{q}\t{%P1, %0|%0, %P1}
2046 mov{q}\t{%a1, %0|%0, %a1}"
2047 [(set_attr "type" "imov")
2048 (set_attr "modrm" "0,*")
2049 (set_attr "length_address" "8,0")
2050 (set_attr "length_immediate" "0")
2051 (set_attr "memory" "load")
2052 (set_attr "mode" "DI")])
2054 ;; Convert impossible stores of immediate to existing instructions.
2055 ;; First try to get scratch register and go through it. In case this
2056 ;; fails, move by 32bit parts.
2058 [(match_scratch:DI 2 "r")
2059 (set (match_operand:DI 0 "memory_operand" "")
2060 (match_operand:DI 1 "immediate_operand" ""))]
2061 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2062 && !x86_64_immediate_operand (operands[1], DImode)"
2063 [(set (match_dup 2) (match_dup 1))
2064 (set (match_dup 0) (match_dup 2))]
2067 ;; We need to define this as both peepholer and splitter for case
2068 ;; peephole2 pass is not run.
2069 ;; "&& 1" is needed to keep it from matching the previous pattern.
2071 [(set (match_operand:DI 0 "memory_operand" "")
2072 (match_operand:DI 1 "immediate_operand" ""))]
2073 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2074 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2075 [(set (match_dup 2) (match_dup 3))
2076 (set (match_dup 4) (match_dup 5))]
2077 "split_di (operands, 2, operands + 2, operands + 4);")
2080 [(set (match_operand:DI 0 "memory_operand" "")
2081 (match_operand:DI 1 "immediate_operand" ""))]
2082 "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
2083 && !symbolic_operand (operands[1], DImode)
2084 && !x86_64_immediate_operand (operands[1], DImode)"
2085 [(set (match_dup 2) (match_dup 3))
2086 (set (match_dup 4) (match_dup 5))]
2087 "split_di (operands, 2, operands + 2, operands + 4);")
2089 (define_insn "*swapdi_rex64"
2090 [(set (match_operand:DI 0 "register_operand" "+r")
2091 (match_operand:DI 1 "register_operand" "+r"))
2096 [(set_attr "type" "imov")
2097 (set_attr "pent_pair" "np")
2098 (set_attr "athlon_decode" "vector")
2099 (set_attr "mode" "DI")
2100 (set_attr "modrm" "0")])
2103 (define_expand "movsf"
2104 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2105 (match_operand:SF 1 "general_operand" ""))]
2107 "ix86_expand_move (SFmode, operands); DONE;")
2109 (define_insn "*pushsf"
2110 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2111 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2114 switch (which_alternative)
2117 return "push{l}\t%1";
2120 /* This insn should be already split before reg-stack. */
2124 [(set_attr "type" "multi,push,multi")
2125 (set_attr "mode" "SF,SI,SF")])
2127 (define_insn "*pushsf_rex64"
2128 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2129 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2132 switch (which_alternative)
2135 return "push{q}\t%q1";
2138 /* This insn should be already split before reg-stack. */
2142 [(set_attr "type" "multi,push,multi")
2143 (set_attr "mode" "SF,DI,SF")])
2146 [(set (match_operand:SF 0 "push_operand" "")
2147 (match_operand:SF 1 "memory_operand" ""))]
2149 && GET_CODE (operands[1]) == MEM
2150 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2151 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2154 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2157 ;; %%% Kill this when call knows how to work this out.
2159 [(set (match_operand:SF 0 "push_operand" "")
2160 (match_operand:SF 1 "any_fp_register_operand" ""))]
2162 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
2163 (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])
2166 [(set (match_operand:SF 0 "push_operand" "")
2167 (match_operand:SF 1 "any_fp_register_operand" ""))]
2169 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2170 (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
2172 (define_insn "*movsf_1"
2173 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2174 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2175 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2176 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2177 && (reload_in_progress || reload_completed
2178 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2179 || GET_CODE (operands[1]) != CONST_DOUBLE
2180 || memory_operand (operands[0], SFmode))"
2182 switch (which_alternative)
2185 return output_387_reg_move (insn, operands);
2188 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2189 return "fstp%z0\t%y0";
2191 return "fst%z0\t%y0";
2194 return standard_80387_constant_opcode (operands[1]);
2198 return "mov{l}\t{%1, %0|%0, %1}";
2200 if (get_attr_mode (insn) == MODE_TI)
2201 return "pxor\t%0, %0";
2203 return "xorps\t%0, %0";
2205 if (get_attr_mode (insn) == MODE_V4SF)
2206 return "movaps\t{%1, %0|%0, %1}";
2208 return "movss\t{%1, %0|%0, %1}";
2211 return "movss\t{%1, %0|%0, %1}";
2215 return "movd\t{%1, %0|%0, %1}";
2218 return "movq\t{%1, %0|%0, %1}";
2224 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2226 (cond [(eq_attr "alternative" "3,4,9,10")
2228 (eq_attr "alternative" "5")
2230 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2232 (ne (symbol_ref "TARGET_SSE2")
2234 (eq (symbol_ref "optimize_size")
2237 (const_string "V4SF"))
2238 /* For architectures resolving dependencies on
2239 whole SSE registers use APS move to break dependency
2240 chains, otherwise use short move to avoid extra work.
2242 Do the same for architectures resolving dependencies on
2243 the parts. While in DF mode it is better to always handle
2244 just register parts, the SF mode is different due to lack
2245 of instructions to load just part of the register. It is
2246 better to maintain the whole registers in single format
2247 to avoid problems on using packed logical operations. */
2248 (eq_attr "alternative" "6")
2250 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2252 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2254 (const_string "V4SF")
2255 (const_string "SF"))
2256 (eq_attr "alternative" "11")
2257 (const_string "DI")]
2258 (const_string "SF")))])
2260 (define_insn "*movsf_1_nointerunit"
2261 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2262 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2263 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2264 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2265 && (reload_in_progress || reload_completed
2266 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2267 || GET_CODE (operands[1]) != CONST_DOUBLE
2268 || memory_operand (operands[0], SFmode))"
2270 switch (which_alternative)
2273 return output_387_reg_move (insn, operands);
2276 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2277 return "fstp%z0\t%y0";
2279 return "fst%z0\t%y0";
2282 return standard_80387_constant_opcode (operands[1]);
2286 return "mov{l}\t{%1, %0|%0, %1}";
2288 if (get_attr_mode (insn) == MODE_TI)
2289 return "pxor\t%0, %0";
2291 return "xorps\t%0, %0";
2293 if (get_attr_mode (insn) == MODE_V4SF)
2294 return "movaps\t{%1, %0|%0, %1}";
2296 return "movss\t{%1, %0|%0, %1}";
2299 return "movss\t{%1, %0|%0, %1}";
2303 return "movd\t{%1, %0|%0, %1}";
2306 return "movq\t{%1, %0|%0, %1}";
2312 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2314 (cond [(eq_attr "alternative" "3,4,9,10")
2316 (eq_attr "alternative" "5")
2318 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2320 (ne (symbol_ref "TARGET_SSE2")
2322 (eq (symbol_ref "optimize_size")
2325 (const_string "V4SF"))
2326 /* For architectures resolving dependencies on
2327 whole SSE registers use APS move to break dependency
2328 chains, otherwise use short move to avoid extra work.
2330 Do the same for architectures resolving dependencies on
2331 the parts. While in DF mode it is better to always handle
2332 just register parts, the SF mode is different due to lack
2333 of instructions to load just part of the register. It is
2334 better to maintain the whole registers in single format
2335 to avoid problems on using packed logical operations. */
2336 (eq_attr "alternative" "6")
2338 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2340 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2342 (const_string "V4SF")
2343 (const_string "SF"))
2344 (eq_attr "alternative" "11")
2345 (const_string "DI")]
2346 (const_string "SF")))])
2348 (define_insn "*swapsf"
2349 [(set (match_operand:SF 0 "register_operand" "+f")
2350 (match_operand:SF 1 "register_operand" "+f"))
2353 "reload_completed || !TARGET_SSE"
2355 if (STACK_TOP_P (operands[0]))
2360 [(set_attr "type" "fxch")
2361 (set_attr "mode" "SF")])
2363 (define_expand "movdf"
2364 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2365 (match_operand:DF 1 "general_operand" ""))]
2367 "ix86_expand_move (DFmode, operands); DONE;")
2369 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2370 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2371 ;; On the average, pushdf using integers can be still shorter. Allow this
2372 ;; pattern for optimize_size too.
2374 (define_insn "*pushdf_nointeger"
2375 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2376 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2377 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2379 /* This insn should be already split before reg-stack. */
2382 [(set_attr "type" "multi")
2383 (set_attr "mode" "DF,SI,SI,DF")])
2385 (define_insn "*pushdf_integer"
2386 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2387 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2388 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2390 /* This insn should be already split before reg-stack. */
2393 [(set_attr "type" "multi")
2394 (set_attr "mode" "DF,SI,DF")])
2396 ;; %%% Kill this when call knows how to work this out.
2398 [(set (match_operand:DF 0 "push_operand" "")
2399 (match_operand:DF 1 "any_fp_register_operand" ""))]
2400 "!TARGET_64BIT && reload_completed"
2401 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
2402 (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
2406 [(set (match_operand:DF 0 "push_operand" "")
2407 (match_operand:DF 1 "any_fp_register_operand" ""))]
2408 "TARGET_64BIT && reload_completed"
2409 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2410 (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
2414 [(set (match_operand:DF 0 "push_operand" "")
2415 (match_operand:DF 1 "general_operand" ""))]
2418 "ix86_split_long_move (operands); DONE;")
2420 ;; Moving is usually shorter when only FP registers are used. This separate
2421 ;; movdf pattern avoids the use of integer registers for FP operations
2422 ;; when optimizing for size.
2424 (define_insn "*movdf_nointeger"
2425 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2426 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2427 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2428 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2429 && (reload_in_progress || reload_completed
2430 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2431 || GET_CODE (operands[1]) != CONST_DOUBLE
2432 || memory_operand (operands[0], DFmode))"
2434 switch (which_alternative)
2437 return output_387_reg_move (insn, operands);
2440 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2441 return "fstp%z0\t%y0";
2443 return "fst%z0\t%y0";
2446 return standard_80387_constant_opcode (operands[1]);
2452 switch (get_attr_mode (insn))
2455 return "xorps\t%0, %0";
2457 return "xorpd\t%0, %0";
2459 return "pxor\t%0, %0";
2464 switch (get_attr_mode (insn))
2467 return "movaps\t{%1, %0|%0, %1}";
2469 return "movapd\t{%1, %0|%0, %1}";
2471 return "movsd\t{%1, %0|%0, %1}";
2476 if (get_attr_mode (insn) == MODE_V2DF)
2477 return "movlpd\t{%1, %0|%0, %1}";
2479 return "movsd\t{%1, %0|%0, %1}";
2481 return "movsd\t{%1, %0|%0, %1}";
2487 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2489 (cond [(eq_attr "alternative" "3,4")
2491 /* xorps is one byte shorter. */
2492 (eq_attr "alternative" "5")
2493 (cond [(ne (symbol_ref "optimize_size")
2495 (const_string "V4SF")
2496 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2498 (const_string "TI")]
2499 (const_string "V2DF"))
2500 /* For architectures resolving dependencies on
2501 whole SSE registers use APD move to break dependency
2502 chains, otherwise use short move to avoid extra work.
2504 movaps encodes one byte shorter. */
2505 (eq_attr "alternative" "6")
2507 [(ne (symbol_ref "optimize_size")
2509 (const_string "V4SF")
2510 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2512 (const_string "V2DF")]
2513 (const_string "DF"))
2514 /* For architectures resolving dependencies on register
2515 parts we may avoid extra work to zero out upper part
2517 (eq_attr "alternative" "7")
2519 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2521 (const_string "V2DF")
2522 (const_string "DF"))]
2523 (const_string "DF")))])
2525 (define_insn "*movdf_integer"
2526 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2527 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2528 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2529 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2530 && (reload_in_progress || reload_completed
2531 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2532 || GET_CODE (operands[1]) != CONST_DOUBLE
2533 || memory_operand (operands[0], DFmode))"
2535 switch (which_alternative)
2538 return output_387_reg_move (insn, operands);
2541 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2542 return "fstp%z0\t%y0";
2544 return "fst%z0\t%y0";
2547 return standard_80387_constant_opcode (operands[1]);
2554 switch (get_attr_mode (insn))
2557 return "xorps\t%0, %0";
2559 return "xorpd\t%0, %0";
2561 return "pxor\t%0, %0";
2566 switch (get_attr_mode (insn))
2569 return "movaps\t{%1, %0|%0, %1}";
2571 return "movapd\t{%1, %0|%0, %1}";
2573 return "movsd\t{%1, %0|%0, %1}";
2578 if (get_attr_mode (insn) == MODE_V2DF)
2579 return "movlpd\t{%1, %0|%0, %1}";
2581 return "movsd\t{%1, %0|%0, %1}";
2583 return "movsd\t{%1, %0|%0, %1}";
2589 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2591 (cond [(eq_attr "alternative" "3,4")
2593 /* xorps is one byte shorter. */
2594 (eq_attr "alternative" "5")
2595 (cond [(ne (symbol_ref "optimize_size")
2597 (const_string "V4SF")
2598 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2600 (const_string "TI")]
2601 (const_string "V2DF"))
2602 /* For architectures resolving dependencies on
2603 whole SSE registers use APD move to break dependency
2604 chains, otherwise use short move to avoid extra work.
2606 movaps encodes one byte shorter. */
2607 (eq_attr "alternative" "6")
2609 [(ne (symbol_ref "optimize_size")
2611 (const_string "V4SF")
2612 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2614 (const_string "V2DF")]
2615 (const_string "DF"))
2616 /* For architectures resolving dependencies on register
2617 parts we may avoid extra work to zero out upper part
2619 (eq_attr "alternative" "7")
2621 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2623 (const_string "V2DF")
2624 (const_string "DF"))]
2625 (const_string "DF")))])
2628 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2629 (match_operand:DF 1 "general_operand" ""))]
2631 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2632 && ! (ANY_FP_REG_P (operands[0]) ||
2633 (GET_CODE (operands[0]) == SUBREG
2634 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2635 && ! (ANY_FP_REG_P (operands[1]) ||
2636 (GET_CODE (operands[1]) == SUBREG
2637 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2639 "ix86_split_long_move (operands); DONE;")
2641 (define_insn "*swapdf"
2642 [(set (match_operand:DF 0 "register_operand" "+f")
2643 (match_operand:DF 1 "register_operand" "+f"))
2646 "reload_completed || !TARGET_SSE2"
2648 if (STACK_TOP_P (operands[0]))
2653 [(set_attr "type" "fxch")
2654 (set_attr "mode" "DF")])
2656 (define_expand "movxf"
2657 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2658 (match_operand:XF 1 "general_operand" ""))]
2660 "ix86_expand_move (XFmode, operands); DONE;")
2662 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2663 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2664 ;; Pushing using integer instructions is longer except for constants
2665 ;; and direct memory references.
2666 ;; (assuming that any given constant is pushed only once, but this ought to be
2667 ;; handled elsewhere).
2669 (define_insn "*pushxf_nointeger"
2670 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2671 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2674 /* This insn should be already split before reg-stack. */
2677 [(set_attr "type" "multi")
2678 (set_attr "mode" "XF,SI,SI")])
2680 (define_insn "*pushxf_integer"
2681 [(set (match_operand:XF 0 "push_operand" "=<,<")
2682 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2685 /* This insn should be already split before reg-stack. */
2688 [(set_attr "type" "multi")
2689 (set_attr "mode" "XF,SI")])
2692 [(set (match_operand 0 "push_operand" "")
2693 (match_operand 1 "general_operand" ""))]
2695 && (GET_MODE (operands[0]) == XFmode
2696 || GET_MODE (operands[0]) == DFmode)
2697 && !ANY_FP_REG_P (operands[1])"
2699 "ix86_split_long_move (operands); DONE;")
2702 [(set (match_operand:XF 0 "push_operand" "")
2703 (match_operand:XF 1 "any_fp_register_operand" ""))]
2705 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
2706 (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
2707 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2710 [(set (match_operand:XF 0 "push_operand" "")
2711 (match_operand:XF 1 "any_fp_register_operand" ""))]
2713 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
2714 (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
2715 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2717 ;; Do not use integer registers when optimizing for size
2718 (define_insn "*movxf_nointeger"
2719 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2720 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2722 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2723 && (reload_in_progress || reload_completed
2724 || GET_CODE (operands[1]) != CONST_DOUBLE
2725 || memory_operand (operands[0], XFmode))"
2727 switch (which_alternative)
2730 return output_387_reg_move (insn, operands);
2733 /* There is no non-popping store to memory for XFmode. So if
2734 we need one, follow the store with a load. */
2735 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2736 return "fstp%z0\t%y0\;fld%z0\t%y0";
2738 return "fstp%z0\t%y0";
2741 return standard_80387_constant_opcode (operands[1]);
2748 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2749 (set_attr "mode" "XF,XF,XF,SI,SI")])
2751 (define_insn "*movxf_integer"
2752 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2753 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2755 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2756 && (reload_in_progress || reload_completed
2757 || GET_CODE (operands[1]) != CONST_DOUBLE
2758 || memory_operand (operands[0], XFmode))"
2760 switch (which_alternative)
2763 return output_387_reg_move (insn, operands);
2766 /* There is no non-popping store to memory for XFmode. So if
2767 we need one, follow the store with a load. */
2768 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2769 return "fstp%z0\t%y0\;fld%z0\t%y0";
2771 return "fstp%z0\t%y0";
2774 return standard_80387_constant_opcode (operands[1]);
2781 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2782 (set_attr "mode" "XF,XF,XF,SI,SI")])
2785 [(set (match_operand 0 "nonimmediate_operand" "")
2786 (match_operand 1 "general_operand" ""))]
2788 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2789 && GET_MODE (operands[0]) == XFmode
2790 && ! (ANY_FP_REG_P (operands[0]) ||
2791 (GET_CODE (operands[0]) == SUBREG
2792 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2793 && ! (ANY_FP_REG_P (operands[1]) ||
2794 (GET_CODE (operands[1]) == SUBREG
2795 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2797 "ix86_split_long_move (operands); DONE;")
2800 [(set (match_operand 0 "register_operand" "")
2801 (match_operand 1 "memory_operand" ""))]
2803 && GET_CODE (operands[1]) == MEM
2804 && (GET_MODE (operands[0]) == XFmode
2805 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2806 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2807 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2808 [(set (match_dup 0) (match_dup 1))]
2810 rtx c = get_pool_constant (XEXP (operands[1], 0));
2811 rtx r = operands[0];
2813 if (GET_CODE (r) == SUBREG)
2818 if (!standard_sse_constant_p (c))
2821 else if (FP_REG_P (r))
2823 if (!standard_80387_constant_p (c))
2826 else if (MMX_REG_P (r))
2832 (define_insn "swapxf"
2833 [(set (match_operand:XF 0 "register_operand" "+f")
2834 (match_operand:XF 1 "register_operand" "+f"))
2839 if (STACK_TOP_P (operands[0]))
2844 [(set_attr "type" "fxch")
2845 (set_attr "mode" "XF")])
2847 ;; Zero extension instructions
2849 (define_expand "zero_extendhisi2"
2850 [(set (match_operand:SI 0 "register_operand" "")
2851 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2854 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2856 operands[1] = force_reg (HImode, operands[1]);
2857 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2862 (define_insn "zero_extendhisi2_and"
2863 [(set (match_operand:SI 0 "register_operand" "=r")
2864 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2865 (clobber (reg:CC FLAGS_REG))]
2866 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2868 [(set_attr "type" "alu1")
2869 (set_attr "mode" "SI")])
2872 [(set (match_operand:SI 0 "register_operand" "")
2873 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2874 (clobber (reg:CC FLAGS_REG))]
2875 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2876 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2877 (clobber (reg:CC FLAGS_REG))])]
2880 (define_insn "*zero_extendhisi2_movzwl"
2881 [(set (match_operand:SI 0 "register_operand" "=r")
2882 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2883 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2884 "movz{wl|x}\t{%1, %0|%0, %1}"
2885 [(set_attr "type" "imovx")
2886 (set_attr "mode" "SI")])
2888 (define_expand "zero_extendqihi2"
2890 [(set (match_operand:HI 0 "register_operand" "")
2891 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2892 (clobber (reg:CC FLAGS_REG))])]
2896 (define_insn "*zero_extendqihi2_and"
2897 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2898 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2899 (clobber (reg:CC FLAGS_REG))]
2900 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2902 [(set_attr "type" "alu1")
2903 (set_attr "mode" "HI")])
2905 (define_insn "*zero_extendqihi2_movzbw_and"
2906 [(set (match_operand:HI 0 "register_operand" "=r,r")
2907 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2908 (clobber (reg:CC FLAGS_REG))]
2909 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2911 [(set_attr "type" "imovx,alu1")
2912 (set_attr "mode" "HI")])
2914 (define_insn "*zero_extendqihi2_movzbw"
2915 [(set (match_operand:HI 0 "register_operand" "=r")
2916 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2917 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2918 "movz{bw|x}\t{%1, %0|%0, %1}"
2919 [(set_attr "type" "imovx")
2920 (set_attr "mode" "HI")])
2922 ;; For the movzbw case strip only the clobber
2924 [(set (match_operand:HI 0 "register_operand" "")
2925 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2926 (clobber (reg:CC FLAGS_REG))]
2928 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2929 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
2930 [(set (match_operand:HI 0 "register_operand" "")
2931 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
2933 ;; When source and destination does not overlap, clear destination
2934 ;; first and then do the movb
2936 [(set (match_operand:HI 0 "register_operand" "")
2937 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2938 (clobber (reg:CC FLAGS_REG))]
2940 && ANY_QI_REG_P (operands[0])
2941 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2942 && !reg_overlap_mentioned_p (operands[0], operands[1])"
2943 [(set (match_dup 0) (const_int 0))
2944 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2945 "operands[2] = gen_lowpart (QImode, operands[0]);")
2947 ;; Rest is handled by single and.
2949 [(set (match_operand:HI 0 "register_operand" "")
2950 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
2951 (clobber (reg:CC FLAGS_REG))]
2953 && true_regnum (operands[0]) == true_regnum (operands[1])"
2954 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
2955 (clobber (reg:CC FLAGS_REG))])]
2958 (define_expand "zero_extendqisi2"
2960 [(set (match_operand:SI 0 "register_operand" "")
2961 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
2962 (clobber (reg:CC FLAGS_REG))])]
2966 (define_insn "*zero_extendqisi2_and"
2967 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
2968 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2969 (clobber (reg:CC FLAGS_REG))]
2970 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2972 [(set_attr "type" "alu1")
2973 (set_attr "mode" "SI")])
2975 (define_insn "*zero_extendqisi2_movzbw_and"
2976 [(set (match_operand:SI 0 "register_operand" "=r,r")
2977 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2978 (clobber (reg:CC FLAGS_REG))]
2979 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2981 [(set_attr "type" "imovx,alu1")
2982 (set_attr "mode" "SI")])
2984 (define_insn "*zero_extendqisi2_movzbw"
2985 [(set (match_operand:SI 0 "register_operand" "=r")
2986 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2987 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2988 "movz{bl|x}\t{%1, %0|%0, %1}"
2989 [(set_attr "type" "imovx")
2990 (set_attr "mode" "SI")])
2992 ;; For the movzbl case strip only the clobber
2994 [(set (match_operand:SI 0 "register_operand" "")
2995 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
2996 (clobber (reg:CC FLAGS_REG))]
2998 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2999 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3001 (zero_extend:SI (match_dup 1)))])
3003 ;; When source and destination does not overlap, clear destination
3004 ;; first and then do the movb
3006 [(set (match_operand:SI 0 "register_operand" "")
3007 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3008 (clobber (reg:CC FLAGS_REG))]
3010 && ANY_QI_REG_P (operands[0])
3011 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3012 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3013 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3014 [(set (match_dup 0) (const_int 0))
3015 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3016 "operands[2] = gen_lowpart (QImode, operands[0]);")
3018 ;; Rest is handled by single and.
3020 [(set (match_operand:SI 0 "register_operand" "")
3021 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3022 (clobber (reg:CC FLAGS_REG))]
3024 && true_regnum (operands[0]) == true_regnum (operands[1])"
3025 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3026 (clobber (reg:CC FLAGS_REG))])]
3029 ;; %%% Kill me once multi-word ops are sane.
3030 (define_expand "zero_extendsidi2"
3031 [(set (match_operand:DI 0 "register_operand" "=r")
3032 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3036 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3041 (define_insn "zero_extendsidi2_32"
3042 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3043 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
3044 (clobber (reg:CC FLAGS_REG))]
3045 "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3050 movd\t{%1, %0|%0, %1}
3051 movd\t{%1, %0|%0, %1}"
3052 [(set_attr "mode" "SI,SI,SI,DI,TI")
3053 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3055 (define_insn "*zero_extendsidi2_32_1"
3056 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3057 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
3058 (clobber (reg:CC FLAGS_REG))]
3059 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3064 movd\t{%1, %0|%0, %1}
3065 movd\t{%1, %0|%0, %1}"
3066 [(set_attr "mode" "SI,SI,SI,DI,TI")
3067 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3069 (define_insn "zero_extendsidi2_rex64"
3070 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
3071 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
3072 "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3074 mov\t{%k1, %k0|%k0, %k1}
3076 movd\t{%1, %0|%0, %1}
3077 movd\t{%1, %0|%0, %1}"
3078 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3079 (set_attr "mode" "SI,DI,DI,TI")])
3081 (define_insn "*zero_extendsidi2_rex64_1"
3082 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
3083 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
3084 "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3086 mov\t{%k1, %k0|%k0, %k1}
3088 movd\t{%1, %0|%0, %1}
3089 movd\t{%1, %0|%0, %1}"
3090 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3091 (set_attr "mode" "SI,DI,SI,SI")])
3094 [(set (match_operand:DI 0 "memory_operand" "")
3095 (zero_extend:DI (match_dup 0)))]
3097 [(set (match_dup 4) (const_int 0))]
3098 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3101 [(set (match_operand:DI 0 "register_operand" "")
3102 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3103 (clobber (reg:CC FLAGS_REG))]
3104 "!TARGET_64BIT && reload_completed
3105 && true_regnum (operands[0]) == true_regnum (operands[1])"
3106 [(set (match_dup 4) (const_int 0))]
3107 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3110 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3111 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3112 (clobber (reg:CC FLAGS_REG))]
3113 "!TARGET_64BIT && reload_completed
3114 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3115 [(set (match_dup 3) (match_dup 1))
3116 (set (match_dup 4) (const_int 0))]
3117 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3119 (define_insn "zero_extendhidi2"
3120 [(set (match_operand:DI 0 "register_operand" "=r,r")
3121 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3124 movz{wl|x}\t{%1, %k0|%k0, %1}
3125 movz{wq|x}\t{%1, %0|%0, %1}"
3126 [(set_attr "type" "imovx")
3127 (set_attr "mode" "SI,DI")])
3129 (define_insn "zero_extendqidi2"
3130 [(set (match_operand:DI 0 "register_operand" "=r,r")
3131 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3134 movz{bl|x}\t{%1, %k0|%k0, %1}
3135 movz{bq|x}\t{%1, %0|%0, %1}"
3136 [(set_attr "type" "imovx")
3137 (set_attr "mode" "SI,DI")])
3139 ;; Sign extension instructions
3141 (define_expand "extendsidi2"
3142 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3143 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3144 (clobber (reg:CC FLAGS_REG))
3145 (clobber (match_scratch:SI 2 ""))])]
3150 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3155 (define_insn "*extendsidi2_1"
3156 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3157 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3158 (clobber (reg:CC FLAGS_REG))
3159 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3163 (define_insn "extendsidi2_rex64"
3164 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3165 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3169 movs{lq|x}\t{%1,%0|%0, %1}"
3170 [(set_attr "type" "imovx")
3171 (set_attr "mode" "DI")
3172 (set_attr "prefix_0f" "0")
3173 (set_attr "modrm" "0,1")])
3175 (define_insn "extendhidi2"
3176 [(set (match_operand:DI 0 "register_operand" "=r")
3177 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3179 "movs{wq|x}\t{%1,%0|%0, %1}"
3180 [(set_attr "type" "imovx")
3181 (set_attr "mode" "DI")])
3183 (define_insn "extendqidi2"
3184 [(set (match_operand:DI 0 "register_operand" "=r")
3185 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3187 "movs{bq|x}\t{%1,%0|%0, %1}"
3188 [(set_attr "type" "imovx")
3189 (set_attr "mode" "DI")])
3191 ;; Extend to memory case when source register does die.
3193 [(set (match_operand:DI 0 "memory_operand" "")
3194 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3195 (clobber (reg:CC FLAGS_REG))
3196 (clobber (match_operand:SI 2 "register_operand" ""))]
3198 && dead_or_set_p (insn, operands[1])
3199 && !reg_mentioned_p (operands[1], operands[0]))"
3200 [(set (match_dup 3) (match_dup 1))
3201 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3202 (clobber (reg:CC FLAGS_REG))])
3203 (set (match_dup 4) (match_dup 1))]
3204 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3206 ;; Extend to memory case when source register does not die.
3208 [(set (match_operand:DI 0 "memory_operand" "")
3209 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3210 (clobber (reg:CC FLAGS_REG))
3211 (clobber (match_operand:SI 2 "register_operand" ""))]
3215 split_di (&operands[0], 1, &operands[3], &operands[4]);
3217 emit_move_insn (operands[3], operands[1]);
3219 /* Generate a cltd if possible and doing so it profitable. */
3220 if (true_regnum (operands[1]) == 0
3221 && true_regnum (operands[2]) == 1
3222 && (optimize_size || TARGET_USE_CLTD))
3224 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3228 emit_move_insn (operands[2], operands[1]);
3229 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3231 emit_move_insn (operands[4], operands[2]);
3235 ;; Extend to register case. Optimize case where source and destination
3236 ;; registers match and cases where we can use cltd.
3238 [(set (match_operand:DI 0 "register_operand" "")
3239 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3240 (clobber (reg:CC FLAGS_REG))
3241 (clobber (match_scratch:SI 2 ""))]
3245 split_di (&operands[0], 1, &operands[3], &operands[4]);
3247 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3248 emit_move_insn (operands[3], operands[1]);
3250 /* Generate a cltd if possible and doing so it profitable. */
3251 if (true_regnum (operands[3]) == 0
3252 && (optimize_size || TARGET_USE_CLTD))
3254 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3258 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3259 emit_move_insn (operands[4], operands[1]);
3261 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3265 (define_insn "extendhisi2"
3266 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3267 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3270 switch (get_attr_prefix_0f (insn))
3273 return "{cwtl|cwde}";
3275 return "movs{wl|x}\t{%1,%0|%0, %1}";
3278 [(set_attr "type" "imovx")
3279 (set_attr "mode" "SI")
3280 (set (attr "prefix_0f")
3281 ;; movsx is short decodable while cwtl is vector decoded.
3282 (if_then_else (and (eq_attr "cpu" "!k6")
3283 (eq_attr "alternative" "0"))
3285 (const_string "1")))
3287 (if_then_else (eq_attr "prefix_0f" "0")
3289 (const_string "1")))])
3291 (define_insn "*extendhisi2_zext"
3292 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3294 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3297 switch (get_attr_prefix_0f (insn))
3300 return "{cwtl|cwde}";
3302 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3305 [(set_attr "type" "imovx")
3306 (set_attr "mode" "SI")
3307 (set (attr "prefix_0f")
3308 ;; movsx is short decodable while cwtl is vector decoded.
3309 (if_then_else (and (eq_attr "cpu" "!k6")
3310 (eq_attr "alternative" "0"))
3312 (const_string "1")))
3314 (if_then_else (eq_attr "prefix_0f" "0")
3316 (const_string "1")))])
3318 (define_insn "extendqihi2"
3319 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3320 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3323 switch (get_attr_prefix_0f (insn))
3326 return "{cbtw|cbw}";
3328 return "movs{bw|x}\t{%1,%0|%0, %1}";
3331 [(set_attr "type" "imovx")
3332 (set_attr "mode" "HI")
3333 (set (attr "prefix_0f")
3334 ;; movsx is short decodable while cwtl is vector decoded.
3335 (if_then_else (and (eq_attr "cpu" "!k6")
3336 (eq_attr "alternative" "0"))
3338 (const_string "1")))
3340 (if_then_else (eq_attr "prefix_0f" "0")
3342 (const_string "1")))])
3344 (define_insn "extendqisi2"
3345 [(set (match_operand:SI 0 "register_operand" "=r")
3346 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3348 "movs{bl|x}\t{%1,%0|%0, %1}"
3349 [(set_attr "type" "imovx")
3350 (set_attr "mode" "SI")])
3352 (define_insn "*extendqisi2_zext"
3353 [(set (match_operand:DI 0 "register_operand" "=r")
3355 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3357 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3358 [(set_attr "type" "imovx")
3359 (set_attr "mode" "SI")])
3361 ;; Conversions between float and double.
3363 ;; These are all no-ops in the model used for the 80387. So just
3366 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3367 (define_insn "*dummy_extendsfdf2"
3368 [(set (match_operand:DF 0 "push_operand" "=<")
3369 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3374 [(set (match_operand:DF 0 "push_operand" "")
3375 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3377 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
3378 (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
3381 [(set (match_operand:DF 0 "push_operand" "")
3382 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3384 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
3385 (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
3387 (define_insn "*dummy_extendsfxf2"
3388 [(set (match_operand:XF 0 "push_operand" "=<")
3389 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3394 [(set (match_operand:XF 0 "push_operand" "")
3395 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3397 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3398 (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3399 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3402 [(set (match_operand:XF 0 "push_operand" "")
3403 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3405 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3406 (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3407 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3410 [(set (match_operand:XF 0 "push_operand" "")
3411 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3413 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3414 (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3415 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3418 [(set (match_operand:XF 0 "push_operand" "")
3419 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3421 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3422 (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3423 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3425 (define_expand "extendsfdf2"
3426 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3427 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3428 "TARGET_80387 || TARGET_SSE2"
3430 /* ??? Needed for compress_float_constant since all fp constants
3431 are LEGITIMATE_CONSTANT_P. */
3432 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3433 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3434 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3435 operands[1] = force_reg (SFmode, operands[1]);
3438 (define_insn "*extendsfdf2_1"
3439 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3440 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3441 "(TARGET_80387 || TARGET_SSE2)
3442 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3444 switch (which_alternative)
3447 return output_387_reg_move (insn, operands);
3450 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3451 return "fstp%z0\t%y0";
3453 return "fst%z0\t%y0";
3456 return "cvtss2sd\t{%1, %0|%0, %1}";
3462 [(set_attr "type" "fmov,fmov,ssecvt")
3463 (set_attr "mode" "SF,XF,DF")])
3465 (define_insn "*extendsfdf2_1_sse_only"
3466 [(set (match_operand:DF 0 "register_operand" "=Y")
3467 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3468 "!TARGET_80387 && TARGET_SSE2
3469 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3470 "cvtss2sd\t{%1, %0|%0, %1}"
3471 [(set_attr "type" "ssecvt")
3472 (set_attr "mode" "DF")])
3474 (define_expand "extendsfxf2"
3475 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3476 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3479 /* ??? Needed for compress_float_constant since all fp constants
3480 are LEGITIMATE_CONSTANT_P. */
3481 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3482 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3483 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3484 operands[1] = force_reg (SFmode, operands[1]);
3487 (define_insn "*extendsfxf2_1"
3488 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3489 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3491 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3493 switch (which_alternative)
3496 return output_387_reg_move (insn, operands);
3499 /* There is no non-popping store to memory for XFmode. So if
3500 we need one, follow the store with a load. */
3501 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3502 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3504 return "fstp%z0\t%y0";
3510 [(set_attr "type" "fmov")
3511 (set_attr "mode" "SF,XF")])
3513 (define_expand "extenddfxf2"
3514 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3515 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3518 /* ??? Needed for compress_float_constant since all fp constants
3519 are LEGITIMATE_CONSTANT_P. */
3520 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3521 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3522 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3523 operands[1] = force_reg (DFmode, operands[1]);
3526 (define_insn "*extenddfxf2_1"
3527 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3528 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3530 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3532 switch (which_alternative)
3535 return output_387_reg_move (insn, operands);
3538 /* There is no non-popping store to memory for XFmode. So if
3539 we need one, follow the store with a load. */
3540 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3541 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3543 return "fstp%z0\t%y0";
3549 [(set_attr "type" "fmov")
3550 (set_attr "mode" "DF,XF")])
3552 ;; %%% This seems bad bad news.
3553 ;; This cannot output into an f-reg because there is no way to be sure
3554 ;; of truncating in that case. Otherwise this is just like a simple move
3555 ;; insn. So we pretend we can output to a reg in order to get better
3556 ;; register preferencing, but we really use a stack slot.
3558 (define_expand "truncdfsf2"
3559 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3561 (match_operand:DF 1 "register_operand" "")))
3562 (clobber (match_dup 2))])]
3563 "TARGET_80387 || TARGET_SSE2"
3567 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3570 else if (flag_unsafe_math_optimizations)
3572 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3573 emit_insn (gen_truncdfsf2_noop (reg, operands[1]));
3574 if (reg != operands[0])
3575 emit_move_insn (operands[0], reg);
3579 operands[2] = assign_386_stack_local (SFmode, 0);
3582 (define_insn "truncdfsf2_noop"
3583 [(set (match_operand:SF 0 "register_operand" "=f")
3584 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3585 "TARGET_80387 && flag_unsafe_math_optimizations"
3587 return output_387_reg_move (insn, operands);
3589 [(set_attr "type" "fmov")
3590 (set_attr "mode" "SF")])
3592 (define_insn "*truncdfsf2_1"
3593 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3595 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3596 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3597 "TARGET_80387 && !TARGET_SSE2"
3599 switch (which_alternative)
3602 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3603 return "fstp%z0\t%y0";
3605 return "fst%z0\t%y0";
3610 [(set_attr "type" "fmov,multi,multi,multi")
3611 (set_attr "mode" "SF,SF,SF,SF")])
3613 (define_insn "*truncdfsf2_1_sse"
3614 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3616 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3617 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3618 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3620 switch (which_alternative)
3623 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3624 return "fstp%z0\t%y0";
3626 return "fst%z0\t%y0";
3633 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3634 (set_attr "mode" "SF,SF,SF,SF,DF")])
3636 (define_insn "*truncdfsf2_1_sse_nooverlap"
3637 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3639 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3640 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3641 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3643 switch (which_alternative)
3646 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3647 return "fstp%z0\t%y0";
3649 return "fst%z0\t%y0";
3656 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3657 (set_attr "mode" "SF,SF,SF,SF,DF")])
3659 (define_insn "*truncdfsf2_2"
3660 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3662 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3663 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3664 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3666 switch (which_alternative)
3670 return "cvtsd2ss\t{%1, %0|%0, %1}";
3672 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3673 return "fstp%z0\t%y0";
3675 return "fst%z0\t%y0";
3680 [(set_attr "type" "ssecvt,ssecvt,fmov")
3681 (set_attr "athlon_decode" "vector,double,*")
3682 (set_attr "mode" "SF,SF,SF")])
3684 (define_insn "*truncdfsf2_2_nooverlap"
3685 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
3687 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3688 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3689 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3691 switch (which_alternative)
3696 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3697 return "fstp%z0\t%y0";
3699 return "fst%z0\t%y0";
3704 [(set_attr "type" "ssecvt,fmov")
3705 (set_attr "mode" "DF,SF")])
3707 (define_insn "*truncdfsf2_3"
3708 [(set (match_operand:SF 0 "memory_operand" "=m")
3710 (match_operand:DF 1 "register_operand" "f")))]
3713 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3714 return "fstp%z0\t%y0";
3716 return "fst%z0\t%y0";
3718 [(set_attr "type" "fmov")
3719 (set_attr "mode" "SF")])
3721 (define_insn "truncdfsf2_sse_only"
3722 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
3724 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
3725 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3726 "cvtsd2ss\t{%1, %0|%0, %1}"
3727 [(set_attr "type" "ssecvt")
3728 (set_attr "athlon_decode" "vector,double")
3729 (set_attr "mode" "SF")])
3731 (define_insn "*truncdfsf2_sse_only_nooverlap"
3732 [(set (match_operand:SF 0 "register_operand" "=&Y")
3734 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3735 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3737 [(set_attr "type" "ssecvt")
3738 (set_attr "mode" "DF")])
3741 [(set (match_operand:SF 0 "memory_operand" "")
3743 (match_operand:DF 1 "register_operand" "")))
3744 (clobber (match_operand:SF 2 "memory_operand" ""))]
3746 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3749 ; Avoid possible reformatting penalty on the destination by first
3752 [(set (match_operand:SF 0 "register_operand" "")
3754 (match_operand:DF 1 "nonimmediate_operand" "")))
3755 (clobber (match_operand 2 "" ""))]
3756 "TARGET_80387 && reload_completed
3757 && SSE_REG_P (operands[0])
3758 && !STACK_REG_P (operands[1])"
3762 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
3763 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3766 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3767 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3768 /* simplify_gen_subreg refuses to widen memory references. */
3769 if (GET_CODE (src) == SUBREG)
3770 alter_subreg (&src);
3771 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3773 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3774 emit_insn (gen_cvtsd2ss (dest, dest, src));
3780 [(set (match_operand:SF 0 "register_operand" "")
3782 (match_operand:DF 1 "nonimmediate_operand" "")))]
3783 "TARGET_80387 && reload_completed
3784 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3788 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3789 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3790 /* simplify_gen_subreg refuses to widen memory references. */
3791 if (GET_CODE (src) == SUBREG)
3792 alter_subreg (&src);
3793 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3795 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3796 emit_insn (gen_cvtsd2ss (dest, dest, src));
3801 [(set (match_operand:SF 0 "register_operand" "")
3803 (match_operand:DF 1 "fp_register_operand" "")))
3804 (clobber (match_operand:SF 2 "memory_operand" ""))]
3805 "TARGET_80387 && reload_completed"
3806 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3807 (set (match_dup 0) (match_dup 2))]
3810 (define_expand "truncxfsf2"
3811 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3813 (match_operand:XF 1 "register_operand" "")))
3814 (clobber (match_dup 2))])]
3817 if (flag_unsafe_math_optimizations)
3819 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3820 emit_insn (gen_truncxfsf2_noop (reg, operands[1]));
3821 if (reg != operands[0])
3822 emit_move_insn (operands[0], reg);
3826 operands[2] = assign_386_stack_local (SFmode, 0);
3829 (define_insn "truncxfsf2_noop"
3830 [(set (match_operand:SF 0 "register_operand" "=f")
3831 (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
3832 "TARGET_80387 && flag_unsafe_math_optimizations"
3834 return output_387_reg_move (insn, operands);
3836 [(set_attr "type" "fmov")
3837 (set_attr "mode" "SF")])
3839 (define_insn "*truncxfsf2_1"
3840 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3842 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3843 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3846 switch (which_alternative)
3849 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3850 return "fstp%z0\t%y0";
3852 return "fst%z0\t%y0";
3857 [(set_attr "type" "fmov,multi,multi,multi")
3858 (set_attr "mode" "SF")])
3860 (define_insn "*truncxfsf2_2"
3861 [(set (match_operand:SF 0 "memory_operand" "=m")
3863 (match_operand:XF 1 "register_operand" "f")))]
3866 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3867 return "fstp%z0\t%y0";
3869 return "fst%z0\t%y0";
3871 [(set_attr "type" "fmov")
3872 (set_attr "mode" "SF")])
3875 [(set (match_operand:SF 0 "memory_operand" "")
3877 (match_operand:XF 1 "register_operand" "")))
3878 (clobber (match_operand:SF 2 "memory_operand" ""))]
3880 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3884 [(set (match_operand:SF 0 "register_operand" "")
3886 (match_operand:XF 1 "register_operand" "")))
3887 (clobber (match_operand:SF 2 "memory_operand" ""))]
3888 "TARGET_80387 && reload_completed"
3889 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3890 (set (match_dup 0) (match_dup 2))]
3893 (define_expand "truncxfdf2"
3894 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3896 (match_operand:XF 1 "register_operand" "")))
3897 (clobber (match_dup 2))])]
3900 if (flag_unsafe_math_optimizations)
3902 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DFmode);
3903 emit_insn (gen_truncxfdf2_noop (reg, operands[1]));
3904 if (reg != operands[0])
3905 emit_move_insn (operands[0], reg);
3909 operands[2] = assign_386_stack_local (DFmode, 0);
3912 (define_insn "truncxfdf2_noop"
3913 [(set (match_operand:DF 0 "register_operand" "=f")
3914 (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
3915 "TARGET_80387 && flag_unsafe_math_optimizations"
3917 return output_387_reg_move (insn, operands);
3919 [(set_attr "type" "fmov")
3920 (set_attr "mode" "DF")])
3922 (define_insn "*truncxfdf2_1"
3923 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3925 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3926 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3929 switch (which_alternative)
3932 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3933 return "fstp%z0\t%y0";
3935 return "fst%z0\t%y0";
3941 [(set_attr "type" "fmov,multi,multi,multi")
3942 (set_attr "mode" "DF")])
3944 (define_insn "*truncxfdf2_2"
3945 [(set (match_operand:DF 0 "memory_operand" "=m")
3947 (match_operand:XF 1 "register_operand" "f")))]
3950 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3951 return "fstp%z0\t%y0";
3953 return "fst%z0\t%y0";
3955 [(set_attr "type" "fmov")
3956 (set_attr "mode" "DF")])
3959 [(set (match_operand:DF 0 "memory_operand" "")
3961 (match_operand:XF 1 "register_operand" "")))
3962 (clobber (match_operand:DF 2 "memory_operand" ""))]
3964 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
3968 [(set (match_operand:DF 0 "register_operand" "")
3970 (match_operand:XF 1 "register_operand" "")))
3971 (clobber (match_operand:DF 2 "memory_operand" ""))]
3972 "TARGET_80387 && reload_completed"
3973 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
3974 (set (match_dup 0) (match_dup 2))]
3978 ;; %%% Break up all these bad boys.
3980 ;; Signed conversion to DImode.
3982 (define_expand "fix_truncxfdi2"
3983 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
3984 (fix:DI (match_operand:XF 1 "register_operand" "")))
3985 (clobber (reg:CC FLAGS_REG))])]
3989 (define_expand "fix_truncdfdi2"
3990 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
3991 (fix:DI (match_operand:DF 1 "register_operand" "")))
3992 (clobber (reg:CC FLAGS_REG))])]
3993 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
3995 if (TARGET_64BIT && TARGET_SSE2)
3997 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
3998 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
3999 if (out != operands[0])
4000 emit_move_insn (operands[0], out);
4005 (define_expand "fix_truncsfdi2"
4006 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4007 (fix:DI (match_operand:SF 1 "register_operand" "")))
4008 (clobber (reg:CC FLAGS_REG))])]
4009 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4011 if (TARGET_SSE && TARGET_64BIT)
4013 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4014 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4015 if (out != operands[0])
4016 emit_move_insn (operands[0], out);
4021 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4022 ;; of the machinery.
4023 (define_insn_and_split "*fix_truncdi_1"
4024 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4025 (fix:DI (match_operand 1 "register_operand" "f,f")))
4026 (clobber (reg:CC FLAGS_REG))]
4027 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4028 && !reload_completed && !reload_in_progress
4029 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4034 ix86_optimize_mode_switching = 1;
4035 operands[2] = assign_386_stack_local (HImode, 1);
4036 operands[3] = assign_386_stack_local (HImode, 2);
4037 if (memory_operand (operands[0], VOIDmode))
4038 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4039 operands[2], operands[3]));
4042 operands[4] = assign_386_stack_local (DImode, 0);
4043 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4044 operands[2], operands[3],
4049 [(set_attr "type" "fistp")
4050 (set_attr "i387_cw" "trunc")
4051 (set_attr "mode" "DI")])
4053 (define_insn "fix_truncdi_nomemory"
4054 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4055 (fix:DI (match_operand 1 "register_operand" "f,f")))
4056 (use (match_operand:HI 2 "memory_operand" "m,m"))
4057 (use (match_operand:HI 3 "memory_operand" "m,m"))
4058 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4059 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4060 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4061 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4063 [(set_attr "type" "fistp")
4064 (set_attr "i387_cw" "trunc")
4065 (set_attr "mode" "DI")])
4067 (define_insn "fix_truncdi_memory"
4068 [(set (match_operand:DI 0 "memory_operand" "=m")
4069 (fix:DI (match_operand 1 "register_operand" "f")))
4070 (use (match_operand:HI 2 "memory_operand" "m"))
4071 (use (match_operand:HI 3 "memory_operand" "m"))
4072 (clobber (match_scratch:DF 4 "=&1f"))]
4073 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4074 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4075 "* return output_fix_trunc (insn, operands);"
4076 [(set_attr "type" "fistp")
4077 (set_attr "i387_cw" "trunc")
4078 (set_attr "mode" "DI")])
4081 [(set (match_operand:DI 0 "register_operand" "")
4082 (fix:DI (match_operand 1 "register_operand" "")))
4083 (use (match_operand:HI 2 "memory_operand" ""))
4084 (use (match_operand:HI 3 "memory_operand" ""))
4085 (clobber (match_operand:DI 4 "memory_operand" ""))
4086 (clobber (match_scratch 5 ""))]
4088 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4091 (clobber (match_dup 5))])
4092 (set (match_dup 0) (match_dup 4))]
4096 [(set (match_operand:DI 0 "memory_operand" "")
4097 (fix:DI (match_operand 1 "register_operand" "")))
4098 (use (match_operand:HI 2 "memory_operand" ""))
4099 (use (match_operand:HI 3 "memory_operand" ""))
4100 (clobber (match_operand:DI 4 "memory_operand" ""))
4101 (clobber (match_scratch 5 ""))]
4103 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4106 (clobber (match_dup 5))])]
4109 ;; When SSE available, it is always faster to use it!
4110 (define_insn "fix_truncsfdi_sse"
4111 [(set (match_operand:DI 0 "register_operand" "=r,r")
4112 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4113 "TARGET_64BIT && TARGET_SSE"
4114 "cvttss2si{q}\t{%1, %0|%0, %1}"
4115 [(set_attr "type" "sseicvt")
4116 (set_attr "mode" "SF")
4117 (set_attr "athlon_decode" "double,vector")])
4119 ;; Avoid vector decoded form of the instruction.
4121 [(match_scratch:SF 2 "x")
4122 (set (match_operand:DI 0 "register_operand" "")
4123 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4124 "TARGET_K8 && !optimize_size"
4125 [(set (match_dup 2) (match_dup 1))
4126 (set (match_dup 0) (fix:DI (match_dup 2)))]
4129 (define_insn "fix_truncdfdi_sse"
4130 [(set (match_operand:DI 0 "register_operand" "=r,r")
4131 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4132 "TARGET_64BIT && TARGET_SSE2"
4133 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4134 [(set_attr "type" "sseicvt,sseicvt")
4135 (set_attr "mode" "DF")
4136 (set_attr "athlon_decode" "double,vector")])
4138 ;; Avoid vector decoded form of the instruction.
4140 [(match_scratch:DF 2 "Y")
4141 (set (match_operand:DI 0 "register_operand" "")
4142 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4143 "TARGET_K8 && !optimize_size"
4144 [(set (match_dup 2) (match_dup 1))
4145 (set (match_dup 0) (fix:DI (match_dup 2)))]
4148 ;; Signed conversion to SImode.
4150 (define_expand "fix_truncxfsi2"
4151 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4152 (fix:SI (match_operand:XF 1 "register_operand" "")))
4153 (clobber (reg:CC FLAGS_REG))])]
4157 (define_expand "fix_truncdfsi2"
4158 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4159 (fix:SI (match_operand:DF 1 "register_operand" "")))
4160 (clobber (reg:CC FLAGS_REG))])]
4161 "TARGET_80387 || TARGET_SSE2"
4165 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4166 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4167 if (out != operands[0])
4168 emit_move_insn (operands[0], out);
4173 (define_expand "fix_truncsfsi2"
4174 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4175 (fix:SI (match_operand:SF 1 "register_operand" "")))
4176 (clobber (reg:CC FLAGS_REG))])]
4177 "TARGET_80387 || TARGET_SSE"
4181 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4182 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4183 if (out != operands[0])
4184 emit_move_insn (operands[0], out);
4189 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4190 ;; of the machinery.
4191 (define_insn_and_split "*fix_truncsi_1"
4192 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4193 (fix:SI (match_operand 1 "register_operand" "f,f")))
4194 (clobber (reg:CC FLAGS_REG))]
4195 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4196 && !reload_completed && !reload_in_progress
4197 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4202 ix86_optimize_mode_switching = 1;
4203 operands[2] = assign_386_stack_local (HImode, 1);
4204 operands[3] = assign_386_stack_local (HImode, 2);
4205 if (memory_operand (operands[0], VOIDmode))
4206 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4207 operands[2], operands[3]));
4210 operands[4] = assign_386_stack_local (SImode, 0);
4211 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4212 operands[2], operands[3],
4217 [(set_attr "type" "fistp")
4218 (set_attr "i387_cw" "trunc")
4219 (set_attr "mode" "SI")])
4221 (define_insn "fix_truncsi_nomemory"
4222 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4223 (fix:SI (match_operand 1 "register_operand" "f,f")))
4224 (use (match_operand:HI 2 "memory_operand" "m,m"))
4225 (use (match_operand:HI 3 "memory_operand" "m,m"))
4226 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4227 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4228 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4230 [(set_attr "type" "fistp")
4231 (set_attr "i387_cw" "trunc")
4232 (set_attr "mode" "SI")])
4234 (define_insn "fix_truncsi_memory"
4235 [(set (match_operand:SI 0 "memory_operand" "=m")
4236 (fix:SI (match_operand 1 "register_operand" "f")))
4237 (use (match_operand:HI 2 "memory_operand" "m"))
4238 (use (match_operand:HI 3 "memory_operand" "m"))]
4239 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4240 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4241 "* return output_fix_trunc (insn, operands);"
4242 [(set_attr "type" "fistp")
4243 (set_attr "i387_cw" "trunc")
4244 (set_attr "mode" "SI")])
4246 ;; When SSE available, it is always faster to use it!
4247 (define_insn "fix_truncsfsi_sse"
4248 [(set (match_operand:SI 0 "register_operand" "=r,r")
4249 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4251 "cvttss2si\t{%1, %0|%0, %1}"
4252 [(set_attr "type" "sseicvt")
4253 (set_attr "mode" "DF")
4254 (set_attr "athlon_decode" "double,vector")])
4256 ;; Avoid vector decoded form of the instruction.
4258 [(match_scratch:SF 2 "x")
4259 (set (match_operand:SI 0 "register_operand" "")
4260 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4261 "TARGET_K8 && !optimize_size"
4262 [(set (match_dup 2) (match_dup 1))
4263 (set (match_dup 0) (fix:SI (match_dup 2)))]
4266 (define_insn "fix_truncdfsi_sse"
4267 [(set (match_operand:SI 0 "register_operand" "=r,r")
4268 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4270 "cvttsd2si\t{%1, %0|%0, %1}"
4271 [(set_attr "type" "sseicvt")
4272 (set_attr "mode" "DF")
4273 (set_attr "athlon_decode" "double,vector")])
4275 ;; Avoid vector decoded form of the instruction.
4277 [(match_scratch:DF 2 "Y")
4278 (set (match_operand:SI 0 "register_operand" "")
4279 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4280 "TARGET_K8 && !optimize_size"
4281 [(set (match_dup 2) (match_dup 1))
4282 (set (match_dup 0) (fix:SI (match_dup 2)))]
4286 [(set (match_operand:SI 0 "register_operand" "")
4287 (fix:SI (match_operand 1 "register_operand" "")))
4288 (use (match_operand:HI 2 "memory_operand" ""))
4289 (use (match_operand:HI 3 "memory_operand" ""))
4290 (clobber (match_operand:SI 4 "memory_operand" ""))]
4292 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4294 (use (match_dup 3))])
4295 (set (match_dup 0) (match_dup 4))]
4299 [(set (match_operand:SI 0 "memory_operand" "")
4300 (fix:SI (match_operand 1 "register_operand" "")))
4301 (use (match_operand:HI 2 "memory_operand" ""))
4302 (use (match_operand:HI 3 "memory_operand" ""))
4303 (clobber (match_operand:SI 4 "memory_operand" ""))]
4305 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4307 (use (match_dup 3))])]
4310 ;; Signed conversion to HImode.
4312 (define_expand "fix_truncxfhi2"
4313 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4314 (fix:HI (match_operand:XF 1 "register_operand" "")))
4315 (clobber (reg:CC FLAGS_REG))])]
4319 (define_expand "fix_truncdfhi2"
4320 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4321 (fix:HI (match_operand:DF 1 "register_operand" "")))
4322 (clobber (reg:CC FLAGS_REG))])]
4323 "TARGET_80387 && !TARGET_SSE2"
4326 (define_expand "fix_truncsfhi2"
4327 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4328 (fix:HI (match_operand:SF 1 "register_operand" "")))
4329 (clobber (reg:CC FLAGS_REG))])]
4330 "TARGET_80387 && !TARGET_SSE"
4333 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4334 ;; of the machinery.
4335 (define_insn_and_split "*fix_trunchi_1"
4336 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4337 (fix:HI (match_operand 1 "register_operand" "f,f")))
4338 (clobber (reg:CC FLAGS_REG))]
4339 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4340 && !reload_completed && !reload_in_progress
4341 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4346 ix86_optimize_mode_switching = 1;
4347 operands[2] = assign_386_stack_local (HImode, 1);
4348 operands[3] = assign_386_stack_local (HImode, 2);
4349 if (memory_operand (operands[0], VOIDmode))
4350 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4351 operands[2], operands[3]));
4354 operands[4] = assign_386_stack_local (HImode, 0);
4355 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4356 operands[2], operands[3],
4361 [(set_attr "type" "fistp")
4362 (set_attr "i387_cw" "trunc")
4363 (set_attr "mode" "HI")])
4365 (define_insn "fix_trunchi_nomemory"
4366 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4367 (fix:HI (match_operand 1 "register_operand" "f,f")))
4368 (use (match_operand:HI 2 "memory_operand" "m,m"))
4369 (use (match_operand:HI 3 "memory_operand" "m,m"))
4370 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4371 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4372 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4374 [(set_attr "type" "fistp")
4375 (set_attr "i387_cw" "trunc")
4376 (set_attr "mode" "HI")])
4378 (define_insn "fix_trunchi_memory"
4379 [(set (match_operand:HI 0 "memory_operand" "=m")
4380 (fix:HI (match_operand 1 "register_operand" "f")))
4381 (use (match_operand:HI 2 "memory_operand" "m"))
4382 (use (match_operand:HI 3 "memory_operand" "m"))]
4383 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4384 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4385 "* return output_fix_trunc (insn, operands);"
4386 [(set_attr "type" "fistp")
4387 (set_attr "i387_cw" "trunc")
4388 (set_attr "mode" "HI")])
4391 [(set (match_operand:HI 0 "memory_operand" "")
4392 (fix:HI (match_operand 1 "register_operand" "")))
4393 (use (match_operand:HI 2 "memory_operand" ""))
4394 (use (match_operand:HI 3 "memory_operand" ""))
4395 (clobber (match_operand:HI 4 "memory_operand" ""))]
4397 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4399 (use (match_dup 3))])]
4403 [(set (match_operand:HI 0 "register_operand" "")
4404 (fix:HI (match_operand 1 "register_operand" "")))
4405 (use (match_operand:HI 2 "memory_operand" ""))
4406 (use (match_operand:HI 3 "memory_operand" ""))
4407 (clobber (match_operand:HI 4 "memory_operand" ""))]
4409 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4412 (clobber (match_dup 4))])
4413 (set (match_dup 0) (match_dup 4))]
4416 (define_insn "x86_fnstcw_1"
4417 [(set (match_operand:HI 0 "memory_operand" "=m")
4418 (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
4421 [(set_attr "length" "2")
4422 (set_attr "mode" "HI")
4423 (set_attr "unit" "i387")])
4425 (define_insn "x86_fldcw_1"
4426 [(set (reg:HI FPSR_REG)
4427 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4430 [(set_attr "length" "2")
4431 (set_attr "mode" "HI")
4432 (set_attr "unit" "i387")
4433 (set_attr "athlon_decode" "vector")])
4435 ;; Conversion between fixed point and floating point.
4437 ;; Even though we only accept memory inputs, the backend _really_
4438 ;; wants to be able to do this between registers.
4440 (define_expand "floathisf2"
4441 [(set (match_operand:SF 0 "register_operand" "")
4442 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4443 "TARGET_SSE || TARGET_80387"
4445 if (TARGET_SSE && TARGET_SSE_MATH)
4447 emit_insn (gen_floatsisf2 (operands[0],
4448 convert_to_mode (SImode, operands[1], 0)));
4453 (define_insn "*floathisf2_1"
4454 [(set (match_operand:SF 0 "register_operand" "=f,f")
4455 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4456 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4460 [(set_attr "type" "fmov,multi")
4461 (set_attr "mode" "SF")
4462 (set_attr "fp_int_src" "true")])
4464 (define_expand "floatsisf2"
4465 [(set (match_operand:SF 0 "register_operand" "")
4466 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4467 "TARGET_SSE || TARGET_80387"
4470 (define_insn "*floatsisf2_i387"
4471 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4472 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4473 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4477 cvtsi2ss\t{%1, %0|%0, %1}
4478 cvtsi2ss\t{%1, %0|%0, %1}"
4479 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4480 (set_attr "mode" "SF")
4481 (set_attr "athlon_decode" "*,*,vector,double")
4482 (set_attr "fp_int_src" "true")])
4484 (define_insn "*floatsisf2_sse"
4485 [(set (match_operand:SF 0 "register_operand" "=x,x")
4486 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4488 "cvtsi2ss\t{%1, %0|%0, %1}"
4489 [(set_attr "type" "sseicvt")
4490 (set_attr "mode" "SF")
4491 (set_attr "athlon_decode" "vector,double")
4492 (set_attr "fp_int_src" "true")])
4494 ; Avoid possible reformatting penalty on the destination by first
4497 [(set (match_operand:SF 0 "register_operand" "")
4498 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4499 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4500 && SSE_REG_P (operands[0])"
4504 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4505 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4506 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4510 (define_expand "floatdisf2"
4511 [(set (match_operand:SF 0 "register_operand" "")
4512 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4513 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4516 (define_insn "*floatdisf2_i387_only"
4517 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4518 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4519 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4523 [(set_attr "type" "fmov,multi")
4524 (set_attr "mode" "SF")
4525 (set_attr "fp_int_src" "true")])
4527 (define_insn "*floatdisf2_i387"
4528 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4529 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4530 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4534 cvtsi2ss{q}\t{%1, %0|%0, %1}
4535 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4536 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4537 (set_attr "mode" "SF")
4538 (set_attr "athlon_decode" "*,*,vector,double")
4539 (set_attr "fp_int_src" "true")])
4541 (define_insn "*floatdisf2_sse"
4542 [(set (match_operand:SF 0 "register_operand" "=x,x")
4543 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4544 "TARGET_64BIT && TARGET_SSE"
4545 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4546 [(set_attr "type" "sseicvt")
4547 (set_attr "mode" "SF")
4548 (set_attr "athlon_decode" "vector,double")
4549 (set_attr "fp_int_src" "true")])
4551 ; Avoid possible reformatting penalty on the destination by first
4554 [(set (match_operand:SF 0 "register_operand" "")
4555 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4556 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4557 && SSE_REG_P (operands[0])"
4561 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4562 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4563 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4567 (define_expand "floathidf2"
4568 [(set (match_operand:DF 0 "register_operand" "")
4569 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4570 "TARGET_SSE2 || TARGET_80387"
4572 if (TARGET_SSE && TARGET_SSE_MATH)
4574 emit_insn (gen_floatsidf2 (operands[0],
4575 convert_to_mode (SImode, operands[1], 0)));
4580 (define_insn "*floathidf2_1"
4581 [(set (match_operand:DF 0 "register_operand" "=f,f")
4582 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4583 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4587 [(set_attr "type" "fmov,multi")
4588 (set_attr "mode" "DF")
4589 (set_attr "fp_int_src" "true")])
4591 (define_expand "floatsidf2"
4592 [(set (match_operand:DF 0 "register_operand" "")
4593 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4594 "TARGET_80387 || TARGET_SSE2"
4597 (define_insn "*floatsidf2_i387"
4598 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4599 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4600 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4604 cvtsi2sd\t{%1, %0|%0, %1}
4605 cvtsi2sd\t{%1, %0|%0, %1}"
4606 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4607 (set_attr "mode" "DF")
4608 (set_attr "athlon_decode" "*,*,double,direct")
4609 (set_attr "fp_int_src" "true")])
4611 (define_insn "*floatsidf2_sse"
4612 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4613 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4615 "cvtsi2sd\t{%1, %0|%0, %1}"
4616 [(set_attr "type" "sseicvt")
4617 (set_attr "mode" "DF")
4618 (set_attr "athlon_decode" "double,direct")
4619 (set_attr "fp_int_src" "true")])
4621 (define_expand "floatdidf2"
4622 [(set (match_operand:DF 0 "register_operand" "")
4623 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4624 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4627 (define_insn "*floatdidf2_i387_only"
4628 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4629 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4630 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4634 [(set_attr "type" "fmov,multi")
4635 (set_attr "mode" "DF")
4636 (set_attr "fp_int_src" "true")])
4638 (define_insn "*floatdidf2_i387"
4639 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4640 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4641 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4645 cvtsi2sd{q}\t{%1, %0|%0, %1}
4646 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4647 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4648 (set_attr "mode" "DF")
4649 (set_attr "athlon_decode" "*,*,double,direct")
4650 (set_attr "fp_int_src" "true")])
4652 (define_insn "*floatdidf2_sse"
4653 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4654 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4656 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4657 [(set_attr "type" "sseicvt")
4658 (set_attr "mode" "DF")
4659 (set_attr "athlon_decode" "double,direct")
4660 (set_attr "fp_int_src" "true")])
4662 (define_insn "floathixf2"
4663 [(set (match_operand:XF 0 "register_operand" "=f,f")
4664 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4669 [(set_attr "type" "fmov,multi")
4670 (set_attr "mode" "XF")
4671 (set_attr "fp_int_src" "true")])
4673 (define_insn "floatsixf2"
4674 [(set (match_operand:XF 0 "register_operand" "=f,f")
4675 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4680 [(set_attr "type" "fmov,multi")
4681 (set_attr "mode" "XF")
4682 (set_attr "fp_int_src" "true")])
4684 (define_insn "floatdixf2"
4685 [(set (match_operand:XF 0 "register_operand" "=f,f")
4686 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4691 [(set_attr "type" "fmov,multi")
4692 (set_attr "mode" "XF")
4693 (set_attr "fp_int_src" "true")])
4695 ;; %%% Kill these when reload knows how to do it.
4697 [(set (match_operand 0 "fp_register_operand" "")
4698 (float (match_operand 1 "register_operand" "")))]
4699 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4702 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4703 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4704 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4705 ix86_free_from_memory (GET_MODE (operands[1]));
4709 (define_expand "floatunssisf2"
4710 [(use (match_operand:SF 0 "register_operand" ""))
4711 (use (match_operand:SI 1 "register_operand" ""))]
4712 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
4713 "x86_emit_floatuns (operands); DONE;")
4715 (define_expand "floatunsdisf2"
4716 [(use (match_operand:SF 0 "register_operand" ""))
4717 (use (match_operand:DI 1 "register_operand" ""))]
4718 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
4719 "x86_emit_floatuns (operands); DONE;")
4721 (define_expand "floatunsdidf2"
4722 [(use (match_operand:DF 0 "register_operand" ""))
4723 (use (match_operand:DI 1 "register_operand" ""))]
4724 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
4725 "x86_emit_floatuns (operands); DONE;")
4727 ;; SSE extract/set expanders
4729 (define_expand "vec_setv2df"
4730 [(match_operand:V2DF 0 "register_operand" "")
4731 (match_operand:DF 1 "register_operand" "")
4732 (match_operand 2 "const_int_operand" "")]
4735 switch (INTVAL (operands[2]))
4738 emit_insn (gen_sse2_movsd (operands[0], operands[0],
4739 simplify_gen_subreg (V2DFmode, operands[1],
4744 rtx op1 = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4746 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], op1));
4755 (define_expand "vec_extractv2df"
4756 [(match_operand:DF 0 "register_operand" "")
4757 (match_operand:V2DF 1 "register_operand" "")
4758 (match_operand 2 "const_int_operand" "")]
4761 switch (INTVAL (operands[2]))
4764 emit_move_insn (operands[0], gen_lowpart (DFmode, operands[1]));
4768 rtx dest = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
4770 emit_insn (gen_sse2_unpckhpd (dest, operands[1], operands[1]));
4779 (define_expand "vec_initv2df"
4780 [(match_operand:V2DF 0 "register_operand" "")
4781 (match_operand 1 "" "")]
4784 ix86_expand_vector_init (operands[0], operands[1]);
4788 (define_expand "vec_setv4sf"
4789 [(match_operand:V4SF 0 "register_operand" "")
4790 (match_operand:SF 1 "register_operand" "")
4791 (match_operand 2 "const_int_operand" "")]
4794 switch (INTVAL (operands[2]))
4797 emit_insn (gen_sse_movss (operands[0], operands[0],
4798 simplify_gen_subreg (V4SFmode, operands[1],
4803 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4804 rtx tmp = gen_reg_rtx (V4SFmode);
4806 emit_move_insn (tmp, operands[0]);
4807 emit_insn (gen_sse_unpcklps (operands[0], operands[0], operands[0]));
4808 emit_insn (gen_sse_movss (operands[0], operands[0], op1));
4809 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4810 GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
4815 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4816 rtx tmp = gen_reg_rtx (V4SFmode);
4818 emit_move_insn (tmp, operands[0]);
4819 emit_insn (gen_sse_movss (tmp, tmp, op1));
4820 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4821 GEN_INT (0 + (1<<2) + (0<<4) + (3<<6))));
4826 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4827 rtx tmp = gen_reg_rtx (V4SFmode);
4829 emit_move_insn (tmp, operands[0]);
4830 emit_insn (gen_sse_movss (tmp, tmp, op1));
4831 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4832 GEN_INT (0 + (1<<2) + (2<<4) + (0<<6))));
4841 (define_expand "vec_extractv4sf"
4842 [(match_operand:SF 0 "register_operand" "")
4843 (match_operand:V4SF 1 "register_operand" "")
4844 (match_operand 2 "const_int_operand" "")]
4847 switch (INTVAL (operands[2]))
4850 emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1]));
4854 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4855 rtx tmp = gen_reg_rtx (V4SFmode);
4857 emit_move_insn (tmp, operands[1]);
4858 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4864 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4865 rtx tmp = gen_reg_rtx (V4SFmode);
4867 emit_move_insn (tmp, operands[1]);
4868 emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
4873 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4874 rtx tmp = gen_reg_rtx (V4SFmode);
4876 emit_move_insn (tmp, operands[1]);
4877 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4887 (define_expand "vec_initv4sf"
4888 [(match_operand:V4SF 0 "register_operand" "")
4889 (match_operand 1 "" "")]
4892 ix86_expand_vector_init (operands[0], operands[1]);
4898 ;; %%% splits for addsidi3
4899 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4900 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4901 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4903 (define_expand "adddi3"
4904 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4905 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4906 (match_operand:DI 2 "x86_64_general_operand" "")))
4907 (clobber (reg:CC FLAGS_REG))]
4909 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4911 (define_insn "*adddi3_1"
4912 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4913 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4914 (match_operand:DI 2 "general_operand" "roiF,riF")))
4915 (clobber (reg:CC FLAGS_REG))]
4916 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4920 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4921 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4922 (match_operand:DI 2 "general_operand" "")))
4923 (clobber (reg:CC FLAGS_REG))]
4924 "!TARGET_64BIT && reload_completed"
4925 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
4927 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4928 (parallel [(set (match_dup 3)
4929 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
4932 (clobber (reg:CC FLAGS_REG))])]
4933 "split_di (operands+0, 1, operands+0, operands+3);
4934 split_di (operands+1, 1, operands+1, operands+4);
4935 split_di (operands+2, 1, operands+2, operands+5);")
4937 (define_insn "adddi3_carry_rex64"
4938 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4939 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
4940 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4941 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4942 (clobber (reg:CC FLAGS_REG))]
4943 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4944 "adc{q}\t{%2, %0|%0, %2}"
4945 [(set_attr "type" "alu")
4946 (set_attr "pent_pair" "pu")
4947 (set_attr "mode" "DI")])
4949 (define_insn "*adddi3_cc_rex64"
4950 [(set (reg:CC FLAGS_REG)
4951 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4952 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4954 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4955 (plus:DI (match_dup 1) (match_dup 2)))]
4956 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4957 "add{q}\t{%2, %0|%0, %2}"
4958 [(set_attr "type" "alu")
4959 (set_attr "mode" "DI")])
4961 (define_insn "addqi3_carry"
4962 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4963 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
4964 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
4965 (match_operand:QI 2 "general_operand" "qi,qm")))
4966 (clobber (reg:CC FLAGS_REG))]
4967 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4968 "adc{b}\t{%2, %0|%0, %2}"
4969 [(set_attr "type" "alu")
4970 (set_attr "pent_pair" "pu")
4971 (set_attr "mode" "QI")])
4973 (define_insn "addhi3_carry"
4974 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4975 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
4976 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
4977 (match_operand:HI 2 "general_operand" "ri,rm")))
4978 (clobber (reg:CC FLAGS_REG))]
4979 "ix86_binary_operator_ok (PLUS, HImode, operands)"
4980 "adc{w}\t{%2, %0|%0, %2}"
4981 [(set_attr "type" "alu")
4982 (set_attr "pent_pair" "pu")
4983 (set_attr "mode" "HI")])
4985 (define_insn "addsi3_carry"
4986 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4987 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
4988 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
4989 (match_operand:SI 2 "general_operand" "ri,rm")))
4990 (clobber (reg:CC FLAGS_REG))]
4991 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4992 "adc{l}\t{%2, %0|%0, %2}"
4993 [(set_attr "type" "alu")
4994 (set_attr "pent_pair" "pu")
4995 (set_attr "mode" "SI")])
4997 (define_insn "*addsi3_carry_zext"
4998 [(set (match_operand:DI 0 "register_operand" "=r")
5000 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5001 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5002 (match_operand:SI 2 "general_operand" "rim"))))
5003 (clobber (reg:CC FLAGS_REG))]
5004 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5005 "adc{l}\t{%2, %k0|%k0, %2}"
5006 [(set_attr "type" "alu")
5007 (set_attr "pent_pair" "pu")
5008 (set_attr "mode" "SI")])
5010 (define_insn "*addsi3_cc"
5011 [(set (reg:CC FLAGS_REG)
5012 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5013 (match_operand:SI 2 "general_operand" "ri,rm")]
5015 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5016 (plus:SI (match_dup 1) (match_dup 2)))]
5017 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5018 "add{l}\t{%2, %0|%0, %2}"
5019 [(set_attr "type" "alu")
5020 (set_attr "mode" "SI")])
5022 (define_insn "addqi3_cc"
5023 [(set (reg:CC FLAGS_REG)
5024 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5025 (match_operand:QI 2 "general_operand" "qi,qm")]
5027 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5028 (plus:QI (match_dup 1) (match_dup 2)))]
5029 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5030 "add{b}\t{%2, %0|%0, %2}"
5031 [(set_attr "type" "alu")
5032 (set_attr "mode" "QI")])
5034 (define_expand "addsi3"
5035 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5036 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5037 (match_operand:SI 2 "general_operand" "")))
5038 (clobber (reg:CC FLAGS_REG))])]
5040 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5042 (define_insn "*lea_1"
5043 [(set (match_operand:SI 0 "register_operand" "=r")
5044 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5046 "lea{l}\t{%a1, %0|%0, %a1}"
5047 [(set_attr "type" "lea")
5048 (set_attr "mode" "SI")])
5050 (define_insn "*lea_1_rex64"
5051 [(set (match_operand:SI 0 "register_operand" "=r")
5052 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5054 "lea{l}\t{%a1, %0|%0, %a1}"
5055 [(set_attr "type" "lea")
5056 (set_attr "mode" "SI")])
5058 (define_insn "*lea_1_zext"
5059 [(set (match_operand:DI 0 "register_operand" "=r")
5061 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5063 "lea{l}\t{%a1, %k0|%k0, %a1}"
5064 [(set_attr "type" "lea")
5065 (set_attr "mode" "SI")])
5067 (define_insn "*lea_2_rex64"
5068 [(set (match_operand:DI 0 "register_operand" "=r")
5069 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5071 "lea{q}\t{%a1, %0|%0, %a1}"
5072 [(set_attr "type" "lea")
5073 (set_attr "mode" "DI")])
5075 ;; The lea patterns for non-Pmodes needs to be matched by several
5076 ;; insns converted to real lea by splitters.
5078 (define_insn_and_split "*lea_general_1"
5079 [(set (match_operand 0 "register_operand" "=r")
5080 (plus (plus (match_operand 1 "index_register_operand" "l")
5081 (match_operand 2 "register_operand" "r"))
5082 (match_operand 3 "immediate_operand" "i")))]
5083 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5084 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5085 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5086 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5087 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5088 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5089 || GET_MODE (operands[3]) == VOIDmode)"
5091 "&& reload_completed"
5095 operands[0] = gen_lowpart (SImode, operands[0]);
5096 operands[1] = gen_lowpart (Pmode, operands[1]);
5097 operands[2] = gen_lowpart (Pmode, operands[2]);
5098 operands[3] = gen_lowpart (Pmode, operands[3]);
5099 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5101 if (Pmode != SImode)
5102 pat = gen_rtx_SUBREG (SImode, pat, 0);
5103 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5106 [(set_attr "type" "lea")
5107 (set_attr "mode" "SI")])
5109 (define_insn_and_split "*lea_general_1_zext"
5110 [(set (match_operand:DI 0 "register_operand" "=r")
5112 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l")
5113 (match_operand:SI 2 "register_operand" "r"))
5114 (match_operand:SI 3 "immediate_operand" "i"))))]
5117 "&& reload_completed"
5119 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5121 (match_dup 3)) 0)))]
5123 operands[1] = gen_lowpart (Pmode, operands[1]);
5124 operands[2] = gen_lowpart (Pmode, operands[2]);
5125 operands[3] = gen_lowpart (Pmode, operands[3]);
5127 [(set_attr "type" "lea")
5128 (set_attr "mode" "SI")])
5130 (define_insn_and_split "*lea_general_2"
5131 [(set (match_operand 0 "register_operand" "=r")
5132 (plus (mult (match_operand 1 "index_register_operand" "l")
5133 (match_operand 2 "const248_operand" "i"))
5134 (match_operand 3 "nonmemory_operand" "ri")))]
5135 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5136 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5137 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5138 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5139 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5140 || GET_MODE (operands[3]) == VOIDmode)"
5142 "&& reload_completed"
5146 operands[0] = gen_lowpart (SImode, operands[0]);
5147 operands[1] = gen_lowpart (Pmode, operands[1]);
5148 operands[3] = gen_lowpart (Pmode, operands[3]);
5149 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5151 if (Pmode != SImode)
5152 pat = gen_rtx_SUBREG (SImode, pat, 0);
5153 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5156 [(set_attr "type" "lea")
5157 (set_attr "mode" "SI")])
5159 (define_insn_and_split "*lea_general_2_zext"
5160 [(set (match_operand:DI 0 "register_operand" "=r")
5162 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l")
5163 (match_operand:SI 2 "const248_operand" "n"))
5164 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5167 "&& reload_completed"
5169 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5171 (match_dup 3)) 0)))]
5173 operands[1] = gen_lowpart (Pmode, operands[1]);
5174 operands[3] = gen_lowpart (Pmode, operands[3]);
5176 [(set_attr "type" "lea")
5177 (set_attr "mode" "SI")])
5179 (define_insn_and_split "*lea_general_3"
5180 [(set (match_operand 0 "register_operand" "=r")
5181 (plus (plus (mult (match_operand 1 "index_register_operand" "l")
5182 (match_operand 2 "const248_operand" "i"))
5183 (match_operand 3 "register_operand" "r"))
5184 (match_operand 4 "immediate_operand" "i")))]
5185 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5186 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5187 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5188 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5189 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5191 "&& reload_completed"
5195 operands[0] = gen_lowpart (SImode, operands[0]);
5196 operands[1] = gen_lowpart (Pmode, operands[1]);
5197 operands[3] = gen_lowpart (Pmode, operands[3]);
5198 operands[4] = gen_lowpart (Pmode, operands[4]);
5199 pat = gen_rtx_PLUS (Pmode,
5200 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5204 if (Pmode != SImode)
5205 pat = gen_rtx_SUBREG (SImode, pat, 0);
5206 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5209 [(set_attr "type" "lea")
5210 (set_attr "mode" "SI")])
5212 (define_insn_and_split "*lea_general_3_zext"
5213 [(set (match_operand:DI 0 "register_operand" "=r")
5215 (plus:SI (plus:SI (mult:SI
5216 (match_operand:SI 1 "index_register_operand" "l")
5217 (match_operand:SI 2 "const248_operand" "n"))
5218 (match_operand:SI 3 "register_operand" "r"))
5219 (match_operand:SI 4 "immediate_operand" "i"))))]
5222 "&& reload_completed"
5224 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5227 (match_dup 4)) 0)))]
5229 operands[1] = gen_lowpart (Pmode, operands[1]);
5230 operands[3] = gen_lowpart (Pmode, operands[3]);
5231 operands[4] = gen_lowpart (Pmode, operands[4]);
5233 [(set_attr "type" "lea")
5234 (set_attr "mode" "SI")])
5236 (define_insn "*adddi_1_rex64"
5237 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5238 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5239 (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
5240 (clobber (reg:CC FLAGS_REG))]
5241 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5243 switch (get_attr_type (insn))
5246 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5247 return "lea{q}\t{%a2, %0|%0, %a2}";
5250 if (! rtx_equal_p (operands[0], operands[1]))
5252 if (operands[2] == const1_rtx)
5253 return "inc{q}\t%0";
5254 else if (operands[2] == constm1_rtx)
5255 return "dec{q}\t%0";
5260 if (! rtx_equal_p (operands[0], operands[1]))
5263 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5264 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5265 if (GET_CODE (operands[2]) == CONST_INT
5266 /* Avoid overflows. */
5267 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5268 && (INTVAL (operands[2]) == 128
5269 || (INTVAL (operands[2]) < 0
5270 && INTVAL (operands[2]) != -128)))
5272 operands[2] = GEN_INT (-INTVAL (operands[2]));
5273 return "sub{q}\t{%2, %0|%0, %2}";
5275 return "add{q}\t{%2, %0|%0, %2}";
5279 (cond [(eq_attr "alternative" "2")
5280 (const_string "lea")
5281 ; Current assemblers are broken and do not allow @GOTOFF in
5282 ; ought but a memory context.
5283 (match_operand:DI 2 "pic_symbolic_operand" "")
5284 (const_string "lea")
5285 (match_operand:DI 2 "incdec_operand" "")
5286 (const_string "incdec")
5288 (const_string "alu")))
5289 (set_attr "mode" "DI")])
5291 ;; Convert lea to the lea pattern to avoid flags dependency.
5293 [(set (match_operand:DI 0 "register_operand" "")
5294 (plus:DI (match_operand:DI 1 "register_operand" "")
5295 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5296 (clobber (reg:CC FLAGS_REG))]
5297 "TARGET_64BIT && reload_completed
5298 && true_regnum (operands[0]) != true_regnum (operands[1])"
5300 (plus:DI (match_dup 1)
5304 (define_insn "*adddi_2_rex64"
5305 [(set (reg FLAGS_REG)
5307 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5308 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5310 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5311 (plus:DI (match_dup 1) (match_dup 2)))]
5312 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5313 && ix86_binary_operator_ok (PLUS, DImode, operands)
5314 /* Current assemblers are broken and do not allow @GOTOFF in
5315 ought but a memory context. */
5316 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5318 switch (get_attr_type (insn))
5321 if (! rtx_equal_p (operands[0], operands[1]))
5323 if (operands[2] == const1_rtx)
5324 return "inc{q}\t%0";
5325 else if (operands[2] == constm1_rtx)
5326 return "dec{q}\t%0";
5331 if (! rtx_equal_p (operands[0], operands[1]))
5333 /* ???? We ought to handle there the 32bit case too
5334 - do we need new constraint? */
5335 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5336 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5337 if (GET_CODE (operands[2]) == CONST_INT
5338 /* Avoid overflows. */
5339 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5340 && (INTVAL (operands[2]) == 128
5341 || (INTVAL (operands[2]) < 0
5342 && INTVAL (operands[2]) != -128)))
5344 operands[2] = GEN_INT (-INTVAL (operands[2]));
5345 return "sub{q}\t{%2, %0|%0, %2}";
5347 return "add{q}\t{%2, %0|%0, %2}";
5351 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5352 (const_string "incdec")
5353 (const_string "alu")))
5354 (set_attr "mode" "DI")])
5356 (define_insn "*adddi_3_rex64"
5357 [(set (reg FLAGS_REG)
5358 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5359 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5360 (clobber (match_scratch:DI 0 "=r"))]
5362 && ix86_match_ccmode (insn, CCZmode)
5363 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5364 /* Current assemblers are broken and do not allow @GOTOFF in
5365 ought but a memory context. */
5366 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5368 switch (get_attr_type (insn))
5371 if (! rtx_equal_p (operands[0], operands[1]))
5373 if (operands[2] == const1_rtx)
5374 return "inc{q}\t%0";
5375 else if (operands[2] == constm1_rtx)
5376 return "dec{q}\t%0";
5381 if (! rtx_equal_p (operands[0], operands[1]))
5383 /* ???? We ought to handle there the 32bit case too
5384 - do we need new constraint? */
5385 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5386 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5387 if (GET_CODE (operands[2]) == CONST_INT
5388 /* Avoid overflows. */
5389 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5390 && (INTVAL (operands[2]) == 128
5391 || (INTVAL (operands[2]) < 0
5392 && INTVAL (operands[2]) != -128)))
5394 operands[2] = GEN_INT (-INTVAL (operands[2]));
5395 return "sub{q}\t{%2, %0|%0, %2}";
5397 return "add{q}\t{%2, %0|%0, %2}";
5401 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5402 (const_string "incdec")
5403 (const_string "alu")))
5404 (set_attr "mode" "DI")])
5406 ; For comparisons against 1, -1 and 128, we may generate better code
5407 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5408 ; is matched then. We can't accept general immediate, because for
5409 ; case of overflows, the result is messed up.
5410 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5412 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5413 ; only for comparisons not depending on it.
5414 (define_insn "*adddi_4_rex64"
5415 [(set (reg FLAGS_REG)
5416 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5417 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5418 (clobber (match_scratch:DI 0 "=rm"))]
5420 && ix86_match_ccmode (insn, CCGCmode)"
5422 switch (get_attr_type (insn))
5425 if (operands[2] == constm1_rtx)
5426 return "inc{q}\t%0";
5427 else if (operands[2] == const1_rtx)
5428 return "dec{q}\t%0";
5433 if (! rtx_equal_p (operands[0], operands[1]))
5435 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5436 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5437 if ((INTVAL (operands[2]) == -128
5438 || (INTVAL (operands[2]) > 0
5439 && INTVAL (operands[2]) != 128))
5440 /* Avoid overflows. */
5441 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5442 return "sub{q}\t{%2, %0|%0, %2}";
5443 operands[2] = GEN_INT (-INTVAL (operands[2]));
5444 return "add{q}\t{%2, %0|%0, %2}";
5448 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5449 (const_string "incdec")
5450 (const_string "alu")))
5451 (set_attr "mode" "DI")])
5453 (define_insn "*adddi_5_rex64"
5454 [(set (reg FLAGS_REG)
5456 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5457 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5459 (clobber (match_scratch:DI 0 "=r"))]
5461 && ix86_match_ccmode (insn, CCGOCmode)
5462 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5463 /* Current assemblers are broken and do not allow @GOTOFF in
5464 ought but a memory context. */
5465 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5467 switch (get_attr_type (insn))
5470 if (! rtx_equal_p (operands[0], operands[1]))
5472 if (operands[2] == const1_rtx)
5473 return "inc{q}\t%0";
5474 else if (operands[2] == constm1_rtx)
5475 return "dec{q}\t%0";
5480 if (! rtx_equal_p (operands[0], operands[1]))
5482 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5483 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5484 if (GET_CODE (operands[2]) == CONST_INT
5485 /* Avoid overflows. */
5486 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5487 && (INTVAL (operands[2]) == 128
5488 || (INTVAL (operands[2]) < 0
5489 && INTVAL (operands[2]) != -128)))
5491 operands[2] = GEN_INT (-INTVAL (operands[2]));
5492 return "sub{q}\t{%2, %0|%0, %2}";
5494 return "add{q}\t{%2, %0|%0, %2}";
5498 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5499 (const_string "incdec")
5500 (const_string "alu")))
5501 (set_attr "mode" "DI")])
5504 (define_insn "*addsi_1"
5505 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5506 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5507 (match_operand:SI 2 "general_operand" "rmni,rni,lni")))
5508 (clobber (reg:CC FLAGS_REG))]
5509 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5511 switch (get_attr_type (insn))
5514 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5515 return "lea{l}\t{%a2, %0|%0, %a2}";
5518 if (! rtx_equal_p (operands[0], operands[1]))
5520 if (operands[2] == const1_rtx)
5521 return "inc{l}\t%0";
5522 else if (operands[2] == constm1_rtx)
5523 return "dec{l}\t%0";
5528 if (! rtx_equal_p (operands[0], operands[1]))
5531 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5532 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5533 if (GET_CODE (operands[2]) == CONST_INT
5534 && (INTVAL (operands[2]) == 128
5535 || (INTVAL (operands[2]) < 0
5536 && INTVAL (operands[2]) != -128)))
5538 operands[2] = GEN_INT (-INTVAL (operands[2]));
5539 return "sub{l}\t{%2, %0|%0, %2}";
5541 return "add{l}\t{%2, %0|%0, %2}";
5545 (cond [(eq_attr "alternative" "2")
5546 (const_string "lea")
5547 ; Current assemblers are broken and do not allow @GOTOFF in
5548 ; ought but a memory context.
5549 (match_operand:SI 2 "pic_symbolic_operand" "")
5550 (const_string "lea")
5551 (match_operand:SI 2 "incdec_operand" "")
5552 (const_string "incdec")
5554 (const_string "alu")))
5555 (set_attr "mode" "SI")])
5557 ;; Convert lea to the lea pattern to avoid flags dependency.
5559 [(set (match_operand 0 "register_operand" "")
5560 (plus (match_operand 1 "register_operand" "")
5561 (match_operand 2 "nonmemory_operand" "")))
5562 (clobber (reg:CC FLAGS_REG))]
5564 && true_regnum (operands[0]) != true_regnum (operands[1])"
5568 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5569 may confuse gen_lowpart. */
5570 if (GET_MODE (operands[0]) != Pmode)
5572 operands[1] = gen_lowpart (Pmode, operands[1]);
5573 operands[2] = gen_lowpart (Pmode, operands[2]);
5575 operands[0] = gen_lowpart (SImode, operands[0]);
5576 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5577 if (Pmode != SImode)
5578 pat = gen_rtx_SUBREG (SImode, pat, 0);
5579 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5583 ;; It may seem that nonimmediate operand is proper one for operand 1.
5584 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5585 ;; we take care in ix86_binary_operator_ok to not allow two memory
5586 ;; operands so proper swapping will be done in reload. This allow
5587 ;; patterns constructed from addsi_1 to match.
5588 (define_insn "addsi_1_zext"
5589 [(set (match_operand:DI 0 "register_operand" "=r,r")
5591 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5592 (match_operand:SI 2 "general_operand" "rmni,lni"))))
5593 (clobber (reg:CC FLAGS_REG))]
5594 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5596 switch (get_attr_type (insn))
5599 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5600 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5603 if (operands[2] == const1_rtx)
5604 return "inc{l}\t%k0";
5605 else if (operands[2] == constm1_rtx)
5606 return "dec{l}\t%k0";
5611 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5612 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5613 if (GET_CODE (operands[2]) == CONST_INT
5614 && (INTVAL (operands[2]) == 128
5615 || (INTVAL (operands[2]) < 0
5616 && INTVAL (operands[2]) != -128)))
5618 operands[2] = GEN_INT (-INTVAL (operands[2]));
5619 return "sub{l}\t{%2, %k0|%k0, %2}";
5621 return "add{l}\t{%2, %k0|%k0, %2}";
5625 (cond [(eq_attr "alternative" "1")
5626 (const_string "lea")
5627 ; Current assemblers are broken and do not allow @GOTOFF in
5628 ; ought but a memory context.
5629 (match_operand:SI 2 "pic_symbolic_operand" "")
5630 (const_string "lea")
5631 (match_operand:SI 2 "incdec_operand" "")
5632 (const_string "incdec")
5634 (const_string "alu")))
5635 (set_attr "mode" "SI")])
5637 ;; Convert lea to the lea pattern to avoid flags dependency.
5639 [(set (match_operand:DI 0 "register_operand" "")
5641 (plus:SI (match_operand:SI 1 "register_operand" "")
5642 (match_operand:SI 2 "nonmemory_operand" ""))))
5643 (clobber (reg:CC FLAGS_REG))]
5644 "TARGET_64BIT && reload_completed
5645 && true_regnum (operands[0]) != true_regnum (operands[1])"
5647 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5649 operands[1] = gen_lowpart (Pmode, operands[1]);
5650 operands[2] = gen_lowpart (Pmode, operands[2]);
5653 (define_insn "*addsi_2"
5654 [(set (reg FLAGS_REG)
5656 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5657 (match_operand:SI 2 "general_operand" "rmni,rni"))
5659 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5660 (plus:SI (match_dup 1) (match_dup 2)))]
5661 "ix86_match_ccmode (insn, CCGOCmode)
5662 && ix86_binary_operator_ok (PLUS, SImode, operands)
5663 /* Current assemblers are broken and do not allow @GOTOFF in
5664 ought but a memory context. */
5665 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5667 switch (get_attr_type (insn))
5670 if (! rtx_equal_p (operands[0], operands[1]))
5672 if (operands[2] == const1_rtx)
5673 return "inc{l}\t%0";
5674 else if (operands[2] == constm1_rtx)
5675 return "dec{l}\t%0";
5680 if (! rtx_equal_p (operands[0], operands[1]))
5682 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5683 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5684 if (GET_CODE (operands[2]) == CONST_INT
5685 && (INTVAL (operands[2]) == 128
5686 || (INTVAL (operands[2]) < 0
5687 && INTVAL (operands[2]) != -128)))
5689 operands[2] = GEN_INT (-INTVAL (operands[2]));
5690 return "sub{l}\t{%2, %0|%0, %2}";
5692 return "add{l}\t{%2, %0|%0, %2}";
5696 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5697 (const_string "incdec")
5698 (const_string "alu")))
5699 (set_attr "mode" "SI")])
5701 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5702 (define_insn "*addsi_2_zext"
5703 [(set (reg FLAGS_REG)
5705 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5706 (match_operand:SI 2 "general_operand" "rmni"))
5708 (set (match_operand:DI 0 "register_operand" "=r")
5709 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5710 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5711 && ix86_binary_operator_ok (PLUS, SImode, operands)
5712 /* Current assemblers are broken and do not allow @GOTOFF in
5713 ought but a memory context. */
5714 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5716 switch (get_attr_type (insn))
5719 if (operands[2] == const1_rtx)
5720 return "inc{l}\t%k0";
5721 else if (operands[2] == constm1_rtx)
5722 return "dec{l}\t%k0";
5727 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5728 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5729 if (GET_CODE (operands[2]) == CONST_INT
5730 && (INTVAL (operands[2]) == 128
5731 || (INTVAL (operands[2]) < 0
5732 && INTVAL (operands[2]) != -128)))
5734 operands[2] = GEN_INT (-INTVAL (operands[2]));
5735 return "sub{l}\t{%2, %k0|%k0, %2}";
5737 return "add{l}\t{%2, %k0|%k0, %2}";
5741 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5742 (const_string "incdec")
5743 (const_string "alu")))
5744 (set_attr "mode" "SI")])
5746 (define_insn "*addsi_3"
5747 [(set (reg FLAGS_REG)
5748 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5749 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5750 (clobber (match_scratch:SI 0 "=r"))]
5751 "ix86_match_ccmode (insn, CCZmode)
5752 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5753 /* Current assemblers are broken and do not allow @GOTOFF in
5754 ought but a memory context. */
5755 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5757 switch (get_attr_type (insn))
5760 if (! rtx_equal_p (operands[0], operands[1]))
5762 if (operands[2] == const1_rtx)
5763 return "inc{l}\t%0";
5764 else if (operands[2] == constm1_rtx)
5765 return "dec{l}\t%0";
5770 if (! rtx_equal_p (operands[0], operands[1]))
5772 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5773 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5774 if (GET_CODE (operands[2]) == CONST_INT
5775 && (INTVAL (operands[2]) == 128
5776 || (INTVAL (operands[2]) < 0
5777 && INTVAL (operands[2]) != -128)))
5779 operands[2] = GEN_INT (-INTVAL (operands[2]));
5780 return "sub{l}\t{%2, %0|%0, %2}";
5782 return "add{l}\t{%2, %0|%0, %2}";
5786 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5787 (const_string "incdec")
5788 (const_string "alu")))
5789 (set_attr "mode" "SI")])
5791 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5792 (define_insn "*addsi_3_zext"
5793 [(set (reg FLAGS_REG)
5794 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5795 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5796 (set (match_operand:DI 0 "register_operand" "=r")
5797 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5798 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5799 && ix86_binary_operator_ok (PLUS, SImode, operands)
5800 /* Current assemblers are broken and do not allow @GOTOFF in
5801 ought but a memory context. */
5802 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5804 switch (get_attr_type (insn))
5807 if (operands[2] == const1_rtx)
5808 return "inc{l}\t%k0";
5809 else if (operands[2] == constm1_rtx)
5810 return "dec{l}\t%k0";
5815 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5816 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5817 if (GET_CODE (operands[2]) == CONST_INT
5818 && (INTVAL (operands[2]) == 128
5819 || (INTVAL (operands[2]) < 0
5820 && INTVAL (operands[2]) != -128)))
5822 operands[2] = GEN_INT (-INTVAL (operands[2]));
5823 return "sub{l}\t{%2, %k0|%k0, %2}";
5825 return "add{l}\t{%2, %k0|%k0, %2}";
5829 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5830 (const_string "incdec")
5831 (const_string "alu")))
5832 (set_attr "mode" "SI")])
5834 ; For comparisons against 1, -1 and 128, we may generate better code
5835 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5836 ; is matched then. We can't accept general immediate, because for
5837 ; case of overflows, the result is messed up.
5838 ; This pattern also don't hold of 0x80000000, since the value overflows
5840 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5841 ; only for comparisons not depending on it.
5842 (define_insn "*addsi_4"
5843 [(set (reg FLAGS_REG)
5844 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5845 (match_operand:SI 2 "const_int_operand" "n")))
5846 (clobber (match_scratch:SI 0 "=rm"))]
5847 "ix86_match_ccmode (insn, CCGCmode)
5848 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5850 switch (get_attr_type (insn))
5853 if (operands[2] == constm1_rtx)
5854 return "inc{l}\t%0";
5855 else if (operands[2] == const1_rtx)
5856 return "dec{l}\t%0";
5861 if (! rtx_equal_p (operands[0], operands[1]))
5863 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5864 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5865 if ((INTVAL (operands[2]) == -128
5866 || (INTVAL (operands[2]) > 0
5867 && INTVAL (operands[2]) != 128)))
5868 return "sub{l}\t{%2, %0|%0, %2}";
5869 operands[2] = GEN_INT (-INTVAL (operands[2]));
5870 return "add{l}\t{%2, %0|%0, %2}";
5874 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5875 (const_string "incdec")
5876 (const_string "alu")))
5877 (set_attr "mode" "SI")])
5879 (define_insn "*addsi_5"
5880 [(set (reg FLAGS_REG)
5882 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5883 (match_operand:SI 2 "general_operand" "rmni"))
5885 (clobber (match_scratch:SI 0 "=r"))]
5886 "ix86_match_ccmode (insn, CCGOCmode)
5887 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5888 /* Current assemblers are broken and do not allow @GOTOFF in
5889 ought but a memory context. */
5890 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5892 switch (get_attr_type (insn))
5895 if (! rtx_equal_p (operands[0], operands[1]))
5897 if (operands[2] == const1_rtx)
5898 return "inc{l}\t%0";
5899 else if (operands[2] == constm1_rtx)
5900 return "dec{l}\t%0";
5905 if (! rtx_equal_p (operands[0], operands[1]))
5907 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5908 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5909 if (GET_CODE (operands[2]) == CONST_INT
5910 && (INTVAL (operands[2]) == 128
5911 || (INTVAL (operands[2]) < 0
5912 && INTVAL (operands[2]) != -128)))
5914 operands[2] = GEN_INT (-INTVAL (operands[2]));
5915 return "sub{l}\t{%2, %0|%0, %2}";
5917 return "add{l}\t{%2, %0|%0, %2}";
5921 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5922 (const_string "incdec")
5923 (const_string "alu")))
5924 (set_attr "mode" "SI")])
5926 (define_expand "addhi3"
5927 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5928 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5929 (match_operand:HI 2 "general_operand" "")))
5930 (clobber (reg:CC FLAGS_REG))])]
5931 "TARGET_HIMODE_MATH"
5932 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5934 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5935 ;; type optimizations enabled by define-splits. This is not important
5936 ;; for PII, and in fact harmful because of partial register stalls.
5938 (define_insn "*addhi_1_lea"
5939 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5940 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5941 (match_operand:HI 2 "general_operand" "ri,rm,lni")))
5942 (clobber (reg:CC FLAGS_REG))]
5943 "!TARGET_PARTIAL_REG_STALL
5944 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5946 switch (get_attr_type (insn))
5951 if (operands[2] == const1_rtx)
5952 return "inc{w}\t%0";
5953 else if (operands[2] == constm1_rtx)
5954 return "dec{w}\t%0";
5958 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5959 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5960 if (GET_CODE (operands[2]) == CONST_INT
5961 && (INTVAL (operands[2]) == 128
5962 || (INTVAL (operands[2]) < 0
5963 && INTVAL (operands[2]) != -128)))
5965 operands[2] = GEN_INT (-INTVAL (operands[2]));
5966 return "sub{w}\t{%2, %0|%0, %2}";
5968 return "add{w}\t{%2, %0|%0, %2}";
5972 (if_then_else (eq_attr "alternative" "2")
5973 (const_string "lea")
5974 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5975 (const_string "incdec")
5976 (const_string "alu"))))
5977 (set_attr "mode" "HI,HI,SI")])
5979 (define_insn "*addhi_1"
5980 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5981 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5982 (match_operand:HI 2 "general_operand" "ri,rm")))
5983 (clobber (reg:CC FLAGS_REG))]
5984 "TARGET_PARTIAL_REG_STALL
5985 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5987 switch (get_attr_type (insn))
5990 if (operands[2] == const1_rtx)
5991 return "inc{w}\t%0";
5992 else if (operands[2] == constm1_rtx)
5993 return "dec{w}\t%0";
5997 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5998 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5999 if (GET_CODE (operands[2]) == CONST_INT
6000 && (INTVAL (operands[2]) == 128
6001 || (INTVAL (operands[2]) < 0
6002 && INTVAL (operands[2]) != -128)))
6004 operands[2] = GEN_INT (-INTVAL (operands[2]));
6005 return "sub{w}\t{%2, %0|%0, %2}";
6007 return "add{w}\t{%2, %0|%0, %2}";
6011 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6012 (const_string "incdec")
6013 (const_string "alu")))
6014 (set_attr "mode" "HI")])
6016 (define_insn "*addhi_2"
6017 [(set (reg FLAGS_REG)
6019 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6020 (match_operand:HI 2 "general_operand" "rmni,rni"))
6022 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6023 (plus:HI (match_dup 1) (match_dup 2)))]
6024 "ix86_match_ccmode (insn, CCGOCmode)
6025 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6027 switch (get_attr_type (insn))
6030 if (operands[2] == const1_rtx)
6031 return "inc{w}\t%0";
6032 else if (operands[2] == constm1_rtx)
6033 return "dec{w}\t%0";
6037 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6038 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6039 if (GET_CODE (operands[2]) == CONST_INT
6040 && (INTVAL (operands[2]) == 128
6041 || (INTVAL (operands[2]) < 0
6042 && INTVAL (operands[2]) != -128)))
6044 operands[2] = GEN_INT (-INTVAL (operands[2]));
6045 return "sub{w}\t{%2, %0|%0, %2}";
6047 return "add{w}\t{%2, %0|%0, %2}";
6051 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6052 (const_string "incdec")
6053 (const_string "alu")))
6054 (set_attr "mode" "HI")])
6056 (define_insn "*addhi_3"
6057 [(set (reg FLAGS_REG)
6058 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6059 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6060 (clobber (match_scratch:HI 0 "=r"))]
6061 "ix86_match_ccmode (insn, CCZmode)
6062 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6064 switch (get_attr_type (insn))
6067 if (operands[2] == const1_rtx)
6068 return "inc{w}\t%0";
6069 else if (operands[2] == constm1_rtx)
6070 return "dec{w}\t%0";
6074 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6075 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6076 if (GET_CODE (operands[2]) == CONST_INT
6077 && (INTVAL (operands[2]) == 128
6078 || (INTVAL (operands[2]) < 0
6079 && INTVAL (operands[2]) != -128)))
6081 operands[2] = GEN_INT (-INTVAL (operands[2]));
6082 return "sub{w}\t{%2, %0|%0, %2}";
6084 return "add{w}\t{%2, %0|%0, %2}";
6088 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6089 (const_string "incdec")
6090 (const_string "alu")))
6091 (set_attr "mode" "HI")])
6093 ; See comments above addsi_3_imm for details.
6094 (define_insn "*addhi_4"
6095 [(set (reg FLAGS_REG)
6096 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6097 (match_operand:HI 2 "const_int_operand" "n")))
6098 (clobber (match_scratch:HI 0 "=rm"))]
6099 "ix86_match_ccmode (insn, CCGCmode)
6100 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6102 switch (get_attr_type (insn))
6105 if (operands[2] == constm1_rtx)
6106 return "inc{w}\t%0";
6107 else if (operands[2] == const1_rtx)
6108 return "dec{w}\t%0";
6113 if (! rtx_equal_p (operands[0], operands[1]))
6115 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6116 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6117 if ((INTVAL (operands[2]) == -128
6118 || (INTVAL (operands[2]) > 0
6119 && INTVAL (operands[2]) != 128)))
6120 return "sub{w}\t{%2, %0|%0, %2}";
6121 operands[2] = GEN_INT (-INTVAL (operands[2]));
6122 return "add{w}\t{%2, %0|%0, %2}";
6126 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6127 (const_string "incdec")
6128 (const_string "alu")))
6129 (set_attr "mode" "SI")])
6132 (define_insn "*addhi_5"
6133 [(set (reg FLAGS_REG)
6135 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6136 (match_operand:HI 2 "general_operand" "rmni"))
6138 (clobber (match_scratch:HI 0 "=r"))]
6139 "ix86_match_ccmode (insn, CCGOCmode)
6140 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6142 switch (get_attr_type (insn))
6145 if (operands[2] == const1_rtx)
6146 return "inc{w}\t%0";
6147 else if (operands[2] == constm1_rtx)
6148 return "dec{w}\t%0";
6152 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6153 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6154 if (GET_CODE (operands[2]) == CONST_INT
6155 && (INTVAL (operands[2]) == 128
6156 || (INTVAL (operands[2]) < 0
6157 && INTVAL (operands[2]) != -128)))
6159 operands[2] = GEN_INT (-INTVAL (operands[2]));
6160 return "sub{w}\t{%2, %0|%0, %2}";
6162 return "add{w}\t{%2, %0|%0, %2}";
6166 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6167 (const_string "incdec")
6168 (const_string "alu")))
6169 (set_attr "mode" "HI")])
6171 (define_expand "addqi3"
6172 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6173 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6174 (match_operand:QI 2 "general_operand" "")))
6175 (clobber (reg:CC FLAGS_REG))])]
6176 "TARGET_QIMODE_MATH"
6177 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6179 ;; %%% Potential partial reg stall on alternative 2. What to do?
6180 (define_insn "*addqi_1_lea"
6181 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6182 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6183 (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
6184 (clobber (reg:CC FLAGS_REG))]
6185 "!TARGET_PARTIAL_REG_STALL
6186 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6188 int widen = (which_alternative == 2);
6189 switch (get_attr_type (insn))
6194 if (operands[2] == const1_rtx)
6195 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6196 else if (operands[2] == constm1_rtx)
6197 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6201 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6202 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6203 if (GET_CODE (operands[2]) == CONST_INT
6204 && (INTVAL (operands[2]) == 128
6205 || (INTVAL (operands[2]) < 0
6206 && INTVAL (operands[2]) != -128)))
6208 operands[2] = GEN_INT (-INTVAL (operands[2]));
6210 return "sub{l}\t{%2, %k0|%k0, %2}";
6212 return "sub{b}\t{%2, %0|%0, %2}";
6215 return "add{l}\t{%k2, %k0|%k0, %k2}";
6217 return "add{b}\t{%2, %0|%0, %2}";
6221 (if_then_else (eq_attr "alternative" "3")
6222 (const_string "lea")
6223 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6224 (const_string "incdec")
6225 (const_string "alu"))))
6226 (set_attr "mode" "QI,QI,SI,SI")])
6228 (define_insn "*addqi_1"
6229 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6230 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6231 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6232 (clobber (reg:CC FLAGS_REG))]
6233 "TARGET_PARTIAL_REG_STALL
6234 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6236 int widen = (which_alternative == 2);
6237 switch (get_attr_type (insn))
6240 if (operands[2] == const1_rtx)
6241 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6242 else if (operands[2] == constm1_rtx)
6243 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6247 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6248 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6249 if (GET_CODE (operands[2]) == CONST_INT
6250 && (INTVAL (operands[2]) == 128
6251 || (INTVAL (operands[2]) < 0
6252 && INTVAL (operands[2]) != -128)))
6254 operands[2] = GEN_INT (-INTVAL (operands[2]));
6256 return "sub{l}\t{%2, %k0|%k0, %2}";
6258 return "sub{b}\t{%2, %0|%0, %2}";
6261 return "add{l}\t{%k2, %k0|%k0, %k2}";
6263 return "add{b}\t{%2, %0|%0, %2}";
6267 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6268 (const_string "incdec")
6269 (const_string "alu")))
6270 (set_attr "mode" "QI,QI,SI")])
6272 (define_insn "*addqi_1_slp"
6273 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6274 (plus:QI (match_dup 0)
6275 (match_operand:QI 1 "general_operand" "qn,qnm")))
6276 (clobber (reg:CC FLAGS_REG))]
6277 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6278 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6280 switch (get_attr_type (insn))
6283 if (operands[1] == const1_rtx)
6284 return "inc{b}\t%0";
6285 else if (operands[1] == constm1_rtx)
6286 return "dec{b}\t%0";
6290 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6291 if (GET_CODE (operands[1]) == CONST_INT
6292 && INTVAL (operands[1]) < 0)
6294 operands[1] = GEN_INT (-INTVAL (operands[1]));
6295 return "sub{b}\t{%1, %0|%0, %1}";
6297 return "add{b}\t{%1, %0|%0, %1}";
6301 (if_then_else (match_operand:QI 1 "incdec_operand" "")
6302 (const_string "incdec")
6303 (const_string "alu1")))
6304 (set_attr "mode" "QI")])
6306 (define_insn "*addqi_2"
6307 [(set (reg FLAGS_REG)
6309 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6310 (match_operand:QI 2 "general_operand" "qmni,qni"))
6312 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6313 (plus:QI (match_dup 1) (match_dup 2)))]
6314 "ix86_match_ccmode (insn, CCGOCmode)
6315 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6317 switch (get_attr_type (insn))
6320 if (operands[2] == const1_rtx)
6321 return "inc{b}\t%0";
6322 else if (operands[2] == constm1_rtx
6323 || (GET_CODE (operands[2]) == CONST_INT
6324 && INTVAL (operands[2]) == 255))
6325 return "dec{b}\t%0";
6329 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6330 if (GET_CODE (operands[2]) == CONST_INT
6331 && INTVAL (operands[2]) < 0)
6333 operands[2] = GEN_INT (-INTVAL (operands[2]));
6334 return "sub{b}\t{%2, %0|%0, %2}";
6336 return "add{b}\t{%2, %0|%0, %2}";
6340 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6341 (const_string "incdec")
6342 (const_string "alu")))
6343 (set_attr "mode" "QI")])
6345 (define_insn "*addqi_3"
6346 [(set (reg FLAGS_REG)
6347 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6348 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6349 (clobber (match_scratch:QI 0 "=q"))]
6350 "ix86_match_ccmode (insn, CCZmode)
6351 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6353 switch (get_attr_type (insn))
6356 if (operands[2] == const1_rtx)
6357 return "inc{b}\t%0";
6358 else if (operands[2] == constm1_rtx
6359 || (GET_CODE (operands[2]) == CONST_INT
6360 && INTVAL (operands[2]) == 255))
6361 return "dec{b}\t%0";
6365 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6366 if (GET_CODE (operands[2]) == CONST_INT
6367 && INTVAL (operands[2]) < 0)
6369 operands[2] = GEN_INT (-INTVAL (operands[2]));
6370 return "sub{b}\t{%2, %0|%0, %2}";
6372 return "add{b}\t{%2, %0|%0, %2}";
6376 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6377 (const_string "incdec")
6378 (const_string "alu")))
6379 (set_attr "mode" "QI")])
6381 ; See comments above addsi_3_imm for details.
6382 (define_insn "*addqi_4"
6383 [(set (reg FLAGS_REG)
6384 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6385 (match_operand:QI 2 "const_int_operand" "n")))
6386 (clobber (match_scratch:QI 0 "=qm"))]
6387 "ix86_match_ccmode (insn, CCGCmode)
6388 && (INTVAL (operands[2]) & 0xff) != 0x80"
6390 switch (get_attr_type (insn))
6393 if (operands[2] == constm1_rtx
6394 || (GET_CODE (operands[2]) == CONST_INT
6395 && INTVAL (operands[2]) == 255))
6396 return "inc{b}\t%0";
6397 else if (operands[2] == const1_rtx)
6398 return "dec{b}\t%0";
6403 if (! rtx_equal_p (operands[0], operands[1]))
6405 if (INTVAL (operands[2]) < 0)
6407 operands[2] = GEN_INT (-INTVAL (operands[2]));
6408 return "add{b}\t{%2, %0|%0, %2}";
6410 return "sub{b}\t{%2, %0|%0, %2}";
6414 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6415 (const_string "incdec")
6416 (const_string "alu")))
6417 (set_attr "mode" "QI")])
6420 (define_insn "*addqi_5"
6421 [(set (reg FLAGS_REG)
6423 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6424 (match_operand:QI 2 "general_operand" "qmni"))
6426 (clobber (match_scratch:QI 0 "=q"))]
6427 "ix86_match_ccmode (insn, CCGOCmode)
6428 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6430 switch (get_attr_type (insn))
6433 if (operands[2] == const1_rtx)
6434 return "inc{b}\t%0";
6435 else if (operands[2] == constm1_rtx
6436 || (GET_CODE (operands[2]) == CONST_INT
6437 && INTVAL (operands[2]) == 255))
6438 return "dec{b}\t%0";
6442 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6443 if (GET_CODE (operands[2]) == CONST_INT
6444 && INTVAL (operands[2]) < 0)
6446 operands[2] = GEN_INT (-INTVAL (operands[2]));
6447 return "sub{b}\t{%2, %0|%0, %2}";
6449 return "add{b}\t{%2, %0|%0, %2}";
6453 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6454 (const_string "incdec")
6455 (const_string "alu")))
6456 (set_attr "mode" "QI")])
6459 (define_insn "addqi_ext_1"
6460 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6465 (match_operand 1 "ext_register_operand" "0")
6468 (match_operand:QI 2 "general_operand" "Qmn")))
6469 (clobber (reg:CC FLAGS_REG))]
6472 switch (get_attr_type (insn))
6475 if (operands[2] == const1_rtx)
6476 return "inc{b}\t%h0";
6477 else if (operands[2] == constm1_rtx
6478 || (GET_CODE (operands[2]) == CONST_INT
6479 && INTVAL (operands[2]) == 255))
6480 return "dec{b}\t%h0";
6484 return "add{b}\t{%2, %h0|%h0, %2}";
6488 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6489 (const_string "incdec")
6490 (const_string "alu")))
6491 (set_attr "mode" "QI")])
6493 (define_insn "*addqi_ext_1_rex64"
6494 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6499 (match_operand 1 "ext_register_operand" "0")
6502 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6503 (clobber (reg:CC FLAGS_REG))]
6506 switch (get_attr_type (insn))
6509 if (operands[2] == const1_rtx)
6510 return "inc{b}\t%h0";
6511 else if (operands[2] == constm1_rtx
6512 || (GET_CODE (operands[2]) == CONST_INT
6513 && INTVAL (operands[2]) == 255))
6514 return "dec{b}\t%h0";
6518 return "add{b}\t{%2, %h0|%h0, %2}";
6522 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6523 (const_string "incdec")
6524 (const_string "alu")))
6525 (set_attr "mode" "QI")])
6527 (define_insn "*addqi_ext_2"
6528 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6533 (match_operand 1 "ext_register_operand" "%0")
6537 (match_operand 2 "ext_register_operand" "Q")
6540 (clobber (reg:CC FLAGS_REG))]
6542 "add{b}\t{%h2, %h0|%h0, %h2}"
6543 [(set_attr "type" "alu")
6544 (set_attr "mode" "QI")])
6546 ;; The patterns that match these are at the end of this file.
6548 (define_expand "addxf3"
6549 [(set (match_operand:XF 0 "register_operand" "")
6550 (plus:XF (match_operand:XF 1 "register_operand" "")
6551 (match_operand:XF 2 "register_operand" "")))]
6555 (define_expand "adddf3"
6556 [(set (match_operand:DF 0 "register_operand" "")
6557 (plus:DF (match_operand:DF 1 "register_operand" "")
6558 (match_operand:DF 2 "nonimmediate_operand" "")))]
6559 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6562 (define_expand "addsf3"
6563 [(set (match_operand:SF 0 "register_operand" "")
6564 (plus:SF (match_operand:SF 1 "register_operand" "")
6565 (match_operand:SF 2 "nonimmediate_operand" "")))]
6566 "TARGET_80387 || TARGET_SSE_MATH"
6569 ;; Subtract instructions
6571 ;; %%% splits for subsidi3
6573 (define_expand "subdi3"
6574 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6575 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6576 (match_operand:DI 2 "x86_64_general_operand" "")))
6577 (clobber (reg:CC FLAGS_REG))])]
6579 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6581 (define_insn "*subdi3_1"
6582 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6583 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6584 (match_operand:DI 2 "general_operand" "roiF,riF")))
6585 (clobber (reg:CC FLAGS_REG))]
6586 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6590 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6591 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6592 (match_operand:DI 2 "general_operand" "")))
6593 (clobber (reg:CC FLAGS_REG))]
6594 "!TARGET_64BIT && reload_completed"
6595 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
6596 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6597 (parallel [(set (match_dup 3)
6598 (minus:SI (match_dup 4)
6599 (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
6601 (clobber (reg:CC FLAGS_REG))])]
6602 "split_di (operands+0, 1, operands+0, operands+3);
6603 split_di (operands+1, 1, operands+1, operands+4);
6604 split_di (operands+2, 1, operands+2, operands+5);")
6606 (define_insn "subdi3_carry_rex64"
6607 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6608 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6609 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6610 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6611 (clobber (reg:CC FLAGS_REG))]
6612 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6613 "sbb{q}\t{%2, %0|%0, %2}"
6614 [(set_attr "type" "alu")
6615 (set_attr "pent_pair" "pu")
6616 (set_attr "mode" "DI")])
6618 (define_insn "*subdi_1_rex64"
6619 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6620 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6621 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6622 (clobber (reg:CC FLAGS_REG))]
6623 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6624 "sub{q}\t{%2, %0|%0, %2}"
6625 [(set_attr "type" "alu")
6626 (set_attr "mode" "DI")])
6628 (define_insn "*subdi_2_rex64"
6629 [(set (reg FLAGS_REG)
6631 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6632 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6634 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6635 (minus:DI (match_dup 1) (match_dup 2)))]
6636 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6637 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6638 "sub{q}\t{%2, %0|%0, %2}"
6639 [(set_attr "type" "alu")
6640 (set_attr "mode" "DI")])
6642 (define_insn "*subdi_3_rex63"
6643 [(set (reg FLAGS_REG)
6644 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6645 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6646 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6647 (minus:DI (match_dup 1) (match_dup 2)))]
6648 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6649 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6650 "sub{q}\t{%2, %0|%0, %2}"
6651 [(set_attr "type" "alu")
6652 (set_attr "mode" "DI")])
6654 (define_insn "subqi3_carry"
6655 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6656 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6657 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6658 (match_operand:QI 2 "general_operand" "qi,qm"))))
6659 (clobber (reg:CC FLAGS_REG))]
6660 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6661 "sbb{b}\t{%2, %0|%0, %2}"
6662 [(set_attr "type" "alu")
6663 (set_attr "pent_pair" "pu")
6664 (set_attr "mode" "QI")])
6666 (define_insn "subhi3_carry"
6667 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6668 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6669 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6670 (match_operand:HI 2 "general_operand" "ri,rm"))))
6671 (clobber (reg:CC FLAGS_REG))]
6672 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6673 "sbb{w}\t{%2, %0|%0, %2}"
6674 [(set_attr "type" "alu")
6675 (set_attr "pent_pair" "pu")
6676 (set_attr "mode" "HI")])
6678 (define_insn "subsi3_carry"
6679 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6680 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6681 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6682 (match_operand:SI 2 "general_operand" "ri,rm"))))
6683 (clobber (reg:CC FLAGS_REG))]
6684 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6685 "sbb{l}\t{%2, %0|%0, %2}"
6686 [(set_attr "type" "alu")
6687 (set_attr "pent_pair" "pu")
6688 (set_attr "mode" "SI")])
6690 (define_insn "subsi3_carry_zext"
6691 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6693 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6694 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6695 (match_operand:SI 2 "general_operand" "ri,rm")))))
6696 (clobber (reg:CC FLAGS_REG))]
6697 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6698 "sbb{l}\t{%2, %k0|%k0, %2}"
6699 [(set_attr "type" "alu")
6700 (set_attr "pent_pair" "pu")
6701 (set_attr "mode" "SI")])
6703 (define_expand "subsi3"
6704 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6705 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6706 (match_operand:SI 2 "general_operand" "")))
6707 (clobber (reg:CC FLAGS_REG))])]
6709 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6711 (define_insn "*subsi_1"
6712 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6713 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6714 (match_operand:SI 2 "general_operand" "ri,rm")))
6715 (clobber (reg:CC FLAGS_REG))]
6716 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6717 "sub{l}\t{%2, %0|%0, %2}"
6718 [(set_attr "type" "alu")
6719 (set_attr "mode" "SI")])
6721 (define_insn "*subsi_1_zext"
6722 [(set (match_operand:DI 0 "register_operand" "=r")
6724 (minus:SI (match_operand:SI 1 "register_operand" "0")
6725 (match_operand:SI 2 "general_operand" "rim"))))
6726 (clobber (reg:CC FLAGS_REG))]
6727 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6728 "sub{l}\t{%2, %k0|%k0, %2}"
6729 [(set_attr "type" "alu")
6730 (set_attr "mode" "SI")])
6732 (define_insn "*subsi_2"
6733 [(set (reg FLAGS_REG)
6735 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6736 (match_operand:SI 2 "general_operand" "ri,rm"))
6738 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6739 (minus:SI (match_dup 1) (match_dup 2)))]
6740 "ix86_match_ccmode (insn, CCGOCmode)
6741 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6742 "sub{l}\t{%2, %0|%0, %2}"
6743 [(set_attr "type" "alu")
6744 (set_attr "mode" "SI")])
6746 (define_insn "*subsi_2_zext"
6747 [(set (reg FLAGS_REG)
6749 (minus:SI (match_operand:SI 1 "register_operand" "0")
6750 (match_operand:SI 2 "general_operand" "rim"))
6752 (set (match_operand:DI 0 "register_operand" "=r")
6754 (minus:SI (match_dup 1)
6756 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6757 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6758 "sub{l}\t{%2, %k0|%k0, %2}"
6759 [(set_attr "type" "alu")
6760 (set_attr "mode" "SI")])
6762 (define_insn "*subsi_3"
6763 [(set (reg FLAGS_REG)
6764 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6765 (match_operand:SI 2 "general_operand" "ri,rm")))
6766 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6767 (minus:SI (match_dup 1) (match_dup 2)))]
6768 "ix86_match_ccmode (insn, CCmode)
6769 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6770 "sub{l}\t{%2, %0|%0, %2}"
6771 [(set_attr "type" "alu")
6772 (set_attr "mode" "SI")])
6774 (define_insn "*subsi_3_zext"
6775 [(set (reg FLAGS_REG)
6776 (compare (match_operand:SI 1 "register_operand" "0")
6777 (match_operand:SI 2 "general_operand" "rim")))
6778 (set (match_operand:DI 0 "register_operand" "=r")
6780 (minus:SI (match_dup 1)
6782 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6783 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6784 "sub{q}\t{%2, %0|%0, %2}"
6785 [(set_attr "type" "alu")
6786 (set_attr "mode" "DI")])
6788 (define_expand "subhi3"
6789 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6790 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6791 (match_operand:HI 2 "general_operand" "")))
6792 (clobber (reg:CC FLAGS_REG))])]
6793 "TARGET_HIMODE_MATH"
6794 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6796 (define_insn "*subhi_1"
6797 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6798 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6799 (match_operand:HI 2 "general_operand" "ri,rm")))
6800 (clobber (reg:CC FLAGS_REG))]
6801 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6802 "sub{w}\t{%2, %0|%0, %2}"
6803 [(set_attr "type" "alu")
6804 (set_attr "mode" "HI")])
6806 (define_insn "*subhi_2"
6807 [(set (reg FLAGS_REG)
6809 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6810 (match_operand:HI 2 "general_operand" "ri,rm"))
6812 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6813 (minus:HI (match_dup 1) (match_dup 2)))]
6814 "ix86_match_ccmode (insn, CCGOCmode)
6815 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6816 "sub{w}\t{%2, %0|%0, %2}"
6817 [(set_attr "type" "alu")
6818 (set_attr "mode" "HI")])
6820 (define_insn "*subhi_3"
6821 [(set (reg FLAGS_REG)
6822 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6823 (match_operand:HI 2 "general_operand" "ri,rm")))
6824 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6825 (minus:HI (match_dup 1) (match_dup 2)))]
6826 "ix86_match_ccmode (insn, CCmode)
6827 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6828 "sub{w}\t{%2, %0|%0, %2}"
6829 [(set_attr "type" "alu")
6830 (set_attr "mode" "HI")])
6832 (define_expand "subqi3"
6833 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6834 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6835 (match_operand:QI 2 "general_operand" "")))
6836 (clobber (reg:CC FLAGS_REG))])]
6837 "TARGET_QIMODE_MATH"
6838 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6840 (define_insn "*subqi_1"
6841 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6842 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6843 (match_operand:QI 2 "general_operand" "qn,qmn")))
6844 (clobber (reg:CC FLAGS_REG))]
6845 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6846 "sub{b}\t{%2, %0|%0, %2}"
6847 [(set_attr "type" "alu")
6848 (set_attr "mode" "QI")])
6850 (define_insn "*subqi_1_slp"
6851 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6852 (minus:QI (match_dup 0)
6853 (match_operand:QI 1 "general_operand" "qn,qmn")))
6854 (clobber (reg:CC FLAGS_REG))]
6855 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6856 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6857 "sub{b}\t{%1, %0|%0, %1}"
6858 [(set_attr "type" "alu1")
6859 (set_attr "mode" "QI")])
6861 (define_insn "*subqi_2"
6862 [(set (reg FLAGS_REG)
6864 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6865 (match_operand:QI 2 "general_operand" "qi,qm"))
6867 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6868 (minus:HI (match_dup 1) (match_dup 2)))]
6869 "ix86_match_ccmode (insn, CCGOCmode)
6870 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6871 "sub{b}\t{%2, %0|%0, %2}"
6872 [(set_attr "type" "alu")
6873 (set_attr "mode" "QI")])
6875 (define_insn "*subqi_3"
6876 [(set (reg FLAGS_REG)
6877 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6878 (match_operand:QI 2 "general_operand" "qi,qm")))
6879 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6880 (minus:HI (match_dup 1) (match_dup 2)))]
6881 "ix86_match_ccmode (insn, CCmode)
6882 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6883 "sub{b}\t{%2, %0|%0, %2}"
6884 [(set_attr "type" "alu")
6885 (set_attr "mode" "QI")])
6887 ;; The patterns that match these are at the end of this file.
6889 (define_expand "subxf3"
6890 [(set (match_operand:XF 0 "register_operand" "")
6891 (minus:XF (match_operand:XF 1 "register_operand" "")
6892 (match_operand:XF 2 "register_operand" "")))]
6896 (define_expand "subdf3"
6897 [(set (match_operand:DF 0 "register_operand" "")
6898 (minus:DF (match_operand:DF 1 "register_operand" "")
6899 (match_operand:DF 2 "nonimmediate_operand" "")))]
6900 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6903 (define_expand "subsf3"
6904 [(set (match_operand:SF 0 "register_operand" "")
6905 (minus:SF (match_operand:SF 1 "register_operand" "")
6906 (match_operand:SF 2 "nonimmediate_operand" "")))]
6907 "TARGET_80387 || TARGET_SSE_MATH"
6910 ;; Multiply instructions
6912 (define_expand "muldi3"
6913 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6914 (mult:DI (match_operand:DI 1 "register_operand" "")
6915 (match_operand:DI 2 "x86_64_general_operand" "")))
6916 (clobber (reg:CC FLAGS_REG))])]
6920 (define_insn "*muldi3_1_rex64"
6921 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6922 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6923 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6924 (clobber (reg:CC FLAGS_REG))]
6926 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6928 imul{q}\t{%2, %1, %0|%0, %1, %2}
6929 imul{q}\t{%2, %1, %0|%0, %1, %2}
6930 imul{q}\t{%2, %0|%0, %2}"
6931 [(set_attr "type" "imul")
6932 (set_attr "prefix_0f" "0,0,1")
6933 (set (attr "athlon_decode")
6934 (cond [(eq_attr "cpu" "athlon")
6935 (const_string "vector")
6936 (eq_attr "alternative" "1")
6937 (const_string "vector")
6938 (and (eq_attr "alternative" "2")
6939 (match_operand 1 "memory_operand" ""))
6940 (const_string "vector")]
6941 (const_string "direct")))
6942 (set_attr "mode" "DI")])
6944 (define_expand "mulsi3"
6945 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6946 (mult:SI (match_operand:SI 1 "register_operand" "")
6947 (match_operand:SI 2 "general_operand" "")))
6948 (clobber (reg:CC FLAGS_REG))])]
6952 (define_insn "*mulsi3_1"
6953 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6954 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6955 (match_operand:SI 2 "general_operand" "K,i,mr")))
6956 (clobber (reg:CC FLAGS_REG))]
6957 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6959 imul{l}\t{%2, %1, %0|%0, %1, %2}
6960 imul{l}\t{%2, %1, %0|%0, %1, %2}
6961 imul{l}\t{%2, %0|%0, %2}"
6962 [(set_attr "type" "imul")
6963 (set_attr "prefix_0f" "0,0,1")
6964 (set (attr "athlon_decode")
6965 (cond [(eq_attr "cpu" "athlon")
6966 (const_string "vector")
6967 (eq_attr "alternative" "1")
6968 (const_string "vector")
6969 (and (eq_attr "alternative" "2")
6970 (match_operand 1 "memory_operand" ""))
6971 (const_string "vector")]
6972 (const_string "direct")))
6973 (set_attr "mode" "SI")])
6975 (define_insn "*mulsi3_1_zext"
6976 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6978 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6979 (match_operand:SI 2 "general_operand" "K,i,mr"))))
6980 (clobber (reg:CC FLAGS_REG))]
6982 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6984 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6985 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6986 imul{l}\t{%2, %k0|%k0, %2}"
6987 [(set_attr "type" "imul")
6988 (set_attr "prefix_0f" "0,0,1")
6989 (set (attr "athlon_decode")
6990 (cond [(eq_attr "cpu" "athlon")
6991 (const_string "vector")
6992 (eq_attr "alternative" "1")
6993 (const_string "vector")
6994 (and (eq_attr "alternative" "2")
6995 (match_operand 1 "memory_operand" ""))
6996 (const_string "vector")]
6997 (const_string "direct")))
6998 (set_attr "mode" "SI")])
7000 (define_expand "mulhi3"
7001 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7002 (mult:HI (match_operand:HI 1 "register_operand" "")
7003 (match_operand:HI 2 "general_operand" "")))
7004 (clobber (reg:CC FLAGS_REG))])]
7005 "TARGET_HIMODE_MATH"
7008 (define_insn "*mulhi3_1"
7009 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7010 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7011 (match_operand:HI 2 "general_operand" "K,i,mr")))
7012 (clobber (reg:CC FLAGS_REG))]
7013 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7015 imul{w}\t{%2, %1, %0|%0, %1, %2}
7016 imul{w}\t{%2, %1, %0|%0, %1, %2}
7017 imul{w}\t{%2, %0|%0, %2}"
7018 [(set_attr "type" "imul")
7019 (set_attr "prefix_0f" "0,0,1")
7020 (set (attr "athlon_decode")
7021 (cond [(eq_attr "cpu" "athlon")
7022 (const_string "vector")
7023 (eq_attr "alternative" "1,2")
7024 (const_string "vector")]
7025 (const_string "direct")))
7026 (set_attr "mode" "HI")])
7028 (define_expand "mulqi3"
7029 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7030 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7031 (match_operand:QI 2 "register_operand" "")))
7032 (clobber (reg:CC FLAGS_REG))])]
7033 "TARGET_QIMODE_MATH"
7036 (define_insn "*mulqi3_1"
7037 [(set (match_operand:QI 0 "register_operand" "=a")
7038 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7039 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7040 (clobber (reg:CC FLAGS_REG))]
7042 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7044 [(set_attr "type" "imul")
7045 (set_attr "length_immediate" "0")
7046 (set (attr "athlon_decode")
7047 (if_then_else (eq_attr "cpu" "athlon")
7048 (const_string "vector")
7049 (const_string "direct")))
7050 (set_attr "mode" "QI")])
7052 (define_expand "umulqihi3"
7053 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7054 (mult:HI (zero_extend:HI
7055 (match_operand:QI 1 "nonimmediate_operand" ""))
7057 (match_operand:QI 2 "register_operand" ""))))
7058 (clobber (reg:CC FLAGS_REG))])]
7059 "TARGET_QIMODE_MATH"
7062 (define_insn "*umulqihi3_1"
7063 [(set (match_operand:HI 0 "register_operand" "=a")
7064 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7065 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7066 (clobber (reg:CC FLAGS_REG))]
7068 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7070 [(set_attr "type" "imul")
7071 (set_attr "length_immediate" "0")
7072 (set (attr "athlon_decode")
7073 (if_then_else (eq_attr "cpu" "athlon")
7074 (const_string "vector")
7075 (const_string "direct")))
7076 (set_attr "mode" "QI")])
7078 (define_expand "mulqihi3"
7079 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7080 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7081 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7082 (clobber (reg:CC FLAGS_REG))])]
7083 "TARGET_QIMODE_MATH"
7086 (define_insn "*mulqihi3_insn"
7087 [(set (match_operand:HI 0 "register_operand" "=a")
7088 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7089 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7090 (clobber (reg:CC FLAGS_REG))]
7092 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7094 [(set_attr "type" "imul")
7095 (set_attr "length_immediate" "0")
7096 (set (attr "athlon_decode")
7097 (if_then_else (eq_attr "cpu" "athlon")
7098 (const_string "vector")
7099 (const_string "direct")))
7100 (set_attr "mode" "QI")])
7102 (define_expand "umulditi3"
7103 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7104 (mult:TI (zero_extend:TI
7105 (match_operand:DI 1 "nonimmediate_operand" ""))
7107 (match_operand:DI 2 "register_operand" ""))))
7108 (clobber (reg:CC FLAGS_REG))])]
7112 (define_insn "*umulditi3_insn"
7113 [(set (match_operand:TI 0 "register_operand" "=A")
7114 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7115 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7116 (clobber (reg:CC FLAGS_REG))]
7118 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7120 [(set_attr "type" "imul")
7121 (set_attr "length_immediate" "0")
7122 (set (attr "athlon_decode")
7123 (if_then_else (eq_attr "cpu" "athlon")
7124 (const_string "vector")
7125 (const_string "double")))
7126 (set_attr "mode" "DI")])
7128 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7129 (define_expand "umulsidi3"
7130 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7131 (mult:DI (zero_extend:DI
7132 (match_operand:SI 1 "nonimmediate_operand" ""))
7134 (match_operand:SI 2 "register_operand" ""))))
7135 (clobber (reg:CC FLAGS_REG))])]
7139 (define_insn "*umulsidi3_insn"
7140 [(set (match_operand:DI 0 "register_operand" "=A")
7141 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7142 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7143 (clobber (reg:CC FLAGS_REG))]
7145 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7147 [(set_attr "type" "imul")
7148 (set_attr "length_immediate" "0")
7149 (set (attr "athlon_decode")
7150 (if_then_else (eq_attr "cpu" "athlon")
7151 (const_string "vector")
7152 (const_string "double")))
7153 (set_attr "mode" "SI")])
7155 (define_expand "mulditi3"
7156 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7157 (mult:TI (sign_extend:TI
7158 (match_operand:DI 1 "nonimmediate_operand" ""))
7160 (match_operand:DI 2 "register_operand" ""))))
7161 (clobber (reg:CC FLAGS_REG))])]
7165 (define_insn "*mulditi3_insn"
7166 [(set (match_operand:TI 0 "register_operand" "=A")
7167 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7168 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7169 (clobber (reg:CC FLAGS_REG))]
7171 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7173 [(set_attr "type" "imul")
7174 (set_attr "length_immediate" "0")
7175 (set (attr "athlon_decode")
7176 (if_then_else (eq_attr "cpu" "athlon")
7177 (const_string "vector")
7178 (const_string "double")))
7179 (set_attr "mode" "DI")])
7181 (define_expand "mulsidi3"
7182 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7183 (mult:DI (sign_extend:DI
7184 (match_operand:SI 1 "nonimmediate_operand" ""))
7186 (match_operand:SI 2 "register_operand" ""))))
7187 (clobber (reg:CC FLAGS_REG))])]
7191 (define_insn "*mulsidi3_insn"
7192 [(set (match_operand:DI 0 "register_operand" "=A")
7193 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7194 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7195 (clobber (reg:CC FLAGS_REG))]
7197 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7199 [(set_attr "type" "imul")
7200 (set_attr "length_immediate" "0")
7201 (set (attr "athlon_decode")
7202 (if_then_else (eq_attr "cpu" "athlon")
7203 (const_string "vector")
7204 (const_string "double")))
7205 (set_attr "mode" "SI")])
7207 (define_expand "umuldi3_highpart"
7208 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7211 (mult:TI (zero_extend:TI
7212 (match_operand:DI 1 "nonimmediate_operand" ""))
7214 (match_operand:DI 2 "register_operand" "")))
7216 (clobber (match_scratch:DI 3 ""))
7217 (clobber (reg:CC FLAGS_REG))])]
7221 (define_insn "*umuldi3_highpart_rex64"
7222 [(set (match_operand:DI 0 "register_operand" "=d")
7225 (mult:TI (zero_extend:TI
7226 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7228 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7230 (clobber (match_scratch:DI 3 "=1"))
7231 (clobber (reg:CC FLAGS_REG))]
7233 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7235 [(set_attr "type" "imul")
7236 (set_attr "length_immediate" "0")
7237 (set (attr "athlon_decode")
7238 (if_then_else (eq_attr "cpu" "athlon")
7239 (const_string "vector")
7240 (const_string "double")))
7241 (set_attr "mode" "DI")])
7243 (define_expand "umulsi3_highpart"
7244 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7247 (mult:DI (zero_extend:DI
7248 (match_operand:SI 1 "nonimmediate_operand" ""))
7250 (match_operand:SI 2 "register_operand" "")))
7252 (clobber (match_scratch:SI 3 ""))
7253 (clobber (reg:CC FLAGS_REG))])]
7257 (define_insn "*umulsi3_highpart_insn"
7258 [(set (match_operand:SI 0 "register_operand" "=d")
7261 (mult:DI (zero_extend:DI
7262 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7264 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7266 (clobber (match_scratch:SI 3 "=1"))
7267 (clobber (reg:CC FLAGS_REG))]
7268 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7270 [(set_attr "type" "imul")
7271 (set_attr "length_immediate" "0")
7272 (set (attr "athlon_decode")
7273 (if_then_else (eq_attr "cpu" "athlon")
7274 (const_string "vector")
7275 (const_string "double")))
7276 (set_attr "mode" "SI")])
7278 (define_insn "*umulsi3_highpart_zext"
7279 [(set (match_operand:DI 0 "register_operand" "=d")
7280 (zero_extend:DI (truncate:SI
7282 (mult:DI (zero_extend:DI
7283 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7285 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7287 (clobber (match_scratch:SI 3 "=1"))
7288 (clobber (reg:CC FLAGS_REG))]
7290 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7292 [(set_attr "type" "imul")
7293 (set_attr "length_immediate" "0")
7294 (set (attr "athlon_decode")
7295 (if_then_else (eq_attr "cpu" "athlon")
7296 (const_string "vector")
7297 (const_string "double")))
7298 (set_attr "mode" "SI")])
7300 (define_expand "smuldi3_highpart"
7301 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7304 (mult:TI (sign_extend:TI
7305 (match_operand:DI 1 "nonimmediate_operand" ""))
7307 (match_operand:DI 2 "register_operand" "")))
7309 (clobber (match_scratch:DI 3 ""))
7310 (clobber (reg:CC FLAGS_REG))])]
7314 (define_insn "*smuldi3_highpart_rex64"
7315 [(set (match_operand:DI 0 "register_operand" "=d")
7318 (mult:TI (sign_extend:TI
7319 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7321 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7323 (clobber (match_scratch:DI 3 "=1"))
7324 (clobber (reg:CC FLAGS_REG))]
7326 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7328 [(set_attr "type" "imul")
7329 (set (attr "athlon_decode")
7330 (if_then_else (eq_attr "cpu" "athlon")
7331 (const_string "vector")
7332 (const_string "double")))
7333 (set_attr "mode" "DI")])
7335 (define_expand "smulsi3_highpart"
7336 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7339 (mult:DI (sign_extend:DI
7340 (match_operand:SI 1 "nonimmediate_operand" ""))
7342 (match_operand:SI 2 "register_operand" "")))
7344 (clobber (match_scratch:SI 3 ""))
7345 (clobber (reg:CC FLAGS_REG))])]
7349 (define_insn "*smulsi3_highpart_insn"
7350 [(set (match_operand:SI 0 "register_operand" "=d")
7353 (mult:DI (sign_extend:DI
7354 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7356 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7358 (clobber (match_scratch:SI 3 "=1"))
7359 (clobber (reg:CC FLAGS_REG))]
7360 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7362 [(set_attr "type" "imul")
7363 (set (attr "athlon_decode")
7364 (if_then_else (eq_attr "cpu" "athlon")
7365 (const_string "vector")
7366 (const_string "double")))
7367 (set_attr "mode" "SI")])
7369 (define_insn "*smulsi3_highpart_zext"
7370 [(set (match_operand:DI 0 "register_operand" "=d")
7371 (zero_extend:DI (truncate:SI
7373 (mult:DI (sign_extend:DI
7374 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7376 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7378 (clobber (match_scratch:SI 3 "=1"))
7379 (clobber (reg:CC FLAGS_REG))]
7381 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7383 [(set_attr "type" "imul")
7384 (set (attr "athlon_decode")
7385 (if_then_else (eq_attr "cpu" "athlon")
7386 (const_string "vector")
7387 (const_string "double")))
7388 (set_attr "mode" "SI")])
7390 ;; The patterns that match these are at the end of this file.
7392 (define_expand "mulxf3"
7393 [(set (match_operand:XF 0 "register_operand" "")
7394 (mult:XF (match_operand:XF 1 "register_operand" "")
7395 (match_operand:XF 2 "register_operand" "")))]
7399 (define_expand "muldf3"
7400 [(set (match_operand:DF 0 "register_operand" "")
7401 (mult:DF (match_operand:DF 1 "register_operand" "")
7402 (match_operand:DF 2 "nonimmediate_operand" "")))]
7403 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7406 (define_expand "mulsf3"
7407 [(set (match_operand:SF 0 "register_operand" "")
7408 (mult:SF (match_operand:SF 1 "register_operand" "")
7409 (match_operand:SF 2 "nonimmediate_operand" "")))]
7410 "TARGET_80387 || TARGET_SSE_MATH"
7413 ;; Divide instructions
7415 (define_insn "divqi3"
7416 [(set (match_operand:QI 0 "register_operand" "=a")
7417 (div:QI (match_operand:HI 1 "register_operand" "0")
7418 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7419 (clobber (reg:CC FLAGS_REG))]
7420 "TARGET_QIMODE_MATH"
7422 [(set_attr "type" "idiv")
7423 (set_attr "mode" "QI")])
7425 (define_insn "udivqi3"
7426 [(set (match_operand:QI 0 "register_operand" "=a")
7427 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7428 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7429 (clobber (reg:CC FLAGS_REG))]
7430 "TARGET_QIMODE_MATH"
7432 [(set_attr "type" "idiv")
7433 (set_attr "mode" "QI")])
7435 ;; The patterns that match these are at the end of this file.
7437 (define_expand "divxf3"
7438 [(set (match_operand:XF 0 "register_operand" "")
7439 (div:XF (match_operand:XF 1 "register_operand" "")
7440 (match_operand:XF 2 "register_operand" "")))]
7444 (define_expand "divdf3"
7445 [(set (match_operand:DF 0 "register_operand" "")
7446 (div:DF (match_operand:DF 1 "register_operand" "")
7447 (match_operand:DF 2 "nonimmediate_operand" "")))]
7448 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7451 (define_expand "divsf3"
7452 [(set (match_operand:SF 0 "register_operand" "")
7453 (div:SF (match_operand:SF 1 "register_operand" "")
7454 (match_operand:SF 2 "nonimmediate_operand" "")))]
7455 "TARGET_80387 || TARGET_SSE_MATH"
7458 ;; Remainder instructions.
7460 (define_expand "divmoddi4"
7461 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7462 (div:DI (match_operand:DI 1 "register_operand" "")
7463 (match_operand:DI 2 "nonimmediate_operand" "")))
7464 (set (match_operand:DI 3 "register_operand" "")
7465 (mod:DI (match_dup 1) (match_dup 2)))
7466 (clobber (reg:CC FLAGS_REG))])]
7470 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7471 ;; Penalize eax case slightly because it results in worse scheduling
7473 (define_insn "*divmoddi4_nocltd_rex64"
7474 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7475 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7476 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7477 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7478 (mod:DI (match_dup 2) (match_dup 3)))
7479 (clobber (reg:CC FLAGS_REG))]
7480 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7482 [(set_attr "type" "multi")])
7484 (define_insn "*divmoddi4_cltd_rex64"
7485 [(set (match_operand:DI 0 "register_operand" "=a")
7486 (div:DI (match_operand:DI 2 "register_operand" "a")
7487 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7488 (set (match_operand:DI 1 "register_operand" "=&d")
7489 (mod:DI (match_dup 2) (match_dup 3)))
7490 (clobber (reg:CC FLAGS_REG))]
7491 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7493 [(set_attr "type" "multi")])
7495 (define_insn "*divmoddi_noext_rex64"
7496 [(set (match_operand:DI 0 "register_operand" "=a")
7497 (div:DI (match_operand:DI 1 "register_operand" "0")
7498 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7499 (set (match_operand:DI 3 "register_operand" "=d")
7500 (mod:DI (match_dup 1) (match_dup 2)))
7501 (use (match_operand:DI 4 "register_operand" "3"))
7502 (clobber (reg:CC FLAGS_REG))]
7505 [(set_attr "type" "idiv")
7506 (set_attr "mode" "DI")])
7509 [(set (match_operand:DI 0 "register_operand" "")
7510 (div:DI (match_operand:DI 1 "register_operand" "")
7511 (match_operand:DI 2 "nonimmediate_operand" "")))
7512 (set (match_operand:DI 3 "register_operand" "")
7513 (mod:DI (match_dup 1) (match_dup 2)))
7514 (clobber (reg:CC FLAGS_REG))]
7515 "TARGET_64BIT && reload_completed"
7516 [(parallel [(set (match_dup 3)
7517 (ashiftrt:DI (match_dup 4) (const_int 63)))
7518 (clobber (reg:CC FLAGS_REG))])
7519 (parallel [(set (match_dup 0)
7520 (div:DI (reg:DI 0) (match_dup 2)))
7522 (mod:DI (reg:DI 0) (match_dup 2)))
7524 (clobber (reg:CC FLAGS_REG))])]
7526 /* Avoid use of cltd in favor of a mov+shift. */
7527 if (!TARGET_USE_CLTD && !optimize_size)
7529 if (true_regnum (operands[1]))
7530 emit_move_insn (operands[0], operands[1]);
7532 emit_move_insn (operands[3], operands[1]);
7533 operands[4] = operands[3];
7537 if (true_regnum (operands[1]))
7539 operands[4] = operands[1];
7544 (define_expand "divmodsi4"
7545 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7546 (div:SI (match_operand:SI 1 "register_operand" "")
7547 (match_operand:SI 2 "nonimmediate_operand" "")))
7548 (set (match_operand:SI 3 "register_operand" "")
7549 (mod:SI (match_dup 1) (match_dup 2)))
7550 (clobber (reg:CC FLAGS_REG))])]
7554 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7555 ;; Penalize eax case slightly because it results in worse scheduling
7557 (define_insn "*divmodsi4_nocltd"
7558 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7559 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7560 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7561 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7562 (mod:SI (match_dup 2) (match_dup 3)))
7563 (clobber (reg:CC FLAGS_REG))]
7564 "!optimize_size && !TARGET_USE_CLTD"
7566 [(set_attr "type" "multi")])
7568 (define_insn "*divmodsi4_cltd"
7569 [(set (match_operand:SI 0 "register_operand" "=a")
7570 (div:SI (match_operand:SI 2 "register_operand" "a")
7571 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7572 (set (match_operand:SI 1 "register_operand" "=&d")
7573 (mod:SI (match_dup 2) (match_dup 3)))
7574 (clobber (reg:CC FLAGS_REG))]
7575 "optimize_size || TARGET_USE_CLTD"
7577 [(set_attr "type" "multi")])
7579 (define_insn "*divmodsi_noext"
7580 [(set (match_operand:SI 0 "register_operand" "=a")
7581 (div:SI (match_operand:SI 1 "register_operand" "0")
7582 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7583 (set (match_operand:SI 3 "register_operand" "=d")
7584 (mod:SI (match_dup 1) (match_dup 2)))
7585 (use (match_operand:SI 4 "register_operand" "3"))
7586 (clobber (reg:CC FLAGS_REG))]
7589 [(set_attr "type" "idiv")
7590 (set_attr "mode" "SI")])
7593 [(set (match_operand:SI 0 "register_operand" "")
7594 (div:SI (match_operand:SI 1 "register_operand" "")
7595 (match_operand:SI 2 "nonimmediate_operand" "")))
7596 (set (match_operand:SI 3 "register_operand" "")
7597 (mod:SI (match_dup 1) (match_dup 2)))
7598 (clobber (reg:CC FLAGS_REG))]
7600 [(parallel [(set (match_dup 3)
7601 (ashiftrt:SI (match_dup 4) (const_int 31)))
7602 (clobber (reg:CC FLAGS_REG))])
7603 (parallel [(set (match_dup 0)
7604 (div:SI (reg:SI 0) (match_dup 2)))
7606 (mod:SI (reg:SI 0) (match_dup 2)))
7608 (clobber (reg:CC FLAGS_REG))])]
7610 /* Avoid use of cltd in favor of a mov+shift. */
7611 if (!TARGET_USE_CLTD && !optimize_size)
7613 if (true_regnum (operands[1]))
7614 emit_move_insn (operands[0], operands[1]);
7616 emit_move_insn (operands[3], operands[1]);
7617 operands[4] = operands[3];
7621 if (true_regnum (operands[1]))
7623 operands[4] = operands[1];
7627 (define_insn "divmodhi4"
7628 [(set (match_operand:HI 0 "register_operand" "=a")
7629 (div:HI (match_operand:HI 1 "register_operand" "0")
7630 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7631 (set (match_operand:HI 3 "register_operand" "=&d")
7632 (mod:HI (match_dup 1) (match_dup 2)))
7633 (clobber (reg:CC FLAGS_REG))]
7634 "TARGET_HIMODE_MATH"
7636 [(set_attr "type" "multi")
7637 (set_attr "length_immediate" "0")
7638 (set_attr "mode" "SI")])
7640 (define_insn "udivmoddi4"
7641 [(set (match_operand:DI 0 "register_operand" "=a")
7642 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7643 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7644 (set (match_operand:DI 3 "register_operand" "=&d")
7645 (umod:DI (match_dup 1) (match_dup 2)))
7646 (clobber (reg:CC FLAGS_REG))]
7648 "xor{q}\t%3, %3\;div{q}\t%2"
7649 [(set_attr "type" "multi")
7650 (set_attr "length_immediate" "0")
7651 (set_attr "mode" "DI")])
7653 (define_insn "*udivmoddi4_noext"
7654 [(set (match_operand:DI 0 "register_operand" "=a")
7655 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7656 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7657 (set (match_operand:DI 3 "register_operand" "=d")
7658 (umod:DI (match_dup 1) (match_dup 2)))
7660 (clobber (reg:CC FLAGS_REG))]
7663 [(set_attr "type" "idiv")
7664 (set_attr "mode" "DI")])
7667 [(set (match_operand:DI 0 "register_operand" "")
7668 (udiv:DI (match_operand:DI 1 "register_operand" "")
7669 (match_operand:DI 2 "nonimmediate_operand" "")))
7670 (set (match_operand:DI 3 "register_operand" "")
7671 (umod:DI (match_dup 1) (match_dup 2)))
7672 (clobber (reg:CC FLAGS_REG))]
7673 "TARGET_64BIT && reload_completed"
7674 [(set (match_dup 3) (const_int 0))
7675 (parallel [(set (match_dup 0)
7676 (udiv:DI (match_dup 1) (match_dup 2)))
7678 (umod:DI (match_dup 1) (match_dup 2)))
7680 (clobber (reg:CC FLAGS_REG))])]
7683 (define_insn "udivmodsi4"
7684 [(set (match_operand:SI 0 "register_operand" "=a")
7685 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7686 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7687 (set (match_operand:SI 3 "register_operand" "=&d")
7688 (umod:SI (match_dup 1) (match_dup 2)))
7689 (clobber (reg:CC FLAGS_REG))]
7691 "xor{l}\t%3, %3\;div{l}\t%2"
7692 [(set_attr "type" "multi")
7693 (set_attr "length_immediate" "0")
7694 (set_attr "mode" "SI")])
7696 (define_insn "*udivmodsi4_noext"
7697 [(set (match_operand:SI 0 "register_operand" "=a")
7698 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7699 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7700 (set (match_operand:SI 3 "register_operand" "=d")
7701 (umod:SI (match_dup 1) (match_dup 2)))
7703 (clobber (reg:CC FLAGS_REG))]
7706 [(set_attr "type" "idiv")
7707 (set_attr "mode" "SI")])
7710 [(set (match_operand:SI 0 "register_operand" "")
7711 (udiv:SI (match_operand:SI 1 "register_operand" "")
7712 (match_operand:SI 2 "nonimmediate_operand" "")))
7713 (set (match_operand:SI 3 "register_operand" "")
7714 (umod:SI (match_dup 1) (match_dup 2)))
7715 (clobber (reg:CC FLAGS_REG))]
7717 [(set (match_dup 3) (const_int 0))
7718 (parallel [(set (match_dup 0)
7719 (udiv:SI (match_dup 1) (match_dup 2)))
7721 (umod:SI (match_dup 1) (match_dup 2)))
7723 (clobber (reg:CC FLAGS_REG))])]
7726 (define_expand "udivmodhi4"
7727 [(set (match_dup 4) (const_int 0))
7728 (parallel [(set (match_operand:HI 0 "register_operand" "")
7729 (udiv:HI (match_operand:HI 1 "register_operand" "")
7730 (match_operand:HI 2 "nonimmediate_operand" "")))
7731 (set (match_operand:HI 3 "register_operand" "")
7732 (umod:HI (match_dup 1) (match_dup 2)))
7734 (clobber (reg:CC FLAGS_REG))])]
7735 "TARGET_HIMODE_MATH"
7736 "operands[4] = gen_reg_rtx (HImode);")
7738 (define_insn "*udivmodhi_noext"
7739 [(set (match_operand:HI 0 "register_operand" "=a")
7740 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7741 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7742 (set (match_operand:HI 3 "register_operand" "=d")
7743 (umod:HI (match_dup 1) (match_dup 2)))
7744 (use (match_operand:HI 4 "register_operand" "3"))
7745 (clobber (reg:CC FLAGS_REG))]
7748 [(set_attr "type" "idiv")
7749 (set_attr "mode" "HI")])
7751 ;; We cannot use div/idiv for double division, because it causes
7752 ;; "division by zero" on the overflow and that's not what we expect
7753 ;; from truncate. Because true (non truncating) double division is
7754 ;; never generated, we can't create this insn anyway.
7757 ; [(set (match_operand:SI 0 "register_operand" "=a")
7759 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7761 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7762 ; (set (match_operand:SI 3 "register_operand" "=d")
7764 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7765 ; (clobber (reg:CC FLAGS_REG))]
7767 ; "div{l}\t{%2, %0|%0, %2}"
7768 ; [(set_attr "type" "idiv")])
7770 ;;- Logical AND instructions
7772 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7773 ;; Note that this excludes ah.
7775 (define_insn "*testdi_1_rex64"
7776 [(set (reg FLAGS_REG)
7778 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7779 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7781 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7782 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7784 test{l}\t{%k1, %k0|%k0, %k1}
7785 test{l}\t{%k1, %k0|%k0, %k1}
7786 test{q}\t{%1, %0|%0, %1}
7787 test{q}\t{%1, %0|%0, %1}
7788 test{q}\t{%1, %0|%0, %1}"
7789 [(set_attr "type" "test")
7790 (set_attr "modrm" "0,1,0,1,1")
7791 (set_attr "mode" "SI,SI,DI,DI,DI")
7792 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7794 (define_insn "testsi_1"
7795 [(set (reg FLAGS_REG)
7797 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
7798 (match_operand:SI 1 "general_operand" "in,in,rin"))
7800 "ix86_match_ccmode (insn, CCNOmode)
7801 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7802 "test{l}\t{%1, %0|%0, %1}"
7803 [(set_attr "type" "test")
7804 (set_attr "modrm" "0,1,1")
7805 (set_attr "mode" "SI")
7806 (set_attr "pent_pair" "uv,np,uv")])
7808 (define_expand "testsi_ccno_1"
7809 [(set (reg:CCNO FLAGS_REG)
7811 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7812 (match_operand:SI 1 "nonmemory_operand" ""))
7817 (define_insn "*testhi_1"
7818 [(set (reg FLAGS_REG)
7819 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
7820 (match_operand:HI 1 "general_operand" "n,n,rn"))
7822 "ix86_match_ccmode (insn, CCNOmode)
7823 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7824 "test{w}\t{%1, %0|%0, %1}"
7825 [(set_attr "type" "test")
7826 (set_attr "modrm" "0,1,1")
7827 (set_attr "mode" "HI")
7828 (set_attr "pent_pair" "uv,np,uv")])
7830 (define_expand "testqi_ccz_1"
7831 [(set (reg:CCZ FLAGS_REG)
7832 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7833 (match_operand:QI 1 "nonmemory_operand" ""))
7838 (define_insn "*testqi_1_maybe_si"
7839 [(set (reg FLAGS_REG)
7842 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7843 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7845 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7846 && ix86_match_ccmode (insn,
7847 GET_CODE (operands[1]) == CONST_INT
7848 && INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)"
7850 if (which_alternative == 3)
7852 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
7853 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7854 return "test{l}\t{%1, %k0|%k0, %1}";
7856 return "test{b}\t{%1, %0|%0, %1}";
7858 [(set_attr "type" "test")
7859 (set_attr "modrm" "0,1,1,1")
7860 (set_attr "mode" "QI,QI,QI,SI")
7861 (set_attr "pent_pair" "uv,np,uv,np")])
7863 (define_insn "*testqi_1"
7864 [(set (reg FLAGS_REG)
7867 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm")
7868 (match_operand:QI 1 "general_operand" "n,n,qn"))
7870 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7871 && ix86_match_ccmode (insn, CCNOmode)"
7872 "test{b}\t{%1, %0|%0, %1}"
7873 [(set_attr "type" "test")
7874 (set_attr "modrm" "0,1,1")
7875 (set_attr "mode" "QI")
7876 (set_attr "pent_pair" "uv,np,uv")])
7878 (define_expand "testqi_ext_ccno_0"
7879 [(set (reg:CCNO FLAGS_REG)
7883 (match_operand 0 "ext_register_operand" "")
7886 (match_operand 1 "const_int_operand" ""))
7891 (define_insn "*testqi_ext_0"
7892 [(set (reg FLAGS_REG)
7896 (match_operand 0 "ext_register_operand" "Q")
7899 (match_operand 1 "const_int_operand" "n"))
7901 "ix86_match_ccmode (insn, CCNOmode)"
7902 "test{b}\t{%1, %h0|%h0, %1}"
7903 [(set_attr "type" "test")
7904 (set_attr "mode" "QI")
7905 (set_attr "length_immediate" "1")
7906 (set_attr "pent_pair" "np")])
7908 (define_insn "*testqi_ext_1"
7909 [(set (reg FLAGS_REG)
7913 (match_operand 0 "ext_register_operand" "Q")
7917 (match_operand:QI 1 "general_operand" "Qm")))
7919 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7920 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7921 "test{b}\t{%1, %h0|%h0, %1}"
7922 [(set_attr "type" "test")
7923 (set_attr "mode" "QI")])
7925 (define_insn "*testqi_ext_1_rex64"
7926 [(set (reg FLAGS_REG)
7930 (match_operand 0 "ext_register_operand" "Q")
7934 (match_operand:QI 1 "register_operand" "Q")))
7936 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7937 "test{b}\t{%1, %h0|%h0, %1}"
7938 [(set_attr "type" "test")
7939 (set_attr "mode" "QI")])
7941 (define_insn "*testqi_ext_2"
7942 [(set (reg FLAGS_REG)
7946 (match_operand 0 "ext_register_operand" "Q")
7950 (match_operand 1 "ext_register_operand" "Q")
7954 "ix86_match_ccmode (insn, CCNOmode)"
7955 "test{b}\t{%h1, %h0|%h0, %h1}"
7956 [(set_attr "type" "test")
7957 (set_attr "mode" "QI")])
7959 ;; Combine likes to form bit extractions for some tests. Humor it.
7960 (define_insn "*testqi_ext_3"
7961 [(set (reg FLAGS_REG)
7962 (compare (zero_extract:SI
7963 (match_operand 0 "nonimmediate_operand" "rm")
7964 (match_operand:SI 1 "const_int_operand" "")
7965 (match_operand:SI 2 "const_int_operand" ""))
7967 "ix86_match_ccmode (insn, CCNOmode)
7968 && (GET_MODE (operands[0]) == SImode
7969 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7970 || GET_MODE (operands[0]) == HImode
7971 || GET_MODE (operands[0]) == QImode)"
7974 (define_insn "*testqi_ext_3_rex64"
7975 [(set (reg FLAGS_REG)
7976 (compare (zero_extract:DI
7977 (match_operand 0 "nonimmediate_operand" "rm")
7978 (match_operand:DI 1 "const_int_operand" "")
7979 (match_operand:DI 2 "const_int_operand" ""))
7982 && ix86_match_ccmode (insn, CCNOmode)
7983 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
7984 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
7985 /* Ensure that resulting mask is zero or sign extended operand. */
7986 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7987 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
7988 && INTVAL (operands[1]) > 32))
7989 && (GET_MODE (operands[0]) == SImode
7990 || GET_MODE (operands[0]) == DImode
7991 || GET_MODE (operands[0]) == HImode
7992 || GET_MODE (operands[0]) == QImode)"
7996 [(set (match_operand 0 "flags_reg_operand" "")
7997 (match_operator 1 "compare_operator"
7999 (match_operand 2 "nonimmediate_operand" "")
8000 (match_operand 3 "const_int_operand" "")
8001 (match_operand 4 "const_int_operand" ""))
8003 "ix86_match_ccmode (insn, CCNOmode)"
8004 [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
8006 rtx val = operands[2];
8007 HOST_WIDE_INT len = INTVAL (operands[3]);
8008 HOST_WIDE_INT pos = INTVAL (operands[4]);
8010 enum machine_mode mode, submode;
8012 mode = GET_MODE (val);
8013 if (GET_CODE (val) == MEM)
8015 /* ??? Combine likes to put non-volatile mem extractions in QImode
8016 no matter the size of the test. So find a mode that works. */
8017 if (! MEM_VOLATILE_P (val))
8019 mode = smallest_mode_for_size (pos + len, MODE_INT);
8020 val = adjust_address (val, mode, 0);
8023 else if (GET_CODE (val) == SUBREG
8024 && (submode = GET_MODE (SUBREG_REG (val)),
8025 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8026 && pos + len <= GET_MODE_BITSIZE (submode))
8028 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8030 val = SUBREG_REG (val);
8032 else if (mode == HImode && pos + len <= 8)
8034 /* Small HImode tests can be converted to QImode. */
8036 val = gen_lowpart (QImode, val);
8039 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8040 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8042 operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
8045 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8046 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8047 ;; this is relatively important trick.
8048 ;; Do the conversion only post-reload to avoid limiting of the register class
8051 [(set (match_operand 0 "flags_reg_operand" "")
8052 (match_operator 1 "compare_operator"
8053 [(and (match_operand 2 "register_operand" "")
8054 (match_operand 3 "const_int_operand" ""))
8057 && QI_REG_P (operands[2])
8058 && GET_MODE (operands[2]) != QImode
8059 && ((ix86_match_ccmode (insn, CCZmode)
8060 && !(INTVAL (operands[3]) & ~(255 << 8)))
8061 || (ix86_match_ccmode (insn, CCNOmode)
8062 && !(INTVAL (operands[3]) & ~(127 << 8))))"
8065 [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
8068 "operands[2] = gen_lowpart (SImode, operands[2]);
8069 operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
8072 [(set (match_operand 0 "flags_reg_operand" "")
8073 (match_operator 1 "compare_operator"
8074 [(and (match_operand 2 "nonimmediate_operand" "")
8075 (match_operand 3 "const_int_operand" ""))
8078 && GET_MODE (operands[2]) != QImode
8079 && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2]))
8080 && ((ix86_match_ccmode (insn, CCZmode)
8081 && !(INTVAL (operands[3]) & ~255))
8082 || (ix86_match_ccmode (insn, CCNOmode)
8083 && !(INTVAL (operands[3]) & ~127)))"
8085 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
8087 "operands[2] = gen_lowpart (QImode, operands[2]);
8088 operands[3] = gen_lowpart (QImode, operands[3]);")
8091 ;; %%% This used to optimize known byte-wide and operations to memory,
8092 ;; and sometimes to QImode registers. If this is considered useful,
8093 ;; it should be done with splitters.
8095 (define_expand "anddi3"
8096 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8097 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8098 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8099 (clobber (reg:CC FLAGS_REG))]
8101 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8103 (define_insn "*anddi_1_rex64"
8104 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8105 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8106 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8107 (clobber (reg:CC FLAGS_REG))]
8108 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8110 switch (get_attr_type (insn))
8114 enum machine_mode mode;
8116 if (GET_CODE (operands[2]) != CONST_INT)
8118 if (INTVAL (operands[2]) == 0xff)
8120 else if (INTVAL (operands[2]) == 0xffff)
8125 operands[1] = gen_lowpart (mode, operands[1]);
8127 return "movz{bq|x}\t{%1,%0|%0, %1}";
8129 return "movz{wq|x}\t{%1,%0|%0, %1}";
8133 if (! rtx_equal_p (operands[0], operands[1]))
8135 if (get_attr_mode (insn) == MODE_SI)
8136 return "and{l}\t{%k2, %k0|%k0, %k2}";
8138 return "and{q}\t{%2, %0|%0, %2}";
8141 [(set_attr "type" "alu,alu,alu,imovx")
8142 (set_attr "length_immediate" "*,*,*,0")
8143 (set_attr "mode" "SI,DI,DI,DI")])
8145 (define_insn "*anddi_2"
8146 [(set (reg FLAGS_REG)
8147 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8148 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8150 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8151 (and:DI (match_dup 1) (match_dup 2)))]
8152 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8153 && ix86_binary_operator_ok (AND, DImode, operands)"
8155 and{l}\t{%k2, %k0|%k0, %k2}
8156 and{q}\t{%2, %0|%0, %2}
8157 and{q}\t{%2, %0|%0, %2}"
8158 [(set_attr "type" "alu")
8159 (set_attr "mode" "SI,DI,DI")])
8161 (define_expand "andsi3"
8162 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8163 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8164 (match_operand:SI 2 "general_operand" "")))
8165 (clobber (reg:CC FLAGS_REG))]
8167 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8169 (define_insn "*andsi_1"
8170 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8171 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8172 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8173 (clobber (reg:CC FLAGS_REG))]
8174 "ix86_binary_operator_ok (AND, SImode, operands)"
8176 switch (get_attr_type (insn))
8180 enum machine_mode mode;
8182 if (GET_CODE (operands[2]) != CONST_INT)
8184 if (INTVAL (operands[2]) == 0xff)
8186 else if (INTVAL (operands[2]) == 0xffff)
8191 operands[1] = gen_lowpart (mode, operands[1]);
8193 return "movz{bl|x}\t{%1,%0|%0, %1}";
8195 return "movz{wl|x}\t{%1,%0|%0, %1}";
8199 if (! rtx_equal_p (operands[0], operands[1]))
8201 return "and{l}\t{%2, %0|%0, %2}";
8204 [(set_attr "type" "alu,alu,imovx")
8205 (set_attr "length_immediate" "*,*,0")
8206 (set_attr "mode" "SI")])
8209 [(set (match_operand 0 "register_operand" "")
8211 (const_int -65536)))
8212 (clobber (reg:CC FLAGS_REG))]
8213 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8214 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8215 "operands[1] = gen_lowpart (HImode, operands[0]);")
8218 [(set (match_operand 0 "ext_register_operand" "")
8221 (clobber (reg:CC FLAGS_REG))]
8222 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8223 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8224 "operands[1] = gen_lowpart (QImode, operands[0]);")
8227 [(set (match_operand 0 "ext_register_operand" "")
8229 (const_int -65281)))
8230 (clobber (reg:CC FLAGS_REG))]
8231 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8232 [(parallel [(set (zero_extract:SI (match_dup 0)
8236 (zero_extract:SI (match_dup 0)
8239 (zero_extract:SI (match_dup 0)
8242 (clobber (reg:CC FLAGS_REG))])]
8243 "operands[0] = gen_lowpart (SImode, operands[0]);")
8245 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8246 (define_insn "*andsi_1_zext"
8247 [(set (match_operand:DI 0 "register_operand" "=r")
8249 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8250 (match_operand:SI 2 "general_operand" "rim"))))
8251 (clobber (reg:CC FLAGS_REG))]
8252 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8253 "and{l}\t{%2, %k0|%k0, %2}"
8254 [(set_attr "type" "alu")
8255 (set_attr "mode" "SI")])
8257 (define_insn "*andsi_2"
8258 [(set (reg FLAGS_REG)
8259 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8260 (match_operand:SI 2 "general_operand" "rim,ri"))
8262 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8263 (and:SI (match_dup 1) (match_dup 2)))]
8264 "ix86_match_ccmode (insn, CCNOmode)
8265 && ix86_binary_operator_ok (AND, SImode, operands)"
8266 "and{l}\t{%2, %0|%0, %2}"
8267 [(set_attr "type" "alu")
8268 (set_attr "mode" "SI")])
8270 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8271 (define_insn "*andsi_2_zext"
8272 [(set (reg FLAGS_REG)
8273 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8274 (match_operand:SI 2 "general_operand" "rim"))
8276 (set (match_operand:DI 0 "register_operand" "=r")
8277 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8278 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8279 && ix86_binary_operator_ok (AND, SImode, operands)"
8280 "and{l}\t{%2, %k0|%k0, %2}"
8281 [(set_attr "type" "alu")
8282 (set_attr "mode" "SI")])
8284 (define_expand "andhi3"
8285 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8286 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8287 (match_operand:HI 2 "general_operand" "")))
8288 (clobber (reg:CC FLAGS_REG))]
8289 "TARGET_HIMODE_MATH"
8290 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8292 (define_insn "*andhi_1"
8293 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8294 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8295 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8296 (clobber (reg:CC FLAGS_REG))]
8297 "ix86_binary_operator_ok (AND, HImode, operands)"
8299 switch (get_attr_type (insn))
8302 if (GET_CODE (operands[2]) != CONST_INT)
8304 if (INTVAL (operands[2]) == 0xff)
8305 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8309 if (! rtx_equal_p (operands[0], operands[1]))
8312 return "and{w}\t{%2, %0|%0, %2}";
8315 [(set_attr "type" "alu,alu,imovx")
8316 (set_attr "length_immediate" "*,*,0")
8317 (set_attr "mode" "HI,HI,SI")])
8319 (define_insn "*andhi_2"
8320 [(set (reg FLAGS_REG)
8321 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8322 (match_operand:HI 2 "general_operand" "rim,ri"))
8324 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8325 (and:HI (match_dup 1) (match_dup 2)))]
8326 "ix86_match_ccmode (insn, CCNOmode)
8327 && ix86_binary_operator_ok (AND, HImode, operands)"
8328 "and{w}\t{%2, %0|%0, %2}"
8329 [(set_attr "type" "alu")
8330 (set_attr "mode" "HI")])
8332 (define_expand "andqi3"
8333 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8334 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8335 (match_operand:QI 2 "general_operand" "")))
8336 (clobber (reg:CC FLAGS_REG))]
8337 "TARGET_QIMODE_MATH"
8338 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8340 ;; %%% Potential partial reg stall on alternative 2. What to do?
8341 (define_insn "*andqi_1"
8342 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8343 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8344 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8345 (clobber (reg:CC FLAGS_REG))]
8346 "ix86_binary_operator_ok (AND, QImode, operands)"
8348 and{b}\t{%2, %0|%0, %2}
8349 and{b}\t{%2, %0|%0, %2}
8350 and{l}\t{%k2, %k0|%k0, %k2}"
8351 [(set_attr "type" "alu")
8352 (set_attr "mode" "QI,QI,SI")])
8354 (define_insn "*andqi_1_slp"
8355 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8356 (and:QI (match_dup 0)
8357 (match_operand:QI 1 "general_operand" "qi,qmi")))
8358 (clobber (reg:CC FLAGS_REG))]
8359 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8360 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8361 "and{b}\t{%1, %0|%0, %1}"
8362 [(set_attr "type" "alu1")
8363 (set_attr "mode" "QI")])
8365 (define_insn "*andqi_2_maybe_si"
8366 [(set (reg FLAGS_REG)
8368 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8369 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8371 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8372 (and:QI (match_dup 1) (match_dup 2)))]
8373 "ix86_binary_operator_ok (AND, QImode, operands)
8374 && ix86_match_ccmode (insn,
8375 GET_CODE (operands[2]) == CONST_INT
8376 && INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)"
8378 if (which_alternative == 2)
8380 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8381 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8382 return "and{l}\t{%2, %k0|%k0, %2}";
8384 return "and{b}\t{%2, %0|%0, %2}";
8386 [(set_attr "type" "alu")
8387 (set_attr "mode" "QI,QI,SI")])
8389 (define_insn "*andqi_2"
8390 [(set (reg FLAGS_REG)
8392 (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8393 (match_operand:QI 2 "general_operand" "qim,qi"))
8395 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8396 (and:QI (match_dup 1) (match_dup 2)))]
8397 "ix86_match_ccmode (insn, CCNOmode)
8398 && ix86_binary_operator_ok (AND, QImode, operands)"
8399 "and{b}\t{%2, %0|%0, %2}"
8400 [(set_attr "type" "alu")
8401 (set_attr "mode" "QI")])
8403 (define_insn "*andqi_2_slp"
8404 [(set (reg FLAGS_REG)
8406 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8407 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8409 (set (strict_low_part (match_dup 0))
8410 (and:QI (match_dup 0) (match_dup 1)))]
8411 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8412 && ix86_match_ccmode (insn, CCNOmode)
8413 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8414 "and{b}\t{%1, %0|%0, %1}"
8415 [(set_attr "type" "alu1")
8416 (set_attr "mode" "QI")])
8418 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8419 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8420 ;; for a QImode operand, which of course failed.
8422 (define_insn "andqi_ext_0"
8423 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8428 (match_operand 1 "ext_register_operand" "0")
8431 (match_operand 2 "const_int_operand" "n")))
8432 (clobber (reg:CC FLAGS_REG))]
8434 "and{b}\t{%2, %h0|%h0, %2}"
8435 [(set_attr "type" "alu")
8436 (set_attr "length_immediate" "1")
8437 (set_attr "mode" "QI")])
8439 ;; Generated by peephole translating test to and. This shows up
8440 ;; often in fp comparisons.
8442 (define_insn "*andqi_ext_0_cc"
8443 [(set (reg FLAGS_REG)
8447 (match_operand 1 "ext_register_operand" "0")
8450 (match_operand 2 "const_int_operand" "n"))
8452 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8461 "ix86_match_ccmode (insn, CCNOmode)"
8462 "and{b}\t{%2, %h0|%h0, %2}"
8463 [(set_attr "type" "alu")
8464 (set_attr "length_immediate" "1")
8465 (set_attr "mode" "QI")])
8467 (define_insn "*andqi_ext_1"
8468 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8473 (match_operand 1 "ext_register_operand" "0")
8477 (match_operand:QI 2 "general_operand" "Qm"))))
8478 (clobber (reg:CC FLAGS_REG))]
8480 "and{b}\t{%2, %h0|%h0, %2}"
8481 [(set_attr "type" "alu")
8482 (set_attr "length_immediate" "0")
8483 (set_attr "mode" "QI")])
8485 (define_insn "*andqi_ext_1_rex64"
8486 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8491 (match_operand 1 "ext_register_operand" "0")
8495 (match_operand 2 "ext_register_operand" "Q"))))
8496 (clobber (reg:CC FLAGS_REG))]
8498 "and{b}\t{%2, %h0|%h0, %2}"
8499 [(set_attr "type" "alu")
8500 (set_attr "length_immediate" "0")
8501 (set_attr "mode" "QI")])
8503 (define_insn "*andqi_ext_2"
8504 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8509 (match_operand 1 "ext_register_operand" "%0")
8513 (match_operand 2 "ext_register_operand" "Q")
8516 (clobber (reg:CC FLAGS_REG))]
8518 "and{b}\t{%h2, %h0|%h0, %h2}"
8519 [(set_attr "type" "alu")
8520 (set_attr "length_immediate" "0")
8521 (set_attr "mode" "QI")])
8523 ;; Convert wide AND instructions with immediate operand to shorter QImode
8524 ;; equivalents when possible.
8525 ;; Don't do the splitting with memory operands, since it introduces risk
8526 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8527 ;; for size, but that can (should?) be handled by generic code instead.
8529 [(set (match_operand 0 "register_operand" "")
8530 (and (match_operand 1 "register_operand" "")
8531 (match_operand 2 "const_int_operand" "")))
8532 (clobber (reg:CC FLAGS_REG))]
8534 && QI_REG_P (operands[0])
8535 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8536 && !(~INTVAL (operands[2]) & ~(255 << 8))
8537 && GET_MODE (operands[0]) != QImode"
8538 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8539 (and:SI (zero_extract:SI (match_dup 1)
8540 (const_int 8) (const_int 8))
8542 (clobber (reg:CC FLAGS_REG))])]
8543 "operands[0] = gen_lowpart (SImode, operands[0]);
8544 operands[1] = gen_lowpart (SImode, operands[1]);
8545 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8547 ;; Since AND can be encoded with sign extended immediate, this is only
8548 ;; profitable when 7th bit is not set.
8550 [(set (match_operand 0 "register_operand" "")
8551 (and (match_operand 1 "general_operand" "")
8552 (match_operand 2 "const_int_operand" "")))
8553 (clobber (reg:CC FLAGS_REG))]
8555 && ANY_QI_REG_P (operands[0])
8556 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8557 && !(~INTVAL (operands[2]) & ~255)
8558 && !(INTVAL (operands[2]) & 128)
8559 && GET_MODE (operands[0]) != QImode"
8560 [(parallel [(set (strict_low_part (match_dup 0))
8561 (and:QI (match_dup 1)
8563 (clobber (reg:CC FLAGS_REG))])]
8564 "operands[0] = gen_lowpart (QImode, operands[0]);
8565 operands[1] = gen_lowpart (QImode, operands[1]);
8566 operands[2] = gen_lowpart (QImode, operands[2]);")
8568 ;; Logical inclusive OR instructions
8570 ;; %%% This used to optimize known byte-wide and operations to memory.
8571 ;; If this is considered useful, it should be done with splitters.
8573 (define_expand "iordi3"
8574 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8575 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8576 (match_operand:DI 2 "x86_64_general_operand" "")))
8577 (clobber (reg:CC FLAGS_REG))]
8579 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8581 (define_insn "*iordi_1_rex64"
8582 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8583 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8584 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8585 (clobber (reg:CC FLAGS_REG))]
8587 && ix86_binary_operator_ok (IOR, DImode, operands)"
8588 "or{q}\t{%2, %0|%0, %2}"
8589 [(set_attr "type" "alu")
8590 (set_attr "mode" "DI")])
8592 (define_insn "*iordi_2_rex64"
8593 [(set (reg FLAGS_REG)
8594 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8595 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8597 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8598 (ior:DI (match_dup 1) (match_dup 2)))]
8600 && ix86_match_ccmode (insn, CCNOmode)
8601 && ix86_binary_operator_ok (IOR, DImode, operands)"
8602 "or{q}\t{%2, %0|%0, %2}"
8603 [(set_attr "type" "alu")
8604 (set_attr "mode" "DI")])
8606 (define_insn "*iordi_3_rex64"
8607 [(set (reg FLAGS_REG)
8608 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8609 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8611 (clobber (match_scratch:DI 0 "=r"))]
8613 && ix86_match_ccmode (insn, CCNOmode)
8614 && ix86_binary_operator_ok (IOR, DImode, operands)"
8615 "or{q}\t{%2, %0|%0, %2}"
8616 [(set_attr "type" "alu")
8617 (set_attr "mode" "DI")])
8620 (define_expand "iorsi3"
8621 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8622 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8623 (match_operand:SI 2 "general_operand" "")))
8624 (clobber (reg:CC FLAGS_REG))]
8626 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8628 (define_insn "*iorsi_1"
8629 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8630 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8631 (match_operand:SI 2 "general_operand" "ri,rmi")))
8632 (clobber (reg:CC FLAGS_REG))]
8633 "ix86_binary_operator_ok (IOR, SImode, operands)"
8634 "or{l}\t{%2, %0|%0, %2}"
8635 [(set_attr "type" "alu")
8636 (set_attr "mode" "SI")])
8638 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8639 (define_insn "*iorsi_1_zext"
8640 [(set (match_operand:DI 0 "register_operand" "=rm")
8642 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8643 (match_operand:SI 2 "general_operand" "rim"))))
8644 (clobber (reg:CC FLAGS_REG))]
8645 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8646 "or{l}\t{%2, %k0|%k0, %2}"
8647 [(set_attr "type" "alu")
8648 (set_attr "mode" "SI")])
8650 (define_insn "*iorsi_1_zext_imm"
8651 [(set (match_operand:DI 0 "register_operand" "=rm")
8652 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8653 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8654 (clobber (reg:CC FLAGS_REG))]
8656 "or{l}\t{%2, %k0|%k0, %2}"
8657 [(set_attr "type" "alu")
8658 (set_attr "mode" "SI")])
8660 (define_insn "*iorsi_2"
8661 [(set (reg FLAGS_REG)
8662 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8663 (match_operand:SI 2 "general_operand" "rim,ri"))
8665 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8666 (ior:SI (match_dup 1) (match_dup 2)))]
8667 "ix86_match_ccmode (insn, CCNOmode)
8668 && ix86_binary_operator_ok (IOR, SImode, operands)"
8669 "or{l}\t{%2, %0|%0, %2}"
8670 [(set_attr "type" "alu")
8671 (set_attr "mode" "SI")])
8673 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8674 ;; ??? Special case for immediate operand is missing - it is tricky.
8675 (define_insn "*iorsi_2_zext"
8676 [(set (reg FLAGS_REG)
8677 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8678 (match_operand:SI 2 "general_operand" "rim"))
8680 (set (match_operand:DI 0 "register_operand" "=r")
8681 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8682 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8683 && ix86_binary_operator_ok (IOR, SImode, operands)"
8684 "or{l}\t{%2, %k0|%k0, %2}"
8685 [(set_attr "type" "alu")
8686 (set_attr "mode" "SI")])
8688 (define_insn "*iorsi_2_zext_imm"
8689 [(set (reg FLAGS_REG)
8690 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8691 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8693 (set (match_operand:DI 0 "register_operand" "=r")
8694 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8695 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8696 && ix86_binary_operator_ok (IOR, SImode, operands)"
8697 "or{l}\t{%2, %k0|%k0, %2}"
8698 [(set_attr "type" "alu")
8699 (set_attr "mode" "SI")])
8701 (define_insn "*iorsi_3"
8702 [(set (reg FLAGS_REG)
8703 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8704 (match_operand:SI 2 "general_operand" "rim"))
8706 (clobber (match_scratch:SI 0 "=r"))]
8707 "ix86_match_ccmode (insn, CCNOmode)
8708 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8709 "or{l}\t{%2, %0|%0, %2}"
8710 [(set_attr "type" "alu")
8711 (set_attr "mode" "SI")])
8713 (define_expand "iorhi3"
8714 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8715 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8716 (match_operand:HI 2 "general_operand" "")))
8717 (clobber (reg:CC FLAGS_REG))]
8718 "TARGET_HIMODE_MATH"
8719 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8721 (define_insn "*iorhi_1"
8722 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8723 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8724 (match_operand:HI 2 "general_operand" "rmi,ri")))
8725 (clobber (reg:CC FLAGS_REG))]
8726 "ix86_binary_operator_ok (IOR, HImode, operands)"
8727 "or{w}\t{%2, %0|%0, %2}"
8728 [(set_attr "type" "alu")
8729 (set_attr "mode" "HI")])
8731 (define_insn "*iorhi_2"
8732 [(set (reg FLAGS_REG)
8733 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8734 (match_operand:HI 2 "general_operand" "rim,ri"))
8736 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8737 (ior:HI (match_dup 1) (match_dup 2)))]
8738 "ix86_match_ccmode (insn, CCNOmode)
8739 && ix86_binary_operator_ok (IOR, HImode, operands)"
8740 "or{w}\t{%2, %0|%0, %2}"
8741 [(set_attr "type" "alu")
8742 (set_attr "mode" "HI")])
8744 (define_insn "*iorhi_3"
8745 [(set (reg FLAGS_REG)
8746 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8747 (match_operand:HI 2 "general_operand" "rim"))
8749 (clobber (match_scratch:HI 0 "=r"))]
8750 "ix86_match_ccmode (insn, CCNOmode)
8751 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8752 "or{w}\t{%2, %0|%0, %2}"
8753 [(set_attr "type" "alu")
8754 (set_attr "mode" "HI")])
8756 (define_expand "iorqi3"
8757 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8758 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8759 (match_operand:QI 2 "general_operand" "")))
8760 (clobber (reg:CC FLAGS_REG))]
8761 "TARGET_QIMODE_MATH"
8762 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8764 ;; %%% Potential partial reg stall on alternative 2. What to do?
8765 (define_insn "*iorqi_1"
8766 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8767 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8768 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8769 (clobber (reg:CC FLAGS_REG))]
8770 "ix86_binary_operator_ok (IOR, QImode, operands)"
8772 or{b}\t{%2, %0|%0, %2}
8773 or{b}\t{%2, %0|%0, %2}
8774 or{l}\t{%k2, %k0|%k0, %k2}"
8775 [(set_attr "type" "alu")
8776 (set_attr "mode" "QI,QI,SI")])
8778 (define_insn "*iorqi_1_slp"
8779 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8780 (ior:QI (match_dup 0)
8781 (match_operand:QI 1 "general_operand" "qmi,qi")))
8782 (clobber (reg:CC FLAGS_REG))]
8783 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8784 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8785 "or{b}\t{%1, %0|%0, %1}"
8786 [(set_attr "type" "alu1")
8787 (set_attr "mode" "QI")])
8789 (define_insn "*iorqi_2"
8790 [(set (reg FLAGS_REG)
8791 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8792 (match_operand:QI 2 "general_operand" "qim,qi"))
8794 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8795 (ior:QI (match_dup 1) (match_dup 2)))]
8796 "ix86_match_ccmode (insn, CCNOmode)
8797 && ix86_binary_operator_ok (IOR, QImode, operands)"
8798 "or{b}\t{%2, %0|%0, %2}"
8799 [(set_attr "type" "alu")
8800 (set_attr "mode" "QI")])
8802 (define_insn "*iorqi_2_slp"
8803 [(set (reg FLAGS_REG)
8804 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8805 (match_operand:QI 1 "general_operand" "qim,qi"))
8807 (set (strict_low_part (match_dup 0))
8808 (ior:QI (match_dup 0) (match_dup 1)))]
8809 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8810 && ix86_match_ccmode (insn, CCNOmode)
8811 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8812 "or{b}\t{%1, %0|%0, %1}"
8813 [(set_attr "type" "alu1")
8814 (set_attr "mode" "QI")])
8816 (define_insn "*iorqi_3"
8817 [(set (reg FLAGS_REG)
8818 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8819 (match_operand:QI 2 "general_operand" "qim"))
8821 (clobber (match_scratch:QI 0 "=q"))]
8822 "ix86_match_ccmode (insn, CCNOmode)
8823 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8824 "or{b}\t{%2, %0|%0, %2}"
8825 [(set_attr "type" "alu")
8826 (set_attr "mode" "QI")])
8828 (define_insn "iorqi_ext_0"
8829 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8834 (match_operand 1 "ext_register_operand" "0")
8837 (match_operand 2 "const_int_operand" "n")))
8838 (clobber (reg:CC FLAGS_REG))]
8839 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8840 "or{b}\t{%2, %h0|%h0, %2}"
8841 [(set_attr "type" "alu")
8842 (set_attr "length_immediate" "1")
8843 (set_attr "mode" "QI")])
8845 (define_insn "*iorqi_ext_1"
8846 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8851 (match_operand 1 "ext_register_operand" "0")
8855 (match_operand:QI 2 "general_operand" "Qm"))))
8856 (clobber (reg:CC FLAGS_REG))]
8858 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8859 "or{b}\t{%2, %h0|%h0, %2}"
8860 [(set_attr "type" "alu")
8861 (set_attr "length_immediate" "0")
8862 (set_attr "mode" "QI")])
8864 (define_insn "*iorqi_ext_1_rex64"
8865 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8870 (match_operand 1 "ext_register_operand" "0")
8874 (match_operand 2 "ext_register_operand" "Q"))))
8875 (clobber (reg:CC FLAGS_REG))]
8877 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8878 "or{b}\t{%2, %h0|%h0, %2}"
8879 [(set_attr "type" "alu")
8880 (set_attr "length_immediate" "0")
8881 (set_attr "mode" "QI")])
8883 (define_insn "*iorqi_ext_2"
8884 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8888 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8891 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8894 (clobber (reg:CC FLAGS_REG))]
8895 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8896 "ior{b}\t{%h2, %h0|%h0, %h2}"
8897 [(set_attr "type" "alu")
8898 (set_attr "length_immediate" "0")
8899 (set_attr "mode" "QI")])
8902 [(set (match_operand 0 "register_operand" "")
8903 (ior (match_operand 1 "register_operand" "")
8904 (match_operand 2 "const_int_operand" "")))
8905 (clobber (reg:CC FLAGS_REG))]
8907 && QI_REG_P (operands[0])
8908 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8909 && !(INTVAL (operands[2]) & ~(255 << 8))
8910 && GET_MODE (operands[0]) != QImode"
8911 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8912 (ior:SI (zero_extract:SI (match_dup 1)
8913 (const_int 8) (const_int 8))
8915 (clobber (reg:CC FLAGS_REG))])]
8916 "operands[0] = gen_lowpart (SImode, operands[0]);
8917 operands[1] = gen_lowpart (SImode, operands[1]);
8918 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8920 ;; Since OR can be encoded with sign extended immediate, this is only
8921 ;; profitable when 7th bit is set.
8923 [(set (match_operand 0 "register_operand" "")
8924 (ior (match_operand 1 "general_operand" "")
8925 (match_operand 2 "const_int_operand" "")))
8926 (clobber (reg:CC FLAGS_REG))]
8928 && ANY_QI_REG_P (operands[0])
8929 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8930 && !(INTVAL (operands[2]) & ~255)
8931 && (INTVAL (operands[2]) & 128)
8932 && GET_MODE (operands[0]) != QImode"
8933 [(parallel [(set (strict_low_part (match_dup 0))
8934 (ior:QI (match_dup 1)
8936 (clobber (reg:CC FLAGS_REG))])]
8937 "operands[0] = gen_lowpart (QImode, operands[0]);
8938 operands[1] = gen_lowpart (QImode, operands[1]);
8939 operands[2] = gen_lowpart (QImode, operands[2]);")
8941 ;; Logical XOR instructions
8943 ;; %%% This used to optimize known byte-wide and operations to memory.
8944 ;; If this is considered useful, it should be done with splitters.
8946 (define_expand "xordi3"
8947 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8948 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8949 (match_operand:DI 2 "x86_64_general_operand" "")))
8950 (clobber (reg:CC FLAGS_REG))]
8952 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8954 (define_insn "*xordi_1_rex64"
8955 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8956 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8957 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8958 (clobber (reg:CC FLAGS_REG))]
8960 && ix86_binary_operator_ok (XOR, DImode, operands)"
8962 xor{q}\t{%2, %0|%0, %2}
8963 xor{q}\t{%2, %0|%0, %2}"
8964 [(set_attr "type" "alu")
8965 (set_attr "mode" "DI,DI")])
8967 (define_insn "*xordi_2_rex64"
8968 [(set (reg FLAGS_REG)
8969 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8970 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8972 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8973 (xor:DI (match_dup 1) (match_dup 2)))]
8975 && ix86_match_ccmode (insn, CCNOmode)
8976 && ix86_binary_operator_ok (XOR, DImode, operands)"
8978 xor{q}\t{%2, %0|%0, %2}
8979 xor{q}\t{%2, %0|%0, %2}"
8980 [(set_attr "type" "alu")
8981 (set_attr "mode" "DI,DI")])
8983 (define_insn "*xordi_3_rex64"
8984 [(set (reg FLAGS_REG)
8985 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8986 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8988 (clobber (match_scratch:DI 0 "=r"))]
8990 && ix86_match_ccmode (insn, CCNOmode)
8991 && ix86_binary_operator_ok (XOR, DImode, operands)"
8992 "xor{q}\t{%2, %0|%0, %2}"
8993 [(set_attr "type" "alu")
8994 (set_attr "mode" "DI")])
8996 (define_expand "xorsi3"
8997 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8998 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8999 (match_operand:SI 2 "general_operand" "")))
9000 (clobber (reg:CC FLAGS_REG))]
9002 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9004 (define_insn "*xorsi_1"
9005 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9006 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9007 (match_operand:SI 2 "general_operand" "ri,rm")))
9008 (clobber (reg:CC FLAGS_REG))]
9009 "ix86_binary_operator_ok (XOR, SImode, operands)"
9010 "xor{l}\t{%2, %0|%0, %2}"
9011 [(set_attr "type" "alu")
9012 (set_attr "mode" "SI")])
9014 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9015 ;; Add speccase for immediates
9016 (define_insn "*xorsi_1_zext"
9017 [(set (match_operand:DI 0 "register_operand" "=r")
9019 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9020 (match_operand:SI 2 "general_operand" "rim"))))
9021 (clobber (reg:CC FLAGS_REG))]
9022 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9023 "xor{l}\t{%2, %k0|%k0, %2}"
9024 [(set_attr "type" "alu")
9025 (set_attr "mode" "SI")])
9027 (define_insn "*xorsi_1_zext_imm"
9028 [(set (match_operand:DI 0 "register_operand" "=r")
9029 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9030 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9031 (clobber (reg:CC FLAGS_REG))]
9032 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9033 "xor{l}\t{%2, %k0|%k0, %2}"
9034 [(set_attr "type" "alu")
9035 (set_attr "mode" "SI")])
9037 (define_insn "*xorsi_2"
9038 [(set (reg FLAGS_REG)
9039 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9040 (match_operand:SI 2 "general_operand" "rim,ri"))
9042 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9043 (xor:SI (match_dup 1) (match_dup 2)))]
9044 "ix86_match_ccmode (insn, CCNOmode)
9045 && ix86_binary_operator_ok (XOR, SImode, operands)"
9046 "xor{l}\t{%2, %0|%0, %2}"
9047 [(set_attr "type" "alu")
9048 (set_attr "mode" "SI")])
9050 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9051 ;; ??? Special case for immediate operand is missing - it is tricky.
9052 (define_insn "*xorsi_2_zext"
9053 [(set (reg FLAGS_REG)
9054 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9055 (match_operand:SI 2 "general_operand" "rim"))
9057 (set (match_operand:DI 0 "register_operand" "=r")
9058 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9059 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9060 && ix86_binary_operator_ok (XOR, SImode, operands)"
9061 "xor{l}\t{%2, %k0|%k0, %2}"
9062 [(set_attr "type" "alu")
9063 (set_attr "mode" "SI")])
9065 (define_insn "*xorsi_2_zext_imm"
9066 [(set (reg FLAGS_REG)
9067 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9068 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9070 (set (match_operand:DI 0 "register_operand" "=r")
9071 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9072 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9073 && ix86_binary_operator_ok (XOR, SImode, operands)"
9074 "xor{l}\t{%2, %k0|%k0, %2}"
9075 [(set_attr "type" "alu")
9076 (set_attr "mode" "SI")])
9078 (define_insn "*xorsi_3"
9079 [(set (reg FLAGS_REG)
9080 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9081 (match_operand:SI 2 "general_operand" "rim"))
9083 (clobber (match_scratch:SI 0 "=r"))]
9084 "ix86_match_ccmode (insn, CCNOmode)
9085 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9086 "xor{l}\t{%2, %0|%0, %2}"
9087 [(set_attr "type" "alu")
9088 (set_attr "mode" "SI")])
9090 (define_expand "xorhi3"
9091 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9092 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9093 (match_operand:HI 2 "general_operand" "")))
9094 (clobber (reg:CC FLAGS_REG))]
9095 "TARGET_HIMODE_MATH"
9096 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9098 (define_insn "*xorhi_1"
9099 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9100 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9101 (match_operand:HI 2 "general_operand" "rmi,ri")))
9102 (clobber (reg:CC FLAGS_REG))]
9103 "ix86_binary_operator_ok (XOR, HImode, operands)"
9104 "xor{w}\t{%2, %0|%0, %2}"
9105 [(set_attr "type" "alu")
9106 (set_attr "mode" "HI")])
9108 (define_insn "*xorhi_2"
9109 [(set (reg FLAGS_REG)
9110 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9111 (match_operand:HI 2 "general_operand" "rim,ri"))
9113 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9114 (xor:HI (match_dup 1) (match_dup 2)))]
9115 "ix86_match_ccmode (insn, CCNOmode)
9116 && ix86_binary_operator_ok (XOR, HImode, operands)"
9117 "xor{w}\t{%2, %0|%0, %2}"
9118 [(set_attr "type" "alu")
9119 (set_attr "mode" "HI")])
9121 (define_insn "*xorhi_3"
9122 [(set (reg FLAGS_REG)
9123 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9124 (match_operand:HI 2 "general_operand" "rim"))
9126 (clobber (match_scratch:HI 0 "=r"))]
9127 "ix86_match_ccmode (insn, CCNOmode)
9128 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9129 "xor{w}\t{%2, %0|%0, %2}"
9130 [(set_attr "type" "alu")
9131 (set_attr "mode" "HI")])
9133 (define_expand "xorqi3"
9134 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9135 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9136 (match_operand:QI 2 "general_operand" "")))
9137 (clobber (reg:CC FLAGS_REG))]
9138 "TARGET_QIMODE_MATH"
9139 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9141 ;; %%% Potential partial reg stall on alternative 2. What to do?
9142 (define_insn "*xorqi_1"
9143 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9144 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9145 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9146 (clobber (reg:CC FLAGS_REG))]
9147 "ix86_binary_operator_ok (XOR, QImode, operands)"
9149 xor{b}\t{%2, %0|%0, %2}
9150 xor{b}\t{%2, %0|%0, %2}
9151 xor{l}\t{%k2, %k0|%k0, %k2}"
9152 [(set_attr "type" "alu")
9153 (set_attr "mode" "QI,QI,SI")])
9155 (define_insn "*xorqi_1_slp"
9156 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9157 (xor:QI (match_dup 0)
9158 (match_operand:QI 1 "general_operand" "qi,qmi")))
9159 (clobber (reg:CC FLAGS_REG))]
9160 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9161 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9162 "xor{b}\t{%1, %0|%0, %1}"
9163 [(set_attr "type" "alu1")
9164 (set_attr "mode" "QI")])
9166 (define_insn "xorqi_ext_0"
9167 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9172 (match_operand 1 "ext_register_operand" "0")
9175 (match_operand 2 "const_int_operand" "n")))
9176 (clobber (reg:CC FLAGS_REG))]
9177 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9178 "xor{b}\t{%2, %h0|%h0, %2}"
9179 [(set_attr "type" "alu")
9180 (set_attr "length_immediate" "1")
9181 (set_attr "mode" "QI")])
9183 (define_insn "*xorqi_ext_1"
9184 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9189 (match_operand 1 "ext_register_operand" "0")
9193 (match_operand:QI 2 "general_operand" "Qm"))))
9194 (clobber (reg:CC FLAGS_REG))]
9196 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9197 "xor{b}\t{%2, %h0|%h0, %2}"
9198 [(set_attr "type" "alu")
9199 (set_attr "length_immediate" "0")
9200 (set_attr "mode" "QI")])
9202 (define_insn "*xorqi_ext_1_rex64"
9203 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9208 (match_operand 1 "ext_register_operand" "0")
9212 (match_operand 2 "ext_register_operand" "Q"))))
9213 (clobber (reg:CC FLAGS_REG))]
9215 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9216 "xor{b}\t{%2, %h0|%h0, %2}"
9217 [(set_attr "type" "alu")
9218 (set_attr "length_immediate" "0")
9219 (set_attr "mode" "QI")])
9221 (define_insn "*xorqi_ext_2"
9222 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9226 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9229 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9232 (clobber (reg:CC FLAGS_REG))]
9233 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9234 "xor{b}\t{%h2, %h0|%h0, %h2}"
9235 [(set_attr "type" "alu")
9236 (set_attr "length_immediate" "0")
9237 (set_attr "mode" "QI")])
9239 (define_insn "*xorqi_cc_1"
9240 [(set (reg FLAGS_REG)
9242 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9243 (match_operand:QI 2 "general_operand" "qim,qi"))
9245 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9246 (xor:QI (match_dup 1) (match_dup 2)))]
9247 "ix86_match_ccmode (insn, CCNOmode)
9248 && ix86_binary_operator_ok (XOR, QImode, operands)"
9249 "xor{b}\t{%2, %0|%0, %2}"
9250 [(set_attr "type" "alu")
9251 (set_attr "mode" "QI")])
9253 (define_insn "*xorqi_2_slp"
9254 [(set (reg FLAGS_REG)
9255 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9256 (match_operand:QI 1 "general_operand" "qim,qi"))
9258 (set (strict_low_part (match_dup 0))
9259 (xor:QI (match_dup 0) (match_dup 1)))]
9260 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9261 && ix86_match_ccmode (insn, CCNOmode)
9262 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9263 "xor{b}\t{%1, %0|%0, %1}"
9264 [(set_attr "type" "alu1")
9265 (set_attr "mode" "QI")])
9267 (define_insn "*xorqi_cc_2"
9268 [(set (reg FLAGS_REG)
9270 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9271 (match_operand:QI 2 "general_operand" "qim"))
9273 (clobber (match_scratch:QI 0 "=q"))]
9274 "ix86_match_ccmode (insn, CCNOmode)
9275 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9276 "xor{b}\t{%2, %0|%0, %2}"
9277 [(set_attr "type" "alu")
9278 (set_attr "mode" "QI")])
9280 (define_insn "*xorqi_cc_ext_1"
9281 [(set (reg FLAGS_REG)
9285 (match_operand 1 "ext_register_operand" "0")
9288 (match_operand:QI 2 "general_operand" "qmn"))
9290 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9294 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9296 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9297 "xor{b}\t{%2, %h0|%h0, %2}"
9298 [(set_attr "type" "alu")
9299 (set_attr "mode" "QI")])
9301 (define_insn "*xorqi_cc_ext_1_rex64"
9302 [(set (reg FLAGS_REG)
9306 (match_operand 1 "ext_register_operand" "0")
9309 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9311 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9315 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9317 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9318 "xor{b}\t{%2, %h0|%h0, %2}"
9319 [(set_attr "type" "alu")
9320 (set_attr "mode" "QI")])
9322 (define_expand "xorqi_cc_ext_1"
9324 (set (reg:CCNO FLAGS_REG)
9328 (match_operand 1 "ext_register_operand" "")
9331 (match_operand:QI 2 "general_operand" ""))
9333 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9337 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9343 [(set (match_operand 0 "register_operand" "")
9344 (xor (match_operand 1 "register_operand" "")
9345 (match_operand 2 "const_int_operand" "")))
9346 (clobber (reg:CC FLAGS_REG))]
9348 && QI_REG_P (operands[0])
9349 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9350 && !(INTVAL (operands[2]) & ~(255 << 8))
9351 && GET_MODE (operands[0]) != QImode"
9352 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9353 (xor:SI (zero_extract:SI (match_dup 1)
9354 (const_int 8) (const_int 8))
9356 (clobber (reg:CC FLAGS_REG))])]
9357 "operands[0] = gen_lowpart (SImode, operands[0]);
9358 operands[1] = gen_lowpart (SImode, operands[1]);
9359 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9361 ;; Since XOR can be encoded with sign extended immediate, this is only
9362 ;; profitable when 7th bit is set.
9364 [(set (match_operand 0 "register_operand" "")
9365 (xor (match_operand 1 "general_operand" "")
9366 (match_operand 2 "const_int_operand" "")))
9367 (clobber (reg:CC FLAGS_REG))]
9369 && ANY_QI_REG_P (operands[0])
9370 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9371 && !(INTVAL (operands[2]) & ~255)
9372 && (INTVAL (operands[2]) & 128)
9373 && GET_MODE (operands[0]) != QImode"
9374 [(parallel [(set (strict_low_part (match_dup 0))
9375 (xor:QI (match_dup 1)
9377 (clobber (reg:CC FLAGS_REG))])]
9378 "operands[0] = gen_lowpart (QImode, operands[0]);
9379 operands[1] = gen_lowpart (QImode, operands[1]);
9380 operands[2] = gen_lowpart (QImode, operands[2]);")
9382 ;; Negation instructions
9384 (define_expand "negdi2"
9385 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9386 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9387 (clobber (reg:CC FLAGS_REG))])]
9389 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9391 (define_insn "*negdi2_1"
9392 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9393 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9394 (clobber (reg:CC FLAGS_REG))]
9396 && ix86_unary_operator_ok (NEG, DImode, operands)"
9400 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9401 (neg:DI (match_operand:DI 1 "general_operand" "")))
9402 (clobber (reg:CC FLAGS_REG))]
9403 "!TARGET_64BIT && reload_completed"
9405 [(set (reg:CCZ FLAGS_REG)
9406 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9407 (set (match_dup 0) (neg:SI (match_dup 2)))])
9410 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
9413 (clobber (reg:CC FLAGS_REG))])
9416 (neg:SI (match_dup 1)))
9417 (clobber (reg:CC FLAGS_REG))])]
9418 "split_di (operands+1, 1, operands+2, operands+3);
9419 split_di (operands+0, 1, operands+0, operands+1);")
9421 (define_insn "*negdi2_1_rex64"
9422 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9423 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9424 (clobber (reg:CC FLAGS_REG))]
9425 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9427 [(set_attr "type" "negnot")
9428 (set_attr "mode" "DI")])
9430 ;; The problem with neg is that it does not perform (compare x 0),
9431 ;; it really performs (compare 0 x), which leaves us with the zero
9432 ;; flag being the only useful item.
9434 (define_insn "*negdi2_cmpz_rex64"
9435 [(set (reg:CCZ FLAGS_REG)
9436 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9438 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9439 (neg:DI (match_dup 1)))]
9440 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9442 [(set_attr "type" "negnot")
9443 (set_attr "mode" "DI")])
9446 (define_expand "negsi2"
9447 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9448 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9449 (clobber (reg:CC FLAGS_REG))])]
9451 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9453 (define_insn "*negsi2_1"
9454 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9455 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9456 (clobber (reg:CC FLAGS_REG))]
9457 "ix86_unary_operator_ok (NEG, SImode, operands)"
9459 [(set_attr "type" "negnot")
9460 (set_attr "mode" "SI")])
9462 ;; Combine is quite creative about this pattern.
9463 (define_insn "*negsi2_1_zext"
9464 [(set (match_operand:DI 0 "register_operand" "=r")
9465 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9468 (clobber (reg:CC FLAGS_REG))]
9469 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9471 [(set_attr "type" "negnot")
9472 (set_attr "mode" "SI")])
9474 ;; The problem with neg is that it does not perform (compare x 0),
9475 ;; it really performs (compare 0 x), which leaves us with the zero
9476 ;; flag being the only useful item.
9478 (define_insn "*negsi2_cmpz"
9479 [(set (reg:CCZ FLAGS_REG)
9480 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9482 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9483 (neg:SI (match_dup 1)))]
9484 "ix86_unary_operator_ok (NEG, SImode, operands)"
9486 [(set_attr "type" "negnot")
9487 (set_attr "mode" "SI")])
9489 (define_insn "*negsi2_cmpz_zext"
9490 [(set (reg:CCZ FLAGS_REG)
9491 (compare:CCZ (lshiftrt:DI
9493 (match_operand:DI 1 "register_operand" "0")
9497 (set (match_operand:DI 0 "register_operand" "=r")
9498 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9501 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9503 [(set_attr "type" "negnot")
9504 (set_attr "mode" "SI")])
9506 (define_expand "neghi2"
9507 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9508 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9509 (clobber (reg:CC FLAGS_REG))])]
9510 "TARGET_HIMODE_MATH"
9511 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9513 (define_insn "*neghi2_1"
9514 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9515 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9516 (clobber (reg:CC FLAGS_REG))]
9517 "ix86_unary_operator_ok (NEG, HImode, operands)"
9519 [(set_attr "type" "negnot")
9520 (set_attr "mode" "HI")])
9522 (define_insn "*neghi2_cmpz"
9523 [(set (reg:CCZ FLAGS_REG)
9524 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9526 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9527 (neg:HI (match_dup 1)))]
9528 "ix86_unary_operator_ok (NEG, HImode, operands)"
9530 [(set_attr "type" "negnot")
9531 (set_attr "mode" "HI")])
9533 (define_expand "negqi2"
9534 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9535 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9536 (clobber (reg:CC FLAGS_REG))])]
9537 "TARGET_QIMODE_MATH"
9538 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9540 (define_insn "*negqi2_1"
9541 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9542 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9543 (clobber (reg:CC FLAGS_REG))]
9544 "ix86_unary_operator_ok (NEG, QImode, operands)"
9546 [(set_attr "type" "negnot")
9547 (set_attr "mode" "QI")])
9549 (define_insn "*negqi2_cmpz"
9550 [(set (reg:CCZ FLAGS_REG)
9551 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9553 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9554 (neg:QI (match_dup 1)))]
9555 "ix86_unary_operator_ok (NEG, QImode, operands)"
9557 [(set_attr "type" "negnot")
9558 (set_attr "mode" "QI")])
9560 ;; Changing of sign for FP values is doable using integer unit too.
9562 (define_expand "negsf2"
9563 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9564 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
9565 "TARGET_80387 || TARGET_SSE_MATH"
9566 "ix86_expand_fp_absneg_operator (NEG, SFmode, operands); DONE;")
9568 (define_expand "abssf2"
9569 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9570 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
9571 "TARGET_80387 || TARGET_SSE_MATH"
9572 "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
9574 (define_insn "*absnegsf2_mixed"
9575 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9576 (match_operator:SF 3 "absneg_operator"
9577 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#fr,0 ,0")]))
9578 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X ,X"))
9579 (clobber (reg:CC FLAGS_REG))]
9580 "TARGET_SSE_MATH && TARGET_MIX_SSE_I387
9581 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9584 (define_insn "*absnegsf2_sse"
9585 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#r,x#r,rm#x")
9586 (match_operator:SF 3 "absneg_operator"
9587 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#r,0")]))
9588 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X"))
9589 (clobber (reg:CC FLAGS_REG))]
9591 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9594 (define_insn "*absnegsf2_i387"
9595 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9596 (match_operator:SF 3 "absneg_operator"
9597 [(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
9598 (use (match_operand 2 "" ""))
9599 (clobber (reg:CC FLAGS_REG))]
9600 "TARGET_80387 && !TARGET_SSE_MATH
9601 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9604 (define_expand "negdf2"
9605 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9606 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
9607 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9608 "ix86_expand_fp_absneg_operator (NEG, DFmode, operands); DONE;")
9610 (define_expand "absdf2"
9611 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9612 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
9613 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9614 "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
9616 (define_insn "*absnegdf2_mixed"
9617 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9618 (match_operator:DF 3 "absneg_operator"
9619 [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#fr,0 ,0")]))
9620 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X ,X"))
9621 (clobber (reg:CC FLAGS_REG))]
9622 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
9623 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9626 (define_insn "*absnegdf2_sse"
9627 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#r,Y#r,rm#Y")
9628 (match_operator:DF 3 "absneg_operator"
9629 [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#r,0")]))
9630 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X"))
9631 (clobber (reg:CC FLAGS_REG))]
9632 "TARGET_SSE2 && TARGET_SSE_MATH
9633 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9636 (define_insn "*absnegdf2_i387"
9637 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9638 (match_operator:DF 3 "absneg_operator"
9639 [(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
9640 (use (match_operand 2 "" ""))
9641 (clobber (reg:CC FLAGS_REG))]
9642 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
9643 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9646 (define_expand "negxf2"
9647 [(set (match_operand:XF 0 "nonimmediate_operand" "")
9648 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
9650 "ix86_expand_fp_absneg_operator (NEG, XFmode, operands); DONE;")
9652 (define_expand "absxf2"
9653 [(set (match_operand:XF 0 "nonimmediate_operand" "")
9654 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
9656 "ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
9658 (define_insn "*absnegxf2_i387"
9659 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9660 (match_operator:XF 3 "absneg_operator"
9661 [(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
9662 (use (match_operand 2 "" ""))
9663 (clobber (reg:CC FLAGS_REG))]
9665 && ix86_unary_operator_ok (GET_CODE (operands[3]), XFmode, operands)"
9668 ;; Splitters for fp abs and neg.
9671 [(set (match_operand 0 "fp_register_operand" "")
9672 (match_operator 1 "absneg_operator" [(match_dup 0)]))
9673 (use (match_operand 2 "" ""))
9674 (clobber (reg:CC FLAGS_REG))]
9676 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
9679 [(set (match_operand 0 "register_operand" "")
9680 (match_operator 3 "absneg_operator"
9681 [(match_operand 1 "register_operand" "")]))
9682 (use (match_operand 2 "nonimmediate_operand" ""))
9683 (clobber (reg:CC FLAGS_REG))]
9684 "reload_completed && SSE_REG_P (operands[0])"
9685 [(set (match_dup 0) (match_dup 3))]
9687 enum machine_mode mode = GET_MODE (operands[0]);
9688 enum machine_mode vmode = GET_MODE (operands[2]);
9691 operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
9692 operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
9693 if (operands_match_p (operands[0], operands[2]))
9696 operands[1] = operands[2];
9699 if (GET_CODE (operands[3]) == ABS)
9700 tmp = gen_rtx_AND (vmode, operands[1], operands[2]);
9702 tmp = gen_rtx_XOR (vmode, operands[1], operands[2]);
9707 [(set (match_operand:SF 0 "register_operand" "")
9708 (match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
9709 (use (match_operand:V4SF 2 "" ""))
9710 (clobber (reg:CC FLAGS_REG))]
9712 [(parallel [(set (match_dup 0) (match_dup 1))
9713 (clobber (reg:CC FLAGS_REG))])]
9716 operands[0] = gen_lowpart (SImode, operands[0]);
9717 if (GET_CODE (operands[1]) == ABS)
9719 tmp = gen_int_mode (0x7fffffff, SImode);
9720 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9724 tmp = gen_int_mode (0x80000000, SImode);
9725 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9731 [(set (match_operand:DF 0 "register_operand" "")
9732 (match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
9733 (use (match_operand 2 "" ""))
9734 (clobber (reg:CC FLAGS_REG))]
9736 [(parallel [(set (match_dup 0) (match_dup 1))
9737 (clobber (reg:CC FLAGS_REG))])]
9742 tmp = gen_lowpart (DImode, operands[0]);
9743 tmp = gen_rtx_ZERO_EXTRACT (DImode, tmp, const1_rtx, GEN_INT (63));
9746 if (GET_CODE (operands[1]) == ABS)
9749 tmp = gen_rtx_NOT (DImode, tmp);
9753 operands[0] = gen_highpart (SImode, operands[0]);
9754 if (GET_CODE (operands[1]) == ABS)
9756 tmp = gen_int_mode (0x7fffffff, SImode);
9757 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9761 tmp = gen_int_mode (0x80000000, SImode);
9762 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9769 [(set (match_operand:XF 0 "register_operand" "")
9770 (match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
9771 (use (match_operand 2 "" ""))
9772 (clobber (reg:CC FLAGS_REG))]
9774 [(parallel [(set (match_dup 0) (match_dup 1))
9775 (clobber (reg:CC FLAGS_REG))])]
9778 operands[0] = gen_rtx_REG (SImode,
9779 true_regnum (operands[0])
9780 + (TARGET_64BIT ? 1 : 2));
9781 if (GET_CODE (operands[1]) == ABS)
9783 tmp = GEN_INT (0x7fff);
9784 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9788 tmp = GEN_INT (0x8000);
9789 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9795 [(set (match_operand 0 "memory_operand" "")
9796 (match_operator 1 "absneg_operator" [(match_dup 0)]))
9797 (use (match_operand 2 "" ""))
9798 (clobber (reg:CC FLAGS_REG))]
9800 [(parallel [(set (match_dup 0) (match_dup 1))
9801 (clobber (reg:CC FLAGS_REG))])]
9803 enum machine_mode mode = GET_MODE (operands[0]);
9804 int size = mode == XFmode ? 10 : GET_MODE_SIZE (mode);
9807 operands[0] = adjust_address (operands[0], QImode, size - 1);
9808 if (GET_CODE (operands[1]) == ABS)
9810 tmp = gen_int_mode (0x7f, QImode);
9811 tmp = gen_rtx_AND (QImode, operands[0], tmp);
9815 tmp = gen_int_mode (0x80, QImode);
9816 tmp = gen_rtx_XOR (QImode, operands[0], tmp);
9821 ;; Conditionalize these after reload. If they match before reload, we
9822 ;; lose the clobber and ability to use integer instructions.
9824 (define_insn "*negsf2_1"
9825 [(set (match_operand:SF 0 "register_operand" "=f")
9826 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9827 "TARGET_80387 && reload_completed"
9829 [(set_attr "type" "fsgn")
9830 (set_attr "mode" "SF")])
9832 (define_insn "*negdf2_1"
9833 [(set (match_operand:DF 0 "register_operand" "=f")
9834 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9835 "TARGET_80387 && reload_completed"
9837 [(set_attr "type" "fsgn")
9838 (set_attr "mode" "DF")])
9840 (define_insn "*negxf2_1"
9841 [(set (match_operand:XF 0 "register_operand" "=f")
9842 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9843 "TARGET_80387 && reload_completed"
9845 [(set_attr "type" "fsgn")
9846 (set_attr "mode" "XF")])
9848 (define_insn "*abssf2_1"
9849 [(set (match_operand:SF 0 "register_operand" "=f")
9850 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
9851 "TARGET_80387 && reload_completed"
9853 [(set_attr "type" "fsgn")
9854 (set_attr "mode" "SF")])
9856 (define_insn "*absdf2_1"
9857 [(set (match_operand:DF 0 "register_operand" "=f")
9858 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
9859 "TARGET_80387 && reload_completed"
9861 [(set_attr "type" "fsgn")
9862 (set_attr "mode" "DF")])
9864 (define_insn "*absxf2_1"
9865 [(set (match_operand:XF 0 "register_operand" "=f")
9866 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
9867 "TARGET_80387 && reload_completed"
9869 [(set_attr "type" "fsgn")
9870 (set_attr "mode" "DF")])
9872 (define_insn "*negextendsfdf2"
9873 [(set (match_operand:DF 0 "register_operand" "=f")
9874 (neg:DF (float_extend:DF
9875 (match_operand:SF 1 "register_operand" "0"))))]
9876 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9878 [(set_attr "type" "fsgn")
9879 (set_attr "mode" "DF")])
9881 (define_insn "*negextenddfxf2"
9882 [(set (match_operand:XF 0 "register_operand" "=f")
9883 (neg:XF (float_extend:XF
9884 (match_operand:DF 1 "register_operand" "0"))))]
9887 [(set_attr "type" "fsgn")
9888 (set_attr "mode" "XF")])
9890 (define_insn "*negextendsfxf2"
9891 [(set (match_operand:XF 0 "register_operand" "=f")
9892 (neg:XF (float_extend:XF
9893 (match_operand:SF 1 "register_operand" "0"))))]
9896 [(set_attr "type" "fsgn")
9897 (set_attr "mode" "XF")])
9899 (define_insn "*absextendsfdf2"
9900 [(set (match_operand:DF 0 "register_operand" "=f")
9901 (abs:DF (float_extend:DF
9902 (match_operand:SF 1 "register_operand" "0"))))]
9903 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9905 [(set_attr "type" "fsgn")
9906 (set_attr "mode" "DF")])
9908 (define_insn "*absextenddfxf2"
9909 [(set (match_operand:XF 0 "register_operand" "=f")
9910 (abs:XF (float_extend:XF
9911 (match_operand:DF 1 "register_operand" "0"))))]
9914 [(set_attr "type" "fsgn")
9915 (set_attr "mode" "XF")])
9917 (define_insn "*absextendsfxf2"
9918 [(set (match_operand:XF 0 "register_operand" "=f")
9919 (abs:XF (float_extend:XF
9920 (match_operand:SF 1 "register_operand" "0"))))]
9923 [(set_attr "type" "fsgn")
9924 (set_attr "mode" "XF")])
9926 ;; One complement instructions
9928 (define_expand "one_cmpldi2"
9929 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9930 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
9932 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
9934 (define_insn "*one_cmpldi2_1_rex64"
9935 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9936 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
9937 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
9939 [(set_attr "type" "negnot")
9940 (set_attr "mode" "DI")])
9942 (define_insn "*one_cmpldi2_2_rex64"
9943 [(set (reg FLAGS_REG)
9944 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9946 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9947 (not:DI (match_dup 1)))]
9948 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9949 && ix86_unary_operator_ok (NOT, DImode, operands)"
9951 [(set_attr "type" "alu1")
9952 (set_attr "mode" "DI")])
9955 [(set (match_operand 0 "flags_reg_operand" "")
9956 (match_operator 2 "compare_operator"
9957 [(not:DI (match_operand:DI 3 "nonimmediate_operand" ""))
9959 (set (match_operand:DI 1 "nonimmediate_operand" "")
9960 (not:DI (match_dup 3)))]
9961 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9962 [(parallel [(set (match_dup 0)
9964 [(xor:DI (match_dup 3) (const_int -1))
9967 (xor:DI (match_dup 3) (const_int -1)))])]
9970 (define_expand "one_cmplsi2"
9971 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9972 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
9974 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
9976 (define_insn "*one_cmplsi2_1"
9977 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9978 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
9979 "ix86_unary_operator_ok (NOT, SImode, operands)"
9981 [(set_attr "type" "negnot")
9982 (set_attr "mode" "SI")])
9984 ;; ??? Currently never generated - xor is used instead.
9985 (define_insn "*one_cmplsi2_1_zext"
9986 [(set (match_operand:DI 0 "register_operand" "=r")
9987 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
9988 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
9990 [(set_attr "type" "negnot")
9991 (set_attr "mode" "SI")])
9993 (define_insn "*one_cmplsi2_2"
9994 [(set (reg FLAGS_REG)
9995 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9997 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9998 (not:SI (match_dup 1)))]
9999 "ix86_match_ccmode (insn, CCNOmode)
10000 && ix86_unary_operator_ok (NOT, SImode, operands)"
10002 [(set_attr "type" "alu1")
10003 (set_attr "mode" "SI")])
10006 [(set (match_operand 0 "flags_reg_operand" "")
10007 (match_operator 2 "compare_operator"
10008 [(not:SI (match_operand:SI 3 "nonimmediate_operand" ""))
10010 (set (match_operand:SI 1 "nonimmediate_operand" "")
10011 (not:SI (match_dup 3)))]
10012 "ix86_match_ccmode (insn, CCNOmode)"
10013 [(parallel [(set (match_dup 0)
10014 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10017 (xor:SI (match_dup 3) (const_int -1)))])]
10020 ;; ??? Currently never generated - xor is used instead.
10021 (define_insn "*one_cmplsi2_2_zext"
10022 [(set (reg FLAGS_REG)
10023 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10025 (set (match_operand:DI 0 "register_operand" "=r")
10026 (zero_extend:DI (not:SI (match_dup 1))))]
10027 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10028 && ix86_unary_operator_ok (NOT, SImode, operands)"
10030 [(set_attr "type" "alu1")
10031 (set_attr "mode" "SI")])
10034 [(set (match_operand 0 "flags_reg_operand" "")
10035 (match_operator 2 "compare_operator"
10036 [(not:SI (match_operand:SI 3 "register_operand" ""))
10038 (set (match_operand:DI 1 "register_operand" "")
10039 (zero_extend:DI (not:SI (match_dup 3))))]
10040 "ix86_match_ccmode (insn, CCNOmode)"
10041 [(parallel [(set (match_dup 0)
10042 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10045 (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
10048 (define_expand "one_cmplhi2"
10049 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10050 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10051 "TARGET_HIMODE_MATH"
10052 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10054 (define_insn "*one_cmplhi2_1"
10055 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10056 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10057 "ix86_unary_operator_ok (NOT, HImode, operands)"
10059 [(set_attr "type" "negnot")
10060 (set_attr "mode" "HI")])
10062 (define_insn "*one_cmplhi2_2"
10063 [(set (reg FLAGS_REG)
10064 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10066 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10067 (not:HI (match_dup 1)))]
10068 "ix86_match_ccmode (insn, CCNOmode)
10069 && ix86_unary_operator_ok (NEG, HImode, operands)"
10071 [(set_attr "type" "alu1")
10072 (set_attr "mode" "HI")])
10075 [(set (match_operand 0 "flags_reg_operand" "")
10076 (match_operator 2 "compare_operator"
10077 [(not:HI (match_operand:HI 3 "nonimmediate_operand" ""))
10079 (set (match_operand:HI 1 "nonimmediate_operand" "")
10080 (not:HI (match_dup 3)))]
10081 "ix86_match_ccmode (insn, CCNOmode)"
10082 [(parallel [(set (match_dup 0)
10083 (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1))
10086 (xor:HI (match_dup 3) (const_int -1)))])]
10089 ;; %%% Potential partial reg stall on alternative 1. What to do?
10090 (define_expand "one_cmplqi2"
10091 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10092 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10093 "TARGET_QIMODE_MATH"
10094 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10096 (define_insn "*one_cmplqi2_1"
10097 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10098 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10099 "ix86_unary_operator_ok (NOT, QImode, operands)"
10103 [(set_attr "type" "negnot")
10104 (set_attr "mode" "QI,SI")])
10106 (define_insn "*one_cmplqi2_2"
10107 [(set (reg FLAGS_REG)
10108 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10110 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10111 (not:QI (match_dup 1)))]
10112 "ix86_match_ccmode (insn, CCNOmode)
10113 && ix86_unary_operator_ok (NOT, QImode, operands)"
10115 [(set_attr "type" "alu1")
10116 (set_attr "mode" "QI")])
10119 [(set (match_operand 0 "flags_reg_operand" "")
10120 (match_operator 2 "compare_operator"
10121 [(not:QI (match_operand:QI 3 "nonimmediate_operand" ""))
10123 (set (match_operand:QI 1 "nonimmediate_operand" "")
10124 (not:QI (match_dup 3)))]
10125 "ix86_match_ccmode (insn, CCNOmode)"
10126 [(parallel [(set (match_dup 0)
10127 (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1))
10130 (xor:QI (match_dup 3) (const_int -1)))])]
10133 ;; Arithmetic shift instructions
10135 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10136 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10137 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10138 ;; from the assembler input.
10140 ;; This instruction shifts the target reg/mem as usual, but instead of
10141 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10142 ;; is a left shift double, bits are taken from the high order bits of
10143 ;; reg, else if the insn is a shift right double, bits are taken from the
10144 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10145 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10147 ;; Since sh[lr]d does not change the `reg' operand, that is done
10148 ;; separately, making all shifts emit pairs of shift double and normal
10149 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10150 ;; support a 63 bit shift, each shift where the count is in a reg expands
10151 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10153 ;; If the shift count is a constant, we need never emit more than one
10154 ;; shift pair, instead using moves and sign extension for counts greater
10157 (define_expand "ashldi3"
10158 [(set (match_operand:DI 0 "shiftdi_operand" "")
10159 (ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
10160 (match_operand:QI 2 "nonmemory_operand" "")))]
10162 "ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;")
10164 (define_insn "*ashldi3_1_rex64"
10165 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10166 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,l")
10167 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10168 (clobber (reg:CC FLAGS_REG))]
10169 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10171 switch (get_attr_type (insn))
10174 if (operands[2] != const1_rtx)
10176 if (!rtx_equal_p (operands[0], operands[1]))
10178 return "add{q}\t{%0, %0|%0, %0}";
10181 if (GET_CODE (operands[2]) != CONST_INT
10182 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10184 operands[1] = gen_rtx_MULT (DImode, operands[1],
10185 GEN_INT (1 << INTVAL (operands[2])));
10186 return "lea{q}\t{%a1, %0|%0, %a1}";
10189 if (REG_P (operands[2]))
10190 return "sal{q}\t{%b2, %0|%0, %b2}";
10191 else if (operands[2] == const1_rtx
10192 && (TARGET_SHIFT1 || optimize_size))
10193 return "sal{q}\t%0";
10195 return "sal{q}\t{%2, %0|%0, %2}";
10198 [(set (attr "type")
10199 (cond [(eq_attr "alternative" "1")
10200 (const_string "lea")
10201 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10203 (match_operand 0 "register_operand" ""))
10204 (match_operand 2 "const1_operand" ""))
10205 (const_string "alu")
10207 (const_string "ishift")))
10208 (set_attr "mode" "DI")])
10210 ;; Convert lea to the lea pattern to avoid flags dependency.
10212 [(set (match_operand:DI 0 "register_operand" "")
10213 (ashift:DI (match_operand:DI 1 "index_register_operand" "")
10214 (match_operand:QI 2 "immediate_operand" "")))
10215 (clobber (reg:CC FLAGS_REG))]
10216 "TARGET_64BIT && reload_completed
10217 && true_regnum (operands[0]) != true_regnum (operands[1])"
10218 [(set (match_dup 0)
10219 (mult:DI (match_dup 1)
10221 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10223 ;; This pattern can't accept a variable shift count, since shifts by
10224 ;; zero don't affect the flags. We assume that shifts by constant
10225 ;; zero are optimized away.
10226 (define_insn "*ashldi3_cmp_rex64"
10227 [(set (reg FLAGS_REG)
10229 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10230 (match_operand:QI 2 "immediate_operand" "e"))
10232 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10233 (ashift:DI (match_dup 1) (match_dup 2)))]
10234 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10235 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10237 switch (get_attr_type (insn))
10240 if (operands[2] != const1_rtx)
10242 return "add{q}\t{%0, %0|%0, %0}";
10245 if (REG_P (operands[2]))
10246 return "sal{q}\t{%b2, %0|%0, %b2}";
10247 else if (operands[2] == const1_rtx
10248 && (TARGET_SHIFT1 || optimize_size))
10249 return "sal{q}\t%0";
10251 return "sal{q}\t{%2, %0|%0, %2}";
10254 [(set (attr "type")
10255 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10257 (match_operand 0 "register_operand" ""))
10258 (match_operand 2 "const1_operand" ""))
10259 (const_string "alu")
10261 (const_string "ishift")))
10262 (set_attr "mode" "DI")])
10264 (define_insn "*ashldi3_1"
10265 [(set (match_operand:DI 0 "register_operand" "=&r,r")
10266 (ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
10267 (match_operand:QI 2 "nonmemory_operand" "Jc,Jc")))
10268 (clobber (reg:CC FLAGS_REG))]
10271 [(set_attr "type" "multi")])
10273 ;; By default we don't ask for a scratch register, because when DImode
10274 ;; values are manipulated, registers are already at a premium. But if
10275 ;; we have one handy, we won't turn it away.
10277 [(match_scratch:SI 3 "r")
10278 (parallel [(set (match_operand:DI 0 "register_operand" "")
10279 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10280 (match_operand:QI 2 "nonmemory_operand" "")))
10281 (clobber (reg:CC FLAGS_REG))])
10283 "!TARGET_64BIT && TARGET_CMOVE"
10285 "ix86_split_ashldi (operands, operands[3]); DONE;")
10288 [(set (match_operand:DI 0 "register_operand" "")
10289 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10290 (match_operand:QI 2 "nonmemory_operand" "")))
10291 (clobber (reg:CC FLAGS_REG))]
10292 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
10294 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10296 (define_insn "x86_shld_1"
10297 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10298 (ior:SI (ashift:SI (match_dup 0)
10299 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10300 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10301 (minus:QI (const_int 32) (match_dup 2)))))
10302 (clobber (reg:CC FLAGS_REG))]
10305 shld{l}\t{%2, %1, %0|%0, %1, %2}
10306 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10307 [(set_attr "type" "ishift")
10308 (set_attr "prefix_0f" "1")
10309 (set_attr "mode" "SI")
10310 (set_attr "pent_pair" "np")
10311 (set_attr "athlon_decode" "vector")])
10313 (define_expand "x86_shift_adj_1"
10314 [(set (reg:CCZ FLAGS_REG)
10315 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10318 (set (match_operand:SI 0 "register_operand" "")
10319 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10320 (match_operand:SI 1 "register_operand" "")
10323 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10324 (match_operand:SI 3 "register_operand" "r")
10329 (define_expand "x86_shift_adj_2"
10330 [(use (match_operand:SI 0 "register_operand" ""))
10331 (use (match_operand:SI 1 "register_operand" ""))
10332 (use (match_operand:QI 2 "register_operand" ""))]
10335 rtx label = gen_label_rtx ();
10338 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10340 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10341 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10342 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10343 gen_rtx_LABEL_REF (VOIDmode, label),
10345 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10346 JUMP_LABEL (tmp) = label;
10348 emit_move_insn (operands[0], operands[1]);
10349 ix86_expand_clear (operands[1]);
10351 emit_label (label);
10352 LABEL_NUSES (label) = 1;
10357 (define_expand "ashlsi3"
10358 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10359 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10360 (match_operand:QI 2 "nonmemory_operand" "")))
10361 (clobber (reg:CC FLAGS_REG))]
10363 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10365 (define_insn "*ashlsi3_1"
10366 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10367 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l")
10368 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10369 (clobber (reg:CC FLAGS_REG))]
10370 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10372 switch (get_attr_type (insn))
10375 if (operands[2] != const1_rtx)
10377 if (!rtx_equal_p (operands[0], operands[1]))
10379 return "add{l}\t{%0, %0|%0, %0}";
10385 if (REG_P (operands[2]))
10386 return "sal{l}\t{%b2, %0|%0, %b2}";
10387 else if (operands[2] == const1_rtx
10388 && (TARGET_SHIFT1 || optimize_size))
10389 return "sal{l}\t%0";
10391 return "sal{l}\t{%2, %0|%0, %2}";
10394 [(set (attr "type")
10395 (cond [(eq_attr "alternative" "1")
10396 (const_string "lea")
10397 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10399 (match_operand 0 "register_operand" ""))
10400 (match_operand 2 "const1_operand" ""))
10401 (const_string "alu")
10403 (const_string "ishift")))
10404 (set_attr "mode" "SI")])
10406 ;; Convert lea to the lea pattern to avoid flags dependency.
10408 [(set (match_operand 0 "register_operand" "")
10409 (ashift (match_operand 1 "index_register_operand" "")
10410 (match_operand:QI 2 "const_int_operand" "")))
10411 (clobber (reg:CC FLAGS_REG))]
10413 && true_regnum (operands[0]) != true_regnum (operands[1])
10414 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 4"
10418 enum machine_mode mode = GET_MODE (operands[0]);
10420 if (GET_MODE_SIZE (mode) < 4)
10421 operands[0] = gen_lowpart (SImode, operands[0]);
10423 operands[1] = gen_lowpart (Pmode, operands[1]);
10424 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10426 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10427 if (Pmode != SImode)
10428 pat = gen_rtx_SUBREG (SImode, pat, 0);
10429 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10433 ;; Rare case of shifting RSP is handled by generating move and shift
10435 [(set (match_operand 0 "register_operand" "")
10436 (ashift (match_operand 1 "register_operand" "")
10437 (match_operand:QI 2 "const_int_operand" "")))
10438 (clobber (reg:CC FLAGS_REG))]
10440 && true_regnum (operands[0]) != true_regnum (operands[1])"
10444 emit_move_insn (operands[1], operands[0]);
10445 pat = gen_rtx_SET (VOIDmode, operands[0],
10446 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10447 operands[0], operands[2]));
10448 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10449 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10453 (define_insn "*ashlsi3_1_zext"
10454 [(set (match_operand:DI 0 "register_operand" "=r,r")
10455 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,l")
10456 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10457 (clobber (reg:CC FLAGS_REG))]
10458 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10460 switch (get_attr_type (insn))
10463 if (operands[2] != const1_rtx)
10465 return "add{l}\t{%k0, %k0|%k0, %k0}";
10471 if (REG_P (operands[2]))
10472 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10473 else if (operands[2] == const1_rtx
10474 && (TARGET_SHIFT1 || optimize_size))
10475 return "sal{l}\t%k0";
10477 return "sal{l}\t{%2, %k0|%k0, %2}";
10480 [(set (attr "type")
10481 (cond [(eq_attr "alternative" "1")
10482 (const_string "lea")
10483 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10485 (match_operand 2 "const1_operand" ""))
10486 (const_string "alu")
10488 (const_string "ishift")))
10489 (set_attr "mode" "SI")])
10491 ;; Convert lea to the lea pattern to avoid flags dependency.
10493 [(set (match_operand:DI 0 "register_operand" "")
10494 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10495 (match_operand:QI 2 "const_int_operand" ""))))
10496 (clobber (reg:CC FLAGS_REG))]
10497 "TARGET_64BIT && reload_completed
10498 && true_regnum (operands[0]) != true_regnum (operands[1])"
10499 [(set (match_dup 0) (zero_extend:DI
10500 (subreg:SI (mult:SI (match_dup 1)
10501 (match_dup 2)) 0)))]
10503 operands[1] = gen_lowpart (Pmode, operands[1]);
10504 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10507 ;; This pattern can't accept a variable shift count, since shifts by
10508 ;; zero don't affect the flags. We assume that shifts by constant
10509 ;; zero are optimized away.
10510 (define_insn "*ashlsi3_cmp"
10511 [(set (reg FLAGS_REG)
10513 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10514 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10516 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10517 (ashift:SI (match_dup 1) (match_dup 2)))]
10518 "ix86_match_ccmode (insn, CCGOCmode)
10519 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10521 switch (get_attr_type (insn))
10524 if (operands[2] != const1_rtx)
10526 return "add{l}\t{%0, %0|%0, %0}";
10529 if (REG_P (operands[2]))
10530 return "sal{l}\t{%b2, %0|%0, %b2}";
10531 else if (operands[2] == const1_rtx
10532 && (TARGET_SHIFT1 || optimize_size))
10533 return "sal{l}\t%0";
10535 return "sal{l}\t{%2, %0|%0, %2}";
10538 [(set (attr "type")
10539 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10541 (match_operand 0 "register_operand" ""))
10542 (match_operand 2 "const1_operand" ""))
10543 (const_string "alu")
10545 (const_string "ishift")))
10546 (set_attr "mode" "SI")])
10548 (define_insn "*ashlsi3_cmp_zext"
10549 [(set (reg FLAGS_REG)
10551 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10552 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10554 (set (match_operand:DI 0 "register_operand" "=r")
10555 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10556 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10557 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10559 switch (get_attr_type (insn))
10562 if (operands[2] != const1_rtx)
10564 return "add{l}\t{%k0, %k0|%k0, %k0}";
10567 if (REG_P (operands[2]))
10568 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10569 else if (operands[2] == const1_rtx
10570 && (TARGET_SHIFT1 || optimize_size))
10571 return "sal{l}\t%k0";
10573 return "sal{l}\t{%2, %k0|%k0, %2}";
10576 [(set (attr "type")
10577 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10579 (match_operand 2 "const1_operand" ""))
10580 (const_string "alu")
10582 (const_string "ishift")))
10583 (set_attr "mode" "SI")])
10585 (define_expand "ashlhi3"
10586 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10587 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10588 (match_operand:QI 2 "nonmemory_operand" "")))
10589 (clobber (reg:CC FLAGS_REG))]
10590 "TARGET_HIMODE_MATH"
10591 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10593 (define_insn "*ashlhi3_1_lea"
10594 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10595 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l")
10596 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10597 (clobber (reg:CC FLAGS_REG))]
10598 "!TARGET_PARTIAL_REG_STALL
10599 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10601 switch (get_attr_type (insn))
10606 if (operands[2] != const1_rtx)
10608 return "add{w}\t{%0, %0|%0, %0}";
10611 if (REG_P (operands[2]))
10612 return "sal{w}\t{%b2, %0|%0, %b2}";
10613 else if (operands[2] == const1_rtx
10614 && (TARGET_SHIFT1 || optimize_size))
10615 return "sal{w}\t%0";
10617 return "sal{w}\t{%2, %0|%0, %2}";
10620 [(set (attr "type")
10621 (cond [(eq_attr "alternative" "1")
10622 (const_string "lea")
10623 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10625 (match_operand 0 "register_operand" ""))
10626 (match_operand 2 "const1_operand" ""))
10627 (const_string "alu")
10629 (const_string "ishift")))
10630 (set_attr "mode" "HI,SI")])
10632 (define_insn "*ashlhi3_1"
10633 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10634 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10635 (match_operand:QI 2 "nonmemory_operand" "cI")))
10636 (clobber (reg:CC FLAGS_REG))]
10637 "TARGET_PARTIAL_REG_STALL
10638 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10640 switch (get_attr_type (insn))
10643 if (operands[2] != const1_rtx)
10645 return "add{w}\t{%0, %0|%0, %0}";
10648 if (REG_P (operands[2]))
10649 return "sal{w}\t{%b2, %0|%0, %b2}";
10650 else if (operands[2] == const1_rtx
10651 && (TARGET_SHIFT1 || optimize_size))
10652 return "sal{w}\t%0";
10654 return "sal{w}\t{%2, %0|%0, %2}";
10657 [(set (attr "type")
10658 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10660 (match_operand 0 "register_operand" ""))
10661 (match_operand 2 "const1_operand" ""))
10662 (const_string "alu")
10664 (const_string "ishift")))
10665 (set_attr "mode" "HI")])
10667 ;; This pattern can't accept a variable shift count, since shifts by
10668 ;; zero don't affect the flags. We assume that shifts by constant
10669 ;; zero are optimized away.
10670 (define_insn "*ashlhi3_cmp"
10671 [(set (reg FLAGS_REG)
10673 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10674 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10676 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10677 (ashift:HI (match_dup 1) (match_dup 2)))]
10678 "ix86_match_ccmode (insn, CCGOCmode)
10679 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10681 switch (get_attr_type (insn))
10684 if (operands[2] != const1_rtx)
10686 return "add{w}\t{%0, %0|%0, %0}";
10689 if (REG_P (operands[2]))
10690 return "sal{w}\t{%b2, %0|%0, %b2}";
10691 else if (operands[2] == const1_rtx
10692 && (TARGET_SHIFT1 || optimize_size))
10693 return "sal{w}\t%0";
10695 return "sal{w}\t{%2, %0|%0, %2}";
10698 [(set (attr "type")
10699 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10701 (match_operand 0 "register_operand" ""))
10702 (match_operand 2 "const1_operand" ""))
10703 (const_string "alu")
10705 (const_string "ishift")))
10706 (set_attr "mode" "HI")])
10708 (define_expand "ashlqi3"
10709 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10710 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10711 (match_operand:QI 2 "nonmemory_operand" "")))
10712 (clobber (reg:CC FLAGS_REG))]
10713 "TARGET_QIMODE_MATH"
10714 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10716 ;; %%% Potential partial reg stall on alternative 2. What to do?
10718 (define_insn "*ashlqi3_1_lea"
10719 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10720 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l")
10721 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10722 (clobber (reg:CC FLAGS_REG))]
10723 "!TARGET_PARTIAL_REG_STALL
10724 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10726 switch (get_attr_type (insn))
10731 if (operands[2] != const1_rtx)
10733 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10734 return "add{l}\t{%k0, %k0|%k0, %k0}";
10736 return "add{b}\t{%0, %0|%0, %0}";
10739 if (REG_P (operands[2]))
10741 if (get_attr_mode (insn) == MODE_SI)
10742 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10744 return "sal{b}\t{%b2, %0|%0, %b2}";
10746 else if (operands[2] == const1_rtx
10747 && (TARGET_SHIFT1 || optimize_size))
10749 if (get_attr_mode (insn) == MODE_SI)
10750 return "sal{l}\t%0";
10752 return "sal{b}\t%0";
10756 if (get_attr_mode (insn) == MODE_SI)
10757 return "sal{l}\t{%2, %k0|%k0, %2}";
10759 return "sal{b}\t{%2, %0|%0, %2}";
10763 [(set (attr "type")
10764 (cond [(eq_attr "alternative" "2")
10765 (const_string "lea")
10766 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10768 (match_operand 0 "register_operand" ""))
10769 (match_operand 2 "const1_operand" ""))
10770 (const_string "alu")
10772 (const_string "ishift")))
10773 (set_attr "mode" "QI,SI,SI")])
10775 (define_insn "*ashlqi3_1"
10776 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10777 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
10778 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
10779 (clobber (reg:CC FLAGS_REG))]
10780 "TARGET_PARTIAL_REG_STALL
10781 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10783 switch (get_attr_type (insn))
10786 if (operands[2] != const1_rtx)
10788 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10789 return "add{l}\t{%k0, %k0|%k0, %k0}";
10791 return "add{b}\t{%0, %0|%0, %0}";
10794 if (REG_P (operands[2]))
10796 if (get_attr_mode (insn) == MODE_SI)
10797 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10799 return "sal{b}\t{%b2, %0|%0, %b2}";
10801 else if (operands[2] == const1_rtx
10802 && (TARGET_SHIFT1 || optimize_size))
10804 if (get_attr_mode (insn) == MODE_SI)
10805 return "sal{l}\t%0";
10807 return "sal{b}\t%0";
10811 if (get_attr_mode (insn) == MODE_SI)
10812 return "sal{l}\t{%2, %k0|%k0, %2}";
10814 return "sal{b}\t{%2, %0|%0, %2}";
10818 [(set (attr "type")
10819 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10821 (match_operand 0 "register_operand" ""))
10822 (match_operand 2 "const1_operand" ""))
10823 (const_string "alu")
10825 (const_string "ishift")))
10826 (set_attr "mode" "QI,SI")])
10828 ;; This pattern can't accept a variable shift count, since shifts by
10829 ;; zero don't affect the flags. We assume that shifts by constant
10830 ;; zero are optimized away.
10831 (define_insn "*ashlqi3_cmp"
10832 [(set (reg FLAGS_REG)
10834 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
10835 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10837 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10838 (ashift:QI (match_dup 1) (match_dup 2)))]
10839 "ix86_match_ccmode (insn, CCGOCmode)
10840 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10842 switch (get_attr_type (insn))
10845 if (operands[2] != const1_rtx)
10847 return "add{b}\t{%0, %0|%0, %0}";
10850 if (REG_P (operands[2]))
10851 return "sal{b}\t{%b2, %0|%0, %b2}";
10852 else if (operands[2] == const1_rtx
10853 && (TARGET_SHIFT1 || optimize_size))
10854 return "sal{b}\t%0";
10856 return "sal{b}\t{%2, %0|%0, %2}";
10859 [(set (attr "type")
10860 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10862 (match_operand 0 "register_operand" ""))
10863 (match_operand 2 "const1_operand" ""))
10864 (const_string "alu")
10866 (const_string "ishift")))
10867 (set_attr "mode" "QI")])
10869 ;; See comment above `ashldi3' about how this works.
10871 (define_expand "ashrdi3"
10872 [(set (match_operand:DI 0 "shiftdi_operand" "")
10873 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
10874 (match_operand:QI 2 "nonmemory_operand" "")))]
10876 "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
10878 (define_insn "*ashrdi3_63_rex64"
10879 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
10880 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
10881 (match_operand:DI 2 "const_int_operand" "i,i")))
10882 (clobber (reg:CC FLAGS_REG))]
10883 "TARGET_64BIT && INTVAL (operands[2]) == 63
10884 && (TARGET_USE_CLTD || optimize_size)
10885 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10888 sar{q}\t{%2, %0|%0, %2}"
10889 [(set_attr "type" "imovx,ishift")
10890 (set_attr "prefix_0f" "0,*")
10891 (set_attr "length_immediate" "0,*")
10892 (set_attr "modrm" "0,1")
10893 (set_attr "mode" "DI")])
10895 (define_insn "*ashrdi3_1_one_bit_rex64"
10896 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10897 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10898 (match_operand:QI 2 "const1_operand" "")))
10899 (clobber (reg:CC FLAGS_REG))]
10900 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
10901 && (TARGET_SHIFT1 || optimize_size)"
10903 [(set_attr "type" "ishift")
10904 (set (attr "length")
10905 (if_then_else (match_operand:DI 0 "register_operand" "")
10907 (const_string "*")))])
10909 (define_insn "*ashrdi3_1_rex64"
10910 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
10911 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
10912 (match_operand:QI 2 "nonmemory_operand" "J,c")))
10913 (clobber (reg:CC FLAGS_REG))]
10914 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10916 sar{q}\t{%2, %0|%0, %2}
10917 sar{q}\t{%b2, %0|%0, %b2}"
10918 [(set_attr "type" "ishift")
10919 (set_attr "mode" "DI")])
10921 ;; This pattern can't accept a variable shift count, since shifts by
10922 ;; zero don't affect the flags. We assume that shifts by constant
10923 ;; zero are optimized away.
10924 (define_insn "*ashrdi3_one_bit_cmp_rex64"
10925 [(set (reg FLAGS_REG)
10927 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10928 (match_operand:QI 2 "const1_operand" ""))
10930 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10931 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10932 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10933 && (TARGET_SHIFT1 || optimize_size)
10934 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10936 [(set_attr "type" "ishift")
10937 (set (attr "length")
10938 (if_then_else (match_operand:DI 0 "register_operand" "")
10940 (const_string "*")))])
10942 ;; This pattern can't accept a variable shift count, since shifts by
10943 ;; zero don't affect the flags. We assume that shifts by constant
10944 ;; zero are optimized away.
10945 (define_insn "*ashrdi3_cmp_rex64"
10946 [(set (reg FLAGS_REG)
10948 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10949 (match_operand:QI 2 "const_int_operand" "n"))
10951 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10952 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10953 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10954 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10955 "sar{q}\t{%2, %0|%0, %2}"
10956 [(set_attr "type" "ishift")
10957 (set_attr "mode" "DI")])
10959 (define_insn "*ashrdi3_1"
10960 [(set (match_operand:DI 0 "register_operand" "=r")
10961 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
10962 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10963 (clobber (reg:CC FLAGS_REG))]
10966 [(set_attr "type" "multi")])
10968 ;; By default we don't ask for a scratch register, because when DImode
10969 ;; values are manipulated, registers are already at a premium. But if
10970 ;; we have one handy, we won't turn it away.
10972 [(match_scratch:SI 3 "r")
10973 (parallel [(set (match_operand:DI 0 "register_operand" "")
10974 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10975 (match_operand:QI 2 "nonmemory_operand" "")))
10976 (clobber (reg:CC FLAGS_REG))])
10978 "!TARGET_64BIT && TARGET_CMOVE"
10980 "ix86_split_ashrdi (operands, operands[3]); DONE;")
10983 [(set (match_operand:DI 0 "register_operand" "")
10984 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10985 (match_operand:QI 2 "nonmemory_operand" "")))
10986 (clobber (reg:CC FLAGS_REG))]
10987 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
10989 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
10991 (define_insn "x86_shrd_1"
10992 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10993 (ior:SI (ashiftrt:SI (match_dup 0)
10994 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10995 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
10996 (minus:QI (const_int 32) (match_dup 2)))))
10997 (clobber (reg:CC FLAGS_REG))]
11000 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11001 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11002 [(set_attr "type" "ishift")
11003 (set_attr "prefix_0f" "1")
11004 (set_attr "pent_pair" "np")
11005 (set_attr "mode" "SI")])
11007 (define_expand "x86_shift_adj_3"
11008 [(use (match_operand:SI 0 "register_operand" ""))
11009 (use (match_operand:SI 1 "register_operand" ""))
11010 (use (match_operand:QI 2 "register_operand" ""))]
11013 rtx label = gen_label_rtx ();
11016 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11018 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11019 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11020 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11021 gen_rtx_LABEL_REF (VOIDmode, label),
11023 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11024 JUMP_LABEL (tmp) = label;
11026 emit_move_insn (operands[0], operands[1]);
11027 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11029 emit_label (label);
11030 LABEL_NUSES (label) = 1;
11035 (define_insn "ashrsi3_31"
11036 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11037 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11038 (match_operand:SI 2 "const_int_operand" "i,i")))
11039 (clobber (reg:CC FLAGS_REG))]
11040 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11041 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11044 sar{l}\t{%2, %0|%0, %2}"
11045 [(set_attr "type" "imovx,ishift")
11046 (set_attr "prefix_0f" "0,*")
11047 (set_attr "length_immediate" "0,*")
11048 (set_attr "modrm" "0,1")
11049 (set_attr "mode" "SI")])
11051 (define_insn "*ashrsi3_31_zext"
11052 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11053 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11054 (match_operand:SI 2 "const_int_operand" "i,i"))))
11055 (clobber (reg:CC FLAGS_REG))]
11056 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11057 && INTVAL (operands[2]) == 31
11058 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11061 sar{l}\t{%2, %k0|%k0, %2}"
11062 [(set_attr "type" "imovx,ishift")
11063 (set_attr "prefix_0f" "0,*")
11064 (set_attr "length_immediate" "0,*")
11065 (set_attr "modrm" "0,1")
11066 (set_attr "mode" "SI")])
11068 (define_expand "ashrsi3"
11069 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11070 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11071 (match_operand:QI 2 "nonmemory_operand" "")))
11072 (clobber (reg:CC FLAGS_REG))]
11074 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11076 (define_insn "*ashrsi3_1_one_bit"
11077 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11078 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11079 (match_operand:QI 2 "const1_operand" "")))
11080 (clobber (reg:CC FLAGS_REG))]
11081 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11082 && (TARGET_SHIFT1 || optimize_size)"
11084 [(set_attr "type" "ishift")
11085 (set (attr "length")
11086 (if_then_else (match_operand:SI 0 "register_operand" "")
11088 (const_string "*")))])
11090 (define_insn "*ashrsi3_1_one_bit_zext"
11091 [(set (match_operand:DI 0 "register_operand" "=r")
11092 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11093 (match_operand:QI 2 "const1_operand" ""))))
11094 (clobber (reg:CC FLAGS_REG))]
11095 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11096 && (TARGET_SHIFT1 || optimize_size)"
11098 [(set_attr "type" "ishift")
11099 (set_attr "length" "2")])
11101 (define_insn "*ashrsi3_1"
11102 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11103 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11104 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11105 (clobber (reg:CC FLAGS_REG))]
11106 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11108 sar{l}\t{%2, %0|%0, %2}
11109 sar{l}\t{%b2, %0|%0, %b2}"
11110 [(set_attr "type" "ishift")
11111 (set_attr "mode" "SI")])
11113 (define_insn "*ashrsi3_1_zext"
11114 [(set (match_operand:DI 0 "register_operand" "=r,r")
11115 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11116 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11117 (clobber (reg:CC FLAGS_REG))]
11118 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11120 sar{l}\t{%2, %k0|%k0, %2}
11121 sar{l}\t{%b2, %k0|%k0, %b2}"
11122 [(set_attr "type" "ishift")
11123 (set_attr "mode" "SI")])
11125 ;; This pattern can't accept a variable shift count, since shifts by
11126 ;; zero don't affect the flags. We assume that shifts by constant
11127 ;; zero are optimized away.
11128 (define_insn "*ashrsi3_one_bit_cmp"
11129 [(set (reg FLAGS_REG)
11131 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11132 (match_operand:QI 2 "const1_operand" ""))
11134 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11135 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11136 "ix86_match_ccmode (insn, CCGOCmode)
11137 && (TARGET_SHIFT1 || optimize_size)
11138 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11140 [(set_attr "type" "ishift")
11141 (set (attr "length")
11142 (if_then_else (match_operand:SI 0 "register_operand" "")
11144 (const_string "*")))])
11146 (define_insn "*ashrsi3_one_bit_cmp_zext"
11147 [(set (reg FLAGS_REG)
11149 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11150 (match_operand:QI 2 "const1_operand" ""))
11152 (set (match_operand:DI 0 "register_operand" "=r")
11153 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11154 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11155 && (TARGET_SHIFT1 || optimize_size)
11156 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11158 [(set_attr "type" "ishift")
11159 (set_attr "length" "2")])
11161 ;; This pattern can't accept a variable shift count, since shifts by
11162 ;; zero don't affect the flags. We assume that shifts by constant
11163 ;; zero are optimized away.
11164 (define_insn "*ashrsi3_cmp"
11165 [(set (reg FLAGS_REG)
11167 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11168 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11170 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11171 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11172 "ix86_match_ccmode (insn, CCGOCmode)
11173 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11174 "sar{l}\t{%2, %0|%0, %2}"
11175 [(set_attr "type" "ishift")
11176 (set_attr "mode" "SI")])
11178 (define_insn "*ashrsi3_cmp_zext"
11179 [(set (reg FLAGS_REG)
11181 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11182 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11184 (set (match_operand:DI 0 "register_operand" "=r")
11185 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11186 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11187 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11188 "sar{l}\t{%2, %k0|%k0, %2}"
11189 [(set_attr "type" "ishift")
11190 (set_attr "mode" "SI")])
11192 (define_expand "ashrhi3"
11193 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11194 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11195 (match_operand:QI 2 "nonmemory_operand" "")))
11196 (clobber (reg:CC FLAGS_REG))]
11197 "TARGET_HIMODE_MATH"
11198 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11200 (define_insn "*ashrhi3_1_one_bit"
11201 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11202 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11203 (match_operand:QI 2 "const1_operand" "")))
11204 (clobber (reg:CC FLAGS_REG))]
11205 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11206 && (TARGET_SHIFT1 || optimize_size)"
11208 [(set_attr "type" "ishift")
11209 (set (attr "length")
11210 (if_then_else (match_operand 0 "register_operand" "")
11212 (const_string "*")))])
11214 (define_insn "*ashrhi3_1"
11215 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11216 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11217 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11218 (clobber (reg:CC FLAGS_REG))]
11219 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11221 sar{w}\t{%2, %0|%0, %2}
11222 sar{w}\t{%b2, %0|%0, %b2}"
11223 [(set_attr "type" "ishift")
11224 (set_attr "mode" "HI")])
11226 ;; This pattern can't accept a variable shift count, since shifts by
11227 ;; zero don't affect the flags. We assume that shifts by constant
11228 ;; zero are optimized away.
11229 (define_insn "*ashrhi3_one_bit_cmp"
11230 [(set (reg FLAGS_REG)
11232 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11233 (match_operand:QI 2 "const1_operand" ""))
11235 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11236 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11237 "ix86_match_ccmode (insn, CCGOCmode)
11238 && (TARGET_SHIFT1 || optimize_size)
11239 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11241 [(set_attr "type" "ishift")
11242 (set (attr "length")
11243 (if_then_else (match_operand 0 "register_operand" "")
11245 (const_string "*")))])
11247 ;; This pattern can't accept a variable shift count, since shifts by
11248 ;; zero don't affect the flags. We assume that shifts by constant
11249 ;; zero are optimized away.
11250 (define_insn "*ashrhi3_cmp"
11251 [(set (reg FLAGS_REG)
11253 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11254 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11256 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11257 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11258 "ix86_match_ccmode (insn, CCGOCmode)
11259 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11260 "sar{w}\t{%2, %0|%0, %2}"
11261 [(set_attr "type" "ishift")
11262 (set_attr "mode" "HI")])
11264 (define_expand "ashrqi3"
11265 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11266 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11267 (match_operand:QI 2 "nonmemory_operand" "")))
11268 (clobber (reg:CC FLAGS_REG))]
11269 "TARGET_QIMODE_MATH"
11270 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11272 (define_insn "*ashrqi3_1_one_bit"
11273 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11274 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11275 (match_operand:QI 2 "const1_operand" "")))
11276 (clobber (reg:CC FLAGS_REG))]
11277 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11278 && (TARGET_SHIFT1 || optimize_size)"
11280 [(set_attr "type" "ishift")
11281 (set (attr "length")
11282 (if_then_else (match_operand 0 "register_operand" "")
11284 (const_string "*")))])
11286 (define_insn "*ashrqi3_1_one_bit_slp"
11287 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11288 (ashiftrt:QI (match_dup 0)
11289 (match_operand:QI 1 "const1_operand" "")))
11290 (clobber (reg:CC FLAGS_REG))]
11291 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11292 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11293 && (TARGET_SHIFT1 || optimize_size)"
11295 [(set_attr "type" "ishift1")
11296 (set (attr "length")
11297 (if_then_else (match_operand 0 "register_operand" "")
11299 (const_string "*")))])
11301 (define_insn "*ashrqi3_1"
11302 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11303 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11304 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11305 (clobber (reg:CC FLAGS_REG))]
11306 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11308 sar{b}\t{%2, %0|%0, %2}
11309 sar{b}\t{%b2, %0|%0, %b2}"
11310 [(set_attr "type" "ishift")
11311 (set_attr "mode" "QI")])
11313 (define_insn "*ashrqi3_1_slp"
11314 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11315 (ashiftrt:QI (match_dup 0)
11316 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11317 (clobber (reg:CC FLAGS_REG))]
11318 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11319 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11321 sar{b}\t{%1, %0|%0, %1}
11322 sar{b}\t{%b1, %0|%0, %b1}"
11323 [(set_attr "type" "ishift1")
11324 (set_attr "mode" "QI")])
11326 ;; This pattern can't accept a variable shift count, since shifts by
11327 ;; zero don't affect the flags. We assume that shifts by constant
11328 ;; zero are optimized away.
11329 (define_insn "*ashrqi3_one_bit_cmp"
11330 [(set (reg FLAGS_REG)
11332 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11333 (match_operand:QI 2 "const1_operand" "I"))
11335 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11336 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11337 "ix86_match_ccmode (insn, CCGOCmode)
11338 && (TARGET_SHIFT1 || optimize_size)
11339 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11341 [(set_attr "type" "ishift")
11342 (set (attr "length")
11343 (if_then_else (match_operand 0 "register_operand" "")
11345 (const_string "*")))])
11347 ;; This pattern can't accept a variable shift count, since shifts by
11348 ;; zero don't affect the flags. We assume that shifts by constant
11349 ;; zero are optimized away.
11350 (define_insn "*ashrqi3_cmp"
11351 [(set (reg FLAGS_REG)
11353 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11354 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11356 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11357 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11358 "ix86_match_ccmode (insn, CCGOCmode)
11359 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11360 "sar{b}\t{%2, %0|%0, %2}"
11361 [(set_attr "type" "ishift")
11362 (set_attr "mode" "QI")])
11364 ;; Logical shift instructions
11366 ;; See comment above `ashldi3' about how this works.
11368 (define_expand "lshrdi3"
11369 [(set (match_operand:DI 0 "shiftdi_operand" "")
11370 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11371 (match_operand:QI 2 "nonmemory_operand" "")))]
11373 "ix86_expand_binary_operator (LSHIFTRT, DImode, operands); DONE;")
11375 (define_insn "*lshrdi3_1_one_bit_rex64"
11376 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11377 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11378 (match_operand:QI 2 "const1_operand" "")))
11379 (clobber (reg:CC FLAGS_REG))]
11380 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11381 && (TARGET_SHIFT1 || optimize_size)"
11383 [(set_attr "type" "ishift")
11384 (set (attr "length")
11385 (if_then_else (match_operand:DI 0 "register_operand" "")
11387 (const_string "*")))])
11389 (define_insn "*lshrdi3_1_rex64"
11390 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11391 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11392 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11393 (clobber (reg:CC FLAGS_REG))]
11394 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11396 shr{q}\t{%2, %0|%0, %2}
11397 shr{q}\t{%b2, %0|%0, %b2}"
11398 [(set_attr "type" "ishift")
11399 (set_attr "mode" "DI")])
11401 ;; This pattern can't accept a variable shift count, since shifts by
11402 ;; zero don't affect the flags. We assume that shifts by constant
11403 ;; zero are optimized away.
11404 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11405 [(set (reg FLAGS_REG)
11407 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11408 (match_operand:QI 2 "const1_operand" ""))
11410 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11411 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11412 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11413 && (TARGET_SHIFT1 || optimize_size)
11414 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11416 [(set_attr "type" "ishift")
11417 (set (attr "length")
11418 (if_then_else (match_operand:DI 0 "register_operand" "")
11420 (const_string "*")))])
11422 ;; This pattern can't accept a variable shift count, since shifts by
11423 ;; zero don't affect the flags. We assume that shifts by constant
11424 ;; zero are optimized away.
11425 (define_insn "*lshrdi3_cmp_rex64"
11426 [(set (reg FLAGS_REG)
11428 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11429 (match_operand:QI 2 "const_int_operand" "e"))
11431 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11432 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11433 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11434 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11435 "shr{q}\t{%2, %0|%0, %2}"
11436 [(set_attr "type" "ishift")
11437 (set_attr "mode" "DI")])
11439 (define_insn "*lshrdi3_1"
11440 [(set (match_operand:DI 0 "register_operand" "=r")
11441 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11442 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11443 (clobber (reg:CC FLAGS_REG))]
11446 [(set_attr "type" "multi")])
11448 ;; By default we don't ask for a scratch register, because when DImode
11449 ;; values are manipulated, registers are already at a premium. But if
11450 ;; we have one handy, we won't turn it away.
11452 [(match_scratch:SI 3 "r")
11453 (parallel [(set (match_operand:DI 0 "register_operand" "")
11454 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11455 (match_operand:QI 2 "nonmemory_operand" "")))
11456 (clobber (reg:CC FLAGS_REG))])
11458 "!TARGET_64BIT && TARGET_CMOVE"
11460 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11463 [(set (match_operand:DI 0 "register_operand" "")
11464 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11465 (match_operand:QI 2 "nonmemory_operand" "")))
11466 (clobber (reg:CC FLAGS_REG))]
11467 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
11469 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11471 (define_expand "lshrsi3"
11472 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11473 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11474 (match_operand:QI 2 "nonmemory_operand" "")))
11475 (clobber (reg:CC FLAGS_REG))]
11477 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11479 (define_insn "*lshrsi3_1_one_bit"
11480 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11481 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11482 (match_operand:QI 2 "const1_operand" "")))
11483 (clobber (reg:CC FLAGS_REG))]
11484 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11485 && (TARGET_SHIFT1 || optimize_size)"
11487 [(set_attr "type" "ishift")
11488 (set (attr "length")
11489 (if_then_else (match_operand:SI 0 "register_operand" "")
11491 (const_string "*")))])
11493 (define_insn "*lshrsi3_1_one_bit_zext"
11494 [(set (match_operand:DI 0 "register_operand" "=r")
11495 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11496 (match_operand:QI 2 "const1_operand" "")))
11497 (clobber (reg:CC FLAGS_REG))]
11498 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11499 && (TARGET_SHIFT1 || optimize_size)"
11501 [(set_attr "type" "ishift")
11502 (set_attr "length" "2")])
11504 (define_insn "*lshrsi3_1"
11505 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11506 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11507 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11508 (clobber (reg:CC FLAGS_REG))]
11509 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11511 shr{l}\t{%2, %0|%0, %2}
11512 shr{l}\t{%b2, %0|%0, %b2}"
11513 [(set_attr "type" "ishift")
11514 (set_attr "mode" "SI")])
11516 (define_insn "*lshrsi3_1_zext"
11517 [(set (match_operand:DI 0 "register_operand" "=r,r")
11519 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11520 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11521 (clobber (reg:CC FLAGS_REG))]
11522 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11524 shr{l}\t{%2, %k0|%k0, %2}
11525 shr{l}\t{%b2, %k0|%k0, %b2}"
11526 [(set_attr "type" "ishift")
11527 (set_attr "mode" "SI")])
11529 ;; This pattern can't accept a variable shift count, since shifts by
11530 ;; zero don't affect the flags. We assume that shifts by constant
11531 ;; zero are optimized away.
11532 (define_insn "*lshrsi3_one_bit_cmp"
11533 [(set (reg FLAGS_REG)
11535 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11536 (match_operand:QI 2 "const1_operand" ""))
11538 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11539 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11540 "ix86_match_ccmode (insn, CCGOCmode)
11541 && (TARGET_SHIFT1 || optimize_size)
11542 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11544 [(set_attr "type" "ishift")
11545 (set (attr "length")
11546 (if_then_else (match_operand:SI 0 "register_operand" "")
11548 (const_string "*")))])
11550 (define_insn "*lshrsi3_cmp_one_bit_zext"
11551 [(set (reg FLAGS_REG)
11553 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11554 (match_operand:QI 2 "const1_operand" ""))
11556 (set (match_operand:DI 0 "register_operand" "=r")
11557 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11558 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11559 && (TARGET_SHIFT1 || optimize_size)
11560 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11562 [(set_attr "type" "ishift")
11563 (set_attr "length" "2")])
11565 ;; This pattern can't accept a variable shift count, since shifts by
11566 ;; zero don't affect the flags. We assume that shifts by constant
11567 ;; zero are optimized away.
11568 (define_insn "*lshrsi3_cmp"
11569 [(set (reg FLAGS_REG)
11571 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11572 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11574 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11575 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11576 "ix86_match_ccmode (insn, CCGOCmode)
11577 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11578 "shr{l}\t{%2, %0|%0, %2}"
11579 [(set_attr "type" "ishift")
11580 (set_attr "mode" "SI")])
11582 (define_insn "*lshrsi3_cmp_zext"
11583 [(set (reg FLAGS_REG)
11585 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11586 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11588 (set (match_operand:DI 0 "register_operand" "=r")
11589 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11590 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11591 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11592 "shr{l}\t{%2, %k0|%k0, %2}"
11593 [(set_attr "type" "ishift")
11594 (set_attr "mode" "SI")])
11596 (define_expand "lshrhi3"
11597 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11598 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11599 (match_operand:QI 2 "nonmemory_operand" "")))
11600 (clobber (reg:CC FLAGS_REG))]
11601 "TARGET_HIMODE_MATH"
11602 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11604 (define_insn "*lshrhi3_1_one_bit"
11605 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11606 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11607 (match_operand:QI 2 "const1_operand" "")))
11608 (clobber (reg:CC FLAGS_REG))]
11609 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11610 && (TARGET_SHIFT1 || optimize_size)"
11612 [(set_attr "type" "ishift")
11613 (set (attr "length")
11614 (if_then_else (match_operand 0 "register_operand" "")
11616 (const_string "*")))])
11618 (define_insn "*lshrhi3_1"
11619 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11620 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11621 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11622 (clobber (reg:CC FLAGS_REG))]
11623 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11625 shr{w}\t{%2, %0|%0, %2}
11626 shr{w}\t{%b2, %0|%0, %b2}"
11627 [(set_attr "type" "ishift")
11628 (set_attr "mode" "HI")])
11630 ;; This pattern can't accept a variable shift count, since shifts by
11631 ;; zero don't affect the flags. We assume that shifts by constant
11632 ;; zero are optimized away.
11633 (define_insn "*lshrhi3_one_bit_cmp"
11634 [(set (reg FLAGS_REG)
11636 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11637 (match_operand:QI 2 "const1_operand" ""))
11639 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11640 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11641 "ix86_match_ccmode (insn, CCGOCmode)
11642 && (TARGET_SHIFT1 || optimize_size)
11643 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11645 [(set_attr "type" "ishift")
11646 (set (attr "length")
11647 (if_then_else (match_operand:SI 0 "register_operand" "")
11649 (const_string "*")))])
11651 ;; This pattern can't accept a variable shift count, since shifts by
11652 ;; zero don't affect the flags. We assume that shifts by constant
11653 ;; zero are optimized away.
11654 (define_insn "*lshrhi3_cmp"
11655 [(set (reg FLAGS_REG)
11657 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11658 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11660 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11661 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11662 "ix86_match_ccmode (insn, CCGOCmode)
11663 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11664 "shr{w}\t{%2, %0|%0, %2}"
11665 [(set_attr "type" "ishift")
11666 (set_attr "mode" "HI")])
11668 (define_expand "lshrqi3"
11669 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11670 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11671 (match_operand:QI 2 "nonmemory_operand" "")))
11672 (clobber (reg:CC FLAGS_REG))]
11673 "TARGET_QIMODE_MATH"
11674 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11676 (define_insn "*lshrqi3_1_one_bit"
11677 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11678 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11679 (match_operand:QI 2 "const1_operand" "")))
11680 (clobber (reg:CC FLAGS_REG))]
11681 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11682 && (TARGET_SHIFT1 || optimize_size)"
11684 [(set_attr "type" "ishift")
11685 (set (attr "length")
11686 (if_then_else (match_operand 0 "register_operand" "")
11688 (const_string "*")))])
11690 (define_insn "*lshrqi3_1_one_bit_slp"
11691 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11692 (lshiftrt:QI (match_dup 0)
11693 (match_operand:QI 1 "const1_operand" "")))
11694 (clobber (reg:CC FLAGS_REG))]
11695 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11696 && (TARGET_SHIFT1 || optimize_size)"
11698 [(set_attr "type" "ishift1")
11699 (set (attr "length")
11700 (if_then_else (match_operand 0 "register_operand" "")
11702 (const_string "*")))])
11704 (define_insn "*lshrqi3_1"
11705 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11706 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11707 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11708 (clobber (reg:CC FLAGS_REG))]
11709 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11711 shr{b}\t{%2, %0|%0, %2}
11712 shr{b}\t{%b2, %0|%0, %b2}"
11713 [(set_attr "type" "ishift")
11714 (set_attr "mode" "QI")])
11716 (define_insn "*lshrqi3_1_slp"
11717 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11718 (lshiftrt:QI (match_dup 0)
11719 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11720 (clobber (reg:CC FLAGS_REG))]
11721 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11722 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11724 shr{b}\t{%1, %0|%0, %1}
11725 shr{b}\t{%b1, %0|%0, %b1}"
11726 [(set_attr "type" "ishift1")
11727 (set_attr "mode" "QI")])
11729 ;; This pattern can't accept a variable shift count, since shifts by
11730 ;; zero don't affect the flags. We assume that shifts by constant
11731 ;; zero are optimized away.
11732 (define_insn "*lshrqi2_one_bit_cmp"
11733 [(set (reg FLAGS_REG)
11735 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11736 (match_operand:QI 2 "const1_operand" ""))
11738 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11739 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11740 "ix86_match_ccmode (insn, CCGOCmode)
11741 && (TARGET_SHIFT1 || optimize_size)
11742 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11744 [(set_attr "type" "ishift")
11745 (set (attr "length")
11746 (if_then_else (match_operand:SI 0 "register_operand" "")
11748 (const_string "*")))])
11750 ;; This pattern can't accept a variable shift count, since shifts by
11751 ;; zero don't affect the flags. We assume that shifts by constant
11752 ;; zero are optimized away.
11753 (define_insn "*lshrqi2_cmp"
11754 [(set (reg FLAGS_REG)
11756 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11757 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11759 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11760 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11761 "ix86_match_ccmode (insn, CCGOCmode)
11762 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11763 "shr{b}\t{%2, %0|%0, %2}"
11764 [(set_attr "type" "ishift")
11765 (set_attr "mode" "QI")])
11767 ;; Rotate instructions
11769 (define_expand "rotldi3"
11770 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11771 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
11772 (match_operand:QI 2 "nonmemory_operand" "")))
11773 (clobber (reg:CC FLAGS_REG))]
11775 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
11777 (define_insn "*rotlsi3_1_one_bit_rex64"
11778 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11779 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11780 (match_operand:QI 2 "const1_operand" "")))
11781 (clobber (reg:CC FLAGS_REG))]
11782 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
11783 && (TARGET_SHIFT1 || optimize_size)"
11785 [(set_attr "type" "rotate")
11786 (set (attr "length")
11787 (if_then_else (match_operand:DI 0 "register_operand" "")
11789 (const_string "*")))])
11791 (define_insn "*rotldi3_1_rex64"
11792 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11793 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11794 (match_operand:QI 2 "nonmemory_operand" "e,c")))
11795 (clobber (reg:CC FLAGS_REG))]
11796 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
11798 rol{q}\t{%2, %0|%0, %2}
11799 rol{q}\t{%b2, %0|%0, %b2}"
11800 [(set_attr "type" "rotate")
11801 (set_attr "mode" "DI")])
11803 (define_expand "rotlsi3"
11804 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11805 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
11806 (match_operand:QI 2 "nonmemory_operand" "")))
11807 (clobber (reg:CC FLAGS_REG))]
11809 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
11811 (define_insn "*rotlsi3_1_one_bit"
11812 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11813 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11814 (match_operand:QI 2 "const1_operand" "")))
11815 (clobber (reg:CC FLAGS_REG))]
11816 "ix86_binary_operator_ok (ROTATE, SImode, operands)
11817 && (TARGET_SHIFT1 || optimize_size)"
11819 [(set_attr "type" "rotate")
11820 (set (attr "length")
11821 (if_then_else (match_operand:SI 0 "register_operand" "")
11823 (const_string "*")))])
11825 (define_insn "*rotlsi3_1_one_bit_zext"
11826 [(set (match_operand:DI 0 "register_operand" "=r")
11828 (rotate:SI (match_operand:SI 1 "register_operand" "0")
11829 (match_operand:QI 2 "const1_operand" ""))))
11830 (clobber (reg:CC FLAGS_REG))]
11831 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
11832 && (TARGET_SHIFT1 || optimize_size)"
11834 [(set_attr "type" "rotate")
11835 (set_attr "length" "2")])
11837 (define_insn "*rotlsi3_1"
11838 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11839 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11840 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11841 (clobber (reg:CC FLAGS_REG))]
11842 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
11844 rol{l}\t{%2, %0|%0, %2}
11845 rol{l}\t{%b2, %0|%0, %b2}"
11846 [(set_attr "type" "rotate")
11847 (set_attr "mode" "SI")])
11849 (define_insn "*rotlsi3_1_zext"
11850 [(set (match_operand:DI 0 "register_operand" "=r,r")
11852 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
11853 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11854 (clobber (reg:CC FLAGS_REG))]
11855 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
11857 rol{l}\t{%2, %k0|%k0, %2}
11858 rol{l}\t{%b2, %k0|%k0, %b2}"
11859 [(set_attr "type" "rotate")
11860 (set_attr "mode" "SI")])
11862 (define_expand "rotlhi3"
11863 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11864 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
11865 (match_operand:QI 2 "nonmemory_operand" "")))
11866 (clobber (reg:CC FLAGS_REG))]
11867 "TARGET_HIMODE_MATH"
11868 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
11870 (define_insn "*rotlhi3_1_one_bit"
11871 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11872 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11873 (match_operand:QI 2 "const1_operand" "")))
11874 (clobber (reg:CC FLAGS_REG))]
11875 "ix86_binary_operator_ok (ROTATE, HImode, operands)
11876 && (TARGET_SHIFT1 || optimize_size)"
11878 [(set_attr "type" "rotate")
11879 (set (attr "length")
11880 (if_then_else (match_operand 0 "register_operand" "")
11882 (const_string "*")))])
11884 (define_insn "*rotlhi3_1"
11885 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11886 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11887 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11888 (clobber (reg:CC FLAGS_REG))]
11889 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
11891 rol{w}\t{%2, %0|%0, %2}
11892 rol{w}\t{%b2, %0|%0, %b2}"
11893 [(set_attr "type" "rotate")
11894 (set_attr "mode" "HI")])
11896 (define_expand "rotlqi3"
11897 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11898 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
11899 (match_operand:QI 2 "nonmemory_operand" "")))
11900 (clobber (reg:CC FLAGS_REG))]
11901 "TARGET_QIMODE_MATH"
11902 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
11904 (define_insn "*rotlqi3_1_one_bit_slp"
11905 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11906 (rotate:QI (match_dup 0)
11907 (match_operand:QI 1 "const1_operand" "")))
11908 (clobber (reg:CC FLAGS_REG))]
11909 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11910 && (TARGET_SHIFT1 || optimize_size)"
11912 [(set_attr "type" "rotate1")
11913 (set (attr "length")
11914 (if_then_else (match_operand 0 "register_operand" "")
11916 (const_string "*")))])
11918 (define_insn "*rotlqi3_1_one_bit"
11919 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11920 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11921 (match_operand:QI 2 "const1_operand" "")))
11922 (clobber (reg:CC FLAGS_REG))]
11923 "ix86_binary_operator_ok (ROTATE, QImode, operands)
11924 && (TARGET_SHIFT1 || optimize_size)"
11926 [(set_attr "type" "rotate")
11927 (set (attr "length")
11928 (if_then_else (match_operand 0 "register_operand" "")
11930 (const_string "*")))])
11932 (define_insn "*rotlqi3_1_slp"
11933 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11934 (rotate:QI (match_dup 0)
11935 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11936 (clobber (reg:CC FLAGS_REG))]
11937 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11938 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11940 rol{b}\t{%1, %0|%0, %1}
11941 rol{b}\t{%b1, %0|%0, %b1}"
11942 [(set_attr "type" "rotate1")
11943 (set_attr "mode" "QI")])
11945 (define_insn "*rotlqi3_1"
11946 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11947 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11948 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11949 (clobber (reg:CC FLAGS_REG))]
11950 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
11952 rol{b}\t{%2, %0|%0, %2}
11953 rol{b}\t{%b2, %0|%0, %b2}"
11954 [(set_attr "type" "rotate")
11955 (set_attr "mode" "QI")])
11957 (define_expand "rotrdi3"
11958 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11959 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
11960 (match_operand:QI 2 "nonmemory_operand" "")))
11961 (clobber (reg:CC FLAGS_REG))]
11963 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
11965 (define_insn "*rotrdi3_1_one_bit_rex64"
11966 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11967 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11968 (match_operand:QI 2 "const1_operand" "")))
11969 (clobber (reg:CC FLAGS_REG))]
11970 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
11971 && (TARGET_SHIFT1 || optimize_size)"
11973 [(set_attr "type" "rotate")
11974 (set (attr "length")
11975 (if_then_else (match_operand:DI 0 "register_operand" "")
11977 (const_string "*")))])
11979 (define_insn "*rotrdi3_1_rex64"
11980 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11981 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11982 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11983 (clobber (reg:CC FLAGS_REG))]
11984 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
11986 ror{q}\t{%2, %0|%0, %2}
11987 ror{q}\t{%b2, %0|%0, %b2}"
11988 [(set_attr "type" "rotate")
11989 (set_attr "mode" "DI")])
11991 (define_expand "rotrsi3"
11992 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11993 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
11994 (match_operand:QI 2 "nonmemory_operand" "")))
11995 (clobber (reg:CC FLAGS_REG))]
11997 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
11999 (define_insn "*rotrsi3_1_one_bit"
12000 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12001 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12002 (match_operand:QI 2 "const1_operand" "")))
12003 (clobber (reg:CC FLAGS_REG))]
12004 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12005 && (TARGET_SHIFT1 || optimize_size)"
12007 [(set_attr "type" "rotate")
12008 (set (attr "length")
12009 (if_then_else (match_operand:SI 0 "register_operand" "")
12011 (const_string "*")))])
12013 (define_insn "*rotrsi3_1_one_bit_zext"
12014 [(set (match_operand:DI 0 "register_operand" "=r")
12016 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12017 (match_operand:QI 2 "const1_operand" ""))))
12018 (clobber (reg:CC FLAGS_REG))]
12019 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12020 && (TARGET_SHIFT1 || optimize_size)"
12022 [(set_attr "type" "rotate")
12023 (set (attr "length")
12024 (if_then_else (match_operand:SI 0 "register_operand" "")
12026 (const_string "*")))])
12028 (define_insn "*rotrsi3_1"
12029 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12030 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12031 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12032 (clobber (reg:CC FLAGS_REG))]
12033 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12035 ror{l}\t{%2, %0|%0, %2}
12036 ror{l}\t{%b2, %0|%0, %b2}"
12037 [(set_attr "type" "rotate")
12038 (set_attr "mode" "SI")])
12040 (define_insn "*rotrsi3_1_zext"
12041 [(set (match_operand:DI 0 "register_operand" "=r,r")
12043 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12044 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12045 (clobber (reg:CC FLAGS_REG))]
12046 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12048 ror{l}\t{%2, %k0|%k0, %2}
12049 ror{l}\t{%b2, %k0|%k0, %b2}"
12050 [(set_attr "type" "rotate")
12051 (set_attr "mode" "SI")])
12053 (define_expand "rotrhi3"
12054 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12055 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12056 (match_operand:QI 2 "nonmemory_operand" "")))
12057 (clobber (reg:CC FLAGS_REG))]
12058 "TARGET_HIMODE_MATH"
12059 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12061 (define_insn "*rotrhi3_one_bit"
12062 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12063 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12064 (match_operand:QI 2 "const1_operand" "")))
12065 (clobber (reg:CC FLAGS_REG))]
12066 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12067 && (TARGET_SHIFT1 || optimize_size)"
12069 [(set_attr "type" "rotate")
12070 (set (attr "length")
12071 (if_then_else (match_operand 0 "register_operand" "")
12073 (const_string "*")))])
12075 (define_insn "*rotrhi3"
12076 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12077 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12078 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12079 (clobber (reg:CC FLAGS_REG))]
12080 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12082 ror{w}\t{%2, %0|%0, %2}
12083 ror{w}\t{%b2, %0|%0, %b2}"
12084 [(set_attr "type" "rotate")
12085 (set_attr "mode" "HI")])
12087 (define_expand "rotrqi3"
12088 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12089 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12090 (match_operand:QI 2 "nonmemory_operand" "")))
12091 (clobber (reg:CC FLAGS_REG))]
12092 "TARGET_QIMODE_MATH"
12093 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12095 (define_insn "*rotrqi3_1_one_bit"
12096 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12097 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12098 (match_operand:QI 2 "const1_operand" "")))
12099 (clobber (reg:CC FLAGS_REG))]
12100 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12101 && (TARGET_SHIFT1 || optimize_size)"
12103 [(set_attr "type" "rotate")
12104 (set (attr "length")
12105 (if_then_else (match_operand 0 "register_operand" "")
12107 (const_string "*")))])
12109 (define_insn "*rotrqi3_1_one_bit_slp"
12110 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12111 (rotatert:QI (match_dup 0)
12112 (match_operand:QI 1 "const1_operand" "")))
12113 (clobber (reg:CC FLAGS_REG))]
12114 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12115 && (TARGET_SHIFT1 || optimize_size)"
12117 [(set_attr "type" "rotate1")
12118 (set (attr "length")
12119 (if_then_else (match_operand 0 "register_operand" "")
12121 (const_string "*")))])
12123 (define_insn "*rotrqi3_1"
12124 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12125 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12126 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12127 (clobber (reg:CC FLAGS_REG))]
12128 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12130 ror{b}\t{%2, %0|%0, %2}
12131 ror{b}\t{%b2, %0|%0, %b2}"
12132 [(set_attr "type" "rotate")
12133 (set_attr "mode" "QI")])
12135 (define_insn "*rotrqi3_1_slp"
12136 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12137 (rotatert:QI (match_dup 0)
12138 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12139 (clobber (reg:CC FLAGS_REG))]
12140 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12141 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12143 ror{b}\t{%1, %0|%0, %1}
12144 ror{b}\t{%b1, %0|%0, %b1}"
12145 [(set_attr "type" "rotate1")
12146 (set_attr "mode" "QI")])
12148 ;; Bit set / bit test instructions
12150 (define_expand "extv"
12151 [(set (match_operand:SI 0 "register_operand" "")
12152 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12153 (match_operand:SI 2 "immediate_operand" "")
12154 (match_operand:SI 3 "immediate_operand" "")))]
12157 /* Handle extractions from %ah et al. */
12158 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12161 /* From mips.md: extract_bit_field doesn't verify that our source
12162 matches the predicate, so check it again here. */
12163 if (! register_operand (operands[1], VOIDmode))
12167 (define_expand "extzv"
12168 [(set (match_operand:SI 0 "register_operand" "")
12169 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12170 (match_operand:SI 2 "immediate_operand" "")
12171 (match_operand:SI 3 "immediate_operand" "")))]
12174 /* Handle extractions from %ah et al. */
12175 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12178 /* From mips.md: extract_bit_field doesn't verify that our source
12179 matches the predicate, so check it again here. */
12180 if (! register_operand (operands[1], VOIDmode))
12184 (define_expand "insv"
12185 [(set (zero_extract (match_operand 0 "ext_register_operand" "")
12186 (match_operand 1 "immediate_operand" "")
12187 (match_operand 2 "immediate_operand" ""))
12188 (match_operand 3 "register_operand" ""))]
12191 /* Handle extractions from %ah et al. */
12192 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12195 /* From mips.md: insert_bit_field doesn't verify that our source
12196 matches the predicate, so check it again here. */
12197 if (! register_operand (operands[0], VOIDmode))
12201 emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
12203 emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
12208 ;; %%% bts, btr, btc, bt.
12209 ;; In general these instructions are *slow* when applied to memory,
12210 ;; since they enforce atomic operation. When applied to registers,
12211 ;; it depends on the cpu implementation. They're never faster than
12212 ;; the corresponding and/ior/xor operations, so with 32-bit there's
12213 ;; no point. But in 64-bit, we can't hold the relevant immediates
12214 ;; within the instruction itself, so operating on bits in the high
12215 ;; 32-bits of a register becomes easier.
12217 ;; These are slow on Nocona, but fast on Athlon64. We do require the use
12218 ;; of btrq and btcq for corner cases of post-reload expansion of absdf and
12219 ;; negdf respectively, so they can never be disabled entirely.
12221 (define_insn "*btsq"
12222 [(set (zero_extract:DI (match_operand 0 "register_operand" "+r")
12224 (match_operand 1 "const_0_to_63_operand" ""))
12226 (clobber (reg:CC FLAGS_REG))]
12227 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12229 [(set_attr "type" "alu1")])
12231 (define_insn "*btrq"
12232 [(set (zero_extract:DI (match_operand 0 "register_operand" "+r")
12234 (match_operand 1 "const_0_to_63_operand" ""))
12236 (clobber (reg:CC FLAGS_REG))]
12237 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12239 [(set_attr "type" "alu1")])
12241 (define_insn "*btcq"
12242 [(set (zero_extract:DI (match_operand 0 "register_operand" "+r")
12244 (match_operand 1 "const_0_to_63_operand" ""))
12245 (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
12246 (clobber (reg:CC FLAGS_REG))]
12247 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12249 [(set_attr "type" "alu1")])
12251 ;; Allow Nocona to avoid these instructions if a register is available.
12254 [(match_scratch:DI 2 "r")
12255 (parallel [(set (zero_extract:DI
12256 (match_operand 0 "register_operand" "")
12258 (match_operand 1 "const_0_to_63_operand" ""))
12260 (clobber (reg:CC FLAGS_REG))])]
12261 "TARGET_64BIT && !TARGET_USE_BT"
12264 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12267 if (HOST_BITS_PER_WIDE_INT >= 64)
12268 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12269 else if (i < HOST_BITS_PER_WIDE_INT)
12270 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12272 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12274 op1 = immed_double_const (lo, hi, DImode);
12277 emit_move_insn (operands[2], op1);
12281 emit_insn (gen_iordi3 (operands[0], operands[0], op1));
12286 [(match_scratch:DI 2 "r")
12287 (parallel [(set (zero_extract:DI
12288 (match_operand 0 "register_operand" "")
12290 (match_operand 1 "const_0_to_63_operand" ""))
12292 (clobber (reg:CC FLAGS_REG))])]
12293 "TARGET_64BIT && !TARGET_USE_BT"
12296 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12299 if (HOST_BITS_PER_WIDE_INT >= 64)
12300 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12301 else if (i < HOST_BITS_PER_WIDE_INT)
12302 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12304 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12306 op1 = immed_double_const (~lo, ~hi, DImode);
12309 emit_move_insn (operands[2], op1);
12313 emit_insn (gen_anddi3 (operands[0], operands[0], op1));
12318 [(match_scratch:DI 2 "r")
12319 (parallel [(set (zero_extract:DI
12320 (match_operand 0 "register_operand" "")
12322 (match_operand 1 "const_0_to_63_operand" ""))
12323 (not:DI (zero_extract:DI
12324 (match_dup 0) (const_int 1) (match_dup 1))))
12325 (clobber (reg:CC FLAGS_REG))])]
12326 "TARGET_64BIT && !TARGET_USE_BT"
12329 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12332 if (HOST_BITS_PER_WIDE_INT >= 64)
12333 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12334 else if (i < HOST_BITS_PER_WIDE_INT)
12335 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12337 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12339 op1 = immed_double_const (lo, hi, DImode);
12342 emit_move_insn (operands[2], op1);
12346 emit_insn (gen_xordi3 (operands[0], operands[0], op1));
12350 ;; Store-flag instructions.
12352 ;; For all sCOND expanders, also expand the compare or test insn that
12353 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12355 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12356 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12357 ;; way, which can later delete the movzx if only QImode is needed.
12359 (define_expand "seq"
12360 [(set (match_operand:QI 0 "register_operand" "")
12361 (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12363 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12365 (define_expand "sne"
12366 [(set (match_operand:QI 0 "register_operand" "")
12367 (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
12369 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12371 (define_expand "sgt"
12372 [(set (match_operand:QI 0 "register_operand" "")
12373 (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12375 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12377 (define_expand "sgtu"
12378 [(set (match_operand:QI 0 "register_operand" "")
12379 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12381 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12383 (define_expand "slt"
12384 [(set (match_operand:QI 0 "register_operand" "")
12385 (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12387 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12389 (define_expand "sltu"
12390 [(set (match_operand:QI 0 "register_operand" "")
12391 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12393 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12395 (define_expand "sge"
12396 [(set (match_operand:QI 0 "register_operand" "")
12397 (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12399 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12401 (define_expand "sgeu"
12402 [(set (match_operand:QI 0 "register_operand" "")
12403 (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12405 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12407 (define_expand "sle"
12408 [(set (match_operand:QI 0 "register_operand" "")
12409 (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
12411 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12413 (define_expand "sleu"
12414 [(set (match_operand:QI 0 "register_operand" "")
12415 (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12417 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12419 (define_expand "sunordered"
12420 [(set (match_operand:QI 0 "register_operand" "")
12421 (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12422 "TARGET_80387 || TARGET_SSE"
12423 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12425 (define_expand "sordered"
12426 [(set (match_operand:QI 0 "register_operand" "")
12427 (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12429 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12431 (define_expand "suneq"
12432 [(set (match_operand:QI 0 "register_operand" "")
12433 (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12434 "TARGET_80387 || TARGET_SSE"
12435 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12437 (define_expand "sunge"
12438 [(set (match_operand:QI 0 "register_operand" "")
12439 (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12440 "TARGET_80387 || TARGET_SSE"
12441 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12443 (define_expand "sungt"
12444 [(set (match_operand:QI 0 "register_operand" "")
12445 (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12446 "TARGET_80387 || TARGET_SSE"
12447 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12449 (define_expand "sunle"
12450 [(set (match_operand:QI 0 "register_operand" "")
12451 (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
12452 "TARGET_80387 || TARGET_SSE"
12453 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12455 (define_expand "sunlt"
12456 [(set (match_operand:QI 0 "register_operand" "")
12457 (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12458 "TARGET_80387 || TARGET_SSE"
12459 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12461 (define_expand "sltgt"
12462 [(set (match_operand:QI 0 "register_operand" "")
12463 (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12464 "TARGET_80387 || TARGET_SSE"
12465 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12467 (define_insn "*setcc_1"
12468 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12469 (match_operator:QI 1 "ix86_comparison_operator"
12470 [(reg FLAGS_REG) (const_int 0)]))]
12473 [(set_attr "type" "setcc")
12474 (set_attr "mode" "QI")])
12476 (define_insn "*setcc_2"
12477 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12478 (match_operator:QI 1 "ix86_comparison_operator"
12479 [(reg FLAGS_REG) (const_int 0)]))]
12482 [(set_attr "type" "setcc")
12483 (set_attr "mode" "QI")])
12485 ;; In general it is not safe to assume too much about CCmode registers,
12486 ;; so simplify-rtx stops when it sees a second one. Under certain
12487 ;; conditions this is safe on x86, so help combine not create
12494 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12495 (ne:QI (match_operator 1 "ix86_comparison_operator"
12496 [(reg FLAGS_REG) (const_int 0)])
12499 [(set (match_dup 0) (match_dup 1))]
12501 PUT_MODE (operands[1], QImode);
12505 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12506 (ne:QI (match_operator 1 "ix86_comparison_operator"
12507 [(reg FLAGS_REG) (const_int 0)])
12510 [(set (match_dup 0) (match_dup 1))]
12512 PUT_MODE (operands[1], QImode);
12516 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12517 (eq:QI (match_operator 1 "ix86_comparison_operator"
12518 [(reg FLAGS_REG) (const_int 0)])
12521 [(set (match_dup 0) (match_dup 1))]
12523 rtx new_op1 = copy_rtx (operands[1]);
12524 operands[1] = new_op1;
12525 PUT_MODE (new_op1, QImode);
12526 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12527 GET_MODE (XEXP (new_op1, 0))));
12529 /* Make sure that (a) the CCmode we have for the flags is strong
12530 enough for the reversed compare or (b) we have a valid FP compare. */
12531 if (! ix86_comparison_operator (new_op1, VOIDmode))
12536 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12537 (eq:QI (match_operator 1 "ix86_comparison_operator"
12538 [(reg FLAGS_REG) (const_int 0)])
12541 [(set (match_dup 0) (match_dup 1))]
12543 rtx new_op1 = copy_rtx (operands[1]);
12544 operands[1] = new_op1;
12545 PUT_MODE (new_op1, QImode);
12546 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12547 GET_MODE (XEXP (new_op1, 0))));
12549 /* Make sure that (a) the CCmode we have for the flags is strong
12550 enough for the reversed compare or (b) we have a valid FP compare. */
12551 if (! ix86_comparison_operator (new_op1, VOIDmode))
12555 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12556 ;; subsequent logical operations are used to imitate conditional moves.
12557 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12558 ;; it directly. Further holding this value in pseudo register might bring
12559 ;; problem in implicit normalization in spill code.
12560 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12561 ;; instructions after reload by splitting the conditional move patterns.
12563 (define_insn "*sse_setccsf"
12564 [(set (match_operand:SF 0 "register_operand" "=x")
12565 (match_operator:SF 1 "sse_comparison_operator"
12566 [(match_operand:SF 2 "register_operand" "0")
12567 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12568 "TARGET_SSE && reload_completed"
12569 "cmp%D1ss\t{%3, %0|%0, %3}"
12570 [(set_attr "type" "ssecmp")
12571 (set_attr "mode" "SF")])
12573 (define_insn "*sse_setccdf"
12574 [(set (match_operand:DF 0 "register_operand" "=Y")
12575 (match_operator:DF 1 "sse_comparison_operator"
12576 [(match_operand:DF 2 "register_operand" "0")
12577 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12578 "TARGET_SSE2 && reload_completed"
12579 "cmp%D1sd\t{%3, %0|%0, %3}"
12580 [(set_attr "type" "ssecmp")
12581 (set_attr "mode" "DF")])
12583 ;; Basic conditional jump instructions.
12584 ;; We ignore the overflow flag for signed branch instructions.
12586 ;; For all bCOND expanders, also expand the compare or test insn that
12587 ;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
12589 (define_expand "beq"
12591 (if_then_else (match_dup 1)
12592 (label_ref (match_operand 0 "" ""))
12595 "ix86_expand_branch (EQ, operands[0]); DONE;")
12597 (define_expand "bne"
12599 (if_then_else (match_dup 1)
12600 (label_ref (match_operand 0 "" ""))
12603 "ix86_expand_branch (NE, operands[0]); DONE;")
12605 (define_expand "bgt"
12607 (if_then_else (match_dup 1)
12608 (label_ref (match_operand 0 "" ""))
12611 "ix86_expand_branch (GT, operands[0]); DONE;")
12613 (define_expand "bgtu"
12615 (if_then_else (match_dup 1)
12616 (label_ref (match_operand 0 "" ""))
12619 "ix86_expand_branch (GTU, operands[0]); DONE;")
12621 (define_expand "blt"
12623 (if_then_else (match_dup 1)
12624 (label_ref (match_operand 0 "" ""))
12627 "ix86_expand_branch (LT, operands[0]); DONE;")
12629 (define_expand "bltu"
12631 (if_then_else (match_dup 1)
12632 (label_ref (match_operand 0 "" ""))
12635 "ix86_expand_branch (LTU, operands[0]); DONE;")
12637 (define_expand "bge"
12639 (if_then_else (match_dup 1)
12640 (label_ref (match_operand 0 "" ""))
12643 "ix86_expand_branch (GE, operands[0]); DONE;")
12645 (define_expand "bgeu"
12647 (if_then_else (match_dup 1)
12648 (label_ref (match_operand 0 "" ""))
12651 "ix86_expand_branch (GEU, operands[0]); DONE;")
12653 (define_expand "ble"
12655 (if_then_else (match_dup 1)
12656 (label_ref (match_operand 0 "" ""))
12659 "ix86_expand_branch (LE, operands[0]); DONE;")
12661 (define_expand "bleu"
12663 (if_then_else (match_dup 1)
12664 (label_ref (match_operand 0 "" ""))
12667 "ix86_expand_branch (LEU, operands[0]); DONE;")
12669 (define_expand "bunordered"
12671 (if_then_else (match_dup 1)
12672 (label_ref (match_operand 0 "" ""))
12674 "TARGET_80387 || TARGET_SSE"
12675 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12677 (define_expand "bordered"
12679 (if_then_else (match_dup 1)
12680 (label_ref (match_operand 0 "" ""))
12682 "TARGET_80387 || TARGET_SSE"
12683 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12685 (define_expand "buneq"
12687 (if_then_else (match_dup 1)
12688 (label_ref (match_operand 0 "" ""))
12690 "TARGET_80387 || TARGET_SSE"
12691 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12693 (define_expand "bunge"
12695 (if_then_else (match_dup 1)
12696 (label_ref (match_operand 0 "" ""))
12698 "TARGET_80387 || TARGET_SSE"
12699 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12701 (define_expand "bungt"
12703 (if_then_else (match_dup 1)
12704 (label_ref (match_operand 0 "" ""))
12706 "TARGET_80387 || TARGET_SSE"
12707 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12709 (define_expand "bunle"
12711 (if_then_else (match_dup 1)
12712 (label_ref (match_operand 0 "" ""))
12714 "TARGET_80387 || TARGET_SSE"
12715 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12717 (define_expand "bunlt"
12719 (if_then_else (match_dup 1)
12720 (label_ref (match_operand 0 "" ""))
12722 "TARGET_80387 || TARGET_SSE"
12723 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12725 (define_expand "bltgt"
12727 (if_then_else (match_dup 1)
12728 (label_ref (match_operand 0 "" ""))
12730 "TARGET_80387 || TARGET_SSE"
12731 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12733 (define_insn "*jcc_1"
12735 (if_then_else (match_operator 1 "ix86_comparison_operator"
12736 [(reg FLAGS_REG) (const_int 0)])
12737 (label_ref (match_operand 0 "" ""))
12741 [(set_attr "type" "ibr")
12742 (set_attr "modrm" "0")
12743 (set (attr "length")
12744 (if_then_else (and (ge (minus (match_dup 0) (pc))
12746 (lt (minus (match_dup 0) (pc))
12751 (define_insn "*jcc_2"
12753 (if_then_else (match_operator 1 "ix86_comparison_operator"
12754 [(reg FLAGS_REG) (const_int 0)])
12756 (label_ref (match_operand 0 "" ""))))]
12759 [(set_attr "type" "ibr")
12760 (set_attr "modrm" "0")
12761 (set (attr "length")
12762 (if_then_else (and (ge (minus (match_dup 0) (pc))
12764 (lt (minus (match_dup 0) (pc))
12769 ;; In general it is not safe to assume too much about CCmode registers,
12770 ;; so simplify-rtx stops when it sees a second one. Under certain
12771 ;; conditions this is safe on x86, so help combine not create
12779 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
12780 [(reg FLAGS_REG) (const_int 0)])
12782 (label_ref (match_operand 1 "" ""))
12786 (if_then_else (match_dup 0)
12787 (label_ref (match_dup 1))
12790 PUT_MODE (operands[0], VOIDmode);
12795 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
12796 [(reg FLAGS_REG) (const_int 0)])
12798 (label_ref (match_operand 1 "" ""))
12802 (if_then_else (match_dup 0)
12803 (label_ref (match_dup 1))
12806 rtx new_op0 = copy_rtx (operands[0]);
12807 operands[0] = new_op0;
12808 PUT_MODE (new_op0, VOIDmode);
12809 PUT_CODE (new_op0, ix86_reverse_condition (GET_CODE (new_op0),
12810 GET_MODE (XEXP (new_op0, 0))));
12812 /* Make sure that (a) the CCmode we have for the flags is strong
12813 enough for the reversed compare or (b) we have a valid FP compare. */
12814 if (! ix86_comparison_operator (new_op0, VOIDmode))
12818 ;; Define combination compare-and-branch fp compare instructions to use
12819 ;; during early optimization. Splitting the operation apart early makes
12820 ;; for bad code when we want to reverse the operation.
12822 (define_insn "*fp_jcc_1"
12824 (if_then_else (match_operator 0 "comparison_operator"
12825 [(match_operand 1 "register_operand" "f")
12826 (match_operand 2 "register_operand" "f")])
12827 (label_ref (match_operand 3 "" ""))
12829 (clobber (reg:CCFP FPSR_REG))
12830 (clobber (reg:CCFP FLAGS_REG))]
12831 "TARGET_CMOVE && TARGET_80387
12832 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12833 && FLOAT_MODE_P (GET_MODE (operands[1]))
12834 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12835 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12838 (define_insn "*fp_jcc_1_sse"
12840 (if_then_else (match_operator 0 "comparison_operator"
12841 [(match_operand 1 "register_operand" "f#x,x#f")
12842 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12843 (label_ref (match_operand 3 "" ""))
12845 (clobber (reg:CCFP FPSR_REG))
12846 (clobber (reg:CCFP FLAGS_REG))]
12848 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12849 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12850 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12853 (define_insn "*fp_jcc_1_sse_only"
12855 (if_then_else (match_operator 0 "comparison_operator"
12856 [(match_operand 1 "register_operand" "x")
12857 (match_operand 2 "nonimmediate_operand" "xm")])
12858 (label_ref (match_operand 3 "" ""))
12860 (clobber (reg:CCFP FPSR_REG))
12861 (clobber (reg:CCFP FLAGS_REG))]
12862 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12863 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12864 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12867 (define_insn "*fp_jcc_2"
12869 (if_then_else (match_operator 0 "comparison_operator"
12870 [(match_operand 1 "register_operand" "f")
12871 (match_operand 2 "register_operand" "f")])
12873 (label_ref (match_operand 3 "" ""))))
12874 (clobber (reg:CCFP FPSR_REG))
12875 (clobber (reg:CCFP FLAGS_REG))]
12876 "TARGET_CMOVE && TARGET_80387
12877 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12878 && FLOAT_MODE_P (GET_MODE (operands[1]))
12879 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12880 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12883 (define_insn "*fp_jcc_2_sse"
12885 (if_then_else (match_operator 0 "comparison_operator"
12886 [(match_operand 1 "register_operand" "f#x,x#f")
12887 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12889 (label_ref (match_operand 3 "" ""))))
12890 (clobber (reg:CCFP FPSR_REG))
12891 (clobber (reg:CCFP FLAGS_REG))]
12893 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12894 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12895 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12898 (define_insn "*fp_jcc_2_sse_only"
12900 (if_then_else (match_operator 0 "comparison_operator"
12901 [(match_operand 1 "register_operand" "x")
12902 (match_operand 2 "nonimmediate_operand" "xm")])
12904 (label_ref (match_operand 3 "" ""))))
12905 (clobber (reg:CCFP FPSR_REG))
12906 (clobber (reg:CCFP FLAGS_REG))]
12907 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12908 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12909 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12912 (define_insn "*fp_jcc_3"
12914 (if_then_else (match_operator 0 "comparison_operator"
12915 [(match_operand 1 "register_operand" "f")
12916 (match_operand 2 "nonimmediate_operand" "fm")])
12917 (label_ref (match_operand 3 "" ""))
12919 (clobber (reg:CCFP FPSR_REG))
12920 (clobber (reg:CCFP FLAGS_REG))
12921 (clobber (match_scratch:HI 4 "=a"))]
12923 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12924 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12925 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12926 && SELECT_CC_MODE (GET_CODE (operands[0]),
12927 operands[1], operands[2]) == CCFPmode
12928 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12931 (define_insn "*fp_jcc_4"
12933 (if_then_else (match_operator 0 "comparison_operator"
12934 [(match_operand 1 "register_operand" "f")
12935 (match_operand 2 "nonimmediate_operand" "fm")])
12937 (label_ref (match_operand 3 "" ""))))
12938 (clobber (reg:CCFP FPSR_REG))
12939 (clobber (reg:CCFP FLAGS_REG))
12940 (clobber (match_scratch:HI 4 "=a"))]
12942 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12943 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12944 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12945 && SELECT_CC_MODE (GET_CODE (operands[0]),
12946 operands[1], operands[2]) == CCFPmode
12947 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12950 (define_insn "*fp_jcc_5"
12952 (if_then_else (match_operator 0 "comparison_operator"
12953 [(match_operand 1 "register_operand" "f")
12954 (match_operand 2 "register_operand" "f")])
12955 (label_ref (match_operand 3 "" ""))
12957 (clobber (reg:CCFP FPSR_REG))
12958 (clobber (reg:CCFP FLAGS_REG))
12959 (clobber (match_scratch:HI 4 "=a"))]
12961 && FLOAT_MODE_P (GET_MODE (operands[1]))
12962 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12963 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12966 (define_insn "*fp_jcc_6"
12968 (if_then_else (match_operator 0 "comparison_operator"
12969 [(match_operand 1 "register_operand" "f")
12970 (match_operand 2 "register_operand" "f")])
12972 (label_ref (match_operand 3 "" ""))))
12973 (clobber (reg:CCFP FPSR_REG))
12974 (clobber (reg:CCFP FLAGS_REG))
12975 (clobber (match_scratch:HI 4 "=a"))]
12977 && FLOAT_MODE_P (GET_MODE (operands[1]))
12978 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12979 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12982 (define_insn "*fp_jcc_7"
12984 (if_then_else (match_operator 0 "comparison_operator"
12985 [(match_operand 1 "register_operand" "f")
12986 (match_operand 2 "const_double_operand" "C")])
12987 (label_ref (match_operand 3 "" ""))
12989 (clobber (reg:CCFP FPSR_REG))
12990 (clobber (reg:CCFP FLAGS_REG))
12991 (clobber (match_scratch:HI 4 "=a"))]
12993 && FLOAT_MODE_P (GET_MODE (operands[1]))
12994 && operands[2] == CONST0_RTX (GET_MODE (operands[1]))
12995 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12996 && SELECT_CC_MODE (GET_CODE (operands[0]),
12997 operands[1], operands[2]) == CCFPmode
12998 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13001 ;; The order of operands in *fp_jcc_8 is forced by combine in
13002 ;; simplify_comparison () function. Float operator is treated as RTX_OBJ
13003 ;; with a precedence over other operators and is always put in the first
13004 ;; place. Swap condition and operands to match ficom instruction.
13006 (define_insn "*fp_jcc_8"
13008 (if_then_else (match_operator 0 "comparison_operator"
13009 [(match_operator 1 "float_operator"
13010 [(match_operand:SI 2 "nonimmediate_operand" "m,?r")])
13011 (match_operand 3 "register_operand" "f,f")])
13012 (label_ref (match_operand 4 "" ""))
13014 (clobber (reg:CCFP FPSR_REG))
13015 (clobber (reg:CCFP FLAGS_REG))
13016 (clobber (match_scratch:HI 5 "=a,a"))]
13017 "TARGET_80387 && TARGET_USE_FIOP
13018 && FLOAT_MODE_P (GET_MODE (operands[3]))
13019 && GET_MODE (operands[1]) == GET_MODE (operands[3])
13020 && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
13021 && ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
13022 && ix86_fp_jump_nontrivial_p (swap_condition (GET_CODE (operands[0])))"
13027 (if_then_else (match_operator 0 "comparison_operator"
13028 [(match_operand 1 "register_operand" "")
13029 (match_operand 2 "nonimmediate_operand" "")])
13030 (match_operand 3 "" "")
13031 (match_operand 4 "" "")))
13032 (clobber (reg:CCFP FPSR_REG))
13033 (clobber (reg:CCFP FLAGS_REG))]
13037 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13038 operands[3], operands[4], NULL_RTX, NULL_RTX);
13044 (if_then_else (match_operator 0 "comparison_operator"
13045 [(match_operand 1 "register_operand" "")
13046 (match_operand 2 "general_operand" "")])
13047 (match_operand 3 "" "")
13048 (match_operand 4 "" "")))
13049 (clobber (reg:CCFP FPSR_REG))
13050 (clobber (reg:CCFP FLAGS_REG))
13051 (clobber (match_scratch:HI 5 "=a"))]
13055 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13056 operands[3], operands[4], operands[5], NULL_RTX);
13062 (if_then_else (match_operator 0 "comparison_operator"
13063 [(match_operator 1 "float_operator"
13064 [(match_operand:SI 2 "memory_operand" "")])
13065 (match_operand 3 "register_operand" "")])
13066 (match_operand 4 "" "")
13067 (match_operand 5 "" "")))
13068 (clobber (reg:CCFP FPSR_REG))
13069 (clobber (reg:CCFP FLAGS_REG))
13070 (clobber (match_scratch:HI 6 "=a"))]
13074 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);
13075 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
13076 operands[3], operands[7],
13077 operands[4], operands[5], operands[6], NULL_RTX);
13081 ;; %%% Kill this when reload knows how to do it.
13084 (if_then_else (match_operator 0 "comparison_operator"
13085 [(match_operator 1 "float_operator"
13086 [(match_operand:SI 2 "register_operand" "")])
13087 (match_operand 3 "register_operand" "")])
13088 (match_operand 4 "" "")
13089 (match_operand 5 "" "")))
13090 (clobber (reg:CCFP FPSR_REG))
13091 (clobber (reg:CCFP FLAGS_REG))
13092 (clobber (match_scratch:HI 6 "=a"))]
13096 operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
13097 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);
13098 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
13099 operands[3], operands[7],
13100 operands[4], operands[5], operands[6], operands[2]);
13104 ;; Unconditional and other jump instructions
13106 (define_insn "jump"
13108 (label_ref (match_operand 0 "" "")))]
13111 [(set_attr "type" "ibr")
13112 (set (attr "length")
13113 (if_then_else (and (ge (minus (match_dup 0) (pc))
13115 (lt (minus (match_dup 0) (pc))
13119 (set_attr "modrm" "0")])
13121 (define_expand "indirect_jump"
13122 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13126 (define_insn "*indirect_jump"
13127 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13130 [(set_attr "type" "ibr")
13131 (set_attr "length_immediate" "0")])
13133 (define_insn "*indirect_jump_rtx64"
13134 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13137 [(set_attr "type" "ibr")
13138 (set_attr "length_immediate" "0")])
13140 (define_expand "tablejump"
13141 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13142 (use (label_ref (match_operand 1 "" "")))])]
13145 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13146 relative. Convert the relative address to an absolute address. */
13150 enum rtx_code code;
13156 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13158 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13162 op1 = pic_offset_table_rtx;
13167 op0 = pic_offset_table_rtx;
13171 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13176 (define_insn "*tablejump_1"
13177 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13178 (use (label_ref (match_operand 1 "" "")))]
13181 [(set_attr "type" "ibr")
13182 (set_attr "length_immediate" "0")])
13184 (define_insn "*tablejump_1_rtx64"
13185 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13186 (use (label_ref (match_operand 1 "" "")))]
13189 [(set_attr "type" "ibr")
13190 (set_attr "length_immediate" "0")])
13192 ;; Loop instruction
13194 ;; This is all complicated by the fact that since this is a jump insn
13195 ;; we must handle our own reloads.
13197 (define_expand "doloop_end"
13198 [(use (match_operand 0 "" "")) ; loop pseudo
13199 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13200 (use (match_operand 2 "" "")) ; max iterations
13201 (use (match_operand 3 "" "")) ; loop level
13202 (use (match_operand 4 "" ""))] ; label
13203 "!TARGET_64BIT && TARGET_USE_LOOP"
13206 /* Only use cloop on innermost loops. */
13207 if (INTVAL (operands[3]) > 1)
13209 if (GET_MODE (operands[0]) != SImode)
13211 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13216 (define_insn "doloop_end_internal"
13218 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13220 (label_ref (match_operand 0 "" ""))
13222 (set (match_operand:SI 2 "nonimmediate_operand" "=1,1,*m*r")
13223 (plus:SI (match_dup 1)
13225 (clobber (match_scratch:SI 3 "=X,X,r"))
13226 (clobber (reg:CC FLAGS_REG))]
13227 "!TARGET_64BIT && TARGET_USE_LOOP
13228 && (reload_in_progress || reload_completed
13229 || register_operand (operands[2], VOIDmode))"
13231 if (which_alternative != 0)
13233 if (get_attr_length (insn) == 2)
13234 return "%+loop\t%l0";
13236 return "dec{l}\t%1\;%+jne\t%l0";
13238 [(set (attr "length")
13239 (if_then_else (and (eq_attr "alternative" "0")
13240 (and (ge (minus (match_dup 0) (pc))
13242 (lt (minus (match_dup 0) (pc))
13246 ;; We don't know the type before shorten branches. Optimistically expect
13247 ;; the loop instruction to match.
13248 (set (attr "type") (const_string "ibr"))])
13252 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13254 (match_operand 0 "" "")
13257 (plus:SI (match_dup 1)
13259 (clobber (match_scratch:SI 2 ""))
13260 (clobber (reg:CC FLAGS_REG))]
13261 "!TARGET_64BIT && TARGET_USE_LOOP
13262 && reload_completed
13263 && REGNO (operands[1]) != 2"
13264 [(parallel [(set (reg:CCZ FLAGS_REG)
13265 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13267 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13268 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13275 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13277 (match_operand 0 "" "")
13279 (set (match_operand:SI 2 "nonimmediate_operand" "")
13280 (plus:SI (match_dup 1)
13282 (clobber (match_scratch:SI 3 ""))
13283 (clobber (reg:CC FLAGS_REG))]
13284 "!TARGET_64BIT && TARGET_USE_LOOP
13285 && reload_completed
13286 && (! REG_P (operands[2])
13287 || ! rtx_equal_p (operands[1], operands[2]))"
13288 [(set (match_dup 3) (match_dup 1))
13289 (parallel [(set (reg:CCZ FLAGS_REG)
13290 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13292 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13293 (set (match_dup 2) (match_dup 3))
13294 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13299 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13302 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
13303 (set (match_operand:QI 1 "register_operand" "")
13304 (match_operator:QI 2 "ix86_comparison_operator"
13305 [(reg FLAGS_REG) (const_int 0)]))
13306 (set (match_operand 3 "q_regs_operand" "")
13307 (zero_extend (match_dup 1)))]
13308 "(peep2_reg_dead_p (3, operands[1])
13309 || operands_match_p (operands[1], operands[3]))
13310 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13311 [(set (match_dup 4) (match_dup 0))
13312 (set (strict_low_part (match_dup 5))
13315 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13316 operands[5] = gen_lowpart (QImode, operands[3]);
13317 ix86_expand_clear (operands[3]);
13320 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13323 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
13324 (set (match_operand:QI 1 "register_operand" "")
13325 (match_operator:QI 2 "ix86_comparison_operator"
13326 [(reg FLAGS_REG) (const_int 0)]))
13327 (parallel [(set (match_operand 3 "q_regs_operand" "")
13328 (zero_extend (match_dup 1)))
13329 (clobber (reg:CC FLAGS_REG))])]
13330 "(peep2_reg_dead_p (3, operands[1])
13331 || operands_match_p (operands[1], operands[3]))
13332 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13333 [(set (match_dup 4) (match_dup 0))
13334 (set (strict_low_part (match_dup 5))
13337 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13338 operands[5] = gen_lowpart (QImode, operands[3]);
13339 ix86_expand_clear (operands[3]);
13342 ;; Call instructions.
13344 ;; The predicates normally associated with named expanders are not properly
13345 ;; checked for calls. This is a bug in the generic code, but it isn't that
13346 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13348 ;; Call subroutine returning no value.
13350 (define_expand "call_pop"
13351 [(parallel [(call (match_operand:QI 0 "" "")
13352 (match_operand:SI 1 "" ""))
13353 (set (reg:SI SP_REG)
13354 (plus:SI (reg:SI SP_REG)
13355 (match_operand:SI 3 "" "")))])]
13358 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13362 (define_insn "*call_pop_0"
13363 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13364 (match_operand:SI 1 "" ""))
13365 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13366 (match_operand:SI 2 "immediate_operand" "")))]
13369 if (SIBLING_CALL_P (insn))
13372 return "call\t%P0";
13374 [(set_attr "type" "call")])
13376 (define_insn "*call_pop_1"
13377 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13378 (match_operand:SI 1 "" ""))
13379 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13380 (match_operand:SI 2 "immediate_operand" "i")))]
13383 if (constant_call_address_operand (operands[0], Pmode))
13385 if (SIBLING_CALL_P (insn))
13388 return "call\t%P0";
13390 if (SIBLING_CALL_P (insn))
13393 return "call\t%A0";
13395 [(set_attr "type" "call")])
13397 (define_expand "call"
13398 [(call (match_operand:QI 0 "" "")
13399 (match_operand 1 "" ""))
13400 (use (match_operand 2 "" ""))]
13403 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13407 (define_expand "sibcall"
13408 [(call (match_operand:QI 0 "" "")
13409 (match_operand 1 "" ""))
13410 (use (match_operand 2 "" ""))]
13413 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13417 (define_insn "*call_0"
13418 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13419 (match_operand 1 "" ""))]
13422 if (SIBLING_CALL_P (insn))
13425 return "call\t%P0";
13427 [(set_attr "type" "call")])
13429 (define_insn "*call_1"
13430 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13431 (match_operand 1 "" ""))]
13432 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13434 if (constant_call_address_operand (operands[0], Pmode))
13435 return "call\t%P0";
13436 return "call\t%A0";
13438 [(set_attr "type" "call")])
13440 (define_insn "*sibcall_1"
13441 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13442 (match_operand 1 "" ""))]
13443 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13445 if (constant_call_address_operand (operands[0], Pmode))
13449 [(set_attr "type" "call")])
13451 (define_insn "*call_1_rex64"
13452 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13453 (match_operand 1 "" ""))]
13454 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13456 if (constant_call_address_operand (operands[0], Pmode))
13457 return "call\t%P0";
13458 return "call\t%A0";
13460 [(set_attr "type" "call")])
13462 (define_insn "*sibcall_1_rex64"
13463 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13464 (match_operand 1 "" ""))]
13465 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13467 [(set_attr "type" "call")])
13469 (define_insn "*sibcall_1_rex64_v"
13470 [(call (mem:QI (reg:DI 40))
13471 (match_operand 0 "" ""))]
13472 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13474 [(set_attr "type" "call")])
13477 ;; Call subroutine, returning value in operand 0
13479 (define_expand "call_value_pop"
13480 [(parallel [(set (match_operand 0 "" "")
13481 (call (match_operand:QI 1 "" "")
13482 (match_operand:SI 2 "" "")))
13483 (set (reg:SI SP_REG)
13484 (plus:SI (reg:SI SP_REG)
13485 (match_operand:SI 4 "" "")))])]
13488 ix86_expand_call (operands[0], operands[1], operands[2],
13489 operands[3], operands[4], 0);
13493 (define_expand "call_value"
13494 [(set (match_operand 0 "" "")
13495 (call (match_operand:QI 1 "" "")
13496 (match_operand:SI 2 "" "")))
13497 (use (match_operand:SI 3 "" ""))]
13498 ;; Operand 2 not used on the i386.
13501 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13505 (define_expand "sibcall_value"
13506 [(set (match_operand 0 "" "")
13507 (call (match_operand:QI 1 "" "")
13508 (match_operand:SI 2 "" "")))
13509 (use (match_operand:SI 3 "" ""))]
13510 ;; Operand 2 not used on the i386.
13513 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13517 ;; Call subroutine returning any type.
13519 (define_expand "untyped_call"
13520 [(parallel [(call (match_operand 0 "" "")
13522 (match_operand 1 "" "")
13523 (match_operand 2 "" "")])]
13528 /* In order to give reg-stack an easier job in validating two
13529 coprocessor registers as containing a possible return value,
13530 simply pretend the untyped call returns a complex long double
13533 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13534 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13535 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13538 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13540 rtx set = XVECEXP (operands[2], 0, i);
13541 emit_move_insn (SET_DEST (set), SET_SRC (set));
13544 /* The optimizer does not know that the call sets the function value
13545 registers we stored in the result block. We avoid problems by
13546 claiming that all hard registers are used and clobbered at this
13548 emit_insn (gen_blockage (const0_rtx));
13553 ;; Prologue and epilogue instructions
13555 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13556 ;; all of memory. This blocks insns from being moved across this point.
13558 (define_insn "blockage"
13559 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13562 [(set_attr "length" "0")])
13564 ;; Insn emitted into the body of a function to return from a function.
13565 ;; This is only done if the function's epilogue is known to be simple.
13566 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13568 (define_expand "return"
13570 "ix86_can_use_return_insn_p ()"
13572 if (current_function_pops_args)
13574 rtx popc = GEN_INT (current_function_pops_args);
13575 emit_jump_insn (gen_return_pop_internal (popc));
13580 (define_insn "return_internal"
13584 [(set_attr "length" "1")
13585 (set_attr "length_immediate" "0")
13586 (set_attr "modrm" "0")])
13588 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
13589 ;; instruction Athlon and K8 have.
13591 (define_insn "return_internal_long"
13593 (unspec [(const_int 0)] UNSPEC_REP)]
13596 [(set_attr "length" "1")
13597 (set_attr "length_immediate" "0")
13598 (set_attr "prefix_rep" "1")
13599 (set_attr "modrm" "0")])
13601 (define_insn "return_pop_internal"
13603 (use (match_operand:SI 0 "const_int_operand" ""))]
13606 [(set_attr "length" "3")
13607 (set_attr "length_immediate" "2")
13608 (set_attr "modrm" "0")])
13610 (define_insn "return_indirect_internal"
13612 (use (match_operand:SI 0 "register_operand" "r"))]
13615 [(set_attr "type" "ibr")
13616 (set_attr "length_immediate" "0")])
13622 [(set_attr "length" "1")
13623 (set_attr "length_immediate" "0")
13624 (set_attr "modrm" "0")])
13626 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
13627 ;; branch prediction penalty for the third jump in a 16-byte
13630 (define_insn "align"
13631 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
13634 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
13635 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
13637 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
13638 The align insn is used to avoid 3 jump instructions in the row to improve
13639 branch prediction and the benefits hardly outweight the cost of extra 8
13640 nops on the average inserted by full alignment pseudo operation. */
13644 [(set_attr "length" "16")])
13646 (define_expand "prologue"
13649 "ix86_expand_prologue (); DONE;")
13651 (define_insn "set_got"
13652 [(set (match_operand:SI 0 "register_operand" "=r")
13653 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13654 (clobber (reg:CC FLAGS_REG))]
13656 { return output_set_got (operands[0]); }
13657 [(set_attr "type" "multi")
13658 (set_attr "length" "12")])
13660 (define_expand "epilogue"
13663 "ix86_expand_epilogue (1); DONE;")
13665 (define_expand "sibcall_epilogue"
13668 "ix86_expand_epilogue (0); DONE;")
13670 (define_expand "eh_return"
13671 [(use (match_operand 0 "register_operand" ""))]
13674 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13676 /* Tricky bit: we write the address of the handler to which we will
13677 be returning into someone else's stack frame, one word below the
13678 stack address we wish to restore. */
13679 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13680 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13681 tmp = gen_rtx_MEM (Pmode, tmp);
13682 emit_move_insn (tmp, ra);
13684 if (Pmode == SImode)
13685 emit_jump_insn (gen_eh_return_si (sa));
13687 emit_jump_insn (gen_eh_return_di (sa));
13692 (define_insn_and_split "eh_return_si"
13694 (unspec [(match_operand:SI 0 "register_operand" "c")]
13695 UNSPEC_EH_RETURN))]
13700 "ix86_expand_epilogue (2); DONE;")
13702 (define_insn_and_split "eh_return_di"
13704 (unspec [(match_operand:DI 0 "register_operand" "c")]
13705 UNSPEC_EH_RETURN))]
13710 "ix86_expand_epilogue (2); DONE;")
13712 (define_insn "leave"
13713 [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
13714 (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
13715 (clobber (mem:BLK (scratch)))]
13718 [(set_attr "type" "leave")])
13720 (define_insn "leave_rex64"
13721 [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
13722 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
13723 (clobber (mem:BLK (scratch)))]
13726 [(set_attr "type" "leave")])
13728 (define_expand "ffssi2"
13730 [(set (match_operand:SI 0 "register_operand" "")
13731 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
13732 (clobber (match_scratch:SI 2 ""))
13733 (clobber (reg:CC FLAGS_REG))])]
13737 (define_insn_and_split "*ffs_cmove"
13738 [(set (match_operand:SI 0 "register_operand" "=r")
13739 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13740 (clobber (match_scratch:SI 2 "=&r"))
13741 (clobber (reg:CC FLAGS_REG))]
13744 "&& reload_completed"
13745 [(set (match_dup 2) (const_int -1))
13746 (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13747 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13748 (set (match_dup 0) (if_then_else:SI
13749 (eq (reg:CCZ FLAGS_REG) (const_int 0))
13752 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13753 (clobber (reg:CC FLAGS_REG))])]
13756 (define_insn_and_split "*ffs_no_cmove"
13757 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
13758 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13759 (clobber (match_scratch:SI 2 "=&q"))
13760 (clobber (reg:CC FLAGS_REG))]
13764 [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13765 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13766 (set (strict_low_part (match_dup 3))
13767 (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
13768 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
13769 (clobber (reg:CC FLAGS_REG))])
13770 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
13771 (clobber (reg:CC FLAGS_REG))])
13772 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13773 (clobber (reg:CC FLAGS_REG))])]
13775 operands[3] = gen_lowpart (QImode, operands[2]);
13776 ix86_expand_clear (operands[2]);
13779 (define_insn "*ffssi_1"
13780 [(set (reg:CCZ FLAGS_REG)
13781 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13783 (set (match_operand:SI 0 "register_operand" "=r")
13784 (ctz:SI (match_dup 1)))]
13786 "bsf{l}\t{%1, %0|%0, %1}"
13787 [(set_attr "prefix_0f" "1")])
13789 (define_expand "ffsdi2"
13791 [(set (match_operand:DI 0 "register_operand" "")
13792 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
13793 (clobber (match_scratch:DI 2 ""))
13794 (clobber (reg:CC FLAGS_REG))])]
13795 "TARGET_64BIT && TARGET_CMOVE"
13798 (define_insn_and_split "*ffs_rex64"
13799 [(set (match_operand:DI 0 "register_operand" "=r")
13800 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
13801 (clobber (match_scratch:DI 2 "=&r"))
13802 (clobber (reg:CC FLAGS_REG))]
13803 "TARGET_64BIT && TARGET_CMOVE"
13805 "&& reload_completed"
13806 [(set (match_dup 2) (const_int -1))
13807 (parallel [(set (reg:CCZ FLAGS_REG)
13808 (compare:CCZ (match_dup 1) (const_int 0)))
13809 (set (match_dup 0) (ctz:DI (match_dup 1)))])
13810 (set (match_dup 0) (if_then_else:DI
13811 (eq (reg:CCZ FLAGS_REG) (const_int 0))
13814 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
13815 (clobber (reg:CC FLAGS_REG))])]
13818 (define_insn "*ffsdi_1"
13819 [(set (reg:CCZ FLAGS_REG)
13820 (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
13822 (set (match_operand:DI 0 "register_operand" "=r")
13823 (ctz:DI (match_dup 1)))]
13825 "bsf{q}\t{%1, %0|%0, %1}"
13826 [(set_attr "prefix_0f" "1")])
13828 (define_insn "ctzsi2"
13829 [(set (match_operand:SI 0 "register_operand" "=r")
13830 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13831 (clobber (reg:CC FLAGS_REG))]
13833 "bsf{l}\t{%1, %0|%0, %1}"
13834 [(set_attr "prefix_0f" "1")])
13836 (define_insn "ctzdi2"
13837 [(set (match_operand:DI 0 "register_operand" "=r")
13838 (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
13839 (clobber (reg:CC FLAGS_REG))]
13841 "bsf{q}\t{%1, %0|%0, %1}"
13842 [(set_attr "prefix_0f" "1")])
13844 (define_expand "clzsi2"
13846 [(set (match_operand:SI 0 "register_operand" "")
13847 (minus:SI (const_int 31)
13848 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
13849 (clobber (reg:CC FLAGS_REG))])
13851 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
13852 (clobber (reg:CC FLAGS_REG))])]
13856 (define_insn "*bsr"
13857 [(set (match_operand:SI 0 "register_operand" "=r")
13858 (minus:SI (const_int 31)
13859 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
13860 (clobber (reg:CC FLAGS_REG))]
13862 "bsr{l}\t{%1, %0|%0, %1}"
13863 [(set_attr "prefix_0f" "1")])
13865 (define_expand "clzdi2"
13867 [(set (match_operand:DI 0 "register_operand" "")
13868 (minus:DI (const_int 63)
13869 (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
13870 (clobber (reg:CC FLAGS_REG))])
13872 [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
13873 (clobber (reg:CC FLAGS_REG))])]
13877 (define_insn "*bsr_rex64"
13878 [(set (match_operand:DI 0 "register_operand" "=r")
13879 (minus:DI (const_int 63)
13880 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
13881 (clobber (reg:CC FLAGS_REG))]
13883 "bsr{q}\t{%1, %0|%0, %1}"
13884 [(set_attr "prefix_0f" "1")])
13886 ;; Thread-local storage patterns for ELF.
13888 ;; Note that these code sequences must appear exactly as shown
13889 ;; in order to allow linker relaxation.
13891 (define_insn "*tls_global_dynamic_32_gnu"
13892 [(set (match_operand:SI 0 "register_operand" "=a")
13893 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13894 (match_operand:SI 2 "tls_symbolic_operand" "")
13895 (match_operand:SI 3 "call_insn_operand" "")]
13897 (clobber (match_scratch:SI 4 "=d"))
13898 (clobber (match_scratch:SI 5 "=c"))
13899 (clobber (reg:CC FLAGS_REG))]
13900 "!TARGET_64BIT && TARGET_GNU_TLS"
13901 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
13902 [(set_attr "type" "multi")
13903 (set_attr "length" "12")])
13905 (define_insn "*tls_global_dynamic_32_sun"
13906 [(set (match_operand:SI 0 "register_operand" "=a")
13907 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13908 (match_operand:SI 2 "tls_symbolic_operand" "")
13909 (match_operand:SI 3 "call_insn_operand" "")]
13911 (clobber (match_scratch:SI 4 "=d"))
13912 (clobber (match_scratch:SI 5 "=c"))
13913 (clobber (reg:CC FLAGS_REG))]
13914 "!TARGET_64BIT && TARGET_SUN_TLS"
13915 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
13916 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
13917 [(set_attr "type" "multi")
13918 (set_attr "length" "14")])
13920 (define_expand "tls_global_dynamic_32"
13921 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13924 (match_operand:SI 1 "tls_symbolic_operand" "")
13927 (clobber (match_scratch:SI 4 ""))
13928 (clobber (match_scratch:SI 5 ""))
13929 (clobber (reg:CC FLAGS_REG))])]
13933 operands[2] = pic_offset_table_rtx;
13936 operands[2] = gen_reg_rtx (Pmode);
13937 emit_insn (gen_set_got (operands[2]));
13939 operands[3] = ix86_tls_get_addr ();
13942 (define_insn "*tls_global_dynamic_64"
13943 [(set (match_operand:DI 0 "register_operand" "=a")
13944 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
13945 (match_operand:DI 3 "" "")))
13946 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
13949 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
13950 [(set_attr "type" "multi")
13951 (set_attr "length" "16")])
13953 (define_expand "tls_global_dynamic_64"
13954 [(parallel [(set (match_operand:DI 0 "register_operand" "")
13955 (call (mem:QI (match_dup 2)) (const_int 0)))
13956 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
13960 operands[2] = ix86_tls_get_addr ();
13963 (define_insn "*tls_local_dynamic_base_32_gnu"
13964 [(set (match_operand:SI 0 "register_operand" "=a")
13965 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13966 (match_operand:SI 2 "call_insn_operand" "")]
13967 UNSPEC_TLS_LD_BASE))
13968 (clobber (match_scratch:SI 3 "=d"))
13969 (clobber (match_scratch:SI 4 "=c"))
13970 (clobber (reg:CC FLAGS_REG))]
13971 "!TARGET_64BIT && TARGET_GNU_TLS"
13972 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
13973 [(set_attr "type" "multi")
13974 (set_attr "length" "11")])
13976 (define_insn "*tls_local_dynamic_base_32_sun"
13977 [(set (match_operand:SI 0 "register_operand" "=a")
13978 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13979 (match_operand:SI 2 "call_insn_operand" "")]
13980 UNSPEC_TLS_LD_BASE))
13981 (clobber (match_scratch:SI 3 "=d"))
13982 (clobber (match_scratch:SI 4 "=c"))
13983 (clobber (reg:CC FLAGS_REG))]
13984 "!TARGET_64BIT && TARGET_SUN_TLS"
13985 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
13986 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
13987 [(set_attr "type" "multi")
13988 (set_attr "length" "13")])
13990 (define_expand "tls_local_dynamic_base_32"
13991 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13992 (unspec:SI [(match_dup 1) (match_dup 2)]
13993 UNSPEC_TLS_LD_BASE))
13994 (clobber (match_scratch:SI 3 ""))
13995 (clobber (match_scratch:SI 4 ""))
13996 (clobber (reg:CC FLAGS_REG))])]
14000 operands[1] = pic_offset_table_rtx;
14003 operands[1] = gen_reg_rtx (Pmode);
14004 emit_insn (gen_set_got (operands[1]));
14006 operands[2] = ix86_tls_get_addr ();
14009 (define_insn "*tls_local_dynamic_base_64"
14010 [(set (match_operand:DI 0 "register_operand" "=a")
14011 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14012 (match_operand:DI 2 "" "")))
14013 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14015 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14016 [(set_attr "type" "multi")
14017 (set_attr "length" "12")])
14019 (define_expand "tls_local_dynamic_base_64"
14020 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14021 (call (mem:QI (match_dup 1)) (const_int 0)))
14022 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14025 operands[1] = ix86_tls_get_addr ();
14028 ;; Local dynamic of a single variable is a lose. Show combine how
14029 ;; to convert that back to global dynamic.
14031 (define_insn_and_split "*tls_local_dynamic_32_once"
14032 [(set (match_operand:SI 0 "register_operand" "=a")
14033 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14034 (match_operand:SI 2 "call_insn_operand" "")]
14035 UNSPEC_TLS_LD_BASE)
14036 (const:SI (unspec:SI
14037 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14039 (clobber (match_scratch:SI 4 "=d"))
14040 (clobber (match_scratch:SI 5 "=c"))
14041 (clobber (reg:CC FLAGS_REG))]
14045 [(parallel [(set (match_dup 0)
14046 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14048 (clobber (match_dup 4))
14049 (clobber (match_dup 5))
14050 (clobber (reg:CC FLAGS_REG))])]
14053 ;; Load and add the thread base pointer from %gs:0.
14055 (define_insn "*load_tp_si"
14056 [(set (match_operand:SI 0 "register_operand" "=r")
14057 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14059 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14060 [(set_attr "type" "imov")
14061 (set_attr "modrm" "0")
14062 (set_attr "length" "7")
14063 (set_attr "memory" "load")
14064 (set_attr "imm_disp" "false")])
14066 (define_insn "*add_tp_si"
14067 [(set (match_operand:SI 0 "register_operand" "=r")
14068 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14069 (match_operand:SI 1 "register_operand" "0")))
14070 (clobber (reg:CC FLAGS_REG))]
14072 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14073 [(set_attr "type" "alu")
14074 (set_attr "modrm" "0")
14075 (set_attr "length" "7")
14076 (set_attr "memory" "load")
14077 (set_attr "imm_disp" "false")])
14079 (define_insn "*load_tp_di"
14080 [(set (match_operand:DI 0 "register_operand" "=r")
14081 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14083 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14084 [(set_attr "type" "imov")
14085 (set_attr "modrm" "0")
14086 (set_attr "length" "7")
14087 (set_attr "memory" "load")
14088 (set_attr "imm_disp" "false")])
14090 (define_insn "*add_tp_di"
14091 [(set (match_operand:DI 0 "register_operand" "=r")
14092 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14093 (match_operand:DI 1 "register_operand" "0")))
14094 (clobber (reg:CC FLAGS_REG))]
14096 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14097 [(set_attr "type" "alu")
14098 (set_attr "modrm" "0")
14099 (set_attr "length" "7")
14100 (set_attr "memory" "load")
14101 (set_attr "imm_disp" "false")])
14103 ;; These patterns match the binary 387 instructions for addM3, subM3,
14104 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14105 ;; SFmode. The first is the normal insn, the second the same insn but
14106 ;; with one operand a conversion, and the third the same insn but with
14107 ;; the other operand a conversion. The conversion may be SFmode or
14108 ;; SImode if the target mode DFmode, but only SImode if the target mode
14111 ;; Gcc is slightly more smart about handling normal two address instructions
14112 ;; so use special patterns for add and mull.
14113 (define_insn "*fop_sf_comm_nosse"
14114 [(set (match_operand:SF 0 "register_operand" "=f")
14115 (match_operator:SF 3 "binary_fp_operator"
14116 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14117 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14118 "TARGET_80387 && !TARGET_SSE_MATH
14119 && COMMUTATIVE_ARITH_P (operands[3])
14120 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14121 "* return output_387_binary_op (insn, operands);"
14122 [(set (attr "type")
14123 (if_then_else (match_operand:SF 3 "mult_operator" "")
14124 (const_string "fmul")
14125 (const_string "fop")))
14126 (set_attr "mode" "SF")])
14128 (define_insn "*fop_sf_comm"
14129 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14130 (match_operator:SF 3 "binary_fp_operator"
14131 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14132 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14133 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14134 && COMMUTATIVE_ARITH_P (operands[3])
14135 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14136 "* return output_387_binary_op (insn, operands);"
14137 [(set (attr "type")
14138 (if_then_else (eq_attr "alternative" "1")
14139 (if_then_else (match_operand:SF 3 "mult_operator" "")
14140 (const_string "ssemul")
14141 (const_string "sseadd"))
14142 (if_then_else (match_operand:SF 3 "mult_operator" "")
14143 (const_string "fmul")
14144 (const_string "fop"))))
14145 (set_attr "mode" "SF")])
14147 (define_insn "*fop_sf_comm_sse"
14148 [(set (match_operand:SF 0 "register_operand" "=x")
14149 (match_operator:SF 3 "binary_fp_operator"
14150 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14151 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14152 "TARGET_SSE_MATH && COMMUTATIVE_ARITH_P (operands[3])
14153 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14154 "* return output_387_binary_op (insn, operands);"
14155 [(set (attr "type")
14156 (if_then_else (match_operand:SF 3 "mult_operator" "")
14157 (const_string "ssemul")
14158 (const_string "sseadd")))
14159 (set_attr "mode" "SF")])
14161 (define_insn "*fop_df_comm_nosse"
14162 [(set (match_operand:DF 0 "register_operand" "=f")
14163 (match_operator:DF 3 "binary_fp_operator"
14164 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14165 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14166 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14167 && COMMUTATIVE_ARITH_P (operands[3])
14168 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14169 "* return output_387_binary_op (insn, operands);"
14170 [(set (attr "type")
14171 (if_then_else (match_operand:SF 3 "mult_operator" "")
14172 (const_string "fmul")
14173 (const_string "fop")))
14174 (set_attr "mode" "DF")])
14176 (define_insn "*fop_df_comm"
14177 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14178 (match_operator:DF 3 "binary_fp_operator"
14179 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14180 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14181 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14182 && COMMUTATIVE_ARITH_P (operands[3])
14183 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14184 "* return output_387_binary_op (insn, operands);"
14185 [(set (attr "type")
14186 (if_then_else (eq_attr "alternative" "1")
14187 (if_then_else (match_operand:SF 3 "mult_operator" "")
14188 (const_string "ssemul")
14189 (const_string "sseadd"))
14190 (if_then_else (match_operand:SF 3 "mult_operator" "")
14191 (const_string "fmul")
14192 (const_string "fop"))))
14193 (set_attr "mode" "DF")])
14195 (define_insn "*fop_df_comm_sse"
14196 [(set (match_operand:DF 0 "register_operand" "=Y")
14197 (match_operator:DF 3 "binary_fp_operator"
14198 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14199 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14200 "TARGET_SSE2 && TARGET_SSE_MATH
14201 && COMMUTATIVE_ARITH_P (operands[3])
14202 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14203 "* return output_387_binary_op (insn, operands);"
14204 [(set (attr "type")
14205 (if_then_else (match_operand:SF 3 "mult_operator" "")
14206 (const_string "ssemul")
14207 (const_string "sseadd")))
14208 (set_attr "mode" "DF")])
14210 (define_insn "*fop_xf_comm"
14211 [(set (match_operand:XF 0 "register_operand" "=f")
14212 (match_operator:XF 3 "binary_fp_operator"
14213 [(match_operand:XF 1 "register_operand" "%0")
14214 (match_operand:XF 2 "register_operand" "f")]))]
14216 && COMMUTATIVE_ARITH_P (operands[3])"
14217 "* return output_387_binary_op (insn, operands);"
14218 [(set (attr "type")
14219 (if_then_else (match_operand:XF 3 "mult_operator" "")
14220 (const_string "fmul")
14221 (const_string "fop")))
14222 (set_attr "mode" "XF")])
14224 (define_insn "*fop_sf_1_nosse"
14225 [(set (match_operand:SF 0 "register_operand" "=f,f")
14226 (match_operator:SF 3 "binary_fp_operator"
14227 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14228 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14229 "TARGET_80387 && !TARGET_SSE_MATH
14230 && !COMMUTATIVE_ARITH_P (operands[3])
14231 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14232 "* return output_387_binary_op (insn, operands);"
14233 [(set (attr "type")
14234 (cond [(match_operand:SF 3 "mult_operator" "")
14235 (const_string "fmul")
14236 (match_operand:SF 3 "div_operator" "")
14237 (const_string "fdiv")
14239 (const_string "fop")))
14240 (set_attr "mode" "SF")])
14242 (define_insn "*fop_sf_1"
14243 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14244 (match_operator:SF 3 "binary_fp_operator"
14245 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14246 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14247 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14248 && !COMMUTATIVE_ARITH_P (operands[3])
14249 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14250 "* return output_387_binary_op (insn, operands);"
14251 [(set (attr "type")
14252 (cond [(and (eq_attr "alternative" "2")
14253 (match_operand:SF 3 "mult_operator" ""))
14254 (const_string "ssemul")
14255 (and (eq_attr "alternative" "2")
14256 (match_operand:SF 3 "div_operator" ""))
14257 (const_string "ssediv")
14258 (eq_attr "alternative" "2")
14259 (const_string "sseadd")
14260 (match_operand:SF 3 "mult_operator" "")
14261 (const_string "fmul")
14262 (match_operand:SF 3 "div_operator" "")
14263 (const_string "fdiv")
14265 (const_string "fop")))
14266 (set_attr "mode" "SF")])
14268 (define_insn "*fop_sf_1_sse"
14269 [(set (match_operand:SF 0 "register_operand" "=x")
14270 (match_operator:SF 3 "binary_fp_operator"
14271 [(match_operand:SF 1 "register_operand" "0")
14272 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14274 && !COMMUTATIVE_ARITH_P (operands[3])"
14275 "* return output_387_binary_op (insn, operands);"
14276 [(set (attr "type")
14277 (cond [(match_operand:SF 3 "mult_operator" "")
14278 (const_string "ssemul")
14279 (match_operand:SF 3 "div_operator" "")
14280 (const_string "ssediv")
14282 (const_string "sseadd")))
14283 (set_attr "mode" "SF")])
14285 ;; ??? Add SSE splitters for these!
14286 (define_insn "*fop_sf_2"
14287 [(set (match_operand:SF 0 "register_operand" "=f,f")
14288 (match_operator:SF 3 "binary_fp_operator"
14289 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14290 (match_operand:SF 2 "register_operand" "0,0")]))]
14291 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14292 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14293 [(set (attr "type")
14294 (cond [(match_operand:SF 3 "mult_operator" "")
14295 (const_string "fmul")
14296 (match_operand:SF 3 "div_operator" "")
14297 (const_string "fdiv")
14299 (const_string "fop")))
14300 (set_attr "fp_int_src" "true")
14301 (set_attr "mode" "SI")])
14303 (define_insn "*fop_sf_3"
14304 [(set (match_operand:SF 0 "register_operand" "=f,f")
14305 (match_operator:SF 3 "binary_fp_operator"
14306 [(match_operand:SF 1 "register_operand" "0,0")
14307 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14308 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14309 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14310 [(set (attr "type")
14311 (cond [(match_operand:SF 3 "mult_operator" "")
14312 (const_string "fmul")
14313 (match_operand:SF 3 "div_operator" "")
14314 (const_string "fdiv")
14316 (const_string "fop")))
14317 (set_attr "fp_int_src" "true")
14318 (set_attr "mode" "SI")])
14320 (define_insn "*fop_df_1_nosse"
14321 [(set (match_operand:DF 0 "register_operand" "=f,f")
14322 (match_operator:DF 3 "binary_fp_operator"
14323 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14324 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14325 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14326 && !COMMUTATIVE_ARITH_P (operands[3])
14327 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14328 "* return output_387_binary_op (insn, operands);"
14329 [(set (attr "type")
14330 (cond [(match_operand:DF 3 "mult_operator" "")
14331 (const_string "fmul")
14332 (match_operand:DF 3 "div_operator" "")
14333 (const_string "fdiv")
14335 (const_string "fop")))
14336 (set_attr "mode" "DF")])
14339 (define_insn "*fop_df_1"
14340 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14341 (match_operator:DF 3 "binary_fp_operator"
14342 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14343 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14344 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14345 && !COMMUTATIVE_ARITH_P (operands[3])
14346 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14347 "* return output_387_binary_op (insn, operands);"
14348 [(set (attr "type")
14349 (cond [(and (eq_attr "alternative" "2")
14350 (match_operand:SF 3 "mult_operator" ""))
14351 (const_string "ssemul")
14352 (and (eq_attr "alternative" "2")
14353 (match_operand:SF 3 "div_operator" ""))
14354 (const_string "ssediv")
14355 (eq_attr "alternative" "2")
14356 (const_string "sseadd")
14357 (match_operand:DF 3 "mult_operator" "")
14358 (const_string "fmul")
14359 (match_operand:DF 3 "div_operator" "")
14360 (const_string "fdiv")
14362 (const_string "fop")))
14363 (set_attr "mode" "DF")])
14365 (define_insn "*fop_df_1_sse"
14366 [(set (match_operand:DF 0 "register_operand" "=Y")
14367 (match_operator:DF 3 "binary_fp_operator"
14368 [(match_operand:DF 1 "register_operand" "0")
14369 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14370 "TARGET_SSE2 && TARGET_SSE_MATH
14371 && !COMMUTATIVE_ARITH_P (operands[3])"
14372 "* return output_387_binary_op (insn, operands);"
14373 [(set_attr "mode" "DF")
14375 (cond [(match_operand:SF 3 "mult_operator" "")
14376 (const_string "ssemul")
14377 (match_operand:SF 3 "div_operator" "")
14378 (const_string "ssediv")
14380 (const_string "sseadd")))])
14382 ;; ??? Add SSE splitters for these!
14383 (define_insn "*fop_df_2"
14384 [(set (match_operand:DF 0 "register_operand" "=f,f")
14385 (match_operator:DF 3 "binary_fp_operator"
14386 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14387 (match_operand:DF 2 "register_operand" "0,0")]))]
14388 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14389 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14390 [(set (attr "type")
14391 (cond [(match_operand:DF 3 "mult_operator" "")
14392 (const_string "fmul")
14393 (match_operand:DF 3 "div_operator" "")
14394 (const_string "fdiv")
14396 (const_string "fop")))
14397 (set_attr "fp_int_src" "true")
14398 (set_attr "mode" "SI")])
14400 (define_insn "*fop_df_3"
14401 [(set (match_operand:DF 0 "register_operand" "=f,f")
14402 (match_operator:DF 3 "binary_fp_operator"
14403 [(match_operand:DF 1 "register_operand" "0,0")
14404 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14405 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14406 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14407 [(set (attr "type")
14408 (cond [(match_operand:DF 3 "mult_operator" "")
14409 (const_string "fmul")
14410 (match_operand:DF 3 "div_operator" "")
14411 (const_string "fdiv")
14413 (const_string "fop")))
14414 (set_attr "fp_int_src" "true")
14415 (set_attr "mode" "SI")])
14417 (define_insn "*fop_df_4"
14418 [(set (match_operand:DF 0 "register_operand" "=f,f")
14419 (match_operator:DF 3 "binary_fp_operator"
14420 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14421 (match_operand:DF 2 "register_operand" "0,f")]))]
14422 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14423 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14424 "* return output_387_binary_op (insn, operands);"
14425 [(set (attr "type")
14426 (cond [(match_operand:DF 3 "mult_operator" "")
14427 (const_string "fmul")
14428 (match_operand:DF 3 "div_operator" "")
14429 (const_string "fdiv")
14431 (const_string "fop")))
14432 (set_attr "mode" "SF")])
14434 (define_insn "*fop_df_5"
14435 [(set (match_operand:DF 0 "register_operand" "=f,f")
14436 (match_operator:DF 3 "binary_fp_operator"
14437 [(match_operand:DF 1 "register_operand" "0,f")
14439 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14440 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14441 "* return output_387_binary_op (insn, operands);"
14442 [(set (attr "type")
14443 (cond [(match_operand:DF 3 "mult_operator" "")
14444 (const_string "fmul")
14445 (match_operand:DF 3 "div_operator" "")
14446 (const_string "fdiv")
14448 (const_string "fop")))
14449 (set_attr "mode" "SF")])
14451 (define_insn "*fop_df_6"
14452 [(set (match_operand:DF 0 "register_operand" "=f,f")
14453 (match_operator:DF 3 "binary_fp_operator"
14455 (match_operand:SF 1 "register_operand" "0,f"))
14457 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14458 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14459 "* return output_387_binary_op (insn, operands);"
14460 [(set (attr "type")
14461 (cond [(match_operand:DF 3 "mult_operator" "")
14462 (const_string "fmul")
14463 (match_operand:DF 3 "div_operator" "")
14464 (const_string "fdiv")
14466 (const_string "fop")))
14467 (set_attr "mode" "SF")])
14469 (define_insn "*fop_xf_1"
14470 [(set (match_operand:XF 0 "register_operand" "=f,f")
14471 (match_operator:XF 3 "binary_fp_operator"
14472 [(match_operand:XF 1 "register_operand" "0,f")
14473 (match_operand:XF 2 "register_operand" "f,0")]))]
14475 && !COMMUTATIVE_ARITH_P (operands[3])"
14476 "* return output_387_binary_op (insn, operands);"
14477 [(set (attr "type")
14478 (cond [(match_operand:XF 3 "mult_operator" "")
14479 (const_string "fmul")
14480 (match_operand:XF 3 "div_operator" "")
14481 (const_string "fdiv")
14483 (const_string "fop")))
14484 (set_attr "mode" "XF")])
14486 (define_insn "*fop_xf_2"
14487 [(set (match_operand:XF 0 "register_operand" "=f,f")
14488 (match_operator:XF 3 "binary_fp_operator"
14489 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14490 (match_operand:XF 2 "register_operand" "0,0")]))]
14491 "TARGET_80387 && TARGET_USE_FIOP"
14492 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14493 [(set (attr "type")
14494 (cond [(match_operand:XF 3 "mult_operator" "")
14495 (const_string "fmul")
14496 (match_operand:XF 3 "div_operator" "")
14497 (const_string "fdiv")
14499 (const_string "fop")))
14500 (set_attr "fp_int_src" "true")
14501 (set_attr "mode" "SI")])
14503 (define_insn "*fop_xf_3"
14504 [(set (match_operand:XF 0 "register_operand" "=f,f")
14505 (match_operator:XF 3 "binary_fp_operator"
14506 [(match_operand:XF 1 "register_operand" "0,0")
14507 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14508 "TARGET_80387 && TARGET_USE_FIOP"
14509 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14510 [(set (attr "type")
14511 (cond [(match_operand:XF 3 "mult_operator" "")
14512 (const_string "fmul")
14513 (match_operand:XF 3 "div_operator" "")
14514 (const_string "fdiv")
14516 (const_string "fop")))
14517 (set_attr "fp_int_src" "true")
14518 (set_attr "mode" "SI")])
14520 (define_insn "*fop_xf_4"
14521 [(set (match_operand:XF 0 "register_operand" "=f,f")
14522 (match_operator:XF 3 "binary_fp_operator"
14523 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14524 (match_operand:XF 2 "register_operand" "0,f")]))]
14526 "* return output_387_binary_op (insn, operands);"
14527 [(set (attr "type")
14528 (cond [(match_operand:XF 3 "mult_operator" "")
14529 (const_string "fmul")
14530 (match_operand:XF 3 "div_operator" "")
14531 (const_string "fdiv")
14533 (const_string "fop")))
14534 (set_attr "mode" "SF")])
14536 (define_insn "*fop_xf_5"
14537 [(set (match_operand:XF 0 "register_operand" "=f,f")
14538 (match_operator:XF 3 "binary_fp_operator"
14539 [(match_operand:XF 1 "register_operand" "0,f")
14541 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14543 "* return output_387_binary_op (insn, operands);"
14544 [(set (attr "type")
14545 (cond [(match_operand:XF 3 "mult_operator" "")
14546 (const_string "fmul")
14547 (match_operand:XF 3 "div_operator" "")
14548 (const_string "fdiv")
14550 (const_string "fop")))
14551 (set_attr "mode" "SF")])
14553 (define_insn "*fop_xf_6"
14554 [(set (match_operand:XF 0 "register_operand" "=f,f")
14555 (match_operator:XF 3 "binary_fp_operator"
14557 (match_operand 1 "register_operand" "0,f"))
14559 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14561 "* return output_387_binary_op (insn, operands);"
14562 [(set (attr "type")
14563 (cond [(match_operand:XF 3 "mult_operator" "")
14564 (const_string "fmul")
14565 (match_operand:XF 3 "div_operator" "")
14566 (const_string "fdiv")
14568 (const_string "fop")))
14569 (set_attr "mode" "SF")])
14572 [(set (match_operand 0 "register_operand" "")
14573 (match_operator 3 "binary_fp_operator"
14574 [(float (match_operand:SI 1 "register_operand" ""))
14575 (match_operand 2 "register_operand" "")]))]
14576 "TARGET_80387 && reload_completed
14577 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14580 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14581 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14582 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14583 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14584 GET_MODE (operands[3]),
14587 ix86_free_from_memory (GET_MODE (operands[1]));
14592 [(set (match_operand 0 "register_operand" "")
14593 (match_operator 3 "binary_fp_operator"
14594 [(match_operand 1 "register_operand" "")
14595 (float (match_operand:SI 2 "register_operand" ""))]))]
14596 "TARGET_80387 && reload_completed
14597 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14600 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14601 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14602 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14603 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14604 GET_MODE (operands[3]),
14607 ix86_free_from_memory (GET_MODE (operands[2]));
14611 ;; FPU special functions.
14613 (define_expand "sqrtsf2"
14614 [(set (match_operand:SF 0 "register_operand" "")
14615 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14616 "TARGET_USE_FANCY_MATH_387 || TARGET_SSE_MATH"
14618 if (!TARGET_SSE_MATH)
14619 operands[1] = force_reg (SFmode, operands[1]);
14622 (define_insn "sqrtsf2_1"
14623 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14624 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14625 "TARGET_USE_FANCY_MATH_387
14626 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14629 sqrtss\t{%1, %0|%0, %1}"
14630 [(set_attr "type" "fpspc,sse")
14631 (set_attr "mode" "SF,SF")
14632 (set_attr "athlon_decode" "direct,*")])
14634 (define_insn "sqrtsf2_1_sse_only"
14635 [(set (match_operand:SF 0 "register_operand" "=x")
14636 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14637 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14638 "sqrtss\t{%1, %0|%0, %1}"
14639 [(set_attr "type" "sse")
14640 (set_attr "mode" "SF")
14641 (set_attr "athlon_decode" "*")])
14643 (define_insn "sqrtsf2_i387"
14644 [(set (match_operand:SF 0 "register_operand" "=f")
14645 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14646 "TARGET_USE_FANCY_MATH_387
14647 && !TARGET_SSE_MATH"
14649 [(set_attr "type" "fpspc")
14650 (set_attr "mode" "SF")
14651 (set_attr "athlon_decode" "direct")])
14653 (define_expand "sqrtdf2"
14654 [(set (match_operand:DF 0 "register_operand" "")
14655 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14656 "TARGET_USE_FANCY_MATH_387
14657 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14659 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
14660 operands[1] = force_reg (DFmode, operands[1]);
14663 (define_insn "sqrtdf2_1"
14664 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14665 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14666 "TARGET_USE_FANCY_MATH_387
14667 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14670 sqrtsd\t{%1, %0|%0, %1}"
14671 [(set_attr "type" "fpspc,sse")
14672 (set_attr "mode" "DF,DF")
14673 (set_attr "athlon_decode" "direct,*")])
14675 (define_insn "sqrtdf2_1_sse_only"
14676 [(set (match_operand:DF 0 "register_operand" "=Y")
14677 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14678 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14679 "sqrtsd\t{%1, %0|%0, %1}"
14680 [(set_attr "type" "sse")
14681 (set_attr "mode" "DF")
14682 (set_attr "athlon_decode" "*")])
14684 (define_insn "sqrtdf2_i387"
14685 [(set (match_operand:DF 0 "register_operand" "=f")
14686 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14687 "TARGET_USE_FANCY_MATH_387
14688 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
14690 [(set_attr "type" "fpspc")
14691 (set_attr "mode" "DF")
14692 (set_attr "athlon_decode" "direct")])
14694 (define_insn "*sqrtextendsfdf2"
14695 [(set (match_operand:DF 0 "register_operand" "=f")
14696 (sqrt:DF (float_extend:DF
14697 (match_operand:SF 1 "register_operand" "0"))))]
14698 "TARGET_USE_FANCY_MATH_387
14699 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14701 [(set_attr "type" "fpspc")
14702 (set_attr "mode" "DF")
14703 (set_attr "athlon_decode" "direct")])
14705 (define_insn "sqrtxf2"
14706 [(set (match_operand:XF 0 "register_operand" "=f")
14707 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14708 "TARGET_USE_FANCY_MATH_387
14709 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14711 [(set_attr "type" "fpspc")
14712 (set_attr "mode" "XF")
14713 (set_attr "athlon_decode" "direct")])
14715 (define_insn "*sqrtextenddfxf2"
14716 [(set (match_operand:XF 0 "register_operand" "=f")
14717 (sqrt:XF (float_extend:XF
14718 (match_operand:DF 1 "register_operand" "0"))))]
14719 "TARGET_USE_FANCY_MATH_387"
14721 [(set_attr "type" "fpspc")
14722 (set_attr "mode" "XF")
14723 (set_attr "athlon_decode" "direct")])
14725 (define_insn "*sqrtextendsfxf2"
14726 [(set (match_operand:XF 0 "register_operand" "=f")
14727 (sqrt:XF (float_extend:XF
14728 (match_operand:SF 1 "register_operand" "0"))))]
14729 "TARGET_USE_FANCY_MATH_387"
14731 [(set_attr "type" "fpspc")
14732 (set_attr "mode" "XF")
14733 (set_attr "athlon_decode" "direct")])
14735 (define_insn "fpremxf4"
14736 [(set (match_operand:XF 0 "register_operand" "=f")
14737 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14738 (match_operand:XF 3 "register_operand" "1")]
14740 (set (match_operand:XF 1 "register_operand" "=u")
14741 (unspec:XF [(match_dup 2) (match_dup 3)]
14743 (set (reg:CCFP FPSR_REG)
14744 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
14745 "TARGET_USE_FANCY_MATH_387
14746 && flag_unsafe_math_optimizations"
14748 [(set_attr "type" "fpspc")
14749 (set_attr "mode" "XF")])
14751 (define_expand "fmodsf3"
14752 [(use (match_operand:SF 0 "register_operand" ""))
14753 (use (match_operand:SF 1 "register_operand" ""))
14754 (use (match_operand:SF 2 "register_operand" ""))]
14755 "TARGET_USE_FANCY_MATH_387
14756 && flag_unsafe_math_optimizations"
14758 rtx label = gen_label_rtx ();
14760 rtx op1 = gen_reg_rtx (XFmode);
14761 rtx op2 = gen_reg_rtx (XFmode);
14763 emit_insn(gen_extendsfxf2 (op1, operands[1]));
14764 emit_insn(gen_extendsfxf2 (op2, operands[2]));
14766 emit_label (label);
14768 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
14769 ix86_emit_fp_unordered_jump (label);
14771 emit_insn (gen_truncxfsf2_noop (operands[0], op1));
14775 (define_expand "fmoddf3"
14776 [(use (match_operand:DF 0 "register_operand" ""))
14777 (use (match_operand:DF 1 "register_operand" ""))
14778 (use (match_operand:DF 2 "register_operand" ""))]
14779 "TARGET_USE_FANCY_MATH_387
14780 && flag_unsafe_math_optimizations"
14782 rtx label = gen_label_rtx ();
14784 rtx op1 = gen_reg_rtx (XFmode);
14785 rtx op2 = gen_reg_rtx (XFmode);
14787 emit_insn (gen_extenddfxf2 (op1, operands[1]));
14788 emit_insn (gen_extenddfxf2 (op2, operands[2]));
14790 emit_label (label);
14792 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
14793 ix86_emit_fp_unordered_jump (label);
14795 emit_insn (gen_truncxfdf2_noop (operands[0], op1));
14799 (define_expand "fmodxf3"
14800 [(use (match_operand:XF 0 "register_operand" ""))
14801 (use (match_operand:XF 1 "register_operand" ""))
14802 (use (match_operand:XF 2 "register_operand" ""))]
14803 "TARGET_USE_FANCY_MATH_387
14804 && flag_unsafe_math_optimizations"
14806 rtx label = gen_label_rtx ();
14808 emit_label (label);
14810 emit_insn (gen_fpremxf4 (operands[1], operands[2],
14811 operands[1], operands[2]));
14812 ix86_emit_fp_unordered_jump (label);
14814 emit_move_insn (operands[0], operands[1]);
14818 (define_insn "fprem1xf4"
14819 [(set (match_operand:XF 0 "register_operand" "=f")
14820 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14821 (match_operand:XF 3 "register_operand" "1")]
14823 (set (match_operand:XF 1 "register_operand" "=u")
14824 (unspec:XF [(match_dup 2) (match_dup 3)]
14826 (set (reg:CCFP FPSR_REG)
14827 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
14828 "TARGET_USE_FANCY_MATH_387
14829 && flag_unsafe_math_optimizations"
14831 [(set_attr "type" "fpspc")
14832 (set_attr "mode" "XF")])
14834 (define_expand "dremsf3"
14835 [(use (match_operand:SF 0 "register_operand" ""))
14836 (use (match_operand:SF 1 "register_operand" ""))
14837 (use (match_operand:SF 2 "register_operand" ""))]
14838 "TARGET_USE_FANCY_MATH_387
14839 && flag_unsafe_math_optimizations"
14841 rtx label = gen_label_rtx ();
14843 rtx op1 = gen_reg_rtx (XFmode);
14844 rtx op2 = gen_reg_rtx (XFmode);
14846 emit_insn(gen_extendsfxf2 (op1, operands[1]));
14847 emit_insn(gen_extendsfxf2 (op2, operands[2]));
14849 emit_label (label);
14851 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
14852 ix86_emit_fp_unordered_jump (label);
14854 emit_insn (gen_truncxfsf2_noop (operands[0], op1));
14858 (define_expand "dremdf3"
14859 [(use (match_operand:DF 0 "register_operand" ""))
14860 (use (match_operand:DF 1 "register_operand" ""))
14861 (use (match_operand:DF 2 "register_operand" ""))]
14862 "TARGET_USE_FANCY_MATH_387
14863 && flag_unsafe_math_optimizations"
14865 rtx label = gen_label_rtx ();
14867 rtx op1 = gen_reg_rtx (XFmode);
14868 rtx op2 = gen_reg_rtx (XFmode);
14870 emit_insn (gen_extenddfxf2 (op1, operands[1]));
14871 emit_insn (gen_extenddfxf2 (op2, operands[2]));
14873 emit_label (label);
14875 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
14876 ix86_emit_fp_unordered_jump (label);
14878 emit_insn (gen_truncxfdf2_noop (operands[0], op1));
14882 (define_expand "dremxf3"
14883 [(use (match_operand:XF 0 "register_operand" ""))
14884 (use (match_operand:XF 1 "register_operand" ""))
14885 (use (match_operand:XF 2 "register_operand" ""))]
14886 "TARGET_USE_FANCY_MATH_387
14887 && flag_unsafe_math_optimizations"
14889 rtx label = gen_label_rtx ();
14891 emit_label (label);
14893 emit_insn (gen_fprem1xf4 (operands[1], operands[2],
14894 operands[1], operands[2]));
14895 ix86_emit_fp_unordered_jump (label);
14897 emit_move_insn (operands[0], operands[1]);
14901 (define_insn "*sindf2"
14902 [(set (match_operand:DF 0 "register_operand" "=f")
14903 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14904 "TARGET_USE_FANCY_MATH_387
14905 && flag_unsafe_math_optimizations"
14907 [(set_attr "type" "fpspc")
14908 (set_attr "mode" "DF")])
14910 (define_insn "*sinsf2"
14911 [(set (match_operand:SF 0 "register_operand" "=f")
14912 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14913 "TARGET_USE_FANCY_MATH_387
14914 && flag_unsafe_math_optimizations"
14916 [(set_attr "type" "fpspc")
14917 (set_attr "mode" "SF")])
14919 (define_insn "*sinextendsfdf2"
14920 [(set (match_operand:DF 0 "register_operand" "=f")
14921 (unspec:DF [(float_extend:DF
14922 (match_operand:SF 1 "register_operand" "0"))]
14924 "TARGET_USE_FANCY_MATH_387
14925 && flag_unsafe_math_optimizations"
14927 [(set_attr "type" "fpspc")
14928 (set_attr "mode" "DF")])
14930 (define_insn "*sinxf2"
14931 [(set (match_operand:XF 0 "register_operand" "=f")
14932 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14933 "TARGET_USE_FANCY_MATH_387
14934 && flag_unsafe_math_optimizations"
14936 [(set_attr "type" "fpspc")
14937 (set_attr "mode" "XF")])
14939 (define_insn "*cosdf2"
14940 [(set (match_operand:DF 0 "register_operand" "=f")
14941 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14942 "TARGET_USE_FANCY_MATH_387
14943 && flag_unsafe_math_optimizations"
14945 [(set_attr "type" "fpspc")
14946 (set_attr "mode" "DF")])
14948 (define_insn "*cossf2"
14949 [(set (match_operand:SF 0 "register_operand" "=f")
14950 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14951 "TARGET_USE_FANCY_MATH_387
14952 && flag_unsafe_math_optimizations"
14954 [(set_attr "type" "fpspc")
14955 (set_attr "mode" "SF")])
14957 (define_insn "*cosextendsfdf2"
14958 [(set (match_operand:DF 0 "register_operand" "=f")
14959 (unspec:DF [(float_extend:DF
14960 (match_operand:SF 1 "register_operand" "0"))]
14962 "TARGET_USE_FANCY_MATH_387
14963 && flag_unsafe_math_optimizations"
14965 [(set_attr "type" "fpspc")
14966 (set_attr "mode" "DF")])
14968 (define_insn "*cosxf2"
14969 [(set (match_operand:XF 0 "register_operand" "=f")
14970 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14971 "TARGET_USE_FANCY_MATH_387
14972 && flag_unsafe_math_optimizations"
14974 [(set_attr "type" "fpspc")
14975 (set_attr "mode" "XF")])
14977 ;; With sincos pattern defined, sin and cos builtin function will be
14978 ;; expanded to sincos pattern with one of its outputs left unused.
14979 ;; Cse pass will detected, if two sincos patterns can be combined,
14980 ;; otherwise sincos pattern will be split back to sin or cos pattern,
14981 ;; depending on the unused output.
14983 (define_insn "sincosdf3"
14984 [(set (match_operand:DF 0 "register_operand" "=f")
14985 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
14986 UNSPEC_SINCOS_COS))
14987 (set (match_operand:DF 1 "register_operand" "=u")
14988 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
14989 "TARGET_USE_FANCY_MATH_387
14990 && flag_unsafe_math_optimizations"
14992 [(set_attr "type" "fpspc")
14993 (set_attr "mode" "DF")])
14996 [(set (match_operand:DF 0 "register_operand" "")
14997 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
14998 UNSPEC_SINCOS_COS))
14999 (set (match_operand:DF 1 "register_operand" "")
15000 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15001 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15002 && !reload_completed && !reload_in_progress"
15003 [(set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_SIN))]
15007 [(set (match_operand:DF 0 "register_operand" "")
15008 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15009 UNSPEC_SINCOS_COS))
15010 (set (match_operand:DF 1 "register_operand" "")
15011 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15012 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15013 && !reload_completed && !reload_in_progress"
15014 [(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_COS))]
15017 (define_insn "sincossf3"
15018 [(set (match_operand:SF 0 "register_operand" "=f")
15019 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15020 UNSPEC_SINCOS_COS))
15021 (set (match_operand:SF 1 "register_operand" "=u")
15022 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15023 "TARGET_USE_FANCY_MATH_387
15024 && flag_unsafe_math_optimizations"
15026 [(set_attr "type" "fpspc")
15027 (set_attr "mode" "SF")])
15030 [(set (match_operand:SF 0 "register_operand" "")
15031 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15032 UNSPEC_SINCOS_COS))
15033 (set (match_operand:SF 1 "register_operand" "")
15034 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15035 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15036 && !reload_completed && !reload_in_progress"
15037 [(set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_SIN))]
15041 [(set (match_operand:SF 0 "register_operand" "")
15042 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15043 UNSPEC_SINCOS_COS))
15044 (set (match_operand:SF 1 "register_operand" "")
15045 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15046 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15047 && !reload_completed && !reload_in_progress"
15048 [(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_COS))]
15051 (define_insn "*sincosextendsfdf3"
15052 [(set (match_operand:DF 0 "register_operand" "=f")
15053 (unspec:DF [(float_extend:DF
15054 (match_operand:SF 2 "register_operand" "0"))]
15055 UNSPEC_SINCOS_COS))
15056 (set (match_operand:DF 1 "register_operand" "=u")
15057 (unspec:DF [(float_extend:DF
15058 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15059 "TARGET_USE_FANCY_MATH_387
15060 && flag_unsafe_math_optimizations"
15062 [(set_attr "type" "fpspc")
15063 (set_attr "mode" "DF")])
15066 [(set (match_operand:DF 0 "register_operand" "")
15067 (unspec:DF [(float_extend:DF
15068 (match_operand:SF 2 "register_operand" ""))]
15069 UNSPEC_SINCOS_COS))
15070 (set (match_operand:DF 1 "register_operand" "")
15071 (unspec:DF [(float_extend:DF
15072 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15073 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15074 && !reload_completed && !reload_in_progress"
15075 [(set (match_dup 1) (unspec:DF [(float_extend:DF
15076 (match_dup 2))] UNSPEC_SIN))]
15080 [(set (match_operand:DF 0 "register_operand" "")
15081 (unspec:DF [(float_extend:DF
15082 (match_operand:SF 2 "register_operand" ""))]
15083 UNSPEC_SINCOS_COS))
15084 (set (match_operand:DF 1 "register_operand" "")
15085 (unspec:DF [(float_extend:DF
15086 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15087 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15088 && !reload_completed && !reload_in_progress"
15089 [(set (match_dup 0) (unspec:DF [(float_extend:DF
15090 (match_dup 2))] UNSPEC_COS))]
15093 (define_insn "sincosxf3"
15094 [(set (match_operand:XF 0 "register_operand" "=f")
15095 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15096 UNSPEC_SINCOS_COS))
15097 (set (match_operand:XF 1 "register_operand" "=u")
15098 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15099 "TARGET_USE_FANCY_MATH_387
15100 && flag_unsafe_math_optimizations"
15102 [(set_attr "type" "fpspc")
15103 (set_attr "mode" "XF")])
15106 [(set (match_operand:XF 0 "register_operand" "")
15107 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15108 UNSPEC_SINCOS_COS))
15109 (set (match_operand:XF 1 "register_operand" "")
15110 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15111 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15112 && !reload_completed && !reload_in_progress"
15113 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
15117 [(set (match_operand:XF 0 "register_operand" "")
15118 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15119 UNSPEC_SINCOS_COS))
15120 (set (match_operand:XF 1 "register_operand" "")
15121 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15122 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15123 && !reload_completed && !reload_in_progress"
15124 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
15127 (define_insn "*tandf3_1"
15128 [(set (match_operand:DF 0 "register_operand" "=f")
15129 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15131 (set (match_operand:DF 1 "register_operand" "=u")
15132 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
15133 "TARGET_USE_FANCY_MATH_387
15134 && flag_unsafe_math_optimizations"
15136 [(set_attr "type" "fpspc")
15137 (set_attr "mode" "DF")])
15139 ;; optimize sequence: fptan
15142 ;; into fptan insn.
15145 [(parallel[(set (match_operand:DF 0 "register_operand" "")
15146 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15148 (set (match_operand:DF 1 "register_operand" "")
15149 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])
15151 (match_operand:DF 3 "immediate_operand" ""))]
15152 "standard_80387_constant_p (operands[3]) == 2"
15153 [(parallel[(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_TAN_ONE))
15154 (set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15157 (define_expand "tandf2"
15158 [(parallel [(set (match_dup 2)
15159 (unspec:DF [(match_operand:DF 1 "register_operand" "")]
15161 (set (match_operand:DF 0 "register_operand" "")
15162 (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15163 "TARGET_USE_FANCY_MATH_387
15164 && flag_unsafe_math_optimizations"
15166 operands[2] = gen_reg_rtx (DFmode);
15169 (define_insn "*tansf3_1"
15170 [(set (match_operand:SF 0 "register_operand" "=f")
15171 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15173 (set (match_operand:SF 1 "register_operand" "=u")
15174 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
15175 "TARGET_USE_FANCY_MATH_387
15176 && flag_unsafe_math_optimizations"
15178 [(set_attr "type" "fpspc")
15179 (set_attr "mode" "SF")])
15181 ;; optimize sequence: fptan
15184 ;; into fptan insn.
15187 [(parallel[(set (match_operand:SF 0 "register_operand" "")
15188 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15190 (set (match_operand:SF 1 "register_operand" "")
15191 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])
15193 (match_operand:SF 3 "immediate_operand" ""))]
15194 "standard_80387_constant_p (operands[3]) == 2"
15195 [(parallel[(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_TAN_ONE))
15196 (set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15199 (define_expand "tansf2"
15200 [(parallel [(set (match_dup 2)
15201 (unspec:SF [(match_operand:SF 1 "register_operand" "")]
15203 (set (match_operand:SF 0 "register_operand" "")
15204 (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15205 "TARGET_USE_FANCY_MATH_387
15206 && flag_unsafe_math_optimizations"
15208 operands[2] = gen_reg_rtx (SFmode);
15211 (define_insn "*tanxf3_1"
15212 [(set (match_operand:XF 0 "register_operand" "=f")
15213 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15215 (set (match_operand:XF 1 "register_operand" "=u")
15216 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
15217 "TARGET_USE_FANCY_MATH_387
15218 && flag_unsafe_math_optimizations"
15220 [(set_attr "type" "fpspc")
15221 (set_attr "mode" "XF")])
15223 ;; optimize sequence: fptan
15226 ;; into fptan insn.
15229 [(parallel[(set (match_operand:XF 0 "register_operand" "")
15230 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15232 (set (match_operand:XF 1 "register_operand" "")
15233 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])
15235 (match_operand:XF 3 "immediate_operand" ""))]
15236 "standard_80387_constant_p (operands[3]) == 2"
15237 [(parallel[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_TAN_ONE))
15238 (set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15241 (define_expand "tanxf2"
15242 [(parallel [(set (match_dup 2)
15243 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15245 (set (match_operand:XF 0 "register_operand" "")
15246 (unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15247 "TARGET_USE_FANCY_MATH_387
15248 && flag_unsafe_math_optimizations"
15250 operands[2] = gen_reg_rtx (XFmode);
15253 (define_insn "atan2df3_1"
15254 [(set (match_operand:DF 0 "register_operand" "=f")
15255 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15256 (match_operand:DF 1 "register_operand" "u")]
15258 (clobber (match_scratch:DF 3 "=1"))]
15259 "TARGET_USE_FANCY_MATH_387
15260 && flag_unsafe_math_optimizations"
15262 [(set_attr "type" "fpspc")
15263 (set_attr "mode" "DF")])
15265 (define_expand "atan2df3"
15266 [(use (match_operand:DF 0 "register_operand" "=f"))
15267 (use (match_operand:DF 2 "register_operand" "0"))
15268 (use (match_operand:DF 1 "register_operand" "u"))]
15269 "TARGET_USE_FANCY_MATH_387
15270 && flag_unsafe_math_optimizations"
15272 rtx copy = gen_reg_rtx (DFmode);
15273 emit_move_insn (copy, operands[1]);
15274 emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
15278 (define_expand "atandf2"
15279 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15280 (unspec:DF [(match_dup 2)
15281 (match_operand:DF 1 "register_operand" "")]
15283 (clobber (match_scratch:DF 3 ""))])]
15284 "TARGET_USE_FANCY_MATH_387
15285 && flag_unsafe_math_optimizations"
15287 operands[2] = gen_reg_rtx (DFmode);
15288 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15291 (define_insn "atan2sf3_1"
15292 [(set (match_operand:SF 0 "register_operand" "=f")
15293 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15294 (match_operand:SF 1 "register_operand" "u")]
15296 (clobber (match_scratch:SF 3 "=1"))]
15297 "TARGET_USE_FANCY_MATH_387
15298 && flag_unsafe_math_optimizations"
15300 [(set_attr "type" "fpspc")
15301 (set_attr "mode" "SF")])
15303 (define_expand "atan2sf3"
15304 [(use (match_operand:SF 0 "register_operand" "=f"))
15305 (use (match_operand:SF 2 "register_operand" "0"))
15306 (use (match_operand:SF 1 "register_operand" "u"))]
15307 "TARGET_USE_FANCY_MATH_387
15308 && flag_unsafe_math_optimizations"
15310 rtx copy = gen_reg_rtx (SFmode);
15311 emit_move_insn (copy, operands[1]);
15312 emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
15316 (define_expand "atansf2"
15317 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15318 (unspec:SF [(match_dup 2)
15319 (match_operand:SF 1 "register_operand" "")]
15321 (clobber (match_scratch:SF 3 ""))])]
15322 "TARGET_USE_FANCY_MATH_387
15323 && flag_unsafe_math_optimizations"
15325 operands[2] = gen_reg_rtx (SFmode);
15326 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15329 (define_insn "atan2xf3_1"
15330 [(set (match_operand:XF 0 "register_operand" "=f")
15331 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15332 (match_operand:XF 1 "register_operand" "u")]
15334 (clobber (match_scratch:XF 3 "=1"))]
15335 "TARGET_USE_FANCY_MATH_387
15336 && flag_unsafe_math_optimizations"
15338 [(set_attr "type" "fpspc")
15339 (set_attr "mode" "XF")])
15341 (define_expand "atan2xf3"
15342 [(use (match_operand:XF 0 "register_operand" "=f"))
15343 (use (match_operand:XF 2 "register_operand" "0"))
15344 (use (match_operand:XF 1 "register_operand" "u"))]
15345 "TARGET_USE_FANCY_MATH_387
15346 && flag_unsafe_math_optimizations"
15348 rtx copy = gen_reg_rtx (XFmode);
15349 emit_move_insn (copy, operands[1]);
15350 emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
15354 (define_expand "atanxf2"
15355 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15356 (unspec:XF [(match_dup 2)
15357 (match_operand:XF 1 "register_operand" "")]
15359 (clobber (match_scratch:XF 3 ""))])]
15360 "TARGET_USE_FANCY_MATH_387
15361 && flag_unsafe_math_optimizations"
15363 operands[2] = gen_reg_rtx (XFmode);
15364 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15367 (define_expand "asindf2"
15368 [(set (match_dup 2)
15369 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15370 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15371 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15372 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15373 (parallel [(set (match_dup 7)
15374 (unspec:XF [(match_dup 6) (match_dup 2)]
15376 (clobber (match_scratch:XF 8 ""))])
15377 (set (match_operand:DF 0 "register_operand" "")
15378 (float_truncate:DF (match_dup 7)))]
15379 "TARGET_USE_FANCY_MATH_387
15380 && flag_unsafe_math_optimizations"
15384 for (i=2; i<8; i++)
15385 operands[i] = gen_reg_rtx (XFmode);
15387 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15390 (define_expand "asinsf2"
15391 [(set (match_dup 2)
15392 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15393 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15394 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15395 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15396 (parallel [(set (match_dup 7)
15397 (unspec:XF [(match_dup 6) (match_dup 2)]
15399 (clobber (match_scratch:XF 8 ""))])
15400 (set (match_operand:SF 0 "register_operand" "")
15401 (float_truncate:SF (match_dup 7)))]
15402 "TARGET_USE_FANCY_MATH_387
15403 && flag_unsafe_math_optimizations"
15407 for (i=2; i<8; i++)
15408 operands[i] = gen_reg_rtx (XFmode);
15410 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15413 (define_expand "asinxf2"
15414 [(set (match_dup 2)
15415 (mult:XF (match_operand:XF 1 "register_operand" "")
15417 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15418 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15419 (parallel [(set (match_operand:XF 0 "register_operand" "")
15420 (unspec:XF [(match_dup 5) (match_dup 1)]
15422 (clobber (match_scratch:XF 6 ""))])]
15423 "TARGET_USE_FANCY_MATH_387
15424 && flag_unsafe_math_optimizations"
15428 for (i=2; i<6; i++)
15429 operands[i] = gen_reg_rtx (XFmode);
15431 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15434 (define_expand "acosdf2"
15435 [(set (match_dup 2)
15436 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15437 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15438 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15439 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15440 (parallel [(set (match_dup 7)
15441 (unspec:XF [(match_dup 2) (match_dup 6)]
15443 (clobber (match_scratch:XF 8 ""))])
15444 (set (match_operand:DF 0 "register_operand" "")
15445 (float_truncate:DF (match_dup 7)))]
15446 "TARGET_USE_FANCY_MATH_387
15447 && flag_unsafe_math_optimizations"
15451 for (i=2; i<8; i++)
15452 operands[i] = gen_reg_rtx (XFmode);
15454 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15457 (define_expand "acossf2"
15458 [(set (match_dup 2)
15459 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15460 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15461 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15462 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15463 (parallel [(set (match_dup 7)
15464 (unspec:XF [(match_dup 2) (match_dup 6)]
15466 (clobber (match_scratch:XF 8 ""))])
15467 (set (match_operand:SF 0 "register_operand" "")
15468 (float_truncate:SF (match_dup 7)))]
15469 "TARGET_USE_FANCY_MATH_387
15470 && flag_unsafe_math_optimizations"
15474 for (i=2; i<8; i++)
15475 operands[i] = gen_reg_rtx (XFmode);
15477 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15480 (define_expand "acosxf2"
15481 [(set (match_dup 2)
15482 (mult:XF (match_operand:XF 1 "register_operand" "")
15484 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15485 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15486 (parallel [(set (match_operand:XF 0 "register_operand" "")
15487 (unspec:XF [(match_dup 1) (match_dup 5)]
15489 (clobber (match_scratch:XF 6 ""))])]
15490 "TARGET_USE_FANCY_MATH_387
15491 && flag_unsafe_math_optimizations"
15495 for (i=2; i<6; i++)
15496 operands[i] = gen_reg_rtx (XFmode);
15498 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15501 (define_insn "fyl2x_xf3"
15502 [(set (match_operand:XF 0 "register_operand" "=f")
15503 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15504 (match_operand:XF 1 "register_operand" "u")]
15506 (clobber (match_scratch:XF 3 "=1"))]
15507 "TARGET_USE_FANCY_MATH_387
15508 && flag_unsafe_math_optimizations"
15510 [(set_attr "type" "fpspc")
15511 (set_attr "mode" "XF")])
15513 (define_expand "logsf2"
15514 [(set (match_dup 2)
15515 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15516 (parallel [(set (match_dup 4)
15517 (unspec:XF [(match_dup 2)
15518 (match_dup 3)] UNSPEC_FYL2X))
15519 (clobber (match_scratch:XF 5 ""))])
15520 (set (match_operand:SF 0 "register_operand" "")
15521 (float_truncate:SF (match_dup 4)))]
15522 "TARGET_USE_FANCY_MATH_387
15523 && flag_unsafe_math_optimizations"
15527 operands[2] = gen_reg_rtx (XFmode);
15528 operands[3] = gen_reg_rtx (XFmode);
15529 operands[4] = gen_reg_rtx (XFmode);
15531 temp = standard_80387_constant_rtx (4); /* fldln2 */
15532 emit_move_insn (operands[3], temp);
15535 (define_expand "logdf2"
15536 [(set (match_dup 2)
15537 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15538 (parallel [(set (match_dup 4)
15539 (unspec:XF [(match_dup 2)
15540 (match_dup 3)] UNSPEC_FYL2X))
15541 (clobber (match_scratch:XF 5 ""))])
15542 (set (match_operand:DF 0 "register_operand" "")
15543 (float_truncate:DF (match_dup 4)))]
15544 "TARGET_USE_FANCY_MATH_387
15545 && flag_unsafe_math_optimizations"
15549 operands[2] = gen_reg_rtx (XFmode);
15550 operands[3] = gen_reg_rtx (XFmode);
15551 operands[4] = gen_reg_rtx (XFmode);
15553 temp = standard_80387_constant_rtx (4); /* fldln2 */
15554 emit_move_insn (operands[3], temp);
15557 (define_expand "logxf2"
15558 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15559 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15560 (match_dup 2)] UNSPEC_FYL2X))
15561 (clobber (match_scratch:XF 3 ""))])]
15562 "TARGET_USE_FANCY_MATH_387
15563 && flag_unsafe_math_optimizations"
15567 operands[2] = gen_reg_rtx (XFmode);
15568 temp = standard_80387_constant_rtx (4); /* fldln2 */
15569 emit_move_insn (operands[2], temp);
15572 (define_expand "log10sf2"
15573 [(set (match_dup 2)
15574 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15575 (parallel [(set (match_dup 4)
15576 (unspec:XF [(match_dup 2)
15577 (match_dup 3)] UNSPEC_FYL2X))
15578 (clobber (match_scratch:XF 5 ""))])
15579 (set (match_operand:SF 0 "register_operand" "")
15580 (float_truncate:SF (match_dup 4)))]
15581 "TARGET_USE_FANCY_MATH_387
15582 && flag_unsafe_math_optimizations"
15586 operands[2] = gen_reg_rtx (XFmode);
15587 operands[3] = gen_reg_rtx (XFmode);
15588 operands[4] = gen_reg_rtx (XFmode);
15590 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15591 emit_move_insn (operands[3], temp);
15594 (define_expand "log10df2"
15595 [(set (match_dup 2)
15596 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15597 (parallel [(set (match_dup 4)
15598 (unspec:XF [(match_dup 2)
15599 (match_dup 3)] UNSPEC_FYL2X))
15600 (clobber (match_scratch:XF 5 ""))])
15601 (set (match_operand:DF 0 "register_operand" "")
15602 (float_truncate:DF (match_dup 4)))]
15603 "TARGET_USE_FANCY_MATH_387
15604 && flag_unsafe_math_optimizations"
15608 operands[2] = gen_reg_rtx (XFmode);
15609 operands[3] = gen_reg_rtx (XFmode);
15610 operands[4] = gen_reg_rtx (XFmode);
15612 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15613 emit_move_insn (operands[3], temp);
15616 (define_expand "log10xf2"
15617 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15618 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15619 (match_dup 2)] UNSPEC_FYL2X))
15620 (clobber (match_scratch:XF 3 ""))])]
15621 "TARGET_USE_FANCY_MATH_387
15622 && flag_unsafe_math_optimizations"
15626 operands[2] = gen_reg_rtx (XFmode);
15627 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15628 emit_move_insn (operands[2], temp);
15631 (define_expand "log2sf2"
15632 [(set (match_dup 2)
15633 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15634 (parallel [(set (match_dup 4)
15635 (unspec:XF [(match_dup 2)
15636 (match_dup 3)] UNSPEC_FYL2X))
15637 (clobber (match_scratch:XF 5 ""))])
15638 (set (match_operand:SF 0 "register_operand" "")
15639 (float_truncate:SF (match_dup 4)))]
15640 "TARGET_USE_FANCY_MATH_387
15641 && flag_unsafe_math_optimizations"
15643 operands[2] = gen_reg_rtx (XFmode);
15644 operands[3] = gen_reg_rtx (XFmode);
15645 operands[4] = gen_reg_rtx (XFmode);
15647 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15650 (define_expand "log2df2"
15651 [(set (match_dup 2)
15652 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15653 (parallel [(set (match_dup 4)
15654 (unspec:XF [(match_dup 2)
15655 (match_dup 3)] UNSPEC_FYL2X))
15656 (clobber (match_scratch:XF 5 ""))])
15657 (set (match_operand:DF 0 "register_operand" "")
15658 (float_truncate:DF (match_dup 4)))]
15659 "TARGET_USE_FANCY_MATH_387
15660 && flag_unsafe_math_optimizations"
15662 operands[2] = gen_reg_rtx (XFmode);
15663 operands[3] = gen_reg_rtx (XFmode);
15664 operands[4] = gen_reg_rtx (XFmode);
15666 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15669 (define_expand "log2xf2"
15670 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15671 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15672 (match_dup 2)] UNSPEC_FYL2X))
15673 (clobber (match_scratch:XF 3 ""))])]
15674 "TARGET_USE_FANCY_MATH_387
15675 && flag_unsafe_math_optimizations"
15677 operands[2] = gen_reg_rtx (XFmode);
15678 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15681 (define_insn "fyl2xp1_xf3"
15682 [(set (match_operand:XF 0 "register_operand" "=f")
15683 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15684 (match_operand:XF 1 "register_operand" "u")]
15686 (clobber (match_scratch:XF 3 "=1"))]
15687 "TARGET_USE_FANCY_MATH_387
15688 && flag_unsafe_math_optimizations"
15690 [(set_attr "type" "fpspc")
15691 (set_attr "mode" "XF")])
15693 (define_expand "log1psf2"
15694 [(use (match_operand:XF 0 "register_operand" ""))
15695 (use (match_operand:XF 1 "register_operand" ""))]
15696 "TARGET_USE_FANCY_MATH_387
15697 && flag_unsafe_math_optimizations"
15699 rtx op0 = gen_reg_rtx (XFmode);
15700 rtx op1 = gen_reg_rtx (XFmode);
15702 emit_insn (gen_extendsfxf2 (op1, operands[1]));
15703 ix86_emit_i387_log1p (op0, op1);
15704 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
15708 (define_expand "log1pdf2"
15709 [(use (match_operand:XF 0 "register_operand" ""))
15710 (use (match_operand:XF 1 "register_operand" ""))]
15711 "TARGET_USE_FANCY_MATH_387
15712 && flag_unsafe_math_optimizations"
15714 rtx op0 = gen_reg_rtx (XFmode);
15715 rtx op1 = gen_reg_rtx (XFmode);
15717 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15718 ix86_emit_i387_log1p (op0, op1);
15719 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
15723 (define_expand "log1pxf2"
15724 [(use (match_operand:XF 0 "register_operand" ""))
15725 (use (match_operand:XF 1 "register_operand" ""))]
15726 "TARGET_USE_FANCY_MATH_387
15727 && flag_unsafe_math_optimizations"
15729 ix86_emit_i387_log1p (operands[0], operands[1]);
15733 (define_insn "*fxtractxf3"
15734 [(set (match_operand:XF 0 "register_operand" "=f")
15735 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15736 UNSPEC_XTRACT_FRACT))
15737 (set (match_operand:XF 1 "register_operand" "=u")
15738 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
15739 "TARGET_USE_FANCY_MATH_387
15740 && flag_unsafe_math_optimizations"
15742 [(set_attr "type" "fpspc")
15743 (set_attr "mode" "XF")])
15745 (define_expand "logbsf2"
15746 [(set (match_dup 2)
15747 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15748 (parallel [(set (match_dup 3)
15749 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
15751 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
15752 (set (match_operand:SF 0 "register_operand" "")
15753 (float_truncate:SF (match_dup 4)))]
15754 "TARGET_USE_FANCY_MATH_387
15755 && flag_unsafe_math_optimizations"
15757 operands[2] = gen_reg_rtx (XFmode);
15758 operands[3] = gen_reg_rtx (XFmode);
15759 operands[4] = gen_reg_rtx (XFmode);
15762 (define_expand "logbdf2"
15763 [(set (match_dup 2)
15764 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15765 (parallel [(set (match_dup 3)
15766 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
15768 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
15769 (set (match_operand:DF 0 "register_operand" "")
15770 (float_truncate:DF (match_dup 4)))]
15771 "TARGET_USE_FANCY_MATH_387
15772 && flag_unsafe_math_optimizations"
15774 operands[2] = gen_reg_rtx (XFmode);
15775 operands[3] = gen_reg_rtx (XFmode);
15776 operands[4] = gen_reg_rtx (XFmode);
15779 (define_expand "logbxf2"
15780 [(parallel [(set (match_dup 2)
15781 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15782 UNSPEC_XTRACT_FRACT))
15783 (set (match_operand:XF 0 "register_operand" "")
15784 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
15785 "TARGET_USE_FANCY_MATH_387
15786 && flag_unsafe_math_optimizations"
15788 operands[2] = gen_reg_rtx (XFmode);
15791 (define_expand "ilogbsi2"
15792 [(parallel [(set (match_dup 2)
15793 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15794 UNSPEC_XTRACT_FRACT))
15795 (set (match_operand:XF 3 "register_operand" "")
15796 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])
15797 (parallel [(set (match_operand:SI 0 "register_operand" "")
15798 (fix:SI (match_dup 3)))
15799 (clobber (reg:CC FLAGS_REG))])]
15800 "TARGET_USE_FANCY_MATH_387
15801 && flag_unsafe_math_optimizations"
15803 operands[2] = gen_reg_rtx (XFmode);
15804 operands[3] = gen_reg_rtx (XFmode);
15807 (define_insn "*f2xm1xf2"
15808 [(set (match_operand:XF 0 "register_operand" "=f")
15809 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15811 "TARGET_USE_FANCY_MATH_387
15812 && flag_unsafe_math_optimizations"
15814 [(set_attr "type" "fpspc")
15815 (set_attr "mode" "XF")])
15817 (define_insn "*fscalexf4"
15818 [(set (match_operand:XF 0 "register_operand" "=f")
15819 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15820 (match_operand:XF 3 "register_operand" "1")]
15821 UNSPEC_FSCALE_FRACT))
15822 (set (match_operand:XF 1 "register_operand" "=u")
15823 (unspec:XF [(match_dup 2) (match_dup 3)]
15824 UNSPEC_FSCALE_EXP))]
15825 "TARGET_USE_FANCY_MATH_387
15826 && flag_unsafe_math_optimizations"
15828 [(set_attr "type" "fpspc")
15829 (set_attr "mode" "XF")])
15831 (define_expand "expsf2"
15832 [(set (match_dup 2)
15833 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15834 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15835 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15836 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15837 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15838 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15839 (parallel [(set (match_dup 10)
15840 (unspec:XF [(match_dup 9) (match_dup 5)]
15841 UNSPEC_FSCALE_FRACT))
15842 (set (match_dup 11)
15843 (unspec:XF [(match_dup 9) (match_dup 5)]
15844 UNSPEC_FSCALE_EXP))])
15845 (set (match_operand:SF 0 "register_operand" "")
15846 (float_truncate:SF (match_dup 10)))]
15847 "TARGET_USE_FANCY_MATH_387
15848 && flag_unsafe_math_optimizations"
15853 for (i=2; i<12; i++)
15854 operands[i] = gen_reg_rtx (XFmode);
15855 temp = standard_80387_constant_rtx (5); /* fldl2e */
15856 emit_move_insn (operands[3], temp);
15857 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15860 (define_expand "expdf2"
15861 [(set (match_dup 2)
15862 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15863 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15864 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15865 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15866 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15867 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15868 (parallel [(set (match_dup 10)
15869 (unspec:XF [(match_dup 9) (match_dup 5)]
15870 UNSPEC_FSCALE_FRACT))
15871 (set (match_dup 11)
15872 (unspec:XF [(match_dup 9) (match_dup 5)]
15873 UNSPEC_FSCALE_EXP))])
15874 (set (match_operand:DF 0 "register_operand" "")
15875 (float_truncate:DF (match_dup 10)))]
15876 "TARGET_USE_FANCY_MATH_387
15877 && flag_unsafe_math_optimizations"
15882 for (i=2; i<12; i++)
15883 operands[i] = gen_reg_rtx (XFmode);
15884 temp = standard_80387_constant_rtx (5); /* fldl2e */
15885 emit_move_insn (operands[3], temp);
15886 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15889 (define_expand "expxf2"
15890 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15892 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15893 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15894 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15895 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15896 (parallel [(set (match_operand:XF 0 "register_operand" "")
15897 (unspec:XF [(match_dup 8) (match_dup 4)]
15898 UNSPEC_FSCALE_FRACT))
15900 (unspec:XF [(match_dup 8) (match_dup 4)]
15901 UNSPEC_FSCALE_EXP))])]
15902 "TARGET_USE_FANCY_MATH_387
15903 && flag_unsafe_math_optimizations"
15908 for (i=2; i<10; i++)
15909 operands[i] = gen_reg_rtx (XFmode);
15910 temp = standard_80387_constant_rtx (5); /* fldl2e */
15911 emit_move_insn (operands[2], temp);
15912 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
15915 (define_expand "exp10sf2"
15916 [(set (match_dup 2)
15917 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15918 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15919 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15920 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15921 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15922 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15923 (parallel [(set (match_dup 10)
15924 (unspec:XF [(match_dup 9) (match_dup 5)]
15925 UNSPEC_FSCALE_FRACT))
15926 (set (match_dup 11)
15927 (unspec:XF [(match_dup 9) (match_dup 5)]
15928 UNSPEC_FSCALE_EXP))])
15929 (set (match_operand:SF 0 "register_operand" "")
15930 (float_truncate:SF (match_dup 10)))]
15931 "TARGET_USE_FANCY_MATH_387
15932 && flag_unsafe_math_optimizations"
15937 for (i=2; i<12; i++)
15938 operands[i] = gen_reg_rtx (XFmode);
15939 temp = standard_80387_constant_rtx (6); /* fldl2t */
15940 emit_move_insn (operands[3], temp);
15941 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15944 (define_expand "exp10df2"
15945 [(set (match_dup 2)
15946 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15947 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15948 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15949 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15950 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15951 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15952 (parallel [(set (match_dup 10)
15953 (unspec:XF [(match_dup 9) (match_dup 5)]
15954 UNSPEC_FSCALE_FRACT))
15955 (set (match_dup 11)
15956 (unspec:XF [(match_dup 9) (match_dup 5)]
15957 UNSPEC_FSCALE_EXP))])
15958 (set (match_operand:DF 0 "register_operand" "")
15959 (float_truncate:DF (match_dup 10)))]
15960 "TARGET_USE_FANCY_MATH_387
15961 && flag_unsafe_math_optimizations"
15966 for (i=2; i<12; i++)
15967 operands[i] = gen_reg_rtx (XFmode);
15968 temp = standard_80387_constant_rtx (6); /* fldl2t */
15969 emit_move_insn (operands[3], temp);
15970 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15973 (define_expand "exp10xf2"
15974 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15976 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15977 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15978 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15979 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15980 (parallel [(set (match_operand:XF 0 "register_operand" "")
15981 (unspec:XF [(match_dup 8) (match_dup 4)]
15982 UNSPEC_FSCALE_FRACT))
15984 (unspec:XF [(match_dup 8) (match_dup 4)]
15985 UNSPEC_FSCALE_EXP))])]
15986 "TARGET_USE_FANCY_MATH_387
15987 && flag_unsafe_math_optimizations"
15992 for (i=2; i<10; i++)
15993 operands[i] = gen_reg_rtx (XFmode);
15994 temp = standard_80387_constant_rtx (6); /* fldl2t */
15995 emit_move_insn (operands[2], temp);
15996 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
15999 (define_expand "exp2sf2"
16000 [(set (match_dup 2)
16001 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16002 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16003 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16004 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16005 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16006 (parallel [(set (match_dup 8)
16007 (unspec:XF [(match_dup 7) (match_dup 3)]
16008 UNSPEC_FSCALE_FRACT))
16010 (unspec:XF [(match_dup 7) (match_dup 3)]
16011 UNSPEC_FSCALE_EXP))])
16012 (set (match_operand:SF 0 "register_operand" "")
16013 (float_truncate:SF (match_dup 8)))]
16014 "TARGET_USE_FANCY_MATH_387
16015 && flag_unsafe_math_optimizations"
16019 for (i=2; i<10; i++)
16020 operands[i] = gen_reg_rtx (XFmode);
16021 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16024 (define_expand "exp2df2"
16025 [(set (match_dup 2)
16026 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16027 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16028 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16029 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16030 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16031 (parallel [(set (match_dup 8)
16032 (unspec:XF [(match_dup 7) (match_dup 3)]
16033 UNSPEC_FSCALE_FRACT))
16035 (unspec:XF [(match_dup 7) (match_dup 3)]
16036 UNSPEC_FSCALE_EXP))])
16037 (set (match_operand:DF 0 "register_operand" "")
16038 (float_truncate:DF (match_dup 8)))]
16039 "TARGET_USE_FANCY_MATH_387
16040 && flag_unsafe_math_optimizations"
16044 for (i=2; i<10; i++)
16045 operands[i] = gen_reg_rtx (XFmode);
16046 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16049 (define_expand "exp2xf2"
16050 [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
16051 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16052 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16053 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16054 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16055 (parallel [(set (match_operand:XF 0 "register_operand" "")
16056 (unspec:XF [(match_dup 7) (match_dup 3)]
16057 UNSPEC_FSCALE_FRACT))
16059 (unspec:XF [(match_dup 7) (match_dup 3)]
16060 UNSPEC_FSCALE_EXP))])]
16061 "TARGET_USE_FANCY_MATH_387
16062 && flag_unsafe_math_optimizations"
16066 for (i=2; i<9; i++)
16067 operands[i] = gen_reg_rtx (XFmode);
16068 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16071 (define_expand "expm1df2"
16072 [(set (match_dup 2)
16073 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16074 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16075 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16076 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16077 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16078 (parallel [(set (match_dup 8)
16079 (unspec:XF [(match_dup 7) (match_dup 5)]
16080 UNSPEC_FSCALE_FRACT))
16082 (unspec:XF [(match_dup 7) (match_dup 5)]
16083 UNSPEC_FSCALE_EXP))])
16084 (parallel [(set (match_dup 11)
16085 (unspec:XF [(match_dup 10) (match_dup 9)]
16086 UNSPEC_FSCALE_FRACT))
16087 (set (match_dup 12)
16088 (unspec:XF [(match_dup 10) (match_dup 9)]
16089 UNSPEC_FSCALE_EXP))])
16090 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16091 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16092 (set (match_operand:DF 0 "register_operand" "")
16093 (float_truncate:DF (match_dup 14)))]
16094 "TARGET_USE_FANCY_MATH_387
16095 && flag_unsafe_math_optimizations"
16100 for (i=2; i<15; i++)
16101 operands[i] = gen_reg_rtx (XFmode);
16102 temp = standard_80387_constant_rtx (5); /* fldl2e */
16103 emit_move_insn (operands[3], temp);
16104 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16107 (define_expand "expm1sf2"
16108 [(set (match_dup 2)
16109 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16110 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16111 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16112 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16113 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16114 (parallel [(set (match_dup 8)
16115 (unspec:XF [(match_dup 7) (match_dup 5)]
16116 UNSPEC_FSCALE_FRACT))
16118 (unspec:XF [(match_dup 7) (match_dup 5)]
16119 UNSPEC_FSCALE_EXP))])
16120 (parallel [(set (match_dup 11)
16121 (unspec:XF [(match_dup 10) (match_dup 9)]
16122 UNSPEC_FSCALE_FRACT))
16123 (set (match_dup 12)
16124 (unspec:XF [(match_dup 10) (match_dup 9)]
16125 UNSPEC_FSCALE_EXP))])
16126 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16127 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16128 (set (match_operand:SF 0 "register_operand" "")
16129 (float_truncate:SF (match_dup 14)))]
16130 "TARGET_USE_FANCY_MATH_387
16131 && flag_unsafe_math_optimizations"
16136 for (i=2; i<15; i++)
16137 operands[i] = gen_reg_rtx (XFmode);
16138 temp = standard_80387_constant_rtx (5); /* fldl2e */
16139 emit_move_insn (operands[3], temp);
16140 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16143 (define_expand "expm1xf2"
16144 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16146 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16147 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16148 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16149 (parallel [(set (match_dup 7)
16150 (unspec:XF [(match_dup 6) (match_dup 4)]
16151 UNSPEC_FSCALE_FRACT))
16153 (unspec:XF [(match_dup 6) (match_dup 4)]
16154 UNSPEC_FSCALE_EXP))])
16155 (parallel [(set (match_dup 10)
16156 (unspec:XF [(match_dup 9) (match_dup 8)]
16157 UNSPEC_FSCALE_FRACT))
16158 (set (match_dup 11)
16159 (unspec:XF [(match_dup 9) (match_dup 8)]
16160 UNSPEC_FSCALE_EXP))])
16161 (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
16162 (set (match_operand:XF 0 "register_operand" "")
16163 (plus:XF (match_dup 12) (match_dup 7)))]
16164 "TARGET_USE_FANCY_MATH_387
16165 && flag_unsafe_math_optimizations"
16170 for (i=2; i<13; i++)
16171 operands[i] = gen_reg_rtx (XFmode);
16172 temp = standard_80387_constant_rtx (5); /* fldl2e */
16173 emit_move_insn (operands[2], temp);
16174 emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
16178 (define_insn "frndintxf2"
16179 [(set (match_operand:XF 0 "register_operand" "=f")
16180 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16182 "TARGET_USE_FANCY_MATH_387
16183 && flag_unsafe_math_optimizations"
16185 [(set_attr "type" "fpspc")
16186 (set_attr "mode" "XF")])
16188 (define_expand "rintdf2"
16189 [(use (match_operand:DF 0 "register_operand" ""))
16190 (use (match_operand:DF 1 "register_operand" ""))]
16191 "TARGET_USE_FANCY_MATH_387
16192 && flag_unsafe_math_optimizations"
16194 rtx op0 = gen_reg_rtx (XFmode);
16195 rtx op1 = gen_reg_rtx (XFmode);
16197 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16198 emit_insn (gen_frndintxf2 (op0, op1));
16200 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16204 (define_expand "rintsf2"
16205 [(use (match_operand:SF 0 "register_operand" ""))
16206 (use (match_operand:SF 1 "register_operand" ""))]
16207 "TARGET_USE_FANCY_MATH_387
16208 && flag_unsafe_math_optimizations"
16210 rtx op0 = gen_reg_rtx (XFmode);
16211 rtx op1 = gen_reg_rtx (XFmode);
16213 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16214 emit_insn (gen_frndintxf2 (op0, op1));
16216 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16220 (define_expand "rintxf2"
16221 [(use (match_operand:XF 0 "register_operand" ""))
16222 (use (match_operand:XF 1 "register_operand" ""))]
16223 "TARGET_USE_FANCY_MATH_387
16224 && flag_unsafe_math_optimizations"
16226 emit_insn (gen_frndintxf2 (operands[0], operands[1]));
16230 (define_insn "frndintxf2_floor"
16231 [(set (match_operand:XF 0 "register_operand" "=f")
16232 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16233 UNSPEC_FRNDINT_FLOOR))
16234 (use (match_operand:HI 2 "memory_operand" "m"))
16235 (use (match_operand:HI 3 "memory_operand" "m"))]
16236 "TARGET_USE_FANCY_MATH_387
16237 && flag_unsafe_math_optimizations"
16238 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16239 [(set_attr "type" "frndint")
16240 (set_attr "i387_cw" "floor")
16241 (set_attr "mode" "XF")])
16243 (define_expand "floordf2"
16244 [(use (match_operand:DF 0 "register_operand" ""))
16245 (use (match_operand:DF 1 "register_operand" ""))]
16246 "TARGET_USE_FANCY_MATH_387
16247 && flag_unsafe_math_optimizations"
16249 rtx op0 = gen_reg_rtx (XFmode);
16250 rtx op1 = gen_reg_rtx (XFmode);
16251 rtx op2 = assign_386_stack_local (HImode, 1);
16252 rtx op3 = assign_386_stack_local (HImode, 2);
16254 ix86_optimize_mode_switching = 1;
16256 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16257 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16259 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16263 (define_expand "floorsf2"
16264 [(use (match_operand:SF 0 "register_operand" ""))
16265 (use (match_operand:SF 1 "register_operand" ""))]
16266 "TARGET_USE_FANCY_MATH_387
16267 && flag_unsafe_math_optimizations"
16269 rtx op0 = gen_reg_rtx (XFmode);
16270 rtx op1 = gen_reg_rtx (XFmode);
16271 rtx op2 = assign_386_stack_local (HImode, 1);
16272 rtx op3 = assign_386_stack_local (HImode, 2);
16274 ix86_optimize_mode_switching = 1;
16276 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16277 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16279 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16283 (define_expand "floorxf2"
16284 [(use (match_operand:XF 0 "register_operand" ""))
16285 (use (match_operand:XF 1 "register_operand" ""))]
16286 "TARGET_USE_FANCY_MATH_387
16287 && flag_unsafe_math_optimizations"
16289 rtx op2 = assign_386_stack_local (HImode, 1);
16290 rtx op3 = assign_386_stack_local (HImode, 2);
16292 ix86_optimize_mode_switching = 1;
16294 emit_insn (gen_frndintxf2_floor (operands[0], operands[1], op2, op3));
16298 (define_insn "frndintxf2_ceil"
16299 [(set (match_operand:XF 0 "register_operand" "=f")
16300 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16301 UNSPEC_FRNDINT_CEIL))
16302 (use (match_operand:HI 2 "memory_operand" "m"))
16303 (use (match_operand:HI 3 "memory_operand" "m"))]
16304 "TARGET_USE_FANCY_MATH_387
16305 && flag_unsafe_math_optimizations"
16306 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16307 [(set_attr "type" "frndint")
16308 (set_attr "i387_cw" "ceil")
16309 (set_attr "mode" "XF")])
16311 (define_expand "ceildf2"
16312 [(use (match_operand:DF 0 "register_operand" ""))
16313 (use (match_operand:DF 1 "register_operand" ""))]
16314 "TARGET_USE_FANCY_MATH_387
16315 && flag_unsafe_math_optimizations"
16317 rtx op0 = gen_reg_rtx (XFmode);
16318 rtx op1 = gen_reg_rtx (XFmode);
16319 rtx op2 = assign_386_stack_local (HImode, 1);
16320 rtx op3 = assign_386_stack_local (HImode, 2);
16322 ix86_optimize_mode_switching = 1;
16324 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16325 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16327 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16331 (define_expand "ceilsf2"
16332 [(use (match_operand:SF 0 "register_operand" ""))
16333 (use (match_operand:SF 1 "register_operand" ""))]
16334 "TARGET_USE_FANCY_MATH_387
16335 && flag_unsafe_math_optimizations"
16337 rtx op0 = gen_reg_rtx (XFmode);
16338 rtx op1 = gen_reg_rtx (XFmode);
16339 rtx op2 = assign_386_stack_local (HImode, 1);
16340 rtx op3 = assign_386_stack_local (HImode, 2);
16342 ix86_optimize_mode_switching = 1;
16344 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16345 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16347 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16351 (define_expand "ceilxf2"
16352 [(use (match_operand:XF 0 "register_operand" ""))
16353 (use (match_operand:XF 1 "register_operand" ""))]
16354 "TARGET_USE_FANCY_MATH_387
16355 && flag_unsafe_math_optimizations"
16357 rtx op2 = assign_386_stack_local (HImode, 1);
16358 rtx op3 = assign_386_stack_local (HImode, 2);
16360 ix86_optimize_mode_switching = 1;
16362 emit_insn (gen_frndintxf2_ceil (operands[0], operands[1], op2, op3));
16366 (define_insn "frndintxf2_trunc"
16367 [(set (match_operand:XF 0 "register_operand" "=f")
16368 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16369 UNSPEC_FRNDINT_TRUNC))
16370 (use (match_operand:HI 2 "memory_operand" "m"))
16371 (use (match_operand:HI 3 "memory_operand" "m"))]
16372 "TARGET_USE_FANCY_MATH_387
16373 && flag_unsafe_math_optimizations"
16374 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16375 [(set_attr "type" "frndint")
16376 (set_attr "i387_cw" "trunc")
16377 (set_attr "mode" "XF")])
16379 (define_expand "btruncdf2"
16380 [(use (match_operand:DF 0 "register_operand" ""))
16381 (use (match_operand:DF 1 "register_operand" ""))]
16382 "TARGET_USE_FANCY_MATH_387
16383 && flag_unsafe_math_optimizations"
16385 rtx op0 = gen_reg_rtx (XFmode);
16386 rtx op1 = gen_reg_rtx (XFmode);
16387 rtx op2 = assign_386_stack_local (HImode, 1);
16388 rtx op3 = assign_386_stack_local (HImode, 2);
16390 ix86_optimize_mode_switching = 1;
16392 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16393 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16395 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16399 (define_expand "btruncsf2"
16400 [(use (match_operand:SF 0 "register_operand" ""))
16401 (use (match_operand:SF 1 "register_operand" ""))]
16402 "TARGET_USE_FANCY_MATH_387
16403 && flag_unsafe_math_optimizations"
16405 rtx op0 = gen_reg_rtx (XFmode);
16406 rtx op1 = gen_reg_rtx (XFmode);
16407 rtx op2 = assign_386_stack_local (HImode, 1);
16408 rtx op3 = assign_386_stack_local (HImode, 2);
16410 ix86_optimize_mode_switching = 1;
16412 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16413 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16415 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16419 (define_expand "btruncxf2"
16420 [(use (match_operand:XF 0 "register_operand" ""))
16421 (use (match_operand:XF 1 "register_operand" ""))]
16422 "TARGET_USE_FANCY_MATH_387
16423 && flag_unsafe_math_optimizations"
16425 rtx op2 = assign_386_stack_local (HImode, 1);
16426 rtx op3 = assign_386_stack_local (HImode, 2);
16428 ix86_optimize_mode_switching = 1;
16430 emit_insn (gen_frndintxf2_trunc (operands[0], operands[1], op2, op3));
16434 (define_insn "frndintxf2_mask_pm"
16435 [(set (match_operand:XF 0 "register_operand" "=f")
16436 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16437 UNSPEC_FRNDINT_MASK_PM))
16438 (use (match_operand:HI 2 "memory_operand" "m"))
16439 (use (match_operand:HI 3 "memory_operand" "m"))]
16440 "TARGET_USE_FANCY_MATH_387
16441 && flag_unsafe_math_optimizations"
16442 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
16443 [(set_attr "type" "frndint")
16444 (set_attr "i387_cw" "mask_pm")
16445 (set_attr "mode" "XF")])
16447 (define_expand "nearbyintdf2"
16448 [(use (match_operand:DF 0 "register_operand" ""))
16449 (use (match_operand:DF 1 "register_operand" ""))]
16450 "TARGET_USE_FANCY_MATH_387
16451 && flag_unsafe_math_optimizations"
16453 rtx op0 = gen_reg_rtx (XFmode);
16454 rtx op1 = gen_reg_rtx (XFmode);
16455 rtx op2 = assign_386_stack_local (HImode, 1);
16456 rtx op3 = assign_386_stack_local (HImode, 2);
16458 ix86_optimize_mode_switching = 1;
16460 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16461 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16463 emit_insn (gen_truncxfdf2_noop (operands[0], op0));
16467 (define_expand "nearbyintsf2"
16468 [(use (match_operand:SF 0 "register_operand" ""))
16469 (use (match_operand:SF 1 "register_operand" ""))]
16470 "TARGET_USE_FANCY_MATH_387
16471 && flag_unsafe_math_optimizations"
16473 rtx op0 = gen_reg_rtx (XFmode);
16474 rtx op1 = gen_reg_rtx (XFmode);
16475 rtx op2 = assign_386_stack_local (HImode, 1);
16476 rtx op3 = assign_386_stack_local (HImode, 2);
16478 ix86_optimize_mode_switching = 1;
16480 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16481 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16483 emit_insn (gen_truncxfsf2_noop (operands[0], op0));
16487 (define_expand "nearbyintxf2"
16488 [(use (match_operand:XF 0 "register_operand" ""))
16489 (use (match_operand:XF 1 "register_operand" ""))]
16490 "TARGET_USE_FANCY_MATH_387
16491 && flag_unsafe_math_optimizations"
16493 rtx op2 = assign_386_stack_local (HImode, 1);
16494 rtx op3 = assign_386_stack_local (HImode, 2);
16496 ix86_optimize_mode_switching = 1;
16498 emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1],
16504 ;; Block operation instructions
16507 [(set (reg:SI DIRFLAG_REG) (const_int 0))]
16510 [(set_attr "type" "cld")])
16512 (define_expand "movmemsi"
16513 [(use (match_operand:BLK 0 "memory_operand" ""))
16514 (use (match_operand:BLK 1 "memory_operand" ""))
16515 (use (match_operand:SI 2 "nonmemory_operand" ""))
16516 (use (match_operand:SI 3 "const_int_operand" ""))]
16519 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16525 (define_expand "movmemdi"
16526 [(use (match_operand:BLK 0 "memory_operand" ""))
16527 (use (match_operand:BLK 1 "memory_operand" ""))
16528 (use (match_operand:DI 2 "nonmemory_operand" ""))
16529 (use (match_operand:DI 3 "const_int_operand" ""))]
16532 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16538 ;; Most CPUs don't like single string operations
16539 ;; Handle this case here to simplify previous expander.
16541 (define_expand "strmov"
16542 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
16543 (set (match_operand 1 "memory_operand" "") (match_dup 4))
16544 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
16545 (clobber (reg:CC FLAGS_REG))])
16546 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
16547 (clobber (reg:CC FLAGS_REG))])]
16550 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
16552 /* If .md ever supports :P for Pmode, these can be directly
16553 in the pattern above. */
16554 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
16555 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
16557 if (TARGET_SINGLE_STRINGOP || optimize_size)
16559 emit_insn (gen_strmov_singleop (operands[0], operands[1],
16560 operands[2], operands[3],
16561 operands[5], operands[6]));
16565 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
16568 (define_expand "strmov_singleop"
16569 [(parallel [(set (match_operand 1 "memory_operand" "")
16570 (match_operand 3 "memory_operand" ""))
16571 (set (match_operand 0 "register_operand" "")
16572 (match_operand 4 "" ""))
16573 (set (match_operand 2 "register_operand" "")
16574 (match_operand 5 "" ""))
16575 (use (reg:SI DIRFLAG_REG))])]
16576 "TARGET_SINGLE_STRINGOP || optimize_size"
16579 (define_insn "*strmovdi_rex_1"
16580 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
16581 (mem:DI (match_operand:DI 3 "register_operand" "1")))
16582 (set (match_operand:DI 0 "register_operand" "=D")
16583 (plus:DI (match_dup 2)
16585 (set (match_operand:DI 1 "register_operand" "=S")
16586 (plus:DI (match_dup 3)
16588 (use (reg:SI DIRFLAG_REG))]
16589 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16591 [(set_attr "type" "str")
16592 (set_attr "mode" "DI")
16593 (set_attr "memory" "both")])
16595 (define_insn "*strmovsi_1"
16596 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
16597 (mem:SI (match_operand:SI 3 "register_operand" "1")))
16598 (set (match_operand:SI 0 "register_operand" "=D")
16599 (plus:SI (match_dup 2)
16601 (set (match_operand:SI 1 "register_operand" "=S")
16602 (plus:SI (match_dup 3)
16604 (use (reg:SI DIRFLAG_REG))]
16605 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16607 [(set_attr "type" "str")
16608 (set_attr "mode" "SI")
16609 (set_attr "memory" "both")])
16611 (define_insn "*strmovsi_rex_1"
16612 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
16613 (mem:SI (match_operand:DI 3 "register_operand" "1")))
16614 (set (match_operand:DI 0 "register_operand" "=D")
16615 (plus:DI (match_dup 2)
16617 (set (match_operand:DI 1 "register_operand" "=S")
16618 (plus:DI (match_dup 3)
16620 (use (reg:SI DIRFLAG_REG))]
16621 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16623 [(set_attr "type" "str")
16624 (set_attr "mode" "SI")
16625 (set_attr "memory" "both")])
16627 (define_insn "*strmovhi_1"
16628 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
16629 (mem:HI (match_operand:SI 3 "register_operand" "1")))
16630 (set (match_operand:SI 0 "register_operand" "=D")
16631 (plus:SI (match_dup 2)
16633 (set (match_operand:SI 1 "register_operand" "=S")
16634 (plus:SI (match_dup 3)
16636 (use (reg:SI DIRFLAG_REG))]
16637 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16639 [(set_attr "type" "str")
16640 (set_attr "memory" "both")
16641 (set_attr "mode" "HI")])
16643 (define_insn "*strmovhi_rex_1"
16644 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
16645 (mem:HI (match_operand:DI 3 "register_operand" "1")))
16646 (set (match_operand:DI 0 "register_operand" "=D")
16647 (plus:DI (match_dup 2)
16649 (set (match_operand:DI 1 "register_operand" "=S")
16650 (plus:DI (match_dup 3)
16652 (use (reg:SI DIRFLAG_REG))]
16653 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16655 [(set_attr "type" "str")
16656 (set_attr "memory" "both")
16657 (set_attr "mode" "HI")])
16659 (define_insn "*strmovqi_1"
16660 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
16661 (mem:QI (match_operand:SI 3 "register_operand" "1")))
16662 (set (match_operand:SI 0 "register_operand" "=D")
16663 (plus:SI (match_dup 2)
16665 (set (match_operand:SI 1 "register_operand" "=S")
16666 (plus:SI (match_dup 3)
16668 (use (reg:SI DIRFLAG_REG))]
16669 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16671 [(set_attr "type" "str")
16672 (set_attr "memory" "both")
16673 (set_attr "mode" "QI")])
16675 (define_insn "*strmovqi_rex_1"
16676 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
16677 (mem:QI (match_operand:DI 3 "register_operand" "1")))
16678 (set (match_operand:DI 0 "register_operand" "=D")
16679 (plus:DI (match_dup 2)
16681 (set (match_operand:DI 1 "register_operand" "=S")
16682 (plus:DI (match_dup 3)
16684 (use (reg:SI DIRFLAG_REG))]
16685 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16687 [(set_attr "type" "str")
16688 (set_attr "memory" "both")
16689 (set_attr "mode" "QI")])
16691 (define_expand "rep_mov"
16692 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
16693 (set (match_operand 0 "register_operand" "")
16694 (match_operand 5 "" ""))
16695 (set (match_operand 2 "register_operand" "")
16696 (match_operand 6 "" ""))
16697 (set (match_operand 1 "memory_operand" "")
16698 (match_operand 3 "memory_operand" ""))
16699 (use (match_dup 4))
16700 (use (reg:SI DIRFLAG_REG))])]
16704 (define_insn "*rep_movdi_rex64"
16705 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16706 (set (match_operand:DI 0 "register_operand" "=D")
16707 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16709 (match_operand:DI 3 "register_operand" "0")))
16710 (set (match_operand:DI 1 "register_operand" "=S")
16711 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
16712 (match_operand:DI 4 "register_operand" "1")))
16713 (set (mem:BLK (match_dup 3))
16714 (mem:BLK (match_dup 4)))
16715 (use (match_dup 5))
16716 (use (reg:SI DIRFLAG_REG))]
16718 "{rep\;movsq|rep movsq}"
16719 [(set_attr "type" "str")
16720 (set_attr "prefix_rep" "1")
16721 (set_attr "memory" "both")
16722 (set_attr "mode" "DI")])
16724 (define_insn "*rep_movsi"
16725 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16726 (set (match_operand:SI 0 "register_operand" "=D")
16727 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
16729 (match_operand:SI 3 "register_operand" "0")))
16730 (set (match_operand:SI 1 "register_operand" "=S")
16731 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
16732 (match_operand:SI 4 "register_operand" "1")))
16733 (set (mem:BLK (match_dup 3))
16734 (mem:BLK (match_dup 4)))
16735 (use (match_dup 5))
16736 (use (reg:SI DIRFLAG_REG))]
16738 "{rep\;movsl|rep movsd}"
16739 [(set_attr "type" "str")
16740 (set_attr "prefix_rep" "1")
16741 (set_attr "memory" "both")
16742 (set_attr "mode" "SI")])
16744 (define_insn "*rep_movsi_rex64"
16745 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16746 (set (match_operand:DI 0 "register_operand" "=D")
16747 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16749 (match_operand:DI 3 "register_operand" "0")))
16750 (set (match_operand:DI 1 "register_operand" "=S")
16751 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
16752 (match_operand:DI 4 "register_operand" "1")))
16753 (set (mem:BLK (match_dup 3))
16754 (mem:BLK (match_dup 4)))
16755 (use (match_dup 5))
16756 (use (reg:SI DIRFLAG_REG))]
16758 "{rep\;movsl|rep movsd}"
16759 [(set_attr "type" "str")
16760 (set_attr "prefix_rep" "1")
16761 (set_attr "memory" "both")
16762 (set_attr "mode" "SI")])
16764 (define_insn "*rep_movqi"
16765 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16766 (set (match_operand:SI 0 "register_operand" "=D")
16767 (plus:SI (match_operand:SI 3 "register_operand" "0")
16768 (match_operand:SI 5 "register_operand" "2")))
16769 (set (match_operand:SI 1 "register_operand" "=S")
16770 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
16771 (set (mem:BLK (match_dup 3))
16772 (mem:BLK (match_dup 4)))
16773 (use (match_dup 5))
16774 (use (reg:SI DIRFLAG_REG))]
16776 "{rep\;movsb|rep movsb}"
16777 [(set_attr "type" "str")
16778 (set_attr "prefix_rep" "1")
16779 (set_attr "memory" "both")
16780 (set_attr "mode" "SI")])
16782 (define_insn "*rep_movqi_rex64"
16783 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16784 (set (match_operand:DI 0 "register_operand" "=D")
16785 (plus:DI (match_operand:DI 3 "register_operand" "0")
16786 (match_operand:DI 5 "register_operand" "2")))
16787 (set (match_operand:DI 1 "register_operand" "=S")
16788 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
16789 (set (mem:BLK (match_dup 3))
16790 (mem:BLK (match_dup 4)))
16791 (use (match_dup 5))
16792 (use (reg:SI DIRFLAG_REG))]
16794 "{rep\;movsb|rep movsb}"
16795 [(set_attr "type" "str")
16796 (set_attr "prefix_rep" "1")
16797 (set_attr "memory" "both")
16798 (set_attr "mode" "SI")])
16800 (define_expand "clrmemsi"
16801 [(use (match_operand:BLK 0 "memory_operand" ""))
16802 (use (match_operand:SI 1 "nonmemory_operand" ""))
16803 (use (match_operand 2 "const_int_operand" ""))]
16806 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
16812 (define_expand "clrmemdi"
16813 [(use (match_operand:BLK 0 "memory_operand" ""))
16814 (use (match_operand:DI 1 "nonmemory_operand" ""))
16815 (use (match_operand 2 "const_int_operand" ""))]
16818 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
16824 ;; Most CPUs don't like single string operations
16825 ;; Handle this case here to simplify previous expander.
16827 (define_expand "strset"
16828 [(set (match_operand 1 "memory_operand" "")
16829 (match_operand 2 "register_operand" ""))
16830 (parallel [(set (match_operand 0 "register_operand" "")
16832 (clobber (reg:CC FLAGS_REG))])]
16835 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
16836 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
16838 /* If .md ever supports :P for Pmode, this can be directly
16839 in the pattern above. */
16840 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
16841 GEN_INT (GET_MODE_SIZE (GET_MODE
16843 if (TARGET_SINGLE_STRINGOP || optimize_size)
16845 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
16851 (define_expand "strset_singleop"
16852 [(parallel [(set (match_operand 1 "memory_operand" "")
16853 (match_operand 2 "register_operand" ""))
16854 (set (match_operand 0 "register_operand" "")
16855 (match_operand 3 "" ""))
16856 (use (reg:SI DIRFLAG_REG))])]
16857 "TARGET_SINGLE_STRINGOP || optimize_size"
16860 (define_insn "*strsetdi_rex_1"
16861 [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
16862 (match_operand:DI 2 "register_operand" "a"))
16863 (set (match_operand:DI 0 "register_operand" "=D")
16864 (plus:DI (match_dup 1)
16866 (use (reg:SI DIRFLAG_REG))]
16867 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16869 [(set_attr "type" "str")
16870 (set_attr "memory" "store")
16871 (set_attr "mode" "DI")])
16873 (define_insn "*strsetsi_1"
16874 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
16875 (match_operand:SI 2 "register_operand" "a"))
16876 (set (match_operand:SI 0 "register_operand" "=D")
16877 (plus:SI (match_dup 1)
16879 (use (reg:SI DIRFLAG_REG))]
16880 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16882 [(set_attr "type" "str")
16883 (set_attr "memory" "store")
16884 (set_attr "mode" "SI")])
16886 (define_insn "*strsetsi_rex_1"
16887 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16888 (match_operand:SI 2 "register_operand" "a"))
16889 (set (match_operand:DI 0 "register_operand" "=D")
16890 (plus:DI (match_dup 1)
16892 (use (reg:SI DIRFLAG_REG))]
16893 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16895 [(set_attr "type" "str")
16896 (set_attr "memory" "store")
16897 (set_attr "mode" "SI")])
16899 (define_insn "*strsethi_1"
16900 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
16901 (match_operand:HI 2 "register_operand" "a"))
16902 (set (match_operand:SI 0 "register_operand" "=D")
16903 (plus:SI (match_dup 1)
16905 (use (reg:SI DIRFLAG_REG))]
16906 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16908 [(set_attr "type" "str")
16909 (set_attr "memory" "store")
16910 (set_attr "mode" "HI")])
16912 (define_insn "*strsethi_rex_1"
16913 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
16914 (match_operand:HI 2 "register_operand" "a"))
16915 (set (match_operand:DI 0 "register_operand" "=D")
16916 (plus:DI (match_dup 1)
16918 (use (reg:SI DIRFLAG_REG))]
16919 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16921 [(set_attr "type" "str")
16922 (set_attr "memory" "store")
16923 (set_attr "mode" "HI")])
16925 (define_insn "*strsetqi_1"
16926 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
16927 (match_operand:QI 2 "register_operand" "a"))
16928 (set (match_operand:SI 0 "register_operand" "=D")
16929 (plus:SI (match_dup 1)
16931 (use (reg:SI DIRFLAG_REG))]
16932 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16934 [(set_attr "type" "str")
16935 (set_attr "memory" "store")
16936 (set_attr "mode" "QI")])
16938 (define_insn "*strsetqi_rex_1"
16939 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
16940 (match_operand:QI 2 "register_operand" "a"))
16941 (set (match_operand:DI 0 "register_operand" "=D")
16942 (plus:DI (match_dup 1)
16944 (use (reg:SI DIRFLAG_REG))]
16945 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16947 [(set_attr "type" "str")
16948 (set_attr "memory" "store")
16949 (set_attr "mode" "QI")])
16951 (define_expand "rep_stos"
16952 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
16953 (set (match_operand 0 "register_operand" "")
16954 (match_operand 4 "" ""))
16955 (set (match_operand 2 "memory_operand" "") (const_int 0))
16956 (use (match_operand 3 "register_operand" ""))
16957 (use (match_dup 1))
16958 (use (reg:SI DIRFLAG_REG))])]
16962 (define_insn "*rep_stosdi_rex64"
16963 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16964 (set (match_operand:DI 0 "register_operand" "=D")
16965 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16967 (match_operand:DI 3 "register_operand" "0")))
16968 (set (mem:BLK (match_dup 3))
16970 (use (match_operand:DI 2 "register_operand" "a"))
16971 (use (match_dup 4))
16972 (use (reg:SI DIRFLAG_REG))]
16974 "{rep\;stosq|rep stosq}"
16975 [(set_attr "type" "str")
16976 (set_attr "prefix_rep" "1")
16977 (set_attr "memory" "store")
16978 (set_attr "mode" "DI")])
16980 (define_insn "*rep_stossi"
16981 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16982 (set (match_operand:SI 0 "register_operand" "=D")
16983 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
16985 (match_operand:SI 3 "register_operand" "0")))
16986 (set (mem:BLK (match_dup 3))
16988 (use (match_operand:SI 2 "register_operand" "a"))
16989 (use (match_dup 4))
16990 (use (reg:SI DIRFLAG_REG))]
16992 "{rep\;stosl|rep stosd}"
16993 [(set_attr "type" "str")
16994 (set_attr "prefix_rep" "1")
16995 (set_attr "memory" "store")
16996 (set_attr "mode" "SI")])
16998 (define_insn "*rep_stossi_rex64"
16999 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17000 (set (match_operand:DI 0 "register_operand" "=D")
17001 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
17003 (match_operand:DI 3 "register_operand" "0")))
17004 (set (mem:BLK (match_dup 3))
17006 (use (match_operand:SI 2 "register_operand" "a"))
17007 (use (match_dup 4))
17008 (use (reg:SI DIRFLAG_REG))]
17010 "{rep\;stosl|rep stosd}"
17011 [(set_attr "type" "str")
17012 (set_attr "prefix_rep" "1")
17013 (set_attr "memory" "store")
17014 (set_attr "mode" "SI")])
17016 (define_insn "*rep_stosqi"
17017 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17018 (set (match_operand:SI 0 "register_operand" "=D")
17019 (plus:SI (match_operand:SI 3 "register_operand" "0")
17020 (match_operand:SI 4 "register_operand" "1")))
17021 (set (mem:BLK (match_dup 3))
17023 (use (match_operand:QI 2 "register_operand" "a"))
17024 (use (match_dup 4))
17025 (use (reg:SI DIRFLAG_REG))]
17027 "{rep\;stosb|rep stosb}"
17028 [(set_attr "type" "str")
17029 (set_attr "prefix_rep" "1")
17030 (set_attr "memory" "store")
17031 (set_attr "mode" "QI")])
17033 (define_insn "*rep_stosqi_rex64"
17034 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17035 (set (match_operand:DI 0 "register_operand" "=D")
17036 (plus:DI (match_operand:DI 3 "register_operand" "0")
17037 (match_operand:DI 4 "register_operand" "1")))
17038 (set (mem:BLK (match_dup 3))
17040 (use (match_operand:QI 2 "register_operand" "a"))
17041 (use (match_dup 4))
17042 (use (reg:SI DIRFLAG_REG))]
17044 "{rep\;stosb|rep stosb}"
17045 [(set_attr "type" "str")
17046 (set_attr "prefix_rep" "1")
17047 (set_attr "memory" "store")
17048 (set_attr "mode" "QI")])
17050 (define_expand "cmpstrsi"
17051 [(set (match_operand:SI 0 "register_operand" "")
17052 (compare:SI (match_operand:BLK 1 "general_operand" "")
17053 (match_operand:BLK 2 "general_operand" "")))
17054 (use (match_operand 3 "general_operand" ""))
17055 (use (match_operand 4 "immediate_operand" ""))]
17056 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
17058 rtx addr1, addr2, out, outlow, count, countreg, align;
17060 /* Can't use this if the user has appropriated esi or edi. */
17061 if (global_regs[4] || global_regs[5])
17065 if (GET_CODE (out) != REG)
17066 out = gen_reg_rtx (SImode);
17068 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
17069 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
17070 if (addr1 != XEXP (operands[1], 0))
17071 operands[1] = replace_equiv_address_nv (operands[1], addr1);
17072 if (addr2 != XEXP (operands[2], 0))
17073 operands[2] = replace_equiv_address_nv (operands[2], addr2);
17075 count = operands[3];
17076 countreg = ix86_zero_extend_to_Pmode (count);
17078 /* %%% Iff we are testing strict equality, we can use known alignment
17079 to good advantage. This may be possible with combine, particularly
17080 once cc0 is dead. */
17081 align = operands[4];
17083 emit_insn (gen_cld ());
17084 if (GET_CODE (count) == CONST_INT)
17086 if (INTVAL (count) == 0)
17088 emit_move_insn (operands[0], const0_rtx);
17091 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
17092 operands[1], operands[2]));
17097 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
17099 emit_insn (gen_cmpsi_1 (countreg, countreg));
17100 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
17101 operands[1], operands[2]));
17104 outlow = gen_lowpart (QImode, out);
17105 emit_insn (gen_cmpintqi (outlow));
17106 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
17108 if (operands[0] != out)
17109 emit_move_insn (operands[0], out);
17114 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
17116 (define_expand "cmpintqi"
17117 [(set (match_dup 1)
17118 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17120 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17121 (parallel [(set (match_operand:QI 0 "register_operand" "")
17122 (minus:QI (match_dup 1)
17124 (clobber (reg:CC FLAGS_REG))])]
17126 "operands[1] = gen_reg_rtx (QImode);
17127 operands[2] = gen_reg_rtx (QImode);")
17129 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
17130 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
17132 (define_expand "cmpstrqi_nz_1"
17133 [(parallel [(set (reg:CC FLAGS_REG)
17134 (compare:CC (match_operand 4 "memory_operand" "")
17135 (match_operand 5 "memory_operand" "")))
17136 (use (match_operand 2 "register_operand" ""))
17137 (use (match_operand:SI 3 "immediate_operand" ""))
17138 (use (reg:SI DIRFLAG_REG))
17139 (clobber (match_operand 0 "register_operand" ""))
17140 (clobber (match_operand 1 "register_operand" ""))
17141 (clobber (match_dup 2))])]
17145 (define_insn "*cmpstrqi_nz_1"
17146 [(set (reg:CC FLAGS_REG)
17147 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17148 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
17149 (use (match_operand:SI 6 "register_operand" "2"))
17150 (use (match_operand:SI 3 "immediate_operand" "i"))
17151 (use (reg:SI DIRFLAG_REG))
17152 (clobber (match_operand:SI 0 "register_operand" "=S"))
17153 (clobber (match_operand:SI 1 "register_operand" "=D"))
17154 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17157 [(set_attr "type" "str")
17158 (set_attr "mode" "QI")
17159 (set_attr "prefix_rep" "1")])
17161 (define_insn "*cmpstrqi_nz_rex_1"
17162 [(set (reg:CC FLAGS_REG)
17163 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17164 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
17165 (use (match_operand:DI 6 "register_operand" "2"))
17166 (use (match_operand:SI 3 "immediate_operand" "i"))
17167 (use (reg:SI DIRFLAG_REG))
17168 (clobber (match_operand:DI 0 "register_operand" "=S"))
17169 (clobber (match_operand:DI 1 "register_operand" "=D"))
17170 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17173 [(set_attr "type" "str")
17174 (set_attr "mode" "QI")
17175 (set_attr "prefix_rep" "1")])
17177 ;; The same, but the count is not known to not be zero.
17179 (define_expand "cmpstrqi_1"
17180 [(parallel [(set (reg:CC FLAGS_REG)
17181 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
17183 (compare:CC (match_operand 4 "memory_operand" "")
17184 (match_operand 5 "memory_operand" ""))
17186 (use (match_operand:SI 3 "immediate_operand" ""))
17187 (use (reg:CC FLAGS_REG))
17188 (use (reg:SI DIRFLAG_REG))
17189 (clobber (match_operand 0 "register_operand" ""))
17190 (clobber (match_operand 1 "register_operand" ""))
17191 (clobber (match_dup 2))])]
17195 (define_insn "*cmpstrqi_1"
17196 [(set (reg:CC FLAGS_REG)
17197 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
17199 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17200 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
17202 (use (match_operand:SI 3 "immediate_operand" "i"))
17203 (use (reg:CC FLAGS_REG))
17204 (use (reg:SI DIRFLAG_REG))
17205 (clobber (match_operand:SI 0 "register_operand" "=S"))
17206 (clobber (match_operand:SI 1 "register_operand" "=D"))
17207 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17210 [(set_attr "type" "str")
17211 (set_attr "mode" "QI")
17212 (set_attr "prefix_rep" "1")])
17214 (define_insn "*cmpstrqi_rex_1"
17215 [(set (reg:CC FLAGS_REG)
17216 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
17218 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17219 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
17221 (use (match_operand:SI 3 "immediate_operand" "i"))
17222 (use (reg:CC FLAGS_REG))
17223 (use (reg:SI DIRFLAG_REG))
17224 (clobber (match_operand:DI 0 "register_operand" "=S"))
17225 (clobber (match_operand:DI 1 "register_operand" "=D"))
17226 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17229 [(set_attr "type" "str")
17230 (set_attr "mode" "QI")
17231 (set_attr "prefix_rep" "1")])
17233 (define_expand "strlensi"
17234 [(set (match_operand:SI 0 "register_operand" "")
17235 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
17236 (match_operand:QI 2 "immediate_operand" "")
17237 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17240 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17246 (define_expand "strlendi"
17247 [(set (match_operand:DI 0 "register_operand" "")
17248 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
17249 (match_operand:QI 2 "immediate_operand" "")
17250 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17253 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17259 (define_expand "strlenqi_1"
17260 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
17261 (use (reg:SI DIRFLAG_REG))
17262 (clobber (match_operand 1 "register_operand" ""))
17263 (clobber (reg:CC FLAGS_REG))])]
17267 (define_insn "*strlenqi_1"
17268 [(set (match_operand:SI 0 "register_operand" "=&c")
17269 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
17270 (match_operand:QI 2 "register_operand" "a")
17271 (match_operand:SI 3 "immediate_operand" "i")
17272 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
17273 (use (reg:SI DIRFLAG_REG))
17274 (clobber (match_operand:SI 1 "register_operand" "=D"))
17275 (clobber (reg:CC FLAGS_REG))]
17278 [(set_attr "type" "str")
17279 (set_attr "mode" "QI")
17280 (set_attr "prefix_rep" "1")])
17282 (define_insn "*strlenqi_rex_1"
17283 [(set (match_operand:DI 0 "register_operand" "=&c")
17284 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
17285 (match_operand:QI 2 "register_operand" "a")
17286 (match_operand:DI 3 "immediate_operand" "i")
17287 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
17288 (use (reg:SI DIRFLAG_REG))
17289 (clobber (match_operand:DI 1 "register_operand" "=D"))
17290 (clobber (reg:CC FLAGS_REG))]
17293 [(set_attr "type" "str")
17294 (set_attr "mode" "QI")
17295 (set_attr "prefix_rep" "1")])
17297 ;; Peephole optimizations to clean up after cmpstr*. This should be
17298 ;; handled in combine, but it is not currently up to the task.
17299 ;; When used for their truth value, the cmpstr* expanders generate
17308 ;; The intermediate three instructions are unnecessary.
17310 ;; This one handles cmpstr*_nz_1...
17313 (set (reg:CC FLAGS_REG)
17314 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17315 (mem:BLK (match_operand 5 "register_operand" ""))))
17316 (use (match_operand 6 "register_operand" ""))
17317 (use (match_operand:SI 3 "immediate_operand" ""))
17318 (use (reg:SI DIRFLAG_REG))
17319 (clobber (match_operand 0 "register_operand" ""))
17320 (clobber (match_operand 1 "register_operand" ""))
17321 (clobber (match_operand 2 "register_operand" ""))])
17322 (set (match_operand:QI 7 "register_operand" "")
17323 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17324 (set (match_operand:QI 8 "register_operand" "")
17325 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17326 (set (reg FLAGS_REG)
17327 (compare (match_dup 7) (match_dup 8)))
17329 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17331 (set (reg:CC FLAGS_REG)
17332 (compare:CC (mem:BLK (match_dup 4))
17333 (mem:BLK (match_dup 5))))
17334 (use (match_dup 6))
17335 (use (match_dup 3))
17336 (use (reg:SI DIRFLAG_REG))
17337 (clobber (match_dup 0))
17338 (clobber (match_dup 1))
17339 (clobber (match_dup 2))])]
17342 ;; ...and this one handles cmpstr*_1.
17345 (set (reg:CC FLAGS_REG)
17346 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
17348 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17349 (mem:BLK (match_operand 5 "register_operand" "")))
17351 (use (match_operand:SI 3 "immediate_operand" ""))
17352 (use (reg:CC FLAGS_REG))
17353 (use (reg:SI DIRFLAG_REG))
17354 (clobber (match_operand 0 "register_operand" ""))
17355 (clobber (match_operand 1 "register_operand" ""))
17356 (clobber (match_operand 2 "register_operand" ""))])
17357 (set (match_operand:QI 7 "register_operand" "")
17358 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17359 (set (match_operand:QI 8 "register_operand" "")
17360 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17361 (set (reg FLAGS_REG)
17362 (compare (match_dup 7) (match_dup 8)))
17364 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17366 (set (reg:CC FLAGS_REG)
17367 (if_then_else:CC (ne (match_dup 6)
17369 (compare:CC (mem:BLK (match_dup 4))
17370 (mem:BLK (match_dup 5)))
17372 (use (match_dup 3))
17373 (use (reg:CC FLAGS_REG))
17374 (use (reg:SI DIRFLAG_REG))
17375 (clobber (match_dup 0))
17376 (clobber (match_dup 1))
17377 (clobber (match_dup 2))])]
17382 ;; Conditional move instructions.
17384 (define_expand "movdicc"
17385 [(set (match_operand:DI 0 "register_operand" "")
17386 (if_then_else:DI (match_operand 1 "comparison_operator" "")
17387 (match_operand:DI 2 "general_operand" "")
17388 (match_operand:DI 3 "general_operand" "")))]
17390 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17392 (define_insn "x86_movdicc_0_m1_rex64"
17393 [(set (match_operand:DI 0 "register_operand" "=r")
17394 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
17397 (clobber (reg:CC FLAGS_REG))]
17400 ; Since we don't have the proper number of operands for an alu insn,
17401 ; fill in all the blanks.
17402 [(set_attr "type" "alu")
17403 (set_attr "pent_pair" "pu")
17404 (set_attr "memory" "none")
17405 (set_attr "imm_disp" "false")
17406 (set_attr "mode" "DI")
17407 (set_attr "length_immediate" "0")])
17409 (define_insn "movdicc_c_rex64"
17410 [(set (match_operand:DI 0 "register_operand" "=r,r")
17411 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
17412 [(reg FLAGS_REG) (const_int 0)])
17413 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
17414 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
17415 "TARGET_64BIT && TARGET_CMOVE
17416 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17418 cmov%O2%C1\t{%2, %0|%0, %2}
17419 cmov%O2%c1\t{%3, %0|%0, %3}"
17420 [(set_attr "type" "icmov")
17421 (set_attr "mode" "DI")])
17423 (define_expand "movsicc"
17424 [(set (match_operand:SI 0 "register_operand" "")
17425 (if_then_else:SI (match_operand 1 "comparison_operator" "")
17426 (match_operand:SI 2 "general_operand" "")
17427 (match_operand:SI 3 "general_operand" "")))]
17429 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17431 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
17432 ;; the register first winds up with `sbbl $0,reg', which is also weird.
17433 ;; So just document what we're doing explicitly.
17435 (define_insn "x86_movsicc_0_m1"
17436 [(set (match_operand:SI 0 "register_operand" "=r")
17437 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
17440 (clobber (reg:CC FLAGS_REG))]
17443 ; Since we don't have the proper number of operands for an alu insn,
17444 ; fill in all the blanks.
17445 [(set_attr "type" "alu")
17446 (set_attr "pent_pair" "pu")
17447 (set_attr "memory" "none")
17448 (set_attr "imm_disp" "false")
17449 (set_attr "mode" "SI")
17450 (set_attr "length_immediate" "0")])
17452 (define_insn "*movsicc_noc"
17453 [(set (match_operand:SI 0 "register_operand" "=r,r")
17454 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
17455 [(reg FLAGS_REG) (const_int 0)])
17456 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
17457 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
17459 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17461 cmov%O2%C1\t{%2, %0|%0, %2}
17462 cmov%O2%c1\t{%3, %0|%0, %3}"
17463 [(set_attr "type" "icmov")
17464 (set_attr "mode" "SI")])
17466 (define_expand "movhicc"
17467 [(set (match_operand:HI 0 "register_operand" "")
17468 (if_then_else:HI (match_operand 1 "comparison_operator" "")
17469 (match_operand:HI 2 "general_operand" "")
17470 (match_operand:HI 3 "general_operand" "")))]
17471 "TARGET_HIMODE_MATH"
17472 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17474 (define_insn "*movhicc_noc"
17475 [(set (match_operand:HI 0 "register_operand" "=r,r")
17476 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
17477 [(reg FLAGS_REG) (const_int 0)])
17478 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
17479 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
17481 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17483 cmov%O2%C1\t{%2, %0|%0, %2}
17484 cmov%O2%c1\t{%3, %0|%0, %3}"
17485 [(set_attr "type" "icmov")
17486 (set_attr "mode" "HI")])
17488 (define_expand "movqicc"
17489 [(set (match_operand:QI 0 "register_operand" "")
17490 (if_then_else:QI (match_operand 1 "comparison_operator" "")
17491 (match_operand:QI 2 "general_operand" "")
17492 (match_operand:QI 3 "general_operand" "")))]
17493 "TARGET_QIMODE_MATH"
17494 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17496 (define_insn_and_split "*movqicc_noc"
17497 [(set (match_operand:QI 0 "register_operand" "=r,r")
17498 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
17499 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17500 (match_operand:QI 2 "register_operand" "r,0")
17501 (match_operand:QI 3 "register_operand" "0,r")))]
17502 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
17504 "&& reload_completed"
17505 [(set (match_dup 0)
17506 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17509 "operands[0] = gen_lowpart (SImode, operands[0]);
17510 operands[2] = gen_lowpart (SImode, operands[2]);
17511 operands[3] = gen_lowpart (SImode, operands[3]);"
17512 [(set_attr "type" "icmov")
17513 (set_attr "mode" "SI")])
17515 (define_expand "movsfcc"
17516 [(set (match_operand:SF 0 "register_operand" "")
17517 (if_then_else:SF (match_operand 1 "comparison_operator" "")
17518 (match_operand:SF 2 "register_operand" "")
17519 (match_operand:SF 3 "register_operand" "")))]
17521 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17523 (define_insn "*movsfcc_1"
17524 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17525 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17526 [(reg FLAGS_REG) (const_int 0)])
17527 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17528 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17530 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17532 fcmov%F1\t{%2, %0|%0, %2}
17533 fcmov%f1\t{%3, %0|%0, %3}
17534 cmov%O2%C1\t{%2, %0|%0, %2}
17535 cmov%O2%c1\t{%3, %0|%0, %3}"
17536 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17537 (set_attr "mode" "SF,SF,SI,SI")])
17539 (define_expand "movdfcc"
17540 [(set (match_operand:DF 0 "register_operand" "")
17541 (if_then_else:DF (match_operand 1 "comparison_operator" "")
17542 (match_operand:DF 2 "register_operand" "")
17543 (match_operand:DF 3 "register_operand" "")))]
17545 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17547 (define_insn "*movdfcc_1"
17548 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
17549 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17550 [(reg FLAGS_REG) (const_int 0)])
17551 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17552 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17553 "!TARGET_64BIT && TARGET_CMOVE
17554 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17556 fcmov%F1\t{%2, %0|%0, %2}
17557 fcmov%f1\t{%3, %0|%0, %3}
17560 [(set_attr "type" "fcmov,fcmov,multi,multi")
17561 (set_attr "mode" "DF")])
17563 (define_insn "*movdfcc_1_rex64"
17564 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17565 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17566 [(reg FLAGS_REG) (const_int 0)])
17567 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
17568 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
17569 "TARGET_64BIT && TARGET_CMOVE
17570 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17572 fcmov%F1\t{%2, %0|%0, %2}
17573 fcmov%f1\t{%3, %0|%0, %3}
17574 cmov%O2%C1\t{%2, %0|%0, %2}
17575 cmov%O2%c1\t{%3, %0|%0, %3}"
17576 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17577 (set_attr "mode" "DF")])
17580 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
17581 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17582 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17583 (match_operand:DF 2 "nonimmediate_operand" "")
17584 (match_operand:DF 3 "nonimmediate_operand" "")))]
17585 "!TARGET_64BIT && reload_completed"
17586 [(set (match_dup 2)
17587 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17591 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17594 "split_di (operands+2, 1, operands+5, operands+6);
17595 split_di (operands+3, 1, operands+7, operands+8);
17596 split_di (operands, 1, operands+2, operands+3);")
17598 (define_expand "movxfcc"
17599 [(set (match_operand:XF 0 "register_operand" "")
17600 (if_then_else:XF (match_operand 1 "comparison_operator" "")
17601 (match_operand:XF 2 "register_operand" "")
17602 (match_operand:XF 3 "register_operand" "")))]
17604 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17606 (define_insn "*movxfcc_1"
17607 [(set (match_operand:XF 0 "register_operand" "=f,f")
17608 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
17609 [(reg FLAGS_REG) (const_int 0)])
17610 (match_operand:XF 2 "register_operand" "f,0")
17611 (match_operand:XF 3 "register_operand" "0,f")))]
17614 fcmov%F1\t{%2, %0|%0, %2}
17615 fcmov%f1\t{%3, %0|%0, %3}"
17616 [(set_attr "type" "fcmov")
17617 (set_attr "mode" "XF")])
17619 (define_expand "minsf3"
17621 (set (match_operand:SF 0 "register_operand" "")
17622 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17623 (match_operand:SF 2 "nonimmediate_operand" ""))
17626 (clobber (reg:CC FLAGS_REG))])]
17630 (define_insn "*minsf"
17631 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17632 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
17633 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17636 (clobber (reg:CC FLAGS_REG))]
17637 "TARGET_SSE && TARGET_IEEE_FP"
17640 (define_insn "*minsf_nonieee"
17641 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17642 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17643 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17646 (clobber (reg:CC FLAGS_REG))]
17647 "TARGET_SSE && !TARGET_IEEE_FP
17648 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17652 [(set (match_operand:SF 0 "register_operand" "")
17653 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17654 (match_operand:SF 2 "nonimmediate_operand" ""))
17655 (match_operand:SF 3 "register_operand" "")
17656 (match_operand:SF 4 "nonimmediate_operand" "")))
17657 (clobber (reg:CC FLAGS_REG))]
17658 "SSE_REG_P (operands[0]) && reload_completed
17659 && ((operands_match_p (operands[1], operands[3])
17660 && operands_match_p (operands[2], operands[4]))
17661 || (operands_match_p (operands[1], operands[4])
17662 && operands_match_p (operands[2], operands[3])))"
17663 [(set (match_dup 0)
17664 (if_then_else:SF (lt (match_dup 1)
17669 ;; Conditional addition patterns
17670 (define_expand "addqicc"
17671 [(match_operand:QI 0 "register_operand" "")
17672 (match_operand 1 "comparison_operator" "")
17673 (match_operand:QI 2 "register_operand" "")
17674 (match_operand:QI 3 "const_int_operand" "")]
17676 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17678 (define_expand "addhicc"
17679 [(match_operand:HI 0 "register_operand" "")
17680 (match_operand 1 "comparison_operator" "")
17681 (match_operand:HI 2 "register_operand" "")
17682 (match_operand:HI 3 "const_int_operand" "")]
17684 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17686 (define_expand "addsicc"
17687 [(match_operand:SI 0 "register_operand" "")
17688 (match_operand 1 "comparison_operator" "")
17689 (match_operand:SI 2 "register_operand" "")
17690 (match_operand:SI 3 "const_int_operand" "")]
17692 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17694 (define_expand "adddicc"
17695 [(match_operand:DI 0 "register_operand" "")
17696 (match_operand 1 "comparison_operator" "")
17697 (match_operand:DI 2 "register_operand" "")
17698 (match_operand:DI 3 "const_int_operand" "")]
17700 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17702 ;; We can't represent the LT test directly. Do this by swapping the operands.
17705 [(set (match_operand:SF 0 "fp_register_operand" "")
17706 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17707 (match_operand:SF 2 "register_operand" ""))
17708 (match_operand:SF 3 "register_operand" "")
17709 (match_operand:SF 4 "register_operand" "")))
17710 (clobber (reg:CC FLAGS_REG))]
17712 && ((operands_match_p (operands[1], operands[3])
17713 && operands_match_p (operands[2], operands[4]))
17714 || (operands_match_p (operands[1], operands[4])
17715 && operands_match_p (operands[2], operands[3])))"
17716 [(set (reg:CCFP FLAGS_REG)
17717 (compare:CCFP (match_dup 2)
17720 (if_then_else:SF (ge (reg:CCFP FLAGS_REG) (const_int 0))
17724 (define_insn "*minsf_sse"
17725 [(set (match_operand:SF 0 "register_operand" "=x")
17726 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
17727 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17730 "TARGET_SSE && reload_completed"
17731 "minss\t{%2, %0|%0, %2}"
17732 [(set_attr "type" "sse")
17733 (set_attr "mode" "SF")])
17735 (define_expand "mindf3"
17737 (set (match_operand:DF 0 "register_operand" "")
17738 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17739 (match_operand:DF 2 "nonimmediate_operand" ""))
17742 (clobber (reg:CC FLAGS_REG))])]
17743 "TARGET_SSE2 && TARGET_SSE_MATH"
17746 (define_insn "*mindf"
17747 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17748 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17749 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17752 (clobber (reg:CC FLAGS_REG))]
17753 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
17756 (define_insn "*mindf_nonieee"
17757 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17758 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17759 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17762 (clobber (reg:CC FLAGS_REG))]
17763 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17764 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17768 [(set (match_operand:DF 0 "register_operand" "")
17769 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17770 (match_operand:DF 2 "nonimmediate_operand" ""))
17771 (match_operand:DF 3 "register_operand" "")
17772 (match_operand:DF 4 "nonimmediate_operand" "")))
17773 (clobber (reg:CC FLAGS_REG))]
17774 "SSE_REG_P (operands[0]) && reload_completed
17775 && ((operands_match_p (operands[1], operands[3])
17776 && operands_match_p (operands[2], operands[4]))
17777 || (operands_match_p (operands[1], operands[4])
17778 && operands_match_p (operands[2], operands[3])))"
17779 [(set (match_dup 0)
17780 (if_then_else:DF (lt (match_dup 1)
17785 ;; We can't represent the LT test directly. Do this by swapping the operands.
17787 [(set (match_operand:DF 0 "fp_register_operand" "")
17788 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17789 (match_operand:DF 2 "register_operand" ""))
17790 (match_operand:DF 3 "register_operand" "")
17791 (match_operand:DF 4 "register_operand" "")))
17792 (clobber (reg:CC FLAGS_REG))]
17794 && ((operands_match_p (operands[1], operands[3])
17795 && operands_match_p (operands[2], operands[4]))
17796 || (operands_match_p (operands[1], operands[4])
17797 && operands_match_p (operands[2], operands[3])))"
17798 [(set (reg:CCFP FLAGS_REG)
17799 (compare:CCFP (match_dup 2)
17802 (if_then_else:DF (ge (reg:CCFP FLAGS_REG) (const_int 0))
17806 (define_insn "*mindf_sse"
17807 [(set (match_operand:DF 0 "register_operand" "=Y")
17808 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
17809 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17812 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17813 "minsd\t{%2, %0|%0, %2}"
17814 [(set_attr "type" "sse")
17815 (set_attr "mode" "DF")])
17817 (define_expand "maxsf3"
17819 (set (match_operand:SF 0 "register_operand" "")
17820 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17821 (match_operand:SF 2 "nonimmediate_operand" ""))
17824 (clobber (reg:CC FLAGS_REG))])]
17828 (define_insn "*maxsf"
17829 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17830 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
17831 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17834 (clobber (reg:CC FLAGS_REG))]
17835 "TARGET_SSE && TARGET_IEEE_FP"
17838 (define_insn "*maxsf_nonieee"
17839 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17840 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17841 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17844 (clobber (reg:CC FLAGS_REG))]
17845 "TARGET_SSE && !TARGET_IEEE_FP
17846 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17850 [(set (match_operand:SF 0 "register_operand" "")
17851 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17852 (match_operand:SF 2 "nonimmediate_operand" ""))
17853 (match_operand:SF 3 "register_operand" "")
17854 (match_operand:SF 4 "nonimmediate_operand" "")))
17855 (clobber (reg:CC FLAGS_REG))]
17856 "SSE_REG_P (operands[0]) && reload_completed
17857 && ((operands_match_p (operands[1], operands[3])
17858 && operands_match_p (operands[2], operands[4]))
17859 || (operands_match_p (operands[1], operands[4])
17860 && operands_match_p (operands[2], operands[3])))"
17861 [(set (match_dup 0)
17862 (if_then_else:SF (gt (match_dup 1)
17868 [(set (match_operand:SF 0 "fp_register_operand" "")
17869 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17870 (match_operand:SF 2 "register_operand" ""))
17871 (match_operand:SF 3 "register_operand" "")
17872 (match_operand:SF 4 "register_operand" "")))
17873 (clobber (reg:CC FLAGS_REG))]
17875 && ((operands_match_p (operands[1], operands[3])
17876 && operands_match_p (operands[2], operands[4]))
17877 || (operands_match_p (operands[1], operands[4])
17878 && operands_match_p (operands[2], operands[3])))"
17879 [(set (reg:CCFP FLAGS_REG)
17880 (compare:CCFP (match_dup 1)
17883 (if_then_else:SF (gt (reg:CCFP FLAGS_REG) (const_int 0))
17887 (define_insn "*maxsf_sse"
17888 [(set (match_operand:SF 0 "register_operand" "=x")
17889 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
17890 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17893 "TARGET_SSE && reload_completed"
17894 "maxss\t{%2, %0|%0, %2}"
17895 [(set_attr "type" "sse")
17896 (set_attr "mode" "SF")])
17898 (define_expand "maxdf3"
17900 (set (match_operand:DF 0 "register_operand" "")
17901 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17902 (match_operand:DF 2 "nonimmediate_operand" ""))
17905 (clobber (reg:CC FLAGS_REG))])]
17906 "TARGET_SSE2 && TARGET_SSE_MATH"
17909 (define_insn "*maxdf"
17910 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17911 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17912 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17915 (clobber (reg:CC FLAGS_REG))]
17916 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
17919 (define_insn "*maxdf_nonieee"
17920 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17921 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17922 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17925 (clobber (reg:CC FLAGS_REG))]
17926 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17927 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17931 [(set (match_operand:DF 0 "register_operand" "")
17932 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17933 (match_operand:DF 2 "nonimmediate_operand" ""))
17934 (match_operand:DF 3 "register_operand" "")
17935 (match_operand:DF 4 "nonimmediate_operand" "")))
17936 (clobber (reg:CC FLAGS_REG))]
17937 "SSE_REG_P (operands[0]) && reload_completed
17938 && ((operands_match_p (operands[1], operands[3])
17939 && operands_match_p (operands[2], operands[4]))
17940 || (operands_match_p (operands[1], operands[4])
17941 && operands_match_p (operands[2], operands[3])))"
17942 [(set (match_dup 0)
17943 (if_then_else:DF (gt (match_dup 1)
17949 [(set (match_operand:DF 0 "fp_register_operand" "")
17950 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17951 (match_operand:DF 2 "register_operand" ""))
17952 (match_operand:DF 3 "register_operand" "")
17953 (match_operand:DF 4 "register_operand" "")))
17954 (clobber (reg:CC FLAGS_REG))]
17956 && ((operands_match_p (operands[1], operands[3])
17957 && operands_match_p (operands[2], operands[4]))
17958 || (operands_match_p (operands[1], operands[4])
17959 && operands_match_p (operands[2], operands[3])))"
17960 [(set (reg:CCFP FLAGS_REG)
17961 (compare:CCFP (match_dup 1)
17964 (if_then_else:DF (gt (reg:CCFP FLAGS_REG) (const_int 0))
17968 (define_insn "*maxdf_sse"
17969 [(set (match_operand:DF 0 "register_operand" "=Y")
17970 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
17971 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17974 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17975 "maxsd\t{%2, %0|%0, %2}"
17976 [(set_attr "type" "sse")
17977 (set_attr "mode" "DF")])
17979 ;; Misc patterns (?)
17981 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
17982 ;; Otherwise there will be nothing to keep
17984 ;; [(set (reg ebp) (reg esp))]
17985 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
17986 ;; (clobber (eflags)]
17987 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
17989 ;; in proper program order.
17990 (define_insn "pro_epilogue_adjust_stack_1"
17991 [(set (match_operand:SI 0 "register_operand" "=r,r")
17992 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17993 (match_operand:SI 2 "immediate_operand" "i,i")))
17994 (clobber (reg:CC FLAGS_REG))
17995 (clobber (mem:BLK (scratch)))]
17998 switch (get_attr_type (insn))
18001 return "mov{l}\t{%1, %0|%0, %1}";
18004 if (GET_CODE (operands[2]) == CONST_INT
18005 && (INTVAL (operands[2]) == 128
18006 || (INTVAL (operands[2]) < 0
18007 && INTVAL (operands[2]) != -128)))
18009 operands[2] = GEN_INT (-INTVAL (operands[2]));
18010 return "sub{l}\t{%2, %0|%0, %2}";
18012 return "add{l}\t{%2, %0|%0, %2}";
18015 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18016 return "lea{l}\t{%a2, %0|%0, %a2}";
18022 [(set (attr "type")
18023 (cond [(eq_attr "alternative" "0")
18024 (const_string "alu")
18025 (match_operand:SI 2 "const0_operand" "")
18026 (const_string "imov")
18028 (const_string "lea")))
18029 (set_attr "mode" "SI")])
18031 (define_insn "pro_epilogue_adjust_stack_rex64"
18032 [(set (match_operand:DI 0 "register_operand" "=r,r")
18033 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18034 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
18035 (clobber (reg:CC FLAGS_REG))
18036 (clobber (mem:BLK (scratch)))]
18039 switch (get_attr_type (insn))
18042 return "mov{q}\t{%1, %0|%0, %1}";
18045 if (GET_CODE (operands[2]) == CONST_INT
18046 /* Avoid overflows. */
18047 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
18048 && (INTVAL (operands[2]) == 128
18049 || (INTVAL (operands[2]) < 0
18050 && INTVAL (operands[2]) != -128)))
18052 operands[2] = GEN_INT (-INTVAL (operands[2]));
18053 return "sub{q}\t{%2, %0|%0, %2}";
18055 return "add{q}\t{%2, %0|%0, %2}";
18058 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18059 return "lea{q}\t{%a2, %0|%0, %a2}";
18065 [(set (attr "type")
18066 (cond [(eq_attr "alternative" "0")
18067 (const_string "alu")
18068 (match_operand:DI 2 "const0_operand" "")
18069 (const_string "imov")
18071 (const_string "lea")))
18072 (set_attr "mode" "DI")])
18074 (define_insn "pro_epilogue_adjust_stack_rex64_2"
18075 [(set (match_operand:DI 0 "register_operand" "=r,r")
18076 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18077 (match_operand:DI 3 "immediate_operand" "i,i")))
18078 (use (match_operand:DI 2 "register_operand" "r,r"))
18079 (clobber (reg:CC FLAGS_REG))
18080 (clobber (mem:BLK (scratch)))]
18083 switch (get_attr_type (insn))
18086 return "add{q}\t{%2, %0|%0, %2}";
18089 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
18090 return "lea{q}\t{%a2, %0|%0, %a2}";
18096 [(set_attr "type" "alu,lea")
18097 (set_attr "mode" "DI")])
18099 ;; Placeholder for the conditional moves. This one is split either to SSE
18100 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
18101 ;; fact is that compares supported by the cmp??ss instructions are exactly
18102 ;; swapped of those supported by cmove sequence.
18103 ;; The EQ/NE comparisons also needs bit care, since they are not directly
18104 ;; supported by i387 comparisons and we do need to emit two conditional moves
18107 (define_insn "sse_movsfcc"
18108 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
18109 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18110 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
18111 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
18112 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
18113 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
18114 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18115 (clobber (reg:CC FLAGS_REG))]
18117 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18118 /* Avoid combine from being smart and converting min/max
18119 instruction patterns into conditional moves. */
18120 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18121 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18122 || !rtx_equal_p (operands[4], operands[2])
18123 || !rtx_equal_p (operands[5], operands[3]))
18124 && (!TARGET_IEEE_FP
18125 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18128 (define_insn "sse_movsfcc_eq"
18129 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
18130 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
18131 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
18132 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
18133 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
18134 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
18135 (clobber (reg:CC FLAGS_REG))]
18137 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18140 (define_insn "sse_movdfcc"
18141 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
18142 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18143 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
18144 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
18145 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
18146 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
18147 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18148 (clobber (reg:CC FLAGS_REG))]
18150 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18151 /* Avoid combine from being smart and converting min/max
18152 instruction patterns into conditional moves. */
18153 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18154 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18155 || !rtx_equal_p (operands[4], operands[2])
18156 || !rtx_equal_p (operands[5], operands[3]))
18157 && (!TARGET_IEEE_FP
18158 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18161 (define_insn "sse_movdfcc_eq"
18162 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
18163 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
18164 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
18165 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
18166 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
18167 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
18168 (clobber (reg:CC FLAGS_REG))]
18170 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18173 ;; For non-sse moves just expand the usual cmove sequence.
18175 [(set (match_operand 0 "register_operand" "")
18176 (if_then_else (match_operator 1 "comparison_operator"
18177 [(match_operand 4 "nonimmediate_operand" "")
18178 (match_operand 5 "register_operand" "")])
18179 (match_operand 2 "nonimmediate_operand" "")
18180 (match_operand 3 "nonimmediate_operand" "")))
18181 (clobber (match_operand 6 "" ""))
18182 (clobber (reg:CC FLAGS_REG))]
18183 "!SSE_REG_P (operands[0]) && reload_completed
18184 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
18187 ix86_compare_op0 = operands[5];
18188 ix86_compare_op1 = operands[4];
18189 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
18190 VOIDmode, operands[5], operands[4]);
18191 ix86_expand_fp_movcc (operands);
18195 ;; Split SSE based conditional move into sequence:
18196 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
18197 ;; and op2, op0 - zero op2 if comparison was false
18198 ;; nand op0, op3 - load op3 to op0 if comparison was false
18199 ;; or op2, op0 - get the nonzero one into the result.
18201 [(set (match_operand:SF 0 "register_operand" "")
18202 (if_then_else (match_operator:SF 1 "sse_comparison_operator"
18203 [(match_operand:SF 4 "register_operand" "")
18204 (match_operand:SF 5 "nonimmediate_operand" "")])
18205 (match_operand:SF 2 "register_operand" "")
18206 (match_operand:SF 3 "register_operand" "")))
18207 (clobber (match_operand 6 "" ""))
18208 (clobber (reg:CC FLAGS_REG))]
18209 "SSE_REG_P (operands[0]) && reload_completed"
18210 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18211 (set (match_dup 2) (and:V4SF (match_dup 2)
18213 (set (match_dup 8) (and:V4SF (not:V4SF (match_dup 8))
18215 (set (match_dup 0) (ior:V4SF (match_dup 6)
18218 /* If op2 == op3, op3 would be clobbered before it is used. */
18219 if (operands_match_p (operands[2], operands[3]))
18221 emit_move_insn (operands[0], operands[2]);
18225 PUT_MODE (operands[1], GET_MODE (operands[0]));
18226 if (operands_match_p (operands[0], operands[4]))
18227 operands[6] = operands[4], operands[7] = operands[2];
18229 operands[6] = operands[2], operands[7] = operands[4];
18230 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18231 operands[2] = simplify_gen_subreg (V4SFmode, operands[2], SFmode, 0);
18232 operands[3] = simplify_gen_subreg (V4SFmode, operands[3], SFmode, 0);
18233 operands[8] = simplify_gen_subreg (V4SFmode, operands[4], SFmode, 0);
18234 operands[6] = simplify_gen_subreg (V4SFmode, operands[6], SFmode, 0);
18235 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18239 [(set (match_operand:DF 0 "register_operand" "")
18240 (if_then_else (match_operator:DF 1 "sse_comparison_operator"
18241 [(match_operand:DF 4 "register_operand" "")
18242 (match_operand:DF 5 "nonimmediate_operand" "")])
18243 (match_operand:DF 2 "register_operand" "")
18244 (match_operand:DF 3 "register_operand" "")))
18245 (clobber (match_operand 6 "" ""))
18246 (clobber (reg:CC FLAGS_REG))]
18247 "SSE_REG_P (operands[0]) && reload_completed"
18248 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18249 (set (match_dup 2) (and:V2DF (match_dup 2)
18251 (set (match_dup 8) (and:V2DF (not:V2DF (match_dup 8))
18253 (set (match_dup 0) (ior:V2DF (match_dup 6)
18256 if (GET_MODE (operands[2]) == DFmode
18257 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
18259 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18260 emit_insn (gen_sse2_unpcklpd (op, op, op));
18261 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18262 emit_insn (gen_sse2_unpcklpd (op, op, op));
18265 /* If op2 == op3, op3 would be clobbered before it is used. */
18266 if (operands_match_p (operands[2], operands[3]))
18268 emit_move_insn (operands[0], operands[2]);
18272 PUT_MODE (operands[1], GET_MODE (operands[0]));
18273 if (operands_match_p (operands[0], operands[4]))
18274 operands[6] = operands[4], operands[7] = operands[2];
18276 operands[6] = operands[2], operands[7] = operands[4];
18277 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18278 operands[2] = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18279 operands[3] = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18280 operands[8] = simplify_gen_subreg (V2DFmode, operands[4], DFmode, 0);
18281 operands[6] = simplify_gen_subreg (V2DFmode, operands[6], DFmode, 0);
18282 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18285 ;; Special case of conditional move we can handle effectively.
18286 ;; Do not brother with the integer/floating point case, since these are
18287 ;; bot considerably slower, unlike in the generic case.
18288 (define_insn "*sse_movsfcc_const0_1"
18289 [(set (match_operand:SF 0 "register_operand" "=&x")
18290 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18291 [(match_operand:SF 4 "register_operand" "0")
18292 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18293 (match_operand:SF 2 "register_operand" "x")
18294 (match_operand:SF 3 "const0_operand" "X")))]
18298 (define_insn "*sse_movsfcc_const0_2"
18299 [(set (match_operand:SF 0 "register_operand" "=&x")
18300 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18301 [(match_operand:SF 4 "register_operand" "0")
18302 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18303 (match_operand:SF 2 "const0_operand" "X")
18304 (match_operand:SF 3 "register_operand" "x")))]
18308 (define_insn "*sse_movsfcc_const0_3"
18309 [(set (match_operand:SF 0 "register_operand" "=&x")
18310 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18311 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18312 (match_operand:SF 5 "register_operand" "0")])
18313 (match_operand:SF 2 "register_operand" "x")
18314 (match_operand:SF 3 "const0_operand" "X")))]
18318 (define_insn "*sse_movsfcc_const0_4"
18319 [(set (match_operand:SF 0 "register_operand" "=&x")
18320 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18321 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18322 (match_operand:SF 5 "register_operand" "0")])
18323 (match_operand:SF 2 "const0_operand" "X")
18324 (match_operand:SF 3 "register_operand" "x")))]
18328 (define_insn "*sse_movdfcc_const0_1"
18329 [(set (match_operand:DF 0 "register_operand" "=&Y")
18330 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18331 [(match_operand:DF 4 "register_operand" "0")
18332 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18333 (match_operand:DF 2 "register_operand" "Y")
18334 (match_operand:DF 3 "const0_operand" "X")))]
18338 (define_insn "*sse_movdfcc_const0_2"
18339 [(set (match_operand:DF 0 "register_operand" "=&Y")
18340 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18341 [(match_operand:DF 4 "register_operand" "0")
18342 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18343 (match_operand:DF 2 "const0_operand" "X")
18344 (match_operand:DF 3 "register_operand" "Y")))]
18348 (define_insn "*sse_movdfcc_const0_3"
18349 [(set (match_operand:DF 0 "register_operand" "=&Y")
18350 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18351 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18352 (match_operand:DF 5 "register_operand" "0")])
18353 (match_operand:DF 2 "register_operand" "Y")
18354 (match_operand:DF 3 "const0_operand" "X")))]
18358 (define_insn "*sse_movdfcc_const0_4"
18359 [(set (match_operand:DF 0 "register_operand" "=&Y")
18360 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18361 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18362 (match_operand:DF 5 "register_operand" "0")])
18363 (match_operand:DF 2 "const0_operand" "X")
18364 (match_operand:DF 3 "register_operand" "Y")))]
18369 [(set (match_operand:SF 0 "register_operand" "")
18370 (if_then_else (match_operator 1 "comparison_operator"
18371 [(match_operand:SF 4 "nonimmediate_operand" "")
18372 (match_operand:SF 5 "nonimmediate_operand" "")])
18373 (match_operand:SF 2 "nonmemory_operand" "")
18374 (match_operand:SF 3 "nonmemory_operand" "")))]
18375 "SSE_REG_P (operands[0]) && reload_completed
18376 && (const0_operand (operands[2], GET_MODE (operands[0]))
18377 || const0_operand (operands[3], GET_MODE (operands[0])))"
18378 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18379 (set (match_dup 8) (and:V4SF (match_dup 6) (match_dup 7)))]
18381 PUT_MODE (operands[1], GET_MODE (operands[0]));
18382 if (!sse_comparison_operator (operands[1], VOIDmode)
18383 || !rtx_equal_p (operands[0], operands[4]))
18385 rtx tmp = operands[5];
18386 operands[5] = operands[4];
18388 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18390 if (!rtx_equal_p (operands[0], operands[4]))
18392 operands[8] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18393 if (const0_operand (operands[2], GET_MODE (operands[2])))
18395 operands[7] = operands[3];
18396 operands[6] = gen_rtx_NOT (V4SFmode, operands[8]);
18400 operands[7] = operands[2];
18401 operands[6] = operands[8];
18403 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18407 [(set (match_operand:DF 0 "register_operand" "")
18408 (if_then_else (match_operator 1 "comparison_operator"
18409 [(match_operand:DF 4 "nonimmediate_operand" "")
18410 (match_operand:DF 5 "nonimmediate_operand" "")])
18411 (match_operand:DF 2 "nonmemory_operand" "")
18412 (match_operand:DF 3 "nonmemory_operand" "")))]
18413 "SSE_REG_P (operands[0]) && reload_completed
18414 && (const0_operand (operands[2], GET_MODE (operands[0]))
18415 || const0_operand (operands[3], GET_MODE (operands[0])))"
18416 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18417 (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))]
18419 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
18420 && GET_MODE (operands[2]) == DFmode)
18422 if (REG_P (operands[2]))
18424 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18425 emit_insn (gen_sse2_unpcklpd (op, op, op));
18427 if (REG_P (operands[3]))
18429 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18430 emit_insn (gen_sse2_unpcklpd (op, op, op));
18433 PUT_MODE (operands[1], GET_MODE (operands[0]));
18434 if (!sse_comparison_operator (operands[1], VOIDmode)
18435 || !rtx_equal_p (operands[0], operands[4]))
18437 rtx tmp = operands[5];
18438 operands[5] = operands[4];
18440 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18442 if (!rtx_equal_p (operands[0], operands[4]))
18444 operands[8] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18445 if (const0_operand (operands[2], GET_MODE (operands[2])))
18447 operands[7] = operands[3];
18448 operands[6] = gen_rtx_NOT (V2DFmode, operands[8]);
18452 operands[7] = operands[2];
18453 operands[6] = operands[8];
18455 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18458 (define_expand "allocate_stack_worker"
18459 [(match_operand:SI 0 "register_operand" "")]
18460 "TARGET_STACK_PROBE"
18462 if (reload_completed)
18465 emit_insn (gen_allocate_stack_worker_rex64_postreload (operands[0]));
18467 emit_insn (gen_allocate_stack_worker_postreload (operands[0]));
18472 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
18474 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
18479 (define_insn "allocate_stack_worker_1"
18480 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18481 UNSPECV_STACK_PROBE)
18482 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18483 (clobber (match_scratch:SI 1 "=0"))
18484 (clobber (reg:CC FLAGS_REG))]
18485 "!TARGET_64BIT && TARGET_STACK_PROBE"
18487 [(set_attr "type" "multi")
18488 (set_attr "length" "5")])
18490 (define_expand "allocate_stack_worker_postreload"
18491 [(parallel [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18492 UNSPECV_STACK_PROBE)
18493 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18494 (clobber (match_dup 0))
18495 (clobber (reg:CC FLAGS_REG))])]
18499 (define_insn "allocate_stack_worker_rex64"
18500 [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18501 UNSPECV_STACK_PROBE)
18502 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18503 (clobber (match_scratch:DI 1 "=0"))
18504 (clobber (reg:CC FLAGS_REG))]
18505 "TARGET_64BIT && TARGET_STACK_PROBE"
18507 [(set_attr "type" "multi")
18508 (set_attr "length" "5")])
18510 (define_expand "allocate_stack_worker_rex64_postreload"
18511 [(parallel [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18512 UNSPECV_STACK_PROBE)
18513 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18514 (clobber (match_dup 0))
18515 (clobber (reg:CC FLAGS_REG))])]
18519 (define_expand "allocate_stack"
18520 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
18521 (minus:SI (reg:SI SP_REG)
18522 (match_operand:SI 1 "general_operand" "")))
18523 (clobber (reg:CC FLAGS_REG))])
18524 (parallel [(set (reg:SI SP_REG)
18525 (minus:SI (reg:SI SP_REG) (match_dup 1)))
18526 (clobber (reg:CC FLAGS_REG))])]
18527 "TARGET_STACK_PROBE"
18529 #ifdef CHECK_STACK_LIMIT
18530 if (GET_CODE (operands[1]) == CONST_INT
18531 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
18532 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
18536 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
18539 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
18543 (define_expand "builtin_setjmp_receiver"
18544 [(label_ref (match_operand 0 "" ""))]
18545 "!TARGET_64BIT && flag_pic"
18547 emit_insn (gen_set_got (pic_offset_table_rtx));
18551 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
18554 [(set (match_operand 0 "register_operand" "")
18555 (match_operator 3 "promotable_binary_operator"
18556 [(match_operand 1 "register_operand" "")
18557 (match_operand 2 "aligned_operand" "")]))
18558 (clobber (reg:CC FLAGS_REG))]
18559 "! TARGET_PARTIAL_REG_STALL && reload_completed
18560 && ((GET_MODE (operands[0]) == HImode
18561 && ((!optimize_size && !TARGET_FAST_PREFIX)
18562 || GET_CODE (operands[2]) != CONST_INT
18563 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
18564 || (GET_MODE (operands[0]) == QImode
18565 && (TARGET_PROMOTE_QImode || optimize_size)))"
18566 [(parallel [(set (match_dup 0)
18567 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18568 (clobber (reg:CC FLAGS_REG))])]
18569 "operands[0] = gen_lowpart (SImode, operands[0]);
18570 operands[1] = gen_lowpart (SImode, operands[1]);
18571 if (GET_CODE (operands[3]) != ASHIFT)
18572 operands[2] = gen_lowpart (SImode, operands[2]);
18573 PUT_MODE (operands[3], SImode);")
18575 ; Promote the QImode tests, as i386 has encoding of the AND
18576 ; instruction with 32-bit sign-extended immediate and thus the
18577 ; instruction size is unchanged, except in the %eax case for
18578 ; which it is increased by one byte, hence the ! optimize_size.
18580 [(set (match_operand 0 "flags_reg_operand" "")
18581 (match_operator 2 "compare_operator"
18582 [(and (match_operand 3 "aligned_operand" "")
18583 (match_operand 4 "const_int_operand" ""))
18585 (set (match_operand 1 "register_operand" "")
18586 (and (match_dup 3) (match_dup 4)))]
18587 "! TARGET_PARTIAL_REG_STALL && reload_completed
18588 /* Ensure that the operand will remain sign-extended immediate. */
18589 && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode)
18591 && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
18592 || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))"
18593 [(parallel [(set (match_dup 0)
18594 (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4))
18597 (and:SI (match_dup 3) (match_dup 4)))])]
18600 = gen_int_mode (INTVAL (operands[4])
18601 & GET_MODE_MASK (GET_MODE (operands[1])), SImode);
18602 operands[1] = gen_lowpart (SImode, operands[1]);
18603 operands[3] = gen_lowpart (SImode, operands[3]);
18606 ; Don't promote the QImode tests, as i386 doesn't have encoding of
18607 ; the TEST instruction with 32-bit sign-extended immediate and thus
18608 ; the instruction size would at least double, which is not what we
18609 ; want even with ! optimize_size.
18611 [(set (match_operand 0 "flags_reg_operand" "")
18612 (match_operator 1 "compare_operator"
18613 [(and (match_operand:HI 2 "aligned_operand" "")
18614 (match_operand:HI 3 "const_int_operand" ""))
18616 "! TARGET_PARTIAL_REG_STALL && reload_completed
18617 /* Ensure that the operand will remain sign-extended immediate. */
18618 && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)
18619 && ! TARGET_FAST_PREFIX
18620 && ! optimize_size"
18621 [(set (match_dup 0)
18622 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
18626 = gen_int_mode (INTVAL (operands[3])
18627 & GET_MODE_MASK (GET_MODE (operands[2])), SImode);
18628 operands[2] = gen_lowpart (SImode, operands[2]);
18632 [(set (match_operand 0 "register_operand" "")
18633 (neg (match_operand 1 "register_operand" "")))
18634 (clobber (reg:CC FLAGS_REG))]
18635 "! TARGET_PARTIAL_REG_STALL && reload_completed
18636 && (GET_MODE (operands[0]) == HImode
18637 || (GET_MODE (operands[0]) == QImode
18638 && (TARGET_PROMOTE_QImode || optimize_size)))"
18639 [(parallel [(set (match_dup 0)
18640 (neg:SI (match_dup 1)))
18641 (clobber (reg:CC FLAGS_REG))])]
18642 "operands[0] = gen_lowpart (SImode, operands[0]);
18643 operands[1] = gen_lowpart (SImode, operands[1]);")
18646 [(set (match_operand 0 "register_operand" "")
18647 (not (match_operand 1 "register_operand" "")))]
18648 "! TARGET_PARTIAL_REG_STALL && reload_completed
18649 && (GET_MODE (operands[0]) == HImode
18650 || (GET_MODE (operands[0]) == QImode
18651 && (TARGET_PROMOTE_QImode || optimize_size)))"
18652 [(set (match_dup 0)
18653 (not:SI (match_dup 1)))]
18654 "operands[0] = gen_lowpart (SImode, operands[0]);
18655 operands[1] = gen_lowpart (SImode, operands[1]);")
18658 [(set (match_operand 0 "register_operand" "")
18659 (if_then_else (match_operator 1 "comparison_operator"
18660 [(reg FLAGS_REG) (const_int 0)])
18661 (match_operand 2 "register_operand" "")
18662 (match_operand 3 "register_operand" "")))]
18663 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
18664 && (GET_MODE (operands[0]) == HImode
18665 || (GET_MODE (operands[0]) == QImode
18666 && (TARGET_PROMOTE_QImode || optimize_size)))"
18667 [(set (match_dup 0)
18668 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
18669 "operands[0] = gen_lowpart (SImode, operands[0]);
18670 operands[2] = gen_lowpart (SImode, operands[2]);
18671 operands[3] = gen_lowpart (SImode, operands[3]);")
18674 ;; RTL Peephole optimizations, run before sched2. These primarily look to
18675 ;; transform a complex memory operation into two memory to register operations.
18677 ;; Don't push memory operands
18679 [(set (match_operand:SI 0 "push_operand" "")
18680 (match_operand:SI 1 "memory_operand" ""))
18681 (match_scratch:SI 2 "r")]
18682 "! optimize_size && ! TARGET_PUSH_MEMORY"
18683 [(set (match_dup 2) (match_dup 1))
18684 (set (match_dup 0) (match_dup 2))]
18688 [(set (match_operand:DI 0 "push_operand" "")
18689 (match_operand:DI 1 "memory_operand" ""))
18690 (match_scratch:DI 2 "r")]
18691 "! optimize_size && ! TARGET_PUSH_MEMORY"
18692 [(set (match_dup 2) (match_dup 1))
18693 (set (match_dup 0) (match_dup 2))]
18696 ;; We need to handle SFmode only, because DFmode and XFmode is split to
18699 [(set (match_operand:SF 0 "push_operand" "")
18700 (match_operand:SF 1 "memory_operand" ""))
18701 (match_scratch:SF 2 "r")]
18702 "! optimize_size && ! TARGET_PUSH_MEMORY"
18703 [(set (match_dup 2) (match_dup 1))
18704 (set (match_dup 0) (match_dup 2))]
18708 [(set (match_operand:HI 0 "push_operand" "")
18709 (match_operand:HI 1 "memory_operand" ""))
18710 (match_scratch:HI 2 "r")]
18711 "! optimize_size && ! TARGET_PUSH_MEMORY"
18712 [(set (match_dup 2) (match_dup 1))
18713 (set (match_dup 0) (match_dup 2))]
18717 [(set (match_operand:QI 0 "push_operand" "")
18718 (match_operand:QI 1 "memory_operand" ""))
18719 (match_scratch:QI 2 "q")]
18720 "! optimize_size && ! TARGET_PUSH_MEMORY"
18721 [(set (match_dup 2) (match_dup 1))
18722 (set (match_dup 0) (match_dup 2))]
18725 ;; Don't move an immediate directly to memory when the instruction
18728 [(match_scratch:SI 1 "r")
18729 (set (match_operand:SI 0 "memory_operand" "")
18732 && ! TARGET_USE_MOV0
18733 && TARGET_SPLIT_LONG_MOVES
18734 && get_attr_length (insn) >= ix86_cost->large_insn
18735 && peep2_regno_dead_p (0, FLAGS_REG)"
18736 [(parallel [(set (match_dup 1) (const_int 0))
18737 (clobber (reg:CC FLAGS_REG))])
18738 (set (match_dup 0) (match_dup 1))]
18742 [(match_scratch:HI 1 "r")
18743 (set (match_operand:HI 0 "memory_operand" "")
18746 && ! TARGET_USE_MOV0
18747 && TARGET_SPLIT_LONG_MOVES
18748 && get_attr_length (insn) >= ix86_cost->large_insn
18749 && peep2_regno_dead_p (0, FLAGS_REG)"
18750 [(parallel [(set (match_dup 2) (const_int 0))
18751 (clobber (reg:CC FLAGS_REG))])
18752 (set (match_dup 0) (match_dup 1))]
18753 "operands[2] = gen_lowpart (SImode, operands[1]);")
18756 [(match_scratch:QI 1 "q")
18757 (set (match_operand:QI 0 "memory_operand" "")
18760 && ! TARGET_USE_MOV0
18761 && TARGET_SPLIT_LONG_MOVES
18762 && get_attr_length (insn) >= ix86_cost->large_insn
18763 && peep2_regno_dead_p (0, FLAGS_REG)"
18764 [(parallel [(set (match_dup 2) (const_int 0))
18765 (clobber (reg:CC FLAGS_REG))])
18766 (set (match_dup 0) (match_dup 1))]
18767 "operands[2] = gen_lowpart (SImode, operands[1]);")
18770 [(match_scratch:SI 2 "r")
18771 (set (match_operand:SI 0 "memory_operand" "")
18772 (match_operand:SI 1 "immediate_operand" ""))]
18774 && get_attr_length (insn) >= ix86_cost->large_insn
18775 && TARGET_SPLIT_LONG_MOVES"
18776 [(set (match_dup 2) (match_dup 1))
18777 (set (match_dup 0) (match_dup 2))]
18781 [(match_scratch:HI 2 "r")
18782 (set (match_operand:HI 0 "memory_operand" "")
18783 (match_operand:HI 1 "immediate_operand" ""))]
18784 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18785 && TARGET_SPLIT_LONG_MOVES"
18786 [(set (match_dup 2) (match_dup 1))
18787 (set (match_dup 0) (match_dup 2))]
18791 [(match_scratch:QI 2 "q")
18792 (set (match_operand:QI 0 "memory_operand" "")
18793 (match_operand:QI 1 "immediate_operand" ""))]
18794 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18795 && TARGET_SPLIT_LONG_MOVES"
18796 [(set (match_dup 2) (match_dup 1))
18797 (set (match_dup 0) (match_dup 2))]
18800 ;; Don't compare memory with zero, load and use a test instead.
18802 [(set (match_operand 0 "flags_reg_operand" "")
18803 (match_operator 1 "compare_operator"
18804 [(match_operand:SI 2 "memory_operand" "")
18806 (match_scratch:SI 3 "r")]
18807 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
18808 [(set (match_dup 3) (match_dup 2))
18809 (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
18812 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
18813 ;; Don't split NOTs with a displacement operand, because resulting XOR
18814 ;; will not be pairable anyway.
18816 ;; On AMD K6, NOT is vector decoded with memory operand that cannot be
18817 ;; represented using a modRM byte. The XOR replacement is long decoded,
18818 ;; so this split helps here as well.
18820 ;; Note: Can't do this as a regular split because we can't get proper
18821 ;; lifetime information then.
18824 [(set (match_operand:SI 0 "nonimmediate_operand" "")
18825 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
18827 && peep2_regno_dead_p (0, FLAGS_REG)
18828 && ((TARGET_PENTIUM
18829 && (GET_CODE (operands[0]) != MEM
18830 || !memory_displacement_operand (operands[0], SImode)))
18831 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
18832 [(parallel [(set (match_dup 0)
18833 (xor:SI (match_dup 1) (const_int -1)))
18834 (clobber (reg:CC FLAGS_REG))])]
18838 [(set (match_operand:HI 0 "nonimmediate_operand" "")
18839 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
18841 && peep2_regno_dead_p (0, FLAGS_REG)
18842 && ((TARGET_PENTIUM
18843 && (GET_CODE (operands[0]) != MEM
18844 || !memory_displacement_operand (operands[0], HImode)))
18845 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
18846 [(parallel [(set (match_dup 0)
18847 (xor:HI (match_dup 1) (const_int -1)))
18848 (clobber (reg:CC FLAGS_REG))])]
18852 [(set (match_operand:QI 0 "nonimmediate_operand" "")
18853 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
18855 && peep2_regno_dead_p (0, FLAGS_REG)
18856 && ((TARGET_PENTIUM
18857 && (GET_CODE (operands[0]) != MEM
18858 || !memory_displacement_operand (operands[0], QImode)))
18859 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
18860 [(parallel [(set (match_dup 0)
18861 (xor:QI (match_dup 1) (const_int -1)))
18862 (clobber (reg:CC FLAGS_REG))])]
18865 ;; Non pairable "test imm, reg" instructions can be translated to
18866 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
18867 ;; byte opcode instead of two, have a short form for byte operands),
18868 ;; so do it for other CPUs as well. Given that the value was dead,
18869 ;; this should not create any new dependencies. Pass on the sub-word
18870 ;; versions if we're concerned about partial register stalls.
18873 [(set (match_operand 0 "flags_reg_operand" "")
18874 (match_operator 1 "compare_operator"
18875 [(and:SI (match_operand:SI 2 "register_operand" "")
18876 (match_operand:SI 3 "immediate_operand" ""))
18878 "ix86_match_ccmode (insn, CCNOmode)
18879 && (true_regnum (operands[2]) != 0
18880 || (GET_CODE (operands[3]) == CONST_INT
18881 && CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'K')))
18882 && peep2_reg_dead_p (1, operands[2])"
18884 [(set (match_dup 0)
18885 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
18888 (and:SI (match_dup 2) (match_dup 3)))])]
18891 ;; We don't need to handle HImode case, because it will be promoted to SImode
18892 ;; on ! TARGET_PARTIAL_REG_STALL
18895 [(set (match_operand 0 "flags_reg_operand" "")
18896 (match_operator 1 "compare_operator"
18897 [(and:QI (match_operand:QI 2 "register_operand" "")
18898 (match_operand:QI 3 "immediate_operand" ""))
18900 "! TARGET_PARTIAL_REG_STALL
18901 && ix86_match_ccmode (insn, CCNOmode)
18902 && true_regnum (operands[2]) != 0
18903 && peep2_reg_dead_p (1, operands[2])"
18905 [(set (match_dup 0)
18906 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
18909 (and:QI (match_dup 2) (match_dup 3)))])]
18913 [(set (match_operand 0 "flags_reg_operand" "")
18914 (match_operator 1 "compare_operator"
18917 (match_operand 2 "ext_register_operand" "")
18920 (match_operand 3 "const_int_operand" ""))
18922 "! TARGET_PARTIAL_REG_STALL
18923 && ix86_match_ccmode (insn, CCNOmode)
18924 && true_regnum (operands[2]) != 0
18925 && peep2_reg_dead_p (1, operands[2])"
18926 [(parallel [(set (match_dup 0)
18935 (set (zero_extract:SI (match_dup 2)
18946 ;; Don't do logical operations with memory inputs.
18948 [(match_scratch:SI 2 "r")
18949 (parallel [(set (match_operand:SI 0 "register_operand" "")
18950 (match_operator:SI 3 "arith_or_logical_operator"
18952 (match_operand:SI 1 "memory_operand" "")]))
18953 (clobber (reg:CC FLAGS_REG))])]
18954 "! optimize_size && ! TARGET_READ_MODIFY"
18955 [(set (match_dup 2) (match_dup 1))
18956 (parallel [(set (match_dup 0)
18957 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
18958 (clobber (reg:CC FLAGS_REG))])]
18962 [(match_scratch:SI 2 "r")
18963 (parallel [(set (match_operand:SI 0 "register_operand" "")
18964 (match_operator:SI 3 "arith_or_logical_operator"
18965 [(match_operand:SI 1 "memory_operand" "")
18967 (clobber (reg:CC FLAGS_REG))])]
18968 "! optimize_size && ! TARGET_READ_MODIFY"
18969 [(set (match_dup 2) (match_dup 1))
18970 (parallel [(set (match_dup 0)
18971 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
18972 (clobber (reg:CC FLAGS_REG))])]
18975 ; Don't do logical operations with memory outputs
18977 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
18978 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
18979 ; the same decoder scheduling characteristics as the original.
18982 [(match_scratch:SI 2 "r")
18983 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18984 (match_operator:SI 3 "arith_or_logical_operator"
18986 (match_operand:SI 1 "nonmemory_operand" "")]))
18987 (clobber (reg:CC FLAGS_REG))])]
18988 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18989 [(set (match_dup 2) (match_dup 0))
18990 (parallel [(set (match_dup 2)
18991 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
18992 (clobber (reg:CC FLAGS_REG))])
18993 (set (match_dup 0) (match_dup 2))]
18997 [(match_scratch:SI 2 "r")
18998 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18999 (match_operator:SI 3 "arith_or_logical_operator"
19000 [(match_operand:SI 1 "nonmemory_operand" "")
19002 (clobber (reg:CC FLAGS_REG))])]
19003 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
19004 [(set (match_dup 2) (match_dup 0))
19005 (parallel [(set (match_dup 2)
19006 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
19007 (clobber (reg:CC FLAGS_REG))])
19008 (set (match_dup 0) (match_dup 2))]
19011 ;; Attempt to always use XOR for zeroing registers.
19013 [(set (match_operand 0 "register_operand" "")
19015 "(GET_MODE (operands[0]) == QImode
19016 || GET_MODE (operands[0]) == HImode
19017 || GET_MODE (operands[0]) == SImode
19018 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19019 && (! TARGET_USE_MOV0 || optimize_size)
19020 && peep2_regno_dead_p (0, FLAGS_REG)"
19021 [(parallel [(set (match_dup 0) (const_int 0))
19022 (clobber (reg:CC FLAGS_REG))])]
19023 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19027 [(set (strict_low_part (match_operand 0 "register_operand" ""))
19029 "(GET_MODE (operands[0]) == QImode
19030 || GET_MODE (operands[0]) == HImode)
19031 && (! TARGET_USE_MOV0 || optimize_size)
19032 && peep2_regno_dead_p (0, FLAGS_REG)"
19033 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
19034 (clobber (reg:CC FLAGS_REG))])])
19036 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
19038 [(set (match_operand 0 "register_operand" "")
19040 "(GET_MODE (operands[0]) == HImode
19041 || GET_MODE (operands[0]) == SImode
19042 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19043 && (optimize_size || TARGET_PENTIUM)
19044 && peep2_regno_dead_p (0, FLAGS_REG)"
19045 [(parallel [(set (match_dup 0) (const_int -1))
19046 (clobber (reg:CC FLAGS_REG))])]
19047 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19050 ;; Attempt to convert simple leas to adds. These can be created by
19053 [(set (match_operand:SI 0 "register_operand" "")
19054 (plus:SI (match_dup 0)
19055 (match_operand:SI 1 "nonmemory_operand" "")))]
19056 "peep2_regno_dead_p (0, FLAGS_REG)"
19057 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
19058 (clobber (reg:CC FLAGS_REG))])]
19062 [(set (match_operand:SI 0 "register_operand" "")
19063 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
19064 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
19065 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
19066 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
19067 (clobber (reg:CC FLAGS_REG))])]
19068 "operands[2] = gen_lowpart (SImode, operands[2]);")
19071 [(set (match_operand:DI 0 "register_operand" "")
19072 (plus:DI (match_dup 0)
19073 (match_operand:DI 1 "x86_64_general_operand" "")))]
19074 "peep2_regno_dead_p (0, FLAGS_REG)"
19075 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
19076 (clobber (reg:CC FLAGS_REG))])]
19080 [(set (match_operand:SI 0 "register_operand" "")
19081 (mult:SI (match_dup 0)
19082 (match_operand:SI 1 "const_int_operand" "")))]
19083 "exact_log2 (INTVAL (operands[1])) >= 0
19084 && peep2_regno_dead_p (0, FLAGS_REG)"
19085 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19086 (clobber (reg:CC FLAGS_REG))])]
19087 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19090 [(set (match_operand:DI 0 "register_operand" "")
19091 (mult:DI (match_dup 0)
19092 (match_operand:DI 1 "const_int_operand" "")))]
19093 "exact_log2 (INTVAL (operands[1])) >= 0
19094 && peep2_regno_dead_p (0, FLAGS_REG)"
19095 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
19096 (clobber (reg:CC FLAGS_REG))])]
19097 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19100 [(set (match_operand:SI 0 "register_operand" "")
19101 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
19102 (match_operand:DI 2 "const_int_operand" "")) 0))]
19103 "exact_log2 (INTVAL (operands[2])) >= 0
19104 && REGNO (operands[0]) == REGNO (operands[1])
19105 && peep2_regno_dead_p (0, FLAGS_REG)"
19106 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19107 (clobber (reg:CC FLAGS_REG))])]
19108 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
19110 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
19111 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
19112 ;; many CPUs it is also faster, since special hardware to avoid esp
19113 ;; dependencies is present.
19115 ;; While some of these conversions may be done using splitters, we use peepholes
19116 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
19118 ;; Convert prologue esp subtractions to push.
19119 ;; We need register to push. In order to keep verify_flow_info happy we have
19121 ;; - use scratch and clobber it in order to avoid dependencies
19122 ;; - use already live register
19123 ;; We can't use the second way right now, since there is no reliable way how to
19124 ;; verify that given register is live. First choice will also most likely in
19125 ;; fewer dependencies. On the place of esp adjustments it is very likely that
19126 ;; call clobbered registers are dead. We may want to use base pointer as an
19127 ;; alternative when no register is available later.
19130 [(match_scratch:SI 0 "r")
19131 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19132 (clobber (reg:CC FLAGS_REG))
19133 (clobber (mem:BLK (scratch)))])]
19134 "optimize_size || !TARGET_SUB_ESP_4"
19135 [(clobber (match_dup 0))
19136 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19137 (clobber (mem:BLK (scratch)))])])
19140 [(match_scratch:SI 0 "r")
19141 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19142 (clobber (reg:CC FLAGS_REG))
19143 (clobber (mem:BLK (scratch)))])]
19144 "optimize_size || !TARGET_SUB_ESP_8"
19145 [(clobber (match_dup 0))
19146 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19147 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19148 (clobber (mem:BLK (scratch)))])])
19150 ;; Convert esp subtractions to push.
19152 [(match_scratch:SI 0 "r")
19153 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19154 (clobber (reg:CC FLAGS_REG))])]
19155 "optimize_size || !TARGET_SUB_ESP_4"
19156 [(clobber (match_dup 0))
19157 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19160 [(match_scratch:SI 0 "r")
19161 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19162 (clobber (reg:CC FLAGS_REG))])]
19163 "optimize_size || !TARGET_SUB_ESP_8"
19164 [(clobber (match_dup 0))
19165 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19166 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19168 ;; Convert epilogue deallocator to pop.
19170 [(match_scratch:SI 0 "r")
19171 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19172 (clobber (reg:CC FLAGS_REG))
19173 (clobber (mem:BLK (scratch)))])]
19174 "optimize_size || !TARGET_ADD_ESP_4"
19175 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19176 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19177 (clobber (mem:BLK (scratch)))])]
19180 ;; Two pops case is tricky, since pop causes dependency on destination register.
19181 ;; We use two registers if available.
19183 [(match_scratch:SI 0 "r")
19184 (match_scratch:SI 1 "r")
19185 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19186 (clobber (reg:CC FLAGS_REG))
19187 (clobber (mem:BLK (scratch)))])]
19188 "optimize_size || !TARGET_ADD_ESP_8"
19189 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19190 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19191 (clobber (mem:BLK (scratch)))])
19192 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19193 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19197 [(match_scratch:SI 0 "r")
19198 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19199 (clobber (reg:CC FLAGS_REG))
19200 (clobber (mem:BLK (scratch)))])]
19202 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19203 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19204 (clobber (mem:BLK (scratch)))])
19205 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19206 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19209 ;; Convert esp additions to pop.
19211 [(match_scratch:SI 0 "r")
19212 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19213 (clobber (reg:CC FLAGS_REG))])]
19215 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19216 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19219 ;; Two pops case is tricky, since pop causes dependency on destination register.
19220 ;; We use two registers if available.
19222 [(match_scratch:SI 0 "r")
19223 (match_scratch:SI 1 "r")
19224 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19225 (clobber (reg:CC FLAGS_REG))])]
19227 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19228 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19229 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19230 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19234 [(match_scratch:SI 0 "r")
19235 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19236 (clobber (reg:CC FLAGS_REG))])]
19238 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19239 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19240 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19241 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19244 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
19245 ;; required and register dies. Similarly for 128 to plus -128.
19247 [(set (match_operand 0 "flags_reg_operand" "")
19248 (match_operator 1 "compare_operator"
19249 [(match_operand 2 "register_operand" "")
19250 (match_operand 3 "const_int_operand" "")]))]
19251 "(INTVAL (operands[3]) == -1
19252 || INTVAL (operands[3]) == 1
19253 || INTVAL (operands[3]) == 128)
19254 && ix86_match_ccmode (insn, CCGCmode)
19255 && peep2_reg_dead_p (1, operands[2])"
19256 [(parallel [(set (match_dup 0)
19257 (match_op_dup 1 [(match_dup 2) (match_dup 3)]))
19258 (clobber (match_dup 2))])]
19262 [(match_scratch:DI 0 "r")
19263 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19264 (clobber (reg:CC FLAGS_REG))
19265 (clobber (mem:BLK (scratch)))])]
19266 "optimize_size || !TARGET_SUB_ESP_4"
19267 [(clobber (match_dup 0))
19268 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19269 (clobber (mem:BLK (scratch)))])])
19272 [(match_scratch:DI 0 "r")
19273 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19274 (clobber (reg:CC FLAGS_REG))
19275 (clobber (mem:BLK (scratch)))])]
19276 "optimize_size || !TARGET_SUB_ESP_8"
19277 [(clobber (match_dup 0))
19278 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19279 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19280 (clobber (mem:BLK (scratch)))])])
19282 ;; Convert esp subtractions to push.
19284 [(match_scratch:DI 0 "r")
19285 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19286 (clobber (reg:CC FLAGS_REG))])]
19287 "optimize_size || !TARGET_SUB_ESP_4"
19288 [(clobber (match_dup 0))
19289 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19292 [(match_scratch:DI 0 "r")
19293 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19294 (clobber (reg:CC FLAGS_REG))])]
19295 "optimize_size || !TARGET_SUB_ESP_8"
19296 [(clobber (match_dup 0))
19297 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19298 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19300 ;; Convert epilogue deallocator to pop.
19302 [(match_scratch:DI 0 "r")
19303 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19304 (clobber (reg:CC FLAGS_REG))
19305 (clobber (mem:BLK (scratch)))])]
19306 "optimize_size || !TARGET_ADD_ESP_4"
19307 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19308 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19309 (clobber (mem:BLK (scratch)))])]
19312 ;; Two pops case is tricky, since pop causes dependency on destination register.
19313 ;; We use two registers if available.
19315 [(match_scratch:DI 0 "r")
19316 (match_scratch:DI 1 "r")
19317 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19318 (clobber (reg:CC FLAGS_REG))
19319 (clobber (mem:BLK (scratch)))])]
19320 "optimize_size || !TARGET_ADD_ESP_8"
19321 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19322 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19323 (clobber (mem:BLK (scratch)))])
19324 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19325 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19329 [(match_scratch:DI 0 "r")
19330 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19331 (clobber (reg:CC FLAGS_REG))
19332 (clobber (mem:BLK (scratch)))])]
19334 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19335 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19336 (clobber (mem:BLK (scratch)))])
19337 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19338 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19341 ;; Convert esp additions to pop.
19343 [(match_scratch:DI 0 "r")
19344 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19345 (clobber (reg:CC FLAGS_REG))])]
19347 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19348 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19351 ;; Two pops case is tricky, since pop causes dependency on destination register.
19352 ;; We use two registers if available.
19354 [(match_scratch:DI 0 "r")
19355 (match_scratch:DI 1 "r")
19356 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19357 (clobber (reg:CC FLAGS_REG))])]
19359 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19360 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19361 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19362 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19366 [(match_scratch:DI 0 "r")
19367 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19368 (clobber (reg:CC FLAGS_REG))])]
19370 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19371 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19372 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19373 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19376 ;; Convert imul by three, five and nine into lea
19379 [(set (match_operand:SI 0 "register_operand" "")
19380 (mult:SI (match_operand:SI 1 "register_operand" "")
19381 (match_operand:SI 2 "const_int_operand" "")))
19382 (clobber (reg:CC FLAGS_REG))])]
19383 "INTVAL (operands[2]) == 3
19384 || INTVAL (operands[2]) == 5
19385 || INTVAL (operands[2]) == 9"
19386 [(set (match_dup 0)
19387 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
19389 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19393 [(set (match_operand:SI 0 "register_operand" "")
19394 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19395 (match_operand:SI 2 "const_int_operand" "")))
19396 (clobber (reg:CC FLAGS_REG))])]
19398 && (INTVAL (operands[2]) == 3
19399 || INTVAL (operands[2]) == 5
19400 || INTVAL (operands[2]) == 9)"
19401 [(set (match_dup 0) (match_dup 1))
19403 (plus:SI (mult:SI (match_dup 0) (match_dup 2))
19405 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19409 [(set (match_operand:DI 0 "register_operand" "")
19410 (mult:DI (match_operand:DI 1 "register_operand" "")
19411 (match_operand:DI 2 "const_int_operand" "")))
19412 (clobber (reg:CC FLAGS_REG))])]
19414 && (INTVAL (operands[2]) == 3
19415 || INTVAL (operands[2]) == 5
19416 || INTVAL (operands[2]) == 9)"
19417 [(set (match_dup 0)
19418 (plus:DI (mult:DI (match_dup 1) (match_dup 2))
19420 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19424 [(set (match_operand:DI 0 "register_operand" "")
19425 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19426 (match_operand:DI 2 "const_int_operand" "")))
19427 (clobber (reg:CC FLAGS_REG))])]
19430 && (INTVAL (operands[2]) == 3
19431 || INTVAL (operands[2]) == 5
19432 || INTVAL (operands[2]) == 9)"
19433 [(set (match_dup 0) (match_dup 1))
19435 (plus:DI (mult:DI (match_dup 0) (match_dup 2))
19437 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19439 ;; Imul $32bit_imm, mem, reg is vector decoded, while
19440 ;; imul $32bit_imm, reg, reg is direct decoded.
19442 [(match_scratch:DI 3 "r")
19443 (parallel [(set (match_operand:DI 0 "register_operand" "")
19444 (mult:DI (match_operand:DI 1 "memory_operand" "")
19445 (match_operand:DI 2 "immediate_operand" "")))
19446 (clobber (reg:CC FLAGS_REG))])]
19447 "TARGET_K8 && !optimize_size
19448 && (GET_CODE (operands[2]) != CONST_INT
19449 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19450 [(set (match_dup 3) (match_dup 1))
19451 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
19452 (clobber (reg:CC FLAGS_REG))])]
19456 [(match_scratch:SI 3 "r")
19457 (parallel [(set (match_operand:SI 0 "register_operand" "")
19458 (mult:SI (match_operand:SI 1 "memory_operand" "")
19459 (match_operand:SI 2 "immediate_operand" "")))
19460 (clobber (reg:CC FLAGS_REG))])]
19461 "TARGET_K8 && !optimize_size
19462 && (GET_CODE (operands[2]) != CONST_INT
19463 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19464 [(set (match_dup 3) (match_dup 1))
19465 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
19466 (clobber (reg:CC FLAGS_REG))])]
19470 [(match_scratch:SI 3 "r")
19471 (parallel [(set (match_operand:DI 0 "register_operand" "")
19473 (mult:SI (match_operand:SI 1 "memory_operand" "")
19474 (match_operand:SI 2 "immediate_operand" ""))))
19475 (clobber (reg:CC FLAGS_REG))])]
19476 "TARGET_K8 && !optimize_size
19477 && (GET_CODE (operands[2]) != CONST_INT
19478 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19479 [(set (match_dup 3) (match_dup 1))
19480 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
19481 (clobber (reg:CC FLAGS_REG))])]
19484 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
19485 ;; Convert it into imul reg, reg
19486 ;; It would be better to force assembler to encode instruction using long
19487 ;; immediate, but there is apparently no way to do so.
19489 [(parallel [(set (match_operand:DI 0 "register_operand" "")
19490 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19491 (match_operand:DI 2 "const_int_operand" "")))
19492 (clobber (reg:CC FLAGS_REG))])
19493 (match_scratch:DI 3 "r")]
19494 "TARGET_K8 && !optimize_size
19495 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19496 [(set (match_dup 3) (match_dup 2))
19497 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
19498 (clobber (reg:CC FLAGS_REG))])]
19500 if (!rtx_equal_p (operands[0], operands[1]))
19501 emit_move_insn (operands[0], operands[1]);
19505 [(parallel [(set (match_operand:SI 0 "register_operand" "")
19506 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19507 (match_operand:SI 2 "const_int_operand" "")))
19508 (clobber (reg:CC FLAGS_REG))])
19509 (match_scratch:SI 3 "r")]
19510 "TARGET_K8 && !optimize_size
19511 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19512 [(set (match_dup 3) (match_dup 2))
19513 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
19514 (clobber (reg:CC FLAGS_REG))])]
19516 if (!rtx_equal_p (operands[0], operands[1]))
19517 emit_move_insn (operands[0], operands[1]);
19521 [(parallel [(set (match_operand:HI 0 "register_operand" "")
19522 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
19523 (match_operand:HI 2 "immediate_operand" "")))
19524 (clobber (reg:CC FLAGS_REG))])
19525 (match_scratch:HI 3 "r")]
19526 "TARGET_K8 && !optimize_size"
19527 [(set (match_dup 3) (match_dup 2))
19528 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
19529 (clobber (reg:CC FLAGS_REG))])]
19531 if (!rtx_equal_p (operands[0], operands[1]))
19532 emit_move_insn (operands[0], operands[1]);
19535 ;; Call-value patterns last so that the wildcard operand does not
19536 ;; disrupt insn-recog's switch tables.
19538 (define_insn "*call_value_pop_0"
19539 [(set (match_operand 0 "" "")
19540 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19541 (match_operand:SI 2 "" "")))
19542 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19543 (match_operand:SI 3 "immediate_operand" "")))]
19546 if (SIBLING_CALL_P (insn))
19549 return "call\t%P1";
19551 [(set_attr "type" "callv")])
19553 (define_insn "*call_value_pop_1"
19554 [(set (match_operand 0 "" "")
19555 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19556 (match_operand:SI 2 "" "")))
19557 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19558 (match_operand:SI 3 "immediate_operand" "i")))]
19561 if (constant_call_address_operand (operands[1], Pmode))
19563 if (SIBLING_CALL_P (insn))
19566 return "call\t%P1";
19568 if (SIBLING_CALL_P (insn))
19571 return "call\t%A1";
19573 [(set_attr "type" "callv")])
19575 (define_insn "*call_value_0"
19576 [(set (match_operand 0 "" "")
19577 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19578 (match_operand:SI 2 "" "")))]
19581 if (SIBLING_CALL_P (insn))
19584 return "call\t%P1";
19586 [(set_attr "type" "callv")])
19588 (define_insn "*call_value_0_rex64"
19589 [(set (match_operand 0 "" "")
19590 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19591 (match_operand:DI 2 "const_int_operand" "")))]
19594 if (SIBLING_CALL_P (insn))
19597 return "call\t%P1";
19599 [(set_attr "type" "callv")])
19601 (define_insn "*call_value_1"
19602 [(set (match_operand 0 "" "")
19603 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19604 (match_operand:SI 2 "" "")))]
19605 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
19607 if (constant_call_address_operand (operands[1], Pmode))
19608 return "call\t%P1";
19609 return "call\t%A1";
19611 [(set_attr "type" "callv")])
19613 (define_insn "*sibcall_value_1"
19614 [(set (match_operand 0 "" "")
19615 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
19616 (match_operand:SI 2 "" "")))]
19617 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
19619 if (constant_call_address_operand (operands[1], Pmode))
19623 [(set_attr "type" "callv")])
19625 (define_insn "*call_value_1_rex64"
19626 [(set (match_operand 0 "" "")
19627 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
19628 (match_operand:DI 2 "" "")))]
19629 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
19631 if (constant_call_address_operand (operands[1], Pmode))
19632 return "call\t%P1";
19633 return "call\t%A1";
19635 [(set_attr "type" "callv")])
19637 (define_insn "*sibcall_value_1_rex64"
19638 [(set (match_operand 0 "" "")
19639 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19640 (match_operand:DI 2 "" "")))]
19641 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19643 [(set_attr "type" "callv")])
19645 (define_insn "*sibcall_value_1_rex64_v"
19646 [(set (match_operand 0 "" "")
19647 (call (mem:QI (reg:DI 40))
19648 (match_operand:DI 1 "" "")))]
19649 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19651 [(set_attr "type" "callv")])
19653 (define_insn "trap"
19654 [(trap_if (const_int 1) (const_int 5))]
19658 ;;; ix86 doesn't have conditional trap instructions, but we fake them
19659 ;;; for the sake of bounds checking. By emitting bounds checks as
19660 ;;; conditional traps rather than as conditional jumps around
19661 ;;; unconditional traps we avoid introducing spurious basic-block
19662 ;;; boundaries and facilitate elimination of redundant checks. In
19663 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
19666 ;;; FIXME: Static branch prediction rules for ix86 are such that
19667 ;;; forward conditional branches predict as untaken. As implemented
19668 ;;; below, pseudo conditional traps violate that rule. We should use
19669 ;;; .pushsection/.popsection to place all of the `int 5's in a special
19670 ;;; section loaded at the end of the text segment and branch forward
19671 ;;; there on bounds-failure, and then jump back immediately (in case
19672 ;;; the system chooses to ignore bounds violations, or to report
19673 ;;; violations and continue execution).
19675 (define_expand "conditional_trap"
19676 [(trap_if (match_operator 0 "comparison_operator"
19677 [(match_dup 2) (const_int 0)])
19678 (match_operand 1 "const_int_operand" ""))]
19681 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
19682 ix86_expand_compare (GET_CODE (operands[0]),
19688 (define_insn "*conditional_trap_1"
19689 [(trap_if (match_operator 0 "comparison_operator"
19690 [(reg FLAGS_REG) (const_int 0)])
19691 (match_operand 1 "const_int_operand" ""))]
19694 operands[2] = gen_label_rtx ();
19695 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
19696 (*targetm.asm_out.internal_label) (asm_out_file, "L",
19697 CODE_LABEL_NUMBER (operands[2]));
19701 ;; Pentium III SIMD instructions.
19703 ;; Moves for SSE/MMX regs.
19705 (define_insn "movv4sf_internal"
19706 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
19707 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
19711 movaps\t{%1, %0|%0, %1}
19712 movaps\t{%1, %0|%0, %1}"
19713 [(set_attr "type" "ssemov")
19714 (set_attr "mode" "V4SF")])
19717 [(set (match_operand:V4SF 0 "register_operand" "")
19718 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
19719 "TARGET_SSE && reload_completed"
19720 [(set (match_dup 0)
19722 (vec_duplicate:V4SF (match_dup 1))
19726 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
19727 operands[2] = CONST0_RTX (V4SFmode);
19730 (define_insn "movv4si_internal"
19731 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
19732 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
19735 switch (which_alternative)
19738 if (get_attr_mode (insn) == MODE_V4SF)
19739 return "xorps\t%0, %0";
19741 return "pxor\t%0, %0";
19744 if (get_attr_mode (insn) == MODE_V4SF)
19745 return "movaps\t{%1, %0|%0, %1}";
19747 return "movdqa\t{%1, %0|%0, %1}";
19752 [(set_attr "type" "ssemov")
19754 (cond [(eq_attr "alternative" "0,1")
19756 (ne (symbol_ref "optimize_size")
19758 (const_string "V4SF")
19759 (const_string "TI"))
19760 (eq_attr "alternative" "2")
19762 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19764 (ne (symbol_ref "optimize_size")
19766 (const_string "V4SF")
19767 (const_string "TI"))]
19768 (const_string "TI")))])
19770 (define_insn "movv2di_internal"
19771 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
19772 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
19775 switch (which_alternative)
19778 if (get_attr_mode (insn) == MODE_V4SF)
19779 return "xorps\t%0, %0";
19781 return "pxor\t%0, %0";
19784 if (get_attr_mode (insn) == MODE_V4SF)
19785 return "movaps\t{%1, %0|%0, %1}";
19787 return "movdqa\t{%1, %0|%0, %1}";
19792 [(set_attr "type" "ssemov")
19794 (cond [(eq_attr "alternative" "0,1")
19796 (ne (symbol_ref "optimize_size")
19798 (const_string "V4SF")
19799 (const_string "TI"))
19800 (eq_attr "alternative" "2")
19802 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19804 (ne (symbol_ref "optimize_size")
19806 (const_string "V4SF")
19807 (const_string "TI"))]
19808 (const_string "TI")))])
19811 [(set (match_operand:V2DF 0 "register_operand" "")
19812 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
19813 "TARGET_SSE2 && reload_completed"
19814 [(set (match_dup 0)
19816 (vec_duplicate:V2DF (match_dup 1))
19820 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
19821 operands[2] = CONST0_RTX (V2DFmode);
19824 (define_insn "movv8qi_internal"
19825 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
19826 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
19828 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19831 movq\t{%1, %0|%0, %1}
19832 movq\t{%1, %0|%0, %1}
19833 movdq2q\t{%1, %0|%0, %1}
19834 movq2dq\t{%1, %0|%0, %1}
19835 movq\t{%1, %0|%0, %1}
19836 movq\t{%1, %0|%0, %1}"
19837 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
19838 (set_attr "mode" "DI")])
19840 (define_insn "movv4hi_internal"
19841 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
19842 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
19844 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19847 movq\t{%1, %0|%0, %1}
19848 movq\t{%1, %0|%0, %1}
19849 movdq2q\t{%1, %0|%0, %1}
19850 movq2dq\t{%1, %0|%0, %1}
19851 movq\t{%1, %0|%0, %1}
19852 movq\t{%1, %0|%0, %1}"
19853 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
19854 (set_attr "mode" "DI")])
19856 (define_insn "*movv2si_internal"
19857 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
19858 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
19860 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19863 movq\t{%1, %0|%0, %1}
19864 movq\t{%1, %0|%0, %1}
19865 movdq2q\t{%1, %0|%0, %1}
19866 movq2dq\t{%1, %0|%0, %1}
19867 movq\t{%1, %0|%0, %1}
19868 movq\t{%1, %0|%0, %1}"
19869 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
19870 (set_attr "mode" "DI")])
19872 (define_insn "movv2sf_internal"
19873 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*x,?m")
19874 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y,*Y,y,*xm,*x"))]
19876 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19879 movq\t{%1, %0|%0, %1}
19880 movq\t{%1, %0|%0, %1}
19881 movdq2q\t{%1, %0|%0, %1}
19882 movq2dq\t{%1, %0|%0, %1}
19883 movlps\t{%1, %0|%0, %1}
19884 movlps\t{%1, %0|%0, %1}"
19885 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
19886 (set_attr "mode" "DI,DI,DI,DI,DI,V2SF,V2SF")])
19888 (define_expand "movti"
19889 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19890 (match_operand:TI 1 "nonimmediate_operand" ""))]
19891 "TARGET_SSE || TARGET_64BIT"
19894 ix86_expand_move (TImode, operands);
19896 ix86_expand_vector_move (TImode, operands);
19900 (define_expand "movtf"
19901 [(set (match_operand:TF 0 "nonimmediate_operand" "")
19902 (match_operand:TF 1 "nonimmediate_operand" ""))]
19906 ix86_expand_move (TFmode, operands);
19908 ix86_expand_vector_move (TFmode, operands);
19912 (define_insn "movv2df_internal"
19913 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
19914 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
19916 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19918 switch (which_alternative)
19921 if (get_attr_mode (insn) == MODE_V4SF)
19922 return "xorps\t%0, %0";
19924 return "xorpd\t%0, %0";
19927 if (get_attr_mode (insn) == MODE_V4SF)
19928 return "movaps\t{%1, %0|%0, %1}";
19930 return "movapd\t{%1, %0|%0, %1}";
19935 [(set_attr "type" "ssemov")
19937 (cond [(eq_attr "alternative" "0,1")
19939 (ne (symbol_ref "optimize_size")
19941 (const_string "V4SF")
19942 (const_string "V2DF"))
19943 (eq_attr "alternative" "2")
19945 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19947 (ne (symbol_ref "optimize_size")
19949 (const_string "V4SF")
19950 (const_string "V2DF"))]
19951 (const_string "V2DF")))])
19953 (define_insn "movv8hi_internal"
19954 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
19955 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
19957 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19959 switch (which_alternative)
19962 if (get_attr_mode (insn) == MODE_V4SF)
19963 return "xorps\t%0, %0";
19965 return "pxor\t%0, %0";
19968 if (get_attr_mode (insn) == MODE_V4SF)
19969 return "movaps\t{%1, %0|%0, %1}";
19971 return "movdqa\t{%1, %0|%0, %1}";
19976 [(set_attr "type" "ssemov")
19978 (cond [(eq_attr "alternative" "0,1")
19980 (ne (symbol_ref "optimize_size")
19982 (const_string "V4SF")
19983 (const_string "TI"))
19984 (eq_attr "alternative" "2")
19986 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19988 (ne (symbol_ref "optimize_size")
19990 (const_string "V4SF")
19991 (const_string "TI"))]
19992 (const_string "TI")))])
19994 (define_insn "movv16qi_internal"
19995 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
19996 (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))]
19998 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20000 switch (which_alternative)
20003 if (get_attr_mode (insn) == MODE_V4SF)
20004 return "xorps\t%0, %0";
20006 return "pxor\t%0, %0";
20009 if (get_attr_mode (insn) == MODE_V4SF)
20010 return "movaps\t{%1, %0|%0, %1}";
20012 return "movdqa\t{%1, %0|%0, %1}";
20017 [(set_attr "type" "ssemov")
20019 (cond [(eq_attr "alternative" "0,1")
20021 (ne (symbol_ref "optimize_size")
20023 (const_string "V4SF")
20024 (const_string "TI"))
20025 (eq_attr "alternative" "2")
20027 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20029 (ne (symbol_ref "optimize_size")
20031 (const_string "V4SF")
20032 (const_string "TI"))]
20033 (const_string "TI")))])
20035 (define_expand "movv2df"
20036 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
20037 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
20040 ix86_expand_vector_move (V2DFmode, operands);
20044 (define_expand "movv8hi"
20045 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
20046 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
20049 ix86_expand_vector_move (V8HImode, operands);
20053 (define_expand "movv16qi"
20054 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
20055 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
20058 ix86_expand_vector_move (V16QImode, operands);
20062 (define_expand "movv4sf"
20063 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20064 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
20067 ix86_expand_vector_move (V4SFmode, operands);
20071 (define_expand "movv4si"
20072 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
20073 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
20076 ix86_expand_vector_move (V4SImode, operands);
20080 (define_expand "movv2di"
20081 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
20082 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
20085 ix86_expand_vector_move (V2DImode, operands);
20089 (define_expand "movv2si"
20090 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
20091 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
20094 ix86_expand_vector_move (V2SImode, operands);
20098 (define_expand "movv4hi"
20099 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
20100 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
20103 ix86_expand_vector_move (V4HImode, operands);
20107 (define_expand "movv8qi"
20108 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
20109 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
20112 ix86_expand_vector_move (V8QImode, operands);
20116 (define_expand "movv2sf"
20117 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
20118 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
20121 ix86_expand_vector_move (V2SFmode, operands);
20125 (define_insn "*pushti"
20126 [(set (match_operand:TI 0 "push_operand" "=<")
20127 (match_operand:TI 1 "register_operand" "x"))]
20131 (define_insn "*pushv2df"
20132 [(set (match_operand:V2DF 0 "push_operand" "=<")
20133 (match_operand:V2DF 1 "register_operand" "x"))]
20137 (define_insn "*pushv2di"
20138 [(set (match_operand:V2DI 0 "push_operand" "=<")
20139 (match_operand:V2DI 1 "register_operand" "x"))]
20143 (define_insn "*pushv8hi"
20144 [(set (match_operand:V8HI 0 "push_operand" "=<")
20145 (match_operand:V8HI 1 "register_operand" "x"))]
20149 (define_insn "*pushv16qi"
20150 [(set (match_operand:V16QI 0 "push_operand" "=<")
20151 (match_operand:V16QI 1 "register_operand" "x"))]
20155 (define_insn "*pushv4sf"
20156 [(set (match_operand:V4SF 0 "push_operand" "=<")
20157 (match_operand:V4SF 1 "register_operand" "x"))]
20161 (define_insn "*pushv4si"
20162 [(set (match_operand:V4SI 0 "push_operand" "=<")
20163 (match_operand:V4SI 1 "register_operand" "x"))]
20167 (define_insn "*pushv2si"
20168 [(set (match_operand:V2SI 0 "push_operand" "=<")
20169 (match_operand:V2SI 1 "register_operand" "y"))]
20173 (define_insn "*pushv4hi"
20174 [(set (match_operand:V4HI 0 "push_operand" "=<")
20175 (match_operand:V4HI 1 "register_operand" "y"))]
20179 (define_insn "*pushv8qi"
20180 [(set (match_operand:V8QI 0 "push_operand" "=<")
20181 (match_operand:V8QI 1 "register_operand" "y"))]
20185 (define_insn "*pushv2sf"
20186 [(set (match_operand:V2SF 0 "push_operand" "=<")
20187 (match_operand:V2SF 1 "register_operand" "y"))]
20192 [(set (match_operand 0 "push_operand" "")
20193 (match_operand 1 "register_operand" ""))]
20194 "!TARGET_64BIT && reload_completed
20195 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
20196 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 3)))
20197 (set (match_dup 2) (match_dup 1))]
20198 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
20199 stack_pointer_rtx);
20200 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
20203 [(set (match_operand 0 "push_operand" "")
20204 (match_operand 1 "register_operand" ""))]
20205 "TARGET_64BIT && reload_completed
20206 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
20207 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 3)))
20208 (set (match_dup 2) (match_dup 1))]
20209 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
20210 stack_pointer_rtx);
20211 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
20214 (define_insn "movti_internal"
20215 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
20216 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
20217 "TARGET_SSE && !TARGET_64BIT
20218 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20220 switch (which_alternative)
20223 if (get_attr_mode (insn) == MODE_V4SF)
20224 return "xorps\t%0, %0";
20226 return "pxor\t%0, %0";
20229 if (get_attr_mode (insn) == MODE_V4SF)
20230 return "movaps\t{%1, %0|%0, %1}";
20232 return "movdqa\t{%1, %0|%0, %1}";
20237 [(set_attr "type" "ssemov,ssemov,ssemov")
20239 (cond [(eq_attr "alternative" "0,1")
20241 (ne (symbol_ref "optimize_size")
20243 (const_string "V4SF")
20244 (const_string "TI"))
20245 (eq_attr "alternative" "2")
20247 (ne (symbol_ref "optimize_size")
20249 (const_string "V4SF")
20250 (const_string "TI"))]
20251 (const_string "TI")))])
20253 (define_insn "*movti_rex64"
20254 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
20255 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
20257 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20259 switch (which_alternative)
20265 if (get_attr_mode (insn) == MODE_V4SF)
20266 return "xorps\t%0, %0";
20268 return "pxor\t%0, %0";
20271 if (get_attr_mode (insn) == MODE_V4SF)
20272 return "movaps\t{%1, %0|%0, %1}";
20274 return "movdqa\t{%1, %0|%0, %1}";
20279 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
20281 (cond [(eq_attr "alternative" "2,3")
20283 (ne (symbol_ref "optimize_size")
20285 (const_string "V4SF")
20286 (const_string "TI"))
20287 (eq_attr "alternative" "4")
20289 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20291 (ne (symbol_ref "optimize_size")
20293 (const_string "V4SF")
20294 (const_string "TI"))]
20295 (const_string "DI")))])
20297 (define_insn "*movtf_rex64"
20298 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
20299 (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
20301 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20303 switch (which_alternative)
20309 if (get_attr_mode (insn) == MODE_V4SF)
20310 return "xorps\t%0, %0";
20312 return "pxor\t%0, %0";
20315 if (get_attr_mode (insn) == MODE_V4SF)
20316 return "movaps\t{%1, %0|%0, %1}";
20318 return "movdqa\t{%1, %0|%0, %1}";
20323 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
20325 (cond [(eq_attr "alternative" "2,3")
20327 (ne (symbol_ref "optimize_size")
20329 (const_string "V4SF")
20330 (const_string "TI"))
20331 (eq_attr "alternative" "4")
20333 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20335 (ne (symbol_ref "optimize_size")
20337 (const_string "V4SF")
20338 (const_string "TI"))]
20339 (const_string "DI")))])
20342 [(set (match_operand:TI 0 "nonimmediate_operand" "")
20343 (match_operand:TI 1 "general_operand" ""))]
20344 "reload_completed && !SSE_REG_P (operands[0])
20345 && !SSE_REG_P (operands[1])"
20347 "ix86_split_long_move (operands); DONE;")
20350 [(set (match_operand:TF 0 "nonimmediate_operand" "")
20351 (match_operand:TF 1 "general_operand" ""))]
20352 "reload_completed && !SSE_REG_P (operands[0])
20353 && !SSE_REG_P (operands[1])"
20355 "ix86_split_long_move (operands); DONE;")
20357 ;; These two patterns are useful for specifying exactly whether to use
20358 ;; movaps or movups
20359 (define_expand "sse_movaps"
20360 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20361 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
20365 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
20367 rtx tmp = gen_reg_rtx (V4SFmode);
20368 emit_insn (gen_sse_movaps (tmp, operands[1]));
20369 emit_move_insn (operands[0], tmp);
20374 (define_insn "*sse_movaps_1"
20375 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20376 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
20379 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20380 "movaps\t{%1, %0|%0, %1}"
20381 [(set_attr "type" "ssemov,ssemov")
20382 (set_attr "mode" "V4SF")])
20384 (define_expand "sse_movups"
20385 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20386 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
20390 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
20392 rtx tmp = gen_reg_rtx (V4SFmode);
20393 emit_insn (gen_sse_movups (tmp, operands[1]));
20394 emit_move_insn (operands[0], tmp);
20399 (define_insn "*sse_movups_1"
20400 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20401 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
20404 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20405 "movups\t{%1, %0|%0, %1}"
20406 [(set_attr "type" "ssecvt,ssecvt")
20407 (set_attr "mode" "V4SF")])
20409 ;; SSE Strange Moves.
20411 (define_insn "sse_movmskps"
20412 [(set (match_operand:SI 0 "register_operand" "=r")
20413 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
20416 "movmskps\t{%1, %0|%0, %1}"
20417 [(set_attr "type" "ssecvt")
20418 (set_attr "mode" "V4SF")])
20420 (define_insn "mmx_pmovmskb"
20421 [(set (match_operand:SI 0 "register_operand" "=r")
20422 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
20424 "TARGET_SSE || TARGET_3DNOW_A"
20425 "pmovmskb\t{%1, %0|%0, %1}"
20426 [(set_attr "type" "ssecvt")
20427 (set_attr "mode" "V4SF")])
20430 (define_insn "mmx_maskmovq"
20431 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
20432 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
20433 (match_operand:V8QI 2 "register_operand" "y")]
20435 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
20436 ;; @@@ check ordering of operands in intel/nonintel syntax
20437 "maskmovq\t{%2, %1|%1, %2}"
20438 [(set_attr "type" "mmxcvt")
20439 (set_attr "mode" "DI")])
20441 (define_insn "mmx_maskmovq_rex"
20442 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
20443 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
20444 (match_operand:V8QI 2 "register_operand" "y")]
20446 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
20447 ;; @@@ check ordering of operands in intel/nonintel syntax
20448 "maskmovq\t{%2, %1|%1, %2}"
20449 [(set_attr "type" "mmxcvt")
20450 (set_attr "mode" "DI")])
20452 (define_insn "sse_movntv4sf"
20453 [(set (match_operand:V4SF 0 "memory_operand" "=m")
20454 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
20457 "movntps\t{%1, %0|%0, %1}"
20458 [(set_attr "type" "ssemov")
20459 (set_attr "mode" "V4SF")])
20461 (define_insn "sse_movntdi"
20462 [(set (match_operand:DI 0 "memory_operand" "=m")
20463 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
20465 "TARGET_SSE || TARGET_3DNOW_A"
20466 "movntq\t{%1, %0|%0, %1}"
20467 [(set_attr "type" "mmxmov")
20468 (set_attr "mode" "DI")])
20470 (define_insn "sse_movhlps"
20471 [(set (match_operand:V4SF 0 "register_operand" "=x")
20473 (match_operand:V4SF 1 "register_operand" "0")
20474 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20475 (parallel [(const_int 2)
20481 "movhlps\t{%2, %0|%0, %2}"
20482 [(set_attr "type" "ssecvt")
20483 (set_attr "mode" "V4SF")])
20485 (define_insn "sse_movlhps"
20486 [(set (match_operand:V4SF 0 "register_operand" "=x")
20488 (match_operand:V4SF 1 "register_operand" "0")
20489 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20490 (parallel [(const_int 2)
20496 "movlhps\t{%2, %0|%0, %2}"
20497 [(set_attr "type" "ssecvt")
20498 (set_attr "mode" "V4SF")])
20500 (define_insn "sse_movhps"
20501 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20503 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
20504 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
20507 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
20508 "movhps\t{%2, %0|%0, %2}"
20509 [(set_attr "type" "ssecvt")
20510 (set_attr "mode" "V4SF")])
20512 (define_insn "sse_movlps"
20513 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20515 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
20516 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
20519 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
20520 "movlps\t{%2, %0|%0, %2}"
20521 [(set_attr "type" "ssecvt")
20522 (set_attr "mode" "V4SF")])
20524 (define_expand "sse_loadss"
20525 [(match_operand:V4SF 0 "register_operand" "")
20526 (match_operand:SF 1 "memory_operand" "")]
20529 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
20530 CONST0_RTX (V4SFmode)));
20534 (define_insn "sse_loadss_1"
20535 [(set (match_operand:V4SF 0 "register_operand" "=x")
20537 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
20538 (match_operand:V4SF 2 "const0_operand" "X")
20541 "movss\t{%1, %0|%0, %1}"
20542 [(set_attr "type" "ssemov")
20543 (set_attr "mode" "SF")])
20545 (define_insn "sse_movss"
20546 [(set (match_operand:V4SF 0 "register_operand" "=x")
20548 (match_operand:V4SF 1 "register_operand" "0")
20549 (match_operand:V4SF 2 "register_operand" "x")
20552 "movss\t{%2, %0|%0, %2}"
20553 [(set_attr "type" "ssemov")
20554 (set_attr "mode" "SF")])
20556 (define_insn "sse_storess"
20557 [(set (match_operand:SF 0 "memory_operand" "=m")
20559 (match_operand:V4SF 1 "register_operand" "x")
20560 (parallel [(const_int 0)])))]
20562 "movss\t{%1, %0|%0, %1}"
20563 [(set_attr "type" "ssemov")
20564 (set_attr "mode" "SF")])
20566 (define_insn "sse_shufps"
20567 [(set (match_operand:V4SF 0 "register_operand" "=x")
20568 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
20569 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
20570 (match_operand:SI 3 "immediate_operand" "i")]
20573 ;; @@@ check operand order for intel/nonintel syntax
20574 "shufps\t{%3, %2, %0|%0, %2, %3}"
20575 [(set_attr "type" "ssecvt")
20576 (set_attr "mode" "V4SF")])
20581 (define_insn "addv4sf3"
20582 [(set (match_operand:V4SF 0 "register_operand" "=x")
20583 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20584 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20586 "addps\t{%2, %0|%0, %2}"
20587 [(set_attr "type" "sseadd")
20588 (set_attr "mode" "V4SF")])
20590 (define_insn "vmaddv4sf3"
20591 [(set (match_operand:V4SF 0 "register_operand" "=x")
20593 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20594 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20598 "addss\t{%2, %0|%0, %2}"
20599 [(set_attr "type" "sseadd")
20600 (set_attr "mode" "SF")])
20602 (define_insn "subv4sf3"
20603 [(set (match_operand:V4SF 0 "register_operand" "=x")
20604 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20605 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20607 "subps\t{%2, %0|%0, %2}"
20608 [(set_attr "type" "sseadd")
20609 (set_attr "mode" "V4SF")])
20611 (define_insn "vmsubv4sf3"
20612 [(set (match_operand:V4SF 0 "register_operand" "=x")
20614 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20615 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20619 "subss\t{%2, %0|%0, %2}"
20620 [(set_attr "type" "sseadd")
20621 (set_attr "mode" "SF")])
20623 ;; ??? Should probably be done by generic code instead.
20624 (define_expand "negv4sf2"
20625 [(set (match_operand:V4SF 0 "register_operand" "")
20626 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
20630 rtx m0 = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
20631 rtx vm0 = gen_rtx_CONST_VECTOR (V4SFmode, gen_rtvec (4, m0, m0, m0, m0));
20632 operands[2] = force_reg (V4SFmode, vm0);
20635 (define_insn "mulv4sf3"
20636 [(set (match_operand:V4SF 0 "register_operand" "=x")
20637 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
20638 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20640 "mulps\t{%2, %0|%0, %2}"
20641 [(set_attr "type" "ssemul")
20642 (set_attr "mode" "V4SF")])
20644 (define_insn "vmmulv4sf3"
20645 [(set (match_operand:V4SF 0 "register_operand" "=x")
20647 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
20648 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20652 "mulss\t{%2, %0|%0, %2}"
20653 [(set_attr "type" "ssemul")
20654 (set_attr "mode" "SF")])
20656 (define_insn "divv4sf3"
20657 [(set (match_operand:V4SF 0 "register_operand" "=x")
20658 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20659 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20661 "divps\t{%2, %0|%0, %2}"
20662 [(set_attr "type" "ssediv")
20663 (set_attr "mode" "V4SF")])
20665 (define_insn "vmdivv4sf3"
20666 [(set (match_operand:V4SF 0 "register_operand" "=x")
20668 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20669 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20673 "divss\t{%2, %0|%0, %2}"
20674 [(set_attr "type" "ssediv")
20675 (set_attr "mode" "SF")])
20678 ;; SSE square root/reciprocal
20680 (define_insn "rcpv4sf2"
20681 [(set (match_operand:V4SF 0 "register_operand" "=x")
20683 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
20685 "rcpps\t{%1, %0|%0, %1}"
20686 [(set_attr "type" "sse")
20687 (set_attr "mode" "V4SF")])
20689 (define_insn "vmrcpv4sf2"
20690 [(set (match_operand:V4SF 0 "register_operand" "=x")
20692 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20694 (match_operand:V4SF 2 "register_operand" "0")
20697 "rcpss\t{%1, %0|%0, %1}"
20698 [(set_attr "type" "sse")
20699 (set_attr "mode" "SF")])
20701 (define_insn "rsqrtv4sf2"
20702 [(set (match_operand:V4SF 0 "register_operand" "=x")
20704 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
20706 "rsqrtps\t{%1, %0|%0, %1}"
20707 [(set_attr "type" "sse")
20708 (set_attr "mode" "V4SF")])
20710 (define_insn "vmrsqrtv4sf2"
20711 [(set (match_operand:V4SF 0 "register_operand" "=x")
20713 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20715 (match_operand:V4SF 2 "register_operand" "0")
20718 "rsqrtss\t{%1, %0|%0, %1}"
20719 [(set_attr "type" "sse")
20720 (set_attr "mode" "SF")])
20722 (define_insn "sqrtv4sf2"
20723 [(set (match_operand:V4SF 0 "register_operand" "=x")
20724 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
20726 "sqrtps\t{%1, %0|%0, %1}"
20727 [(set_attr "type" "sse")
20728 (set_attr "mode" "V4SF")])
20730 (define_insn "vmsqrtv4sf2"
20731 [(set (match_operand:V4SF 0 "register_operand" "=x")
20733 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
20734 (match_operand:V4SF 2 "register_operand" "0")
20737 "sqrtss\t{%1, %0|%0, %1}"
20738 [(set_attr "type" "sse")
20739 (set_attr "mode" "SF")])
20741 ;; SSE logical operations.
20743 ;; SSE defines logical operations on floating point values. This brings
20744 ;; interesting challenge to RTL representation where logicals are only valid
20745 ;; on integral types. We deal with this by representing the floating point
20746 ;; logical as logical on arguments casted to TImode as this is what hardware
20747 ;; really does. Unfortunately hardware requires the type information to be
20748 ;; present and thus we must avoid subregs from being simplified and eliminated
20749 ;; in later compilation phases.
20751 ;; We have following variants from each instruction:
20752 ;; sse_andsf3 - the operation taking V4SF vector operands
20753 ;; and doing TImode cast on them
20754 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
20755 ;; TImode, since backend insist on eliminating casts
20756 ;; on memory operands
20757 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
20758 ;; We cannot accept memory operand here as instruction reads
20759 ;; whole scalar. This is generated only post reload by GCC
20760 ;; scalar float operations that expands to logicals (fabs)
20761 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
20762 ;; memory operand. Eventually combine can be able
20763 ;; to synthesize these using splitter.
20764 ;; sse2_anddf3, *sse2_anddf3_memory
20767 ;; These are not called andti3 etc. because we really really don't want
20768 ;; the compiler to widen DImode ands to TImode ands and then try to move
20769 ;; into DImode subregs of SSE registers, and them together, and move out
20770 ;; of DImode subregs again!
20771 ;; SSE1 single precision floating point logical operation
20772 (define_expand "sse_andv4sf3"
20773 [(set (match_operand:V4SF 0 "register_operand" "")
20774 (and:V4SF (match_operand:V4SF 1 "register_operand" "")
20775 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
20779 (define_insn "*sse_andv4sf3"
20780 [(set (match_operand:V4SF 0 "register_operand" "=x")
20781 (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
20782 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20784 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20785 "andps\t{%2, %0|%0, %2}"
20786 [(set_attr "type" "sselog")
20787 (set_attr "mode" "V4SF")])
20789 (define_expand "sse_nandv4sf3"
20790 [(set (match_operand:V4SF 0 "register_operand" "")
20791 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" ""))
20792 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
20796 (define_insn "*sse_nandv4sf3"
20797 [(set (match_operand:V4SF 0 "register_operand" "=x")
20798 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "0"))
20799 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20801 "andnps\t{%2, %0|%0, %2}"
20802 [(set_attr "type" "sselog")
20803 (set_attr "mode" "V4SF")])
20805 (define_expand "sse_iorv4sf3"
20806 [(set (match_operand:V4SF 0 "register_operand" "")
20807 (ior:V4SF (match_operand:V4SF 1 "register_operand" "")
20808 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
20812 (define_insn "*sse_iorv4sf3"
20813 [(set (match_operand:V4SF 0 "register_operand" "=x")
20814 (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
20815 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20817 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20818 "orps\t{%2, %0|%0, %2}"
20819 [(set_attr "type" "sselog")
20820 (set_attr "mode" "V4SF")])
20822 (define_expand "sse_xorv4sf3"
20823 [(set (match_operand:V4SF 0 "register_operand" "")
20824 (xor:V4SF (match_operand:V4SF 1 "register_operand" "")
20825 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
20829 (define_insn "*sse_xorv4sf3"
20830 [(set (match_operand:V4SF 0 "register_operand" "=x")
20831 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
20832 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20834 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20835 "xorps\t{%2, %0|%0, %2}"
20836 [(set_attr "type" "sselog")
20837 (set_attr "mode" "V4SF")])
20839 ;; SSE2 double precision floating point logical operation
20841 (define_expand "sse2_andv2df3"
20842 [(set (match_operand:V2DF 0 "register_operand" "")
20843 (and:V2DF (match_operand:V2DF 1 "register_operand" "")
20844 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
20848 (define_insn "*sse2_andv2df3"
20849 [(set (match_operand:V2DF 0 "register_operand" "=x")
20850 (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
20851 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20853 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20854 "andpd\t{%2, %0|%0, %2}"
20855 [(set_attr "type" "sselog")
20856 (set_attr "mode" "V2DF")])
20858 (define_expand "sse2_nandv2df3"
20859 [(set (match_operand:V2DF 0 "register_operand" "")
20860 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" ""))
20861 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
20865 (define_insn "*sse2_nandv2df3"
20866 [(set (match_operand:V2DF 0 "register_operand" "=x")
20867 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "0"))
20868 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20870 "andnpd\t{%2, %0|%0, %2}"
20871 [(set_attr "type" "sselog")
20872 (set_attr "mode" "V2DF")])
20874 (define_expand "sse2_iorv2df3"
20875 [(set (match_operand:V2DF 0 "register_operand" "")
20876 (ior:V2DF (match_operand:V2DF 1 "register_operand" "")
20877 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
20881 (define_insn "*sse2_iorv2df3"
20882 [(set (match_operand:V2DF 0 "register_operand" "=x")
20883 (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
20884 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20886 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20887 "orpd\t{%2, %0|%0, %2}"
20888 [(set_attr "type" "sselog")
20889 (set_attr "mode" "V2DF")])
20891 (define_expand "sse2_xorv2df3"
20892 [(set (match_operand:V2DF 0 "register_operand" "")
20893 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
20894 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
20898 (define_insn "*sse2_xorv2df3"
20899 [(set (match_operand:V2DF 0 "register_operand" "=x")
20900 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
20901 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20903 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20904 "xorpd\t{%2, %0|%0, %2}"
20905 [(set_attr "type" "sselog")
20906 (set_attr "mode" "V2DF")])
20908 ;; SSE2 integral logicals. These patterns must always come after floating
20909 ;; point ones since we don't want compiler to use integer opcodes on floating
20910 ;; point SSE values to avoid matching of subregs in the match_operand.
20911 (define_insn "*sse2_andti3"
20912 [(set (match_operand:TI 0 "register_operand" "=x")
20913 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20914 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20916 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20917 "pand\t{%2, %0|%0, %2}"
20918 [(set_attr "type" "sselog")
20919 (set_attr "mode" "TI")])
20921 (define_insn "sse2_andv2di3"
20922 [(set (match_operand:V2DI 0 "register_operand" "=x")
20923 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20924 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20926 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20927 "pand\t{%2, %0|%0, %2}"
20928 [(set_attr "type" "sselog")
20929 (set_attr "mode" "TI")])
20931 (define_insn "*sse2_nandti3"
20932 [(set (match_operand:TI 0 "register_operand" "=x")
20933 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20934 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20936 "pandn\t{%2, %0|%0, %2}"
20937 [(set_attr "type" "sselog")
20938 (set_attr "mode" "TI")])
20940 (define_insn "sse2_nandv2di3"
20941 [(set (match_operand:V2DI 0 "register_operand" "=x")
20942 (and:V2DI (not:V2DI (match_operand:V2DI 1 "register_operand" "0"))
20943 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20945 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20946 "pandn\t{%2, %0|%0, %2}"
20947 [(set_attr "type" "sselog")
20948 (set_attr "mode" "TI")])
20950 (define_insn "*sse2_iorti3"
20951 [(set (match_operand:TI 0 "register_operand" "=x")
20952 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20953 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20955 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20956 "por\t{%2, %0|%0, %2}"
20957 [(set_attr "type" "sselog")
20958 (set_attr "mode" "TI")])
20960 (define_insn "sse2_iorv2di3"
20961 [(set (match_operand:V2DI 0 "register_operand" "=x")
20962 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20963 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20965 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20966 "por\t{%2, %0|%0, %2}"
20967 [(set_attr "type" "sselog")
20968 (set_attr "mode" "TI")])
20970 (define_insn "*sse2_xorti3"
20971 [(set (match_operand:TI 0 "register_operand" "=x")
20972 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20973 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20975 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20976 "pxor\t{%2, %0|%0, %2}"
20977 [(set_attr "type" "sselog")
20978 (set_attr "mode" "TI")])
20980 (define_insn "sse2_xorv2di3"
20981 [(set (match_operand:V2DI 0 "register_operand" "=x")
20982 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20983 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20985 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20986 "pxor\t{%2, %0|%0, %2}"
20987 [(set_attr "type" "sselog")
20988 (set_attr "mode" "TI")])
20990 ;; Use xor, but don't show input operands so they aren't live before
20992 (define_insn "sse_clrv4sf"
20993 [(set (match_operand:V4SF 0 "register_operand" "=x")
20994 (match_operand:V4SF 1 "const0_operand" "X"))]
20997 if (get_attr_mode (insn) == MODE_TI)
20998 return "pxor\t{%0, %0|%0, %0}";
21000 return "xorps\t{%0, %0|%0, %0}";
21002 [(set_attr "type" "sselog")
21003 (set_attr "memory" "none")
21006 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
21008 (ne (symbol_ref "TARGET_SSE2")
21010 (eq (symbol_ref "optimize_size")
21012 (const_string "TI")
21013 (const_string "V4SF")))])
21015 ;; Use xor, but don't show input operands so they aren't live before
21017 (define_insn "sse_clrv2df"
21018 [(set (match_operand:V2DF 0 "register_operand" "=x")
21019 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
21021 "xorpd\t{%0, %0|%0, %0}"
21022 [(set_attr "type" "sselog")
21023 (set_attr "memory" "none")
21024 (set_attr "mode" "V4SF")])
21026 ;; SSE mask-generating compares
21028 (define_insn "maskcmpv4sf3"
21029 [(set (match_operand:V4SI 0 "register_operand" "=x")
21030 (match_operator:V4SI 3 "sse_comparison_operator"
21031 [(match_operand:V4SF 1 "register_operand" "0")
21032 (match_operand:V4SF 2 "register_operand" "x")]))]
21034 "cmp%D3ps\t{%2, %0|%0, %2}"
21035 [(set_attr "type" "ssecmp")
21036 (set_attr "mode" "V4SF")])
21038 (define_insn "maskncmpv4sf3"
21039 [(set (match_operand:V4SI 0 "register_operand" "=x")
21041 (match_operator:V4SI 3 "sse_comparison_operator"
21042 [(match_operand:V4SF 1 "register_operand" "0")
21043 (match_operand:V4SF 2 "register_operand" "x")])))]
21046 if (GET_CODE (operands[3]) == UNORDERED)
21047 return "cmpordps\t{%2, %0|%0, %2}";
21049 return "cmpn%D3ps\t{%2, %0|%0, %2}";
21051 [(set_attr "type" "ssecmp")
21052 (set_attr "mode" "V4SF")])
21054 (define_insn "vmmaskcmpv4sf3"
21055 [(set (match_operand:V4SI 0 "register_operand" "=x")
21057 (match_operator:V4SI 3 "sse_comparison_operator"
21058 [(match_operand:V4SF 1 "register_operand" "0")
21059 (match_operand:V4SF 2 "register_operand" "x")])
21060 (subreg:V4SI (match_dup 1) 0)
21063 "cmp%D3ss\t{%2, %0|%0, %2}"
21064 [(set_attr "type" "ssecmp")
21065 (set_attr "mode" "SF")])
21067 (define_insn "vmmaskncmpv4sf3"
21068 [(set (match_operand:V4SI 0 "register_operand" "=x")
21071 (match_operator:V4SI 3 "sse_comparison_operator"
21072 [(match_operand:V4SF 1 "register_operand" "0")
21073 (match_operand:V4SF 2 "register_operand" "x")]))
21074 (subreg:V4SI (match_dup 1) 0)
21078 if (GET_CODE (operands[3]) == UNORDERED)
21079 return "cmpordss\t{%2, %0|%0, %2}";
21081 return "cmpn%D3ss\t{%2, %0|%0, %2}";
21083 [(set_attr "type" "ssecmp")
21084 (set_attr "mode" "SF")])
21086 (define_insn "sse_comi"
21087 [(set (reg:CCFP FLAGS_REG)
21088 (compare:CCFP (vec_select:SF
21089 (match_operand:V4SF 0 "register_operand" "x")
21090 (parallel [(const_int 0)]))
21092 (match_operand:V4SF 1 "register_operand" "x")
21093 (parallel [(const_int 0)]))))]
21095 "comiss\t{%1, %0|%0, %1}"
21096 [(set_attr "type" "ssecomi")
21097 (set_attr "mode" "SF")])
21099 (define_insn "sse_ucomi"
21100 [(set (reg:CCFPU FLAGS_REG)
21101 (compare:CCFPU (vec_select:SF
21102 (match_operand:V4SF 0 "register_operand" "x")
21103 (parallel [(const_int 0)]))
21105 (match_operand:V4SF 1 "register_operand" "x")
21106 (parallel [(const_int 0)]))))]
21108 "ucomiss\t{%1, %0|%0, %1}"
21109 [(set_attr "type" "ssecomi")
21110 (set_attr "mode" "SF")])
21115 (define_insn "sse_unpckhps"
21116 [(set (match_operand:V4SF 0 "register_operand" "=x")
21118 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
21119 (parallel [(const_int 2)
21123 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
21124 (parallel [(const_int 0)
21130 "unpckhps\t{%2, %0|%0, %2}"
21131 [(set_attr "type" "ssecvt")
21132 (set_attr "mode" "V4SF")])
21134 (define_insn "sse_unpcklps"
21135 [(set (match_operand:V4SF 0 "register_operand" "=x")
21137 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
21138 (parallel [(const_int 0)
21142 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
21143 (parallel [(const_int 2)
21149 "unpcklps\t{%2, %0|%0, %2}"
21150 [(set_attr "type" "ssecvt")
21151 (set_attr "mode" "V4SF")])
21156 (define_insn "smaxv4sf3"
21157 [(set (match_operand:V4SF 0 "register_operand" "=x")
21158 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
21159 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21161 "maxps\t{%2, %0|%0, %2}"
21162 [(set_attr "type" "sse")
21163 (set_attr "mode" "V4SF")])
21165 (define_insn "vmsmaxv4sf3"
21166 [(set (match_operand:V4SF 0 "register_operand" "=x")
21168 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
21169 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
21173 "maxss\t{%2, %0|%0, %2}"
21174 [(set_attr "type" "sse")
21175 (set_attr "mode" "SF")])
21177 (define_insn "sminv4sf3"
21178 [(set (match_operand:V4SF 0 "register_operand" "=x")
21179 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
21180 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
21182 "minps\t{%2, %0|%0, %2}"
21183 [(set_attr "type" "sse")
21184 (set_attr "mode" "V4SF")])
21186 (define_insn "vmsminv4sf3"
21187 [(set (match_operand:V4SF 0 "register_operand" "=x")
21189 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
21190 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
21194 "minss\t{%2, %0|%0, %2}"
21195 [(set_attr "type" "sse")
21196 (set_attr "mode" "SF")])
21198 ;; SSE <-> integer/MMX conversions
21200 (define_insn "cvtpi2ps"
21201 [(set (match_operand:V4SF 0 "register_operand" "=x")
21203 (match_operand:V4SF 1 "register_operand" "0")
21204 (vec_duplicate:V4SF
21205 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
21208 "cvtpi2ps\t{%2, %0|%0, %2}"
21209 [(set_attr "type" "ssecvt")
21210 (set_attr "mode" "V4SF")])
21212 (define_insn "cvtps2pi"
21213 [(set (match_operand:V2SI 0 "register_operand" "=y")
21215 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
21216 (parallel [(const_int 0) (const_int 1)])))]
21218 "cvtps2pi\t{%1, %0|%0, %1}"
21219 [(set_attr "type" "ssecvt")
21220 (set_attr "mode" "V4SF")])
21222 (define_insn "cvttps2pi"
21223 [(set (match_operand:V2SI 0 "register_operand" "=y")
21225 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21227 (parallel [(const_int 0) (const_int 1)])))]
21229 "cvttps2pi\t{%1, %0|%0, %1}"
21230 [(set_attr "type" "ssecvt")
21231 (set_attr "mode" "SF")])
21233 (define_insn "cvtsi2ss"
21234 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21236 (match_operand:V4SF 1 "register_operand" "0,0")
21237 (vec_duplicate:V4SF
21238 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
21241 "cvtsi2ss\t{%2, %0|%0, %2}"
21242 [(set_attr "type" "sseicvt")
21243 (set_attr "athlon_decode" "vector,double")
21244 (set_attr "mode" "SF")])
21246 (define_insn "cvtsi2ssq"
21247 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21249 (match_operand:V4SF 1 "register_operand" "0,0")
21250 (vec_duplicate:V4SF
21251 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
21253 "TARGET_SSE && TARGET_64BIT"
21254 "cvtsi2ssq\t{%2, %0|%0, %2}"
21255 [(set_attr "type" "sseicvt")
21256 (set_attr "athlon_decode" "vector,double")
21257 (set_attr "mode" "SF")])
21259 (define_insn "cvtss2si"
21260 [(set (match_operand:SI 0 "register_operand" "=r,r")
21262 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
21263 (parallel [(const_int 0)])))]
21265 "cvtss2si\t{%1, %0|%0, %1}"
21266 [(set_attr "type" "sseicvt")
21267 (set_attr "athlon_decode" "double,vector")
21268 (set_attr "mode" "SI")])
21270 (define_insn "cvtss2siq"
21271 [(set (match_operand:DI 0 "register_operand" "=r,r")
21273 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
21274 (parallel [(const_int 0)])))]
21276 "cvtss2siq\t{%1, %0|%0, %1}"
21277 [(set_attr "type" "sseicvt")
21278 (set_attr "athlon_decode" "double,vector")
21279 (set_attr "mode" "DI")])
21281 (define_insn "cvttss2si"
21282 [(set (match_operand:SI 0 "register_operand" "=r,r")
21284 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
21286 (parallel [(const_int 0)])))]
21288 "cvttss2si\t{%1, %0|%0, %1}"
21289 [(set_attr "type" "sseicvt")
21290 (set_attr "mode" "SF")
21291 (set_attr "athlon_decode" "double,vector")])
21293 (define_insn "cvttss2siq"
21294 [(set (match_operand:DI 0 "register_operand" "=r,r")
21296 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
21298 (parallel [(const_int 0)])))]
21299 "TARGET_SSE && TARGET_64BIT"
21300 "cvttss2siq\t{%1, %0|%0, %1}"
21301 [(set_attr "type" "sseicvt")
21302 (set_attr "mode" "SF")
21303 (set_attr "athlon_decode" "double,vector")])
21310 (define_insn "addv8qi3"
21311 [(set (match_operand:V8QI 0 "register_operand" "=y")
21312 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21313 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21315 "paddb\t{%2, %0|%0, %2}"
21316 [(set_attr "type" "mmxadd")
21317 (set_attr "mode" "DI")])
21319 (define_insn "addv4hi3"
21320 [(set (match_operand:V4HI 0 "register_operand" "=y")
21321 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21322 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21324 "paddw\t{%2, %0|%0, %2}"
21325 [(set_attr "type" "mmxadd")
21326 (set_attr "mode" "DI")])
21328 (define_insn "addv2si3"
21329 [(set (match_operand:V2SI 0 "register_operand" "=y")
21330 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
21331 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21333 "paddd\t{%2, %0|%0, %2}"
21334 [(set_attr "type" "mmxadd")
21335 (set_attr "mode" "DI")])
21337 (define_insn "mmx_adddi3"
21338 [(set (match_operand:DI 0 "register_operand" "=y")
21340 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
21341 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21344 "paddq\t{%2, %0|%0, %2}"
21345 [(set_attr "type" "mmxadd")
21346 (set_attr "mode" "DI")])
21348 (define_insn "ssaddv8qi3"
21349 [(set (match_operand:V8QI 0 "register_operand" "=y")
21350 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21351 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21353 "paddsb\t{%2, %0|%0, %2}"
21354 [(set_attr "type" "mmxadd")
21355 (set_attr "mode" "DI")])
21357 (define_insn "ssaddv4hi3"
21358 [(set (match_operand:V4HI 0 "register_operand" "=y")
21359 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21360 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21362 "paddsw\t{%2, %0|%0, %2}"
21363 [(set_attr "type" "mmxadd")
21364 (set_attr "mode" "DI")])
21366 (define_insn "usaddv8qi3"
21367 [(set (match_operand:V8QI 0 "register_operand" "=y")
21368 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21369 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21371 "paddusb\t{%2, %0|%0, %2}"
21372 [(set_attr "type" "mmxadd")
21373 (set_attr "mode" "DI")])
21375 (define_insn "usaddv4hi3"
21376 [(set (match_operand:V4HI 0 "register_operand" "=y")
21377 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21378 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21380 "paddusw\t{%2, %0|%0, %2}"
21381 [(set_attr "type" "mmxadd")
21382 (set_attr "mode" "DI")])
21384 (define_insn "subv8qi3"
21385 [(set (match_operand:V8QI 0 "register_operand" "=y")
21386 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21387 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21389 "psubb\t{%2, %0|%0, %2}"
21390 [(set_attr "type" "mmxadd")
21391 (set_attr "mode" "DI")])
21393 (define_insn "subv4hi3"
21394 [(set (match_operand:V4HI 0 "register_operand" "=y")
21395 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21396 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21398 "psubw\t{%2, %0|%0, %2}"
21399 [(set_attr "type" "mmxadd")
21400 (set_attr "mode" "DI")])
21402 (define_insn "subv2si3"
21403 [(set (match_operand:V2SI 0 "register_operand" "=y")
21404 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
21405 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21407 "psubd\t{%2, %0|%0, %2}"
21408 [(set_attr "type" "mmxadd")
21409 (set_attr "mode" "DI")])
21411 (define_insn "mmx_subdi3"
21412 [(set (match_operand:DI 0 "register_operand" "=y")
21414 [(minus:DI (match_operand:DI 1 "register_operand" "0")
21415 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21418 "psubq\t{%2, %0|%0, %2}"
21419 [(set_attr "type" "mmxadd")
21420 (set_attr "mode" "DI")])
21422 (define_insn "sssubv8qi3"
21423 [(set (match_operand:V8QI 0 "register_operand" "=y")
21424 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21425 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21427 "psubsb\t{%2, %0|%0, %2}"
21428 [(set_attr "type" "mmxadd")
21429 (set_attr "mode" "DI")])
21431 (define_insn "sssubv4hi3"
21432 [(set (match_operand:V4HI 0 "register_operand" "=y")
21433 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21434 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21436 "psubsw\t{%2, %0|%0, %2}"
21437 [(set_attr "type" "mmxadd")
21438 (set_attr "mode" "DI")])
21440 (define_insn "ussubv8qi3"
21441 [(set (match_operand:V8QI 0 "register_operand" "=y")
21442 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21443 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21445 "psubusb\t{%2, %0|%0, %2}"
21446 [(set_attr "type" "mmxadd")
21447 (set_attr "mode" "DI")])
21449 (define_insn "ussubv4hi3"
21450 [(set (match_operand:V4HI 0 "register_operand" "=y")
21451 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21452 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21454 "psubusw\t{%2, %0|%0, %2}"
21455 [(set_attr "type" "mmxadd")
21456 (set_attr "mode" "DI")])
21458 (define_insn "mulv4hi3"
21459 [(set (match_operand:V4HI 0 "register_operand" "=y")
21460 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
21461 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21463 "pmullw\t{%2, %0|%0, %2}"
21464 [(set_attr "type" "mmxmul")
21465 (set_attr "mode" "DI")])
21467 (define_insn "smulv4hi3_highpart"
21468 [(set (match_operand:V4HI 0 "register_operand" "=y")
21471 (mult:V4SI (sign_extend:V4SI
21472 (match_operand:V4HI 1 "register_operand" "0"))
21474 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21477 "pmulhw\t{%2, %0|%0, %2}"
21478 [(set_attr "type" "mmxmul")
21479 (set_attr "mode" "DI")])
21481 (define_insn "umulv4hi3_highpart"
21482 [(set (match_operand:V4HI 0 "register_operand" "=y")
21485 (mult:V4SI (zero_extend:V4SI
21486 (match_operand:V4HI 1 "register_operand" "0"))
21488 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21490 "TARGET_SSE || TARGET_3DNOW_A"
21491 "pmulhuw\t{%2, %0|%0, %2}"
21492 [(set_attr "type" "mmxmul")
21493 (set_attr "mode" "DI")])
21495 (define_insn "mmx_pmaddwd"
21496 [(set (match_operand:V2SI 0 "register_operand" "=y")
21500 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
21501 (parallel [(const_int 0) (const_int 2)])))
21503 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
21504 (parallel [(const_int 0) (const_int 2)]))))
21506 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
21507 (parallel [(const_int 1)
21509 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
21510 (parallel [(const_int 1)
21511 (const_int 3)]))))))]
21513 "pmaddwd\t{%2, %0|%0, %2}"
21514 [(set_attr "type" "mmxmul")
21515 (set_attr "mode" "DI")])
21518 ;; MMX logical operations
21519 ;; Note we don't want to declare these as regular iordi3 insns to prevent
21520 ;; normal code that also wants to use the FPU from getting broken.
21521 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
21522 (define_insn "mmx_iordi3"
21523 [(set (match_operand:DI 0 "register_operand" "=y")
21525 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
21526 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21529 "por\t{%2, %0|%0, %2}"
21530 [(set_attr "type" "mmxadd")
21531 (set_attr "mode" "DI")])
21533 (define_insn "mmx_xordi3"
21534 [(set (match_operand:DI 0 "register_operand" "=y")
21536 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
21537 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21540 "pxor\t{%2, %0|%0, %2}"
21541 [(set_attr "type" "mmxadd")
21542 (set_attr "mode" "DI")
21543 (set_attr "memory" "none")])
21545 ;; Same as pxor, but don't show input operands so that we don't think
21547 (define_insn "mmx_clrdi"
21548 [(set (match_operand:DI 0 "register_operand" "=y")
21549 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
21551 "pxor\t{%0, %0|%0, %0}"
21552 [(set_attr "type" "mmxadd")
21553 (set_attr "mode" "DI")
21554 (set_attr "memory" "none")])
21556 (define_insn "mmx_anddi3"
21557 [(set (match_operand:DI 0 "register_operand" "=y")
21559 [(and:DI (match_operand:DI 1 "register_operand" "%0")
21560 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21563 "pand\t{%2, %0|%0, %2}"
21564 [(set_attr "type" "mmxadd")
21565 (set_attr "mode" "DI")])
21567 (define_insn "mmx_nanddi3"
21568 [(set (match_operand:DI 0 "register_operand" "=y")
21570 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
21571 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21574 "pandn\t{%2, %0|%0, %2}"
21575 [(set_attr "type" "mmxadd")
21576 (set_attr "mode" "DI")])
21579 ;; MMX unsigned averages/sum of absolute differences
21581 (define_insn "mmx_uavgv8qi3"
21582 [(set (match_operand:V8QI 0 "register_operand" "=y")
21584 (plus:V8QI (plus:V8QI
21585 (match_operand:V8QI 1 "register_operand" "0")
21586 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
21587 (const_vector:V8QI [(const_int 1)
21596 "TARGET_SSE || TARGET_3DNOW_A"
21597 "pavgb\t{%2, %0|%0, %2}"
21598 [(set_attr "type" "mmxshft")
21599 (set_attr "mode" "DI")])
21601 (define_insn "mmx_uavgv4hi3"
21602 [(set (match_operand:V4HI 0 "register_operand" "=y")
21604 (plus:V4HI (plus:V4HI
21605 (match_operand:V4HI 1 "register_operand" "0")
21606 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
21607 (const_vector:V4HI [(const_int 1)
21612 "TARGET_SSE || TARGET_3DNOW_A"
21613 "pavgw\t{%2, %0|%0, %2}"
21614 [(set_attr "type" "mmxshft")
21615 (set_attr "mode" "DI")])
21617 (define_insn "mmx_psadbw"
21618 [(set (match_operand:DI 0 "register_operand" "=y")
21619 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
21620 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21622 "TARGET_SSE || TARGET_3DNOW_A"
21623 "psadbw\t{%2, %0|%0, %2}"
21624 [(set_attr "type" "mmxshft")
21625 (set_attr "mode" "DI")])
21628 ;; MMX insert/extract/shuffle
21630 (define_insn "mmx_pinsrw"
21631 [(set (match_operand:V4HI 0 "register_operand" "=y")
21632 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
21633 (vec_duplicate:V4HI
21634 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
21635 (match_operand:SI 3 "const_0_to_15_operand" "N")))]
21636 "TARGET_SSE || TARGET_3DNOW_A"
21637 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
21638 [(set_attr "type" "mmxcvt")
21639 (set_attr "mode" "DI")])
21641 (define_insn "mmx_pextrw"
21642 [(set (match_operand:SI 0 "register_operand" "=r")
21643 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
21645 [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
21646 "TARGET_SSE || TARGET_3DNOW_A"
21647 "pextrw\t{%2, %1, %0|%0, %1, %2}"
21648 [(set_attr "type" "mmxcvt")
21649 (set_attr "mode" "DI")])
21651 (define_insn "mmx_pshufw"
21652 [(set (match_operand:V4HI 0 "register_operand" "=y")
21653 (unspec:V4HI [(match_operand:V4HI 1 "nonimmediate_operand" "ym")
21654 (match_operand:SI 2 "immediate_operand" "i")]
21656 "TARGET_SSE || TARGET_3DNOW_A"
21657 "pshufw\t{%2, %1, %0|%0, %1, %2}"
21658 [(set_attr "type" "mmxcvt")
21659 (set_attr "mode" "DI")])
21662 ;; MMX mask-generating comparisons
21664 (define_insn "eqv8qi3"
21665 [(set (match_operand:V8QI 0 "register_operand" "=y")
21666 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
21667 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21669 "pcmpeqb\t{%2, %0|%0, %2}"
21670 [(set_attr "type" "mmxcmp")
21671 (set_attr "mode" "DI")])
21673 (define_insn "eqv4hi3"
21674 [(set (match_operand:V4HI 0 "register_operand" "=y")
21675 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
21676 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21678 "pcmpeqw\t{%2, %0|%0, %2}"
21679 [(set_attr "type" "mmxcmp")
21680 (set_attr "mode" "DI")])
21682 (define_insn "eqv2si3"
21683 [(set (match_operand:V2SI 0 "register_operand" "=y")
21684 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
21685 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21687 "pcmpeqd\t{%2, %0|%0, %2}"
21688 [(set_attr "type" "mmxcmp")
21689 (set_attr "mode" "DI")])
21691 (define_insn "gtv8qi3"
21692 [(set (match_operand:V8QI 0 "register_operand" "=y")
21693 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
21694 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21696 "pcmpgtb\t{%2, %0|%0, %2}"
21697 [(set_attr "type" "mmxcmp")
21698 (set_attr "mode" "DI")])
21700 (define_insn "gtv4hi3"
21701 [(set (match_operand:V4HI 0 "register_operand" "=y")
21702 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21703 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21705 "pcmpgtw\t{%2, %0|%0, %2}"
21706 [(set_attr "type" "mmxcmp")
21707 (set_attr "mode" "DI")])
21709 (define_insn "gtv2si3"
21710 [(set (match_operand:V2SI 0 "register_operand" "=y")
21711 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21712 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21714 "pcmpgtd\t{%2, %0|%0, %2}"
21715 [(set_attr "type" "mmxcmp")
21716 (set_attr "mode" "DI")])
21719 ;; MMX max/min insns
21721 (define_insn "umaxv8qi3"
21722 [(set (match_operand:V8QI 0 "register_operand" "=y")
21723 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
21724 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21725 "TARGET_SSE || TARGET_3DNOW_A"
21726 "pmaxub\t{%2, %0|%0, %2}"
21727 [(set_attr "type" "mmxadd")
21728 (set_attr "mode" "DI")])
21730 (define_insn "smaxv4hi3"
21731 [(set (match_operand:V4HI 0 "register_operand" "=y")
21732 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
21733 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21734 "TARGET_SSE || TARGET_3DNOW_A"
21735 "pmaxsw\t{%2, %0|%0, %2}"
21736 [(set_attr "type" "mmxadd")
21737 (set_attr "mode" "DI")])
21739 (define_insn "uminv8qi3"
21740 [(set (match_operand:V8QI 0 "register_operand" "=y")
21741 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
21742 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21743 "TARGET_SSE || TARGET_3DNOW_A"
21744 "pminub\t{%2, %0|%0, %2}"
21745 [(set_attr "type" "mmxadd")
21746 (set_attr "mode" "DI")])
21748 (define_insn "sminv4hi3"
21749 [(set (match_operand:V4HI 0 "register_operand" "=y")
21750 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
21751 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21752 "TARGET_SSE || TARGET_3DNOW_A"
21753 "pminsw\t{%2, %0|%0, %2}"
21754 [(set_attr "type" "mmxadd")
21755 (set_attr "mode" "DI")])
21760 (define_insn "ashrv4hi3"
21761 [(set (match_operand:V4HI 0 "register_operand" "=y")
21762 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21763 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21765 "psraw\t{%2, %0|%0, %2}"
21766 [(set_attr "type" "mmxshft")
21767 (set_attr "mode" "DI")])
21769 (define_insn "ashrv2si3"
21770 [(set (match_operand:V2SI 0 "register_operand" "=y")
21771 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21772 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21774 "psrad\t{%2, %0|%0, %2}"
21775 [(set_attr "type" "mmxshft")
21776 (set_attr "mode" "DI")])
21778 (define_insn "lshrv4hi3"
21779 [(set (match_operand:V4HI 0 "register_operand" "=y")
21780 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21781 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21783 "psrlw\t{%2, %0|%0, %2}"
21784 [(set_attr "type" "mmxshft")
21785 (set_attr "mode" "DI")])
21787 (define_insn "lshrv2si3"
21788 [(set (match_operand:V2SI 0 "register_operand" "=y")
21789 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21790 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21792 "psrld\t{%2, %0|%0, %2}"
21793 [(set_attr "type" "mmxshft")
21794 (set_attr "mode" "DI")])
21796 ;; See logical MMX insns.
21797 (define_insn "mmx_lshrdi3"
21798 [(set (match_operand:DI 0 "register_operand" "=y")
21800 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
21801 (match_operand:DI 2 "nonmemory_operand" "yi"))]
21804 "psrlq\t{%2, %0|%0, %2}"
21805 [(set_attr "type" "mmxshft")
21806 (set_attr "mode" "DI")])
21808 (define_insn "ashlv4hi3"
21809 [(set (match_operand:V4HI 0 "register_operand" "=y")
21810 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
21811 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21813 "psllw\t{%2, %0|%0, %2}"
21814 [(set_attr "type" "mmxshft")
21815 (set_attr "mode" "DI")])
21817 (define_insn "ashlv2si3"
21818 [(set (match_operand:V2SI 0 "register_operand" "=y")
21819 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
21820 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21822 "pslld\t{%2, %0|%0, %2}"
21823 [(set_attr "type" "mmxshft")
21824 (set_attr "mode" "DI")])
21826 ;; See logical MMX insns.
21827 (define_insn "mmx_ashldi3"
21828 [(set (match_operand:DI 0 "register_operand" "=y")
21830 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
21831 (match_operand:DI 2 "nonmemory_operand" "yi"))]
21834 "psllq\t{%2, %0|%0, %2}"
21835 [(set_attr "type" "mmxshft")
21836 (set_attr "mode" "DI")])
21839 ;; MMX pack/unpack insns.
21841 (define_insn "mmx_packsswb"
21842 [(set (match_operand:V8QI 0 "register_operand" "=y")
21844 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
21845 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
21847 "packsswb\t{%2, %0|%0, %2}"
21848 [(set_attr "type" "mmxshft")
21849 (set_attr "mode" "DI")])
21851 (define_insn "mmx_packssdw"
21852 [(set (match_operand:V4HI 0 "register_operand" "=y")
21854 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
21855 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
21857 "packssdw\t{%2, %0|%0, %2}"
21858 [(set_attr "type" "mmxshft")
21859 (set_attr "mode" "DI")])
21861 (define_insn "mmx_packuswb"
21862 [(set (match_operand:V8QI 0 "register_operand" "=y")
21864 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
21865 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
21867 "packuswb\t{%2, %0|%0, %2}"
21868 [(set_attr "type" "mmxshft")
21869 (set_attr "mode" "DI")])
21871 (define_insn "mmx_punpckhbw"
21872 [(set (match_operand:V8QI 0 "register_operand" "=y")
21874 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21875 (parallel [(const_int 4)
21883 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21884 (parallel [(const_int 0)
21894 "punpckhbw\t{%2, %0|%0, %2}"
21895 [(set_attr "type" "mmxcvt")
21896 (set_attr "mode" "DI")])
21898 (define_insn "mmx_punpckhwd"
21899 [(set (match_operand:V4HI 0 "register_operand" "=y")
21901 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21902 (parallel [(const_int 0)
21906 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21907 (parallel [(const_int 2)
21913 "punpckhwd\t{%2, %0|%0, %2}"
21914 [(set_attr "type" "mmxcvt")
21915 (set_attr "mode" "DI")])
21917 (define_insn "mmx_punpckhdq"
21918 [(set (match_operand:V2SI 0 "register_operand" "=y")
21920 (match_operand:V2SI 1 "register_operand" "0")
21921 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
21922 (parallel [(const_int 1)
21926 "punpckhdq\t{%2, %0|%0, %2}"
21927 [(set_attr "type" "mmxcvt")
21928 (set_attr "mode" "DI")])
21930 (define_insn "mmx_punpcklbw"
21931 [(set (match_operand:V8QI 0 "register_operand" "=y")
21933 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21934 (parallel [(const_int 0)
21942 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21943 (parallel [(const_int 4)
21953 "punpcklbw\t{%2, %0|%0, %2}"
21954 [(set_attr "type" "mmxcvt")
21955 (set_attr "mode" "DI")])
21957 (define_insn "mmx_punpcklwd"
21958 [(set (match_operand:V4HI 0 "register_operand" "=y")
21960 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21961 (parallel [(const_int 2)
21965 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21966 (parallel [(const_int 0)
21972 "punpcklwd\t{%2, %0|%0, %2}"
21973 [(set_attr "type" "mmxcvt")
21974 (set_attr "mode" "DI")])
21976 (define_insn "mmx_punpckldq"
21977 [(set (match_operand:V2SI 0 "register_operand" "=y")
21979 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
21980 (parallel [(const_int 1)
21982 (match_operand:V2SI 2 "register_operand" "y")
21985 "punpckldq\t{%2, %0|%0, %2}"
21986 [(set_attr "type" "mmxcvt")
21987 (set_attr "mode" "DI")])
21990 ;; Miscellaneous stuff
21992 (define_insn "emms"
21993 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
21994 (clobber (reg:XF 8))
21995 (clobber (reg:XF 9))
21996 (clobber (reg:XF 10))
21997 (clobber (reg:XF 11))
21998 (clobber (reg:XF 12))
21999 (clobber (reg:XF 13))
22000 (clobber (reg:XF 14))
22001 (clobber (reg:XF 15))
22002 (clobber (reg:DI 29))
22003 (clobber (reg:DI 30))
22004 (clobber (reg:DI 31))
22005 (clobber (reg:DI 32))
22006 (clobber (reg:DI 33))
22007 (clobber (reg:DI 34))
22008 (clobber (reg:DI 35))
22009 (clobber (reg:DI 36))]
22012 [(set_attr "type" "mmx")
22013 (set_attr "memory" "unknown")])
22015 (define_insn "ldmxcsr"
22016 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
22020 [(set_attr "type" "sse")
22021 (set_attr "memory" "load")])
22023 (define_insn "stmxcsr"
22024 [(set (match_operand:SI 0 "memory_operand" "=m")
22025 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
22028 [(set_attr "type" "sse")
22029 (set_attr "memory" "store")])
22031 (define_expand "sfence"
22032 [(set (match_dup 0)
22033 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
22034 "TARGET_SSE || TARGET_3DNOW_A"
22036 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22037 MEM_VOLATILE_P (operands[0]) = 1;
22040 (define_insn "*sfence_insn"
22041 [(set (match_operand:BLK 0 "" "")
22042 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
22043 "TARGET_SSE || TARGET_3DNOW_A"
22045 [(set_attr "type" "sse")
22046 (set_attr "memory" "unknown")])
22048 (define_expand "sse_prologue_save"
22049 [(parallel [(set (match_operand:BLK 0 "" "")
22050 (unspec:BLK [(reg:DI 21)
22057 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
22058 (use (match_operand:DI 1 "register_operand" ""))
22059 (use (match_operand:DI 2 "immediate_operand" ""))
22060 (use (label_ref:DI (match_operand 3 "" "")))])]
22064 (define_insn "*sse_prologue_save_insn"
22065 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
22066 (match_operand:DI 4 "const_int_operand" "n")))
22067 (unspec:BLK [(reg:DI 21)
22074 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
22075 (use (match_operand:DI 1 "register_operand" "r"))
22076 (use (match_operand:DI 2 "const_int_operand" "i"))
22077 (use (label_ref:DI (match_operand 3 "" "X")))]
22079 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
22080 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
22084 operands[0] = gen_rtx_MEM (Pmode,
22085 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
22086 output_asm_insn (\"jmp\\t%A1\", operands);
22087 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
22089 operands[4] = adjust_address (operands[0], DImode, i*16);
22090 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
22091 PUT_MODE (operands[4], TImode);
22092 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
22093 output_asm_insn (\"rex\", operands);
22094 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
22096 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
22097 CODE_LABEL_NUMBER (operands[3]));
22101 [(set_attr "type" "other")
22102 (set_attr "length_immediate" "0")
22103 (set_attr "length_address" "0")
22104 (set_attr "length" "135")
22105 (set_attr "memory" "store")
22106 (set_attr "modrm" "0")
22107 (set_attr "mode" "DI")])
22109 ;; 3Dnow! instructions
22111 (define_insn "addv2sf3"
22112 [(set (match_operand:V2SF 0 "register_operand" "=y")
22113 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
22114 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22116 "pfadd\\t{%2, %0|%0, %2}"
22117 [(set_attr "type" "mmxadd")
22118 (set_attr "mode" "V2SF")])
22120 (define_insn "subv2sf3"
22121 [(set (match_operand:V2SF 0 "register_operand" "=y")
22122 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
22123 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22125 "pfsub\\t{%2, %0|%0, %2}"
22126 [(set_attr "type" "mmxadd")
22127 (set_attr "mode" "V2SF")])
22129 (define_insn "subrv2sf3"
22130 [(set (match_operand:V2SF 0 "register_operand" "=y")
22131 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
22132 (match_operand:V2SF 1 "register_operand" "0")))]
22134 "pfsubr\\t{%2, %0|%0, %2}"
22135 [(set_attr "type" "mmxadd")
22136 (set_attr "mode" "V2SF")])
22138 (define_insn "gtv2sf3"
22139 [(set (match_operand:V2SI 0 "register_operand" "=y")
22140 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
22141 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22143 "pfcmpgt\\t{%2, %0|%0, %2}"
22144 [(set_attr "type" "mmxcmp")
22145 (set_attr "mode" "V2SF")])
22147 (define_insn "gev2sf3"
22148 [(set (match_operand:V2SI 0 "register_operand" "=y")
22149 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
22150 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22152 "pfcmpge\\t{%2, %0|%0, %2}"
22153 [(set_attr "type" "mmxcmp")
22154 (set_attr "mode" "V2SF")])
22156 (define_insn "eqv2sf3"
22157 [(set (match_operand:V2SI 0 "register_operand" "=y")
22158 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
22159 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22161 "pfcmpeq\\t{%2, %0|%0, %2}"
22162 [(set_attr "type" "mmxcmp")
22163 (set_attr "mode" "V2SF")])
22165 (define_insn "pfmaxv2sf3"
22166 [(set (match_operand:V2SF 0 "register_operand" "=y")
22167 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
22168 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22170 "pfmax\\t{%2, %0|%0, %2}"
22171 [(set_attr "type" "mmxadd")
22172 (set_attr "mode" "V2SF")])
22174 (define_insn "pfminv2sf3"
22175 [(set (match_operand:V2SF 0 "register_operand" "=y")
22176 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
22177 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22179 "pfmin\\t{%2, %0|%0, %2}"
22180 [(set_attr "type" "mmxadd")
22181 (set_attr "mode" "V2SF")])
22183 (define_insn "mulv2sf3"
22184 [(set (match_operand:V2SF 0 "register_operand" "=y")
22185 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
22186 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
22188 "pfmul\\t{%2, %0|%0, %2}"
22189 [(set_attr "type" "mmxmul")
22190 (set_attr "mode" "V2SF")])
22192 (define_insn "femms"
22193 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
22194 (clobber (reg:XF 8))
22195 (clobber (reg:XF 9))
22196 (clobber (reg:XF 10))
22197 (clobber (reg:XF 11))
22198 (clobber (reg:XF 12))
22199 (clobber (reg:XF 13))
22200 (clobber (reg:XF 14))
22201 (clobber (reg:XF 15))
22202 (clobber (reg:DI 29))
22203 (clobber (reg:DI 30))
22204 (clobber (reg:DI 31))
22205 (clobber (reg:DI 32))
22206 (clobber (reg:DI 33))
22207 (clobber (reg:DI 34))
22208 (clobber (reg:DI 35))
22209 (clobber (reg:DI 36))]
22212 [(set_attr "type" "mmx")
22213 (set_attr "memory" "none")])
22215 (define_insn "pf2id"
22216 [(set (match_operand:V2SI 0 "register_operand" "=y")
22217 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
22219 "pf2id\\t{%1, %0|%0, %1}"
22220 [(set_attr "type" "mmxcvt")
22221 (set_attr "mode" "V2SF")])
22223 (define_insn "pf2iw"
22224 [(set (match_operand:V2SI 0 "register_operand" "=y")
22227 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
22229 "pf2iw\\t{%1, %0|%0, %1}"
22230 [(set_attr "type" "mmxcvt")
22231 (set_attr "mode" "V2SF")])
22233 (define_insn "pfacc"
22234 [(set (match_operand:V2SF 0 "register_operand" "=y")
22237 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22238 (parallel [(const_int 0)]))
22239 (vec_select:SF (match_dup 1)
22240 (parallel [(const_int 1)])))
22242 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22243 (parallel [(const_int 0)]))
22244 (vec_select:SF (match_dup 2)
22245 (parallel [(const_int 1)])))))]
22247 "pfacc\\t{%2, %0|%0, %2}"
22248 [(set_attr "type" "mmxadd")
22249 (set_attr "mode" "V2SF")])
22251 (define_insn "pfnacc"
22252 [(set (match_operand:V2SF 0 "register_operand" "=y")
22255 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22256 (parallel [(const_int 0)]))
22257 (vec_select:SF (match_dup 1)
22258 (parallel [(const_int 1)])))
22260 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22261 (parallel [(const_int 0)]))
22262 (vec_select:SF (match_dup 2)
22263 (parallel [(const_int 1)])))))]
22265 "pfnacc\\t{%2, %0|%0, %2}"
22266 [(set_attr "type" "mmxadd")
22267 (set_attr "mode" "V2SF")])
22269 (define_insn "pfpnacc"
22270 [(set (match_operand:V2SF 0 "register_operand" "=y")
22273 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22274 (parallel [(const_int 0)]))
22275 (vec_select:SF (match_dup 1)
22276 (parallel [(const_int 1)])))
22278 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22279 (parallel [(const_int 0)]))
22280 (vec_select:SF (match_dup 2)
22281 (parallel [(const_int 1)])))))]
22283 "pfpnacc\\t{%2, %0|%0, %2}"
22284 [(set_attr "type" "mmxadd")
22285 (set_attr "mode" "V2SF")])
22287 (define_insn "pi2fw"
22288 [(set (match_operand:V2SF 0 "register_operand" "=y")
22293 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
22294 (parallel [(const_int 0)]))))
22297 (vec_select:SI (match_dup 1)
22298 (parallel [(const_int 1)])))))))]
22300 "pi2fw\\t{%1, %0|%0, %1}"
22301 [(set_attr "type" "mmxcvt")
22302 (set_attr "mode" "V2SF")])
22304 (define_insn "floatv2si2"
22305 [(set (match_operand:V2SF 0 "register_operand" "=y")
22306 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22308 "pi2fd\\t{%1, %0|%0, %1}"
22309 [(set_attr "type" "mmxcvt")
22310 (set_attr "mode" "V2SF")])
22312 ;; This insn is identical to pavgb in operation, but the opcode is
22313 ;; different. To avoid accidentally matching pavgb, use an unspec.
22315 (define_insn "pavgusb"
22316 [(set (match_operand:V8QI 0 "register_operand" "=y")
22318 [(match_operand:V8QI 1 "register_operand" "0")
22319 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
22322 "pavgusb\\t{%2, %0|%0, %2}"
22323 [(set_attr "type" "mmxshft")
22324 (set_attr "mode" "TI")])
22326 ;; 3DNow reciprocal and sqrt
22328 (define_insn "pfrcpv2sf2"
22329 [(set (match_operand:V2SF 0 "register_operand" "=y")
22330 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
22333 "pfrcp\\t{%1, %0|%0, %1}"
22334 [(set_attr "type" "mmx")
22335 (set_attr "mode" "TI")])
22337 (define_insn "pfrcpit1v2sf3"
22338 [(set (match_operand:V2SF 0 "register_operand" "=y")
22339 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22340 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22343 "pfrcpit1\\t{%2, %0|%0, %2}"
22344 [(set_attr "type" "mmx")
22345 (set_attr "mode" "TI")])
22347 (define_insn "pfrcpit2v2sf3"
22348 [(set (match_operand:V2SF 0 "register_operand" "=y")
22349 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22350 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22353 "pfrcpit2\\t{%2, %0|%0, %2}"
22354 [(set_attr "type" "mmx")
22355 (set_attr "mode" "TI")])
22357 (define_insn "pfrsqrtv2sf2"
22358 [(set (match_operand:V2SF 0 "register_operand" "=y")
22359 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
22362 "pfrsqrt\\t{%1, %0|%0, %1}"
22363 [(set_attr "type" "mmx")
22364 (set_attr "mode" "TI")])
22366 (define_insn "pfrsqit1v2sf3"
22367 [(set (match_operand:V2SF 0 "register_operand" "=y")
22368 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22369 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22372 "pfrsqit1\\t{%2, %0|%0, %2}"
22373 [(set_attr "type" "mmx")
22374 (set_attr "mode" "TI")])
22376 (define_insn "pmulhrwv4hi3"
22377 [(set (match_operand:V4HI 0 "register_operand" "=y")
22383 (match_operand:V4HI 1 "register_operand" "0"))
22385 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
22386 (const_vector:V4SI [(const_int 32768)
22389 (const_int 32768)]))
22392 "pmulhrw\\t{%2, %0|%0, %2}"
22393 [(set_attr "type" "mmxmul")
22394 (set_attr "mode" "TI")])
22396 (define_insn "pswapdv2si2"
22397 [(set (match_operand:V2SI 0 "register_operand" "=y")
22398 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
22399 (parallel [(const_int 1) (const_int 0)])))]
22401 "pswapd\\t{%1, %0|%0, %1}"
22402 [(set_attr "type" "mmxcvt")
22403 (set_attr "mode" "TI")])
22405 (define_insn "pswapdv2sf2"
22406 [(set (match_operand:V2SF 0 "register_operand" "=y")
22407 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
22408 (parallel [(const_int 1) (const_int 0)])))]
22410 "pswapd\\t{%1, %0|%0, %1}"
22411 [(set_attr "type" "mmxcvt")
22412 (set_attr "mode" "TI")])
22414 (define_expand "prefetch"
22415 [(prefetch (match_operand 0 "address_operand" "")
22416 (match_operand:SI 1 "const_int_operand" "")
22417 (match_operand:SI 2 "const_int_operand" ""))]
22418 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
22420 int rw = INTVAL (operands[1]);
22421 int locality = INTVAL (operands[2]);
22423 if (rw != 0 && rw != 1)
22425 if (locality < 0 || locality > 3)
22427 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
22430 /* Use 3dNOW prefetch in case we are asking for write prefetch not
22431 suported by SSE counterpart or the SSE prefetch is not available
22432 (K6 machines). Otherwise use SSE prefetch as it allows specifying
22434 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
22435 operands[2] = GEN_INT (3);
22437 operands[1] = const0_rtx;
22440 (define_insn "*prefetch_sse"
22441 [(prefetch (match_operand:SI 0 "address_operand" "p")
22443 (match_operand:SI 1 "const_int_operand" ""))]
22444 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
22446 static const char * const patterns[4] = {
22447 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
22450 int locality = INTVAL (operands[1]);
22451 if (locality < 0 || locality > 3)
22454 return patterns[locality];
22456 [(set_attr "type" "sse")
22457 (set_attr "memory" "none")])
22459 (define_insn "*prefetch_sse_rex"
22460 [(prefetch (match_operand:DI 0 "address_operand" "p")
22462 (match_operand:SI 1 "const_int_operand" ""))]
22463 "TARGET_PREFETCH_SSE && TARGET_64BIT"
22465 static const char * const patterns[4] = {
22466 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
22469 int locality = INTVAL (operands[1]);
22470 if (locality < 0 || locality > 3)
22473 return patterns[locality];
22475 [(set_attr "type" "sse")
22476 (set_attr "memory" "none")])
22478 (define_insn "*prefetch_3dnow"
22479 [(prefetch (match_operand:SI 0 "address_operand" "p")
22480 (match_operand:SI 1 "const_int_operand" "n")
22482 "TARGET_3DNOW && !TARGET_64BIT"
22484 if (INTVAL (operands[1]) == 0)
22485 return "prefetch\t%a0";
22487 return "prefetchw\t%a0";
22489 [(set_attr "type" "mmx")
22490 (set_attr "memory" "none")])
22492 (define_insn "*prefetch_3dnow_rex"
22493 [(prefetch (match_operand:DI 0 "address_operand" "p")
22494 (match_operand:SI 1 "const_int_operand" "n")
22496 "TARGET_3DNOW && TARGET_64BIT"
22498 if (INTVAL (operands[1]) == 0)
22499 return "prefetch\t%a0";
22501 return "prefetchw\t%a0";
22503 [(set_attr "type" "mmx")
22504 (set_attr "memory" "none")])
22508 (define_insn "addv2df3"
22509 [(set (match_operand:V2DF 0 "register_operand" "=x")
22510 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22511 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22513 "addpd\t{%2, %0|%0, %2}"
22514 [(set_attr "type" "sseadd")
22515 (set_attr "mode" "V2DF")])
22517 (define_insn "vmaddv2df3"
22518 [(set (match_operand:V2DF 0 "register_operand" "=x")
22519 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22520 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22524 "addsd\t{%2, %0|%0, %2}"
22525 [(set_attr "type" "sseadd")
22526 (set_attr "mode" "DF")])
22528 (define_insn "subv2df3"
22529 [(set (match_operand:V2DF 0 "register_operand" "=x")
22530 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22531 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22533 "subpd\t{%2, %0|%0, %2}"
22534 [(set_attr "type" "sseadd")
22535 (set_attr "mode" "V2DF")])
22537 (define_insn "vmsubv2df3"
22538 [(set (match_operand:V2DF 0 "register_operand" "=x")
22539 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22540 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22544 "subsd\t{%2, %0|%0, %2}"
22545 [(set_attr "type" "sseadd")
22546 (set_attr "mode" "DF")])
22548 (define_insn "mulv2df3"
22549 [(set (match_operand:V2DF 0 "register_operand" "=x")
22550 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
22551 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22553 "mulpd\t{%2, %0|%0, %2}"
22554 [(set_attr "type" "ssemul")
22555 (set_attr "mode" "V2DF")])
22557 (define_insn "vmmulv2df3"
22558 [(set (match_operand:V2DF 0 "register_operand" "=x")
22559 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
22560 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22564 "mulsd\t{%2, %0|%0, %2}"
22565 [(set_attr "type" "ssemul")
22566 (set_attr "mode" "DF")])
22568 (define_insn "divv2df3"
22569 [(set (match_operand:V2DF 0 "register_operand" "=x")
22570 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22571 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22573 "divpd\t{%2, %0|%0, %2}"
22574 [(set_attr "type" "ssediv")
22575 (set_attr "mode" "V2DF")])
22577 (define_insn "vmdivv2df3"
22578 [(set (match_operand:V2DF 0 "register_operand" "=x")
22579 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22580 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22584 "divsd\t{%2, %0|%0, %2}"
22585 [(set_attr "type" "ssediv")
22586 (set_attr "mode" "DF")])
22590 (define_insn "smaxv2df3"
22591 [(set (match_operand:V2DF 0 "register_operand" "=x")
22592 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22593 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22595 "maxpd\t{%2, %0|%0, %2}"
22596 [(set_attr "type" "sseadd")
22597 (set_attr "mode" "V2DF")])
22599 (define_insn "vmsmaxv2df3"
22600 [(set (match_operand:V2DF 0 "register_operand" "=x")
22601 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22602 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22606 "maxsd\t{%2, %0|%0, %2}"
22607 [(set_attr "type" "sseadd")
22608 (set_attr "mode" "DF")])
22610 (define_insn "sminv2df3"
22611 [(set (match_operand:V2DF 0 "register_operand" "=x")
22612 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22613 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22615 "minpd\t{%2, %0|%0, %2}"
22616 [(set_attr "type" "sseadd")
22617 (set_attr "mode" "V2DF")])
22619 (define_insn "vmsminv2df3"
22620 [(set (match_operand:V2DF 0 "register_operand" "=x")
22621 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22622 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22626 "minsd\t{%2, %0|%0, %2}"
22627 [(set_attr "type" "sseadd")
22628 (set_attr "mode" "DF")])
22629 ;; SSE2 square root. There doesn't appear to be an extension for the
22630 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
22632 (define_insn "sqrtv2df2"
22633 [(set (match_operand:V2DF 0 "register_operand" "=x")
22634 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
22636 "sqrtpd\t{%1, %0|%0, %1}"
22637 [(set_attr "type" "sse")
22638 (set_attr "mode" "V2DF")])
22640 (define_insn "vmsqrtv2df2"
22641 [(set (match_operand:V2DF 0 "register_operand" "=x")
22642 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
22643 (match_operand:V2DF 2 "register_operand" "0")
22646 "sqrtsd\t{%1, %0|%0, %1}"
22647 [(set_attr "type" "sse")
22648 (set_attr "mode" "SF")])
22650 ;; SSE mask-generating compares
22652 (define_insn "maskcmpv2df3"
22653 [(set (match_operand:V2DI 0 "register_operand" "=x")
22654 (match_operator:V2DI 3 "sse_comparison_operator"
22655 [(match_operand:V2DF 1 "register_operand" "0")
22656 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
22658 "cmp%D3pd\t{%2, %0|%0, %2}"
22659 [(set_attr "type" "ssecmp")
22660 (set_attr "mode" "V2DF")])
22662 (define_insn "maskncmpv2df3"
22663 [(set (match_operand:V2DI 0 "register_operand" "=x")
22665 (match_operator:V2DI 3 "sse_comparison_operator"
22666 [(match_operand:V2DF 1 "register_operand" "0")
22667 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
22670 if (GET_CODE (operands[3]) == UNORDERED)
22671 return "cmpordps\t{%2, %0|%0, %2}";
22673 return "cmpn%D3pd\t{%2, %0|%0, %2}";
22675 [(set_attr "type" "ssecmp")
22676 (set_attr "mode" "V2DF")])
22678 (define_insn "vmmaskcmpv2df3"
22679 [(set (match_operand:V2DI 0 "register_operand" "=x")
22681 (match_operator:V2DI 3 "sse_comparison_operator"
22682 [(match_operand:V2DF 1 "register_operand" "0")
22683 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
22684 (subreg:V2DI (match_dup 1) 0)
22687 "cmp%D3sd\t{%2, %0|%0, %2}"
22688 [(set_attr "type" "ssecmp")
22689 (set_attr "mode" "DF")])
22691 (define_insn "vmmaskncmpv2df3"
22692 [(set (match_operand:V2DI 0 "register_operand" "=x")
22695 (match_operator:V2DI 3 "sse_comparison_operator"
22696 [(match_operand:V2DF 1 "register_operand" "0")
22697 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
22698 (subreg:V2DI (match_dup 1) 0)
22702 if (GET_CODE (operands[3]) == UNORDERED)
22703 return "cmpordsd\t{%2, %0|%0, %2}";
22705 return "cmpn%D3sd\t{%2, %0|%0, %2}";
22707 [(set_attr "type" "ssecmp")
22708 (set_attr "mode" "DF")])
22710 (define_insn "sse2_comi"
22711 [(set (reg:CCFP FLAGS_REG)
22712 (compare:CCFP (vec_select:DF
22713 (match_operand:V2DF 0 "register_operand" "x")
22714 (parallel [(const_int 0)]))
22716 (match_operand:V2DF 1 "register_operand" "x")
22717 (parallel [(const_int 0)]))))]
22719 "comisd\t{%1, %0|%0, %1}"
22720 [(set_attr "type" "ssecomi")
22721 (set_attr "mode" "DF")])
22723 (define_insn "sse2_ucomi"
22724 [(set (reg:CCFPU FLAGS_REG)
22725 (compare:CCFPU (vec_select:DF
22726 (match_operand:V2DF 0 "register_operand" "x")
22727 (parallel [(const_int 0)]))
22729 (match_operand:V2DF 1 "register_operand" "x")
22730 (parallel [(const_int 0)]))))]
22732 "ucomisd\t{%1, %0|%0, %1}"
22733 [(set_attr "type" "ssecomi")
22734 (set_attr "mode" "DF")])
22736 ;; SSE Strange Moves.
22738 (define_insn "sse2_movmskpd"
22739 [(set (match_operand:SI 0 "register_operand" "=r")
22740 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
22743 "movmskpd\t{%1, %0|%0, %1}"
22744 [(set_attr "type" "ssecvt")
22745 (set_attr "mode" "V2DF")])
22747 (define_insn "sse2_pmovmskb"
22748 [(set (match_operand:SI 0 "register_operand" "=r")
22749 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
22752 "pmovmskb\t{%1, %0|%0, %1}"
22753 [(set_attr "type" "ssecvt")
22754 (set_attr "mode" "V2DF")])
22756 (define_insn "sse2_maskmovdqu"
22757 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
22758 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
22759 (match_operand:V16QI 2 "register_operand" "x")]
22762 ;; @@@ check ordering of operands in intel/nonintel syntax
22763 "maskmovdqu\t{%2, %1|%1, %2}"
22764 [(set_attr "type" "ssecvt")
22765 (set_attr "mode" "TI")])
22767 (define_insn "sse2_maskmovdqu_rex64"
22768 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
22769 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
22770 (match_operand:V16QI 2 "register_operand" "x")]
22773 ;; @@@ check ordering of operands in intel/nonintel syntax
22774 "maskmovdqu\t{%2, %1|%1, %2}"
22775 [(set_attr "type" "ssecvt")
22776 (set_attr "mode" "TI")])
22778 (define_insn "sse2_movntv2df"
22779 [(set (match_operand:V2DF 0 "memory_operand" "=m")
22780 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
22783 "movntpd\t{%1, %0|%0, %1}"
22784 [(set_attr "type" "ssecvt")
22785 (set_attr "mode" "V2DF")])
22787 (define_insn "sse2_movntv2di"
22788 [(set (match_operand:V2DI 0 "memory_operand" "=m")
22789 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
22792 "movntdq\t{%1, %0|%0, %1}"
22793 [(set_attr "type" "ssecvt")
22794 (set_attr "mode" "TI")])
22796 (define_insn "sse2_movntsi"
22797 [(set (match_operand:SI 0 "memory_operand" "=m")
22798 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
22801 "movnti\t{%1, %0|%0, %1}"
22802 [(set_attr "type" "ssecvt")
22803 (set_attr "mode" "V2DF")])
22805 ;; SSE <-> integer/MMX conversions
22807 ;; Conversions between SI and SF
22809 (define_insn "cvtdq2ps"
22810 [(set (match_operand:V4SF 0 "register_operand" "=x")
22811 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
22813 "cvtdq2ps\t{%1, %0|%0, %1}"
22814 [(set_attr "type" "ssecvt")
22815 (set_attr "mode" "V2DF")])
22817 (define_insn "cvtps2dq"
22818 [(set (match_operand:V4SI 0 "register_operand" "=x")
22819 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
22821 "cvtps2dq\t{%1, %0|%0, %1}"
22822 [(set_attr "type" "ssecvt")
22823 (set_attr "mode" "TI")])
22825 (define_insn "cvttps2dq"
22826 [(set (match_operand:V4SI 0 "register_operand" "=x")
22827 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
22830 "cvttps2dq\t{%1, %0|%0, %1}"
22831 [(set_attr "type" "ssecvt")
22832 (set_attr "mode" "TI")])
22834 ;; Conversions between SI and DF
22836 (define_insn "cvtdq2pd"
22837 [(set (match_operand:V2DF 0 "register_operand" "=x")
22838 (float:V2DF (vec_select:V2SI
22839 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
22842 (const_int 1)]))))]
22844 "cvtdq2pd\t{%1, %0|%0, %1}"
22845 [(set_attr "type" "ssecvt")
22846 (set_attr "mode" "V2DF")])
22848 (define_insn "cvtpd2dq"
22849 [(set (match_operand:V4SI 0 "register_operand" "=x")
22851 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
22852 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
22854 "cvtpd2dq\t{%1, %0|%0, %1}"
22855 [(set_attr "type" "ssecvt")
22856 (set_attr "mode" "TI")])
22858 (define_insn "cvttpd2dq"
22859 [(set (match_operand:V4SI 0 "register_operand" "=x")
22861 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22863 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
22865 "cvttpd2dq\t{%1, %0|%0, %1}"
22866 [(set_attr "type" "ssecvt")
22867 (set_attr "mode" "TI")])
22869 (define_insn "cvtpd2pi"
22870 [(set (match_operand:V2SI 0 "register_operand" "=y")
22871 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
22873 "cvtpd2pi\t{%1, %0|%0, %1}"
22874 [(set_attr "type" "ssecvt")
22875 (set_attr "mode" "TI")])
22877 (define_insn "cvttpd2pi"
22878 [(set (match_operand:V2SI 0 "register_operand" "=y")
22879 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22882 "cvttpd2pi\t{%1, %0|%0, %1}"
22883 [(set_attr "type" "ssecvt")
22884 (set_attr "mode" "TI")])
22886 (define_insn "cvtpi2pd"
22887 [(set (match_operand:V2DF 0 "register_operand" "=x")
22888 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22890 "cvtpi2pd\t{%1, %0|%0, %1}"
22891 [(set_attr "type" "ssecvt")
22892 (set_attr "mode" "TI")])
22894 ;; Conversions between SI and DF
22896 (define_insn "cvtsd2si"
22897 [(set (match_operand:SI 0 "register_operand" "=r,r")
22898 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22899 (parallel [(const_int 0)]))))]
22901 "cvtsd2si\t{%1, %0|%0, %1}"
22902 [(set_attr "type" "sseicvt")
22903 (set_attr "athlon_decode" "double,vector")
22904 (set_attr "mode" "SI")])
22906 (define_insn "cvtsd2siq"
22907 [(set (match_operand:DI 0 "register_operand" "=r,r")
22908 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22909 (parallel [(const_int 0)]))))]
22910 "TARGET_SSE2 && TARGET_64BIT"
22911 "cvtsd2siq\t{%1, %0|%0, %1}"
22912 [(set_attr "type" "sseicvt")
22913 (set_attr "athlon_decode" "double,vector")
22914 (set_attr "mode" "DI")])
22916 (define_insn "cvttsd2si"
22917 [(set (match_operand:SI 0 "register_operand" "=r,r")
22918 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22919 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22921 "cvttsd2si\t{%1, %0|%0, %1}"
22922 [(set_attr "type" "sseicvt")
22923 (set_attr "mode" "SI")
22924 (set_attr "athlon_decode" "double,vector")])
22926 (define_insn "cvttsd2siq"
22927 [(set (match_operand:DI 0 "register_operand" "=r,r")
22928 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22929 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22930 "TARGET_SSE2 && TARGET_64BIT"
22931 "cvttsd2siq\t{%1, %0|%0, %1}"
22932 [(set_attr "type" "sseicvt")
22933 (set_attr "mode" "DI")
22934 (set_attr "athlon_decode" "double,vector")])
22936 (define_insn "cvtsi2sd"
22937 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22938 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22939 (vec_duplicate:V2DF
22941 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
22944 "cvtsi2sd\t{%2, %0|%0, %2}"
22945 [(set_attr "type" "sseicvt")
22946 (set_attr "mode" "DF")
22947 (set_attr "athlon_decode" "double,direct")])
22949 (define_insn "cvtsi2sdq"
22950 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22951 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22952 (vec_duplicate:V2DF
22954 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
22956 "TARGET_SSE2 && TARGET_64BIT"
22957 "cvtsi2sdq\t{%2, %0|%0, %2}"
22958 [(set_attr "type" "sseicvt")
22959 (set_attr "mode" "DF")
22960 (set_attr "athlon_decode" "double,direct")])
22962 ;; Conversions between SF and DF
22964 (define_insn "cvtsd2ss"
22965 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
22966 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
22967 (vec_duplicate:V4SF
22968 (float_truncate:V2SF
22969 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
22972 "cvtsd2ss\t{%2, %0|%0, %2}"
22973 [(set_attr "type" "ssecvt")
22974 (set_attr "athlon_decode" "vector,double")
22975 (set_attr "mode" "SF")])
22977 (define_insn "cvtss2sd"
22978 [(set (match_operand:V2DF 0 "register_operand" "=x")
22979 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
22982 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
22983 (parallel [(const_int 0)
22987 "cvtss2sd\t{%2, %0|%0, %2}"
22988 [(set_attr "type" "ssecvt")
22989 (set_attr "mode" "DF")])
22991 (define_insn "cvtpd2ps"
22992 [(set (match_operand:V4SF 0 "register_operand" "=x")
22995 (subreg:V2SI (float_truncate:V2SF
22996 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
22997 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
22999 "cvtpd2ps\t{%1, %0|%0, %1}"
23000 [(set_attr "type" "ssecvt")
23001 (set_attr "mode" "V4SF")])
23003 (define_insn "cvtps2pd"
23004 [(set (match_operand:V2DF 0 "register_operand" "=x")
23006 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
23007 (parallel [(const_int 0)
23008 (const_int 1)]))))]
23010 "cvtps2pd\t{%1, %0|%0, %1}"
23011 [(set_attr "type" "ssecvt")
23012 (set_attr "mode" "V2DF")])
23014 ;; SSE2 variants of MMX insns
23018 (define_insn "addv16qi3"
23019 [(set (match_operand:V16QI 0 "register_operand" "=x")
23020 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23021 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23023 "paddb\t{%2, %0|%0, %2}"
23024 [(set_attr "type" "sseiadd")
23025 (set_attr "mode" "TI")])
23027 (define_insn "addv8hi3"
23028 [(set (match_operand:V8HI 0 "register_operand" "=x")
23029 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23030 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23032 "paddw\t{%2, %0|%0, %2}"
23033 [(set_attr "type" "sseiadd")
23034 (set_attr "mode" "TI")])
23036 (define_insn "addv4si3"
23037 [(set (match_operand:V4SI 0 "register_operand" "=x")
23038 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
23039 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23041 "paddd\t{%2, %0|%0, %2}"
23042 [(set_attr "type" "sseiadd")
23043 (set_attr "mode" "TI")])
23045 (define_insn "addv2di3"
23046 [(set (match_operand:V2DI 0 "register_operand" "=x")
23047 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
23048 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
23050 "paddq\t{%2, %0|%0, %2}"
23051 [(set_attr "type" "sseiadd")
23052 (set_attr "mode" "TI")])
23054 (define_insn "ssaddv16qi3"
23055 [(set (match_operand:V16QI 0 "register_operand" "=x")
23056 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23057 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23059 "paddsb\t{%2, %0|%0, %2}"
23060 [(set_attr "type" "sseiadd")
23061 (set_attr "mode" "TI")])
23063 (define_insn "ssaddv8hi3"
23064 [(set (match_operand:V8HI 0 "register_operand" "=x")
23065 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23066 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23068 "paddsw\t{%2, %0|%0, %2}"
23069 [(set_attr "type" "sseiadd")
23070 (set_attr "mode" "TI")])
23072 (define_insn "usaddv16qi3"
23073 [(set (match_operand:V16QI 0 "register_operand" "=x")
23074 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
23075 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23077 "paddusb\t{%2, %0|%0, %2}"
23078 [(set_attr "type" "sseiadd")
23079 (set_attr "mode" "TI")])
23081 (define_insn "usaddv8hi3"
23082 [(set (match_operand:V8HI 0 "register_operand" "=x")
23083 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
23084 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23086 "paddusw\t{%2, %0|%0, %2}"
23087 [(set_attr "type" "sseiadd")
23088 (set_attr "mode" "TI")])
23090 (define_insn "subv16qi3"
23091 [(set (match_operand:V16QI 0 "register_operand" "=x")
23092 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23093 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23095 "psubb\t{%2, %0|%0, %2}"
23096 [(set_attr "type" "sseiadd")
23097 (set_attr "mode" "TI")])
23099 (define_insn "subv8hi3"
23100 [(set (match_operand:V8HI 0 "register_operand" "=x")
23101 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23102 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23104 "psubw\t{%2, %0|%0, %2}"
23105 [(set_attr "type" "sseiadd")
23106 (set_attr "mode" "TI")])
23108 (define_insn "subv4si3"
23109 [(set (match_operand:V4SI 0 "register_operand" "=x")
23110 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
23111 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23113 "psubd\t{%2, %0|%0, %2}"
23114 [(set_attr "type" "sseiadd")
23115 (set_attr "mode" "TI")])
23117 (define_insn "subv2di3"
23118 [(set (match_operand:V2DI 0 "register_operand" "=x")
23119 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
23120 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
23122 "psubq\t{%2, %0|%0, %2}"
23123 [(set_attr "type" "sseiadd")
23124 (set_attr "mode" "TI")])
23126 (define_insn "sssubv16qi3"
23127 [(set (match_operand:V16QI 0 "register_operand" "=x")
23128 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23129 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23131 "psubsb\t{%2, %0|%0, %2}"
23132 [(set_attr "type" "sseiadd")
23133 (set_attr "mode" "TI")])
23135 (define_insn "sssubv8hi3"
23136 [(set (match_operand:V8HI 0 "register_operand" "=x")
23137 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23138 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23140 "psubsw\t{%2, %0|%0, %2}"
23141 [(set_attr "type" "sseiadd")
23142 (set_attr "mode" "TI")])
23144 (define_insn "ussubv16qi3"
23145 [(set (match_operand:V16QI 0 "register_operand" "=x")
23146 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
23147 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23149 "psubusb\t{%2, %0|%0, %2}"
23150 [(set_attr "type" "sseiadd")
23151 (set_attr "mode" "TI")])
23153 (define_insn "ussubv8hi3"
23154 [(set (match_operand:V8HI 0 "register_operand" "=x")
23155 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
23156 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23158 "psubusw\t{%2, %0|%0, %2}"
23159 [(set_attr "type" "sseiadd")
23160 (set_attr "mode" "TI")])
23162 (define_insn "mulv8hi3"
23163 [(set (match_operand:V8HI 0 "register_operand" "=x")
23164 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
23165 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23167 "pmullw\t{%2, %0|%0, %2}"
23168 [(set_attr "type" "sseimul")
23169 (set_attr "mode" "TI")])
23171 (define_insn "smulv8hi3_highpart"
23172 [(set (match_operand:V8HI 0 "register_operand" "=x")
23175 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
23176 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
23179 "pmulhw\t{%2, %0|%0, %2}"
23180 [(set_attr "type" "sseimul")
23181 (set_attr "mode" "TI")])
23183 (define_insn "umulv8hi3_highpart"
23184 [(set (match_operand:V8HI 0 "register_operand" "=x")
23187 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
23188 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
23191 "pmulhuw\t{%2, %0|%0, %2}"
23192 [(set_attr "type" "sseimul")
23193 (set_attr "mode" "TI")])
23195 (define_insn "sse2_umulsidi3"
23196 [(set (match_operand:DI 0 "register_operand" "=y")
23197 (mult:DI (zero_extend:DI (vec_select:SI
23198 (match_operand:V2SI 1 "register_operand" "0")
23199 (parallel [(const_int 0)])))
23200 (zero_extend:DI (vec_select:SI
23201 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
23202 (parallel [(const_int 0)])))))]
23204 "pmuludq\t{%2, %0|%0, %2}"
23205 [(set_attr "type" "mmxmul")
23206 (set_attr "mode" "DI")])
23208 (define_insn "sse2_umulv2siv2di3"
23209 [(set (match_operand:V2DI 0 "register_operand" "=x")
23210 (mult:V2DI (zero_extend:V2DI
23212 (match_operand:V4SI 1 "register_operand" "0")
23213 (parallel [(const_int 0) (const_int 2)])))
23216 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
23217 (parallel [(const_int 0) (const_int 2)])))))]
23219 "pmuludq\t{%2, %0|%0, %2}"
23220 [(set_attr "type" "sseimul")
23221 (set_attr "mode" "TI")])
23223 (define_insn "sse2_pmaddwd"
23224 [(set (match_operand:V4SI 0 "register_operand" "=x")
23227 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
23228 (parallel [(const_int 0)
23232 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
23233 (parallel [(const_int 0)
23238 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
23239 (parallel [(const_int 1)
23243 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
23244 (parallel [(const_int 1)
23247 (const_int 7)]))))))]
23249 "pmaddwd\t{%2, %0|%0, %2}"
23250 [(set_attr "type" "sseiadd")
23251 (set_attr "mode" "TI")])
23253 ;; Same as pxor, but don't show input operands so that we don't think
23255 (define_insn "sse2_clrti"
23256 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
23259 if (get_attr_mode (insn) == MODE_TI)
23260 return "pxor\t%0, %0";
23262 return "xorps\t%0, %0";
23264 [(set_attr "type" "ssemov")
23265 (set_attr "memory" "none")
23268 (ne (symbol_ref "optimize_size")
23270 (const_string "V4SF")
23271 (const_string "TI")))])
23273 ;; MMX unsigned averages/sum of absolute differences
23275 (define_insn "sse2_uavgv16qi3"
23276 [(set (match_operand:V16QI 0 "register_operand" "=x")
23278 (plus:V16QI (plus:V16QI
23279 (match_operand:V16QI 1 "register_operand" "0")
23280 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
23281 (const_vector:V16QI [(const_int 1) (const_int 1)
23282 (const_int 1) (const_int 1)
23283 (const_int 1) (const_int 1)
23284 (const_int 1) (const_int 1)
23285 (const_int 1) (const_int 1)
23286 (const_int 1) (const_int 1)
23287 (const_int 1) (const_int 1)
23288 (const_int 1) (const_int 1)]))
23291 "pavgb\t{%2, %0|%0, %2}"
23292 [(set_attr "type" "sseiadd")
23293 (set_attr "mode" "TI")])
23295 (define_insn "sse2_uavgv8hi3"
23296 [(set (match_operand:V8HI 0 "register_operand" "=x")
23298 (plus:V8HI (plus:V8HI
23299 (match_operand:V8HI 1 "register_operand" "0")
23300 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
23301 (const_vector:V8HI [(const_int 1) (const_int 1)
23302 (const_int 1) (const_int 1)
23303 (const_int 1) (const_int 1)
23304 (const_int 1) (const_int 1)]))
23307 "pavgw\t{%2, %0|%0, %2}"
23308 [(set_attr "type" "sseiadd")
23309 (set_attr "mode" "TI")])
23311 ;; @@@ this isn't the right representation.
23312 (define_insn "sse2_psadbw"
23313 [(set (match_operand:V2DI 0 "register_operand" "=x")
23314 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
23315 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
23318 "psadbw\t{%2, %0|%0, %2}"
23319 [(set_attr "type" "sseiadd")
23320 (set_attr "mode" "TI")])
23323 ;; MMX insert/extract/shuffle
23325 (define_insn "sse2_pinsrw"
23326 [(set (match_operand:V8HI 0 "register_operand" "=x")
23327 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
23328 (vec_duplicate:V8HI
23330 (match_operand:SI 2 "nonimmediate_operand" "rm")))
23331 (match_operand:SI 3 "const_0_to_255_operand" "N")))]
23333 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
23334 [(set_attr "type" "ssecvt")
23335 (set_attr "mode" "TI")])
23337 (define_insn "sse2_pextrw"
23338 [(set (match_operand:SI 0 "register_operand" "=r")
23340 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
23342 [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
23344 "pextrw\t{%2, %1, %0|%0, %1, %2}"
23345 [(set_attr "type" "ssecvt")
23346 (set_attr "mode" "TI")])
23348 (define_insn "sse2_pshufd"
23349 [(set (match_operand:V4SI 0 "register_operand" "=x")
23350 (unspec:V4SI [(match_operand:V4SI 1 "nonimmediate_operand" "xm")
23351 (match_operand:SI 2 "immediate_operand" "i")]
23354 "pshufd\t{%2, %1, %0|%0, %1, %2}"
23355 [(set_attr "type" "ssecvt")
23356 (set_attr "mode" "TI")])
23358 (define_insn "sse2_pshuflw"
23359 [(set (match_operand:V8HI 0 "register_operand" "=x")
23360 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
23361 (match_operand:SI 2 "immediate_operand" "i")]
23364 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
23365 [(set_attr "type" "ssecvt")
23366 (set_attr "mode" "TI")])
23368 (define_insn "sse2_pshufhw"
23369 [(set (match_operand:V8HI 0 "register_operand" "=x")
23370 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
23371 (match_operand:SI 2 "immediate_operand" "i")]
23374 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
23375 [(set_attr "type" "ssecvt")
23376 (set_attr "mode" "TI")])
23378 ;; MMX mask-generating comparisons
23380 (define_insn "eqv16qi3"
23381 [(set (match_operand:V16QI 0 "register_operand" "=x")
23382 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
23383 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23385 "pcmpeqb\t{%2, %0|%0, %2}"
23386 [(set_attr "type" "ssecmp")
23387 (set_attr "mode" "TI")])
23389 (define_insn "eqv8hi3"
23390 [(set (match_operand:V8HI 0 "register_operand" "=x")
23391 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
23392 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23394 "pcmpeqw\t{%2, %0|%0, %2}"
23395 [(set_attr "type" "ssecmp")
23396 (set_attr "mode" "TI")])
23398 (define_insn "eqv4si3"
23399 [(set (match_operand:V4SI 0 "register_operand" "=x")
23400 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
23401 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23403 "pcmpeqd\t{%2, %0|%0, %2}"
23404 [(set_attr "type" "ssecmp")
23405 (set_attr "mode" "TI")])
23407 (define_insn "gtv16qi3"
23408 [(set (match_operand:V16QI 0 "register_operand" "=x")
23409 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
23410 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23412 "pcmpgtb\t{%2, %0|%0, %2}"
23413 [(set_attr "type" "ssecmp")
23414 (set_attr "mode" "TI")])
23416 (define_insn "gtv8hi3"
23417 [(set (match_operand:V8HI 0 "register_operand" "=x")
23418 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23419 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23421 "pcmpgtw\t{%2, %0|%0, %2}"
23422 [(set_attr "type" "ssecmp")
23423 (set_attr "mode" "TI")])
23425 (define_insn "gtv4si3"
23426 [(set (match_operand:V4SI 0 "register_operand" "=x")
23427 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23428 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23430 "pcmpgtd\t{%2, %0|%0, %2}"
23431 [(set_attr "type" "ssecmp")
23432 (set_attr "mode" "TI")])
23435 ;; MMX max/min insns
23437 (define_insn "umaxv16qi3"
23438 [(set (match_operand:V16QI 0 "register_operand" "=x")
23439 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
23440 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23442 "pmaxub\t{%2, %0|%0, %2}"
23443 [(set_attr "type" "sseiadd")
23444 (set_attr "mode" "TI")])
23446 (define_insn "smaxv8hi3"
23447 [(set (match_operand:V8HI 0 "register_operand" "=x")
23448 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
23449 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23451 "pmaxsw\t{%2, %0|%0, %2}"
23452 [(set_attr "type" "sseiadd")
23453 (set_attr "mode" "TI")])
23455 (define_insn "uminv16qi3"
23456 [(set (match_operand:V16QI 0 "register_operand" "=x")
23457 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
23458 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23460 "pminub\t{%2, %0|%0, %2}"
23461 [(set_attr "type" "sseiadd")
23462 (set_attr "mode" "TI")])
23464 (define_insn "sminv8hi3"
23465 [(set (match_operand:V8HI 0 "register_operand" "=x")
23466 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
23467 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23469 "pminsw\t{%2, %0|%0, %2}"
23470 [(set_attr "type" "sseiadd")
23471 (set_attr "mode" "TI")])
23476 (define_insn "ashrv8hi3"
23477 [(set (match_operand:V8HI 0 "register_operand" "=x")
23478 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23479 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23481 "psraw\t{%2, %0|%0, %2}"
23482 [(set_attr "type" "sseishft")
23483 (set_attr "mode" "TI")])
23485 (define_insn "ashrv4si3"
23486 [(set (match_operand:V4SI 0 "register_operand" "=x")
23487 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23488 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23490 "psrad\t{%2, %0|%0, %2}"
23491 [(set_attr "type" "sseishft")
23492 (set_attr "mode" "TI")])
23494 (define_insn "lshrv8hi3"
23495 [(set (match_operand:V8HI 0 "register_operand" "=x")
23496 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23497 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23499 "psrlw\t{%2, %0|%0, %2}"
23500 [(set_attr "type" "sseishft")
23501 (set_attr "mode" "TI")])
23503 (define_insn "lshrv4si3"
23504 [(set (match_operand:V4SI 0 "register_operand" "=x")
23505 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23506 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23508 "psrld\t{%2, %0|%0, %2}"
23509 [(set_attr "type" "sseishft")
23510 (set_attr "mode" "TI")])
23512 (define_insn "lshrv2di3"
23513 [(set (match_operand:V2DI 0 "register_operand" "=x")
23514 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23515 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23517 "psrlq\t{%2, %0|%0, %2}"
23518 [(set_attr "type" "sseishft")
23519 (set_attr "mode" "TI")])
23521 (define_insn "ashlv8hi3"
23522 [(set (match_operand:V8HI 0 "register_operand" "=x")
23523 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23524 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23526 "psllw\t{%2, %0|%0, %2}"
23527 [(set_attr "type" "sseishft")
23528 (set_attr "mode" "TI")])
23530 (define_insn "ashlv4si3"
23531 [(set (match_operand:V4SI 0 "register_operand" "=x")
23532 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23533 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23535 "pslld\t{%2, %0|%0, %2}"
23536 [(set_attr "type" "sseishft")
23537 (set_attr "mode" "TI")])
23539 (define_insn "ashlv2di3"
23540 [(set (match_operand:V2DI 0 "register_operand" "=x")
23541 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23542 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23544 "psllq\t{%2, %0|%0, %2}"
23545 [(set_attr "type" "sseishft")
23546 (set_attr "mode" "TI")])
23548 (define_insn "ashrv8hi3_ti"
23549 [(set (match_operand:V8HI 0 "register_operand" "=x")
23550 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23551 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23553 "psraw\t{%2, %0|%0, %2}"
23554 [(set_attr "type" "sseishft")
23555 (set_attr "mode" "TI")])
23557 (define_insn "ashrv4si3_ti"
23558 [(set (match_operand:V4SI 0 "register_operand" "=x")
23559 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23560 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23562 "psrad\t{%2, %0|%0, %2}"
23563 [(set_attr "type" "sseishft")
23564 (set_attr "mode" "TI")])
23566 (define_insn "lshrv8hi3_ti"
23567 [(set (match_operand:V8HI 0 "register_operand" "=x")
23568 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23569 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23571 "psrlw\t{%2, %0|%0, %2}"
23572 [(set_attr "type" "sseishft")
23573 (set_attr "mode" "TI")])
23575 (define_insn "lshrv4si3_ti"
23576 [(set (match_operand:V4SI 0 "register_operand" "=x")
23577 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23578 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23580 "psrld\t{%2, %0|%0, %2}"
23581 [(set_attr "type" "sseishft")
23582 (set_attr "mode" "TI")])
23584 (define_insn "lshrv2di3_ti"
23585 [(set (match_operand:V2DI 0 "register_operand" "=x")
23586 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23587 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23589 "psrlq\t{%2, %0|%0, %2}"
23590 [(set_attr "type" "sseishft")
23591 (set_attr "mode" "TI")])
23593 (define_insn "ashlv8hi3_ti"
23594 [(set (match_operand:V8HI 0 "register_operand" "=x")
23595 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23596 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23598 "psllw\t{%2, %0|%0, %2}"
23599 [(set_attr "type" "sseishft")
23600 (set_attr "mode" "TI")])
23602 (define_insn "ashlv4si3_ti"
23603 [(set (match_operand:V4SI 0 "register_operand" "=x")
23604 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23605 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23607 "pslld\t{%2, %0|%0, %2}"
23608 [(set_attr "type" "sseishft")
23609 (set_attr "mode" "TI")])
23611 (define_insn "ashlv2di3_ti"
23612 [(set (match_operand:V2DI 0 "register_operand" "=x")
23613 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23614 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23616 "psllq\t{%2, %0|%0, %2}"
23617 [(set_attr "type" "sseishft")
23618 (set_attr "mode" "TI")])
23620 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
23621 ;; we wouldn't need here it since we never generate TImode arithmetic.
23623 ;; There has to be some kind of prize for the weirdest new instruction...
23624 (define_insn "sse2_ashlti3"
23625 [(set (match_operand:TI 0 "register_operand" "=x")
23627 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
23628 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23629 (const_int 8)))] UNSPEC_NOP))]
23631 "pslldq\t{%2, %0|%0, %2}"
23632 [(set_attr "type" "sseishft")
23633 (set_attr "mode" "TI")])
23635 (define_insn "sse2_lshrti3"
23636 [(set (match_operand:TI 0 "register_operand" "=x")
23638 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
23639 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23640 (const_int 8)))] UNSPEC_NOP))]
23642 "psrldq\t{%2, %0|%0, %2}"
23643 [(set_attr "type" "sseishft")
23644 (set_attr "mode" "TI")])
23648 (define_insn "sse2_unpckhpd"
23649 [(set (match_operand:V2DF 0 "register_operand" "=x")
23651 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23652 (parallel [(const_int 1)]))
23653 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23654 (parallel [(const_int 1)]))))]
23656 "unpckhpd\t{%2, %0|%0, %2}"
23657 [(set_attr "type" "ssecvt")
23658 (set_attr "mode" "V2DF")])
23660 (define_insn "sse2_unpcklpd"
23661 [(set (match_operand:V2DF 0 "register_operand" "=x")
23663 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23664 (parallel [(const_int 0)]))
23665 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23666 (parallel [(const_int 0)]))))]
23668 "unpcklpd\t{%2, %0|%0, %2}"
23669 [(set_attr "type" "ssecvt")
23670 (set_attr "mode" "V2DF")])
23672 ;; MMX pack/unpack insns.
23674 (define_insn "sse2_packsswb"
23675 [(set (match_operand:V16QI 0 "register_operand" "=x")
23677 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23678 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23680 "packsswb\t{%2, %0|%0, %2}"
23681 [(set_attr "type" "ssecvt")
23682 (set_attr "mode" "TI")])
23684 (define_insn "sse2_packssdw"
23685 [(set (match_operand:V8HI 0 "register_operand" "=x")
23687 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
23688 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
23690 "packssdw\t{%2, %0|%0, %2}"
23691 [(set_attr "type" "ssecvt")
23692 (set_attr "mode" "TI")])
23694 (define_insn "sse2_packuswb"
23695 [(set (match_operand:V16QI 0 "register_operand" "=x")
23697 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23698 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23700 "packuswb\t{%2, %0|%0, %2}"
23701 [(set_attr "type" "ssecvt")
23702 (set_attr "mode" "TI")])
23704 (define_insn "sse2_punpckhbw"
23705 [(set (match_operand:V16QI 0 "register_operand" "=x")
23707 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
23708 (parallel [(const_int 8) (const_int 0)
23709 (const_int 9) (const_int 1)
23710 (const_int 10) (const_int 2)
23711 (const_int 11) (const_int 3)
23712 (const_int 12) (const_int 4)
23713 (const_int 13) (const_int 5)
23714 (const_int 14) (const_int 6)
23715 (const_int 15) (const_int 7)]))
23716 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
23717 (parallel [(const_int 0) (const_int 8)
23718 (const_int 1) (const_int 9)
23719 (const_int 2) (const_int 10)
23720 (const_int 3) (const_int 11)
23721 (const_int 4) (const_int 12)
23722 (const_int 5) (const_int 13)
23723 (const_int 6) (const_int 14)
23724 (const_int 7) (const_int 15)]))
23725 (const_int 21845)))]
23727 "punpckhbw\t{%2, %0|%0, %2}"
23728 [(set_attr "type" "ssecvt")
23729 (set_attr "mode" "TI")])
23731 (define_insn "sse2_punpckhwd"
23732 [(set (match_operand:V8HI 0 "register_operand" "=x")
23734 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
23735 (parallel [(const_int 4) (const_int 0)
23736 (const_int 5) (const_int 1)
23737 (const_int 6) (const_int 2)
23738 (const_int 7) (const_int 3)]))
23739 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
23740 (parallel [(const_int 0) (const_int 4)
23741 (const_int 1) (const_int 5)
23742 (const_int 2) (const_int 6)
23743 (const_int 3) (const_int 7)]))
23746 "punpckhwd\t{%2, %0|%0, %2}"
23747 [(set_attr "type" "ssecvt")
23748 (set_attr "mode" "TI")])
23750 (define_insn "sse2_punpckhdq"
23751 [(set (match_operand:V4SI 0 "register_operand" "=x")
23753 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
23754 (parallel [(const_int 2) (const_int 0)
23755 (const_int 3) (const_int 1)]))
23756 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
23757 (parallel [(const_int 0) (const_int 2)
23758 (const_int 1) (const_int 3)]))
23761 "punpckhdq\t{%2, %0|%0, %2}"
23762 [(set_attr "type" "ssecvt")
23763 (set_attr "mode" "TI")])
23765 (define_insn "sse2_punpcklbw"
23766 [(set (match_operand:V16QI 0 "register_operand" "=x")
23768 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
23769 (parallel [(const_int 0) (const_int 8)
23770 (const_int 1) (const_int 9)
23771 (const_int 2) (const_int 10)
23772 (const_int 3) (const_int 11)
23773 (const_int 4) (const_int 12)
23774 (const_int 5) (const_int 13)
23775 (const_int 6) (const_int 14)
23776 (const_int 7) (const_int 15)]))
23777 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
23778 (parallel [(const_int 8) (const_int 0)
23779 (const_int 9) (const_int 1)
23780 (const_int 10) (const_int 2)
23781 (const_int 11) (const_int 3)
23782 (const_int 12) (const_int 4)
23783 (const_int 13) (const_int 5)
23784 (const_int 14) (const_int 6)
23785 (const_int 15) (const_int 7)]))
23786 (const_int 21845)))]
23788 "punpcklbw\t{%2, %0|%0, %2}"
23789 [(set_attr "type" "ssecvt")
23790 (set_attr "mode" "TI")])
23792 (define_insn "sse2_punpcklwd"
23793 [(set (match_operand:V8HI 0 "register_operand" "=x")
23795 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
23796 (parallel [(const_int 0) (const_int 4)
23797 (const_int 1) (const_int 5)
23798 (const_int 2) (const_int 6)
23799 (const_int 3) (const_int 7)]))
23800 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
23801 (parallel [(const_int 4) (const_int 0)
23802 (const_int 5) (const_int 1)
23803 (const_int 6) (const_int 2)
23804 (const_int 7) (const_int 3)]))
23807 "punpcklwd\t{%2, %0|%0, %2}"
23808 [(set_attr "type" "ssecvt")
23809 (set_attr "mode" "TI")])
23811 (define_insn "sse2_punpckldq"
23812 [(set (match_operand:V4SI 0 "register_operand" "=x")
23814 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
23815 (parallel [(const_int 0) (const_int 2)
23816 (const_int 1) (const_int 3)]))
23817 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
23818 (parallel [(const_int 2) (const_int 0)
23819 (const_int 3) (const_int 1)]))
23822 "punpckldq\t{%2, %0|%0, %2}"
23823 [(set_attr "type" "ssecvt")
23824 (set_attr "mode" "TI")])
23826 (define_insn "sse2_punpcklqdq"
23827 [(set (match_operand:V2DI 0 "register_operand" "=x")
23829 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
23830 (parallel [(const_int 1)
23832 (match_operand:V2DI 1 "register_operand" "0")
23835 "punpcklqdq\t{%2, %0|%0, %2}"
23836 [(set_attr "type" "ssecvt")
23837 (set_attr "mode" "TI")])
23839 (define_insn "sse2_punpckhqdq"
23840 [(set (match_operand:V2DI 0 "register_operand" "=x")
23842 (match_operand:V2DI 1 "register_operand" "0")
23843 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
23844 (parallel [(const_int 1)
23848 "punpckhqdq\t{%2, %0|%0, %2}"
23849 [(set_attr "type" "ssecvt")
23850 (set_attr "mode" "TI")])
23854 (define_insn "sse2_movapd"
23855 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23856 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
23859 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23860 "movapd\t{%1, %0|%0, %1}"
23861 [(set_attr "type" "ssemov")
23862 (set_attr "mode" "V2DF")])
23864 (define_insn "sse2_movupd"
23865 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23866 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
23869 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23870 "movupd\t{%1, %0|%0, %1}"
23871 [(set_attr "type" "ssecvt")
23872 (set_attr "mode" "V2DF")])
23874 (define_insn "sse2_movdqa"
23875 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23876 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23879 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23880 "movdqa\t{%1, %0|%0, %1}"
23881 [(set_attr "type" "ssemov")
23882 (set_attr "mode" "TI")])
23884 (define_insn "sse2_movdqu"
23885 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23886 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23889 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23890 "movdqu\t{%1, %0|%0, %1}"
23891 [(set_attr "type" "ssecvt")
23892 (set_attr "mode" "TI")])
23894 (define_insn "sse2_movdq2q"
23895 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
23896 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
23897 (parallel [(const_int 0)])))]
23898 "TARGET_SSE2 && !TARGET_64BIT"
23900 movq\t{%1, %0|%0, %1}
23901 movdq2q\t{%1, %0|%0, %1}"
23902 [(set_attr "type" "ssecvt")
23903 (set_attr "mode" "TI")])
23905 (define_insn "sse2_movdq2q_rex64"
23906 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
23907 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
23908 (parallel [(const_int 0)])))]
23909 "TARGET_SSE2 && TARGET_64BIT"
23911 movq\t{%1, %0|%0, %1}
23912 movdq2q\t{%1, %0|%0, %1}
23913 movd\t{%1, %0|%0, %1}"
23914 [(set_attr "type" "ssecvt")
23915 (set_attr "mode" "TI")])
23917 (define_insn "sse2_movq2dq"
23918 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
23919 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
23921 "TARGET_SSE2 && !TARGET_64BIT"
23923 movq\t{%1, %0|%0, %1}
23924 movq2dq\t{%1, %0|%0, %1}"
23925 [(set_attr "type" "ssecvt,ssemov")
23926 (set_attr "mode" "TI")])
23928 (define_insn "sse2_movq2dq_rex64"
23929 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
23930 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
23932 "TARGET_SSE2 && TARGET_64BIT"
23934 movq\t{%1, %0|%0, %1}
23935 movq2dq\t{%1, %0|%0, %1}
23936 movd\t{%1, %0|%0, %1}"
23937 [(set_attr "type" "ssecvt,ssemov,ssecvt")
23938 (set_attr "mode" "TI")])
23940 (define_insn "sse2_movq"
23941 [(set (match_operand:V2DI 0 "register_operand" "=x")
23942 (vec_concat:V2DI (vec_select:DI
23943 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
23944 (parallel [(const_int 0)]))
23947 "movq\t{%1, %0|%0, %1}"
23948 [(set_attr "type" "ssemov")
23949 (set_attr "mode" "TI")])
23951 (define_insn "sse2_loadd"
23952 [(set (match_operand:V4SI 0 "register_operand" "=x")
23954 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
23955 (const_vector:V4SI [(const_int 0)
23961 "movd\t{%1, %0|%0, %1}"
23962 [(set_attr "type" "ssemov")
23963 (set_attr "mode" "TI")])
23965 (define_insn "sse2_stored"
23966 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
23968 (match_operand:V4SI 1 "register_operand" "x")
23969 (parallel [(const_int 0)])))]
23971 "movd\t{%1, %0|%0, %1}"
23972 [(set_attr "type" "ssemov")
23973 (set_attr "mode" "TI")])
23975 (define_insn "sse2_movhpd"
23976 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23978 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
23979 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
23981 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
23982 "movhpd\t{%2, %0|%0, %2}"
23983 [(set_attr "type" "ssecvt")
23984 (set_attr "mode" "V2DF")])
23986 (define_expand "sse2_loadsd"
23987 [(match_operand:V2DF 0 "register_operand" "")
23988 (match_operand:DF 1 "memory_operand" "")]
23991 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
23992 CONST0_RTX (V2DFmode)));
23996 (define_insn "sse2_loadsd_1"
23997 [(set (match_operand:V2DF 0 "register_operand" "=x")
23999 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
24000 (match_operand:V2DF 2 "const0_operand" "X")
24003 "movsd\t{%1, %0|%0, %1}"
24004 [(set_attr "type" "ssecvt")
24005 (set_attr "mode" "DF")])
24007 (define_insn "sse2_movsd"
24008 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
24010 (match_operand:V2DF 1 "nonimmediate_operand" "0,0,0")
24011 (match_operand:V2DF 2 "nonimmediate_operand" "x,m,x")
24013 "TARGET_SSE2 && ix86_binary_operator_ok (UNKNOWN, V2DFmode, operands)"
24014 "@movsd\t{%2, %0|%0, %2}
24015 movlpd\t{%2, %0|%0, %2}
24016 movlpd\t{%2, %0|%0, %2}"
24017 [(set_attr "type" "ssecvt")
24018 (set_attr "mode" "DF,V2DF,V2DF")])
24020 (define_insn "sse2_storesd"
24021 [(set (match_operand:DF 0 "memory_operand" "=m")
24023 (match_operand:V2DF 1 "register_operand" "x")
24024 (parallel [(const_int 0)])))]
24026 "movsd\t{%1, %0|%0, %1}"
24027 [(set_attr "type" "ssecvt")
24028 (set_attr "mode" "DF")])
24030 (define_insn "sse2_shufpd"
24031 [(set (match_operand:V2DF 0 "register_operand" "=x")
24032 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24033 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
24034 (match_operand:SI 3 "immediate_operand" "i")]
24037 ;; @@@ check operand order for intel/nonintel syntax
24038 "shufpd\t{%3, %2, %0|%0, %2, %3}"
24039 [(set_attr "type" "ssecvt")
24040 (set_attr "mode" "V2DF")])
24042 (define_insn "sse2_clflush"
24043 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
24047 [(set_attr "type" "sse")
24048 (set_attr "memory" "unknown")])
24050 (define_expand "sse2_mfence"
24051 [(set (match_dup 0)
24052 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
24055 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
24056 MEM_VOLATILE_P (operands[0]) = 1;
24059 (define_insn "*mfence_insn"
24060 [(set (match_operand:BLK 0 "" "")
24061 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
24064 [(set_attr "type" "sse")
24065 (set_attr "memory" "unknown")])
24067 (define_expand "sse2_lfence"
24068 [(set (match_dup 0)
24069 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
24072 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
24073 MEM_VOLATILE_P (operands[0]) = 1;
24076 (define_insn "*lfence_insn"
24077 [(set (match_operand:BLK 0 "" "")
24078 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
24081 [(set_attr "type" "sse")
24082 (set_attr "memory" "unknown")])
24086 (define_insn "mwait"
24087 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
24088 (match_operand:SI 1 "register_operand" "c")]
24092 [(set_attr "length" "3")])
24094 (define_insn "monitor"
24095 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
24096 (match_operand:SI 1 "register_operand" "c")
24097 (match_operand:SI 2 "register_operand" "d")]
24100 "monitor\t%0, %1, %2"
24101 [(set_attr "length" "3")])
24105 (define_insn "addsubv4sf3"
24106 [(set (match_operand:V4SF 0 "register_operand" "=x")
24107 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24108 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24111 "addsubps\t{%2, %0|%0, %2}"
24112 [(set_attr "type" "sseadd")
24113 (set_attr "mode" "V4SF")])
24115 (define_insn "addsubv2df3"
24116 [(set (match_operand:V2DF 0 "register_operand" "=x")
24117 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24118 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24121 "addsubpd\t{%2, %0|%0, %2}"
24122 [(set_attr "type" "sseadd")
24123 (set_attr "mode" "V2DF")])
24125 (define_insn "haddv4sf3"
24126 [(set (match_operand:V4SF 0 "register_operand" "=x")
24127 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24128 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24131 "haddps\t{%2, %0|%0, %2}"
24132 [(set_attr "type" "sseadd")
24133 (set_attr "mode" "V4SF")])
24135 (define_insn "haddv2df3"
24136 [(set (match_operand:V2DF 0 "register_operand" "=x")
24137 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24138 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24141 "haddpd\t{%2, %0|%0, %2}"
24142 [(set_attr "type" "sseadd")
24143 (set_attr "mode" "V2DF")])
24145 (define_insn "hsubv4sf3"
24146 [(set (match_operand:V4SF 0 "register_operand" "=x")
24147 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
24148 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
24151 "hsubps\t{%2, %0|%0, %2}"
24152 [(set_attr "type" "sseadd")
24153 (set_attr "mode" "V4SF")])
24155 (define_insn "hsubv2df3"
24156 [(set (match_operand:V2DF 0 "register_operand" "=x")
24157 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24158 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24161 "hsubpd\t{%2, %0|%0, %2}"
24162 [(set_attr "type" "sseadd")
24163 (set_attr "mode" "V2DF")])
24165 (define_insn "movshdup"
24166 [(set (match_operand:V4SF 0 "register_operand" "=x")
24168 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
24170 "movshdup\t{%1, %0|%0, %1}"
24171 [(set_attr "type" "sse")
24172 (set_attr "mode" "V4SF")])
24174 (define_insn "movsldup"
24175 [(set (match_operand:V4SF 0 "register_operand" "=x")
24177 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
24179 "movsldup\t{%1, %0|%0, %1}"
24180 [(set_attr "type" "sse")
24181 (set_attr "mode" "V4SF")])
24183 (define_insn "lddqu"
24184 [(set (match_operand:V16QI 0 "register_operand" "=x")
24185 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
24188 "lddqu\t{%1, %0|%0, %1}"
24189 [(set_attr "type" "ssecvt")
24190 (set_attr "mode" "TI")])
24192 (define_insn "loadddup"
24193 [(set (match_operand:V2DF 0 "register_operand" "=x")
24194 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
24196 "movddup\t{%1, %0|%0, %1}"
24197 [(set_attr "type" "ssecvt")
24198 (set_attr "mode" "DF")])
24200 (define_insn "movddup"
24201 [(set (match_operand:V2DF 0 "register_operand" "=x")
24202 (vec_duplicate:V2DF
24203 (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
24204 (parallel [(const_int 0)]))))]
24206 "movddup\t{%1, %0|%0, %1}"
24207 [(set_attr "type" "ssecvt")
24208 (set_attr "mode" "DF")])