1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
54 ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
55 ;; operand 0 is the memory address to scan.
56 ;; operand 1 is a register containing the value to scan for. The mode
57 ;; of the scas opcode will be the same as the mode of this operand.
58 ;; operand 2 is the known alignment of operand 0.
59 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
60 ;; operand 0 is the argument for `sin'.
61 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
62 ;; operand 0 is the argument for `cos'.
63 ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
64 ;; always SImode. operand 0 is the size of the stack allocation.
65 ;; 4 This is the source of a fake SET of the frame pointer which is used to
66 ;; prevent insns referencing it being scheduled across the initial
67 ;; decrement of the stack pointer.
68 ;; 5 This is a `bsf' operation.
69 ;; 6 This is the @GOT offset of a PIC address.
70 ;; 7 This is the @GOTOFF offset of a PIC address.
71 ;; 8 This is a reference to a symbol's @PLT address.
72 ;; 9 This is an `fnstsw' operation.
73 ;; 10 This is a `sahf' operation.
74 ;; 11 This is a `fstcw' operation
75 ;; 12 This is behaviour of add when setting carry flag.
76 ;; 13 This is a `eh_return' placeholder.
78 ;; For SSE/MMX support:
79 ;; 30 This is `fix', guaranteed to be truncating.
80 ;; 31 This is a `emms' operation.
81 ;; 32 This is a `maskmov' operation.
82 ;; 33 This is a `movmsk' operation.
83 ;; 34 This is a `non-temporal' move.
84 ;; 35 This is a `prefetch' operation.
85 ;; 36 This is used to distinguish COMISS from UCOMISS.
86 ;; 37 This is a `ldmxcsr' operation.
87 ;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
88 ;; 39 This is a forced `movups' instruction (rather than whatever movti does)
89 ;; 40 This is a `stmxcsr' operation.
90 ;; 41 This is a `shuffle' operation.
91 ;; 42 This is a `rcp' operation.
92 ;; 43 This is a `rsqsrt' operation.
93 ;; 44 This is a `sfence' operation.
94 ;; 45 This is a noop to prevent excessive combiner cleverness.
96 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
100 ;; Processor type. This attribute must exactly match the processor_type
101 ;; enumeration in i386.h.
102 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
103 (const (symbol_ref "ix86_cpu")))
105 ;; A basic instruction type. Refinements due to arguments to be
106 ;; provided in other attributes.
108 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx"
109 (const_string "other"))
111 ;; Main data type used by the insn
112 (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
113 (const_string "unknown"))
115 ;; Set for i387 operations.
116 (define_attr "i387" ""
117 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch")
121 ;; The (bounding maximum) length of an instruction immediate.
122 (define_attr "length_immediate" ""
123 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
127 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
128 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
129 (eq_attr "type" "imov,test")
130 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
131 (eq_attr "type" "call")
132 (if_then_else (match_operand 0 "constant_call_address_operand" "")
135 (eq_attr "type" "callv")
136 (if_then_else (match_operand 1 "constant_call_address_operand" "")
139 (eq_attr "type" "ibr")
140 (if_then_else (and (ge (minus (match_dup 0) (pc))
142 (lt (minus (match_dup 0) (pc))
147 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
149 ;; The (bounding maximum) length of an instruction address.
150 (define_attr "length_address" ""
151 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
153 (and (eq_attr "type" "call")
154 (match_operand 1 "constant_call_address_operand" ""))
156 (and (eq_attr "type" "callv")
157 (match_operand 1 "constant_call_address_operand" ""))
160 (symbol_ref "ix86_attr_length_address_default (insn)")))
162 ;; Set when length prefix is used.
163 (define_attr "prefix_data16" ""
164 (if_then_else (eq_attr "mode" "HI")
168 ;; Set when string REP prefix is used.
169 (define_attr "prefix_rep" "" (const_int 0))
171 ;; Set when 0f opcode prefix is used.
172 (define_attr "prefix_0f" ""
173 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
177 ;; Set when modrm byte is used.
178 (define_attr "modrm" ""
179 (cond [(eq_attr "type" "str,cld")
183 (and (eq_attr "type" "incdec")
184 (ior (match_operand:SI 1 "register_operand" "")
185 (match_operand:HI 1 "register_operand" "")))
187 (and (eq_attr "type" "push")
188 (not (match_operand 1 "memory_operand" "")))
190 (and (eq_attr "type" "pop")
191 (not (match_operand 0 "memory_operand" "")))
193 (and (eq_attr "type" "imov")
194 (and (match_operand 0 "register_operand" "")
195 (match_operand 1 "immediate_operand" "")))
200 ;; The (bounding maximum) length of an instruction in bytes.
201 (define_attr "length" ""
202 (cond [(eq_attr "type" "other,multi")
205 (plus (plus (attr "modrm")
206 (plus (attr "prefix_0f")
209 (plus (attr "prefix_rep")
210 (plus (attr "prefix_data16")
211 (plus (attr "length_immediate")
212 (attr "length_address")))))))
214 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
215 ;; `store' if there is a simple memory reference therein, or `unknown'
216 ;; if the instruction is complex.
218 (define_attr "memory" "none,load,store,both,unknown"
219 (cond [(eq_attr "type" "other,multi,str")
220 (const_string "unknown")
221 (eq_attr "type" "lea,fcmov,fpspc,cld")
222 (const_string "none")
223 (eq_attr "type" "push")
224 (if_then_else (match_operand 1 "memory_operand" "")
225 (const_string "both")
226 (const_string "store"))
227 (eq_attr "type" "pop,setcc")
228 (if_then_else (match_operand 0 "memory_operand" "")
229 (const_string "both")
230 (const_string "load"))
231 (eq_attr "type" "icmp,test")
232 (if_then_else (ior (match_operand 0 "memory_operand" "")
233 (match_operand 1 "memory_operand" ""))
234 (const_string "load")
235 (const_string "none"))
236 (eq_attr "type" "ibr")
237 (if_then_else (match_operand 0 "memory_operand" "")
238 (const_string "load")
239 (const_string "none"))
240 (eq_attr "type" "call")
241 (if_then_else (match_operand 0 "constant_call_address_operand" "")
242 (const_string "none")
243 (const_string "load"))
244 (eq_attr "type" "callv")
245 (if_then_else (match_operand 1 "constant_call_address_operand" "")
246 (const_string "none")
247 (const_string "load"))
248 (and (eq_attr "type" "alu1,negnot")
249 (match_operand 1 "memory_operand" ""))
250 (const_string "both")
251 (and (match_operand 0 "memory_operand" "")
252 (match_operand 1 "memory_operand" ""))
253 (const_string "both")
254 (match_operand 0 "memory_operand" "")
255 (const_string "store")
256 (match_operand 1 "memory_operand" "")
257 (const_string "load")
258 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
259 (match_operand 2 "memory_operand" ""))
260 (const_string "load")
261 (and (eq_attr "type" "icmov")
262 (match_operand 3 "memory_operand" ""))
263 (const_string "load")
265 (const_string "none")))
267 ;; Indicates if an instruction has both an immediate and a displacement.
269 (define_attr "imm_disp" "false,true,unknown"
270 (cond [(eq_attr "type" "other,multi")
271 (const_string "unknown")
272 (and (eq_attr "type" "icmp,test,imov")
273 (and (match_operand 0 "memory_displacement_operand" "")
274 (match_operand 1 "immediate_operand" "")))
275 (const_string "true")
276 (and (eq_attr "type" "alu,ishift,imul,idiv")
277 (and (match_operand 0 "memory_displacement_operand" "")
278 (match_operand 2 "immediate_operand" "")))
279 (const_string "true")
281 (const_string "false")))
283 ;; Indicates if an FP operation has an integer source.
285 (define_attr "fp_int_src" "false,true"
286 (const_string "false"))
288 ;; Describe a user's asm statement.
289 (define_asm_attributes
290 [(set_attr "length" "128")
291 (set_attr "type" "multi")])
293 ;; Pentium Scheduling
295 ;; The Pentium is an in-order core with two integer pipelines.
297 ;; True for insns that behave like prefixed insns on the Pentium.
298 (define_attr "pent_prefix" "false,true"
299 (if_then_else (ior (eq_attr "prefix_0f" "1")
300 (ior (eq_attr "prefix_data16" "1")
301 (eq_attr "prefix_rep" "1")))
302 (const_string "true")
303 (const_string "false")))
305 ;; Categorize how an instruction slots.
307 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
308 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
309 ;; rules, because it results in noticeably better code on non-MMX Pentium
310 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
311 ;; common, so the scheduler usualy has a non-prefixed insn to pair).
313 (define_attr "pent_pair" "uv,pu,pv,np"
314 (cond [(eq_attr "imm_disp" "true")
316 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
317 (and (eq_attr "type" "pop,push")
318 (eq_attr "memory" "!both")))
319 (if_then_else (eq_attr "pent_prefix" "true")
322 (eq_attr "type" "ibr")
324 (and (eq_attr "type" "ishift")
325 (match_operand 2 "const_int_operand" ""))
327 (and (eq_attr "type" "call")
328 (match_operand 0 "constant_call_address_operand" ""))
330 (and (eq_attr "type" "callv")
331 (match_operand 1 "constant_call_address_operand" ""))
334 (const_string "np")))
336 ;; Rough readiness numbers. Fine tuning happens in i386.c.
338 ;; u describes pipe U
339 ;; v describes pipe V
340 ;; uv describes either pipe U or V for those that can issue to either
341 ;; np describes not paring
343 ;; fpm describes fp insns of different types are not pipelined.
345 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
347 (define_function_unit "pent_np" 1 0
348 (and (eq_attr "cpu" "pentium")
349 (eq_attr "type" "imul"))
352 (define_function_unit "pent_mul" 1 1
353 (and (eq_attr "cpu" "pentium")
354 (eq_attr "type" "imul"))
357 ;; Rep movs takes minimally 12 cycles.
358 (define_function_unit "pent_np" 1 0
359 (and (eq_attr "cpu" "pentium")
360 (eq_attr "type" "str"))
363 ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
364 (define_function_unit "pent_np" 1 0
365 (and (eq_attr "cpu" "pentium")
366 (eq_attr "type" "idiv"))
369 ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
370 ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
371 ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
372 ; The integer <-> fp conversion is not modeled correctly. Fild behaves
373 ; like normal fp operation and fist takes 6 cycles.
375 (define_function_unit "fpu" 1 0
376 (and (eq_attr "cpu" "pentium")
377 (and (eq_attr "type" "fmov")
378 (and (eq_attr "memory" "load,store")
379 (eq_attr "mode" "XF"))))
382 (define_function_unit "pent_np" 1 0
383 (and (eq_attr "cpu" "pentium")
384 (and (eq_attr "type" "fmov")
385 (and (eq_attr "memory" "load,store")
386 (eq_attr "mode" "XF"))))
389 (define_function_unit "fpu" 1 0
390 (and (eq_attr "cpu" "pentium")
391 (and (eq_attr "type" "fmov")
392 (ior (match_operand 1 "immediate_operand" "")
393 (eq_attr "memory" "store"))))
396 (define_function_unit "pent_np" 1 0
397 (and (eq_attr "cpu" "pentium")
398 (and (eq_attr "type" "fmov")
399 (ior (match_operand 1 "immediate_operand" "")
400 (eq_attr "memory" "store"))))
403 (define_function_unit "pent_np" 1 0
404 (and (eq_attr "cpu" "pentium")
405 (eq_attr "type" "cld"))
408 (define_function_unit "fpu" 1 0
409 (and (eq_attr "cpu" "pentium")
410 (and (eq_attr "type" "fmov")
411 (eq_attr "memory" "none,load")))
414 ; Read/Modify/Write instructions usually take 3 cycles.
415 (define_function_unit "pent_u" 1 0
416 (and (eq_attr "cpu" "pentium")
417 (and (eq_attr "type" "alu,alu1,ishift")
418 (and (eq_attr "pent_pair" "pu")
419 (eq_attr "memory" "both"))))
422 (define_function_unit "pent_uv" 2 0
423 (and (eq_attr "cpu" "pentium")
424 (and (eq_attr "type" "alu,alu1,ishift")
425 (and (eq_attr "pent_pair" "!np")
426 (eq_attr "memory" "both"))))
429 (define_function_unit "pent_np" 1 0
430 (and (eq_attr "cpu" "pentium")
431 (and (eq_attr "type" "alu,alu1,negnot,ishift")
432 (and (eq_attr "pent_pair" "np")
433 (eq_attr "memory" "both"))))
436 ; Read/Modify or Modify/Write instructions usually take 2 cycles.
437 (define_function_unit "pent_u" 1 0
438 (and (eq_attr "cpu" "pentium")
439 (and (eq_attr "type" "alu,ishift")
440 (and (eq_attr "pent_pair" "pu")
441 (eq_attr "memory" "load,store"))))
444 (define_function_unit "pent_uv" 2 0
445 (and (eq_attr "cpu" "pentium")
446 (and (eq_attr "type" "alu,ishift")
447 (and (eq_attr "pent_pair" "!np")
448 (eq_attr "memory" "load,store"))))
451 (define_function_unit "pent_np" 1 0
452 (and (eq_attr "cpu" "pentium")
453 (and (eq_attr "type" "alu,ishift")
454 (and (eq_attr "pent_pair" "np")
455 (eq_attr "memory" "load,store"))))
458 ; Insns w/o memory operands and move instructions usually take one cycle.
459 (define_function_unit "pent_u" 1 0
460 (and (eq_attr "cpu" "pentium")
461 (eq_attr "pent_pair" "pu"))
464 (define_function_unit "pent_v" 1 0
465 (and (eq_attr "cpu" "pentium")
466 (eq_attr "pent_pair" "pv"))
469 (define_function_unit "pent_uv" 2 0
470 (and (eq_attr "cpu" "pentium")
471 (eq_attr "pent_pair" "!np"))
474 (define_function_unit "pent_np" 1 0
475 (and (eq_attr "cpu" "pentium")
476 (eq_attr "pent_pair" "np"))
479 ; Pairable insns only conflict with other non-pairable insns.
480 (define_function_unit "pent_np" 1 0
481 (and (eq_attr "cpu" "pentium")
482 (and (eq_attr "type" "alu,alu1,ishift")
483 (and (eq_attr "pent_pair" "!np")
484 (eq_attr "memory" "both"))))
486 [(eq_attr "pent_pair" "np")])
488 (define_function_unit "pent_np" 1 0
489 (and (eq_attr "cpu" "pentium")
490 (and (eq_attr "type" "alu,alu1,ishift")
491 (and (eq_attr "pent_pair" "!np")
492 (eq_attr "memory" "load,store"))))
494 [(eq_attr "pent_pair" "np")])
496 (define_function_unit "pent_np" 1 0
497 (and (eq_attr "cpu" "pentium")
498 (eq_attr "pent_pair" "!np"))
500 [(eq_attr "pent_pair" "np")])
502 ; Floating point instructions usually blocks cycle longer when combined with
503 ; integer instructions, because of the inpaired fxch instruction.
504 (define_function_unit "pent_np" 1 0
505 (and (eq_attr "cpu" "pentium")
506 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp"))
508 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp")])
510 (define_function_unit "fpu" 1 0
511 (and (eq_attr "cpu" "pentium")
512 (eq_attr "type" "fcmp,fxch,fsgn"))
515 ; Addition takes 3 cycles; assume other random cruft does as well.
516 ; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
517 (define_function_unit "fpu" 1 0
518 (and (eq_attr "cpu" "pentium")
519 (eq_attr "type" "fop,fop1"))
522 ; Multiplication takes 3 cycles and is only half pipelined.
523 (define_function_unit "fpu" 1 0
524 (and (eq_attr "cpu" "pentium")
525 (eq_attr "type" "fmul"))
528 (define_function_unit "pent_mul" 1 1
529 (and (eq_attr "cpu" "pentium")
530 (eq_attr "type" "fmul"))
533 ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
534 ; They can overlap with integer insns. Only the last two cycles can overlap
535 ; with other fp insns. Only fsin/fcos can overlap with multiplies.
536 ; Only last two cycles of fsin/fcos can overlap with other instructions.
537 (define_function_unit "fpu" 1 0
538 (and (eq_attr "cpu" "pentium")
539 (eq_attr "type" "fdiv"))
542 (define_function_unit "pent_mul" 1 1
543 (and (eq_attr "cpu" "pentium")
544 (eq_attr "type" "fdiv"))
547 (define_function_unit "fpu" 1 0
548 (and (eq_attr "cpu" "pentium")
549 (eq_attr "type" "fpspc"))
552 (define_function_unit "pent_mul" 1 1
553 (and (eq_attr "cpu" "pentium")
554 (eq_attr "type" "fpspc"))
557 ;; Pentium Pro/PII Scheduling
559 ;; The PPro has an out-of-order core, but the instruction decoders are
560 ;; naturally in-order and asymmetric. We get best performance by scheduling
561 ;; for the decoders, for in doing so we give the oo execution unit the
564 ;; Categorize how many uops an ia32 instruction evaluates to:
565 ;; one -- an instruction with 1 uop can be decoded by any of the
567 ;; few -- an instruction with 1 to 4 uops can be decoded only by
569 ;; many -- a complex instruction may take an unspecified number of
570 ;; cycles to decode in decoder 0.
572 (define_attr "ppro_uops" "one,few,many"
573 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
574 (const_string "many")
575 (eq_attr "type" "icmov,fcmov,str,cld")
577 (eq_attr "type" "imov")
578 (if_then_else (eq_attr "memory" "store,both")
580 (const_string "one"))
581 (eq_attr "memory" "!none")
584 (const_string "one")))
586 ;; Rough readiness numbers. Fine tuning happens in i386.c.
588 ;; p0 describes port 0.
589 ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
590 ;; p2 describes port 2 for loads.
591 ;; p34 describes ports 3 and 4 for stores.
592 ;; fpu describes the fpu accessed via port 0.
593 ;; ??? It is less than clear if there are separate fadd and fmul units
594 ;; that could operate in parallel.
596 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
598 (define_function_unit "ppro_p0" 1 0
599 (and (eq_attr "cpu" "pentiumpro")
600 (eq_attr "type" "ishift,lea,ibr,cld"))
603 (define_function_unit "ppro_p0" 1 0
604 (and (eq_attr "cpu" "pentiumpro")
605 (eq_attr "type" "imul"))
608 ;; ??? Does the divider lock out the pipe while it works,
609 ;; or is there a disconnected unit?
610 (define_function_unit "ppro_p0" 1 0
611 (and (eq_attr "cpu" "pentiumpro")
612 (eq_attr "type" "idiv"))
615 (define_function_unit "ppro_p0" 1 0
616 (and (eq_attr "cpu" "pentiumpro")
617 (eq_attr "type" "fop,fop1,fsgn"))
620 (define_function_unit "ppro_p0" 1 0
621 (and (eq_attr "cpu" "pentiumpro")
622 (eq_attr "type" "fcmov"))
625 (define_function_unit "ppro_p0" 1 0
626 (and (eq_attr "cpu" "pentiumpro")
627 (eq_attr "type" "fcmp"))
630 (define_function_unit "ppro_p0" 1 0
631 (and (eq_attr "cpu" "pentiumpro")
632 (eq_attr "type" "fmov"))
635 (define_function_unit "ppro_p0" 1 0
636 (and (eq_attr "cpu" "pentiumpro")
637 (eq_attr "type" "fmul"))
640 (define_function_unit "ppro_p0" 1 0
641 (and (eq_attr "cpu" "pentiumpro")
642 (eq_attr "type" "fdiv,fpspc"))
645 (define_function_unit "ppro_p01" 2 0
646 (and (eq_attr "cpu" "pentiumpro")
647 (eq_attr "type" "!imov,fmov"))
650 (define_function_unit "ppro_p01" 2 0
651 (and (and (eq_attr "cpu" "pentiumpro")
652 (eq_attr "type" "imov,fmov"))
653 (eq_attr "memory" "none"))
656 (define_function_unit "ppro_p2" 1 0
657 (and (eq_attr "cpu" "pentiumpro")
658 (ior (eq_attr "type" "pop")
659 (eq_attr "memory" "load,both")))
662 (define_function_unit "ppro_p34" 1 0
663 (and (eq_attr "cpu" "pentiumpro")
664 (ior (eq_attr "type" "push")
665 (eq_attr "memory" "store,both")))
668 (define_function_unit "fpu" 1 0
669 (and (eq_attr "cpu" "pentiumpro")
670 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov"))
673 (define_function_unit "fpu" 1 0
674 (and (eq_attr "cpu" "pentiumpro")
675 (eq_attr "type" "fmul"))
678 (define_function_unit "fpu" 1 0
679 (and (eq_attr "cpu" "pentiumpro")
680 (eq_attr "type" "fdiv,fpspc"))
683 ;; imul uses the fpu. ??? does it have the same throughput as fmul?
684 (define_function_unit "fpu" 1 0
685 (and (eq_attr "cpu" "pentiumpro")
686 (eq_attr "type" "imul"))
689 ;; AMD K6/K6-2 Scheduling
691 ;; The K6 has similar architecture to PPro. Important difference is, that
692 ;; there are only two decoders and they seems to be much slower than execution
693 ;; units. So we have to pay much more attention to proper decoding for
694 ;; schedulers. We share most of scheduler code for PPro in i386.c
696 ;; The fp unit is not pipelined and do one operation per two cycles including
699 ;; alu describes both ALU units (ALU-X and ALU-Y).
700 ;; alux describes X alu unit
701 ;; fpu describes FPU unit
702 ;; load describes load unit.
703 ;; branch describes branch unit.
704 ;; store decsribes store unit. This unit is not modelled completely and only
705 ;; used to model lea operation. Otherwise it lie outside of the critical
708 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
710 ;; The decoder specification is in the PPro section above!
712 ;; Shift instructions and certain arithmetic are issued only to X pipe.
713 (define_function_unit "k6_alux" 1 0
714 (and (eq_attr "cpu" "k6")
715 (eq_attr "type" "ishift,alu1,negnot,cld"))
718 ;; The QI mode arithmetic is issued to X pipe only.
719 (define_function_unit "k6_alux" 1 0
720 (and (eq_attr "cpu" "k6")
721 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
722 (match_operand:QI 0 "general_operand" "")))
725 (define_function_unit "k6_alu" 2 0
726 (and (eq_attr "cpu" "k6")
727 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
730 (define_function_unit "k6_alu" 2 0
731 (and (eq_attr "cpu" "k6")
732 (and (eq_attr "type" "imov")
733 (eq_attr "memory" "none")))
736 (define_function_unit "k6_branch" 1 0
737 (and (eq_attr "cpu" "k6")
738 (eq_attr "type" "call,callv,ibr"))
741 ;; Load unit have two cycle latency, but we take care for it in adjust_cost
742 (define_function_unit "k6_load" 1 0
743 (and (eq_attr "cpu" "k6")
744 (ior (eq_attr "type" "pop")
745 (eq_attr "memory" "load,both")))
748 (define_function_unit "k6_load" 1 0
749 (and (eq_attr "cpu" "k6")
750 (and (eq_attr "type" "str")
751 (eq_attr "memory" "load,both")))
754 ;; Lea have two instructions, so latency is probably 2
755 (define_function_unit "k6_store" 1 0
756 (and (eq_attr "cpu" "k6")
757 (eq_attr "type" "lea"))
760 (define_function_unit "k6_store" 1 0
761 (and (eq_attr "cpu" "k6")
762 (eq_attr "type" "str"))
765 (define_function_unit "k6_store" 1 0
766 (and (eq_attr "cpu" "k6")
767 (ior (eq_attr "type" "push")
768 (eq_attr "memory" "store,both")))
771 (define_function_unit "k6_fpu" 1 1
772 (and (eq_attr "cpu" "k6")
773 (eq_attr "type" "fop,fop1,fmov,fcmp"))
776 (define_function_unit "k6_fpu" 1 1
777 (and (eq_attr "cpu" "k6")
778 (eq_attr "type" "fmul"))
782 (define_function_unit "k6_fpu" 1 1
783 (and (eq_attr "cpu" "k6")
784 (eq_attr "type" "fdiv,fpspc"))
787 (define_function_unit "k6_alu" 2 0
788 (and (eq_attr "cpu" "k6")
789 (eq_attr "type" "imul"))
792 (define_function_unit "k6_alux" 1 0
793 (and (eq_attr "cpu" "k6")
794 (eq_attr "type" "imul"))
798 (define_function_unit "k6_alu" 2 0
799 (and (eq_attr "cpu" "k6")
800 (eq_attr "type" "idiv"))
803 (define_function_unit "k6_alux" 1 0
804 (and (eq_attr "cpu" "k6")
805 (eq_attr "type" "idiv"))
808 ;; AMD Athlon Scheduling
810 ;; The Athlon does contain three pipelined FP units, three integer units and
811 ;; three address generation units.
813 ;; The predecode logic is determining boundaries of instructions in the 64
814 ;; byte cache line. So the cache line straddling problem of K6 might be issue
815 ;; here as well, but it is not noted in the documentation.
817 ;; Three DirectPath instructions decoders and only one VectorPath decoder
818 ;; is available. They can decode three DirectPath instructions or one VectorPath
819 ;; instruction per cycle.
820 ;; Decoded macro instructions are then passed to 72 entry instruction control
822 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
824 ;; The load/store queue unit is not attached to the schedulers but
825 ;; communicates with all the execution units seperately instead.
827 (define_attr "athlon_decode" "direct,vector"
828 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
829 (const_string "vector")
830 (and (eq_attr "type" "push")
831 (match_operand 1 "memory_operand" ""))
832 (const_string "vector")
833 (and (eq_attr "type" "fmov")
834 (and (eq_attr "memory" "load,store")
835 (eq_attr "mode" "XF")))
836 (const_string "vector")]
837 (const_string "direct")))
839 (define_function_unit "athlon_vectordec" 1 0
840 (and (eq_attr "cpu" "athlon")
841 (eq_attr "athlon_decode" "vector"))
844 (define_function_unit "athlon_directdec" 3 0
845 (and (eq_attr "cpu" "athlon")
846 (eq_attr "athlon_decode" "direct"))
849 (define_function_unit "athlon_vectordec" 1 0
850 (and (eq_attr "cpu" "athlon")
851 (eq_attr "athlon_decode" "direct"))
852 1 1 [(eq_attr "athlon_decode" "vector")])
854 (define_function_unit "athlon_ieu" 3 0
855 (and (eq_attr "cpu" "athlon")
856 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
859 (define_function_unit "athlon_ieu" 3 0
860 (and (eq_attr "cpu" "athlon")
861 (eq_attr "type" "str"))
864 (define_function_unit "athlon_ieu" 3 0
865 (and (eq_attr "cpu" "athlon")
866 (eq_attr "type" "imul"))
869 (define_function_unit "athlon_ieu" 3 0
870 (and (eq_attr "cpu" "athlon")
871 (eq_attr "type" "idiv"))
874 (define_function_unit "athlon_muldiv" 1 0
875 (and (eq_attr "cpu" "athlon")
876 (eq_attr "type" "imul"))
879 (define_function_unit "athlon_muldiv" 1 0
880 (and (eq_attr "cpu" "athlon")
881 (eq_attr "type" "idiv"))
884 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
885 (cond [(eq_attr "type" "fop,fop1,fcmp")
887 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
889 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
890 (const_string "store")
891 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
893 (and (eq_attr "type" "fmov")
894 (ior (match_operand:SI 1 "register_operand" "")
895 (match_operand 1 "immediate_operand" "")))
896 (const_string "store")
897 (eq_attr "type" "fmov")
898 (const_string "muladd")]
899 (const_string "none")))
901 ;; We use latencies 1 for definitions. This is OK to model colisions
902 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
904 ;; fsin, fcos: 96-192
906 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
907 (define_function_unit "athlon_fp" 3 0
908 (and (eq_attr "cpu" "athlon")
909 (eq_attr "type" "fpspc"))
912 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
913 (define_function_unit "athlon_fp" 3 0
914 (and (eq_attr "cpu" "athlon")
915 (eq_attr "type" "fdiv"))
918 (define_function_unit "athlon_fp" 3 0
919 (and (eq_attr "cpu" "athlon")
920 (eq_attr "type" "fop,fop1,fmul"))
923 ;; XFmode loads are slow.
924 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
925 ;; there are no dependent instructions.
927 (define_function_unit "athlon_fp" 3 0
928 (and (eq_attr "cpu" "athlon")
929 (and (eq_attr "type" "fmov")
930 (and (eq_attr "memory" "load")
931 (eq_attr "mode" "XF"))))
934 (define_function_unit "athlon_fp" 3 0
935 (and (eq_attr "cpu" "athlon")
936 (eq_attr "type" "fmov,fsgn"))
939 ;; fcmp and ftst instructions
940 (define_function_unit "athlon_fp" 3 0
941 (and (eq_attr "cpu" "athlon")
942 (and (eq_attr "type" "fcmp")
943 (eq_attr "athlon_decode" "direct")))
946 ;; fcmpi instructions.
947 (define_function_unit "athlon_fp" 3 0
948 (and (eq_attr "cpu" "athlon")
949 (and (eq_attr "type" "fcmp")
950 (eq_attr "athlon_decode" "vector")))
953 (define_function_unit "athlon_fp" 3 0
954 (and (eq_attr "cpu" "athlon")
955 (eq_attr "type" "fcmov"))
958 (define_function_unit "athlon_fp_mul" 1 0
959 (and (eq_attr "cpu" "athlon")
960 (eq_attr "athlon_fpunits" "mul"))
963 (define_function_unit "athlon_fp_add" 1 0
964 (and (eq_attr "cpu" "athlon")
965 (eq_attr "athlon_fpunits" "add"))
968 (define_function_unit "athlon_fp_muladd" 2 0
969 (and (eq_attr "cpu" "athlon")
970 (eq_attr "athlon_fpunits" "muladd,mul,add"))
973 (define_function_unit "athlon_fp_store" 1 0
974 (and (eq_attr "cpu" "athlon")
975 (eq_attr "athlon_fpunits" "store"))
978 ;; We don't need to model the Adress Generation Unit, since we don't model
979 ;; the re-order buffer yet and thus we never schedule more than three operations
980 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
981 ;; decoders independently on the functional units.
983 ;(define_function_unit "athlon_agu" 3 0
984 ; (and (eq_attr "cpu" "athlon")
985 ; (and (eq_attr "memory" "!none")
986 ; (eq_attr "athlon_fpunits" "none")))
989 ;; Model load unit to avoid too long sequences of loads. We don't need to
990 ;; model store queue, since it is hardly going to be bottleneck.
992 (define_function_unit "athlon_load" 2 0
993 (and (eq_attr "cpu" "athlon")
994 (eq_attr "memory" "load,both"))
998 ;; Compare instructions.
1000 ;; All compare insns have expanders that save the operands away without
1001 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
1002 ;; after the cmp) will actually emit the cmpM.
1004 (define_expand "cmpdi"
1006 (compare:CC (match_operand:DI 0 "x86_64_general_operand" "")
1007 (match_operand:DI 1 "x86_64_general_operand" "")))]
1011 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1012 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1013 operands[0] = force_reg (DImode, operands[0]);
1014 ix86_compare_op0 = operands[0];
1015 ix86_compare_op1 = operands[1];
1019 (define_expand "cmpsi"
1021 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
1022 (match_operand:SI 1 "general_operand" "")))]
1026 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1027 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1028 operands[0] = force_reg (SImode, operands[0]);
1029 ix86_compare_op0 = operands[0];
1030 ix86_compare_op1 = operands[1];
1034 (define_expand "cmphi"
1036 (compare:CC (match_operand:HI 0 "general_operand" "")
1037 (match_operand:HI 1 "general_operand" "")))]
1041 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1042 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1043 operands[0] = force_reg (HImode, operands[0]);
1044 ix86_compare_op0 = operands[0];
1045 ix86_compare_op1 = operands[1];
1049 (define_expand "cmpqi"
1051 (compare:CC (match_operand:QI 0 "general_operand" "")
1052 (match_operand:QI 1 "general_operand" "")))]
1053 "TARGET_QIMODE_MATH"
1056 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1057 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1058 operands[0] = force_reg (QImode, operands[0]);
1059 ix86_compare_op0 = operands[0];
1060 ix86_compare_op1 = operands[1];
1064 (define_insn "cmpdi_ccno_1_rex64"
1066 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
1067 (match_operand:DI 1 "const0_operand" "n,n")))]
1068 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
1070 test{q}\\t{%0, %0|%0, %0}
1071 cmp{q}\\t{%1, %0|%0, %1}"
1072 [(set_attr "type" "test,icmp")
1073 (set_attr "length_immediate" "0,1")
1074 (set_attr "mode" "DI")])
1076 (define_insn "*cmpdi_minus_1_rex64"
1078 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
1079 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
1081 "ix86_match_ccmode (insn, CCGOCmode)"
1082 "cmp{q}\\t{%1, %0|%0, %1}"
1083 [(set_attr "type" "icmp")
1084 (set_attr "mode" "DI")])
1086 (define_expand "cmpdi_1_rex64"
1088 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
1089 (match_operand:DI 1 "general_operand" "")))]
1093 (define_insn "cmpdi_1_insn_rex64"
1095 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
1096 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
1097 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1098 "cmp{q}\\t{%1, %0|%0, %1}"
1099 [(set_attr "type" "icmp")
1100 (set_attr "mode" "DI")])
1103 (define_insn "*cmpsi_ccno_1"
1105 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
1106 (match_operand:SI 1 "const0_operand" "n,n")))]
1107 "ix86_match_ccmode (insn, CCNOmode)"
1109 test{l}\\t{%0, %0|%0, %0}
1110 cmp{l}\\t{%1, %0|%0, %1}"
1111 [(set_attr "type" "test,icmp")
1112 (set_attr "length_immediate" "0,1")
1113 (set_attr "mode" "SI")])
1115 (define_insn "*cmpsi_minus_1"
1117 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1118 (match_operand:SI 1 "general_operand" "ri,mr"))
1120 "ix86_match_ccmode (insn, CCGOCmode)"
1121 "cmp{l}\\t{%1, %0|%0, %1}"
1122 [(set_attr "type" "icmp")
1123 (set_attr "mode" "SI")])
1125 (define_expand "cmpsi_1"
1127 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1128 (match_operand:SI 1 "general_operand" "ri,mr")))]
1132 (define_insn "*cmpsi_1_insn"
1134 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1135 (match_operand:SI 1 "general_operand" "ri,mr")))]
1136 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1137 && ix86_match_ccmode (insn, CCmode)"
1138 "cmp{l}\\t{%1, %0|%0, %1}"
1139 [(set_attr "type" "icmp")
1140 (set_attr "mode" "SI")])
1142 (define_insn "*cmphi_ccno_1"
1144 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
1145 (match_operand:HI 1 "const0_operand" "n,n")))]
1146 "ix86_match_ccmode (insn, CCNOmode)"
1148 test{w}\\t{%0, %0|%0, %0}
1149 cmp{w}\\t{%1, %0|%0, %1}"
1150 [(set_attr "type" "test,icmp")
1151 (set_attr "length_immediate" "0,1")
1152 (set_attr "mode" "HI")])
1154 (define_insn "*cmphi_minus_1"
1156 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1157 (match_operand:HI 1 "general_operand" "ri,mr"))
1159 "ix86_match_ccmode (insn, CCGOCmode)"
1160 "cmp{w}\\t{%1, %0|%0, %1}"
1161 [(set_attr "type" "icmp")
1162 (set_attr "mode" "HI")])
1164 (define_insn "*cmphi_1"
1166 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1167 (match_operand:HI 1 "general_operand" "ri,mr")))]
1168 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1169 && ix86_match_ccmode (insn, CCmode)"
1170 "cmp{w}\\t{%1, %0|%0, %1}"
1171 [(set_attr "type" "icmp")
1172 (set_attr "mode" "HI")])
1174 (define_insn "*cmpqi_ccno_1"
1176 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
1177 (match_operand:QI 1 "const0_operand" "n,n")))]
1178 "ix86_match_ccmode (insn, CCNOmode)"
1180 test{b}\\t{%0, %0|%0, %0}
1181 cmp{b}\\t{$0, %0|%0, 0}"
1182 [(set_attr "type" "test,icmp")
1183 (set_attr "length_immediate" "0,1")
1184 (set_attr "mode" "QI")])
1186 (define_insn "*cmpqi_1"
1188 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1189 (match_operand:QI 1 "general_operand" "qi,mq")))]
1190 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1191 && ix86_match_ccmode (insn, CCmode)"
1192 "cmp{b}\\t{%1, %0|%0, %1}"
1193 [(set_attr "type" "icmp")
1194 (set_attr "mode" "QI")])
1196 (define_insn "*cmpqi_minus_1"
1198 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1199 (match_operand:QI 1 "general_operand" "qi,mq"))
1201 "ix86_match_ccmode (insn, CCGOCmode)"
1202 "cmp{b}\\t{%1, %0|%0, %1}"
1203 [(set_attr "type" "icmp")
1204 (set_attr "mode" "QI")])
1206 (define_insn "*cmpqi_ext_1"
1209 (match_operand:QI 0 "general_operand" "Qm")
1212 (match_operand 1 "ext_register_operand" "Q")
1214 (const_int 8)) 0)))]
1215 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1216 "cmp{b}\\t{%h1, %0|%0, %h1}"
1217 [(set_attr "type" "icmp")
1218 (set_attr "mode" "QI")])
1220 (define_insn "*cmpqi_ext_1_rex64"
1223 (match_operand:QI 0 "ext_register_operand" "Q")
1226 (match_operand 1 "ext_register_operand" "Q")
1228 (const_int 8)) 0)))]
1229 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1230 "cmp{b}\\t{%h1, %0|%0, %h1}"
1231 [(set_attr "type" "icmp")
1232 (set_attr "mode" "QI")])
1234 (define_insn "*cmpqi_ext_2"
1239 (match_operand 0 "ext_register_operand" "Q")
1242 (match_operand:QI 1 "const0_operand" "n")))]
1243 "ix86_match_ccmode (insn, CCNOmode)"
1244 "test{b}\\t%h0, %h0"
1245 [(set_attr "type" "test")
1246 (set_attr "length_immediate" "0")
1247 (set_attr "mode" "QI")])
1249 (define_expand "cmpqi_ext_3"
1254 (match_operand 0 "ext_register_operand" "")
1257 (match_operand:QI 1 "general_operand" "")))]
1261 (define_insn "cmpqi_ext_3_insn"
1266 (match_operand 0 "ext_register_operand" "Q")
1269 (match_operand:QI 1 "general_operand" "Qmn")))]
1270 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1271 "cmp{b}\\t{%1, %h0|%h0, %1}"
1272 [(set_attr "type" "icmp")
1273 (set_attr "mode" "QI")])
1275 (define_insn "cmpqi_ext_3_insn_rex64"
1280 (match_operand 0 "ext_register_operand" "Q")
1283 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1284 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1285 "cmp{b}\\t{%1, %h0|%h0, %1}"
1286 [(set_attr "type" "icmp")
1287 (set_attr "mode" "QI")])
1289 (define_insn "*cmpqi_ext_4"
1294 (match_operand 0 "ext_register_operand" "Q")
1299 (match_operand 1 "ext_register_operand" "Q")
1301 (const_int 8)) 0)))]
1302 "ix86_match_ccmode (insn, CCmode)"
1303 "cmp{b}\\t{%h1, %h0|%h0, %h1}"
1304 [(set_attr "type" "icmp")
1305 (set_attr "mode" "QI")])
1307 ;; These implement float point compares.
1308 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1309 ;; which would allow mix and match FP modes on the compares. Which is what
1310 ;; the old patterns did, but with many more of them.
1312 (define_expand "cmpxf"
1314 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
1315 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
1316 "TARGET_80387 && !TARGET_64BIT"
1319 ix86_compare_op0 = operands[0];
1320 ix86_compare_op1 = operands[1];
1324 (define_expand "cmptf"
1326 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
1327 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
1331 ix86_compare_op0 = operands[0];
1332 ix86_compare_op1 = operands[1];
1336 (define_expand "cmpdf"
1338 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
1339 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
1340 "TARGET_80387 || TARGET_SSE2"
1343 ix86_compare_op0 = operands[0];
1344 ix86_compare_op1 = operands[1];
1348 (define_expand "cmpsf"
1350 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
1351 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
1352 "TARGET_80387 || TARGET_SSE"
1355 ix86_compare_op0 = operands[0];
1356 ix86_compare_op1 = operands[1];
1360 ;; FP compares, step 1:
1361 ;; Set the FP condition codes.
1363 ;; CCFPmode compare with exceptions
1364 ;; CCFPUmode compare with no exceptions
1366 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
1367 ;; and that fp moves clobber the condition codes, and that there is
1368 ;; currently no way to describe this fact to reg-stack. So there are
1369 ;; no splitters yet for this.
1371 ;; %%% YIKES! This scheme does not retain a strong connection between
1372 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
1373 ;; work! Only allow tos/mem with tos in op 0.
1375 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
1376 ;; things aren't as bad as they sound...
1378 (define_insn "*cmpfp_0"
1379 [(set (match_operand:HI 0 "register_operand" "=a")
1381 [(compare:CCFP (match_operand 1 "register_operand" "f")
1382 (match_operand 2 "const0_operand" "X"))] 9))]
1384 && FLOAT_MODE_P (GET_MODE (operands[1]))
1385 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1388 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1389 return \"ftst\;fnstsw\\t%0\;fstp\\t%y0\";
1391 return \"ftst\;fnstsw\\t%0\";
1393 [(set_attr "type" "multi")
1394 (set_attr "mode" "unknownfp")])
1396 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1397 ;; used to manage the reg stack popping would not be preserved.
1399 (define_insn "*cmpfp_2_sf"
1402 (match_operand:SF 0 "register_operand" "f")
1403 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
1405 "* return output_fp_compare (insn, operands, 0, 0);"
1406 [(set_attr "type" "fcmp")
1407 (set_attr "mode" "SF")])
1409 (define_insn "*cmpfp_2_sf_1"
1410 [(set (match_operand:HI 0 "register_operand" "=a")
1413 (match_operand:SF 1 "register_operand" "f")
1414 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
1416 "* return output_fp_compare (insn, operands, 2, 0);"
1417 [(set_attr "type" "fcmp")
1418 (set_attr "mode" "SF")])
1420 (define_insn "*cmpfp_2_df"
1423 (match_operand:DF 0 "register_operand" "f")
1424 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
1426 "* return output_fp_compare (insn, operands, 0, 0);"
1427 [(set_attr "type" "fcmp")
1428 (set_attr "mode" "DF")])
1430 (define_insn "*cmpfp_2_df_1"
1431 [(set (match_operand:HI 0 "register_operand" "=a")
1434 (match_operand:DF 1 "register_operand" "f")
1435 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
1437 "* return output_fp_compare (insn, operands, 2, 0);"
1438 [(set_attr "type" "multi")
1439 (set_attr "mode" "DF")])
1441 (define_insn "*cmpfp_2_xf"
1444 (match_operand:XF 0 "register_operand" "f")
1445 (match_operand:XF 1 "register_operand" "f")))]
1446 "TARGET_80387 && !TARGET_64BIT"
1447 "* return output_fp_compare (insn, operands, 0, 0);"
1448 [(set_attr "type" "fcmp")
1449 (set_attr "mode" "XF")])
1451 (define_insn "*cmpfp_2_tf"
1454 (match_operand:TF 0 "register_operand" "f")
1455 (match_operand:TF 1 "register_operand" "f")))]
1457 "* return output_fp_compare (insn, operands, 0, 0);"
1458 [(set_attr "type" "fcmp")
1459 (set_attr "mode" "XF")])
1461 (define_insn "*cmpfp_2_xf_1"
1462 [(set (match_operand:HI 0 "register_operand" "=a")
1465 (match_operand:XF 1 "register_operand" "f")
1466 (match_operand:XF 2 "register_operand" "f"))] 9))]
1467 "TARGET_80387 && !TARGET_64BIT"
1468 "* return output_fp_compare (insn, operands, 2, 0);"
1469 [(set_attr "type" "multi")
1470 (set_attr "mode" "XF")])
1472 (define_insn "*cmpfp_2_tf_1"
1473 [(set (match_operand:HI 0 "register_operand" "=a")
1476 (match_operand:TF 1 "register_operand" "f")
1477 (match_operand:TF 2 "register_operand" "f"))] 9))]
1479 "* return output_fp_compare (insn, operands, 2, 0);"
1480 [(set_attr "type" "multi")
1481 (set_attr "mode" "XF")])
1483 (define_insn "*cmpfp_2u"
1484 [(set (reg:CCFPU 18)
1486 (match_operand 0 "register_operand" "f")
1487 (match_operand 1 "register_operand" "f")))]
1489 && FLOAT_MODE_P (GET_MODE (operands[0]))
1490 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1491 "* return output_fp_compare (insn, operands, 0, 1);"
1492 [(set_attr "type" "fcmp")
1493 (set_attr "mode" "unknownfp")])
1495 (define_insn "*cmpfp_2u_1"
1496 [(set (match_operand:HI 0 "register_operand" "=a")
1499 (match_operand 1 "register_operand" "f")
1500 (match_operand 2 "register_operand" "f"))] 9))]
1502 && FLOAT_MODE_P (GET_MODE (operands[1]))
1503 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1504 "* return output_fp_compare (insn, operands, 2, 1);"
1505 [(set_attr "type" "multi")
1506 (set_attr "mode" "unknownfp")])
1508 ;; Patterns to match the SImode-in-memory ficom instructions.
1510 ;; %%% Play games with accepting gp registers, as otherwise we have to
1511 ;; force them to memory during rtl generation, which is no good. We
1512 ;; can get rid of this once we teach reload to do memory input reloads
1515 (define_insn "*ficom_1"
1518 (match_operand 0 "register_operand" "f,f")
1519 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
1520 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
1521 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
1524 ;; Split the not-really-implemented gp register case into a
1525 ;; push-op-pop sequence.
1527 ;; %%% This is most efficient, but am I gonna get in trouble
1528 ;; for separating cc0_setter and cc0_user?
1533 (match_operand:SF 0 "register_operand" "")
1534 (float (match_operand:SI 1 "register_operand" ""))))]
1535 "0 && TARGET_80387 && reload_completed"
1536 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
1537 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
1538 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
1539 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
1540 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1541 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
1543 ;; FP compares, step 2
1544 ;; Move the fpsw to ax.
1546 (define_insn "x86_fnstsw_1"
1547 [(set (match_operand:HI 0 "register_operand" "=a")
1548 (unspec:HI [(reg 18)] 9))]
1551 [(set_attr "length" "2")
1552 (set_attr "mode" "SI")
1553 (set_attr "i387" "1")
1554 (set_attr "ppro_uops" "few")])
1556 ;; FP compares, step 3
1557 ;; Get ax into flags, general case.
1559 (define_insn "x86_sahf_1"
1561 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
1564 [(set_attr "length" "1")
1565 (set_attr "athlon_decode" "vector")
1566 (set_attr "mode" "SI")
1567 (set_attr "ppro_uops" "one")])
1569 ;; Pentium Pro can do steps 1 through 3 in one go.
1571 (define_insn "*cmpfp_i"
1573 (compare:CCFP (match_operand 0 "register_operand" "f")
1574 (match_operand 1 "register_operand" "f")))]
1575 "TARGET_80387 && TARGET_CMOVE
1576 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1577 && FLOAT_MODE_P (GET_MODE (operands[0]))
1578 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1579 "* return output_fp_compare (insn, operands, 1, 0);"
1580 [(set_attr "type" "fcmp")
1581 (set_attr "mode" "unknownfp")
1582 (set_attr "athlon_decode" "vector")])
1584 (define_insn "*cmpfp_i_sse"
1586 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1587 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1589 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1590 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1591 "* return output_fp_compare (insn, operands, 1, 0);"
1592 [(set_attr "type" "fcmp,sse")
1593 (set_attr "mode" "unknownfp")
1594 (set_attr "athlon_decode" "vector")])
1596 (define_insn "*cmpfp_i_sse_only"
1598 (compare:CCFP (match_operand 0 "register_operand" "x")
1599 (match_operand 1 "nonimmediate_operand" "xm")))]
1600 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1601 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1602 "* return output_fp_compare (insn, operands, 1, 0);"
1603 [(set_attr "type" "sse")
1604 (set_attr "mode" "unknownfp")
1605 (set_attr "athlon_decode" "vector")])
1607 (define_insn "*cmpfp_iu"
1608 [(set (reg:CCFPU 17)
1609 (compare:CCFPU (match_operand 0 "register_operand" "f")
1610 (match_operand 1 "register_operand" "f")))]
1611 "TARGET_80387 && TARGET_CMOVE
1612 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1613 && FLOAT_MODE_P (GET_MODE (operands[0]))
1614 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1615 "* return output_fp_compare (insn, operands, 1, 1);"
1616 [(set_attr "type" "fcmp")
1617 (set_attr "mode" "unknownfp")
1618 (set_attr "athlon_decode" "vector")])
1620 (define_insn "*cmpfp_iu_sse"
1621 [(set (reg:CCFPU 17)
1622 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1623 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1625 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1626 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1627 "* return output_fp_compare (insn, operands, 1, 1);"
1628 [(set_attr "type" "fcmp,sse")
1629 (set_attr "mode" "unknownfp")
1630 (set_attr "athlon_decode" "vector")])
1632 (define_insn "*cmpfp_iu_sse_only"
1633 [(set (reg:CCFPU 17)
1634 (compare:CCFPU (match_operand 0 "register_operand" "x")
1635 (match_operand 1 "nonimmediate_operand" "xm")))]
1636 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1637 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1638 "* return output_fp_compare (insn, operands, 1, 1);"
1639 [(set_attr "type" "sse")
1640 (set_attr "mode" "unknownfp")
1641 (set_attr "athlon_decode" "vector")])
1643 ;; Move instructions.
1645 ;; General case of fullword move.
1647 (define_expand "movsi"
1648 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1649 (match_operand:SI 1 "general_operand" ""))]
1651 "ix86_expand_move (SImode, operands); DONE;")
1653 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1656 ;; %%% We don't use a post-inc memory reference because x86 is not a
1657 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1658 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1659 ;; targets without our curiosities, and it is just as easy to represent
1660 ;; this differently.
1662 (define_insn "*pushsi2"
1663 [(set (match_operand:SI 0 "push_operand" "=<")
1664 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1667 [(set_attr "type" "push")
1668 (set_attr "mode" "SI")])
1670 ;; For 64BIT abi we always round up to 8 bytes.
1671 (define_insn "*pushsi2_rex64"
1672 [(set (match_operand:SI 0 "push_operand" "=X")
1673 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1676 [(set_attr "type" "push")
1677 (set_attr "mode" "SI")])
1679 (define_insn "*pushsi2_prologue"
1680 [(set (match_operand:SI 0 "push_operand" "=<")
1681 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1682 (set (reg:SI 6) (reg:SI 6))]
1685 [(set_attr "type" "push")
1686 (set_attr "mode" "SI")])
1688 (define_insn "*popsi1_epilogue"
1689 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1690 (mem:SI (reg:SI 7)))
1692 (plus:SI (reg:SI 7) (const_int 4)))
1693 (set (reg:SI 6) (reg:SI 6))]
1696 [(set_attr "type" "pop")
1697 (set_attr "mode" "SI")])
1699 (define_insn "popsi1"
1700 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1701 (mem:SI (reg:SI 7)))
1703 (plus:SI (reg:SI 7) (const_int 4)))]
1706 [(set_attr "type" "pop")
1707 (set_attr "mode" "SI")])
1709 (define_insn "*movsi_xor"
1710 [(set (match_operand:SI 0 "register_operand" "=r")
1711 (match_operand:SI 1 "const0_operand" "i"))
1712 (clobber (reg:CC 17))]
1713 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1714 "xor{l}\\t{%0, %0|%0, %0}"
1715 [(set_attr "type" "alu1")
1716 (set_attr "mode" "SI")
1717 (set_attr "length_immediate" "0")])
1719 (define_insn "*movsi_or"
1720 [(set (match_operand:SI 0 "register_operand" "=r")
1721 (match_operand:SI 1 "immediate_operand" "i"))
1722 (clobber (reg:CC 17))]
1723 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1724 && INTVAL (operands[1]) == -1
1725 && (TARGET_PENTIUM || optimize_size)"
1728 operands[1] = constm1_rtx;
1729 return \"or{l}\\t{%1, %0|%0, %1}\";
1731 [(set_attr "type" "alu1")
1732 (set_attr "mode" "SI")
1733 (set_attr "length_immediate" "1")])
1735 (define_insn "*movsi_1"
1736 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!r")
1737 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,r,*y"))]
1738 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1741 switch (get_attr_type (insn))
1744 return \"movd\\t{%1, %0|%0, %1}\";
1747 return \"lea{l}\\t{%1, %0|%0, %1}\";
1750 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1752 return \"mov{l}\\t{%1, %0|%0, %1}\";
1756 (cond [(ior (match_operand:SI 0 "mmx_reg_operand" "")
1757 (match_operand:SI 1 "mmx_reg_operand" ""))
1758 (const_string "mmx")
1759 (and (ne (symbol_ref "flag_pic") (const_int 0))
1760 (match_operand:SI 1 "symbolic_operand" ""))
1761 (const_string "lea")
1763 (const_string "imov")))
1764 (set_attr "modrm" "0,*,0,*,*,*")
1765 (set_attr "mode" "SI")])
1767 ;; Stores and loads of ax to arbitary constant address.
1768 ;; We fake an second form of instruction to force reload to load address
1769 ;; into register when rax is not available
1770 (define_insn "*movabssi_1_rex64"
1771 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1772 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1775 movabs{l}\\t{%1, %P0|%P0, %1}
1776 mov{l}\\t{%1, %a0|%a0, %1}
1777 movabs{l}\\t{%1, %a0|%a0, %1}"
1778 [(set_attr "type" "imov")
1779 (set_attr "modrm" "0,*,*")
1780 (set_attr "length_address" "8,0,0")
1781 (set_attr "length_immediate" "0,*,*")
1782 (set_attr "memory" "store")
1783 (set_attr "mode" "SI")])
1785 (define_insn "*movabssi_2_rex64"
1786 [(set (match_operand:SI 0 "register_operand" "=a,r")
1787 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1790 movabs{l}\\t{%P1, %0|%0, %P1}
1791 mov{l}\\t{%a1, %0|%0, %a1}"
1792 [(set_attr "type" "imov")
1793 (set_attr "modrm" "0,*")
1794 (set_attr "length_address" "8,0")
1795 (set_attr "length_immediate" "0")
1796 (set_attr "memory" "load")
1797 (set_attr "mode" "SI")])
1799 (define_insn "*swapsi"
1800 [(set (match_operand:SI 0 "register_operand" "+r")
1801 (match_operand:SI 1 "register_operand" "+r"))
1806 [(set_attr "type" "imov")
1807 (set_attr "pent_pair" "np")
1808 (set_attr "athlon_decode" "vector")
1809 (set_attr "mode" "SI")
1810 (set_attr "modrm" "0")
1811 (set_attr "ppro_uops" "few")])
1813 (define_expand "movhi"
1814 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1815 (match_operand:HI 1 "general_operand" ""))]
1817 "ix86_expand_move (HImode, operands); DONE;")
1819 (define_insn "*pushhi2"
1820 [(set (match_operand:HI 0 "push_operand" "=<,<")
1821 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1824 push{w}\\t{|WORD PTR }%1
1826 [(set_attr "type" "push")
1827 (set_attr "mode" "HI")])
1829 (define_insn "*movhi_1"
1830 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1831 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1832 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1835 switch (get_attr_type (insn))
1838 /* movzwl is faster than movw on p2 due to partial word stalls,
1839 though not as fast as an aligned movl. */
1840 return \"movz{wl|x}\\t{%1, %k0|%k0, %1}\";
1842 if (get_attr_mode (insn) == MODE_SI)
1843 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
1845 return \"mov{w}\\t{%1, %0|%0, %1}\";
1849 (cond [(and (eq_attr "alternative" "0,1")
1850 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1852 (eq (symbol_ref "TARGET_HIMODE_MATH")
1854 (const_string "imov")
1855 (and (eq_attr "alternative" "2,3,4")
1856 (match_operand:HI 1 "aligned_operand" ""))
1857 (const_string "imov")
1858 (and (ne (symbol_ref "TARGET_MOVX")
1860 (eq_attr "alternative" "0,1,3,4"))
1861 (const_string "imovx")
1863 (const_string "imov")))
1865 (cond [(eq_attr "type" "imovx")
1867 (and (eq_attr "alternative" "2,3,4")
1868 (match_operand:HI 1 "aligned_operand" ""))
1870 (and (eq_attr "alternative" "0,1")
1871 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1873 (eq (symbol_ref "TARGET_HIMODE_MATH")
1877 (const_string "HI")))
1878 (set_attr "modrm" "0,*,*,0,*,*")])
1880 ;; Stores and loads of ax to arbitary constant address.
1881 ;; We fake an second form of instruction to force reload to load address
1882 ;; into register when rax is not available
1883 (define_insn "*movabshi_1_rex64"
1884 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1885 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1888 movabs{w}\\t{%1, %P0|%P0, %1}
1889 mov{w}\\t{%1, %a0|%a0, %1}
1890 movabs{w}\\t{%1, %a0|%a0, %1}"
1891 [(set_attr "type" "imov")
1892 (set_attr "modrm" "0,*,*")
1893 (set_attr "length_address" "8,0,0")
1894 (set_attr "length_immediate" "0,*,*")
1895 (set_attr "memory" "store")
1896 (set_attr "mode" "HI")])
1898 (define_insn "*movabshi_2_rex64"
1899 [(set (match_operand:HI 0 "register_operand" "=a,r")
1900 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1903 movabs{w}\\t{%P1, %0|%0, %P1}
1904 mov{w}\\t{%a1, %0|%0, %a1}"
1905 [(set_attr "type" "imov")
1906 (set_attr "modrm" "0,*")
1907 (set_attr "length_address" "8,0")
1908 (set_attr "length_immediate" "0")
1909 (set_attr "memory" "load")
1910 (set_attr "mode" "HI")])
1912 (define_insn "*swaphi_1"
1913 [(set (match_operand:HI 0 "register_operand" "+r")
1914 (match_operand:HI 1 "register_operand" "+r"))
1917 "TARGET_PARTIAL_REG_STALL"
1919 [(set_attr "type" "imov")
1920 (set_attr "pent_pair" "np")
1921 (set_attr "mode" "HI")
1922 (set_attr "modrm" "0")
1923 (set_attr "ppro_uops" "few")])
1925 (define_insn "*swaphi_2"
1926 [(set (match_operand:HI 0 "register_operand" "+r")
1927 (match_operand:HI 1 "register_operand" "+r"))
1930 "! TARGET_PARTIAL_REG_STALL"
1931 "xchg{l}\\t%k1, %k0"
1932 [(set_attr "type" "imov")
1933 (set_attr "pent_pair" "np")
1934 (set_attr "mode" "SI")
1935 (set_attr "modrm" "0")
1936 (set_attr "ppro_uops" "few")])
1938 (define_expand "movstricthi"
1939 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1940 (match_operand:HI 1 "general_operand" ""))]
1941 "! TARGET_PARTIAL_REG_STALL"
1944 /* Don't generate memory->memory moves, go through a register */
1945 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1946 operands[1] = force_reg (HImode, operands[1]);
1949 (define_insn "*movstricthi_1"
1950 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1951 (match_operand:HI 1 "general_operand" "rn,m"))]
1952 "! TARGET_PARTIAL_REG_STALL
1953 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1954 "mov{w}\\t{%1, %0|%0, %1}"
1955 [(set_attr "type" "imov")
1956 (set_attr "mode" "HI")])
1958 (define_insn "*movstricthi_xor"
1959 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1960 (match_operand:HI 1 "const0_operand" "i"))
1961 (clobber (reg:CC 17))]
1962 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1963 "xor{w}\\t{%0, %0|%0, %0}"
1964 [(set_attr "type" "alu1")
1965 (set_attr "mode" "HI")
1966 (set_attr "length_immediate" "0")])
1968 (define_expand "movqi"
1969 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1970 (match_operand:QI 1 "general_operand" ""))]
1972 "ix86_expand_move (QImode, operands); DONE;")
1974 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1975 ;; "push a byte". But actually we use pushw, which has the effect
1976 ;; of rounding the amount pushed up to a halfword.
1978 (define_insn "*pushqi2"
1979 [(set (match_operand:QI 0 "push_operand" "=X,X")
1980 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1983 push{w}\\t{|word ptr }%1
1985 [(set_attr "type" "push")
1986 (set_attr "mode" "HI")])
1988 ;; Situation is quite tricky about when to choose full sized (SImode) move
1989 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1990 ;; partial register dependency machines (such as AMD Athlon), where QImode
1991 ;; moves issue extra dependency and for partial register stalls machines
1992 ;; that don't use QImode patterns (and QImode move cause stall on the next
1995 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1996 ;; register stall machines with, where we use QImode instructions, since
1997 ;; partial register stall can be caused there. Then we use movzx.
1998 (define_insn "*movqi_1"
1999 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
2000 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
2001 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
2004 switch (get_attr_type (insn))
2007 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
2009 return \"movz{bl|x}\\t{%1, %k0|%k0, %1}\";
2011 if (get_attr_mode (insn) == MODE_SI)
2012 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2014 return \"mov{b}\\t{%1, %0|%0, %1}\";
2018 (cond [(and (eq_attr "alternative" "3")
2019 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
2021 (eq (symbol_ref "TARGET_QIMODE_MATH")
2023 (const_string "imov")
2024 (eq_attr "alternative" "3,5")
2025 (const_string "imovx")
2026 (and (ne (symbol_ref "TARGET_MOVX")
2028 (eq_attr "alternative" "2"))
2029 (const_string "imovx")
2031 (const_string "imov")))
2033 (cond [(eq_attr "alternative" "3,4,5")
2035 (eq_attr "alternative" "6")
2037 (eq_attr "type" "imovx")
2039 (and (eq_attr "type" "imov")
2040 (and (eq_attr "alternative" "0,1,2")
2041 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
2044 ;; Avoid partial register stalls when not using QImode arithmetic
2045 (and (eq_attr "type" "imov")
2046 (and (eq_attr "alternative" "0,1,2")
2047 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
2049 (eq (symbol_ref "TARGET_QIMODE_MATH")
2053 (const_string "QI")))])
2055 (define_expand "reload_outqi"
2056 [(parallel [(match_operand:QI 0 "" "=m")
2057 (match_operand:QI 1 "register_operand" "r")
2058 (match_operand:QI 2 "register_operand" "=&q")])]
2063 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
2065 if (reg_overlap_mentioned_p (op2, op0))
2067 if (! q_regs_operand (op1, QImode))
2069 emit_insn (gen_movqi (op2, op1));
2072 emit_insn (gen_movqi (op0, op1));
2076 (define_insn "*swapqi"
2077 [(set (match_operand:QI 0 "register_operand" "+r")
2078 (match_operand:QI 1 "register_operand" "+r"))
2083 [(set_attr "type" "imov")
2084 (set_attr "pent_pair" "np")
2085 (set_attr "mode" "QI")
2086 (set_attr "modrm" "0")
2087 (set_attr "ppro_uops" "few")])
2089 (define_expand "movstrictqi"
2090 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
2091 (match_operand:QI 1 "general_operand" ""))]
2092 "! TARGET_PARTIAL_REG_STALL"
2095 /* Don't generate memory->memory moves, go through a register */
2096 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2097 operands[1] = force_reg (QImode, operands[1]);
2100 (define_insn "*movstrictqi_1"
2101 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
2102 (match_operand:QI 1 "general_operand" "*qn,m"))]
2103 "! TARGET_PARTIAL_REG_STALL
2104 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2105 "mov{b}\\t{%1, %0|%0, %1}"
2106 [(set_attr "type" "imov")
2107 (set_attr "mode" "QI")])
2109 (define_insn "*movstrictqi_xor"
2110 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
2111 (match_operand:QI 1 "const0_operand" "i"))
2112 (clobber (reg:CC 17))]
2113 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
2114 "xor{b}\\t{%0, %0|%0, %0}"
2115 [(set_attr "type" "alu1")
2116 (set_attr "mode" "QI")
2117 (set_attr "length_immediate" "0")])
2119 (define_insn "*movsi_extv_1"
2120 [(set (match_operand:SI 0 "register_operand" "=R")
2121 (sign_extract:SI (match_operand:SI 1 "ext_register_operand" "Q")
2125 "movs{bl|x}\\t{%h1, %0|%0, %h1}"
2126 [(set_attr "type" "imovx")
2127 (set_attr "mode" "SI")])
2129 (define_insn "*movhi_extv_1"
2130 [(set (match_operand:HI 0 "register_operand" "=R")
2131 (sign_extract:HI (match_operand:SI 1 "ext_register_operand" "Q")
2135 "movs{bl|x}\\t{%h1, %k0|%k0, %h1}"
2136 [(set_attr "type" "imovx")
2137 (set_attr "mode" "SI")])
2139 (define_insn "*movqi_extv_1"
2140 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2141 (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
2147 switch (get_attr_type (insn))
2150 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2152 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2156 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2157 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2158 (ne (symbol_ref "TARGET_MOVX")
2160 (const_string "imovx")
2161 (const_string "imov")))
2163 (if_then_else (eq_attr "type" "imovx")
2165 (const_string "QI")))])
2167 (define_insn "*movqi_extv_1_rex64"
2168 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2169 (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
2175 switch (get_attr_type (insn))
2178 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2180 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2184 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2185 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2186 (ne (symbol_ref "TARGET_MOVX")
2188 (const_string "imovx")
2189 (const_string "imov")))
2191 (if_then_else (eq_attr "type" "imovx")
2193 (const_string "QI")))])
2195 ;; Stores and loads of ax to arbitary constant address.
2196 ;; We fake an second form of instruction to force reload to load address
2197 ;; into register when rax is not available
2198 (define_insn "*movabsqi_1_rex64"
2199 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2200 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
2203 movabs{q}\\t{%1, %P0|%P0, %1}
2204 mov{q}\\t{%1, %a0|%a0, %1}
2205 movabs{q}\\t{%1, %a0|%a0, %1}"
2206 [(set_attr "type" "imov")
2207 (set_attr "modrm" "0,*,*")
2208 (set_attr "length_address" "8,0,0")
2209 (set_attr "length_immediate" "0,*,*")
2210 (set_attr "memory" "store")
2211 (set_attr "mode" "QI")])
2213 (define_insn "*movabsqi_2_rex64"
2214 [(set (match_operand:QI 0 "register_operand" "=a,r")
2215 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2218 movabs{q}\\t{%P1, %0|%0, %P1}
2219 mov{q}\\t{%a1, %0|%0, %a1}"
2220 [(set_attr "type" "imov")
2221 (set_attr "modrm" "0,*")
2222 (set_attr "length_address" "8,0")
2223 (set_attr "length_immediate" "0")
2224 (set_attr "memory" "load")
2225 (set_attr "mode" "QI")])
2227 (define_insn "*movsi_extzv_1"
2228 [(set (match_operand:SI 0 "register_operand" "=R")
2229 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
2233 "movz{bl|x}\\t{%h1, %0|%0, %h1}"
2234 [(set_attr "type" "imovx")
2235 (set_attr "mode" "SI")])
2237 (define_insn "*movqi_extzv_2"
2238 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2239 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2245 switch (get_attr_type (insn))
2248 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2250 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2254 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2255 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2256 (ne (symbol_ref "TARGET_MOVX")
2258 (const_string "imovx")
2259 (const_string "imov")))
2261 (if_then_else (eq_attr "type" "imovx")
2263 (const_string "QI")))])
2265 (define_insn "*movqi_extzv_2_rex64"
2266 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2267 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2273 switch (get_attr_type (insn))
2276 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2278 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2282 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2283 (ne (symbol_ref "TARGET_MOVX")
2285 (const_string "imovx")
2286 (const_string "imov")))
2288 (if_then_else (eq_attr "type" "imovx")
2290 (const_string "QI")))])
2292 (define_insn "*movsi_insv_1"
2293 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2296 (match_operand:SI 1 "nonimmediate_operand" "Qm"))]
2298 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2299 [(set_attr "type" "imov")
2300 (set_attr "mode" "QI")])
2302 (define_insn "*movsi_insv_1_rex64"
2303 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2306 (match_operand:SI 1 "ext_register_operand" "Q"))]
2308 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2309 [(set_attr "type" "imov")
2310 (set_attr "mode" "QI")])
2312 (define_insn "*movqi_insv_2"
2313 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2316 (and:SI (lshiftrt:SI (match_operand:SI 1 "ext_register_operand" "Q")
2320 "mov{b}\\t{%h1, %h0|%h0, %h1}"
2321 [(set_attr "type" "imov")
2322 (set_attr "mode" "QI")])
2324 (define_expand "movdi"
2325 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2326 (match_operand:DI 1 "general_operand" ""))]
2328 "ix86_expand_move (DImode, operands); DONE;")
2330 (define_insn "*pushdi"
2331 [(set (match_operand:DI 0 "push_operand" "=<")
2332 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2336 (define_insn "pushdi2_rex64"
2337 [(set (match_operand:DI 0 "push_operand" "=<,!<")
2338 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
2343 [(set_attr "type" "push,multi")
2344 (set_attr "mode" "DI")])
2346 ;; Convert impossible pushes of immediate to existing instructions.
2347 ;; First try to get scratch register and go trought it. In case this
2348 ;; fails, push sign extended lower part first and then overwrite
2349 ;; upper part by 32bit move.
2351 [(match_scratch:DI 2 "r")
2352 (set (match_operand:DI 0 "push_operand" "")
2353 (match_operand:DI 1 "immediate_operand" ""))]
2354 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2355 && !x86_64_immediate_operand (operands[1], DImode)"
2356 [(set (match_dup 2) (match_dup 1))
2357 (set (match_dup 0) (match_dup 2))]
2360 ;; We need to define this as both peepholer and splitter for case
2361 ;; peephole2 pass is not run.
2363 [(set (match_operand:DI 0 "push_operand" "")
2364 (match_operand:DI 1 "immediate_operand" ""))]
2365 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2366 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2367 [(set (match_dup 0) (match_dup 1))
2368 (set (match_dup 2) (match_dup 3))]
2369 "split_di (operands + 1, 1, operands + 2, operands + 3);
2370 operands[1] = gen_lowpart (DImode, operands[2]);
2371 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2376 [(set (match_operand:DI 0 "push_operand" "")
2377 (match_operand:DI 1 "immediate_operand" ""))]
2378 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2379 && !symbolic_operand (operands[1], DImode)
2380 && !x86_64_immediate_operand (operands[1], DImode)"
2381 [(set (match_dup 0) (match_dup 1))
2382 (set (match_dup 2) (match_dup 3))]
2383 "split_di (operands + 1, 1, operands + 2, operands + 3);
2384 operands[1] = gen_lowpart (DImode, operands[2]);
2385 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2389 (define_insn "*pushdi2_prologue_rex64"
2390 [(set (match_operand:DI 0 "push_operand" "=<")
2391 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
2392 (set (reg:DI 6) (reg:DI 6))]
2395 [(set_attr "type" "push")
2396 (set_attr "mode" "DI")])
2398 (define_insn "*popdi1_epilogue_rex64"
2399 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2400 (mem:DI (reg:DI 7)))
2402 (plus:DI (reg:DI 7) (const_int 8)))
2403 (set (reg:DI 6) (reg:DI 6))]
2406 [(set_attr "type" "pop")
2407 (set_attr "mode" "DI")])
2409 (define_insn "popdi1"
2410 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2411 (mem:DI (reg:DI 7)))
2413 (plus:DI (reg:DI 7) (const_int 8)))]
2416 [(set_attr "type" "pop")
2417 (set_attr "mode" "DI")])
2419 (define_insn "*movdi_xor_rex64"
2420 [(set (match_operand:DI 0 "register_operand" "=r")
2421 (match_operand:DI 1 "const0_operand" "i"))
2422 (clobber (reg:CC 17))]
2423 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)
2425 "xor{l}\\t{%k0, %k0|%k0, %k0}"
2426 [(set_attr "type" "alu1")
2427 (set_attr "mode" "SI")
2428 (set_attr "length_immediate" "0")])
2430 (define_insn "*movdi_or_rex64"
2431 [(set (match_operand:DI 0 "register_operand" "=r")
2432 (match_operand:DI 1 "const_int_operand" "i"))
2433 (clobber (reg:CC 17))]
2434 "reload_completed && GET_CODE (operands[1]) == CONST_INT
2436 && INTVAL (operands[1]) == -1
2437 && (TARGET_PENTIUM || optimize_size)"
2440 operands[1] = constm1_rtx;
2441 return \"or{q}\\t{%1, %0|%0, %1}\";
2443 [(set_attr "type" "alu1")
2444 (set_attr "mode" "DI")
2445 (set_attr "length_immediate" "1")])
2447 (define_insn "*movdi_2"
2448 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y")
2449 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m"))]
2451 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2455 movq\\t{%1, %0|%0, %1}
2456 movq\\t{%1, %0|%0, %1}"
2457 [(set_attr "type" "*,*,mmx,mmx")])
2460 [(set (match_operand:DI 0 "push_operand" "")
2461 (match_operand:DI 1 "general_operand" ""))]
2462 "!TARGET_64BIT && reload_completed && ! MMX_REG_P (operands[1])"
2464 "ix86_split_long_move (operands); DONE;")
2466 ;; %%% This multiword shite has got to go.
2468 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2469 (match_operand:DI 1 "general_operand" ""))]
2470 "!TARGET_64BIT && reload_completed && ! MMX_REG_P (operands[0])
2471 && ! MMX_REG_P (operands[1])"
2473 "ix86_split_long_move (operands); DONE;")
2475 (define_insn "*movdi_1_rex64"
2476 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,*m,*Y")
2477 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*m"))]
2478 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2482 switch (get_attr_type (insn))
2486 return \"movd\\t{%1, %0|%0, %1}\";
2490 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
2492 if (flag_pic && SYMBOLIC_CONST (operands[1]))
2494 if (get_attr_mode (insn) == MODE_SI)
2495 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
2496 else if (which_alternative == 2)
2497 return \"movabs{q}\\t{%1, %0|%0, %1}\";
2499 return \"mov{q}\\t{%1, %0|%0, %1}\";
2503 (cond [(eq_attr "alternative" "5,6")
2504 (const_string "mmx")
2505 (eq_attr "alternative" "7,8")
2506 (const_string "sse")
2507 (eq_attr "alternative" "4")
2508 (const_string "multi")
2509 (and (ne (symbol_ref "flag_pic") (const_int 0))
2510 (match_operand:DI 1 "symbolic_operand" ""))
2511 (const_string "lea")
2513 (const_string "imov")))
2514 (set_attr "modrm" "*,0,0,*,*,*,*,*,*")
2515 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*")
2516 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI")])
2518 ;; Stores and loads of ax to arbitary constant address.
2519 ;; We fake an second form of instruction to force reload to load address
2520 ;; into register when rax is not available
2521 (define_insn "*movabsdi_1_rex64"
2522 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2523 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2526 movabs{q}\\t{%1, %P0|%P0, %1}
2527 mov{q}\\t{%1, %a0|%a0, %1}
2528 movabs{q}\\t{%1, %a0|%a0, %1}"
2529 [(set_attr "type" "imov")
2530 (set_attr "modrm" "0,*,*")
2531 (set_attr "length_address" "8,0,0")
2532 (set_attr "length_immediate" "0,*,*")
2533 (set_attr "memory" "store")
2534 (set_attr "mode" "DI")])
2536 (define_insn "*movabsdi_2_rex64"
2537 [(set (match_operand:DI 0 "register_operand" "=a,r")
2538 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2541 movabs{q}\\t{%P1, %0|%0, %P1}
2542 mov{q}\\t{%a1, %0|%0, %a1}"
2543 [(set_attr "type" "imov")
2544 (set_attr "modrm" "0,*")
2545 (set_attr "length_address" "8,0")
2546 (set_attr "length_immediate" "0")
2547 (set_attr "memory" "load")
2548 (set_attr "mode" "DI")])
2550 ;; Convert impossible stores of immediate to existing instructions.
2551 ;; First try to get scratch register and go trought it. In case this
2552 ;; fails, move by 32bit parts.
2554 [(match_scratch:DI 2 "r")
2555 (set (match_operand:DI 0 "memory_operand" "")
2556 (match_operand:DI 1 "immediate_operand" ""))]
2557 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2558 && !x86_64_immediate_operand (operands[1], DImode)"
2559 [(set (match_dup 2) (match_dup 1))
2560 (set (match_dup 0) (match_dup 2))]
2563 ;; We need to define this as both peepholer and splitter for case
2564 ;; peephole2 pass is not run.
2566 [(set (match_operand:DI 0 "memory_operand" "")
2567 (match_operand:DI 1 "immediate_operand" ""))]
2568 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2569 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2570 [(set (match_dup 2) (match_dup 3))
2571 (set (match_dup 4) (match_dup 5))]
2572 "split_di (operands, 2, operands + 2, operands + 4);")
2575 [(set (match_operand:DI 0 "memory_operand" "")
2576 (match_operand:DI 1 "immediate_operand" ""))]
2577 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2578 && !symbolic_operand (operands[1], DImode)
2579 && !x86_64_immediate_operand (operands[1], DImode)"
2580 [(set (match_dup 2) (match_dup 3))
2581 (set (match_dup 4) (match_dup 5))]
2582 "split_di (operands, 2, operands + 2, operands + 4);")
2584 (define_insn "*swapdi_rex64"
2585 [(set (match_operand:DI 0 "register_operand" "+r")
2586 (match_operand:DI 1 "register_operand" "+r"))
2591 [(set_attr "type" "imov")
2592 (set_attr "pent_pair" "np")
2593 (set_attr "athlon_decode" "vector")
2594 (set_attr "mode" "DI")
2595 (set_attr "modrm" "0")
2596 (set_attr "ppro_uops" "few")])
2599 (define_expand "movsf"
2600 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2601 (match_operand:SF 1 "general_operand" ""))]
2603 "ix86_expand_move (SFmode, operands); DONE;")
2605 (define_insn "*pushsf"
2606 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2607 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2611 switch (which_alternative)
2614 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2615 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2616 operands[2] = stack_pointer_rtx;
2617 operands[3] = GEN_INT (4);
2618 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2619 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2621 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2624 return \"push{l}\\t%1\";
2632 [(set_attr "type" "multi,push,multi")
2633 (set_attr "mode" "SF,SI,SF")])
2635 (define_insn "*pushsf_rex64"
2636 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2637 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2641 switch (which_alternative)
2644 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2645 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2646 operands[2] = stack_pointer_rtx;
2647 operands[3] = GEN_INT (8);
2648 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2649 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2651 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2654 return \"push{q}\\t%q1\";
2663 [(set_attr "type" "multi,push,multi")
2664 (set_attr "mode" "SF,DI,SF")])
2667 [(set (match_operand:SF 0 "push_operand" "")
2668 (match_operand:SF 1 "memory_operand" ""))]
2670 && GET_CODE (operands[1]) == MEM
2671 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2672 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2675 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2678 ;; %%% Kill this when call knows how to work this out.
2680 [(set (match_operand:SF 0 "push_operand" "")
2681 (match_operand:SF 1 "register_operand" ""))]
2682 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2683 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2684 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2687 [(set (match_operand:SF 0 "push_operand" "")
2688 (match_operand:SF 1 "register_operand" ""))]
2689 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
2690 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2691 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2693 (define_insn "*movsf_1"
2694 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2695 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2696 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2697 && (reload_in_progress || reload_completed
2698 || GET_CODE (operands[1]) != CONST_DOUBLE
2699 || memory_operand (operands[0], SFmode))"
2702 switch (which_alternative)
2705 if (REG_P (operands[1])
2706 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2707 return \"fstp\\t%y0\";
2708 else if (STACK_TOP_P (operands[0]))
2709 return \"fld%z1\\t%y1\";
2711 return \"fst\\t%y0\";
2714 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2715 return \"fstp%z0\\t%y0\";
2717 return \"fst%z0\\t%y0\";
2720 switch (standard_80387_constant_p (operands[1]))
2731 return \"mov{l}\\t{%1, %0|%0, %1}\";
2733 return \"pxor\\t%0, %0\";
2735 if (TARGET_PARTIAL_REG_DEPENDENCY)
2736 return \"movaps\\t{%1, %0|%0, %1}\";
2738 return \"movss\\t{%1, %0|%0, %1}\";
2741 return \"movss\\t{%1, %0|%0, %1}\";
2747 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2748 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2750 (define_insn "*swapsf"
2751 [(set (match_operand:SF 0 "register_operand" "+f")
2752 (match_operand:SF 1 "register_operand" "+f"))
2755 "reload_completed || !TARGET_SSE2"
2758 if (STACK_TOP_P (operands[0]))
2759 return \"fxch\\t%1\";
2761 return \"fxch\\t%0\";
2763 [(set_attr "type" "fxch")
2764 (set_attr "mode" "SF")])
2766 (define_expand "movdf"
2767 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2768 (match_operand:DF 1 "general_operand" ""))]
2770 "ix86_expand_move (DFmode, operands); DONE;")
2772 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2773 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2774 ;; On the average, pushdf using integers can be still shorter. Allow this
2775 ;; pattern for optimize_size too.
2777 (define_insn "*pushdf_nointeger"
2778 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2779 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2780 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2783 switch (which_alternative)
2786 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2787 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2788 operands[2] = stack_pointer_rtx;
2789 operands[3] = GEN_INT (8);
2790 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2791 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2793 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2804 [(set_attr "type" "multi")
2805 (set_attr "mode" "DF,SI,SI,DF")])
2807 (define_insn "*pushdf_integer"
2808 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2809 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2810 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2813 switch (which_alternative)
2816 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2817 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2818 operands[2] = stack_pointer_rtx;
2819 operands[3] = GEN_INT (8);
2821 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2822 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2824 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2826 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2827 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2829 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2840 [(set_attr "type" "multi")
2841 (set_attr "mode" "DF,SI,DF")])
2843 ;; %%% Kill this when call knows how to work this out.
2845 [(set (match_operand:DF 0 "push_operand" "")
2846 (match_operand:DF 1 "register_operand" ""))]
2847 "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2848 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2849 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2853 [(set (match_operand:DF 0 "push_operand" "")
2854 (match_operand:DF 1 "register_operand" ""))]
2855 "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2856 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2857 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2861 [(set (match_operand:DF 0 "push_operand" "")
2862 (match_operand:DF 1 "general_operand" ""))]
2865 "ix86_split_long_move (operands); DONE;")
2867 ;; Moving is usually shorter when only FP registers are used. This separate
2868 ;; movdf pattern avoids the use of integer registers for FP operations
2869 ;; when optimizing for size.
2871 (define_insn "*movdf_nointeger"
2872 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2873 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2874 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2875 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2876 && (reload_in_progress || reload_completed
2877 || GET_CODE (operands[1]) != CONST_DOUBLE
2878 || memory_operand (operands[0], DFmode))"
2881 switch (which_alternative)
2884 if (REG_P (operands[1])
2885 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2886 return \"fstp\\t%y0\";
2887 else if (STACK_TOP_P (operands[0]))
2888 return \"fld%z1\\t%y1\";
2890 return \"fst\\t%y0\";
2893 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2894 return \"fstp%z0\\t%y0\";
2896 return \"fst%z0\\t%y0\";
2899 switch (standard_80387_constant_p (operands[1]))
2912 return \"pxor\\t%0, %0\";
2914 if (TARGET_PARTIAL_REG_DEPENDENCY)
2915 return \"movapd\\t{%1, %0|%0, %1}\";
2917 return \"movsd\\t{%1, %0|%0, %1}\";
2920 return \"movsd\\t{%1, %0|%0, %1}\";
2926 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2927 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2929 (define_insn "*movdf_integer"
2930 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2931 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2932 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2933 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2934 && (reload_in_progress || reload_completed
2935 || GET_CODE (operands[1]) != CONST_DOUBLE
2936 || memory_operand (operands[0], DFmode))"
2939 switch (which_alternative)
2942 if (REG_P (operands[1])
2943 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2944 return \"fstp\\t%y0\";
2945 else if (STACK_TOP_P (operands[0]))
2946 return \"fld%z1\\t%y1\";
2948 return \"fst\\t%y0\";
2951 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2952 return \"fstp%z0\\t%y0\";
2954 return \"fst%z0\\t%y0\";
2957 switch (standard_80387_constant_p (operands[1]))
2971 return \"pxor\\t%0, %0\";
2973 if (TARGET_PARTIAL_REG_DEPENDENCY)
2974 return \"movapd\\t{%1, %0|%0, %1}\";
2976 return \"movsd\\t{%1, %0|%0, %1}\";
2979 return \"movsd\\t{%1, %0|%0, %1}\";
2985 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2986 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2989 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2990 (match_operand:DF 1 "general_operand" ""))]
2992 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2993 && ! (ANY_FP_REG_P (operands[0]) ||
2994 (GET_CODE (operands[0]) == SUBREG
2995 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2996 && ! (ANY_FP_REG_P (operands[1]) ||
2997 (GET_CODE (operands[1]) == SUBREG
2998 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3000 "ix86_split_long_move (operands); DONE;")
3002 (define_insn "*swapdf"
3003 [(set (match_operand:DF 0 "register_operand" "+f")
3004 (match_operand:DF 1 "register_operand" "+f"))
3007 "reload_completed || !TARGET_SSE2"
3010 if (STACK_TOP_P (operands[0]))
3011 return \"fxch\\t%1\";
3013 return \"fxch\\t%0\";
3015 [(set_attr "type" "fxch")
3016 (set_attr "mode" "DF")])
3018 (define_expand "movxf"
3019 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3020 (match_operand:XF 1 "general_operand" ""))]
3022 "ix86_expand_move (XFmode, operands); DONE;")
3024 (define_expand "movtf"
3025 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3026 (match_operand:TF 1 "general_operand" ""))]
3028 "ix86_expand_move (TFmode, operands); DONE;")
3030 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
3031 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
3032 ;; Pushing using integer instructions is longer except for constants
3033 ;; and direct memory references.
3034 ;; (assuming that any given constant is pushed only once, but this ought to be
3035 ;; handled elsewhere).
3037 (define_insn "*pushxf_nointeger"
3038 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
3039 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
3040 "optimize_size && !TARGET_64BIT"
3043 switch (which_alternative)
3046 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3047 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3048 operands[2] = stack_pointer_rtx;
3049 operands[3] = GEN_INT (12);
3050 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3051 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3053 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3063 [(set_attr "type" "multi")
3064 (set_attr "mode" "XF,SI,SI")])
3066 (define_insn "*pushtf_nointeger"
3067 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
3068 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
3072 switch (which_alternative)
3075 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3076 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3077 operands[2] = stack_pointer_rtx;
3078 operands[3] = GEN_INT (16);
3079 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3080 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3082 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3092 [(set_attr "type" "multi")
3093 (set_attr "mode" "XF,SI,SI")])
3095 (define_insn "*pushxf_integer"
3096 [(set (match_operand:XF 0 "push_operand" "=<,<")
3097 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
3098 "!optimize_size && !TARGET_64BIT"
3101 switch (which_alternative)
3104 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3105 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3106 operands[2] = stack_pointer_rtx;
3107 operands[3] = GEN_INT (12);
3108 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3109 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3111 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3120 [(set_attr "type" "multi")
3121 (set_attr "mode" "XF,SI")])
3123 (define_insn "*pushtf_integer"
3124 [(set (match_operand:TF 0 "push_operand" "=<,<")
3125 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
3129 switch (which_alternative)
3132 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
3133 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
3134 operands[2] = stack_pointer_rtx;
3135 operands[3] = GEN_INT (16);
3137 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3138 return \"sub{q}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3140 return \"sub{q}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3142 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3143 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
3145 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
3154 [(set_attr "type" "multi")
3155 (set_attr "mode" "XF,SI")])
3158 [(set (match_operand 0 "push_operand" "")
3159 (match_operand 1 "general_operand" ""))]
3161 && (GET_MODE (operands[0]) == XFmode
3162 || GET_MODE (operands[0]) == TFmode
3163 || GET_MODE (operands[0]) == DFmode)
3164 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
3166 "ix86_split_long_move (operands); DONE;")
3169 [(set (match_operand:XF 0 "push_operand" "")
3170 (match_operand:XF 1 "register_operand" ""))]
3171 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3172 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3173 (set (mem:XF (reg:SI 7)) (match_dup 1))])
3176 [(set (match_operand:TF 0 "push_operand" "")
3177 (match_operand:TF 1 "register_operand" ""))]
3178 "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3179 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3180 (set (mem:TF (reg:SI 7)) (match_dup 1))])
3183 [(set (match_operand:TF 0 "push_operand" "")
3184 (match_operand:TF 1 "register_operand" ""))]
3185 "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))"
3186 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3187 (set (mem:TF (reg:DI 7)) (match_dup 1))])
3189 ;; Do not use integer registers when optimizing for size
3190 (define_insn "*movxf_nointeger"
3191 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3192 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3193 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3196 && (reload_in_progress || reload_completed
3197 || GET_CODE (operands[1]) != CONST_DOUBLE
3198 || memory_operand (operands[0], XFmode))"
3201 switch (which_alternative)
3204 if (REG_P (operands[1])
3205 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3206 return \"fstp\\t%y0\";
3207 else if (STACK_TOP_P (operands[0]))
3208 return \"fld%z1\\t%y1\";
3210 return \"fst\\t%y0\";
3213 /* There is no non-popping store to memory for XFmode. So if
3214 we need one, follow the store with a load. */
3215 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3216 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3218 return \"fstp%z0\\t%y0\";
3221 switch (standard_80387_constant_p (operands[1]))
3235 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3236 (set_attr "mode" "XF,XF,XF,SI,SI")])
3238 (define_insn "*movtf_nointeger"
3239 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3240 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3241 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3243 && (reload_in_progress || reload_completed
3244 || GET_CODE (operands[1]) != CONST_DOUBLE
3245 || memory_operand (operands[0], TFmode))"
3248 switch (which_alternative)
3251 if (REG_P (operands[1])
3252 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3253 return \"fstp\\t%y0\";
3254 else if (STACK_TOP_P (operands[0]))
3255 return \"fld%z1\\t%y1\";
3257 return \"fst\\t%y0\";
3260 /* There is no non-popping store to memory for XFmode. So if
3261 we need one, follow the store with a load. */
3262 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3263 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3265 return \"fstp%z0\\t%y0\";
3268 switch (standard_80387_constant_p (operands[1]))
3282 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3283 (set_attr "mode" "XF,XF,XF,SI,SI")])
3285 (define_insn "*movxf_integer"
3286 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3287 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3288 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3291 && (reload_in_progress || reload_completed
3292 || GET_CODE (operands[1]) != CONST_DOUBLE
3293 || memory_operand (operands[0], XFmode))"
3296 switch (which_alternative)
3299 if (REG_P (operands[1])
3300 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3301 return \"fstp\\t%y0\";
3302 else if (STACK_TOP_P (operands[0]))
3303 return \"fld%z1\\t%y1\";
3305 return \"fst\\t%y0\";
3308 /* There is no non-popping store to memory for XFmode. So if
3309 we need one, follow the store with a load. */
3310 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3311 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3313 return \"fstp%z0\\t%y0\";
3316 switch (standard_80387_constant_p (operands[1]))
3330 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3331 (set_attr "mode" "XF,XF,XF,SI,SI")])
3333 (define_insn "*movtf_integer"
3334 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
3335 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
3336 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3338 && (reload_in_progress || reload_completed
3339 || GET_CODE (operands[1]) != CONST_DOUBLE
3340 || memory_operand (operands[0], TFmode))"
3343 switch (which_alternative)
3346 if (REG_P (operands[1])
3347 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3348 return \"fstp\\t%y0\";
3349 else if (STACK_TOP_P (operands[0]))
3350 return \"fld%z1\\t%y1\";
3352 return \"fst\\t%y0\";
3355 /* There is no non-popping store to memory for XFmode. So if
3356 we need one, follow the store with a load. */
3357 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3358 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
3360 return \"fstp%z0\\t%y0\";
3363 switch (standard_80387_constant_p (operands[1]))
3377 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3378 (set_attr "mode" "XF,XF,XF,SI,SI")])
3381 [(set (match_operand 0 "nonimmediate_operand" "")
3382 (match_operand 1 "general_operand" ""))]
3384 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3385 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3386 && ! (ANY_FP_REG_P (operands[0]) ||
3387 (GET_CODE (operands[0]) == SUBREG
3388 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3389 && ! (ANY_FP_REG_P (operands[1]) ||
3390 (GET_CODE (operands[1]) == SUBREG
3391 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3393 "ix86_split_long_move (operands); DONE;")
3396 [(set (match_operand 0 "register_operand" "")
3397 (match_operand 1 "memory_operand" ""))]
3399 && GET_CODE (operands[1]) == MEM
3400 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3401 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3402 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3403 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3404 && (!(SSE_REG_P (operands[0]) ||
3405 (GET_CODE (operands[0]) == SUBREG
3406 && SSE_REG_P (SUBREG_REG (operands[0]))))
3407 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3408 && (!(FP_REG_P (operands[0]) ||
3409 (GET_CODE (operands[0]) == SUBREG
3410 && FP_REG_P (SUBREG_REG (operands[0]))))
3411 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3414 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3416 (define_insn "swapxf"
3417 [(set (match_operand:XF 0 "register_operand" "+f")
3418 (match_operand:XF 1 "register_operand" "+f"))
3424 if (STACK_TOP_P (operands[0]))
3425 return \"fxch\\t%1\";
3427 return \"fxch\\t%0\";
3429 [(set_attr "type" "fxch")
3430 (set_attr "mode" "XF")])
3432 (define_insn "swaptf"
3433 [(set (match_operand:TF 0 "register_operand" "+f")
3434 (match_operand:TF 1 "register_operand" "+f"))
3440 if (STACK_TOP_P (operands[0]))
3441 return \"fxch\\t%1\";
3443 return \"fxch\\t%0\";
3445 [(set_attr "type" "fxch")
3446 (set_attr "mode" "XF")])
3448 ;; Zero extension instructions
3450 (define_expand "zero_extendhisi2"
3451 [(set (match_operand:SI 0 "register_operand" "")
3452 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3456 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3458 operands[1] = force_reg (HImode, operands[1]);
3459 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3464 (define_insn "zero_extendhisi2_and"
3465 [(set (match_operand:SI 0 "register_operand" "=r")
3466 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3467 (clobber (reg:CC 17))]
3468 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3470 [(set_attr "type" "alu1")
3471 (set_attr "mode" "SI")])
3474 [(set (match_operand:SI 0 "register_operand" "")
3475 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3476 (clobber (reg:CC 17))]
3477 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3478 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3479 (clobber (reg:CC 17))])]
3482 (define_insn "*zero_extendhisi2_movzwl"
3483 [(set (match_operand:SI 0 "register_operand" "=r")
3484 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3485 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3486 "movz{wl|x}\\t{%1, %0|%0, %1}"
3487 [(set_attr "type" "imovx")
3488 (set_attr "mode" "SI")])
3490 (define_expand "zero_extendqihi2"
3492 [(set (match_operand:HI 0 "register_operand" "")
3493 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3494 (clobber (reg:CC 17))])]
3498 (define_insn "*zero_extendqihi2_and"
3499 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3500 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3501 (clobber (reg:CC 17))]
3502 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3504 [(set_attr "type" "alu1")
3505 (set_attr "mode" "HI")])
3507 (define_insn "*zero_extendqihi2_movzbw_and"
3508 [(set (match_operand:HI 0 "register_operand" "=r,r")
3509 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3510 (clobber (reg:CC 17))]
3511 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3513 [(set_attr "type" "imovx,alu1")
3514 (set_attr "mode" "HI")])
3516 (define_insn "*zero_extendqihi2_movzbw"
3517 [(set (match_operand:HI 0 "register_operand" "=r")
3518 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3519 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3520 "movz{bw|x}\\t{%1, %0|%0, %1}"
3521 [(set_attr "type" "imovx")
3522 (set_attr "mode" "HI")])
3524 ;; For the movzbw case strip only the clobber
3526 [(set (match_operand:HI 0 "register_operand" "")
3527 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3528 (clobber (reg:CC 17))]
3530 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3531 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3532 [(set (match_operand:HI 0 "register_operand" "")
3533 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3535 ;; When source and destination does not overlap, clear destination
3536 ;; first and then do the movb
3538 [(set (match_operand:HI 0 "register_operand" "")
3539 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3540 (clobber (reg:CC 17))]
3542 && ANY_QI_REG_P (operands[0])
3543 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3544 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3545 [(set (match_dup 0) (const_int 0))
3546 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3547 "operands[2] = gen_lowpart (QImode, operands[0]);")
3549 ;; Rest is handled by single and.
3551 [(set (match_operand:HI 0 "register_operand" "")
3552 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3553 (clobber (reg:CC 17))]
3555 && true_regnum (operands[0]) == true_regnum (operands[1])"
3556 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3557 (clobber (reg:CC 17))])]
3560 (define_expand "zero_extendqisi2"
3562 [(set (match_operand:SI 0 "register_operand" "")
3563 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3564 (clobber (reg:CC 17))])]
3568 (define_insn "*zero_extendqisi2_and"
3569 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3570 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3571 (clobber (reg:CC 17))]
3572 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3574 [(set_attr "type" "alu1")
3575 (set_attr "mode" "SI")])
3577 (define_insn "*zero_extendqisi2_movzbw_and"
3578 [(set (match_operand:SI 0 "register_operand" "=r,r")
3579 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3580 (clobber (reg:CC 17))]
3581 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3583 [(set_attr "type" "imovx,alu1")
3584 (set_attr "mode" "SI")])
3586 (define_insn "*zero_extendqisi2_movzbw"
3587 [(set (match_operand:SI 0 "register_operand" "=r")
3588 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3589 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3590 "movz{bl|x}\\t{%1, %0|%0, %1}"
3591 [(set_attr "type" "imovx")
3592 (set_attr "mode" "SI")])
3594 ;; For the movzbl case strip only the clobber
3596 [(set (match_operand:SI 0 "register_operand" "")
3597 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3598 (clobber (reg:CC 17))]
3600 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3601 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3603 (zero_extend:SI (match_dup 1)))])
3605 ;; When source and destination does not overlap, clear destination
3606 ;; first and then do the movb
3608 [(set (match_operand:SI 0 "register_operand" "")
3609 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3610 (clobber (reg:CC 17))]
3612 && ANY_QI_REG_P (operands[0])
3613 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3614 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3615 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3616 [(set (match_dup 0) (const_int 0))
3617 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3618 "operands[2] = gen_lowpart (QImode, operands[0]);")
3620 ;; Rest is handled by single and.
3622 [(set (match_operand:SI 0 "register_operand" "")
3623 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3624 (clobber (reg:CC 17))]
3626 && true_regnum (operands[0]) == true_regnum (operands[1])"
3627 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3628 (clobber (reg:CC 17))])]
3631 ;; %%% Kill me once multi-word ops are sane.
3632 (define_expand "zero_extendsidi2"
3633 [(set (match_operand:DI 0 "register_operand" "=r")
3634 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3638 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3643 (define_insn "zero_extendsidi2_32"
3644 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3645 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3646 (clobber (reg:CC 17))]
3649 [(set_attr "mode" "SI")])
3651 (define_insn "zero_extendsidi2_rex64"
3652 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3653 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3656 mov\\t{%k1, %k0|%k0, %k1}
3658 [(set_attr "type" "imovx,imov")
3659 (set_attr "mode" "SI,DI")])
3662 [(set (match_operand:DI 0 "memory_operand" "")
3663 (zero_extend:DI (match_dup 0)))]
3665 [(set (match_dup 4) (const_int 0))]
3666 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3669 [(set (match_operand:DI 0 "register_operand" "")
3670 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3671 (clobber (reg:CC 17))]
3672 "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])
3674 [(set (match_dup 4) (const_int 0))]
3675 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3678 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3679 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3680 (clobber (reg:CC 17))]
3681 "reload_completed && !TARGET_64BIT"
3682 [(set (match_dup 3) (match_dup 1))
3683 (set (match_dup 4) (const_int 0))]
3684 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3686 (define_insn "zero_extendhidi2"
3687 [(set (match_operand:DI 0 "register_operand" "=r,r")
3688 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3691 movz{wl|x}\\t{%1, %k0|%k0, %1}
3692 movz{wq|x}\\t{%1, %0|%0, %1}"
3693 [(set_attr "type" "imovx")
3694 (set_attr "mode" "SI,DI")])
3696 (define_insn "zero_extendqidi2"
3697 [(set (match_operand:DI 0 "register_operand" "=r,r")
3698 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3701 movz{bl|x}\\t{%1, %k0|%k0, %1}
3702 movz{bq|x}\\t{%1, %0|%0, %1}"
3703 [(set_attr "type" "imovx")
3704 (set_attr "mode" "SI,DI")])
3706 ;; Sign extension instructions
3708 (define_expand "extendsidi2"
3709 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3710 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3711 (clobber (reg:CC 17))
3712 (clobber (match_scratch:SI 2 ""))])]
3718 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3723 (define_insn "*extendsidi2_1"
3724 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3725 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3726 (clobber (reg:CC 17))
3727 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3731 (define_insn "extendsidi2_rex64"
3732 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3733 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3737 movs{lq|x}\\t{%1,%0|%0, %1}"
3738 [(set_attr "type" "imovx")
3739 (set_attr "mode" "DI")
3740 (set_attr "prefix_0f" "0")
3741 (set_attr "modrm" "0,1")])
3743 (define_insn "extendhidi2"
3744 [(set (match_operand:DI 0 "register_operand" "=r")
3745 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3747 "movs{wq|x}\\t{%1,%0|%0, %1}"
3748 [(set_attr "type" "imovx")
3749 (set_attr "mode" "DI")])
3751 (define_insn "extendqidi2"
3752 [(set (match_operand:DI 0 "register_operand" "=r")
3753 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3755 "movs{bq|x}\\t{%1,%0|%0, %1}"
3756 [(set_attr "type" "imovx")
3757 (set_attr "mode" "DI")])
3759 ;; Extend to memory case when source register does die.
3761 [(set (match_operand:DI 0 "memory_operand" "")
3762 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3763 (clobber (reg:CC 17))
3764 (clobber (match_operand:SI 2 "register_operand" ""))]
3766 && dead_or_set_p (insn, operands[1])
3767 && !reg_mentioned_p (operands[1], operands[0]))"
3768 [(set (match_dup 3) (match_dup 1))
3769 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3770 (clobber (reg:CC 17))])
3771 (set (match_dup 4) (match_dup 1))]
3772 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3774 ;; Extend to memory case when source register does not die.
3776 [(set (match_operand:DI 0 "memory_operand" "")
3777 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3778 (clobber (reg:CC 17))
3779 (clobber (match_operand:SI 2 "register_operand" ""))]
3784 split_di (&operands[0], 1, &operands[3], &operands[4]);
3786 emit_move_insn (operands[3], operands[1]);
3788 /* Generate a cltd if possible and doing so it profitable. */
3789 if (true_regnum (operands[1]) == 0
3790 && true_regnum (operands[2]) == 1
3791 && (optimize_size || TARGET_USE_CLTD))
3793 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3797 emit_move_insn (operands[2], operands[1]);
3798 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3800 emit_move_insn (operands[4], operands[2]);
3804 ;; Extend to register case. Optimize case where source and destination
3805 ;; registers match and cases where we can use cltd.
3807 [(set (match_operand:DI 0 "register_operand" "")
3808 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3809 (clobber (reg:CC 17))
3810 (clobber (match_scratch:SI 2 ""))]
3815 split_di (&operands[0], 1, &operands[3], &operands[4]);
3817 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3818 emit_move_insn (operands[3], operands[1]);
3820 /* Generate a cltd if possible and doing so it profitable. */
3821 if (true_regnum (operands[3]) == 0
3822 && (optimize_size || TARGET_USE_CLTD))
3824 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3828 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3829 emit_move_insn (operands[4], operands[1]);
3831 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3835 (define_insn "extendhisi2"
3836 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3837 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3841 switch (get_attr_prefix_0f (insn))
3844 return \"{cwtl|cwde}\";
3846 return \"movs{wl|x}\\t{%1,%0|%0, %1}\";
3849 [(set_attr "type" "imovx")
3850 (set_attr "mode" "SI")
3851 (set (attr "prefix_0f")
3852 ;; movsx is short decodable while cwtl is vector decoded.
3853 (if_then_else (and (eq_attr "cpu" "!k6")
3854 (eq_attr "alternative" "0"))
3856 (const_string "1")))
3858 (if_then_else (eq_attr "prefix_0f" "0")
3860 (const_string "1")))])
3862 (define_insn "*extendhisi2_zext"
3863 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3865 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3869 switch (get_attr_prefix_0f (insn))
3872 return \"{cwtl|cwde}\";
3874 return \"movs{wl|x}\\t{%1,%k0|%k0, %1}\";
3877 [(set_attr "type" "imovx")
3878 (set_attr "mode" "SI")
3879 (set (attr "prefix_0f")
3880 ;; movsx is short decodable while cwtl is vector decoded.
3881 (if_then_else (and (eq_attr "cpu" "!k6")
3882 (eq_attr "alternative" "0"))
3884 (const_string "1")))
3886 (if_then_else (eq_attr "prefix_0f" "0")
3888 (const_string "1")))])
3890 (define_insn "extendqihi2"
3891 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3892 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3896 switch (get_attr_prefix_0f (insn))
3899 return \"{cbtw|cbw}\";
3901 return \"movs{bw|x}\\t{%1,%0|%0, %1}\";
3904 [(set_attr "type" "imovx")
3905 (set_attr "mode" "HI")
3906 (set (attr "prefix_0f")
3907 ;; movsx is short decodable while cwtl is vector decoded.
3908 (if_then_else (and (eq_attr "cpu" "!k6")
3909 (eq_attr "alternative" "0"))
3911 (const_string "1")))
3913 (if_then_else (eq_attr "prefix_0f" "0")
3915 (const_string "1")))])
3917 (define_insn "extendqisi2"
3918 [(set (match_operand:SI 0 "register_operand" "=r")
3919 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3921 "movs{bl|x}\\t{%1,%0|%0, %1}"
3922 [(set_attr "type" "imovx")
3923 (set_attr "mode" "SI")])
3925 (define_insn "*extendqisi2_zext"
3926 [(set (match_operand:DI 0 "register_operand" "=r")
3928 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3930 "movs{bl|x}\\t{%1,%k0|%k0, %1}"
3931 [(set_attr "type" "imovx")
3932 (set_attr "mode" "SI")])
3934 ;; Conversions between float and double.
3936 ;; These are all no-ops in the model used for the 80387. So just
3939 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3940 (define_insn "*dummy_extendsfdf2"
3941 [(set (match_operand:DF 0 "push_operand" "=<")
3942 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3947 [(set (match_operand:DF 0 "push_operand" "")
3948 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3949 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3950 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3951 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3954 [(set (match_operand:DF 0 "push_operand" "")
3955 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3956 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3957 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3958 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3960 (define_insn "*dummy_extendsfxf2"
3961 [(set (match_operand:XF 0 "push_operand" "=<")
3962 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3967 [(set (match_operand:XF 0 "push_operand" "")
3968 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
3969 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3970 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3971 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3973 (define_insn "*dummy_extendsftf2"
3974 [(set (match_operand:TF 0 "push_operand" "=<")
3975 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3980 [(set (match_operand:TF 0 "push_operand" "")
3981 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3982 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
3983 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3984 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3987 [(set (match_operand:TF 0 "push_operand" "")
3988 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3989 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
3990 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3991 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3993 (define_insn "*dummy_extenddfxf2"
3994 [(set (match_operand:XF 0 "push_operand" "=<")
3995 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4000 [(set (match_operand:XF 0 "push_operand" "")
4001 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
4002 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4003 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
4004 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4006 (define_insn "*dummy_extenddftf2"
4007 [(set (match_operand:TF 0 "push_operand" "=<")
4008 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
4013 [(set (match_operand:TF 0 "push_operand" "")
4014 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4015 "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
4016 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
4017 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
4020 [(set (match_operand:TF 0 "push_operand" "")
4021 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
4022 "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
4023 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
4024 (set (mem:TF (reg:DI 7)) (float_extend:XF (match_dup 1)))])
4026 (define_expand "extendsfdf2"
4027 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4028 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
4029 "TARGET_80387 || TARGET_SSE2"
4032 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4033 operands[1] = force_reg (SFmode, operands[1]);
4036 (define_insn "*extendsfdf2_1"
4037 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
4038 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
4039 "(TARGET_80387 || TARGET_SSE2)
4040 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4043 switch (which_alternative)
4046 if (REG_P (operands[1])
4047 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4048 return \"fstp\\t%y0\";
4049 else if (STACK_TOP_P (operands[0]))
4050 return \"fld%z1\\t%y1\";
4052 return \"fst\\t%y0\";
4055 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4056 return \"fstp%z0\\t%y0\";
4059 return \"fst%z0\\t%y0\";
4061 return \"cvtss2sd\\t{%1, %0|%0, %1}\";
4067 [(set_attr "type" "fmov,fmov,sse")
4068 (set_attr "mode" "SF,XF,DF")])
4070 (define_insn "*extendsfdf2_1_sse_only"
4071 [(set (match_operand:DF 0 "register_operand" "=Y")
4072 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
4073 "!TARGET_80387 && TARGET_SSE2
4074 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4075 "cvtss2sd\\t{%1, %0|%0, %1}"
4076 [(set_attr "type" "sse")
4077 (set_attr "mode" "DF")])
4079 (define_expand "extendsfxf2"
4080 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4081 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
4082 "TARGET_80387 && !TARGET_64BIT"
4085 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4086 operands[1] = force_reg (SFmode, operands[1]);
4089 (define_insn "*extendsfxf2_1"
4090 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4091 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4092 "TARGET_80387 && !TARGET_64BIT
4093 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4096 switch (which_alternative)
4099 if (REG_P (operands[1])
4100 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4101 return \"fstp\\t%y0\";
4102 else if (STACK_TOP_P (operands[0]))
4103 return \"fld%z1\\t%y1\";
4105 return \"fst\\t%y0\";
4108 /* There is no non-popping store to memory for XFmode. So if
4109 we need one, follow the store with a load. */
4110 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4111 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4113 return \"fstp%z0\\t%y0\";
4119 [(set_attr "type" "fmov")
4120 (set_attr "mode" "SF,XF")])
4122 (define_expand "extendsftf2"
4123 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4124 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
4128 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4129 operands[1] = force_reg (SFmode, operands[1]);
4132 (define_insn "*extendsftf2_1"
4133 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4134 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4136 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4139 switch (which_alternative)
4142 if (REG_P (operands[1])
4143 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4144 return \"fstp\\t%y0\";
4145 else if (STACK_TOP_P (operands[0]))
4146 return \"fld%z1\\t%y1\";
4148 return \"fst\\t%y0\";
4151 /* There is no non-popping store to memory for XFmode. So if
4152 we need one, follow the store with a load. */
4153 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4154 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4156 return \"fstp%z0\\t%y0\";
4162 [(set_attr "type" "fmov")
4163 (set_attr "mode" "SF,XF")])
4165 (define_expand "extenddfxf2"
4166 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4167 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
4168 "TARGET_80387 && !TARGET_64BIT"
4171 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4172 operands[1] = force_reg (DFmode, operands[1]);
4175 (define_insn "*extenddfxf2_1"
4176 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4177 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4178 "TARGET_80387 && !TARGET_64BIT
4179 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4182 switch (which_alternative)
4185 if (REG_P (operands[1])
4186 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4187 return \"fstp\\t%y0\";
4188 else if (STACK_TOP_P (operands[0]))
4189 return \"fld%z1\\t%y1\";
4191 return \"fst\\t%y0\";
4194 /* There is no non-popping store to memory for XFmode. So if
4195 we need one, follow the store with a load. */
4196 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4197 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4199 return \"fstp%z0\\t%y0\";
4205 [(set_attr "type" "fmov")
4206 (set_attr "mode" "DF,XF")])
4208 (define_expand "extenddftf2"
4209 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4210 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
4214 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4215 operands[1] = force_reg (DFmode, operands[1]);
4218 (define_insn "*extenddftf2_1"
4219 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
4220 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
4222 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4225 switch (which_alternative)
4228 if (REG_P (operands[1])
4229 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4230 return \"fstp\\t%y0\";
4231 else if (STACK_TOP_P (operands[0]))
4232 return \"fld%z1\\t%y1\";
4234 return \"fst\\t%y0\";
4237 /* There is no non-popping store to memory for XFmode. So if
4238 we need one, follow the store with a load. */
4239 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4240 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
4242 return \"fstp%z0\\t%y0\";
4248 [(set_attr "type" "fmov")
4249 (set_attr "mode" "DF,XF")])
4251 ;; %%% This seems bad bad news.
4252 ;; This cannot output into an f-reg because there is no way to be sure
4253 ;; of truncating in that case. Otherwise this is just like a simple move
4254 ;; insn. So we pretend we can output to a reg in order to get better
4255 ;; register preferencing, but we really use a stack slot.
4257 (define_expand "truncdfsf2"
4258 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4260 (match_operand:DF 1 "register_operand" "")))
4261 (clobber (match_dup 2))])]
4262 "TARGET_80387 || TARGET_SSE2"
4265 operands[2] = assign_386_stack_local (SFmode, 0);
4268 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4273 (define_insn "*truncdfsf2_1"
4274 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f")
4276 (match_operand:DF 1 "register_operand" "f,0")))
4277 (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
4278 "TARGET_80387 && !TARGET_SSE2"
4281 switch (which_alternative)
4284 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4285 return \"fstp%z0\\t%y0\";
4287 return \"fst%z0\\t%y0\";
4289 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4293 [(set_attr "type" "fmov,multi")
4294 (set_attr "mode" "SF,SF")])
4296 (define_insn "*truncdfsf2_1_sse"
4297 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f,Y")
4299 (match_operand:DF 1 "nonimmediate_operand" "f,0,mY")))
4300 (clobber (match_operand:SF 2 "memory_operand" "=X,m,X"))]
4301 "TARGET_80387 && TARGET_SSE2"
4304 switch (which_alternative)
4307 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4308 return \"fstp%z0\\t%y0\";
4310 return \"fst%z0\\t%y0\";
4312 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4315 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4319 [(set_attr "type" "fmov,multi,sse")
4320 (set_attr "mode" "SF,SF,DF")])
4322 (define_insn "*truncdfsf2_2"
4323 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
4325 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4326 "TARGET_80387 && TARGET_SSE2
4327 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4330 switch (which_alternative)
4333 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
4335 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4336 return \"fstp%z0\\t%y0\";
4338 return \"fst%z0\\t%y0\";
4341 [(set_attr "type" "sse,fmov")
4342 (set_attr "mode" "DF,SF")])
4344 (define_insn "truncdfsf2_3"
4345 [(set (match_operand:SF 0 "memory_operand" "=m")
4347 (match_operand:DF 1 "register_operand" "f")))]
4351 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4352 return \"fstp%z0\\t%y0\";
4354 return \"fst%z0\\t%y0\";
4356 [(set_attr "type" "fmov")
4357 (set_attr "mode" "SF")])
4359 (define_insn "truncdfsf2_sse_only"
4360 [(set (match_operand:SF 0 "register_operand" "=Y")
4362 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4363 "!TARGET_80387 && TARGET_SSE2"
4364 "cvtsd2ss\\t{%1, %0|%0, %1}"
4365 [(set_attr "type" "sse")
4366 (set_attr "mode" "DF")])
4369 [(set (match_operand:SF 0 "memory_operand" "")
4371 (match_operand:DF 1 "register_operand" "")))
4372 (clobber (match_operand:SF 2 "memory_operand" ""))]
4374 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4378 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4380 (match_operand:DF 1 "nonimmediate_operand" "")))
4381 (clobber (match_operand 2 "" ""))]
4382 "TARGET_80387 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
4383 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4387 [(set (match_operand:SF 0 "register_operand" "")
4389 (match_operand:DF 1 "register_operand" "")))
4390 (clobber (match_operand:SF 2 "memory_operand" ""))]
4391 "TARGET_80387 && reload_completed
4392 && FP_REG_P (operands[0])"
4393 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4394 (set (match_dup 0) (match_dup 2))]
4397 (define_expand "truncxfsf2"
4398 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4400 (match_operand:XF 1 "register_operand" "")))
4401 (clobber (match_dup 2))])]
4402 "TARGET_80387 && !TARGET_64BIT"
4403 "operands[2] = assign_386_stack_local (SFmode, 0);")
4405 (define_insn "*truncxfsf2_1"
4406 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f")
4408 (match_operand:XF 1 "register_operand" "f,0")))
4409 (clobber (match_operand:SF 2 "memory_operand" "=m,m"))]
4410 "TARGET_80387 && !TARGET_64BIT"
4413 switch (which_alternative)
4416 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4417 return \"fstp%z0\\t%y0\";
4419 return \"fst%z0\\t%y0\";
4421 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4425 [(set_attr "type" "fmov,multi")
4426 (set_attr "mode" "SF")])
4428 (define_insn "*truncxfsf2_2"
4429 [(set (match_operand:SF 0 "memory_operand" "=m")
4431 (match_operand:XF 1 "register_operand" "f")))]
4432 "TARGET_80387 && !TARGET_64BIT"
4435 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4436 return \"fstp%z0\\t%y0\";
4438 return \"fst%z0\\t%y0\";
4440 [(set_attr "type" "fmov")
4441 (set_attr "mode" "SF")])
4444 [(set (match_operand:SF 0 "memory_operand" "")
4446 (match_operand:XF 1 "register_operand" "")))
4447 (clobber (match_operand:SF 2 "memory_operand" ""))]
4449 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4453 [(set (match_operand:SF 0 "register_operand" "")
4455 (match_operand:XF 1 "register_operand" "")))
4456 (clobber (match_operand:SF 2 "memory_operand" ""))]
4457 "TARGET_80387 && reload_completed"
4458 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4459 (set (match_dup 0) (match_dup 2))]
4462 (define_expand "trunctfsf2"
4463 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4465 (match_operand:TF 1 "register_operand" "")))
4466 (clobber (match_dup 2))])]
4468 "operands[2] = assign_386_stack_local (SFmode, 0);")
4470 (define_insn "*trunctfsf2_1"
4471 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f")
4473 (match_operand:TF 1 "register_operand" "f,0")))
4474 (clobber (match_operand:SF 2 "memory_operand" "=m,m"))]
4478 switch (which_alternative)
4481 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4482 return \"fstp%z0\\t%y0\";
4484 return \"fst%z0\\t%y0\";
4486 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4490 [(set_attr "type" "fmov,multi")
4491 (set_attr "mode" "SF")])
4493 (define_insn "*trunctfsf2_2"
4494 [(set (match_operand:SF 0 "memory_operand" "=m")
4496 (match_operand:TF 1 "register_operand" "f")))]
4500 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4501 return \"fstp%z0\\t%y0\";
4503 return \"fst%z0\\t%y0\";
4505 [(set_attr "type" "fmov")
4506 (set_attr "mode" "SF")])
4509 [(set (match_operand:SF 0 "memory_operand" "")
4511 (match_operand:TF 1 "register_operand" "")))
4512 (clobber (match_operand:SF 2 "memory_operand" ""))]
4514 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4518 [(set (match_operand:SF 0 "register_operand" "")
4520 (match_operand:TF 1 "register_operand" "")))
4521 (clobber (match_operand:SF 2 "memory_operand" ""))]
4522 "TARGET_80387 && reload_completed"
4523 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4524 (set (match_dup 0) (match_dup 2))]
4528 (define_expand "truncxfdf2"
4529 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4531 (match_operand:XF 1 "register_operand" "")))
4532 (clobber (match_dup 2))])]
4533 "TARGET_80387 && !TARGET_64BIT"
4534 "operands[2] = assign_386_stack_local (DFmode, 0);")
4536 (define_insn "*truncxfdf2_1"
4537 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,f")
4539 (match_operand:XF 1 "register_operand" "f,0")))
4540 (clobber (match_operand:DF 2 "memory_operand" "=m,m"))]
4541 "TARGET_80387 && !TARGET_64BIT"
4544 switch (which_alternative)
4547 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4548 return \"fstp%z0\\t%y0\";
4550 return \"fst%z0\\t%y0\";
4552 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4556 [(set_attr "type" "fmov,multi")
4557 (set_attr "mode" "DF")])
4559 (define_insn "*truncxfdf2_2"
4560 [(set (match_operand:DF 0 "memory_operand" "=m")
4562 (match_operand:XF 1 "register_operand" "f")))]
4563 "TARGET_80387 && !TARGET_64BIT"
4566 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4567 return \"fstp%z0\\t%y0\";
4569 return \"fst%z0\\t%y0\";
4571 [(set_attr "type" "fmov")
4572 (set_attr "mode" "DF")])
4575 [(set (match_operand:DF 0 "memory_operand" "")
4577 (match_operand:XF 1 "register_operand" "")))
4578 (clobber (match_operand:DF 2 "memory_operand" ""))]
4580 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4584 [(set (match_operand:DF 0 "register_operand" "")
4586 (match_operand:XF 1 "register_operand" "")))
4587 (clobber (match_operand:DF 2 "memory_operand" ""))]
4588 "TARGET_80387 && reload_completed"
4589 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4590 (set (match_dup 0) (match_dup 2))]
4593 (define_expand "trunctfdf2"
4594 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4596 (match_operand:TF 1 "register_operand" "")))
4597 (clobber (match_dup 2))])]
4599 "operands[2] = assign_386_stack_local (DFmode, 0);")
4601 (define_insn "*trunctfdf2_1"
4602 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,f")
4604 (match_operand:TF 1 "register_operand" "f,0")))
4605 (clobber (match_operand:DF 2 "memory_operand" "=m,m"))]
4609 switch (which_alternative)
4612 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4613 return \"fstp%z0\\t%y0\";
4615 return \"fst%z0\\t%y0\";
4617 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
4621 [(set_attr "type" "fmov,multi")
4622 (set_attr "mode" "DF")])
4624 (define_insn "*trunctfdf2_2"
4625 [(set (match_operand:DF 0 "memory_operand" "=m")
4627 (match_operand:TF 1 "register_operand" "f")))]
4631 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4632 return \"fstp%z0\\t%y0\";
4634 return \"fst%z0\\t%y0\";
4636 [(set_attr "type" "fmov")
4637 (set_attr "mode" "DF")])
4640 [(set (match_operand:DF 0 "memory_operand" "")
4642 (match_operand:TF 1 "register_operand" "")))
4643 (clobber (match_operand:DF 2 "memory_operand" ""))]
4645 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4649 [(set (match_operand:DF 0 "register_operand" "")
4651 (match_operand:TF 1 "register_operand" "")))
4652 (clobber (match_operand:DF 2 "memory_operand" ""))]
4653 "TARGET_80387 && reload_completed"
4654 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4655 (set (match_dup 0) (match_dup 2))]
4659 ;; %%% Break up all these bad boys.
4661 ;; Signed conversion to DImode.
4663 (define_expand "fix_truncxfdi2"
4664 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4665 (fix:DI (match_operand:XF 1 "register_operand" "")))
4666 (clobber (match_dup 2))
4667 (clobber (match_dup 3))
4668 (clobber (match_scratch:SI 4 ""))
4669 (clobber (match_scratch:XF 5 ""))])]
4670 "TARGET_80387 && !TARGET_64BIT"
4671 "operands[2] = assign_386_stack_local (SImode, 0);
4672 operands[3] = assign_386_stack_local (DImode, 1);")
4674 (define_expand "fix_trunctfdi2"
4675 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4676 (fix:DI (match_operand:TF 1 "register_operand" "")))
4677 (clobber (match_dup 2))
4678 (clobber (match_dup 3))
4679 (clobber (match_scratch:SI 4 ""))
4680 (clobber (match_scratch:TF 5 ""))])]
4682 "operands[2] = assign_386_stack_local (SImode, 0);
4683 operands[3] = assign_386_stack_local (DImode, 1);")
4685 (define_expand "fix_truncdfdi2"
4686 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4687 (fix:DI (match_operand:DF 1 "register_operand" "")))
4688 (clobber (match_dup 2))
4689 (clobber (match_dup 3))
4690 (clobber (match_scratch:SI 4 ""))
4691 (clobber (match_scratch:DF 5 ""))])]
4693 "operands[2] = assign_386_stack_local (SImode, 0);
4694 operands[3] = assign_386_stack_local (DImode, 1);")
4696 (define_expand "fix_truncsfdi2"
4697 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4698 (fix:DI (match_operand:SF 1 "register_operand" "")))
4699 (clobber (match_dup 2))
4700 (clobber (match_dup 3))
4701 (clobber (match_scratch:SI 4 ""))
4702 (clobber (match_scratch:SF 5 ""))])]
4704 "operands[2] = assign_386_stack_local (SImode, 0);
4705 operands[3] = assign_386_stack_local (DImode, 1);")
4707 (define_insn "*fix_truncdi_1"
4708 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4709 (fix:DI (match_operand 1 "register_operand" "f,f")))
4710 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4711 (clobber (match_operand:DI 3 "memory_operand" "=m,m"))
4712 (clobber (match_scratch:SI 4 "=&r,&r"))
4713 (clobber (match_scratch 5 "=&f,&f"))]
4714 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))"
4715 "* return output_fix_trunc (insn, operands);"
4716 [(set_attr "type" "multi")])
4719 [(set (match_operand:DI 0 "register_operand" "")
4720 (fix:DI (match_operand 1 "register_operand" "")))
4721 (clobber (match_operand:SI 2 "memory_operand" ""))
4722 (clobber (match_operand:DI 3 "memory_operand" ""))
4723 (clobber (match_scratch:SI 4 ""))
4724 (clobber (match_scratch 5 ""))]
4725 "reload_completed && !reg_overlap_mentioned_p (operands[4], operands[3])"
4726 [(parallel [(set (match_dup 3) (fix:DI (match_dup 1)))
4727 (clobber (match_dup 2))
4728 (clobber (match_dup 3))
4729 (clobber (match_dup 4))
4730 (clobber (match_dup 5))])
4731 (set (match_dup 0) (match_dup 3))]
4734 ;; Signed conversion to SImode.
4736 (define_expand "fix_truncxfsi2"
4737 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4738 (fix:SI (match_operand:XF 1 "register_operand" "")))
4739 (clobber (match_dup 2))
4740 (clobber (match_dup 3))
4741 (clobber (match_scratch:SI 4 ""))])]
4742 "TARGET_80387 && !TARGET_64BIT"
4743 "operands[2] = assign_386_stack_local (SImode, 0);
4744 operands[3] = assign_386_stack_local (SImode, 1);")
4746 (define_expand "fix_trunctfsi2"
4747 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4748 (fix:SI (match_operand:TF 1 "register_operand" "")))
4749 (clobber (match_dup 2))
4750 (clobber (match_dup 3))
4751 (clobber (match_scratch:SI 4 ""))])]
4753 "operands[2] = assign_386_stack_local (SImode, 0);
4754 operands[3] = assign_386_stack_local (SImode, 1);")
4756 (define_expand "fix_truncdfsi2"
4757 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4758 (fix:SI (match_operand:DF 1 "register_operand" "")))
4759 (clobber (match_dup 2))
4760 (clobber (match_dup 3))
4761 (clobber (match_scratch:SI 4 ""))])]
4762 "TARGET_80387 || TARGET_SSE2"
4767 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4768 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4769 if (out != operands[0])
4770 emit_move_insn (operands[0], out);
4775 operands[2] = assign_386_stack_local (SImode, 0);
4776 operands[3] = assign_386_stack_local (SImode, 1);
4780 (define_expand "fix_truncsfsi2"
4781 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4782 (fix:SI (match_operand:SF 1 "register_operand" "")))
4783 (clobber (match_dup 2))
4784 (clobber (match_dup 3))
4785 (clobber (match_scratch:SI 4 ""))])]
4786 "TARGET_80387 || TARGET_SSE"
4791 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4792 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4793 if (out != operands[0])
4794 emit_move_insn (operands[0], out);
4799 operands[2] = assign_386_stack_local (SImode, 0);
4800 operands[3] = assign_386_stack_local (SImode, 1);
4804 (define_insn "*fix_truncsi_1"
4805 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4806 (fix:SI (match_operand 1 "register_operand" "f,f")))
4807 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4808 (clobber (match_operand:SI 3 "memory_operand" "=m,m"))
4809 (clobber (match_scratch:SI 4 "=&r,r"))]
4810 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4811 && (!TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4812 "* return output_fix_trunc (insn, operands);"
4813 [(set_attr "type" "multi")])
4815 ;; When SSE available, it is always faster to use it!
4816 (define_insn "fix_truncsfsi_sse"
4817 [(set (match_operand:SI 0 "register_operand" "=r")
4818 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4820 "cvttss2si\\t{%1, %0|%0, %1}"
4821 [(set_attr "type" "sse")])
4823 (define_insn "fix_truncdfsi_sse"
4824 [(set (match_operand:SI 0 "register_operand" "=r")
4825 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4827 "cvttsd2si\\t{%1, %0|%0, %1}"
4828 [(set_attr "type" "sse")])
4831 [(set (match_operand:SI 0 "register_operand" "")
4832 (fix:SI (match_operand 1 "register_operand" "")))
4833 (clobber (match_operand:SI 2 "memory_operand" ""))
4834 (clobber (match_operand:SI 3 "memory_operand" ""))
4835 (clobber (match_scratch:SI 4 ""))]
4837 [(parallel [(set (match_dup 3) (fix:SI (match_dup 1)))
4838 (clobber (match_dup 2))
4839 (clobber (match_dup 3))
4840 (clobber (match_dup 4))])
4841 (set (match_dup 0) (match_dup 3))]
4844 ;; Signed conversion to HImode.
4846 (define_expand "fix_truncxfhi2"
4847 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4848 (fix:HI (match_operand:XF 1 "register_operand" "")))
4849 (clobber (match_dup 2))
4850 (clobber (match_dup 3))
4851 (clobber (match_scratch:SI 4 ""))])]
4852 "TARGET_80387 && !TARGET_64BIT"
4853 "operands[2] = assign_386_stack_local (SImode, 0);
4854 operands[3] = assign_386_stack_local (HImode, 1);")
4856 (define_expand "fix_trunctfhi2"
4857 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4858 (fix:HI (match_operand:TF 1 "register_operand" "")))
4859 (clobber (match_dup 2))
4860 (clobber (match_dup 3))
4861 (clobber (match_scratch:SI 4 ""))])]
4863 "operands[2] = assign_386_stack_local (SImode, 0);
4864 operands[3] = assign_386_stack_local (HImode, 1);")
4866 (define_expand "fix_truncdfhi2"
4867 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4868 (fix:HI (match_operand:DF 1 "register_operand" "")))
4869 (clobber (match_dup 2))
4870 (clobber (match_dup 3))
4871 (clobber (match_scratch:SI 4 ""))])]
4872 "TARGET_80387 && !TARGET_SSE2"
4873 "operands[2] = assign_386_stack_local (SImode, 0);
4874 operands[3] = assign_386_stack_local (HImode, 1);")
4876 (define_expand "fix_truncsfhi2"
4877 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4878 (fix:HI (match_operand:SF 1 "register_operand" "")))
4879 (clobber (match_dup 2))
4880 (clobber (match_dup 3))
4881 (clobber (match_scratch:SI 4 ""))])]
4882 "TARGET_80387 && !TARGET_SSE"
4883 "operands[2] = assign_386_stack_local (SImode, 0);
4884 operands[3] = assign_386_stack_local (HImode, 1);")
4886 (define_insn "*fix_trunchi_1"
4887 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4888 (fix:HI (match_operand 1 "register_operand" "f,f")))
4889 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4890 (clobber (match_operand:HI 3 "memory_operand" "=m,m"))
4891 (clobber (match_scratch:SI 4 "=&r,r"))]
4892 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4893 && (TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4894 "* return output_fix_trunc (insn, operands);"
4895 [(set_attr "type" "multi")])
4898 [(set (match_operand:HI 0 "register_operand" "")
4899 (fix:HI (match_operand 1 "register_operand" "")))
4900 (clobber (match_operand:SI 2 "memory_operand" ""))
4901 (clobber (match_operand:HI 3 "memory_operand" ""))
4902 (clobber (match_scratch:SI 4 ""))]
4904 [(parallel [(set (match_dup 3) (fix:HI (match_dup 1)))
4905 (clobber (match_dup 2))
4906 (clobber (match_dup 3))
4907 (clobber (match_dup 4))])
4908 (set (match_dup 0) (match_dup 3))]
4911 ;; %%% Kill these when reload knows how to do it.
4913 [(set (match_operand 0 "register_operand" "")
4914 (fix (match_operand 1 "register_operand" "")))]
4915 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[1]))
4916 && FP_REG_P (operands[1])"
4920 operands[2] = ix86_force_to_memory (GET_MODE (operands[0]), operands[0]);
4921 operands[2] = gen_rtx_FIX (GET_MODE (operands[2]), operands[1]);
4922 emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1]));
4923 emit_move_insn (operands[0], operands[2]);
4924 ix86_free_from_memory (GET_MODE (operands[0]));
4929 (define_insn "x86_fnstcw_1"
4930 [(set (match_operand:HI 0 "memory_operand" "=m")
4931 (unspec:HI [(reg:HI 18)] 11))]
4934 [(set_attr "length" "2")
4935 (set_attr "mode" "HI")
4936 (set_attr "i387" "1")
4937 (set_attr "ppro_uops" "few")])
4939 (define_insn "x86_fldcw_1"
4941 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
4944 [(set_attr "length" "2")
4945 (set_attr "mode" "HI")
4946 (set_attr "i387" "1")
4947 (set_attr "athlon_decode" "vector")
4948 (set_attr "ppro_uops" "few")])
4950 ;; Conversion between fixed point and floating point.
4952 ;; Even though we only accept memory inputs, the backend _really_
4953 ;; wants to be able to do this between registers.
4955 (define_insn "floathisf2"
4956 [(set (match_operand:SF 0 "register_operand" "=f,f")
4957 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4958 "TARGET_80387 && !TARGET_SSE"
4962 [(set_attr "type" "fmov,multi")
4963 (set_attr "mode" "SF")
4964 (set_attr "fp_int_src" "true")])
4966 (define_expand "floatsisf2"
4967 [(set (match_operand:SF 0 "register_operand" "")
4968 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4969 "TARGET_SSE || TARGET_80387"
4972 (define_insn "*floatsisf2_i387"
4973 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4974 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4975 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4979 cvtsi2ss\\t{%1, %0|%0, %1}"
4980 [(set_attr "type" "fmov,multi,sse")
4981 (set_attr "mode" "SF")
4982 (set_attr "fp_int_src" "true")])
4984 (define_insn "*floatsisf2_sse"
4985 [(set (match_operand:SF 0 "register_operand" "=x")
4986 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4987 "TARGET_80387 && TARGET_SSE"
4988 "cvtsi2ss\\t{%1, %0|%0, %1}"
4989 [(set_attr "type" "sse")
4990 (set_attr "mode" "SF")
4991 (set_attr "fp_int_src" "true")])
4993 (define_insn "floatdisf2"
4994 [(set (match_operand:SF 0 "register_operand" "=f,f")
4995 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5000 [(set_attr "type" "fmov,multi")
5001 (set_attr "mode" "SF")
5002 (set_attr "fp_int_src" "true")])
5004 (define_insn "floathidf2"
5005 [(set (match_operand:DF 0 "register_operand" "=f,f")
5006 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5007 "TARGET_80387 && !TARGET_SSE2"
5011 [(set_attr "type" "fmov,multi")
5012 (set_attr "mode" "DF")
5013 (set_attr "fp_int_src" "true")])
5015 (define_expand "floatsidf2"
5016 [(set (match_operand:DF 0 "register_operand" "")
5017 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
5021 (define_insn "*floatsidf2_i387"
5022 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
5023 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
5024 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5028 cvtsi2sd\\t{%1, %0|%0, %1}"
5029 [(set_attr "type" "fmov,multi,sse")
5030 (set_attr "mode" "DF")
5031 (set_attr "fp_int_src" "true")])
5033 (define_insn "*floatsidf2_sse"
5034 [(set (match_operand:DF 0 "register_operand" "=Y")
5035 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
5037 "cvtsi2sd\\t{%1, %0|%0, %1}"
5038 [(set_attr "type" "sse")
5039 (set_attr "mode" "DF")
5040 (set_attr "fp_int_src" "true")])
5042 (define_insn "floatdidf2"
5043 [(set (match_operand:DF 0 "register_operand" "=f,f")
5044 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5045 "TARGET_80387 && TARGET_SSE2"
5049 [(set_attr "type" "fmov,multi")
5050 (set_attr "mode" "DF")
5051 (set_attr "fp_int_src" "true")])
5053 (define_insn "floathixf2"
5054 [(set (match_operand:XF 0 "register_operand" "=f,f")
5055 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5056 "TARGET_80387 && !TARGET_64BIT"
5060 [(set_attr "type" "fmov,multi")
5061 (set_attr "mode" "XF")
5062 (set_attr "fp_int_src" "true")])
5064 (define_insn "floathitf2"
5065 [(set (match_operand:TF 0 "register_operand" "=f,f")
5066 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5071 [(set_attr "type" "fmov,multi")
5072 (set_attr "mode" "XF")
5073 (set_attr "fp_int_src" "true")])
5075 (define_insn "floatsixf2"
5076 [(set (match_operand:XF 0 "register_operand" "=f,f")
5077 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5078 "TARGET_80387 && !TARGET_64BIT"
5082 [(set_attr "type" "fmov,multi")
5083 (set_attr "mode" "XF")
5084 (set_attr "fp_int_src" "true")])
5086 (define_insn "floatsitf2"
5087 [(set (match_operand:TF 0 "register_operand" "=f,f")
5088 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5093 [(set_attr "type" "fmov,multi")
5094 (set_attr "mode" "XF")
5095 (set_attr "fp_int_src" "true")])
5097 (define_insn "floatdixf2"
5098 [(set (match_operand:XF 0 "register_operand" "=f,f")
5099 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5100 "TARGET_80387 && !TARGET_64BIT"
5104 [(set_attr "type" "fmov,multi")
5105 (set_attr "mode" "XF")
5106 (set_attr "fp_int_src" "true")])
5108 (define_insn "floatditf2"
5109 [(set (match_operand:TF 0 "register_operand" "=f,f")
5110 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5115 [(set_attr "type" "fmov,multi")
5116 (set_attr "mode" "XF")
5117 (set_attr "fp_int_src" "true")])
5119 ;; %%% Kill these when reload knows how to do it.
5121 [(set (match_operand 0 "register_operand" "")
5122 (float (match_operand 1 "register_operand" "")))]
5123 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))
5124 && FP_REG_P (operands[0])"
5128 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5129 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5130 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5131 ix86_free_from_memory (GET_MODE (operands[1]));
5137 ;; %%% splits for addsidi3
5138 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5139 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5140 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5142 (define_expand "adddi3"
5143 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5144 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5145 (match_operand:DI 2 "x86_64_general_operand" "")))
5146 (clobber (reg:CC 17))]
5148 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5150 (define_insn "*adddi3_1"
5151 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5152 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5153 (match_operand:DI 2 "general_operand" "roiF,riF")))
5154 (clobber (reg:CC 17))]
5159 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5160 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5161 (match_operand:DI 2 "general_operand" "")))
5162 (clobber (reg:CC 17))]
5163 "reload_completed && !TARGET_64BIT"
5164 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
5165 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5166 (parallel [(set (match_dup 3)
5167 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5170 (clobber (reg:CC 17))])]
5171 "split_di (operands+0, 1, operands+0, operands+3);
5172 split_di (operands+1, 1, operands+1, operands+4);
5173 split_di (operands+2, 1, operands+2, operands+5);")
5175 (define_insn "*adddi3_carry_rex64"
5176 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5177 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
5178 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5179 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5180 (clobber (reg:CC 17))]
5181 "ix86_binary_operator_ok (PLUS, DImode, operands)"
5182 "adc{q}\\t{%2, %0|%0, %2}"
5183 [(set_attr "type" "alu")
5184 (set_attr "pent_pair" "pu")
5185 (set_attr "mode" "DI")
5186 (set_attr "ppro_uops" "few")])
5188 (define_insn "*adddi3_cc_rex64"
5189 [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5190 (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12))
5191 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5192 (plus:DI (match_dup 1) (match_dup 2)))]
5193 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5194 "add{q}\\t{%2, %0|%0, %2}"
5195 [(set_attr "type" "alu")
5196 (set_attr "mode" "DI")])
5198 (define_insn "*addsi3_carry"
5199 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5200 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5201 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5202 (match_operand:SI 2 "general_operand" "ri,rm")))
5203 (clobber (reg:CC 17))]
5204 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5205 "adc{l}\\t{%2, %0|%0, %2}"
5206 [(set_attr "type" "alu")
5207 (set_attr "pent_pair" "pu")
5208 (set_attr "mode" "SI")
5209 (set_attr "ppro_uops" "few")])
5211 (define_insn "*addsi3_carry_zext"
5212 [(set (match_operand:DI 0 "register_operand" "=r")
5214 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5215 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5216 (match_operand:SI 2 "general_operand" "rim"))))
5217 (clobber (reg:CC 17))]
5218 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5219 "adc{l}\\t{%2, %k0|%k0, %2}"
5220 [(set_attr "type" "alu")
5221 (set_attr "pent_pair" "pu")
5222 (set_attr "mode" "SI")
5223 (set_attr "ppro_uops" "few")])
5225 (define_insn "*addsi3_cc"
5226 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5227 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
5228 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5229 (plus:SI (match_dup 1) (match_dup 2)))]
5230 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5231 "add{l}\\t{%2, %0|%0, %2}"
5232 [(set_attr "type" "alu")
5233 (set_attr "mode" "SI")])
5235 (define_insn "addqi3_cc"
5236 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5237 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
5238 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5239 (plus:QI (match_dup 1) (match_dup 2)))]
5240 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5241 "add{b}\\t{%2, %0|%0, %2}"
5242 [(set_attr "type" "alu")
5243 (set_attr "mode" "QI")])
5245 (define_expand "addsi3"
5246 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5247 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5248 (match_operand:SI 2 "general_operand" "")))
5249 (clobber (reg:CC 17))])]
5251 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5253 (define_insn "*lea_0"
5254 [(set (match_operand:SI 0 "register_operand" "=r")
5255 (match_operand:SI 1 "address_operand" "p"))]
5257 "lea{l}\\t{%a1, %0|%0, %a1}"
5258 [(set_attr "type" "lea")
5259 (set_attr "mode" "SI")])
5261 ;; The lea patterns for non-Pmodes needs to be matched by several
5262 ;; insns converted to real lea by splitters.
5264 (define_insn_and_split "*lea_general_1"
5265 [(set (match_operand 0 "register_operand" "=r")
5266 (plus (plus (match_operand 1 "register_operand" "r")
5267 (match_operand 2 "register_operand" "r"))
5268 (match_operand 3 "immediate_operand" "i")))]
5269 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
5270 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5271 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5272 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5273 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5274 || GET_MODE (operands[3]) == VOIDmode)"
5276 "&& reload_completed"
5281 operands[0] = gen_lowpart (SImode, operands[0]);
5282 operands[1] = gen_lowpart (Pmode, operands[1]);
5283 operands[2] = gen_lowpart (Pmode, operands[2]);
5284 operands[3] = gen_lowpart (Pmode, operands[3]);
5285 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5287 if (Pmode != SImode)
5288 pat = gen_rtx_SUBREG (SImode, pat, 0);
5289 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5292 [(set_attr "type" "lea")
5293 (set_attr "mode" "SI")])
5295 (define_insn_and_split "*lea_general_2"
5296 [(set (match_operand 0 "register_operand" "=r")
5297 (plus (mult (match_operand 1 "register_operand" "r")
5298 (match_operand 2 "const248_operand" "i"))
5299 (match_operand 3 "nonmemory_operand" "ri")))]
5300 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
5301 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5302 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5303 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5304 || GET_MODE (operands[3]) == VOIDmode)"
5306 "&& reload_completed"
5311 operands[0] = gen_lowpart (SImode, operands[0]);
5312 operands[1] = gen_lowpart (Pmode, operands[1]);
5313 operands[3] = gen_lowpart (Pmode, operands[3]);
5314 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5316 if (Pmode != SImode)
5317 pat = gen_rtx_SUBREG (SImode, pat, 0);
5318 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5321 [(set_attr "type" "lea")
5322 (set_attr "mode" "SI")])
5324 (define_insn_and_split "*lea_general_3"
5325 [(set (match_operand 0 "register_operand" "=r")
5326 (plus (plus (mult (match_operand 1 "register_operand" "r")
5327 (match_operand 2 "const248_operand" "i"))
5328 (match_operand 3 "register_operand" "r"))
5329 (match_operand 4 "immediate_operand" "i")))]
5330 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
5331 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5332 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5333 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5335 "&& reload_completed"
5340 operands[0] = gen_lowpart (SImode, operands[0]);
5341 operands[1] = gen_lowpart (Pmode, operands[1]);
5342 operands[3] = gen_lowpart (Pmode, operands[3]);
5343 operands[4] = gen_lowpart (Pmode, operands[4]);
5344 pat = gen_rtx_PLUS (Pmode,
5345 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5349 if (Pmode != SImode)
5350 pat = gen_rtx_SUBREG (SImode, pat, 0);
5351 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5354 [(set_attr "type" "lea")
5355 (set_attr "mode" "SI")])
5357 (define_insn "*adddi_1_rex64"
5358 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5359 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5360 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5361 (clobber (reg:CC 17))]
5362 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5365 switch (get_attr_type (insn))
5368 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5369 return \"lea{q}\\t{%a2, %0|%0, %a2}\";
5372 if (! rtx_equal_p (operands[0], operands[1]))
5374 if (operands[2] == const1_rtx)
5375 return \"inc{q}\\t%0\";
5376 else if (operands[2] == constm1_rtx)
5377 return \"dec{q}\\t%0\";
5382 if (! rtx_equal_p (operands[0], operands[1]))
5385 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5386 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5387 if (GET_CODE (operands[2]) == CONST_INT
5388 && (INTVAL (operands[2]) == 128
5389 || (INTVAL (operands[2]) < 0
5390 && INTVAL (operands[2]) != -128)))
5392 operands[2] = GEN_INT (-INTVAL (operands[2]));
5393 return \"sub{q}\\t{%2, %0|%0, %2}\";
5395 return \"add{q}\\t{%2, %0|%0, %2}\";
5399 (cond [(eq_attr "alternative" "2")
5400 (const_string "lea")
5401 ; Current assemblers are broken and do not allow @GOTOFF in
5402 ; ought but a memory context.
5403 (match_operand:DI 2 "pic_symbolic_operand" "")
5404 (const_string "lea")
5405 (match_operand:DI 2 "incdec_operand" "")
5406 (const_string "incdec")
5408 (const_string "alu")))
5409 (set_attr "mode" "DI")])
5411 ;; Convert lea to the lea pattern to avoid flags dependency.
5413 [(set (match_operand:DI 0 "register_operand" "")
5414 (plus:DI (match_operand:DI 1 "register_operand" "")
5415 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5416 (clobber (reg:CC 17))]
5417 "reload_completed && TARGET_64BIT
5418 && true_regnum (operands[0]) != true_regnum (operands[1])"
5420 (plus:DI (match_dup 1)
5424 (define_insn "*adddi_2_rex64"
5427 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5428 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5430 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5431 (plus:DI (match_dup 1) (match_dup 2)))]
5432 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5433 && ix86_binary_operator_ok (PLUS, DImode, operands)
5434 /* Current assemblers are broken and do not allow @GOTOFF in
5435 ought but a memory context. */
5436 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5439 switch (get_attr_type (insn))
5442 if (! rtx_equal_p (operands[0], operands[1]))
5444 if (operands[2] == const1_rtx)
5445 return \"inc{q}\\t%0\";
5446 else if (operands[2] == constm1_rtx)
5447 return \"dec{q}\\t%0\";
5452 if (! rtx_equal_p (operands[0], operands[1]))
5454 /* ???? We ought to handle there the 32bit case too
5455 - do we need new constrant? */
5456 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5457 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5458 if (GET_CODE (operands[2]) == CONST_INT
5459 && (INTVAL (operands[2]) == 128
5460 || (INTVAL (operands[2]) < 0
5461 && INTVAL (operands[2]) != -128)))
5463 operands[2] = GEN_INT (-INTVAL (operands[2]));
5464 return \"sub{q}\\t{%2, %0|%0, %2}\";
5466 return \"add{q}\\t{%2, %0|%0, %2}\";
5470 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5471 (const_string "incdec")
5472 (const_string "alu")))
5473 (set_attr "mode" "DI")])
5475 (define_insn "*adddi_3_rex64"
5477 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5478 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5479 (clobber (match_scratch:DI 0 "=r"))]
5481 && ix86_match_ccmode (insn, CCZmode)
5482 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5483 /* Current assemblers are broken and do not allow @GOTOFF in
5484 ought but a memory context. */
5485 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5488 switch (get_attr_type (insn))
5491 if (! rtx_equal_p (operands[0], operands[1]))
5493 if (operands[2] == const1_rtx)
5494 return \"inc{q}\\t%0\";
5495 else if (operands[2] == constm1_rtx)
5496 return \"dec{q}\\t%0\";
5501 if (! rtx_equal_p (operands[0], operands[1]))
5503 /* ???? We ought to handle there the 32bit case too
5504 - do we need new constrant? */
5505 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5506 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5507 if (GET_CODE (operands[2]) == CONST_INT
5508 && (INTVAL (operands[2]) == 128
5509 || (INTVAL (operands[2]) < 0
5510 && INTVAL (operands[2]) != -128)))
5512 operands[2] = GEN_INT (-INTVAL (operands[2]));
5513 return \"sub{q}\\t{%2, %0|%0, %2}\";
5515 return \"add{q}\\t{%2, %0|%0, %2}\";
5519 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5520 (const_string "incdec")
5521 (const_string "alu")))
5522 (set_attr "mode" "DI")])
5524 ; For comparisons against 1, -1 and 128, we may generate better code
5525 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5526 ; is matched then. We can't accept general immediate, because for
5527 ; case of overflows, the result is messed up.
5528 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5530 ; Also carry flag is reversed compared to cmp, so this converison is valid
5531 ; only for comparisons not depending on it.
5532 (define_insn "*adddi_4_rex64"
5534 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5535 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5536 (clobber (match_scratch:DI 0 "=rm"))]
5538 && ix86_match_ccmode (insn, CCGCmode)"
5541 switch (get_attr_type (insn))
5544 if (operands[2] == constm1_rtx)
5545 return \"inc{q}\\t%0\";
5546 else if (operands[2] == const1_rtx)
5547 return \"dec{q}\\t%0\";
5552 if (! rtx_equal_p (operands[0], operands[1]))
5554 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5555 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5556 if ((INTVAL (operands[2]) == -128
5557 || (INTVAL (operands[2]) > 0
5558 && INTVAL (operands[2]) != 128)))
5559 return \"sub{q}\\t{%2, %0|%0, %2}\";
5560 operands[2] = GEN_INT (-INTVAL (operands[2]));
5561 return \"add{q}\\t{%2, %0|%0, %2}\";
5565 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5566 (const_string "incdec")
5567 (const_string "alu")))
5568 (set_attr "mode" "DI")])
5570 (define_insn "*adddi_5_rex64"
5573 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5574 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5576 (clobber (match_scratch:DI 0 "=r"))]
5578 && ix86_match_ccmode (insn, CCGOCmode)
5579 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5580 /* Current assemblers are broken and do not allow @GOTOFF in
5581 ought but a memory context. */
5582 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5585 switch (get_attr_type (insn))
5588 if (! rtx_equal_p (operands[0], operands[1]))
5590 if (operands[2] == const1_rtx)
5591 return \"inc{q}\\t%0\";
5592 else if (operands[2] == constm1_rtx)
5593 return \"dec{q}\\t%0\";
5598 if (! rtx_equal_p (operands[0], operands[1]))
5600 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5601 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5602 if (GET_CODE (operands[2]) == CONST_INT
5603 && (INTVAL (operands[2]) == 128
5604 || (INTVAL (operands[2]) < 0
5605 && INTVAL (operands[2]) != -128)))
5607 operands[2] = GEN_INT (-INTVAL (operands[2]));
5608 return \"sub{q}\\t{%2, %0|%0, %2}\";
5610 return \"add{q}\\t{%2, %0|%0, %2}\";
5614 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5615 (const_string "incdec")
5616 (const_string "alu")))
5617 (set_attr "mode" "DI")])
5620 (define_insn "*addsi_1"
5621 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5622 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5623 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5624 (clobber (reg:CC 17))]
5625 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5628 switch (get_attr_type (insn))
5631 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5632 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
5635 if (! rtx_equal_p (operands[0], operands[1]))
5637 if (operands[2] == const1_rtx)
5638 return \"inc{l}\\t%0\";
5639 else if (operands[2] == constm1_rtx)
5640 return \"dec{l}\\t%0\";
5645 if (! rtx_equal_p (operands[0], operands[1]))
5648 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5649 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5650 if (GET_CODE (operands[2]) == CONST_INT
5651 && (INTVAL (operands[2]) == 128
5652 || (INTVAL (operands[2]) < 0
5653 && INTVAL (operands[2]) != -128)))
5655 operands[2] = GEN_INT (-INTVAL (operands[2]));
5656 return \"sub{l}\\t{%2, %0|%0, %2}\";
5658 return \"add{l}\\t{%2, %0|%0, %2}\";
5662 (cond [(eq_attr "alternative" "2")
5663 (const_string "lea")
5664 ; Current assemblers are broken and do not allow @GOTOFF in
5665 ; ought but a memory context.
5666 (match_operand:SI 2 "pic_symbolic_operand" "")
5667 (const_string "lea")
5668 (match_operand:SI 2 "incdec_operand" "")
5669 (const_string "incdec")
5671 (const_string "alu")))
5672 (set_attr "mode" "SI")])
5674 ;; Convert lea to the lea pattern to avoid flags dependency.
5676 [(set (match_operand 0 "register_operand" "")
5677 (plus (match_operand 1 "register_operand" "")
5678 (match_operand 2 "nonmemory_operand" "")))
5679 (clobber (reg:CC 17))]
5681 && true_regnum (operands[0]) != true_regnum (operands[1])"
5686 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5687 may confuse gen_lowpart. */
5688 if (GET_MODE (operands[0]) != Pmode)
5690 operands[1] = gen_lowpart (Pmode, operands[1]);
5691 operands[2] = gen_lowpart (Pmode, operands[2]);
5693 operands[0] = gen_lowpart (SImode, operands[0]);
5694 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5695 if (Pmode != SImode)
5696 pat = gen_rtx_SUBREG (SImode, pat, 0);
5697 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5701 ;; It may seem that nonimmediate operand is proper one for operand 1.
5702 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5703 ;; we take care in ix86_binary_operator_ok to not allow two memory
5704 ;; operands so proper swapping will be done in reload. This allow
5705 ;; patterns constructed from addsi_1 to match.
5706 (define_insn "addsi_1_zext"
5707 [(set (match_operand:DI 0 "register_operand" "=r,r")
5709 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5710 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5711 (clobber (reg:CC 17))]
5712 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5715 switch (get_attr_type (insn))
5718 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5719 return \"lea{l}\\t{%a2, %k0|%k0, %a2}\";
5722 if (operands[2] == const1_rtx)
5723 return \"inc{l}\\t%k0\";
5724 else if (operands[2] == constm1_rtx)
5725 return \"dec{l}\\t%k0\";
5730 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5731 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5732 if (GET_CODE (operands[2]) == CONST_INT
5733 && (INTVAL (operands[2]) == 128
5734 || (INTVAL (operands[2]) < 0
5735 && INTVAL (operands[2]) != -128)))
5737 operands[2] = GEN_INT (-INTVAL (operands[2]));
5738 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5740 return \"add{l}\\t{%2, %k0|%k0, %2}\";
5744 (cond [(eq_attr "alternative" "1")
5745 (const_string "lea")
5746 ; Current assemblers are broken and do not allow @GOTOFF in
5747 ; ought but a memory context.
5748 (match_operand:SI 2 "pic_symbolic_operand" "")
5749 (const_string "lea")
5750 (match_operand:SI 2 "incdec_operand" "")
5751 (const_string "incdec")
5753 (const_string "alu")))
5754 (set_attr "mode" "SI")])
5756 ;; Convert lea to the lea pattern to avoid flags dependency.
5758 [(set (match_operand:DI 0 "register_operand" "")
5760 (plus:SI (match_operand:SI 1 "register_operand" "")
5761 (match_operand:SI 2 "nonmemory_operand" ""))))
5762 (clobber (reg:CC 17))]
5764 && true_regnum (operands[0]) != true_regnum (operands[1])"
5766 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5769 operands[1] = gen_lowpart (Pmode, operands[1]);
5770 operands[2] = gen_lowpart (Pmode, operands[2]);
5773 (define_insn "*addsi_2"
5776 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5777 (match_operand:SI 2 "general_operand" "rmni,rni"))
5779 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5780 (plus:SI (match_dup 1) (match_dup 2)))]
5781 "ix86_match_ccmode (insn, CCGOCmode)
5782 && ix86_binary_operator_ok (PLUS, SImode, operands)
5783 /* Current assemblers are broken and do not allow @GOTOFF in
5784 ought but a memory context. */
5785 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5788 switch (get_attr_type (insn))
5791 if (! rtx_equal_p (operands[0], operands[1]))
5793 if (operands[2] == const1_rtx)
5794 return \"inc{l}\\t%0\";
5795 else if (operands[2] == constm1_rtx)
5796 return \"dec{l}\\t%0\";
5801 if (! rtx_equal_p (operands[0], operands[1]))
5803 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5804 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5805 if (GET_CODE (operands[2]) == CONST_INT
5806 && (INTVAL (operands[2]) == 128
5807 || (INTVAL (operands[2]) < 0
5808 && INTVAL (operands[2]) != -128)))
5810 operands[2] = GEN_INT (-INTVAL (operands[2]));
5811 return \"sub{l}\\t{%2, %0|%0, %2}\";
5813 return \"add{l}\\t{%2, %0|%0, %2}\";
5817 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5818 (const_string "incdec")
5819 (const_string "alu")))
5820 (set_attr "mode" "SI")])
5822 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5823 (define_insn "*addsi_2_zext"
5826 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5827 (match_operand:SI 2 "general_operand" "rmni"))
5829 (set (match_operand:DI 0 "register_operand" "=r")
5830 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5831 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5832 && ix86_binary_operator_ok (PLUS, SImode, operands)
5833 /* Current assemblers are broken and do not allow @GOTOFF in
5834 ought but a memory context. */
5835 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5838 switch (get_attr_type (insn))
5841 if (operands[2] == const1_rtx)
5842 return \"inc{l}\\t%k0\";
5843 else if (operands[2] == constm1_rtx)
5844 return \"dec{l}\\t%k0\";
5849 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5850 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5851 if (GET_CODE (operands[2]) == CONST_INT
5852 && (INTVAL (operands[2]) == 128
5853 || (INTVAL (operands[2]) < 0
5854 && INTVAL (operands[2]) != -128)))
5856 operands[2] = GEN_INT (-INTVAL (operands[2]));
5857 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5859 return \"add{l}\\t{%2, %k0|%k0, %2}\";
5863 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5864 (const_string "incdec")
5865 (const_string "alu")))
5866 (set_attr "mode" "SI")])
5868 (define_insn "*addsi_3"
5870 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5871 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5872 (clobber (match_scratch:SI 0 "=r"))]
5873 "ix86_match_ccmode (insn, CCZmode)
5874 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5875 /* Current assemblers are broken and do not allow @GOTOFF in
5876 ought but a memory context. */
5877 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5880 switch (get_attr_type (insn))
5883 if (! rtx_equal_p (operands[0], operands[1]))
5885 if (operands[2] == const1_rtx)
5886 return \"inc{l}\\t%0\";
5887 else if (operands[2] == constm1_rtx)
5888 return \"dec{l}\\t%0\";
5893 if (! rtx_equal_p (operands[0], operands[1]))
5895 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5896 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5897 if (GET_CODE (operands[2]) == CONST_INT
5898 && (INTVAL (operands[2]) == 128
5899 || (INTVAL (operands[2]) < 0
5900 && INTVAL (operands[2]) != -128)))
5902 operands[2] = GEN_INT (-INTVAL (operands[2]));
5903 return \"sub{l}\\t{%2, %0|%0, %2}\";
5905 return \"add{l}\\t{%2, %0|%0, %2}\";
5909 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5910 (const_string "incdec")
5911 (const_string "alu")))
5912 (set_attr "mode" "SI")])
5914 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5915 (define_insn "*addsi_3_zext"
5917 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5918 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5919 (set (match_operand:DI 0 "register_operand" "=r")
5920 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5921 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5922 && ix86_binary_operator_ok (PLUS, SImode, operands)
5923 /* Current assemblers are broken and do not allow @GOTOFF in
5924 ought but a memory context. */
5925 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5928 switch (get_attr_type (insn))
5931 if (operands[2] == const1_rtx)
5932 return \"inc{l}\\t%k0\";
5933 else if (operands[2] == constm1_rtx)
5934 return \"dec{l}\\t%k0\";
5939 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5940 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5941 if (GET_CODE (operands[2]) == CONST_INT
5942 && (INTVAL (operands[2]) == 128
5943 || (INTVAL (operands[2]) < 0
5944 && INTVAL (operands[2]) != -128)))
5946 operands[2] = GEN_INT (-INTVAL (operands[2]));
5947 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5949 return \"add{l}\\t{%2, %k0|%k0, %2}\";
5953 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5954 (const_string "incdec")
5955 (const_string "alu")))
5956 (set_attr "mode" "SI")])
5958 ; For comparisons agains 1, -1 and 128, we may generate better code
5959 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5960 ; is matched then. We can't accept general immediate, because for
5961 ; case of overflows, the result is messed up.
5962 ; This pattern also don't hold of 0x80000000, since the value overflows
5964 ; Also carry flag is reversed compared to cmp, so this converison is valid
5965 ; only for comparisons not depending on it.
5966 (define_insn "*addsi_4"
5968 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5969 (match_operand:SI 2 "const_int_operand" "n")))
5970 (clobber (match_scratch:SI 0 "=rm"))]
5971 "ix86_match_ccmode (insn, CCGCmode)
5972 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5975 switch (get_attr_type (insn))
5978 if (operands[2] == constm1_rtx)
5979 return \"inc{l}\\t%0\";
5980 else if (operands[2] == const1_rtx)
5981 return \"dec{l}\\t%0\";
5986 if (! rtx_equal_p (operands[0], operands[1]))
5988 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5989 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5990 if ((INTVAL (operands[2]) == -128
5991 || (INTVAL (operands[2]) > 0
5992 && INTVAL (operands[2]) != 128)))
5993 return \"sub{l}\\t{%2, %0|%0, %2}\";
5994 operands[2] = GEN_INT (-INTVAL (operands[2]));
5995 return \"add{l}\\t{%2, %0|%0, %2}\";
5999 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6000 (const_string "incdec")
6001 (const_string "alu")))
6002 (set_attr "mode" "SI")])
6004 (define_insn "*addsi_5"
6007 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6008 (match_operand:SI 2 "general_operand" "rmni"))
6010 (clobber (match_scratch:SI 0 "=r"))]
6011 "ix86_match_ccmode (insn, CCGOCmode)
6012 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6013 /* Current assemblers are broken and do not allow @GOTOFF in
6014 ought but a memory context. */
6015 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6018 switch (get_attr_type (insn))
6021 if (! rtx_equal_p (operands[0], operands[1]))
6023 if (operands[2] == const1_rtx)
6024 return \"inc{l}\\t%0\";
6025 else if (operands[2] == constm1_rtx)
6026 return \"dec{l}\\t%0\";
6031 if (! rtx_equal_p (operands[0], operands[1]))
6033 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6034 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6035 if (GET_CODE (operands[2]) == CONST_INT
6036 && (INTVAL (operands[2]) == 128
6037 || (INTVAL (operands[2]) < 0
6038 && INTVAL (operands[2]) != -128)))
6040 operands[2] = GEN_INT (-INTVAL (operands[2]));
6041 return \"sub{l}\\t{%2, %0|%0, %2}\";
6043 return \"add{l}\\t{%2, %0|%0, %2}\";
6047 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6048 (const_string "incdec")
6049 (const_string "alu")))
6050 (set_attr "mode" "SI")])
6052 (define_expand "addhi3"
6053 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6054 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6055 (match_operand:HI 2 "general_operand" "")))
6056 (clobber (reg:CC 17))])]
6057 "TARGET_HIMODE_MATH"
6058 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6060 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6061 ;; type optimizations enabled by define-splits. This is not important
6062 ;; for PII, and in fact harmful because of partial register stalls.
6064 (define_insn "*addhi_1_lea"
6065 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6066 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6067 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6068 (clobber (reg:CC 17))]
6069 "!TARGET_PARTIAL_REG_STALL
6070 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6073 switch (get_attr_type (insn))
6078 if (operands[2] == const1_rtx)
6079 return \"inc{w}\\t%0\";
6080 else if (operands[2] == constm1_rtx
6081 || (GET_CODE (operands[2]) == CONST_INT
6082 && INTVAL (operands[2]) == 65535))
6083 return \"dec{w}\\t%0\";
6087 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6088 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6089 if (GET_CODE (operands[2]) == CONST_INT
6090 && (INTVAL (operands[2]) == 128
6091 || (INTVAL (operands[2]) < 0
6092 && INTVAL (operands[2]) != -128)))
6094 operands[2] = GEN_INT (-INTVAL (operands[2]));
6095 return \"sub{w}\\t{%2, %0|%0, %2}\";
6097 return \"add{w}\\t{%2, %0|%0, %2}\";
6101 (if_then_else (eq_attr "alternative" "2")
6102 (const_string "lea")
6103 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6104 (const_string "incdec")
6105 (const_string "alu"))))
6106 (set_attr "mode" "HI,HI,SI")])
6108 (define_insn "*addhi_1"
6109 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6110 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6111 (match_operand:HI 2 "general_operand" "ri,rm")))
6112 (clobber (reg:CC 17))]
6113 "TARGET_PARTIAL_REG_STALL
6114 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6117 switch (get_attr_type (insn))
6120 if (operands[2] == const1_rtx)
6121 return \"inc{w}\\t%0\";
6122 else if (operands[2] == constm1_rtx
6123 || (GET_CODE (operands[2]) == CONST_INT
6124 && INTVAL (operands[2]) == 65535))
6125 return \"dec{w}\\t%0\";
6129 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6130 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6131 if (GET_CODE (operands[2]) == CONST_INT
6132 && (INTVAL (operands[2]) == 128
6133 || (INTVAL (operands[2]) < 0
6134 && INTVAL (operands[2]) != -128)))
6136 operands[2] = GEN_INT (-INTVAL (operands[2]));
6137 return \"sub{w}\\t{%2, %0|%0, %2}\";
6139 return \"add{w}\\t{%2, %0|%0, %2}\";
6143 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6144 (const_string "incdec")
6145 (const_string "alu")))
6146 (set_attr "mode" "HI")])
6148 (define_insn "*addhi_2"
6151 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6152 (match_operand:HI 2 "general_operand" "rmni,rni"))
6154 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6155 (plus:HI (match_dup 1) (match_dup 2)))]
6156 "ix86_match_ccmode (insn, CCGOCmode)
6157 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6160 switch (get_attr_type (insn))
6163 if (operands[2] == const1_rtx)
6164 return \"inc{w}\\t%0\";
6165 else if (operands[2] == constm1_rtx
6166 || (GET_CODE (operands[2]) == CONST_INT
6167 && INTVAL (operands[2]) == 65535))
6168 return \"dec{w}\\t%0\";
6172 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6173 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6174 if (GET_CODE (operands[2]) == CONST_INT
6175 && (INTVAL (operands[2]) == 128
6176 || (INTVAL (operands[2]) < 0
6177 && INTVAL (operands[2]) != -128)))
6179 operands[2] = GEN_INT (-INTVAL (operands[2]));
6180 return \"sub{w}\\t{%2, %0|%0, %2}\";
6182 return \"add{w}\\t{%2, %0|%0, %2}\";
6186 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6187 (const_string "incdec")
6188 (const_string "alu")))
6189 (set_attr "mode" "HI")])
6191 (define_insn "*addhi_3"
6193 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6194 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6195 (clobber (match_scratch:HI 0 "=r"))]
6196 "ix86_match_ccmode (insn, CCZmode)
6197 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6200 switch (get_attr_type (insn))
6203 if (operands[2] == const1_rtx)
6204 return \"inc{w}\\t%0\";
6205 else if (operands[2] == constm1_rtx
6206 || (GET_CODE (operands[2]) == CONST_INT
6207 && INTVAL (operands[2]) == 65535))
6208 return \"dec{w}\\t%0\";
6212 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6213 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6214 if (GET_CODE (operands[2]) == CONST_INT
6215 && (INTVAL (operands[2]) == 128
6216 || (INTVAL (operands[2]) < 0
6217 && INTVAL (operands[2]) != -128)))
6219 operands[2] = GEN_INT (-INTVAL (operands[2]));
6220 return \"sub{w}\\t{%2, %0|%0, %2}\";
6222 return \"add{w}\\t{%2, %0|%0, %2}\";
6226 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6227 (const_string "incdec")
6228 (const_string "alu")))
6229 (set_attr "mode" "HI")])
6231 ; See comments above addsi_3_imm for details.
6232 (define_insn "*addhi_4"
6234 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6235 (match_operand:HI 2 "const_int_operand" "n")))
6236 (clobber (match_scratch:HI 0 "=rm"))]
6237 "ix86_match_ccmode (insn, CCGCmode)
6238 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6241 switch (get_attr_type (insn))
6244 if (operands[2] == constm1_rtx
6245 || (GET_CODE (operands[2]) == CONST_INT
6246 && INTVAL (operands[2]) == 65535))
6247 return \"inc{w}\\t%0\";
6248 else if (operands[2] == const1_rtx)
6249 return \"dec{w}\\t%0\";
6254 if (! rtx_equal_p (operands[0], operands[1]))
6256 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6257 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6258 if ((INTVAL (operands[2]) == -128
6259 || (INTVAL (operands[2]) > 0
6260 && INTVAL (operands[2]) != 128)))
6261 return \"sub{w}\\t{%2, %0|%0, %2}\";
6262 operands[2] = GEN_INT (-INTVAL (operands[2]));
6263 return \"add{w}\\t{%2, %0|%0, %2}\";
6267 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6268 (const_string "incdec")
6269 (const_string "alu")))
6270 (set_attr "mode" "SI")])
6273 (define_insn "*addhi_5"
6276 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6277 (match_operand:HI 2 "general_operand" "rmni"))
6279 (clobber (match_scratch:HI 0 "=r"))]
6280 "ix86_match_ccmode (insn, CCGOCmode)
6281 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6284 switch (get_attr_type (insn))
6287 if (operands[2] == const1_rtx)
6288 return \"inc{w}\\t%0\";
6289 else if (operands[2] == constm1_rtx
6290 || (GET_CODE (operands[2]) == CONST_INT
6291 && INTVAL (operands[2]) == 65535))
6292 return \"dec{w}\\t%0\";
6296 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6297 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6298 if (GET_CODE (operands[2]) == CONST_INT
6299 && (INTVAL (operands[2]) == 128
6300 || (INTVAL (operands[2]) < 0
6301 && INTVAL (operands[2]) != -128)))
6303 operands[2] = GEN_INT (-INTVAL (operands[2]));
6304 return \"sub{w}\\t{%2, %0|%0, %2}\";
6306 return \"add{w}\\t{%2, %0|%0, %2}\";
6310 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6311 (const_string "incdec")
6312 (const_string "alu")))
6313 (set_attr "mode" "HI")])
6315 (define_expand "addqi3"
6316 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6317 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6318 (match_operand:QI 2 "general_operand" "")))
6319 (clobber (reg:CC 17))])]
6320 "TARGET_QIMODE_MATH"
6321 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6323 ;; %%% Potential partial reg stall on alternative 2. What to do?
6324 (define_insn "*addqi_1_lea"
6325 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6326 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6327 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6328 (clobber (reg:CC 17))]
6329 "!TARGET_PARTIAL_REG_STALL
6330 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6333 int widen = (which_alternative == 2);
6334 switch (get_attr_type (insn))
6339 if (operands[2] == const1_rtx)
6340 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
6341 else if (operands[2] == constm1_rtx
6342 || (GET_CODE (operands[2]) == CONST_INT
6343 && INTVAL (operands[2]) == 255))
6344 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
6348 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6349 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6350 if (GET_CODE (operands[2]) == CONST_INT
6351 && (INTVAL (operands[2]) == 128
6352 || (INTVAL (operands[2]) < 0
6353 && INTVAL (operands[2]) != -128)))
6355 operands[2] = GEN_INT (-INTVAL (operands[2]));
6357 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6359 return \"sub{b}\\t{%2, %0|%0, %2}\";
6362 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
6364 return \"add{b}\\t{%2, %0|%0, %2}\";
6368 (if_then_else (eq_attr "alternative" "3")
6369 (const_string "lea")
6370 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6371 (const_string "incdec")
6372 (const_string "alu"))))
6373 (set_attr "mode" "QI,QI,SI,SI")])
6375 (define_insn "*addqi_1"
6376 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6377 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6378 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6379 (clobber (reg:CC 17))]
6380 "TARGET_PARTIAL_REG_STALL
6381 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6384 int widen = (which_alternative == 2);
6385 switch (get_attr_type (insn))
6388 if (operands[2] == const1_rtx)
6389 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
6390 else if (operands[2] == constm1_rtx
6391 || (GET_CODE (operands[2]) == CONST_INT
6392 && INTVAL (operands[2]) == 255))
6393 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
6397 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6398 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6399 if (GET_CODE (operands[2]) == CONST_INT
6400 && (INTVAL (operands[2]) == 128
6401 || (INTVAL (operands[2]) < 0
6402 && INTVAL (operands[2]) != -128)))
6404 operands[2] = GEN_INT (-INTVAL (operands[2]));
6406 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
6408 return \"sub{b}\\t{%2, %0|%0, %2}\";
6411 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
6413 return \"add{b}\\t{%2, %0|%0, %2}\";
6417 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6418 (const_string "incdec")
6419 (const_string "alu")))
6420 (set_attr "mode" "QI,QI,SI")])
6422 (define_insn "*addqi_2"
6425 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6426 (match_operand:QI 2 "general_operand" "qmni,qni"))
6428 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6429 (plus:QI (match_dup 1) (match_dup 2)))]
6430 "ix86_match_ccmode (insn, CCGOCmode)
6431 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6434 switch (get_attr_type (insn))
6437 if (operands[2] == const1_rtx)
6438 return \"inc{b}\\t%0\";
6439 else if (operands[2] == constm1_rtx
6440 || (GET_CODE (operands[2]) == CONST_INT
6441 && INTVAL (operands[2]) == 255))
6442 return \"dec{b}\\t%0\";
6446 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6447 if (GET_CODE (operands[2]) == CONST_INT
6448 && INTVAL (operands[2]) < 0)
6450 operands[2] = GEN_INT (-INTVAL (operands[2]));
6451 return \"sub{b}\\t{%2, %0|%0, %2}\";
6453 return \"add{b}\\t{%2, %0|%0, %2}\";
6457 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6458 (const_string "incdec")
6459 (const_string "alu")))
6460 (set_attr "mode" "QI")])
6462 (define_insn "*addqi_3"
6464 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6465 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6466 (clobber (match_scratch:QI 0 "=q"))]
6467 "ix86_match_ccmode (insn, CCZmode)
6468 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6471 switch (get_attr_type (insn))
6474 if (operands[2] == const1_rtx)
6475 return \"inc{b}\\t%0\";
6476 else if (operands[2] == constm1_rtx
6477 || (GET_CODE (operands[2]) == CONST_INT
6478 && INTVAL (operands[2]) == 255))
6479 return \"dec{b}\\t%0\";
6483 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6484 if (GET_CODE (operands[2]) == CONST_INT
6485 && INTVAL (operands[2]) < 0)
6487 operands[2] = GEN_INT (-INTVAL (operands[2]));
6488 return \"sub{b}\\t{%2, %0|%0, %2}\";
6490 return \"add{b}\\t{%2, %0|%0, %2}\";
6494 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6495 (const_string "incdec")
6496 (const_string "alu")))
6497 (set_attr "mode" "QI")])
6499 ; See comments above addsi_3_imm for details.
6500 (define_insn "*addqi_4"
6502 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6503 (match_operand:QI 2 "const_int_operand" "n")))
6504 (clobber (match_scratch:QI 0 "=qm"))]
6505 "ix86_match_ccmode (insn, CCGCmode)
6506 && (INTVAL (operands[2]) & 0xff) != 0x80"
6509 switch (get_attr_type (insn))
6512 if (operands[2] == constm1_rtx
6513 || (GET_CODE (operands[2]) == CONST_INT
6514 && INTVAL (operands[2]) == 255))
6515 return \"inc{b}\\t%0\";
6516 else if (operands[2] == const1_rtx)
6517 return \"dec{b}\\t%0\";
6522 if (! rtx_equal_p (operands[0], operands[1]))
6524 if (INTVAL (operands[2]) < 0)
6526 operands[2] = GEN_INT (-INTVAL (operands[2]));
6527 return \"add{b}\\t{%2, %0|%0, %2}\";
6529 return \"sub{b}\\t{%2, %0|%0, %2}\";
6533 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6534 (const_string "incdec")
6535 (const_string "alu")))
6536 (set_attr "mode" "QI")])
6539 (define_insn "*addqi_5"
6542 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6543 (match_operand:QI 2 "general_operand" "qmni"))
6545 (clobber (match_scratch:QI 0 "=q"))]
6546 "ix86_match_ccmode (insn, CCGOCmode)
6547 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6550 switch (get_attr_type (insn))
6553 if (operands[2] == const1_rtx)
6554 return \"inc{b}\\t%0\";
6555 else if (operands[2] == constm1_rtx
6556 || (GET_CODE (operands[2]) == CONST_INT
6557 && INTVAL (operands[2]) == 255))
6558 return \"dec{b}\\t%0\";
6562 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6563 if (GET_CODE (operands[2]) == CONST_INT
6564 && INTVAL (operands[2]) < 0)
6566 operands[2] = GEN_INT (-INTVAL (operands[2]));
6567 return \"sub{b}\\t{%2, %0|%0, %2}\";
6569 return \"add{b}\\t{%2, %0|%0, %2}\";
6573 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6574 (const_string "incdec")
6575 (const_string "alu")))
6576 (set_attr "mode" "QI")])
6579 (define_insn "addqi_ext_1"
6580 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6585 (match_operand 1 "ext_register_operand" "0")
6588 (match_operand:QI 2 "general_operand" "qmn")))
6589 (clobber (reg:CC 17))]
6593 switch (get_attr_type (insn))
6596 if (operands[2] == const1_rtx)
6597 return \"inc{b}\\t%h0\";
6598 else if (operands[2] == constm1_rtx
6599 || (GET_CODE (operands[2]) == CONST_INT
6600 && INTVAL (operands[2]) == 255))
6601 return \"dec{b}\\t%h0\";
6605 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6609 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6610 (const_string "incdec")
6611 (const_string "alu")))
6612 (set_attr "mode" "QI")])
6614 (define_insn "*addqi_ext_1_rex64"
6615 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6620 (match_operand 1 "ext_register_operand" "0")
6623 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6624 (clobber (reg:CC 17))]
6628 switch (get_attr_type (insn))
6631 if (operands[2] == const1_rtx)
6632 return \"inc{b}\\t%h0\";
6633 else if (operands[2] == constm1_rtx
6634 || (GET_CODE (operands[2]) == CONST_INT
6635 && INTVAL (operands[2]) == 255))
6636 return \"dec{b}\\t%h0\";
6640 return \"add{b}\\t{%2, %h0|%h0, %2}\";
6644 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6645 (const_string "incdec")
6646 (const_string "alu")))
6647 (set_attr "mode" "QI")])
6649 (define_insn "*addqi_ext_2"
6650 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6655 (match_operand 1 "ext_register_operand" "%0")
6659 (match_operand 2 "ext_register_operand" "Q")
6662 (clobber (reg:CC 17))]
6664 "add{b}\\t{%h2, %h0|%h0, %h2}"
6665 [(set_attr "type" "alu")
6666 (set_attr "mode" "QI")])
6668 ;; The patterns that match these are at the end of this file.
6670 (define_expand "addxf3"
6671 [(set (match_operand:XF 0 "register_operand" "")
6672 (plus:XF (match_operand:XF 1 "register_operand" "")
6673 (match_operand:XF 2 "register_operand" "")))]
6674 "TARGET_80387 && !TARGET_64BIT"
6677 (define_expand "addtf3"
6678 [(set (match_operand:TF 0 "register_operand" "")
6679 (plus:TF (match_operand:TF 1 "register_operand" "")
6680 (match_operand:TF 2 "register_operand" "")))]
6684 (define_expand "adddf3"
6685 [(set (match_operand:DF 0 "register_operand" "")
6686 (plus:DF (match_operand:DF 1 "register_operand" "")
6687 (match_operand:DF 2 "nonimmediate_operand" "")))]
6688 "TARGET_80387 || TARGET_SSE2"
6691 (define_expand "addsf3"
6692 [(set (match_operand:SF 0 "register_operand" "")
6693 (plus:SF (match_operand:SF 1 "register_operand" "")
6694 (match_operand:SF 2 "nonimmediate_operand" "")))]
6695 "TARGET_80387 || TARGET_SSE"
6698 ;; Subtract instructions
6700 ;; %%% splits for subsidi3
6702 (define_expand "subdi3"
6703 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6704 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6705 (match_operand:DI 2 "x86_64_general_operand" "")))
6706 (clobber (reg:CC 17))])]
6708 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6710 (define_insn "*subdi3_1"
6711 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6712 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6713 (match_operand:DI 2 "general_operand" "roiF,riF")))
6714 (clobber (reg:CC 17))]
6719 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6720 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6721 (match_operand:DI 2 "general_operand" "")))
6722 (clobber (reg:CC 17))]
6723 "reload_completed && !TARGET_64BIT"
6724 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6725 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6726 (parallel [(set (match_dup 3)
6727 (minus:SI (match_dup 4)
6728 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6730 (clobber (reg:CC 17))])]
6731 "split_di (operands+0, 1, operands+0, operands+3);
6732 split_di (operands+1, 1, operands+1, operands+4);
6733 split_di (operands+2, 1, operands+2, operands+5);")
6735 (define_insn "subdi3_carry_rex64"
6736 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6737 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6738 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6739 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6740 (clobber (reg:CC 17))]
6741 "ix86_binary_operator_ok (MINUS, DImode, operands)"
6742 "sbb{q}\\t{%2, %0|%0, %2}"
6743 [(set_attr "type" "alu")
6744 (set_attr "pent_pair" "pu")
6745 (set_attr "ppro_uops" "few")
6746 (set_attr "mode" "DI")])
6748 (define_insn "*subdi_1_rex64"
6749 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6750 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6751 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6752 (clobber (reg:CC 17))]
6753 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6754 "sub{q}\\t{%2, %0|%0, %2}"
6755 [(set_attr "type" "alu")
6756 (set_attr "mode" "DI")])
6758 (define_insn "*subdi_2_rex64"
6761 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6762 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6764 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6765 (minus:DI (match_dup 1) (match_dup 2)))]
6766 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6767 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6768 "sub{q}\\t{%2, %0|%0, %2}"
6769 [(set_attr "type" "alu")
6770 (set_attr "mode" "DI")])
6772 (define_insn "*subdi_3_rex63"
6774 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6775 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6776 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6777 (minus:DI (match_dup 1) (match_dup 2)))]
6778 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6779 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6780 "sub{q}\\t{%2, %0|%0, %2}"
6781 [(set_attr "type" "alu")
6782 (set_attr "mode" "DI")])
6785 (define_insn "subsi3_carry"
6786 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6787 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6788 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6789 (match_operand:SI 2 "general_operand" "ri,rm"))))
6790 (clobber (reg:CC 17))]
6791 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6792 "sbb{l}\\t{%2, %0|%0, %2}"
6793 [(set_attr "type" "alu")
6794 (set_attr "pent_pair" "pu")
6795 (set_attr "ppro_uops" "few")
6796 (set_attr "mode" "SI")])
6798 (define_insn "subsi3_carry_zext"
6799 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6801 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6802 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6803 (match_operand:SI 2 "general_operand" "ri,rm")))))
6804 (clobber (reg:CC 17))]
6805 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6806 "sbb{l}\\t{%2, %k0|%k0, %2}"
6807 [(set_attr "type" "alu")
6808 (set_attr "pent_pair" "pu")
6809 (set_attr "ppro_uops" "few")
6810 (set_attr "mode" "SI")])
6812 (define_expand "subsi3"
6813 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6814 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6815 (match_operand:SI 2 "general_operand" "")))
6816 (clobber (reg:CC 17))])]
6818 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6820 (define_insn "*subsi_1"
6821 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6822 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6823 (match_operand:SI 2 "general_operand" "ri,rm")))
6824 (clobber (reg:CC 17))]
6825 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6826 "sub{l}\\t{%2, %0|%0, %2}"
6827 [(set_attr "type" "alu")
6828 (set_attr "mode" "SI")])
6830 (define_insn "*subsi_1_zext"
6831 [(set (match_operand:DI 0 "register_operand" "=r")
6833 (minus:SI (match_operand:SI 1 "register_operand" "0")
6834 (match_operand:SI 2 "general_operand" "rim"))))
6835 (clobber (reg:CC 17))]
6836 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6837 "sub{l}\\t{%2, %k0|%k0, %2}"
6838 [(set_attr "type" "alu")
6839 (set_attr "mode" "SI")])
6841 (define_insn "*subsi_2"
6844 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6845 (match_operand:SI 2 "general_operand" "ri,rm"))
6847 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6848 (minus:SI (match_dup 1) (match_dup 2)))]
6849 "ix86_match_ccmode (insn, CCGOCmode)
6850 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6851 "sub{l}\\t{%2, %0|%0, %2}"
6852 [(set_attr "type" "alu")
6853 (set_attr "mode" "SI")])
6855 (define_insn "*subsi_2_zext"
6858 (minus:SI (match_operand:SI 1 "register_operand" "0")
6859 (match_operand:SI 2 "general_operand" "rim"))
6861 (set (match_operand:DI 0 "register_operand" "=r")
6863 (minus:SI (match_dup 1)
6865 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6866 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6867 "sub{l}\\t{%2, %k0|%k0, %2}"
6868 [(set_attr "type" "alu")
6869 (set_attr "mode" "SI")])
6871 (define_insn "*subsi_3"
6873 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6874 (match_operand:SI 2 "general_operand" "ri,rm")))
6875 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6876 (minus:SI (match_dup 1) (match_dup 2)))]
6877 "ix86_match_ccmode (insn, CCmode)
6878 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6879 "sub{l}\\t{%2, %0|%0, %2}"
6880 [(set_attr "type" "alu")
6881 (set_attr "mode" "SI")])
6883 (define_insn "*subsi_3_zext"
6885 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6886 (match_operand:SI 2 "general_operand" "rim")))
6887 (set (match_operand:DI 0 "register_operand" "=r")
6889 (minus:SI (match_dup 1)
6891 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6892 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6893 "sub{q}\\t{%2, %0|%0, %2}"
6894 [(set_attr "type" "alu")
6895 (set_attr "mode" "DI")])
6897 (define_expand "subhi3"
6898 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6899 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6900 (match_operand:HI 2 "general_operand" "")))
6901 (clobber (reg:CC 17))])]
6902 "TARGET_HIMODE_MATH"
6903 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6905 (define_insn "*subhi_1"
6906 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6907 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6908 (match_operand:HI 2 "general_operand" "ri,rm")))
6909 (clobber (reg:CC 17))]
6910 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6911 "sub{w}\\t{%2, %0|%0, %2}"
6912 [(set_attr "type" "alu")
6913 (set_attr "mode" "HI")])
6915 (define_insn "*subhi_2"
6918 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6919 (match_operand:HI 2 "general_operand" "ri,rm"))
6921 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6922 (minus:HI (match_dup 1) (match_dup 2)))]
6923 "ix86_match_ccmode (insn, CCGOCmode)
6924 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6925 "sub{w}\\t{%2, %0|%0, %2}"
6926 [(set_attr "type" "alu")
6927 (set_attr "mode" "HI")])
6929 (define_insn "*subhi_3"
6931 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6932 (match_operand:HI 2 "general_operand" "ri,rm")))
6933 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6934 (minus:HI (match_dup 1) (match_dup 2)))]
6935 "ix86_match_ccmode (insn, CCmode)
6936 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6937 "sub{w}\\t{%2, %0|%0, %2}"
6938 [(set_attr "type" "alu")
6939 (set_attr "mode" "HI")])
6941 (define_expand "subqi3"
6942 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6943 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6944 (match_operand:QI 2 "general_operand" "")))
6945 (clobber (reg:CC 17))])]
6946 "TARGET_QIMODE_MATH"
6947 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6949 (define_insn "*subqi_1"
6950 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6951 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6952 (match_operand:QI 2 "general_operand" "qn,qmn")))
6953 (clobber (reg:CC 17))]
6954 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6955 "sub{b}\\t{%2, %0|%0, %2}"
6956 [(set_attr "type" "alu")
6957 (set_attr "mode" "QI")])
6959 (define_insn "*subqi_2"
6962 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6963 (match_operand:QI 2 "general_operand" "qi,qm"))
6965 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6966 (minus:HI (match_dup 1) (match_dup 2)))]
6967 "ix86_match_ccmode (insn, CCGOCmode)
6968 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6969 "sub{b}\\t{%2, %0|%0, %2}"
6970 [(set_attr "type" "alu")
6971 (set_attr "mode" "QI")])
6973 (define_insn "*subqi_3"
6975 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6976 (match_operand:QI 2 "general_operand" "qi,qm")))
6977 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6978 (minus:HI (match_dup 1) (match_dup 2)))]
6979 "ix86_match_ccmode (insn, CCmode)
6980 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6981 "sub{b}\\t{%2, %0|%0, %2}"
6982 [(set_attr "type" "alu")
6983 (set_attr "mode" "QI")])
6985 ;; The patterns that match these are at the end of this file.
6987 (define_expand "subxf3"
6988 [(set (match_operand:XF 0 "register_operand" "")
6989 (minus:XF (match_operand:XF 1 "register_operand" "")
6990 (match_operand:XF 2 "register_operand" "")))]
6991 "TARGET_80387 && !TARGET_64BIT"
6994 (define_expand "subtf3"
6995 [(set (match_operand:TF 0 "register_operand" "")
6996 (minus:TF (match_operand:TF 1 "register_operand" "")
6997 (match_operand:TF 2 "register_operand" "")))]
7001 (define_expand "subdf3"
7002 [(set (match_operand:DF 0 "register_operand" "")
7003 (minus:DF (match_operand:DF 1 "register_operand" "")
7004 (match_operand:DF 2 "nonimmediate_operand" "")))]
7005 "TARGET_80387 || TARGET_SSE2"
7008 (define_expand "subsf3"
7009 [(set (match_operand:SF 0 "register_operand" "")
7010 (minus:SF (match_operand:SF 1 "register_operand" "")
7011 (match_operand:SF 2 "nonimmediate_operand" "")))]
7012 "TARGET_80387 || TARGET_SSE"
7015 ;; Multiply instructions
7017 (define_expand "muldi3"
7018 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7019 (mult:DI (match_operand:DI 1 "register_operand" "")
7020 (match_operand:DI 2 "x86_64_general_operand" "")))
7021 (clobber (reg:CC 17))])]
7025 (define_insn "*muldi3_1_rex64"
7026 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7027 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
7028 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7029 (clobber (reg:CC 17))]
7030 "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
7033 imul{q}\\t{%2, %1, %0|%0, %1, %2}
7034 imul{q}\\t{%2, %1, %0|%0, %1, %2}
7035 imul{q}\\t{%2, %0|%0, %2}"
7036 [(set_attr "type" "imul")
7037 (set_attr "prefix_0f" "0,0,1")
7038 (set_attr "mode" "DI")])
7040 (define_expand "mulsi3"
7041 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7042 (mult:SI (match_operand:SI 1 "register_operand" "")
7043 (match_operand:SI 2 "general_operand" "")))
7044 (clobber (reg:CC 17))])]
7048 (define_insn "*mulsi3_1"
7049 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7050 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7051 (match_operand:SI 2 "general_operand" "K,i,mr")))
7052 (clobber (reg:CC 17))]
7053 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7054 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7055 ; there are two ways of writing the exact same machine instruction
7056 ; in assembly language. One, for example, is:
7060 ; while the other is:
7062 ; imul $12, %eax, %eax
7064 ; The first is simply short-hand for the latter. But, some assemblers,
7065 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7067 imul{l}\\t{%2, %1, %0|%0, %1, %2}
7068 imul{l}\\t{%2, %1, %0|%0, %1, %2}
7069 imul{l}\\t{%2, %0|%0, %2}"
7070 [(set_attr "type" "imul")
7071 (set_attr "prefix_0f" "0,0,1")
7072 (set_attr "mode" "SI")])
7074 (define_insn "*mulsi3_1_zext"
7075 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7077 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
7078 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7079 (clobber (reg:CC 17))]
7081 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7082 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
7083 ; there are two ways of writing the exact same machine instruction
7084 ; in assembly language. One, for example, is:
7088 ; while the other is:
7090 ; imul $12, %eax, %eax
7092 ; The first is simply short-hand for the latter. But, some assemblers,
7093 ; like the SCO OSR5 COFF assembler, don't handle the first form.
7095 imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
7096 imul{l}\\t{%2, %1, %k0|%k0, %1, %2}
7097 imul{l}\\t{%2, %k0|%k0, %2}"
7098 [(set_attr "type" "imul")
7099 (set_attr "prefix_0f" "0,0,1")
7100 (set_attr "mode" "SI")])
7102 (define_expand "mulhi3"
7103 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7104 (mult:HI (match_operand:HI 1 "register_operand" "")
7105 (match_operand:HI 2 "general_operand" "")))
7106 (clobber (reg:CC 17))])]
7107 "TARGET_HIMODE_MATH"
7110 (define_insn "*mulhi3_1"
7111 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7112 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
7113 (match_operand:HI 2 "general_operand" "K,i,mr")))
7114 (clobber (reg:CC 17))]
7115 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7116 ; %%% There was a note about "Assembler has weird restrictions",
7117 ; concerning alternative 1 when op1 == op0. True?
7119 imul{w}\\t{%2, %1, %0|%0, %1, %2}
7120 imul{w}\\t{%2, %1, %0|%0, %1, %2}
7121 imul{w}\\t{%2, %0|%0, %2}"
7122 [(set_attr "type" "imul")
7123 (set_attr "prefix_0f" "0,0,1")
7124 (set_attr "mode" "HI")])
7126 (define_insn "mulqi3"
7127 [(set (match_operand:QI 0 "register_operand" "=a")
7128 (mult:QI (match_operand:QI 1 "register_operand" "%0")
7129 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7130 (clobber (reg:CC 17))]
7131 "TARGET_QIMODE_MATH"
7133 [(set_attr "type" "imul")
7134 (set_attr "length_immediate" "0")
7135 (set_attr "mode" "QI")])
7137 (define_insn "umulqihi3"
7138 [(set (match_operand:HI 0 "register_operand" "=a")
7139 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7140 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7141 (clobber (reg:CC 17))]
7142 "TARGET_QIMODE_MATH"
7144 [(set_attr "type" "imul")
7145 (set_attr "length_immediate" "0")
7146 (set_attr "mode" "QI")])
7148 (define_insn "mulqihi3"
7149 [(set (match_operand:HI 0 "register_operand" "=a")
7150 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
7151 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7152 (clobber (reg:CC 17))]
7153 "TARGET_QIMODE_MATH"
7155 [(set_attr "type" "imul")
7156 (set_attr "length_immediate" "0")
7157 (set_attr "mode" "QI")])
7159 (define_insn "umulditi3"
7160 [(set (match_operand:TI 0 "register_operand" "=A")
7161 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7162 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7163 (clobber (reg:CC 17))]
7166 [(set_attr "type" "imul")
7167 (set_attr "ppro_uops" "few")
7168 (set_attr "length_immediate" "0")
7169 (set_attr "mode" "DI")])
7171 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7172 (define_insn "umulsidi3"
7173 [(set (match_operand:DI 0 "register_operand" "=A")
7174 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7175 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7176 (clobber (reg:CC 17))]
7179 [(set_attr "type" "imul")
7180 (set_attr "ppro_uops" "few")
7181 (set_attr "length_immediate" "0")
7182 (set_attr "mode" "SI")])
7184 (define_insn "mulditi3"
7185 [(set (match_operand:TI 0 "register_operand" "=A")
7186 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0"))
7187 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7188 (clobber (reg:CC 17))]
7191 [(set_attr "type" "imul")
7192 (set_attr "length_immediate" "0")
7193 (set_attr "mode" "DI")])
7195 (define_insn "mulsidi3"
7196 [(set (match_operand:DI 0 "register_operand" "=A")
7197 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
7198 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7199 (clobber (reg:CC 17))]
7202 [(set_attr "type" "imul")
7203 (set_attr "length_immediate" "0")
7204 (set_attr "mode" "SI")])
7206 (define_insn "*umuldi3_highpart_rex64"
7207 [(set (match_operand:DI 0 "register_operand" "=d")
7210 (mult:TI (zero_extend:TI
7211 (match_operand:DI 1 "register_operand" "%a"))
7213 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7215 (clobber (match_scratch:DI 3 "=a"))
7216 (clobber (reg:CC 17))]
7219 [(set_attr "type" "imul")
7220 (set_attr "ppro_uops" "few")
7221 (set_attr "length_immediate" "0")
7222 (set_attr "mode" "DI")])
7224 (define_insn "umulsi3_highpart"
7225 [(set (match_operand:SI 0 "register_operand" "=d")
7228 (mult:DI (zero_extend:DI
7229 (match_operand:SI 1 "register_operand" "%a"))
7231 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7233 (clobber (match_scratch:SI 3 "=a"))
7234 (clobber (reg:CC 17))]
7237 [(set_attr "type" "imul")
7238 (set_attr "ppro_uops" "few")
7239 (set_attr "length_immediate" "0")
7240 (set_attr "mode" "SI")])
7242 (define_insn "*umulsi3_highpart_zext"
7243 [(set (match_operand:DI 0 "register_operand" "=d")
7244 (zero_extend:DI (truncate:SI
7246 (mult:DI (zero_extend:DI
7247 (match_operand:SI 1 "register_operand" "%a"))
7249 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7251 (clobber (match_scratch:SI 3 "=a"))
7252 (clobber (reg:CC 17))]
7255 [(set_attr "type" "imul")
7256 (set_attr "ppro_uops" "few")
7257 (set_attr "length_immediate" "0")
7258 (set_attr "mode" "SI")])
7260 (define_insn "*smuldi3_highpart_rex64"
7261 [(set (match_operand:DI 0 "register_operand" "=d")
7264 (mult:TI (sign_extend:TI
7265 (match_operand:DI 1 "register_operand" "%a"))
7267 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7269 (clobber (match_scratch:DI 3 "=a"))
7270 (clobber (reg:CC 17))]
7273 [(set_attr "type" "imul")
7274 (set_attr "ppro_uops" "few")
7275 (set_attr "mode" "DI")])
7277 (define_insn "smulsi3_highpart"
7278 [(set (match_operand:SI 0 "register_operand" "=d")
7281 (mult:DI (sign_extend:DI
7282 (match_operand:SI 1 "register_operand" "%a"))
7284 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7286 (clobber (match_scratch:SI 3 "=a"))
7287 (clobber (reg:CC 17))]
7290 [(set_attr "type" "imul")
7291 (set_attr "ppro_uops" "few")
7292 (set_attr "mode" "SI")])
7294 (define_insn "*smulsi3_highpart_zext"
7295 [(set (match_operand:DI 0 "register_operand" "=d")
7296 (zero_extend:DI (truncate:SI
7298 (mult:DI (sign_extend:DI
7299 (match_operand:SI 1 "register_operand" "%a"))
7301 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7303 (clobber (match_scratch:SI 3 "=a"))
7304 (clobber (reg:CC 17))]
7307 [(set_attr "type" "imul")
7308 (set_attr "ppro_uops" "few")
7309 (set_attr "mode" "SI")])
7311 ;; The patterns that match these are at the end of this file.
7313 (define_expand "mulxf3"
7314 [(set (match_operand:XF 0 "register_operand" "")
7315 (mult:XF (match_operand:XF 1 "register_operand" "")
7316 (match_operand:XF 2 "register_operand" "")))]
7317 "TARGET_80387 && !TARGET_64BIT"
7320 (define_expand "multf3"
7321 [(set (match_operand:TF 0 "register_operand" "")
7322 (mult:TF (match_operand:TF 1 "register_operand" "")
7323 (match_operand:TF 2 "register_operand" "")))]
7327 (define_expand "muldf3"
7328 [(set (match_operand:DF 0 "register_operand" "")
7329 (mult:DF (match_operand:DF 1 "register_operand" "")
7330 (match_operand:DF 2 "nonimmediate_operand" "")))]
7331 "TARGET_80387 || TARGET_SSE2"
7334 (define_expand "mulsf3"
7335 [(set (match_operand:SF 0 "register_operand" "")
7336 (mult:SF (match_operand:SF 1 "register_operand" "")
7337 (match_operand:SF 2 "nonimmediate_operand" "")))]
7338 "TARGET_80387 || TARGET_SSE"
7341 ;; Divide instructions
7343 (define_insn "divqi3"
7344 [(set (match_operand:QI 0 "register_operand" "=a")
7345 (div:QI (match_operand:HI 1 "register_operand" "0")
7346 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7347 (clobber (reg:CC 17))]
7348 "TARGET_QIMODE_MATH"
7350 [(set_attr "type" "idiv")
7351 (set_attr "mode" "QI")
7352 (set_attr "ppro_uops" "few")])
7354 (define_insn "udivqi3"
7355 [(set (match_operand:QI 0 "register_operand" "=a")
7356 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7357 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7358 (clobber (reg:CC 17))]
7359 "TARGET_QIMODE_MATH"
7361 [(set_attr "type" "idiv")
7362 (set_attr "mode" "QI")
7363 (set_attr "ppro_uops" "few")])
7365 ;; The patterns that match these are at the end of this file.
7367 (define_expand "divxf3"
7368 [(set (match_operand:XF 0 "register_operand" "")
7369 (div:XF (match_operand:XF 1 "register_operand" "")
7370 (match_operand:XF 2 "register_operand" "")))]
7371 "TARGET_80387 && !TARGET_64BIT"
7374 (define_expand "divtf3"
7375 [(set (match_operand:TF 0 "register_operand" "")
7376 (div:TF (match_operand:TF 1 "register_operand" "")
7377 (match_operand:TF 2 "register_operand" "")))]
7381 (define_expand "divdf3"
7382 [(set (match_operand:DF 0 "register_operand" "")
7383 (div:DF (match_operand:DF 1 "register_operand" "")
7384 (match_operand:DF 2 "nonimmediate_operand" "")))]
7385 "TARGET_80387 || TARGET_SSE2"
7388 (define_expand "divsf3"
7389 [(set (match_operand:SF 0 "register_operand" "")
7390 (div:SF (match_operand:SF 1 "register_operand" "")
7391 (match_operand:SF 2 "nonimmediate_operand" "")))]
7392 "TARGET_80387 || TARGET_SSE"
7395 ;; Remainder instructions.
7397 (define_expand "divmoddi4"
7398 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7399 (div:DI (match_operand:DI 1 "register_operand" "")
7400 (match_operand:DI 2 "nonimmediate_operand" "")))
7401 (set (match_operand:DI 3 "register_operand" "")
7402 (mod:DI (match_dup 1) (match_dup 2)))
7403 (clobber (reg:CC 17))])]
7407 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7408 ;; Penalize eax case sligthly because it results in worse scheduling
7410 (define_insn "*divmoddi4_nocltd_rex64"
7411 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7412 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7413 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7414 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7415 (mod:DI (match_dup 2) (match_dup 3)))
7416 (clobber (reg:CC 17))]
7417 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7419 [(set_attr "type" "multi")])
7421 (define_insn "*divmoddi4_cltd_rex64"
7422 [(set (match_operand:DI 0 "register_operand" "=a")
7423 (div:DI (match_operand:DI 2 "register_operand" "a")
7424 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7425 (set (match_operand:DI 1 "register_operand" "=&d")
7426 (mod:DI (match_dup 2) (match_dup 3)))
7427 (clobber (reg:CC 17))]
7428 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7430 [(set_attr "type" "multi")])
7432 (define_insn "*divmoddi_noext_rex64"
7433 [(set (match_operand:DI 0 "register_operand" "=a")
7434 (div:DI (match_operand:DI 1 "register_operand" "0")
7435 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7436 (set (match_operand:DI 3 "register_operand" "=d")
7437 (mod:DI (match_dup 1) (match_dup 2)))
7438 (use (match_operand:DI 4 "register_operand" "3"))
7439 (clobber (reg:CC 17))]
7442 [(set_attr "type" "idiv")
7443 (set_attr "mode" "DI")
7444 (set_attr "ppro_uops" "few")])
7447 [(set (match_operand:DI 0 "register_operand" "")
7448 (div:DI (match_operand:DI 1 "register_operand" "")
7449 (match_operand:DI 2 "nonimmediate_operand" "")))
7450 (set (match_operand:DI 3 "register_operand" "")
7451 (mod:DI (match_dup 1) (match_dup 2)))
7452 (clobber (reg:CC 17))]
7453 "TARGET_64BIT && reload_completed"
7454 [(parallel [(set (match_dup 3)
7455 (ashiftrt:DI (match_dup 4) (const_int 63)))
7456 (clobber (reg:CC 17))])
7457 (parallel [(set (match_dup 0)
7458 (div:DI (reg:DI 0) (match_dup 2)))
7460 (mod:DI (reg:DI 0) (match_dup 2)))
7462 (clobber (reg:CC 17))])]
7465 /* Avoid use of cltd in favour of a mov+shift. */
7466 if (!TARGET_USE_CLTD && !optimize_size)
7468 if (true_regnum (operands[1]))
7469 emit_move_insn (operands[0], operands[1]);
7471 emit_move_insn (operands[3], operands[1]);
7472 operands[4] = operands[3];
7476 if (true_regnum (operands[1]))
7478 operands[4] = operands[1];
7483 (define_expand "divmodsi4"
7484 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7485 (div:SI (match_operand:SI 1 "register_operand" "")
7486 (match_operand:SI 2 "nonimmediate_operand" "")))
7487 (set (match_operand:SI 3 "register_operand" "")
7488 (mod:SI (match_dup 1) (match_dup 2)))
7489 (clobber (reg:CC 17))])]
7493 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7494 ;; Penalize eax case sligthly because it results in worse scheduling
7496 (define_insn "*divmodsi4_nocltd"
7497 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7498 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7499 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7500 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7501 (mod:SI (match_dup 2) (match_dup 3)))
7502 (clobber (reg:CC 17))]
7503 "!optimize_size && !TARGET_USE_CLTD"
7505 [(set_attr "type" "multi")])
7507 (define_insn "*divmodsi4_cltd"
7508 [(set (match_operand:SI 0 "register_operand" "=a")
7509 (div:SI (match_operand:SI 2 "register_operand" "a")
7510 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7511 (set (match_operand:SI 1 "register_operand" "=&d")
7512 (mod:SI (match_dup 2) (match_dup 3)))
7513 (clobber (reg:CC 17))]
7514 "optimize_size || TARGET_USE_CLTD"
7516 [(set_attr "type" "multi")])
7518 (define_insn "*divmodsi_noext"
7519 [(set (match_operand:SI 0 "register_operand" "=a")
7520 (div:SI (match_operand:SI 1 "register_operand" "0")
7521 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7522 (set (match_operand:SI 3 "register_operand" "=d")
7523 (mod:SI (match_dup 1) (match_dup 2)))
7524 (use (match_operand:SI 4 "register_operand" "3"))
7525 (clobber (reg:CC 17))]
7528 [(set_attr "type" "idiv")
7529 (set_attr "mode" "SI")
7530 (set_attr "ppro_uops" "few")])
7533 [(set (match_operand:SI 0 "register_operand" "")
7534 (div:SI (match_operand:SI 1 "register_operand" "")
7535 (match_operand:SI 2 "nonimmediate_operand" "")))
7536 (set (match_operand:SI 3 "register_operand" "")
7537 (mod:SI (match_dup 1) (match_dup 2)))
7538 (clobber (reg:CC 17))]
7540 [(parallel [(set (match_dup 3)
7541 (ashiftrt:SI (match_dup 4) (const_int 31)))
7542 (clobber (reg:CC 17))])
7543 (parallel [(set (match_dup 0)
7544 (div:SI (reg:SI 0) (match_dup 2)))
7546 (mod:SI (reg:SI 0) (match_dup 2)))
7548 (clobber (reg:CC 17))])]
7551 /* Avoid use of cltd in favour of a mov+shift. */
7552 if (!TARGET_USE_CLTD && !optimize_size)
7554 if (true_regnum (operands[1]))
7555 emit_move_insn (operands[0], operands[1]);
7557 emit_move_insn (operands[3], operands[1]);
7558 operands[4] = operands[3];
7562 if (true_regnum (operands[1]))
7564 operands[4] = operands[1];
7568 (define_insn "divmodhi4"
7569 [(set (match_operand:HI 0 "register_operand" "=a")
7570 (div:HI (match_operand:HI 1 "register_operand" "0")
7571 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7572 (set (match_operand:HI 3 "register_operand" "=&d")
7573 (mod:HI (match_dup 1) (match_dup 2)))
7574 (clobber (reg:CC 17))]
7575 "TARGET_HIMODE_MATH"
7576 "cwtd\;idiv{w}\\t%2"
7577 [(set_attr "type" "multi")
7578 (set_attr "length_immediate" "0")
7579 (set_attr "mode" "SI")])
7581 (define_insn "udivmoddi4"
7582 [(set (match_operand:DI 0 "register_operand" "=a")
7583 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7584 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7585 (set (match_operand:DI 3 "register_operand" "=&d")
7586 (umod:DI (match_dup 1) (match_dup 2)))
7587 (clobber (reg:CC 17))]
7589 "xor{q}\\t%3, %3\;div{q}\\t%2"
7590 [(set_attr "type" "multi")
7591 (set_attr "length_immediate" "0")
7592 (set_attr "mode" "DI")])
7594 (define_insn "*udivmoddi4_noext"
7595 [(set (match_operand:DI 0 "register_operand" "=a")
7596 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7597 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7598 (set (match_operand:DI 3 "register_operand" "=d")
7599 (umod:DI (match_dup 1) (match_dup 2)))
7601 (clobber (reg:CC 17))]
7604 [(set_attr "type" "idiv")
7605 (set_attr "ppro_uops" "few")
7606 (set_attr "mode" "DI")])
7609 [(set (match_operand:DI 0 "register_operand" "")
7610 (udiv:DI (match_operand:DI 1 "register_operand" "")
7611 (match_operand:DI 2 "nonimmediate_operand" "")))
7612 (set (match_operand:DI 3 "register_operand" "")
7613 (umod:DI (match_dup 1) (match_dup 2)))
7614 (clobber (reg:CC 17))]
7615 "reload_completed && TARGET_64BIT"
7616 [(set (match_dup 3) (const_int 0))
7617 (parallel [(set (match_dup 0)
7618 (udiv:DI (match_dup 1) (match_dup 2)))
7620 (umod:DI (match_dup 1) (match_dup 2)))
7622 (clobber (reg:CC 17))])]
7625 (define_insn "udivmodsi4"
7626 [(set (match_operand:SI 0 "register_operand" "=a")
7627 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7628 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7629 (set (match_operand:SI 3 "register_operand" "=&d")
7630 (umod:SI (match_dup 1) (match_dup 2)))
7631 (clobber (reg:CC 17))]
7633 "xor{l}\\t%3, %3\;div{l}\\t%2"
7634 [(set_attr "type" "multi")
7635 (set_attr "length_immediate" "0")
7636 (set_attr "mode" "SI")])
7638 (define_insn "*udivmodsi4_noext"
7639 [(set (match_operand:SI 0 "register_operand" "=a")
7640 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7641 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7642 (set (match_operand:SI 3 "register_operand" "=d")
7643 (umod:SI (match_dup 1) (match_dup 2)))
7645 (clobber (reg:CC 17))]
7648 [(set_attr "type" "idiv")
7649 (set_attr "ppro_uops" "few")
7650 (set_attr "mode" "SI")])
7653 [(set (match_operand:SI 0 "register_operand" "")
7654 (udiv:SI (match_operand:SI 1 "register_operand" "")
7655 (match_operand:SI 2 "nonimmediate_operand" "")))
7656 (set (match_operand:SI 3 "register_operand" "")
7657 (umod:SI (match_dup 1) (match_dup 2)))
7658 (clobber (reg:CC 17))]
7660 [(set (match_dup 3) (const_int 0))
7661 (parallel [(set (match_dup 0)
7662 (udiv:SI (match_dup 1) (match_dup 2)))
7664 (umod:SI (match_dup 1) (match_dup 2)))
7666 (clobber (reg:CC 17))])]
7669 (define_expand "udivmodhi4"
7670 [(set (match_dup 4) (const_int 0))
7671 (parallel [(set (match_operand:HI 0 "register_operand" "")
7672 (udiv:HI (match_operand:HI 1 "register_operand" "")
7673 (match_operand:HI 2 "nonimmediate_operand" "")))
7674 (set (match_operand:HI 3 "register_operand" "")
7675 (umod:HI (match_dup 1) (match_dup 2)))
7677 (clobber (reg:CC 17))])]
7678 "TARGET_HIMODE_MATH"
7679 "operands[4] = gen_reg_rtx (HImode);")
7681 (define_insn "*udivmodhi_noext"
7682 [(set (match_operand:HI 0 "register_operand" "=a")
7683 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7684 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7685 (set (match_operand:HI 3 "register_operand" "=d")
7686 (umod:HI (match_dup 1) (match_dup 2)))
7687 (use (match_operand:HI 4 "register_operand" "3"))
7688 (clobber (reg:CC 17))]
7691 [(set_attr "type" "idiv")
7692 (set_attr "mode" "HI")
7693 (set_attr "ppro_uops" "few")])
7695 ;; We can not use div/idiv for double division, because it causes
7696 ;; "division by zero" on the overflow and that's not what we expect
7697 ;; from truncate. Because true (non truncating) double division is
7698 ;; never generated, we can't create this insn anyway.
7701 ; [(set (match_operand:SI 0 "register_operand" "=a")
7703 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7705 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7706 ; (set (match_operand:SI 3 "register_operand" "=d")
7708 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7709 ; (clobber (reg:CC 17))]
7711 ; "div{l}\\t{%2, %0|%0, %2}"
7712 ; [(set_attr "type" "idiv")
7713 ; (set_attr "ppro_uops" "few")])
7715 ;;- Logical AND instructions
7717 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7718 ;; Note that this excludes ah.
7720 (define_insn "*testdi_1_rex64"
7723 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7724 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7726 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7728 test{l}\\t{%k1, %k0|%k0, %k1}
7729 test{l}\\t{%k1, %k0|%k0, %k1}
7730 test{q}\\t{%1, %0|%0, %1}
7731 test{q}\\t{%1, %0|%0, %1}
7732 test{q}\\t{%1, %0|%0, %1}"
7733 [(set_attr "type" "test")
7734 (set_attr "modrm" "0,1,0,1,1")
7735 (set_attr "mode" "SI,SI,DI,DI,DI")
7736 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7738 (define_insn "testsi_1"
7741 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7742 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7744 "ix86_match_ccmode (insn, CCNOmode)"
7745 "test{l}\\t{%1, %0|%0, %1}"
7746 [(set_attr "type" "test")
7747 (set_attr "modrm" "0,1,1")
7748 (set_attr "mode" "SI")
7749 (set_attr "pent_pair" "uv,np,uv")])
7751 (define_expand "testsi_ccno_1"
7754 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7755 (match_operand:SI 1 "nonmemory_operand" ""))
7760 (define_insn "*testhi_1"
7762 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7763 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7765 "ix86_match_ccmode (insn, CCNOmode)"
7766 "test{w}\\t{%1, %0|%0, %1}"
7767 [(set_attr "type" "test")
7768 (set_attr "modrm" "0,1,1")
7769 (set_attr "mode" "HI")
7770 (set_attr "pent_pair" "uv,np,uv")])
7772 (define_expand "testqi_ccz_1"
7774 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7775 (match_operand:QI 1 "nonmemory_operand" ""))
7780 (define_insn "*testqi_1"
7782 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7783 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7785 "ix86_match_ccmode (insn, CCNOmode)"
7788 if (which_alternative == 3)
7790 if (GET_CODE (operands[1]) == CONST_INT
7791 && (INTVAL (operands[1]) & 0xffffff00))
7792 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7793 return \"test{l}\\t{%1, %k0|%k0, %1}\";
7795 return \"test{b}\\t{%1, %0|%0, %1}\";
7797 [(set_attr "type" "test")
7798 (set_attr "modrm" "0,1,1,1")
7799 (set_attr "mode" "QI,QI,QI,SI")
7800 (set_attr "pent_pair" "uv,np,uv,np")])
7802 (define_expand "testqi_ext_ccno_0"
7807 (match_operand 0 "ext_register_operand" "")
7810 (match_operand 1 "const_int_operand" ""))
7815 (define_insn "*testqi_ext_0"
7820 (match_operand 0 "ext_register_operand" "Q")
7823 (match_operand 1 "const_int_operand" "n"))
7825 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
7826 && ix86_match_ccmode (insn, CCNOmode)"
7827 "test{b}\\t{%1, %h0|%h0, %1}"
7828 [(set_attr "type" "test")
7829 (set_attr "mode" "QI")
7830 (set_attr "length_immediate" "1")
7831 (set_attr "pent_pair" "np")])
7833 (define_insn "*testqi_ext_1"
7838 (match_operand 0 "ext_register_operand" "Q")
7842 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
7844 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7845 "test{b}\\t{%1, %h0|%h0, %1}"
7846 [(set_attr "type" "test")
7847 (set_attr "mode" "QI")])
7849 (define_insn "*testqi_ext_1_rex64"
7854 (match_operand 0 "ext_register_operand" "Q")
7858 (match_operand:QI 1 "ext_register_operand" "Q")))
7860 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7861 "test{b}\\t{%1, %h0|%h0, %1}"
7862 [(set_attr "type" "test")
7863 (set_attr "mode" "QI")])
7865 (define_insn "*testqi_ext_2"
7870 (match_operand 0 "ext_register_operand" "Q")
7874 (match_operand 1 "ext_register_operand" "Q")
7878 "ix86_match_ccmode (insn, CCNOmode)"
7879 "test{b}\\t{%h1, %h0|%h0, %h1}"
7880 [(set_attr "type" "test")
7881 (set_attr "mode" "QI")])
7883 ;; Combine likes to form bit extractions for some tests. Humor it.
7884 (define_insn "*testqi_ext_3"
7886 (compare (zero_extract:SI
7887 (match_operand 0 "nonimmediate_operand" "rm")
7888 (match_operand:SI 1 "const_int_operand" "")
7889 (match_operand:SI 2 "const_int_operand" ""))
7891 "ix86_match_ccmode (insn, CCNOmode)
7892 && (GET_MODE (operands[0]) == SImode
7893 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7894 || GET_MODE (operands[0]) == HImode
7895 || GET_MODE (operands[0]) == QImode)"
7898 (define_insn "*testqi_ext_3_rex64"
7900 (compare (zero_extract:DI
7901 (match_operand 0 "nonimmediate_operand" "rm")
7902 (match_operand:DI 1 "const_int_operand" "")
7903 (match_operand:DI 2 "const_int_operand" ""))
7905 "ix86_match_ccmode (insn, CCNOmode)
7907 && (GET_MODE (operands[0]) == SImode
7908 || GET_MODE (operands[0]) == DImode
7909 || GET_MODE (operands[0]) == HImode
7910 || GET_MODE (operands[0]) == QImode)"
7915 (compare (zero_extract
7916 (match_operand 0 "nonimmediate_operand" "rm")
7917 (match_operand 1 "const_int_operand" "")
7918 (match_operand 2 "const_int_operand" ""))
7920 "ix86_match_ccmode (insn, CCNOmode)"
7921 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
7924 HOST_WIDE_INT len = INTVAL (operands[1]);
7925 HOST_WIDE_INT pos = INTVAL (operands[2]);
7927 enum machine_mode mode;
7929 mode = GET_MODE (operands[0]);
7930 if (GET_CODE (operands[0]) == MEM)
7932 /* ??? Combine likes to put non-volatile mem extractions in QImode
7933 no matter the size of the test. So find a mode that works. */
7934 if (! MEM_VOLATILE_P (operands[0]))
7936 mode = smallest_mode_for_size (pos + len, MODE_INT);
7937 operands[0] = change_address (operands[0], mode, NULL_RTX);
7940 else if (mode == HImode && pos + len <= 8)
7942 /* Small HImode tests can be converted to QImode. */
7944 operands[0] = gen_lowpart (QImode, operands[0]);
7947 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
7948 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
7950 operands[3] = gen_rtx_AND (mode, operands[0], GEN_INT (mask));
7953 ;; %%% This used to optimize known byte-wide and operations to memory,
7954 ;; and sometimes to QImode registers. If this is considered useful,
7955 ;; it should be done with splitters.
7957 (define_expand "anddi3"
7958 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7959 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
7960 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
7961 (clobber (reg:CC 17))]
7963 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
7965 (define_insn "*anddi_1_rex64"
7966 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
7967 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
7968 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
7969 (clobber (reg:CC 17))]
7970 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
7973 switch (get_attr_type (insn))
7977 enum machine_mode mode;
7979 if (GET_CODE (operands[2]) != CONST_INT)
7981 if (INTVAL (operands[2]) == 0xff)
7983 else if (INTVAL (operands[2]) == 0xffff)
7988 operands[1] = gen_lowpart (mode, operands[1]);
7990 return \"movz{bq|x}\\t{%1,%0|%0, %1}\";
7992 return \"movz{wq|x}\\t{%1,%0|%0, %1}\";
7996 if (! rtx_equal_p (operands[0], operands[1]))
7998 if (get_attr_mode (insn) == MODE_SI)
7999 return \"and{l}\\t{%k2, %k0|%k0, %k2}\";
8001 return \"and{q}\\t{%2, %0|%0, %2}\";
8004 [(set_attr "type" "alu,alu,alu,imovx")
8005 (set_attr "length_immediate" "*,*,*,0")
8006 (set_attr "mode" "SI,DI,DI,DI")])
8008 (define_insn "*anddi_2"
8010 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8011 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8013 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8014 (and:DI (match_dup 1) (match_dup 2)))]
8015 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8016 && ix86_binary_operator_ok (AND, DImode, operands)"
8018 and{l}\\t{%k2, %k0|%k0, %k2}
8019 and{q}\\t{%2, %0|%0, %2}
8020 and{q}\\t{%2, %0|%0, %2}"
8021 [(set_attr "type" "alu")
8022 (set_attr "mode" "SI,DI,DI")])
8024 (define_expand "andsi3"
8025 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8026 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8027 (match_operand:SI 2 "general_operand" "")))
8028 (clobber (reg:CC 17))]
8030 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8032 (define_insn "*andsi_1"
8033 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8034 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8035 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8036 (clobber (reg:CC 17))]
8037 "ix86_binary_operator_ok (AND, SImode, operands)"
8040 switch (get_attr_type (insn))
8044 enum machine_mode mode;
8046 if (GET_CODE (operands[2]) != CONST_INT)
8048 if (INTVAL (operands[2]) == 0xff)
8050 else if (INTVAL (operands[2]) == 0xffff)
8055 operands[1] = gen_lowpart (mode, operands[1]);
8057 return \"movz{bl|x}\\t{%1,%0|%0, %1}\";
8059 return \"movz{wl|x}\\t{%1,%0|%0, %1}\";
8063 if (! rtx_equal_p (operands[0], operands[1]))
8065 return \"and{l}\\t{%2, %0|%0, %2}\";
8068 [(set_attr "type" "alu,alu,imovx")
8069 (set_attr "length_immediate" "*,*,0")
8070 (set_attr "mode" "SI")])
8073 [(set (match_operand 0 "register_operand" "")
8075 (const_int -65536)))
8076 (clobber (reg:CC 17))]
8078 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8079 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))"
8080 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8081 "operands[1] = gen_lowpart (HImode, operands[0]);")
8084 [(set (match_operand 0 "q_regs_operand" "")
8087 (clobber (reg:CC 17))]
8088 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
8089 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8090 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))"
8091 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8092 "operands[1] = gen_lowpart (QImode, operands[0]);")
8095 [(set (match_operand 0 "register_operand" "")
8097 (const_int -65281)))
8098 (clobber (reg:CC 17))]
8099 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
8100 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
8101 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
8102 && (! reload_completed || ANY_QI_REG_P (operands[0]))"
8103 [(parallel [(set (zero_extract:SI (match_dup 0)
8107 (zero_extract:SI (match_dup 0)
8110 (zero_extract:SI (match_dup 0)
8113 (clobber (reg:CC 17))])]
8114 "operands[0] = gen_lowpart (SImode, operands[0]);")
8116 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8117 (define_insn "*andsi_1_zext"
8118 [(set (match_operand:DI 0 "register_operand" "=r")
8120 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8121 (match_operand:SI 2 "general_operand" "rim"))))
8122 (clobber (reg:CC 17))]
8123 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8124 "and{l}\\t{%2, %k0|%k0, %2}"
8125 [(set_attr "type" "alu")
8126 (set_attr "mode" "SI")])
8128 (define_insn "*andsi_2"
8130 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8131 (match_operand:SI 2 "general_operand" "rim,ri"))
8133 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8134 (and:SI (match_dup 1) (match_dup 2)))]
8135 "ix86_match_ccmode (insn, CCNOmode)
8136 && ix86_binary_operator_ok (AND, SImode, operands)"
8137 "and{l}\\t{%2, %0|%0, %2}"
8138 [(set_attr "type" "alu")
8139 (set_attr "mode" "SI")])
8141 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8142 (define_insn "*andsi_2_zext"
8144 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8145 (match_operand:SI 2 "general_operand" "rim"))
8147 (set (match_operand:DI 0 "register_operand" "=r")
8148 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8149 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8150 && ix86_binary_operator_ok (AND, SImode, operands)"
8151 "and{l}\\t{%2, %k0|%k0, %2}"
8152 [(set_attr "type" "alu")
8153 (set_attr "mode" "SI")])
8155 (define_expand "andhi3"
8156 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8157 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8158 (match_operand:HI 2 "general_operand" "")))
8159 (clobber (reg:CC 17))]
8160 "TARGET_HIMODE_MATH"
8161 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8163 (define_insn "*andhi_1"
8164 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8165 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8166 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8167 (clobber (reg:CC 17))]
8168 "ix86_binary_operator_ok (AND, HImode, operands)"
8171 switch (get_attr_type (insn))
8174 if (GET_CODE (operands[2]) != CONST_INT)
8176 if (INTVAL (operands[2]) == 0xff)
8177 return \"movz{bl|x}\\t{%b1, %k0|%k0, %b1}\";
8181 if (! rtx_equal_p (operands[0], operands[1]))
8184 return \"and{w}\\t{%2, %0|%0, %2}\";
8187 [(set_attr "type" "alu,alu,imovx")
8188 (set_attr "length_immediate" "*,*,0")
8189 (set_attr "mode" "HI,HI,SI")])
8191 (define_insn "*andhi_2"
8193 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8194 (match_operand:HI 2 "general_operand" "rim,ri"))
8196 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8197 (and:HI (match_dup 1) (match_dup 2)))]
8198 "ix86_match_ccmode (insn, CCNOmode)
8199 && ix86_binary_operator_ok (AND, HImode, operands)"
8200 "and{w}\\t{%2, %0|%0, %2}"
8201 [(set_attr "type" "alu")
8202 (set_attr "mode" "HI")])
8204 (define_expand "andqi3"
8205 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8206 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8207 (match_operand:QI 2 "general_operand" "")))
8208 (clobber (reg:CC 17))]
8209 "TARGET_QIMODE_MATH"
8210 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8212 ;; %%% Potential partial reg stall on alternative 2. What to do?
8213 (define_insn "*andqi_1"
8214 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8215 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8216 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8217 (clobber (reg:CC 17))]
8218 "ix86_binary_operator_ok (AND, QImode, operands)"
8220 and{b}\\t{%2, %0|%0, %2}
8221 and{b}\\t{%2, %0|%0, %2}
8222 and{l}\\t{%k2, %k0|%k0, %k2}"
8223 [(set_attr "type" "alu")
8224 (set_attr "mode" "QI,QI,SI")])
8226 (define_insn "*andqi_1_slp"
8227 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8228 (and:QI (match_dup 0)
8229 (match_operand:QI 1 "general_operand" "qi,qmi")))
8230 (clobber (reg:CC 17))]
8232 "and{b}\\t{%1, %0|%0, %1}"
8233 [(set_attr "type" "alu1")
8234 (set_attr "mode" "QI")])
8236 (define_insn "*andqi_2"
8239 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8240 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8242 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8243 (and:QI (match_dup 1) (match_dup 2)))]
8244 "ix86_match_ccmode (insn, CCNOmode)
8245 && ix86_binary_operator_ok (AND, QImode, operands)"
8248 if (which_alternative == 2)
8250 if (GET_CODE (operands[2]) == CONST_INT
8251 && (INTVAL (operands[2]) & 0xffffff00))
8252 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8253 return \"and{l}\\t{%2, %k0|%k0, %2}\";
8255 return \"and{b}\\t{%2, %0|%0, %2}\";
8257 [(set_attr "type" "alu")
8258 (set_attr "mode" "QI,QI,SI")])
8260 (define_insn "*andqi_2_slp"
8263 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8264 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8266 (set (strict_low_part (match_dup 0))
8267 (and:QI (match_dup 0) (match_dup 1)))]
8268 "ix86_match_ccmode (insn, CCNOmode)"
8269 "and{b}\\t{%1, %0|%0, %1}"
8270 [(set_attr "type" "alu1")
8271 (set_attr "mode" "QI")])
8273 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8274 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8275 ;; for a QImode operand, which of course failed.
8277 (define_insn "andqi_ext_0"
8278 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8283 (match_operand 1 "ext_register_operand" "0")
8286 (match_operand 2 "const_int_operand" "n")))
8287 (clobber (reg:CC 17))]
8288 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8289 "and{b}\\t{%2, %h0|%h0, %2}"
8290 [(set_attr "type" "alu")
8291 (set_attr "length_immediate" "1")
8292 (set_attr "mode" "QI")])
8294 ;; Generated by peephole translating test to and. This shows up
8295 ;; often in fp comparisons.
8297 (define_insn "*andqi_ext_0_cc"
8302 (match_operand 1 "ext_register_operand" "0")
8305 (match_operand 2 "const_int_operand" "n"))
8307 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8316 "ix86_match_ccmode (insn, CCNOmode)
8317 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
8318 "and{b}\\t{%2, %h0|%h0, %2}"
8319 [(set_attr "type" "alu")
8320 (set_attr "length_immediate" "1")
8321 (set_attr "mode" "QI")])
8323 (define_insn "*andqi_ext_1"
8324 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8329 (match_operand 1 "ext_register_operand" "0")
8333 (match_operand:QI 2 "general_operand" "Qm"))))
8334 (clobber (reg:CC 17))]
8336 "and{b}\\t{%2, %h0|%h0, %2}"
8337 [(set_attr "type" "alu")
8338 (set_attr "length_immediate" "0")
8339 (set_attr "mode" "QI")])
8341 (define_insn "*andqi_ext_1_rex64"
8342 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8347 (match_operand 1 "ext_register_operand" "0")
8351 (match_operand:QI 2 "ext_register_operand" "Q"))))
8352 (clobber (reg:CC 17))]
8354 "and{b}\\t{%2, %h0|%h0, %2}"
8355 [(set_attr "type" "alu")
8356 (set_attr "length_immediate" "0")
8357 (set_attr "mode" "QI")])
8359 (define_insn "*andqi_ext_2"
8360 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8365 (match_operand 1 "ext_register_operand" "%0")
8369 (match_operand 2 "ext_register_operand" "Q")
8372 (clobber (reg:CC 17))]
8374 "and{b}\\t{%h2, %h0|%h0, %h2}"
8375 [(set_attr "type" "alu")
8376 (set_attr "length_immediate" "0")
8377 (set_attr "mode" "QI")])
8379 ;; Logical inclusive OR instructions
8381 ;; %%% This used to optimize known byte-wide and operations to memory.
8382 ;; If this is considered useful, it should be done with splitters.
8384 (define_expand "iordi3"
8385 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8386 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8387 (match_operand:DI 2 "x86_64_general_operand" "")))
8388 (clobber (reg:CC 17))]
8390 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8392 (define_insn "*iordi_1_rex64"
8393 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8394 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8395 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8396 (clobber (reg:CC 17))]
8398 && ix86_binary_operator_ok (IOR, DImode, operands)"
8399 "or{q}\\t{%2, %0|%0, %2}"
8400 [(set_attr "type" "alu")
8401 (set_attr "mode" "DI")])
8403 (define_insn "*iordi_2_rex64"
8405 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8406 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8408 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8409 (ior:DI (match_dup 1) (match_dup 2)))]
8411 && ix86_match_ccmode (insn, CCNOmode)
8412 && ix86_binary_operator_ok (IOR, DImode, operands)"
8413 "or{q}\\t{%2, %0|%0, %2}"
8414 [(set_attr "type" "alu")
8415 (set_attr "mode" "DI")])
8417 (define_insn "*iordi_3_rex64"
8419 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8420 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8422 (clobber (match_scratch:DI 0 "=r"))]
8424 && ix86_match_ccmode (insn, CCNOmode)
8425 && ix86_binary_operator_ok (IOR, DImode, operands)"
8426 "or{q}\\t{%2, %0|%0, %2}"
8427 [(set_attr "type" "alu")
8428 (set_attr "mode" "DI")])
8431 (define_expand "iorsi3"
8432 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8433 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8434 (match_operand:SI 2 "general_operand" "")))
8435 (clobber (reg:CC 17))]
8437 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8439 (define_insn "*iorsi_1"
8440 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8441 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8442 (match_operand:SI 2 "general_operand" "ri,rmi")))
8443 (clobber (reg:CC 17))]
8444 "ix86_binary_operator_ok (IOR, SImode, operands)"
8445 "or{l}\\t{%2, %0|%0, %2}"
8446 [(set_attr "type" "alu")
8447 (set_attr "mode" "SI")])
8449 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8450 (define_insn "*iorsi_1_zext"
8451 [(set (match_operand:DI 0 "register_operand" "=rm")
8453 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8454 (match_operand:SI 2 "general_operand" "rim"))))
8455 (clobber (reg:CC 17))]
8456 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8457 "or{l}\\t{%2, %k0|%k0, %2}"
8458 [(set_attr "type" "alu")
8459 (set_attr "mode" "SI")])
8461 (define_insn "*iorsi_1_zext_imm"
8462 [(set (match_operand:DI 0 "register_operand" "=rm")
8463 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8464 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8465 (clobber (reg:CC 17))]
8467 "or{l}\\t{%2, %k0|%k0, %2}"
8468 [(set_attr "type" "alu")
8469 (set_attr "mode" "SI")])
8471 (define_insn "*iorsi_2"
8473 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8474 (match_operand:SI 2 "general_operand" "rim,ri"))
8476 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8477 (ior:SI (match_dup 1) (match_dup 2)))]
8478 "ix86_match_ccmode (insn, CCNOmode)
8479 && ix86_binary_operator_ok (IOR, SImode, operands)"
8480 "or{l}\\t{%2, %0|%0, %2}"
8481 [(set_attr "type" "alu")
8482 (set_attr "mode" "SI")])
8484 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8485 ;; ??? Special case for immediate operand is missing - it is tricky.
8486 (define_insn "*iorsi_2_zext"
8488 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8489 (match_operand:SI 2 "general_operand" "rim"))
8491 (set (match_operand:DI 0 "register_operand" "=r")
8492 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8493 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8494 && ix86_binary_operator_ok (IOR, SImode, operands)"
8495 "or{l}\\t{%2, %k0|%k0, %2}"
8496 [(set_attr "type" "alu")
8497 (set_attr "mode" "SI")])
8499 (define_insn "*iorsi_2_zext_imm"
8501 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8502 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8504 (set (match_operand:DI 0 "register_operand" "=r")
8505 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8506 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8507 && ix86_binary_operator_ok (IOR, SImode, operands)"
8508 "or{l}\\t{%2, %k0|%k0, %2}"
8509 [(set_attr "type" "alu")
8510 (set_attr "mode" "SI")])
8512 (define_insn "*iorsi_3"
8514 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8515 (match_operand:SI 2 "general_operand" "rim"))
8517 (clobber (match_scratch:SI 0 "=r"))]
8518 "ix86_match_ccmode (insn, CCNOmode)
8519 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8520 "or{l}\\t{%2, %0|%0, %2}"
8521 [(set_attr "type" "alu")
8522 (set_attr "mode" "SI")])
8524 (define_expand "iorhi3"
8525 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8526 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8527 (match_operand:HI 2 "general_operand" "")))
8528 (clobber (reg:CC 17))]
8529 "TARGET_HIMODE_MATH"
8530 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8532 (define_insn "*iorhi_1"
8533 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8534 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8535 (match_operand:HI 2 "general_operand" "rmi,ri")))
8536 (clobber (reg:CC 17))]
8537 "ix86_binary_operator_ok (IOR, HImode, operands)"
8538 "or{w}\\t{%2, %0|%0, %2}"
8539 [(set_attr "type" "alu")
8540 (set_attr "mode" "HI")])
8542 (define_insn "*iorhi_2"
8544 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8545 (match_operand:HI 2 "general_operand" "rim,ri"))
8547 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8548 (ior:HI (match_dup 1) (match_dup 2)))]
8549 "ix86_match_ccmode (insn, CCNOmode)
8550 && ix86_binary_operator_ok (IOR, HImode, operands)"
8551 "or{w}\\t{%2, %0|%0, %2}"
8552 [(set_attr "type" "alu")
8553 (set_attr "mode" "HI")])
8555 (define_insn "*iorhi_3"
8557 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8558 (match_operand:HI 2 "general_operand" "rim"))
8560 (clobber (match_scratch:HI 0 "=r"))]
8561 "ix86_match_ccmode (insn, CCNOmode)
8562 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8563 "or{w}\\t{%2, %0|%0, %2}"
8564 [(set_attr "type" "alu")
8565 (set_attr "mode" "HI")])
8567 (define_expand "iorqi3"
8568 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8569 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8570 (match_operand:QI 2 "general_operand" "")))
8571 (clobber (reg:CC 17))]
8572 "TARGET_QIMODE_MATH"
8573 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8575 ;; %%% Potential partial reg stall on alternative 2. What to do?
8576 (define_insn "*iorqi_1"
8577 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8578 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8579 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8580 (clobber (reg:CC 17))]
8581 "ix86_binary_operator_ok (IOR, QImode, operands)"
8583 or{b}\\t{%2, %0|%0, %2}
8584 or{b}\\t{%2, %0|%0, %2}
8585 or{l}\\t{%k2, %k0|%k0, %k2}"
8586 [(set_attr "type" "alu")
8587 (set_attr "mode" "QI,QI,SI")])
8589 (define_insn "*iorqi_1_slp"
8590 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8591 (ior:QI (match_dup 0)
8592 (match_operand:QI 1 "general_operand" "qmi,qi")))
8593 (clobber (reg:CC 17))]
8595 "or{b}\\t{%1, %0|%0, %1}"
8596 [(set_attr "type" "alu1")
8597 (set_attr "mode" "QI")])
8599 (define_insn "*iorqi_2"
8601 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8602 (match_operand:QI 2 "general_operand" "qim,qi"))
8604 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8605 (ior:QI (match_dup 1) (match_dup 2)))]
8606 "ix86_match_ccmode (insn, CCNOmode)
8607 && ix86_binary_operator_ok (IOR, QImode, operands)"
8608 "or{b}\\t{%2, %0|%0, %2}"
8609 [(set_attr "type" "alu")
8610 (set_attr "mode" "QI")])
8612 (define_insn "*iorqi_2_slp"
8614 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8615 (match_operand:QI 1 "general_operand" "qim,qi"))
8617 (set (strict_low_part (match_dup 0))
8618 (ior:QI (match_dup 0) (match_dup 1)))]
8619 "ix86_match_ccmode (insn, CCNOmode)"
8620 "or{b}\\t{%1, %0|%0, %1}"
8621 [(set_attr "type" "alu1")
8622 (set_attr "mode" "QI")])
8624 (define_insn "*iorqi_3"
8626 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8627 (match_operand:QI 2 "general_operand" "qim"))
8629 (clobber (match_scratch:QI 0 "=q"))]
8630 "ix86_match_ccmode (insn, CCNOmode)
8631 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8632 "or{b}\\t{%2, %0|%0, %2}"
8633 [(set_attr "type" "alu")
8634 (set_attr "mode" "QI")])
8637 ;; Logical XOR instructions
8639 ;; %%% This used to optimize known byte-wide and operations to memory.
8640 ;; If this is considered useful, it should be done with splitters.
8642 (define_expand "xordi3"
8643 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8644 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8645 (match_operand:DI 2 "x86_64_general_operand" "")))
8646 (clobber (reg:CC 17))]
8648 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8650 (define_insn "*xordi_1_rex64"
8651 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8652 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8653 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8654 (clobber (reg:CC 17))]
8656 && ix86_binary_operator_ok (XOR, DImode, operands)"
8658 xor{q}\\t{%2, %0|%0, %2}
8659 xor{q}\\t{%2, %0|%0, %2}"
8660 [(set_attr "type" "alu")
8661 (set_attr "mode" "DI,DI")])
8663 (define_insn "*xordi_2_rex64"
8665 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8666 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8668 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8669 (xor:DI (match_dup 1) (match_dup 2)))]
8671 && ix86_match_ccmode (insn, CCNOmode)
8672 && ix86_binary_operator_ok (XOR, DImode, operands)"
8674 xor{q}\\t{%2, %0|%0, %2}
8675 xor{q}\\t{%2, %0|%0, %2}"
8676 [(set_attr "type" "alu")
8677 (set_attr "mode" "DI,DI")])
8679 (define_insn "*xordi_3_rex64"
8681 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8682 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8684 (clobber (match_scratch:DI 0 "=r"))]
8686 && ix86_match_ccmode (insn, CCNOmode)
8687 && ix86_binary_operator_ok (XOR, DImode, operands)"
8688 "xor{q}\\t{%2, %0|%0, %2}"
8689 [(set_attr "type" "alu")
8690 (set_attr "mode" "DI")])
8692 (define_expand "xorsi3"
8693 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8694 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8695 (match_operand:SI 2 "general_operand" "")))
8696 (clobber (reg:CC 17))]
8698 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8700 (define_insn "*xorsi_1"
8701 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8702 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8703 (match_operand:SI 2 "general_operand" "ri,rm")))
8704 (clobber (reg:CC 17))]
8705 "ix86_binary_operator_ok (XOR, SImode, operands)"
8706 "xor{l}\\t{%2, %0|%0, %2}"
8707 [(set_attr "type" "alu")
8708 (set_attr "mode" "SI")])
8710 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8711 ;; Add speccase for immediates
8712 (define_insn "*xorsi_1_zext"
8713 [(set (match_operand:DI 0 "register_operand" "=r")
8715 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8716 (match_operand:SI 2 "general_operand" "rim"))))
8717 (clobber (reg:CC 17))]
8718 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8719 "xor{l}\\t{%2, %k0|%k0, %2}"
8720 [(set_attr "type" "alu")
8721 (set_attr "mode" "SI")])
8723 (define_insn "*xorsi_1_zext_imm"
8724 [(set (match_operand:DI 0 "register_operand" "=r")
8725 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8726 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8727 (clobber (reg:CC 17))]
8728 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8729 "xor{l}\\t{%2, %k0|%k0, %2}"
8730 [(set_attr "type" "alu")
8731 (set_attr "mode" "SI")])
8733 (define_insn "*xorsi_2"
8735 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8736 (match_operand:SI 2 "general_operand" "rim,ri"))
8738 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8739 (xor:SI (match_dup 1) (match_dup 2)))]
8740 "ix86_match_ccmode (insn, CCNOmode)
8741 && ix86_binary_operator_ok (XOR, SImode, operands)"
8742 "xor{l}\\t{%2, %0|%0, %2}"
8743 [(set_attr "type" "alu")
8744 (set_attr "mode" "SI")])
8746 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8747 ;; ??? Special case for immediate operand is missing - it is tricky.
8748 (define_insn "*xorsi_2_zext"
8750 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8751 (match_operand:SI 2 "general_operand" "rim"))
8753 (set (match_operand:DI 0 "register_operand" "=r")
8754 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8755 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8756 && ix86_binary_operator_ok (XOR, SImode, operands)"
8757 "xor{l}\\t{%2, %k0|%k0, %2}"
8758 [(set_attr "type" "alu")
8759 (set_attr "mode" "SI")])
8761 (define_insn "*xorsi_2_zext_imm"
8763 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8764 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8766 (set (match_operand:DI 0 "register_operand" "=r")
8767 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8768 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8769 && ix86_binary_operator_ok (XOR, SImode, operands)"
8770 "xor{l}\\t{%2, %k0|%k0, %2}"
8771 [(set_attr "type" "alu")
8772 (set_attr "mode" "SI")])
8774 (define_insn "*xorsi_3"
8776 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8777 (match_operand:SI 2 "general_operand" "rim"))
8779 (clobber (match_scratch:SI 0 "=r"))]
8780 "ix86_match_ccmode (insn, CCNOmode)
8781 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8782 "xor{l}\\t{%2, %0|%0, %2}"
8783 [(set_attr "type" "alu")
8784 (set_attr "mode" "SI")])
8786 (define_expand "xorhi3"
8787 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8788 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
8789 (match_operand:HI 2 "general_operand" "")))
8790 (clobber (reg:CC 17))]
8791 "TARGET_HIMODE_MATH"
8792 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
8794 (define_insn "*xorhi_1"
8795 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8796 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8797 (match_operand:HI 2 "general_operand" "rmi,ri")))
8798 (clobber (reg:CC 17))]
8799 "ix86_binary_operator_ok (XOR, HImode, operands)"
8800 "xor{w}\\t{%2, %0|%0, %2}"
8801 [(set_attr "type" "alu")
8802 (set_attr "mode" "HI")])
8804 (define_insn "*xorhi_2"
8806 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8807 (match_operand:HI 2 "general_operand" "rim,ri"))
8809 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8810 (xor:HI (match_dup 1) (match_dup 2)))]
8811 "ix86_match_ccmode (insn, CCNOmode)
8812 && ix86_binary_operator_ok (XOR, HImode, operands)"
8813 "xor{w}\\t{%2, %0|%0, %2}"
8814 [(set_attr "type" "alu")
8815 (set_attr "mode" "HI")])
8817 (define_insn "*xorhi_3"
8819 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8820 (match_operand:HI 2 "general_operand" "rim"))
8822 (clobber (match_scratch:HI 0 "=r"))]
8823 "ix86_match_ccmode (insn, CCNOmode)
8824 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8825 "xor{w}\\t{%2, %0|%0, %2}"
8826 [(set_attr "type" "alu")
8827 (set_attr "mode" "HI")])
8829 (define_expand "xorqi3"
8830 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8831 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
8832 (match_operand:QI 2 "general_operand" "")))
8833 (clobber (reg:CC 17))]
8834 "TARGET_QIMODE_MATH"
8835 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
8837 ;; %%% Potential partial reg stall on alternative 2. What to do?
8838 (define_insn "*xorqi_1"
8839 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8840 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8841 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8842 (clobber (reg:CC 17))]
8843 "ix86_binary_operator_ok (XOR, QImode, operands)"
8845 xor{b}\\t{%2, %0|%0, %2}
8846 xor{b}\\t{%2, %0|%0, %2}
8847 xor{l}\\t{%k2, %k0|%k0, %k2}"
8848 [(set_attr "type" "alu")
8849 (set_attr "mode" "QI,QI,SI")])
8851 (define_insn "*xorqi_ext_1"
8852 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8856 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8859 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8862 (clobber (reg:CC 17))]
8864 "xor{b}\\t{%h2, %h0|%h0, %h2}"
8865 [(set_attr "type" "alu")
8866 (set_attr "length_immediate" "0")
8867 (set_attr "mode" "QI")])
8869 (define_insn "*xorqi_cc_1"
8872 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8873 (match_operand:QI 2 "general_operand" "qim,qi"))
8875 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8876 (xor:QI (match_dup 1) (match_dup 2)))]
8877 "ix86_match_ccmode (insn, CCNOmode)
8878 && ix86_binary_operator_ok (XOR, QImode, operands)"
8879 "xor{b}\\t{%2, %0|%0, %2}"
8880 [(set_attr "type" "alu")
8881 (set_attr "mode" "QI")])
8883 (define_insn "*xorqi_cc_2"
8886 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8887 (match_operand:QI 2 "general_operand" "qim"))
8889 (clobber (match_scratch:QI 0 "=q"))]
8890 "ix86_match_ccmode (insn, CCNOmode)
8891 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8892 "xor{b}\\t{%2, %0|%0, %2}"
8893 [(set_attr "type" "alu")
8894 (set_attr "mode" "QI")])
8896 (define_insn "*xorqi_cc_ext_1"
8901 (match_operand 1 "ext_register_operand" "0")
8904 (match_operand:QI 2 "general_operand" "qmn"))
8906 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
8910 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
8912 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8913 "xor{b}\\t{%2, %h0|%h0, %2}"
8914 [(set_attr "type" "alu")
8915 (set_attr "mode" "QI")])
8917 (define_insn "*xorqi_cc_ext_1_rex64"
8922 (match_operand 1 "ext_register_operand" "0")
8925 (match_operand:QI 2 "nonmemory_operand" "Qn"))
8927 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8931 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
8933 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8934 "xor{b}\\t{%2, %h0|%h0, %2}"
8935 [(set_attr "type" "alu")
8936 (set_attr "mode" "QI")])
8938 (define_expand "xorqi_cc_ext_1"
8944 (match_operand 1 "ext_register_operand" "")
8947 (match_operand:QI 2 "general_operand" ""))
8949 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
8953 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
8958 ;; Negation instructions
8960 (define_expand "negdi2"
8961 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
8962 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
8963 (clobber (reg:CC 17))])]
8965 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
8967 (define_insn "*negdi2_1"
8968 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
8969 (neg:DI (match_operand:DI 1 "general_operand" "0")))
8970 (clobber (reg:CC 17))]
8972 && ix86_unary_operator_ok (NEG, DImode, operands)"
8976 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8977 (neg:DI (match_operand:DI 1 "general_operand" "")))
8978 (clobber (reg:CC 17))]
8983 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
8984 (set (match_dup 0) (neg:SI (match_dup 2)))])
8987 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
8990 (clobber (reg:CC 17))])
8993 (neg:SI (match_dup 1)))
8994 (clobber (reg:CC 17))])]
8995 "split_di (operands+1, 1, operands+2, operands+3);
8996 split_di (operands+0, 1, operands+0, operands+1);")
8998 (define_insn "*negdi2_1_rex64"
8999 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9000 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9001 (clobber (reg:CC 17))]
9002 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9004 [(set_attr "type" "negnot")
9005 (set_attr "mode" "DI")])
9007 ;; The problem with neg is that it does not perform (compare x 0),
9008 ;; it really performs (compare 0 x), which leaves us with the zero
9009 ;; flag being the only useful item.
9011 (define_insn "*negdi2_cmpz_rex64"
9013 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9015 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9016 (neg:DI (match_dup 1)))]
9017 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9019 [(set_attr "type" "negnot")
9020 (set_attr "mode" "DI")])
9023 (define_expand "negsi2"
9024 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9025 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9026 (clobber (reg:CC 17))])]
9028 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9030 (define_insn "*negsi2_1"
9031 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9032 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9033 (clobber (reg:CC 17))]
9034 "ix86_unary_operator_ok (NEG, SImode, operands)"
9036 [(set_attr "type" "negnot")
9037 (set_attr "mode" "SI")])
9039 ;; Combine is quite creative about this pattern.
9040 (define_insn "*negsi2_1_zext"
9041 [(set (match_operand:DI 0 "register_operand" "=r")
9042 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9045 (clobber (reg:CC 17))]
9046 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9048 [(set_attr "type" "negnot")
9049 (set_attr "mode" "SI")])
9051 ;; The problem with neg is that it does not perform (compare x 0),
9052 ;; it really performs (compare 0 x), which leaves us with the zero
9053 ;; flag being the only useful item.
9055 (define_insn "*negsi2_cmpz"
9057 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9059 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9060 (neg:SI (match_dup 1)))]
9061 "ix86_unary_operator_ok (NEG, SImode, operands)"
9063 [(set_attr "type" "negnot")
9064 (set_attr "mode" "SI")])
9066 (define_insn "*negsi2_cmpz_zext"
9068 (compare:CCZ (lshiftrt:DI
9070 (match_operand:DI 1 "register_operand" "0")
9074 (set (match_operand:DI 0 "register_operand" "=r")
9075 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9078 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9080 [(set_attr "type" "negnot")
9081 (set_attr "mode" "SI")])
9083 (define_expand "neghi2"
9084 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9085 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9086 (clobber (reg:CC 17))])]
9087 "TARGET_HIMODE_MATH"
9088 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9090 (define_insn "*neghi2_1"
9091 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9092 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9093 (clobber (reg:CC 17))]
9094 "ix86_unary_operator_ok (NEG, HImode, operands)"
9096 [(set_attr "type" "negnot")
9097 (set_attr "mode" "HI")])
9099 (define_insn "*neghi2_cmpz"
9101 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9103 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9104 (neg:HI (match_dup 1)))]
9105 "ix86_unary_operator_ok (NEG, HImode, operands)"
9107 [(set_attr "type" "negnot")
9108 (set_attr "mode" "HI")])
9110 (define_expand "negqi2"
9111 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9112 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9113 (clobber (reg:CC 17))])]
9114 "TARGET_QIMODE_MATH"
9115 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9117 (define_insn "*negqi2_1"
9118 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9119 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9120 (clobber (reg:CC 17))]
9121 "ix86_unary_operator_ok (NEG, QImode, operands)"
9123 [(set_attr "type" "negnot")
9124 (set_attr "mode" "QI")])
9126 (define_insn "*negqi2_cmpz"
9128 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9130 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9131 (neg:QI (match_dup 1)))]
9132 "ix86_unary_operator_ok (NEG, QImode, operands)"
9134 [(set_attr "type" "negnot")
9135 (set_attr "mode" "QI")])
9137 ;; Changing of sign for FP values is doable using integer unit too.
9139 (define_expand "negsf2"
9140 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9141 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9142 (clobber (reg:CC 17))])]
9144 "ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9146 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9147 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9149 (define_insn "*negsf2_if"
9150 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9151 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9152 (clobber (reg:CC 17))]
9153 "TARGET_80387 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9157 [(set (match_operand:SF 0 "register_operand" "")
9158 (neg:SF (match_operand:SF 1 "register_operand" "")))
9159 (clobber (reg:CC 17))]
9160 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9162 (neg:SF (match_dup 1)))]
9166 [(set (match_operand:SF 0 "register_operand" "")
9167 (neg:SF (match_operand:SF 1 "register_operand" "")))
9168 (clobber (reg:CC 17))]
9169 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9170 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9171 (clobber (reg:CC 17))])]
9172 "operands[1] = GEN_INT (0x80000000);
9173 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9176 [(set (match_operand 0 "memory_operand" "")
9177 (neg (match_operand 1 "memory_operand" "")))
9178 (clobber (reg:CC 17))]
9179 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9180 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9181 (clobber (reg:CC 17))])]
9184 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9186 /* XFmode's size is 12, but only 10 bytes are used. */
9189 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
9190 operands[0] = adj_offsettable_operand (operands[0], size - 1);
9191 operands[1] = GEN_INT (0x80);
9194 (define_expand "negdf2"
9195 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9196 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9197 (clobber (reg:CC 17))])]
9199 "ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9201 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9202 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9204 (define_insn "*negdf2_if"
9205 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9206 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9207 (clobber (reg:CC 17))]
9208 "TARGET_80387 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9212 [(set (match_operand:DF 0 "register_operand" "")
9213 (neg:DF (match_operand:DF 1 "register_operand" "")))
9214 (clobber (reg:CC 17))]
9215 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9217 (neg:DF (match_dup 1)))]
9221 [(set (match_operand:DF 0 "register_operand" "")
9222 (neg:DF (match_operand:DF 1 "register_operand" "")))
9223 (clobber (reg:CC 17))]
9224 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9225 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9226 (clobber (reg:CC 17))])]
9227 "operands[4] = GEN_INT (0x80000000);
9228 split_di (operands+0, 1, operands+2, operands+3);")
9230 (define_expand "negxf2"
9231 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9232 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9233 (clobber (reg:CC 17))])]
9234 "TARGET_80387 && !TARGET_64BIT"
9235 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9237 (define_expand "negtf2"
9238 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9239 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9240 (clobber (reg:CC 17))])]
9242 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9244 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9245 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9247 (define_insn "*negxf2_if"
9248 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9249 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9250 (clobber (reg:CC 17))]
9251 "TARGET_80387 && !TARGET_64BIT
9252 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9256 [(set (match_operand:XF 0 "register_operand" "")
9257 (neg:XF (match_operand:XF 1 "register_operand" "")))
9258 (clobber (reg:CC 17))]
9259 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9261 (neg:XF (match_dup 1)))]
9265 [(set (match_operand:XF 0 "register_operand" "")
9266 (neg:XF (match_operand:XF 1 "register_operand" "")))
9267 (clobber (reg:CC 17))]
9268 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9269 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9270 (clobber (reg:CC 17))])]
9271 "operands[1] = GEN_INT (0x8000);
9272 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
9274 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9275 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9277 (define_insn "*negtf2_if"
9278 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9279 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9280 (clobber (reg:CC 17))]
9281 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9285 [(set (match_operand:TF 0 "register_operand" "")
9286 (neg:TF (match_operand:TF 1 "register_operand" "")))
9287 (clobber (reg:CC 17))]
9288 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9290 (neg:TF (match_dup 1)))]
9294 [(set (match_operand:TF 0 "register_operand" "")
9295 (neg:TF (match_operand:TF 1 "register_operand" "")))
9296 (clobber (reg:CC 17))]
9297 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9298 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9299 (clobber (reg:CC 17))])]
9300 "operands[1] = GEN_INT (0x8000);
9301 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
9303 ;; Conditionize these after reload. If they matches before reload, we
9304 ;; lose the clobber and ability to use integer instructions.
9306 (define_insn "*negsf2_1"
9307 [(set (match_operand:SF 0 "register_operand" "=f")
9308 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9309 "TARGET_80387 && reload_completed"
9311 [(set_attr "type" "fsgn")
9312 (set_attr "mode" "SF")
9313 (set_attr "ppro_uops" "few")])
9315 (define_insn "*negdf2_1"
9316 [(set (match_operand:DF 0 "register_operand" "=f")
9317 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9318 "TARGET_80387 && reload_completed"
9320 [(set_attr "type" "fsgn")
9321 (set_attr "mode" "DF")
9322 (set_attr "ppro_uops" "few")])
9324 (define_insn "*negextendsfdf2"
9325 [(set (match_operand:DF 0 "register_operand" "=f")
9326 (neg:DF (float_extend:DF
9327 (match_operand:SF 1 "register_operand" "0"))))]
9330 [(set_attr "type" "fsgn")
9331 (set_attr "mode" "DF")
9332 (set_attr "ppro_uops" "few")])
9334 (define_insn "*negxf2_1"
9335 [(set (match_operand:XF 0 "register_operand" "=f")
9336 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9337 "TARGET_80387 && !TARGET_64BIT && reload_completed"
9339 [(set_attr "type" "fsgn")
9340 (set_attr "mode" "XF")
9341 (set_attr "ppro_uops" "few")])
9343 (define_insn "*negextenddfxf2"
9344 [(set (match_operand:XF 0 "register_operand" "=f")
9345 (neg:XF (float_extend:XF
9346 (match_operand:DF 1 "register_operand" "0"))))]
9347 "TARGET_80387 && !TARGET_64BIT"
9349 [(set_attr "type" "fsgn")
9350 (set_attr "mode" "XF")
9351 (set_attr "ppro_uops" "few")])
9353 (define_insn "*negextendsfxf2"
9354 [(set (match_operand:XF 0 "register_operand" "=f")
9355 (neg:XF (float_extend:XF
9356 (match_operand:SF 1 "register_operand" "0"))))]
9357 "TARGET_80387 && !TARGET_64BIT"
9359 [(set_attr "type" "fsgn")
9360 (set_attr "mode" "XF")
9361 (set_attr "ppro_uops" "few")])
9363 (define_insn "*negtf2_1"
9364 [(set (match_operand:TF 0 "register_operand" "=f")
9365 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9366 "TARGET_80387 && reload_completed"
9368 [(set_attr "type" "fsgn")
9369 (set_attr "mode" "XF")
9370 (set_attr "ppro_uops" "few")])
9372 (define_insn "*negextenddftf2"
9373 [(set (match_operand:TF 0 "register_operand" "=f")
9374 (neg:TF (float_extend:TF
9375 (match_operand:DF 1 "register_operand" "0"))))]
9378 [(set_attr "type" "fsgn")
9379 (set_attr "mode" "XF")
9380 (set_attr "ppro_uops" "few")])
9382 (define_insn "*negextendsftf2"
9383 [(set (match_operand:TF 0 "register_operand" "=f")
9384 (neg:TF (float_extend:TF
9385 (match_operand:SF 1 "register_operand" "0"))))]
9388 [(set_attr "type" "fsgn")
9389 (set_attr "mode" "XF")
9390 (set_attr "ppro_uops" "few")])
9392 ;; Absolute value instructions
9394 (define_expand "abssf2"
9395 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9396 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9397 (clobber (reg:CC 17))])]
9401 /* In case operand is in memory, we will not use SSE. */
9402 if (memory_operand (operands[0], VOIDmode)
9403 && rtx_equal_p (operands[0], operands[1]))
9404 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9407 /* Using SSE is tricky, since we need bitwise negation of -0
9409 rtx reg = gen_reg_rtx (SFmode);
9410 emit_move_insn (reg, gen_lowpart (SFmode, GEN_INT (0x80000000)));
9411 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9415 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9417 (define_insn "abssf2_memory"
9418 [(set (match_operand:SF 0 "memory_operand" "=m")
9419 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9420 (clobber (reg:CC 17))]
9421 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9424 (define_insn "abssf2_ifs"
9425 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,r#xf")
9426 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9427 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*X#x,*X#x"))
9428 (clobber (reg:CC 17))]
9433 [(set (match_operand:SF 0 "memory_operand" "")
9434 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9435 (use (match_operand:SF 2 "" ""))
9436 (clobber (reg:CC 17))]
9438 [(parallel [(set (match_dup 0)
9439 (abs:SF (match_dup 1)))
9440 (clobber (reg:CC 17))])])
9443 [(set (match_operand:SF 0 "register_operand" "")
9444 (abs:SF (match_operand:SF 1 "register_operand" "")))
9445 (use (match_operand:SF 2 "" ""))
9446 (clobber (reg:CC 17))]
9447 "reload_completed && !SSE_REG_P (operands[0])"
9448 [(parallel [(set (match_dup 0)
9449 (abs:SF (match_dup 1)))
9450 (clobber (reg:CC 17))])])
9453 [(set (match_operand:SF 0 "register_operand" "")
9454 (abs:SF (match_operand:SF 1 "register_operand" "")))
9455 (use (match_operand:SF 2 "register_operand" ""))
9456 (clobber (reg:CC 17))]
9457 "reload_completed && SSE_REG_P (operands[0])"
9458 [(set (subreg:TI (match_dup 0) 0)
9459 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9460 (subreg:TI (match_dup 1) 0)))])
9462 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9463 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9465 (define_insn "*abssf2_if"
9466 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9467 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9468 (clobber (reg:CC 17))]
9469 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9473 [(set (match_operand:SF 0 "register_operand" "")
9474 (abs:SF (match_operand:SF 1 "register_operand" "")))
9475 (clobber (reg:CC 17))]
9476 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
9478 (abs:SF (match_dup 1)))]
9482 [(set (match_operand:SF 0 "register_operand" "")
9483 (abs:SF (match_operand:SF 1 "register_operand" "")))
9484 (clobber (reg:CC 17))]
9485 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9486 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9487 (clobber (reg:CC 17))])]
9488 "operands[1] = GEN_INT (~0x80000000);
9489 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9492 [(set (match_operand 0 "memory_operand" "")
9493 (abs (match_operand 1 "memory_operand" "")))
9494 (clobber (reg:CC 17))]
9495 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9496 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9497 (clobber (reg:CC 17))])]
9500 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9502 /* XFmode's size is 12, but only 10 bytes are used. */
9505 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
9506 operands[0] = adj_offsettable_operand (operands[0], size - 1);
9507 operands[1] = GEN_INT (~0x80);
9510 (define_expand "absdf2"
9511 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9512 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9513 (clobber (reg:CC 17))])]
9517 /* In case operand is in memory, we will not use SSE. */
9518 if (memory_operand (operands[0], VOIDmode)
9519 && rtx_equal_p (operands[0], operands[1]))
9520 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9523 /* Using SSE is tricky, since we need bitwise negation of -0
9525 rtx reg = gen_reg_rtx (DFmode);
9526 #if HOST_BITS_PER_WIDE_INT >= 64
9527 rtx imm = GEN_INT (0x80000000);
9529 rtx imm = immed_double_const (0, 0x80000000, DImode);
9531 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9532 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9536 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9538 (define_insn "absdf2_memory"
9539 [(set (match_operand:DF 0 "memory_operand" "=m")
9540 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9541 (clobber (reg:CC 17))]
9542 "ix86_unary_operator_ok (ABS, DFmode, operands)"
9545 (define_insn "absdf2_ifs"
9546 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,f#Yr,r#Yf")
9547 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
9548 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*X#Y,*X#Y"))
9549 (clobber (reg:CC 17))]
9554 [(set (match_operand:DF 0 "memory_operand" "")
9555 (abs:DF (match_operand:DF 1 "memory_operand" "")))
9556 (use (match_operand:DF 2 "" ""))
9557 (clobber (reg:CC 17))]
9559 [(parallel [(set (match_dup 0)
9560 (abs:DF (match_dup 1)))
9561 (clobber (reg:CC 17))])])
9564 [(set (match_operand:DF 0 "register_operand" "")
9565 (abs:DF (match_operand:DF 1 "register_operand" "")))
9566 (use (match_operand:DF 2 "" ""))
9567 (clobber (reg:CC 17))]
9568 "reload_completed && !SSE_REG_P (operands[0])"
9569 [(parallel [(set (match_dup 0)
9570 (abs:DF (match_dup 1)))
9571 (clobber (reg:CC 17))])])
9574 [(set (match_operand:DF 0 "register_operand" "")
9575 (abs:DF (match_operand:DF 1 "register_operand" "")))
9576 (use (match_operand:DF 2 "register_operand" ""))
9577 (clobber (reg:CC 17))]
9578 "reload_completed && SSE_REG_P (operands[0])"
9579 [(set (subreg:TI (match_dup 0) 0)
9580 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9581 (subreg:TI (match_dup 1) 0)))])
9584 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9585 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9587 (define_insn "*absdf2_if"
9588 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9589 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9590 (clobber (reg:CC 17))]
9591 "TARGET_80387 && ix86_unary_operator_ok (ABS, DFmode, operands)"
9595 [(set (match_operand:DF 0 "register_operand" "")
9596 (abs:DF (match_operand:DF 1 "register_operand" "")))
9597 (clobber (reg:CC 17))]
9598 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9600 (abs:DF (match_dup 1)))]
9604 [(set (match_operand:DF 0 "register_operand" "")
9605 (abs:DF (match_operand:DF 1 "register_operand" "")))
9606 (clobber (reg:CC 17))]
9607 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9608 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
9609 (clobber (reg:CC 17))])]
9610 "operands[4] = GEN_INT (~0x80000000);
9611 split_di (operands+0, 1, operands+2, operands+3);")
9613 (define_expand "absxf2"
9614 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9615 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9616 (clobber (reg:CC 17))])]
9617 "TARGET_80387 && !TARGET_64BIT"
9618 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
9620 (define_expand "abstf2"
9621 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9622 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9623 (clobber (reg:CC 17))])]
9625 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
9627 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9628 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9630 (define_insn "*absxf2_if"
9631 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9632 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9633 (clobber (reg:CC 17))]
9634 "TARGET_80387 && !TARGET_64BIT
9635 && ix86_unary_operator_ok (ABS, XFmode, operands)"
9639 [(set (match_operand:XF 0 "register_operand" "")
9640 (abs:XF (match_operand:XF 1 "register_operand" "")))
9641 (clobber (reg:CC 17))]
9642 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9644 (abs:XF (match_dup 1)))]
9648 [(set (match_operand:XF 0 "register_operand" "")
9649 (abs:XF (match_operand:XF 1 "register_operand" "")))
9650 (clobber (reg:CC 17))]
9651 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9652 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9653 (clobber (reg:CC 17))])]
9654 "operands[1] = GEN_INT (~0x8000);
9655 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
9657 (define_insn "*abstf2_if"
9658 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9659 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9660 (clobber (reg:CC 17))]
9661 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
9665 [(set (match_operand:TF 0 "register_operand" "")
9666 (abs:TF (match_operand:TF 1 "register_operand" "")))
9667 (clobber (reg:CC 17))]
9668 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
9670 (abs:TF (match_dup 1)))]
9674 [(set (match_operand:TF 0 "register_operand" "")
9675 (abs:TF (match_operand:TF 1 "register_operand" "")))
9676 (clobber (reg:CC 17))]
9677 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
9678 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9679 (clobber (reg:CC 17))])]
9680 "operands[1] = GEN_INT (~0x8000);
9681 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
9683 (define_insn "*abssf2_1"
9684 [(set (match_operand:SF 0 "register_operand" "=f")
9685 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
9686 "TARGET_80387 && reload_completed"
9688 [(set_attr "type" "fsgn")
9689 (set_attr "mode" "SF")])
9691 (define_insn "*absdf2_1"
9692 [(set (match_operand:DF 0 "register_operand" "=f")
9693 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
9694 "TARGET_80387 && reload_completed"
9696 [(set_attr "type" "fsgn")
9697 (set_attr "mode" "DF")])
9699 (define_insn "*absextendsfdf2"
9700 [(set (match_operand:DF 0 "register_operand" "=f")
9701 (abs:DF (float_extend:DF
9702 (match_operand:SF 1 "register_operand" "0"))))]
9705 [(set_attr "type" "fsgn")
9706 (set_attr "mode" "DF")])
9708 (define_insn "*absxf2_1"
9709 [(set (match_operand:XF 0 "register_operand" "=f")
9710 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
9711 "TARGET_80387 && !TARGET_64BIT && reload_completed"
9713 [(set_attr "type" "fsgn")
9714 (set_attr "mode" "DF")])
9716 (define_insn "*absextenddfxf2"
9717 [(set (match_operand:XF 0 "register_operand" "=f")
9718 (abs:XF (float_extend:XF
9719 (match_operand:DF 1 "register_operand" "0"))))]
9720 "TARGET_80387 && !TARGET_64BIT"
9722 [(set_attr "type" "fsgn")
9723 (set_attr "mode" "XF")])
9725 (define_insn "*absextendsfxf2"
9726 [(set (match_operand:XF 0 "register_operand" "=f")
9727 (abs:XF (float_extend:XF
9728 (match_operand:SF 1 "register_operand" "0"))))]
9729 "TARGET_80387 && !TARGET_64BIT"
9731 [(set_attr "type" "fsgn")
9732 (set_attr "mode" "XF")])
9734 (define_insn "*abstf2_1"
9735 [(set (match_operand:TF 0 "register_operand" "=f")
9736 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
9737 "TARGET_80387 && reload_completed"
9739 [(set_attr "type" "fsgn")
9740 (set_attr "mode" "DF")])
9742 (define_insn "*absextenddftf2"
9743 [(set (match_operand:TF 0 "register_operand" "=f")
9744 (abs:TF (float_extend:TF
9745 (match_operand:DF 1 "register_operand" "0"))))]
9748 [(set_attr "type" "fsgn")
9749 (set_attr "mode" "XF")])
9751 (define_insn "*absextendsftf2"
9752 [(set (match_operand:TF 0 "register_operand" "=f")
9753 (abs:TF (float_extend:TF
9754 (match_operand:SF 1 "register_operand" "0"))))]
9757 [(set_attr "type" "fsgn")
9758 (set_attr "mode" "XF")])
9760 ;; One complement instructions
9762 (define_expand "one_cmpldi2"
9763 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9764 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
9766 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
9768 (define_insn "*one_cmpldi2_1_rex64"
9769 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9770 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
9771 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
9773 [(set_attr "type" "negnot")
9774 (set_attr "mode" "DI")])
9776 (define_insn "*one_cmpldi2_2_rex64"
9778 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9780 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9781 (not:DI (match_dup 1)))]
9782 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9783 && ix86_unary_operator_ok (NOT, DImode, operands)"
9785 [(set_attr "type" "alu1")
9786 (set_attr "mode" "DI")])
9790 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
9792 (set (match_operand:DI 0 "nonimmediate_operand" "")
9793 (not:DI (match_dup 1)))]
9794 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9795 [(parallel [(set (reg:CCNO 17)
9796 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
9799 (xor:DI (match_dup 1) (const_int -1)))])]
9802 (define_expand "one_cmplsi2"
9803 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9804 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
9806 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
9808 (define_insn "*one_cmplsi2_1"
9809 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9810 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
9811 "ix86_unary_operator_ok (NOT, SImode, operands)"
9813 [(set_attr "type" "negnot")
9814 (set_attr "mode" "SI")])
9816 ;; ??? Currently never generated - xor is used instead.
9817 (define_insn "*one_cmplsi2_1_zext"
9818 [(set (match_operand:DI 0 "register_operand" "=r")
9819 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
9820 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
9822 [(set_attr "type" "negnot")
9823 (set_attr "mode" "SI")])
9825 (define_insn "*one_cmplsi2_2"
9827 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9829 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9830 (not:SI (match_dup 1)))]
9831 "ix86_match_ccmode (insn, CCNOmode)
9832 && ix86_unary_operator_ok (NOT, SImode, operands)"
9834 [(set_attr "type" "alu1")
9835 (set_attr "mode" "SI")])
9839 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
9841 (set (match_operand:SI 0 "nonimmediate_operand" "")
9842 (not:SI (match_dup 1)))]
9843 "ix86_match_ccmode (insn, CCNOmode)"
9844 [(parallel [(set (reg:CCNO 17)
9845 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
9848 (xor:SI (match_dup 1) (const_int -1)))])]
9851 ;; ??? Currently never generated - xor is used instead.
9852 (define_insn "*one_cmplsi2_2_zext"
9854 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
9856 (set (match_operand:DI 0 "register_operand" "=r")
9857 (zero_extend:DI (not:SI (match_dup 1))))]
9858 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9859 && ix86_unary_operator_ok (NOT, SImode, operands)"
9861 [(set_attr "type" "alu1")
9862 (set_attr "mode" "SI")])
9866 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
9868 (set (match_operand:DI 0 "register_operand" "")
9869 (zero_extend:DI (not:SI (match_dup 1))))]
9870 "ix86_match_ccmode (insn, CCNOmode)"
9871 [(parallel [(set (reg:CCNO 17)
9872 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
9875 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
9878 (define_expand "one_cmplhi2"
9879 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9880 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
9881 "TARGET_HIMODE_MATH"
9882 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
9884 (define_insn "*one_cmplhi2_1"
9885 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9886 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
9887 "ix86_unary_operator_ok (NOT, HImode, operands)"
9889 [(set_attr "type" "negnot")
9890 (set_attr "mode" "HI")])
9892 (define_insn "*one_cmplhi2_2"
9894 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9896 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9897 (not:HI (match_dup 1)))]
9898 "ix86_match_ccmode (insn, CCNOmode)
9899 && ix86_unary_operator_ok (NEG, HImode, operands)"
9901 [(set_attr "type" "alu1")
9902 (set_attr "mode" "HI")])
9906 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
9908 (set (match_operand:HI 0 "nonimmediate_operand" "")
9909 (not:HI (match_dup 1)))]
9910 "ix86_match_ccmode (insn, CCNOmode)"
9911 [(parallel [(set (reg:CCNO 17)
9912 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
9915 (xor:HI (match_dup 1) (const_int -1)))])]
9918 ;; %%% Potential partial reg stall on alternative 1. What to do?
9919 (define_expand "one_cmplqi2"
9920 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9921 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
9922 "TARGET_QIMODE_MATH"
9923 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
9925 (define_insn "*one_cmplqi2_1"
9926 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
9927 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
9928 "ix86_unary_operator_ok (NOT, QImode, operands)"
9932 [(set_attr "type" "negnot")
9933 (set_attr "mode" "QI,SI")])
9935 (define_insn "*one_cmplqi2_2"
9937 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9939 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9940 (not:QI (match_dup 1)))]
9941 "ix86_match_ccmode (insn, CCNOmode)
9942 && ix86_unary_operator_ok (NOT, QImode, operands)"
9944 [(set_attr "type" "alu1")
9945 (set_attr "mode" "QI")])
9949 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
9951 (set (match_operand:QI 0 "nonimmediate_operand" "")
9952 (not:QI (match_dup 1)))]
9953 "ix86_match_ccmode (insn, CCNOmode)"
9954 [(parallel [(set (reg:CCNO 17)
9955 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
9958 (xor:QI (match_dup 1) (const_int -1)))])]
9961 ;; Arithmetic shift instructions
9963 ;; DImode shifts are implemented using the i386 "shift double" opcode,
9964 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
9965 ;; is variable, then the count is in %cl and the "imm" operand is dropped
9966 ;; from the assembler input.
9968 ;; This instruction shifts the target reg/mem as usual, but instead of
9969 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
9970 ;; is a left shift double, bits are taken from the high order bits of
9971 ;; reg, else if the insn is a shift right double, bits are taken from the
9972 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
9973 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
9975 ;; Since sh[lr]d does not change the `reg' operand, that is done
9976 ;; separately, making all shifts emit pairs of shift double and normal
9977 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
9978 ;; support a 63 bit shift, each shift where the count is in a reg expands
9979 ;; to a pair of shifts, a branch, a shift by 32 and a label.
9981 ;; If the shift count is a constant, we need never emit more than one
9982 ;; shift pair, instead using moves and sign extension for counts greater
9985 (define_expand "ashldi3"
9986 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
9987 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
9988 (match_operand:QI 2 "nonmemory_operand" "")))
9989 (clobber (reg:CC 17))])]
9993 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
9995 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
9998 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10002 (define_insn "*ashldi3_1_rex64"
10003 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10004 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10005 (match_operand:QI 2 "nonmemory_operand" "c,M")))
10006 (clobber (reg:CC 17))]
10007 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10010 switch (get_attr_type (insn))
10013 if (operands[2] != const1_rtx)
10015 if (!rtx_equal_p (operands[0], operands[1]))
10017 return \"add{q}\\t{%0, %0|%0, %0}\";
10020 if (GET_CODE (operands[2]) != CONST_INT
10021 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10023 operands[1] = gen_rtx_MULT (DImode, operands[1],
10024 GEN_INT (1 << INTVAL (operands[2])));
10025 return \"lea{q}\\t{%a1, %0|%0, %a1}\";
10028 if (REG_P (operands[2]))
10029 return \"sal{q}\\t{%b2, %0|%0, %b2}\";
10030 else if (GET_CODE (operands[2]) == CONST_INT
10031 && INTVAL (operands[2]) == 1
10032 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10033 return \"sal{q}\\t%0\";
10035 return \"sal{q}\\t{%2, %0|%0, %2}\";
10038 [(set (attr "type")
10039 (cond [(eq_attr "alternative" "1")
10040 (const_string "lea")
10041 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10043 (match_operand 0 "register_operand" ""))
10044 (match_operand 2 "const1_operand" ""))
10045 (const_string "alu")
10047 (const_string "ishift")))
10048 (set_attr "mode" "DI")])
10050 ;; Convert lea to the lea pattern to avoid flags dependency.
10052 [(set (match_operand:DI 0 "register_operand" "")
10053 (ashift:DI (match_operand:DI 1 "register_operand" "")
10054 (match_operand:QI 2 "immediate_operand" "")))
10055 (clobber (reg:CC 17))]
10058 && true_regnum (operands[0]) != true_regnum (operands[1])"
10059 [(set (match_dup 0)
10060 (mult:DI (match_dup 1)
10062 "operands[2] = GEN_INT (1 << INTVAL (operands[2]));")
10064 ;; This pattern can't accept a variable shift count, since shifts by
10065 ;; zero don't affect the flags. We assume that shifts by constant
10066 ;; zero are optimized away.
10067 (define_insn "*ashldi3_cmp_rex64"
10070 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10071 (match_operand:QI 2 "immediate_operand" "e"))
10073 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10074 (ashift:DI (match_dup 1) (match_dup 2)))]
10075 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10076 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10079 switch (get_attr_type (insn))
10082 if (operands[2] != const1_rtx)
10084 return \"add{q}\\t{%0, %0|%0, %0}\";
10087 if (REG_P (operands[2]))
10088 return \"sal{q}\\t{%b2, %0|%0, %b2}\";
10089 else if (GET_CODE (operands[2]) == CONST_INT
10090 && INTVAL (operands[2]) == 1
10091 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10092 return \"sal{q}\\t%0\";
10094 return \"sal{q}\\t{%2, %0|%0, %2}\";
10097 [(set (attr "type")
10098 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10100 (match_operand 0 "register_operand" ""))
10101 (match_operand 2 "const1_operand" ""))
10102 (const_string "alu")
10104 (const_string "ishift")))
10105 (set_attr "mode" "DI")])
10107 (define_insn "ashldi3_1"
10108 [(set (match_operand:DI 0 "register_operand" "=r")
10109 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10110 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10111 (clobber (match_scratch:SI 3 "=&r"))
10112 (clobber (reg:CC 17))]
10113 "!TARGET_64BIT && TARGET_CMOVE"
10115 [(set_attr "type" "multi")])
10117 (define_insn "*ashldi3_2"
10118 [(set (match_operand:DI 0 "register_operand" "=r")
10119 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10120 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10121 (clobber (reg:CC 17))]
10124 [(set_attr "type" "multi")])
10127 [(set (match_operand:DI 0 "register_operand" "")
10128 (ashift:DI (match_operand:DI 1 "register_operand" "")
10129 (match_operand:QI 2 "nonmemory_operand" "")))
10130 (clobber (match_scratch:SI 3 ""))
10131 (clobber (reg:CC 17))]
10132 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10134 "ix86_split_ashldi (operands, operands[3]); DONE;")
10137 [(set (match_operand:DI 0 "register_operand" "")
10138 (ashift:DI (match_operand:DI 1 "register_operand" "")
10139 (match_operand:QI 2 "nonmemory_operand" "")))
10140 (clobber (reg:CC 17))]
10141 "!TARGET_64BIT && reload_completed"
10143 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10145 (define_insn "x86_shld_1"
10146 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10147 (ior:SI (ashift:SI (match_dup 0)
10148 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10149 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10150 (minus:QI (const_int 32) (match_dup 2)))))
10151 (clobber (reg:CC 17))]
10154 shld{l}\\t{%2, %1, %0|%0, %1, %2}
10155 shld{l}\\t{%s2%1, %0|%0, %1, %2}"
10156 [(set_attr "type" "ishift")
10157 (set_attr "prefix_0f" "1")
10158 (set_attr "mode" "SI")
10159 (set_attr "pent_pair" "np")
10160 (set_attr "athlon_decode" "vector")
10161 (set_attr "ppro_uops" "few")])
10163 (define_expand "x86_shift_adj_1"
10165 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10168 (set (match_operand:SI 0 "register_operand" "")
10169 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10170 (match_operand:SI 1 "register_operand" "")
10173 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10174 (match_operand:SI 3 "register_operand" "r")
10179 (define_expand "x86_shift_adj_2"
10180 [(use (match_operand:SI 0 "register_operand" ""))
10181 (use (match_operand:SI 1 "register_operand" ""))
10182 (use (match_operand:QI 2 "register_operand" ""))]
10186 rtx label = gen_label_rtx ();
10189 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10191 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10192 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10193 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10194 gen_rtx_LABEL_REF (VOIDmode, label),
10196 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10197 JUMP_LABEL (tmp) = label;
10199 emit_move_insn (operands[0], operands[1]);
10200 emit_move_insn (operands[1], const0_rtx);
10202 emit_label (label);
10203 LABEL_NUSES (label) = 1;
10208 (define_expand "ashlsi3"
10209 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10210 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10211 (match_operand:QI 2 "nonmemory_operand" "")))
10212 (clobber (reg:CC 17))]
10214 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10216 (define_insn "*ashlsi3_1"
10217 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10218 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10219 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10220 (clobber (reg:CC 17))]
10221 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10224 switch (get_attr_type (insn))
10227 if (operands[2] != const1_rtx)
10229 if (!rtx_equal_p (operands[0], operands[1]))
10231 return \"add{l}\\t{%0, %0|%0, %0}\";
10237 if (REG_P (operands[2]))
10238 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
10239 else if (GET_CODE (operands[2]) == CONST_INT
10240 && INTVAL (operands[2]) == 1
10241 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10242 return \"sal{l}\\t%0\";
10244 return \"sal{l}\\t{%2, %0|%0, %2}\";
10247 [(set (attr "type")
10248 (cond [(eq_attr "alternative" "1")
10249 (const_string "lea")
10250 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10252 (match_operand 0 "register_operand" ""))
10253 (match_operand 2 "const1_operand" ""))
10254 (const_string "alu")
10256 (const_string "ishift")))
10257 (set_attr "mode" "SI")])
10259 ;; Convert lea to the lea pattern to avoid flags dependency.
10261 [(set (match_operand 0 "register_operand" "")
10262 (ashift (match_operand 1 "register_operand" "")
10263 (match_operand:QI 2 "const_int_operand" "")))
10264 (clobber (reg:CC 17))]
10266 && true_regnum (operands[0]) != true_regnum (operands[1])"
10271 operands[0] = gen_lowpart (SImode, operands[0]);
10272 operands[1] = gen_lowpart (Pmode, operands[1]);
10273 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
10274 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10275 if (Pmode != SImode)
10276 pat = gen_rtx_SUBREG (SImode, pat, 0);
10277 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10281 (define_insn "*ashlsi3_1_zext"
10282 [(set (match_operand:DI 0 "register_operand" "=r,r")
10283 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10284 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10285 (clobber (reg:CC 17))]
10286 "ix86_binary_operator_ok (ASHIFT, SImode, operands) && TARGET_64BIT"
10289 switch (get_attr_type (insn))
10292 if (operands[2] != const1_rtx)
10294 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10300 if (REG_P (operands[2]))
10301 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10302 else if (GET_CODE (operands[2]) == CONST_INT
10303 && INTVAL (operands[2]) == 1
10304 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10305 return \"sal{l}\\t%k0\";
10307 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10310 [(set (attr "type")
10311 (cond [(eq_attr "alternative" "1")
10312 (const_string "lea")
10313 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10315 (match_operand 2 "const1_operand" ""))
10316 (const_string "alu")
10318 (const_string "ishift")))
10319 (set_attr "mode" "SI")])
10321 ;; Convert lea to the lea pattern to avoid flags dependency.
10323 [(set (match_operand:DI 0 "register_operand" "")
10324 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10325 (match_operand:QI 2 "const_int_operand" ""))))
10326 (clobber (reg:CC 17))]
10328 && true_regnum (operands[0]) != true_regnum (operands[1])"
10329 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10332 operands[1] = gen_lowpart (Pmode, operands[1]);
10333 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
10336 ;; This pattern can't accept a variable shift count, since shifts by
10337 ;; zero don't affect the flags. We assume that shifts by constant
10338 ;; zero are optimized away.
10339 (define_insn "*ashlsi3_cmp"
10342 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10343 (match_operand:QI 2 "immediate_operand" "I"))
10345 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10346 (ashift:SI (match_dup 1) (match_dup 2)))]
10347 "ix86_match_ccmode (insn, CCGOCmode)
10348 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10351 switch (get_attr_type (insn))
10354 if (operands[2] != const1_rtx)
10356 return \"add{l}\\t{%0, %0|%0, %0}\";
10359 if (REG_P (operands[2]))
10360 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
10361 else if (GET_CODE (operands[2]) == CONST_INT
10362 && INTVAL (operands[2]) == 1
10363 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10364 return \"sal{l}\\t%0\";
10366 return \"sal{l}\\t{%2, %0|%0, %2}\";
10369 [(set (attr "type")
10370 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10372 (match_operand 0 "register_operand" ""))
10373 (match_operand 2 "const1_operand" ""))
10374 (const_string "alu")
10376 (const_string "ishift")))
10377 (set_attr "mode" "SI")])
10379 (define_insn "*ashlsi3_cmp_zext"
10382 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10383 (match_operand:QI 2 "immediate_operand" "I"))
10385 (set (match_operand:DI 0 "register_operand" "=r")
10386 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10387 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10388 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10391 switch (get_attr_type (insn))
10394 if (operands[2] != const1_rtx)
10396 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10399 if (REG_P (operands[2]))
10400 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10401 else if (GET_CODE (operands[2]) == CONST_INT
10402 && INTVAL (operands[2]) == 1
10403 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10404 return \"sal{l}\\t%k0\";
10406 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10409 [(set (attr "type")
10410 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10412 (match_operand 2 "const1_operand" ""))
10413 (const_string "alu")
10415 (const_string "ishift")))
10416 (set_attr "mode" "SI")])
10418 (define_expand "ashlhi3"
10419 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10420 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10421 (match_operand:QI 2 "nonmemory_operand" "")))
10422 (clobber (reg:CC 17))]
10423 "TARGET_HIMODE_MATH"
10424 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10426 (define_insn "*ashlhi3_1_lea"
10427 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10428 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10429 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10430 (clobber (reg:CC 17))]
10431 "!TARGET_PARTIAL_REG_STALL
10432 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10435 switch (get_attr_type (insn))
10440 if (operands[2] != const1_rtx)
10442 return \"add{w}\\t{%0, %0|%0, %0}\";
10445 if (REG_P (operands[2]))
10446 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10447 else if (GET_CODE (operands[2]) == CONST_INT
10448 && INTVAL (operands[2]) == 1
10449 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10450 return \"sal{w}\\t%0\";
10452 return \"sal{w}\\t{%2, %0|%0, %2}\";
10455 [(set (attr "type")
10456 (cond [(eq_attr "alternative" "1")
10457 (const_string "lea")
10458 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10460 (match_operand 0 "register_operand" ""))
10461 (match_operand 2 "const1_operand" ""))
10462 (const_string "alu")
10464 (const_string "ishift")))
10465 (set_attr "mode" "HI,SI")])
10467 (define_insn "*ashlhi3_1"
10468 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10469 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10470 (match_operand:QI 2 "nonmemory_operand" "cI")))
10471 (clobber (reg:CC 17))]
10472 "TARGET_PARTIAL_REG_STALL
10473 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10476 switch (get_attr_type (insn))
10479 if (operands[2] != const1_rtx)
10481 return \"add{w}\\t{%0, %0|%0, %0}\";
10484 if (REG_P (operands[2]))
10485 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10486 else if (GET_CODE (operands[2]) == CONST_INT
10487 && INTVAL (operands[2]) == 1
10488 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10489 return \"sal{w}\\t%0\";
10491 return \"sal{w}\\t{%2, %0|%0, %2}\";
10494 [(set (attr "type")
10495 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10497 (match_operand 0 "register_operand" ""))
10498 (match_operand 2 "const1_operand" ""))
10499 (const_string "alu")
10501 (const_string "ishift")))
10502 (set_attr "mode" "HI")])
10504 ;; This pattern can't accept a variable shift count, since shifts by
10505 ;; zero don't affect the flags. We assume that shifts by constant
10506 ;; zero are optimized away.
10507 (define_insn "*ashlhi3_cmp"
10510 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10511 (match_operand:QI 2 "immediate_operand" "I"))
10513 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10514 (ashift:HI (match_dup 1) (match_dup 2)))]
10515 "ix86_match_ccmode (insn, CCGOCmode)
10516 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10519 switch (get_attr_type (insn))
10522 if (operands[2] != const1_rtx)
10524 return \"add{w}\\t{%0, %0|%0, %0}\";
10527 if (REG_P (operands[2]))
10528 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
10529 else if (GET_CODE (operands[2]) == CONST_INT
10530 && INTVAL (operands[2]) == 1
10531 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10532 return \"sal{w}\\t%0\";
10534 return \"sal{w}\\t{%2, %0|%0, %2}\";
10537 [(set (attr "type")
10538 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10540 (match_operand 0 "register_operand" ""))
10541 (match_operand 2 "const1_operand" ""))
10542 (const_string "alu")
10544 (const_string "ishift")))
10545 (set_attr "mode" "HI")])
10547 (define_expand "ashlqi3"
10548 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10549 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10550 (match_operand:QI 2 "nonmemory_operand" "")))
10551 (clobber (reg:CC 17))]
10552 "TARGET_QIMODE_MATH"
10553 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10555 ;; %%% Potential partial reg stall on alternative 2. What to do?
10557 (define_insn "*ashlqi3_1_lea"
10558 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10559 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
10560 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10561 (clobber (reg:CC 17))]
10562 "!TARGET_PARTIAL_REG_STALL
10563 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10566 switch (get_attr_type (insn))
10571 if (operands[2] != const1_rtx)
10573 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10574 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10576 return \"add{b}\\t{%0, %0|%0, %0}\";
10579 if (REG_P (operands[2]))
10581 if (get_attr_mode (insn) == MODE_SI)
10582 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10584 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
10586 else if (GET_CODE (operands[2]) == CONST_INT
10587 && INTVAL (operands[2]) == 1
10588 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10590 if (get_attr_mode (insn) == MODE_SI)
10591 return \"sal{l}\\t%0\";
10593 return \"sal{b}\\t%0\";
10597 if (get_attr_mode (insn) == MODE_SI)
10598 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10600 return \"sal{b}\\t{%2, %0|%0, %2}\";
10604 [(set (attr "type")
10605 (cond [(eq_attr "alternative" "2")
10606 (const_string "lea")
10607 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10609 (match_operand 0 "register_operand" ""))
10610 (match_operand 2 "const1_operand" ""))
10611 (const_string "alu")
10613 (const_string "ishift")))
10614 (set_attr "mode" "QI,SI,SI")])
10616 (define_insn "*ashlqi3_1"
10617 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10618 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
10619 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
10620 (clobber (reg:CC 17))]
10621 "TARGET_PARTIAL_REG_STALL
10622 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10625 switch (get_attr_type (insn))
10628 if (operands[2] != const1_rtx)
10630 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10631 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
10633 return \"add{b}\\t{%0, %0|%0, %0}\";
10636 if (REG_P (operands[2]))
10638 if (get_attr_mode (insn) == MODE_SI)
10639 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
10641 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
10643 else if (GET_CODE (operands[2]) == CONST_INT
10644 && INTVAL (operands[2]) == 1
10645 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10647 if (get_attr_mode (insn) == MODE_SI)
10648 return \"sal{l}\\t%0\";
10650 return \"sal{b}\\t%0\";
10654 if (get_attr_mode (insn) == MODE_SI)
10655 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
10657 return \"sal{b}\\t{%2, %0|%0, %2}\";
10661 [(set (attr "type")
10662 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10664 (match_operand 0 "register_operand" ""))
10665 (match_operand 2 "const1_operand" ""))
10666 (const_string "alu")
10668 (const_string "ishift")))
10669 (set_attr "mode" "QI,SI")])
10671 ;; This pattern can't accept a variable shift count, since shifts by
10672 ;; zero don't affect the flags. We assume that shifts by constant
10673 ;; zero are optimized away.
10674 (define_insn "*ashlqi3_cmp"
10677 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
10678 (match_operand:QI 2 "immediate_operand" "I"))
10680 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10681 (ashift:QI (match_dup 1) (match_dup 2)))]
10682 "ix86_match_ccmode (insn, CCGOCmode)
10683 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10686 switch (get_attr_type (insn))
10689 if (operands[2] != const1_rtx)
10691 return \"add{b}\\t{%0, %0|%0, %0}\";
10694 if (REG_P (operands[2]))
10695 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
10696 else if (GET_CODE (operands[2]) == CONST_INT
10697 && INTVAL (operands[2]) == 1
10698 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
10699 return \"sal{b}\\t%0\";
10701 return \"sal{b}\\t{%2, %0|%0, %2}\";
10704 [(set (attr "type")
10705 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10707 (match_operand 0 "register_operand" ""))
10708 (match_operand 2 "const1_operand" ""))
10709 (const_string "alu")
10711 (const_string "ishift")))
10712 (set_attr "mode" "QI")])
10714 ;; See comment above `ashldi3' about how this works.
10716 (define_expand "ashrdi3"
10717 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10718 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
10719 (match_operand:QI 2 "nonmemory_operand" "")))
10720 (clobber (reg:CC 17))])]
10724 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10726 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
10729 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
10733 (define_insn "ashrdi3_63_rex64"
10734 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
10735 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
10736 (match_operand:DI 2 "const_int_operand" "i,i")))
10737 (clobber (reg:CC 17))]
10738 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
10739 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10742 sar{q}\\t{%2, %0|%0, %2}"
10743 [(set_attr "type" "imovx,ishift")
10744 (set_attr "prefix_0f" "0,*")
10745 (set_attr "length_immediate" "0,*")
10746 (set_attr "modrm" "0,1")
10747 (set_attr "mode" "DI")])
10749 (define_insn "*ashrdi3_1_one_bit_rex64"
10750 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10751 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10752 (match_operand:QI 2 "const_int_1_operand" "")))
10753 (clobber (reg:CC 17))]
10754 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
10755 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
10757 [(set_attr "type" "ishift")
10758 (set (attr "length")
10759 (if_then_else (match_operand:DI 0 "register_operand" "")
10761 (const_string "*")))])
10763 (define_insn "*ashrdi3_1_rex64"
10764 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
10765 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
10766 (match_operand:QI 2 "nonmemory_operand" "n,c")))
10767 (clobber (reg:CC 17))]
10768 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10770 sar{q}\\t{%2, %0|%0, %2}
10771 sar{q}\\t{%b2, %0|%0, %b2}"
10772 [(set_attr "type" "ishift")
10773 (set_attr "mode" "DI")])
10775 ;; This pattern can't accept a variable shift count, since shifts by
10776 ;; zero don't affect the flags. We assume that shifts by constant
10777 ;; zero are optimized away.
10778 (define_insn "*ashrdi3_one_bit_cmp_rex64"
10781 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10782 (match_operand:QI 2 "const_int_1_operand" ""))
10784 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10785 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10786 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10787 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
10788 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10790 [(set_attr "type" "ishift")
10791 (set (attr "length")
10792 (if_then_else (match_operand:DI 0 "register_operand" "")
10794 (const_string "*")))])
10796 ;; This pattern can't accept a variable shift count, since shifts by
10797 ;; zero don't affect the flags. We assume that shifts by constant
10798 ;; zero are optimized away.
10799 (define_insn "*ashrdi3_cmp_rex64"
10802 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10803 (match_operand:QI 2 "const_int_operand" "n"))
10805 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10806 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10807 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10808 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10809 "sar{q}\\t{%2, %0|%0, %2}"
10810 [(set_attr "type" "ishift")
10811 (set_attr "mode" "DI")])
10814 (define_insn "ashrdi3_1"
10815 [(set (match_operand:DI 0 "register_operand" "=r")
10816 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
10817 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10818 (clobber (match_scratch:SI 3 "=&r"))
10819 (clobber (reg:CC 17))]
10820 "!TARGET_64BIT && TARGET_CMOVE"
10822 [(set_attr "type" "multi")])
10824 (define_insn "*ashrdi3_2"
10825 [(set (match_operand:DI 0 "register_operand" "=r")
10826 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
10827 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10828 (clobber (reg:CC 17))]
10831 [(set_attr "type" "multi")])
10834 [(set (match_operand:DI 0 "register_operand" "")
10835 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10836 (match_operand:QI 2 "nonmemory_operand" "")))
10837 (clobber (match_scratch:SI 3 ""))
10838 (clobber (reg:CC 17))]
10839 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10841 "ix86_split_ashrdi (operands, operands[3]); DONE;")
10844 [(set (match_operand:DI 0 "register_operand" "")
10845 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10846 (match_operand:QI 2 "nonmemory_operand" "")))
10847 (clobber (reg:CC 17))]
10848 "!TARGET_64BIT && reload_completed"
10850 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
10852 (define_insn "x86_shrd_1"
10853 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10854 (ior:SI (ashiftrt:SI (match_dup 0)
10855 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10856 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
10857 (minus:QI (const_int 32) (match_dup 2)))))
10858 (clobber (reg:CC 17))]
10861 shrd{l}\\t{%2, %1, %0|%0, %1, %2}
10862 shrd{l}\\t{%s2%1, %0|%0, %1, %2}"
10863 [(set_attr "type" "ishift")
10864 (set_attr "prefix_0f" "1")
10865 (set_attr "pent_pair" "np")
10866 (set_attr "ppro_uops" "few")
10867 (set_attr "mode" "SI")])
10869 (define_expand "x86_shift_adj_3"
10870 [(use (match_operand:SI 0 "register_operand" ""))
10871 (use (match_operand:SI 1 "register_operand" ""))
10872 (use (match_operand:QI 2 "register_operand" ""))]
10876 rtx label = gen_label_rtx ();
10879 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10881 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10882 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10883 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10884 gen_rtx_LABEL_REF (VOIDmode, label),
10886 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10887 JUMP_LABEL (tmp) = label;
10889 emit_move_insn (operands[0], operands[1]);
10890 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
10892 emit_label (label);
10893 LABEL_NUSES (label) = 1;
10898 (define_insn "ashrsi3_31"
10899 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
10900 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
10901 (match_operand:SI 2 "const_int_operand" "i,i")))
10902 (clobber (reg:CC 17))]
10903 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
10904 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
10907 sar{l}\\t{%2, %0|%0, %2}"
10908 [(set_attr "type" "imovx,ishift")
10909 (set_attr "prefix_0f" "0,*")
10910 (set_attr "length_immediate" "0,*")
10911 (set_attr "modrm" "0,1")
10912 (set_attr "mode" "SI")])
10914 (define_insn "*ashrsi3_31_zext"
10915 [(set (match_operand:DI 0 "register_operand" "=*d,r")
10916 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
10917 (match_operand:SI 2 "const_int_operand" "i,i"))))
10918 (clobber (reg:CC 17))]
10919 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
10920 && TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
10923 sar{l}\\t{%2, %k0|%k0, %2}"
10924 [(set_attr "type" "imovx,ishift")
10925 (set_attr "prefix_0f" "0,*")
10926 (set_attr "length_immediate" "0,*")
10927 (set_attr "modrm" "0,1")
10928 (set_attr "mode" "SI")])
10930 (define_expand "ashrsi3"
10931 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10932 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
10933 (match_operand:QI 2 "nonmemory_operand" "")))
10934 (clobber (reg:CC 17))]
10936 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
10938 (define_insn "*ashrsi3_1_one_bit"
10939 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10940 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10941 (match_operand:QI 2 "const_int_1_operand" "")))
10942 (clobber (reg:CC 17))]
10943 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
10944 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
10946 [(set_attr "type" "ishift")
10947 (set (attr "length")
10948 (if_then_else (match_operand:SI 0 "register_operand" "")
10950 (const_string "*")))])
10952 (define_insn "*ashrsi3_1_one_bit_zext"
10953 [(set (match_operand:DI 0 "register_operand" "=r")
10954 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
10955 (match_operand:QI 2 "const_int_1_operand" ""))))
10956 (clobber (reg:CC 17))]
10957 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
10958 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
10960 [(set_attr "type" "ishift")
10961 (set_attr "length" "2")])
10963 (define_insn "*ashrsi3_1"
10964 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
10965 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
10966 (match_operand:QI 2 "nonmemory_operand" "I,c")))
10967 (clobber (reg:CC 17))]
10968 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
10970 sar{l}\\t{%2, %0|%0, %2}
10971 sar{l}\\t{%b2, %0|%0, %b2}"
10972 [(set_attr "type" "ishift")
10973 (set_attr "mode" "SI")])
10975 (define_insn "*ashrsi3_1_zext"
10976 [(set (match_operand:DI 0 "register_operand" "=r,r")
10977 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
10978 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
10979 (clobber (reg:CC 17))]
10980 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
10982 sar{l}\\t{%2, %k0|%k0, %2}
10983 sar{l}\\t{%b2, %k0|%k0, %b2}"
10984 [(set_attr "type" "ishift")
10985 (set_attr "mode" "SI")])
10987 ;; This pattern can't accept a variable shift count, since shifts by
10988 ;; zero don't affect the flags. We assume that shifts by constant
10989 ;; zero are optimized away.
10990 (define_insn "*ashrsi3_one_bit_cmp"
10993 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10994 (match_operand:QI 2 "const_int_1_operand" ""))
10996 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10997 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
10998 "ix86_match_ccmode (insn, CCGOCmode)
10999 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11000 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11002 [(set_attr "type" "ishift")
11003 (set (attr "length")
11004 (if_then_else (match_operand:SI 0 "register_operand" "")
11006 (const_string "*")))])
11008 (define_insn "*ashrsi3_one_bit_cmp_zext"
11011 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11012 (match_operand:QI 2 "const_int_1_operand" ""))
11014 (set (match_operand:DI 0 "register_operand" "=r")
11015 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11016 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11017 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11018 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11020 [(set_attr "type" "ishift")
11021 (set_attr "length" "2")])
11023 ;; This pattern can't accept a variable shift count, since shifts by
11024 ;; zero don't affect the flags. We assume that shifts by constant
11025 ;; zero are optimized away.
11026 (define_insn "*ashrsi3_cmp"
11029 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11030 (match_operand:QI 2 "immediate_operand" "I"))
11032 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11033 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11034 "ix86_match_ccmode (insn, CCGOCmode)
11035 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11036 "sar{l}\\t{%2, %0|%0, %2}"
11037 [(set_attr "type" "ishift")
11038 (set_attr "mode" "SI")])
11040 (define_insn "*ashrsi3_cmp_zext"
11043 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11044 (match_operand:QI 2 "immediate_operand" "I"))
11046 (set (match_operand:DI 0 "register_operand" "=r")
11047 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11048 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11049 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11050 "sar{l}\\t{%2, %k0|%k0, %2}"
11051 [(set_attr "type" "ishift")
11052 (set_attr "mode" "SI")])
11054 (define_expand "ashrhi3"
11055 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11056 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11057 (match_operand:QI 2 "nonmemory_operand" "")))
11058 (clobber (reg:CC 17))]
11059 "TARGET_HIMODE_MATH"
11060 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11062 (define_insn "*ashrhi3_1_one_bit"
11063 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11064 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11065 (match_operand:QI 2 "const_int_1_operand" "")))
11066 (clobber (reg:CC 17))]
11067 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11068 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11070 [(set_attr "type" "ishift")
11071 (set (attr "length")
11072 (if_then_else (match_operand 0 "register_operand" "")
11074 (const_string "*")))])
11076 (define_insn "*ashrhi3_1"
11077 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11078 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11079 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11080 (clobber (reg:CC 17))]
11081 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11083 sar{w}\\t{%2, %0|%0, %2}
11084 sar{w}\\t{%b2, %0|%0, %b2}"
11085 [(set_attr "type" "ishift")
11086 (set_attr "mode" "HI")])
11088 ;; This pattern can't accept a variable shift count, since shifts by
11089 ;; zero don't affect the flags. We assume that shifts by constant
11090 ;; zero are optimized away.
11091 (define_insn "*ashrhi3_one_bit_cmp"
11094 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11095 (match_operand:QI 2 "const_int_1_operand" ""))
11097 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11098 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11099 "ix86_match_ccmode (insn, CCGOCmode)
11100 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11101 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11103 [(set_attr "type" "ishift")
11104 (set (attr "length")
11105 (if_then_else (match_operand 0 "register_operand" "")
11107 (const_string "*")))])
11109 ;; This pattern can't accept a variable shift count, since shifts by
11110 ;; zero don't affect the flags. We assume that shifts by constant
11111 ;; zero are optimized away.
11112 (define_insn "*ashrhi3_cmp"
11115 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11116 (match_operand:QI 2 "immediate_operand" "I"))
11118 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11119 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11120 "ix86_match_ccmode (insn, CCGOCmode)
11121 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11122 "sar{w}\\t{%2, %0|%0, %2}"
11123 [(set_attr "type" "ishift")
11124 (set_attr "mode" "HI")])
11126 (define_expand "ashrqi3"
11127 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11128 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11129 (match_operand:QI 2 "nonmemory_operand" "")))
11130 (clobber (reg:CC 17))]
11131 "TARGET_QIMODE_MATH"
11132 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11134 (define_insn "*ashrqi3_1_one_bit"
11135 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11136 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11137 (match_operand:QI 2 "const_int_1_operand" "")))
11138 (clobber (reg:CC 17))]
11139 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11140 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11142 [(set_attr "type" "ishift")
11143 (set (attr "length")
11144 (if_then_else (match_operand 0 "register_operand" "")
11146 (const_string "*")))])
11148 (define_insn "*ashrqi3_1"
11149 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11150 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11151 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11152 (clobber (reg:CC 17))]
11153 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11155 sar{b}\\t{%2, %0|%0, %2}
11156 sar{b}\\t{%b2, %0|%0, %b2}"
11157 [(set_attr "type" "ishift")
11158 (set_attr "mode" "QI")])
11160 ;; This pattern can't accept a variable shift count, since shifts by
11161 ;; zero don't affect the flags. We assume that shifts by constant
11162 ;; zero are optimized away.
11163 (define_insn "*ashrqi3_one_bit_cmp"
11166 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11167 (match_operand:QI 2 "const_int_1_operand" "I"))
11169 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11170 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11171 "ix86_match_ccmode (insn, CCGOCmode)
11172 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11173 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11175 [(set_attr "type" "ishift")
11176 (set (attr "length")
11177 (if_then_else (match_operand 0 "register_operand" "")
11179 (const_string "*")))])
11181 ;; This pattern can't accept a variable shift count, since shifts by
11182 ;; zero don't affect the flags. We assume that shifts by constant
11183 ;; zero are optimized away.
11184 (define_insn "*ashrqi3_cmp"
11187 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11188 (match_operand:QI 2 "immediate_operand" "I"))
11190 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
11191 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11192 "ix86_match_ccmode (insn, CCGOCmode)
11193 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11194 "sar{b}\\t{%2, %0|%0, %2}"
11195 [(set_attr "type" "ishift")
11196 (set_attr "mode" "QI")])
11198 ;; Logical shift instructions
11200 ;; See comment above `ashldi3' about how this works.
11202 (define_expand "lshrdi3"
11203 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11204 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11205 (match_operand:QI 2 "nonmemory_operand" "")))
11206 (clobber (reg:CC 17))])]
11210 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11212 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11215 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11219 (define_insn "*lshrdi3_1_one_bit_rex64"
11220 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11221 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11222 (match_operand:QI 2 "const_int_1_operand" "")))
11223 (clobber (reg:CC 17))]
11224 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11225 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11227 [(set_attr "type" "ishift")
11228 (set (attr "length")
11229 (if_then_else (match_operand:DI 0 "register_operand" "")
11231 (const_string "*")))])
11233 (define_insn "*lshrdi3_1_rex64"
11234 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11235 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11236 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11237 (clobber (reg:CC 17))]
11238 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11240 shr{q}\\t{%2, %0|%0, %2}
11241 shr{q}\\t{%b2, %0|%0, %b2}"
11242 [(set_attr "type" "ishift")
11243 (set_attr "mode" "DI")])
11245 ;; This pattern can't accept a variable shift count, since shifts by
11246 ;; zero don't affect the flags. We assume that shifts by constant
11247 ;; zero are optimized away.
11248 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11251 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11252 (match_operand:QI 2 "const_int_1_operand" ""))
11254 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11255 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11256 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11257 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11258 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11260 [(set_attr "type" "ishift")
11261 (set (attr "length")
11262 (if_then_else (match_operand:DI 0 "register_operand" "")
11264 (const_string "*")))])
11266 ;; This pattern can't accept a variable shift count, since shifts by
11267 ;; zero don't affect the flags. We assume that shifts by constant
11268 ;; zero are optimized away.
11269 (define_insn "*lshrdi3_cmp_rex64"
11272 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11273 (match_operand:QI 2 "const_int_operand" "e"))
11275 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11276 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11277 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11278 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11279 "shr{q}\\t{%2, %0|%0, %2}"
11280 [(set_attr "type" "ishift")
11281 (set_attr "mode" "DI")])
11283 (define_insn "lshrdi3_1"
11284 [(set (match_operand:DI 0 "register_operand" "=r")
11285 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11286 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11287 (clobber (match_scratch:SI 3 "=&r"))
11288 (clobber (reg:CC 17))]
11289 "!TARGET_64BIT && TARGET_CMOVE"
11291 [(set_attr "type" "multi")])
11293 (define_insn "*lshrdi3_2"
11294 [(set (match_operand:DI 0 "register_operand" "=r")
11295 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11296 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11297 (clobber (reg:CC 17))]
11300 [(set_attr "type" "multi")])
11303 [(set (match_operand:DI 0 "register_operand" "")
11304 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11305 (match_operand:QI 2 "nonmemory_operand" "")))
11306 (clobber (match_scratch:SI 3 ""))
11307 (clobber (reg:CC 17))]
11308 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11310 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11313 [(set (match_operand:DI 0 "register_operand" "")
11314 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11315 (match_operand:QI 2 "nonmemory_operand" "")))
11316 (clobber (reg:CC 17))]
11317 "!TARGET_64BIT && reload_completed"
11319 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11321 (define_expand "lshrsi3"
11322 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11323 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11324 (match_operand:QI 2 "nonmemory_operand" "")))
11325 (clobber (reg:CC 17))]
11327 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11329 (define_insn "*lshrsi3_1_one_bit"
11330 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11331 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11332 (match_operand:QI 2 "const_int_1_operand" "")))
11333 (clobber (reg:CC 17))]
11334 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11335 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11337 [(set_attr "type" "ishift")
11338 (set (attr "length")
11339 (if_then_else (match_operand:SI 0 "register_operand" "")
11341 (const_string "*")))])
11343 (define_insn "*lshrsi3_1_one_bit_zext"
11344 [(set (match_operand:DI 0 "register_operand" "=r")
11345 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11346 (match_operand:QI 2 "const_int_1_operand" "")))
11347 (clobber (reg:CC 17))]
11348 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11349 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11351 [(set_attr "type" "ishift")
11352 (set_attr "length" "2")])
11354 (define_insn "*lshrsi3_1"
11355 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11356 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11357 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11358 (clobber (reg:CC 17))]
11359 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11361 shr{l}\\t{%2, %0|%0, %2}
11362 shr{l}\\t{%b2, %0|%0, %b2}"
11363 [(set_attr "type" "ishift")
11364 (set_attr "mode" "SI")])
11366 (define_insn "*lshrsi3_1_zext"
11367 [(set (match_operand:DI 0 "register_operand" "=r,r")
11369 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11370 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11371 (clobber (reg:CC 17))]
11372 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11374 shr{l}\\t{%2, %k0|%k0, %2}
11375 shr{l}\\t{%b2, %k0|%k0, %b2}"
11376 [(set_attr "type" "ishift")
11377 (set_attr "mode" "SI")])
11379 ;; This pattern can't accept a variable shift count, since shifts by
11380 ;; zero don't affect the flags. We assume that shifts by constant
11381 ;; zero are optimized away.
11382 (define_insn "*lshrsi3_one_bit_cmp"
11385 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11386 (match_operand:QI 2 "const_int_1_operand" ""))
11388 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11389 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11390 "ix86_match_ccmode (insn, CCGOCmode)
11391 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11392 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11394 [(set_attr "type" "ishift")
11395 (set (attr "length")
11396 (if_then_else (match_operand:SI 0 "register_operand" "")
11398 (const_string "*")))])
11400 (define_insn "*lshrsi3_cmp_one_bit_zext"
11403 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11404 (match_operand:QI 2 "const_int_1_operand" ""))
11406 (set (match_operand:DI 0 "register_operand" "=r")
11407 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11408 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11409 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11410 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11412 [(set_attr "type" "ishift")
11413 (set_attr "length" "2")])
11415 ;; This pattern can't accept a variable shift count, since shifts by
11416 ;; zero don't affect the flags. We assume that shifts by constant
11417 ;; zero are optimized away.
11418 (define_insn "*lshrsi3_cmp"
11421 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11422 (match_operand:QI 2 "immediate_operand" "I"))
11424 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11425 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11426 "ix86_match_ccmode (insn, CCGOCmode)
11427 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11428 "shr{l}\\t{%2, %0|%0, %2}"
11429 [(set_attr "type" "ishift")
11430 (set_attr "mode" "SI")])
11432 (define_insn "*lshrsi3_cmp_zext"
11435 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11436 (match_operand:QI 2 "immediate_operand" "I"))
11438 (set (match_operand:DI 0 "register_operand" "=r")
11439 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11440 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11441 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11442 "shr{l}\\t{%2, %k0|%k0, %2}"
11443 [(set_attr "type" "ishift")
11444 (set_attr "mode" "SI")])
11446 (define_expand "lshrhi3"
11447 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11448 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11449 (match_operand:QI 2 "nonmemory_operand" "")))
11450 (clobber (reg:CC 17))]
11451 "TARGET_HIMODE_MATH"
11452 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11454 (define_insn "*lshrhi3_1_one_bit"
11455 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11456 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11457 (match_operand:QI 2 "const_int_1_operand" "")))
11458 (clobber (reg:CC 17))]
11459 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11460 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11462 [(set_attr "type" "ishift")
11463 (set (attr "length")
11464 (if_then_else (match_operand 0 "register_operand" "")
11466 (const_string "*")))])
11468 (define_insn "*lshrhi3_1"
11469 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11470 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11471 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11472 (clobber (reg:CC 17))]
11473 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11475 shr{w}\\t{%2, %0|%0, %2}
11476 shr{w}\\t{%b2, %0|%0, %b2}"
11477 [(set_attr "type" "ishift")
11478 (set_attr "mode" "HI")])
11480 ;; This pattern can't accept a variable shift count, since shifts by
11481 ;; zero don't affect the flags. We assume that shifts by constant
11482 ;; zero are optimized away.
11483 (define_insn "*lshrhi3_one_bit_cmp"
11486 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11487 (match_operand:QI 2 "const_int_1_operand" ""))
11489 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11490 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11491 "ix86_match_ccmode (insn, CCGOCmode)
11492 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11493 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11495 [(set_attr "type" "ishift")
11496 (set (attr "length")
11497 (if_then_else (match_operand:SI 0 "register_operand" "")
11499 (const_string "*")))])
11501 ;; This pattern can't accept a variable shift count, since shifts by
11502 ;; zero don't affect the flags. We assume that shifts by constant
11503 ;; zero are optimized away.
11504 (define_insn "*lshrhi3_cmp"
11507 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11508 (match_operand:QI 2 "immediate_operand" "I"))
11510 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11511 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11512 "ix86_match_ccmode (insn, CCGOCmode)
11513 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11514 "shr{w}\\t{%2, %0|%0, %2}"
11515 [(set_attr "type" "ishift")
11516 (set_attr "mode" "HI")])
11518 (define_expand "lshrqi3"
11519 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11520 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11521 (match_operand:QI 2 "nonmemory_operand" "")))
11522 (clobber (reg:CC 17))]
11523 "TARGET_QIMODE_MATH"
11524 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11526 (define_insn "*lshrqi3_1_one_bit"
11527 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11528 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11529 (match_operand:QI 2 "const_int_1_operand" "")))
11530 (clobber (reg:CC 17))]
11531 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11532 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11534 [(set_attr "type" "ishift")
11535 (set (attr "length")
11536 (if_then_else (match_operand 0 "register_operand" "")
11538 (const_string "*")))])
11540 (define_insn "*lshrqi3_1"
11541 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11542 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11543 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11544 (clobber (reg:CC 17))]
11545 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11547 shr{b}\\t{%2, %0|%0, %2}
11548 shr{b}\\t{%b2, %0|%0, %b2}"
11549 [(set_attr "type" "ishift")
11550 (set_attr "mode" "QI")])
11552 ;; This pattern can't accept a variable shift count, since shifts by
11553 ;; zero don't affect the flags. We assume that shifts by constant
11554 ;; zero are optimized away.
11555 (define_insn "*lshrqi2_one_bit_cmp"
11558 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11559 (match_operand:QI 2 "const_int_1_operand" ""))
11561 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11562 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11563 "ix86_match_ccmode (insn, CCGOCmode)
11564 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
11565 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11567 [(set_attr "type" "ishift")
11568 (set (attr "length")
11569 (if_then_else (match_operand:SI 0 "register_operand" "")
11571 (const_string "*")))])
11573 ;; This pattern can't accept a variable shift count, since shifts by
11574 ;; zero don't affect the flags. We assume that shifts by constant
11575 ;; zero are optimized away.
11576 (define_insn "*lshrqi2_cmp"
11579 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11580 (match_operand:QI 2 "immediate_operand" "I"))
11582 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11583 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11584 "ix86_match_ccmode (insn, CCGOCmode)
11585 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11586 "shr{b}\\t{%2, %0|%0, %2}"
11587 [(set_attr "type" "ishift")
11588 (set_attr "mode" "QI")])
11590 ;; Rotate instructions
11592 (define_expand "rotldi3"
11593 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11594 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
11595 (match_operand:QI 2 "nonmemory_operand" "")))
11596 (clobber (reg:CC 17))]
11598 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
11600 (define_insn "*rotlsi3_1_one_bit_rex64"
11601 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11602 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11603 (match_operand:QI 2 "const_int_1_operand" "")))
11604 (clobber (reg:CC 17))]
11605 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
11606 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11608 [(set_attr "type" "ishift")
11609 (set (attr "length")
11610 (if_then_else (match_operand:DI 0 "register_operand" "")
11612 (const_string "*")))])
11614 (define_insn "*rotldi3_1_rex64"
11615 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11616 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11617 (match_operand:QI 2 "nonmemory_operand" "e,c")))
11618 (clobber (reg:CC 17))]
11619 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
11621 rol{q}\\t{%2, %0|%0, %2}
11622 rol{q}\\t{%b2, %0|%0, %b2}"
11623 [(set_attr "type" "ishift")
11624 (set_attr "mode" "DI")])
11626 (define_expand "rotlsi3"
11627 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11628 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
11629 (match_operand:QI 2 "nonmemory_operand" "")))
11630 (clobber (reg:CC 17))]
11632 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
11634 (define_insn "*rotlsi3_1_one_bit"
11635 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11636 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11637 (match_operand:QI 2 "const_int_1_operand" "")))
11638 (clobber (reg:CC 17))]
11639 "ix86_binary_operator_ok (ROTATE, SImode, operands)
11640 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11642 [(set_attr "type" "ishift")
11643 (set (attr "length")
11644 (if_then_else (match_operand:SI 0 "register_operand" "")
11646 (const_string "*")))])
11648 (define_insn "*rotlsi3_1_one_bit_zext"
11649 [(set (match_operand:DI 0 "register_operand" "=r")
11651 (rotate:SI (match_operand:SI 1 "register_operand" "0")
11652 (match_operand:QI 2 "const_int_1_operand" ""))))
11653 (clobber (reg:CC 17))]
11654 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
11655 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11657 [(set_attr "type" "ishift")
11658 (set_attr "length" "2")])
11660 (define_insn "*rotlsi3_1"
11661 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11662 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11663 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11664 (clobber (reg:CC 17))]
11665 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
11667 rol{l}\\t{%2, %0|%0, %2}
11668 rol{l}\\t{%b2, %0|%0, %b2}"
11669 [(set_attr "type" "ishift")
11670 (set_attr "mode" "SI")])
11672 (define_insn "*rotlsi3_1_zext"
11673 [(set (match_operand:DI 0 "register_operand" "=r,r")
11675 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
11676 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11677 (clobber (reg:CC 17))]
11678 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
11680 rol{l}\\t{%2, %k0|%k0, %2}
11681 rol{l}\\t{%b2, %k0|%k0, %b2}"
11682 [(set_attr "type" "ishift")
11683 (set_attr "mode" "SI")])
11685 (define_expand "rotlhi3"
11686 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11687 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
11688 (match_operand:QI 2 "nonmemory_operand" "")))
11689 (clobber (reg:CC 17))]
11690 "TARGET_HIMODE_MATH"
11691 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
11693 (define_insn "*rotlhi3_1_one_bit"
11694 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11695 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11696 (match_operand:QI 2 "const_int_1_operand" "")))
11697 (clobber (reg:CC 17))]
11698 "ix86_binary_operator_ok (ROTATE, HImode, operands)
11699 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11701 [(set_attr "type" "ishift")
11702 (set (attr "length")
11703 (if_then_else (match_operand 0 "register_operand" "")
11705 (const_string "*")))])
11707 (define_insn "*rotlhi3_1"
11708 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11709 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11710 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11711 (clobber (reg:CC 17))]
11712 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
11714 rol{w}\\t{%2, %0|%0, %2}
11715 rol{w}\\t{%b2, %0|%0, %b2}"
11716 [(set_attr "type" "ishift")
11717 (set_attr "mode" "HI")])
11719 (define_expand "rotlqi3"
11720 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11721 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
11722 (match_operand:QI 2 "nonmemory_operand" "")))
11723 (clobber (reg:CC 17))]
11724 "TARGET_QIMODE_MATH"
11725 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
11727 (define_insn "*rotlqi3_1_one_bit"
11728 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11729 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11730 (match_operand:QI 2 "const_int_1_operand" "")))
11731 (clobber (reg:CC 17))]
11732 "ix86_binary_operator_ok (ROTATE, QImode, operands)
11733 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11735 [(set_attr "type" "ishift")
11736 (set (attr "length")
11737 (if_then_else (match_operand 0 "register_operand" "")
11739 (const_string "*")))])
11741 (define_insn "*rotlqi3_1"
11742 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11743 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11744 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11745 (clobber (reg:CC 17))]
11746 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
11748 rol{b}\\t{%2, %0|%0, %2}
11749 rol{b}\\t{%b2, %0|%0, %b2}"
11750 [(set_attr "type" "ishift")
11751 (set_attr "mode" "QI")])
11753 (define_expand "rotrdi3"
11754 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11755 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
11756 (match_operand:QI 2 "nonmemory_operand" "")))
11757 (clobber (reg:CC 17))]
11759 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
11761 (define_insn "*rotrdi3_1_one_bit_rex64"
11762 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11763 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11764 (match_operand:QI 2 "const_int_1_operand" "")))
11765 (clobber (reg:CC 17))]
11766 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
11767 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11769 [(set_attr "type" "ishift")
11770 (set (attr "length")
11771 (if_then_else (match_operand:DI 0 "register_operand" "")
11773 (const_string "*")))])
11775 (define_insn "*rotrdi3_1_rex64"
11776 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11777 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11778 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11779 (clobber (reg:CC 17))]
11780 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
11782 ror{q}\\t{%2, %0|%0, %2}
11783 ror{q}\\t{%b2, %0|%0, %b2}"
11784 [(set_attr "type" "ishift")
11785 (set_attr "mode" "DI")])
11787 (define_expand "rotrsi3"
11788 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11789 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
11790 (match_operand:QI 2 "nonmemory_operand" "")))
11791 (clobber (reg:CC 17))]
11793 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
11795 (define_insn "*rotrsi3_1_one_bit"
11796 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11797 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11798 (match_operand:QI 2 "const_int_1_operand" "")))
11799 (clobber (reg:CC 17))]
11800 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
11801 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11803 [(set_attr "type" "ishift")
11804 (set (attr "length")
11805 (if_then_else (match_operand:SI 0 "register_operand" "")
11807 (const_string "*")))])
11809 (define_insn "*rotrsi3_1_one_bit_zext"
11810 [(set (match_operand:DI 0 "register_operand" "=r")
11812 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
11813 (match_operand:QI 2 "const_int_1_operand" ""))))
11814 (clobber (reg:CC 17))]
11815 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
11816 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11818 [(set_attr "type" "ishift")
11819 (set (attr "length")
11820 (if_then_else (match_operand:SI 0 "register_operand" "")
11822 (const_string "*")))])
11824 (define_insn "*rotrsi3_1"
11825 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11826 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11827 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11828 (clobber (reg:CC 17))]
11829 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
11831 ror{l}\\t{%2, %0|%0, %2}
11832 ror{l}\\t{%b2, %0|%0, %b2}"
11833 [(set_attr "type" "ishift")
11834 (set_attr "mode" "SI")])
11836 (define_insn "*rotrsi3_1_zext"
11837 [(set (match_operand:DI 0 "register_operand" "=r,r")
11839 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
11840 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11841 (clobber (reg:CC 17))]
11842 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
11844 ror{l}\\t{%2, %k0|%k0, %2}
11845 ror{l}\\t{%b2, %k0|%k0, %b2}"
11846 [(set_attr "type" "ishift")
11847 (set_attr "mode" "SI")])
11849 (define_expand "rotrhi3"
11850 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11851 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
11852 (match_operand:QI 2 "nonmemory_operand" "")))
11853 (clobber (reg:CC 17))]
11854 "TARGET_HIMODE_MATH"
11855 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
11857 (define_insn "*rotrhi3_one_bit"
11858 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11859 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11860 (match_operand:QI 2 "const_int_1_operand" "")))
11861 (clobber (reg:CC 17))]
11862 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
11863 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11865 [(set_attr "type" "ishift")
11866 (set (attr "length")
11867 (if_then_else (match_operand 0 "register_operand" "")
11869 (const_string "*")))])
11871 (define_insn "*rotrhi3"
11872 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11873 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11874 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11875 (clobber (reg:CC 17))]
11876 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
11878 ror{w}\\t{%2, %0|%0, %2}
11879 ror{w}\\t{%b2, %0|%0, %b2}"
11880 [(set_attr "type" "ishift")
11881 (set_attr "mode" "HI")])
11883 (define_expand "rotrqi3"
11884 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11885 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
11886 (match_operand:QI 2 "nonmemory_operand" "")))
11887 (clobber (reg:CC 17))]
11888 "TARGET_QIMODE_MATH"
11889 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
11891 (define_insn "*rotrqi3_1_one_bit"
11892 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11893 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11894 (match_operand:QI 2 "const_int_1_operand" "")))
11895 (clobber (reg:CC 17))]
11896 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
11897 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
11899 [(set_attr "type" "ishift")
11900 (set (attr "length")
11901 (if_then_else (match_operand 0 "register_operand" "")
11903 (const_string "*")))])
11905 (define_insn "*rotrqi3_1"
11906 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11907 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11908 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11909 (clobber (reg:CC 17))]
11910 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
11912 ror{b}\\t{%2, %0|%0, %2}
11913 ror{b}\\t{%b2, %0|%0, %b2}"
11914 [(set_attr "type" "ishift")
11915 (set_attr "mode" "QI")])
11917 ;; Bit set / bit test instructions
11919 (define_expand "extv"
11920 [(set (match_operand:SI 0 "register_operand" "")
11921 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
11922 (match_operand:SI 2 "immediate_operand" "")
11923 (match_operand:SI 3 "immediate_operand" "")))]
11927 /* Handle extractions from %ah et al. */
11928 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
11931 /* From mips.md: extract_bit_field doesn't verify that our source
11932 matches the predicate, so check it again here. */
11933 if (! register_operand (operands[1], VOIDmode))
11937 (define_expand "extzv"
11938 [(set (match_operand:SI 0 "register_operand" "")
11939 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
11940 (match_operand:SI 2 "immediate_operand" "")
11941 (match_operand:SI 3 "immediate_operand" "")))]
11945 /* Handle extractions from %ah et al. */
11946 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
11949 /* From mips.md: extract_bit_field doesn't verify that our source
11950 matches the predicate, so check it again here. */
11951 if (! register_operand (operands[1], VOIDmode))
11955 (define_expand "insv"
11956 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
11957 (match_operand:SI 1 "immediate_operand" "")
11958 (match_operand:SI 2 "immediate_operand" ""))
11959 (match_operand:SI 3 "register_operand" ""))]
11963 /* Handle extractions from %ah et al. */
11964 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
11967 /* From mips.md: insert_bit_field doesn't verify that our source
11968 matches the predicate, so check it again here. */
11969 if (! register_operand (operands[0], VOIDmode))
11973 ;; %%% bts, btr, btc, bt.
11975 ;; Store-flag instructions.
11977 ;; For all sCOND expanders, also expand the compare or test insn that
11978 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
11980 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
11981 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
11982 ;; way, which can later delete the movzx if only QImode is needed.
11984 (define_expand "seq"
11985 [(set (match_operand:SI 0 "register_operand" "")
11986 (eq:SI (reg:CC 17) (const_int 0)))]
11988 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
11990 (define_expand "sne"
11991 [(set (match_operand:SI 0 "register_operand" "")
11992 (ne:SI (reg:CC 17) (const_int 0)))]
11994 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
11996 (define_expand "sgt"
11997 [(set (match_operand:SI 0 "register_operand" "")
11998 (gt:SI (reg:CC 17) (const_int 0)))]
12000 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12002 (define_expand "sgtu"
12003 [(set (match_operand:SI 0 "register_operand" "")
12004 (gtu:SI (reg:CC 17) (const_int 0)))]
12006 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12008 (define_expand "slt"
12009 [(set (match_operand:SI 0 "register_operand" "")
12010 (lt:SI (reg:CC 17) (const_int 0)))]
12012 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12014 (define_expand "sltu"
12015 [(set (match_operand:SI 0 "register_operand" "")
12016 (ltu:SI (reg:CC 17) (const_int 0)))]
12018 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12020 (define_expand "sge"
12021 [(set (match_operand:SI 0 "register_operand" "")
12022 (ge:SI (reg:CC 17) (const_int 0)))]
12024 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12026 (define_expand "sgeu"
12027 [(set (match_operand:SI 0 "register_operand" "")
12028 (geu:SI (reg:CC 17) (const_int 0)))]
12030 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12032 (define_expand "sle"
12033 [(set (match_operand:SI 0 "register_operand" "")
12034 (le:SI (reg:CC 17) (const_int 0)))]
12036 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12038 (define_expand "sleu"
12039 [(set (match_operand:SI 0 "register_operand" "")
12040 (leu:SI (reg:CC 17) (const_int 0)))]
12042 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12044 (define_expand "sunordered"
12045 [(set (match_operand:SI 0 "register_operand" "")
12046 (unordered:SI (reg:CC 17) (const_int 0)))]
12047 "TARGET_80387 || TARGET_SSE"
12048 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12050 (define_expand "sordered"
12051 [(set (match_operand:SI 0 "register_operand" "")
12052 (ordered:SI (reg:CC 17) (const_int 0)))]
12054 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12056 (define_expand "suneq"
12057 [(set (match_operand:SI 0 "register_operand" "")
12058 (uneq:SI (reg:CC 17) (const_int 0)))]
12059 "TARGET_80387 || TARGET_SSE"
12060 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12062 (define_expand "sunge"
12063 [(set (match_operand:SI 0 "register_operand" "")
12064 (unge:SI (reg:CC 17) (const_int 0)))]
12065 "TARGET_80387 || TARGET_SSE"
12066 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12068 (define_expand "sungt"
12069 [(set (match_operand:SI 0 "register_operand" "")
12070 (ungt:SI (reg:CC 17) (const_int 0)))]
12071 "TARGET_80387 || TARGET_SSE"
12072 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12074 (define_expand "sunle"
12075 [(set (match_operand:SI 0 "register_operand" "")
12076 (unle:SI (reg:CC 17) (const_int 0)))]
12077 "TARGET_80387 || TARGET_SSE"
12078 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12080 (define_expand "sunlt"
12081 [(set (match_operand:SI 0 "register_operand" "")
12082 (unlt:SI (reg:CC 17) (const_int 0)))]
12083 "TARGET_80387 || TARGET_SSE"
12084 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12086 (define_expand "sltgt"
12087 [(set (match_operand:SI 0 "register_operand" "")
12088 (ltgt:SI (reg:CC 17) (const_int 0)))]
12089 "TARGET_80387 || TARGET_SSE"
12090 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12092 (define_insn "*setcc_1"
12093 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12094 (match_operator:QI 1 "ix86_comparison_operator"
12095 [(reg 17) (const_int 0)]))]
12098 [(set_attr "type" "setcc")
12099 (set_attr "mode" "QI")])
12101 (define_insn "setcc_2"
12102 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12103 (match_operator:QI 1 "ix86_comparison_operator"
12104 [(reg 17) (const_int 0)]))]
12107 [(set_attr "type" "setcc")
12108 (set_attr "mode" "QI")])
12110 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12111 ;; subsequent logical operations are used to imitate conditional moves.
12112 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12113 ;; it directly. Futher holding this value in pseudo register might bring
12114 ;; problem in implicit normalization in spill code.
12115 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12116 ;; instructions after reload by splitting the conditional move patterns.
12118 (define_insn "*sse_setccsf"
12119 [(set (match_operand:SF 0 "register_operand" "=x")
12120 (match_operator:SF 1 "sse_comparison_operator"
12121 [(match_operand:SF 2 "register_operand" "0")
12122 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12123 "TARGET_SSE && reload_completed"
12124 "cmp%D1ss\\t{%3, %0|%0, %3}"
12125 [(set_attr "type" "sse")
12126 (set_attr "mode" "SF")])
12128 (define_insn "*sse_setccdf"
12129 [(set (match_operand:DF 0 "register_operand" "=Y")
12130 (match_operator:DF 1 "sse_comparison_operator"
12131 [(match_operand:DF 2 "register_operand" "0")
12132 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12133 "TARGET_SSE2 && reload_completed"
12134 "cmp%D1sd\\t{%3, %0|%0, %3}"
12135 [(set_attr "type" "sse")
12136 (set_attr "mode" "DF")])
12138 ;; Basic conditional jump instructions.
12139 ;; We ignore the overflow flag for signed branch instructions.
12141 ;; For all bCOND expanders, also expand the compare or test insn that
12142 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12144 (define_expand "beq"
12146 (if_then_else (match_dup 1)
12147 (label_ref (match_operand 0 "" ""))
12150 "ix86_expand_branch (EQ, operands[0]); DONE;")
12152 (define_expand "bne"
12154 (if_then_else (match_dup 1)
12155 (label_ref (match_operand 0 "" ""))
12158 "ix86_expand_branch (NE, operands[0]); DONE;")
12160 (define_expand "bgt"
12162 (if_then_else (match_dup 1)
12163 (label_ref (match_operand 0 "" ""))
12166 "ix86_expand_branch (GT, operands[0]); DONE;")
12168 (define_expand "bgtu"
12170 (if_then_else (match_dup 1)
12171 (label_ref (match_operand 0 "" ""))
12174 "ix86_expand_branch (GTU, operands[0]); DONE;")
12176 (define_expand "blt"
12178 (if_then_else (match_dup 1)
12179 (label_ref (match_operand 0 "" ""))
12182 "ix86_expand_branch (LT, operands[0]); DONE;")
12184 (define_expand "bltu"
12186 (if_then_else (match_dup 1)
12187 (label_ref (match_operand 0 "" ""))
12190 "ix86_expand_branch (LTU, operands[0]); DONE;")
12192 (define_expand "bge"
12194 (if_then_else (match_dup 1)
12195 (label_ref (match_operand 0 "" ""))
12198 "ix86_expand_branch (GE, operands[0]); DONE;")
12200 (define_expand "bgeu"
12202 (if_then_else (match_dup 1)
12203 (label_ref (match_operand 0 "" ""))
12206 "ix86_expand_branch (GEU, operands[0]); DONE;")
12208 (define_expand "ble"
12210 (if_then_else (match_dup 1)
12211 (label_ref (match_operand 0 "" ""))
12214 "ix86_expand_branch (LE, operands[0]); DONE;")
12216 (define_expand "bleu"
12218 (if_then_else (match_dup 1)
12219 (label_ref (match_operand 0 "" ""))
12222 "ix86_expand_branch (LEU, operands[0]); DONE;")
12224 (define_expand "bunordered"
12226 (if_then_else (match_dup 1)
12227 (label_ref (match_operand 0 "" ""))
12229 "TARGET_80387 || TARGET_SSE"
12230 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12232 (define_expand "bordered"
12234 (if_then_else (match_dup 1)
12235 (label_ref (match_operand 0 "" ""))
12237 "TARGET_80387 || TARGET_SSE"
12238 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12240 (define_expand "buneq"
12242 (if_then_else (match_dup 1)
12243 (label_ref (match_operand 0 "" ""))
12245 "TARGET_80387 || TARGET_SSE"
12246 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12248 (define_expand "bunge"
12250 (if_then_else (match_dup 1)
12251 (label_ref (match_operand 0 "" ""))
12253 "TARGET_80387 || TARGET_SSE"
12254 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12256 (define_expand "bungt"
12258 (if_then_else (match_dup 1)
12259 (label_ref (match_operand 0 "" ""))
12261 "TARGET_80387 || TARGET_SSE"
12262 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12264 (define_expand "bunle"
12266 (if_then_else (match_dup 1)
12267 (label_ref (match_operand 0 "" ""))
12269 "TARGET_80387 || TARGET_SSE"
12270 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12272 (define_expand "bunlt"
12274 (if_then_else (match_dup 1)
12275 (label_ref (match_operand 0 "" ""))
12277 "TARGET_80387 || TARGET_SSE"
12278 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12280 (define_expand "bltgt"
12282 (if_then_else (match_dup 1)
12283 (label_ref (match_operand 0 "" ""))
12285 "TARGET_80387 || TARGET_SSE"
12286 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12288 (define_insn "*jcc_1"
12290 (if_then_else (match_operator 1 "ix86_comparison_operator"
12291 [(reg 17) (const_int 0)])
12292 (label_ref (match_operand 0 "" ""))
12296 [(set_attr "type" "ibr")
12297 (set (attr "prefix_0f")
12298 (if_then_else (and (ge (minus (match_dup 0) (pc))
12300 (lt (minus (match_dup 0) (pc))
12305 (define_insn "*jcc_2"
12307 (if_then_else (match_operator 1 "ix86_comparison_operator"
12308 [(reg 17) (const_int 0)])
12310 (label_ref (match_operand 0 "" ""))))]
12313 [(set_attr "type" "ibr")
12314 (set (attr "prefix_0f")
12315 (if_then_else (and (ge (minus (match_dup 0) (pc))
12317 (lt (minus (match_dup 0) (pc))
12322 ;; Define combination compare-and-branch fp compare instructions to use
12323 ;; during early optimization. Splitting the operation apart early makes
12324 ;; for bad code when we want to reverse the operation.
12326 (define_insn "*fp_jcc_1"
12328 (if_then_else (match_operator 0 "comparison_operator"
12329 [(match_operand 1 "register_operand" "f")
12330 (match_operand 2 "register_operand" "f")])
12331 (label_ref (match_operand 3 "" ""))
12333 (clobber (reg:CCFP 18))
12334 (clobber (reg:CCFP 17))]
12335 "TARGET_CMOVE && TARGET_80387
12336 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12337 && FLOAT_MODE_P (GET_MODE (operands[1]))
12338 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12341 (define_insn "*fp_jcc_1_sse"
12343 (if_then_else (match_operator 0 "comparison_operator"
12344 [(match_operand 1 "register_operand" "f#x,x#f")
12345 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12346 (label_ref (match_operand 3 "" ""))
12348 (clobber (reg:CCFP 18))
12349 (clobber (reg:CCFP 17))]
12351 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12352 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12355 (define_insn "*fp_jcc_1_sse_only"
12357 (if_then_else (match_operator 0 "comparison_operator"
12358 [(match_operand 1 "register_operand" "x")
12359 (match_operand 2 "nonimmediate_operand" "xm")])
12360 (label_ref (match_operand 3 "" ""))
12362 (clobber (reg:CCFP 18))
12363 (clobber (reg:CCFP 17))]
12364 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12365 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12368 (define_insn "*fp_jcc_2"
12370 (if_then_else (match_operator 0 "comparison_operator"
12371 [(match_operand 1 "register_operand" "f")
12372 (match_operand 2 "register_operand" "f")])
12374 (label_ref (match_operand 3 "" ""))))
12375 (clobber (reg:CCFP 18))
12376 (clobber (reg:CCFP 17))]
12377 "TARGET_CMOVE && TARGET_80387
12378 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12379 && FLOAT_MODE_P (GET_MODE (operands[1]))
12380 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12383 (define_insn "*fp_jcc_2_sse"
12385 (if_then_else (match_operator 0 "comparison_operator"
12386 [(match_operand 1 "register_operand" "f#x,x#f")
12387 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12389 (label_ref (match_operand 3 "" ""))))
12390 (clobber (reg:CCFP 18))
12391 (clobber (reg:CCFP 17))]
12393 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12394 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12397 (define_insn "*fp_jcc_2_sse_only"
12399 (if_then_else (match_operator 0 "comparison_operator"
12400 [(match_operand 1 "register_operand" "x")
12401 (match_operand 2 "nonimmediate_operand" "xm")])
12403 (label_ref (match_operand 3 "" ""))))
12404 (clobber (reg:CCFP 18))
12405 (clobber (reg:CCFP 17))]
12406 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12407 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12410 (define_insn "*fp_jcc_3"
12412 (if_then_else (match_operator 0 "comparison_operator"
12413 [(match_operand 1 "register_operand" "f")
12414 (match_operand 2 "nonimmediate_operand" "fm")])
12415 (label_ref (match_operand 3 "" ""))
12417 (clobber (reg:CCFP 18))
12418 (clobber (reg:CCFP 17))
12419 (clobber (match_scratch:HI 4 "=a"))]
12421 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12422 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12423 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12424 && SELECT_CC_MODE (GET_CODE (operands[0]),
12425 operands[1], operands[2]) == CCFPmode"
12428 (define_insn "*fp_jcc_4"
12430 (if_then_else (match_operator 0 "comparison_operator"
12431 [(match_operand 1 "register_operand" "f")
12432 (match_operand 2 "nonimmediate_operand" "fm")])
12434 (label_ref (match_operand 3 "" ""))))
12435 (clobber (reg:CCFP 18))
12436 (clobber (reg:CCFP 17))
12437 (clobber (match_scratch:HI 4 "=a"))]
12439 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12440 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12441 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12442 && SELECT_CC_MODE (GET_CODE (operands[0]),
12443 operands[1], operands[2]) == CCFPmode"
12446 (define_insn "*fp_jcc_5"
12448 (if_then_else (match_operator 0 "comparison_operator"
12449 [(match_operand 1 "register_operand" "f")
12450 (match_operand 2 "register_operand" "f")])
12451 (label_ref (match_operand 3 "" ""))
12453 (clobber (reg:CCFP 18))
12454 (clobber (reg:CCFP 17))
12455 (clobber (match_scratch:HI 4 "=a"))]
12457 && FLOAT_MODE_P (GET_MODE (operands[1]))
12458 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12461 (define_insn "*fp_jcc_6"
12463 (if_then_else (match_operator 0 "comparison_operator"
12464 [(match_operand 1 "register_operand" "f")
12465 (match_operand 2 "register_operand" "f")])
12467 (label_ref (match_operand 3 "" ""))))
12468 (clobber (reg:CCFP 18))
12469 (clobber (reg:CCFP 17))
12470 (clobber (match_scratch:HI 4 "=a"))]
12472 && FLOAT_MODE_P (GET_MODE (operands[1]))
12473 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
12478 (if_then_else (match_operator 0 "comparison_operator"
12479 [(match_operand 1 "register_operand" "")
12480 (match_operand 2 "nonimmediate_operand" "")])
12481 (match_operand 3 "" "")
12482 (match_operand 4 "" "")))
12483 (clobber (reg:CCFP 18))
12484 (clobber (reg:CCFP 17))]
12489 ix86_split_fp_branch (operands[0], operands[1], operands[2],
12490 operands[3], operands[4], NULL_RTX);
12496 (if_then_else (match_operator 0 "comparison_operator"
12497 [(match_operand 1 "register_operand" "")
12498 (match_operand 2 "nonimmediate_operand" "")])
12499 (match_operand 3 "" "")
12500 (match_operand 4 "" "")))
12501 (clobber (reg:CCFP 18))
12502 (clobber (reg:CCFP 17))
12503 (clobber (match_scratch:HI 5 "=a"))]
12506 (if_then_else (match_dup 6)
12511 ix86_split_fp_branch (operands[0], operands[1], operands[2],
12512 operands[3], operands[4], operands[5]);
12516 ;; Unconditional and other jump instructions
12518 (define_insn "jump"
12520 (label_ref (match_operand 0 "" "")))]
12523 [(set_attr "type" "ibr")])
12525 (define_insn "indirect_jump"
12526 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
12529 [(set_attr "type" "ibr")
12530 (set_attr "length_immediate" "0")])
12532 (define_insn "tablejump"
12533 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
12534 (use (label_ref (match_operand 1 "" "")))]
12537 [(set_attr "type" "ibr")
12538 (set_attr "length_immediate" "0")])
12540 ;; Implement switch statements when generating PIC code. Switches are
12541 ;; implemented by `tablejump' when not using -fpic.
12543 ;; Emit code here to do the range checking and make the index zero based.
12545 ;; Each entry in the "addr_diff_vec" looks like this as the result of the
12546 ;; two rules below:
12548 ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
12550 ;; 1. An expression involving an external reference may only use the
12551 ;; addition operator, and only with an assembly-time constant.
12552 ;; The example above satisfies this because ".-.L2" is a constant.
12554 ;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
12555 ;; given the value of "GOT - .", where GOT is the actual address of
12556 ;; the Global Offset Table. Therefore, the .long above actually
12557 ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
12558 ;; expression "GOT - .L2" by itself would generate an error from as(1).
12560 ;; The pattern below emits code that looks like this:
12563 ;; subl TABLE@GOTOFF(%ebx,index,4),reg
12566 ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
12567 ;; the addr_diff_vec is known to be part of this module.
12569 ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
12570 ;; evaluates to just ".L2".
12572 (define_expand "casesi"
12573 [(set (match_dup 5)
12574 (match_operand:SI 0 "general_operand" ""))
12575 (parallel [(set (match_dup 6)
12576 (minus:SI (match_dup 5)
12577 (match_operand:SI 1 "general_operand" "")))
12578 (clobber (reg:CC 17))])
12580 (compare:CC (match_dup 6)
12581 (match_operand:SI 2 "general_operand" "")))
12583 (if_then_else (gtu (reg:CC 17)
12585 (label_ref (match_operand 4 "" ""))
12588 [(set (match_dup 7)
12589 (minus:SI (match_dup 8)
12590 (mem:SI (plus:SI (plus:SI (mult:SI (match_dup 6) (const_int 4))
12592 (const (unspec [(label_ref (match_operand 3 "" ""))] 7))))))
12593 (clobber (reg:CC 17))])
12594 (parallel [(set (pc) (match_dup 7))
12595 (use (label_ref (match_dup 3)))])]
12599 operands[5] = gen_reg_rtx (SImode);
12600 operands[6] = gen_reg_rtx (SImode);
12601 operands[7] = gen_reg_rtx (SImode);
12602 operands[8] = pic_offset_table_rtx;
12603 current_function_uses_pic_offset_table = 1;
12606 (define_insn "*tablejump_pic"
12607 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
12608 (use (label_ref (match_operand 1 "" "")))]
12611 [(set_attr "type" "ibr")
12612 (set_attr "length_immediate" "0")])
12614 ;; Loop instruction
12616 ;; This is all complicated by the fact that since this is a jump insn
12617 ;; we must handle our own reloads.
12619 (define_expand "doloop_end"
12620 [(use (match_operand 0 "" "")) ; loop pseudo
12621 (use (match_operand 1 "" "")) ; iterations; zero if unknown
12622 (use (match_operand 2 "" "")) ; max iterations
12623 (use (match_operand 3 "" "")) ; loop level
12624 (use (match_operand 4 "" ""))] ; label
12625 "TARGET_USE_LOOP && !TARGET_64BIT"
12628 /* Only use cloop on innermost loops. */
12629 if (INTVAL (operands[3]) > 1)
12631 if (GET_MODE (operands[0]) != SImode)
12633 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
12638 (define_insn "doloop_end_internal"
12640 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
12642 (label_ref (match_operand 0 "" ""))
12644 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
12645 (plus:SI (match_dup 1)
12647 (clobber (match_scratch:SI 3 "=X,X,r"))
12648 (clobber (reg:CC 17))]
12649 "TARGET_USE_LOOP && !TARGET_64BIT"
12652 if (which_alternative != 0)
12654 if (get_attr_length (insn) == 2)
12655 return \"loop\\t%l0\";
12657 return \"dec{l}\\t%1\;jne\\t%l0\";
12659 [(set_attr "ppro_uops" "many")
12661 (if_then_else (and (eq_attr "alternative" "0")
12662 (and (ge (minus (match_dup 0) (pc))
12664 (lt (minus (match_dup 0) (pc))
12666 (const_string "ibr")
12667 (const_string "multi")))])
12671 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
12673 (match_operand 0 "" "")
12676 (plus:SI (match_dup 1)
12678 (clobber (match_scratch:SI 2 ""))
12679 (clobber (reg:CC 17))]
12680 "TARGET_USE_LOOP && !TARGET_64BIT
12681 && reload_completed
12682 && REGNO (operands[1]) != 2"
12683 [(parallel [(set (reg:CCZ 17)
12684 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
12686 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
12687 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
12694 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
12696 (match_operand 0 "" "")
12698 (set (match_operand:SI 2 "nonimmediate_operand" "")
12699 (plus:SI (match_dup 1)
12701 (clobber (match_scratch:SI 3 ""))
12702 (clobber (reg:CC 17))]
12703 "TARGET_USE_LOOP && !TARGET_64BIT
12704 && reload_completed
12705 && (! REG_P (operands[2])
12706 || ! rtx_equal_p (operands[1], operands[2]))"
12707 [(set (match_dup 3) (match_dup 1))
12708 (parallel [(set (reg:CCZ 17)
12709 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
12711 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
12712 (set (match_dup 2) (match_dup 3))
12713 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
12718 ;; Call instructions.
12720 ;; The predicates normally associated with named expanders are not properly
12721 ;; checked for calls. This is a bug in the generic code, but it isn't that
12722 ;; easy to fix. Ignore it for now and be prepared to fix things up.
12724 ;; Call subroutine returning no value.
12726 (define_expand "call_pop"
12727 [(parallel [(call (match_operand:QI 0 "" "")
12728 (match_operand:SI 1 "" ""))
12730 (plus:SI (reg:SI 7)
12731 (match_operand:SI 3 "" "")))])]
12735 if (operands[3] == const0_rtx)
12737 emit_insn (gen_call (operands[0], operands[1], constm1_rtx));
12740 /* Static functions and indirect calls don't need
12741 current_function_uses_pic_offset_table. */
12743 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
12744 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
12745 current_function_uses_pic_offset_table = 1;
12746 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
12747 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
12752 (define_insn "*call_pop_0"
12753 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
12754 (match_operand:SI 1 "" ""))
12755 (set (reg:SI 7) (plus:SI (reg:SI 7)
12756 (match_operand:SI 2 "immediate_operand" "")))]
12760 if (SIBLING_CALL_P (insn))
12761 return \"jmp\\t%P0\";
12763 return \"call\\t%P0\";
12765 [(set_attr "type" "call")])
12767 (define_insn "*call_pop_1"
12768 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
12769 (match_operand:SI 1 "" ""))
12770 (set (reg:SI 7) (plus:SI (reg:SI 7)
12771 (match_operand:SI 2 "immediate_operand" "i")))]
12775 if (constant_call_address_operand (operands[0], Pmode))
12777 if (SIBLING_CALL_P (insn))
12778 return \"jmp\\t%P0\";
12780 return \"call\\t%P0\";
12782 if (SIBLING_CALL_P (insn))
12783 return \"jmp\\t%A0\";
12785 return \"call\\t%A0\";
12787 [(set_attr "type" "call")])
12789 (define_expand "call"
12790 [(call (match_operand:QI 0 "" "")
12791 (match_operand 2 "" ""))]
12792 ;; Operand 1 not used on the i386.
12796 /* Static functions and indirect calls don't need
12797 current_function_uses_pic_offset_table. */
12799 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
12800 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
12801 current_function_uses_pic_offset_table = 1;
12803 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
12804 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
12805 if (TARGET_64BIT && INTVAL (operands[2]) >= 0)
12808 rtx reg = gen_rtx_REG (QImode, 0);
12809 emit_move_insn (reg, operands[2]);
12810 insn = emit_call_insn (gen_call_exp (operands[0], operands[2]));
12811 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
12816 (define_expand "call_exp"
12817 [(call (match_operand:QI 0 "" "")
12818 (match_operand 1 "" ""))]
12822 (define_insn "*call_0"
12823 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
12824 (match_operand 1 "" ""))]
12828 if (SIBLING_CALL_P (insn))
12829 return \"jmp\\t%P0\";
12831 return \"call\\t%P0\";
12833 [(set_attr "type" "call")])
12835 (define_insn "*call_1"
12836 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
12837 (match_operand 1 "" ""))]
12841 if (constant_call_address_operand (operands[0], QImode))
12843 if (SIBLING_CALL_P (insn))
12844 return \"jmp\\t%P0\";
12846 return \"call\\t%P0\";
12848 if (SIBLING_CALL_P (insn))
12849 return \"jmp\\t%A0\";
12851 return \"call\\t%A0\";
12853 [(set_attr "type" "call")])
12855 (define_insn "*call_1_rex64"
12856 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
12857 (match_operand 1 "" ""))]
12861 if (constant_call_address_operand (operands[0], QImode))
12863 if (SIBLING_CALL_P (insn))
12864 return \"jmp\\t%P0\";
12866 return \"call\\t%P0\";
12868 if (SIBLING_CALL_P (insn))
12869 return \"jmp\\t%A0\";
12871 return \"call\\t%A0\";
12873 [(set_attr "type" "call")])
12875 ;; Call subroutine, returning value in operand 0
12876 ;; (which must be a hard register).
12878 (define_expand "call_value_pop"
12879 [(parallel [(set (match_operand 0 "" "")
12880 (call (match_operand:QI 1 "" "")
12881 (match_operand:SI 2 "" "")))
12883 (plus:SI (reg:SI 7)
12884 (match_operand:SI 4 "" "")))])]
12888 if (operands[4] == const0_rtx)
12890 emit_insn (gen_call_value (operands[0], operands[1], operands[2],
12894 /* Static functions and indirect calls don't need
12895 current_function_uses_pic_offset_table. */
12897 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
12898 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
12899 current_function_uses_pic_offset_table = 1;
12900 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
12901 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
12904 (define_expand "call_value"
12905 [(set (match_operand 0 "" "")
12906 (call (match_operand:QI 1 "" "")
12907 (match_operand:SI 3 "" "")))]
12908 ;; Operand 2 not used on the i386.
12912 /* Static functions and indirect calls don't need
12913 current_function_uses_pic_offset_table. */
12915 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
12916 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
12917 current_function_uses_pic_offset_table = 1;
12918 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
12919 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
12920 if (TARGET_64BIT && INTVAL (operands[3]) >= 0)
12923 rtx reg = gen_rtx_REG (QImode, 0);
12924 emit_move_insn (reg, operands[3]);
12925 insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
12927 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
12932 (define_expand "call_value_exp"
12933 [(set (match_operand 0 "" "")
12934 (call (match_operand:QI 1 "" "")
12935 (match_operand:SI 2 "" "")))]
12939 ;; Call subroutine returning any type.
12941 (define_expand "untyped_call"
12942 [(parallel [(call (match_operand 0 "" "")
12944 (match_operand 1 "" "")
12945 (match_operand 2 "" "")])]
12951 /* In order to give reg-stack an easier job in validating two
12952 coprocessor registers as containing a possible return value,
12953 simply pretend the untyped call returns a complex long double
12956 emit_call_insn (TARGET_80387
12957 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
12958 operands[0], const0_rtx,
12959 GEN_INT (SSE_REGPARM_MAX - 1))
12960 : gen_call (operands[0], const0_rtx,
12961 GEN_INT (SSE_REGPARM_MAX - 1)));
12963 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12965 rtx set = XVECEXP (operands[2], 0, i);
12966 emit_move_insn (SET_DEST (set), SET_SRC (set));
12969 /* The optimizer does not know that the call sets the function value
12970 registers we stored in the result block. We avoid problems by
12971 claiming that all hard registers are used and clobbered at this
12973 emit_insn (gen_blockage ());
12978 ;; Prologue and epilogue instructions
12980 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12981 ;; all of memory. This blocks insns from being moved across this point.
12983 (define_insn "blockage"
12984 [(unspec_volatile [(const_int 0)] 0)]
12987 [(set_attr "length" "0")])
12989 ;; Insn emitted into the body of a function to return from a function.
12990 ;; This is only done if the function's epilogue is known to be simple.
12991 ;; See comments for ix86_can_use_return_insn_p in i386.c.
12993 (define_expand "return"
12995 "ix86_can_use_return_insn_p ()"
12998 if (current_function_pops_args)
13000 rtx popc = GEN_INT (current_function_pops_args);
13001 emit_jump_insn (gen_return_pop_internal (popc));
13006 (define_insn "return_internal"
13010 [(set_attr "length" "1")
13011 (set_attr "length_immediate" "0")
13012 (set_attr "modrm" "0")])
13014 (define_insn "return_pop_internal"
13016 (use (match_operand:SI 0 "const_int_operand" ""))]
13019 [(set_attr "length" "3")
13020 (set_attr "length_immediate" "2")
13021 (set_attr "modrm" "0")])
13023 (define_insn "return_indirect_internal"
13025 (use (match_operand:SI 0 "register_operand" "r"))]
13028 [(set_attr "type" "ibr")
13029 (set_attr "length_immediate" "0")])
13035 [(set_attr "length" "1")
13036 (set_attr "length_immediate" "0")
13037 (set_attr "modrm" "0")
13038 (set_attr "ppro_uops" "one")])
13040 (define_expand "prologue"
13043 "ix86_expand_prologue (); DONE;")
13045 (define_insn "prologue_set_got"
13046 [(set (match_operand:SI 0 "register_operand" "=r")
13047 (unspec_volatile:SI
13048 [(plus:SI (match_dup 0)
13049 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
13050 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
13051 (clobber (reg:CC 17))]
13055 if (GET_CODE (operands[2]) == LABEL_REF)
13056 operands[2] = XEXP (operands[2], 0);
13057 if (TARGET_DEEP_BRANCH_PREDICTION)
13058 return \"add{l}\\t{%1, %0|%0, %1}\";
13060 return \"add{l}\\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}\";
13062 [(set_attr "type" "alu")
13063 ; Since this insn may have two constant operands, we must set the
13065 (set_attr "length_immediate" "4")
13066 (set_attr "mode" "SI")])
13068 (define_insn "prologue_get_pc"
13069 [(set (match_operand:SI 0 "register_operand" "=r")
13070 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
13074 if (GET_CODE (operands[1]) == LABEL_REF)
13075 operands[1] = XEXP (operands[1], 0);
13076 output_asm_insn (\"call\\t%X1\", operands);
13077 if (! TARGET_DEEP_BRANCH_PREDICTION)
13079 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
13080 CODE_LABEL_NUMBER (operands[1]));
13084 [(set_attr "type" "multi")])
13086 (define_expand "epilogue"
13089 "ix86_expand_epilogue (1); DONE;")
13091 (define_expand "sibcall_epilogue"
13094 "ix86_expand_epilogue (0); DONE;")
13096 (define_expand "eh_return"
13097 [(use (match_operand 0 "register_operand" ""))
13098 (use (match_operand 1 "register_operand" ""))]
13102 rtx tmp, sa = operands[0], ra = operands[1];
13104 /* Tricky bit: we write the address of the handler to which we will
13105 be returning into someone else's stack frame, one word below the
13106 stack address we wish to restore. */
13107 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13108 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13109 tmp = gen_rtx_MEM (Pmode, tmp);
13110 emit_move_insn (tmp, ra);
13112 emit_insn (gen_eh_return_1 (sa));
13117 (define_insn_and_split "eh_return_1"
13118 [(unspec_volatile [(match_operand 0 "register_operand" "c")] 13)]
13123 "ix86_expand_epilogue (2); DONE;")
13125 (define_insn "leave"
13126 [(set (reg:SI 7) (reg:SI 6))
13127 (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))]
13130 [(set_attr "length_immediate" "0")
13131 (set_attr "length" "1")
13132 (set_attr "modrm" "0")
13133 (set_attr "modrm" "0")
13134 (set_attr "athlon_decode" "vector")
13135 (set_attr "ppro_uops" "few")])
13137 (define_insn "leave_rex64"
13138 [(set (reg:DI 7) (reg:DI 6))
13139 (set (reg:DI 6) (mem:DI (pre_dec:DI (reg:DI 7))))]
13142 [(set_attr "length_immediate" "0")
13143 (set_attr "length" "1")
13144 (set_attr "modrm" "0")
13145 (set_attr "modrm" "0")
13146 (set_attr "athlon_decode" "vector")
13147 (set_attr "ppro_uops" "few")])
13149 (define_expand "ffssi2"
13150 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13151 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13155 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13156 rtx in = operands[1];
13160 emit_move_insn (tmp, constm1_rtx);
13161 emit_insn (gen_ffssi_1 (out, in));
13162 emit_insn (gen_rtx_SET (VOIDmode, out,
13163 gen_rtx_IF_THEN_ELSE (SImode,
13164 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13168 emit_insn (gen_addsi3 (out, out, const1_rtx));
13169 emit_move_insn (operands[0], out);
13172 /* Pentium bsf instruction is extremly slow. The following code is
13173 recommended by the Intel Optimizing Manual as a reasonable replacement:
13177 MOV DWORD PTR [TEMP+4],ECX
13180 MOV DWORD PTR [TEMP],EAX
13181 FILD QWORD PTR [TEMP]
13182 FSTP QWORD PTR [TEMP]
13183 WAIT ; WAIT only needed for compatibility with
13184 ; earlier processors
13185 MOV ECX, DWORD PTR [TEMP+4]
13188 TEST EAX,EAX ; clear zero flag
13190 Following piece of code expand ffs to similar beast.
13193 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13195 rtx label = gen_label_rtx ();
13197 rtx mem = assign_386_stack_local (DImode, 0);
13198 rtx fptmp = gen_reg_rtx (DFmode);
13199 split_di (&mem, 1, &lo, &hi);
13201 emit_move_insn (out, const0_rtx);
13203 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, 0, label);
13205 emit_move_insn (hi, out);
13206 emit_insn (gen_subsi3 (out, out, in));
13207 emit_insn (gen_andsi3 (out, out, in));
13208 emit_move_insn (lo, out);
13209 emit_insn (gen_floatdidf2 (fptmp,mem));
13210 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13211 emit_move_insn (out, hi);
13212 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13213 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13215 emit_label (label);
13216 LABEL_NUSES (label) = 1;
13218 emit_move_insn (operands[0], out);
13222 emit_move_insn (tmp, const0_rtx);
13223 emit_insn (gen_ffssi_1 (out, in));
13224 emit_insn (gen_rtx_SET (VOIDmode,
13225 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13226 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13228 emit_insn (gen_negsi2 (tmp, tmp));
13229 emit_insn (gen_iorsi3 (out, out, tmp));
13230 emit_insn (gen_addsi3 (out, out, const1_rtx));
13231 emit_move_insn (operands[0], out);
13236 (define_insn "ffssi_1"
13238 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13240 (set (match_operand:SI 0 "register_operand" "=r")
13241 (unspec:SI [(match_dup 1)] 5))]
13243 "bsf{l}\\t{%1, %0|%0, %1}"
13244 [(set_attr "prefix_0f" "1")
13245 (set_attr "ppro_uops" "few")])
13247 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13248 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13250 ;; These patterns match the binary 387 instructions for addM3, subM3,
13251 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13252 ;; SFmode. The first is the normal insn, the second the same insn but
13253 ;; with one operand a conversion, and the third the same insn but with
13254 ;; the other operand a conversion. The conversion may be SFmode or
13255 ;; SImode if the target mode DFmode, but only SImode if the target mode
13258 ;; Gcc is slightly more smart about handling normal two address instructions
13259 ;; so use special patterns for add and mull.
13260 (define_insn "*fop_sf_comm"
13261 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13262 (match_operator:SF 3 "binary_fp_operator"
13263 [(match_operand:SF 1 "register_operand" "%0,0")
13264 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13265 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13266 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13267 "* return output_387_binary_op (insn, operands);"
13268 [(set (attr "type")
13269 (if_then_else (eq_attr "alternative" "1")
13270 (const_string "sse")
13271 (if_then_else (match_operand:SF 3 "mult_operator" "")
13272 (const_string "fmul")
13273 (const_string "fop"))))
13274 (set_attr "mode" "SF")])
13276 (define_insn "*fop_sf_comm_sse"
13277 [(set (match_operand:SF 0 "register_operand" "=x")
13278 (match_operator:SF 3 "binary_fp_operator"
13279 [(match_operand:SF 1 "register_operand" "%0")
13280 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13281 "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13282 "* return output_387_binary_op (insn, operands);"
13283 [(set_attr "type" "sse")
13284 (set_attr "mode" "SF")])
13286 (define_insn "*fop_df_comm"
13287 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13288 (match_operator:DF 3 "binary_fp_operator"
13289 [(match_operand:DF 1 "register_operand" "%0,0")
13290 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13291 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13292 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13293 "* return output_387_binary_op (insn, operands);"
13294 [(set (attr "type")
13295 (if_then_else (eq_attr "alternative" "1")
13296 (const_string "sse")
13297 (if_then_else (match_operand:SF 3 "mult_operator" "")
13298 (const_string "fmul")
13299 (const_string "fop"))))
13300 (set_attr "mode" "DF")])
13302 (define_insn "*fop_df_comm_sse"
13303 [(set (match_operand:DF 0 "register_operand" "=Y")
13304 (match_operator:DF 3 "binary_fp_operator"
13305 [(match_operand:DF 1 "register_operand" "%0")
13306 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13308 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13309 "* return output_387_binary_op (insn, operands);"
13310 [(set_attr "type" "sse")
13311 (set_attr "mode" "DF")])
13313 (define_insn "*fop_xf_comm"
13314 [(set (match_operand:XF 0 "register_operand" "=f")
13315 (match_operator:XF 3 "binary_fp_operator"
13316 [(match_operand:XF 1 "register_operand" "%0")
13317 (match_operand:XF 2 "register_operand" "f")]))]
13318 "TARGET_80387 && !TARGET_64BIT
13319 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13320 "* return output_387_binary_op (insn, operands);"
13321 [(set (attr "type")
13322 (if_then_else (match_operand:XF 3 "mult_operator" "")
13323 (const_string "fmul")
13324 (const_string "fop")))
13325 (set_attr "mode" "XF")])
13327 (define_insn "*fop_tf_comm"
13328 [(set (match_operand:TF 0 "register_operand" "=f")
13329 (match_operator:TF 3 "binary_fp_operator"
13330 [(match_operand:TF 1 "register_operand" "%0")
13331 (match_operand:TF 2 "register_operand" "f")]))]
13332 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
13333 "* return output_387_binary_op (insn, operands);"
13334 [(set (attr "type")
13335 (if_then_else (match_operand:TF 3 "mult_operator" "")
13336 (const_string "fmul")
13337 (const_string "fop")))
13338 (set_attr "mode" "XF")])
13340 (define_insn "*fop_sf_1"
13341 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
13342 (match_operator:SF 3 "binary_fp_operator"
13343 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
13344 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
13345 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
13346 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13347 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13348 "* return output_387_binary_op (insn, operands);"
13349 [(set (attr "type")
13350 (cond [(eq_attr "alternative" "2")
13351 (const_string "sse")
13352 (match_operand:SF 3 "mult_operator" "")
13353 (const_string "fmul")
13354 (match_operand:SF 3 "div_operator" "")
13355 (const_string "fdiv")
13357 (const_string "fop")))
13358 (set_attr "mode" "SF")])
13360 (define_insn "*fop_sf_1_sse"
13361 [(set (match_operand:SF 0 "register_operand" "=x")
13362 (match_operator:SF 3 "binary_fp_operator"
13363 [(match_operand:SF 1 "register_operand" "0")
13364 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13366 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13367 "* return output_387_binary_op (insn, operands);"
13368 [(set_attr "type" "sse")
13369 (set_attr "mode" "SF")])
13371 ;; ??? Add SSE splitters for these!
13372 (define_insn "*fop_sf_2"
13373 [(set (match_operand:SF 0 "register_operand" "=f,f")
13374 (match_operator:SF 3 "binary_fp_operator"
13375 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13376 (match_operand:SF 2 "register_operand" "0,0")]))]
13377 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13378 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13379 [(set (attr "type")
13380 (cond [(match_operand:SF 3 "mult_operator" "")
13381 (const_string "fmul")
13382 (match_operand:SF 3 "div_operator" "")
13383 (const_string "fdiv")
13385 (const_string "fop")))
13386 (set_attr "fp_int_src" "true")
13387 (set_attr "ppro_uops" "many")
13388 (set_attr "mode" "SI")])
13390 (define_insn "*fop_sf_3"
13391 [(set (match_operand:SF 0 "register_operand" "=f,f")
13392 (match_operator:SF 3 "binary_fp_operator"
13393 [(match_operand:SF 1 "register_operand" "0,0")
13394 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13395 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
13396 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13397 [(set (attr "type")
13398 (cond [(match_operand:SF 3 "mult_operator" "")
13399 (const_string "fmul")
13400 (match_operand:SF 3 "div_operator" "")
13401 (const_string "fdiv")
13403 (const_string "fop")))
13404 (set_attr "fp_int_src" "true")
13405 (set_attr "ppro_uops" "many")
13406 (set_attr "mode" "SI")])
13408 (define_insn "*fop_df_1"
13409 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
13410 (match_operator:DF 3 "binary_fp_operator"
13411 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
13412 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
13413 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
13414 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
13415 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13416 "* return output_387_binary_op (insn, operands);"
13417 [(set (attr "type")
13418 (cond [(eq_attr "alternative" "2")
13419 (const_string "sse")
13420 (match_operand:DF 3 "mult_operator" "")
13421 (const_string "fmul")
13422 (match_operand:DF 3 "div_operator" "")
13423 (const_string "fdiv")
13425 (const_string "fop")))
13426 (set_attr "mode" "DF")])
13428 (define_insn "*fop_df_1_sse"
13429 [(set (match_operand:DF 0 "register_operand" "=Y")
13430 (match_operator:DF 3 "binary_fp_operator"
13431 [(match_operand:DF 1 "register_operand" "0")
13432 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13434 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13435 "* return output_387_binary_op (insn, operands);"
13436 [(set_attr "type" "sse")])
13438 ;; ??? Add SSE splitters for these!
13439 (define_insn "*fop_df_2"
13440 [(set (match_operand:DF 0 "register_operand" "=f,f")
13441 (match_operator:DF 3 "binary_fp_operator"
13442 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13443 (match_operand:DF 2 "register_operand" "0,0")]))]
13444 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13445 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13446 [(set (attr "type")
13447 (cond [(match_operand:DF 3 "mult_operator" "")
13448 (const_string "fmul")
13449 (match_operand:DF 3 "div_operator" "")
13450 (const_string "fdiv")
13452 (const_string "fop")))
13453 (set_attr "fp_int_src" "true")
13454 (set_attr "ppro_uops" "many")
13455 (set_attr "mode" "SI")])
13457 (define_insn "*fop_df_3"
13458 [(set (match_operand:DF 0 "register_operand" "=f,f")
13459 (match_operator:DF 3 "binary_fp_operator"
13460 [(match_operand:DF 1 "register_operand" "0,0")
13461 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13462 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
13463 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13464 [(set (attr "type")
13465 (cond [(match_operand:DF 3 "mult_operator" "")
13466 (const_string "fmul")
13467 (match_operand:DF 3 "div_operator" "")
13468 (const_string "fdiv")
13470 (const_string "fop")))
13471 (set_attr "fp_int_src" "true")
13472 (set_attr "ppro_uops" "many")
13473 (set_attr "mode" "SI")])
13475 (define_insn "*fop_df_4"
13476 [(set (match_operand:DF 0 "register_operand" "=f,f")
13477 (match_operator:DF 3 "binary_fp_operator"
13478 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13479 (match_operand:DF 2 "register_operand" "0,f")]))]
13481 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13482 "* return output_387_binary_op (insn, operands);"
13483 [(set (attr "type")
13484 (cond [(match_operand:DF 3 "mult_operator" "")
13485 (const_string "fmul")
13486 (match_operand:DF 3 "div_operator" "")
13487 (const_string "fdiv")
13489 (const_string "fop")))
13490 (set_attr "mode" "SF")])
13492 (define_insn "*fop_df_5"
13493 [(set (match_operand:DF 0 "register_operand" "=f,f")
13494 (match_operator:DF 3 "binary_fp_operator"
13495 [(match_operand:DF 1 "register_operand" "0,f")
13497 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13498 "TARGET_80387 && !TARGET_SSE2"
13499 "* return output_387_binary_op (insn, operands);"
13500 [(set (attr "type")
13501 (cond [(match_operand:DF 3 "mult_operator" "")
13502 (const_string "fmul")
13503 (match_operand:DF 3 "div_operator" "")
13504 (const_string "fdiv")
13506 (const_string "fop")))
13507 (set_attr "mode" "SF")])
13509 (define_insn "*fop_xf_1"
13510 [(set (match_operand:XF 0 "register_operand" "=f,f")
13511 (match_operator:XF 3 "binary_fp_operator"
13512 [(match_operand:XF 1 "register_operand" "0,f")
13513 (match_operand:XF 2 "register_operand" "f,0")]))]
13514 "TARGET_80387 && !TARGET_64BIT
13515 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13516 "* return output_387_binary_op (insn, operands);"
13517 [(set (attr "type")
13518 (cond [(match_operand:XF 3 "mult_operator" "")
13519 (const_string "fmul")
13520 (match_operand:XF 3 "div_operator" "")
13521 (const_string "fdiv")
13523 (const_string "fop")))
13524 (set_attr "mode" "XF")])
13526 (define_insn "*fop_tf_1"
13527 [(set (match_operand:TF 0 "register_operand" "=f,f")
13528 (match_operator:TF 3 "binary_fp_operator"
13529 [(match_operand:TF 1 "register_operand" "0,f")
13530 (match_operand:TF 2 "register_operand" "f,0")]))]
13532 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
13533 "* return output_387_binary_op (insn, operands);"
13534 [(set (attr "type")
13535 (cond [(match_operand:TF 3 "mult_operator" "")
13536 (const_string "fmul")
13537 (match_operand:TF 3 "div_operator" "")
13538 (const_string "fdiv")
13540 (const_string "fop")))
13541 (set_attr "mode" "XF")])
13543 (define_insn "*fop_xf_2"
13544 [(set (match_operand:XF 0 "register_operand" "=f,f")
13545 (match_operator:XF 3 "binary_fp_operator"
13546 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13547 (match_operand:XF 2 "register_operand" "0,0")]))]
13548 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
13549 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13550 [(set (attr "type")
13551 (cond [(match_operand:XF 3 "mult_operator" "")
13552 (const_string "fmul")
13553 (match_operand:XF 3 "div_operator" "")
13554 (const_string "fdiv")
13556 (const_string "fop")))
13557 (set_attr "fp_int_src" "true")
13558 (set_attr "mode" "SI")
13559 (set_attr "ppro_uops" "many")])
13561 (define_insn "*fop_tf_2"
13562 [(set (match_operand:TF 0 "register_operand" "=f,f")
13563 (match_operator:TF 3 "binary_fp_operator"
13564 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
13565 (match_operand:TF 2 "register_operand" "0,0")]))]
13566 "TARGET_80387 && TARGET_USE_FIOP"
13567 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13568 [(set (attr "type")
13569 (cond [(match_operand:TF 3 "mult_operator" "")
13570 (const_string "fmul")
13571 (match_operand:TF 3 "div_operator" "")
13572 (const_string "fdiv")
13574 (const_string "fop")))
13575 (set_attr "fp_int_src" "true")
13576 (set_attr "mode" "SI")
13577 (set_attr "ppro_uops" "many")])
13579 (define_insn "*fop_xf_3"
13580 [(set (match_operand:XF 0 "register_operand" "=f,f")
13581 (match_operator:XF 3 "binary_fp_operator"
13582 [(match_operand:XF 1 "register_operand" "0,0")
13583 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13584 "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
13585 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13586 [(set (attr "type")
13587 (cond [(match_operand:XF 3 "mult_operator" "")
13588 (const_string "fmul")
13589 (match_operand:XF 3 "div_operator" "")
13590 (const_string "fdiv")
13592 (const_string "fop")))
13593 (set_attr "fp_int_src" "true")
13594 (set_attr "mode" "SI")
13595 (set_attr "ppro_uops" "many")])
13597 (define_insn "*fop_tf_3"
13598 [(set (match_operand:TF 0 "register_operand" "=f,f")
13599 (match_operator:TF 3 "binary_fp_operator"
13600 [(match_operand:TF 1 "register_operand" "0,0")
13601 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
13602 "TARGET_80387 && TARGET_USE_FIOP"
13603 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
13604 [(set (attr "type")
13605 (cond [(match_operand:TF 3 "mult_operator" "")
13606 (const_string "fmul")
13607 (match_operand:TF 3 "div_operator" "")
13608 (const_string "fdiv")
13610 (const_string "fop")))
13611 (set_attr "fp_int_src" "true")
13612 (set_attr "mode" "SI")
13613 (set_attr "ppro_uops" "many")])
13615 (define_insn "*fop_xf_4"
13616 [(set (match_operand:XF 0 "register_operand" "=f,f")
13617 (match_operator:XF 3 "binary_fp_operator"
13618 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13619 (match_operand:XF 2 "register_operand" "0,f")]))]
13620 "TARGET_80387 && !TARGET_64BIT"
13621 "* return output_387_binary_op (insn, operands);"
13622 [(set (attr "type")
13623 (cond [(match_operand:XF 3 "mult_operator" "")
13624 (const_string "fmul")
13625 (match_operand:XF 3 "div_operator" "")
13626 (const_string "fdiv")
13628 (const_string "fop")))
13629 (set_attr "mode" "SF")])
13631 (define_insn "*fop_tf_4"
13632 [(set (match_operand:TF 0 "register_operand" "=f,f")
13633 (match_operator:TF 3 "binary_fp_operator"
13634 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
13635 (match_operand:TF 2 "register_operand" "0,f")]))]
13637 "* return output_387_binary_op (insn, operands);"
13638 [(set (attr "type")
13639 (cond [(match_operand:TF 3 "mult_operator" "")
13640 (const_string "fmul")
13641 (match_operand:TF 3 "div_operator" "")
13642 (const_string "fdiv")
13644 (const_string "fop")))
13645 (set_attr "mode" "SF")])
13647 (define_insn "*fop_xf_5"
13648 [(set (match_operand:XF 0 "register_operand" "=f,f")
13649 (match_operator:XF 3 "binary_fp_operator"
13650 [(match_operand:XF 1 "register_operand" "0,f")
13652 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13653 "TARGET_80387 && !TARGET_64BIT"
13654 "* return output_387_binary_op (insn, operands);"
13655 [(set (attr "type")
13656 (cond [(match_operand:XF 3 "mult_operator" "")
13657 (const_string "fmul")
13658 (match_operand:XF 3 "div_operator" "")
13659 (const_string "fdiv")
13661 (const_string "fop")))
13662 (set_attr "mode" "SF")])
13664 (define_insn "*fop_tf_5"
13665 [(set (match_operand:TF 0 "register_operand" "=f,f")
13666 (match_operator:TF 3 "binary_fp_operator"
13667 [(match_operand:TF 1 "register_operand" "0,f")
13669 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
13671 "* return output_387_binary_op (insn, operands);"
13672 [(set (attr "type")
13673 (cond [(match_operand:TF 3 "mult_operator" "")
13674 (const_string "fmul")
13675 (match_operand:TF 3 "div_operator" "")
13676 (const_string "fdiv")
13678 (const_string "fop")))
13679 (set_attr "mode" "SF")])
13681 (define_insn "*fop_xf_6"
13682 [(set (match_operand:XF 0 "register_operand" "=f,f")
13683 (match_operator:XF 3 "binary_fp_operator"
13684 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
13685 (match_operand:XF 2 "register_operand" "0,f")]))]
13686 "TARGET_80387 && !TARGET_64BIT"
13687 "* return output_387_binary_op (insn, operands);"
13688 [(set (attr "type")
13689 (cond [(match_operand:XF 3 "mult_operator" "")
13690 (const_string "fmul")
13691 (match_operand:XF 3 "div_operator" "")
13692 (const_string "fdiv")
13694 (const_string "fop")))
13695 (set_attr "mode" "DF")])
13697 (define_insn "*fop_tf_6"
13698 [(set (match_operand:TF 0 "register_operand" "=f,f")
13699 (match_operator:TF 3 "binary_fp_operator"
13700 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
13701 (match_operand:TF 2 "register_operand" "0,f")]))]
13703 "* return output_387_binary_op (insn, operands);"
13704 [(set (attr "type")
13705 (cond [(match_operand:TF 3 "mult_operator" "")
13706 (const_string "fmul")
13707 (match_operand:TF 3 "div_operator" "")
13708 (const_string "fdiv")
13710 (const_string "fop")))
13711 (set_attr "mode" "DF")])
13713 (define_insn "*fop_xf_7"
13714 [(set (match_operand:XF 0 "register_operand" "=f,f")
13715 (match_operator:XF 3 "binary_fp_operator"
13716 [(match_operand:XF 1 "register_operand" "0,f")
13718 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
13719 "TARGET_80387 && !TARGET_64BIT"
13720 "* return output_387_binary_op (insn, operands);"
13721 [(set (attr "type")
13722 (cond [(match_operand:XF 3 "mult_operator" "")
13723 (const_string "fmul")
13724 (match_operand:XF 3 "div_operator" "")
13725 (const_string "fdiv")
13727 (const_string "fop")))
13728 (set_attr "mode" "DF")])
13730 (define_insn "*fop_tf_7"
13731 [(set (match_operand:TF 0 "register_operand" "=f,f")
13732 (match_operator:TF 3 "binary_fp_operator"
13733 [(match_operand:TF 1 "register_operand" "0,f")
13735 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
13737 "* return output_387_binary_op (insn, operands);"
13738 [(set (attr "type")
13739 (cond [(match_operand:TF 3 "mult_operator" "")
13740 (const_string "fmul")
13741 (match_operand:TF 3 "div_operator" "")
13742 (const_string "fdiv")
13744 (const_string "fop")))
13745 (set_attr "mode" "DF")])
13748 [(set (match_operand 0 "register_operand" "")
13749 (match_operator 3 "binary_fp_operator"
13750 [(float (match_operand:SI 1 "register_operand" ""))
13751 (match_operand 2 "register_operand" "")]))]
13752 "TARGET_80387 && reload_completed
13753 && FLOAT_MODE_P (GET_MODE (operands[0]))"
13757 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
13758 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
13759 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13760 gen_rtx_fmt_ee (GET_CODE (operands[3]),
13761 GET_MODE (operands[3]),
13764 ix86_free_from_memory (GET_MODE (operands[1]));
13769 [(set (match_operand 0 "register_operand" "")
13770 (match_operator 3 "binary_fp_operator"
13771 [(match_operand 1 "register_operand" "")
13772 (float (match_operand:SI 2 "register_operand" ""))]))]
13773 "TARGET_80387 && reload_completed
13774 && FLOAT_MODE_P (GET_MODE (operands[0]))"
13778 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
13779 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
13780 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13781 gen_rtx_fmt_ee (GET_CODE (operands[3]),
13782 GET_MODE (operands[3]),
13785 ix86_free_from_memory (GET_MODE (operands[2]));
13789 ;; FPU special functions.
13791 (define_expand "sqrtsf2"
13792 [(set (match_operand:SF 0 "register_operand" "")
13793 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
13794 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
13798 operands[1] = force_reg (SFmode, operands[1]);
13801 (define_insn "sqrtsf2_1"
13802 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13803 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
13804 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13805 && (TARGET_SSE && TARGET_MIX_SSE_I387)"
13808 sqrtss\\t{%1, %0|%0, %1}"
13809 [(set_attr "type" "fpspc,sse")
13810 (set_attr "mode" "SF,SF")
13811 (set_attr "athlon_decode" "direct,*")])
13813 (define_insn "sqrtsf2_1_sse_only"
13814 [(set (match_operand:SF 0 "register_operand" "=x")
13815 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
13816 "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
13817 "sqrtss\\t{%1, %0|%0, %1}"
13818 [(set_attr "type" "sse")
13819 (set_attr "mode" "SF")
13820 (set_attr "athlon_decode" "*")])
13822 (define_insn "sqrtsf2_i387"
13823 [(set (match_operand:SF 0 "register_operand" "=f")
13824 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
13825 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13826 && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
13828 [(set_attr "type" "fpspc")
13829 (set_attr "mode" "SF")
13830 (set_attr "athlon_decode" "direct")])
13832 (define_expand "sqrtdf2"
13833 [(set (match_operand:DF 0 "register_operand" "")
13834 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
13835 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
13839 operands[1] = force_reg (SFmode, operands[1]);
13842 (define_insn "sqrtdf2_1"
13843 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13844 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
13845 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13846 && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
13849 sqrtsd\\t{%1, %0|%0, %1}"
13850 [(set_attr "type" "fpspc,sse")
13851 (set_attr "mode" "DF,DF")
13852 (set_attr "athlon_decode" "direct,*")])
13854 (define_insn "sqrtdf2_1_sse_only"
13855 [(set (match_operand:DF 0 "register_operand" "=Y")
13856 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
13857 "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
13858 "sqrtsd\\t{%1, %0|%0, %1}"
13859 [(set_attr "type" "sse")
13860 (set_attr "mode" "DF")
13861 (set_attr "athlon_decode" "*")])
13863 (define_insn "sqrtdf2_i387"
13864 [(set (match_operand:DF 0 "register_operand" "=f")
13865 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
13866 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13867 && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
13869 [(set_attr "type" "fpspc")
13870 (set_attr "mode" "DF")
13871 (set_attr "athlon_decode" "direct")])
13873 (define_insn "*sqrtextendsfdf2"
13874 [(set (match_operand:DF 0 "register_operand" "=f")
13875 (sqrt:DF (float_extend:DF
13876 (match_operand:SF 1 "register_operand" "0"))))]
13877 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
13879 [(set_attr "type" "fpspc")
13880 (set_attr "mode" "DF")
13881 (set_attr "athlon_decode" "direct")])
13883 (define_insn "sqrtxf2"
13884 [(set (match_operand:XF 0 "register_operand" "=f")
13885 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
13886 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
13887 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
13889 [(set_attr "type" "fpspc")
13890 (set_attr "mode" "XF")
13891 (set_attr "athlon_decode" "direct")])
13893 (define_insn "sqrttf2"
13894 [(set (match_operand:TF 0 "register_operand" "=f")
13895 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
13896 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13897 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
13899 [(set_attr "type" "fpspc")
13900 (set_attr "mode" "XF")
13901 (set_attr "athlon_decode" "direct")])
13903 (define_insn "*sqrtextenddfxf2"
13904 [(set (match_operand:XF 0 "register_operand" "=f")
13905 (sqrt:XF (float_extend:XF
13906 (match_operand:DF 1 "register_operand" "0"))))]
13907 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
13909 [(set_attr "type" "fpspc")
13910 (set_attr "mode" "XF")
13911 (set_attr "athlon_decode" "direct")])
13913 (define_insn "*sqrtextenddftf2"
13914 [(set (match_operand:TF 0 "register_operand" "=f")
13915 (sqrt:TF (float_extend:TF
13916 (match_operand:DF 1 "register_operand" "0"))))]
13917 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
13919 [(set_attr "type" "fpspc")
13920 (set_attr "mode" "XF")
13921 (set_attr "athlon_decode" "direct")])
13923 (define_insn "*sqrtextendsfxf2"
13924 [(set (match_operand:XF 0 "register_operand" "=f")
13925 (sqrt:XF (float_extend:XF
13926 (match_operand:SF 1 "register_operand" "0"))))]
13927 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
13929 [(set_attr "type" "fpspc")
13930 (set_attr "mode" "XF")
13931 (set_attr "athlon_decode" "direct")])
13933 (define_insn "*sqrtextendsftf2"
13934 [(set (match_operand:TF 0 "register_operand" "=f")
13935 (sqrt:TF (float_extend:TF
13936 (match_operand:SF 1 "register_operand" "0"))))]
13937 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
13939 [(set_attr "type" "fpspc")
13940 (set_attr "mode" "XF")
13941 (set_attr "athlon_decode" "direct")])
13943 (define_insn "sindf2"
13944 [(set (match_operand:DF 0 "register_operand" "=f")
13945 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
13946 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13947 && flag_unsafe_math_optimizations"
13949 [(set_attr "type" "fpspc")
13950 (set_attr "mode" "DF")])
13952 (define_insn "sinsf2"
13953 [(set (match_operand:SF 0 "register_operand" "=f")
13954 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
13955 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13956 && flag_unsafe_math_optimizations"
13958 [(set_attr "type" "fpspc")
13959 (set_attr "mode" "SF")])
13961 (define_insn "*sinextendsfdf2"
13962 [(set (match_operand:DF 0 "register_operand" "=f")
13963 (unspec:DF [(float_extend:DF
13964 (match_operand:SF 1 "register_operand" "0"))] 1))]
13965 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13966 && flag_unsafe_math_optimizations"
13968 [(set_attr "type" "fpspc")
13969 (set_attr "mode" "DF")])
13971 (define_insn "sinxf2"
13972 [(set (match_operand:XF 0 "register_operand" "=f")
13973 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
13974 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
13975 && flag_unsafe_math_optimizations"
13977 [(set_attr "type" "fpspc")
13978 (set_attr "mode" "XF")])
13980 (define_insn "sintf2"
13981 [(set (match_operand:TF 0 "register_operand" "=f")
13982 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
13983 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13984 && flag_unsafe_math_optimizations"
13986 [(set_attr "type" "fpspc")
13987 (set_attr "mode" "XF")])
13989 (define_insn "cosdf2"
13990 [(set (match_operand:DF 0 "register_operand" "=f")
13991 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
13992 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
13993 && flag_unsafe_math_optimizations"
13995 [(set_attr "type" "fpspc")
13996 (set_attr "mode" "DF")])
13998 (define_insn "cossf2"
13999 [(set (match_operand:SF 0 "register_operand" "=f")
14000 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
14001 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14002 && flag_unsafe_math_optimizations"
14004 [(set_attr "type" "fpspc")
14005 (set_attr "mode" "SF")])
14007 (define_insn "*cosextendsfdf2"
14008 [(set (match_operand:DF 0 "register_operand" "=f")
14009 (unspec:DF [(float_extend:DF
14010 (match_operand:SF 1 "register_operand" "0"))] 2))]
14011 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14012 && flag_unsafe_math_optimizations"
14014 [(set_attr "type" "fpspc")
14015 (set_attr "mode" "DF")])
14017 (define_insn "cosxf2"
14018 [(set (match_operand:XF 0 "register_operand" "=f")
14019 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
14020 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14021 && flag_unsafe_math_optimizations"
14023 [(set_attr "type" "fpspc")
14024 (set_attr "mode" "XF")])
14026 (define_insn "costf2"
14027 [(set (match_operand:TF 0 "register_operand" "=f")
14028 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
14029 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14030 && flag_unsafe_math_optimizations"
14032 [(set_attr "type" "fpspc")
14033 (set_attr "mode" "XF")])
14035 ;; Block operation instructions
14038 [(set (reg:SI 19) (const_int 0))]
14041 [(set_attr "type" "cld")])
14043 (define_expand "movstrsi"
14044 [(use (match_operand:BLK 0 "memory_operand" ""))
14045 (use (match_operand:BLK 1 "memory_operand" ""))
14046 (use (match_operand:SI 2 "nonmemory_operand" ""))
14047 (use (match_operand:SI 3 "const_int_operand" ""))]
14051 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14057 (define_expand "movstrdi"
14058 [(use (match_operand:BLK 0 "memory_operand" ""))
14059 (use (match_operand:BLK 1 "memory_operand" ""))
14060 (use (match_operand:DI 2 "nonmemory_operand" ""))
14061 (use (match_operand:DI 3 "const_int_operand" ""))]
14065 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14071 ;; Most CPUs don't like single string operations
14072 ;; Handle this case here to simplify previous expander.
14074 (define_expand "strmovdi_rex64"
14075 [(set (match_dup 2)
14076 (mem:DI (match_operand:DI 1 "register_operand" "")))
14077 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14079 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14080 (clobber (reg:CC 17))])
14081 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14082 (clobber (reg:CC 17))])]
14086 if (TARGET_SINGLE_STRINGOP || optimize_size)
14088 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14093 operands[2] = gen_reg_rtx (DImode);
14097 (define_expand "strmovsi"
14098 [(set (match_dup 2)
14099 (mem:SI (match_operand:SI 1 "register_operand" "")))
14100 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14102 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14103 (clobber (reg:CC 17))])
14104 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14105 (clobber (reg:CC 17))])]
14111 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14114 if (TARGET_SINGLE_STRINGOP || optimize_size)
14116 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14121 operands[2] = gen_reg_rtx (SImode);
14124 (define_expand "strmovsi_rex64"
14125 [(set (match_dup 2)
14126 (mem:SI (match_operand:DI 1 "register_operand" "")))
14127 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14129 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14130 (clobber (reg:CC 17))])
14131 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14132 (clobber (reg:CC 17))])]
14136 if (TARGET_SINGLE_STRINGOP || optimize_size)
14138 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14143 operands[2] = gen_reg_rtx (SImode);
14146 (define_expand "strmovhi"
14147 [(set (match_dup 2)
14148 (mem:HI (match_operand:SI 1 "register_operand" "")))
14149 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14151 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14152 (clobber (reg:CC 17))])
14153 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14154 (clobber (reg:CC 17))])]
14160 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14163 if (TARGET_SINGLE_STRINGOP || optimize_size)
14165 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14170 operands[2] = gen_reg_rtx (HImode);
14173 (define_expand "strmovhi_rex64"
14174 [(set (match_dup 2)
14175 (mem:HI (match_operand:DI 1 "register_operand" "")))
14176 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14178 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14179 (clobber (reg:CC 17))])
14180 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14181 (clobber (reg:CC 17))])]
14185 if (TARGET_SINGLE_STRINGOP || optimize_size)
14187 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14192 operands[2] = gen_reg_rtx (HImode);
14195 (define_expand "strmovqi"
14196 [(set (match_dup 2)
14197 (mem:QI (match_operand:SI 1 "register_operand" "")))
14198 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14200 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14201 (clobber (reg:CC 17))])
14202 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14203 (clobber (reg:CC 17))])]
14209 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14212 if (TARGET_SINGLE_STRINGOP || optimize_size)
14214 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14219 operands[2] = gen_reg_rtx (QImode);
14222 (define_expand "strmovqi_rex64"
14223 [(set (match_dup 2)
14224 (mem:QI (match_operand:DI 1 "register_operand" "")))
14225 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14227 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14228 (clobber (reg:CC 17))])
14229 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14230 (clobber (reg:CC 17))])]
14234 if (TARGET_SINGLE_STRINGOP || optimize_size)
14236 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14241 operands[2] = gen_reg_rtx (QImode);
14244 (define_insn "strmovdi_rex_1"
14245 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14246 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14247 (set (match_operand:DI 0 "register_operand" "=D")
14248 (plus:DI (match_dup 2)
14250 (set (match_operand:DI 1 "register_operand" "=S")
14251 (plus:DI (match_dup 3)
14254 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14256 [(set_attr "type" "str")
14257 (set_attr "mode" "DI")
14258 (set_attr "memory" "both")])
14260 (define_insn "strmovsi_1"
14261 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
14262 (mem:SI (match_operand:SI 3 "register_operand" "1")))
14263 (set (match_operand:SI 0 "register_operand" "=D")
14264 (plus:SI (match_dup 2)
14266 (set (match_operand:SI 1 "register_operand" "=S")
14267 (plus:SI (match_dup 3)
14270 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14272 [(set_attr "type" "str")
14273 (set_attr "mode" "SI")
14274 (set_attr "memory" "both")])
14276 (define_insn "strmovsi_rex_1"
14277 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
14278 (mem:SI (match_operand:DI 3 "register_operand" "1")))
14279 (set (match_operand:DI 0 "register_operand" "=D")
14280 (plus:DI (match_dup 2)
14282 (set (match_operand:DI 1 "register_operand" "=S")
14283 (plus:DI (match_dup 3)
14286 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14288 [(set_attr "type" "str")
14289 (set_attr "mode" "SI")
14290 (set_attr "memory" "both")])
14292 (define_insn "strmovhi_1"
14293 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
14294 (mem:HI (match_operand:SI 3 "register_operand" "1")))
14295 (set (match_operand:SI 0 "register_operand" "=D")
14296 (plus:SI (match_dup 2)
14298 (set (match_operand:SI 1 "register_operand" "=S")
14299 (plus:SI (match_dup 3)
14302 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14304 [(set_attr "type" "str")
14305 (set_attr "memory" "both")
14306 (set_attr "mode" "HI")])
14308 (define_insn "strmovhi_rex_1"
14309 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
14310 (mem:HI (match_operand:DI 3 "register_operand" "1")))
14311 (set (match_operand:DI 0 "register_operand" "=D")
14312 (plus:DI (match_dup 2)
14314 (set (match_operand:DI 1 "register_operand" "=S")
14315 (plus:DI (match_dup 3)
14318 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14320 [(set_attr "type" "str")
14321 (set_attr "memory" "both")
14322 (set_attr "mode" "HI")])
14324 (define_insn "strmovqi_1"
14325 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
14326 (mem:QI (match_operand:SI 3 "register_operand" "1")))
14327 (set (match_operand:SI 0 "register_operand" "=D")
14328 (plus:SI (match_dup 2)
14330 (set (match_operand:SI 1 "register_operand" "=S")
14331 (plus:SI (match_dup 3)
14334 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14336 [(set_attr "type" "str")
14337 (set_attr "memory" "both")
14338 (set_attr "mode" "QI")])
14340 (define_insn "strmovqi_rex_1"
14341 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
14342 (mem:QI (match_operand:DI 3 "register_operand" "1")))
14343 (set (match_operand:DI 0 "register_operand" "=D")
14344 (plus:DI (match_dup 2)
14346 (set (match_operand:DI 1 "register_operand" "=S")
14347 (plus:DI (match_dup 3)
14350 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14352 [(set_attr "type" "str")
14353 (set_attr "memory" "both")
14354 (set_attr "mode" "QI")])
14356 (define_insn "rep_movdi_rex64"
14357 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14358 (set (match_operand:DI 0 "register_operand" "=D")
14359 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14361 (match_operand:DI 3 "register_operand" "0")))
14362 (set (match_operand:DI 1 "register_operand" "=S")
14363 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
14364 (match_operand:DI 4 "register_operand" "1")))
14365 (set (mem:BLK (match_dup 3))
14366 (mem:BLK (match_dup 4)))
14367 (use (match_dup 5))
14370 "rep\;movsq|rep movsq"
14371 [(set_attr "type" "str")
14372 (set_attr "prefix_rep" "1")
14373 (set_attr "memory" "both")
14374 (set_attr "mode" "DI")])
14376 (define_insn "rep_movsi"
14377 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14378 (set (match_operand:SI 0 "register_operand" "=D")
14379 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
14381 (match_operand:SI 3 "register_operand" "0")))
14382 (set (match_operand:SI 1 "register_operand" "=S")
14383 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
14384 (match_operand:SI 4 "register_operand" "1")))
14385 (set (mem:BLK (match_dup 3))
14386 (mem:BLK (match_dup 4)))
14387 (use (match_dup 5))
14390 "rep\;movsl|rep movsd"
14391 [(set_attr "type" "str")
14392 (set_attr "prefix_rep" "1")
14393 (set_attr "memory" "both")
14394 (set_attr "mode" "SI")])
14396 (define_insn "rep_movsi_rex64"
14397 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14398 (set (match_operand:DI 0 "register_operand" "=D")
14399 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
14401 (match_operand:DI 3 "register_operand" "0")))
14402 (set (match_operand:DI 1 "register_operand" "=S")
14403 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
14404 (match_operand:DI 4 "register_operand" "1")))
14405 (set (mem:BLK (match_dup 3))
14406 (mem:BLK (match_dup 4)))
14407 (use (match_dup 5))
14410 "rep\;movsl|rep movsd"
14411 [(set_attr "type" "str")
14412 (set_attr "prefix_rep" "1")
14413 (set_attr "memory" "both")
14414 (set_attr "mode" "SI")])
14416 (define_insn "rep_movqi"
14417 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
14418 (set (match_operand:SI 0 "register_operand" "=D")
14419 (plus:SI (match_operand:SI 3 "register_operand" "0")
14420 (match_operand:SI 5 "register_operand" "2")))
14421 (set (match_operand:SI 1 "register_operand" "=S")
14422 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
14423 (set (mem:BLK (match_dup 3))
14424 (mem:BLK (match_dup 4)))
14425 (use (match_dup 5))
14428 "rep\;movsb|rep movsb"
14429 [(set_attr "type" "str")
14430 (set_attr "prefix_rep" "1")
14431 (set_attr "memory" "both")
14432 (set_attr "mode" "SI")])
14434 (define_insn "rep_movqi_rex64"
14435 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
14436 (set (match_operand:DI 0 "register_operand" "=D")
14437 (plus:DI (match_operand:DI 3 "register_operand" "0")
14438 (match_operand:DI 5 "register_operand" "2")))
14439 (set (match_operand:DI 1 "register_operand" "=S")
14440 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
14441 (set (mem:BLK (match_dup 3))
14442 (mem:BLK (match_dup 4)))
14443 (use (match_dup 5))
14446 "rep\;movsb|rep movsb"
14447 [(set_attr "type" "str")
14448 (set_attr "prefix_rep" "1")
14449 (set_attr "memory" "both")
14450 (set_attr "mode" "SI")])
14452 (define_expand "clrstrsi"
14453 [(use (match_operand:BLK 0 "memory_operand" ""))
14454 (use (match_operand:SI 1 "nonmemory_operand" ""))
14455 (use (match_operand 2 "const_int_operand" ""))]
14459 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14465 (define_expand "clrstrdi"
14466 [(use (match_operand:BLK 0 "memory_operand" ""))
14467 (use (match_operand:DI 1 "nonmemory_operand" ""))
14468 (use (match_operand 2 "const_int_operand" ""))]
14472 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
14478 ;; Most CPUs don't like single string operations
14479 ;; Handle this case here to simplify previous expander.
14481 (define_expand "strsetdi_rex64"
14482 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
14483 (match_operand:DI 1 "register_operand" ""))
14484 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14485 (clobber (reg:CC 17))])]
14489 if (TARGET_SINGLE_STRINGOP || optimize_size)
14491 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
14496 (define_expand "strsetsi"
14497 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
14498 (match_operand:SI 1 "register_operand" ""))
14499 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14500 (clobber (reg:CC 17))])]
14506 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
14509 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14511 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
14516 (define_expand "strsetsi_rex64"
14517 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
14518 (match_operand:SI 1 "register_operand" ""))
14519 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14520 (clobber (reg:CC 17))])]
14524 if (TARGET_SINGLE_STRINGOP || optimize_size)
14526 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
14531 (define_expand "strsethi"
14532 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
14533 (match_operand:HI 1 "register_operand" ""))
14534 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14535 (clobber (reg:CC 17))])]
14541 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
14544 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14546 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
14551 (define_expand "strsethi_rex64"
14552 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
14553 (match_operand:HI 1 "register_operand" ""))
14554 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14555 (clobber (reg:CC 17))])]
14559 if (TARGET_SINGLE_STRINGOP || optimize_size)
14561 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
14566 (define_expand "strsetqi"
14567 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
14568 (match_operand:QI 1 "register_operand" ""))
14569 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14570 (clobber (reg:CC 17))])]
14576 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
14579 else if (TARGET_SINGLE_STRINGOP || optimize_size)
14581 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
14586 (define_expand "strsetqi_rex64"
14587 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
14588 (match_operand:QI 1 "register_operand" ""))
14589 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14590 (clobber (reg:CC 17))])]
14594 if (TARGET_SINGLE_STRINGOP || optimize_size)
14596 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
14601 (define_insn "strsetdi_rex_1"
14602 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
14603 (match_operand:SI 2 "register_operand" "a"))
14604 (set (match_operand:DI 0 "register_operand" "=D")
14605 (plus:DI (match_dup 1)
14608 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14610 [(set_attr "type" "str")
14611 (set_attr "memory" "store")
14612 (set_attr "mode" "DI")])
14614 (define_insn "strsetsi_1"
14615 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
14616 (match_operand:SI 2 "register_operand" "a"))
14617 (set (match_operand:SI 0 "register_operand" "=D")
14618 (plus:SI (match_dup 1)
14621 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14623 [(set_attr "type" "str")
14624 (set_attr "memory" "store")
14625 (set_attr "mode" "SI")])
14627 (define_insn "strsetsi_rex_1"
14628 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
14629 (match_operand:SI 2 "register_operand" "a"))
14630 (set (match_operand:DI 0 "register_operand" "=D")
14631 (plus:DI (match_dup 1)
14634 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14636 [(set_attr "type" "str")
14637 (set_attr "memory" "store")
14638 (set_attr "mode" "SI")])
14640 (define_insn "strsethi_1"
14641 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
14642 (match_operand:HI 2 "register_operand" "a"))
14643 (set (match_operand:SI 0 "register_operand" "=D")
14644 (plus:SI (match_dup 1)
14647 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14649 [(set_attr "type" "str")
14650 (set_attr "memory" "store")
14651 (set_attr "mode" "HI")])
14653 (define_insn "strsethi_rex_1"
14654 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
14655 (match_operand:HI 2 "register_operand" "a"))
14656 (set (match_operand:DI 0 "register_operand" "=D")
14657 (plus:DI (match_dup 1)
14660 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14662 [(set_attr "type" "str")
14663 (set_attr "memory" "store")
14664 (set_attr "mode" "HI")])
14666 (define_insn "strsetqi_1"
14667 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
14668 (match_operand:QI 2 "register_operand" "a"))
14669 (set (match_operand:SI 0 "register_operand" "=D")
14670 (plus:SI (match_dup 1)
14673 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14675 [(set_attr "type" "str")
14676 (set_attr "memory" "store")
14677 (set_attr "mode" "QI")])
14679 (define_insn "strsetqi_rex_1"
14680 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
14681 (match_operand:QI 2 "register_operand" "a"))
14682 (set (match_operand:DI 0 "register_operand" "=D")
14683 (plus:DI (match_dup 1)
14686 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
14688 [(set_attr "type" "str")
14689 (set_attr "memory" "store")
14690 (set_attr "mode" "QI")])
14692 (define_insn "rep_stosdi_rex64"
14693 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
14694 (set (match_operand:DI 0 "register_operand" "=D")
14695 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
14697 (match_operand:DI 3 "register_operand" "0")))
14698 (set (mem:BLK (match_dup 3))
14700 (use (match_operand:DI 2 "register_operand" "a"))
14701 (use (match_dup 4))
14704 "rep\;stosq|rep stosq"
14705 [(set_attr "type" "str")
14706 (set_attr "prefix_rep" "1")
14707 (set_attr "memory" "store")
14708 (set_attr "mode" "DI")])
14710 (define_insn "rep_stossi"
14711 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
14712 (set (match_operand:SI 0 "register_operand" "=D")
14713 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
14715 (match_operand:SI 3 "register_operand" "0")))
14716 (set (mem:BLK (match_dup 3))
14718 (use (match_operand:SI 2 "register_operand" "a"))
14719 (use (match_dup 4))
14722 "rep\;stosl|rep stosd"
14723 [(set_attr "type" "str")
14724 (set_attr "prefix_rep" "1")
14725 (set_attr "memory" "store")
14726 (set_attr "mode" "SI")])
14728 (define_insn "rep_stossi_rex64"
14729 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
14730 (set (match_operand:DI 0 "register_operand" "=D")
14731 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
14733 (match_operand:DI 3 "register_operand" "0")))
14734 (set (mem:BLK (match_dup 3))
14736 (use (match_operand:SI 2 "register_operand" "a"))
14737 (use (match_dup 4))
14740 "rep\;stosl|rep stosd"
14741 [(set_attr "type" "str")
14742 (set_attr "prefix_rep" "1")
14743 (set_attr "memory" "store")
14744 (set_attr "mode" "SI")])
14746 (define_insn "rep_stosqi"
14747 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
14748 (set (match_operand:SI 0 "register_operand" "=D")
14749 (plus:SI (match_operand:SI 3 "register_operand" "0")
14750 (match_operand:SI 4 "register_operand" "1")))
14751 (set (mem:BLK (match_dup 3))
14753 (use (match_operand:QI 2 "register_operand" "a"))
14754 (use (match_dup 4))
14757 "rep\;stosb|rep stosb"
14758 [(set_attr "type" "str")
14759 (set_attr "prefix_rep" "1")
14760 (set_attr "memory" "store")
14761 (set_attr "mode" "QI")])
14763 (define_insn "rep_stosqi_rex64"
14764 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
14765 (set (match_operand:DI 0 "register_operand" "=D")
14766 (plus:DI (match_operand:DI 3 "register_operand" "0")
14767 (match_operand:DI 4 "register_operand" "1")))
14768 (set (mem:BLK (match_dup 3))
14770 (use (match_operand:QI 2 "register_operand" "a"))
14771 (use (match_dup 4))
14774 "rep\;stosb|rep stosb"
14775 [(set_attr "type" "str")
14776 (set_attr "prefix_rep" "1")
14777 (set_attr "memory" "store")
14778 (set_attr "mode" "QI")])
14780 (define_expand "cmpstrsi"
14781 [(set (match_operand:SI 0 "register_operand" "")
14782 (compare:SI (match_operand:BLK 1 "general_operand" "")
14783 (match_operand:BLK 2 "general_operand" "")))
14784 (use (match_operand 3 "general_operand" ""))
14785 (use (match_operand 4 "immediate_operand" ""))]
14789 rtx addr1, addr2, out, outlow, count, countreg, align;
14792 if (GET_CODE (out) != REG)
14793 out = gen_reg_rtx (SImode);
14795 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
14796 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
14798 count = operands[3];
14799 countreg = copy_to_mode_reg (Pmode, count);
14801 /* %%% Iff we are testing strict equality, we can use known alignment
14802 to good advantage. This may be possible with combine, particularly
14803 once cc0 is dead. */
14804 align = operands[4];
14806 emit_insn (gen_cld ());
14807 if (GET_CODE (count) == CONST_INT)
14809 if (INTVAL (count) == 0)
14811 emit_move_insn (operands[0], const0_rtx);
14815 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
14816 addr1, addr2, countreg));
14818 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
14819 addr1, addr2, countreg));
14825 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
14826 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
14827 addr1, addr2, countreg));
14831 emit_insn (gen_cmpsi_1 (countreg, countreg));
14832 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
14833 addr1, addr2, countreg));
14837 outlow = gen_lowpart (QImode, out);
14838 emit_insn (gen_cmpintqi (outlow));
14839 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
14841 if (operands[0] != out)
14842 emit_move_insn (operands[0], out);
14847 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
14849 (define_expand "cmpintqi"
14850 [(set (match_dup 1)
14851 (gtu:QI (reg:CC 17) (const_int 0)))
14853 (ltu:QI (reg:CC 17) (const_int 0)))
14854 (parallel [(set (match_operand:QI 0 "register_operand" "")
14855 (minus:QI (match_dup 1)
14857 (clobber (reg:CC 17))])]
14859 "operands[1] = gen_reg_rtx (QImode);
14860 operands[2] = gen_reg_rtx (QImode);")
14862 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
14863 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
14865 (define_insn "cmpstrqi_nz_1"
14867 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
14868 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
14869 (use (match_operand:SI 6 "register_operand" "2"))
14870 (use (match_operand:SI 3 "immediate_operand" "i"))
14872 (clobber (match_operand:SI 0 "register_operand" "=S"))
14873 (clobber (match_operand:SI 1 "register_operand" "=D"))
14874 (clobber (match_operand:SI 2 "register_operand" "=c"))]
14877 [(set_attr "type" "str")
14878 (set_attr "mode" "QI")
14879 (set_attr "prefix_rep" "1")])
14881 (define_insn "cmpstrqi_nz_rex_1"
14883 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
14884 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
14885 (use (match_operand:DI 6 "register_operand" "2"))
14886 (use (match_operand:SI 3 "immediate_operand" "i"))
14888 (clobber (match_operand:DI 0 "register_operand" "=S"))
14889 (clobber (match_operand:DI 1 "register_operand" "=D"))
14890 (clobber (match_operand:DI 2 "register_operand" "=c"))]
14893 [(set_attr "type" "str")
14894 (set_attr "mode" "QI")
14895 (set_attr "prefix_rep" "1")])
14897 ;; The same, but the count is not known to not be zero.
14899 (define_insn "cmpstrqi_1"
14901 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
14903 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
14904 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
14906 (use (match_operand:SI 3 "immediate_operand" "i"))
14909 (clobber (match_operand:SI 0 "register_operand" "=S"))
14910 (clobber (match_operand:SI 1 "register_operand" "=D"))
14911 (clobber (match_operand:SI 2 "register_operand" "=c"))]
14914 [(set_attr "type" "str")
14915 (set_attr "mode" "QI")
14916 (set_attr "prefix_rep" "1")])
14918 (define_insn "cmpstrqi_rex_1"
14920 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
14922 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
14923 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
14925 (use (match_operand:SI 3 "immediate_operand" "i"))
14928 (clobber (match_operand:DI 0 "register_operand" "=S"))
14929 (clobber (match_operand:DI 1 "register_operand" "=D"))
14930 (clobber (match_operand:DI 2 "register_operand" "=c"))]
14933 [(set_attr "type" "str")
14934 (set_attr "mode" "QI")
14935 (set_attr "prefix_rep" "1")])
14937 (define_expand "strlensi"
14938 [(set (match_operand:SI 0 "register_operand" "")
14939 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
14940 (match_operand:QI 2 "immediate_operand" "")
14941 (match_operand 3 "immediate_operand" "")] 0))]
14945 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
14951 (define_expand "strlendi"
14952 [(set (match_operand:DI 0 "register_operand" "")
14953 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
14954 (match_operand:QI 2 "immediate_operand" "")
14955 (match_operand 3 "immediate_operand" "")] 0))]
14959 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
14965 (define_insn "strlenqi_1"
14966 [(set (match_operand:SI 0 "register_operand" "=&c")
14967 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
14968 (match_operand:QI 2 "register_operand" "a")
14969 (match_operand:SI 3 "immediate_operand" "i")
14970 (match_operand:SI 4 "register_operand" "0")] 0))
14972 (clobber (match_operand:SI 1 "register_operand" "=D"))
14973 (clobber (reg:CC 17))]
14976 [(set_attr "type" "str")
14977 (set_attr "mode" "QI")
14978 (set_attr "prefix_rep" "1")])
14980 (define_insn "strlenqi_rex_1"
14981 [(set (match_operand:DI 0 "register_operand" "=&c")
14982 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
14983 (match_operand:QI 2 "register_operand" "a")
14984 (match_operand:DI 3 "immediate_operand" "i")
14985 (match_operand:DI 4 "register_operand" "0")] 0))
14987 (clobber (match_operand:DI 1 "register_operand" "=D"))
14988 (clobber (reg:CC 17))]
14991 [(set_attr "type" "str")
14992 (set_attr "mode" "QI")
14993 (set_attr "prefix_rep" "1")])
14995 ;; Conditional move instructions.
14997 (define_expand "movdicc_rex64"
14998 [(set (match_operand:DI 0 "register_operand" "")
14999 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15000 (match_operand:DI 2 "x86_64_general_operand" "")
15001 (match_operand:DI 3 "x86_64_general_operand" "")))]
15003 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15005 (define_insn "x86_movdicc_0_m1_rex64"
15006 [(set (match_operand:DI 0 "register_operand" "=r")
15007 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15010 (clobber (reg:CC 17))]
15013 ; Since we don't have the proper number of operands for an alu insn,
15014 ; fill in all the blanks.
15015 [(set_attr "type" "alu")
15016 (set_attr "memory" "none")
15017 (set_attr "imm_disp" "false")
15018 (set_attr "mode" "DI")
15019 (set_attr "length_immediate" "0")])
15021 (define_insn "*movdicc_c_rex64"
15022 [(set (match_operand:DI 0 "register_operand" "=r,r")
15023 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15024 [(reg 17) (const_int 0)])
15025 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15026 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15027 "TARGET_64BIT && TARGET_CMOVE
15028 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15030 cmov%C1\\t{%2, %0|%0, %2}
15031 cmov%c1\\t{%3, %0|%0, %3}"
15032 [(set_attr "type" "icmov")
15033 (set_attr "mode" "DI")])
15035 (define_expand "movsicc"
15036 [(set (match_operand:SI 0 "register_operand" "")
15037 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15038 (match_operand:SI 2 "general_operand" "")
15039 (match_operand:SI 3 "general_operand" "")))]
15041 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15043 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15044 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15045 ;; So just document what we're doing explicitly.
15047 (define_insn "x86_movsicc_0_m1"
15048 [(set (match_operand:SI 0 "register_operand" "=r")
15049 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15052 (clobber (reg:CC 17))]
15055 ; Since we don't have the proper number of operands for an alu insn,
15056 ; fill in all the blanks.
15057 [(set_attr "type" "alu")
15058 (set_attr "memory" "none")
15059 (set_attr "imm_disp" "false")
15060 (set_attr "mode" "SI")
15061 (set_attr "length_immediate" "0")])
15063 (define_insn "*movsicc_noc"
15064 [(set (match_operand:SI 0 "register_operand" "=r,r")
15065 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15066 [(reg 17) (const_int 0)])
15067 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15068 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15070 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15072 cmov%C1\\t{%2, %0|%0, %2}
15073 cmov%c1\\t{%3, %0|%0, %3}"
15074 [(set_attr "type" "icmov")
15075 (set_attr "mode" "SI")])
15077 (define_expand "movhicc"
15078 [(set (match_operand:HI 0 "register_operand" "")
15079 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15080 (match_operand:HI 2 "nonimmediate_operand" "")
15081 (match_operand:HI 3 "nonimmediate_operand" "")))]
15082 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15083 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15085 (define_insn "*movhicc_noc"
15086 [(set (match_operand:HI 0 "register_operand" "=r,r")
15087 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15088 [(reg 17) (const_int 0)])
15089 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15090 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15092 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15094 cmov%C1\\t{%2, %0|%0, %2}
15095 cmov%c1\\t{%3, %0|%0, %3}"
15096 [(set_attr "type" "icmov")
15097 (set_attr "mode" "HI")])
15099 (define_expand "movsfcc"
15100 [(set (match_operand:SF 0 "register_operand" "")
15101 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15102 (match_operand:SF 2 "register_operand" "")
15103 (match_operand:SF 3 "register_operand" "")))]
15105 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15107 (define_insn "*movsfcc_1"
15108 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15109 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15110 [(reg 17) (const_int 0)])
15111 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15112 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15114 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15116 fcmov%F1\\t{%2, %0|%0, %2}
15117 fcmov%f1\\t{%3, %0|%0, %3}
15118 cmov%C1\\t{%2, %0|%0, %2}
15119 cmov%c1\\t{%3, %0|%0, %3}"
15120 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15121 (set_attr "mode" "SF,SF,SI,SI")])
15123 (define_expand "movdfcc"
15124 [(set (match_operand:DF 0 "register_operand" "")
15125 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15126 (match_operand:DF 2 "register_operand" "")
15127 (match_operand:DF 3 "register_operand" "")))]
15129 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15131 (define_insn "*movdfcc_1"
15132 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15133 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15134 [(reg 17) (const_int 0)])
15135 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15136 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15137 "TARGET_CMOVE && !TARGET_64BIT
15138 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15140 fcmov%F1\\t{%2, %0|%0, %2}
15141 fcmov%f1\\t{%3, %0|%0, %3}
15144 [(set_attr "type" "fcmov,fcmov,multi,multi")
15145 (set_attr "mode" "DF")])
15147 (define_insn "*movdfcc_1_rex64"
15148 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15149 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15150 [(reg 17) (const_int 0)])
15151 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15152 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15153 "TARGET_CMOVE && TARGET_64BIT
15154 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15156 fcmov%F1\\t{%2, %0|%0, %2}
15157 fcmov%f1\\t{%3, %0|%0, %3}
15158 cmov%C1\\t{%2, %0|%0, %2}
15159 cmov%c1\\t{%3, %0|%0, %3}"
15160 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15161 (set_attr "mode" "DF")])
15164 [(set (match_operand:DF 0 "register_operand" "")
15165 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15166 [(match_operand 4 "" "") (const_int 0)])
15167 (match_operand:DF 2 "nonimmediate_operand" "")
15168 (match_operand:DF 3 "nonimmediate_operand" "")))]
15169 "!ANY_FP_REG_P (operands[0]) && reload_completed && !TARGET_64BIT"
15170 [(set (match_dup 2)
15171 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15175 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15178 "split_di (operands+2, 1, operands+5, operands+6);
15179 split_di (operands+3, 1, operands+7, operands+8);
15180 split_di (operands, 1, operands+2, operands+3);")
15182 (define_expand "movxfcc"
15183 [(set (match_operand:XF 0 "register_operand" "")
15184 (if_then_else:XF (match_operand 1 "comparison_operator" "")
15185 (match_operand:XF 2 "register_operand" "")
15186 (match_operand:XF 3 "register_operand" "")))]
15187 "TARGET_CMOVE && !TARGET_64BIT"
15188 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15190 (define_expand "movtfcc"
15191 [(set (match_operand:TF 0 "register_operand" "")
15192 (if_then_else:TF (match_operand 1 "comparison_operator" "")
15193 (match_operand:TF 2 "register_operand" "")
15194 (match_operand:TF 3 "register_operand" "")))]
15196 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15198 (define_insn "*movxfcc_1"
15199 [(set (match_operand:XF 0 "register_operand" "=f,f")
15200 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
15201 [(reg 17) (const_int 0)])
15202 (match_operand:XF 2 "register_operand" "f,0")
15203 (match_operand:XF 3 "register_operand" "0,f")))]
15204 "TARGET_CMOVE && !TARGET_64BIT"
15206 fcmov%F1\\t{%2, %0|%0, %2}
15207 fcmov%f1\\t{%3, %0|%0, %3}"
15208 [(set_attr "type" "fcmov")
15209 (set_attr "mode" "XF")])
15211 (define_insn "*movtfcc_1"
15212 [(set (match_operand:TF 0 "register_operand" "=f,f")
15213 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
15214 [(reg 17) (const_int 0)])
15215 (match_operand:TF 2 "register_operand" "f,0")
15216 (match_operand:TF 3 "register_operand" "0,f")))]
15219 fcmov%F1\\t{%2, %0|%0, %2}
15220 fcmov%f1\\t{%3, %0|%0, %3}"
15221 [(set_attr "type" "fcmov")
15222 (set_attr "mode" "XF")])
15224 (define_expand "minsf3"
15226 (set (match_operand:SF 0 "register_operand" "")
15227 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15228 (match_operand:SF 2 "nonimmediate_operand" ""))
15231 (clobber (reg:CC 17))])]
15235 (define_insn "*minsf"
15236 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15237 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
15238 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
15241 (clobber (reg:CC 17))]
15242 "TARGET_SSE && TARGET_IEEE_FP"
15245 (define_insn "*minsf_nonieee"
15246 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15247 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
15248 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15251 (clobber (reg:CC 17))]
15252 "TARGET_SSE && !TARGET_IEEE_FP"
15256 [(set (match_operand:SF 0 "register_operand" "")
15257 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15258 (match_operand:SF 2 "nonimmediate_operand" ""))
15261 (clobber (reg:CC 17))]
15262 "SSE_REG_P (operands[0]) && reload_completed"
15263 [(set (match_dup 0)
15264 (if_then_else:SF (lt (match_dup 1)
15269 ;; We can't represent the LT test directly. Do this by swapping the operands.
15271 [(set (match_operand:SF 0 "register_operand" "")
15272 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
15273 (match_operand:SF 2 "register_operand" ""))
15276 (clobber (reg:CC 17))]
15277 "FP_REG_P (operands[0]) && reload_completed"
15278 [(set (reg:CCFP 17)
15279 (compare:CCFP (match_dup 2)
15282 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
15286 (define_insn "*minsf_sse"
15287 [(set (match_operand:SF 0 "register_operand" "=x")
15288 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
15289 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15292 "TARGET_SSE && reload_completed"
15293 "minss\\t{%2, %0|%0, %2}"
15294 [(set_attr "type" "sse")
15295 (set_attr "mode" "SF")])
15297 (define_expand "mindf3"
15299 (set (match_operand:DF 0 "register_operand" "")
15300 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15301 (match_operand:DF 2 "nonimmediate_operand" ""))
15304 (clobber (reg:CC 17))])]
15308 (define_insn "*mindf"
15309 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15310 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15311 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
15314 (clobber (reg:CC 17))]
15315 "TARGET_SSE2 && TARGET_IEEE_FP"
15318 (define_insn "*mindf_nonieee"
15319 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15320 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
15321 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15324 (clobber (reg:CC 17))]
15325 "TARGET_SSE2 && !TARGET_IEEE_FP"
15329 [(set (match_operand:DF 0 "register_operand" "")
15330 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15331 (match_operand:DF 2 "nonimmediate_operand" ""))
15334 (clobber (reg:CC 17))]
15335 "SSE_REG_P (operands[0]) && reload_completed"
15336 [(set (match_dup 0)
15337 (if_then_else:DF (lt (match_dup 1)
15342 ;; We can't represent the LT test directly. Do this by swapping the operands.
15344 [(set (match_operand:DF 0 "register_operand" "")
15345 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
15346 (match_operand:DF 2 "register_operand" ""))
15349 (clobber (reg:CC 17))]
15350 "FP_REG_P (operands[0]) && reload_completed"
15351 [(set (reg:CCFP 17)
15352 (compare:CCFP (match_dup 2)
15355 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
15359 (define_insn "*mindf_sse"
15360 [(set (match_operand:DF 0 "register_operand" "=Y")
15361 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
15362 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15365 "TARGET_SSE2 && reload_completed"
15366 "minsd\\t{%2, %0|%0, %2}"
15367 [(set_attr "type" "sse")
15368 (set_attr "mode" "DF")])
15370 (define_expand "maxsf3"
15372 (set (match_operand:SF 0 "register_operand" "")
15373 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15374 (match_operand:SF 2 "nonimmediate_operand" ""))
15377 (clobber (reg:CC 17))])]
15381 (define_insn "*maxsf"
15382 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
15383 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
15384 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x,0"))
15387 (clobber (reg:CC 17))]
15388 "TARGET_SSE && TARGET_IEEE_FP"
15391 (define_insn "*maxsf_nonieee"
15392 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
15393 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
15394 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
15397 (clobber (reg:CC 17))]
15398 "TARGET_SSE && !TARGET_IEEE_FP"
15402 [(set (match_operand:SF 0 "register_operand" "")
15403 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15404 (match_operand:SF 2 "nonimmediate_operand" ""))
15407 (clobber (reg:CC 17))]
15408 "SSE_REG_P (operands[0]) && reload_completed"
15409 [(set (match_dup 0)
15410 (if_then_else:SF (gt (match_dup 1)
15416 [(set (match_operand:SF 0 "register_operand" "")
15417 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
15418 (match_operand:SF 2 "register_operand" ""))
15421 (clobber (reg:CC 17))]
15422 "FP_REG_P (operands[0]) && reload_completed"
15423 [(set (reg:CCFP 17)
15424 (compare:CCFP (match_dup 1)
15427 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
15431 (define_insn "*maxsf_sse"
15432 [(set (match_operand:SF 0 "register_operand" "=x")
15433 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
15434 (match_operand:SF 2 "nonimmediate_operand" "xm"))
15437 "TARGET_SSE && reload_completed"
15438 "maxss\\t{%2, %0|%0, %2}"
15439 [(set_attr "type" "sse")
15440 (set_attr "mode" "SF")])
15442 (define_expand "maxdf3"
15444 (set (match_operand:DF 0 "register_operand" "")
15445 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15446 (match_operand:DF 2 "nonimmediate_operand" ""))
15449 (clobber (reg:CC 17))])]
15453 (define_insn "*maxdf"
15454 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
15455 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
15456 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y,0"))
15459 (clobber (reg:CC 17))]
15460 "TARGET_SSE2 && TARGET_IEEE_FP"
15463 (define_insn "*maxdf_nonieee"
15464 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
15465 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
15466 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
15469 (clobber (reg:CC 17))]
15470 "TARGET_SSE2 && !TARGET_IEEE_FP"
15474 [(set (match_operand:DF 0 "register_operand" "")
15475 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15476 (match_operand:DF 2 "nonimmediate_operand" ""))
15479 (clobber (reg:CC 17))]
15480 "SSE_REG_P (operands[0]) && reload_completed"
15481 [(set (match_dup 0)
15482 (if_then_else:DF (gt (match_dup 1)
15488 [(set (match_operand:DF 0 "register_operand" "")
15489 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
15490 (match_operand:DF 2 "register_operand" ""))
15493 (clobber (reg:CC 17))]
15494 "FP_REG_P (operands[0]) && reload_completed"
15495 [(set (reg:CCFP 17)
15496 (compare:CCFP (match_dup 1)
15499 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
15503 (define_insn "*maxdf_sse"
15504 [(set (match_operand:DF 0 "register_operand" "=Y")
15505 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
15506 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
15509 "TARGET_SSE2 && reload_completed"
15510 "maxsd\\t{%2, %0|%0, %2}"
15511 [(set_attr "type" "sse")
15512 (set_attr "mode" "DF")])
15514 ;; Misc patterns (?)
15516 ;; This pattern exists to put a dependancy on all ebp-based memory accesses.
15517 ;; Otherwise there will be nothing to keep
15519 ;; [(set (reg ebp) (reg esp))]
15520 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
15521 ;; (clobber (eflags)]
15522 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
15524 ;; in proper program order.
15525 (define_expand "pro_epilogue_adjust_stack"
15526 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
15527 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
15528 (match_operand:SI 2 "immediate_operand" "i,i")))
15529 (set (match_operand:SI 3 "register_operand" "+r,r")
15531 (clobber (reg:CC 17))])]
15537 emit_insn (gen_pro_epilogue_adjust_stack_rex64 (operands[0], operands[1],
15538 operands[2], operands[3]));
15543 (define_insn "*pro_epilogue_adjust_stack_1"
15544 [(set (match_operand:SI 0 "register_operand" "=r,r")
15545 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
15546 (match_operand:SI 2 "immediate_operand" "i,i")))
15547 (set (match_operand:SI 3 "register_operand" "+r,r")
15549 (clobber (reg:CC 17))]
15553 switch (get_attr_type (insn))
15556 return \"mov{l}\\t{%1, %0|%0, %1}\";
15559 if (GET_CODE (operands[2]) == CONST_INT
15560 && (INTVAL (operands[2]) == 128
15561 || (INTVAL (operands[2]) < 0
15562 && INTVAL (operands[2]) != -128)))
15564 operands[2] = GEN_INT (-INTVAL (operands[2]));
15565 return \"sub{l}\\t{%2, %0|%0, %2}\";
15567 return \"add{l}\\t{%2, %0|%0, %2}\";
15570 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
15571 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
15577 [(set (attr "type")
15578 (cond [(eq_attr "alternative" "0")
15579 (const_string "alu")
15580 (match_operand:SI 2 "const0_operand" "")
15581 (const_string "imov")
15583 (const_string "lea")))
15584 (set_attr "mode" "SI")])
15586 (define_insn "pro_epilogue_adjust_stack_rex64"
15587 [(set (match_operand:DI 0 "register_operand" "=r,r")
15588 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
15589 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
15590 (set (match_operand:DI 3 "register_operand" "+r,r")
15592 (clobber (reg:CC 17))]
15596 switch (get_attr_type (insn))
15599 return \"mov{q}\\t{%1, %0|%0, %1}\";
15602 if (GET_CODE (operands[2]) == CONST_INT
15603 && (INTVAL (operands[2]) == 128
15604 || (INTVAL (operands[2]) < 0
15605 && INTVAL (operands[2]) != -128)))
15607 operands[2] = GEN_INT (-INTVAL (operands[2]));
15608 return \"sub{q}\\t{%2, %0|%0, %2}\";
15610 return \"add{q}\\t{%2, %0|%0, %2}\";
15613 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
15614 return \"lea{q}\\t{%a2, %0|%0, %a2}\";
15620 [(set (attr "type")
15621 (cond [(eq_attr "alternative" "0")
15622 (const_string "alu")
15623 (match_operand:DI 2 "const0_operand" "")
15624 (const_string "imov")
15626 (const_string "lea")))
15627 (set_attr "mode" "DI")])
15630 ;; Placeholder for the conditional moves. This one is split eighter to SSE
15631 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
15632 ;; fact is that compares supported by the cmp??ss instructions are exactly
15633 ;; swapped of those supported by cmove sequence.
15634 ;; The EQ/NE comparisons also needs bit care, since they are not directly
15635 ;; supported by i387 comparisons and we do need to emit two conditional moves
15638 (define_insn "sse_movsfcc"
15639 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
15640 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
15641 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
15642 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
15643 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
15644 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
15645 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
15646 (clobber (reg:CC 17))]
15648 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
15649 && (!TARGET_IEEE_FP
15650 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
15653 (define_insn "sse_movsfcc_eq"
15654 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
15655 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
15656 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
15657 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
15658 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
15659 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
15660 (clobber (reg:CC 17))]
15662 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15665 (define_insn "sse_movdfcc"
15666 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
15667 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
15668 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
15669 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
15670 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
15671 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
15672 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
15673 (clobber (reg:CC 17))]
15675 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
15676 && (!TARGET_IEEE_FP
15677 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
15680 (define_insn "sse_movdfcc_eq"
15681 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
15682 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
15683 (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
15684 (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
15685 (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
15686 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
15687 (clobber (reg:CC 17))]
15689 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15692 ;; For non-sse moves just expand the usual cmove sequence.
15694 [(set (match_operand 0 "register_operand" "")
15695 (if_then_else (match_operator 1 "comparison_operator"
15696 [(match_operand 4 "nonimmediate_operand" "")
15697 (match_operand 5 "register_operand" "")])
15698 (match_operand 2 "nonimmediate_operand" "")
15699 (match_operand 3 "nonimmediate_operand" "")))
15700 (clobber (match_operand 6 "" ""))
15701 (clobber (reg:CC 17))]
15702 "!SSE_REG_P (operands[0]) && reload_completed
15703 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
15707 ix86_compare_op0 = operands[5];
15708 ix86_compare_op1 = operands[4];
15709 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
15710 VOIDmode, operands[5], operands[4]);
15711 ix86_expand_fp_movcc (operands);
15715 ;; Split SSE based conditional move into seqence:
15716 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
15717 ;; and op2, op0 - zero op2 if comparison was false
15718 ;; nand op0, op3 - load op3 to op0 if comparison was false
15719 ;; or op2, op0 - get the non-zero one into the result.
15721 [(set (match_operand 0 "register_operand" "")
15722 (if_then_else (match_operator 1 "sse_comparison_operator"
15723 [(match_operand 4 "register_operand" "")
15724 (match_operand 5 "nonimmediate_operand" "")])
15725 (match_operand 2 "register_operand" "")
15726 (match_operand 3 "register_operand" "")))
15727 (clobber (match_operand 6 "" ""))
15728 (clobber (reg:CC 17))]
15729 "SSE_REG_P (operands[0]) && reload_completed"
15730 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
15731 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
15732 (subreg:TI (match_dup 4) 0)))
15733 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
15734 (subreg:TI (match_dup 3) 0)))
15735 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
15736 (subreg:TI (match_dup 7) 0)))]
15739 PUT_MODE (operands[1], GET_MODE (operands[0]));
15740 if (operands_match_p (operands[0], operands[4]))
15741 operands[6] = operands[4], operands[7] = operands[2];
15743 operands[6] = operands[2], operands[7] = operands[4];
15746 ;; Special case of conditional move we can handle effectivly.
15747 ;; Do not brother with the integer/floating point case, since these are
15748 ;; bot considerably slower, unlike in the generic case.
15749 (define_insn "*sse_movsfcc_const0_1"
15750 [(set (match_operand:SF 0 "register_operand" "=x")
15751 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
15752 [(match_operand:SF 4 "register_operand" "0")
15753 (match_operand:SF 5 "nonimmediate_operand" "xm")])
15754 (match_operand:SF 2 "register_operand" "x")
15755 (match_operand:SF 3 "const0_operand" "X")))]
15759 (define_insn "*sse_movsfcc_const0_2"
15760 [(set (match_operand:SF 0 "register_operand" "=x")
15761 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
15762 [(match_operand:SF 4 "register_operand" "0")
15763 (match_operand:SF 5 "nonimmediate_operand" "xm")])
15764 (match_operand:SF 2 "const0_operand" "x")
15765 (match_operand:SF 3 "register_operand" "X")))]
15769 (define_insn "*sse_movsfcc_const0_3"
15770 [(set (match_operand:SF 0 "register_operand" "=x")
15771 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15772 [(match_operand:SF 4 "nonimmediate_operand" "xm")
15773 (match_operand:SF 5 "register_operand" "0")])
15774 (match_operand:SF 2 "register_operand" "x")
15775 (match_operand:SF 3 "const0_operand" "X")))]
15779 (define_insn "*sse_movsfcc_const0_4"
15780 [(set (match_operand:SF 0 "register_operand" "=x")
15781 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15782 [(match_operand:SF 4 "nonimmediate_operand" "xm")
15783 (match_operand:SF 5 "register_operand" "0")])
15784 (match_operand:SF 2 "const0_operand" "x")
15785 (match_operand:SF 3 "register_operand" "X")))]
15789 (define_insn "*sse_movdfcc_const0_1"
15790 [(set (match_operand:SF 0 "register_operand" "=x")
15791 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
15792 [(match_operand:SF 4 "register_operand" "0")
15793 (match_operand:SF 5 "nonimmediate_operand" "xm")])
15794 (match_operand:SF 2 "register_operand" "x")
15795 (match_operand:SF 3 "const0_operand" "X")))]
15799 (define_insn "*sse_movdfcc_const0_2"
15800 [(set (match_operand:SF 0 "register_operand" "=x")
15801 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
15802 [(match_operand:SF 4 "register_operand" "0")
15803 (match_operand:SF 5 "nonimmediate_operand" "xm")])
15804 (match_operand:SF 2 "const0_operand" "x")
15805 (match_operand:SF 3 "register_operand" "X")))]
15809 (define_insn "*sse_movdfcc_const0_3"
15810 [(set (match_operand:SF 0 "register_operand" "=x")
15811 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15812 [(match_operand:SF 4 "nonimmediate_operand" "xm")
15813 (match_operand:SF 5 "register_operand" "0")])
15814 (match_operand:SF 2 "register_operand" "x")
15815 (match_operand:SF 3 "const0_operand" "X")))]
15819 (define_insn "*sse_movdfcc_const0_4"
15820 [(set (match_operand:SF 0 "register_operand" "=x")
15821 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15822 [(match_operand:SF 4 "nonimmediate_operand" "xm")
15823 (match_operand:SF 5 "register_operand" "0")])
15824 (match_operand:SF 2 "const0_operand" "x")
15825 (match_operand:SF 3 "register_operand" "X")))]
15830 [(set (match_operand 0 "register_operand" "")
15831 (if_then_else (match_operator 1 "comparison_operator"
15832 [(match_operand 4 "register_operand" "")
15833 (match_operand 5 "nonimmediate_operand" "")])
15834 (match_operand 2 "nonmemory_operand" "")
15835 (match_operand 3 "nonmemory_operand" "")))]
15836 "SSE_REG_P (operands[0]) && reload_completed
15837 && (const0_operand (operands[2], GET_MODE (operands[0]))
15838 || const0_operand (operands[3], GET_MODE (operands[0])))"
15839 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
15840 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
15841 (subreg:TI (match_dup 7) 0)))]
15844 PUT_MODE (operands[1], GET_MODE (operands[0]));
15845 if (!sse_comparison_operator (operands[1], VOIDmode))
15847 rtx tmp = operands[5];
15848 operands[5] = operands[4];
15850 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
15852 if (const0_operand (operands[2], GET_MODE (operands[0])))
15854 operands[7] = operands[3];
15855 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
15860 operands[7] = operands[2];
15861 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
15865 (define_expand "allocate_stack_worker"
15866 [(match_operand:SI 0 "register_operand" "")]
15867 "TARGET_STACK_PROBE"
15871 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
15873 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
15877 (define_insn "allocate_stack_worker_1"
15878 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
15879 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
15880 (clobber (match_dup 0))
15881 (clobber (reg:CC 17))]
15882 "TARGET_STACK_PROBE && !TARGET_64BIT"
15884 [(set_attr "type" "multi")
15885 (set_attr "length" "5")])
15887 (define_insn "allocate_stack_worker_rex64"
15888 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
15889 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
15890 (clobber (match_dup 0))
15891 (clobber (reg:CC 17))]
15892 "TARGET_STACK_PROBE && TARGET_64BIT"
15894 [(set_attr "type" "multi")
15895 (set_attr "length" "5")])
15897 (define_expand "allocate_stack"
15898 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
15899 (minus:SI (reg:SI 7)
15900 (match_operand:SI 1 "general_operand" "")))
15901 (clobber (reg:CC 17))])
15902 (parallel [(set (reg:SI 7)
15903 (minus:SI (reg:SI 7) (match_dup 1)))
15904 (clobber (reg:CC 17))])]
15905 "TARGET_STACK_PROBE"
15908 #ifdef CHECK_STACK_LIMIT
15909 if (GET_CODE (operands[1]) == CONST_INT
15910 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
15911 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
15915 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
15918 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
15922 (define_expand "builtin_setjmp_receiver"
15923 [(label_ref (match_operand 0 "" ""))]
15924 "flag_pic && !TARGET_64BIT"
15927 load_pic_register ();
15931 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
15934 [(set (match_operand 0 "register_operand" "")
15935 (match_operator 3 "promotable_binary_operator"
15936 [(match_operand 1 "register_operand" "")
15937 (match_operand 2 "aligned_operand" "")]))
15938 (clobber (reg:CC 17))]
15939 "! TARGET_PARTIAL_REG_STALL && reload_completed
15940 && ((GET_MODE (operands[0]) == HImode
15941 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
15942 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
15943 || (GET_MODE (operands[0]) == QImode
15944 && (TARGET_PROMOTE_QImode || optimize_size)))"
15945 [(parallel [(set (match_dup 0)
15946 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
15947 (clobber (reg:CC 17))])]
15948 "operands[0] = gen_lowpart (SImode, operands[0]);
15949 operands[1] = gen_lowpart (SImode, operands[1]);
15950 if (GET_CODE (operands[3]) != ASHIFT)
15951 operands[2] = gen_lowpart (SImode, operands[2]);
15952 PUT_MODE (operands[3], SImode);")
15956 (compare (and (match_operand 1 "aligned_operand" "")
15957 (match_operand 2 "const_int_operand" ""))
15959 (set (match_operand 0 "register_operand" "")
15960 (and (match_dup 1) (match_dup 2)))]
15961 "! TARGET_PARTIAL_REG_STALL && reload_completed
15962 && ix86_match_ccmode (insn, CCNOmode)
15963 && (GET_MODE (operands[0]) == HImode
15964 || (GET_MODE (operands[0]) == QImode
15965 && (TARGET_PROMOTE_QImode || optimize_size)))"
15966 [(parallel [(set (reg:CCNO 17)
15967 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
15970 (and:SI (match_dup 1) (match_dup 2)))])]
15972 = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (GET_MODE (operands[0])));
15973 operands[0] = gen_lowpart (SImode, operands[0]);
15974 operands[1] = gen_lowpart (SImode, operands[1]);")
15978 (compare (and (match_operand 0 "aligned_operand" "")
15979 (match_operand 1 "const_int_operand" ""))
15981 "! TARGET_PARTIAL_REG_STALL && reload_completed
15982 && ix86_match_ccmode (insn, CCNOmode)
15983 && (GET_MODE (operands[0]) == HImode
15984 || (GET_MODE (operands[0]) == QImode
15985 && (TARGET_PROMOTE_QImode || optimize_size)))"
15986 [(set (reg:CCNO 17)
15987 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
15990 = GEN_INT (INTVAL (operands[1]) & GET_MODE_MASK (GET_MODE (operands[0])));
15991 operands[0] = gen_lowpart (SImode, operands[0]);")
15994 [(set (match_operand 0 "register_operand" "")
15995 (neg (match_operand 1 "register_operand" "")))
15996 (clobber (reg:CC 17))]
15997 "! TARGET_PARTIAL_REG_STALL && reload_completed
15998 && (GET_MODE (operands[0]) == HImode
15999 || (GET_MODE (operands[0]) == QImode
16000 && (TARGET_PROMOTE_QImode || optimize_size)))"
16001 [(parallel [(set (match_dup 0)
16002 (neg:SI (match_dup 1)))
16003 (clobber (reg:CC 17))])]
16004 "operands[0] = gen_lowpart (SImode, operands[0]);
16005 operands[1] = gen_lowpart (SImode, operands[1]);")
16008 [(set (match_operand 0 "register_operand" "")
16009 (not (match_operand 1 "register_operand" "")))]
16010 "! TARGET_PARTIAL_REG_STALL && reload_completed
16011 && (GET_MODE (operands[0]) == HImode
16012 || (GET_MODE (operands[0]) == QImode
16013 && (TARGET_PROMOTE_QImode || optimize_size)))"
16014 [(set (match_dup 0)
16015 (not:SI (match_dup 1)))]
16016 "operands[0] = gen_lowpart (SImode, operands[0]);
16017 operands[1] = gen_lowpart (SImode, operands[1]);")
16020 [(set (match_operand 0 "register_operand" "")
16021 (if_then_else (match_operator 1 "comparison_operator"
16022 [(reg 17) (const_int 0)])
16023 (match_operand 2 "register_operand" "")
16024 (match_operand 3 "register_operand" "")))]
16025 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16026 && (GET_MODE (operands[0]) == HImode
16027 || (GET_MODE (operands[0]) == QImode
16028 && (TARGET_PROMOTE_QImode || optimize_size)))"
16029 [(set (match_dup 0)
16030 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16031 "operands[0] = gen_lowpart (SImode, operands[0]);
16032 operands[2] = gen_lowpart (SImode, operands[2]);
16033 operands[3] = gen_lowpart (SImode, operands[3]);")
16036 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16037 ;; transform a complex memory operation into two memory to register operations.
16039 ;; Don't push memory operands
16041 [(set (match_operand:SI 0 "push_operand" "")
16042 (match_operand:SI 1 "memory_operand" ""))
16043 (match_scratch:SI 2 "r")]
16044 "! optimize_size && ! TARGET_PUSH_MEMORY"
16045 [(set (match_dup 2) (match_dup 1))
16046 (set (match_dup 0) (match_dup 2))]
16050 [(set (match_operand:DI 0 "push_operand" "")
16051 (match_operand:DI 1 "memory_operand" ""))
16052 (match_scratch:DI 2 "r")]
16053 "! optimize_size && ! TARGET_PUSH_MEMORY"
16054 [(set (match_dup 2) (match_dup 1))
16055 (set (match_dup 0) (match_dup 2))]
16058 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16061 [(set (match_operand:SF 0 "push_operand" "")
16062 (match_operand:SF 1 "memory_operand" ""))
16063 (match_scratch:SF 2 "r")]
16064 "! optimize_size && ! TARGET_PUSH_MEMORY"
16065 [(set (match_dup 2) (match_dup 1))
16066 (set (match_dup 0) (match_dup 2))]
16070 [(set (match_operand:HI 0 "push_operand" "")
16071 (match_operand:HI 1 "memory_operand" ""))
16072 (match_scratch:HI 2 "r")]
16073 "! optimize_size && ! TARGET_PUSH_MEMORY"
16074 [(set (match_dup 2) (match_dup 1))
16075 (set (match_dup 0) (match_dup 2))]
16079 [(set (match_operand:QI 0 "push_operand" "")
16080 (match_operand:QI 1 "memory_operand" ""))
16081 (match_scratch:QI 2 "q")]
16082 "! optimize_size && ! TARGET_PUSH_MEMORY"
16083 [(set (match_dup 2) (match_dup 1))
16084 (set (match_dup 0) (match_dup 2))]
16087 ;; Don't move an immediate directly to memory when the instruction
16090 [(match_scratch:SI 1 "r")
16091 (set (match_operand:SI 0 "memory_operand" "")
16094 && ! TARGET_USE_MOV0
16095 && TARGET_SPLIT_LONG_MOVES
16096 && get_attr_length (insn) >= ix86_cost->large_insn
16097 && peep2_regno_dead_p (0, FLAGS_REG)"
16098 [(parallel [(set (match_dup 1) (const_int 0))
16099 (clobber (reg:CC 17))])
16100 (set (match_dup 0) (match_dup 1))]
16104 [(match_scratch:HI 1 "r")
16105 (set (match_operand:HI 0 "memory_operand" "")
16108 && ! TARGET_USE_MOV0
16109 && TARGET_SPLIT_LONG_MOVES
16110 && get_attr_length (insn) >= ix86_cost->large_insn
16111 && peep2_regno_dead_p (0, FLAGS_REG)"
16112 [(parallel [(set (match_dup 2) (const_int 0))
16113 (clobber (reg:CC 17))])
16114 (set (match_dup 0) (match_dup 1))]
16115 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16118 [(match_scratch:QI 1 "q")
16119 (set (match_operand:QI 0 "memory_operand" "")
16122 && ! TARGET_USE_MOV0
16123 && TARGET_SPLIT_LONG_MOVES
16124 && get_attr_length (insn) >= ix86_cost->large_insn
16125 && peep2_regno_dead_p (0, FLAGS_REG)"
16126 [(parallel [(set (match_dup 2) (const_int 0))
16127 (clobber (reg:CC 17))])
16128 (set (match_dup 0) (match_dup 1))]
16129 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16132 [(match_scratch:SI 2 "r")
16133 (set (match_operand:SI 0 "memory_operand" "")
16134 (match_operand:SI 1 "immediate_operand" ""))]
16136 && get_attr_length (insn) >= ix86_cost->large_insn
16137 && TARGET_SPLIT_LONG_MOVES"
16138 [(set (match_dup 2) (match_dup 1))
16139 (set (match_dup 0) (match_dup 2))]
16143 [(match_scratch:HI 2 "r")
16144 (set (match_operand:HI 0 "memory_operand" "")
16145 (match_operand:HI 1 "immediate_operand" ""))]
16146 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16147 && TARGET_SPLIT_LONG_MOVES"
16148 [(set (match_dup 2) (match_dup 1))
16149 (set (match_dup 0) (match_dup 2))]
16153 [(match_scratch:QI 2 "q")
16154 (set (match_operand:QI 0 "memory_operand" "")
16155 (match_operand:QI 1 "immediate_operand" ""))]
16156 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
16157 && TARGET_SPLIT_LONG_MOVES"
16158 [(set (match_dup 2) (match_dup 1))
16159 (set (match_dup 0) (match_dup 2))]
16162 ;; Don't compare memory with zero, load and use a test instead.
16165 (compare (match_operand:SI 0 "memory_operand" "")
16167 (match_scratch:SI 3 "r")]
16168 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
16169 [(set (match_dup 3) (match_dup 0))
16170 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
16173 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
16174 ;; Don't split NOTs with a displacement operand, because resulting XOR
16175 ;; will not be pariable anyway.
16177 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
16178 ;; represented using a modRM byte. The XOR replacement is long decoded,
16179 ;; so this split helps here as well.
16181 ;; Note: Can't do this as a regular split because we can't get proper
16182 ;; lifetime information then.
16185 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
16186 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
16188 && peep2_regno_dead_p (0, FLAGS_REG)
16189 && ((TARGET_PENTIUM
16190 && (GET_CODE (operands[0]) != MEM
16191 || !memory_displacement_operand (operands[0], SImode)))
16192 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
16193 [(parallel [(set (match_dup 0)
16194 (xor:SI (match_dup 1) (const_int -1)))
16195 (clobber (reg:CC 17))])]
16199 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
16200 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
16202 && peep2_regno_dead_p (0, FLAGS_REG)
16203 && ((TARGET_PENTIUM
16204 && (GET_CODE (operands[0]) != MEM
16205 || !memory_displacement_operand (operands[0], HImode)))
16206 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
16207 [(parallel [(set (match_dup 0)
16208 (xor:HI (match_dup 1) (const_int -1)))
16209 (clobber (reg:CC 17))])]
16213 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
16214 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
16216 && peep2_regno_dead_p (0, FLAGS_REG)
16217 && ((TARGET_PENTIUM
16218 && (GET_CODE (operands[0]) != MEM
16219 || !memory_displacement_operand (operands[0], QImode)))
16220 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
16221 [(parallel [(set (match_dup 0)
16222 (xor:QI (match_dup 1) (const_int -1)))
16223 (clobber (reg:CC 17))])]
16226 ;; Non pairable "test imm, reg" instructions can be translated to
16227 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
16228 ;; byte opcode instead of two, have a short form for byte operands),
16229 ;; so do it for other CPUs as well. Given that the value was dead,
16230 ;; this should not create any new dependancies. Pass on the sub-word
16231 ;; versions if we're concerned about partial register stalls.
16235 (compare (and:SI (match_operand:SI 0 "register_operand" "")
16236 (match_operand:SI 1 "immediate_operand" ""))
16238 "ix86_match_ccmode (insn, CCNOmode)
16239 && (true_regnum (operands[0]) != 0
16240 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
16241 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16243 [(set (reg:CCNO 17)
16244 (compare:CCNO (and:SI (match_dup 0)
16248 (and:SI (match_dup 0) (match_dup 1)))])]
16251 ;; We don't need to handle HImode case, because it will be promoted to SImode
16252 ;; on ! TARGET_PARTIAL_REG_STALL
16256 (compare (and:QI (match_operand:QI 0 "register_operand" "")
16257 (match_operand:QI 1 "immediate_operand" ""))
16259 "! TARGET_PARTIAL_REG_STALL
16260 && ix86_match_ccmode (insn, CCNOmode)
16261 && true_regnum (operands[0]) != 0
16262 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16264 [(set (reg:CCNO 17)
16265 (compare:CCNO (and:QI (match_dup 0)
16269 (and:QI (match_dup 0) (match_dup 1)))])]
16277 (match_operand 0 "ext_register_operand" "q")
16280 (match_operand 1 "const_int_operand" "n"))
16282 "! TARGET_PARTIAL_REG_STALL
16283 && ix86_match_ccmode (insn, CCNOmode)
16284 && true_regnum (operands[0]) != 0
16285 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16286 [(parallel [(set (reg:CCNO 17)
16295 (set (zero_extract:SI (match_dup 0)
16306 ;; Don't do logical operations with memory inputs.
16308 [(match_scratch:SI 2 "r")
16309 (parallel [(set (match_operand:SI 0 "register_operand" "")
16310 (match_operator:SI 3 "arith_or_logical_operator"
16312 (match_operand:SI 1 "memory_operand" "")]))
16313 (clobber (reg:CC 17))])]
16314 "! optimize_size && ! TARGET_READ_MODIFY"
16315 [(set (match_dup 2) (match_dup 1))
16316 (parallel [(set (match_dup 0)
16317 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
16318 (clobber (reg:CC 17))])]
16322 [(match_scratch:SI 2 "r")
16323 (parallel [(set (match_operand:SI 0 "register_operand" "")
16324 (match_operator:SI 3 "arith_or_logical_operator"
16325 [(match_operand:SI 1 "memory_operand" "")
16327 (clobber (reg:CC 17))])]
16328 "! optimize_size && ! TARGET_READ_MODIFY"
16329 [(set (match_dup 2) (match_dup 1))
16330 (parallel [(set (match_dup 0)
16331 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
16332 (clobber (reg:CC 17))])]
16335 ; Don't do logical operations with memory outputs
16337 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
16338 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
16339 ; the same decoder scheduling characteristics as the original.
16342 [(match_scratch:SI 2 "r")
16343 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16344 (match_operator:SI 3 "arith_or_logical_operator"
16346 (match_operand:SI 1 "nonmemory_operand" "")]))
16347 (clobber (reg:CC 17))])]
16348 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16349 [(set (match_dup 2) (match_dup 0))
16350 (parallel [(set (match_dup 2)
16351 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
16352 (clobber (reg:CC 17))])
16353 (set (match_dup 0) (match_dup 2))]
16357 [(match_scratch:SI 2 "r")
16358 (parallel [(set (match_operand:SI 0 "memory_operand" "")
16359 (match_operator:SI 3 "arith_or_logical_operator"
16360 [(match_operand:SI 1 "nonmemory_operand" "")
16362 (clobber (reg:CC 17))])]
16363 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
16364 [(set (match_dup 2) (match_dup 0))
16365 (parallel [(set (match_dup 2)
16366 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16367 (clobber (reg:CC 17))])
16368 (set (match_dup 0) (match_dup 2))]
16371 ;; Attempt to always use XOR for zeroing registers.
16373 [(set (match_operand 0 "register_operand" "")
16375 "(GET_MODE (operands[0]) == QImode
16376 || GET_MODE (operands[0]) == HImode
16377 || GET_MODE (operands[0]) == SImode
16378 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16379 && (! TARGET_USE_MOV0 || optimize_size)
16380 && peep2_regno_dead_p (0, FLAGS_REG)"
16381 [(parallel [(set (match_dup 0) (const_int 0))
16382 (clobber (reg:CC 17))])]
16383 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16384 true_regnum (operands[0]));")
16387 [(set (strict_low_part (match_operand 0 "register_operand" ""))
16389 "(GET_MODE (operands[0]) == QImode
16390 || GET_MODE (operands[0]) == HImode)
16391 && (! TARGET_USE_MOV0 || optimize_size)
16392 && peep2_regno_dead_p (0, FLAGS_REG)"
16393 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
16394 (clobber (reg:CC 17))])])
16396 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
16398 [(set (match_operand 0 "register_operand" "")
16400 "(GET_MODE (operands[0]) == HImode
16401 || GET_MODE (operands[0]) == SImode
16402 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
16403 && (optimize_size || TARGET_PENTIUM)
16404 && peep2_regno_dead_p (0, FLAGS_REG)"
16405 [(parallel [(set (match_dup 0) (const_int -1))
16406 (clobber (reg:CC 17))])]
16407 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
16408 true_regnum (operands[0]));")
16410 ;; Attempt to convert simple leas to adds. These can be created by
16413 [(set (match_operand:SI 0 "register_operand" "")
16414 (plus:SI (match_dup 0)
16415 (match_operand:SI 1 "nonmemory_operand" "")))]
16416 "peep2_regno_dead_p (0, FLAGS_REG)"
16417 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
16418 (clobber (reg:CC 17))])]
16422 [(set (match_operand:SI 0 "register_operand" "")
16423 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
16424 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
16425 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
16426 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
16427 (clobber (reg:CC 17))])]
16428 "operands[2] = gen_lowpart (SImode, operands[2]);")
16431 [(set (match_operand:DI 0 "register_operand" "")
16432 (plus:DI (match_dup 0)
16433 (match_operand:DI 1 "x86_64_general_operand" "")))]
16434 "peep2_regno_dead_p (0, FLAGS_REG)"
16435 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
16436 (clobber (reg:CC 17))])]
16440 [(set (match_operand:SI 0 "register_operand" "")
16441 (mult:SI (match_dup 0)
16442 (match_operand:SI 1 "const_int_operand" "")))]
16443 "exact_log2 (INTVAL (operands[1])) >= 0
16444 && peep2_regno_dead_p (0, FLAGS_REG)"
16445 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
16446 (clobber (reg:CC 17))])]
16447 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
16450 [(set (match_operand:DI 0 "register_operand" "")
16451 (mult:DI (match_dup 0)
16452 (match_operand:DI 1 "const_int_operand" "")))]
16453 "exact_log2 (INTVAL (operands[1])) >= 0
16454 && peep2_regno_dead_p (0, FLAGS_REG)"
16455 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
16456 (clobber (reg:CC 17))])]
16457 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
16460 [(set (match_operand:SI 0 "register_operand" "")
16461 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
16462 (match_operand:DI 2 "const_int_operand" "")) 0))]
16463 "exact_log2 (INTVAL (operands[1])) >= 0
16464 && REGNO (operands[0]) == REGNO (operands[1])
16465 && peep2_regno_dead_p (0, FLAGS_REG)"
16466 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
16467 (clobber (reg:CC 17))])]
16468 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
16470 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
16471 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
16472 ;; many CPUs it is also faster, since special hardware to avoid esp
16473 ;; dependancies is present.
16475 ;; While some of these converisons may be done using splitters, we use peepholes
16476 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
16478 ;; Convert prologue esp substractions to push.
16479 ;; We need register to push. In order to keep verify_flow_info happy we have
16481 ;; - use scratch and clobber it in order to avoid dependencies
16482 ;; - use already live register
16483 ;; We can't use the second way right now, since there is no reliable way how to
16484 ;; verify that given register is live. First choice will also most likely in
16485 ;; fewer dependencies. On the place of esp adjustments it is very likely that
16486 ;; call clobbered registers are dead. We may want to use base pointer as an
16487 ;; alternative when no register is available later.
16490 [(match_scratch:SI 0 "r")
16491 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
16492 (set (reg:SI 6) (reg:SI 6))
16493 (clobber (reg:CC 17))])]
16494 "optimize_size || !TARGET_SUB_ESP_4"
16495 [(clobber (match_dup 0))
16496 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16497 (set (reg:SI 6) (reg:SI 6))])])
16500 [(match_scratch:SI 0 "r")
16501 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
16502 (set (reg:SI 6) (reg:SI 6))
16503 (clobber (reg:CC 17))])]
16504 "optimize_size || !TARGET_SUB_ESP_8"
16505 [(clobber (match_dup 0))
16506 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16507 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16508 (set (reg:SI 6) (reg:SI 6))])])
16510 ;; Convert esp substractions to push.
16512 [(match_scratch:SI 0 "r")
16513 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
16514 (clobber (reg:CC 17))])]
16515 "optimize_size || !TARGET_SUB_ESP_4"
16516 [(clobber (match_dup 0))
16517 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
16520 [(match_scratch:SI 0 "r")
16521 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
16522 (clobber (reg:CC 17))])]
16523 "optimize_size || !TARGET_SUB_ESP_8"
16524 [(clobber (match_dup 0))
16525 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
16526 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
16528 ;; Convert epilogue deallocator to pop.
16530 [(match_scratch:SI 0 "r")
16531 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16532 (set (reg:SI 6) (reg:SI 6))
16533 (clobber (reg:CC 17))])]
16534 "optimize_size || !TARGET_ADD_ESP_4"
16535 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16536 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16537 (set (reg:SI 6) (reg:SI 6))])]
16540 ;; Two pops case is tricky, since pop causes dependency on destination register.
16541 ;; We use two registers if available.
16543 [(match_scratch:SI 0 "r")
16544 (match_scratch:SI 1 "r")
16545 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
16546 (set (reg:SI 6) (reg:SI 6))
16547 (clobber (reg:CC 17))])]
16548 "optimize_size || !TARGET_ADD_ESP_8"
16549 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16550 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16551 (set (reg:SI 6) (reg:SI 6))])
16552 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
16553 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
16557 [(match_scratch:SI 0 "r")
16558 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
16559 (set (reg:SI 6) (reg:SI 6))
16560 (clobber (reg:CC 17))])]
16562 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16563 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16564 (set (reg:SI 6) (reg:SI 6))])
16565 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16566 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
16569 ;; Convert esp additions to pop.
16571 [(match_scratch:SI 0 "r")
16572 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
16573 (clobber (reg:CC 17))])]
16575 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16576 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
16579 ;; Two pops case is tricky, since pop causes dependency on destination register.
16580 ;; We use two registers if available.
16582 [(match_scratch:SI 0 "r")
16583 (match_scratch:SI 1 "r")
16584 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
16585 (clobber (reg:CC 17))])]
16587 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16588 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
16589 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
16590 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
16594 [(match_scratch:SI 0 "r")
16595 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
16596 (clobber (reg:CC 17))])]
16598 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16599 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
16600 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
16601 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
16604 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
16605 ;; required and register dies.
16608 (compare (match_operand:SI 0 "register_operand" "")
16609 (match_operand:SI 1 "incdec_operand" "")))]
16610 "ix86_match_ccmode (insn, CCGCmode)
16611 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16612 [(parallel [(set (reg:CCGC 17)
16613 (compare:CCGC (match_dup 0)
16615 (clobber (match_dup 0))])]
16620 (compare (match_operand:HI 0 "register_operand" "")
16621 (match_operand:HI 1 "incdec_operand" "")))]
16622 "ix86_match_ccmode (insn, CCGCmode)
16623 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16624 [(parallel [(set (reg:CCGC 17)
16625 (compare:CCGC (match_dup 0)
16627 (clobber (match_dup 0))])]
16632 (compare (match_operand:QI 0 "register_operand" "")
16633 (match_operand:QI 1 "incdec_operand" "")))]
16634 "ix86_match_ccmode (insn, CCGCmode)
16635 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16636 [(parallel [(set (reg:CCGC 17)
16637 (compare:CCGC (match_dup 0)
16639 (clobber (match_dup 0))])]
16642 ;; Convert compares with 128 to shorter add -128
16645 (compare (match_operand:SI 0 "register_operand" "")
16647 "ix86_match_ccmode (insn, CCGCmode)
16648 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16649 [(parallel [(set (reg:CCGC 17)
16650 (compare:CCGC (match_dup 0)
16652 (clobber (match_dup 0))])]
16657 (compare (match_operand:HI 0 "register_operand" "")
16659 "ix86_match_ccmode (insn, CCGCmode)
16660 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
16661 [(parallel [(set (reg:CCGC 17)
16662 (compare:CCGC (match_dup 0)
16664 (clobber (match_dup 0))])]
16668 [(match_scratch:DI 0 "r")
16669 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
16670 (set (reg:DI 6) (reg:DI 6))
16671 (clobber (reg:CC 17))])]
16672 "optimize_size || !TARGET_SUB_ESP_4"
16673 [(clobber (match_dup 0))
16674 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
16675 (set (reg:DI 6) (reg:DI 6))])])
16678 [(match_scratch:DI 0 "r")
16679 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
16680 (set (reg:DI 6) (reg:DI 6))
16681 (clobber (reg:CC 17))])]
16682 "optimize_size || !TARGET_SUB_ESP_8"
16683 [(clobber (match_dup 0))
16684 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
16685 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
16686 (set (reg:DI 6) (reg:DI 6))])])
16688 ;; Convert esp substractions to push.
16690 [(match_scratch:DI 0 "r")
16691 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
16692 (clobber (reg:CC 17))])]
16693 "optimize_size || !TARGET_SUB_ESP_4"
16694 [(clobber (match_dup 0))
16695 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
16698 [(match_scratch:DI 0 "r")
16699 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
16700 (clobber (reg:CC 17))])]
16701 "optimize_size || !TARGET_SUB_ESP_8"
16702 [(clobber (match_dup 0))
16703 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
16704 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
16706 ;; Convert epilogue deallocator to pop.
16708 [(match_scratch:DI 0 "r")
16709 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
16710 (set (reg:DI 6) (reg:DI 6))
16711 (clobber (reg:CC 17))])]
16712 "optimize_size || !TARGET_ADD_ESP_4"
16713 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
16714 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
16715 (set (reg:DI 6) (reg:DI 6))])]
16718 ;; Two pops case is tricky, since pop causes dependency on destination register.
16719 ;; We use two registers if available.
16721 [(match_scratch:DI 0 "r")
16722 (match_scratch:DI 1 "r")
16723 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
16724 (set (reg:DI 6) (reg:DI 6))
16725 (clobber (reg:CC 17))])]
16726 "optimize_size || !TARGET_ADD_ESP_8"
16727 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
16728 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
16729 (set (reg:DI 6) (reg:DI 6))])
16730 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
16731 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
16735 [(match_scratch:DI 0 "r")
16736 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
16737 (set (reg:DI 6) (reg:DI 6))
16738 (clobber (reg:CC 17))])]
16740 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
16741 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
16742 (set (reg:DI 6) (reg:DI 6))])
16743 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
16744 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
16747 ;; Convert esp additions to pop.
16749 [(match_scratch:DI 0 "r")
16750 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
16751 (clobber (reg:CC 17))])]
16753 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
16754 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
16757 ;; Two pops case is tricky, since pop causes dependency on destination register.
16758 ;; We use two registers if available.
16760 [(match_scratch:DI 0 "r")
16761 (match_scratch:DI 1 "r")
16762 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
16763 (clobber (reg:CC 17))])]
16765 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
16766 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
16767 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
16768 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
16772 [(match_scratch:DI 0 "r")
16773 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
16774 (clobber (reg:CC 17))])]
16776 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
16777 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
16778 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
16779 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
16782 ;; Call-value patterns last so that the wildcard operand does not
16783 ;; disrupt insn-recog's switch tables.
16785 (define_insn "*call_value_pop_0"
16786 [(set (match_operand 0 "" "")
16787 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
16788 (match_operand:SI 2 "" "")))
16789 (set (reg:SI 7) (plus:SI (reg:SI 7)
16790 (match_operand:SI 3 "immediate_operand" "")))]
16794 if (SIBLING_CALL_P (insn))
16795 return \"jmp\\t%P1\";
16797 return \"call\\t%P1\";
16799 [(set_attr "type" "callv")])
16801 (define_insn "*call_value_pop_1"
16802 [(set (match_operand 0 "" "")
16803 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
16804 (match_operand:SI 2 "" "")))
16805 (set (reg:SI 7) (plus:SI (reg:SI 7)
16806 (match_operand:SI 3 "immediate_operand" "i")))]
16810 if (constant_call_address_operand (operands[1], QImode))
16812 if (SIBLING_CALL_P (insn))
16813 return \"jmp\\t%P1\";
16815 return \"call\\t%P1\";
16817 if (SIBLING_CALL_P (insn))
16818 return \"jmp\\t%A1\";
16820 return \"call\\t%A1\";
16822 [(set_attr "type" "callv")])
16824 (define_insn "*call_value_0"
16825 [(set (match_operand 0 "" "")
16826 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
16827 (match_operand:SI 2 "" "")))]
16831 if (SIBLING_CALL_P (insn))
16832 return \"jmp\\t%P1\";
16834 return \"call\\t%P1\";
16836 [(set_attr "type" "callv")])
16838 (define_insn "*call_value_0_rex64"
16839 [(set (match_operand 0 "" "")
16840 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
16841 (match_operand:DI 2 "const_int_operand" "")))]
16845 if (SIBLING_CALL_P (insn))
16846 return \"jmp\\t%P1\";
16848 return \"call\\t%P1\";
16850 [(set_attr "type" "callv")])
16852 (define_insn "*call_value_1"
16853 [(set (match_operand 0 "" "")
16854 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
16855 (match_operand:SI 2 "" "")))]
16859 if (constant_call_address_operand (operands[1], QImode))
16861 if (SIBLING_CALL_P (insn))
16862 return \"jmp\\t%P1\";
16864 return \"call\\t%P1\";
16866 if (SIBLING_CALL_P (insn))
16867 return \"jmp\\t%*%1\";
16869 return \"call\\t%*%1\";
16871 [(set_attr "type" "callv")])
16873 (define_insn "*call_value_1_rex64"
16874 [(set (match_operand 0 "" "")
16875 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
16876 (match_operand:DI 2 "" "")))]
16880 if (constant_call_address_operand (operands[1], QImode))
16882 if (SIBLING_CALL_P (insn))
16883 return \"jmp\\t%P1\";
16885 return \"call\\t%P1\";
16887 if (SIBLING_CALL_P (insn))
16888 return \"jmp\\t%A1\";
16890 return \"call\\t%A1\";
16892 [(set_attr "type" "callv")])
16894 (define_insn "trap"
16895 [(trap_if (const_int 1) (const_int 5))]
16899 ;;; ix86 doesn't have conditional trap instructions, but we fake them
16900 ;;; for the sake of bounds checking. By emitting bounds checks as
16901 ;;; conditional traps rather than as conditional jumps around
16902 ;;; unconditional traps we avoid introducing spurious basic-block
16903 ;;; boundaries and facilitate elimination of redundant checks. In
16904 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
16907 ;;; FIXME: Static branch prediction rules for ix86 are such that
16908 ;;; forward conditional branches predict as untaken. As implemented
16909 ;;; below, pseudo conditional traps violate that rule. We should use
16910 ;;; .pushsection/.popsection to place all of the `int 5's in a special
16911 ;;; section loaded at the end of the text segment and branch forward
16912 ;;; there on bounds-failure, and then jump back immediately (in case
16913 ;;; the system chooses to ignore bounds violations, or to report
16914 ;;; violations and continue execution).
16916 (define_expand "conditional_trap"
16917 [(trap_if (match_operator 0 "comparison_operator"
16918 [(match_dup 2) (const_int 0)])
16919 (match_operand 1 "const_int_operand" ""))]
16923 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
16924 ix86_expand_compare (GET_CODE (operands[0]),
16925 NULL_PTR, NULL_PTR),
16931 [(trap_if (match_operator 0 "comparison_operator"
16932 [(reg 17) (const_int 0)])
16933 (match_operand 1 "const_int_operand" ""))]
16937 operands[2] = gen_label_rtx ();
16938 output_asm_insn (\"j%c0\\t%l2\; int\\t%1\", operands);
16939 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
16940 CODE_LABEL_NUMBER (operands[2]));
16944 ;; Pentium III SIMD instructions.
16946 ;; Moves for SSE/MMX regs.
16948 (define_insn "movv4sf_internal"
16949 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
16950 (match_operand:V4SF 1 "general_operand" "xm,x"))]
16952 ;; @@@ let's try to use movaps here.
16953 "movaps\\t{%1, %0|%0, %1}"
16954 [(set_attr "type" "sse")])
16956 (define_insn "movv4si_internal"
16957 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
16958 (match_operand:V4SI 1 "general_operand" "xm,x"))]
16960 ;; @@@ let's try to use movaps here.
16961 "movaps\\t{%1, %0|%0, %1}"
16962 [(set_attr "type" "sse")])
16964 (define_insn "movv8qi_internal"
16965 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
16966 (match_operand:V8QI 1 "general_operand" "ym,y"))]
16968 "movq\\t{%1, %0|%0, %1}"
16969 [(set_attr "type" "mmx")])
16971 (define_insn "movv4hi_internal"
16972 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
16973 (match_operand:V4HI 1 "general_operand" "ym,y"))]
16975 "movq\\t{%1, %0|%0, %1}"
16976 [(set_attr "type" "mmx")])
16978 (define_insn "movv2si_internal"
16979 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
16980 (match_operand:V2SI 1 "general_operand" "ym,y"))]
16982 "movq\\t{%1, %0|%0, %1}"
16983 [(set_attr "type" "mmx")])
16985 (define_expand "movti"
16986 [(set (match_operand:TI 0 "general_operand" "")
16987 (match_operand:TI 1 "general_operand" ""))]
16991 /* For constants other than zero into memory. We do not know how the
16992 instructions used to build constants modify the upper 64 bits
16993 of the register, once we have that information we may be able
16994 to handle some of them more efficiently. */
16995 if ((reload_in_progress | reload_completed) == 0
16996 && register_operand (operands[0], TImode)
16997 && CONSTANT_P (operands[1]))
16999 rtx addr = gen_reg_rtx (Pmode);
17001 emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0));
17002 operands[1] = gen_rtx_MEM (TImode, addr);
17005 /* Make operand1 a register if it isn't already. */
17006 if ((reload_in_progress | reload_completed) == 0
17007 && !register_operand (operands[0], TImode)
17008 && !register_operand (operands[1], TImode)
17009 && operands[1] != CONST0_RTX (TImode))
17011 rtx temp = force_reg (TImode, operands[1]);
17012 emit_move_insn (operands[0], temp);
17017 (define_expand "movv4sf"
17018 [(set (match_operand:V4SF 0 "general_operand" "")
17019 (match_operand:V4SF 1 "general_operand" ""))]
17023 /* For constants other than zero into memory. We do not know how the
17024 instructions used to build constants modify the upper 64 bits
17025 of the register, once we have that information we may be able
17026 to handle some of them more efficiently. */
17027 if ((reload_in_progress | reload_completed) == 0
17028 && register_operand (operands[0], V4SFmode)
17029 && CONSTANT_P (operands[1]))
17031 rtx addr = gen_reg_rtx (Pmode);
17033 emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0));
17034 operands[1] = gen_rtx_MEM (V4SFmode, addr);
17037 /* Make operand1 a register if it isn't already. */
17038 if ((reload_in_progress | reload_completed) == 0
17039 && !register_operand (operands[0], V4SFmode)
17040 && !register_operand (operands[1], V4SFmode)
17041 && operands[1] != CONST0_RTX (V4SFmode))
17043 rtx temp = force_reg (V4SFmode, operands[1]);
17044 emit_move_insn (operands[0], temp);
17049 (define_expand "movv4si"
17050 [(set (match_operand:V4SI 0 "general_operand" "")
17051 (match_operand:V4SI 1 "general_operand" ""))]
17055 /* For constants other than zero into memory. We do not know how the
17056 instructions used to build constants modify the upper 64 bits
17057 of the register, once we have that information we may be able
17058 to handle some of them more efficiently. */
17059 if ((reload_in_progress | reload_completed) == 0
17060 && register_operand (operands[0], V4SImode)
17061 && CONSTANT_P (operands[1]))
17063 rtx addr = gen_reg_rtx (Pmode);
17065 emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0));
17066 operands[1] = gen_rtx_MEM (V4SImode, addr);
17069 /* Make operand1 a register if it isn't already. */
17070 if ((reload_in_progress | reload_completed) == 0
17071 && !register_operand (operands[0], V4SImode)
17072 && !register_operand (operands[1], V4SImode)
17073 && operands[1] != CONST0_RTX (V4SImode))
17075 rtx temp = force_reg (V4SImode, operands[1]);
17076 emit_move_insn (operands[0], temp);
17081 (define_expand "movv2si"
17082 [(set (match_operand:V2SI 0 "general_operand" "")
17083 (match_operand:V2SI 1 "general_operand" ""))]
17087 /* For constants other than zero into memory. We do not know how the
17088 instructions used to build constants modify the upper 64 bits
17089 of the register, once we have that information we may be able
17090 to handle some of them more efficiently. */
17091 if ((reload_in_progress | reload_completed) == 0
17092 && register_operand (operands[0], V2SImode)
17093 && CONSTANT_P (operands[1]))
17095 rtx addr = gen_reg_rtx (Pmode);
17097 emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0));
17098 operands[1] = gen_rtx_MEM (V2SImode, addr);
17101 /* Make operand1 a register if it isn't already. */
17102 if ((reload_in_progress | reload_completed) == 0
17103 && !register_operand (operands[0], V2SImode)
17104 && !register_operand (operands[1], V2SImode)
17105 && operands[1] != CONST0_RTX (V2SImode))
17107 rtx temp = force_reg (V2SImode, operands[1]);
17108 emit_move_insn (operands[0], temp);
17113 (define_expand "movv4hi"
17114 [(set (match_operand:V4HI 0 "general_operand" "")
17115 (match_operand:V4HI 1 "general_operand" ""))]
17119 /* For constants other than zero into memory. We do not know how the
17120 instructions used to build constants modify the upper 64 bits
17121 of the register, once we have that information we may be able
17122 to handle some of them more efficiently. */
17123 if ((reload_in_progress | reload_completed) == 0
17124 && register_operand (operands[0], V4HImode)
17125 && CONSTANT_P (operands[1]))
17127 rtx addr = gen_reg_rtx (Pmode);
17129 emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0));
17130 operands[1] = gen_rtx_MEM (V4HImode, addr);
17133 /* Make operand1 a register if it isn't already. */
17134 if ((reload_in_progress | reload_completed) == 0
17135 && !register_operand (operands[0], V4HImode)
17136 && !register_operand (operands[1], V4HImode)
17137 && operands[1] != CONST0_RTX (V4HImode))
17139 rtx temp = force_reg (V4HImode, operands[1]);
17140 emit_move_insn (operands[0], temp);
17145 (define_expand "movv8qi"
17146 [(set (match_operand:V8QI 0 "general_operand" "")
17147 (match_operand:V8QI 1 "general_operand" ""))]
17151 /* For constants other than zero into memory. We do not know how the
17152 instructions used to build constants modify the upper 64 bits
17153 of the register, once we have that information we may be able
17154 to handle some of them more efficiently. */
17155 if ((reload_in_progress | reload_completed) == 0
17156 && register_operand (operands[0], V8QImode)
17157 && CONSTANT_P (operands[1]))
17159 rtx addr = gen_reg_rtx (Pmode);
17161 emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0));
17162 operands[1] = gen_rtx_MEM (V8QImode, addr);
17165 /* Make operand1 a register if it isn't already. */
17166 if ((reload_in_progress | reload_completed) == 0
17167 && !register_operand (operands[0], V8QImode)
17168 && !register_operand (operands[1], V8QImode)
17169 && operands[1] != CONST0_RTX (V8QImode))
17171 rtx temp = force_reg (V8QImode, operands[1]);
17172 emit_move_insn (operands[0], temp);
17177 (define_insn_and_split "*pushti"
17178 [(set (match_operand:TI 0 "push_operand" "=<")
17179 (match_operand:TI 1 "nonmemory_operand" "x"))]
17183 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17184 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17186 [(set_attr "type" "sse")])
17188 (define_insn_and_split "*pushv4sf"
17189 [(set (match_operand:V4SF 0 "push_operand" "=<")
17190 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
17194 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17195 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
17197 [(set_attr "type" "sse")])
17199 (define_insn_and_split "*pushv4si"
17200 [(set (match_operand:V4SI 0 "push_operand" "=<")
17201 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
17205 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17206 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
17208 [(set_attr "type" "sse")])
17210 (define_insn_and_split "*pushv2si"
17211 [(set (match_operand:V2SI 0 "push_operand" "=<")
17212 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
17216 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17217 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
17219 [(set_attr "type" "mmx")])
17221 (define_insn_and_split "*pushv4hi"
17222 [(set (match_operand:V4HI 0 "push_operand" "=<")
17223 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
17227 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17228 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
17230 [(set_attr "type" "mmx")])
17232 (define_insn_and_split "*pushv8qi"
17233 [(set (match_operand:V8QI 0 "push_operand" "=<")
17234 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
17238 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17239 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
17241 [(set_attr "type" "mmx")])
17243 (define_insn "movti_internal"
17244 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
17245 (match_operand:TI 1 "general_operand" "xm,x"))]
17248 movaps\\t{%1, %0|%0, %1}
17249 movaps\\t{%1, %0|%0, %1}"
17250 [(set_attr "type" "sse")])
17252 ;; These two patterns are useful for specifying exactly whether to use
17253 ;; movaps or movups
17254 (define_insn "sse_movaps"
17255 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17256 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
17259 movaps\\t{%1, %0|%0, %1}
17260 movaps\\t{%1, %0|%0, %1}"
17261 [(set_attr "type" "sse")])
17263 (define_insn "sse_movups"
17264 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17265 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
17268 movups\\t{%1, %0|%0, %1}
17269 movups\\t{%1, %0|%0, %1}"
17270 [(set_attr "type" "sse")])
17273 ;; SSE Strange Moves.
17275 (define_insn "sse_movmskps"
17276 [(set (match_operand:SI 0 "register_operand" "=r")
17277 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
17279 "movmskps\\t{%1, %0|%0, %1}"
17280 [(set_attr "type" "sse")])
17282 (define_insn "mmx_pmovmskb"
17283 [(set (match_operand:SI 0 "register_operand" "=r")
17284 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
17286 "pmovmskb\\t{%1, %0|%0, %1}"
17287 [(set_attr "type" "sse")])
17289 (define_insn "mmx_maskmovq"
17290 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
17291 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
17292 (match_operand:V8QI 2 "register_operand" "y")] 32))]
17294 ;; @@@ check ordering of operands in intel/nonintel syntax
17295 "maskmovq\\t{%2, %1|%1, %2}"
17296 [(set_attr "type" "sse")])
17298 (define_insn "sse_movntv4sf"
17299 [(set (match_operand:V4SF 0 "memory_operand" "=m")
17300 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
17302 "movntps\\t{%1, %0|%0, %1}"
17303 [(set_attr "type" "sse")])
17305 (define_insn "sse_movntdi"
17306 [(set (match_operand:DI 0 "memory_operand" "=m")
17307 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
17309 "movntq\\t{%1, %0|%0, %1}"
17310 [(set_attr "type" "sse")])
17312 (define_insn "sse_movhlps"
17313 [(set (match_operand:V4SF 0 "register_operand" "=x")
17315 (match_operand:V4SF 1 "register_operand" "0")
17316 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17317 (parallel [(const_int 2)
17323 "movhlps\\t{%2, %0|%0, %2}"
17324 [(set_attr "type" "sse")])
17326 (define_insn "sse_movlhps"
17327 [(set (match_operand:V4SF 0 "register_operand" "=x")
17329 (match_operand:V4SF 1 "register_operand" "0")
17330 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
17331 (parallel [(const_int 2)
17337 "movlhps\\t{%2, %0|%0, %2}"
17338 [(set_attr "type" "sse")])
17340 (define_insn "sse_movhps"
17341 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17343 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17344 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17346 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17347 "movhps\\t{%2, %0|%0, %2}"
17348 [(set_attr "type" "sse")])
17350 (define_insn "sse_movlps"
17351 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17353 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
17354 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
17356 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
17357 "movlps\\t{%2, %0|%0, %2}"
17358 [(set_attr "type" "sse")])
17360 (define_insn "sse_loadss"
17361 [(set (match_operand:V4SF 0 "register_operand" "=x")
17363 (match_operand:V4SF 1 "memory_operand" "m")
17364 (vec_duplicate:V4SF (float:SF (const_int 0)))
17367 "movss\\t{%1, %0|%0, %1}"
17368 [(set_attr "type" "sse")])
17370 (define_insn "sse_movss"
17371 [(set (match_operand:V4SF 0 "register_operand" "=x")
17373 (match_operand:V4SF 1 "register_operand" "0")
17374 (match_operand:V4SF 2 "register_operand" "x")
17377 "movss\\t{%2, %0|%0, %2}"
17378 [(set_attr "type" "sse")])
17380 (define_insn "sse_storess"
17381 [(set (match_operand:SF 0 "memory_operand" "=m")
17383 (match_operand:V4SF 1 "register_operand" "x")
17384 (parallel [(const_int 0)])))]
17386 "movss\\t{%1, %0|%0, %1}"
17387 [(set_attr "type" "sse")])
17389 (define_insn "sse_shufps"
17390 [(set (match_operand:V4SF 0 "register_operand" "=x")
17391 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
17392 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
17393 (match_operand:SI 3 "immediate_operand" "i")] 41))]
17395 ;; @@@ check operand order for intel/nonintel syntax
17396 "shufps\\t{%3, %2, %0|%0, %2, %3}"
17397 [(set_attr "type" "sse")])
17402 (define_insn "addv4sf3"
17403 [(set (match_operand:V4SF 0 "register_operand" "=x")
17404 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17405 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17407 "addps\\t{%2, %0|%0, %2}"
17408 [(set_attr "type" "sse")])
17410 (define_insn "vmaddv4sf3"
17411 [(set (match_operand:V4SF 0 "register_operand" "=x")
17412 (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17413 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17417 "addss\\t{%2, %0|%0, %2}"
17418 [(set_attr "type" "sse")])
17420 (define_insn "subv4sf3"
17421 [(set (match_operand:V4SF 0 "register_operand" "=x")
17422 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17423 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17425 "subps\\t{%2, %0|%0, %2}"
17426 [(set_attr "type" "sse")])
17428 (define_insn "vmsubv4sf3"
17429 [(set (match_operand:V4SF 0 "register_operand" "=x")
17430 (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
17431 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17435 "subss\\t{%2, %0|%0, %2}"
17436 [(set_attr "type" "sse")])
17438 (define_insn "mulv4sf3"
17439 [(set (match_operand:V4SF 0 "register_operand" "=x")
17440 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
17441 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17443 "mulps\\t{%2, %0|%0, %2}"
17444 [(set_attr "type" "sse")])
17446 (define_insn "vmmulv4sf3"
17447 [(set (match_operand:V4SF 0 "register_operand" "=x")
17448 (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
17449 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17453 "mulss\\t{%2, %0|%0, %2}"
17454 [(set_attr "type" "sse")])
17456 (define_insn "divv4sf3"
17457 [(set (match_operand:V4SF 0 "register_operand" "=x")
17458 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
17459 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17461 "divps\\t{%2, %0|%0, %2}"
17462 [(set_attr "type" "sse")])
17464 (define_insn "vmdivv4sf3"
17465 [(set (match_operand:V4SF 0 "register_operand" "=x")
17466 (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
17467 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17471 "divss\\t{%2, %0|%0, %2}"
17472 [(set_attr "type" "sse")])
17475 ;; SSE square root/reciprocal
17477 (define_insn "rcpv4sf2"
17478 [(set (match_operand:V4SF 0 "register_operand" "=x")
17479 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
17481 "rcpps\\t{%1, %0|%0, %1}"
17482 [(set_attr "type" "sse")])
17484 (define_insn "vmrcpv4sf2"
17485 [(set (match_operand:V4SF 0 "register_operand" "=x")
17486 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42)
17487 (match_operand:V4SF 2 "register_operand" "0")
17490 "rcpss\\t{%1, %0|%0, %1}"
17491 [(set_attr "type" "sse")])
17493 (define_insn "rsqrtv4sf2"
17494 [(set (match_operand:V4SF 0 "register_operand" "=x")
17495 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
17497 "rsqrtps\\t{%1, %0|%0, %1}"
17498 [(set_attr "type" "sse")])
17500 (define_insn "vmrsqrtv4sf2"
17501 [(set (match_operand:V4SF 0 "register_operand" "=x")
17502 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43)
17503 (match_operand:V4SF 2 "register_operand" "0")
17506 "rsqrtss\\t{%1, %0|%0, %1}"
17507 [(set_attr "type" "sse")])
17509 (define_insn "sqrtv4sf2"
17510 [(set (match_operand:V4SF 0 "register_operand" "=x")
17511 (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
17513 "sqrtps\\t{%1, %0|%0, %1}"
17514 [(set_attr "type" "sse")])
17516 (define_insn "vmsqrtv4sf2"
17517 [(set (match_operand:V4SF 0 "register_operand" "=x")
17518 (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm"))
17519 (match_operand:V4SF 2 "register_operand" "0")
17522 "sqrtss\\t{%1, %0|%0, %1}"
17523 [(set_attr "type" "sse")])
17526 ;; SSE logical operations.
17528 ;; These are not called andti3 etc. because we really really don't want
17529 ;; the compiler to widen DImode ands to TImode ands and then try to move
17530 ;; into DImode subregs of SSE registers, and them together, and move out
17531 ;; of DImode subregs again!
17533 (define_insn "*sse_andti3_df_1"
17534 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
17535 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
17536 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
17538 "andpd\\t{%2, %0|%0, %2}"
17539 [(set_attr "type" "sse")])
17541 (define_insn "*sse_andti3_df_2"
17542 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
17543 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
17544 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
17546 "andpd\\t{%2, %0|%0, %2}"
17547 [(set_attr "type" "sse")])
17549 (define_insn "*sse_andti3_sf_1"
17550 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
17551 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
17552 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
17554 "andps\\t{%2, %0|%0, %2}"
17555 [(set_attr "type" "sse")])
17557 (define_insn "*sse_andti3_sf_2"
17558 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
17559 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
17560 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17562 "andps\\t{%2, %0|%0, %2}"
17563 [(set_attr "type" "sse")])
17565 (define_insn "sse_andti3"
17566 [(set (match_operand:TI 0 "register_operand" "=x")
17567 (and:TI (match_operand:TI 1 "register_operand" "%0")
17568 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17569 "TARGET_SSE && !TARGET_SSE2"
17570 "andps\\t{%2, %0|%0, %2}"
17571 [(set_attr "type" "sse")])
17573 (define_insn "*sse_andti3_sse2"
17574 [(set (match_operand:TI 0 "register_operand" "=x")
17575 (and:TI (match_operand:TI 1 "register_operand" "%0")
17576 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17578 "pand\\t{%2, %0|%0, %2}"
17579 [(set_attr "type" "sse")])
17581 (define_insn "*sse_nandti3_df"
17582 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
17583 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
17584 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
17586 "andnpd\\t{%2, %0|%0, %2}"
17587 [(set_attr "type" "sse")])
17589 (define_insn "*sse_nandti3_sf"
17590 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
17591 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
17592 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17594 "andnps\\t{%2, %0|%0, %2}"
17595 [(set_attr "type" "sse")])
17597 (define_insn "sse_nandti3"
17598 [(set (match_operand:TI 0 "register_operand" "=x")
17599 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
17600 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17601 "TARGET_SSE && !TARGET_SSE2"
17602 "andnps\\t{%2, %0|%0, %2}"
17603 [(set_attr "type" "sse")])
17605 (define_insn "*sse_nandti3_sse2"
17606 [(set (match_operand:TI 0 "register_operand" "=x")
17607 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
17608 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17610 "pnand\\t{%2, %0|%0, %2}"
17611 [(set_attr "type" "sse")])
17613 (define_insn "*sse_iorti3_df_1"
17614 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
17615 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
17616 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
17618 "orpd\\t{%2, %0|%0, %2}"
17619 [(set_attr "type" "sse")])
17621 (define_insn "*sse_iorti3_df_2"
17622 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
17623 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
17624 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
17626 "orpd\\t{%2, %0|%0, %2}"
17627 [(set_attr "type" "sse")])
17629 (define_insn "*sse_iorti3_sf_1"
17630 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
17631 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
17632 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
17634 "orps\\t{%2, %0|%0, %2}"
17635 [(set_attr "type" "sse")])
17637 (define_insn "*sse_iorti3_sf_2"
17638 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
17639 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
17640 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17642 "orps\\t{%2, %0|%0, %2}"
17643 [(set_attr "type" "sse")])
17645 (define_insn "sse_iorti3"
17646 [(set (match_operand:TI 0 "register_operand" "=x")
17647 (ior:TI (match_operand:TI 1 "register_operand" "%0")
17648 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17649 "TARGET_SSE && !TARGET_SSE2"
17650 "orps\\t{%2, %0|%0, %2}"
17651 [(set_attr "type" "sse")])
17653 (define_insn "*sse_iorti3_sse2"
17654 [(set (match_operand:TI 0 "register_operand" "=x")
17655 (ior:TI (match_operand:TI 1 "register_operand" "%0")
17656 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17658 "por\\t{%2, %0|%0, %2}"
17659 [(set_attr "type" "sse")])
17661 (define_insn "*sse_xorti3_df_1"
17662 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
17663 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
17664 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
17666 "xorpd\\t{%2, %0|%0, %2}"
17667 [(set_attr "type" "sse")])
17669 (define_insn "*sse_xorti3_df_2"
17670 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
17671 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
17672 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
17674 "xorpd\\t{%2, %0|%0, %2}"
17675 [(set_attr "type" "sse")])
17677 (define_insn "*sse_xorti3_sf_1"
17678 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
17679 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
17680 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
17682 "xorps\\t{%2, %0|%0, %2}"
17683 [(set_attr "type" "sse")])
17685 (define_insn "*sse_xorti3_sf_2"
17686 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
17687 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
17688 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17690 "xorps\\t{%2, %0|%0, %2}"
17691 [(set_attr "type" "sse")])
17693 (define_insn "sse_xorti3"
17694 [(set (match_operand:TI 0 "register_operand" "=x")
17695 (xor:TI (match_operand:TI 1 "register_operand" "%0")
17696 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17697 "TARGET_SSE && !TARGET_SSE2"
17698 "xorps\\t{%2, %0|%0, %2}"
17699 [(set_attr "type" "sse")])
17701 (define_insn "*sse_xorti3_sse2"
17702 [(set (match_operand:TI 0 "register_operand" "=x")
17703 (xor:TI (match_operand:TI 1 "register_operand" "%0")
17704 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
17706 "pxor\\t{%2, %0|%0, %2}"
17707 [(set_attr "type" "sse")])
17709 ;; Use xor, but don't show input operands so they aren't live before
17711 (define_insn "sse_clrti"
17712 [(set (match_operand:TI 0 "register_operand" "=x")
17713 (unspec:TI [(const_int 0)] 45))]
17715 "xorps\\t{%0, %0|%0, %0}"
17716 [(set_attr "type" "sse")])
17719 ;; SSE mask-generating compares
17721 (define_insn "maskcmpv4sf3"
17722 [(set (match_operand:V4SI 0 "register_operand" "=x")
17723 (match_operator:V4SI 3 "sse_comparison_operator"
17724 [(match_operand:V4SF 1 "register_operand" "0")
17725 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
17727 "cmp%D3ps\\t{%2, %0|%0, %2}"
17728 [(set_attr "type" "sse")])
17730 (define_insn "maskncmpv4sf3"
17731 [(set (match_operand:V4SI 0 "register_operand" "=x")
17733 (match_operator:V4SI 3 "sse_comparison_operator"
17734 [(match_operand:V4SF 1 "register_operand" "0")
17735 (match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
17737 "cmpn%D3ps\\t{%2, %0|%0, %2}"
17738 [(set_attr "type" "sse")])
17740 (define_insn "vmmaskcmpv4sf3"
17741 [(set (match_operand:V4SI 0 "register_operand" "=x")
17743 (match_operator:V4SI 3 "sse_comparison_operator"
17744 [(match_operand:V4SF 1 "register_operand" "0")
17745 (match_operand:V4SF 2 "nonimmediate_operand" "x")])
17749 "cmp%D3ss\\t{%2, %0|%0, %2}"
17750 [(set_attr "type" "sse")])
17752 (define_insn "vmmaskncmpv4sf3"
17753 [(set (match_operand:V4SI 0 "register_operand" "=x")
17756 (match_operator:V4SI 3 "sse_comparison_operator"
17757 [(match_operand:V4SF 1 "register_operand" "0")
17758 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))
17759 (subreg:V4SI (match_dup 1) 0)
17762 "cmp%D3ss\\t{%2, %0|%0, %2}"
17763 [(set_attr "type" "sse")])
17765 (define_insn "sse_comi"
17766 [(set (reg:CCFP 17)
17767 (match_operator:CCFP 2 "sse_comparison_operator"
17769 (match_operand:V4SF 0 "register_operand" "x")
17770 (parallel [(const_int 0)]))
17772 (match_operand:V4SF 1 "register_operand" "x")
17773 (parallel [(const_int 0)]))]))]
17775 "comiss\\t{%2, %0|%0, %2}"
17776 [(set_attr "type" "sse")])
17778 (define_insn "sse_ucomi"
17779 [(set (reg:CCFPU 17)
17780 (match_operator:CCFPU 2 "sse_comparison_operator"
17782 (match_operand:V4SF 0 "register_operand" "x")
17783 (parallel [(const_int 0)]))
17785 (match_operand:V4SF 1 "register_operand" "x")
17786 (parallel [(const_int 0)]))]))]
17788 "ucomiss\\t{%2, %0|%0, %2}"
17789 [(set_attr "type" "sse")])
17794 (define_insn "sse_unpckhps"
17795 [(set (match_operand:V4SF 0 "register_operand" "=x")
17797 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
17798 (parallel [(const_int 2)
17802 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
17803 (parallel [(const_int 0)
17809 "unpckhps\\t{%2, %0|%0, %2}"
17810 [(set_attr "type" "sse")])
17812 (define_insn "sse_unpcklps"
17813 [(set (match_operand:V4SF 0 "register_operand" "=x")
17815 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
17816 (parallel [(const_int 0)
17820 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
17821 (parallel [(const_int 2)
17827 "unpcklps\\t{%2, %0|%0, %2}"
17828 [(set_attr "type" "sse")])
17833 (define_insn "smaxv4sf3"
17834 [(set (match_operand:V4SF 0 "register_operand" "=x")
17835 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
17836 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17838 "maxps\\t{%2, %0|%0, %2}"
17839 [(set_attr "type" "sse")])
17841 (define_insn "vmsmaxv4sf3"
17842 [(set (match_operand:V4SF 0 "register_operand" "=x")
17843 (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
17844 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17848 "maxss\\t{%2, %0|%0, %2}"
17849 [(set_attr "type" "sse")])
17851 (define_insn "sminv4sf3"
17852 [(set (match_operand:V4SF 0 "register_operand" "=x")
17853 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
17854 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
17856 "minps\\t{%2, %0|%0, %2}"
17857 [(set_attr "type" "sse")])
17859 (define_insn "vmsminv4sf3"
17860 [(set (match_operand:V4SF 0 "register_operand" "=x")
17861 (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
17862 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
17866 "minss\\t{%2, %0|%0, %2}"
17867 [(set_attr "type" "sse")])
17870 ;; SSE <-> integer/MMX conversions
17872 (define_insn "cvtpi2ps"
17873 [(set (match_operand:V4SF 0 "register_operand" "=x")
17874 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
17875 (vec_duplicate:V4SF
17876 (float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
17879 "cvtpi2ps\\t{%2, %0|%0, %2}"
17880 [(set_attr "type" "sse")])
17882 (define_insn "cvtps2pi"
17883 [(set (match_operand:V2SI 0 "register_operand" "=y")
17884 (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
17889 "cvtps2pi\\t{%1, %0|%0, %1}"
17890 [(set_attr "type" "sse")])
17892 (define_insn "cvttps2pi"
17893 [(set (match_operand:V2SI 0 "register_operand" "=y")
17894 (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
17899 "cvttps2pi\\t{%1, %0|%0, %1}"
17900 [(set_attr "type" "sse")])
17902 (define_insn "cvtsi2ss"
17903 [(set (match_operand:V4SF 0 "register_operand" "=x")
17904 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
17905 (vec_duplicate:V4SF
17906 (float:SF (match_operand:SI 2 "register_operand" "rm")))
17909 "cvtsi2ss\\t{%2, %0|%0, %2}"
17910 [(set_attr "type" "sse")])
17912 (define_insn "cvtss2si"
17913 [(set (match_operand:SI 0 "register_operand" "=y")
17914 (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
17915 (parallel [(const_int 0)])))]
17917 "cvtss2si\\t{%1, %0|%0, %1}"
17918 [(set_attr "type" "sse")])
17920 (define_insn "cvttss2si"
17921 [(set (match_operand:SI 0 "register_operand" "=y")
17922 (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
17923 (parallel [(const_int 0)])))]
17925 "cvttss2si\\t{%1, %0|%0, %1}"
17926 [(set_attr "type" "sse")])
17933 (define_insn "addv8qi3"
17934 [(set (match_operand:V8QI 0 "register_operand" "=y")
17935 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
17936 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
17938 "paddb\\t{%2, %0|%0, %2}"
17939 [(set_attr "type" "mmx")])
17941 (define_insn "addv4hi3"
17942 [(set (match_operand:V4HI 0 "register_operand" "=y")
17943 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
17944 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
17946 "paddw\\t{%2, %0|%0, %2}"
17947 [(set_attr "type" "mmx")])
17949 (define_insn "addv2si3"
17950 [(set (match_operand:V2SI 0 "register_operand" "=y")
17951 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
17952 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
17954 "paddd\\t{%2, %0|%0, %2}"
17955 [(set_attr "type" "mmx")])
17957 (define_insn "ssaddv8qi3"
17958 [(set (match_operand:V8QI 0 "register_operand" "=y")
17959 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
17960 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
17962 "paddsb\\t{%2, %0|%0, %2}"
17963 [(set_attr "type" "mmx")])
17965 (define_insn "ssaddv4hi3"
17966 [(set (match_operand:V4HI 0 "register_operand" "=y")
17967 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
17968 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
17970 "paddsw\\t{%2, %0|%0, %2}"
17971 [(set_attr "type" "mmx")])
17973 (define_insn "usaddv8qi3"
17974 [(set (match_operand:V8QI 0 "register_operand" "=y")
17975 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
17976 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
17978 "paddusb\\t{%2, %0|%0, %2}"
17979 [(set_attr "type" "mmx")])
17981 (define_insn "usaddv4hi3"
17982 [(set (match_operand:V4HI 0 "register_operand" "=y")
17983 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
17984 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
17986 "paddusw\\t{%2, %0|%0, %2}"
17987 [(set_attr "type" "mmx")])
17989 (define_insn "subv8qi3"
17990 [(set (match_operand:V8QI 0 "register_operand" "=y")
17991 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
17992 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
17994 "psubb\\t{%2, %0|%0, %2}"
17995 [(set_attr "type" "mmx")])
17997 (define_insn "subv4hi3"
17998 [(set (match_operand:V4HI 0 "register_operand" "=y")
17999 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18000 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18002 "psubw\\t{%2, %0|%0, %2}"
18003 [(set_attr "type" "mmx")])
18005 (define_insn "subv2si3"
18006 [(set (match_operand:V2SI 0 "register_operand" "=y")
18007 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18008 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18010 "psubd\\t{%2, %0|%0, %2}"
18011 [(set_attr "type" "mmx")])
18013 (define_insn "sssubv8qi3"
18014 [(set (match_operand:V8QI 0 "register_operand" "=y")
18015 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18016 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18018 "psubsb\\t{%2, %0|%0, %2}"
18019 [(set_attr "type" "mmx")])
18021 (define_insn "sssubv4hi3"
18022 [(set (match_operand:V4HI 0 "register_operand" "=y")
18023 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18024 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18026 "psubsw\\t{%2, %0|%0, %2}"
18027 [(set_attr "type" "mmx")])
18029 (define_insn "ussubv8qi3"
18030 [(set (match_operand:V8QI 0 "register_operand" "=y")
18031 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18032 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18034 "psubusb\\t{%2, %0|%0, %2}"
18035 [(set_attr "type" "mmx")])
18037 (define_insn "ussubv4hi3"
18038 [(set (match_operand:V4HI 0 "register_operand" "=y")
18039 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18040 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18042 "psubusw\\t{%2, %0|%0, %2}"
18043 [(set_attr "type" "mmx")])
18045 (define_insn "mulv4hi3"
18046 [(set (match_operand:V4HI 0 "register_operand" "=y")
18047 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
18048 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18050 "pmullw\\t{%2, %0|%0, %2}"
18051 [(set_attr "type" "mmx")])
18053 (define_insn "smulv4hi3_highpart"
18054 [(set (match_operand:V4HI 0 "register_operand" "=y")
18057 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18058 (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18061 "pmulhw\\t{%2, %0|%0, %2}"
18062 [(set_attr "type" "mmx")])
18064 (define_insn "umulv4hi3_highpart"
18065 [(set (match_operand:V4HI 0 "register_operand" "=y")
18068 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
18069 (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
18072 "pmulhuw\\t{%2, %0|%0, %2}"
18073 [(set_attr "type" "mmx")])
18075 (define_insn "mmx_pmaddwd"
18076 [(set (match_operand:V2SI 0 "register_operand" "=y")
18079 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
18080 (parallel [(const_int 0)
18082 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18083 (parallel [(const_int 0)
18086 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
18087 (parallel [(const_int 1)
18089 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
18090 (parallel [(const_int 1)
18091 (const_int 3)]))))))]
18093 "pmaddwd\\t{%2, %0|%0, %2}"
18094 [(set_attr "type" "mmx")])
18097 ;; MMX logical operations
18098 ;; Note we don't want to declare these as regular iordi3 insns to prevent
18099 ;; normal code that also wants to use the FPU from getting broken.
18100 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
18101 (define_insn "mmx_iordi3"
18102 [(set (match_operand:DI 0 "register_operand" "=y")
18104 [(ior:DI (match_operand:DI 1 "register_operand" "0")
18105 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18107 "por\\t{%2, %0|%0, %2}"
18108 [(set_attr "type" "mmx")])
18110 (define_insn "mmx_xordi3"
18111 [(set (match_operand:DI 0 "register_operand" "=y")
18113 [(xor:DI (match_operand:DI 1 "register_operand" "0")
18114 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18116 "pxor\\t{%2, %0|%0, %2}"
18117 [(set_attr "type" "mmx")])
18119 ;; Same as pxor, but don't show input operands so that we don't think
18121 (define_insn "mmx_clrdi"
18122 [(set (match_operand:DI 0 "register_operand" "=y")
18123 (unspec:DI [(const_int 0)] 45))]
18125 "pxor\\t{%0, %0|%0, %0}"
18126 [(set_attr "type" "mmx")])
18128 (define_insn "mmx_anddi3"
18129 [(set (match_operand:DI 0 "register_operand" "=y")
18131 [(and:DI (match_operand:DI 1 "register_operand" "0")
18132 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18134 "pand\\t{%2, %0|%0, %2}"
18135 [(set_attr "type" "mmx")])
18137 (define_insn "mmx_nanddi3"
18138 [(set (match_operand:DI 0 "register_operand" "=y")
18140 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
18141 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
18143 "pandn\\t{%2, %0|%0, %2}"
18144 [(set_attr "type" "mmx")])
18147 ;; MMX unsigned averages/sum of absolute differences
18149 (define_insn "mmx_uavgv8qi3"
18150 [(set (match_operand:V8QI 0 "register_operand" "=y")
18152 (plus:V8QI (plus:V8QI
18153 (match_operand:V8QI 1 "register_operand" "0")
18154 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
18155 (vec_const:V8QI (parallel [(const_int 1)
18165 "pavgb\\t{%2, %0|%0, %2}"
18166 [(set_attr "type" "sse")])
18168 (define_insn "mmx_uavgv4hi3"
18169 [(set (match_operand:V4HI 0 "register_operand" "=y")
18171 (plus:V4HI (plus:V4HI
18172 (match_operand:V4HI 1 "register_operand" "0")
18173 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
18174 (vec_const:V4HI (parallel [(const_int 1)
18180 "pavgw\\t{%2, %0|%0, %2}"
18181 [(set_attr "type" "sse")])
18183 (define_insn "mmx_psadbw"
18184 [(set (match_operand:V8QI 0 "register_operand" "=y")
18185 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18186 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
18188 "psadbw\\t{%2, %0|%0, %2}"
18189 [(set_attr "type" "sse")])
18192 ;; MMX insert/extract/shuffle
18194 (define_insn "mmx_pinsrw"
18195 [(set (match_operand:V4HI 0 "register_operand" "=y")
18196 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
18197 (vec_duplicate:V4HI
18198 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
18199 (match_operand:SI 3 "immediate_operand" "i")))]
18201 "pinsrw\\t{%3, %2, %0|%0, %2, %3}"
18202 [(set_attr "type" "sse")])
18204 (define_insn "mmx_pextrw"
18205 [(set (match_operand:SI 0 "register_operand" "=r")
18206 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
18208 [(match_operand:SI 2 "immediate_operand" "i")]))))]
18210 "pextrw\\t{%2, %1, %0|%0, %1, %2}"
18211 [(set_attr "type" "sse")])
18213 (define_insn "mmx_pshufw"
18214 [(set (match_operand:V4HI 0 "register_operand" "=y")
18215 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
18216 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
18217 (match_operand:SI 3 "immediate_operand" "i")] 41))]
18219 "pshufw\\t{%3, %2, %0|%0, %2, %3}"
18220 [(set_attr "type" "sse")])
18223 ;; MMX mask-generating comparisons
18225 (define_insn "eqv8qi3"
18226 [(set (match_operand:V8QI 0 "register_operand" "=y")
18227 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
18228 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18230 "pcmpeqb\\t{%2, %0|%0, %2}"
18231 [(set_attr "type" "mmx")])
18233 (define_insn "eqv4hi3"
18234 [(set (match_operand:V4HI 0 "register_operand" "=y")
18235 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
18236 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18238 "pcmpeqw\\t{%2, %0|%0, %2}"
18239 [(set_attr "type" "mmx")])
18241 (define_insn "eqv2si3"
18242 [(set (match_operand:V2SI 0 "register_operand" "=y")
18243 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
18244 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18246 "pcmpeqd\\t{%2, %0|%0, %2}"
18247 [(set_attr "type" "mmx")])
18249 (define_insn "gtv8qi3"
18250 [(set (match_operand:V8QI 0 "register_operand" "=y")
18251 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
18252 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18254 "pcmpgtb\\t{%2, %0|%0, %2}"
18255 [(set_attr "type" "mmx")])
18257 (define_insn "gtv4hi3"
18258 [(set (match_operand:V4HI 0 "register_operand" "=y")
18259 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18260 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18262 "pcmpgtw\\t{%2, %0|%0, %2}"
18263 [(set_attr "type" "mmx")])
18265 (define_insn "gtv2si3"
18266 [(set (match_operand:V2SI 0 "register_operand" "=y")
18267 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18268 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18270 "pcmpgtd\\t{%2, %0|%0, %2}"
18271 [(set_attr "type" "mmx")])
18274 ;; MMX max/min insns
18276 (define_insn "umaxv8qi3"
18277 [(set (match_operand:V8QI 0 "register_operand" "=y")
18278 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
18279 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18281 "pmaxub\\t{%2, %0|%0, %2}"
18282 [(set_attr "type" "sse")])
18284 (define_insn "smaxv4hi3"
18285 [(set (match_operand:V4HI 0 "register_operand" "=y")
18286 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
18287 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18289 "pmaxsw\\t{%2, %0|%0, %2}"
18290 [(set_attr "type" "sse")])
18292 (define_insn "uminv8qi3"
18293 [(set (match_operand:V8QI 0 "register_operand" "=y")
18294 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
18295 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18297 "pminub\\t{%2, %0|%0, %2}"
18298 [(set_attr "type" "sse")])
18300 (define_insn "sminv4hi3"
18301 [(set (match_operand:V4HI 0 "register_operand" "=y")
18302 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
18303 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18305 "pminsw\\t{%2, %0|%0, %2}"
18306 [(set_attr "type" "sse")])
18311 (define_insn "ashrv4hi3"
18312 [(set (match_operand:V4HI 0 "register_operand" "=y")
18313 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18314 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18316 "psraw\\t{%2, %0|%0, %2}"
18317 [(set_attr "type" "mmx")])
18319 (define_insn "ashrv2si3"
18320 [(set (match_operand:V2SI 0 "register_operand" "=y")
18321 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18322 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18324 "psrad\\t{%2, %0|%0, %2}"
18325 [(set_attr "type" "mmx")])
18327 (define_insn "lshrv4hi3"
18328 [(set (match_operand:V4HI 0 "register_operand" "=y")
18329 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
18330 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18332 "psrlw\\t{%2, %0|%0, %2}"
18333 [(set_attr "type" "mmx")])
18335 (define_insn "lshrv2si3"
18336 [(set (match_operand:V2SI 0 "register_operand" "=y")
18337 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
18338 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18340 "psrld\\t{%2, %0|%0, %2}"
18341 [(set_attr "type" "mmx")])
18343 ;; See logical MMX insns.
18344 (define_insn "mmx_lshrdi3"
18345 [(set (match_operand:DI 0 "register_operand" "=y")
18347 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
18348 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18350 "psrlq\\t{%2, %0|%0, %2}"
18351 [(set_attr "type" "mmx")])
18353 (define_insn "ashlv4hi3"
18354 [(set (match_operand:V4HI 0 "register_operand" "=y")
18355 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
18356 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18358 "psllw\\t{%2, %0|%0, %2}"
18359 [(set_attr "type" "mmx")])
18361 (define_insn "ashlv2si3"
18362 [(set (match_operand:V2SI 0 "register_operand" "=y")
18363 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
18364 (match_operand:DI 2 "nonmemory_operand" "yi")))]
18366 "pslld\\t{%2, %0|%0, %2}"
18367 [(set_attr "type" "mmx")])
18369 ;; See logical MMX insns.
18370 (define_insn "mmx_ashldi3"
18371 [(set (match_operand:DI 0 "register_operand" "=y")
18373 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
18374 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
18376 "psllq\\t{%2, %0|%0, %2}"
18377 [(set_attr "type" "mmx")])
18380 ;; MMX pack/unpack insns.
18382 (define_insn "mmx_packsswb"
18383 [(set (match_operand:V8QI 0 "register_operand" "=y")
18385 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
18386 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
18388 "packsswb\\t{%2, %0|%0, %2}"
18389 [(set_attr "type" "mmx")])
18391 (define_insn "mmx_packssdw"
18392 [(set (match_operand:V4HI 0 "register_operand" "=y")
18394 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
18395 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
18397 "packssdw\\t{%2, %0|%0, %2}"
18398 [(set_attr "type" "mmx")])
18400 (define_insn "mmx_packuswb"
18401 [(set (match_operand:V8QI 0 "register_operand" "=y")
18403 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
18404 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
18406 "packuswb\\t{%2, %0|%0, %2}"
18407 [(set_attr "type" "mmx")])
18409 (define_insn "mmx_punpckhbw"
18410 [(set (match_operand:V8QI 0 "register_operand" "=y")
18412 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
18413 (parallel [(const_int 4)
18421 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
18422 (parallel [(const_int 0)
18432 "punpckhbw\\t{%2, %0|%0, %2}"
18433 [(set_attr "type" "mmx")])
18435 (define_insn "mmx_punpckhwd"
18436 [(set (match_operand:V4HI 0 "register_operand" "=y")
18438 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
18439 (parallel [(const_int 0)
18443 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
18444 (parallel [(const_int 2)
18450 "punpckhwd\\t{%2, %0|%0, %2}"
18451 [(set_attr "type" "mmx")])
18453 (define_insn "mmx_punpckhdq"
18454 [(set (match_operand:V2SI 0 "register_operand" "=y")
18456 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
18457 (parallel [(const_int 0)
18459 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
18460 (parallel [(const_int 1)
18464 "punpckhdq\\t{%2, %0|%0, %2}"
18465 [(set_attr "type" "mmx")])
18467 (define_insn "mmx_punpcklbw"
18468 [(set (match_operand:V8QI 0 "register_operand" "=y")
18470 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
18471 (parallel [(const_int 0)
18479 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
18480 (parallel [(const_int 4)
18490 "punpcklbw\\t{%2, %0|%0, %2}"
18491 [(set_attr "type" "mmx")])
18493 (define_insn "mmx_punpcklwd"
18494 [(set (match_operand:V4HI 0 "register_operand" "=y")
18496 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
18497 (parallel [(const_int 2)
18501 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
18502 (parallel [(const_int 0)
18508 "punpcklwd\\t{%2, %0|%0, %2}"
18509 [(set_attr "type" "mmx")])
18511 (define_insn "mmx_punpckldq"
18512 [(set (match_operand:V2SI 0 "register_operand" "=y")
18514 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
18515 (parallel [(const_int 1)
18517 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
18518 (parallel [(const_int 0)
18522 "punpckldq\\t{%2, %0|%0, %2}"
18523 [(set_attr "type" "mmx")])
18526 ;; Miscellaneous stuff
18528 (define_insn "emms"
18529 [(unspec_volatile [(const_int 0)] 31)
18530 (clobber (reg:XF 8))
18531 (clobber (reg:XF 9))
18532 (clobber (reg:XF 10))
18533 (clobber (reg:XF 11))
18534 (clobber (reg:XF 12))
18535 (clobber (reg:XF 13))
18536 (clobber (reg:XF 14))
18537 (clobber (reg:XF 15))
18538 (clobber (reg:DI 29))
18539 (clobber (reg:DI 30))
18540 (clobber (reg:DI 31))
18541 (clobber (reg:DI 32))
18542 (clobber (reg:DI 33))
18543 (clobber (reg:DI 34))
18544 (clobber (reg:DI 35))
18545 (clobber (reg:DI 36))]
18548 [(set_attr "type" "mmx")
18549 (set_attr "memory" "unknown")])
18551 (define_insn "ldmxcsr"
18552 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
18555 [(set_attr "type" "mmx")])
18557 (define_insn "stmxcsr"
18558 [(set (match_operand:SI 0 "memory_operand" "=m")
18559 (unspec_volatile:SI [(const_int 0)] 40))]
18562 [(set_attr "type" "mmx")])
18564 (define_expand "sfence"
18565 [(set (match_dup 0)
18566 (unspec:BLK [(match_dup 0)] 44))]
18570 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
18571 MEM_VOLATILE_P (operands[0]) = 1;
18574 (define_insn "*sfence_insn"
18575 [(set (match_operand:BLK 0 "" "")
18576 (unspec:BLK [(match_dup 0)] 44))]
18579 [(set_attr "type" "sse")
18580 (set_attr "memory" "unknown")])
18582 (define_insn "prefetch"
18583 [(unspec [(match_operand:SI 0 "address_operand" "p")
18584 (match_operand:SI 1 "immediate_operand" "n")] 35)]
18588 switch (INTVAL (operands[1]))
18591 return \"prefetchnta\\t%a0\";
18593 return \"prefetcht0\\t%a0\";
18595 return \"prefetcht1\\t%a0\";
18597 return \"prefetcht2\\t%a0\";
18602 [(set_attr "type" "sse")])