1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
5 ;; x86_64 support added by Jan Hubicka
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
30 ;; updates for most instructions.
32 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
33 ;; constraint letters.
35 ;; The special asm out single letter directives following a '%' are:
36 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
38 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
39 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
40 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
41 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
42 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
43 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
44 ;; 'J' Print the appropriate jump operand.
46 ;; 'b' Print the QImode name of the register for the indicated operand.
47 ;; %b0 would print %al if operands[0] is reg 0.
48 ;; 'w' Likewise, print the HImode name of the register.
49 ;; 'k' Likewise, print the SImode name of the register.
50 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
51 ;; 'y' Print "st(0)" instead of "st" as a register.
56 [; Relocation specifiers
68 (UNSPEC_STACK_PROBE 10)
69 (UNSPEC_STACK_ALLOC 11)
71 (UNSPEC_SSE_PROLOGUE_SAVE 13)
76 (UNSPEC_TLS_LD_BASE 17)
78 ; Other random patterns
89 ; For SSE/MMX support:
100 (UNSPEC_NOP 45) ; prevents combiner cleverness
115 [(UNSPECV_BLOCKAGE 0)
116 (UNSPECV_EH_RETURN 13)
124 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
127 ;; In C guard expressions, put expressions which may be compile-time
128 ;; constants first. This allows for better optimization. For
129 ;; example, write "TARGET_64BIT && reload_completed", not
130 ;; "reload_completed && TARGET_64BIT".
133 ;; Processor type. This attribute must exactly match the processor_type
134 ;; enumeration in i386.h.
135 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
136 (const (symbol_ref "ix86_cpu")))
138 ;; A basic instruction type. Refinements due to arguments to be
139 ;; provided in other attributes.
142 alu,alu1,negnot,imov,imovx,lea,
143 incdec,ishift,rotate,imul,idiv,
144 icmp,test,ibr,setcc,icmov,
147 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
148 sselog,sseiadd,sseishft,sseimul,
149 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv,
150 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
151 (const_string "other"))
153 ;; Main data type used by the insn
155 "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI,V4SF,V2DF,V2SF"
156 (const_string "unknown"))
158 ;; The CPU unit operations uses.
159 (define_attr "unit" "integer,i387,sse,mmx,unknown"
160 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
161 (const_string "i387")
162 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
163 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv")
165 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
166 (const_string "mmx")]
167 (const_string "integer")))
169 ;; The (bounding maximum) length of an instruction immediate.
170 (define_attr "length_immediate" ""
171 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv")
173 (eq_attr "unit" "i387,sse,mmx")
175 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,imul,
177 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
178 (eq_attr "type" "imov,test")
179 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
180 (eq_attr "type" "call")
181 (if_then_else (match_operand 0 "constant_call_address_operand" "")
184 (eq_attr "type" "callv")
185 (if_then_else (match_operand 1 "constant_call_address_operand" "")
188 (eq_attr "type" "ibr")
189 (if_then_else (and (ge (minus (match_dup 0) (pc))
191 (lt (minus (match_dup 0) (pc))
196 (symbol_ref "/* Update immediate_length and other attributes! */
199 ;; The (bounding maximum) length of an instruction address.
200 (define_attr "length_address" ""
201 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
203 (and (eq_attr "type" "call")
204 (match_operand 0 "constant_call_address_operand" ""))
206 (and (eq_attr "type" "callv")
207 (match_operand 1 "constant_call_address_operand" ""))
210 (symbol_ref "ix86_attr_length_address_default (insn)")))
212 ;; Set when length prefix is used.
213 (define_attr "prefix_data16" ""
214 (if_then_else (ior (eq_attr "mode" "HI")
215 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
219 ;; Set when string REP prefix is used.
220 (define_attr "prefix_rep" ""
221 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
225 ;; Set when 0f opcode prefix is used.
226 (define_attr "prefix_0f" ""
230 sselog,sseiadd,sseishft,sseimul,
231 sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv,
232 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
236 ;; Set when modrm byte is used.
237 (define_attr "modrm" ""
238 (cond [(eq_attr "type" "str,cld")
240 (eq_attr "unit" "i387")
242 (and (eq_attr "type" "incdec")
243 (ior (match_operand:SI 1 "register_operand" "")
244 (match_operand:HI 1 "register_operand" "")))
246 (and (eq_attr "type" "push")
247 (not (match_operand 1 "memory_operand" "")))
249 (and (eq_attr "type" "pop")
250 (not (match_operand 0 "memory_operand" "")))
252 (and (eq_attr "type" "imov")
253 (and (match_operand 0 "register_operand" "")
254 (match_operand 1 "immediate_operand" "")))
256 (and (eq_attr "type" "call")
257 (match_operand 0 "constant_call_address_operand" ""))
259 (and (eq_attr "type" "callv")
260 (match_operand 1 "constant_call_address_operand" ""))
265 ;; The (bounding maximum) length of an instruction in bytes.
266 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
267 ;; to split it and compute proper length as for other insns.
268 (define_attr "length" ""
269 (cond [(eq_attr "type" "other,multi,fistp")
271 (eq_attr "unit" "i387")
273 (plus (attr "prefix_data16")
274 (attr "length_address")))]
275 (plus (plus (attr "modrm")
276 (plus (attr "prefix_0f")
278 (plus (attr "prefix_rep")
279 (plus (attr "prefix_data16")
280 (plus (attr "length_immediate")
281 (attr "length_address")))))))
283 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
284 ;; `store' if there is a simple memory reference therein, or `unknown'
285 ;; if the instruction is complex.
287 (define_attr "memory" "none,load,store,both,unknown"
288 (cond [(eq_attr "type" "other,multi,str")
289 (const_string "unknown")
290 (eq_attr "type" "lea,fcmov,fpspc,cld")
291 (const_string "none")
292 (eq_attr "type" "fistp")
293 (const_string "both")
294 (eq_attr "type" "push")
295 (if_then_else (match_operand 1 "memory_operand" "")
296 (const_string "both")
297 (const_string "store"))
298 (eq_attr "type" "pop,setcc")
299 (if_then_else (match_operand 0 "memory_operand" "")
300 (const_string "both")
301 (const_string "load"))
302 (eq_attr "type" "icmp,test,ssecmp,mmxcmp,fcmp")
303 (if_then_else (ior (match_operand 0 "memory_operand" "")
304 (match_operand 1 "memory_operand" ""))
305 (const_string "load")
306 (const_string "none"))
307 (eq_attr "type" "ibr")
308 (if_then_else (match_operand 0 "memory_operand" "")
309 (const_string "load")
310 (const_string "none"))
311 (eq_attr "type" "call")
312 (if_then_else (match_operand 0 "constant_call_address_operand" "")
313 (const_string "none")
314 (const_string "load"))
315 (eq_attr "type" "callv")
316 (if_then_else (match_operand 1 "constant_call_address_operand" "")
317 (const_string "none")
318 (const_string "load"))
319 (and (eq_attr "type" "alu1,negnot")
320 (match_operand 1 "memory_operand" ""))
321 (const_string "both")
322 (and (match_operand 0 "memory_operand" "")
323 (match_operand 1 "memory_operand" ""))
324 (const_string "both")
325 (match_operand 0 "memory_operand" "")
326 (const_string "store")
327 (match_operand 1 "memory_operand" "")
328 (const_string "load")
331 imov,imovx,icmp,test,
333 sse,ssemov,ssecmp,ssecvt,
334 mmx,mmxmov,mmxcmp,mmxcvt")
335 (match_operand 2 "memory_operand" ""))
336 (const_string "load")
337 (and (eq_attr "type" "icmov")
338 (match_operand 3 "memory_operand" ""))
339 (const_string "load")
341 (const_string "none")))
343 ;; Indicates if an instruction has both an immediate and a displacement.
345 (define_attr "imm_disp" "false,true,unknown"
346 (cond [(eq_attr "type" "other,multi")
347 (const_string "unknown")
348 (and (eq_attr "type" "icmp,test,imov")
349 (and (match_operand 0 "memory_displacement_operand" "")
350 (match_operand 1 "immediate_operand" "")))
351 (const_string "true")
352 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
353 (and (match_operand 0 "memory_displacement_operand" "")
354 (match_operand 2 "immediate_operand" "")))
355 (const_string "true")
357 (const_string "false")))
359 ;; Indicates if an FP operation has an integer source.
361 (define_attr "fp_int_src" "false,true"
362 (const_string "false"))
364 ;; Describe a user's asm statement.
365 (define_asm_attributes
366 [(set_attr "length" "128")
367 (set_attr "type" "multi")])
369 (include "pentium.md")
372 (include "athlon.md")
374 ;; Compare instructions.
376 ;; All compare insns have expanders that save the operands away without
377 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
378 ;; after the cmp) will actually emit the cmpM.
380 (define_expand "cmpdi"
382 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
383 (match_operand:DI 1 "x86_64_general_operand" "")))]
386 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
387 operands[0] = force_reg (DImode, operands[0]);
388 ix86_compare_op0 = operands[0];
389 ix86_compare_op1 = operands[1];
393 (define_expand "cmpsi"
395 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
396 (match_operand:SI 1 "general_operand" "")))]
399 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
400 operands[0] = force_reg (SImode, operands[0]);
401 ix86_compare_op0 = operands[0];
402 ix86_compare_op1 = operands[1];
406 (define_expand "cmphi"
408 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
409 (match_operand:HI 1 "general_operand" "")))]
412 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
413 operands[0] = force_reg (HImode, operands[0]);
414 ix86_compare_op0 = operands[0];
415 ix86_compare_op1 = operands[1];
419 (define_expand "cmpqi"
421 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
422 (match_operand:QI 1 "general_operand" "")))]
425 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
426 operands[0] = force_reg (QImode, operands[0]);
427 ix86_compare_op0 = operands[0];
428 ix86_compare_op1 = operands[1];
432 (define_insn "cmpdi_ccno_1_rex64"
434 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
435 (match_operand:DI 1 "const0_operand" "n,n")))]
436 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
438 test{q}\t{%0, %0|%0, %0}
439 cmp{q}\t{%1, %0|%0, %1}"
440 [(set_attr "type" "test,icmp")
441 (set_attr "length_immediate" "0,1")
442 (set_attr "mode" "DI")])
444 (define_insn "*cmpdi_minus_1_rex64"
446 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
447 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
449 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
450 "cmp{q}\t{%1, %0|%0, %1}"
451 [(set_attr "type" "icmp")
452 (set_attr "mode" "DI")])
454 (define_expand "cmpdi_1_rex64"
456 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
457 (match_operand:DI 1 "general_operand" "")))]
461 (define_insn "cmpdi_1_insn_rex64"
463 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
464 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
465 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
466 "cmp{q}\t{%1, %0|%0, %1}"
467 [(set_attr "type" "icmp")
468 (set_attr "mode" "DI")])
471 (define_insn "*cmpsi_ccno_1"
473 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
474 (match_operand:SI 1 "const0_operand" "n,n")))]
475 "ix86_match_ccmode (insn, CCNOmode)"
477 test{l}\t{%0, %0|%0, %0}
478 cmp{l}\t{%1, %0|%0, %1}"
479 [(set_attr "type" "test,icmp")
480 (set_attr "length_immediate" "0,1")
481 (set_attr "mode" "SI")])
483 (define_insn "*cmpsi_minus_1"
485 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
486 (match_operand:SI 1 "general_operand" "ri,mr"))
488 "ix86_match_ccmode (insn, CCGOCmode)"
489 "cmp{l}\t{%1, %0|%0, %1}"
490 [(set_attr "type" "icmp")
491 (set_attr "mode" "SI")])
493 (define_expand "cmpsi_1"
495 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
496 (match_operand:SI 1 "general_operand" "ri,mr")))]
500 (define_insn "*cmpsi_1_insn"
502 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
503 (match_operand:SI 1 "general_operand" "ri,mr")))]
504 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
505 && ix86_match_ccmode (insn, CCmode)"
506 "cmp{l}\t{%1, %0|%0, %1}"
507 [(set_attr "type" "icmp")
508 (set_attr "mode" "SI")])
510 (define_insn "*cmphi_ccno_1"
512 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
513 (match_operand:HI 1 "const0_operand" "n,n")))]
514 "ix86_match_ccmode (insn, CCNOmode)"
516 test{w}\t{%0, %0|%0, %0}
517 cmp{w}\t{%1, %0|%0, %1}"
518 [(set_attr "type" "test,icmp")
519 (set_attr "length_immediate" "0,1")
520 (set_attr "mode" "HI")])
522 (define_insn "*cmphi_minus_1"
524 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
525 (match_operand:HI 1 "general_operand" "ri,mr"))
527 "ix86_match_ccmode (insn, CCGOCmode)"
528 "cmp{w}\t{%1, %0|%0, %1}"
529 [(set_attr "type" "icmp")
530 (set_attr "mode" "HI")])
532 (define_insn "*cmphi_1"
534 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
535 (match_operand:HI 1 "general_operand" "ri,mr")))]
536 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
537 && ix86_match_ccmode (insn, CCmode)"
538 "cmp{w}\t{%1, %0|%0, %1}"
539 [(set_attr "type" "icmp")
540 (set_attr "mode" "HI")])
542 (define_insn "*cmpqi_ccno_1"
544 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
545 (match_operand:QI 1 "const0_operand" "n,n")))]
546 "ix86_match_ccmode (insn, CCNOmode)"
548 test{b}\t{%0, %0|%0, %0}
549 cmp{b}\t{$0, %0|%0, 0}"
550 [(set_attr "type" "test,icmp")
551 (set_attr "length_immediate" "0,1")
552 (set_attr "mode" "QI")])
554 (define_insn "*cmpqi_1"
556 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
557 (match_operand:QI 1 "general_operand" "qi,mq")))]
558 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
559 && ix86_match_ccmode (insn, CCmode)"
560 "cmp{b}\t{%1, %0|%0, %1}"
561 [(set_attr "type" "icmp")
562 (set_attr "mode" "QI")])
564 (define_insn "*cmpqi_minus_1"
566 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
567 (match_operand:QI 1 "general_operand" "qi,mq"))
569 "ix86_match_ccmode (insn, CCGOCmode)"
570 "cmp{b}\t{%1, %0|%0, %1}"
571 [(set_attr "type" "icmp")
572 (set_attr "mode" "QI")])
574 (define_insn "*cmpqi_ext_1"
577 (match_operand:QI 0 "general_operand" "Qm")
580 (match_operand 1 "ext_register_operand" "Q")
583 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
584 "cmp{b}\t{%h1, %0|%0, %h1}"
585 [(set_attr "type" "icmp")
586 (set_attr "mode" "QI")])
588 (define_insn "*cmpqi_ext_1_rex64"
591 (match_operand:QI 0 "register_operand" "Q")
594 (match_operand 1 "ext_register_operand" "Q")
597 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
598 "cmp{b}\t{%h1, %0|%0, %h1}"
599 [(set_attr "type" "icmp")
600 (set_attr "mode" "QI")])
602 (define_insn "*cmpqi_ext_2"
607 (match_operand 0 "ext_register_operand" "Q")
610 (match_operand:QI 1 "const0_operand" "n")))]
611 "ix86_match_ccmode (insn, CCNOmode)"
613 [(set_attr "type" "test")
614 (set_attr "length_immediate" "0")
615 (set_attr "mode" "QI")])
617 (define_expand "cmpqi_ext_3"
622 (match_operand 0 "ext_register_operand" "")
625 (match_operand:QI 1 "general_operand" "")))]
629 (define_insn "cmpqi_ext_3_insn"
634 (match_operand 0 "ext_register_operand" "Q")
637 (match_operand:QI 1 "general_operand" "Qmn")))]
638 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
639 "cmp{b}\t{%1, %h0|%h0, %1}"
640 [(set_attr "type" "icmp")
641 (set_attr "mode" "QI")])
643 (define_insn "cmpqi_ext_3_insn_rex64"
648 (match_operand 0 "ext_register_operand" "Q")
651 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
652 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
653 "cmp{b}\t{%1, %h0|%h0, %1}"
654 [(set_attr "type" "icmp")
655 (set_attr "mode" "QI")])
657 (define_insn "*cmpqi_ext_4"
662 (match_operand 0 "ext_register_operand" "Q")
667 (match_operand 1 "ext_register_operand" "Q")
670 "ix86_match_ccmode (insn, CCmode)"
671 "cmp{b}\t{%h1, %h0|%h0, %h1}"
672 [(set_attr "type" "icmp")
673 (set_attr "mode" "QI")])
675 ;; These implement float point compares.
676 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
677 ;; which would allow mix and match FP modes on the compares. Which is what
678 ;; the old patterns did, but with many more of them.
680 (define_expand "cmpxf"
682 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
683 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
684 "!TARGET_64BIT && TARGET_80387"
686 ix86_compare_op0 = operands[0];
687 ix86_compare_op1 = operands[1];
691 (define_expand "cmptf"
693 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
694 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
697 ix86_compare_op0 = operands[0];
698 ix86_compare_op1 = operands[1];
702 (define_expand "cmpdf"
704 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
705 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
706 "TARGET_80387 || TARGET_SSE2"
708 ix86_compare_op0 = operands[0];
709 ix86_compare_op1 = operands[1];
713 (define_expand "cmpsf"
715 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
716 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
717 "TARGET_80387 || TARGET_SSE"
719 ix86_compare_op0 = operands[0];
720 ix86_compare_op1 = operands[1];
724 ;; FP compares, step 1:
725 ;; Set the FP condition codes.
727 ;; CCFPmode compare with exceptions
728 ;; CCFPUmode compare with no exceptions
730 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
731 ;; and that fp moves clobber the condition codes, and that there is
732 ;; currently no way to describe this fact to reg-stack. So there are
733 ;; no splitters yet for this.
735 ;; %%% YIKES! This scheme does not retain a strong connection between
736 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
737 ;; work! Only allow tos/mem with tos in op 0.
739 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
740 ;; things aren't as bad as they sound...
742 (define_insn "*cmpfp_0"
743 [(set (match_operand:HI 0 "register_operand" "=a")
745 [(compare:CCFP (match_operand 1 "register_operand" "f")
746 (match_operand 2 "const0_operand" "X"))]
749 && FLOAT_MODE_P (GET_MODE (operands[1]))
750 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
752 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
753 return "ftst\;fnstsw\t%0\;fstp\t%y0";
755 return "ftst\;fnstsw\t%0";
757 [(set_attr "type" "multi")
758 (set_attr "mode" "unknownfp")])
760 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
761 ;; used to manage the reg stack popping would not be preserved.
763 (define_insn "*cmpfp_2_sf"
766 (match_operand:SF 0 "register_operand" "f")
767 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
769 "* return output_fp_compare (insn, operands, 0, 0);"
770 [(set_attr "type" "fcmp")
771 (set_attr "mode" "SF")])
773 (define_insn "*cmpfp_2_sf_1"
774 [(set (match_operand:HI 0 "register_operand" "=a")
777 (match_operand:SF 1 "register_operand" "f")
778 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
781 "* return output_fp_compare (insn, operands, 2, 0);"
782 [(set_attr "type" "fcmp")
783 (set_attr "mode" "SF")])
785 (define_insn "*cmpfp_2_df"
788 (match_operand:DF 0 "register_operand" "f")
789 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
791 "* return output_fp_compare (insn, operands, 0, 0);"
792 [(set_attr "type" "fcmp")
793 (set_attr "mode" "DF")])
795 (define_insn "*cmpfp_2_df_1"
796 [(set (match_operand:HI 0 "register_operand" "=a")
799 (match_operand:DF 1 "register_operand" "f")
800 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
803 "* return output_fp_compare (insn, operands, 2, 0);"
804 [(set_attr "type" "multi")
805 (set_attr "mode" "DF")])
807 (define_insn "*cmpfp_2_xf"
810 (match_operand:XF 0 "register_operand" "f")
811 (match_operand:XF 1 "register_operand" "f")))]
812 "!TARGET_64BIT && TARGET_80387"
813 "* return output_fp_compare (insn, operands, 0, 0);"
814 [(set_attr "type" "fcmp")
815 (set_attr "mode" "XF")])
817 (define_insn "*cmpfp_2_tf"
820 (match_operand:TF 0 "register_operand" "f")
821 (match_operand:TF 1 "register_operand" "f")))]
823 "* return output_fp_compare (insn, operands, 0, 0);"
824 [(set_attr "type" "fcmp")
825 (set_attr "mode" "XF")])
827 (define_insn "*cmpfp_2_xf_1"
828 [(set (match_operand:HI 0 "register_operand" "=a")
831 (match_operand:XF 1 "register_operand" "f")
832 (match_operand:XF 2 "register_operand" "f"))]
834 "!TARGET_64BIT && TARGET_80387"
835 "* return output_fp_compare (insn, operands, 2, 0);"
836 [(set_attr "type" "multi")
837 (set_attr "mode" "XF")])
839 (define_insn "*cmpfp_2_tf_1"
840 [(set (match_operand:HI 0 "register_operand" "=a")
843 (match_operand:TF 1 "register_operand" "f")
844 (match_operand:TF 2 "register_operand" "f"))]
847 "* return output_fp_compare (insn, operands, 2, 0);"
848 [(set_attr "type" "multi")
849 (set_attr "mode" "XF")])
851 (define_insn "*cmpfp_2u"
854 (match_operand 0 "register_operand" "f")
855 (match_operand 1 "register_operand" "f")))]
857 && FLOAT_MODE_P (GET_MODE (operands[0]))
858 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
859 "* return output_fp_compare (insn, operands, 0, 1);"
860 [(set_attr "type" "fcmp")
861 (set_attr "mode" "unknownfp")])
863 (define_insn "*cmpfp_2u_1"
864 [(set (match_operand:HI 0 "register_operand" "=a")
867 (match_operand 1 "register_operand" "f")
868 (match_operand 2 "register_operand" "f"))]
871 && FLOAT_MODE_P (GET_MODE (operands[1]))
872 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
873 "* return output_fp_compare (insn, operands, 2, 1);"
874 [(set_attr "type" "multi")
875 (set_attr "mode" "unknownfp")])
877 ;; Patterns to match the SImode-in-memory ficom instructions.
879 ;; %%% Play games with accepting gp registers, as otherwise we have to
880 ;; force them to memory during rtl generation, which is no good. We
881 ;; can get rid of this once we teach reload to do memory input reloads
884 (define_insn "*ficom_1"
887 (match_operand 0 "register_operand" "f,f")
888 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
889 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
890 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
893 ;; Split the not-really-implemented gp register case into a
894 ;; push-op-pop sequence.
896 ;; %%% This is most efficient, but am I gonna get in trouble
897 ;; for separating cc0_setter and cc0_user?
902 (match_operand:SF 0 "register_operand" "")
903 (float (match_operand:SI 1 "register_operand" ""))))]
904 "0 && TARGET_80387 && reload_completed"
905 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
906 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
907 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
908 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
909 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
910 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
912 ;; FP compares, step 2
913 ;; Move the fpsw to ax.
915 (define_insn "x86_fnstsw_1"
916 [(set (match_operand:HI 0 "register_operand" "=a")
917 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
920 [(set_attr "length" "2")
921 (set_attr "mode" "SI")
922 (set_attr "unit" "i387")
923 (set_attr "ppro_uops" "few")])
925 ;; FP compares, step 3
926 ;; Get ax into flags, general case.
928 (define_insn "x86_sahf_1"
930 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
933 [(set_attr "length" "1")
934 (set_attr "athlon_decode" "vector")
935 (set_attr "mode" "SI")
936 (set_attr "ppro_uops" "one")])
938 ;; Pentium Pro can do steps 1 through 3 in one go.
940 (define_insn "*cmpfp_i"
942 (compare:CCFP (match_operand 0 "register_operand" "f")
943 (match_operand 1 "register_operand" "f")))]
944 "TARGET_80387 && TARGET_CMOVE
945 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
946 && FLOAT_MODE_P (GET_MODE (operands[0]))
947 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
948 "* return output_fp_compare (insn, operands, 1, 0);"
949 [(set_attr "type" "fcmp")
950 (set_attr "mode" "unknownfp")
951 (set_attr "athlon_decode" "vector")])
953 (define_insn "*cmpfp_i_sse"
955 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
956 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
958 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
959 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
960 "* return output_fp_compare (insn, operands, 1, 0);"
961 [(set_attr "type" "fcmp,ssecmp")
962 (set_attr "mode" "unknownfp")
963 (set_attr "athlon_decode" "vector")])
965 (define_insn "*cmpfp_i_sse_only"
967 (compare:CCFP (match_operand 0 "register_operand" "x")
968 (match_operand 1 "nonimmediate_operand" "xm")))]
969 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
970 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
971 "* return output_fp_compare (insn, operands, 1, 0);"
972 [(set_attr "type" "ssecmp")
973 (set_attr "mode" "unknownfp")
974 (set_attr "athlon_decode" "vector")])
976 (define_insn "*cmpfp_iu"
978 (compare:CCFPU (match_operand 0 "register_operand" "f")
979 (match_operand 1 "register_operand" "f")))]
980 "TARGET_80387 && TARGET_CMOVE
981 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
982 && FLOAT_MODE_P (GET_MODE (operands[0]))
983 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
984 "* return output_fp_compare (insn, operands, 1, 1);"
985 [(set_attr "type" "fcmp")
986 (set_attr "mode" "unknownfp")
987 (set_attr "athlon_decode" "vector")])
989 (define_insn "*cmpfp_iu_sse"
991 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
992 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
994 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
995 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
996 "* return output_fp_compare (insn, operands, 1, 1);"
997 [(set_attr "type" "fcmp,ssecmp")
998 (set_attr "mode" "unknownfp")
999 (set_attr "athlon_decode" "vector")])
1001 (define_insn "*cmpfp_iu_sse_only"
1002 [(set (reg:CCFPU 17)
1003 (compare:CCFPU (match_operand 0 "register_operand" "x")
1004 (match_operand 1 "nonimmediate_operand" "xm")))]
1005 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1006 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1007 "* return output_fp_compare (insn, operands, 1, 1);"
1008 [(set_attr "type" "ssecmp")
1009 (set_attr "mode" "unknownfp")
1010 (set_attr "athlon_decode" "vector")])
1012 ;; Move instructions.
1014 ;; General case of fullword move.
1016 (define_expand "movsi"
1017 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1018 (match_operand:SI 1 "general_operand" ""))]
1020 "ix86_expand_move (SImode, operands); DONE;")
1022 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1025 ;; %%% We don't use a post-inc memory reference because x86 is not a
1026 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1027 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1028 ;; targets without our curiosities, and it is just as easy to represent
1029 ;; this differently.
1031 (define_insn "*pushsi2"
1032 [(set (match_operand:SI 0 "push_operand" "=<")
1033 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1036 [(set_attr "type" "push")
1037 (set_attr "mode" "SI")])
1039 ;; For 64BIT abi we always round up to 8 bytes.
1040 (define_insn "*pushsi2_rex64"
1041 [(set (match_operand:SI 0 "push_operand" "=X")
1042 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1045 [(set_attr "type" "push")
1046 (set_attr "mode" "SI")])
1048 (define_insn "*pushsi2_prologue"
1049 [(set (match_operand:SI 0 "push_operand" "=<")
1050 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1051 (clobber (mem:BLK (scratch)))]
1054 [(set_attr "type" "push")
1055 (set_attr "mode" "SI")])
1057 (define_insn "*popsi1_epilogue"
1058 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1059 (mem:SI (reg:SI 7)))
1061 (plus:SI (reg:SI 7) (const_int 4)))
1062 (clobber (mem:BLK (scratch)))]
1065 [(set_attr "type" "pop")
1066 (set_attr "mode" "SI")])
1068 (define_insn "popsi1"
1069 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1070 (mem:SI (reg:SI 7)))
1072 (plus:SI (reg:SI 7) (const_int 4)))]
1075 [(set_attr "type" "pop")
1076 (set_attr "mode" "SI")])
1078 (define_insn "*movsi_xor"
1079 [(set (match_operand:SI 0 "register_operand" "=r")
1080 (match_operand:SI 1 "const0_operand" "i"))
1081 (clobber (reg:CC 17))]
1082 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1083 "xor{l}\t{%0, %0|%0, %0}"
1084 [(set_attr "type" "alu1")
1085 (set_attr "mode" "SI")
1086 (set_attr "length_immediate" "0")])
1088 (define_insn "*movsi_or"
1089 [(set (match_operand:SI 0 "register_operand" "=r")
1090 (match_operand:SI 1 "immediate_operand" "i"))
1091 (clobber (reg:CC 17))]
1092 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1093 && INTVAL (operands[1]) == -1
1094 && (TARGET_PENTIUM || optimize_size)"
1096 operands[1] = constm1_rtx;
1097 return "or{l}\t{%1, %0|%0, %1}";
1099 [(set_attr "type" "alu1")
1100 (set_attr "mode" "SI")
1101 (set_attr "length_immediate" "1")])
1103 ; The first alternative is used only to compute proper length of instruction.
1104 ; Reload's algorithm does not take into account the cost of spill instructions
1105 ; needed to free register in given class, so avoid it from choosing the first
1106 ; alternative when eax is not available.
1108 (define_insn "*movsi_1"
1109 [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1110 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))]
1111 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1113 switch (get_attr_type (insn))
1116 if (get_attr_mode (insn) == TImode)
1117 return "movdqa\t{%1, %0|%0, %1}";
1118 return "movd\t{%1, %0|%0, %1}";
1121 if (get_attr_mode (insn) == DImode)
1122 return "movq\t{%1, %0|%0, %1}";
1123 return "movd\t{%1, %0|%0, %1}";
1126 return "lea{l}\t{%1, %0|%0, %1}";
1129 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1131 return "mov{l}\t{%1, %0|%0, %1}";
1135 (cond [(eq_attr "alternative" "4,5,6")
1136 (const_string "mmxmov")
1137 (eq_attr "alternative" "7,8,9")
1138 (const_string "ssemov")
1139 (and (ne (symbol_ref "flag_pic") (const_int 0))
1140 (match_operand:SI 1 "symbolic_operand" ""))
1141 (const_string "lea")
1143 (const_string "imov")))
1144 (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*")
1145 (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")])
1147 ;; Stores and loads of ax to arbitary constant address.
1148 ;; We fake an second form of instruction to force reload to load address
1149 ;; into register when rax is not available
1150 (define_insn "*movabssi_1_rex64"
1151 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1152 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1155 movabs{l}\t{%1, %P0|%P0, %1}
1156 mov{l}\t{%1, %a0|%a0, %1}
1157 movabs{l}\t{%1, %a0|%a0, %1}"
1158 [(set_attr "type" "imov")
1159 (set_attr "modrm" "0,*,*")
1160 (set_attr "length_address" "8,0,0")
1161 (set_attr "length_immediate" "0,*,*")
1162 (set_attr "memory" "store")
1163 (set_attr "mode" "SI")])
1165 (define_insn "*movabssi_2_rex64"
1166 [(set (match_operand:SI 0 "register_operand" "=a,r")
1167 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1170 movabs{l}\t{%P1, %0|%0, %P1}
1171 mov{l}\t{%a1, %0|%0, %a1}"
1172 [(set_attr "type" "imov")
1173 (set_attr "modrm" "0,*")
1174 (set_attr "length_address" "8,0")
1175 (set_attr "length_immediate" "0")
1176 (set_attr "memory" "load")
1177 (set_attr "mode" "SI")])
1179 (define_insn "*swapsi"
1180 [(set (match_operand:SI 0 "register_operand" "+r")
1181 (match_operand:SI 1 "register_operand" "+r"))
1186 [(set_attr "type" "imov")
1187 (set_attr "pent_pair" "np")
1188 (set_attr "athlon_decode" "vector")
1189 (set_attr "mode" "SI")
1190 (set_attr "modrm" "0")
1191 (set_attr "ppro_uops" "few")])
1193 (define_expand "movhi"
1194 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1195 (match_operand:HI 1 "general_operand" ""))]
1197 "ix86_expand_move (HImode, operands); DONE;")
1199 (define_insn "*pushhi2"
1200 [(set (match_operand:HI 0 "push_operand" "=<,<")
1201 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1204 push{w}\t{|WORD PTR }%1
1206 [(set_attr "type" "push")
1207 (set_attr "mode" "HI")])
1209 ;; For 64BIT abi we always round up to 8 bytes.
1210 (define_insn "*pushhi2_rex64"
1211 [(set (match_operand:HI 0 "push_operand" "=X")
1212 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1215 [(set_attr "type" "push")
1216 (set_attr "mode" "QI")])
1218 ; The first alternative is used only to compute proper length of instruction.
1219 ; Reload's algorithm does not take into account the cost of spill instructions
1220 ; needed to free register in given class, so avoid it from choosing the first
1221 ; alternative when eax is not available.
1223 (define_insn "*movhi_1"
1224 [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m")
1225 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1226 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1228 switch (get_attr_type (insn))
1231 /* movzwl is faster than movw on p2 due to partial word stalls,
1232 though not as fast as an aligned movl. */
1233 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1235 if (get_attr_mode (insn) == MODE_SI)
1236 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1238 return "mov{w}\t{%1, %0|%0, %1}";
1242 (cond [(and (eq_attr "alternative" "0,1")
1243 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1245 (eq (symbol_ref "TARGET_HIMODE_MATH")
1247 (const_string "imov")
1248 (and (eq_attr "alternative" "2,3,4")
1249 (match_operand:HI 1 "aligned_operand" ""))
1250 (const_string "imov")
1251 (and (ne (symbol_ref "TARGET_MOVX")
1253 (eq_attr "alternative" "0,1,3,4"))
1254 (const_string "imovx")
1256 (const_string "imov")))
1258 (cond [(eq_attr "type" "imovx")
1260 (and (eq_attr "alternative" "2,3,4")
1261 (match_operand:HI 1 "aligned_operand" ""))
1263 (and (eq_attr "alternative" "0,1")
1264 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1266 (eq (symbol_ref "TARGET_HIMODE_MATH")
1270 (const_string "HI")))
1271 (set_attr "modrm" "0,*,*,0,*,*")])
1273 ;; Stores and loads of ax to arbitary constant address.
1274 ;; We fake an second form of instruction to force reload to load address
1275 ;; into register when rax is not available
1276 (define_insn "*movabshi_1_rex64"
1277 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1278 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1281 movabs{w}\t{%1, %P0|%P0, %1}
1282 mov{w}\t{%1, %a0|%a0, %1}
1283 movabs{w}\t{%1, %a0|%a0, %1}"
1284 [(set_attr "type" "imov")
1285 (set_attr "modrm" "0,*,*")
1286 (set_attr "length_address" "8,0,0")
1287 (set_attr "length_immediate" "0,*,*")
1288 (set_attr "memory" "store")
1289 (set_attr "mode" "HI")])
1291 (define_insn "*movabshi_2_rex64"
1292 [(set (match_operand:HI 0 "register_operand" "=a,r")
1293 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1296 movabs{w}\t{%P1, %0|%0, %P1}
1297 mov{w}\t{%a1, %0|%0, %a1}"
1298 [(set_attr "type" "imov")
1299 (set_attr "modrm" "0,*")
1300 (set_attr "length_address" "8,0")
1301 (set_attr "length_immediate" "0")
1302 (set_attr "memory" "load")
1303 (set_attr "mode" "HI")])
1305 (define_insn "*swaphi_1"
1306 [(set (match_operand:HI 0 "register_operand" "+r")
1307 (match_operand:HI 1 "register_operand" "+r"))
1310 "TARGET_PARTIAL_REG_STALL"
1312 [(set_attr "type" "imov")
1313 (set_attr "pent_pair" "np")
1314 (set_attr "mode" "HI")
1315 (set_attr "modrm" "0")
1316 (set_attr "ppro_uops" "few")])
1318 (define_insn "*swaphi_2"
1319 [(set (match_operand:HI 0 "register_operand" "+r")
1320 (match_operand:HI 1 "register_operand" "+r"))
1323 "! TARGET_PARTIAL_REG_STALL"
1325 [(set_attr "type" "imov")
1326 (set_attr "pent_pair" "np")
1327 (set_attr "mode" "SI")
1328 (set_attr "modrm" "0")
1329 (set_attr "ppro_uops" "few")])
1331 (define_expand "movstricthi"
1332 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1333 (match_operand:HI 1 "general_operand" ""))]
1334 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1336 /* Don't generate memory->memory moves, go through a register */
1337 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1338 operands[1] = force_reg (HImode, operands[1]);
1341 (define_insn "*movstricthi_1"
1342 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1343 (match_operand:HI 1 "general_operand" "rn,m"))]
1344 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1345 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1346 "mov{w}\t{%1, %0|%0, %1}"
1347 [(set_attr "type" "imov")
1348 (set_attr "mode" "HI")])
1350 (define_insn "*movstricthi_xor"
1351 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1352 (match_operand:HI 1 "const0_operand" "i"))
1353 (clobber (reg:CC 17))]
1355 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1356 "xor{w}\t{%0, %0|%0, %0}"
1357 [(set_attr "type" "alu1")
1358 (set_attr "mode" "HI")
1359 (set_attr "length_immediate" "0")])
1361 (define_expand "movqi"
1362 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1363 (match_operand:QI 1 "general_operand" ""))]
1365 "ix86_expand_move (QImode, operands); DONE;")
1367 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1368 ;; "push a byte". But actually we use pushw, which has the effect
1369 ;; of rounding the amount pushed up to a halfword.
1371 (define_insn "*pushqi2"
1372 [(set (match_operand:QI 0 "push_operand" "=X,X")
1373 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1376 push{w}\t{|word ptr }%1
1378 [(set_attr "type" "push")
1379 (set_attr "mode" "HI")])
1381 ;; For 64BIT abi we always round up to 8 bytes.
1382 (define_insn "*pushqi2_rex64"
1383 [(set (match_operand:QI 0 "push_operand" "=X")
1384 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1387 [(set_attr "type" "push")
1388 (set_attr "mode" "QI")])
1390 ;; Situation is quite tricky about when to choose full sized (SImode) move
1391 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1392 ;; partial register dependency machines (such as AMD Athlon), where QImode
1393 ;; moves issue extra dependency and for partial register stalls machines
1394 ;; that don't use QImode patterns (and QImode move cause stall on the next
1397 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1398 ;; register stall machines with, where we use QImode instructions, since
1399 ;; partial register stall can be caused there. Then we use movzx.
1400 (define_insn "*movqi_1"
1401 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1402 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1403 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1405 switch (get_attr_type (insn))
1408 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1410 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1412 if (get_attr_mode (insn) == MODE_SI)
1413 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1415 return "mov{b}\t{%1, %0|%0, %1}";
1419 (cond [(and (eq_attr "alternative" "3")
1420 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1422 (eq (symbol_ref "TARGET_QIMODE_MATH")
1424 (const_string "imov")
1425 (eq_attr "alternative" "3,5")
1426 (const_string "imovx")
1427 (and (ne (symbol_ref "TARGET_MOVX")
1429 (eq_attr "alternative" "2"))
1430 (const_string "imovx")
1432 (const_string "imov")))
1434 (cond [(eq_attr "alternative" "3,4,5")
1436 (eq_attr "alternative" "6")
1438 (eq_attr "type" "imovx")
1440 (and (eq_attr "type" "imov")
1441 (and (eq_attr "alternative" "0,1,2")
1442 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1445 ;; Avoid partial register stalls when not using QImode arithmetic
1446 (and (eq_attr "type" "imov")
1447 (and (eq_attr "alternative" "0,1,2")
1448 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1450 (eq (symbol_ref "TARGET_QIMODE_MATH")
1454 (const_string "QI")))])
1456 (define_expand "reload_outqi"
1457 [(parallel [(match_operand:QI 0 "" "=m")
1458 (match_operand:QI 1 "register_operand" "r")
1459 (match_operand:QI 2 "register_operand" "=&q")])]
1463 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1465 if (reg_overlap_mentioned_p (op2, op0))
1467 if (! q_regs_operand (op1, QImode))
1469 emit_insn (gen_movqi (op2, op1));
1472 emit_insn (gen_movqi (op0, op1));
1476 (define_insn "*swapqi"
1477 [(set (match_operand:QI 0 "register_operand" "+r")
1478 (match_operand:QI 1 "register_operand" "+r"))
1483 [(set_attr "type" "imov")
1484 (set_attr "pent_pair" "np")
1485 (set_attr "mode" "QI")
1486 (set_attr "modrm" "0")
1487 (set_attr "ppro_uops" "few")])
1489 (define_expand "movstrictqi"
1490 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1491 (match_operand:QI 1 "general_operand" ""))]
1492 "! TARGET_PARTIAL_REG_STALL"
1494 /* Don't generate memory->memory moves, go through a register. */
1495 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1496 operands[1] = force_reg (QImode, operands[1]);
1499 (define_insn "*movstrictqi_1"
1500 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1501 (match_operand:QI 1 "general_operand" "*qn,m"))]
1502 "! TARGET_PARTIAL_REG_STALL
1503 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1504 "mov{b}\t{%1, %0|%0, %1}"
1505 [(set_attr "type" "imov")
1506 (set_attr "mode" "QI")])
1508 (define_insn "*movstrictqi_xor"
1509 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1510 (match_operand:QI 1 "const0_operand" "i"))
1511 (clobber (reg:CC 17))]
1512 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1513 "xor{b}\t{%0, %0|%0, %0}"
1514 [(set_attr "type" "alu1")
1515 (set_attr "mode" "QI")
1516 (set_attr "length_immediate" "0")])
1518 (define_insn "*movsi_extv_1"
1519 [(set (match_operand:SI 0 "register_operand" "=R")
1520 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1524 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1525 [(set_attr "type" "imovx")
1526 (set_attr "mode" "SI")])
1528 (define_insn "*movhi_extv_1"
1529 [(set (match_operand:HI 0 "register_operand" "=R")
1530 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1534 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1535 [(set_attr "type" "imovx")
1536 (set_attr "mode" "SI")])
1538 (define_insn "*movqi_extv_1"
1539 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1540 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1545 switch (get_attr_type (insn))
1548 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1550 return "mov{b}\t{%h1, %0|%0, %h1}";
1554 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1555 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1556 (ne (symbol_ref "TARGET_MOVX")
1558 (const_string "imovx")
1559 (const_string "imov")))
1561 (if_then_else (eq_attr "type" "imovx")
1563 (const_string "QI")))])
1565 (define_insn "*movqi_extv_1_rex64"
1566 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1567 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1572 switch (get_attr_type (insn))
1575 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1577 return "mov{b}\t{%h1, %0|%0, %h1}";
1581 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1582 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1583 (ne (symbol_ref "TARGET_MOVX")
1585 (const_string "imovx")
1586 (const_string "imov")))
1588 (if_then_else (eq_attr "type" "imovx")
1590 (const_string "QI")))])
1592 ;; Stores and loads of ax to arbitary constant address.
1593 ;; We fake an second form of instruction to force reload to load address
1594 ;; into register when rax is not available
1595 (define_insn "*movabsqi_1_rex64"
1596 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1597 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
1600 movabs{b}\t{%1, %P0|%P0, %1}
1601 mov{b}\t{%1, %a0|%a0, %1}
1602 movabs{b}\t{%1, %a0|%a0, %1}"
1603 [(set_attr "type" "imov")
1604 (set_attr "modrm" "0,*,*")
1605 (set_attr "length_address" "8,0,0")
1606 (set_attr "length_immediate" "0,*,*")
1607 (set_attr "memory" "store")
1608 (set_attr "mode" "QI")])
1610 (define_insn "*movabsqi_2_rex64"
1611 [(set (match_operand:QI 0 "register_operand" "=a,r")
1612 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1615 movabs{b}\t{%P1, %0|%0, %P1}
1616 mov{b}\t{%a1, %0|%0, %a1}"
1617 [(set_attr "type" "imov")
1618 (set_attr "modrm" "0,*")
1619 (set_attr "length_address" "8,0")
1620 (set_attr "length_immediate" "0")
1621 (set_attr "memory" "load")
1622 (set_attr "mode" "QI")])
1624 (define_insn "*movsi_extzv_1"
1625 [(set (match_operand:SI 0 "register_operand" "=R")
1626 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1630 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1631 [(set_attr "type" "imovx")
1632 (set_attr "mode" "SI")])
1634 (define_insn "*movqi_extzv_2"
1635 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1636 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1641 switch (get_attr_type (insn))
1644 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1646 return "mov{b}\t{%h1, %0|%0, %h1}";
1650 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1651 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1652 (ne (symbol_ref "TARGET_MOVX")
1654 (const_string "imovx")
1655 (const_string "imov")))
1657 (if_then_else (eq_attr "type" "imovx")
1659 (const_string "QI")))])
1661 (define_insn "*movqi_extzv_2_rex64"
1662 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1663 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1668 switch (get_attr_type (insn))
1671 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1673 return "mov{b}\t{%h1, %0|%0, %h1}";
1677 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1678 (ne (symbol_ref "TARGET_MOVX")
1680 (const_string "imovx")
1681 (const_string "imov")))
1683 (if_then_else (eq_attr "type" "imovx")
1685 (const_string "QI")))])
1687 (define_insn "movsi_insv_1"
1688 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1691 (match_operand:SI 1 "general_operand" "Qmn"))]
1693 "mov{b}\t{%b1, %h0|%h0, %b1}"
1694 [(set_attr "type" "imov")
1695 (set_attr "mode" "QI")])
1697 (define_insn "*movsi_insv_1_rex64"
1698 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1701 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1703 "mov{b}\t{%b1, %h0|%h0, %b1}"
1704 [(set_attr "type" "imov")
1705 (set_attr "mode" "QI")])
1707 (define_insn "*movqi_insv_2"
1708 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1711 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1715 "mov{b}\t{%h1, %h0|%h0, %h1}"
1716 [(set_attr "type" "imov")
1717 (set_attr "mode" "QI")])
1719 (define_expand "movdi"
1720 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1721 (match_operand:DI 1 "general_operand" ""))]
1723 "ix86_expand_move (DImode, operands); DONE;")
1725 (define_insn "*pushdi"
1726 [(set (match_operand:DI 0 "push_operand" "=<")
1727 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1731 (define_insn "pushdi2_rex64"
1732 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1733 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1738 [(set_attr "type" "push,multi")
1739 (set_attr "mode" "DI")])
1741 ;; Convert impossible pushes of immediate to existing instructions.
1742 ;; First try to get scratch register and go through it. In case this
1743 ;; fails, push sign extended lower part first and then overwrite
1744 ;; upper part by 32bit move.
1746 [(match_scratch:DI 2 "r")
1747 (set (match_operand:DI 0 "push_operand" "")
1748 (match_operand:DI 1 "immediate_operand" ""))]
1749 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1750 && !x86_64_immediate_operand (operands[1], DImode)"
1751 [(set (match_dup 2) (match_dup 1))
1752 (set (match_dup 0) (match_dup 2))]
1755 ;; We need to define this as both peepholer and splitter for case
1756 ;; peephole2 pass is not run.
1758 [(set (match_operand:DI 0 "push_operand" "")
1759 (match_operand:DI 1 "immediate_operand" ""))]
1760 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1761 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1762 [(set (match_dup 0) (match_dup 1))
1763 (set (match_dup 2) (match_dup 3))]
1764 "split_di (operands + 1, 1, operands + 2, operands + 3);
1765 operands[1] = gen_lowpart (DImode, operands[2]);
1766 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1771 [(set (match_operand:DI 0 "push_operand" "")
1772 (match_operand:DI 1 "immediate_operand" ""))]
1773 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1774 && !symbolic_operand (operands[1], DImode)
1775 && !x86_64_immediate_operand (operands[1], DImode)"
1776 [(set (match_dup 0) (match_dup 1))
1777 (set (match_dup 2) (match_dup 3))]
1778 "split_di (operands + 1, 1, operands + 2, operands + 3);
1779 operands[1] = gen_lowpart (DImode, operands[2]);
1780 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1784 (define_insn "*pushdi2_prologue_rex64"
1785 [(set (match_operand:DI 0 "push_operand" "=<")
1786 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1787 (clobber (mem:BLK (scratch)))]
1790 [(set_attr "type" "push")
1791 (set_attr "mode" "DI")])
1793 (define_insn "*popdi1_epilogue_rex64"
1794 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1795 (mem:DI (reg:DI 7)))
1797 (plus:DI (reg:DI 7) (const_int 8)))
1798 (clobber (mem:BLK (scratch)))]
1801 [(set_attr "type" "pop")
1802 (set_attr "mode" "DI")])
1804 (define_insn "popdi1"
1805 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1806 (mem:DI (reg:DI 7)))
1808 (plus:DI (reg:DI 7) (const_int 8)))]
1811 [(set_attr "type" "pop")
1812 (set_attr "mode" "DI")])
1814 (define_insn "*movdi_xor_rex64"
1815 [(set (match_operand:DI 0 "register_operand" "=r")
1816 (match_operand:DI 1 "const0_operand" "i"))
1817 (clobber (reg:CC 17))]
1818 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1819 && reload_completed"
1820 "xor{l}\t{%k0, %k0|%k0, %k0}"
1821 [(set_attr "type" "alu1")
1822 (set_attr "mode" "SI")
1823 (set_attr "length_immediate" "0")])
1825 (define_insn "*movdi_or_rex64"
1826 [(set (match_operand:DI 0 "register_operand" "=r")
1827 (match_operand:DI 1 "const_int_operand" "i"))
1828 (clobber (reg:CC 17))]
1829 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1831 && GET_CODE (operands[1]) == CONST_INT
1832 && INTVAL (operands[1]) == -1"
1834 operands[1] = constm1_rtx;
1835 return "or{q}\t{%1, %0|%0, %1}";
1837 [(set_attr "type" "alu1")
1838 (set_attr "mode" "DI")
1839 (set_attr "length_immediate" "1")])
1841 (define_insn "*movdi_2"
1842 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1843 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1845 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1849 movq\t{%1, %0|%0, %1}
1850 movq\t{%1, %0|%0, %1}
1851 movq\t{%1, %0|%0, %1}
1852 movdqa\t{%1, %0|%0, %1}
1853 movq\t{%1, %0|%0, %1}"
1854 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1855 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1858 [(set (match_operand:DI 0 "push_operand" "")
1859 (match_operand:DI 1 "general_operand" ""))]
1860 "!TARGET_64BIT && reload_completed
1861 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1863 "ix86_split_long_move (operands); DONE;")
1865 ;; %%% This multiword shite has got to go.
1867 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1868 (match_operand:DI 1 "general_operand" ""))]
1869 "!TARGET_64BIT && reload_completed
1870 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1871 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1873 "ix86_split_long_move (operands); DONE;")
1875 (define_insn "*movdi_1_rex64"
1876 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
1877 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
1879 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1881 switch (get_attr_type (insn))
1884 if (register_operand (operands[0], DImode)
1885 && register_operand (operands[1], DImode))
1886 return "movdqa\t{%1, %0|%0, %1}";
1889 return "movq\t{%1, %0|%0, %1}";
1893 return "lea{q}\t{%a1, %0|%0, %a1}";
1895 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1897 if (get_attr_mode (insn) == MODE_SI)
1898 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1899 else if (which_alternative == 2)
1900 return "movabs{q}\t{%1, %0|%0, %1}";
1902 return "mov{q}\t{%1, %0|%0, %1}";
1906 (cond [(eq_attr "alternative" "5,6")
1907 (const_string "mmxmov")
1908 (eq_attr "alternative" "7,8")
1909 (const_string "ssemov")
1910 (eq_attr "alternative" "4")
1911 (const_string "multi")
1912 (and (ne (symbol_ref "flag_pic") (const_int 0))
1913 (match_operand:DI 1 "symbolic_operand" ""))
1914 (const_string "lea")
1916 (const_string "imov")))
1917 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*")
1918 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*")
1919 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")])
1921 ;; Stores and loads of ax to arbitary constant address.
1922 ;; We fake an second form of instruction to force reload to load address
1923 ;; into register when rax is not available
1924 (define_insn "*movabsdi_1_rex64"
1925 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1926 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
1929 movabs{q}\t{%1, %P0|%P0, %1}
1930 mov{q}\t{%1, %a0|%a0, %1}
1931 movabs{q}\t{%1, %a0|%a0, %1}"
1932 [(set_attr "type" "imov")
1933 (set_attr "modrm" "0,*,*")
1934 (set_attr "length_address" "8,0,0")
1935 (set_attr "length_immediate" "0,*,*")
1936 (set_attr "memory" "store")
1937 (set_attr "mode" "DI")])
1939 (define_insn "*movabsdi_2_rex64"
1940 [(set (match_operand:DI 0 "register_operand" "=a,r")
1941 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1944 movabs{q}\t{%P1, %0|%0, %P1}
1945 mov{q}\t{%a1, %0|%0, %a1}"
1946 [(set_attr "type" "imov")
1947 (set_attr "modrm" "0,*")
1948 (set_attr "length_address" "8,0")
1949 (set_attr "length_immediate" "0")
1950 (set_attr "memory" "load")
1951 (set_attr "mode" "DI")])
1953 ;; Convert impossible stores of immediate to existing instructions.
1954 ;; First try to get scratch register and go through it. In case this
1955 ;; fails, move by 32bit parts.
1957 [(match_scratch:DI 2 "r")
1958 (set (match_operand:DI 0 "memory_operand" "")
1959 (match_operand:DI 1 "immediate_operand" ""))]
1960 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1961 && !x86_64_immediate_operand (operands[1], DImode)"
1962 [(set (match_dup 2) (match_dup 1))
1963 (set (match_dup 0) (match_dup 2))]
1966 ;; We need to define this as both peepholer and splitter for case
1967 ;; peephole2 pass is not run.
1969 [(set (match_operand:DI 0 "memory_operand" "")
1970 (match_operand:DI 1 "immediate_operand" ""))]
1971 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1972 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1973 [(set (match_dup 2) (match_dup 3))
1974 (set (match_dup 4) (match_dup 5))]
1975 "split_di (operands, 2, operands + 2, operands + 4);")
1978 [(set (match_operand:DI 0 "memory_operand" "")
1979 (match_operand:DI 1 "immediate_operand" ""))]
1980 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1981 && !symbolic_operand (operands[1], DImode)
1982 && !x86_64_immediate_operand (operands[1], DImode)"
1983 [(set (match_dup 2) (match_dup 3))
1984 (set (match_dup 4) (match_dup 5))]
1985 "split_di (operands, 2, operands + 2, operands + 4);")
1987 (define_insn "*swapdi_rex64"
1988 [(set (match_operand:DI 0 "register_operand" "+r")
1989 (match_operand:DI 1 "register_operand" "+r"))
1994 [(set_attr "type" "imov")
1995 (set_attr "pent_pair" "np")
1996 (set_attr "athlon_decode" "vector")
1997 (set_attr "mode" "DI")
1998 (set_attr "modrm" "0")
1999 (set_attr "ppro_uops" "few")])
2002 (define_expand "movsf"
2003 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2004 (match_operand:SF 1 "general_operand" ""))]
2006 "ix86_expand_move (SFmode, operands); DONE;")
2008 (define_insn "*pushsf"
2009 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2010 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2013 switch (which_alternative)
2016 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2017 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2018 operands[2] = stack_pointer_rtx;
2019 operands[3] = GEN_INT (4);
2020 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2021 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2023 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2026 return "push{l}\t%1";
2034 [(set_attr "type" "multi,push,multi")
2035 (set_attr "mode" "SF,SI,SF")])
2037 (define_insn "*pushsf_rex64"
2038 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2039 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2042 switch (which_alternative)
2045 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2046 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2047 operands[2] = stack_pointer_rtx;
2048 operands[3] = GEN_INT (8);
2049 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2050 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2052 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2055 return "push{q}\t%q1";
2064 [(set_attr "type" "multi,push,multi")
2065 (set_attr "mode" "SF,DI,SF")])
2068 [(set (match_operand:SF 0 "push_operand" "")
2069 (match_operand:SF 1 "memory_operand" ""))]
2071 && GET_CODE (operands[1]) == MEM
2072 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2073 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2076 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2079 ;; %%% Kill this when call knows how to work this out.
2081 [(set (match_operand:SF 0 "push_operand" "")
2082 (match_operand:SF 1 "any_fp_register_operand" ""))]
2084 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2085 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2088 [(set (match_operand:SF 0 "push_operand" "")
2089 (match_operand:SF 1 "any_fp_register_operand" ""))]
2091 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2092 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2094 (define_insn "*movsf_1"
2095 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2096 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))]
2097 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2098 && (reload_in_progress || reload_completed
2099 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2100 || GET_CODE (operands[1]) != CONST_DOUBLE
2101 || memory_operand (operands[0], SFmode))"
2103 switch (which_alternative)
2106 if (REG_P (operands[1])
2107 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2109 else if (STACK_TOP_P (operands[0]))
2110 return "fld%z1\t%y1";
2115 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2116 return "fstp%z0\t%y0";
2118 return "fst%z0\t%y0";
2121 switch (standard_80387_constant_p (operands[1]))
2132 return "mov{l}\t{%1, %0|%0, %1}";
2134 if (TARGET_SSE2 && !TARGET_ATHLON)
2135 return "pxor\t%0, %0";
2137 return "xorps\t%0, %0";
2139 if (TARGET_PARTIAL_REG_DEPENDENCY)
2140 return "movaps\t{%1, %0|%0, %1}";
2142 return "movss\t{%1, %0|%0, %1}";
2145 return "movss\t{%1, %0|%0, %1}";
2149 return "movd\t{%1, %0|%0, %1}";
2152 return "movq\t{%1, %0|%0, %1}";
2158 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2159 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
2161 (define_insn "*swapsf"
2162 [(set (match_operand:SF 0 "register_operand" "+f")
2163 (match_operand:SF 1 "register_operand" "+f"))
2166 "reload_completed || !TARGET_SSE"
2168 if (STACK_TOP_P (operands[0]))
2173 [(set_attr "type" "fxch")
2174 (set_attr "mode" "SF")])
2176 (define_expand "movdf"
2177 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2178 (match_operand:DF 1 "general_operand" ""))]
2180 "ix86_expand_move (DFmode, operands); DONE;")
2182 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2183 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2184 ;; On the average, pushdf using integers can be still shorter. Allow this
2185 ;; pattern for optimize_size too.
2187 (define_insn "*pushdf_nointeger"
2188 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2189 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2190 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2192 switch (which_alternative)
2195 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2196 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2197 operands[2] = stack_pointer_rtx;
2198 operands[3] = GEN_INT (8);
2199 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2200 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2202 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2213 [(set_attr "type" "multi")
2214 (set_attr "mode" "DF,SI,SI,DF")])
2216 (define_insn "*pushdf_integer"
2217 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2218 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2219 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2221 switch (which_alternative)
2224 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2225 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2226 operands[2] = stack_pointer_rtx;
2227 operands[3] = GEN_INT (8);
2229 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2230 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2232 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2234 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2235 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2237 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2248 [(set_attr "type" "multi")
2249 (set_attr "mode" "DF,SI,DF")])
2251 ;; %%% Kill this when call knows how to work this out.
2253 [(set (match_operand:DF 0 "push_operand" "")
2254 (match_operand:DF 1 "any_fp_register_operand" ""))]
2255 "!TARGET_64BIT && reload_completed"
2256 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2257 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2261 [(set (match_operand:DF 0 "push_operand" "")
2262 (match_operand:DF 1 "any_fp_register_operand" ""))]
2263 "TARGET_64BIT && reload_completed"
2264 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2265 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2269 [(set (match_operand:DF 0 "push_operand" "")
2270 (match_operand:DF 1 "general_operand" ""))]
2273 "ix86_split_long_move (operands); DONE;")
2275 ;; Moving is usually shorter when only FP registers are used. This separate
2276 ;; movdf pattern avoids the use of integer registers for FP operations
2277 ;; when optimizing for size.
2279 (define_insn "*movdf_nointeger"
2280 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2281 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2282 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2283 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2284 && (reload_in_progress || reload_completed
2285 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2286 || GET_CODE (operands[1]) != CONST_DOUBLE
2287 || memory_operand (operands[0], DFmode))"
2289 switch (which_alternative)
2292 if (REG_P (operands[1])
2293 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2295 else if (STACK_TOP_P (operands[0]))
2296 return "fld%z1\t%y1";
2301 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2302 return "fstp%z0\t%y0";
2304 return "fst%z0\t%y0";
2307 switch (standard_80387_constant_p (operands[1]))
2321 return "xorpd\t%0, %0";
2323 return "pxor\t%0, %0";
2325 if (TARGET_PARTIAL_REG_DEPENDENCY)
2326 return "movapd\t{%1, %0|%0, %1}";
2328 return "movsd\t{%1, %0|%0, %1}";
2331 return "movsd\t{%1, %0|%0, %1}";
2337 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2338 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2340 (define_insn "*movdf_integer"
2341 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2342 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2343 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2344 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2345 && (reload_in_progress || reload_completed
2346 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2347 || GET_CODE (operands[1]) != CONST_DOUBLE
2348 || memory_operand (operands[0], DFmode))"
2350 switch (which_alternative)
2353 if (REG_P (operands[1])
2354 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2356 else if (STACK_TOP_P (operands[0]))
2357 return "fld%z1\t%y1";
2362 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2363 return "fstp%z0\t%y0";
2365 return "fst%z0\t%y0";
2368 switch (standard_80387_constant_p (operands[1]))
2383 return "xorpd\t%0, %0";
2385 return "pxor\t%0, %0";
2387 if (TARGET_PARTIAL_REG_DEPENDENCY)
2388 return "movapd\t{%1, %0|%0, %1}";
2390 return "movsd\t{%1, %0|%0, %1}";
2393 return "movsd\t{%1, %0|%0, %1}";
2399 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2400 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2403 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2404 (match_operand:DF 1 "general_operand" ""))]
2406 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2407 && ! (ANY_FP_REG_P (operands[0]) ||
2408 (GET_CODE (operands[0]) == SUBREG
2409 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2410 && ! (ANY_FP_REG_P (operands[1]) ||
2411 (GET_CODE (operands[1]) == SUBREG
2412 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2414 "ix86_split_long_move (operands); DONE;")
2416 (define_insn "*swapdf"
2417 [(set (match_operand:DF 0 "register_operand" "+f")
2418 (match_operand:DF 1 "register_operand" "+f"))
2421 "reload_completed || !TARGET_SSE2"
2423 if (STACK_TOP_P (operands[0]))
2428 [(set_attr "type" "fxch")
2429 (set_attr "mode" "DF")])
2431 (define_expand "movxf"
2432 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2433 (match_operand:XF 1 "general_operand" ""))]
2435 "ix86_expand_move (XFmode, operands); DONE;")
2437 (define_expand "movtf"
2438 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2439 (match_operand:TF 1 "general_operand" ""))]
2441 "ix86_expand_move (TFmode, operands); DONE;")
2443 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2444 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
2445 ;; Pushing using integer instructions is longer except for constants
2446 ;; and direct memory references.
2447 ;; (assuming that any given constant is pushed only once, but this ought to be
2448 ;; handled elsewhere).
2450 (define_insn "*pushxf_nointeger"
2451 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2452 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2453 "!TARGET_64BIT && optimize_size"
2455 switch (which_alternative)
2458 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2459 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2460 operands[2] = stack_pointer_rtx;
2461 operands[3] = GEN_INT (12);
2462 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2463 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2465 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2475 [(set_attr "type" "multi")
2476 (set_attr "mode" "XF,SI,SI")])
2478 (define_insn "*pushtf_nointeger"
2479 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2480 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2483 switch (which_alternative)
2486 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2487 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2488 operands[2] = stack_pointer_rtx;
2489 operands[3] = GEN_INT (16);
2490 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2491 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2493 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2503 [(set_attr "type" "multi")
2504 (set_attr "mode" "XF,SI,SI")])
2506 (define_insn "*pushxf_integer"
2507 [(set (match_operand:XF 0 "push_operand" "=<,<")
2508 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2509 "!TARGET_64BIT && !optimize_size"
2511 switch (which_alternative)
2514 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2515 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2516 operands[2] = stack_pointer_rtx;
2517 operands[3] = GEN_INT (12);
2518 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2519 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2521 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2530 [(set_attr "type" "multi")
2531 (set_attr "mode" "XF,SI")])
2533 (define_insn "*pushtf_integer"
2534 [(set (match_operand:TF 0 "push_operand" "=<,<")
2535 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2538 switch (which_alternative)
2541 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2542 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2543 operands[2] = stack_pointer_rtx;
2544 operands[3] = GEN_INT (16);
2546 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2547 return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2549 return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2551 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2552 return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0";
2554 return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0";
2563 [(set_attr "type" "multi")
2564 (set_attr "mode" "XF,SI")])
2567 [(set (match_operand 0 "push_operand" "")
2568 (match_operand 1 "general_operand" ""))]
2570 && (GET_MODE (operands[0]) == XFmode
2571 || GET_MODE (operands[0]) == TFmode
2572 || GET_MODE (operands[0]) == DFmode)
2573 && !ANY_FP_REG_P (operands[1])"
2575 "ix86_split_long_move (operands); DONE;")
2578 [(set (match_operand:XF 0 "push_operand" "")
2579 (match_operand:XF 1 "any_fp_register_operand" ""))]
2581 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2582 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2585 [(set (match_operand:TF 0 "push_operand" "")
2586 (match_operand:TF 1 "any_fp_register_operand" ""))]
2588 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2589 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2592 [(set (match_operand:TF 0 "push_operand" "")
2593 (match_operand:TF 1 "any_fp_register_operand" ""))]
2595 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2596 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2598 ;; Do not use integer registers when optimizing for size
2599 (define_insn "*movxf_nointeger"
2600 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2601 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2604 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2605 && (reload_in_progress || reload_completed
2606 || GET_CODE (operands[1]) != CONST_DOUBLE
2607 || memory_operand (operands[0], XFmode))"
2609 switch (which_alternative)
2612 if (REG_P (operands[1])
2613 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2615 else if (STACK_TOP_P (operands[0]))
2616 return "fld%z1\t%y1";
2621 /* There is no non-popping store to memory for XFmode. So if
2622 we need one, follow the store with a load. */
2623 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2624 return "fstp%z0\t%y0\;fld%z0\t%y0";
2626 return "fstp%z0\t%y0";
2629 switch (standard_80387_constant_p (operands[1]))
2643 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2644 (set_attr "mode" "XF,XF,XF,SI,SI")])
2646 (define_insn "*movtf_nointeger"
2647 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2648 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2649 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2651 && (reload_in_progress || reload_completed
2652 || GET_CODE (operands[1]) != CONST_DOUBLE
2653 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2654 || memory_operand (operands[0], TFmode))"
2656 switch (which_alternative)
2659 if (REG_P (operands[1])
2660 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2662 else if (STACK_TOP_P (operands[0]))
2663 return "fld%z1\t%y1";
2668 /* There is no non-popping store to memory for XFmode. So if
2669 we need one, follow the store with a load. */
2670 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2671 return "fstp%z0\t%y0\;fld%z0\t%y0";
2673 return "fstp%z0\t%y0";
2676 switch (standard_80387_constant_p (operands[1]))
2690 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2691 (set_attr "mode" "XF,XF,XF,SI,SI")])
2693 (define_insn "*movxf_integer"
2694 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2695 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2698 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2699 && (reload_in_progress || reload_completed
2700 || GET_CODE (operands[1]) != CONST_DOUBLE
2701 || memory_operand (operands[0], XFmode))"
2703 switch (which_alternative)
2706 if (REG_P (operands[1])
2707 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2709 else if (STACK_TOP_P (operands[0]))
2710 return "fld%z1\t%y1";
2715 /* There is no non-popping store to memory for XFmode. So if
2716 we need one, follow the store with a load. */
2717 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2718 return "fstp%z0\t%y0\;fld%z0\t%y0";
2720 return "fstp%z0\t%y0";
2723 switch (standard_80387_constant_p (operands[1]))
2737 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2738 (set_attr "mode" "XF,XF,XF,SI,SI")])
2740 (define_insn "*movtf_integer"
2741 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2742 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2743 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2745 && (reload_in_progress || reload_completed
2746 || GET_CODE (operands[1]) != CONST_DOUBLE
2747 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2748 || memory_operand (operands[0], TFmode))"
2750 switch (which_alternative)
2753 if (REG_P (operands[1])
2754 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2756 else if (STACK_TOP_P (operands[0]))
2757 return "fld%z1\t%y1";
2762 /* There is no non-popping store to memory for XFmode. So if
2763 we need one, follow the store with a load. */
2764 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2765 return "fstp%z0\t%y0\;fld%z0\t%y0";
2767 return "fstp%z0\t%y0";
2770 switch (standard_80387_constant_p (operands[1]))
2784 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2785 (set_attr "mode" "XF,XF,XF,SI,SI")])
2788 [(set (match_operand 0 "nonimmediate_operand" "")
2789 (match_operand 1 "general_operand" ""))]
2791 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2792 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
2793 && ! (ANY_FP_REG_P (operands[0]) ||
2794 (GET_CODE (operands[0]) == SUBREG
2795 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2796 && ! (ANY_FP_REG_P (operands[1]) ||
2797 (GET_CODE (operands[1]) == SUBREG
2798 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2800 "ix86_split_long_move (operands); DONE;")
2803 [(set (match_operand 0 "register_operand" "")
2804 (match_operand 1 "memory_operand" ""))]
2806 && GET_CODE (operands[1]) == MEM
2807 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
2808 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2809 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2810 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
2811 && (!(SSE_REG_P (operands[0]) ||
2812 (GET_CODE (operands[0]) == SUBREG
2813 && SSE_REG_P (SUBREG_REG (operands[0]))))
2814 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
2815 && (!(FP_REG_P (operands[0]) ||
2816 (GET_CODE (operands[0]) == SUBREG
2817 && FP_REG_P (SUBREG_REG (operands[0]))))
2818 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
2821 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2823 (define_insn "swapxf"
2824 [(set (match_operand:XF 0 "register_operand" "+f")
2825 (match_operand:XF 1 "register_operand" "+f"))
2830 if (STACK_TOP_P (operands[0]))
2835 [(set_attr "type" "fxch")
2836 (set_attr "mode" "XF")])
2838 (define_insn "swaptf"
2839 [(set (match_operand:TF 0 "register_operand" "+f")
2840 (match_operand:TF 1 "register_operand" "+f"))
2845 if (STACK_TOP_P (operands[0]))
2850 [(set_attr "type" "fxch")
2851 (set_attr "mode" "XF")])
2853 ;; Zero extension instructions
2855 (define_expand "zero_extendhisi2"
2856 [(set (match_operand:SI 0 "register_operand" "")
2857 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2860 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2862 operands[1] = force_reg (HImode, operands[1]);
2863 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2868 (define_insn "zero_extendhisi2_and"
2869 [(set (match_operand:SI 0 "register_operand" "=r")
2870 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2871 (clobber (reg:CC 17))]
2872 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2874 [(set_attr "type" "alu1")
2875 (set_attr "mode" "SI")])
2878 [(set (match_operand:SI 0 "register_operand" "")
2879 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2880 (clobber (reg:CC 17))]
2881 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2882 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2883 (clobber (reg:CC 17))])]
2886 (define_insn "*zero_extendhisi2_movzwl"
2887 [(set (match_operand:SI 0 "register_operand" "=r")
2888 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2889 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2890 "movz{wl|x}\t{%1, %0|%0, %1}"
2891 [(set_attr "type" "imovx")
2892 (set_attr "mode" "SI")])
2894 (define_expand "zero_extendqihi2"
2896 [(set (match_operand:HI 0 "register_operand" "")
2897 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2898 (clobber (reg:CC 17))])]
2902 (define_insn "*zero_extendqihi2_and"
2903 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2904 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2905 (clobber (reg:CC 17))]
2906 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2908 [(set_attr "type" "alu1")
2909 (set_attr "mode" "HI")])
2911 (define_insn "*zero_extendqihi2_movzbw_and"
2912 [(set (match_operand:HI 0 "register_operand" "=r,r")
2913 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2914 (clobber (reg:CC 17))]
2915 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2917 [(set_attr "type" "imovx,alu1")
2918 (set_attr "mode" "HI")])
2920 (define_insn "*zero_extendqihi2_movzbw"
2921 [(set (match_operand:HI 0 "register_operand" "=r")
2922 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2923 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2924 "movz{bw|x}\t{%1, %0|%0, %1}"
2925 [(set_attr "type" "imovx")
2926 (set_attr "mode" "HI")])
2928 ;; For the movzbw case strip only the clobber
2930 [(set (match_operand:HI 0 "register_operand" "")
2931 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2932 (clobber (reg:CC 17))]
2934 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2935 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
2936 [(set (match_operand:HI 0 "register_operand" "")
2937 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
2939 ;; When source and destination does not overlap, clear destination
2940 ;; first and then do the movb
2942 [(set (match_operand:HI 0 "register_operand" "")
2943 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2944 (clobber (reg:CC 17))]
2946 && ANY_QI_REG_P (operands[0])
2947 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2948 && !reg_overlap_mentioned_p (operands[0], operands[1])"
2949 [(set (match_dup 0) (const_int 0))
2950 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2951 "operands[2] = gen_lowpart (QImode, operands[0]);")
2953 ;; Rest is handled by single and.
2955 [(set (match_operand:HI 0 "register_operand" "")
2956 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
2957 (clobber (reg:CC 17))]
2959 && true_regnum (operands[0]) == true_regnum (operands[1])"
2960 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
2961 (clobber (reg:CC 17))])]
2964 (define_expand "zero_extendqisi2"
2966 [(set (match_operand:SI 0 "register_operand" "")
2967 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
2968 (clobber (reg:CC 17))])]
2972 (define_insn "*zero_extendqisi2_and"
2973 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
2974 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2975 (clobber (reg:CC 17))]
2976 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2978 [(set_attr "type" "alu1")
2979 (set_attr "mode" "SI")])
2981 (define_insn "*zero_extendqisi2_movzbw_and"
2982 [(set (match_operand:SI 0 "register_operand" "=r,r")
2983 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2984 (clobber (reg:CC 17))]
2985 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2987 [(set_attr "type" "imovx,alu1")
2988 (set_attr "mode" "SI")])
2990 (define_insn "*zero_extendqisi2_movzbw"
2991 [(set (match_operand:SI 0 "register_operand" "=r")
2992 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2993 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2994 "movz{bl|x}\t{%1, %0|%0, %1}"
2995 [(set_attr "type" "imovx")
2996 (set_attr "mode" "SI")])
2998 ;; For the movzbl case strip only the clobber
3000 [(set (match_operand:SI 0 "register_operand" "")
3001 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3002 (clobber (reg:CC 17))]
3004 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3005 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3007 (zero_extend:SI (match_dup 1)))])
3009 ;; When source and destination does not overlap, clear destination
3010 ;; first and then do the movb
3012 [(set (match_operand:SI 0 "register_operand" "")
3013 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3014 (clobber (reg:CC 17))]
3016 && ANY_QI_REG_P (operands[0])
3017 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3018 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3019 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3020 [(set (match_dup 0) (const_int 0))
3021 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3022 "operands[2] = gen_lowpart (QImode, operands[0]);")
3024 ;; Rest is handled by single and.
3026 [(set (match_operand:SI 0 "register_operand" "")
3027 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3028 (clobber (reg:CC 17))]
3030 && true_regnum (operands[0]) == true_regnum (operands[1])"
3031 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3032 (clobber (reg:CC 17))])]
3035 ;; %%% Kill me once multi-word ops are sane.
3036 (define_expand "zero_extendsidi2"
3037 [(set (match_operand:DI 0 "register_operand" "=r")
3038 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3042 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3047 (define_insn "zero_extendsidi2_32"
3048 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3049 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3050 (clobber (reg:CC 17))]
3053 [(set_attr "mode" "SI")])
3055 (define_insn "zero_extendsidi2_rex64"
3056 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3057 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3060 mov\t{%k1, %k0|%k0, %k1}
3062 [(set_attr "type" "imovx,imov")
3063 (set_attr "mode" "SI,DI")])
3066 [(set (match_operand:DI 0 "memory_operand" "")
3067 (zero_extend:DI (match_dup 0)))]
3069 [(set (match_dup 4) (const_int 0))]
3070 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3073 [(set (match_operand:DI 0 "register_operand" "")
3074 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3075 (clobber (reg:CC 17))]
3076 "!TARGET_64BIT && reload_completed
3077 && true_regnum (operands[0]) == true_regnum (operands[1])"
3078 [(set (match_dup 4) (const_int 0))]
3079 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3082 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3083 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3084 (clobber (reg:CC 17))]
3085 "!TARGET_64BIT && reload_completed"
3086 [(set (match_dup 3) (match_dup 1))
3087 (set (match_dup 4) (const_int 0))]
3088 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3090 (define_insn "zero_extendhidi2"
3091 [(set (match_operand:DI 0 "register_operand" "=r,r")
3092 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3095 movz{wl|x}\t{%1, %k0|%k0, %1}
3096 movz{wq|x}\t{%1, %0|%0, %1}"
3097 [(set_attr "type" "imovx")
3098 (set_attr "mode" "SI,DI")])
3100 (define_insn "zero_extendqidi2"
3101 [(set (match_operand:DI 0 "register_operand" "=r,r")
3102 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3105 movz{bl|x}\t{%1, %k0|%k0, %1}
3106 movz{bq|x}\t{%1, %0|%0, %1}"
3107 [(set_attr "type" "imovx")
3108 (set_attr "mode" "SI,DI")])
3110 ;; Sign extension instructions
3112 (define_expand "extendsidi2"
3113 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3114 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3115 (clobber (reg:CC 17))
3116 (clobber (match_scratch:SI 2 ""))])]
3121 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3126 (define_insn "*extendsidi2_1"
3127 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3128 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3129 (clobber (reg:CC 17))
3130 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3134 (define_insn "extendsidi2_rex64"
3135 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3136 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3140 movs{lq|x}\t{%1,%0|%0, %1}"
3141 [(set_attr "type" "imovx")
3142 (set_attr "mode" "DI")
3143 (set_attr "prefix_0f" "0")
3144 (set_attr "modrm" "0,1")])
3146 (define_insn "extendhidi2"
3147 [(set (match_operand:DI 0 "register_operand" "=r")
3148 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3150 "movs{wq|x}\t{%1,%0|%0, %1}"
3151 [(set_attr "type" "imovx")
3152 (set_attr "mode" "DI")])
3154 (define_insn "extendqidi2"
3155 [(set (match_operand:DI 0 "register_operand" "=r")
3156 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3158 "movs{bq|x}\t{%1,%0|%0, %1}"
3159 [(set_attr "type" "imovx")
3160 (set_attr "mode" "DI")])
3162 ;; Extend to memory case when source register does die.
3164 [(set (match_operand:DI 0 "memory_operand" "")
3165 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3166 (clobber (reg:CC 17))
3167 (clobber (match_operand:SI 2 "register_operand" ""))]
3169 && dead_or_set_p (insn, operands[1])
3170 && !reg_mentioned_p (operands[1], operands[0]))"
3171 [(set (match_dup 3) (match_dup 1))
3172 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3173 (clobber (reg:CC 17))])
3174 (set (match_dup 4) (match_dup 1))]
3175 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3177 ;; Extend to memory case when source register does not die.
3179 [(set (match_operand:DI 0 "memory_operand" "")
3180 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3181 (clobber (reg:CC 17))
3182 (clobber (match_operand:SI 2 "register_operand" ""))]
3186 split_di (&operands[0], 1, &operands[3], &operands[4]);
3188 emit_move_insn (operands[3], operands[1]);
3190 /* Generate a cltd if possible and doing so it profitable. */
3191 if (true_regnum (operands[1]) == 0
3192 && true_regnum (operands[2]) == 1
3193 && (optimize_size || TARGET_USE_CLTD))
3195 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3199 emit_move_insn (operands[2], operands[1]);
3200 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3202 emit_move_insn (operands[4], operands[2]);
3206 ;; Extend to register case. Optimize case where source and destination
3207 ;; registers match and cases where we can use cltd.
3209 [(set (match_operand:DI 0 "register_operand" "")
3210 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3211 (clobber (reg:CC 17))
3212 (clobber (match_scratch:SI 2 ""))]
3216 split_di (&operands[0], 1, &operands[3], &operands[4]);
3218 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3219 emit_move_insn (operands[3], operands[1]);
3221 /* Generate a cltd if possible and doing so it profitable. */
3222 if (true_regnum (operands[3]) == 0
3223 && (optimize_size || TARGET_USE_CLTD))
3225 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3229 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3230 emit_move_insn (operands[4], operands[1]);
3232 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3236 (define_insn "extendhisi2"
3237 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3238 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3241 switch (get_attr_prefix_0f (insn))
3244 return "{cwtl|cwde}";
3246 return "movs{wl|x}\t{%1,%0|%0, %1}";
3249 [(set_attr "type" "imovx")
3250 (set_attr "mode" "SI")
3251 (set (attr "prefix_0f")
3252 ;; movsx is short decodable while cwtl is vector decoded.
3253 (if_then_else (and (eq_attr "cpu" "!k6")
3254 (eq_attr "alternative" "0"))
3256 (const_string "1")))
3258 (if_then_else (eq_attr "prefix_0f" "0")
3260 (const_string "1")))])
3262 (define_insn "*extendhisi2_zext"
3263 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3265 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3268 switch (get_attr_prefix_0f (insn))
3271 return "{cwtl|cwde}";
3273 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3276 [(set_attr "type" "imovx")
3277 (set_attr "mode" "SI")
3278 (set (attr "prefix_0f")
3279 ;; movsx is short decodable while cwtl is vector decoded.
3280 (if_then_else (and (eq_attr "cpu" "!k6")
3281 (eq_attr "alternative" "0"))
3283 (const_string "1")))
3285 (if_then_else (eq_attr "prefix_0f" "0")
3287 (const_string "1")))])
3289 (define_insn "extendqihi2"
3290 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3291 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3294 switch (get_attr_prefix_0f (insn))
3297 return "{cbtw|cbw}";
3299 return "movs{bw|x}\t{%1,%0|%0, %1}";
3302 [(set_attr "type" "imovx")
3303 (set_attr "mode" "HI")
3304 (set (attr "prefix_0f")
3305 ;; movsx is short decodable while cwtl is vector decoded.
3306 (if_then_else (and (eq_attr "cpu" "!k6")
3307 (eq_attr "alternative" "0"))
3309 (const_string "1")))
3311 (if_then_else (eq_attr "prefix_0f" "0")
3313 (const_string "1")))])
3315 (define_insn "extendqisi2"
3316 [(set (match_operand:SI 0 "register_operand" "=r")
3317 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3319 "movs{bl|x}\t{%1,%0|%0, %1}"
3320 [(set_attr "type" "imovx")
3321 (set_attr "mode" "SI")])
3323 (define_insn "*extendqisi2_zext"
3324 [(set (match_operand:DI 0 "register_operand" "=r")
3326 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3328 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3329 [(set_attr "type" "imovx")
3330 (set_attr "mode" "SI")])
3332 ;; Conversions between float and double.
3334 ;; These are all no-ops in the model used for the 80387. So just
3337 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3338 (define_insn "*dummy_extendsfdf2"
3339 [(set (match_operand:DF 0 "push_operand" "=<")
3340 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3345 [(set (match_operand:DF 0 "push_operand" "")
3346 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3348 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3349 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3352 [(set (match_operand:DF 0 "push_operand" "")
3353 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3355 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3356 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3358 (define_insn "*dummy_extendsfxf2"
3359 [(set (match_operand:XF 0 "push_operand" "=<")
3360 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3365 [(set (match_operand:XF 0 "push_operand" "")
3366 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3368 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3369 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3371 (define_insn "*dummy_extendsftf2"
3372 [(set (match_operand:TF 0 "push_operand" "=<")
3373 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3378 [(set (match_operand:TF 0 "push_operand" "")
3379 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3381 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3382 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3385 [(set (match_operand:TF 0 "push_operand" "")
3386 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3388 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3389 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3391 (define_insn "*dummy_extenddfxf2"
3392 [(set (match_operand:XF 0 "push_operand" "=<")
3393 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3398 [(set (match_operand:XF 0 "push_operand" "")
3399 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3401 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3402 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3404 (define_insn "*dummy_extenddftf2"
3405 [(set (match_operand:TF 0 "push_operand" "=<")
3406 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3411 [(set (match_operand:TF 0 "push_operand" "")
3412 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3414 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3415 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3418 [(set (match_operand:TF 0 "push_operand" "")
3419 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3421 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3422 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3424 (define_expand "extendsfdf2"
3425 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3426 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3427 "TARGET_80387 || TARGET_SSE2"
3429 /* ??? Needed for compress_float_constant since all fp constants
3430 are LEGITIMATE_CONSTANT_P. */
3431 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3432 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3433 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3434 operands[1] = force_reg (SFmode, operands[1]);
3437 (define_insn "*extendsfdf2_1"
3438 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3439 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3440 "(TARGET_80387 || TARGET_SSE2)
3441 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3443 switch (which_alternative)
3446 if (REG_P (operands[1])
3447 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3449 else if (STACK_TOP_P (operands[0]))
3450 return "fld%z1\t%y1";
3455 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3456 return "fstp%z0\t%y0";
3459 return "fst%z0\t%y0";
3461 return "cvtss2sd\t{%1, %0|%0, %1}";
3467 [(set_attr "type" "fmov,fmov,ssecvt")
3468 (set_attr "mode" "SF,XF,DF")])
3470 (define_insn "*extendsfdf2_1_sse_only"
3471 [(set (match_operand:DF 0 "register_operand" "=Y")
3472 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3473 "!TARGET_80387 && TARGET_SSE2
3474 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3475 "cvtss2sd\t{%1, %0|%0, %1}"
3476 [(set_attr "type" "ssecvt")
3477 (set_attr "mode" "DF")])
3479 (define_expand "extendsfxf2"
3480 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3481 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3482 "!TARGET_64BIT && TARGET_80387"
3484 /* ??? Needed for compress_float_constant since all fp constants
3485 are LEGITIMATE_CONSTANT_P. */
3486 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3487 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3488 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3489 operands[1] = force_reg (SFmode, operands[1]);
3492 (define_insn "*extendsfxf2_1"
3493 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3494 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3495 "!TARGET_64BIT && TARGET_80387
3496 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3498 switch (which_alternative)
3501 if (REG_P (operands[1])
3502 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3504 else if (STACK_TOP_P (operands[0]))
3505 return "fld%z1\t%y1";
3510 /* There is no non-popping store to memory for XFmode. So if
3511 we need one, follow the store with a load. */
3512 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3513 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3515 return "fstp%z0\t%y0";
3521 [(set_attr "type" "fmov")
3522 (set_attr "mode" "SF,XF")])
3524 (define_expand "extendsftf2"
3525 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3526 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3529 /* ??? Needed for compress_float_constant since all fp constants
3530 are LEGITIMATE_CONSTANT_P. */
3531 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3532 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3533 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3534 operands[1] = force_reg (SFmode, operands[1]);
3537 (define_insn "*extendsftf2_1"
3538 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3539 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3541 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3543 switch (which_alternative)
3546 if (REG_P (operands[1])
3547 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3549 else if (STACK_TOP_P (operands[0]))
3550 return "fld%z1\t%y1";
3555 /* There is no non-popping store to memory for XFmode. So if
3556 we need one, follow the store with a load. */
3557 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3558 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3560 return "fstp%z0\t%y0";
3566 [(set_attr "type" "fmov")
3567 (set_attr "mode" "SF,XF")])
3569 (define_expand "extenddfxf2"
3570 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3571 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3572 "!TARGET_64BIT && TARGET_80387"
3574 /* ??? Needed for compress_float_constant since all fp constants
3575 are LEGITIMATE_CONSTANT_P. */
3576 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3577 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3578 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3579 operands[1] = force_reg (DFmode, operands[1]);
3582 (define_insn "*extenddfxf2_1"
3583 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3584 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3585 "!TARGET_64BIT && TARGET_80387
3586 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3588 switch (which_alternative)
3591 if (REG_P (operands[1])
3592 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3594 else if (STACK_TOP_P (operands[0]))
3595 return "fld%z1\t%y1";
3600 /* There is no non-popping store to memory for XFmode. So if
3601 we need one, follow the store with a load. */
3602 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3603 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3605 return "fstp%z0\t%y0";
3611 [(set_attr "type" "fmov")
3612 (set_attr "mode" "DF,XF")])
3614 (define_expand "extenddftf2"
3615 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3616 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3619 /* ??? Needed for compress_float_constant since all fp constants
3620 are LEGITIMATE_CONSTANT_P. */
3621 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3622 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3623 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3624 operands[1] = force_reg (DFmode, operands[1]);
3627 (define_insn "*extenddftf2_1"
3628 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3629 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3631 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3633 switch (which_alternative)
3636 if (REG_P (operands[1])
3637 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3639 else if (STACK_TOP_P (operands[0]))
3640 return "fld%z1\t%y1";
3645 /* There is no non-popping store to memory for XFmode. So if
3646 we need one, follow the store with a load. */
3647 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3648 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3650 return "fstp%z0\t%y0";
3656 [(set_attr "type" "fmov")
3657 (set_attr "mode" "DF,XF")])
3659 ;; %%% This seems bad bad news.
3660 ;; This cannot output into an f-reg because there is no way to be sure
3661 ;; of truncating in that case. Otherwise this is just like a simple move
3662 ;; insn. So we pretend we can output to a reg in order to get better
3663 ;; register preferencing, but we really use a stack slot.
3665 (define_expand "truncdfsf2"
3666 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3668 (match_operand:DF 1 "register_operand" "")))
3669 (clobber (match_dup 2))])]
3670 "TARGET_80387 || TARGET_SSE2"
3673 operands[2] = assign_386_stack_local (SFmode, 0);
3676 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3681 (define_insn "*truncdfsf2_1"
3682 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3684 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3685 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3686 "TARGET_80387 && !TARGET_SSE2"
3688 switch (which_alternative)
3691 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3692 return "fstp%z0\t%y0";
3694 return "fst%z0\t%y0";
3699 [(set_attr "type" "fmov,multi,multi,multi")
3700 (set_attr "mode" "SF,SF,SF,SF")])
3702 (define_insn "*truncdfsf2_1_sse"
3703 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y")
3705 (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY")))
3706 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3707 "TARGET_80387 && TARGET_SSE2"
3709 switch (which_alternative)
3712 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3713 return "fstp%z0\t%y0";
3715 return "fst%z0\t%y0";
3717 return "cvtsd2ss\t{%1, %0|%0, %1}";
3722 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3723 (set_attr "mode" "SF,SF,SF,SF,DF")])
3725 (define_insn "*truncdfsf2_2"
3726 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
3728 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3729 "TARGET_80387 && TARGET_SSE2
3730 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3732 switch (which_alternative)
3735 return "cvtsd2ss\t{%1, %0|%0, %1}";
3737 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3738 return "fstp%z0\t%y0";
3740 return "fst%z0\t%y0";
3745 [(set_attr "type" "ssecvt,fmov")
3746 (set_attr "mode" "DF,SF")])
3748 (define_insn "truncdfsf2_3"
3749 [(set (match_operand:SF 0 "memory_operand" "=m")
3751 (match_operand:DF 1 "register_operand" "f")))]
3754 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3755 return "fstp%z0\t%y0";
3757 return "fst%z0\t%y0";
3759 [(set_attr "type" "fmov")
3760 (set_attr "mode" "SF")])
3762 (define_insn "truncdfsf2_sse_only"
3763 [(set (match_operand:SF 0 "register_operand" "=Y")
3765 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3766 "!TARGET_80387 && TARGET_SSE2"
3767 "cvtsd2ss\t{%1, %0|%0, %1}"
3768 [(set_attr "type" "ssecvt")
3769 (set_attr "mode" "DF")])
3772 [(set (match_operand:SF 0 "memory_operand" "")
3774 (match_operand:DF 1 "register_operand" "")))
3775 (clobber (match_operand:SF 2 "memory_operand" ""))]
3777 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3781 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3783 (match_operand:DF 1 "nonimmediate_operand" "")))
3784 (clobber (match_operand 2 "" ""))]
3785 "TARGET_80387 && reload_completed
3786 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
3787 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3791 [(set (match_operand:SF 0 "register_operand" "")
3793 (match_operand:DF 1 "fp_register_operand" "")))
3794 (clobber (match_operand:SF 2 "memory_operand" ""))]
3795 "TARGET_80387 && reload_completed"
3796 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3797 (set (match_dup 0) (match_dup 2))]
3800 (define_expand "truncxfsf2"
3801 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3803 (match_operand:XF 1 "register_operand" "")))
3804 (clobber (match_dup 2))])]
3805 "!TARGET_64BIT && TARGET_80387"
3806 "operands[2] = assign_386_stack_local (SFmode, 0);")
3808 (define_insn "*truncxfsf2_1"
3809 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3811 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3812 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3813 "!TARGET_64BIT && TARGET_80387"
3815 switch (which_alternative)
3818 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3819 return "fstp%z0\t%y0";
3821 return "fst%z0\t%y0";
3826 [(set_attr "type" "fmov,multi,multi,multi")
3827 (set_attr "mode" "SF")])
3829 (define_insn "*truncxfsf2_2"
3830 [(set (match_operand:SF 0 "memory_operand" "=m")
3832 (match_operand:XF 1 "register_operand" "f")))]
3833 "!TARGET_64BIT && TARGET_80387"
3835 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3836 return "fstp%z0\t%y0";
3838 return "fst%z0\t%y0";
3840 [(set_attr "type" "fmov")
3841 (set_attr "mode" "SF")])
3844 [(set (match_operand:SF 0 "memory_operand" "")
3846 (match_operand:XF 1 "register_operand" "")))
3847 (clobber (match_operand:SF 2 "memory_operand" ""))]
3849 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3853 [(set (match_operand:SF 0 "register_operand" "")
3855 (match_operand:XF 1 "register_operand" "")))
3856 (clobber (match_operand:SF 2 "memory_operand" ""))]
3857 "TARGET_80387 && reload_completed"
3858 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3859 (set (match_dup 0) (match_dup 2))]
3862 (define_expand "trunctfsf2"
3863 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3865 (match_operand:TF 1 "register_operand" "")))
3866 (clobber (match_dup 2))])]
3868 "operands[2] = assign_386_stack_local (SFmode, 0);")
3870 (define_insn "*trunctfsf2_1"
3871 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3873 (match_operand:TF 1 "register_operand" "f,f,f,f")))
3874 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3877 switch (which_alternative)
3880 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3881 return "fstp%z0\t%y0";
3883 return "fst%z0\t%y0";
3888 [(set_attr "type" "fmov,multi,multi,multi")
3889 (set_attr "mode" "SF")])
3891 (define_insn "*trunctfsf2_2"
3892 [(set (match_operand:SF 0 "memory_operand" "=m")
3894 (match_operand:TF 1 "register_operand" "f")))]
3897 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3898 return "fstp%z0\t%y0";
3900 return "fst%z0\t%y0";
3902 [(set_attr "type" "fmov")
3903 (set_attr "mode" "SF")])
3906 [(set (match_operand:SF 0 "memory_operand" "")
3908 (match_operand:TF 1 "register_operand" "")))
3909 (clobber (match_operand:SF 2 "memory_operand" ""))]
3911 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3915 [(set (match_operand:SF 0 "register_operand" "")
3917 (match_operand:TF 1 "register_operand" "")))
3918 (clobber (match_operand:SF 2 "memory_operand" ""))]
3919 "TARGET_80387 && reload_completed"
3920 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3921 (set (match_dup 0) (match_dup 2))]
3925 (define_expand "truncxfdf2"
3926 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3928 (match_operand:XF 1 "register_operand" "")))
3929 (clobber (match_dup 2))])]
3930 "!TARGET_64BIT && TARGET_80387"
3931 "operands[2] = assign_386_stack_local (DFmode, 0);")
3933 (define_insn "*truncxfdf2_1"
3934 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3936 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3937 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3938 "!TARGET_64BIT && TARGET_80387"
3940 switch (which_alternative)
3943 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3944 return "fstp%z0\t%y0";
3946 return "fst%z0\t%y0";
3952 [(set_attr "type" "fmov,multi,multi,multi")
3953 (set_attr "mode" "DF")])
3955 (define_insn "*truncxfdf2_2"
3956 [(set (match_operand:DF 0 "memory_operand" "=m")
3958 (match_operand:XF 1 "register_operand" "f")))]
3959 "!TARGET_64BIT && TARGET_80387"
3961 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3962 return "fstp%z0\t%y0";
3964 return "fst%z0\t%y0";
3966 [(set_attr "type" "fmov")
3967 (set_attr "mode" "DF")])
3970 [(set (match_operand:DF 0 "memory_operand" "")
3972 (match_operand:XF 1 "register_operand" "")))
3973 (clobber (match_operand:DF 2 "memory_operand" ""))]
3975 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
3979 [(set (match_operand:DF 0 "register_operand" "")
3981 (match_operand:XF 1 "register_operand" "")))
3982 (clobber (match_operand:DF 2 "memory_operand" ""))]
3983 "TARGET_80387 && reload_completed"
3984 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
3985 (set (match_dup 0) (match_dup 2))]
3988 (define_expand "trunctfdf2"
3989 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3991 (match_operand:TF 1 "register_operand" "")))
3992 (clobber (match_dup 2))])]
3994 "operands[2] = assign_386_stack_local (DFmode, 0);")
3996 (define_insn "*trunctfdf2_1"
3997 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3999 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4000 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4003 switch (which_alternative)
4006 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4007 return "fstp%z0\t%y0";
4009 return "fst%z0\t%y0";
4015 [(set_attr "type" "fmov,multi,multi,multi")
4016 (set_attr "mode" "DF")])
4018 (define_insn "*trunctfdf2_2"
4019 [(set (match_operand:DF 0 "memory_operand" "=m")
4021 (match_operand:TF 1 "register_operand" "f")))]
4024 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4025 return "fstp%z0\t%y0";
4027 return "fst%z0\t%y0";
4029 [(set_attr "type" "fmov")
4030 (set_attr "mode" "DF")])
4033 [(set (match_operand:DF 0 "memory_operand" "")
4035 (match_operand:TF 1 "register_operand" "")))
4036 (clobber (match_operand:DF 2 "memory_operand" ""))]
4038 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4042 [(set (match_operand:DF 0 "register_operand" "")
4044 (match_operand:TF 1 "register_operand" "")))
4045 (clobber (match_operand:DF 2 "memory_operand" ""))]
4046 "TARGET_80387 && reload_completed"
4047 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4048 (set (match_dup 0) (match_dup 2))]
4052 ;; %%% Break up all these bad boys.
4054 ;; Signed conversion to DImode.
4056 (define_expand "fix_truncxfdi2"
4057 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4058 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4059 "!TARGET_64BIT && TARGET_80387"
4062 (define_expand "fix_trunctfdi2"
4063 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4064 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4068 (define_expand "fix_truncdfdi2"
4069 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4070 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4071 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4073 if (TARGET_64BIT && TARGET_SSE2)
4075 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4076 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4077 if (out != operands[0])
4078 emit_move_insn (operands[0], out);
4083 (define_expand "fix_truncsfdi2"
4084 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4085 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4086 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4088 if (TARGET_SSE && TARGET_64BIT)
4090 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4091 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4092 if (out != operands[0])
4093 emit_move_insn (operands[0], out);
4098 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4099 ;; of the machinery.
4100 (define_insn_and_split "*fix_truncdi_1"
4101 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4102 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4103 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4104 && !reload_completed && !reload_in_progress
4105 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4110 operands[2] = assign_386_stack_local (HImode, 1);
4111 operands[3] = assign_386_stack_local (HImode, 2);
4112 if (memory_operand (operands[0], VOIDmode))
4113 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4114 operands[2], operands[3]));
4117 operands[4] = assign_386_stack_local (DImode, 0);
4118 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4119 operands[2], operands[3],
4124 [(set_attr "type" "fistp")])
4126 (define_insn "fix_truncdi_nomemory"
4127 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4128 (fix:DI (match_operand 1 "register_operand" "f,f")))
4129 (use (match_operand:HI 2 "memory_operand" "m,m"))
4130 (use (match_operand:HI 3 "memory_operand" "m,m"))
4131 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4132 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4133 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4134 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4136 [(set_attr "type" "fistp")])
4138 (define_insn "fix_truncdi_memory"
4139 [(set (match_operand:DI 0 "memory_operand" "=m")
4140 (fix:DI (match_operand 1 "register_operand" "f")))
4141 (use (match_operand:HI 2 "memory_operand" "m"))
4142 (use (match_operand:HI 3 "memory_operand" "m"))
4143 (clobber (match_scratch:DF 4 "=&1f"))]
4144 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4145 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4146 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4147 [(set_attr "type" "fistp")])
4150 [(set (match_operand:DI 0 "register_operand" "")
4151 (fix:DI (match_operand 1 "register_operand" "")))
4152 (use (match_operand:HI 2 "memory_operand" ""))
4153 (use (match_operand:HI 3 "memory_operand" ""))
4154 (clobber (match_operand:DI 4 "memory_operand" ""))
4155 (clobber (match_scratch 5 ""))]
4157 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4160 (clobber (match_dup 5))])
4161 (set (match_dup 0) (match_dup 4))]
4165 [(set (match_operand:DI 0 "memory_operand" "")
4166 (fix:DI (match_operand 1 "register_operand" "")))
4167 (use (match_operand:HI 2 "memory_operand" ""))
4168 (use (match_operand:HI 3 "memory_operand" ""))
4169 (clobber (match_operand:DI 4 "memory_operand" ""))
4170 (clobber (match_scratch 5 ""))]
4172 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4175 (clobber (match_dup 5))])]
4178 ;; When SSE available, it is always faster to use it!
4179 (define_insn "fix_truncsfdi_sse"
4180 [(set (match_operand:DI 0 "register_operand" "=r")
4181 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4182 "TARGET_64BIT && TARGET_SSE"
4183 "cvttss2si{q}\t{%1, %0|%0, %1}"
4184 [(set_attr "type" "ssecvt")])
4186 (define_insn "fix_truncdfdi_sse"
4187 [(set (match_operand:DI 0 "register_operand" "=r")
4188 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4189 "TARGET_64BIT && TARGET_SSE2"
4190 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4191 [(set_attr "type" "ssecvt")])
4193 ;; Signed conversion to SImode.
4195 (define_expand "fix_truncxfsi2"
4196 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4197 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4198 "!TARGET_64BIT && TARGET_80387"
4201 (define_expand "fix_trunctfsi2"
4202 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4203 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4207 (define_expand "fix_truncdfsi2"
4208 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4209 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4210 "TARGET_80387 || TARGET_SSE2"
4214 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4215 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4216 if (out != operands[0])
4217 emit_move_insn (operands[0], out);
4222 (define_expand "fix_truncsfsi2"
4223 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4224 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4225 "TARGET_80387 || TARGET_SSE"
4229 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4230 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4231 if (out != operands[0])
4232 emit_move_insn (operands[0], out);
4237 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4238 ;; of the machinery.
4239 (define_insn_and_split "*fix_truncsi_1"
4240 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4241 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4242 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4243 && !reload_completed && !reload_in_progress
4244 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4249 operands[2] = assign_386_stack_local (HImode, 1);
4250 operands[3] = assign_386_stack_local (HImode, 2);
4251 if (memory_operand (operands[0], VOIDmode))
4252 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4253 operands[2], operands[3]));
4256 operands[4] = assign_386_stack_local (SImode, 0);
4257 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4258 operands[2], operands[3],
4263 [(set_attr "type" "fistp")])
4265 (define_insn "fix_truncsi_nomemory"
4266 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4267 (fix:SI (match_operand 1 "register_operand" "f,f")))
4268 (use (match_operand:HI 2 "memory_operand" "m,m"))
4269 (use (match_operand:HI 3 "memory_operand" "m,m"))
4270 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4271 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4272 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4274 [(set_attr "type" "fistp")])
4276 (define_insn "fix_truncsi_memory"
4277 [(set (match_operand:SI 0 "memory_operand" "=m")
4278 (fix:SI (match_operand 1 "register_operand" "f")))
4279 (use (match_operand:HI 2 "memory_operand" "m"))
4280 (use (match_operand:HI 3 "memory_operand" "m"))]
4281 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4282 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4283 "* return output_fix_trunc (insn, operands);"
4284 [(set_attr "type" "fistp")])
4286 ;; When SSE available, it is always faster to use it!
4287 (define_insn "fix_truncsfsi_sse"
4288 [(set (match_operand:SI 0 "register_operand" "=r")
4289 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4291 "cvttss2si\t{%1, %0|%0, %1}"
4292 [(set_attr "type" "ssecvt")])
4294 (define_insn "fix_truncdfsi_sse"
4295 [(set (match_operand:SI 0 "register_operand" "=r")
4296 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4298 "cvttsd2si\t{%1, %0|%0, %1}"
4299 [(set_attr "type" "ssecvt")])
4302 [(set (match_operand:SI 0 "register_operand" "")
4303 (fix:SI (match_operand 1 "register_operand" "")))
4304 (use (match_operand:HI 2 "memory_operand" ""))
4305 (use (match_operand:HI 3 "memory_operand" ""))
4306 (clobber (match_operand:SI 4 "memory_operand" ""))]
4308 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4310 (use (match_dup 3))])
4311 (set (match_dup 0) (match_dup 4))]
4315 [(set (match_operand:SI 0 "memory_operand" "")
4316 (fix:SI (match_operand 1 "register_operand" "")))
4317 (use (match_operand:HI 2 "memory_operand" ""))
4318 (use (match_operand:HI 3 "memory_operand" ""))
4319 (clobber (match_operand:SI 4 "memory_operand" ""))]
4321 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4323 (use (match_dup 3))])]
4326 ;; Signed conversion to HImode.
4328 (define_expand "fix_truncxfhi2"
4329 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4330 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4331 "!TARGET_64BIT && TARGET_80387"
4334 (define_expand "fix_trunctfhi2"
4335 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4336 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4340 (define_expand "fix_truncdfhi2"
4341 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4342 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4343 "TARGET_80387 && !TARGET_SSE2"
4346 (define_expand "fix_truncsfhi2"
4347 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4348 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4349 "TARGET_80387 && !TARGET_SSE"
4352 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4353 ;; of the machinery.
4354 (define_insn_and_split "*fix_trunchi_1"
4355 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4356 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4357 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4358 && !reload_completed && !reload_in_progress
4359 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4364 operands[2] = assign_386_stack_local (HImode, 1);
4365 operands[3] = assign_386_stack_local (HImode, 2);
4366 if (memory_operand (operands[0], VOIDmode))
4367 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4368 operands[2], operands[3]));
4371 operands[4] = assign_386_stack_local (HImode, 0);
4372 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4373 operands[2], operands[3],
4378 [(set_attr "type" "fistp")])
4380 (define_insn "fix_trunchi_nomemory"
4381 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4382 (fix:HI (match_operand 1 "register_operand" "f,f")))
4383 (use (match_operand:HI 2 "memory_operand" "m,m"))
4384 (use (match_operand:HI 3 "memory_operand" "m,m"))
4385 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4386 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4387 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4389 [(set_attr "type" "fistp")])
4391 (define_insn "fix_trunchi_memory"
4392 [(set (match_operand:HI 0 "memory_operand" "=m")
4393 (fix:HI (match_operand 1 "register_operand" "f")))
4394 (use (match_operand:HI 2 "memory_operand" "m"))
4395 (use (match_operand:HI 3 "memory_operand" "m"))]
4396 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4397 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4398 "* return output_fix_trunc (insn, operands);"
4399 [(set_attr "type" "fistp")])
4402 [(set (match_operand:HI 0 "memory_operand" "")
4403 (fix:HI (match_operand 1 "register_operand" "")))
4404 (use (match_operand:HI 2 "memory_operand" ""))
4405 (use (match_operand:HI 3 "memory_operand" ""))
4406 (clobber (match_operand:HI 4 "memory_operand" ""))]
4408 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4410 (use (match_dup 3))])]
4414 [(set (match_operand:HI 0 "register_operand" "")
4415 (fix:HI (match_operand 1 "register_operand" "")))
4416 (use (match_operand:HI 2 "memory_operand" ""))
4417 (use (match_operand:HI 3 "memory_operand" ""))
4418 (clobber (match_operand:HI 4 "memory_operand" ""))]
4420 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4423 (clobber (match_dup 4))])
4424 (set (match_dup 0) (match_dup 4))]
4428 (define_insn "x86_fnstcw_1"
4429 [(set (match_operand:HI 0 "memory_operand" "=m")
4430 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4433 [(set_attr "length" "2")
4434 (set_attr "mode" "HI")
4435 (set_attr "unit" "i387")
4436 (set_attr "ppro_uops" "few")])
4438 (define_insn "x86_fldcw_1"
4440 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4443 [(set_attr "length" "2")
4444 (set_attr "mode" "HI")
4445 (set_attr "unit" "i387")
4446 (set_attr "athlon_decode" "vector")
4447 (set_attr "ppro_uops" "few")])
4449 ;; Conversion between fixed point and floating point.
4451 ;; Even though we only accept memory inputs, the backend _really_
4452 ;; wants to be able to do this between registers.
4454 (define_insn "floathisf2"
4455 [(set (match_operand:SF 0 "register_operand" "=f,f")
4456 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4457 "TARGET_80387 && !TARGET_SSE"
4461 [(set_attr "type" "fmov,multi")
4462 (set_attr "mode" "SF")
4463 (set_attr "fp_int_src" "true")])
4465 (define_expand "floatsisf2"
4466 [(set (match_operand:SF 0 "register_operand" "")
4467 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4468 "TARGET_SSE || TARGET_80387"
4471 (define_insn "*floatsisf2_i387"
4472 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4473 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4474 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4478 cvtsi2ss\t{%1, %0|%0, %1}"
4479 [(set_attr "type" "fmov,multi,ssecvt")
4480 (set_attr "mode" "SF")
4481 (set_attr "fp_int_src" "true")])
4483 (define_insn "*floatsisf2_sse"
4484 [(set (match_operand:SF 0 "register_operand" "=x")
4485 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4487 "cvtsi2ss\t{%1, %0|%0, %1}"
4488 [(set_attr "type" "ssecvt")
4489 (set_attr "mode" "SF")
4490 (set_attr "fp_int_src" "true")])
4492 (define_expand "floatdisf2"
4493 [(set (match_operand:SF 0 "register_operand" "")
4494 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4495 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4498 (define_insn "*floatdisf2_i387_only"
4499 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4500 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4501 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4505 [(set_attr "type" "fmov,multi")
4506 (set_attr "mode" "SF")
4507 (set_attr "fp_int_src" "true")])
4509 (define_insn "*floatdisf2_i387"
4510 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4511 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
4512 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4516 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4517 [(set_attr "type" "fmov,multi,ssecvt")
4518 (set_attr "mode" "SF")
4519 (set_attr "fp_int_src" "true")])
4521 (define_insn "*floatdisf2_sse"
4522 [(set (match_operand:SF 0 "register_operand" "=x")
4523 (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
4524 "TARGET_64BIT && TARGET_SSE"
4525 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4526 [(set_attr "type" "ssecvt")
4527 (set_attr "mode" "SF")
4528 (set_attr "fp_int_src" "true")])
4530 (define_insn "floathidf2"
4531 [(set (match_operand:DF 0 "register_operand" "=f,f")
4532 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4533 "TARGET_80387 && !TARGET_SSE2"
4537 [(set_attr "type" "fmov,multi")
4538 (set_attr "mode" "DF")
4539 (set_attr "fp_int_src" "true")])
4541 (define_expand "floatsidf2"
4542 [(set (match_operand:DF 0 "register_operand" "")
4543 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4544 "TARGET_80387 || TARGET_SSE2"
4547 (define_insn "*floatsidf2_i387"
4548 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4549 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4550 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4554 cvtsi2sd\t{%1, %0|%0, %1}"
4555 [(set_attr "type" "fmov,multi,ssecvt")
4556 (set_attr "mode" "DF")
4557 (set_attr "fp_int_src" "true")])
4559 (define_insn "*floatsidf2_sse"
4560 [(set (match_operand:DF 0 "register_operand" "=Y")
4561 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4563 "cvtsi2sd\t{%1, %0|%0, %1}"
4564 [(set_attr "type" "ssecvt")
4565 (set_attr "mode" "DF")
4566 (set_attr "fp_int_src" "true")])
4568 (define_expand "floatdidf2"
4569 [(set (match_operand:DF 0 "register_operand" "")
4570 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4571 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4574 (define_insn "*floatdidf2_i387_only"
4575 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4576 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4577 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4581 [(set_attr "type" "fmov,multi")
4582 (set_attr "mode" "DF")
4583 (set_attr "fp_int_src" "true")])
4585 (define_insn "*floatdidf2_i387"
4586 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4587 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
4588 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4592 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4593 [(set_attr "type" "fmov,multi,ssecvt")
4594 (set_attr "mode" "DF")
4595 (set_attr "fp_int_src" "true")])
4597 (define_insn "*floatdidf2_sse"
4598 [(set (match_operand:DF 0 "register_operand" "=Y")
4599 (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
4601 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4602 [(set_attr "type" "ssecvt")
4603 (set_attr "mode" "DF")
4604 (set_attr "fp_int_src" "true")])
4606 (define_insn "floathixf2"
4607 [(set (match_operand:XF 0 "register_operand" "=f,f")
4608 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4609 "!TARGET_64BIT && TARGET_80387"
4613 [(set_attr "type" "fmov,multi")
4614 (set_attr "mode" "XF")
4615 (set_attr "fp_int_src" "true")])
4617 (define_insn "floathitf2"
4618 [(set (match_operand:TF 0 "register_operand" "=f,f")
4619 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4624 [(set_attr "type" "fmov,multi")
4625 (set_attr "mode" "XF")
4626 (set_attr "fp_int_src" "true")])
4628 (define_insn "floatsixf2"
4629 [(set (match_operand:XF 0 "register_operand" "=f,f")
4630 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4631 "!TARGET_64BIT && TARGET_80387"
4635 [(set_attr "type" "fmov,multi")
4636 (set_attr "mode" "XF")
4637 (set_attr "fp_int_src" "true")])
4639 (define_insn "floatsitf2"
4640 [(set (match_operand:TF 0 "register_operand" "=f,f")
4641 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4646 [(set_attr "type" "fmov,multi")
4647 (set_attr "mode" "XF")
4648 (set_attr "fp_int_src" "true")])
4650 (define_insn "floatdixf2"
4651 [(set (match_operand:XF 0 "register_operand" "=f,f")
4652 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4653 "!TARGET_64BIT && TARGET_80387"
4657 [(set_attr "type" "fmov,multi")
4658 (set_attr "mode" "XF")
4659 (set_attr "fp_int_src" "true")])
4661 (define_insn "floatditf2"
4662 [(set (match_operand:TF 0 "register_operand" "=f,f")
4663 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4668 [(set_attr "type" "fmov,multi")
4669 (set_attr "mode" "XF")
4670 (set_attr "fp_int_src" "true")])
4672 ;; %%% Kill these when reload knows how to do it.
4674 [(set (match_operand 0 "fp_register_operand" "")
4675 (float (match_operand 1 "register_operand" "")))]
4676 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4679 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4680 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4681 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4682 ix86_free_from_memory (GET_MODE (operands[1]));
4688 ;; %%% splits for addsidi3
4689 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4690 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4691 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4693 (define_expand "adddi3"
4694 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4695 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4696 (match_operand:DI 2 "x86_64_general_operand" "")))
4697 (clobber (reg:CC 17))]
4699 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4701 (define_insn "*adddi3_1"
4702 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4703 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4704 (match_operand:DI 2 "general_operand" "roiF,riF")))
4705 (clobber (reg:CC 17))]
4710 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4711 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4712 (match_operand:DI 2 "general_operand" "")))
4713 (clobber (reg:CC 17))]
4714 "!TARGET_64BIT && reload_completed"
4715 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
4717 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4718 (parallel [(set (match_dup 3)
4719 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4722 (clobber (reg:CC 17))])]
4723 "split_di (operands+0, 1, operands+0, operands+3);
4724 split_di (operands+1, 1, operands+1, operands+4);
4725 split_di (operands+2, 1, operands+2, operands+5);")
4727 (define_insn "*adddi3_carry_rex64"
4728 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4729 (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
4730 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4731 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4732 (clobber (reg:CC 17))]
4733 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4734 "adc{q}\t{%2, %0|%0, %2}"
4735 [(set_attr "type" "alu")
4736 (set_attr "pent_pair" "pu")
4737 (set_attr "mode" "DI")
4738 (set_attr "ppro_uops" "few")])
4740 (define_insn "*adddi3_cc_rex64"
4742 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4743 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4745 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4746 (plus:DI (match_dup 1) (match_dup 2)))]
4747 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4748 "add{q}\t{%2, %0|%0, %2}"
4749 [(set_attr "type" "alu")
4750 (set_attr "mode" "DI")])
4752 (define_insn "*addsi3_carry"
4753 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4754 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4755 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
4756 (match_operand:SI 2 "general_operand" "ri,rm")))
4757 (clobber (reg:CC 17))]
4758 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4759 "adc{l}\t{%2, %0|%0, %2}"
4760 [(set_attr "type" "alu")
4761 (set_attr "pent_pair" "pu")
4762 (set_attr "mode" "SI")
4763 (set_attr "ppro_uops" "few")])
4765 (define_insn "*addsi3_carry_zext"
4766 [(set (match_operand:DI 0 "register_operand" "=r")
4768 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4769 (match_operand:SI 1 "nonimmediate_operand" "%0"))
4770 (match_operand:SI 2 "general_operand" "rim"))))
4771 (clobber (reg:CC 17))]
4772 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
4773 "adc{l}\t{%2, %k0|%k0, %2}"
4774 [(set_attr "type" "alu")
4775 (set_attr "pent_pair" "pu")
4776 (set_attr "mode" "SI")
4777 (set_attr "ppro_uops" "few")])
4779 (define_insn "*addsi3_cc"
4781 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
4782 (match_operand:SI 2 "general_operand" "ri,rm")]
4784 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4785 (plus:SI (match_dup 1) (match_dup 2)))]
4786 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4787 "add{l}\t{%2, %0|%0, %2}"
4788 [(set_attr "type" "alu")
4789 (set_attr "mode" "SI")])
4791 (define_insn "addqi3_cc"
4793 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
4794 (match_operand:QI 2 "general_operand" "qi,qm")]
4796 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4797 (plus:QI (match_dup 1) (match_dup 2)))]
4798 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4799 "add{b}\t{%2, %0|%0, %2}"
4800 [(set_attr "type" "alu")
4801 (set_attr "mode" "QI")])
4803 (define_expand "addsi3"
4804 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4805 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4806 (match_operand:SI 2 "general_operand" "")))
4807 (clobber (reg:CC 17))])]
4809 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
4811 (define_insn "*lea_1"
4812 [(set (match_operand:SI 0 "register_operand" "=r")
4813 (match_operand:SI 1 "address_operand" "p"))]
4815 "lea{l}\t{%a1, %0|%0, %a1}"
4816 [(set_attr "type" "lea")
4817 (set_attr "mode" "SI")])
4819 (define_insn "*lea_1_rex64"
4820 [(set (match_operand:SI 0 "register_operand" "=r")
4821 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
4823 "lea{l}\t{%a1, %0|%0, %a1}"
4824 [(set_attr "type" "lea")
4825 (set_attr "mode" "SI")])
4827 (define_insn "*lea_1_zext"
4828 [(set (match_operand:DI 0 "register_operand" "=r")
4829 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
4831 "lea{l}\t{%a1, %k0|%k0, %a1}"
4832 [(set_attr "type" "lea")
4833 (set_attr "mode" "SI")])
4835 (define_insn "*lea_2_rex64"
4836 [(set (match_operand:DI 0 "register_operand" "=r")
4837 (match_operand:DI 1 "address_operand" "p"))]
4839 "lea{q}\t{%a1, %0|%0, %a1}"
4840 [(set_attr "type" "lea")
4841 (set_attr "mode" "DI")])
4843 ;; The lea patterns for non-Pmodes needs to be matched by several
4844 ;; insns converted to real lea by splitters.
4846 (define_insn_and_split "*lea_general_1"
4847 [(set (match_operand 0 "register_operand" "=r")
4848 (plus (plus (match_operand 1 "index_register_operand" "r")
4849 (match_operand 2 "register_operand" "r"))
4850 (match_operand 3 "immediate_operand" "i")))]
4851 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4852 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4853 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4854 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4855 && GET_MODE (operands[0]) == GET_MODE (operands[2])
4856 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4857 || GET_MODE (operands[3]) == VOIDmode)"
4859 "&& reload_completed"
4863 operands[0] = gen_lowpart (SImode, operands[0]);
4864 operands[1] = gen_lowpart (Pmode, operands[1]);
4865 operands[2] = gen_lowpart (Pmode, operands[2]);
4866 operands[3] = gen_lowpart (Pmode, operands[3]);
4867 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
4869 if (Pmode != SImode)
4870 pat = gen_rtx_SUBREG (SImode, pat, 0);
4871 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4874 [(set_attr "type" "lea")
4875 (set_attr "mode" "SI")])
4877 (define_insn_and_split "*lea_general_1_zext"
4878 [(set (match_operand:DI 0 "register_operand" "=r")
4880 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
4881 (match_operand:SI 2 "register_operand" "r"))
4882 (match_operand:SI 3 "immediate_operand" "i"))))]
4885 "&& reload_completed"
4887 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
4889 (match_dup 3)) 0)))]
4891 operands[1] = gen_lowpart (Pmode, operands[1]);
4892 operands[2] = gen_lowpart (Pmode, operands[2]);
4893 operands[3] = gen_lowpart (Pmode, operands[3]);
4895 [(set_attr "type" "lea")
4896 (set_attr "mode" "SI")])
4898 (define_insn_and_split "*lea_general_2"
4899 [(set (match_operand 0 "register_operand" "=r")
4900 (plus (mult (match_operand 1 "index_register_operand" "r")
4901 (match_operand 2 "const248_operand" "i"))
4902 (match_operand 3 "nonmemory_operand" "ri")))]
4903 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4904 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4905 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4906 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4907 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4908 || GET_MODE (operands[3]) == VOIDmode)"
4910 "&& reload_completed"
4914 operands[0] = gen_lowpart (SImode, operands[0]);
4915 operands[1] = gen_lowpart (Pmode, operands[1]);
4916 operands[3] = gen_lowpart (Pmode, operands[3]);
4917 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
4919 if (Pmode != SImode)
4920 pat = gen_rtx_SUBREG (SImode, pat, 0);
4921 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4924 [(set_attr "type" "lea")
4925 (set_attr "mode" "SI")])
4927 (define_insn_and_split "*lea_general_2_zext"
4928 [(set (match_operand:DI 0 "register_operand" "=r")
4930 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
4931 (match_operand:SI 2 "const248_operand" "n"))
4932 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
4935 "&& reload_completed"
4937 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
4939 (match_dup 3)) 0)))]
4941 operands[1] = gen_lowpart (Pmode, operands[1]);
4942 operands[3] = gen_lowpart (Pmode, operands[3]);
4944 [(set_attr "type" "lea")
4945 (set_attr "mode" "SI")])
4947 (define_insn_and_split "*lea_general_3"
4948 [(set (match_operand 0 "register_operand" "=r")
4949 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
4950 (match_operand 2 "const248_operand" "i"))
4951 (match_operand 3 "register_operand" "r"))
4952 (match_operand 4 "immediate_operand" "i")))]
4953 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4954 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4955 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4956 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4957 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
4959 "&& reload_completed"
4963 operands[0] = gen_lowpart (SImode, operands[0]);
4964 operands[1] = gen_lowpart (Pmode, operands[1]);
4965 operands[3] = gen_lowpart (Pmode, operands[3]);
4966 operands[4] = gen_lowpart (Pmode, operands[4]);
4967 pat = gen_rtx_PLUS (Pmode,
4968 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
4972 if (Pmode != SImode)
4973 pat = gen_rtx_SUBREG (SImode, pat, 0);
4974 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4977 [(set_attr "type" "lea")
4978 (set_attr "mode" "SI")])
4980 (define_insn_and_split "*lea_general_3_zext"
4981 [(set (match_operand:DI 0 "register_operand" "=r")
4983 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
4984 (match_operand:SI 2 "const248_operand" "n"))
4985 (match_operand:SI 3 "register_operand" "r"))
4986 (match_operand:SI 4 "immediate_operand" "i"))))]
4989 "&& reload_completed"
4991 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
4994 (match_dup 4)) 0)))]
4996 operands[1] = gen_lowpart (Pmode, operands[1]);
4997 operands[3] = gen_lowpart (Pmode, operands[3]);
4998 operands[4] = gen_lowpart (Pmode, operands[4]);
5000 [(set_attr "type" "lea")
5001 (set_attr "mode" "SI")])
5003 (define_insn "*adddi_1_rex64"
5004 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5005 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5006 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5007 (clobber (reg:CC 17))]
5008 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5010 switch (get_attr_type (insn))
5013 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5014 return "lea{q}\t{%a2, %0|%0, %a2}";
5017 if (! rtx_equal_p (operands[0], operands[1]))
5019 if (operands[2] == const1_rtx)
5020 return "inc{q}\t%0";
5021 else if (operands[2] == constm1_rtx)
5022 return "dec{q}\t%0";
5027 if (! rtx_equal_p (operands[0], operands[1]))
5030 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5031 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5032 if (GET_CODE (operands[2]) == CONST_INT
5033 /* Avoid overflows. */
5034 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5035 && (INTVAL (operands[2]) == 128
5036 || (INTVAL (operands[2]) < 0
5037 && INTVAL (operands[2]) != -128)))
5039 operands[2] = GEN_INT (-INTVAL (operands[2]));
5040 return "sub{q}\t{%2, %0|%0, %2}";
5042 return "add{q}\t{%2, %0|%0, %2}";
5046 (cond [(eq_attr "alternative" "2")
5047 (const_string "lea")
5048 ; Current assemblers are broken and do not allow @GOTOFF in
5049 ; ought but a memory context.
5050 (match_operand:DI 2 "pic_symbolic_operand" "")
5051 (const_string "lea")
5052 (match_operand:DI 2 "incdec_operand" "")
5053 (const_string "incdec")
5055 (const_string "alu")))
5056 (set_attr "mode" "DI")])
5058 ;; Convert lea to the lea pattern to avoid flags dependency.
5060 [(set (match_operand:DI 0 "register_operand" "")
5061 (plus:DI (match_operand:DI 1 "register_operand" "")
5062 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5063 (clobber (reg:CC 17))]
5064 "TARGET_64BIT && reload_completed
5065 && true_regnum (operands[0]) != true_regnum (operands[1])"
5067 (plus:DI (match_dup 1)
5071 (define_insn "*adddi_2_rex64"
5074 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5075 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5077 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5078 (plus:DI (match_dup 1) (match_dup 2)))]
5079 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5080 && ix86_binary_operator_ok (PLUS, DImode, operands)
5081 /* Current assemblers are broken and do not allow @GOTOFF in
5082 ought but a memory context. */
5083 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5085 switch (get_attr_type (insn))
5088 if (! rtx_equal_p (operands[0], operands[1]))
5090 if (operands[2] == const1_rtx)
5091 return "inc{q}\t%0";
5092 else if (operands[2] == constm1_rtx)
5093 return "dec{q}\t%0";
5098 if (! rtx_equal_p (operands[0], operands[1]))
5100 /* ???? We ought to handle there the 32bit case too
5101 - do we need new constrant? */
5102 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5103 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5104 if (GET_CODE (operands[2]) == CONST_INT
5105 /* Avoid overflows. */
5106 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5107 && (INTVAL (operands[2]) == 128
5108 || (INTVAL (operands[2]) < 0
5109 && INTVAL (operands[2]) != -128)))
5111 operands[2] = GEN_INT (-INTVAL (operands[2]));
5112 return "sub{q}\t{%2, %0|%0, %2}";
5114 return "add{q}\t{%2, %0|%0, %2}";
5118 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5119 (const_string "incdec")
5120 (const_string "alu")))
5121 (set_attr "mode" "DI")])
5123 (define_insn "*adddi_3_rex64"
5125 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5126 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5127 (clobber (match_scratch:DI 0 "=r"))]
5129 && ix86_match_ccmode (insn, CCZmode)
5130 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5131 /* Current assemblers are broken and do not allow @GOTOFF in
5132 ought but a memory context. */
5133 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5135 switch (get_attr_type (insn))
5138 if (! rtx_equal_p (operands[0], operands[1]))
5140 if (operands[2] == const1_rtx)
5141 return "inc{q}\t%0";
5142 else if (operands[2] == constm1_rtx)
5143 return "dec{q}\t%0";
5148 if (! rtx_equal_p (operands[0], operands[1]))
5150 /* ???? We ought to handle there the 32bit case too
5151 - do we need new constrant? */
5152 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5153 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5154 if (GET_CODE (operands[2]) == CONST_INT
5155 /* Avoid overflows. */
5156 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5157 && (INTVAL (operands[2]) == 128
5158 || (INTVAL (operands[2]) < 0
5159 && INTVAL (operands[2]) != -128)))
5161 operands[2] = GEN_INT (-INTVAL (operands[2]));
5162 return "sub{q}\t{%2, %0|%0, %2}";
5164 return "add{q}\t{%2, %0|%0, %2}";
5168 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5169 (const_string "incdec")
5170 (const_string "alu")))
5171 (set_attr "mode" "DI")])
5173 ; For comparisons against 1, -1 and 128, we may generate better code
5174 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5175 ; is matched then. We can't accept general immediate, because for
5176 ; case of overflows, the result is messed up.
5177 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5179 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5180 ; only for comparisons not depending on it.
5181 (define_insn "*adddi_4_rex64"
5183 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5184 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5185 (clobber (match_scratch:DI 0 "=rm"))]
5187 && ix86_match_ccmode (insn, CCGCmode)"
5189 switch (get_attr_type (insn))
5192 if (operands[2] == constm1_rtx)
5193 return "inc{q}\t%0";
5194 else if (operands[2] == const1_rtx)
5195 return "dec{q}\t%0";
5200 if (! rtx_equal_p (operands[0], operands[1]))
5202 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5203 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5204 if ((INTVAL (operands[2]) == -128
5205 || (INTVAL (operands[2]) > 0
5206 && INTVAL (operands[2]) != 128))
5207 /* Avoid overflows. */
5208 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5209 return "sub{q}\t{%2, %0|%0, %2}";
5210 operands[2] = GEN_INT (-INTVAL (operands[2]));
5211 return "add{q}\t{%2, %0|%0, %2}";
5215 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5216 (const_string "incdec")
5217 (const_string "alu")))
5218 (set_attr "mode" "DI")])
5220 (define_insn "*adddi_5_rex64"
5223 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5224 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5226 (clobber (match_scratch:DI 0 "=r"))]
5228 && ix86_match_ccmode (insn, CCGOCmode)
5229 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5230 /* Current assemblers are broken and do not allow @GOTOFF in
5231 ought but a memory context. */
5232 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5234 switch (get_attr_type (insn))
5237 if (! rtx_equal_p (operands[0], operands[1]))
5239 if (operands[2] == const1_rtx)
5240 return "inc{q}\t%0";
5241 else if (operands[2] == constm1_rtx)
5242 return "dec{q}\t%0";
5247 if (! rtx_equal_p (operands[0], operands[1]))
5249 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5250 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5251 if (GET_CODE (operands[2]) == CONST_INT
5252 /* Avoid overflows. */
5253 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5254 && (INTVAL (operands[2]) == 128
5255 || (INTVAL (operands[2]) < 0
5256 && INTVAL (operands[2]) != -128)))
5258 operands[2] = GEN_INT (-INTVAL (operands[2]));
5259 return "sub{q}\t{%2, %0|%0, %2}";
5261 return "add{q}\t{%2, %0|%0, %2}";
5265 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5266 (const_string "incdec")
5267 (const_string "alu")))
5268 (set_attr "mode" "DI")])
5271 (define_insn "*addsi_1"
5272 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5273 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5274 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5275 (clobber (reg:CC 17))]
5276 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5278 switch (get_attr_type (insn))
5281 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5282 return "lea{l}\t{%a2, %0|%0, %a2}";
5285 if (! rtx_equal_p (operands[0], operands[1]))
5287 if (operands[2] == const1_rtx)
5288 return "inc{l}\t%0";
5289 else if (operands[2] == constm1_rtx)
5290 return "dec{l}\t%0";
5295 if (! rtx_equal_p (operands[0], operands[1]))
5298 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5299 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5300 if (GET_CODE (operands[2]) == CONST_INT
5301 && (INTVAL (operands[2]) == 128
5302 || (INTVAL (operands[2]) < 0
5303 && INTVAL (operands[2]) != -128)))
5305 operands[2] = GEN_INT (-INTVAL (operands[2]));
5306 return "sub{l}\t{%2, %0|%0, %2}";
5308 return "add{l}\t{%2, %0|%0, %2}";
5312 (cond [(eq_attr "alternative" "2")
5313 (const_string "lea")
5314 ; Current assemblers are broken and do not allow @GOTOFF in
5315 ; ought but a memory context.
5316 (match_operand:SI 2 "pic_symbolic_operand" "")
5317 (const_string "lea")
5318 (match_operand:SI 2 "incdec_operand" "")
5319 (const_string "incdec")
5321 (const_string "alu")))
5322 (set_attr "mode" "SI")])
5324 ;; Convert lea to the lea pattern to avoid flags dependency.
5326 [(set (match_operand 0 "register_operand" "")
5327 (plus (match_operand 1 "register_operand" "")
5328 (match_operand 2 "nonmemory_operand" "")))
5329 (clobber (reg:CC 17))]
5331 && true_regnum (operands[0]) != true_regnum (operands[1])"
5335 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5336 may confuse gen_lowpart. */
5337 if (GET_MODE (operands[0]) != Pmode)
5339 operands[1] = gen_lowpart (Pmode, operands[1]);
5340 operands[2] = gen_lowpart (Pmode, operands[2]);
5342 operands[0] = gen_lowpart (SImode, operands[0]);
5343 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5344 if (Pmode != SImode)
5345 pat = gen_rtx_SUBREG (SImode, pat, 0);
5346 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5350 ;; It may seem that nonimmediate operand is proper one for operand 1.
5351 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5352 ;; we take care in ix86_binary_operator_ok to not allow two memory
5353 ;; operands so proper swapping will be done in reload. This allow
5354 ;; patterns constructed from addsi_1 to match.
5355 (define_insn "addsi_1_zext"
5356 [(set (match_operand:DI 0 "register_operand" "=r,r")
5358 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5359 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5360 (clobber (reg:CC 17))]
5361 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5363 switch (get_attr_type (insn))
5366 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5367 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5370 if (operands[2] == const1_rtx)
5371 return "inc{l}\t%k0";
5372 else if (operands[2] == constm1_rtx)
5373 return "dec{l}\t%k0";
5378 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5379 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5380 if (GET_CODE (operands[2]) == CONST_INT
5381 && (INTVAL (operands[2]) == 128
5382 || (INTVAL (operands[2]) < 0
5383 && INTVAL (operands[2]) != -128)))
5385 operands[2] = GEN_INT (-INTVAL (operands[2]));
5386 return "sub{l}\t{%2, %k0|%k0, %2}";
5388 return "add{l}\t{%2, %k0|%k0, %2}";
5392 (cond [(eq_attr "alternative" "1")
5393 (const_string "lea")
5394 ; Current assemblers are broken and do not allow @GOTOFF in
5395 ; ought but a memory context.
5396 (match_operand:SI 2 "pic_symbolic_operand" "")
5397 (const_string "lea")
5398 (match_operand:SI 2 "incdec_operand" "")
5399 (const_string "incdec")
5401 (const_string "alu")))
5402 (set_attr "mode" "SI")])
5404 ;; Convert lea to the lea pattern to avoid flags dependency.
5406 [(set (match_operand:DI 0 "register_operand" "")
5408 (plus:SI (match_operand:SI 1 "register_operand" "")
5409 (match_operand:SI 2 "nonmemory_operand" ""))))
5410 (clobber (reg:CC 17))]
5412 && true_regnum (operands[0]) != true_regnum (operands[1])"
5414 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5416 operands[1] = gen_lowpart (Pmode, operands[1]);
5417 operands[2] = gen_lowpart (Pmode, operands[2]);
5420 (define_insn "*addsi_2"
5423 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5424 (match_operand:SI 2 "general_operand" "rmni,rni"))
5426 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5427 (plus:SI (match_dup 1) (match_dup 2)))]
5428 "ix86_match_ccmode (insn, CCGOCmode)
5429 && ix86_binary_operator_ok (PLUS, SImode, operands)
5430 /* Current assemblers are broken and do not allow @GOTOFF in
5431 ought but a memory context. */
5432 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5434 switch (get_attr_type (insn))
5437 if (! rtx_equal_p (operands[0], operands[1]))
5439 if (operands[2] == const1_rtx)
5440 return "inc{l}\t%0";
5441 else if (operands[2] == constm1_rtx)
5442 return "dec{l}\t%0";
5447 if (! rtx_equal_p (operands[0], operands[1]))
5449 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5450 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5451 if (GET_CODE (operands[2]) == CONST_INT
5452 && (INTVAL (operands[2]) == 128
5453 || (INTVAL (operands[2]) < 0
5454 && INTVAL (operands[2]) != -128)))
5456 operands[2] = GEN_INT (-INTVAL (operands[2]));
5457 return "sub{l}\t{%2, %0|%0, %2}";
5459 return "add{l}\t{%2, %0|%0, %2}";
5463 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5464 (const_string "incdec")
5465 (const_string "alu")))
5466 (set_attr "mode" "SI")])
5468 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5469 (define_insn "*addsi_2_zext"
5472 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5473 (match_operand:SI 2 "general_operand" "rmni"))
5475 (set (match_operand:DI 0 "register_operand" "=r")
5476 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5477 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5478 && ix86_binary_operator_ok (PLUS, SImode, operands)
5479 /* Current assemblers are broken and do not allow @GOTOFF in
5480 ought but a memory context. */
5481 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5483 switch (get_attr_type (insn))
5486 if (operands[2] == const1_rtx)
5487 return "inc{l}\t%k0";
5488 else if (operands[2] == constm1_rtx)
5489 return "dec{l}\t%k0";
5494 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5495 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5496 if (GET_CODE (operands[2]) == CONST_INT
5497 && (INTVAL (operands[2]) == 128
5498 || (INTVAL (operands[2]) < 0
5499 && INTVAL (operands[2]) != -128)))
5501 operands[2] = GEN_INT (-INTVAL (operands[2]));
5502 return "sub{l}\t{%2, %k0|%k0, %2}";
5504 return "add{l}\t{%2, %k0|%k0, %2}";
5508 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5509 (const_string "incdec")
5510 (const_string "alu")))
5511 (set_attr "mode" "SI")])
5513 (define_insn "*addsi_3"
5515 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5516 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5517 (clobber (match_scratch:SI 0 "=r"))]
5518 "ix86_match_ccmode (insn, CCZmode)
5519 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5520 /* Current assemblers are broken and do not allow @GOTOFF in
5521 ought but a memory context. */
5522 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5524 switch (get_attr_type (insn))
5527 if (! rtx_equal_p (operands[0], operands[1]))
5529 if (operands[2] == const1_rtx)
5530 return "inc{l}\t%0";
5531 else if (operands[2] == constm1_rtx)
5532 return "dec{l}\t%0";
5537 if (! rtx_equal_p (operands[0], operands[1]))
5539 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5540 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5541 if (GET_CODE (operands[2]) == CONST_INT
5542 && (INTVAL (operands[2]) == 128
5543 || (INTVAL (operands[2]) < 0
5544 && INTVAL (operands[2]) != -128)))
5546 operands[2] = GEN_INT (-INTVAL (operands[2]));
5547 return "sub{l}\t{%2, %0|%0, %2}";
5549 return "add{l}\t{%2, %0|%0, %2}";
5553 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5554 (const_string "incdec")
5555 (const_string "alu")))
5556 (set_attr "mode" "SI")])
5558 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5559 (define_insn "*addsi_3_zext"
5561 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5562 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5563 (set (match_operand:DI 0 "register_operand" "=r")
5564 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5565 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5566 && ix86_binary_operator_ok (PLUS, SImode, operands)
5567 /* Current assemblers are broken and do not allow @GOTOFF in
5568 ought but a memory context. */
5569 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5571 switch (get_attr_type (insn))
5574 if (operands[2] == const1_rtx)
5575 return "inc{l}\t%k0";
5576 else if (operands[2] == constm1_rtx)
5577 return "dec{l}\t%k0";
5582 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5583 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5584 if (GET_CODE (operands[2]) == CONST_INT
5585 && (INTVAL (operands[2]) == 128
5586 || (INTVAL (operands[2]) < 0
5587 && INTVAL (operands[2]) != -128)))
5589 operands[2] = GEN_INT (-INTVAL (operands[2]));
5590 return "sub{l}\t{%2, %k0|%k0, %2}";
5592 return "add{l}\t{%2, %k0|%k0, %2}";
5596 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5597 (const_string "incdec")
5598 (const_string "alu")))
5599 (set_attr "mode" "SI")])
5601 ; For comparisons agains 1, -1 and 128, we may generate better code
5602 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5603 ; is matched then. We can't accept general immediate, because for
5604 ; case of overflows, the result is messed up.
5605 ; This pattern also don't hold of 0x80000000, since the value overflows
5607 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5608 ; only for comparisons not depending on it.
5609 (define_insn "*addsi_4"
5611 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5612 (match_operand:SI 2 "const_int_operand" "n")))
5613 (clobber (match_scratch:SI 0 "=rm"))]
5614 "ix86_match_ccmode (insn, CCGCmode)
5615 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5617 switch (get_attr_type (insn))
5620 if (operands[2] == constm1_rtx)
5621 return "inc{l}\t%0";
5622 else if (operands[2] == const1_rtx)
5623 return "dec{l}\t%0";
5628 if (! rtx_equal_p (operands[0], operands[1]))
5630 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5631 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5632 if ((INTVAL (operands[2]) == -128
5633 || (INTVAL (operands[2]) > 0
5634 && INTVAL (operands[2]) != 128)))
5635 return "sub{l}\t{%2, %0|%0, %2}";
5636 operands[2] = GEN_INT (-INTVAL (operands[2]));
5637 return "add{l}\t{%2, %0|%0, %2}";
5641 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5642 (const_string "incdec")
5643 (const_string "alu")))
5644 (set_attr "mode" "SI")])
5646 (define_insn "*addsi_5"
5649 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5650 (match_operand:SI 2 "general_operand" "rmni"))
5652 (clobber (match_scratch:SI 0 "=r"))]
5653 "ix86_match_ccmode (insn, CCGOCmode)
5654 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5655 /* Current assemblers are broken and do not allow @GOTOFF in
5656 ought but a memory context. */
5657 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5659 switch (get_attr_type (insn))
5662 if (! rtx_equal_p (operands[0], operands[1]))
5664 if (operands[2] == const1_rtx)
5665 return "inc{l}\t%0";
5666 else if (operands[2] == constm1_rtx)
5667 return "dec{l}\t%0";
5672 if (! rtx_equal_p (operands[0], operands[1]))
5674 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5675 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5676 if (GET_CODE (operands[2]) == CONST_INT
5677 && (INTVAL (operands[2]) == 128
5678 || (INTVAL (operands[2]) < 0
5679 && INTVAL (operands[2]) != -128)))
5681 operands[2] = GEN_INT (-INTVAL (operands[2]));
5682 return "sub{l}\t{%2, %0|%0, %2}";
5684 return "add{l}\t{%2, %0|%0, %2}";
5688 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5689 (const_string "incdec")
5690 (const_string "alu")))
5691 (set_attr "mode" "SI")])
5693 (define_expand "addhi3"
5694 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5695 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5696 (match_operand:HI 2 "general_operand" "")))
5697 (clobber (reg:CC 17))])]
5698 "TARGET_HIMODE_MATH"
5699 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5701 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5702 ;; type optimizations enabled by define-splits. This is not important
5703 ;; for PII, and in fact harmful because of partial register stalls.
5705 (define_insn "*addhi_1_lea"
5706 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5707 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5708 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
5709 (clobber (reg:CC 17))]
5710 "!TARGET_PARTIAL_REG_STALL
5711 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5713 switch (get_attr_type (insn))
5718 if (operands[2] == const1_rtx)
5719 return "inc{w}\t%0";
5720 else if (operands[2] == constm1_rtx)
5721 return "dec{w}\t%0";
5725 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5726 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5727 if (GET_CODE (operands[2]) == CONST_INT
5728 && (INTVAL (operands[2]) == 128
5729 || (INTVAL (operands[2]) < 0
5730 && INTVAL (operands[2]) != -128)))
5732 operands[2] = GEN_INT (-INTVAL (operands[2]));
5733 return "sub{w}\t{%2, %0|%0, %2}";
5735 return "add{w}\t{%2, %0|%0, %2}";
5739 (if_then_else (eq_attr "alternative" "2")
5740 (const_string "lea")
5741 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5742 (const_string "incdec")
5743 (const_string "alu"))))
5744 (set_attr "mode" "HI,HI,SI")])
5746 (define_insn "*addhi_1"
5747 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5748 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5749 (match_operand:HI 2 "general_operand" "ri,rm")))
5750 (clobber (reg:CC 17))]
5751 "TARGET_PARTIAL_REG_STALL
5752 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5754 switch (get_attr_type (insn))
5757 if (operands[2] == const1_rtx)
5758 return "inc{w}\t%0";
5759 else if (operands[2] == constm1_rtx)
5760 return "dec{w}\t%0";
5764 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5765 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5766 if (GET_CODE (operands[2]) == CONST_INT
5767 && (INTVAL (operands[2]) == 128
5768 || (INTVAL (operands[2]) < 0
5769 && INTVAL (operands[2]) != -128)))
5771 operands[2] = GEN_INT (-INTVAL (operands[2]));
5772 return "sub{w}\t{%2, %0|%0, %2}";
5774 return "add{w}\t{%2, %0|%0, %2}";
5778 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5779 (const_string "incdec")
5780 (const_string "alu")))
5781 (set_attr "mode" "HI")])
5783 (define_insn "*addhi_2"
5786 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5787 (match_operand:HI 2 "general_operand" "rmni,rni"))
5789 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
5790 (plus:HI (match_dup 1) (match_dup 2)))]
5791 "ix86_match_ccmode (insn, CCGOCmode)
5792 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5794 switch (get_attr_type (insn))
5797 if (operands[2] == const1_rtx)
5798 return "inc{w}\t%0";
5799 else if (operands[2] == constm1_rtx)
5800 return "dec{w}\t%0";
5804 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5805 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5806 if (GET_CODE (operands[2]) == CONST_INT
5807 && (INTVAL (operands[2]) == 128
5808 || (INTVAL (operands[2]) < 0
5809 && INTVAL (operands[2]) != -128)))
5811 operands[2] = GEN_INT (-INTVAL (operands[2]));
5812 return "sub{w}\t{%2, %0|%0, %2}";
5814 return "add{w}\t{%2, %0|%0, %2}";
5818 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5819 (const_string "incdec")
5820 (const_string "alu")))
5821 (set_attr "mode" "HI")])
5823 (define_insn "*addhi_3"
5825 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
5826 (match_operand:HI 1 "nonimmediate_operand" "%0")))
5827 (clobber (match_scratch:HI 0 "=r"))]
5828 "ix86_match_ccmode (insn, CCZmode)
5829 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5831 switch (get_attr_type (insn))
5834 if (operands[2] == const1_rtx)
5835 return "inc{w}\t%0";
5836 else if (operands[2] == constm1_rtx)
5837 return "dec{w}\t%0";
5841 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5842 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5843 if (GET_CODE (operands[2]) == CONST_INT
5844 && (INTVAL (operands[2]) == 128
5845 || (INTVAL (operands[2]) < 0
5846 && INTVAL (operands[2]) != -128)))
5848 operands[2] = GEN_INT (-INTVAL (operands[2]));
5849 return "sub{w}\t{%2, %0|%0, %2}";
5851 return "add{w}\t{%2, %0|%0, %2}";
5855 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5856 (const_string "incdec")
5857 (const_string "alu")))
5858 (set_attr "mode" "HI")])
5860 ; See comments above addsi_3_imm for details.
5861 (define_insn "*addhi_4"
5863 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
5864 (match_operand:HI 2 "const_int_operand" "n")))
5865 (clobber (match_scratch:HI 0 "=rm"))]
5866 "ix86_match_ccmode (insn, CCGCmode)
5867 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
5869 switch (get_attr_type (insn))
5872 if (operands[2] == constm1_rtx)
5873 return "inc{w}\t%0";
5874 else if (operands[2] == const1_rtx)
5875 return "dec{w}\t%0";
5880 if (! rtx_equal_p (operands[0], operands[1]))
5882 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5883 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5884 if ((INTVAL (operands[2]) == -128
5885 || (INTVAL (operands[2]) > 0
5886 && INTVAL (operands[2]) != 128)))
5887 return "sub{w}\t{%2, %0|%0, %2}";
5888 operands[2] = GEN_INT (-INTVAL (operands[2]));
5889 return "add{w}\t{%2, %0|%0, %2}";
5893 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5894 (const_string "incdec")
5895 (const_string "alu")))
5896 (set_attr "mode" "SI")])
5899 (define_insn "*addhi_5"
5902 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
5903 (match_operand:HI 2 "general_operand" "rmni"))
5905 (clobber (match_scratch:HI 0 "=r"))]
5906 "ix86_match_ccmode (insn, CCGOCmode)
5907 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5909 switch (get_attr_type (insn))
5912 if (operands[2] == const1_rtx)
5913 return "inc{w}\t%0";
5914 else if (operands[2] == constm1_rtx)
5915 return "dec{w}\t%0";
5919 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5920 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5921 if (GET_CODE (operands[2]) == CONST_INT
5922 && (INTVAL (operands[2]) == 128
5923 || (INTVAL (operands[2]) < 0
5924 && INTVAL (operands[2]) != -128)))
5926 operands[2] = GEN_INT (-INTVAL (operands[2]));
5927 return "sub{w}\t{%2, %0|%0, %2}";
5929 return "add{w}\t{%2, %0|%0, %2}";
5933 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5934 (const_string "incdec")
5935 (const_string "alu")))
5936 (set_attr "mode" "HI")])
5938 (define_expand "addqi3"
5939 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
5940 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
5941 (match_operand:QI 2 "general_operand" "")))
5942 (clobber (reg:CC 17))])]
5943 "TARGET_QIMODE_MATH"
5944 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
5946 ;; %%% Potential partial reg stall on alternative 2. What to do?
5947 (define_insn "*addqi_1_lea"
5948 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
5949 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
5950 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
5951 (clobber (reg:CC 17))]
5952 "!TARGET_PARTIAL_REG_STALL
5953 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5955 int widen = (which_alternative == 2);
5956 switch (get_attr_type (insn))
5961 if (operands[2] == const1_rtx)
5962 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
5963 else if (operands[2] == constm1_rtx)
5964 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
5968 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5969 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5970 if (GET_CODE (operands[2]) == CONST_INT
5971 && (INTVAL (operands[2]) == 128
5972 || (INTVAL (operands[2]) < 0
5973 && INTVAL (operands[2]) != -128)))
5975 operands[2] = GEN_INT (-INTVAL (operands[2]));
5977 return "sub{l}\t{%2, %k0|%k0, %2}";
5979 return "sub{b}\t{%2, %0|%0, %2}";
5982 return "add{l}\t{%k2, %k0|%k0, %k2}";
5984 return "add{b}\t{%2, %0|%0, %2}";
5988 (if_then_else (eq_attr "alternative" "3")
5989 (const_string "lea")
5990 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5991 (const_string "incdec")
5992 (const_string "alu"))))
5993 (set_attr "mode" "QI,QI,SI,SI")])
5995 (define_insn "*addqi_1"
5996 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
5997 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5998 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
5999 (clobber (reg:CC 17))]
6000 "TARGET_PARTIAL_REG_STALL
6001 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6003 int widen = (which_alternative == 2);
6004 switch (get_attr_type (insn))
6007 if (operands[2] == const1_rtx)
6008 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6009 else if (operands[2] == constm1_rtx)
6010 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6014 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6015 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6016 if (GET_CODE (operands[2]) == CONST_INT
6017 && (INTVAL (operands[2]) == 128
6018 || (INTVAL (operands[2]) < 0
6019 && INTVAL (operands[2]) != -128)))
6021 operands[2] = GEN_INT (-INTVAL (operands[2]));
6023 return "sub{l}\t{%2, %k0|%k0, %2}";
6025 return "sub{b}\t{%2, %0|%0, %2}";
6028 return "add{l}\t{%k2, %k0|%k0, %k2}";
6030 return "add{b}\t{%2, %0|%0, %2}";
6034 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6035 (const_string "incdec")
6036 (const_string "alu")))
6037 (set_attr "mode" "QI,QI,SI")])
6039 (define_insn "*addqi_1_slp"
6040 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6041 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6042 (match_operand:QI 2 "general_operand" "qn,qnm")))
6043 (clobber (reg:CC 17))]
6044 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6045 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6047 switch (get_attr_type (insn))
6050 if (operands[2] == const1_rtx)
6051 return "inc{b}\t%0";
6052 else if (operands[2] == constm1_rtx)
6053 return "dec{b}\t%0";
6057 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6058 if (GET_CODE (operands[2]) == CONST_INT
6059 && INTVAL (operands[2]) < 0)
6061 operands[2] = GEN_INT (-INTVAL (operands[2]));
6062 return "sub{b}\t{%2, %0|%0, %2}";
6064 return "add{b}\t{%2, %0|%0, %2}";
6068 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6069 (const_string "incdec")
6070 (const_string "alu")))
6071 (set_attr "mode" "QI")])
6073 (define_insn "*addqi_2"
6076 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6077 (match_operand:QI 2 "general_operand" "qmni,qni"))
6079 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6080 (plus:QI (match_dup 1) (match_dup 2)))]
6081 "ix86_match_ccmode (insn, CCGOCmode)
6082 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6084 switch (get_attr_type (insn))
6087 if (operands[2] == const1_rtx)
6088 return "inc{b}\t%0";
6089 else if (operands[2] == constm1_rtx
6090 || (GET_CODE (operands[2]) == CONST_INT
6091 && INTVAL (operands[2]) == 255))
6092 return "dec{b}\t%0";
6096 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6097 if (GET_CODE (operands[2]) == CONST_INT
6098 && INTVAL (operands[2]) < 0)
6100 operands[2] = GEN_INT (-INTVAL (operands[2]));
6101 return "sub{b}\t{%2, %0|%0, %2}";
6103 return "add{b}\t{%2, %0|%0, %2}";
6107 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6108 (const_string "incdec")
6109 (const_string "alu")))
6110 (set_attr "mode" "QI")])
6112 (define_insn "*addqi_3"
6114 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6115 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6116 (clobber (match_scratch:QI 0 "=q"))]
6117 "ix86_match_ccmode (insn, CCZmode)
6118 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6120 switch (get_attr_type (insn))
6123 if (operands[2] == const1_rtx)
6124 return "inc{b}\t%0";
6125 else if (operands[2] == constm1_rtx
6126 || (GET_CODE (operands[2]) == CONST_INT
6127 && INTVAL (operands[2]) == 255))
6128 return "dec{b}\t%0";
6132 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6133 if (GET_CODE (operands[2]) == CONST_INT
6134 && INTVAL (operands[2]) < 0)
6136 operands[2] = GEN_INT (-INTVAL (operands[2]));
6137 return "sub{b}\t{%2, %0|%0, %2}";
6139 return "add{b}\t{%2, %0|%0, %2}";
6143 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6144 (const_string "incdec")
6145 (const_string "alu")))
6146 (set_attr "mode" "QI")])
6148 ; See comments above addsi_3_imm for details.
6149 (define_insn "*addqi_4"
6151 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6152 (match_operand:QI 2 "const_int_operand" "n")))
6153 (clobber (match_scratch:QI 0 "=qm"))]
6154 "ix86_match_ccmode (insn, CCGCmode)
6155 && (INTVAL (operands[2]) & 0xff) != 0x80"
6157 switch (get_attr_type (insn))
6160 if (operands[2] == constm1_rtx
6161 || (GET_CODE (operands[2]) == CONST_INT
6162 && INTVAL (operands[2]) == 255))
6163 return "inc{b}\t%0";
6164 else if (operands[2] == const1_rtx)
6165 return "dec{b}\t%0";
6170 if (! rtx_equal_p (operands[0], operands[1]))
6172 if (INTVAL (operands[2]) < 0)
6174 operands[2] = GEN_INT (-INTVAL (operands[2]));
6175 return "add{b}\t{%2, %0|%0, %2}";
6177 return "sub{b}\t{%2, %0|%0, %2}";
6181 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6182 (const_string "incdec")
6183 (const_string "alu")))
6184 (set_attr "mode" "QI")])
6187 (define_insn "*addqi_5"
6190 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6191 (match_operand:QI 2 "general_operand" "qmni"))
6193 (clobber (match_scratch:QI 0 "=q"))]
6194 "ix86_match_ccmode (insn, CCGOCmode)
6195 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6197 switch (get_attr_type (insn))
6200 if (operands[2] == const1_rtx)
6201 return "inc{b}\t%0";
6202 else if (operands[2] == constm1_rtx
6203 || (GET_CODE (operands[2]) == CONST_INT
6204 && INTVAL (operands[2]) == 255))
6205 return "dec{b}\t%0";
6209 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6210 if (GET_CODE (operands[2]) == CONST_INT
6211 && INTVAL (operands[2]) < 0)
6213 operands[2] = GEN_INT (-INTVAL (operands[2]));
6214 return "sub{b}\t{%2, %0|%0, %2}";
6216 return "add{b}\t{%2, %0|%0, %2}";
6220 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6221 (const_string "incdec")
6222 (const_string "alu")))
6223 (set_attr "mode" "QI")])
6226 (define_insn "addqi_ext_1"
6227 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6232 (match_operand 1 "ext_register_operand" "0")
6235 (match_operand:QI 2 "general_operand" "Qmn")))
6236 (clobber (reg:CC 17))]
6239 switch (get_attr_type (insn))
6242 if (operands[2] == const1_rtx)
6243 return "inc{b}\t%h0";
6244 else if (operands[2] == constm1_rtx
6245 || (GET_CODE (operands[2]) == CONST_INT
6246 && INTVAL (operands[2]) == 255))
6247 return "dec{b}\t%h0";
6251 return "add{b}\t{%2, %h0|%h0, %2}";
6255 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6256 (const_string "incdec")
6257 (const_string "alu")))
6258 (set_attr "mode" "QI")])
6260 (define_insn "*addqi_ext_1_rex64"
6261 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6266 (match_operand 1 "ext_register_operand" "0")
6269 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6270 (clobber (reg:CC 17))]
6273 switch (get_attr_type (insn))
6276 if (operands[2] == const1_rtx)
6277 return "inc{b}\t%h0";
6278 else if (operands[2] == constm1_rtx
6279 || (GET_CODE (operands[2]) == CONST_INT
6280 && INTVAL (operands[2]) == 255))
6281 return "dec{b}\t%h0";
6285 return "add{b}\t{%2, %h0|%h0, %2}";
6289 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6290 (const_string "incdec")
6291 (const_string "alu")))
6292 (set_attr "mode" "QI")])
6294 (define_insn "*addqi_ext_2"
6295 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6300 (match_operand 1 "ext_register_operand" "%0")
6304 (match_operand 2 "ext_register_operand" "Q")
6307 (clobber (reg:CC 17))]
6309 "add{b}\t{%h2, %h0|%h0, %h2}"
6310 [(set_attr "type" "alu")
6311 (set_attr "mode" "QI")])
6313 ;; The patterns that match these are at the end of this file.
6315 (define_expand "addxf3"
6316 [(set (match_operand:XF 0 "register_operand" "")
6317 (plus:XF (match_operand:XF 1 "register_operand" "")
6318 (match_operand:XF 2 "register_operand" "")))]
6319 "!TARGET_64BIT && TARGET_80387"
6322 (define_expand "addtf3"
6323 [(set (match_operand:TF 0 "register_operand" "")
6324 (plus:TF (match_operand:TF 1 "register_operand" "")
6325 (match_operand:TF 2 "register_operand" "")))]
6329 (define_expand "adddf3"
6330 [(set (match_operand:DF 0 "register_operand" "")
6331 (plus:DF (match_operand:DF 1 "register_operand" "")
6332 (match_operand:DF 2 "nonimmediate_operand" "")))]
6333 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6336 (define_expand "addsf3"
6337 [(set (match_operand:SF 0 "register_operand" "")
6338 (plus:SF (match_operand:SF 1 "register_operand" "")
6339 (match_operand:SF 2 "nonimmediate_operand" "")))]
6340 "TARGET_80387 || TARGET_SSE_MATH"
6343 ;; Subtract instructions
6345 ;; %%% splits for subsidi3
6347 (define_expand "subdi3"
6348 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6349 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6350 (match_operand:DI 2 "x86_64_general_operand" "")))
6351 (clobber (reg:CC 17))])]
6353 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6355 (define_insn "*subdi3_1"
6356 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6357 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6358 (match_operand:DI 2 "general_operand" "roiF,riF")))
6359 (clobber (reg:CC 17))]
6364 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6365 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6366 (match_operand:DI 2 "general_operand" "")))
6367 (clobber (reg:CC 17))]
6368 "!TARGET_64BIT && reload_completed"
6369 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6370 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6371 (parallel [(set (match_dup 3)
6372 (minus:SI (match_dup 4)
6373 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6375 (clobber (reg:CC 17))])]
6376 "split_di (operands+0, 1, operands+0, operands+3);
6377 split_di (operands+1, 1, operands+1, operands+4);
6378 split_di (operands+2, 1, operands+2, operands+5);")
6380 (define_insn "subdi3_carry_rex64"
6381 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6382 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6383 (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
6384 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6385 (clobber (reg:CC 17))]
6386 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6387 "sbb{q}\t{%2, %0|%0, %2}"
6388 [(set_attr "type" "alu")
6389 (set_attr "pent_pair" "pu")
6390 (set_attr "ppro_uops" "few")
6391 (set_attr "mode" "DI")])
6393 (define_insn "*subdi_1_rex64"
6394 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6395 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6396 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6397 (clobber (reg:CC 17))]
6398 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6399 "sub{q}\t{%2, %0|%0, %2}"
6400 [(set_attr "type" "alu")
6401 (set_attr "mode" "DI")])
6403 (define_insn "*subdi_2_rex64"
6406 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6407 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6409 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6410 (minus:DI (match_dup 1) (match_dup 2)))]
6411 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6412 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6413 "sub{q}\t{%2, %0|%0, %2}"
6414 [(set_attr "type" "alu")
6415 (set_attr "mode" "DI")])
6417 (define_insn "*subdi_3_rex63"
6419 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6420 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6421 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6422 (minus:DI (match_dup 1) (match_dup 2)))]
6423 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6424 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6425 "sub{q}\t{%2, %0|%0, %2}"
6426 [(set_attr "type" "alu")
6427 (set_attr "mode" "DI")])
6430 (define_insn "subsi3_carry"
6431 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6432 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6433 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6434 (match_operand:SI 2 "general_operand" "ri,rm"))))
6435 (clobber (reg:CC 17))]
6436 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6437 "sbb{l}\t{%2, %0|%0, %2}"
6438 [(set_attr "type" "alu")
6439 (set_attr "pent_pair" "pu")
6440 (set_attr "ppro_uops" "few")
6441 (set_attr "mode" "SI")])
6443 (define_insn "subsi3_carry_zext"
6444 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6446 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6447 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6448 (match_operand:SI 2 "general_operand" "ri,rm")))))
6449 (clobber (reg:CC 17))]
6450 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6451 "sbb{l}\t{%2, %k0|%k0, %2}"
6452 [(set_attr "type" "alu")
6453 (set_attr "pent_pair" "pu")
6454 (set_attr "ppro_uops" "few")
6455 (set_attr "mode" "SI")])
6457 (define_expand "subsi3"
6458 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6459 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6460 (match_operand:SI 2 "general_operand" "")))
6461 (clobber (reg:CC 17))])]
6463 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6465 (define_insn "*subsi_1"
6466 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6467 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6468 (match_operand:SI 2 "general_operand" "ri,rm")))
6469 (clobber (reg:CC 17))]
6470 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6471 "sub{l}\t{%2, %0|%0, %2}"
6472 [(set_attr "type" "alu")
6473 (set_attr "mode" "SI")])
6475 (define_insn "*subsi_1_zext"
6476 [(set (match_operand:DI 0 "register_operand" "=r")
6478 (minus:SI (match_operand:SI 1 "register_operand" "0")
6479 (match_operand:SI 2 "general_operand" "rim"))))
6480 (clobber (reg:CC 17))]
6481 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6482 "sub{l}\t{%2, %k0|%k0, %2}"
6483 [(set_attr "type" "alu")
6484 (set_attr "mode" "SI")])
6486 (define_insn "*subsi_2"
6489 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6490 (match_operand:SI 2 "general_operand" "ri,rm"))
6492 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6493 (minus:SI (match_dup 1) (match_dup 2)))]
6494 "ix86_match_ccmode (insn, CCGOCmode)
6495 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6496 "sub{l}\t{%2, %0|%0, %2}"
6497 [(set_attr "type" "alu")
6498 (set_attr "mode" "SI")])
6500 (define_insn "*subsi_2_zext"
6503 (minus:SI (match_operand:SI 1 "register_operand" "0")
6504 (match_operand:SI 2 "general_operand" "rim"))
6506 (set (match_operand:DI 0 "register_operand" "=r")
6508 (minus:SI (match_dup 1)
6510 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6511 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6512 "sub{l}\t{%2, %k0|%k0, %2}"
6513 [(set_attr "type" "alu")
6514 (set_attr "mode" "SI")])
6516 (define_insn "*subsi_3"
6518 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6519 (match_operand:SI 2 "general_operand" "ri,rm")))
6520 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6521 (minus:SI (match_dup 1) (match_dup 2)))]
6522 "ix86_match_ccmode (insn, CCmode)
6523 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6524 "sub{l}\t{%2, %0|%0, %2}"
6525 [(set_attr "type" "alu")
6526 (set_attr "mode" "SI")])
6528 (define_insn "*subsi_3_zext"
6530 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6531 (match_operand:SI 2 "general_operand" "rim")))
6532 (set (match_operand:DI 0 "register_operand" "=r")
6534 (minus:SI (match_dup 1)
6536 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6537 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6538 "sub{q}\t{%2, %0|%0, %2}"
6539 [(set_attr "type" "alu")
6540 (set_attr "mode" "DI")])
6542 (define_expand "subhi3"
6543 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6544 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6545 (match_operand:HI 2 "general_operand" "")))
6546 (clobber (reg:CC 17))])]
6547 "TARGET_HIMODE_MATH"
6548 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6550 (define_insn "*subhi_1"
6551 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6552 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6553 (match_operand:HI 2 "general_operand" "ri,rm")))
6554 (clobber (reg:CC 17))]
6555 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6556 "sub{w}\t{%2, %0|%0, %2}"
6557 [(set_attr "type" "alu")
6558 (set_attr "mode" "HI")])
6560 (define_insn "*subhi_2"
6563 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6564 (match_operand:HI 2 "general_operand" "ri,rm"))
6566 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6567 (minus:HI (match_dup 1) (match_dup 2)))]
6568 "ix86_match_ccmode (insn, CCGOCmode)
6569 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6570 "sub{w}\t{%2, %0|%0, %2}"
6571 [(set_attr "type" "alu")
6572 (set_attr "mode" "HI")])
6574 (define_insn "*subhi_3"
6576 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6577 (match_operand:HI 2 "general_operand" "ri,rm")))
6578 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6579 (minus:HI (match_dup 1) (match_dup 2)))]
6580 "ix86_match_ccmode (insn, CCmode)
6581 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6582 "sub{w}\t{%2, %0|%0, %2}"
6583 [(set_attr "type" "alu")
6584 (set_attr "mode" "HI")])
6586 (define_expand "subqi3"
6587 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6588 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6589 (match_operand:QI 2 "general_operand" "")))
6590 (clobber (reg:CC 17))])]
6591 "TARGET_QIMODE_MATH"
6592 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6594 (define_insn "*subqi_1"
6595 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6596 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6597 (match_operand:QI 2 "general_operand" "qn,qmn")))
6598 (clobber (reg:CC 17))]
6599 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6600 "sub{b}\t{%2, %0|%0, %2}"
6601 [(set_attr "type" "alu")
6602 (set_attr "mode" "QI")])
6604 (define_insn "*subqi_1_slp"
6605 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6606 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6607 (match_operand:QI 2 "general_operand" "qn,qmn")))
6608 (clobber (reg:CC 17))]
6609 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6610 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6611 "sub{b}\t{%2, %0|%0, %2}"
6612 [(set_attr "type" "alu")
6613 (set_attr "mode" "QI")])
6615 (define_insn "*subqi_2"
6618 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6619 (match_operand:QI 2 "general_operand" "qi,qm"))
6621 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6622 (minus:HI (match_dup 1) (match_dup 2)))]
6623 "ix86_match_ccmode (insn, CCGOCmode)
6624 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6625 "sub{b}\t{%2, %0|%0, %2}"
6626 [(set_attr "type" "alu")
6627 (set_attr "mode" "QI")])
6629 (define_insn "*subqi_3"
6631 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6632 (match_operand:QI 2 "general_operand" "qi,qm")))
6633 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6634 (minus:HI (match_dup 1) (match_dup 2)))]
6635 "ix86_match_ccmode (insn, CCmode)
6636 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6637 "sub{b}\t{%2, %0|%0, %2}"
6638 [(set_attr "type" "alu")
6639 (set_attr "mode" "QI")])
6641 ;; The patterns that match these are at the end of this file.
6643 (define_expand "subxf3"
6644 [(set (match_operand:XF 0 "register_operand" "")
6645 (minus:XF (match_operand:XF 1 "register_operand" "")
6646 (match_operand:XF 2 "register_operand" "")))]
6647 "!TARGET_64BIT && TARGET_80387"
6650 (define_expand "subtf3"
6651 [(set (match_operand:TF 0 "register_operand" "")
6652 (minus:TF (match_operand:TF 1 "register_operand" "")
6653 (match_operand:TF 2 "register_operand" "")))]
6657 (define_expand "subdf3"
6658 [(set (match_operand:DF 0 "register_operand" "")
6659 (minus:DF (match_operand:DF 1 "register_operand" "")
6660 (match_operand:DF 2 "nonimmediate_operand" "")))]
6661 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6664 (define_expand "subsf3"
6665 [(set (match_operand:SF 0 "register_operand" "")
6666 (minus:SF (match_operand:SF 1 "register_operand" "")
6667 (match_operand:SF 2 "nonimmediate_operand" "")))]
6668 "TARGET_80387 || TARGET_SSE_MATH"
6671 ;; Multiply instructions
6673 (define_expand "muldi3"
6674 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6675 (mult:DI (match_operand:DI 1 "register_operand" "")
6676 (match_operand:DI 2 "x86_64_general_operand" "")))
6677 (clobber (reg:CC 17))])]
6681 (define_insn "*muldi3_1_rex64"
6682 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6683 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
6684 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6685 (clobber (reg:CC 17))]
6687 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6689 imul{q}\t{%2, %1, %0|%0, %1, %2}
6690 imul{q}\t{%2, %1, %0|%0, %1, %2}
6691 imul{q}\t{%2, %0|%0, %2}"
6692 [(set_attr "type" "imul")
6693 (set_attr "prefix_0f" "0,0,1")
6694 (set_attr "mode" "DI")])
6696 (define_expand "mulsi3"
6697 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6698 (mult:SI (match_operand:SI 1 "register_operand" "")
6699 (match_operand:SI 2 "general_operand" "")))
6700 (clobber (reg:CC 17))])]
6704 (define_insn "*mulsi3_1"
6705 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6706 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
6707 (match_operand:SI 2 "general_operand" "K,i,mr")))
6708 (clobber (reg:CC 17))]
6709 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6710 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
6711 ; there are two ways of writing the exact same machine instruction
6712 ; in assembly language. One, for example, is:
6716 ; while the other is:
6718 ; imul $12, %eax, %eax
6720 ; The first is simply short-hand for the latter. But, some assemblers,
6721 ; like the SCO OSR5 COFF assembler, don't handle the first form.
6723 imul{l}\t{%2, %1, %0|%0, %1, %2}
6724 imul{l}\t{%2, %1, %0|%0, %1, %2}
6725 imul{l}\t{%2, %0|%0, %2}"
6726 [(set_attr "type" "imul")
6727 (set_attr "prefix_0f" "0,0,1")
6728 (set_attr "mode" "SI")])
6730 (define_insn "*mulsi3_1_zext"
6731 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6733 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
6734 (match_operand:SI 2 "general_operand" "K,i,mr"))))
6735 (clobber (reg:CC 17))]
6737 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6738 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
6739 ; there are two ways of writing the exact same machine instruction
6740 ; in assembly language. One, for example, is:
6744 ; while the other is:
6746 ; imul $12, %eax, %eax
6748 ; The first is simply short-hand for the latter. But, some assemblers,
6749 ; like the SCO OSR5 COFF assembler, don't handle the first form.
6751 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6752 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6753 imul{l}\t{%2, %k0|%k0, %2}"
6754 [(set_attr "type" "imul")
6755 (set_attr "prefix_0f" "0,0,1")
6756 (set_attr "mode" "SI")])
6758 (define_expand "mulhi3"
6759 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6760 (mult:HI (match_operand:HI 1 "register_operand" "")
6761 (match_operand:HI 2 "general_operand" "")))
6762 (clobber (reg:CC 17))])]
6763 "TARGET_HIMODE_MATH"
6766 (define_insn "*mulhi3_1"
6767 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
6768 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
6769 (match_operand:HI 2 "general_operand" "K,i,mr")))
6770 (clobber (reg:CC 17))]
6771 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6772 ; %%% There was a note about "Assembler has weird restrictions",
6773 ; concerning alternative 1 when op1 == op0. True?
6775 imul{w}\t{%2, %1, %0|%0, %1, %2}
6776 imul{w}\t{%2, %1, %0|%0, %1, %2}
6777 imul{w}\t{%2, %0|%0, %2}"
6778 [(set_attr "type" "imul")
6779 (set_attr "prefix_0f" "0,0,1")
6780 (set_attr "mode" "HI")])
6782 (define_expand "mulqi3"
6783 [(parallel [(set (match_operand:QI 0 "register_operand" "")
6784 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
6785 (match_operand:QI 2 "register_operand" "")))
6786 (clobber (reg:CC 17))])]
6787 "TARGET_QIMODE_MATH"
6790 (define_insn "*mulqi3_1"
6791 [(set (match_operand:QI 0 "register_operand" "=a")
6792 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6793 (match_operand:QI 2 "nonimmediate_operand" "qm")))
6794 (clobber (reg:CC 17))]
6796 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6798 [(set_attr "type" "imul")
6799 (set_attr "length_immediate" "0")
6800 (set_attr "mode" "QI")])
6802 (define_expand "umulqihi3"
6803 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6804 (mult:HI (zero_extend:HI
6805 (match_operand:QI 1 "nonimmediate_operand" ""))
6807 (match_operand:QI 2 "register_operand" ""))))
6808 (clobber (reg:CC 17))])]
6809 "TARGET_QIMODE_MATH"
6812 (define_insn "*umulqihi3_1"
6813 [(set (match_operand:HI 0 "register_operand" "=a")
6814 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
6815 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6816 (clobber (reg:CC 17))]
6818 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6820 [(set_attr "type" "imul")
6821 (set_attr "length_immediate" "0")
6822 (set_attr "mode" "QI")])
6824 (define_expand "mulqihi3"
6825 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6826 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
6827 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
6828 (clobber (reg:CC 17))])]
6829 "TARGET_QIMODE_MATH"
6832 (define_insn "*mulqihi3_insn"
6833 [(set (match_operand:HI 0 "register_operand" "=a")
6834 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
6835 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6836 (clobber (reg:CC 17))]
6838 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6840 [(set_attr "type" "imul")
6841 (set_attr "length_immediate" "0")
6842 (set_attr "mode" "QI")])
6844 (define_expand "umulditi3"
6845 [(parallel [(set (match_operand:TI 0 "register_operand" "")
6846 (mult:TI (zero_extend:TI
6847 (match_operand:DI 1 "nonimmediate_operand" ""))
6849 (match_operand:DI 2 "register_operand" ""))))
6850 (clobber (reg:CC 17))])]
6854 (define_insn "*umulditi3_insn"
6855 [(set (match_operand:TI 0 "register_operand" "=A")
6856 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
6857 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
6858 (clobber (reg:CC 17))]
6860 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6862 [(set_attr "type" "imul")
6863 (set_attr "ppro_uops" "few")
6864 (set_attr "length_immediate" "0")
6865 (set_attr "mode" "DI")])
6867 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
6868 (define_expand "umulsidi3"
6869 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6870 (mult:DI (zero_extend:DI
6871 (match_operand:SI 1 "nonimmediate_operand" ""))
6873 (match_operand:SI 2 "register_operand" ""))))
6874 (clobber (reg:CC 17))])]
6878 (define_insn "*umulsidi3_insn"
6879 [(set (match_operand:DI 0 "register_operand" "=A")
6880 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
6881 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
6882 (clobber (reg:CC 17))]
6884 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6886 [(set_attr "type" "imul")
6887 (set_attr "ppro_uops" "few")
6888 (set_attr "length_immediate" "0")
6889 (set_attr "mode" "SI")])
6891 (define_expand "mulditi3"
6892 [(parallel [(set (match_operand:TI 0 "register_operand" "")
6893 (mult:TI (sign_extend:TI
6894 (match_operand:DI 1 "nonimmediate_operand" ""))
6896 (match_operand:DI 2 "register_operand" ""))))
6897 (clobber (reg:CC 17))])]
6901 (define_insn "*mulditi3_insn"
6902 [(set (match_operand:TI 0 "register_operand" "=A")
6903 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
6904 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
6905 (clobber (reg:CC 17))]
6907 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6909 [(set_attr "type" "imul")
6910 (set_attr "length_immediate" "0")
6911 (set_attr "mode" "DI")])
6913 (define_expand "mulsidi3"
6914 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6915 (mult:DI (sign_extend:DI
6916 (match_operand:SI 1 "nonimmediate_operand" ""))
6918 (match_operand:SI 2 "register_operand" ""))))
6919 (clobber (reg:CC 17))])]
6923 (define_insn "*mulsidi3_insn"
6924 [(set (match_operand:DI 0 "register_operand" "=A")
6925 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
6926 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
6927 (clobber (reg:CC 17))]
6929 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6931 [(set_attr "type" "imul")
6932 (set_attr "length_immediate" "0")
6933 (set_attr "mode" "SI")])
6935 (define_expand "umuldi3_highpart"
6936 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6939 (mult:TI (zero_extend:TI
6940 (match_operand:DI 1 "nonimmediate_operand" ""))
6942 (match_operand:DI 2 "register_operand" "")))
6944 (clobber (match_scratch:DI 3 ""))
6945 (clobber (reg:CC 17))])]
6949 (define_insn "*umuldi3_highpart_rex64"
6950 [(set (match_operand:DI 0 "register_operand" "=d")
6953 (mult:TI (zero_extend:TI
6954 (match_operand:DI 1 "nonimmediate_operand" "%a"))
6956 (match_operand:DI 2 "nonimmediate_operand" "rm")))
6958 (clobber (match_scratch:DI 3 "=1"))
6959 (clobber (reg:CC 17))]
6961 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6963 [(set_attr "type" "imul")
6964 (set_attr "ppro_uops" "few")
6965 (set_attr "length_immediate" "0")
6966 (set_attr "mode" "DI")])
6968 (define_expand "umulsi3_highpart"
6969 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6972 (mult:DI (zero_extend:DI
6973 (match_operand:SI 1 "nonimmediate_operand" ""))
6975 (match_operand:SI 2 "register_operand" "")))
6977 (clobber (match_scratch:SI 3 ""))
6978 (clobber (reg:CC 17))])]
6982 (define_insn "*umulsi3_highpart_insn"
6983 [(set (match_operand:SI 0 "register_operand" "=d")
6986 (mult:DI (zero_extend:DI
6987 (match_operand:SI 1 "nonimmediate_operand" "%a"))
6989 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6991 (clobber (match_scratch:SI 3 "=1"))
6992 (clobber (reg:CC 17))]
6993 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6995 [(set_attr "type" "imul")
6996 (set_attr "ppro_uops" "few")
6997 (set_attr "length_immediate" "0")
6998 (set_attr "mode" "SI")])
7000 (define_insn "*umulsi3_highpart_zext"
7001 [(set (match_operand:DI 0 "register_operand" "=d")
7002 (zero_extend:DI (truncate:SI
7004 (mult:DI (zero_extend:DI
7005 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7007 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7009 (clobber (match_scratch:SI 3 "=1"))
7010 (clobber (reg:CC 17))]
7012 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7014 [(set_attr "type" "imul")
7015 (set_attr "ppro_uops" "few")
7016 (set_attr "length_immediate" "0")
7017 (set_attr "mode" "SI")])
7019 (define_expand "smuldi3_highpart"
7020 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7023 (mult:TI (sign_extend:TI
7024 (match_operand:DI 1 "nonimmediate_operand" ""))
7026 (match_operand:DI 2 "register_operand" "")))
7028 (clobber (match_scratch:DI 3 ""))
7029 (clobber (reg:CC 17))])]
7033 (define_insn "*smuldi3_highpart_rex64"
7034 [(set (match_operand:DI 0 "register_operand" "=d")
7037 (mult:TI (sign_extend:TI
7038 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7040 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7042 (clobber (match_scratch:DI 3 "=1"))
7043 (clobber (reg:CC 17))]
7045 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7047 [(set_attr "type" "imul")
7048 (set_attr "ppro_uops" "few")
7049 (set_attr "mode" "DI")])
7051 (define_expand "smulsi3_highpart"
7052 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7055 (mult:DI (sign_extend:DI
7056 (match_operand:SI 1 "nonimmediate_operand" ""))
7058 (match_operand:SI 2 "register_operand" "")))
7060 (clobber (match_scratch:SI 3 ""))
7061 (clobber (reg:CC 17))])]
7065 (define_insn "*smulsi3_highpart_insn"
7066 [(set (match_operand:SI 0 "register_operand" "=d")
7069 (mult:DI (sign_extend:DI
7070 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7072 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7074 (clobber (match_scratch:SI 3 "=1"))
7075 (clobber (reg:CC 17))]
7076 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7078 [(set_attr "type" "imul")
7079 (set_attr "ppro_uops" "few")
7080 (set_attr "mode" "SI")])
7082 (define_insn "*smulsi3_highpart_zext"
7083 [(set (match_operand:DI 0 "register_operand" "=d")
7084 (zero_extend:DI (truncate:SI
7086 (mult:DI (sign_extend:DI
7087 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7089 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7091 (clobber (match_scratch:SI 3 "=1"))
7092 (clobber (reg:CC 17))]
7094 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7096 [(set_attr "type" "imul")
7097 (set_attr "ppro_uops" "few")
7098 (set_attr "mode" "SI")])
7100 ;; The patterns that match these are at the end of this file.
7102 (define_expand "mulxf3"
7103 [(set (match_operand:XF 0 "register_operand" "")
7104 (mult:XF (match_operand:XF 1 "register_operand" "")
7105 (match_operand:XF 2 "register_operand" "")))]
7106 "!TARGET_64BIT && TARGET_80387"
7109 (define_expand "multf3"
7110 [(set (match_operand:TF 0 "register_operand" "")
7111 (mult:TF (match_operand:TF 1 "register_operand" "")
7112 (match_operand:TF 2 "register_operand" "")))]
7116 (define_expand "muldf3"
7117 [(set (match_operand:DF 0 "register_operand" "")
7118 (mult:DF (match_operand:DF 1 "register_operand" "")
7119 (match_operand:DF 2 "nonimmediate_operand" "")))]
7120 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7123 (define_expand "mulsf3"
7124 [(set (match_operand:SF 0 "register_operand" "")
7125 (mult:SF (match_operand:SF 1 "register_operand" "")
7126 (match_operand:SF 2 "nonimmediate_operand" "")))]
7127 "TARGET_80387 || TARGET_SSE_MATH"
7130 ;; Divide instructions
7132 (define_insn "divqi3"
7133 [(set (match_operand:QI 0 "register_operand" "=a")
7134 (div:QI (match_operand:HI 1 "register_operand" "0")
7135 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7136 (clobber (reg:CC 17))]
7137 "TARGET_QIMODE_MATH"
7139 [(set_attr "type" "idiv")
7140 (set_attr "mode" "QI")
7141 (set_attr "ppro_uops" "few")])
7143 (define_insn "udivqi3"
7144 [(set (match_operand:QI 0 "register_operand" "=a")
7145 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7146 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7147 (clobber (reg:CC 17))]
7148 "TARGET_QIMODE_MATH"
7150 [(set_attr "type" "idiv")
7151 (set_attr "mode" "QI")
7152 (set_attr "ppro_uops" "few")])
7154 ;; The patterns that match these are at the end of this file.
7156 (define_expand "divxf3"
7157 [(set (match_operand:XF 0 "register_operand" "")
7158 (div:XF (match_operand:XF 1 "register_operand" "")
7159 (match_operand:XF 2 "register_operand" "")))]
7160 "!TARGET_64BIT && TARGET_80387"
7163 (define_expand "divtf3"
7164 [(set (match_operand:TF 0 "register_operand" "")
7165 (div:TF (match_operand:TF 1 "register_operand" "")
7166 (match_operand:TF 2 "register_operand" "")))]
7170 (define_expand "divdf3"
7171 [(set (match_operand:DF 0 "register_operand" "")
7172 (div:DF (match_operand:DF 1 "register_operand" "")
7173 (match_operand:DF 2 "nonimmediate_operand" "")))]
7174 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7177 (define_expand "divsf3"
7178 [(set (match_operand:SF 0 "register_operand" "")
7179 (div:SF (match_operand:SF 1 "register_operand" "")
7180 (match_operand:SF 2 "nonimmediate_operand" "")))]
7181 "TARGET_80387 || TARGET_SSE_MATH"
7184 ;; Remainder instructions.
7186 (define_expand "divmoddi4"
7187 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7188 (div:DI (match_operand:DI 1 "register_operand" "")
7189 (match_operand:DI 2 "nonimmediate_operand" "")))
7190 (set (match_operand:DI 3 "register_operand" "")
7191 (mod:DI (match_dup 1) (match_dup 2)))
7192 (clobber (reg:CC 17))])]
7196 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7197 ;; Penalize eax case sligthly because it results in worse scheduling
7199 (define_insn "*divmoddi4_nocltd_rex64"
7200 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7201 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7202 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7203 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7204 (mod:DI (match_dup 2) (match_dup 3)))
7205 (clobber (reg:CC 17))]
7206 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7208 [(set_attr "type" "multi")])
7210 (define_insn "*divmoddi4_cltd_rex64"
7211 [(set (match_operand:DI 0 "register_operand" "=a")
7212 (div:DI (match_operand:DI 2 "register_operand" "a")
7213 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7214 (set (match_operand:DI 1 "register_operand" "=&d")
7215 (mod:DI (match_dup 2) (match_dup 3)))
7216 (clobber (reg:CC 17))]
7217 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7219 [(set_attr "type" "multi")])
7221 (define_insn "*divmoddi_noext_rex64"
7222 [(set (match_operand:DI 0 "register_operand" "=a")
7223 (div:DI (match_operand:DI 1 "register_operand" "0")
7224 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7225 (set (match_operand:DI 3 "register_operand" "=d")
7226 (mod:DI (match_dup 1) (match_dup 2)))
7227 (use (match_operand:DI 4 "register_operand" "3"))
7228 (clobber (reg:CC 17))]
7231 [(set_attr "type" "idiv")
7232 (set_attr "mode" "DI")
7233 (set_attr "ppro_uops" "few")])
7236 [(set (match_operand:DI 0 "register_operand" "")
7237 (div:DI (match_operand:DI 1 "register_operand" "")
7238 (match_operand:DI 2 "nonimmediate_operand" "")))
7239 (set (match_operand:DI 3 "register_operand" "")
7240 (mod:DI (match_dup 1) (match_dup 2)))
7241 (clobber (reg:CC 17))]
7242 "TARGET_64BIT && reload_completed"
7243 [(parallel [(set (match_dup 3)
7244 (ashiftrt:DI (match_dup 4) (const_int 63)))
7245 (clobber (reg:CC 17))])
7246 (parallel [(set (match_dup 0)
7247 (div:DI (reg:DI 0) (match_dup 2)))
7249 (mod:DI (reg:DI 0) (match_dup 2)))
7251 (clobber (reg:CC 17))])]
7253 /* Avoid use of cltd in favor of a mov+shift. */
7254 if (!TARGET_USE_CLTD && !optimize_size)
7256 if (true_regnum (operands[1]))
7257 emit_move_insn (operands[0], operands[1]);
7259 emit_move_insn (operands[3], operands[1]);
7260 operands[4] = operands[3];
7264 if (true_regnum (operands[1]))
7266 operands[4] = operands[1];
7271 (define_expand "divmodsi4"
7272 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7273 (div:SI (match_operand:SI 1 "register_operand" "")
7274 (match_operand:SI 2 "nonimmediate_operand" "")))
7275 (set (match_operand:SI 3 "register_operand" "")
7276 (mod:SI (match_dup 1) (match_dup 2)))
7277 (clobber (reg:CC 17))])]
7281 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7282 ;; Penalize eax case sligthly because it results in worse scheduling
7284 (define_insn "*divmodsi4_nocltd"
7285 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7286 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7287 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7288 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7289 (mod:SI (match_dup 2) (match_dup 3)))
7290 (clobber (reg:CC 17))]
7291 "!optimize_size && !TARGET_USE_CLTD"
7293 [(set_attr "type" "multi")])
7295 (define_insn "*divmodsi4_cltd"
7296 [(set (match_operand:SI 0 "register_operand" "=a")
7297 (div:SI (match_operand:SI 2 "register_operand" "a")
7298 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7299 (set (match_operand:SI 1 "register_operand" "=&d")
7300 (mod:SI (match_dup 2) (match_dup 3)))
7301 (clobber (reg:CC 17))]
7302 "optimize_size || TARGET_USE_CLTD"
7304 [(set_attr "type" "multi")])
7306 (define_insn "*divmodsi_noext"
7307 [(set (match_operand:SI 0 "register_operand" "=a")
7308 (div:SI (match_operand:SI 1 "register_operand" "0")
7309 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7310 (set (match_operand:SI 3 "register_operand" "=d")
7311 (mod:SI (match_dup 1) (match_dup 2)))
7312 (use (match_operand:SI 4 "register_operand" "3"))
7313 (clobber (reg:CC 17))]
7316 [(set_attr "type" "idiv")
7317 (set_attr "mode" "SI")
7318 (set_attr "ppro_uops" "few")])
7321 [(set (match_operand:SI 0 "register_operand" "")
7322 (div:SI (match_operand:SI 1 "register_operand" "")
7323 (match_operand:SI 2 "nonimmediate_operand" "")))
7324 (set (match_operand:SI 3 "register_operand" "")
7325 (mod:SI (match_dup 1) (match_dup 2)))
7326 (clobber (reg:CC 17))]
7328 [(parallel [(set (match_dup 3)
7329 (ashiftrt:SI (match_dup 4) (const_int 31)))
7330 (clobber (reg:CC 17))])
7331 (parallel [(set (match_dup 0)
7332 (div:SI (reg:SI 0) (match_dup 2)))
7334 (mod:SI (reg:SI 0) (match_dup 2)))
7336 (clobber (reg:CC 17))])]
7338 /* Avoid use of cltd in favor of a mov+shift. */
7339 if (!TARGET_USE_CLTD && !optimize_size)
7341 if (true_regnum (operands[1]))
7342 emit_move_insn (operands[0], operands[1]);
7344 emit_move_insn (operands[3], operands[1]);
7345 operands[4] = operands[3];
7349 if (true_regnum (operands[1]))
7351 operands[4] = operands[1];
7355 (define_insn "divmodhi4"
7356 [(set (match_operand:HI 0 "register_operand" "=a")
7357 (div:HI (match_operand:HI 1 "register_operand" "0")
7358 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7359 (set (match_operand:HI 3 "register_operand" "=&d")
7360 (mod:HI (match_dup 1) (match_dup 2)))
7361 (clobber (reg:CC 17))]
7362 "TARGET_HIMODE_MATH"
7364 [(set_attr "type" "multi")
7365 (set_attr "length_immediate" "0")
7366 (set_attr "mode" "SI")])
7368 (define_insn "udivmoddi4"
7369 [(set (match_operand:DI 0 "register_operand" "=a")
7370 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7371 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7372 (set (match_operand:DI 3 "register_operand" "=&d")
7373 (umod:DI (match_dup 1) (match_dup 2)))
7374 (clobber (reg:CC 17))]
7376 "xor{q}\t%3, %3\;div{q}\t%2"
7377 [(set_attr "type" "multi")
7378 (set_attr "length_immediate" "0")
7379 (set_attr "mode" "DI")])
7381 (define_insn "*udivmoddi4_noext"
7382 [(set (match_operand:DI 0 "register_operand" "=a")
7383 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7384 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7385 (set (match_operand:DI 3 "register_operand" "=d")
7386 (umod:DI (match_dup 1) (match_dup 2)))
7388 (clobber (reg:CC 17))]
7391 [(set_attr "type" "idiv")
7392 (set_attr "ppro_uops" "few")
7393 (set_attr "mode" "DI")])
7396 [(set (match_operand:DI 0 "register_operand" "")
7397 (udiv:DI (match_operand:DI 1 "register_operand" "")
7398 (match_operand:DI 2 "nonimmediate_operand" "")))
7399 (set (match_operand:DI 3 "register_operand" "")
7400 (umod:DI (match_dup 1) (match_dup 2)))
7401 (clobber (reg:CC 17))]
7402 "TARGET_64BIT && reload_completed"
7403 [(set (match_dup 3) (const_int 0))
7404 (parallel [(set (match_dup 0)
7405 (udiv:DI (match_dup 1) (match_dup 2)))
7407 (umod:DI (match_dup 1) (match_dup 2)))
7409 (clobber (reg:CC 17))])]
7412 (define_insn "udivmodsi4"
7413 [(set (match_operand:SI 0 "register_operand" "=a")
7414 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7415 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7416 (set (match_operand:SI 3 "register_operand" "=&d")
7417 (umod:SI (match_dup 1) (match_dup 2)))
7418 (clobber (reg:CC 17))]
7420 "xor{l}\t%3, %3\;div{l}\t%2"
7421 [(set_attr "type" "multi")
7422 (set_attr "length_immediate" "0")
7423 (set_attr "mode" "SI")])
7425 (define_insn "*udivmodsi4_noext"
7426 [(set (match_operand:SI 0 "register_operand" "=a")
7427 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7428 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7429 (set (match_operand:SI 3 "register_operand" "=d")
7430 (umod:SI (match_dup 1) (match_dup 2)))
7432 (clobber (reg:CC 17))]
7435 [(set_attr "type" "idiv")
7436 (set_attr "ppro_uops" "few")
7437 (set_attr "mode" "SI")])
7440 [(set (match_operand:SI 0 "register_operand" "")
7441 (udiv:SI (match_operand:SI 1 "register_operand" "")
7442 (match_operand:SI 2 "nonimmediate_operand" "")))
7443 (set (match_operand:SI 3 "register_operand" "")
7444 (umod:SI (match_dup 1) (match_dup 2)))
7445 (clobber (reg:CC 17))]
7447 [(set (match_dup 3) (const_int 0))
7448 (parallel [(set (match_dup 0)
7449 (udiv:SI (match_dup 1) (match_dup 2)))
7451 (umod:SI (match_dup 1) (match_dup 2)))
7453 (clobber (reg:CC 17))])]
7456 (define_expand "udivmodhi4"
7457 [(set (match_dup 4) (const_int 0))
7458 (parallel [(set (match_operand:HI 0 "register_operand" "")
7459 (udiv:HI (match_operand:HI 1 "register_operand" "")
7460 (match_operand:HI 2 "nonimmediate_operand" "")))
7461 (set (match_operand:HI 3 "register_operand" "")
7462 (umod:HI (match_dup 1) (match_dup 2)))
7464 (clobber (reg:CC 17))])]
7465 "TARGET_HIMODE_MATH"
7466 "operands[4] = gen_reg_rtx (HImode);")
7468 (define_insn "*udivmodhi_noext"
7469 [(set (match_operand:HI 0 "register_operand" "=a")
7470 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7471 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7472 (set (match_operand:HI 3 "register_operand" "=d")
7473 (umod:HI (match_dup 1) (match_dup 2)))
7474 (use (match_operand:HI 4 "register_operand" "3"))
7475 (clobber (reg:CC 17))]
7478 [(set_attr "type" "idiv")
7479 (set_attr "mode" "HI")
7480 (set_attr "ppro_uops" "few")])
7482 ;; We can not use div/idiv for double division, because it causes
7483 ;; "division by zero" on the overflow and that's not what we expect
7484 ;; from truncate. Because true (non truncating) double division is
7485 ;; never generated, we can't create this insn anyway.
7488 ; [(set (match_operand:SI 0 "register_operand" "=a")
7490 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7492 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7493 ; (set (match_operand:SI 3 "register_operand" "=d")
7495 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7496 ; (clobber (reg:CC 17))]
7498 ; "div{l}\t{%2, %0|%0, %2}"
7499 ; [(set_attr "type" "idiv")
7500 ; (set_attr "ppro_uops" "few")])
7502 ;;- Logical AND instructions
7504 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7505 ;; Note that this excludes ah.
7507 (define_insn "*testdi_1_rex64"
7510 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm")
7511 (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re"))
7513 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7515 test{l}\t{%k1, %k0|%k0, %k1}
7516 test{l}\t{%k1, %k0|%k0, %k1}
7517 test{q}\t{%1, %0|%0, %1}
7518 test{q}\t{%1, %0|%0, %1}
7519 test{q}\t{%1, %0|%0, %1}"
7520 [(set_attr "type" "test")
7521 (set_attr "modrm" "0,1,0,1,1")
7522 (set_attr "mode" "SI,SI,DI,DI,DI")
7523 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7525 (define_insn "testsi_1"
7528 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
7529 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
7531 "ix86_match_ccmode (insn, CCNOmode)"
7532 "test{l}\t{%1, %0|%0, %1}"
7533 [(set_attr "type" "test")
7534 (set_attr "modrm" "0,1,1")
7535 (set_attr "mode" "SI")
7536 (set_attr "pent_pair" "uv,np,uv")])
7538 (define_expand "testsi_ccno_1"
7541 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7542 (match_operand:SI 1 "nonmemory_operand" ""))
7547 (define_insn "*testhi_1"
7549 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
7550 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
7552 "ix86_match_ccmode (insn, CCNOmode)"
7553 "test{w}\t{%1, %0|%0, %1}"
7554 [(set_attr "type" "test")
7555 (set_attr "modrm" "0,1,1")
7556 (set_attr "mode" "HI")
7557 (set_attr "pent_pair" "uv,np,uv")])
7559 (define_expand "testqi_ccz_1"
7561 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7562 (match_operand:QI 1 "nonmemory_operand" ""))
7567 (define_insn "*testqi_1"
7569 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
7570 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
7572 "ix86_match_ccmode (insn, CCNOmode)"
7574 if (which_alternative == 3)
7576 if (GET_CODE (operands[1]) == CONST_INT
7577 && (INTVAL (operands[1]) & 0xffffff00))
7578 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7579 return "test{l}\t{%1, %k0|%k0, %1}";
7581 return "test{b}\t{%1, %0|%0, %1}";
7583 [(set_attr "type" "test")
7584 (set_attr "modrm" "0,1,1,1")
7585 (set_attr "mode" "QI,QI,QI,SI")
7586 (set_attr "pent_pair" "uv,np,uv,np")])
7588 (define_expand "testqi_ext_ccno_0"
7593 (match_operand 0 "ext_register_operand" "")
7596 (match_operand 1 "const_int_operand" ""))
7601 (define_insn "*testqi_ext_0"
7606 (match_operand 0 "ext_register_operand" "Q")
7609 (match_operand 1 "const_int_operand" "n"))
7611 "ix86_match_ccmode (insn, CCNOmode)"
7612 "test{b}\t{%1, %h0|%h0, %1}"
7613 [(set_attr "type" "test")
7614 (set_attr "mode" "QI")
7615 (set_attr "length_immediate" "1")
7616 (set_attr "pent_pair" "np")])
7618 (define_insn "*testqi_ext_1"
7623 (match_operand 0 "ext_register_operand" "Q")
7627 (match_operand:QI 1 "nonimmediate_operand" "Qm")))
7629 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7630 "test{b}\t{%1, %h0|%h0, %1}"
7631 [(set_attr "type" "test")
7632 (set_attr "mode" "QI")])
7634 (define_insn "*testqi_ext_1_rex64"
7639 (match_operand 0 "ext_register_operand" "Q")
7643 (match_operand:QI 1 "register_operand" "Q")))
7645 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7646 "test{b}\t{%1, %h0|%h0, %1}"
7647 [(set_attr "type" "test")
7648 (set_attr "mode" "QI")])
7650 (define_insn "*testqi_ext_2"
7655 (match_operand 0 "ext_register_operand" "Q")
7659 (match_operand 1 "ext_register_operand" "Q")
7663 "ix86_match_ccmode (insn, CCNOmode)"
7664 "test{b}\t{%h1, %h0|%h0, %h1}"
7665 [(set_attr "type" "test")
7666 (set_attr "mode" "QI")])
7668 ;; Combine likes to form bit extractions for some tests. Humor it.
7669 (define_insn "*testqi_ext_3"
7671 (compare (zero_extract:SI
7672 (match_operand 0 "nonimmediate_operand" "rm")
7673 (match_operand:SI 1 "const_int_operand" "")
7674 (match_operand:SI 2 "const_int_operand" ""))
7676 "ix86_match_ccmode (insn, CCNOmode)
7677 && (GET_MODE (operands[0]) == SImode
7678 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7679 || GET_MODE (operands[0]) == HImode
7680 || GET_MODE (operands[0]) == QImode)"
7683 (define_insn "*testqi_ext_3_rex64"
7685 (compare (zero_extract:DI
7686 (match_operand 0 "nonimmediate_operand" "rm")
7687 (match_operand:DI 1 "const_int_operand" "")
7688 (match_operand:DI 2 "const_int_operand" ""))
7691 && ix86_match_ccmode (insn, CCNOmode)
7692 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
7693 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
7694 /* Ensure that resulting mask is zero or sign extended operand. */
7695 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7696 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
7697 && INTVAL (operands[1]) > 32))
7698 && (GET_MODE (operands[0]) == SImode
7699 || GET_MODE (operands[0]) == DImode
7700 || GET_MODE (operands[0]) == HImode
7701 || GET_MODE (operands[0]) == QImode)"
7706 (compare (zero_extract
7707 (match_operand 0 "nonimmediate_operand" "")
7708 (match_operand 1 "const_int_operand" "")
7709 (match_operand 2 "const_int_operand" ""))
7711 "ix86_match_ccmode (insn, CCNOmode)"
7712 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
7714 HOST_WIDE_INT len = INTVAL (operands[1]);
7715 HOST_WIDE_INT pos = INTVAL (operands[2]);
7717 enum machine_mode mode, submode;
7719 mode = GET_MODE (operands[0]);
7720 if (GET_CODE (operands[0]) == MEM)
7722 /* ??? Combine likes to put non-volatile mem extractions in QImode
7723 no matter the size of the test. So find a mode that works. */
7724 if (! MEM_VOLATILE_P (operands[0]))
7726 mode = smallest_mode_for_size (pos + len, MODE_INT);
7727 operands[0] = adjust_address (operands[0], mode, 0);
7730 else if (GET_CODE (operands[0]) == SUBREG
7731 && (submode = GET_MODE (SUBREG_REG (operands[0])),
7732 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
7733 && pos + len <= GET_MODE_BITSIZE (submode))
7735 /* Narrow a paradoxical subreg to prevent partial register stalls. */
7737 operands[0] = SUBREG_REG (operands[0]);
7739 else if (mode == HImode && pos + len <= 8)
7741 /* Small HImode tests can be converted to QImode. */
7743 operands[0] = gen_lowpart (QImode, operands[0]);
7746 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
7747 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
7749 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
7752 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
7753 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
7754 ;; this is relatively important trick.
7755 ;; Do the converison only post-reload to avoid limiting of the register class
7760 (and (match_operand 0 "register_operand" "")
7761 (match_operand 1 "const_int_operand" ""))
7764 && QI_REG_P (operands[0])
7765 && ((ix86_match_ccmode (insn, CCZmode)
7766 && !(INTVAL (operands[1]) & ~(255 << 8)))
7767 || (ix86_match_ccmode (insn, CCNOmode)
7768 && !(INTVAL (operands[1]) & ~(127 << 8))))
7769 && GET_MODE (operands[0]) != QImode"
7772 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
7775 "operands[0] = gen_lowpart (SImode, operands[0]);
7776 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
7781 (and (match_operand 0 "nonimmediate_operand" "")
7782 (match_operand 1 "const_int_operand" ""))
7785 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
7786 && ((ix86_match_ccmode (insn, CCZmode)
7787 && !(INTVAL (operands[1]) & ~255))
7788 || (ix86_match_ccmode (insn, CCNOmode)
7789 && !(INTVAL (operands[1]) & ~127)))
7790 && GET_MODE (operands[0]) != QImode"
7793 (and:QI (match_dup 0)
7796 "operands[0] = gen_lowpart (QImode, operands[0]);
7797 operands[1] = gen_lowpart (QImode, operands[1]);")
7800 ;; %%% This used to optimize known byte-wide and operations to memory,
7801 ;; and sometimes to QImode registers. If this is considered useful,
7802 ;; it should be done with splitters.
7804 (define_expand "anddi3"
7805 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7806 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
7807 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
7808 (clobber (reg:CC 17))]
7810 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
7812 (define_insn "*anddi_1_rex64"
7813 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
7814 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
7815 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
7816 (clobber (reg:CC 17))]
7817 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
7819 switch (get_attr_type (insn))
7823 enum machine_mode mode;
7825 if (GET_CODE (operands[2]) != CONST_INT)
7827 if (INTVAL (operands[2]) == 0xff)
7829 else if (INTVAL (operands[2]) == 0xffff)
7834 operands[1] = gen_lowpart (mode, operands[1]);
7836 return "movz{bq|x}\t{%1,%0|%0, %1}";
7838 return "movz{wq|x}\t{%1,%0|%0, %1}";
7842 if (! rtx_equal_p (operands[0], operands[1]))
7844 if (get_attr_mode (insn) == MODE_SI)
7845 return "and{l}\t{%k2, %k0|%k0, %k2}";
7847 return "and{q}\t{%2, %0|%0, %2}";
7850 [(set_attr "type" "alu,alu,alu,imovx")
7851 (set_attr "length_immediate" "*,*,*,0")
7852 (set_attr "mode" "SI,DI,DI,DI")])
7854 (define_insn "*anddi_2"
7856 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
7857 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
7859 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
7860 (and:DI (match_dup 1) (match_dup 2)))]
7861 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7862 && ix86_binary_operator_ok (AND, DImode, operands)"
7864 and{l}\t{%k2, %k0|%k0, %k2}
7865 and{q}\t{%2, %0|%0, %2}
7866 and{q}\t{%2, %0|%0, %2}"
7867 [(set_attr "type" "alu")
7868 (set_attr "mode" "SI,DI,DI")])
7870 (define_expand "andsi3"
7871 [(set (match_operand:SI 0 "nonimmediate_operand" "")
7872 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
7873 (match_operand:SI 2 "general_operand" "")))
7874 (clobber (reg:CC 17))]
7876 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
7878 (define_insn "*andsi_1"
7879 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
7880 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
7881 (match_operand:SI 2 "general_operand" "ri,rm,L")))
7882 (clobber (reg:CC 17))]
7883 "ix86_binary_operator_ok (AND, SImode, operands)"
7885 switch (get_attr_type (insn))
7889 enum machine_mode mode;
7891 if (GET_CODE (operands[2]) != CONST_INT)
7893 if (INTVAL (operands[2]) == 0xff)
7895 else if (INTVAL (operands[2]) == 0xffff)
7900 operands[1] = gen_lowpart (mode, operands[1]);
7902 return "movz{bl|x}\t{%1,%0|%0, %1}";
7904 return "movz{wl|x}\t{%1,%0|%0, %1}";
7908 if (! rtx_equal_p (operands[0], operands[1]))
7910 return "and{l}\t{%2, %0|%0, %2}";
7913 [(set_attr "type" "alu,alu,imovx")
7914 (set_attr "length_immediate" "*,*,0")
7915 (set_attr "mode" "SI")])
7918 [(set (match_operand 0 "register_operand" "")
7920 (const_int -65536)))
7921 (clobber (reg:CC 17))]
7922 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
7923 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7924 "operands[1] = gen_lowpart (HImode, operands[0]);")
7927 [(set (match_operand 0 "ext_register_operand" "")
7930 (clobber (reg:CC 17))]
7931 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
7932 [(set (strict_low_part (match_dup 1)) (const_int 0))]
7933 "operands[1] = gen_lowpart (QImode, operands[0]);")
7936 [(set (match_operand 0 "ext_register_operand" "")
7938 (const_int -65281)))
7939 (clobber (reg:CC 17))]
7940 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
7941 [(parallel [(set (zero_extract:SI (match_dup 0)
7945 (zero_extract:SI (match_dup 0)
7948 (zero_extract:SI (match_dup 0)
7951 (clobber (reg:CC 17))])]
7952 "operands[0] = gen_lowpart (SImode, operands[0]);")
7954 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
7955 (define_insn "*andsi_1_zext"
7956 [(set (match_operand:DI 0 "register_operand" "=r")
7958 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7959 (match_operand:SI 2 "general_operand" "rim"))))
7960 (clobber (reg:CC 17))]
7961 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
7962 "and{l}\t{%2, %k0|%k0, %2}"
7963 [(set_attr "type" "alu")
7964 (set_attr "mode" "SI")])
7966 (define_insn "*andsi_2"
7968 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
7969 (match_operand:SI 2 "general_operand" "rim,ri"))
7971 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
7972 (and:SI (match_dup 1) (match_dup 2)))]
7973 "ix86_match_ccmode (insn, CCNOmode)
7974 && ix86_binary_operator_ok (AND, SImode, operands)"
7975 "and{l}\t{%2, %0|%0, %2}"
7976 [(set_attr "type" "alu")
7977 (set_attr "mode" "SI")])
7979 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
7980 (define_insn "*andsi_2_zext"
7982 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
7983 (match_operand:SI 2 "general_operand" "rim"))
7985 (set (match_operand:DI 0 "register_operand" "=r")
7986 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
7987 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7988 && ix86_binary_operator_ok (AND, SImode, operands)"
7989 "and{l}\t{%2, %k0|%k0, %2}"
7990 [(set_attr "type" "alu")
7991 (set_attr "mode" "SI")])
7993 (define_expand "andhi3"
7994 [(set (match_operand:HI 0 "nonimmediate_operand" "")
7995 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
7996 (match_operand:HI 2 "general_operand" "")))
7997 (clobber (reg:CC 17))]
7998 "TARGET_HIMODE_MATH"
7999 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8001 (define_insn "*andhi_1"
8002 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8003 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8004 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8005 (clobber (reg:CC 17))]
8006 "ix86_binary_operator_ok (AND, HImode, operands)"
8008 switch (get_attr_type (insn))
8011 if (GET_CODE (operands[2]) != CONST_INT)
8013 if (INTVAL (operands[2]) == 0xff)
8014 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8018 if (! rtx_equal_p (operands[0], operands[1]))
8021 return "and{w}\t{%2, %0|%0, %2}";
8024 [(set_attr "type" "alu,alu,imovx")
8025 (set_attr "length_immediate" "*,*,0")
8026 (set_attr "mode" "HI,HI,SI")])
8028 (define_insn "*andhi_2"
8030 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8031 (match_operand:HI 2 "general_operand" "rim,ri"))
8033 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8034 (and:HI (match_dup 1) (match_dup 2)))]
8035 "ix86_match_ccmode (insn, CCNOmode)
8036 && ix86_binary_operator_ok (AND, HImode, operands)"
8037 "and{w}\t{%2, %0|%0, %2}"
8038 [(set_attr "type" "alu")
8039 (set_attr "mode" "HI")])
8041 (define_expand "andqi3"
8042 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8043 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8044 (match_operand:QI 2 "general_operand" "")))
8045 (clobber (reg:CC 17))]
8046 "TARGET_QIMODE_MATH"
8047 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8049 ;; %%% Potential partial reg stall on alternative 2. What to do?
8050 (define_insn "*andqi_1"
8051 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8052 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8053 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8054 (clobber (reg:CC 17))]
8055 "ix86_binary_operator_ok (AND, QImode, operands)"
8057 and{b}\t{%2, %0|%0, %2}
8058 and{b}\t{%2, %0|%0, %2}
8059 and{l}\t{%k2, %k0|%k0, %k2}"
8060 [(set_attr "type" "alu")
8061 (set_attr "mode" "QI,QI,SI")])
8063 (define_insn "*andqi_1_slp"
8064 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8065 (and:QI (match_dup 0)
8066 (match_operand:QI 1 "general_operand" "qi,qmi")))
8067 (clobber (reg:CC 17))]
8068 "! TARGET_PARTIAL_REG_STALL || optimize_size"
8069 "and{b}\t{%1, %0|%0, %1}"
8070 [(set_attr "type" "alu1")
8071 (set_attr "mode" "QI")])
8073 (define_insn "*andqi_2"
8076 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8077 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8079 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8080 (and:QI (match_dup 1) (match_dup 2)))]
8081 "ix86_match_ccmode (insn, CCNOmode)
8082 && ix86_binary_operator_ok (AND, QImode, operands)"
8084 if (which_alternative == 2)
8086 if (GET_CODE (operands[2]) == CONST_INT
8087 && (INTVAL (operands[2]) & 0xffffff00))
8088 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8089 return "and{l}\t{%2, %k0|%k0, %2}";
8091 return "and{b}\t{%2, %0|%0, %2}";
8093 [(set_attr "type" "alu")
8094 (set_attr "mode" "QI,QI,SI")])
8096 (define_insn "*andqi_2_slp"
8099 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8100 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8102 (set (strict_low_part (match_dup 0))
8103 (and:QI (match_dup 0) (match_dup 1)))]
8104 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8105 && ix86_match_ccmode (insn, CCNOmode)"
8106 "and{b}\t{%1, %0|%0, %1}"
8107 [(set_attr "type" "alu1")
8108 (set_attr "mode" "QI")])
8110 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8111 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8112 ;; for a QImode operand, which of course failed.
8114 (define_insn "andqi_ext_0"
8115 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8120 (match_operand 1 "ext_register_operand" "0")
8123 (match_operand 2 "const_int_operand" "n")))
8124 (clobber (reg:CC 17))]
8126 "and{b}\t{%2, %h0|%h0, %2}"
8127 [(set_attr "type" "alu")
8128 (set_attr "length_immediate" "1")
8129 (set_attr "mode" "QI")])
8131 ;; Generated by peephole translating test to and. This shows up
8132 ;; often in fp comparisons.
8134 (define_insn "*andqi_ext_0_cc"
8139 (match_operand 1 "ext_register_operand" "0")
8142 (match_operand 2 "const_int_operand" "n"))
8144 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8153 "ix86_match_ccmode (insn, CCNOmode)"
8154 "and{b}\t{%2, %h0|%h0, %2}"
8155 [(set_attr "type" "alu")
8156 (set_attr "length_immediate" "1")
8157 (set_attr "mode" "QI")])
8159 (define_insn "*andqi_ext_1"
8160 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8165 (match_operand 1 "ext_register_operand" "0")
8169 (match_operand:QI 2 "general_operand" "Qm"))))
8170 (clobber (reg:CC 17))]
8172 "and{b}\t{%2, %h0|%h0, %2}"
8173 [(set_attr "type" "alu")
8174 (set_attr "length_immediate" "0")
8175 (set_attr "mode" "QI")])
8177 (define_insn "*andqi_ext_1_rex64"
8178 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8183 (match_operand 1 "ext_register_operand" "0")
8187 (match_operand 2 "ext_register_operand" "Q"))))
8188 (clobber (reg:CC 17))]
8190 "and{b}\t{%2, %h0|%h0, %2}"
8191 [(set_attr "type" "alu")
8192 (set_attr "length_immediate" "0")
8193 (set_attr "mode" "QI")])
8195 (define_insn "*andqi_ext_2"
8196 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8201 (match_operand 1 "ext_register_operand" "%0")
8205 (match_operand 2 "ext_register_operand" "Q")
8208 (clobber (reg:CC 17))]
8210 "and{b}\t{%h2, %h0|%h0, %h2}"
8211 [(set_attr "type" "alu")
8212 (set_attr "length_immediate" "0")
8213 (set_attr "mode" "QI")])
8215 ;; Convert wide AND instructions with immediate operand to shorter QImode
8216 ;; equivalents when possible.
8217 ;; Don't do the splitting with memory operands, since it intoduces risc
8218 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8219 ;; for size, but that can (should?) be handled by generic code instead.
8221 [(set (match_operand 0 "register_operand" "")
8222 (and (match_operand 1 "register_operand" "")
8223 (match_operand 2 "const_int_operand" "")))
8224 (clobber (reg:CC 17))]
8226 && QI_REG_P (operands[0])
8227 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8228 && !(~INTVAL (operands[2]) & ~(255 << 8))
8229 && GET_MODE (operands[0]) != QImode"
8230 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8231 (and:SI (zero_extract:SI (match_dup 1)
8232 (const_int 8) (const_int 8))
8234 (clobber (reg:CC 17))])]
8235 "operands[0] = gen_lowpart (SImode, operands[0]);
8236 operands[1] = gen_lowpart (SImode, operands[1]);
8237 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8239 ;; Since AND can be encoded with sign extended immediate, this is only
8240 ;; profitable when 7th bit is not set.
8242 [(set (match_operand 0 "register_operand" "")
8243 (and (match_operand 1 "general_operand" "")
8244 (match_operand 2 "const_int_operand" "")))
8245 (clobber (reg:CC 17))]
8247 && ANY_QI_REG_P (operands[0])
8248 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8249 && !(~INTVAL (operands[2]) & ~255)
8250 && !(INTVAL (operands[2]) & 128)
8251 && GET_MODE (operands[0]) != QImode"
8252 [(parallel [(set (strict_low_part (match_dup 0))
8253 (and:QI (match_dup 1)
8255 (clobber (reg:CC 17))])]
8256 "operands[0] = gen_lowpart (QImode, operands[0]);
8257 operands[1] = gen_lowpart (QImode, operands[1]);
8258 operands[2] = gen_lowpart (QImode, operands[2]);")
8260 ;; Logical inclusive OR instructions
8262 ;; %%% This used to optimize known byte-wide and operations to memory.
8263 ;; If this is considered useful, it should be done with splitters.
8265 (define_expand "iordi3"
8266 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8267 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8268 (match_operand:DI 2 "x86_64_general_operand" "")))
8269 (clobber (reg:CC 17))]
8271 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8273 (define_insn "*iordi_1_rex64"
8274 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8275 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8276 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8277 (clobber (reg:CC 17))]
8279 && ix86_binary_operator_ok (IOR, DImode, operands)"
8280 "or{q}\t{%2, %0|%0, %2}"
8281 [(set_attr "type" "alu")
8282 (set_attr "mode" "DI")])
8284 (define_insn "*iordi_2_rex64"
8286 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8287 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8289 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8290 (ior:DI (match_dup 1) (match_dup 2)))]
8292 && ix86_match_ccmode (insn, CCNOmode)
8293 && ix86_binary_operator_ok (IOR, DImode, operands)"
8294 "or{q}\t{%2, %0|%0, %2}"
8295 [(set_attr "type" "alu")
8296 (set_attr "mode" "DI")])
8298 (define_insn "*iordi_3_rex64"
8300 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8301 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8303 (clobber (match_scratch:DI 0 "=r"))]
8305 && ix86_match_ccmode (insn, CCNOmode)
8306 && ix86_binary_operator_ok (IOR, DImode, operands)"
8307 "or{q}\t{%2, %0|%0, %2}"
8308 [(set_attr "type" "alu")
8309 (set_attr "mode" "DI")])
8312 (define_expand "iorsi3"
8313 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8314 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8315 (match_operand:SI 2 "general_operand" "")))
8316 (clobber (reg:CC 17))]
8318 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8320 (define_insn "*iorsi_1"
8321 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8322 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8323 (match_operand:SI 2 "general_operand" "ri,rmi")))
8324 (clobber (reg:CC 17))]
8325 "ix86_binary_operator_ok (IOR, SImode, operands)"
8326 "or{l}\t{%2, %0|%0, %2}"
8327 [(set_attr "type" "alu")
8328 (set_attr "mode" "SI")])
8330 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8331 (define_insn "*iorsi_1_zext"
8332 [(set (match_operand:DI 0 "register_operand" "=rm")
8334 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8335 (match_operand:SI 2 "general_operand" "rim"))))
8336 (clobber (reg:CC 17))]
8337 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8338 "or{l}\t{%2, %k0|%k0, %2}"
8339 [(set_attr "type" "alu")
8340 (set_attr "mode" "SI")])
8342 (define_insn "*iorsi_1_zext_imm"
8343 [(set (match_operand:DI 0 "register_operand" "=rm")
8344 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8345 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8346 (clobber (reg:CC 17))]
8348 "or{l}\t{%2, %k0|%k0, %2}"
8349 [(set_attr "type" "alu")
8350 (set_attr "mode" "SI")])
8352 (define_insn "*iorsi_2"
8354 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8355 (match_operand:SI 2 "general_operand" "rim,ri"))
8357 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8358 (ior:SI (match_dup 1) (match_dup 2)))]
8359 "ix86_match_ccmode (insn, CCNOmode)
8360 && ix86_binary_operator_ok (IOR, SImode, operands)"
8361 "or{l}\t{%2, %0|%0, %2}"
8362 [(set_attr "type" "alu")
8363 (set_attr "mode" "SI")])
8365 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8366 ;; ??? Special case for immediate operand is missing - it is tricky.
8367 (define_insn "*iorsi_2_zext"
8369 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8370 (match_operand:SI 2 "general_operand" "rim"))
8372 (set (match_operand:DI 0 "register_operand" "=r")
8373 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8374 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8375 && ix86_binary_operator_ok (IOR, SImode, operands)"
8376 "or{l}\t{%2, %k0|%k0, %2}"
8377 [(set_attr "type" "alu")
8378 (set_attr "mode" "SI")])
8380 (define_insn "*iorsi_2_zext_imm"
8382 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8383 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8385 (set (match_operand:DI 0 "register_operand" "=r")
8386 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8387 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8388 && ix86_binary_operator_ok (IOR, SImode, operands)"
8389 "or{l}\t{%2, %k0|%k0, %2}"
8390 [(set_attr "type" "alu")
8391 (set_attr "mode" "SI")])
8393 (define_insn "*iorsi_3"
8395 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8396 (match_operand:SI 2 "general_operand" "rim"))
8398 (clobber (match_scratch:SI 0 "=r"))]
8399 "ix86_match_ccmode (insn, CCNOmode)
8400 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8401 "or{l}\t{%2, %0|%0, %2}"
8402 [(set_attr "type" "alu")
8403 (set_attr "mode" "SI")])
8405 (define_expand "iorhi3"
8406 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8407 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8408 (match_operand:HI 2 "general_operand" "")))
8409 (clobber (reg:CC 17))]
8410 "TARGET_HIMODE_MATH"
8411 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8413 (define_insn "*iorhi_1"
8414 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8415 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8416 (match_operand:HI 2 "general_operand" "rmi,ri")))
8417 (clobber (reg:CC 17))]
8418 "ix86_binary_operator_ok (IOR, HImode, operands)"
8419 "or{w}\t{%2, %0|%0, %2}"
8420 [(set_attr "type" "alu")
8421 (set_attr "mode" "HI")])
8423 (define_insn "*iorhi_2"
8425 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8426 (match_operand:HI 2 "general_operand" "rim,ri"))
8428 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8429 (ior:HI (match_dup 1) (match_dup 2)))]
8430 "ix86_match_ccmode (insn, CCNOmode)
8431 && ix86_binary_operator_ok (IOR, HImode, operands)"
8432 "or{w}\t{%2, %0|%0, %2}"
8433 [(set_attr "type" "alu")
8434 (set_attr "mode" "HI")])
8436 (define_insn "*iorhi_3"
8438 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8439 (match_operand:HI 2 "general_operand" "rim"))
8441 (clobber (match_scratch:HI 0 "=r"))]
8442 "ix86_match_ccmode (insn, CCNOmode)
8443 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8444 "or{w}\t{%2, %0|%0, %2}"
8445 [(set_attr "type" "alu")
8446 (set_attr "mode" "HI")])
8448 (define_expand "iorqi3"
8449 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8450 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8451 (match_operand:QI 2 "general_operand" "")))
8452 (clobber (reg:CC 17))]
8453 "TARGET_QIMODE_MATH"
8454 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8456 ;; %%% Potential partial reg stall on alternative 2. What to do?
8457 (define_insn "*iorqi_1"
8458 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8459 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8460 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8461 (clobber (reg:CC 17))]
8462 "ix86_binary_operator_ok (IOR, QImode, operands)"
8464 or{b}\t{%2, %0|%0, %2}
8465 or{b}\t{%2, %0|%0, %2}
8466 or{l}\t{%k2, %k0|%k0, %k2}"
8467 [(set_attr "type" "alu")
8468 (set_attr "mode" "QI,QI,SI")])
8470 (define_insn "*iorqi_1_slp"
8471 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8472 (ior:QI (match_dup 0)
8473 (match_operand:QI 1 "general_operand" "qmi,qi")))
8474 (clobber (reg:CC 17))]
8475 "! TARGET_PARTIAL_REG_STALL || optimize_size"
8476 "or{b}\t{%1, %0|%0, %1}"
8477 [(set_attr "type" "alu1")
8478 (set_attr "mode" "QI")])
8480 (define_insn "*iorqi_2"
8482 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8483 (match_operand:QI 2 "general_operand" "qim,qi"))
8485 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8486 (ior:QI (match_dup 1) (match_dup 2)))]
8487 "ix86_match_ccmode (insn, CCNOmode)
8488 && ix86_binary_operator_ok (IOR, QImode, operands)"
8489 "or{b}\t{%2, %0|%0, %2}"
8490 [(set_attr "type" "alu")
8491 (set_attr "mode" "QI")])
8493 (define_insn "*iorqi_2_slp"
8495 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8496 (match_operand:QI 1 "general_operand" "qim,qi"))
8498 (set (strict_low_part (match_dup 0))
8499 (ior:QI (match_dup 0) (match_dup 1)))]
8500 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8501 && ix86_match_ccmode (insn, CCNOmode)"
8502 "or{b}\t{%1, %0|%0, %1}"
8503 [(set_attr "type" "alu1")
8504 (set_attr "mode" "QI")])
8506 (define_insn "*iorqi_3"
8508 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8509 (match_operand:QI 2 "general_operand" "qim"))
8511 (clobber (match_scratch:QI 0 "=q"))]
8512 "ix86_match_ccmode (insn, CCNOmode)
8513 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8514 "or{b}\t{%2, %0|%0, %2}"
8515 [(set_attr "type" "alu")
8516 (set_attr "mode" "QI")])
8518 (define_insn "iorqi_ext_0"
8519 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8524 (match_operand 1 "ext_register_operand" "0")
8527 (match_operand 2 "const_int_operand" "n")))
8528 (clobber (reg:CC 17))]
8529 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8530 "or{b}\t{%2, %h0|%h0, %2}"
8531 [(set_attr "type" "alu")
8532 (set_attr "length_immediate" "1")
8533 (set_attr "mode" "QI")])
8535 (define_insn "*iorqi_ext_1"
8536 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8541 (match_operand 1 "ext_register_operand" "0")
8545 (match_operand:QI 2 "general_operand" "Qm"))))
8546 (clobber (reg:CC 17))]
8548 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8549 "or{b}\t{%2, %h0|%h0, %2}"
8550 [(set_attr "type" "alu")
8551 (set_attr "length_immediate" "0")
8552 (set_attr "mode" "QI")])
8554 (define_insn "*iorqi_ext_1_rex64"
8555 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8560 (match_operand 1 "ext_register_operand" "0")
8564 (match_operand 2 "ext_register_operand" "Q"))))
8565 (clobber (reg:CC 17))]
8567 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8568 "or{b}\t{%2, %h0|%h0, %2}"
8569 [(set_attr "type" "alu")
8570 (set_attr "length_immediate" "0")
8571 (set_attr "mode" "QI")])
8573 (define_insn "*iorqi_ext_2"
8574 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8578 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8581 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8584 (clobber (reg:CC 17))]
8585 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8586 "ior{b}\t{%h2, %h0|%h0, %h2}"
8587 [(set_attr "type" "alu")
8588 (set_attr "length_immediate" "0")
8589 (set_attr "mode" "QI")])
8592 [(set (match_operand 0 "register_operand" "")
8593 (ior (match_operand 1 "register_operand" "")
8594 (match_operand 2 "const_int_operand" "")))
8595 (clobber (reg:CC 17))]
8597 && QI_REG_P (operands[0])
8598 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8599 && !(INTVAL (operands[2]) & ~(255 << 8))
8600 && GET_MODE (operands[0]) != QImode"
8601 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8602 (ior:SI (zero_extract:SI (match_dup 1)
8603 (const_int 8) (const_int 8))
8605 (clobber (reg:CC 17))])]
8606 "operands[0] = gen_lowpart (SImode, operands[0]);
8607 operands[1] = gen_lowpart (SImode, operands[1]);
8608 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8610 ;; Since OR can be encoded with sign extended immediate, this is only
8611 ;; profitable when 7th bit is set.
8613 [(set (match_operand 0 "register_operand" "")
8614 (ior (match_operand 1 "general_operand" "")
8615 (match_operand 2 "const_int_operand" "")))
8616 (clobber (reg:CC 17))]
8618 && ANY_QI_REG_P (operands[0])
8619 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8620 && !(INTVAL (operands[2]) & ~255)
8621 && (INTVAL (operands[2]) & 128)
8622 && GET_MODE (operands[0]) != QImode"
8623 [(parallel [(set (strict_low_part (match_dup 0))
8624 (ior:QI (match_dup 1)
8626 (clobber (reg:CC 17))])]
8627 "operands[0] = gen_lowpart (QImode, operands[0]);
8628 operands[1] = gen_lowpart (QImode, operands[1]);
8629 operands[2] = gen_lowpart (QImode, operands[2]);")
8631 ;; Logical XOR instructions
8633 ;; %%% This used to optimize known byte-wide and operations to memory.
8634 ;; If this is considered useful, it should be done with splitters.
8636 (define_expand "xordi3"
8637 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8638 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8639 (match_operand:DI 2 "x86_64_general_operand" "")))
8640 (clobber (reg:CC 17))]
8642 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8644 (define_insn "*xordi_1_rex64"
8645 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8646 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8647 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8648 (clobber (reg:CC 17))]
8650 && ix86_binary_operator_ok (XOR, DImode, operands)"
8652 xor{q}\t{%2, %0|%0, %2}
8653 xor{q}\t{%2, %0|%0, %2}"
8654 [(set_attr "type" "alu")
8655 (set_attr "mode" "DI,DI")])
8657 (define_insn "*xordi_2_rex64"
8659 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8660 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8662 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8663 (xor:DI (match_dup 1) (match_dup 2)))]
8665 && ix86_match_ccmode (insn, CCNOmode)
8666 && ix86_binary_operator_ok (XOR, DImode, operands)"
8668 xor{q}\t{%2, %0|%0, %2}
8669 xor{q}\t{%2, %0|%0, %2}"
8670 [(set_attr "type" "alu")
8671 (set_attr "mode" "DI,DI")])
8673 (define_insn "*xordi_3_rex64"
8675 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8676 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8678 (clobber (match_scratch:DI 0 "=r"))]
8680 && ix86_match_ccmode (insn, CCNOmode)
8681 && ix86_binary_operator_ok (XOR, DImode, operands)"
8682 "xor{q}\t{%2, %0|%0, %2}"
8683 [(set_attr "type" "alu")
8684 (set_attr "mode" "DI")])
8686 (define_expand "xorsi3"
8687 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8688 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8689 (match_operand:SI 2 "general_operand" "")))
8690 (clobber (reg:CC 17))]
8692 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8694 (define_insn "*xorsi_1"
8695 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8696 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8697 (match_operand:SI 2 "general_operand" "ri,rm")))
8698 (clobber (reg:CC 17))]
8699 "ix86_binary_operator_ok (XOR, SImode, operands)"
8700 "xor{l}\t{%2, %0|%0, %2}"
8701 [(set_attr "type" "alu")
8702 (set_attr "mode" "SI")])
8704 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8705 ;; Add speccase for immediates
8706 (define_insn "*xorsi_1_zext"
8707 [(set (match_operand:DI 0 "register_operand" "=r")
8709 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8710 (match_operand:SI 2 "general_operand" "rim"))))
8711 (clobber (reg:CC 17))]
8712 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8713 "xor{l}\t{%2, %k0|%k0, %2}"
8714 [(set_attr "type" "alu")
8715 (set_attr "mode" "SI")])
8717 (define_insn "*xorsi_1_zext_imm"
8718 [(set (match_operand:DI 0 "register_operand" "=r")
8719 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8720 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8721 (clobber (reg:CC 17))]
8722 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8723 "xor{l}\t{%2, %k0|%k0, %2}"
8724 [(set_attr "type" "alu")
8725 (set_attr "mode" "SI")])
8727 (define_insn "*xorsi_2"
8729 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8730 (match_operand:SI 2 "general_operand" "rim,ri"))
8732 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8733 (xor:SI (match_dup 1) (match_dup 2)))]
8734 "ix86_match_ccmode (insn, CCNOmode)
8735 && ix86_binary_operator_ok (XOR, SImode, operands)"
8736 "xor{l}\t{%2, %0|%0, %2}"
8737 [(set_attr "type" "alu")
8738 (set_attr "mode" "SI")])
8740 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8741 ;; ??? Special case for immediate operand is missing - it is tricky.
8742 (define_insn "*xorsi_2_zext"
8744 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8745 (match_operand:SI 2 "general_operand" "rim"))
8747 (set (match_operand:DI 0 "register_operand" "=r")
8748 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8749 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8750 && ix86_binary_operator_ok (XOR, SImode, operands)"
8751 "xor{l}\t{%2, %k0|%k0, %2}"
8752 [(set_attr "type" "alu")
8753 (set_attr "mode" "SI")])
8755 (define_insn "*xorsi_2_zext_imm"
8757 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8758 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8760 (set (match_operand:DI 0 "register_operand" "=r")
8761 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8762 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8763 && ix86_binary_operator_ok (XOR, SImode, operands)"
8764 "xor{l}\t{%2, %k0|%k0, %2}"
8765 [(set_attr "type" "alu")
8766 (set_attr "mode" "SI")])
8768 (define_insn "*xorsi_3"
8770 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8771 (match_operand:SI 2 "general_operand" "rim"))
8773 (clobber (match_scratch:SI 0 "=r"))]
8774 "ix86_match_ccmode (insn, CCNOmode)
8775 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8776 "xor{l}\t{%2, %0|%0, %2}"
8777 [(set_attr "type" "alu")
8778 (set_attr "mode" "SI")])
8780 (define_expand "xorhi3"
8781 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8782 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
8783 (match_operand:HI 2 "general_operand" "")))
8784 (clobber (reg:CC 17))]
8785 "TARGET_HIMODE_MATH"
8786 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
8788 (define_insn "*xorhi_1"
8789 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8790 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8791 (match_operand:HI 2 "general_operand" "rmi,ri")))
8792 (clobber (reg:CC 17))]
8793 "ix86_binary_operator_ok (XOR, HImode, operands)"
8794 "xor{w}\t{%2, %0|%0, %2}"
8795 [(set_attr "type" "alu")
8796 (set_attr "mode" "HI")])
8798 (define_insn "*xorhi_2"
8800 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8801 (match_operand:HI 2 "general_operand" "rim,ri"))
8803 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8804 (xor:HI (match_dup 1) (match_dup 2)))]
8805 "ix86_match_ccmode (insn, CCNOmode)
8806 && ix86_binary_operator_ok (XOR, HImode, operands)"
8807 "xor{w}\t{%2, %0|%0, %2}"
8808 [(set_attr "type" "alu")
8809 (set_attr "mode" "HI")])
8811 (define_insn "*xorhi_3"
8813 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8814 (match_operand:HI 2 "general_operand" "rim"))
8816 (clobber (match_scratch:HI 0 "=r"))]
8817 "ix86_match_ccmode (insn, CCNOmode)
8818 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8819 "xor{w}\t{%2, %0|%0, %2}"
8820 [(set_attr "type" "alu")
8821 (set_attr "mode" "HI")])
8823 (define_expand "xorqi3"
8824 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8825 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
8826 (match_operand:QI 2 "general_operand" "")))
8827 (clobber (reg:CC 17))]
8828 "TARGET_QIMODE_MATH"
8829 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
8831 ;; %%% Potential partial reg stall on alternative 2. What to do?
8832 (define_insn "*xorqi_1"
8833 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8834 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8835 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8836 (clobber (reg:CC 17))]
8837 "ix86_binary_operator_ok (XOR, QImode, operands)"
8839 xor{b}\t{%2, %0|%0, %2}
8840 xor{b}\t{%2, %0|%0, %2}
8841 xor{l}\t{%k2, %k0|%k0, %k2}"
8842 [(set_attr "type" "alu")
8843 (set_attr "mode" "QI,QI,SI")])
8845 (define_insn "*xorqi_1_slp"
8846 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8847 (xor:QI (match_dup 0)
8848 (match_operand:QI 1 "general_operand" "qi,qmi")))
8849 (clobber (reg:CC 17))]
8850 "! TARGET_PARTIAL_REG_STALL || optimize_size"
8851 "xor{b}\t{%1, %0|%0, %1}"
8852 [(set_attr "type" "alu1")
8853 (set_attr "mode" "QI")])
8855 (define_insn "xorqi_ext_0"
8856 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8861 (match_operand 1 "ext_register_operand" "0")
8864 (match_operand 2 "const_int_operand" "n")))
8865 (clobber (reg:CC 17))]
8866 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8867 "xor{b}\t{%2, %h0|%h0, %2}"
8868 [(set_attr "type" "alu")
8869 (set_attr "length_immediate" "1")
8870 (set_attr "mode" "QI")])
8872 (define_insn "*xorqi_ext_1"
8873 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8878 (match_operand 1 "ext_register_operand" "0")
8882 (match_operand:QI 2 "general_operand" "Qm"))))
8883 (clobber (reg:CC 17))]
8885 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8886 "xor{b}\t{%2, %h0|%h0, %2}"
8887 [(set_attr "type" "alu")
8888 (set_attr "length_immediate" "0")
8889 (set_attr "mode" "QI")])
8891 (define_insn "*xorqi_ext_1_rex64"
8892 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8897 (match_operand 1 "ext_register_operand" "0")
8901 (match_operand 2 "ext_register_operand" "Q"))))
8902 (clobber (reg:CC 17))]
8904 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8905 "xor{b}\t{%2, %h0|%h0, %2}"
8906 [(set_attr "type" "alu")
8907 (set_attr "length_immediate" "0")
8908 (set_attr "mode" "QI")])
8910 (define_insn "*xorqi_ext_2"
8911 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8915 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8918 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8921 (clobber (reg:CC 17))]
8922 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8923 "xor{b}\t{%h2, %h0|%h0, %h2}"
8924 [(set_attr "type" "alu")
8925 (set_attr "length_immediate" "0")
8926 (set_attr "mode" "QI")])
8928 (define_insn "*xorqi_cc_1"
8931 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8932 (match_operand:QI 2 "general_operand" "qim,qi"))
8934 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8935 (xor:QI (match_dup 1) (match_dup 2)))]
8936 "ix86_match_ccmode (insn, CCNOmode)
8937 && ix86_binary_operator_ok (XOR, QImode, operands)"
8938 "xor{b}\t{%2, %0|%0, %2}"
8939 [(set_attr "type" "alu")
8940 (set_attr "mode" "QI")])
8942 (define_insn "*xorqi_2_slp"
8944 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8945 (match_operand:QI 1 "general_operand" "qim,qi"))
8947 (set (strict_low_part (match_dup 0))
8948 (xor:QI (match_dup 0) (match_dup 1)))]
8949 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8950 && ix86_match_ccmode (insn, CCNOmode)"
8951 "xor{b}\t{%1, %0|%0, %1}"
8952 [(set_attr "type" "alu1")
8953 (set_attr "mode" "QI")])
8955 (define_insn "*xorqi_cc_2"
8958 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8959 (match_operand:QI 2 "general_operand" "qim"))
8961 (clobber (match_scratch:QI 0 "=q"))]
8962 "ix86_match_ccmode (insn, CCNOmode)
8963 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8964 "xor{b}\t{%2, %0|%0, %2}"
8965 [(set_attr "type" "alu")
8966 (set_attr "mode" "QI")])
8968 (define_insn "*xorqi_cc_ext_1"
8973 (match_operand 1 "ext_register_operand" "0")
8976 (match_operand:QI 2 "general_operand" "qmn"))
8978 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
8982 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
8984 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8985 "xor{b}\t{%2, %h0|%h0, %2}"
8986 [(set_attr "type" "alu")
8987 (set_attr "mode" "QI")])
8989 (define_insn "*xorqi_cc_ext_1_rex64"
8994 (match_operand 1 "ext_register_operand" "0")
8997 (match_operand:QI 2 "nonmemory_operand" "Qn"))
8999 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9003 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9005 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9006 "xor{b}\t{%2, %h0|%h0, %2}"
9007 [(set_attr "type" "alu")
9008 (set_attr "mode" "QI")])
9010 (define_expand "xorqi_cc_ext_1"
9016 (match_operand 1 "ext_register_operand" "")
9019 (match_operand:QI 2 "general_operand" ""))
9021 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9025 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9031 [(set (match_operand 0 "register_operand" "")
9032 (xor (match_operand 1 "register_operand" "")
9033 (match_operand 2 "const_int_operand" "")))
9034 (clobber (reg:CC 17))]
9036 && QI_REG_P (operands[0])
9037 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9038 && !(INTVAL (operands[2]) & ~(255 << 8))
9039 && GET_MODE (operands[0]) != QImode"
9040 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9041 (xor:SI (zero_extract:SI (match_dup 1)
9042 (const_int 8) (const_int 8))
9044 (clobber (reg:CC 17))])]
9045 "operands[0] = gen_lowpart (SImode, operands[0]);
9046 operands[1] = gen_lowpart (SImode, operands[1]);
9047 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9049 ;; Since XOR can be encoded with sign extended immediate, this is only
9050 ;; profitable when 7th bit is set.
9052 [(set (match_operand 0 "register_operand" "")
9053 (xor (match_operand 1 "general_operand" "")
9054 (match_operand 2 "const_int_operand" "")))
9055 (clobber (reg:CC 17))]
9057 && ANY_QI_REG_P (operands[0])
9058 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9059 && !(INTVAL (operands[2]) & ~255)
9060 && (INTVAL (operands[2]) & 128)
9061 && GET_MODE (operands[0]) != QImode"
9062 [(parallel [(set (strict_low_part (match_dup 0))
9063 (xor:QI (match_dup 1)
9065 (clobber (reg:CC 17))])]
9066 "operands[0] = gen_lowpart (QImode, operands[0]);
9067 operands[1] = gen_lowpart (QImode, operands[1]);
9068 operands[2] = gen_lowpart (QImode, operands[2]);")
9070 ;; Negation instructions
9072 (define_expand "negdi2"
9073 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9074 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9075 (clobber (reg:CC 17))])]
9077 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9079 (define_insn "*negdi2_1"
9080 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9081 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9082 (clobber (reg:CC 17))]
9084 && ix86_unary_operator_ok (NEG, DImode, operands)"
9088 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9089 (neg:DI (match_operand:DI 1 "general_operand" "")))
9090 (clobber (reg:CC 17))]
9091 "!TARGET_64BIT && reload_completed"
9094 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9095 (set (match_dup 0) (neg:SI (match_dup 2)))])
9098 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9101 (clobber (reg:CC 17))])
9104 (neg:SI (match_dup 1)))
9105 (clobber (reg:CC 17))])]
9106 "split_di (operands+1, 1, operands+2, operands+3);
9107 split_di (operands+0, 1, operands+0, operands+1);")
9109 (define_insn "*negdi2_1_rex64"
9110 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9111 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9112 (clobber (reg:CC 17))]
9113 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9115 [(set_attr "type" "negnot")
9116 (set_attr "mode" "DI")])
9118 ;; The problem with neg is that it does not perform (compare x 0),
9119 ;; it really performs (compare 0 x), which leaves us with the zero
9120 ;; flag being the only useful item.
9122 (define_insn "*negdi2_cmpz_rex64"
9124 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9126 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9127 (neg:DI (match_dup 1)))]
9128 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9130 [(set_attr "type" "negnot")
9131 (set_attr "mode" "DI")])
9134 (define_expand "negsi2"
9135 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9136 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9137 (clobber (reg:CC 17))])]
9139 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9141 (define_insn "*negsi2_1"
9142 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9143 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9144 (clobber (reg:CC 17))]
9145 "ix86_unary_operator_ok (NEG, SImode, operands)"
9147 [(set_attr "type" "negnot")
9148 (set_attr "mode" "SI")])
9150 ;; Combine is quite creative about this pattern.
9151 (define_insn "*negsi2_1_zext"
9152 [(set (match_operand:DI 0 "register_operand" "=r")
9153 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9156 (clobber (reg:CC 17))]
9157 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9159 [(set_attr "type" "negnot")
9160 (set_attr "mode" "SI")])
9162 ;; The problem with neg is that it does not perform (compare x 0),
9163 ;; it really performs (compare 0 x), which leaves us with the zero
9164 ;; flag being the only useful item.
9166 (define_insn "*negsi2_cmpz"
9168 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9170 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9171 (neg:SI (match_dup 1)))]
9172 "ix86_unary_operator_ok (NEG, SImode, operands)"
9174 [(set_attr "type" "negnot")
9175 (set_attr "mode" "SI")])
9177 (define_insn "*negsi2_cmpz_zext"
9179 (compare:CCZ (lshiftrt:DI
9181 (match_operand:DI 1 "register_operand" "0")
9185 (set (match_operand:DI 0 "register_operand" "=r")
9186 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9189 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9191 [(set_attr "type" "negnot")
9192 (set_attr "mode" "SI")])
9194 (define_expand "neghi2"
9195 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9196 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9197 (clobber (reg:CC 17))])]
9198 "TARGET_HIMODE_MATH"
9199 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9201 (define_insn "*neghi2_1"
9202 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9203 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9204 (clobber (reg:CC 17))]
9205 "ix86_unary_operator_ok (NEG, HImode, operands)"
9207 [(set_attr "type" "negnot")
9208 (set_attr "mode" "HI")])
9210 (define_insn "*neghi2_cmpz"
9212 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9214 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9215 (neg:HI (match_dup 1)))]
9216 "ix86_unary_operator_ok (NEG, HImode, operands)"
9218 [(set_attr "type" "negnot")
9219 (set_attr "mode" "HI")])
9221 (define_expand "negqi2"
9222 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9223 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9224 (clobber (reg:CC 17))])]
9225 "TARGET_QIMODE_MATH"
9226 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9228 (define_insn "*negqi2_1"
9229 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9230 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9231 (clobber (reg:CC 17))]
9232 "ix86_unary_operator_ok (NEG, QImode, operands)"
9234 [(set_attr "type" "negnot")
9235 (set_attr "mode" "QI")])
9237 (define_insn "*negqi2_cmpz"
9239 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9241 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9242 (neg:QI (match_dup 1)))]
9243 "ix86_unary_operator_ok (NEG, QImode, operands)"
9245 [(set_attr "type" "negnot")
9246 (set_attr "mode" "QI")])
9248 ;; Changing of sign for FP values is doable using integer unit too.
9250 (define_expand "negsf2"
9251 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9252 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9253 (clobber (reg:CC 17))])]
9257 /* In case operand is in memory, we will not use SSE. */
9258 if (memory_operand (operands[0], VOIDmode)
9259 && rtx_equal_p (operands[0], operands[1]))
9260 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9263 /* Using SSE is tricky, since we need bitwise negation of -0
9265 rtx reg = gen_reg_rtx (SFmode);
9266 rtx dest = operands[0];
9268 operands[1] = force_reg (SFmode, operands[1]);
9269 operands[0] = force_reg (SFmode, operands[0]);
9270 emit_move_insn (reg,
9271 gen_lowpart (SFmode,
9272 gen_int_mode (0x80000000, SImode)));
9273 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9274 if (dest != operands[0])
9275 emit_move_insn (dest, operands[0]);
9279 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9281 (define_insn "negsf2_memory"
9282 [(set (match_operand:SF 0 "memory_operand" "=m")
9283 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9284 (clobber (reg:CC 17))]
9285 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9288 (define_insn "negsf2_ifs"
9289 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9290 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9291 (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x"))
9292 (clobber (reg:CC 17))]
9294 && (reload_in_progress || reload_completed
9295 || (register_operand (operands[0], VOIDmode)
9296 && register_operand (operands[1], VOIDmode)))"
9300 [(set (match_operand:SF 0 "memory_operand" "")
9301 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9302 (use (match_operand:SF 2 "" ""))
9303 (clobber (reg:CC 17))]
9305 [(parallel [(set (match_dup 0)
9306 (neg:SF (match_dup 1)))
9307 (clobber (reg:CC 17))])])
9310 [(set (match_operand:SF 0 "register_operand" "")
9311 (neg:SF (match_operand:SF 1 "register_operand" "")))
9312 (use (match_operand:SF 2 "" ""))
9313 (clobber (reg:CC 17))]
9314 "reload_completed && !SSE_REG_P (operands[0])"
9315 [(parallel [(set (match_dup 0)
9316 (neg:SF (match_dup 1)))
9317 (clobber (reg:CC 17))])])
9320 [(set (match_operand:SF 0 "register_operand" "")
9321 (neg:SF (match_operand:SF 1 "register_operand" "")))
9322 (use (match_operand:SF 2 "register_operand" ""))
9323 (clobber (reg:CC 17))]
9324 "reload_completed && SSE_REG_P (operands[0])"
9325 [(set (subreg:TI (match_dup 0) 0)
9326 (xor:TI (subreg:TI (match_dup 1) 0)
9327 (subreg:TI (match_dup 2) 0)))]
9329 if (operands_match_p (operands[0], operands[2]))
9333 operands[1] = operands[2];
9339 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9340 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9342 (define_insn "*negsf2_if"
9343 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9344 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9345 (clobber (reg:CC 17))]
9346 "TARGET_80387 && !TARGET_SSE
9347 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9351 [(set (match_operand:SF 0 "fp_register_operand" "")
9352 (neg:SF (match_operand:SF 1 "register_operand" "")))
9353 (clobber (reg:CC 17))]
9354 "TARGET_80387 && reload_completed"
9356 (neg:SF (match_dup 1)))]
9360 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9361 (neg:SF (match_operand:SF 1 "register_operand" "")))
9362 (clobber (reg:CC 17))]
9363 "TARGET_80387 && reload_completed"
9364 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9365 (clobber (reg:CC 17))])]
9366 "operands[1] = gen_int_mode (0x80000000, SImode);
9367 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9370 [(set (match_operand 0 "memory_operand" "")
9371 (neg (match_operand 1 "memory_operand" "")))
9372 (clobber (reg:CC 17))]
9373 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9374 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9375 (clobber (reg:CC 17))])]
9377 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9379 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9382 operands[0] = adjust_address (operands[0], QImode, size - 1);
9383 operands[1] = gen_int_mode (0x80, QImode);
9386 (define_expand "negdf2"
9387 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9388 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9389 (clobber (reg:CC 17))])]
9393 /* In case operand is in memory, we will not use SSE. */
9394 if (memory_operand (operands[0], VOIDmode)
9395 && rtx_equal_p (operands[0], operands[1]))
9396 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9399 /* Using SSE is tricky, since we need bitwise negation of -0
9401 rtx reg = gen_reg_rtx (DFmode);
9402 #if HOST_BITS_PER_WIDE_INT >= 64
9403 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9405 rtx imm = immed_double_const (0, 0x80000000, DImode);
9407 rtx dest = operands[0];
9409 operands[1] = force_reg (DFmode, operands[1]);
9410 operands[0] = force_reg (DFmode, operands[0]);
9411 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9412 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9413 if (dest != operands[0])
9414 emit_move_insn (dest, operands[0]);
9418 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9420 (define_insn "negdf2_memory"
9421 [(set (match_operand:DF 0 "memory_operand" "=m")
9422 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9423 (clobber (reg:CC 17))]
9424 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9427 (define_insn "negdf2_ifs"
9428 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9429 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9430 (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
9431 (clobber (reg:CC 17))]
9432 "!TARGET_64BIT && TARGET_SSE2
9433 && (reload_in_progress || reload_completed
9434 || (register_operand (operands[0], VOIDmode)
9435 && register_operand (operands[1], VOIDmode)))"
9438 (define_insn "*negdf2_ifs_rex64"
9439 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf")
9440 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9441 (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
9442 (clobber (reg:CC 17))]
9443 "TARGET_64BIT && TARGET_SSE2
9444 && (reload_in_progress || reload_completed
9445 || (register_operand (operands[0], VOIDmode)
9446 && register_operand (operands[1], VOIDmode)))"
9450 [(set (match_operand:DF 0 "memory_operand" "")
9451 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9452 (use (match_operand:DF 2 "" ""))
9453 (clobber (reg:CC 17))]
9455 [(parallel [(set (match_dup 0)
9456 (neg:DF (match_dup 1)))
9457 (clobber (reg:CC 17))])])
9460 [(set (match_operand:DF 0 "register_operand" "")
9461 (neg:DF (match_operand:DF 1 "register_operand" "")))
9462 (use (match_operand:DF 2 "" ""))
9463 (clobber (reg:CC 17))]
9464 "reload_completed && !SSE_REG_P (operands[0])
9465 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9466 [(parallel [(set (match_dup 0)
9467 (neg:DF (match_dup 1)))
9468 (clobber (reg:CC 17))])])
9471 [(set (match_operand:DF 0 "register_operand" "")
9472 (neg:DF (match_operand:DF 1 "register_operand" "")))
9473 (use (match_operand:DF 2 "" ""))
9474 (clobber (reg:CC 17))]
9475 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9476 [(parallel [(set (match_dup 0)
9477 (xor:DI (match_dup 1) (match_dup 2)))
9478 (clobber (reg:CC 17))])]
9479 "operands[0] = gen_lowpart (DImode, operands[0]);
9480 operands[1] = gen_lowpart (DImode, operands[1]);
9481 operands[2] = gen_lowpart (DImode, operands[2]);")
9484 [(set (match_operand:DF 0 "register_operand" "")
9485 (neg:DF (match_operand:DF 1 "register_operand" "")))
9486 (use (match_operand:DF 2 "register_operand" ""))
9487 (clobber (reg:CC 17))]
9488 "reload_completed && SSE_REG_P (operands[0])"
9489 [(set (subreg:TI (match_dup 0) 0)
9490 (xor:TI (subreg:TI (match_dup 1) 0)
9491 (subreg:TI (match_dup 2) 0)))]
9493 if (operands_match_p (operands[0], operands[2]))
9497 operands[1] = operands[2];
9502 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9503 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9505 (define_insn "*negdf2_if"
9506 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9507 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9508 (clobber (reg:CC 17))]
9509 "!TARGET_64BIT && TARGET_80387
9510 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9513 ;; FIXME: We should to allow integer registers here. Problem is that
9514 ;; we need another scratch register to get constant from.
9515 ;; Forcing constant to mem if no register available in peep2 should be
9516 ;; safe even for PIC mode, because of RIP relative addressing.
9517 (define_insn "*negdf2_if_rex64"
9518 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9519 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9520 (clobber (reg:CC 17))]
9521 "TARGET_64BIT && TARGET_80387
9522 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9526 [(set (match_operand:DF 0 "fp_register_operand" "")
9527 (neg:DF (match_operand:DF 1 "register_operand" "")))
9528 (clobber (reg:CC 17))]
9529 "TARGET_80387 && reload_completed"
9531 (neg:DF (match_dup 1)))]
9535 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9536 (neg:DF (match_operand:DF 1 "register_operand" "")))
9537 (clobber (reg:CC 17))]
9538 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9539 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9540 (clobber (reg:CC 17))])]
9541 "operands[4] = gen_int_mode (0x80000000, SImode);
9542 split_di (operands+0, 1, operands+2, operands+3);")
9544 (define_expand "negxf2"
9545 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9546 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9547 (clobber (reg:CC 17))])]
9548 "!TARGET_64BIT && TARGET_80387"
9549 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9551 (define_expand "negtf2"
9552 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9553 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9554 (clobber (reg:CC 17))])]
9556 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
9558 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9559 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9561 (define_insn "*negxf2_if"
9562 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9563 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9564 (clobber (reg:CC 17))]
9565 "!TARGET_64BIT && TARGET_80387
9566 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9570 [(set (match_operand:XF 0 "fp_register_operand" "")
9571 (neg:XF (match_operand:XF 1 "register_operand" "")))
9572 (clobber (reg:CC 17))]
9573 "TARGET_80387 && reload_completed"
9575 (neg:XF (match_dup 1)))]
9579 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
9580 (neg:XF (match_operand:XF 1 "register_operand" "")))
9581 (clobber (reg:CC 17))]
9582 "TARGET_80387 && reload_completed"
9583 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9584 (clobber (reg:CC 17))])]
9585 "operands[1] = GEN_INT (0x8000);
9586 operands[0] = gen_rtx_REG (SImode,
9587 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9589 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9590 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9592 (define_insn "*negtf2_if"
9593 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
9594 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
9595 (clobber (reg:CC 17))]
9596 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
9600 [(set (match_operand:TF 0 "fp_register_operand" "")
9601 (neg:TF (match_operand:TF 1 "register_operand" "")))
9602 (clobber (reg:CC 17))]
9603 "TARGET_80387 && reload_completed"
9605 (neg:TF (match_dup 1)))]
9609 [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
9610 (neg:TF (match_operand:TF 1 "register_operand" "")))
9611 (clobber (reg:CC 17))]
9612 "TARGET_80387 && reload_completed"
9613 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9614 (clobber (reg:CC 17))])]
9615 "operands[1] = GEN_INT (0x8000);
9616 operands[0] = gen_rtx_REG (SImode,
9617 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9619 ;; Conditionize these after reload. If they matches before reload, we
9620 ;; lose the clobber and ability to use integer instructions.
9622 (define_insn "*negsf2_1"
9623 [(set (match_operand:SF 0 "register_operand" "=f")
9624 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9625 "TARGET_80387 && reload_completed"
9627 [(set_attr "type" "fsgn")
9628 (set_attr "mode" "SF")
9629 (set_attr "ppro_uops" "few")])
9631 (define_insn "*negdf2_1"
9632 [(set (match_operand:DF 0 "register_operand" "=f")
9633 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9634 "TARGET_80387 && reload_completed"
9636 [(set_attr "type" "fsgn")
9637 (set_attr "mode" "DF")
9638 (set_attr "ppro_uops" "few")])
9640 (define_insn "*negextendsfdf2"
9641 [(set (match_operand:DF 0 "register_operand" "=f")
9642 (neg:DF (float_extend:DF
9643 (match_operand:SF 1 "register_operand" "0"))))]
9646 [(set_attr "type" "fsgn")
9647 (set_attr "mode" "DF")
9648 (set_attr "ppro_uops" "few")])
9650 (define_insn "*negxf2_1"
9651 [(set (match_operand:XF 0 "register_operand" "=f")
9652 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9653 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9655 [(set_attr "type" "fsgn")
9656 (set_attr "mode" "XF")
9657 (set_attr "ppro_uops" "few")])
9659 (define_insn "*negextenddfxf2"
9660 [(set (match_operand:XF 0 "register_operand" "=f")
9661 (neg:XF (float_extend:XF
9662 (match_operand:DF 1 "register_operand" "0"))))]
9663 "!TARGET_64BIT && TARGET_80387"
9665 [(set_attr "type" "fsgn")
9666 (set_attr "mode" "XF")
9667 (set_attr "ppro_uops" "few")])
9669 (define_insn "*negextendsfxf2"
9670 [(set (match_operand:XF 0 "register_operand" "=f")
9671 (neg:XF (float_extend:XF
9672 (match_operand:SF 1 "register_operand" "0"))))]
9673 "!TARGET_64BIT && TARGET_80387"
9675 [(set_attr "type" "fsgn")
9676 (set_attr "mode" "XF")
9677 (set_attr "ppro_uops" "few")])
9679 (define_insn "*negtf2_1"
9680 [(set (match_operand:TF 0 "register_operand" "=f")
9681 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
9682 "TARGET_80387 && reload_completed"
9684 [(set_attr "type" "fsgn")
9685 (set_attr "mode" "XF")
9686 (set_attr "ppro_uops" "few")])
9688 (define_insn "*negextenddftf2"
9689 [(set (match_operand:TF 0 "register_operand" "=f")
9690 (neg:TF (float_extend:TF
9691 (match_operand:DF 1 "register_operand" "0"))))]
9694 [(set_attr "type" "fsgn")
9695 (set_attr "mode" "XF")
9696 (set_attr "ppro_uops" "few")])
9698 (define_insn "*negextendsftf2"
9699 [(set (match_operand:TF 0 "register_operand" "=f")
9700 (neg:TF (float_extend:TF
9701 (match_operand:SF 1 "register_operand" "0"))))]
9704 [(set_attr "type" "fsgn")
9705 (set_attr "mode" "XF")
9706 (set_attr "ppro_uops" "few")])
9708 ;; Absolute value instructions
9710 (define_expand "abssf2"
9711 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9712 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9713 (clobber (reg:CC 17))])]
9717 /* In case operand is in memory, we will not use SSE. */
9718 if (memory_operand (operands[0], VOIDmode)
9719 && rtx_equal_p (operands[0], operands[1]))
9720 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9723 /* Using SSE is tricky, since we need bitwise negation of -0
9725 rtx reg = gen_reg_rtx (SFmode);
9726 rtx dest = operands[0];
9728 operands[1] = force_reg (SFmode, operands[1]);
9729 operands[0] = force_reg (SFmode, operands[0]);
9730 emit_move_insn (reg,
9731 gen_lowpart (SFmode,
9732 gen_int_mode (0x80000000, SImode)));
9733 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
9734 if (dest != operands[0])
9735 emit_move_insn (dest, operands[0]);
9739 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
9741 (define_insn "abssf2_memory"
9742 [(set (match_operand:SF 0 "memory_operand" "=m")
9743 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
9744 (clobber (reg:CC 17))]
9745 "ix86_unary_operator_ok (ABS, SFmode, operands)"
9748 (define_insn "abssf2_ifs"
9749 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf")
9750 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0")))
9751 (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x"))
9752 (clobber (reg:CC 17))]
9754 && (reload_in_progress || reload_completed
9755 || (register_operand (operands[0], VOIDmode)
9756 && register_operand (operands[1], VOIDmode)))"
9760 [(set (match_operand:SF 0 "memory_operand" "")
9761 (abs:SF (match_operand:SF 1 "memory_operand" "")))
9762 (use (match_operand:SF 2 "" ""))
9763 (clobber (reg:CC 17))]
9765 [(parallel [(set (match_dup 0)
9766 (abs:SF (match_dup 1)))
9767 (clobber (reg:CC 17))])])
9770 [(set (match_operand:SF 0 "register_operand" "")
9771 (abs:SF (match_operand:SF 1 "register_operand" "")))
9772 (use (match_operand:SF 2 "" ""))
9773 (clobber (reg:CC 17))]
9774 "reload_completed && !SSE_REG_P (operands[0])"
9775 [(parallel [(set (match_dup 0)
9776 (abs:SF (match_dup 1)))
9777 (clobber (reg:CC 17))])])
9780 [(set (match_operand:SF 0 "register_operand" "")
9781 (abs:SF (match_operand:SF 1 "register_operand" "")))
9782 (use (match_operand:SF 2 "register_operand" ""))
9783 (clobber (reg:CC 17))]
9784 "reload_completed && SSE_REG_P (operands[0])"
9785 [(set (subreg:TI (match_dup 0) 0)
9786 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9787 (subreg:TI (match_dup 1) 0)))])
9789 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9790 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9792 (define_insn "*abssf2_if"
9793 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9794 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9795 (clobber (reg:CC 17))]
9796 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
9800 [(set (match_operand:SF 0 "fp_register_operand" "")
9801 (abs:SF (match_operand:SF 1 "register_operand" "")))
9802 (clobber (reg:CC 17))]
9805 (abs:SF (match_dup 1)))]
9809 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9810 (abs:SF (match_operand:SF 1 "register_operand" "")))
9811 (clobber (reg:CC 17))]
9812 "TARGET_80387 && reload_completed"
9813 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
9814 (clobber (reg:CC 17))])]
9815 "operands[1] = gen_int_mode (~0x80000000, SImode);
9816 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
9819 [(set (match_operand 0 "memory_operand" "")
9820 (abs (match_operand 1 "memory_operand" "")))
9821 (clobber (reg:CC 17))]
9822 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9823 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
9824 (clobber (reg:CC 17))])]
9826 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9828 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9831 operands[0] = adjust_address (operands[0], QImode, size - 1);
9832 operands[1] = gen_int_mode (~0x80, QImode);
9835 (define_expand "absdf2"
9836 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9837 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9838 (clobber (reg:CC 17))])]
9842 /* In case operand is in memory, we will not use SSE. */
9843 if (memory_operand (operands[0], VOIDmode)
9844 && rtx_equal_p (operands[0], operands[1]))
9845 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
9848 /* Using SSE is tricky, since we need bitwise negation of -0
9850 rtx reg = gen_reg_rtx (DFmode);
9851 #if HOST_BITS_PER_WIDE_INT >= 64
9852 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9854 rtx imm = immed_double_const (0, 0x80000000, DImode);
9856 rtx dest = operands[0];
9858 operands[1] = force_reg (DFmode, operands[1]);
9859 operands[0] = force_reg (DFmode, operands[0]);
9860 emit_move_insn (reg, gen_lowpart (DFmode, imm));
9861 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
9862 if (dest != operands[0])
9863 emit_move_insn (dest, operands[0]);
9867 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
9869 (define_insn "absdf2_memory"
9870 [(set (match_operand:DF 0 "memory_operand" "=m")
9871 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
9872 (clobber (reg:CC 17))]
9873 "ix86_unary_operator_ok (ABS, DFmode, operands)"
9876 (define_insn "absdf2_ifs"
9877 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf")
9878 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
9879 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
9880 (clobber (reg:CC 17))]
9881 "!TARGET_64BIT && TARGET_SSE2
9882 && (reload_in_progress || reload_completed
9883 || (register_operand (operands[0], VOIDmode)
9884 && register_operand (operands[1], VOIDmode)))"
9887 (define_insn "*absdf2_ifs_rex64"
9888 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr")
9889 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
9890 (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
9891 (clobber (reg:CC 17))]
9892 "TARGET_64BIT && TARGET_SSE2
9893 && (reload_in_progress || reload_completed
9894 || (register_operand (operands[0], VOIDmode)
9895 && register_operand (operands[1], VOIDmode)))"
9899 [(set (match_operand:DF 0 "memory_operand" "")
9900 (abs:DF (match_operand:DF 1 "memory_operand" "")))
9901 (use (match_operand:DF 2 "" ""))
9902 (clobber (reg:CC 17))]
9904 [(parallel [(set (match_dup 0)
9905 (abs:DF (match_dup 1)))
9906 (clobber (reg:CC 17))])])
9909 [(set (match_operand:DF 0 "register_operand" "")
9910 (abs:DF (match_operand:DF 1 "register_operand" "")))
9911 (use (match_operand:DF 2 "" ""))
9912 (clobber (reg:CC 17))]
9913 "reload_completed && !SSE_REG_P (operands[0])"
9914 [(parallel [(set (match_dup 0)
9915 (abs:DF (match_dup 1)))
9916 (clobber (reg:CC 17))])])
9919 [(set (match_operand:DF 0 "register_operand" "")
9920 (abs:DF (match_operand:DF 1 "register_operand" "")))
9921 (use (match_operand:DF 2 "register_operand" ""))
9922 (clobber (reg:CC 17))]
9923 "reload_completed && SSE_REG_P (operands[0])"
9924 [(set (subreg:TI (match_dup 0) 0)
9925 (and:TI (not:TI (subreg:TI (match_dup 2) 0))
9926 (subreg:TI (match_dup 1) 0)))])
9929 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9930 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9932 (define_insn "*absdf2_if"
9933 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9934 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9935 (clobber (reg:CC 17))]
9936 "!TARGET_64BIT && TARGET_80387
9937 && ix86_unary_operator_ok (ABS, DFmode, operands)"
9940 ;; FIXME: We should to allow integer registers here. Problem is that
9941 ;; we need another scratch register to get constant from.
9942 ;; Forcing constant to mem if no register available in peep2 should be
9943 ;; safe even for PIC mode, because of RIP relative addressing.
9944 (define_insn "*absdf2_if_rex64"
9945 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9946 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9947 (clobber (reg:CC 17))]
9948 "TARGET_64BIT && TARGET_80387
9949 && ix86_unary_operator_ok (ABS, DFmode, operands)"
9953 [(set (match_operand:DF 0 "fp_register_operand" "")
9954 (abs:DF (match_operand:DF 1 "register_operand" "")))
9955 (clobber (reg:CC 17))]
9956 "TARGET_80387 && reload_completed"
9958 (abs:DF (match_dup 1)))]
9962 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9963 (abs:DF (match_operand:DF 1 "register_operand" "")))
9964 (clobber (reg:CC 17))]
9965 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9966 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
9967 (clobber (reg:CC 17))])]
9968 "operands[4] = gen_int_mode (~0x80000000, SImode);
9969 split_di (operands+0, 1, operands+2, operands+3);")
9971 (define_expand "absxf2"
9972 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9973 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9974 (clobber (reg:CC 17))])]
9975 "!TARGET_64BIT && TARGET_80387"
9976 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
9978 (define_expand "abstf2"
9979 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9980 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
9981 (clobber (reg:CC 17))])]
9983 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
9985 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9986 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9988 (define_insn "*absxf2_if"
9989 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9990 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9991 (clobber (reg:CC 17))]
9992 "!TARGET_64BIT && TARGET_80387
9993 && ix86_unary_operator_ok (ABS, XFmode, operands)"
9997 [(set (match_operand:XF 0 "fp_register_operand" "")
9998 (abs:XF (match_operand:XF 1 "register_operand" "")))
9999 (clobber (reg:CC 17))]
10000 "TARGET_80387 && reload_completed"
10001 [(set (match_dup 0)
10002 (abs:XF (match_dup 1)))]
10006 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10007 (abs:XF (match_operand:XF 1 "register_operand" "")))
10008 (clobber (reg:CC 17))]
10009 "TARGET_80387 && reload_completed"
10010 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10011 (clobber (reg:CC 17))])]
10012 "operands[1] = GEN_INT (~0x8000);
10013 operands[0] = gen_rtx_REG (SImode,
10014 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10016 (define_insn "*abstf2_if"
10017 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10018 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10019 (clobber (reg:CC 17))]
10020 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10024 [(set (match_operand:TF 0 "fp_register_operand" "")
10025 (abs:TF (match_operand:TF 1 "register_operand" "")))
10026 (clobber (reg:CC 17))]
10027 "TARGET_80387 && reload_completed"
10028 [(set (match_dup 0)
10029 (abs:TF (match_dup 1)))]
10033 [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
10034 (abs:TF (match_operand:TF 1 "register_operand" "")))
10035 (clobber (reg:CC 17))]
10036 "TARGET_80387 && reload_completed"
10037 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10038 (clobber (reg:CC 17))])]
10039 "operands[1] = GEN_INT (~0x8000);
10040 operands[0] = gen_rtx_REG (SImode,
10041 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10043 (define_insn "*abssf2_1"
10044 [(set (match_operand:SF 0 "register_operand" "=f")
10045 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10046 "TARGET_80387 && reload_completed"
10048 [(set_attr "type" "fsgn")
10049 (set_attr "mode" "SF")])
10051 (define_insn "*absdf2_1"
10052 [(set (match_operand:DF 0 "register_operand" "=f")
10053 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10054 "TARGET_80387 && reload_completed"
10056 [(set_attr "type" "fsgn")
10057 (set_attr "mode" "DF")])
10059 (define_insn "*absextendsfdf2"
10060 [(set (match_operand:DF 0 "register_operand" "=f")
10061 (abs:DF (float_extend:DF
10062 (match_operand:SF 1 "register_operand" "0"))))]
10065 [(set_attr "type" "fsgn")
10066 (set_attr "mode" "DF")])
10068 (define_insn "*absxf2_1"
10069 [(set (match_operand:XF 0 "register_operand" "=f")
10070 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10071 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10073 [(set_attr "type" "fsgn")
10074 (set_attr "mode" "DF")])
10076 (define_insn "*absextenddfxf2"
10077 [(set (match_operand:XF 0 "register_operand" "=f")
10078 (abs:XF (float_extend:XF
10079 (match_operand:DF 1 "register_operand" "0"))))]
10080 "!TARGET_64BIT && TARGET_80387"
10082 [(set_attr "type" "fsgn")
10083 (set_attr "mode" "XF")])
10085 (define_insn "*absextendsfxf2"
10086 [(set (match_operand:XF 0 "register_operand" "=f")
10087 (abs:XF (float_extend:XF
10088 (match_operand:SF 1 "register_operand" "0"))))]
10089 "!TARGET_64BIT && TARGET_80387"
10091 [(set_attr "type" "fsgn")
10092 (set_attr "mode" "XF")])
10094 (define_insn "*abstf2_1"
10095 [(set (match_operand:TF 0 "register_operand" "=f")
10096 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10097 "TARGET_80387 && reload_completed"
10099 [(set_attr "type" "fsgn")
10100 (set_attr "mode" "DF")])
10102 (define_insn "*absextenddftf2"
10103 [(set (match_operand:TF 0 "register_operand" "=f")
10104 (abs:TF (float_extend:TF
10105 (match_operand:DF 1 "register_operand" "0"))))]
10108 [(set_attr "type" "fsgn")
10109 (set_attr "mode" "XF")])
10111 (define_insn "*absextendsftf2"
10112 [(set (match_operand:TF 0 "register_operand" "=f")
10113 (abs:TF (float_extend:TF
10114 (match_operand:SF 1 "register_operand" "0"))))]
10117 [(set_attr "type" "fsgn")
10118 (set_attr "mode" "XF")])
10120 ;; One complement instructions
10122 (define_expand "one_cmpldi2"
10123 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10124 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10126 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10128 (define_insn "*one_cmpldi2_1_rex64"
10129 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10130 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10131 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10133 [(set_attr "type" "negnot")
10134 (set_attr "mode" "DI")])
10136 (define_insn "*one_cmpldi2_2_rex64"
10138 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10140 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10141 (not:DI (match_dup 1)))]
10142 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10143 && ix86_unary_operator_ok (NOT, DImode, operands)"
10145 [(set_attr "type" "alu1")
10146 (set_attr "mode" "DI")])
10150 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10152 (set (match_operand:DI 0 "nonimmediate_operand" "")
10153 (not:DI (match_dup 1)))]
10154 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10155 [(parallel [(set (reg:CCNO 17)
10156 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10159 (xor:DI (match_dup 1) (const_int -1)))])]
10162 (define_expand "one_cmplsi2"
10163 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10164 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10166 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10168 (define_insn "*one_cmplsi2_1"
10169 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10170 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10171 "ix86_unary_operator_ok (NOT, SImode, operands)"
10173 [(set_attr "type" "negnot")
10174 (set_attr "mode" "SI")])
10176 ;; ??? Currently never generated - xor is used instead.
10177 (define_insn "*one_cmplsi2_1_zext"
10178 [(set (match_operand:DI 0 "register_operand" "=r")
10179 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10180 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10182 [(set_attr "type" "negnot")
10183 (set_attr "mode" "SI")])
10185 (define_insn "*one_cmplsi2_2"
10187 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10189 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10190 (not:SI (match_dup 1)))]
10191 "ix86_match_ccmode (insn, CCNOmode)
10192 && ix86_unary_operator_ok (NOT, SImode, operands)"
10194 [(set_attr "type" "alu1")
10195 (set_attr "mode" "SI")])
10199 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10201 (set (match_operand:SI 0 "nonimmediate_operand" "")
10202 (not:SI (match_dup 1)))]
10203 "ix86_match_ccmode (insn, CCNOmode)"
10204 [(parallel [(set (reg:CCNO 17)
10205 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10208 (xor:SI (match_dup 1) (const_int -1)))])]
10211 ;; ??? Currently never generated - xor is used instead.
10212 (define_insn "*one_cmplsi2_2_zext"
10214 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10216 (set (match_operand:DI 0 "register_operand" "=r")
10217 (zero_extend:DI (not:SI (match_dup 1))))]
10218 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10219 && ix86_unary_operator_ok (NOT, SImode, operands)"
10221 [(set_attr "type" "alu1")
10222 (set_attr "mode" "SI")])
10226 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10228 (set (match_operand:DI 0 "register_operand" "")
10229 (zero_extend:DI (not:SI (match_dup 1))))]
10230 "ix86_match_ccmode (insn, CCNOmode)"
10231 [(parallel [(set (reg:CCNO 17)
10232 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10235 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10238 (define_expand "one_cmplhi2"
10239 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10240 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10241 "TARGET_HIMODE_MATH"
10242 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10244 (define_insn "*one_cmplhi2_1"
10245 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10246 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10247 "ix86_unary_operator_ok (NOT, HImode, operands)"
10249 [(set_attr "type" "negnot")
10250 (set_attr "mode" "HI")])
10252 (define_insn "*one_cmplhi2_2"
10254 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10256 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10257 (not:HI (match_dup 1)))]
10258 "ix86_match_ccmode (insn, CCNOmode)
10259 && ix86_unary_operator_ok (NEG, HImode, operands)"
10261 [(set_attr "type" "alu1")
10262 (set_attr "mode" "HI")])
10266 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10268 (set (match_operand:HI 0 "nonimmediate_operand" "")
10269 (not:HI (match_dup 1)))]
10270 "ix86_match_ccmode (insn, CCNOmode)"
10271 [(parallel [(set (reg:CCNO 17)
10272 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10275 (xor:HI (match_dup 1) (const_int -1)))])]
10278 ;; %%% Potential partial reg stall on alternative 1. What to do?
10279 (define_expand "one_cmplqi2"
10280 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10281 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10282 "TARGET_QIMODE_MATH"
10283 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10285 (define_insn "*one_cmplqi2_1"
10286 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10287 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10288 "ix86_unary_operator_ok (NOT, QImode, operands)"
10292 [(set_attr "type" "negnot")
10293 (set_attr "mode" "QI,SI")])
10295 (define_insn "*one_cmplqi2_2"
10297 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10299 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10300 (not:QI (match_dup 1)))]
10301 "ix86_match_ccmode (insn, CCNOmode)
10302 && ix86_unary_operator_ok (NOT, QImode, operands)"
10304 [(set_attr "type" "alu1")
10305 (set_attr "mode" "QI")])
10309 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10311 (set (match_operand:QI 0 "nonimmediate_operand" "")
10312 (not:QI (match_dup 1)))]
10313 "ix86_match_ccmode (insn, CCNOmode)"
10314 [(parallel [(set (reg:CCNO 17)
10315 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10318 (xor:QI (match_dup 1) (const_int -1)))])]
10321 ;; Arithmetic shift instructions
10323 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10324 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10325 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10326 ;; from the assembler input.
10328 ;; This instruction shifts the target reg/mem as usual, but instead of
10329 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10330 ;; is a left shift double, bits are taken from the high order bits of
10331 ;; reg, else if the insn is a shift right double, bits are taken from the
10332 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10333 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10335 ;; Since sh[lr]d does not change the `reg' operand, that is done
10336 ;; separately, making all shifts emit pairs of shift double and normal
10337 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10338 ;; support a 63 bit shift, each shift where the count is in a reg expands
10339 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10341 ;; If the shift count is a constant, we need never emit more than one
10342 ;; shift pair, instead using moves and sign extension for counts greater
10345 (define_expand "ashldi3"
10346 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10347 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10348 (match_operand:QI 2 "nonmemory_operand" "")))
10349 (clobber (reg:CC 17))])]
10352 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10354 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10357 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10361 (define_insn "*ashldi3_1_rex64"
10362 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10363 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10364 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10365 (clobber (reg:CC 17))]
10366 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10368 switch (get_attr_type (insn))
10371 if (operands[2] != const1_rtx)
10373 if (!rtx_equal_p (operands[0], operands[1]))
10375 return "add{q}\t{%0, %0|%0, %0}";
10378 if (GET_CODE (operands[2]) != CONST_INT
10379 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10381 operands[1] = gen_rtx_MULT (DImode, operands[1],
10382 GEN_INT (1 << INTVAL (operands[2])));
10383 return "lea{q}\t{%a1, %0|%0, %a1}";
10386 if (REG_P (operands[2]))
10387 return "sal{q}\t{%b2, %0|%0, %b2}";
10388 else if (GET_CODE (operands[2]) == CONST_INT
10389 && INTVAL (operands[2]) == 1
10390 && (TARGET_SHIFT1 || optimize_size))
10391 return "sal{q}\t%0";
10393 return "sal{q}\t{%2, %0|%0, %2}";
10396 [(set (attr "type")
10397 (cond [(eq_attr "alternative" "1")
10398 (const_string "lea")
10399 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10401 (match_operand 0 "register_operand" ""))
10402 (match_operand 2 "const1_operand" ""))
10403 (const_string "alu")
10405 (const_string "ishift")))
10406 (set_attr "mode" "DI")])
10408 ;; Convert lea to the lea pattern to avoid flags dependency.
10410 [(set (match_operand:DI 0 "register_operand" "")
10411 (ashift:DI (match_operand:DI 1 "register_operand" "")
10412 (match_operand:QI 2 "immediate_operand" "")))
10413 (clobber (reg:CC 17))]
10414 "TARGET_64BIT && reload_completed
10415 && true_regnum (operands[0]) != true_regnum (operands[1])"
10416 [(set (match_dup 0)
10417 (mult:DI (match_dup 1)
10419 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10421 ;; This pattern can't accept a variable shift count, since shifts by
10422 ;; zero don't affect the flags. We assume that shifts by constant
10423 ;; zero are optimized away.
10424 (define_insn "*ashldi3_cmp_rex64"
10427 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10428 (match_operand:QI 2 "immediate_operand" "e"))
10430 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10431 (ashift:DI (match_dup 1) (match_dup 2)))]
10432 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10433 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10435 switch (get_attr_type (insn))
10438 if (operands[2] != const1_rtx)
10440 return "add{q}\t{%0, %0|%0, %0}";
10443 if (REG_P (operands[2]))
10444 return "sal{q}\t{%b2, %0|%0, %b2}";
10445 else if (GET_CODE (operands[2]) == CONST_INT
10446 && INTVAL (operands[2]) == 1
10447 && (TARGET_SHIFT1 || optimize_size))
10448 return "sal{q}\t%0";
10450 return "sal{q}\t{%2, %0|%0, %2}";
10453 [(set (attr "type")
10454 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10456 (match_operand 0 "register_operand" ""))
10457 (match_operand 2 "const1_operand" ""))
10458 (const_string "alu")
10460 (const_string "ishift")))
10461 (set_attr "mode" "DI")])
10463 (define_insn "ashldi3_1"
10464 [(set (match_operand:DI 0 "register_operand" "=r")
10465 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10466 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10467 (clobber (match_scratch:SI 3 "=&r"))
10468 (clobber (reg:CC 17))]
10469 "!TARGET_64BIT && TARGET_CMOVE"
10471 [(set_attr "type" "multi")])
10473 (define_insn "*ashldi3_2"
10474 [(set (match_operand:DI 0 "register_operand" "=r")
10475 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10476 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10477 (clobber (reg:CC 17))]
10480 [(set_attr "type" "multi")])
10483 [(set (match_operand:DI 0 "register_operand" "")
10484 (ashift:DI (match_operand:DI 1 "register_operand" "")
10485 (match_operand:QI 2 "nonmemory_operand" "")))
10486 (clobber (match_scratch:SI 3 ""))
10487 (clobber (reg:CC 17))]
10488 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10490 "ix86_split_ashldi (operands, operands[3]); DONE;")
10493 [(set (match_operand:DI 0 "register_operand" "")
10494 (ashift:DI (match_operand:DI 1 "register_operand" "")
10495 (match_operand:QI 2 "nonmemory_operand" "")))
10496 (clobber (reg:CC 17))]
10497 "!TARGET_64BIT && reload_completed"
10499 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10501 (define_insn "x86_shld_1"
10502 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10503 (ior:SI (ashift:SI (match_dup 0)
10504 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10505 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10506 (minus:QI (const_int 32) (match_dup 2)))))
10507 (clobber (reg:CC 17))]
10510 shld{l}\t{%2, %1, %0|%0, %1, %2}
10511 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10512 [(set_attr "type" "ishift")
10513 (set_attr "prefix_0f" "1")
10514 (set_attr "mode" "SI")
10515 (set_attr "pent_pair" "np")
10516 (set_attr "athlon_decode" "vector")
10517 (set_attr "ppro_uops" "few")])
10519 (define_expand "x86_shift_adj_1"
10521 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10524 (set (match_operand:SI 0 "register_operand" "")
10525 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10526 (match_operand:SI 1 "register_operand" "")
10529 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10530 (match_operand:SI 3 "register_operand" "r")
10535 (define_expand "x86_shift_adj_2"
10536 [(use (match_operand:SI 0 "register_operand" ""))
10537 (use (match_operand:SI 1 "register_operand" ""))
10538 (use (match_operand:QI 2 "register_operand" ""))]
10541 rtx label = gen_label_rtx ();
10544 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10546 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10547 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10548 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10549 gen_rtx_LABEL_REF (VOIDmode, label),
10551 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10552 JUMP_LABEL (tmp) = label;
10554 emit_move_insn (operands[0], operands[1]);
10555 emit_move_insn (operands[1], const0_rtx);
10557 emit_label (label);
10558 LABEL_NUSES (label) = 1;
10563 (define_expand "ashlsi3"
10564 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10565 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10566 (match_operand:QI 2 "nonmemory_operand" "")))
10567 (clobber (reg:CC 17))]
10569 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10571 (define_insn "*ashlsi3_1"
10572 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10573 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10574 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10575 (clobber (reg:CC 17))]
10576 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10578 switch (get_attr_type (insn))
10581 if (operands[2] != const1_rtx)
10583 if (!rtx_equal_p (operands[0], operands[1]))
10585 return "add{l}\t{%0, %0|%0, %0}";
10591 if (REG_P (operands[2]))
10592 return "sal{l}\t{%b2, %0|%0, %b2}";
10593 else if (GET_CODE (operands[2]) == CONST_INT
10594 && INTVAL (operands[2]) == 1
10595 && (TARGET_SHIFT1 || optimize_size))
10596 return "sal{l}\t%0";
10598 return "sal{l}\t{%2, %0|%0, %2}";
10601 [(set (attr "type")
10602 (cond [(eq_attr "alternative" "1")
10603 (const_string "lea")
10604 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10606 (match_operand 0 "register_operand" ""))
10607 (match_operand 2 "const1_operand" ""))
10608 (const_string "alu")
10610 (const_string "ishift")))
10611 (set_attr "mode" "SI")])
10613 ;; Convert lea to the lea pattern to avoid flags dependency.
10615 [(set (match_operand 0 "register_operand" "")
10616 (ashift (match_operand 1 "index_register_operand" "")
10617 (match_operand:QI 2 "const_int_operand" "")))
10618 (clobber (reg:CC 17))]
10620 && true_regnum (operands[0]) != true_regnum (operands[1])"
10624 operands[0] = gen_lowpart (SImode, operands[0]);
10625 operands[1] = gen_lowpart (Pmode, operands[1]);
10626 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10627 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10628 if (Pmode != SImode)
10629 pat = gen_rtx_SUBREG (SImode, pat, 0);
10630 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10634 ;; Rare case of shifting RSP is handled by generating move and shift
10636 [(set (match_operand 0 "register_operand" "")
10637 (ashift (match_operand 1 "register_operand" "")
10638 (match_operand:QI 2 "const_int_operand" "")))
10639 (clobber (reg:CC 17))]
10641 && true_regnum (operands[0]) != true_regnum (operands[1])"
10645 emit_move_insn (operands[1], operands[0]);
10646 pat = gen_rtx_SET (VOIDmode, operands[0],
10647 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10648 operands[0], operands[2]));
10649 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10650 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10654 (define_insn "*ashlsi3_1_zext"
10655 [(set (match_operand:DI 0 "register_operand" "=r,r")
10656 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10657 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10658 (clobber (reg:CC 17))]
10659 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10661 switch (get_attr_type (insn))
10664 if (operands[2] != const1_rtx)
10666 return "add{l}\t{%k0, %k0|%k0, %k0}";
10672 if (REG_P (operands[2]))
10673 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10674 else if (GET_CODE (operands[2]) == CONST_INT
10675 && INTVAL (operands[2]) == 1
10676 && (TARGET_SHIFT1 || optimize_size))
10677 return "sal{l}\t%k0";
10679 return "sal{l}\t{%2, %k0|%k0, %2}";
10682 [(set (attr "type")
10683 (cond [(eq_attr "alternative" "1")
10684 (const_string "lea")
10685 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10687 (match_operand 2 "const1_operand" ""))
10688 (const_string "alu")
10690 (const_string "ishift")))
10691 (set_attr "mode" "SI")])
10693 ;; Convert lea to the lea pattern to avoid flags dependency.
10695 [(set (match_operand:DI 0 "register_operand" "")
10696 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10697 (match_operand:QI 2 "const_int_operand" ""))))
10698 (clobber (reg:CC 17))]
10700 && true_regnum (operands[0]) != true_regnum (operands[1])"
10701 [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
10703 operands[1] = gen_lowpart (Pmode, operands[1]);
10704 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10707 ;; This pattern can't accept a variable shift count, since shifts by
10708 ;; zero don't affect the flags. We assume that shifts by constant
10709 ;; zero are optimized away.
10710 (define_insn "*ashlsi3_cmp"
10713 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10714 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10716 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10717 (ashift:SI (match_dup 1) (match_dup 2)))]
10718 "ix86_match_ccmode (insn, CCGOCmode)
10719 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10721 switch (get_attr_type (insn))
10724 if (operands[2] != const1_rtx)
10726 return "add{l}\t{%0, %0|%0, %0}";
10729 if (REG_P (operands[2]))
10730 return "sal{l}\t{%b2, %0|%0, %b2}";
10731 else if (GET_CODE (operands[2]) == CONST_INT
10732 && INTVAL (operands[2]) == 1
10733 && (TARGET_SHIFT1 || optimize_size))
10734 return "sal{l}\t%0";
10736 return "sal{l}\t{%2, %0|%0, %2}";
10739 [(set (attr "type")
10740 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10742 (match_operand 0 "register_operand" ""))
10743 (match_operand 2 "const1_operand" ""))
10744 (const_string "alu")
10746 (const_string "ishift")))
10747 (set_attr "mode" "SI")])
10749 (define_insn "*ashlsi3_cmp_zext"
10752 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10753 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10755 (set (match_operand:DI 0 "register_operand" "=r")
10756 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10757 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10758 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10760 switch (get_attr_type (insn))
10763 if (operands[2] != const1_rtx)
10765 return "add{l}\t{%k0, %k0|%k0, %k0}";
10768 if (REG_P (operands[2]))
10769 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10770 else if (GET_CODE (operands[2]) == CONST_INT
10771 && INTVAL (operands[2]) == 1
10772 && (TARGET_SHIFT1 || optimize_size))
10773 return "sal{l}\t%k0";
10775 return "sal{l}\t{%2, %k0|%k0, %2}";
10778 [(set (attr "type")
10779 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10781 (match_operand 2 "const1_operand" ""))
10782 (const_string "alu")
10784 (const_string "ishift")))
10785 (set_attr "mode" "SI")])
10787 (define_expand "ashlhi3"
10788 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10789 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10790 (match_operand:QI 2 "nonmemory_operand" "")))
10791 (clobber (reg:CC 17))]
10792 "TARGET_HIMODE_MATH"
10793 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10795 (define_insn "*ashlhi3_1_lea"
10796 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10797 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
10798 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10799 (clobber (reg:CC 17))]
10800 "!TARGET_PARTIAL_REG_STALL
10801 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10803 switch (get_attr_type (insn))
10808 if (operands[2] != const1_rtx)
10810 return "add{w}\t{%0, %0|%0, %0}";
10813 if (REG_P (operands[2]))
10814 return "sal{w}\t{%b2, %0|%0, %b2}";
10815 else if (GET_CODE (operands[2]) == CONST_INT
10816 && INTVAL (operands[2]) == 1
10817 && (TARGET_SHIFT1 || optimize_size))
10818 return "sal{w}\t%0";
10820 return "sal{w}\t{%2, %0|%0, %2}";
10823 [(set (attr "type")
10824 (cond [(eq_attr "alternative" "1")
10825 (const_string "lea")
10826 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10828 (match_operand 0 "register_operand" ""))
10829 (match_operand 2 "const1_operand" ""))
10830 (const_string "alu")
10832 (const_string "ishift")))
10833 (set_attr "mode" "HI,SI")])
10835 (define_insn "*ashlhi3_1"
10836 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10837 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10838 (match_operand:QI 2 "nonmemory_operand" "cI")))
10839 (clobber (reg:CC 17))]
10840 "TARGET_PARTIAL_REG_STALL
10841 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10843 switch (get_attr_type (insn))
10846 if (operands[2] != const1_rtx)
10848 return "add{w}\t{%0, %0|%0, %0}";
10851 if (REG_P (operands[2]))
10852 return "sal{w}\t{%b2, %0|%0, %b2}";
10853 else if (GET_CODE (operands[2]) == CONST_INT
10854 && INTVAL (operands[2]) == 1
10855 && (TARGET_SHIFT1 || optimize_size))
10856 return "sal{w}\t%0";
10858 return "sal{w}\t{%2, %0|%0, %2}";
10861 [(set (attr "type")
10862 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10864 (match_operand 0 "register_operand" ""))
10865 (match_operand 2 "const1_operand" ""))
10866 (const_string "alu")
10868 (const_string "ishift")))
10869 (set_attr "mode" "HI")])
10871 ;; This pattern can't accept a variable shift count, since shifts by
10872 ;; zero don't affect the flags. We assume that shifts by constant
10873 ;; zero are optimized away.
10874 (define_insn "*ashlhi3_cmp"
10877 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10878 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10880 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10881 (ashift:HI (match_dup 1) (match_dup 2)))]
10882 "ix86_match_ccmode (insn, CCGOCmode)
10883 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10885 switch (get_attr_type (insn))
10888 if (operands[2] != const1_rtx)
10890 return "add{w}\t{%0, %0|%0, %0}";
10893 if (REG_P (operands[2]))
10894 return "sal{w}\t{%b2, %0|%0, %b2}";
10895 else if (GET_CODE (operands[2]) == CONST_INT
10896 && INTVAL (operands[2]) == 1
10897 && (TARGET_SHIFT1 || optimize_size))
10898 return "sal{w}\t%0";
10900 return "sal{w}\t{%2, %0|%0, %2}";
10903 [(set (attr "type")
10904 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10906 (match_operand 0 "register_operand" ""))
10907 (match_operand 2 "const1_operand" ""))
10908 (const_string "alu")
10910 (const_string "ishift")))
10911 (set_attr "mode" "HI")])
10913 (define_expand "ashlqi3"
10914 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10915 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10916 (match_operand:QI 2 "nonmemory_operand" "")))
10917 (clobber (reg:CC 17))]
10918 "TARGET_QIMODE_MATH"
10919 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10921 ;; %%% Potential partial reg stall on alternative 2. What to do?
10923 (define_insn "*ashlqi3_1_lea"
10924 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10925 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
10926 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10927 (clobber (reg:CC 17))]
10928 "!TARGET_PARTIAL_REG_STALL
10929 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10931 switch (get_attr_type (insn))
10936 if (operands[2] != const1_rtx)
10938 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10939 return "add{l}\t{%k0, %k0|%k0, %k0}";
10941 return "add{b}\t{%0, %0|%0, %0}";
10944 if (REG_P (operands[2]))
10946 if (get_attr_mode (insn) == MODE_SI)
10947 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10949 return "sal{b}\t{%b2, %0|%0, %b2}";
10951 else if (GET_CODE (operands[2]) == CONST_INT
10952 && INTVAL (operands[2]) == 1
10953 && (TARGET_SHIFT1 || optimize_size))
10955 if (get_attr_mode (insn) == MODE_SI)
10956 return "sal{l}\t%0";
10958 return "sal{b}\t%0";
10962 if (get_attr_mode (insn) == MODE_SI)
10963 return "sal{l}\t{%2, %k0|%k0, %2}";
10965 return "sal{b}\t{%2, %0|%0, %2}";
10969 [(set (attr "type")
10970 (cond [(eq_attr "alternative" "2")
10971 (const_string "lea")
10972 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10974 (match_operand 0 "register_operand" ""))
10975 (match_operand 2 "const1_operand" ""))
10976 (const_string "alu")
10978 (const_string "ishift")))
10979 (set_attr "mode" "QI,SI,SI")])
10981 (define_insn "*ashlqi3_1"
10982 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10983 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
10984 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
10985 (clobber (reg:CC 17))]
10986 "TARGET_PARTIAL_REG_STALL
10987 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10989 switch (get_attr_type (insn))
10992 if (operands[2] != const1_rtx)
10994 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10995 return "add{l}\t{%k0, %k0|%k0, %k0}";
10997 return "add{b}\t{%0, %0|%0, %0}";
11000 if (REG_P (operands[2]))
11002 if (get_attr_mode (insn) == MODE_SI)
11003 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11005 return "sal{b}\t{%b2, %0|%0, %b2}";
11007 else if (GET_CODE (operands[2]) == CONST_INT
11008 && INTVAL (operands[2]) == 1
11009 && (TARGET_SHIFT1 || optimize_size))
11011 if (get_attr_mode (insn) == MODE_SI)
11012 return "sal{l}\t%0";
11014 return "sal{b}\t%0";
11018 if (get_attr_mode (insn) == MODE_SI)
11019 return "sal{l}\t{%2, %k0|%k0, %2}";
11021 return "sal{b}\t{%2, %0|%0, %2}";
11025 [(set (attr "type")
11026 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11028 (match_operand 0 "register_operand" ""))
11029 (match_operand 2 "const1_operand" ""))
11030 (const_string "alu")
11032 (const_string "ishift")))
11033 (set_attr "mode" "QI,SI")])
11035 ;; This pattern can't accept a variable shift count, since shifts by
11036 ;; zero don't affect the flags. We assume that shifts by constant
11037 ;; zero are optimized away.
11038 (define_insn "*ashlqi3_cmp"
11041 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11042 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11044 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11045 (ashift:QI (match_dup 1) (match_dup 2)))]
11046 "ix86_match_ccmode (insn, CCGOCmode)
11047 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11049 switch (get_attr_type (insn))
11052 if (operands[2] != const1_rtx)
11054 return "add{b}\t{%0, %0|%0, %0}";
11057 if (REG_P (operands[2]))
11058 return "sal{b}\t{%b2, %0|%0, %b2}";
11059 else if (GET_CODE (operands[2]) == CONST_INT
11060 && INTVAL (operands[2]) == 1
11061 && (TARGET_SHIFT1 || optimize_size))
11062 return "sal{b}\t%0";
11064 return "sal{b}\t{%2, %0|%0, %2}";
11067 [(set (attr "type")
11068 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11070 (match_operand 0 "register_operand" ""))
11071 (match_operand 2 "const1_operand" ""))
11072 (const_string "alu")
11074 (const_string "ishift")))
11075 (set_attr "mode" "QI")])
11077 ;; See comment above `ashldi3' about how this works.
11079 (define_expand "ashrdi3"
11080 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11081 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11082 (match_operand:QI 2 "nonmemory_operand" "")))
11083 (clobber (reg:CC 17))])]
11086 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11088 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11091 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11095 (define_insn "ashrdi3_63_rex64"
11096 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11097 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11098 (match_operand:DI 2 "const_int_operand" "i,i")))
11099 (clobber (reg:CC 17))]
11100 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11101 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11104 sar{q}\t{%2, %0|%0, %2}"
11105 [(set_attr "type" "imovx,ishift")
11106 (set_attr "prefix_0f" "0,*")
11107 (set_attr "length_immediate" "0,*")
11108 (set_attr "modrm" "0,1")
11109 (set_attr "mode" "DI")])
11111 (define_insn "*ashrdi3_1_one_bit_rex64"
11112 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11113 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11114 (match_operand:QI 2 "const_int_1_operand" "")))
11115 (clobber (reg:CC 17))]
11116 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11117 && (TARGET_SHIFT1 || optimize_size)"
11119 [(set_attr "type" "ishift")
11120 (set (attr "length")
11121 (if_then_else (match_operand:DI 0 "register_operand" "")
11123 (const_string "*")))])
11125 (define_insn "*ashrdi3_1_rex64"
11126 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11127 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11128 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11129 (clobber (reg:CC 17))]
11130 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11132 sar{q}\t{%2, %0|%0, %2}
11133 sar{q}\t{%b2, %0|%0, %b2}"
11134 [(set_attr "type" "ishift")
11135 (set_attr "mode" "DI")])
11137 ;; This pattern can't accept a variable shift count, since shifts by
11138 ;; zero don't affect the flags. We assume that shifts by constant
11139 ;; zero are optimized away.
11140 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11143 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11144 (match_operand:QI 2 "const_int_1_operand" ""))
11146 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11147 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11148 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11149 && (TARGET_SHIFT1 || optimize_size)
11150 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11152 [(set_attr "type" "ishift")
11153 (set (attr "length")
11154 (if_then_else (match_operand:DI 0 "register_operand" "")
11156 (const_string "*")))])
11158 ;; This pattern can't accept a variable shift count, since shifts by
11159 ;; zero don't affect the flags. We assume that shifts by constant
11160 ;; zero are optimized away.
11161 (define_insn "*ashrdi3_cmp_rex64"
11164 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11165 (match_operand:QI 2 "const_int_operand" "n"))
11167 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11168 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11169 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11170 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11171 "sar{q}\t{%2, %0|%0, %2}"
11172 [(set_attr "type" "ishift")
11173 (set_attr "mode" "DI")])
11176 (define_insn "ashrdi3_1"
11177 [(set (match_operand:DI 0 "register_operand" "=r")
11178 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11179 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11180 (clobber (match_scratch:SI 3 "=&r"))
11181 (clobber (reg:CC 17))]
11182 "!TARGET_64BIT && TARGET_CMOVE"
11184 [(set_attr "type" "multi")])
11186 (define_insn "*ashrdi3_2"
11187 [(set (match_operand:DI 0 "register_operand" "=r")
11188 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11189 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11190 (clobber (reg:CC 17))]
11193 [(set_attr "type" "multi")])
11196 [(set (match_operand:DI 0 "register_operand" "")
11197 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11198 (match_operand:QI 2 "nonmemory_operand" "")))
11199 (clobber (match_scratch:SI 3 ""))
11200 (clobber (reg:CC 17))]
11201 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11203 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11206 [(set (match_operand:DI 0 "register_operand" "")
11207 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11208 (match_operand:QI 2 "nonmemory_operand" "")))
11209 (clobber (reg:CC 17))]
11210 "!TARGET_64BIT && reload_completed"
11212 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11214 (define_insn "x86_shrd_1"
11215 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11216 (ior:SI (ashiftrt:SI (match_dup 0)
11217 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11218 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11219 (minus:QI (const_int 32) (match_dup 2)))))
11220 (clobber (reg:CC 17))]
11223 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11224 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11225 [(set_attr "type" "ishift")
11226 (set_attr "prefix_0f" "1")
11227 (set_attr "pent_pair" "np")
11228 (set_attr "ppro_uops" "few")
11229 (set_attr "mode" "SI")])
11231 (define_expand "x86_shift_adj_3"
11232 [(use (match_operand:SI 0 "register_operand" ""))
11233 (use (match_operand:SI 1 "register_operand" ""))
11234 (use (match_operand:QI 2 "register_operand" ""))]
11237 rtx label = gen_label_rtx ();
11240 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11242 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11243 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11244 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11245 gen_rtx_LABEL_REF (VOIDmode, label),
11247 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11248 JUMP_LABEL (tmp) = label;
11250 emit_move_insn (operands[0], operands[1]);
11251 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11253 emit_label (label);
11254 LABEL_NUSES (label) = 1;
11259 (define_insn "ashrsi3_31"
11260 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11261 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11262 (match_operand:SI 2 "const_int_operand" "i,i")))
11263 (clobber (reg:CC 17))]
11264 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11265 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11268 sar{l}\t{%2, %0|%0, %2}"
11269 [(set_attr "type" "imovx,ishift")
11270 (set_attr "prefix_0f" "0,*")
11271 (set_attr "length_immediate" "0,*")
11272 (set_attr "modrm" "0,1")
11273 (set_attr "mode" "SI")])
11275 (define_insn "*ashrsi3_31_zext"
11276 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11277 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11278 (match_operand:SI 2 "const_int_operand" "i,i"))))
11279 (clobber (reg:CC 17))]
11280 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11281 && INTVAL (operands[2]) == 31
11282 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11285 sar{l}\t{%2, %k0|%k0, %2}"
11286 [(set_attr "type" "imovx,ishift")
11287 (set_attr "prefix_0f" "0,*")
11288 (set_attr "length_immediate" "0,*")
11289 (set_attr "modrm" "0,1")
11290 (set_attr "mode" "SI")])
11292 (define_expand "ashrsi3"
11293 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11294 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11295 (match_operand:QI 2 "nonmemory_operand" "")))
11296 (clobber (reg:CC 17))]
11298 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11300 (define_insn "*ashrsi3_1_one_bit"
11301 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11302 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11303 (match_operand:QI 2 "const_int_1_operand" "")))
11304 (clobber (reg:CC 17))]
11305 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11306 && (TARGET_SHIFT1 || optimize_size)"
11308 [(set_attr "type" "ishift")
11309 (set (attr "length")
11310 (if_then_else (match_operand:SI 0 "register_operand" "")
11312 (const_string "*")))])
11314 (define_insn "*ashrsi3_1_one_bit_zext"
11315 [(set (match_operand:DI 0 "register_operand" "=r")
11316 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11317 (match_operand:QI 2 "const_int_1_operand" ""))))
11318 (clobber (reg:CC 17))]
11319 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11320 && (TARGET_SHIFT1 || optimize_size)"
11322 [(set_attr "type" "ishift")
11323 (set_attr "length" "2")])
11325 (define_insn "*ashrsi3_1"
11326 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11327 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11328 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11329 (clobber (reg:CC 17))]
11330 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11332 sar{l}\t{%2, %0|%0, %2}
11333 sar{l}\t{%b2, %0|%0, %b2}"
11334 [(set_attr "type" "ishift")
11335 (set_attr "mode" "SI")])
11337 (define_insn "*ashrsi3_1_zext"
11338 [(set (match_operand:DI 0 "register_operand" "=r,r")
11339 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11340 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11341 (clobber (reg:CC 17))]
11342 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11344 sar{l}\t{%2, %k0|%k0, %2}
11345 sar{l}\t{%b2, %k0|%k0, %b2}"
11346 [(set_attr "type" "ishift")
11347 (set_attr "mode" "SI")])
11349 ;; This pattern can't accept a variable shift count, since shifts by
11350 ;; zero don't affect the flags. We assume that shifts by constant
11351 ;; zero are optimized away.
11352 (define_insn "*ashrsi3_one_bit_cmp"
11355 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11356 (match_operand:QI 2 "const_int_1_operand" ""))
11358 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11359 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11360 "ix86_match_ccmode (insn, CCGOCmode)
11361 && (TARGET_SHIFT1 || optimize_size)
11362 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11364 [(set_attr "type" "ishift")
11365 (set (attr "length")
11366 (if_then_else (match_operand:SI 0 "register_operand" "")
11368 (const_string "*")))])
11370 (define_insn "*ashrsi3_one_bit_cmp_zext"
11373 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11374 (match_operand:QI 2 "const_int_1_operand" ""))
11376 (set (match_operand:DI 0 "register_operand" "=r")
11377 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11378 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11379 && (TARGET_SHIFT1 || optimize_size)
11380 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11382 [(set_attr "type" "ishift")
11383 (set_attr "length" "2")])
11385 ;; This pattern can't accept a variable shift count, since shifts by
11386 ;; zero don't affect the flags. We assume that shifts by constant
11387 ;; zero are optimized away.
11388 (define_insn "*ashrsi3_cmp"
11391 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11392 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11394 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11395 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11396 "ix86_match_ccmode (insn, CCGOCmode)
11397 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11398 "sar{l}\t{%2, %0|%0, %2}"
11399 [(set_attr "type" "ishift")
11400 (set_attr "mode" "SI")])
11402 (define_insn "*ashrsi3_cmp_zext"
11405 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11406 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11408 (set (match_operand:DI 0 "register_operand" "=r")
11409 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11410 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11411 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11412 "sar{l}\t{%2, %k0|%k0, %2}"
11413 [(set_attr "type" "ishift")
11414 (set_attr "mode" "SI")])
11416 (define_expand "ashrhi3"
11417 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11418 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11419 (match_operand:QI 2 "nonmemory_operand" "")))
11420 (clobber (reg:CC 17))]
11421 "TARGET_HIMODE_MATH"
11422 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11424 (define_insn "*ashrhi3_1_one_bit"
11425 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11426 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11427 (match_operand:QI 2 "const_int_1_operand" "")))
11428 (clobber (reg:CC 17))]
11429 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11430 && (TARGET_SHIFT1 || optimize_size)"
11432 [(set_attr "type" "ishift")
11433 (set (attr "length")
11434 (if_then_else (match_operand 0 "register_operand" "")
11436 (const_string "*")))])
11438 (define_insn "*ashrhi3_1"
11439 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11440 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11441 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11442 (clobber (reg:CC 17))]
11443 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11445 sar{w}\t{%2, %0|%0, %2}
11446 sar{w}\t{%b2, %0|%0, %b2}"
11447 [(set_attr "type" "ishift")
11448 (set_attr "mode" "HI")])
11450 ;; This pattern can't accept a variable shift count, since shifts by
11451 ;; zero don't affect the flags. We assume that shifts by constant
11452 ;; zero are optimized away.
11453 (define_insn "*ashrhi3_one_bit_cmp"
11456 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11457 (match_operand:QI 2 "const_int_1_operand" ""))
11459 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11460 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11461 "ix86_match_ccmode (insn, CCGOCmode)
11462 && (TARGET_SHIFT1 || optimize_size)
11463 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11465 [(set_attr "type" "ishift")
11466 (set (attr "length")
11467 (if_then_else (match_operand 0 "register_operand" "")
11469 (const_string "*")))])
11471 ;; This pattern can't accept a variable shift count, since shifts by
11472 ;; zero don't affect the flags. We assume that shifts by constant
11473 ;; zero are optimized away.
11474 (define_insn "*ashrhi3_cmp"
11477 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11478 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11480 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11481 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11482 "ix86_match_ccmode (insn, CCGOCmode)
11483 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11484 "sar{w}\t{%2, %0|%0, %2}"
11485 [(set_attr "type" "ishift")
11486 (set_attr "mode" "HI")])
11488 (define_expand "ashrqi3"
11489 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11490 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11491 (match_operand:QI 2 "nonmemory_operand" "")))
11492 (clobber (reg:CC 17))]
11493 "TARGET_QIMODE_MATH"
11494 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11496 (define_insn "*ashrqi3_1_one_bit"
11497 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11498 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11499 (match_operand:QI 2 "const_int_1_operand" "")))
11500 (clobber (reg:CC 17))]
11501 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11502 && (TARGET_SHIFT1 || optimize_size)"
11504 [(set_attr "type" "ishift")
11505 (set (attr "length")
11506 (if_then_else (match_operand 0 "register_operand" "")
11508 (const_string "*")))])
11510 (define_insn "*ashrqi3_1_one_bit_slp"
11511 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11512 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11513 (match_operand:QI 2 "const_int_1_operand" "")))
11514 (clobber (reg:CC 17))]
11515 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11516 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11517 && (TARGET_SHIFT1 || optimize_size)"
11519 [(set_attr "type" "ishift")
11520 (set (attr "length")
11521 (if_then_else (match_operand 0 "register_operand" "")
11523 (const_string "*")))])
11525 (define_insn "*ashrqi3_1"
11526 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11527 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11528 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11529 (clobber (reg:CC 17))]
11530 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11532 sar{b}\t{%2, %0|%0, %2}
11533 sar{b}\t{%b2, %0|%0, %b2}"
11534 [(set_attr "type" "ishift")
11535 (set_attr "mode" "QI")])
11537 (define_insn "*ashrqi3_1_slp"
11538 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11539 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11540 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11541 (clobber (reg:CC 17))]
11542 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11543 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11545 sar{b}\t{%2, %0|%0, %2}
11546 sar{b}\t{%b2, %0|%0, %b2}"
11547 [(set_attr "type" "ishift")
11548 (set_attr "mode" "QI")])
11550 ;; This pattern can't accept a variable shift count, since shifts by
11551 ;; zero don't affect the flags. We assume that shifts by constant
11552 ;; zero are optimized away.
11553 (define_insn "*ashrqi3_one_bit_cmp"
11556 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11557 (match_operand:QI 2 "const_int_1_operand" "I"))
11559 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11560 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11561 "ix86_match_ccmode (insn, CCGOCmode)
11562 && (TARGET_SHIFT1 || optimize_size)
11563 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11565 [(set_attr "type" "ishift")
11566 (set (attr "length")
11567 (if_then_else (match_operand 0 "register_operand" "")
11569 (const_string "*")))])
11571 ;; This pattern can't accept a variable shift count, since shifts by
11572 ;; zero don't affect the flags. We assume that shifts by constant
11573 ;; zero are optimized away.
11574 (define_insn "*ashrqi3_cmp"
11577 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11578 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11580 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11581 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11582 "ix86_match_ccmode (insn, CCGOCmode)
11583 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11584 "sar{b}\t{%2, %0|%0, %2}"
11585 [(set_attr "type" "ishift")
11586 (set_attr "mode" "QI")])
11588 ;; Logical shift instructions
11590 ;; See comment above `ashldi3' about how this works.
11592 (define_expand "lshrdi3"
11593 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11594 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11595 (match_operand:QI 2 "nonmemory_operand" "")))
11596 (clobber (reg:CC 17))])]
11599 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11601 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11604 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11608 (define_insn "*lshrdi3_1_one_bit_rex64"
11609 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11610 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11611 (match_operand:QI 2 "const_int_1_operand" "")))
11612 (clobber (reg:CC 17))]
11613 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11614 && (TARGET_SHIFT1 || optimize_size)"
11616 [(set_attr "type" "ishift")
11617 (set (attr "length")
11618 (if_then_else (match_operand:DI 0 "register_operand" "")
11620 (const_string "*")))])
11622 (define_insn "*lshrdi3_1_rex64"
11623 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11624 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11625 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11626 (clobber (reg:CC 17))]
11627 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11629 shr{q}\t{%2, %0|%0, %2}
11630 shr{q}\t{%b2, %0|%0, %b2}"
11631 [(set_attr "type" "ishift")
11632 (set_attr "mode" "DI")])
11634 ;; This pattern can't accept a variable shift count, since shifts by
11635 ;; zero don't affect the flags. We assume that shifts by constant
11636 ;; zero are optimized away.
11637 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11640 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11641 (match_operand:QI 2 "const_int_1_operand" ""))
11643 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11644 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11645 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11646 && (TARGET_SHIFT1 || optimize_size)
11647 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11649 [(set_attr "type" "ishift")
11650 (set (attr "length")
11651 (if_then_else (match_operand:DI 0 "register_operand" "")
11653 (const_string "*")))])
11655 ;; This pattern can't accept a variable shift count, since shifts by
11656 ;; zero don't affect the flags. We assume that shifts by constant
11657 ;; zero are optimized away.
11658 (define_insn "*lshrdi3_cmp_rex64"
11661 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11662 (match_operand:QI 2 "const_int_operand" "e"))
11664 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11665 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11666 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11667 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11668 "shr{q}\t{%2, %0|%0, %2}"
11669 [(set_attr "type" "ishift")
11670 (set_attr "mode" "DI")])
11672 (define_insn "lshrdi3_1"
11673 [(set (match_operand:DI 0 "register_operand" "=r")
11674 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11675 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11676 (clobber (match_scratch:SI 3 "=&r"))
11677 (clobber (reg:CC 17))]
11678 "!TARGET_64BIT && TARGET_CMOVE"
11680 [(set_attr "type" "multi")])
11682 (define_insn "*lshrdi3_2"
11683 [(set (match_operand:DI 0 "register_operand" "=r")
11684 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11685 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11686 (clobber (reg:CC 17))]
11689 [(set_attr "type" "multi")])
11692 [(set (match_operand:DI 0 "register_operand" "")
11693 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11694 (match_operand:QI 2 "nonmemory_operand" "")))
11695 (clobber (match_scratch:SI 3 ""))
11696 (clobber (reg:CC 17))]
11697 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11699 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11702 [(set (match_operand:DI 0 "register_operand" "")
11703 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11704 (match_operand:QI 2 "nonmemory_operand" "")))
11705 (clobber (reg:CC 17))]
11706 "!TARGET_64BIT && reload_completed"
11708 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11710 (define_expand "lshrsi3"
11711 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11712 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11713 (match_operand:QI 2 "nonmemory_operand" "")))
11714 (clobber (reg:CC 17))]
11716 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11718 (define_insn "*lshrsi3_1_one_bit"
11719 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11720 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11721 (match_operand:QI 2 "const_int_1_operand" "")))
11722 (clobber (reg:CC 17))]
11723 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11724 && (TARGET_SHIFT1 || optimize_size)"
11726 [(set_attr "type" "ishift")
11727 (set (attr "length")
11728 (if_then_else (match_operand:SI 0 "register_operand" "")
11730 (const_string "*")))])
11732 (define_insn "*lshrsi3_1_one_bit_zext"
11733 [(set (match_operand:DI 0 "register_operand" "=r")
11734 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11735 (match_operand:QI 2 "const_int_1_operand" "")))
11736 (clobber (reg:CC 17))]
11737 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11738 && (TARGET_SHIFT1 || optimize_size)"
11740 [(set_attr "type" "ishift")
11741 (set_attr "length" "2")])
11743 (define_insn "*lshrsi3_1"
11744 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11745 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11746 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11747 (clobber (reg:CC 17))]
11748 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11750 shr{l}\t{%2, %0|%0, %2}
11751 shr{l}\t{%b2, %0|%0, %b2}"
11752 [(set_attr "type" "ishift")
11753 (set_attr "mode" "SI")])
11755 (define_insn "*lshrsi3_1_zext"
11756 [(set (match_operand:DI 0 "register_operand" "=r,r")
11758 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11759 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11760 (clobber (reg:CC 17))]
11761 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11763 shr{l}\t{%2, %k0|%k0, %2}
11764 shr{l}\t{%b2, %k0|%k0, %b2}"
11765 [(set_attr "type" "ishift")
11766 (set_attr "mode" "SI")])
11768 ;; This pattern can't accept a variable shift count, since shifts by
11769 ;; zero don't affect the flags. We assume that shifts by constant
11770 ;; zero are optimized away.
11771 (define_insn "*lshrsi3_one_bit_cmp"
11774 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11775 (match_operand:QI 2 "const_int_1_operand" ""))
11777 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11778 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11779 "ix86_match_ccmode (insn, CCGOCmode)
11780 && (TARGET_SHIFT1 || optimize_size)
11781 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11783 [(set_attr "type" "ishift")
11784 (set (attr "length")
11785 (if_then_else (match_operand:SI 0 "register_operand" "")
11787 (const_string "*")))])
11789 (define_insn "*lshrsi3_cmp_one_bit_zext"
11792 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11793 (match_operand:QI 2 "const_int_1_operand" ""))
11795 (set (match_operand:DI 0 "register_operand" "=r")
11796 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11797 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11798 && (TARGET_SHIFT1 || optimize_size)
11799 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11801 [(set_attr "type" "ishift")
11802 (set_attr "length" "2")])
11804 ;; This pattern can't accept a variable shift count, since shifts by
11805 ;; zero don't affect the flags. We assume that shifts by constant
11806 ;; zero are optimized away.
11807 (define_insn "*lshrsi3_cmp"
11810 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11811 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11813 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11814 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11815 "ix86_match_ccmode (insn, CCGOCmode)
11816 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11817 "shr{l}\t{%2, %0|%0, %2}"
11818 [(set_attr "type" "ishift")
11819 (set_attr "mode" "SI")])
11821 (define_insn "*lshrsi3_cmp_zext"
11824 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11825 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11827 (set (match_operand:DI 0 "register_operand" "=r")
11828 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11829 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11830 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11831 "shr{l}\t{%2, %k0|%k0, %2}"
11832 [(set_attr "type" "ishift")
11833 (set_attr "mode" "SI")])
11835 (define_expand "lshrhi3"
11836 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11837 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11838 (match_operand:QI 2 "nonmemory_operand" "")))
11839 (clobber (reg:CC 17))]
11840 "TARGET_HIMODE_MATH"
11841 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11843 (define_insn "*lshrhi3_1_one_bit"
11844 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11845 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11846 (match_operand:QI 2 "const_int_1_operand" "")))
11847 (clobber (reg:CC 17))]
11848 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11849 && (TARGET_SHIFT1 || optimize_size)"
11851 [(set_attr "type" "ishift")
11852 (set (attr "length")
11853 (if_then_else (match_operand 0 "register_operand" "")
11855 (const_string "*")))])
11857 (define_insn "*lshrhi3_1"
11858 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11859 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11860 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11861 (clobber (reg:CC 17))]
11862 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11864 shr{w}\t{%2, %0|%0, %2}
11865 shr{w}\t{%b2, %0|%0, %b2}"
11866 [(set_attr "type" "ishift")
11867 (set_attr "mode" "HI")])
11869 ;; This pattern can't accept a variable shift count, since shifts by
11870 ;; zero don't affect the flags. We assume that shifts by constant
11871 ;; zero are optimized away.
11872 (define_insn "*lshrhi3_one_bit_cmp"
11875 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11876 (match_operand:QI 2 "const_int_1_operand" ""))
11878 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11879 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11880 "ix86_match_ccmode (insn, CCGOCmode)
11881 && (TARGET_SHIFT1 || optimize_size)
11882 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11884 [(set_attr "type" "ishift")
11885 (set (attr "length")
11886 (if_then_else (match_operand:SI 0 "register_operand" "")
11888 (const_string "*")))])
11890 ;; This pattern can't accept a variable shift count, since shifts by
11891 ;; zero don't affect the flags. We assume that shifts by constant
11892 ;; zero are optimized away.
11893 (define_insn "*lshrhi3_cmp"
11896 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11897 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11899 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11900 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11901 "ix86_match_ccmode (insn, CCGOCmode)
11902 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11903 "shr{w}\t{%2, %0|%0, %2}"
11904 [(set_attr "type" "ishift")
11905 (set_attr "mode" "HI")])
11907 (define_expand "lshrqi3"
11908 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11909 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11910 (match_operand:QI 2 "nonmemory_operand" "")))
11911 (clobber (reg:CC 17))]
11912 "TARGET_QIMODE_MATH"
11913 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11915 (define_insn "*lshrqi3_1_one_bit"
11916 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11917 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11918 (match_operand:QI 2 "const_int_1_operand" "")))
11919 (clobber (reg:CC 17))]
11920 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11921 && (TARGET_SHIFT1 || optimize_size)"
11923 [(set_attr "type" "ishift")
11924 (set (attr "length")
11925 (if_then_else (match_operand 0 "register_operand" "")
11927 (const_string "*")))])
11929 (define_insn "*lshrqi3_1_one_bit_slp"
11930 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11931 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11932 (match_operand:QI 2 "const_int_1_operand" "")))
11933 (clobber (reg:CC 17))]
11934 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11935 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11936 && (TARGET_SHIFT1 || optimize_size)"
11938 [(set_attr "type" "ishift")
11939 (set (attr "length")
11940 (if_then_else (match_operand 0 "register_operand" "")
11942 (const_string "*")))])
11944 (define_insn "*lshrqi3_1"
11945 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11946 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11947 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11948 (clobber (reg:CC 17))]
11949 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11951 shr{b}\t{%2, %0|%0, %2}
11952 shr{b}\t{%b2, %0|%0, %b2}"
11953 [(set_attr "type" "ishift")
11954 (set_attr "mode" "QI")])
11956 (define_insn "*lshrqi3_1_slp"
11957 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11958 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11959 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11960 (clobber (reg:CC 17))]
11961 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11962 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11964 shr{b}\t{%2, %0|%0, %2}
11965 shr{b}\t{%b2, %0|%0, %b2}"
11966 [(set_attr "type" "ishift")
11967 (set_attr "mode" "QI")])
11969 ;; This pattern can't accept a variable shift count, since shifts by
11970 ;; zero don't affect the flags. We assume that shifts by constant
11971 ;; zero are optimized away.
11972 (define_insn "*lshrqi2_one_bit_cmp"
11975 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11976 (match_operand:QI 2 "const_int_1_operand" ""))
11978 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11979 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11980 "ix86_match_ccmode (insn, CCGOCmode)
11981 && (TARGET_SHIFT1 || optimize_size)
11982 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11984 [(set_attr "type" "ishift")
11985 (set (attr "length")
11986 (if_then_else (match_operand:SI 0 "register_operand" "")
11988 (const_string "*")))])
11990 ;; This pattern can't accept a variable shift count, since shifts by
11991 ;; zero don't affect the flags. We assume that shifts by constant
11992 ;; zero are optimized away.
11993 (define_insn "*lshrqi2_cmp"
11996 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11997 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11999 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12000 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12001 "ix86_match_ccmode (insn, CCGOCmode)
12002 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12003 "shr{b}\t{%2, %0|%0, %2}"
12004 [(set_attr "type" "ishift")
12005 (set_attr "mode" "QI")])
12007 ;; Rotate instructions
12009 (define_expand "rotldi3"
12010 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12011 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12012 (match_operand:QI 2 "nonmemory_operand" "")))
12013 (clobber (reg:CC 17))]
12015 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12017 (define_insn "*rotlsi3_1_one_bit_rex64"
12018 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12019 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12020 (match_operand:QI 2 "const_int_1_operand" "")))
12021 (clobber (reg:CC 17))]
12022 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12023 && (TARGET_SHIFT1 || optimize_size)"
12025 [(set_attr "type" "rotate")
12026 (set (attr "length")
12027 (if_then_else (match_operand:DI 0 "register_operand" "")
12029 (const_string "*")))])
12031 (define_insn "*rotldi3_1_rex64"
12032 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12033 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12034 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12035 (clobber (reg:CC 17))]
12036 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12038 rol{q}\t{%2, %0|%0, %2}
12039 rol{q}\t{%b2, %0|%0, %b2}"
12040 [(set_attr "type" "rotate")
12041 (set_attr "mode" "DI")])
12043 (define_expand "rotlsi3"
12044 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12045 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12046 (match_operand:QI 2 "nonmemory_operand" "")))
12047 (clobber (reg:CC 17))]
12049 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12051 (define_insn "*rotlsi3_1_one_bit"
12052 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12053 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12054 (match_operand:QI 2 "const_int_1_operand" "")))
12055 (clobber (reg:CC 17))]
12056 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12057 && (TARGET_SHIFT1 || optimize_size)"
12059 [(set_attr "type" "rotate")
12060 (set (attr "length")
12061 (if_then_else (match_operand:SI 0 "register_operand" "")
12063 (const_string "*")))])
12065 (define_insn "*rotlsi3_1_one_bit_zext"
12066 [(set (match_operand:DI 0 "register_operand" "=r")
12068 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12069 (match_operand:QI 2 "const_int_1_operand" ""))))
12070 (clobber (reg:CC 17))]
12071 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12072 && (TARGET_SHIFT1 || optimize_size)"
12074 [(set_attr "type" "rotate")
12075 (set_attr "length" "2")])
12077 (define_insn "*rotlsi3_1"
12078 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12079 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12080 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12081 (clobber (reg:CC 17))]
12082 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12084 rol{l}\t{%2, %0|%0, %2}
12085 rol{l}\t{%b2, %0|%0, %b2}"
12086 [(set_attr "type" "rotate")
12087 (set_attr "mode" "SI")])
12089 (define_insn "*rotlsi3_1_zext"
12090 [(set (match_operand:DI 0 "register_operand" "=r,r")
12092 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12093 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12094 (clobber (reg:CC 17))]
12095 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12097 rol{l}\t{%2, %k0|%k0, %2}
12098 rol{l}\t{%b2, %k0|%k0, %b2}"
12099 [(set_attr "type" "rotate")
12100 (set_attr "mode" "SI")])
12102 (define_expand "rotlhi3"
12103 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12104 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12105 (match_operand:QI 2 "nonmemory_operand" "")))
12106 (clobber (reg:CC 17))]
12107 "TARGET_HIMODE_MATH"
12108 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12110 (define_insn "*rotlhi3_1_one_bit"
12111 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12112 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12113 (match_operand:QI 2 "const_int_1_operand" "")))
12114 (clobber (reg:CC 17))]
12115 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12116 && (TARGET_SHIFT1 || optimize_size)"
12118 [(set_attr "type" "rotate")
12119 (set (attr "length")
12120 (if_then_else (match_operand 0 "register_operand" "")
12122 (const_string "*")))])
12124 (define_insn "*rotlhi3_1"
12125 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12126 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12127 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12128 (clobber (reg:CC 17))]
12129 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12131 rol{w}\t{%2, %0|%0, %2}
12132 rol{w}\t{%b2, %0|%0, %b2}"
12133 [(set_attr "type" "rotate")
12134 (set_attr "mode" "HI")])
12136 (define_expand "rotlqi3"
12137 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12138 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12139 (match_operand:QI 2 "nonmemory_operand" "")))
12140 (clobber (reg:CC 17))]
12141 "TARGET_QIMODE_MATH"
12142 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12144 (define_insn "*rotlqi3_1_one_bit_slp"
12145 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12146 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12147 (match_operand:QI 2 "const_int_1_operand" "")))
12148 (clobber (reg:CC 17))]
12149 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12150 && ix86_binary_operator_ok (ROTATE, QImode, operands)
12151 && (TARGET_SHIFT1 || optimize_size)"
12153 [(set_attr "type" "rotate")
12154 (set (attr "length")
12155 (if_then_else (match_operand 0 "register_operand" "")
12157 (const_string "*")))])
12159 (define_insn "*rotlqi3_1_one_bit"
12160 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12161 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12162 (match_operand:QI 2 "const_int_1_operand" "")))
12163 (clobber (reg:CC 17))]
12164 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12165 && (TARGET_SHIFT1 || optimize_size)"
12167 [(set_attr "type" "rotate")
12168 (set (attr "length")
12169 (if_then_else (match_operand 0 "register_operand" "")
12171 (const_string "*")))])
12173 (define_insn "*rotlqi3_1_slp"
12174 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12175 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12176 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12177 (clobber (reg:CC 17))]
12178 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12179 && ix86_binary_operator_ok (ROTATE, QImode, operands)"
12181 rol{b}\t{%2, %0|%0, %2}
12182 rol{b}\t{%b2, %0|%0, %b2}"
12183 [(set_attr "type" "rotate")
12184 (set_attr "mode" "QI")])
12186 (define_insn "*rotlqi3_1"
12187 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12188 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12189 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12190 (clobber (reg:CC 17))]
12191 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12193 rol{b}\t{%2, %0|%0, %2}
12194 rol{b}\t{%b2, %0|%0, %b2}"
12195 [(set_attr "type" "rotate")
12196 (set_attr "mode" "QI")])
12198 (define_expand "rotrdi3"
12199 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12200 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12201 (match_operand:QI 2 "nonmemory_operand" "")))
12202 (clobber (reg:CC 17))]
12204 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12206 (define_insn "*rotrdi3_1_one_bit_rex64"
12207 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12208 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12209 (match_operand:QI 2 "const_int_1_operand" "")))
12210 (clobber (reg:CC 17))]
12211 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12212 && (TARGET_SHIFT1 || optimize_size)"
12214 [(set_attr "type" "rotate")
12215 (set (attr "length")
12216 (if_then_else (match_operand:DI 0 "register_operand" "")
12218 (const_string "*")))])
12220 (define_insn "*rotrdi3_1_rex64"
12221 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12222 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12223 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12224 (clobber (reg:CC 17))]
12225 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12227 ror{q}\t{%2, %0|%0, %2}
12228 ror{q}\t{%b2, %0|%0, %b2}"
12229 [(set_attr "type" "rotate")
12230 (set_attr "mode" "DI")])
12232 (define_expand "rotrsi3"
12233 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12234 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12235 (match_operand:QI 2 "nonmemory_operand" "")))
12236 (clobber (reg:CC 17))]
12238 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12240 (define_insn "*rotrsi3_1_one_bit"
12241 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12242 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12243 (match_operand:QI 2 "const_int_1_operand" "")))
12244 (clobber (reg:CC 17))]
12245 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12246 && (TARGET_SHIFT1 || optimize_size)"
12248 [(set_attr "type" "rotate")
12249 (set (attr "length")
12250 (if_then_else (match_operand:SI 0 "register_operand" "")
12252 (const_string "*")))])
12254 (define_insn "*rotrsi3_1_one_bit_zext"
12255 [(set (match_operand:DI 0 "register_operand" "=r")
12257 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12258 (match_operand:QI 2 "const_int_1_operand" ""))))
12259 (clobber (reg:CC 17))]
12260 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12261 && (TARGET_SHIFT1 || optimize_size)"
12263 [(set_attr "type" "rotate")
12264 (set (attr "length")
12265 (if_then_else (match_operand:SI 0 "register_operand" "")
12267 (const_string "*")))])
12269 (define_insn "*rotrsi3_1"
12270 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12271 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12272 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12273 (clobber (reg:CC 17))]
12274 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12276 ror{l}\t{%2, %0|%0, %2}
12277 ror{l}\t{%b2, %0|%0, %b2}"
12278 [(set_attr "type" "rotate")
12279 (set_attr "mode" "SI")])
12281 (define_insn "*rotrsi3_1_zext"
12282 [(set (match_operand:DI 0 "register_operand" "=r,r")
12284 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12285 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12286 (clobber (reg:CC 17))]
12287 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12289 ror{l}\t{%2, %k0|%k0, %2}
12290 ror{l}\t{%b2, %k0|%k0, %b2}"
12291 [(set_attr "type" "rotate")
12292 (set_attr "mode" "SI")])
12294 (define_expand "rotrhi3"
12295 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12296 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12297 (match_operand:QI 2 "nonmemory_operand" "")))
12298 (clobber (reg:CC 17))]
12299 "TARGET_HIMODE_MATH"
12300 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12302 (define_insn "*rotrhi3_one_bit"
12303 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12304 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12305 (match_operand:QI 2 "const_int_1_operand" "")))
12306 (clobber (reg:CC 17))]
12307 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12308 && (TARGET_SHIFT1 || optimize_size)"
12310 [(set_attr "type" "rotate")
12311 (set (attr "length")
12312 (if_then_else (match_operand 0 "register_operand" "")
12314 (const_string "*")))])
12316 (define_insn "*rotrhi3"
12317 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12318 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12319 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12320 (clobber (reg:CC 17))]
12321 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12323 ror{w}\t{%2, %0|%0, %2}
12324 ror{w}\t{%b2, %0|%0, %b2}"
12325 [(set_attr "type" "rotate")
12326 (set_attr "mode" "HI")])
12328 (define_expand "rotrqi3"
12329 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12330 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12331 (match_operand:QI 2 "nonmemory_operand" "")))
12332 (clobber (reg:CC 17))]
12333 "TARGET_QIMODE_MATH"
12334 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12336 (define_insn "*rotrqi3_1_one_bit"
12337 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12338 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12339 (match_operand:QI 2 "const_int_1_operand" "")))
12340 (clobber (reg:CC 17))]
12341 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12342 && (TARGET_SHIFT1 || optimize_size)"
12344 [(set_attr "type" "rotate")
12345 (set (attr "length")
12346 (if_then_else (match_operand 0 "register_operand" "")
12348 (const_string "*")))])
12350 (define_insn "*rotrqi3_1_one_bit_slp"
12351 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12352 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12353 (match_operand:QI 2 "const_int_1_operand" "")))
12354 (clobber (reg:CC 17))]
12355 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12356 && ix86_binary_operator_ok (ROTATERT, QImode, operands)
12357 && (TARGET_SHIFT1 || optimize_size)"
12359 [(set_attr "type" "rotate")
12360 (set (attr "length")
12361 (if_then_else (match_operand 0 "register_operand" "")
12363 (const_string "*")))])
12365 (define_insn "*rotrqi3_1"
12366 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12367 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12368 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12369 (clobber (reg:CC 17))]
12370 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12372 ror{b}\t{%2, %0|%0, %2}
12373 ror{b}\t{%b2, %0|%0, %b2}"
12374 [(set_attr "type" "rotate")
12375 (set_attr "mode" "QI")])
12377 (define_insn "*rotrqi3_1_slp"
12378 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12379 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12380 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12381 (clobber (reg:CC 17))]
12382 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12383 && ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12385 ror{b}\t{%2, %0|%0, %2}
12386 ror{b}\t{%b2, %0|%0, %b2}"
12387 [(set_attr "type" "rotate")
12388 (set_attr "mode" "QI")])
12390 ;; Bit set / bit test instructions
12392 (define_expand "extv"
12393 [(set (match_operand:SI 0 "register_operand" "")
12394 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12395 (match_operand:SI 2 "immediate_operand" "")
12396 (match_operand:SI 3 "immediate_operand" "")))]
12399 /* Handle extractions from %ah et al. */
12400 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12403 /* From mips.md: extract_bit_field doesn't verify that our source
12404 matches the predicate, so check it again here. */
12405 if (! register_operand (operands[1], VOIDmode))
12409 (define_expand "extzv"
12410 [(set (match_operand:SI 0 "register_operand" "")
12411 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12412 (match_operand:SI 2 "immediate_operand" "")
12413 (match_operand:SI 3 "immediate_operand" "")))]
12416 /* Handle extractions from %ah et al. */
12417 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12420 /* From mips.md: extract_bit_field doesn't verify that our source
12421 matches the predicate, so check it again here. */
12422 if (! register_operand (operands[1], VOIDmode))
12426 (define_expand "insv"
12427 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12428 (match_operand:SI 1 "immediate_operand" "")
12429 (match_operand:SI 2 "immediate_operand" ""))
12430 (match_operand:SI 3 "register_operand" ""))]
12433 /* Handle extractions from %ah et al. */
12434 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12437 /* From mips.md: insert_bit_field doesn't verify that our source
12438 matches the predicate, so check it again here. */
12439 if (! register_operand (operands[0], VOIDmode))
12443 ;; %%% bts, btr, btc, bt.
12445 ;; Store-flag instructions.
12447 ;; For all sCOND expanders, also expand the compare or test insn that
12448 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12450 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12451 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12452 ;; way, which can later delete the movzx if only QImode is needed.
12454 (define_expand "seq"
12455 [(set (match_operand:QI 0 "register_operand" "")
12456 (eq:QI (reg:CC 17) (const_int 0)))]
12458 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12460 (define_expand "sne"
12461 [(set (match_operand:QI 0 "register_operand" "")
12462 (ne:QI (reg:CC 17) (const_int 0)))]
12464 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12466 (define_expand "sgt"
12467 [(set (match_operand:QI 0 "register_operand" "")
12468 (gt:QI (reg:CC 17) (const_int 0)))]
12470 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12472 (define_expand "sgtu"
12473 [(set (match_operand:QI 0 "register_operand" "")
12474 (gtu:QI (reg:CC 17) (const_int 0)))]
12476 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12478 (define_expand "slt"
12479 [(set (match_operand:QI 0 "register_operand" "")
12480 (lt:QI (reg:CC 17) (const_int 0)))]
12482 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12484 (define_expand "sltu"
12485 [(set (match_operand:QI 0 "register_operand" "")
12486 (ltu:QI (reg:CC 17) (const_int 0)))]
12488 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12490 (define_expand "sge"
12491 [(set (match_operand:QI 0 "register_operand" "")
12492 (ge:QI (reg:CC 17) (const_int 0)))]
12494 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12496 (define_expand "sgeu"
12497 [(set (match_operand:QI 0 "register_operand" "")
12498 (geu:QI (reg:CC 17) (const_int 0)))]
12500 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12502 (define_expand "sle"
12503 [(set (match_operand:QI 0 "register_operand" "")
12504 (le:QI (reg:CC 17) (const_int 0)))]
12506 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12508 (define_expand "sleu"
12509 [(set (match_operand:QI 0 "register_operand" "")
12510 (leu:QI (reg:CC 17) (const_int 0)))]
12512 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12514 (define_expand "sunordered"
12515 [(set (match_operand:QI 0 "register_operand" "")
12516 (unordered:QI (reg:CC 17) (const_int 0)))]
12517 "TARGET_80387 || TARGET_SSE"
12518 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12520 (define_expand "sordered"
12521 [(set (match_operand:QI 0 "register_operand" "")
12522 (ordered:QI (reg:CC 17) (const_int 0)))]
12524 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12526 (define_expand "suneq"
12527 [(set (match_operand:QI 0 "register_operand" "")
12528 (uneq:QI (reg:CC 17) (const_int 0)))]
12529 "TARGET_80387 || TARGET_SSE"
12530 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12532 (define_expand "sunge"
12533 [(set (match_operand:QI 0 "register_operand" "")
12534 (unge:QI (reg:CC 17) (const_int 0)))]
12535 "TARGET_80387 || TARGET_SSE"
12536 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12538 (define_expand "sungt"
12539 [(set (match_operand:QI 0 "register_operand" "")
12540 (ungt:QI (reg:CC 17) (const_int 0)))]
12541 "TARGET_80387 || TARGET_SSE"
12542 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12544 (define_expand "sunle"
12545 [(set (match_operand:QI 0 "register_operand" "")
12546 (unle:QI (reg:CC 17) (const_int 0)))]
12547 "TARGET_80387 || TARGET_SSE"
12548 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12550 (define_expand "sunlt"
12551 [(set (match_operand:QI 0 "register_operand" "")
12552 (unlt:QI (reg:CC 17) (const_int 0)))]
12553 "TARGET_80387 || TARGET_SSE"
12554 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12556 (define_expand "sltgt"
12557 [(set (match_operand:QI 0 "register_operand" "")
12558 (ltgt:QI (reg:CC 17) (const_int 0)))]
12559 "TARGET_80387 || TARGET_SSE"
12560 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12562 (define_insn "*setcc_1"
12563 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12564 (match_operator:QI 1 "ix86_comparison_operator"
12565 [(reg 17) (const_int 0)]))]
12568 [(set_attr "type" "setcc")
12569 (set_attr "mode" "QI")])
12571 (define_insn "setcc_2"
12572 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12573 (match_operator:QI 1 "ix86_comparison_operator"
12574 [(reg 17) (const_int 0)]))]
12577 [(set_attr "type" "setcc")
12578 (set_attr "mode" "QI")])
12580 ;; In general it is not safe to assume too much about CCmode registers,
12581 ;; so simplify-rtx stops when it sees a second one. Under certain
12582 ;; conditions this is safe on x86, so help combine not create
12589 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12590 (ne:QI (match_operator 1 "ix86_comparison_operator"
12591 [(reg 17) (const_int 0)])
12594 [(set (match_dup 0) (match_dup 1))]
12596 PUT_MODE (operands[1], QImode);
12600 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12601 (ne:QI (match_operator 1 "ix86_comparison_operator"
12602 [(reg 17) (const_int 0)])
12605 [(set (match_dup 0) (match_dup 1))]
12607 PUT_MODE (operands[1], QImode);
12611 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12612 (eq:QI (match_operator 1 "ix86_comparison_operator"
12613 [(reg 17) (const_int 0)])
12616 [(set (match_dup 0) (match_dup 1))]
12618 rtx new_op1 = copy_rtx (operands[1]);
12619 operands[1] = new_op1;
12620 PUT_MODE (new_op1, QImode);
12621 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12622 GET_MODE (XEXP (new_op1, 0))));
12624 /* Make sure that (a) the CCmode we have for the flags is strong
12625 enough for the reversed compare or (b) we have a valid FP compare. */
12626 if (! ix86_comparison_operator (new_op1, VOIDmode))
12631 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12632 (eq:QI (match_operator 1 "ix86_comparison_operator"
12633 [(reg 17) (const_int 0)])
12636 [(set (match_dup 0) (match_dup 1))]
12638 rtx new_op1 = copy_rtx (operands[1]);
12639 operands[1] = new_op1;
12640 PUT_MODE (new_op1, QImode);
12641 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12642 GET_MODE (XEXP (new_op1, 0))));
12644 /* Make sure that (a) the CCmode we have for the flags is strong
12645 enough for the reversed compare or (b) we have a valid FP compare. */
12646 if (! ix86_comparison_operator (new_op1, VOIDmode))
12650 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12651 ;; subsequent logical operations are used to imitate conditional moves.
12652 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12653 ;; it directly. Futher holding this value in pseudo register might bring
12654 ;; problem in implicit normalization in spill code.
12655 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12656 ;; instructions after reload by splitting the conditional move patterns.
12658 (define_insn "*sse_setccsf"
12659 [(set (match_operand:SF 0 "register_operand" "=x")
12660 (match_operator:SF 1 "sse_comparison_operator"
12661 [(match_operand:SF 2 "register_operand" "0")
12662 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12663 "TARGET_SSE && reload_completed"
12664 "cmp%D1ss\t{%3, %0|%0, %3}"
12665 [(set_attr "type" "ssecmp")
12666 (set_attr "mode" "SF")])
12668 (define_insn "*sse_setccdf"
12669 [(set (match_operand:DF 0 "register_operand" "=Y")
12670 (match_operator:DF 1 "sse_comparison_operator"
12671 [(match_operand:DF 2 "register_operand" "0")
12672 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12673 "TARGET_SSE2 && reload_completed"
12674 "cmp%D1sd\t{%3, %0|%0, %3}"
12675 [(set_attr "type" "ssecmp")
12676 (set_attr "mode" "DF")])
12678 ;; Basic conditional jump instructions.
12679 ;; We ignore the overflow flag for signed branch instructions.
12681 ;; For all bCOND expanders, also expand the compare or test insn that
12682 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12684 (define_expand "beq"
12686 (if_then_else (match_dup 1)
12687 (label_ref (match_operand 0 "" ""))
12690 "ix86_expand_branch (EQ, operands[0]); DONE;")
12692 (define_expand "bne"
12694 (if_then_else (match_dup 1)
12695 (label_ref (match_operand 0 "" ""))
12698 "ix86_expand_branch (NE, operands[0]); DONE;")
12700 (define_expand "bgt"
12702 (if_then_else (match_dup 1)
12703 (label_ref (match_operand 0 "" ""))
12706 "ix86_expand_branch (GT, operands[0]); DONE;")
12708 (define_expand "bgtu"
12710 (if_then_else (match_dup 1)
12711 (label_ref (match_operand 0 "" ""))
12714 "ix86_expand_branch (GTU, operands[0]); DONE;")
12716 (define_expand "blt"
12718 (if_then_else (match_dup 1)
12719 (label_ref (match_operand 0 "" ""))
12722 "ix86_expand_branch (LT, operands[0]); DONE;")
12724 (define_expand "bltu"
12726 (if_then_else (match_dup 1)
12727 (label_ref (match_operand 0 "" ""))
12730 "ix86_expand_branch (LTU, operands[0]); DONE;")
12732 (define_expand "bge"
12734 (if_then_else (match_dup 1)
12735 (label_ref (match_operand 0 "" ""))
12738 "ix86_expand_branch (GE, operands[0]); DONE;")
12740 (define_expand "bgeu"
12742 (if_then_else (match_dup 1)
12743 (label_ref (match_operand 0 "" ""))
12746 "ix86_expand_branch (GEU, operands[0]); DONE;")
12748 (define_expand "ble"
12750 (if_then_else (match_dup 1)
12751 (label_ref (match_operand 0 "" ""))
12754 "ix86_expand_branch (LE, operands[0]); DONE;")
12756 (define_expand "bleu"
12758 (if_then_else (match_dup 1)
12759 (label_ref (match_operand 0 "" ""))
12762 "ix86_expand_branch (LEU, operands[0]); DONE;")
12764 (define_expand "bunordered"
12766 (if_then_else (match_dup 1)
12767 (label_ref (match_operand 0 "" ""))
12769 "TARGET_80387 || TARGET_SSE"
12770 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12772 (define_expand "bordered"
12774 (if_then_else (match_dup 1)
12775 (label_ref (match_operand 0 "" ""))
12777 "TARGET_80387 || TARGET_SSE"
12778 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12780 (define_expand "buneq"
12782 (if_then_else (match_dup 1)
12783 (label_ref (match_operand 0 "" ""))
12785 "TARGET_80387 || TARGET_SSE"
12786 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12788 (define_expand "bunge"
12790 (if_then_else (match_dup 1)
12791 (label_ref (match_operand 0 "" ""))
12793 "TARGET_80387 || TARGET_SSE"
12794 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12796 (define_expand "bungt"
12798 (if_then_else (match_dup 1)
12799 (label_ref (match_operand 0 "" ""))
12801 "TARGET_80387 || TARGET_SSE"
12802 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12804 (define_expand "bunle"
12806 (if_then_else (match_dup 1)
12807 (label_ref (match_operand 0 "" ""))
12809 "TARGET_80387 || TARGET_SSE"
12810 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12812 (define_expand "bunlt"
12814 (if_then_else (match_dup 1)
12815 (label_ref (match_operand 0 "" ""))
12817 "TARGET_80387 || TARGET_SSE"
12818 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12820 (define_expand "bltgt"
12822 (if_then_else (match_dup 1)
12823 (label_ref (match_operand 0 "" ""))
12825 "TARGET_80387 || TARGET_SSE"
12826 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12828 (define_insn "*jcc_1"
12830 (if_then_else (match_operator 1 "ix86_comparison_operator"
12831 [(reg 17) (const_int 0)])
12832 (label_ref (match_operand 0 "" ""))
12836 [(set_attr "type" "ibr")
12837 (set_attr "modrm" "0")
12838 (set (attr "prefix_0f")
12839 (if_then_else (and (ge (minus (match_dup 0) (pc))
12841 (lt (minus (match_dup 0) (pc))
12846 (define_insn "*jcc_2"
12848 (if_then_else (match_operator 1 "ix86_comparison_operator"
12849 [(reg 17) (const_int 0)])
12851 (label_ref (match_operand 0 "" ""))))]
12854 [(set_attr "type" "ibr")
12855 (set_attr "modrm" "0")
12856 (set (attr "prefix_0f")
12857 (if_then_else (and (ge (minus (match_dup 0) (pc))
12859 (lt (minus (match_dup 0) (pc))
12864 ;; In general it is not safe to assume too much about CCmode registers,
12865 ;; so simplify-rtx stops when it sees a second one. Under certain
12866 ;; conditions this is safe on x86, so help combine not create
12874 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
12875 [(reg 17) (const_int 0)])
12877 (label_ref (match_operand 1 "" ""))
12881 (if_then_else (match_dup 0)
12882 (label_ref (match_dup 1))
12885 PUT_MODE (operands[0], VOIDmode);
12890 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
12891 [(reg 17) (const_int 0)])
12893 (label_ref (match_operand 1 "" ""))
12897 (if_then_else (match_dup 0)
12898 (label_ref (match_dup 1))
12901 rtx new_op0 = copy_rtx (operands[0]);
12902 operands[0] = new_op0;
12903 PUT_MODE (new_op0, VOIDmode);
12904 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
12905 GET_MODE (XEXP (new_op0, 0))));
12907 /* Make sure that (a) the CCmode we have for the flags is strong
12908 enough for the reversed compare or (b) we have a valid FP compare. */
12909 if (! ix86_comparison_operator (new_op0, VOIDmode))
12913 ;; Define combination compare-and-branch fp compare instructions to use
12914 ;; during early optimization. Splitting the operation apart early makes
12915 ;; for bad code when we want to reverse the operation.
12917 (define_insn "*fp_jcc_1"
12919 (if_then_else (match_operator 0 "comparison_operator"
12920 [(match_operand 1 "register_operand" "f")
12921 (match_operand 2 "register_operand" "f")])
12922 (label_ref (match_operand 3 "" ""))
12924 (clobber (reg:CCFP 18))
12925 (clobber (reg:CCFP 17))]
12926 "TARGET_CMOVE && TARGET_80387
12927 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12928 && FLOAT_MODE_P (GET_MODE (operands[1]))
12929 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12930 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12933 (define_insn "*fp_jcc_1_sse"
12935 (if_then_else (match_operator 0 "comparison_operator"
12936 [(match_operand 1 "register_operand" "f#x,x#f")
12937 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12938 (label_ref (match_operand 3 "" ""))
12940 (clobber (reg:CCFP 18))
12941 (clobber (reg:CCFP 17))]
12943 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12944 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12945 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12948 (define_insn "*fp_jcc_1_sse_only"
12950 (if_then_else (match_operator 0 "comparison_operator"
12951 [(match_operand 1 "register_operand" "x")
12952 (match_operand 2 "nonimmediate_operand" "xm")])
12953 (label_ref (match_operand 3 "" ""))
12955 (clobber (reg:CCFP 18))
12956 (clobber (reg:CCFP 17))]
12957 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12958 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12959 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12962 (define_insn "*fp_jcc_2"
12964 (if_then_else (match_operator 0 "comparison_operator"
12965 [(match_operand 1 "register_operand" "f")
12966 (match_operand 2 "register_operand" "f")])
12968 (label_ref (match_operand 3 "" ""))))
12969 (clobber (reg:CCFP 18))
12970 (clobber (reg:CCFP 17))]
12971 "TARGET_CMOVE && TARGET_80387
12972 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12973 && FLOAT_MODE_P (GET_MODE (operands[1]))
12974 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12975 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12978 (define_insn "*fp_jcc_2_sse"
12980 (if_then_else (match_operator 0 "comparison_operator"
12981 [(match_operand 1 "register_operand" "f#x,x#f")
12982 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12984 (label_ref (match_operand 3 "" ""))))
12985 (clobber (reg:CCFP 18))
12986 (clobber (reg:CCFP 17))]
12988 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12989 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12990 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12993 (define_insn "*fp_jcc_2_sse_only"
12995 (if_then_else (match_operator 0 "comparison_operator"
12996 [(match_operand 1 "register_operand" "x")
12997 (match_operand 2 "nonimmediate_operand" "xm")])
12999 (label_ref (match_operand 3 "" ""))))
13000 (clobber (reg:CCFP 18))
13001 (clobber (reg:CCFP 17))]
13002 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13003 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13004 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13007 (define_insn "*fp_jcc_3"
13009 (if_then_else (match_operator 0 "comparison_operator"
13010 [(match_operand 1 "register_operand" "f")
13011 (match_operand 2 "nonimmediate_operand" "fm")])
13012 (label_ref (match_operand 3 "" ""))
13014 (clobber (reg:CCFP 18))
13015 (clobber (reg:CCFP 17))
13016 (clobber (match_scratch:HI 4 "=a"))]
13018 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13019 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13020 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13021 && SELECT_CC_MODE (GET_CODE (operands[0]),
13022 operands[1], operands[2]) == CCFPmode
13023 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13026 (define_insn "*fp_jcc_4"
13028 (if_then_else (match_operator 0 "comparison_operator"
13029 [(match_operand 1 "register_operand" "f")
13030 (match_operand 2 "nonimmediate_operand" "fm")])
13032 (label_ref (match_operand 3 "" ""))))
13033 (clobber (reg:CCFP 18))
13034 (clobber (reg:CCFP 17))
13035 (clobber (match_scratch:HI 4 "=a"))]
13037 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13038 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13039 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13040 && SELECT_CC_MODE (GET_CODE (operands[0]),
13041 operands[1], operands[2]) == CCFPmode
13042 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13045 (define_insn "*fp_jcc_5"
13047 (if_then_else (match_operator 0 "comparison_operator"
13048 [(match_operand 1 "register_operand" "f")
13049 (match_operand 2 "register_operand" "f")])
13050 (label_ref (match_operand 3 "" ""))
13052 (clobber (reg:CCFP 18))
13053 (clobber (reg:CCFP 17))
13054 (clobber (match_scratch:HI 4 "=a"))]
13056 && FLOAT_MODE_P (GET_MODE (operands[1]))
13057 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13058 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13061 (define_insn "*fp_jcc_6"
13063 (if_then_else (match_operator 0 "comparison_operator"
13064 [(match_operand 1 "register_operand" "f")
13065 (match_operand 2 "register_operand" "f")])
13067 (label_ref (match_operand 3 "" ""))))
13068 (clobber (reg:CCFP 18))
13069 (clobber (reg:CCFP 17))
13070 (clobber (match_scratch:HI 4 "=a"))]
13072 && FLOAT_MODE_P (GET_MODE (operands[1]))
13073 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13074 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13079 (if_then_else (match_operator 0 "comparison_operator"
13080 [(match_operand 1 "register_operand" "")
13081 (match_operand 2 "nonimmediate_operand" "")])
13082 (match_operand 3 "" "")
13083 (match_operand 4 "" "")))
13084 (clobber (reg:CCFP 18))
13085 (clobber (reg:CCFP 17))]
13089 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13090 operands[3], operands[4], NULL_RTX);
13096 (if_then_else (match_operator 0 "comparison_operator"
13097 [(match_operand 1 "register_operand" "")
13098 (match_operand 2 "nonimmediate_operand" "")])
13099 (match_operand 3 "" "")
13100 (match_operand 4 "" "")))
13101 (clobber (reg:CCFP 18))
13102 (clobber (reg:CCFP 17))
13103 (clobber (match_scratch:HI 5 "=a"))]
13106 (if_then_else (match_dup 6)
13110 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13111 operands[3], operands[4], operands[5]);
13115 ;; Unconditional and other jump instructions
13117 (define_insn "jump"
13119 (label_ref (match_operand 0 "" "")))]
13122 [(set_attr "type" "ibr")
13123 (set_attr "modrm" "0")])
13125 (define_expand "indirect_jump"
13126 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13130 (define_insn "*indirect_jump"
13131 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13134 [(set_attr "type" "ibr")
13135 (set_attr "length_immediate" "0")])
13137 (define_insn "*indirect_jump_rtx64"
13138 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13141 [(set_attr "type" "ibr")
13142 (set_attr "length_immediate" "0")])
13144 (define_expand "tablejump"
13145 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13146 (use (label_ref (match_operand 1 "" "")))])]
13149 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13150 relative. Convert the relative address to an absolute address. */
13154 enum rtx_code code;
13160 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13162 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13166 op1 = pic_offset_table_rtx;
13171 op0 = pic_offset_table_rtx;
13175 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13180 (define_insn "*tablejump_1"
13181 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13182 (use (label_ref (match_operand 1 "" "")))]
13185 [(set_attr "type" "ibr")
13186 (set_attr "length_immediate" "0")])
13188 (define_insn "*tablejump_1_rtx64"
13189 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13190 (use (label_ref (match_operand 1 "" "")))]
13193 [(set_attr "type" "ibr")
13194 (set_attr "length_immediate" "0")])
13196 ;; Loop instruction
13198 ;; This is all complicated by the fact that since this is a jump insn
13199 ;; we must handle our own reloads.
13201 (define_expand "doloop_end"
13202 [(use (match_operand 0 "" "")) ; loop pseudo
13203 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13204 (use (match_operand 2 "" "")) ; max iterations
13205 (use (match_operand 3 "" "")) ; loop level
13206 (use (match_operand 4 "" ""))] ; label
13207 "!TARGET_64BIT && TARGET_USE_LOOP"
13210 /* Only use cloop on innermost loops. */
13211 if (INTVAL (operands[3]) > 1)
13213 if (GET_MODE (operands[0]) != SImode)
13215 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13220 (define_insn "doloop_end_internal"
13222 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13224 (label_ref (match_operand 0 "" ""))
13226 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13227 (plus:SI (match_dup 1)
13229 (clobber (match_scratch:SI 3 "=X,X,r"))
13230 (clobber (reg:CC 17))]
13231 "!TARGET_64BIT && TARGET_USE_LOOP"
13233 if (which_alternative != 0)
13235 if (get_attr_length (insn) == 2)
13236 return "%+loop\t%l0";
13238 return "dec{l}\t%1\;%+jne\t%l0";
13240 [(set_attr "ppro_uops" "many")
13241 (set (attr "length")
13242 (if_then_else (and (eq_attr "alternative" "0")
13243 (and (ge (minus (match_dup 0) (pc))
13245 (lt (minus (match_dup 0) (pc))
13250 (if_then_else (and (eq_attr "alternative" "0")
13251 (and (ge (minus (match_dup 0) (pc))
13253 (lt (minus (match_dup 0) (pc))
13255 (const_string "ibr")
13256 (const_string "multi")))])
13260 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13262 (match_operand 0 "" "")
13265 (plus:SI (match_dup 1)
13267 (clobber (match_scratch:SI 2 ""))
13268 (clobber (reg:CC 17))]
13269 "!TARGET_64BIT && TARGET_USE_LOOP
13270 && reload_completed
13271 && REGNO (operands[1]) != 2"
13272 [(parallel [(set (reg:CCZ 17)
13273 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13275 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13276 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13283 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13285 (match_operand 0 "" "")
13287 (set (match_operand:SI 2 "nonimmediate_operand" "")
13288 (plus:SI (match_dup 1)
13290 (clobber (match_scratch:SI 3 ""))
13291 (clobber (reg:CC 17))]
13292 "!TARGET_64BIT && TARGET_USE_LOOP
13293 && reload_completed
13294 && (! REG_P (operands[2])
13295 || ! rtx_equal_p (operands[1], operands[2]))"
13296 [(set (match_dup 3) (match_dup 1))
13297 (parallel [(set (reg:CCZ 17)
13298 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13300 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13301 (set (match_dup 2) (match_dup 3))
13302 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13307 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13310 [(set (reg 17) (match_operand 0 "" ""))
13311 (set (match_operand:QI 1 "register_operand" "")
13312 (match_operator:QI 2 "ix86_comparison_operator"
13313 [(reg 17) (const_int 0)]))
13314 (set (match_operand 3 "q_regs_operand" "")
13315 (zero_extend (match_dup 1)))]
13316 "(peep2_reg_dead_p (3, operands[1])
13317 || operands_match_p (operands[1], operands[3]))
13318 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13319 [(set (match_dup 4) (match_dup 0))
13320 (set (strict_low_part (match_dup 5))
13323 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13324 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
13325 ix86_expand_clear (operands[3]);
13328 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13331 [(set (reg 17) (match_operand 0 "" ""))
13332 (set (match_operand:QI 1 "register_operand" "")
13333 (match_operator:QI 2 "ix86_comparison_operator"
13334 [(reg 17) (const_int 0)]))
13335 (parallel [(set (match_operand 3 "q_regs_operand" "")
13336 (zero_extend (match_dup 1)))
13337 (clobber (reg:CC 17))])]
13338 "(peep2_reg_dead_p (3, operands[1])
13339 || operands_match_p (operands[1], operands[3]))
13340 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13341 [(set (match_dup 4) (match_dup 0))
13342 (set (strict_low_part (match_dup 5))
13345 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13346 operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
13347 ix86_expand_clear (operands[3]);
13350 ;; Call instructions.
13352 ;; The predicates normally associated with named expanders are not properly
13353 ;; checked for calls. This is a bug in the generic code, but it isn't that
13354 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13356 ;; Call subroutine returning no value.
13358 (define_expand "call_pop"
13359 [(parallel [(call (match_operand:QI 0 "" "")
13360 (match_operand:SI 1 "" ""))
13362 (plus:SI (reg:SI 7)
13363 (match_operand:SI 3 "" "")))])]
13366 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3]);
13370 (define_insn "*call_pop_0"
13371 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13372 (match_operand:SI 1 "" ""))
13373 (set (reg:SI 7) (plus:SI (reg:SI 7)
13374 (match_operand:SI 2 "immediate_operand" "")))]
13377 if (SIBLING_CALL_P (insn))
13380 return "call\t%P0";
13382 [(set_attr "type" "call")])
13384 (define_insn "*call_pop_1"
13385 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13386 (match_operand:SI 1 "" ""))
13387 (set (reg:SI 7) (plus:SI (reg:SI 7)
13388 (match_operand:SI 2 "immediate_operand" "i")))]
13391 if (constant_call_address_operand (operands[0], Pmode))
13393 if (SIBLING_CALL_P (insn))
13396 return "call\t%P0";
13398 if (SIBLING_CALL_P (insn))
13401 return "call\t%A0";
13403 [(set_attr "type" "call")])
13405 (define_expand "call"
13406 [(call (match_operand:QI 0 "" "")
13407 (match_operand 1 "" ""))
13408 (use (match_operand 2 "" ""))]
13411 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL);
13415 (define_insn "*call_0"
13416 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13417 (match_operand 1 "" ""))]
13420 if (SIBLING_CALL_P (insn))
13423 return "call\t%P0";
13425 [(set_attr "type" "call")])
13427 (define_insn "*call_1"
13428 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13429 (match_operand 1 "" ""))]
13432 if (constant_call_address_operand (operands[0], QImode))
13434 if (SIBLING_CALL_P (insn))
13437 return "call\t%P0";
13439 if (SIBLING_CALL_P (insn))
13442 return "call\t%A0";
13444 [(set_attr "type" "call")])
13446 (define_insn "*call_1_rex64"
13447 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13448 (match_operand 1 "" ""))]
13451 if (constant_call_address_operand (operands[0], QImode))
13453 if (SIBLING_CALL_P (insn))
13456 return "call\t%P0";
13458 if (SIBLING_CALL_P (insn))
13461 return "call\t%A0";
13463 [(set_attr "type" "call")])
13465 ;; Call subroutine, returning value in operand 0
13467 (define_expand "call_value_pop"
13468 [(parallel [(set (match_operand 0 "" "")
13469 (call (match_operand:QI 1 "" "")
13470 (match_operand:SI 2 "" "")))
13472 (plus:SI (reg:SI 7)
13473 (match_operand:SI 4 "" "")))])]
13476 ix86_expand_call (operands[0], operands[1], operands[2],
13477 operands[3], operands[4]);
13481 (define_expand "call_value"
13482 [(set (match_operand 0 "" "")
13483 (call (match_operand:QI 1 "" "")
13484 (match_operand:SI 2 "" "")))
13485 (use (match_operand:SI 3 "" ""))]
13486 ;; Operand 2 not used on the i386.
13489 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL);
13493 ;; Call subroutine returning any type.
13495 (define_expand "untyped_call"
13496 [(parallel [(call (match_operand 0 "" "")
13498 (match_operand 1 "" "")
13499 (match_operand 2 "" "")])]
13504 /* In order to give reg-stack an easier job in validating two
13505 coprocessor registers as containing a possible return value,
13506 simply pretend the untyped call returns a complex long double
13509 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13510 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13511 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13514 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13516 rtx set = XVECEXP (operands[2], 0, i);
13517 emit_move_insn (SET_DEST (set), SET_SRC (set));
13520 /* The optimizer does not know that the call sets the function value
13521 registers we stored in the result block. We avoid problems by
13522 claiming that all hard registers are used and clobbered at this
13524 emit_insn (gen_blockage (const0_rtx));
13529 ;; Prologue and epilogue instructions
13531 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13532 ;; all of memory. This blocks insns from being moved across this point.
13534 (define_insn "blockage"
13535 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13538 [(set_attr "length" "0")])
13540 ;; Insn emitted into the body of a function to return from a function.
13541 ;; This is only done if the function's epilogue is known to be simple.
13542 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13544 (define_expand "return"
13546 "ix86_can_use_return_insn_p ()"
13548 if (current_function_pops_args)
13550 rtx popc = GEN_INT (current_function_pops_args);
13551 emit_jump_insn (gen_return_pop_internal (popc));
13556 (define_insn "return_internal"
13560 [(set_attr "length" "1")
13561 (set_attr "length_immediate" "0")
13562 (set_attr "modrm" "0")])
13564 (define_insn "return_pop_internal"
13566 (use (match_operand:SI 0 "const_int_operand" ""))]
13569 [(set_attr "length" "3")
13570 (set_attr "length_immediate" "2")
13571 (set_attr "modrm" "0")])
13573 (define_insn "return_indirect_internal"
13575 (use (match_operand:SI 0 "register_operand" "r"))]
13578 [(set_attr "type" "ibr")
13579 (set_attr "length_immediate" "0")])
13585 [(set_attr "length" "1")
13586 (set_attr "length_immediate" "0")
13587 (set_attr "modrm" "0")
13588 (set_attr "ppro_uops" "one")])
13590 (define_expand "prologue"
13593 "ix86_expand_prologue (); DONE;")
13595 (define_insn "set_got"
13596 [(set (match_operand:SI 0 "register_operand" "=r")
13597 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13598 (clobber (reg:CC 17))]
13600 { return output_set_got (operands[0]); }
13601 [(set_attr "type" "multi")
13602 (set_attr "length" "12")])
13604 (define_expand "epilogue"
13607 "ix86_expand_epilogue (1); DONE;")
13609 (define_expand "sibcall_epilogue"
13612 "ix86_expand_epilogue (0); DONE;")
13614 (define_expand "eh_return"
13615 [(use (match_operand 0 "register_operand" ""))
13616 (use (match_operand 1 "register_operand" ""))]
13619 rtx tmp, sa = operands[0], ra = operands[1];
13621 /* Tricky bit: we write the address of the handler to which we will
13622 be returning into someone else's stack frame, one word below the
13623 stack address we wish to restore. */
13624 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13625 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13626 tmp = gen_rtx_MEM (Pmode, tmp);
13627 emit_move_insn (tmp, ra);
13629 if (Pmode == SImode)
13630 emit_insn (gen_eh_return_si (sa));
13632 emit_insn (gen_eh_return_di (sa));
13637 (define_insn_and_split "eh_return_si"
13638 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
13639 UNSPECV_EH_RETURN)]
13644 "ix86_expand_epilogue (2); DONE;")
13646 (define_insn_and_split "eh_return_di"
13647 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
13648 UNSPECV_EH_RETURN)]
13653 "ix86_expand_epilogue (2); DONE;")
13655 (define_insn "leave"
13656 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
13657 (set (reg:SI 6) (mem:SI (reg:SI 6)))
13658 (clobber (mem:BLK (scratch)))]
13661 [(set_attr "length_immediate" "0")
13662 (set_attr "length" "1")
13663 (set_attr "modrm" "0")
13664 (set_attr "athlon_decode" "vector")
13665 (set_attr "ppro_uops" "few")])
13667 (define_insn "leave_rex64"
13668 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
13669 (set (reg:DI 6) (mem:DI (reg:DI 6)))
13670 (clobber (mem:BLK (scratch)))]
13673 [(set_attr "length_immediate" "0")
13674 (set_attr "length" "1")
13675 (set_attr "modrm" "0")
13676 (set_attr "athlon_decode" "vector")
13677 (set_attr "ppro_uops" "few")])
13679 (define_expand "ffssi2"
13680 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13681 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
13684 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
13685 rtx in = operands[1];
13689 emit_move_insn (tmp, constm1_rtx);
13690 emit_insn (gen_ffssi_1 (out, in));
13691 emit_insn (gen_rtx_SET (VOIDmode, out,
13692 gen_rtx_IF_THEN_ELSE (SImode,
13693 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
13697 emit_insn (gen_addsi3 (out, out, const1_rtx));
13698 emit_move_insn (operands[0], out);
13701 /* Pentium bsf instruction is extremly slow. The following code is
13702 recommended by the Intel Optimizing Manual as a reasonable replacement:
13706 MOV DWORD PTR [TEMP+4],ECX
13709 MOV DWORD PTR [TEMP],EAX
13710 FILD QWORD PTR [TEMP]
13711 FSTP QWORD PTR [TEMP]
13712 WAIT ; WAIT only needed for compatibility with
13713 ; earlier processors
13714 MOV ECX, DWORD PTR [TEMP+4]
13717 TEST EAX,EAX ; clear zero flag
13719 Following piece of code expand ffs to similar beast.
13722 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
13724 rtx label = gen_label_rtx ();
13726 rtx mem = assign_386_stack_local (DImode, 0);
13727 rtx fptmp = gen_reg_rtx (DFmode);
13728 split_di (&mem, 1, &lo, &hi);
13730 emit_move_insn (out, const0_rtx);
13732 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label);
13734 emit_move_insn (hi, out);
13735 emit_insn (gen_subsi3 (out, out, in));
13736 emit_insn (gen_andsi3 (out, out, in));
13737 emit_move_insn (lo, out);
13738 emit_insn (gen_floatdidf2 (fptmp,mem));
13739 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
13740 emit_move_insn (out, hi);
13741 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
13742 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
13744 emit_label (label);
13745 LABEL_NUSES (label) = 1;
13747 emit_move_insn (operands[0], out);
13751 emit_move_insn (tmp, const0_rtx);
13752 emit_insn (gen_ffssi_1 (out, in));
13753 emit_insn (gen_rtx_SET (VOIDmode,
13754 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
13755 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
13757 emit_insn (gen_negsi2 (tmp, tmp));
13758 emit_insn (gen_iorsi3 (out, out, tmp));
13759 emit_insn (gen_addsi3 (out, out, const1_rtx));
13760 emit_move_insn (operands[0], out);
13765 (define_insn "ffssi_1"
13767 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13769 (set (match_operand:SI 0 "register_operand" "=r")
13770 (unspec:SI [(match_dup 1)] UNSPEC_BSF))]
13772 "bsf{l}\t{%1, %0|%0, %1}"
13773 [(set_attr "prefix_0f" "1")
13774 (set_attr "ppro_uops" "few")])
13776 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
13777 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
13779 ;; Thread-local storage patterns for ELF.
13781 ;; Note that these code sequences must appear exactly as shown
13782 ;; in order to allow linker relaxation.
13784 (define_insn "*tls_global_dynamic_gnu"
13785 [(set (match_operand:SI 0 "register_operand" "=a")
13786 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13787 (match_operand:SI 2 "tls_symbolic_operand" "")
13788 (match_operand:SI 3 "call_insn_operand" "")]
13790 (clobber (match_scratch:SI 4 "=d"))
13791 (clobber (match_scratch:SI 5 "=c"))
13792 (clobber (reg:CC 17))]
13794 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
13795 [(set_attr "type" "multi")
13796 (set_attr "length" "12")])
13798 (define_insn "*tls_global_dynamic_sun"
13799 [(set (match_operand:SI 0 "register_operand" "=a")
13800 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13801 (match_operand:SI 2 "tls_symbolic_operand" "")
13802 (match_operand:SI 3 "call_insn_operand" "")]
13804 (clobber (match_scratch:SI 4 "=d"))
13805 (clobber (match_scratch:SI 5 "=c"))
13806 (clobber (reg:CC 17))]
13808 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
13809 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
13810 [(set_attr "type" "multi")
13811 (set_attr "length" "14")])
13813 (define_expand "tls_global_dynamic"
13814 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13817 (match_operand:SI 1 "tls_symbolic_operand" "")
13820 (clobber (match_scratch:SI 4 ""))
13821 (clobber (match_scratch:SI 5 ""))
13822 (clobber (reg:CC 17))])]
13827 operands[2] = pic_offset_table_rtx;
13828 operands[3] = ix86_tls_get_addr ();
13831 (define_insn "*tls_local_dynamic_base_gnu"
13832 [(set (match_operand:SI 0 "register_operand" "=a")
13833 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13834 (match_operand:SI 2 "call_insn_operand" "")]
13835 UNSPEC_TLS_LD_BASE))
13836 (clobber (match_scratch:SI 3 "=d"))
13837 (clobber (match_scratch:SI 4 "=c"))
13838 (clobber (reg:CC 17))]
13840 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
13841 [(set_attr "type" "multi")
13842 (set_attr "length" "11")])
13844 (define_insn "*tls_local_dynamic_base_sun"
13845 [(set (match_operand:SI 0 "register_operand" "=a")
13846 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13847 (match_operand:SI 2 "call_insn_operand" "")]
13848 UNSPEC_TLS_LD_BASE))
13849 (clobber (match_scratch:SI 3 "=d"))
13850 (clobber (match_scratch:SI 4 "=c"))
13851 (clobber (reg:CC 17))]
13853 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
13854 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
13855 [(set_attr "type" "multi")
13856 (set_attr "length" "13")])
13858 (define_expand "tls_local_dynamic_base"
13859 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13860 (unspec:SI [(match_dup 1) (match_dup 2)]
13861 UNSPEC_TLS_LD_BASE))
13862 (clobber (match_scratch:SI 3 ""))
13863 (clobber (match_scratch:SI 4 ""))
13864 (clobber (reg:CC 17))])]
13869 operands[1] = pic_offset_table_rtx;
13870 operands[2] = ix86_tls_get_addr ();
13873 ;; Local dynamic of a single variable is a lose. Show combine how
13874 ;; to convert that back to global dynamic.
13876 (define_insn_and_split "*tls_local_dynamic_once"
13877 [(set (match_operand:SI 0 "register_operand" "=a")
13878 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13879 (match_operand:SI 2 "call_insn_operand" "")]
13880 UNSPEC_TLS_LD_BASE)
13881 (const:SI (unspec:SI
13882 [(match_operand:SI 3 "tls_symbolic_operand" "")]
13884 (clobber (match_scratch:SI 4 "=d"))
13885 (clobber (match_scratch:SI 5 "=c"))
13886 (clobber (reg:CC 17))]
13890 [(parallel [(set (match_dup 0)
13891 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
13893 (clobber (match_dup 4))
13894 (clobber (match_dup 5))
13895 (clobber (reg:CC 17))])]
13898 ;; These patterns match the binary 387 instructions for addM3, subM3,
13899 ;; mulM3 and divM3. There are three patterns for each of DFmode and
13900 ;; SFmode. The first is the normal insn, the second the same insn but
13901 ;; with one operand a conversion, and the third the same insn but with
13902 ;; the other operand a conversion. The conversion may be SFmode or
13903 ;; SImode if the target mode DFmode, but only SImode if the target mode
13906 ;; Gcc is slightly more smart about handling normal two address instructions
13907 ;; so use special patterns for add and mull.
13908 (define_insn "*fop_sf_comm_nosse"
13909 [(set (match_operand:SF 0 "register_operand" "=f")
13910 (match_operator:SF 3 "binary_fp_operator"
13911 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13912 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
13913 "TARGET_80387 && !TARGET_SSE_MATH
13914 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13915 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13916 "* return output_387_binary_op (insn, operands);"
13917 [(set (attr "type")
13918 (if_then_else (match_operand:SF 3 "mult_operator" "")
13919 (const_string "fmul")
13920 (const_string "fop")))
13921 (set_attr "mode" "SF")])
13923 (define_insn "*fop_sf_comm"
13924 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
13925 (match_operator:SF 3 "binary_fp_operator"
13926 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
13927 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
13928 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
13929 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13930 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13931 "* return output_387_binary_op (insn, operands);"
13932 [(set (attr "type")
13933 (if_then_else (eq_attr "alternative" "1")
13934 (if_then_else (match_operand:SF 3 "mult_operator" "")
13935 (const_string "ssemul")
13936 (const_string "sseadd"))
13937 (if_then_else (match_operand:SF 3 "mult_operator" "")
13938 (const_string "fmul")
13939 (const_string "fop"))))
13940 (set_attr "mode" "SF")])
13942 (define_insn "*fop_sf_comm_sse"
13943 [(set (match_operand:SF 0 "register_operand" "=x")
13944 (match_operator:SF 3 "binary_fp_operator"
13945 [(match_operand:SF 1 "nonimmediate_operand" "%0")
13946 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
13947 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13948 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13949 "* return output_387_binary_op (insn, operands);"
13950 [(set (attr "type")
13951 (if_then_else (match_operand:SF 3 "mult_operator" "")
13952 (const_string "ssemul")
13953 (const_string "sseadd")))
13954 (set_attr "mode" "SF")])
13956 (define_insn "*fop_df_comm_nosse"
13957 [(set (match_operand:DF 0 "register_operand" "=f")
13958 (match_operator:DF 3 "binary_fp_operator"
13959 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13960 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
13961 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
13962 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13963 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13964 "* return output_387_binary_op (insn, operands);"
13965 [(set (attr "type")
13966 (if_then_else (match_operand:SF 3 "mult_operator" "")
13967 (const_string "fmul")
13968 (const_string "fop")))
13969 (set_attr "mode" "DF")])
13971 (define_insn "*fop_df_comm"
13972 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
13973 (match_operator:DF 3 "binary_fp_operator"
13974 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
13975 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
13976 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
13977 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13978 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13979 "* return output_387_binary_op (insn, operands);"
13980 [(set (attr "type")
13981 (if_then_else (eq_attr "alternative" "1")
13982 (if_then_else (match_operand:SF 3 "mult_operator" "")
13983 (const_string "ssemul")
13984 (const_string "sseadd"))
13985 (if_then_else (match_operand:SF 3 "mult_operator" "")
13986 (const_string "fmul")
13987 (const_string "fop"))))
13988 (set_attr "mode" "DF")])
13990 (define_insn "*fop_df_comm_sse"
13991 [(set (match_operand:DF 0 "register_operand" "=Y")
13992 (match_operator:DF 3 "binary_fp_operator"
13993 [(match_operand:DF 1 "nonimmediate_operand" "%0")
13994 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
13995 "TARGET_SSE2 && TARGET_SSE_MATH
13996 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
13997 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
13998 "* return output_387_binary_op (insn, operands);"
13999 [(set (attr "type")
14000 (if_then_else (match_operand:SF 3 "mult_operator" "")
14001 (const_string "ssemul")
14002 (const_string "sseadd")))
14003 (set_attr "mode" "DF")])
14005 (define_insn "*fop_xf_comm"
14006 [(set (match_operand:XF 0 "register_operand" "=f")
14007 (match_operator:XF 3 "binary_fp_operator"
14008 [(match_operand:XF 1 "register_operand" "%0")
14009 (match_operand:XF 2 "register_operand" "f")]))]
14010 "!TARGET_64BIT && TARGET_80387
14011 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14012 "* return output_387_binary_op (insn, operands);"
14013 [(set (attr "type")
14014 (if_then_else (match_operand:XF 3 "mult_operator" "")
14015 (const_string "fmul")
14016 (const_string "fop")))
14017 (set_attr "mode" "XF")])
14019 (define_insn "*fop_tf_comm"
14020 [(set (match_operand:TF 0 "register_operand" "=f")
14021 (match_operator:TF 3 "binary_fp_operator"
14022 [(match_operand:TF 1 "register_operand" "%0")
14023 (match_operand:TF 2 "register_operand" "f")]))]
14024 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14025 "* return output_387_binary_op (insn, operands);"
14026 [(set (attr "type")
14027 (if_then_else (match_operand:TF 3 "mult_operator" "")
14028 (const_string "fmul")
14029 (const_string "fop")))
14030 (set_attr "mode" "XF")])
14032 (define_insn "*fop_sf_1_nosse"
14033 [(set (match_operand:SF 0 "register_operand" "=f,f")
14034 (match_operator:SF 3 "binary_fp_operator"
14035 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14036 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14037 "TARGET_80387 && !TARGET_SSE_MATH
14038 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14039 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14040 "* return output_387_binary_op (insn, operands);"
14041 [(set (attr "type")
14042 (cond [(match_operand:SF 3 "mult_operator" "")
14043 (const_string "fmul")
14044 (match_operand:SF 3 "div_operator" "")
14045 (const_string "fdiv")
14047 (const_string "fop")))
14048 (set_attr "mode" "SF")])
14050 (define_insn "*fop_sf_1"
14051 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14052 (match_operator:SF 3 "binary_fp_operator"
14053 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14054 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14055 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14056 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14057 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14058 "* return output_387_binary_op (insn, operands);"
14059 [(set (attr "type")
14060 (cond [(and (eq_attr "alternative" "2")
14061 (match_operand:SF 3 "mult_operator" ""))
14062 (const_string "ssemul")
14063 (and (eq_attr "alternative" "2")
14064 (match_operand:SF 3 "div_operator" ""))
14065 (const_string "ssediv")
14066 (eq_attr "alternative" "2")
14067 (const_string "sseadd")
14068 (match_operand:SF 3 "mult_operator" "")
14069 (const_string "fmul")
14070 (match_operand:SF 3 "div_operator" "")
14071 (const_string "fdiv")
14073 (const_string "fop")))
14074 (set_attr "mode" "SF")])
14076 (define_insn "*fop_sf_1_sse"
14077 [(set (match_operand:SF 0 "register_operand" "=x")
14078 (match_operator:SF 3 "binary_fp_operator"
14079 [(match_operand:SF 1 "register_operand" "0")
14080 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14082 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14083 "* return output_387_binary_op (insn, operands);"
14084 [(set (attr "type")
14085 (cond [(match_operand:SF 3 "mult_operator" "")
14086 (const_string "ssemul")
14087 (match_operand:SF 3 "div_operator" "")
14088 (const_string "ssediv")
14090 (const_string "sseadd")))
14091 (set_attr "mode" "SF")])
14093 ;; ??? Add SSE splitters for these!
14094 (define_insn "*fop_sf_2"
14095 [(set (match_operand:SF 0 "register_operand" "=f,f")
14096 (match_operator:SF 3 "binary_fp_operator"
14097 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14098 (match_operand:SF 2 "register_operand" "0,0")]))]
14099 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14100 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14101 [(set (attr "type")
14102 (cond [(match_operand:SF 3 "mult_operator" "")
14103 (const_string "fmul")
14104 (match_operand:SF 3 "div_operator" "")
14105 (const_string "fdiv")
14107 (const_string "fop")))
14108 (set_attr "fp_int_src" "true")
14109 (set_attr "ppro_uops" "many")
14110 (set_attr "mode" "SI")])
14112 (define_insn "*fop_sf_3"
14113 [(set (match_operand:SF 0 "register_operand" "=f,f")
14114 (match_operator:SF 3 "binary_fp_operator"
14115 [(match_operand:SF 1 "register_operand" "0,0")
14116 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14117 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14118 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14119 [(set (attr "type")
14120 (cond [(match_operand:SF 3 "mult_operator" "")
14121 (const_string "fmul")
14122 (match_operand:SF 3 "div_operator" "")
14123 (const_string "fdiv")
14125 (const_string "fop")))
14126 (set_attr "fp_int_src" "true")
14127 (set_attr "ppro_uops" "many")
14128 (set_attr "mode" "SI")])
14130 (define_insn "*fop_df_1_nosse"
14131 [(set (match_operand:DF 0 "register_operand" "=f,f")
14132 (match_operator:DF 3 "binary_fp_operator"
14133 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14134 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14135 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14136 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14137 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14138 "* return output_387_binary_op (insn, operands);"
14139 [(set (attr "type")
14140 (cond [(match_operand:DF 3 "mult_operator" "")
14141 (const_string "fmul")
14142 (match_operand:DF 3 "div_operator" "")
14143 (const_string "fdiv")
14145 (const_string "fop")))
14146 (set_attr "mode" "DF")])
14149 (define_insn "*fop_df_1"
14150 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14151 (match_operator:DF 3 "binary_fp_operator"
14152 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14153 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14154 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14155 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14156 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14157 "* return output_387_binary_op (insn, operands);"
14158 [(set (attr "type")
14159 (cond [(and (eq_attr "alternative" "2")
14160 (match_operand:SF 3 "mult_operator" ""))
14161 (const_string "ssemul")
14162 (and (eq_attr "alternative" "2")
14163 (match_operand:SF 3 "div_operator" ""))
14164 (const_string "ssediv")
14165 (eq_attr "alternative" "2")
14166 (const_string "sseadd")
14167 (match_operand:DF 3 "mult_operator" "")
14168 (const_string "fmul")
14169 (match_operand:DF 3 "div_operator" "")
14170 (const_string "fdiv")
14172 (const_string "fop")))
14173 (set_attr "mode" "DF")])
14175 (define_insn "*fop_df_1_sse"
14176 [(set (match_operand:DF 0 "register_operand" "=Y")
14177 (match_operator:DF 3 "binary_fp_operator"
14178 [(match_operand:DF 1 "register_operand" "0")
14179 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14180 "TARGET_SSE2 && TARGET_SSE_MATH
14181 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14182 "* return output_387_binary_op (insn, operands);"
14183 [(set_attr "mode" "DF")
14185 (cond [(match_operand:SF 3 "mult_operator" "")
14186 (const_string "ssemul")
14187 (match_operand:SF 3 "div_operator" "")
14188 (const_string "ssediv")
14190 (const_string "sseadd")))])
14192 ;; ??? Add SSE splitters for these!
14193 (define_insn "*fop_df_2"
14194 [(set (match_operand:DF 0 "register_operand" "=f,f")
14195 (match_operator:DF 3 "binary_fp_operator"
14196 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14197 (match_operand:DF 2 "register_operand" "0,0")]))]
14198 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14199 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14200 [(set (attr "type")
14201 (cond [(match_operand:DF 3 "mult_operator" "")
14202 (const_string "fmul")
14203 (match_operand:DF 3 "div_operator" "")
14204 (const_string "fdiv")
14206 (const_string "fop")))
14207 (set_attr "fp_int_src" "true")
14208 (set_attr "ppro_uops" "many")
14209 (set_attr "mode" "SI")])
14211 (define_insn "*fop_df_3"
14212 [(set (match_operand:DF 0 "register_operand" "=f,f")
14213 (match_operator:DF 3 "binary_fp_operator"
14214 [(match_operand:DF 1 "register_operand" "0,0")
14215 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14216 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14217 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14218 [(set (attr "type")
14219 (cond [(match_operand:DF 3 "mult_operator" "")
14220 (const_string "fmul")
14221 (match_operand:DF 3 "div_operator" "")
14222 (const_string "fdiv")
14224 (const_string "fop")))
14225 (set_attr "fp_int_src" "true")
14226 (set_attr "ppro_uops" "many")
14227 (set_attr "mode" "SI")])
14229 (define_insn "*fop_df_4"
14230 [(set (match_operand:DF 0 "register_operand" "=f,f")
14231 (match_operator:DF 3 "binary_fp_operator"
14232 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14233 (match_operand:DF 2 "register_operand" "0,f")]))]
14234 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14235 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14236 "* return output_387_binary_op (insn, operands);"
14237 [(set (attr "type")
14238 (cond [(match_operand:DF 3 "mult_operator" "")
14239 (const_string "fmul")
14240 (match_operand:DF 3 "div_operator" "")
14241 (const_string "fdiv")
14243 (const_string "fop")))
14244 (set_attr "mode" "SF")])
14246 (define_insn "*fop_df_5"
14247 [(set (match_operand:DF 0 "register_operand" "=f,f")
14248 (match_operator:DF 3 "binary_fp_operator"
14249 [(match_operand:DF 1 "register_operand" "0,f")
14251 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14252 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14253 "* return output_387_binary_op (insn, operands);"
14254 [(set (attr "type")
14255 (cond [(match_operand:DF 3 "mult_operator" "")
14256 (const_string "fmul")
14257 (match_operand:DF 3 "div_operator" "")
14258 (const_string "fdiv")
14260 (const_string "fop")))
14261 (set_attr "mode" "SF")])
14263 (define_insn "*fop_xf_1"
14264 [(set (match_operand:XF 0 "register_operand" "=f,f")
14265 (match_operator:XF 3 "binary_fp_operator"
14266 [(match_operand:XF 1 "register_operand" "0,f")
14267 (match_operand:XF 2 "register_operand" "f,0")]))]
14268 "!TARGET_64BIT && TARGET_80387
14269 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14270 "* return output_387_binary_op (insn, operands);"
14271 [(set (attr "type")
14272 (cond [(match_operand:XF 3 "mult_operator" "")
14273 (const_string "fmul")
14274 (match_operand:XF 3 "div_operator" "")
14275 (const_string "fdiv")
14277 (const_string "fop")))
14278 (set_attr "mode" "XF")])
14280 (define_insn "*fop_tf_1"
14281 [(set (match_operand:TF 0 "register_operand" "=f,f")
14282 (match_operator:TF 3 "binary_fp_operator"
14283 [(match_operand:TF 1 "register_operand" "0,f")
14284 (match_operand:TF 2 "register_operand" "f,0")]))]
14286 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14287 "* return output_387_binary_op (insn, operands);"
14288 [(set (attr "type")
14289 (cond [(match_operand:TF 3 "mult_operator" "")
14290 (const_string "fmul")
14291 (match_operand:TF 3 "div_operator" "")
14292 (const_string "fdiv")
14294 (const_string "fop")))
14295 (set_attr "mode" "XF")])
14297 (define_insn "*fop_xf_2"
14298 [(set (match_operand:XF 0 "register_operand" "=f,f")
14299 (match_operator:XF 3 "binary_fp_operator"
14300 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14301 (match_operand:XF 2 "register_operand" "0,0")]))]
14302 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
14303 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14304 [(set (attr "type")
14305 (cond [(match_operand:XF 3 "mult_operator" "")
14306 (const_string "fmul")
14307 (match_operand:XF 3 "div_operator" "")
14308 (const_string "fdiv")
14310 (const_string "fop")))
14311 (set_attr "fp_int_src" "true")
14312 (set_attr "mode" "SI")
14313 (set_attr "ppro_uops" "many")])
14315 (define_insn "*fop_tf_2"
14316 [(set (match_operand:TF 0 "register_operand" "=f,f")
14317 (match_operator:TF 3 "binary_fp_operator"
14318 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14319 (match_operand:TF 2 "register_operand" "0,0")]))]
14320 "TARGET_80387 && TARGET_USE_FIOP"
14321 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14322 [(set (attr "type")
14323 (cond [(match_operand:TF 3 "mult_operator" "")
14324 (const_string "fmul")
14325 (match_operand:TF 3 "div_operator" "")
14326 (const_string "fdiv")
14328 (const_string "fop")))
14329 (set_attr "fp_int_src" "true")
14330 (set_attr "mode" "SI")
14331 (set_attr "ppro_uops" "many")])
14333 (define_insn "*fop_xf_3"
14334 [(set (match_operand:XF 0 "register_operand" "=f,f")
14335 (match_operator:XF 3 "binary_fp_operator"
14336 [(match_operand:XF 1 "register_operand" "0,0")
14337 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14338 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
14339 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14340 [(set (attr "type")
14341 (cond [(match_operand:XF 3 "mult_operator" "")
14342 (const_string "fmul")
14343 (match_operand:XF 3 "div_operator" "")
14344 (const_string "fdiv")
14346 (const_string "fop")))
14347 (set_attr "fp_int_src" "true")
14348 (set_attr "mode" "SI")
14349 (set_attr "ppro_uops" "many")])
14351 (define_insn "*fop_tf_3"
14352 [(set (match_operand:TF 0 "register_operand" "=f,f")
14353 (match_operator:TF 3 "binary_fp_operator"
14354 [(match_operand:TF 1 "register_operand" "0,0")
14355 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14356 "TARGET_80387 && TARGET_USE_FIOP"
14357 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14358 [(set (attr "type")
14359 (cond [(match_operand:TF 3 "mult_operator" "")
14360 (const_string "fmul")
14361 (match_operand:TF 3 "div_operator" "")
14362 (const_string "fdiv")
14364 (const_string "fop")))
14365 (set_attr "fp_int_src" "true")
14366 (set_attr "mode" "SI")
14367 (set_attr "ppro_uops" "many")])
14369 (define_insn "*fop_xf_4"
14370 [(set (match_operand:XF 0 "register_operand" "=f,f")
14371 (match_operator:XF 3 "binary_fp_operator"
14372 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14373 (match_operand:XF 2 "register_operand" "0,f")]))]
14374 "!TARGET_64BIT && TARGET_80387"
14375 "* return output_387_binary_op (insn, operands);"
14376 [(set (attr "type")
14377 (cond [(match_operand:XF 3 "mult_operator" "")
14378 (const_string "fmul")
14379 (match_operand:XF 3 "div_operator" "")
14380 (const_string "fdiv")
14382 (const_string "fop")))
14383 (set_attr "mode" "SF")])
14385 (define_insn "*fop_tf_4"
14386 [(set (match_operand:TF 0 "register_operand" "=f,f")
14387 (match_operator:TF 3 "binary_fp_operator"
14388 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14389 (match_operand:TF 2 "register_operand" "0,f")]))]
14391 "* return output_387_binary_op (insn, operands);"
14392 [(set (attr "type")
14393 (cond [(match_operand:TF 3 "mult_operator" "")
14394 (const_string "fmul")
14395 (match_operand:TF 3 "div_operator" "")
14396 (const_string "fdiv")
14398 (const_string "fop")))
14399 (set_attr "mode" "SF")])
14401 (define_insn "*fop_xf_5"
14402 [(set (match_operand:XF 0 "register_operand" "=f,f")
14403 (match_operator:XF 3 "binary_fp_operator"
14404 [(match_operand:XF 1 "register_operand" "0,f")
14406 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14407 "!TARGET_64BIT && TARGET_80387"
14408 "* return output_387_binary_op (insn, operands);"
14409 [(set (attr "type")
14410 (cond [(match_operand:XF 3 "mult_operator" "")
14411 (const_string "fmul")
14412 (match_operand:XF 3 "div_operator" "")
14413 (const_string "fdiv")
14415 (const_string "fop")))
14416 (set_attr "mode" "SF")])
14418 (define_insn "*fop_tf_5"
14419 [(set (match_operand:TF 0 "register_operand" "=f,f")
14420 (match_operator:TF 3 "binary_fp_operator"
14421 [(match_operand:TF 1 "register_operand" "0,f")
14423 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14425 "* return output_387_binary_op (insn, operands);"
14426 [(set (attr "type")
14427 (cond [(match_operand:TF 3 "mult_operator" "")
14428 (const_string "fmul")
14429 (match_operand:TF 3 "div_operator" "")
14430 (const_string "fdiv")
14432 (const_string "fop")))
14433 (set_attr "mode" "SF")])
14435 (define_insn "*fop_xf_6"
14436 [(set (match_operand:XF 0 "register_operand" "=f,f")
14437 (match_operator:XF 3 "binary_fp_operator"
14438 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14439 (match_operand:XF 2 "register_operand" "0,f")]))]
14440 "!TARGET_64BIT && TARGET_80387"
14441 "* return output_387_binary_op (insn, operands);"
14442 [(set (attr "type")
14443 (cond [(match_operand:XF 3 "mult_operator" "")
14444 (const_string "fmul")
14445 (match_operand:XF 3 "div_operator" "")
14446 (const_string "fdiv")
14448 (const_string "fop")))
14449 (set_attr "mode" "DF")])
14451 (define_insn "*fop_tf_6"
14452 [(set (match_operand:TF 0 "register_operand" "=f,f")
14453 (match_operator:TF 3 "binary_fp_operator"
14454 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
14455 (match_operand:TF 2 "register_operand" "0,f")]))]
14457 "* return output_387_binary_op (insn, operands);"
14458 [(set (attr "type")
14459 (cond [(match_operand:TF 3 "mult_operator" "")
14460 (const_string "fmul")
14461 (match_operand:TF 3 "div_operator" "")
14462 (const_string "fdiv")
14464 (const_string "fop")))
14465 (set_attr "mode" "DF")])
14467 (define_insn "*fop_xf_7"
14468 [(set (match_operand:XF 0 "register_operand" "=f,f")
14469 (match_operator:XF 3 "binary_fp_operator"
14470 [(match_operand:XF 1 "register_operand" "0,f")
14472 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14473 "!TARGET_64BIT && TARGET_80387"
14474 "* return output_387_binary_op (insn, operands);"
14475 [(set (attr "type")
14476 (cond [(match_operand:XF 3 "mult_operator" "")
14477 (const_string "fmul")
14478 (match_operand:XF 3 "div_operator" "")
14479 (const_string "fdiv")
14481 (const_string "fop")))
14482 (set_attr "mode" "DF")])
14484 (define_insn "*fop_tf_7"
14485 [(set (match_operand:TF 0 "register_operand" "=f,f")
14486 (match_operator:TF 3 "binary_fp_operator"
14487 [(match_operand:TF 1 "register_operand" "0,f")
14489 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
14491 "* return output_387_binary_op (insn, operands);"
14492 [(set (attr "type")
14493 (cond [(match_operand:TF 3 "mult_operator" "")
14494 (const_string "fmul")
14495 (match_operand:TF 3 "div_operator" "")
14496 (const_string "fdiv")
14498 (const_string "fop")))
14499 (set_attr "mode" "DF")])
14502 [(set (match_operand 0 "register_operand" "")
14503 (match_operator 3 "binary_fp_operator"
14504 [(float (match_operand:SI 1 "register_operand" ""))
14505 (match_operand 2 "register_operand" "")]))]
14506 "TARGET_80387 && reload_completed
14507 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14510 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14511 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14512 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14513 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14514 GET_MODE (operands[3]),
14517 ix86_free_from_memory (GET_MODE (operands[1]));
14522 [(set (match_operand 0 "register_operand" "")
14523 (match_operator 3 "binary_fp_operator"
14524 [(match_operand 1 "register_operand" "")
14525 (float (match_operand:SI 2 "register_operand" ""))]))]
14526 "TARGET_80387 && reload_completed
14527 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14530 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14531 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14532 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14533 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14534 GET_MODE (operands[3]),
14537 ix86_free_from_memory (GET_MODE (operands[2]));
14541 ;; FPU special functions.
14543 (define_expand "sqrtsf2"
14544 [(set (match_operand:SF 0 "register_operand" "")
14545 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14546 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
14548 if (!TARGET_SSE_MATH)
14549 operands[1] = force_reg (SFmode, operands[1]);
14552 (define_insn "sqrtsf2_1"
14553 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14554 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14555 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14556 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14559 sqrtss\t{%1, %0|%0, %1}"
14560 [(set_attr "type" "fpspc,sse")
14561 (set_attr "mode" "SF,SF")
14562 (set_attr "athlon_decode" "direct,*")])
14564 (define_insn "sqrtsf2_1_sse_only"
14565 [(set (match_operand:SF 0 "register_operand" "=x")
14566 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14567 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14568 "sqrtss\t{%1, %0|%0, %1}"
14569 [(set_attr "type" "sse")
14570 (set_attr "mode" "SF")
14571 (set_attr "athlon_decode" "*")])
14573 (define_insn "sqrtsf2_i387"
14574 [(set (match_operand:SF 0 "register_operand" "=f")
14575 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14576 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14577 && !TARGET_SSE_MATH"
14579 [(set_attr "type" "fpspc")
14580 (set_attr "mode" "SF")
14581 (set_attr "athlon_decode" "direct")])
14583 (define_expand "sqrtdf2"
14584 [(set (match_operand:DF 0 "register_operand" "")
14585 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14586 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
14587 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14589 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
14590 operands[1] = force_reg (DFmode, operands[1]);
14593 (define_insn "sqrtdf2_1"
14594 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14595 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14596 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14597 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14600 sqrtsd\t{%1, %0|%0, %1}"
14601 [(set_attr "type" "fpspc,sse")
14602 (set_attr "mode" "DF,DF")
14603 (set_attr "athlon_decode" "direct,*")])
14605 (define_insn "sqrtdf2_1_sse_only"
14606 [(set (match_operand:DF 0 "register_operand" "=Y")
14607 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14608 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14609 "sqrtsd\t{%1, %0|%0, %1}"
14610 [(set_attr "type" "sse")
14611 (set_attr "mode" "DF")
14612 (set_attr "athlon_decode" "*")])
14614 (define_insn "sqrtdf2_i387"
14615 [(set (match_operand:DF 0 "register_operand" "=f")
14616 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14617 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14618 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
14620 [(set_attr "type" "fpspc")
14621 (set_attr "mode" "DF")
14622 (set_attr "athlon_decode" "direct")])
14624 (define_insn "*sqrtextendsfdf2"
14625 [(set (match_operand:DF 0 "register_operand" "=f")
14626 (sqrt:DF (float_extend:DF
14627 (match_operand:SF 1 "register_operand" "0"))))]
14628 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14629 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14631 [(set_attr "type" "fpspc")
14632 (set_attr "mode" "DF")
14633 (set_attr "athlon_decode" "direct")])
14635 (define_insn "sqrtxf2"
14636 [(set (match_operand:XF 0 "register_operand" "=f")
14637 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14638 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14639 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14641 [(set_attr "type" "fpspc")
14642 (set_attr "mode" "XF")
14643 (set_attr "athlon_decode" "direct")])
14645 (define_insn "sqrttf2"
14646 [(set (match_operand:TF 0 "register_operand" "=f")
14647 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
14648 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14649 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14651 [(set_attr "type" "fpspc")
14652 (set_attr "mode" "XF")
14653 (set_attr "athlon_decode" "direct")])
14655 (define_insn "*sqrtextenddfxf2"
14656 [(set (match_operand:XF 0 "register_operand" "=f")
14657 (sqrt:XF (float_extend:XF
14658 (match_operand:DF 1 "register_operand" "0"))))]
14659 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14661 [(set_attr "type" "fpspc")
14662 (set_attr "mode" "XF")
14663 (set_attr "athlon_decode" "direct")])
14665 (define_insn "*sqrtextenddftf2"
14666 [(set (match_operand:TF 0 "register_operand" "=f")
14667 (sqrt:TF (float_extend:TF
14668 (match_operand:DF 1 "register_operand" "0"))))]
14669 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14671 [(set_attr "type" "fpspc")
14672 (set_attr "mode" "XF")
14673 (set_attr "athlon_decode" "direct")])
14675 (define_insn "*sqrtextendsfxf2"
14676 [(set (match_operand:XF 0 "register_operand" "=f")
14677 (sqrt:XF (float_extend:XF
14678 (match_operand:SF 1 "register_operand" "0"))))]
14679 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14681 [(set_attr "type" "fpspc")
14682 (set_attr "mode" "XF")
14683 (set_attr "athlon_decode" "direct")])
14685 (define_insn "*sqrtextendsftf2"
14686 [(set (match_operand:TF 0 "register_operand" "=f")
14687 (sqrt:TF (float_extend:TF
14688 (match_operand:SF 1 "register_operand" "0"))))]
14689 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
14691 [(set_attr "type" "fpspc")
14692 (set_attr "mode" "XF")
14693 (set_attr "athlon_decode" "direct")])
14695 (define_insn "sindf2"
14696 [(set (match_operand:DF 0 "register_operand" "=f")
14697 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14698 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14699 && flag_unsafe_math_optimizations"
14701 [(set_attr "type" "fpspc")
14702 (set_attr "mode" "DF")])
14704 (define_insn "sinsf2"
14705 [(set (match_operand:SF 0 "register_operand" "=f")
14706 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14707 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14708 && flag_unsafe_math_optimizations"
14710 [(set_attr "type" "fpspc")
14711 (set_attr "mode" "SF")])
14713 (define_insn "*sinextendsfdf2"
14714 [(set (match_operand:DF 0 "register_operand" "=f")
14715 (unspec:DF [(float_extend:DF
14716 (match_operand:SF 1 "register_operand" "0"))]
14718 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14719 && flag_unsafe_math_optimizations"
14721 [(set_attr "type" "fpspc")
14722 (set_attr "mode" "DF")])
14724 (define_insn "sinxf2"
14725 [(set (match_operand:XF 0 "register_operand" "=f")
14726 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14727 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14728 && flag_unsafe_math_optimizations"
14730 [(set_attr "type" "fpspc")
14731 (set_attr "mode" "XF")])
14733 (define_insn "sintf2"
14734 [(set (match_operand:TF 0 "register_operand" "=f")
14735 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
14736 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14737 && flag_unsafe_math_optimizations"
14739 [(set_attr "type" "fpspc")
14740 (set_attr "mode" "XF")])
14742 (define_insn "cosdf2"
14743 [(set (match_operand:DF 0 "register_operand" "=f")
14744 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14745 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14746 && flag_unsafe_math_optimizations"
14748 [(set_attr "type" "fpspc")
14749 (set_attr "mode" "DF")])
14751 (define_insn "cossf2"
14752 [(set (match_operand:SF 0 "register_operand" "=f")
14753 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14754 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14755 && flag_unsafe_math_optimizations"
14757 [(set_attr "type" "fpspc")
14758 (set_attr "mode" "SF")])
14760 (define_insn "*cosextendsfdf2"
14761 [(set (match_operand:DF 0 "register_operand" "=f")
14762 (unspec:DF [(float_extend:DF
14763 (match_operand:SF 1 "register_operand" "0"))]
14765 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14766 && flag_unsafe_math_optimizations"
14768 [(set_attr "type" "fpspc")
14769 (set_attr "mode" "DF")])
14771 (define_insn "cosxf2"
14772 [(set (match_operand:XF 0 "register_operand" "=f")
14773 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14774 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14775 && flag_unsafe_math_optimizations"
14777 [(set_attr "type" "fpspc")
14778 (set_attr "mode" "XF")])
14780 (define_insn "costf2"
14781 [(set (match_operand:TF 0 "register_operand" "=f")
14782 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
14783 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14784 && flag_unsafe_math_optimizations"
14786 [(set_attr "type" "fpspc")
14787 (set_attr "mode" "XF")])
14789 ;; Block operation instructions
14792 [(set (reg:SI 19) (const_int 0))]
14795 [(set_attr "type" "cld")])
14797 (define_expand "movstrsi"
14798 [(use (match_operand:BLK 0 "memory_operand" ""))
14799 (use (match_operand:BLK 1 "memory_operand" ""))
14800 (use (match_operand:SI 2 "nonmemory_operand" ""))
14801 (use (match_operand:SI 3 "const_int_operand" ""))]
14804 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14810 (define_expand "movstrdi"
14811 [(use (match_operand:BLK 0 "memory_operand" ""))
14812 (use (match_operand:BLK 1 "memory_operand" ""))
14813 (use (match_operand:DI 2 "nonmemory_operand" ""))
14814 (use (match_operand:DI 3 "const_int_operand" ""))]
14817 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
14823 ;; Most CPUs don't like single string operations
14824 ;; Handle this case here to simplify previous expander.
14826 (define_expand "strmovdi_rex64"
14827 [(set (match_dup 2)
14828 (mem:DI (match_operand:DI 1 "register_operand" "")))
14829 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
14831 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
14832 (clobber (reg:CC 17))])
14833 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
14834 (clobber (reg:CC 17))])]
14837 if (TARGET_SINGLE_STRINGOP || optimize_size)
14839 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
14844 operands[2] = gen_reg_rtx (DImode);
14848 (define_expand "strmovsi"
14849 [(set (match_dup 2)
14850 (mem:SI (match_operand:SI 1 "register_operand" "")))
14851 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
14853 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
14854 (clobber (reg:CC 17))])
14855 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
14856 (clobber (reg:CC 17))])]
14861 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
14864 if (TARGET_SINGLE_STRINGOP || optimize_size)
14866 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
14871 operands[2] = gen_reg_rtx (SImode);
14874 (define_expand "strmovsi_rex64"
14875 [(set (match_dup 2)
14876 (mem:SI (match_operand:DI 1 "register_operand" "")))
14877 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
14879 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
14880 (clobber (reg:CC 17))])
14881 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
14882 (clobber (reg:CC 17))])]
14885 if (TARGET_SINGLE_STRINGOP || optimize_size)
14887 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
14892 operands[2] = gen_reg_rtx (SImode);
14895 (define_expand "strmovhi"
14896 [(set (match_dup 2)
14897 (mem:HI (match_operand:SI 1 "register_operand" "")))
14898 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
14900 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
14901 (clobber (reg:CC 17))])
14902 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
14903 (clobber (reg:CC 17))])]
14908 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
14911 if (TARGET_SINGLE_STRINGOP || optimize_size)
14913 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
14918 operands[2] = gen_reg_rtx (HImode);
14921 (define_expand "strmovhi_rex64"
14922 [(set (match_dup 2)
14923 (mem:HI (match_operand:DI 1 "register_operand" "")))
14924 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
14926 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
14927 (clobber (reg:CC 17))])
14928 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
14929 (clobber (reg:CC 17))])]
14932 if (TARGET_SINGLE_STRINGOP || optimize_size)
14934 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
14939 operands[2] = gen_reg_rtx (HImode);
14942 (define_expand "strmovqi"
14943 [(set (match_dup 2)
14944 (mem:QI (match_operand:SI 1 "register_operand" "")))
14945 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
14947 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14948 (clobber (reg:CC 17))])
14949 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
14950 (clobber (reg:CC 17))])]
14955 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
14958 if (TARGET_SINGLE_STRINGOP || optimize_size)
14960 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
14965 operands[2] = gen_reg_rtx (QImode);
14968 (define_expand "strmovqi_rex64"
14969 [(set (match_dup 2)
14970 (mem:QI (match_operand:DI 1 "register_operand" "")))
14971 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
14973 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14974 (clobber (reg:CC 17))])
14975 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
14976 (clobber (reg:CC 17))])]
14979 if (TARGET_SINGLE_STRINGOP || optimize_size)
14981 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
14986 operands[2] = gen_reg_rtx (QImode);
14989 (define_insn "strmovdi_rex_1"
14990 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
14991 (mem:DI (match_operand:DI 3 "register_operand" "1")))
14992 (set (match_operand:DI 0 "register_operand" "=D")
14993 (plus:DI (match_dup 2)
14995 (set (match_operand:DI 1 "register_operand" "=S")
14996 (plus:DI (match_dup 3)
14999 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15001 [(set_attr "type" "str")
15002 (set_attr "mode" "DI")
15003 (set_attr "memory" "both")])
15005 (define_insn "strmovsi_1"
15006 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
15007 (mem:SI (match_operand:SI 3 "register_operand" "1")))
15008 (set (match_operand:SI 0 "register_operand" "=D")
15009 (plus:SI (match_dup 2)
15011 (set (match_operand:SI 1 "register_operand" "=S")
15012 (plus:SI (match_dup 3)
15015 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15017 [(set_attr "type" "str")
15018 (set_attr "mode" "SI")
15019 (set_attr "memory" "both")])
15021 (define_insn "strmovsi_rex_1"
15022 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
15023 (mem:SI (match_operand:DI 3 "register_operand" "1")))
15024 (set (match_operand:DI 0 "register_operand" "=D")
15025 (plus:DI (match_dup 2)
15027 (set (match_operand:DI 1 "register_operand" "=S")
15028 (plus:DI (match_dup 3)
15031 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15033 [(set_attr "type" "str")
15034 (set_attr "mode" "SI")
15035 (set_attr "memory" "both")])
15037 (define_insn "strmovhi_1"
15038 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
15039 (mem:HI (match_operand:SI 3 "register_operand" "1")))
15040 (set (match_operand:SI 0 "register_operand" "=D")
15041 (plus:SI (match_dup 2)
15043 (set (match_operand:SI 1 "register_operand" "=S")
15044 (plus:SI (match_dup 3)
15047 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15049 [(set_attr "type" "str")
15050 (set_attr "memory" "both")
15051 (set_attr "mode" "HI")])
15053 (define_insn "strmovhi_rex_1"
15054 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
15055 (mem:HI (match_operand:DI 3 "register_operand" "1")))
15056 (set (match_operand:DI 0 "register_operand" "=D")
15057 (plus:DI (match_dup 2)
15059 (set (match_operand:DI 1 "register_operand" "=S")
15060 (plus:DI (match_dup 3)
15063 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15065 [(set_attr "type" "str")
15066 (set_attr "memory" "both")
15067 (set_attr "mode" "HI")])
15069 (define_insn "strmovqi_1"
15070 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
15071 (mem:QI (match_operand:SI 3 "register_operand" "1")))
15072 (set (match_operand:SI 0 "register_operand" "=D")
15073 (plus:SI (match_dup 2)
15075 (set (match_operand:SI 1 "register_operand" "=S")
15076 (plus:SI (match_dup 3)
15079 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15081 [(set_attr "type" "str")
15082 (set_attr "memory" "both")
15083 (set_attr "mode" "QI")])
15085 (define_insn "strmovqi_rex_1"
15086 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
15087 (mem:QI (match_operand:DI 3 "register_operand" "1")))
15088 (set (match_operand:DI 0 "register_operand" "=D")
15089 (plus:DI (match_dup 2)
15091 (set (match_operand:DI 1 "register_operand" "=S")
15092 (plus:DI (match_dup 3)
15095 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15097 [(set_attr "type" "str")
15098 (set_attr "memory" "both")
15099 (set_attr "mode" "QI")])
15101 (define_insn "rep_movdi_rex64"
15102 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15103 (set (match_operand:DI 0 "register_operand" "=D")
15104 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15106 (match_operand:DI 3 "register_operand" "0")))
15107 (set (match_operand:DI 1 "register_operand" "=S")
15108 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15109 (match_operand:DI 4 "register_operand" "1")))
15110 (set (mem:BLK (match_dup 3))
15111 (mem:BLK (match_dup 4)))
15112 (use (match_dup 5))
15115 "{rep\;movsq|rep movsq}"
15116 [(set_attr "type" "str")
15117 (set_attr "prefix_rep" "1")
15118 (set_attr "memory" "both")
15119 (set_attr "mode" "DI")])
15121 (define_insn "rep_movsi"
15122 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15123 (set (match_operand:SI 0 "register_operand" "=D")
15124 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
15126 (match_operand:SI 3 "register_operand" "0")))
15127 (set (match_operand:SI 1 "register_operand" "=S")
15128 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
15129 (match_operand:SI 4 "register_operand" "1")))
15130 (set (mem:BLK (match_dup 3))
15131 (mem:BLK (match_dup 4)))
15132 (use (match_dup 5))
15135 "{rep\;movsl|rep movsd}"
15136 [(set_attr "type" "str")
15137 (set_attr "prefix_rep" "1")
15138 (set_attr "memory" "both")
15139 (set_attr "mode" "SI")])
15141 (define_insn "rep_movsi_rex64"
15142 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15143 (set (match_operand:DI 0 "register_operand" "=D")
15144 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15146 (match_operand:DI 3 "register_operand" "0")))
15147 (set (match_operand:DI 1 "register_operand" "=S")
15148 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
15149 (match_operand:DI 4 "register_operand" "1")))
15150 (set (mem:BLK (match_dup 3))
15151 (mem:BLK (match_dup 4)))
15152 (use (match_dup 5))
15155 "{rep\;movsl|rep movsd}"
15156 [(set_attr "type" "str")
15157 (set_attr "prefix_rep" "1")
15158 (set_attr "memory" "both")
15159 (set_attr "mode" "SI")])
15161 (define_insn "rep_movqi"
15162 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15163 (set (match_operand:SI 0 "register_operand" "=D")
15164 (plus:SI (match_operand:SI 3 "register_operand" "0")
15165 (match_operand:SI 5 "register_operand" "2")))
15166 (set (match_operand:SI 1 "register_operand" "=S")
15167 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
15168 (set (mem:BLK (match_dup 3))
15169 (mem:BLK (match_dup 4)))
15170 (use (match_dup 5))
15173 "{rep\;movsb|rep movsb}"
15174 [(set_attr "type" "str")
15175 (set_attr "prefix_rep" "1")
15176 (set_attr "memory" "both")
15177 (set_attr "mode" "SI")])
15179 (define_insn "rep_movqi_rex64"
15180 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15181 (set (match_operand:DI 0 "register_operand" "=D")
15182 (plus:DI (match_operand:DI 3 "register_operand" "0")
15183 (match_operand:DI 5 "register_operand" "2")))
15184 (set (match_operand:DI 1 "register_operand" "=S")
15185 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
15186 (set (mem:BLK (match_dup 3))
15187 (mem:BLK (match_dup 4)))
15188 (use (match_dup 5))
15191 "{rep\;movsb|rep movsb}"
15192 [(set_attr "type" "str")
15193 (set_attr "prefix_rep" "1")
15194 (set_attr "memory" "both")
15195 (set_attr "mode" "SI")])
15197 (define_expand "clrstrsi"
15198 [(use (match_operand:BLK 0 "memory_operand" ""))
15199 (use (match_operand:SI 1 "nonmemory_operand" ""))
15200 (use (match_operand 2 "const_int_operand" ""))]
15203 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15209 (define_expand "clrstrdi"
15210 [(use (match_operand:BLK 0 "memory_operand" ""))
15211 (use (match_operand:DI 1 "nonmemory_operand" ""))
15212 (use (match_operand 2 "const_int_operand" ""))]
15215 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15221 ;; Most CPUs don't like single string operations
15222 ;; Handle this case here to simplify previous expander.
15224 (define_expand "strsetdi_rex64"
15225 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
15226 (match_operand:DI 1 "register_operand" ""))
15227 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15228 (clobber (reg:CC 17))])]
15231 if (TARGET_SINGLE_STRINGOP || optimize_size)
15233 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
15238 (define_expand "strsetsi"
15239 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
15240 (match_operand:SI 1 "register_operand" ""))
15241 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15242 (clobber (reg:CC 17))])]
15247 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
15250 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15252 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
15257 (define_expand "strsetsi_rex64"
15258 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
15259 (match_operand:SI 1 "register_operand" ""))
15260 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15261 (clobber (reg:CC 17))])]
15264 if (TARGET_SINGLE_STRINGOP || optimize_size)
15266 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
15271 (define_expand "strsethi"
15272 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
15273 (match_operand:HI 1 "register_operand" ""))
15274 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15275 (clobber (reg:CC 17))])]
15280 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
15283 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15285 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
15290 (define_expand "strsethi_rex64"
15291 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
15292 (match_operand:HI 1 "register_operand" ""))
15293 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15294 (clobber (reg:CC 17))])]
15297 if (TARGET_SINGLE_STRINGOP || optimize_size)
15299 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
15304 (define_expand "strsetqi"
15305 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
15306 (match_operand:QI 1 "register_operand" ""))
15307 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15308 (clobber (reg:CC 17))])]
15313 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
15316 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15318 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
15323 (define_expand "strsetqi_rex64"
15324 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
15325 (match_operand:QI 1 "register_operand" ""))
15326 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15327 (clobber (reg:CC 17))])]
15330 if (TARGET_SINGLE_STRINGOP || optimize_size)
15332 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
15337 (define_insn "strsetdi_rex_1"
15338 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15339 (match_operand:SI 2 "register_operand" "a"))
15340 (set (match_operand:DI 0 "register_operand" "=D")
15341 (plus:DI (match_dup 1)
15344 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15346 [(set_attr "type" "str")
15347 (set_attr "memory" "store")
15348 (set_attr "mode" "DI")])
15350 (define_insn "strsetsi_1"
15351 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15352 (match_operand:SI 2 "register_operand" "a"))
15353 (set (match_operand:SI 0 "register_operand" "=D")
15354 (plus:SI (match_dup 1)
15357 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15359 [(set_attr "type" "str")
15360 (set_attr "memory" "store")
15361 (set_attr "mode" "SI")])
15363 (define_insn "strsetsi_rex_1"
15364 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15365 (match_operand:SI 2 "register_operand" "a"))
15366 (set (match_operand:DI 0 "register_operand" "=D")
15367 (plus:DI (match_dup 1)
15370 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15372 [(set_attr "type" "str")
15373 (set_attr "memory" "store")
15374 (set_attr "mode" "SI")])
15376 (define_insn "strsethi_1"
15377 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15378 (match_operand:HI 2 "register_operand" "a"))
15379 (set (match_operand:SI 0 "register_operand" "=D")
15380 (plus:SI (match_dup 1)
15383 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15385 [(set_attr "type" "str")
15386 (set_attr "memory" "store")
15387 (set_attr "mode" "HI")])
15389 (define_insn "strsethi_rex_1"
15390 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15391 (match_operand:HI 2 "register_operand" "a"))
15392 (set (match_operand:DI 0 "register_operand" "=D")
15393 (plus:DI (match_dup 1)
15396 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15398 [(set_attr "type" "str")
15399 (set_attr "memory" "store")
15400 (set_attr "mode" "HI")])
15402 (define_insn "strsetqi_1"
15403 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15404 (match_operand:QI 2 "register_operand" "a"))
15405 (set (match_operand:SI 0 "register_operand" "=D")
15406 (plus:SI (match_dup 1)
15409 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15411 [(set_attr "type" "str")
15412 (set_attr "memory" "store")
15413 (set_attr "mode" "QI")])
15415 (define_insn "strsetqi_rex_1"
15416 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15417 (match_operand:QI 2 "register_operand" "a"))
15418 (set (match_operand:DI 0 "register_operand" "=D")
15419 (plus:DI (match_dup 1)
15422 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15424 [(set_attr "type" "str")
15425 (set_attr "memory" "store")
15426 (set_attr "mode" "QI")])
15428 (define_insn "rep_stosdi_rex64"
15429 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15430 (set (match_operand:DI 0 "register_operand" "=D")
15431 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15433 (match_operand:DI 3 "register_operand" "0")))
15434 (set (mem:BLK (match_dup 3))
15436 (use (match_operand:DI 2 "register_operand" "a"))
15437 (use (match_dup 4))
15440 "{rep\;stosq|rep stosq}"
15441 [(set_attr "type" "str")
15442 (set_attr "prefix_rep" "1")
15443 (set_attr "memory" "store")
15444 (set_attr "mode" "DI")])
15446 (define_insn "rep_stossi"
15447 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15448 (set (match_operand:SI 0 "register_operand" "=D")
15449 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15451 (match_operand:SI 3 "register_operand" "0")))
15452 (set (mem:BLK (match_dup 3))
15454 (use (match_operand:SI 2 "register_operand" "a"))
15455 (use (match_dup 4))
15458 "{rep\;stosl|rep stosd}"
15459 [(set_attr "type" "str")
15460 (set_attr "prefix_rep" "1")
15461 (set_attr "memory" "store")
15462 (set_attr "mode" "SI")])
15464 (define_insn "rep_stossi_rex64"
15465 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15466 (set (match_operand:DI 0 "register_operand" "=D")
15467 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15469 (match_operand:DI 3 "register_operand" "0")))
15470 (set (mem:BLK (match_dup 3))
15472 (use (match_operand:SI 2 "register_operand" "a"))
15473 (use (match_dup 4))
15476 "{rep\;stosl|rep stosd}"
15477 [(set_attr "type" "str")
15478 (set_attr "prefix_rep" "1")
15479 (set_attr "memory" "store")
15480 (set_attr "mode" "SI")])
15482 (define_insn "rep_stosqi"
15483 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15484 (set (match_operand:SI 0 "register_operand" "=D")
15485 (plus:SI (match_operand:SI 3 "register_operand" "0")
15486 (match_operand:SI 4 "register_operand" "1")))
15487 (set (mem:BLK (match_dup 3))
15489 (use (match_operand:QI 2 "register_operand" "a"))
15490 (use (match_dup 4))
15493 "{rep\;stosb|rep stosb}"
15494 [(set_attr "type" "str")
15495 (set_attr "prefix_rep" "1")
15496 (set_attr "memory" "store")
15497 (set_attr "mode" "QI")])
15499 (define_insn "rep_stosqi_rex64"
15500 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15501 (set (match_operand:DI 0 "register_operand" "=D")
15502 (plus:DI (match_operand:DI 3 "register_operand" "0")
15503 (match_operand:DI 4 "register_operand" "1")))
15504 (set (mem:BLK (match_dup 3))
15506 (use (match_operand:QI 2 "register_operand" "a"))
15507 (use (match_dup 4))
15510 "{rep\;stosb|rep stosb}"
15511 [(set_attr "type" "str")
15512 (set_attr "prefix_rep" "1")
15513 (set_attr "memory" "store")
15514 (set_attr "mode" "QI")])
15516 (define_expand "cmpstrsi"
15517 [(set (match_operand:SI 0 "register_operand" "")
15518 (compare:SI (match_operand:BLK 1 "general_operand" "")
15519 (match_operand:BLK 2 "general_operand" "")))
15520 (use (match_operand 3 "general_operand" ""))
15521 (use (match_operand 4 "immediate_operand" ""))]
15524 rtx addr1, addr2, out, outlow, count, countreg, align;
15527 if (GET_CODE (out) != REG)
15528 out = gen_reg_rtx (SImode);
15530 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15531 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15533 count = operands[3];
15534 countreg = ix86_zero_extend_to_Pmode (count);
15536 /* %%% Iff we are testing strict equality, we can use known alignment
15537 to good advantage. This may be possible with combine, particularly
15538 once cc0 is dead. */
15539 align = operands[4];
15541 emit_insn (gen_cld ());
15542 if (GET_CODE (count) == CONST_INT)
15544 if (INTVAL (count) == 0)
15546 emit_move_insn (operands[0], const0_rtx);
15550 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
15551 addr1, addr2, countreg));
15553 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15554 addr1, addr2, countreg));
15560 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15561 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
15562 addr1, addr2, countreg));
15566 emit_insn (gen_cmpsi_1 (countreg, countreg));
15567 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15568 addr1, addr2, countreg));
15572 outlow = gen_lowpart (QImode, out);
15573 emit_insn (gen_cmpintqi (outlow));
15574 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15576 if (operands[0] != out)
15577 emit_move_insn (operands[0], out);
15582 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15584 (define_expand "cmpintqi"
15585 [(set (match_dup 1)
15586 (gtu:QI (reg:CC 17) (const_int 0)))
15588 (ltu:QI (reg:CC 17) (const_int 0)))
15589 (parallel [(set (match_operand:QI 0 "register_operand" "")
15590 (minus:QI (match_dup 1)
15592 (clobber (reg:CC 17))])]
15594 "operands[1] = gen_reg_rtx (QImode);
15595 operands[2] = gen_reg_rtx (QImode);")
15597 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15598 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15600 (define_insn "cmpstrqi_nz_1"
15602 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15603 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15604 (use (match_operand:SI 6 "register_operand" "2"))
15605 (use (match_operand:SI 3 "immediate_operand" "i"))
15607 (clobber (match_operand:SI 0 "register_operand" "=S"))
15608 (clobber (match_operand:SI 1 "register_operand" "=D"))
15609 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15612 [(set_attr "type" "str")
15613 (set_attr "mode" "QI")
15614 (set_attr "prefix_rep" "1")])
15616 (define_insn "cmpstrqi_nz_rex_1"
15618 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15619 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15620 (use (match_operand:DI 6 "register_operand" "2"))
15621 (use (match_operand:SI 3 "immediate_operand" "i"))
15623 (clobber (match_operand:DI 0 "register_operand" "=S"))
15624 (clobber (match_operand:DI 1 "register_operand" "=D"))
15625 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15628 [(set_attr "type" "str")
15629 (set_attr "mode" "QI")
15630 (set_attr "prefix_rep" "1")])
15632 ;; The same, but the count is not known to not be zero.
15634 (define_insn "cmpstrqi_1"
15636 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
15638 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15639 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
15641 (use (match_operand:SI 3 "immediate_operand" "i"))
15644 (clobber (match_operand:SI 0 "register_operand" "=S"))
15645 (clobber (match_operand:SI 1 "register_operand" "=D"))
15646 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15649 [(set_attr "type" "str")
15650 (set_attr "mode" "QI")
15651 (set_attr "prefix_rep" "1")])
15653 (define_insn "cmpstrqi_rex_1"
15655 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
15657 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15658 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
15660 (use (match_operand:SI 3 "immediate_operand" "i"))
15663 (clobber (match_operand:DI 0 "register_operand" "=S"))
15664 (clobber (match_operand:DI 1 "register_operand" "=D"))
15665 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15668 [(set_attr "type" "str")
15669 (set_attr "mode" "QI")
15670 (set_attr "prefix_rep" "1")])
15672 (define_expand "strlensi"
15673 [(set (match_operand:SI 0 "register_operand" "")
15674 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
15675 (match_operand:QI 2 "immediate_operand" "")
15676 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
15679 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15685 (define_expand "strlendi"
15686 [(set (match_operand:DI 0 "register_operand" "")
15687 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
15688 (match_operand:QI 2 "immediate_operand" "")
15689 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
15692 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
15698 (define_insn "strlenqi_1"
15699 [(set (match_operand:SI 0 "register_operand" "=&c")
15700 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
15701 (match_operand:QI 2 "register_operand" "a")
15702 (match_operand:SI 3 "immediate_operand" "i")
15703 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
15705 (clobber (match_operand:SI 1 "register_operand" "=D"))
15706 (clobber (reg:CC 17))]
15709 [(set_attr "type" "str")
15710 (set_attr "mode" "QI")
15711 (set_attr "prefix_rep" "1")])
15713 (define_insn "strlenqi_rex_1"
15714 [(set (match_operand:DI 0 "register_operand" "=&c")
15715 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
15716 (match_operand:QI 2 "register_operand" "a")
15717 (match_operand:DI 3 "immediate_operand" "i")
15718 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
15720 (clobber (match_operand:DI 1 "register_operand" "=D"))
15721 (clobber (reg:CC 17))]
15724 [(set_attr "type" "str")
15725 (set_attr "mode" "QI")
15726 (set_attr "prefix_rep" "1")])
15728 ;; Peephole optimizations to clean up after cmpstr*. This should be
15729 ;; handled in combine, but it is not currently up to the task.
15730 ;; When used for their truth value, the cmpstr* expanders generate
15739 ;; The intermediate three instructions are unnecessary.
15741 ;; This one handles cmpstr*_nz_1...
15745 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15746 (mem:BLK (match_operand 5 "register_operand" ""))))
15747 (use (match_operand 6 "register_operand" ""))
15748 (use (match_operand:SI 3 "immediate_operand" ""))
15750 (clobber (match_operand 0 "register_operand" ""))
15751 (clobber (match_operand 1 "register_operand" ""))
15752 (clobber (match_operand 2 "register_operand" ""))])
15753 (set (match_operand:QI 7 "register_operand" "")
15754 (gtu:QI (reg:CC 17) (const_int 0)))
15755 (set (match_operand:QI 8 "register_operand" "")
15756 (ltu:QI (reg:CC 17) (const_int 0)))
15758 (compare (match_dup 7) (match_dup 8)))
15760 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15763 (compare:CC (mem:BLK (match_dup 4))
15764 (mem:BLK (match_dup 5))))
15765 (use (match_dup 6))
15766 (use (match_dup 3))
15768 (clobber (match_dup 0))
15769 (clobber (match_dup 1))
15770 (clobber (match_dup 2))])]
15773 ;; ...and this one handles cmpstr*_1.
15777 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
15779 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
15780 (mem:BLK (match_operand 5 "register_operand" "")))
15782 (use (match_operand:SI 3 "immediate_operand" ""))
15785 (clobber (match_operand 0 "register_operand" ""))
15786 (clobber (match_operand 1 "register_operand" ""))
15787 (clobber (match_operand 2 "register_operand" ""))])
15788 (set (match_operand:QI 7 "register_operand" "")
15789 (gtu:QI (reg:CC 17) (const_int 0)))
15790 (set (match_operand:QI 8 "register_operand" "")
15791 (ltu:QI (reg:CC 17) (const_int 0)))
15793 (compare (match_dup 7) (match_dup 8)))
15795 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
15798 (if_then_else:CC (ne (match_dup 6)
15800 (compare:CC (mem:BLK (match_dup 4))
15801 (mem:BLK (match_dup 5)))
15803 (use (match_dup 3))
15806 (clobber (match_dup 0))
15807 (clobber (match_dup 1))
15808 (clobber (match_dup 2))])]
15813 ;; Conditional move instructions.
15815 (define_expand "movdicc"
15816 [(set (match_operand:DI 0 "register_operand" "")
15817 (if_then_else:DI (match_operand 1 "comparison_operator" "")
15818 (match_operand:DI 2 "general_operand" "")
15819 (match_operand:DI 3 "general_operand" "")))]
15821 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15823 (define_insn "x86_movdicc_0_m1_rex64"
15824 [(set (match_operand:DI 0 "register_operand" "=r")
15825 (if_then_else:DI (ltu (reg:CC 17) (const_int 0))
15828 (clobber (reg:CC 17))]
15831 ; Since we don't have the proper number of operands for an alu insn,
15832 ; fill in all the blanks.
15833 [(set_attr "type" "alu")
15834 (set_attr "pent_pair" "pu")
15835 (set_attr "memory" "none")
15836 (set_attr "imm_disp" "false")
15837 (set_attr "mode" "DI")
15838 (set_attr "length_immediate" "0")])
15840 (define_insn "*movdicc_c_rex64"
15841 [(set (match_operand:DI 0 "register_operand" "=r,r")
15842 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
15843 [(reg 17) (const_int 0)])
15844 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
15845 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
15846 "TARGET_64BIT && TARGET_CMOVE
15847 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15849 cmov%O2%C1\t{%2, %0|%0, %2}
15850 cmov%O2%c1\t{%3, %0|%0, %3}"
15851 [(set_attr "type" "icmov")
15852 (set_attr "mode" "DI")])
15854 (define_expand "movsicc"
15855 [(set (match_operand:SI 0 "register_operand" "")
15856 (if_then_else:SI (match_operand 1 "comparison_operator" "")
15857 (match_operand:SI 2 "general_operand" "")
15858 (match_operand:SI 3 "general_operand" "")))]
15860 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15862 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
15863 ;; the register first winds up with `sbbl $0,reg', which is also weird.
15864 ;; So just document what we're doing explicitly.
15866 (define_insn "x86_movsicc_0_m1"
15867 [(set (match_operand:SI 0 "register_operand" "=r")
15868 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
15871 (clobber (reg:CC 17))]
15874 ; Since we don't have the proper number of operands for an alu insn,
15875 ; fill in all the blanks.
15876 [(set_attr "type" "alu")
15877 (set_attr "pent_pair" "pu")
15878 (set_attr "memory" "none")
15879 (set_attr "imm_disp" "false")
15880 (set_attr "mode" "SI")
15881 (set_attr "length_immediate" "0")])
15883 (define_insn "*movsicc_noc"
15884 [(set (match_operand:SI 0 "register_operand" "=r,r")
15885 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
15886 [(reg 17) (const_int 0)])
15887 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
15888 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
15890 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15892 cmov%O2%C1\t{%2, %0|%0, %2}
15893 cmov%O2%c1\t{%3, %0|%0, %3}"
15894 [(set_attr "type" "icmov")
15895 (set_attr "mode" "SI")])
15897 (define_expand "movhicc"
15898 [(set (match_operand:HI 0 "register_operand" "")
15899 (if_then_else:HI (match_operand 1 "comparison_operator" "")
15900 (match_operand:HI 2 "nonimmediate_operand" "")
15901 (match_operand:HI 3 "nonimmediate_operand" "")))]
15902 "TARGET_CMOVE && TARGET_HIMODE_MATH"
15903 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
15905 (define_insn "*movhicc_noc"
15906 [(set (match_operand:HI 0 "register_operand" "=r,r")
15907 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
15908 [(reg 17) (const_int 0)])
15909 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
15910 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
15912 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15914 cmov%O2%C1\t{%2, %0|%0, %2}
15915 cmov%O2%c1\t{%3, %0|%0, %3}"
15916 [(set_attr "type" "icmov")
15917 (set_attr "mode" "HI")])
15919 (define_expand "movsfcc"
15920 [(set (match_operand:SF 0 "register_operand" "")
15921 (if_then_else:SF (match_operand 1 "comparison_operator" "")
15922 (match_operand:SF 2 "register_operand" "")
15923 (match_operand:SF 3 "register_operand" "")))]
15925 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15927 (define_insn "*movsfcc_1"
15928 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
15929 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
15930 [(reg 17) (const_int 0)])
15931 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
15932 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
15934 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15936 fcmov%F1\t{%2, %0|%0, %2}
15937 fcmov%f1\t{%3, %0|%0, %3}
15938 cmov%O2%C1\t{%2, %0|%0, %2}
15939 cmov%O2%c1\t{%3, %0|%0, %3}"
15940 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15941 (set_attr "mode" "SF,SF,SI,SI")])
15943 (define_expand "movdfcc"
15944 [(set (match_operand:DF 0 "register_operand" "")
15945 (if_then_else:DF (match_operand 1 "comparison_operator" "")
15946 (match_operand:DF 2 "register_operand" "")
15947 (match_operand:DF 3 "register_operand" "")))]
15949 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
15951 (define_insn "*movdfcc_1"
15952 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15953 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15954 [(reg 17) (const_int 0)])
15955 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15956 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15957 "!TARGET_64BIT && TARGET_CMOVE
15958 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15960 fcmov%F1\t{%2, %0|%0, %2}
15961 fcmov%f1\t{%3, %0|%0, %3}
15964 [(set_attr "type" "fcmov,fcmov,multi,multi")
15965 (set_attr "mode" "DF")])
15967 (define_insn "*movdfcc_1_rex64"
15968 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
15969 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15970 [(reg 17) (const_int 0)])
15971 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
15972 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
15973 "TARGET_64BIT && TARGET_CMOVE
15974 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
15976 fcmov%F1\t{%2, %0|%0, %2}
15977 fcmov%f1\t{%3, %0|%0, %3}
15978 cmov%O2%C1\t{%2, %0|%0, %2}
15979 cmov%O2%c1\t{%3, %0|%0, %3}"
15980 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
15981 (set_attr "mode" "DF")])
15984 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
15985 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
15986 [(match_operand 4 "" "") (const_int 0)])
15987 (match_operand:DF 2 "nonimmediate_operand" "")
15988 (match_operand:DF 3 "nonimmediate_operand" "")))]
15989 "!TARGET_64BIT && reload_completed"
15990 [(set (match_dup 2)
15991 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15995 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
15998 "split_di (operands+2, 1, operands+5, operands+6);
15999 split_di (operands+3, 1, operands+7, operands+8);
16000 split_di (operands, 1, operands+2, operands+3);")
16002 (define_expand "movxfcc"
16003 [(set (match_operand:XF 0 "register_operand" "")
16004 (if_then_else:XF (match_operand 1 "comparison_operator" "")
16005 (match_operand:XF 2 "register_operand" "")
16006 (match_operand:XF 3 "register_operand" "")))]
16007 "!TARGET_64BIT && TARGET_CMOVE"
16008 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16010 (define_expand "movtfcc"
16011 [(set (match_operand:TF 0 "register_operand" "")
16012 (if_then_else:TF (match_operand 1 "comparison_operator" "")
16013 (match_operand:TF 2 "register_operand" "")
16014 (match_operand:TF 3 "register_operand" "")))]
16016 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16018 (define_insn "*movxfcc_1"
16019 [(set (match_operand:XF 0 "register_operand" "=f,f")
16020 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16021 [(reg 17) (const_int 0)])
16022 (match_operand:XF 2 "register_operand" "f,0")
16023 (match_operand:XF 3 "register_operand" "0,f")))]
16024 "!TARGET_64BIT && TARGET_CMOVE"
16026 fcmov%F1\t{%2, %0|%0, %2}
16027 fcmov%f1\t{%3, %0|%0, %3}"
16028 [(set_attr "type" "fcmov")
16029 (set_attr "mode" "XF")])
16031 (define_insn "*movtfcc_1"
16032 [(set (match_operand:TF 0 "register_operand" "=f,f")
16033 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
16034 [(reg 17) (const_int 0)])
16035 (match_operand:TF 2 "register_operand" "f,0")
16036 (match_operand:TF 3 "register_operand" "0,f")))]
16039 fcmov%F1\t{%2, %0|%0, %2}
16040 fcmov%f1\t{%3, %0|%0, %3}"
16041 [(set_attr "type" "fcmov")
16042 (set_attr "mode" "XF")])
16044 (define_expand "minsf3"
16046 (set (match_operand:SF 0 "register_operand" "")
16047 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16048 (match_operand:SF 2 "nonimmediate_operand" ""))
16051 (clobber (reg:CC 17))])]
16055 (define_insn "*minsf"
16056 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16057 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
16058 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16061 (clobber (reg:CC 17))]
16062 "TARGET_SSE && TARGET_IEEE_FP"
16065 (define_insn "*minsf_nonieee"
16066 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16067 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16068 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16071 (clobber (reg:CC 17))]
16072 "TARGET_SSE && !TARGET_IEEE_FP
16073 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16077 [(set (match_operand:SF 0 "register_operand" "")
16078 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16079 (match_operand:SF 2 "nonimmediate_operand" ""))
16080 (match_operand:SF 3 "register_operand" "")
16081 (match_operand:SF 4 "nonimmediate_operand" "")))
16082 (clobber (reg:CC 17))]
16083 "SSE_REG_P (operands[0]) && reload_completed
16084 && ((operands_match_p (operands[1], operands[3])
16085 && operands_match_p (operands[2], operands[4]))
16086 || (operands_match_p (operands[1], operands[4])
16087 && operands_match_p (operands[2], operands[3])))"
16088 [(set (match_dup 0)
16089 (if_then_else:SF (lt (match_dup 1)
16094 ;; We can't represent the LT test directly. Do this by swapping the operands.
16097 [(set (match_operand:SF 0 "fp_register_operand" "")
16098 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16099 (match_operand:SF 2 "register_operand" ""))
16100 (match_operand:SF 3 "register_operand" "")
16101 (match_operand:SF 4 "register_operand" "")))
16102 (clobber (reg:CC 17))]
16104 && ((operands_match_p (operands[1], operands[3])
16105 && operands_match_p (operands[2], operands[4]))
16106 || (operands_match_p (operands[1], operands[4])
16107 && operands_match_p (operands[2], operands[3])))"
16108 [(set (reg:CCFP 17)
16109 (compare:CCFP (match_dup 2)
16112 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
16116 (define_insn "*minsf_sse"
16117 [(set (match_operand:SF 0 "register_operand" "=x")
16118 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
16119 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16122 "TARGET_SSE && reload_completed"
16123 "minss\t{%2, %0|%0, %2}"
16124 [(set_attr "type" "sse")
16125 (set_attr "mode" "SF")])
16127 (define_expand "mindf3"
16129 (set (match_operand:DF 0 "register_operand" "")
16130 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16131 (match_operand:DF 2 "nonimmediate_operand" ""))
16134 (clobber (reg:CC 17))])]
16135 "TARGET_SSE2 && TARGET_SSE_MATH"
16138 (define_insn "*mindf"
16139 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16140 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16141 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16144 (clobber (reg:CC 17))]
16145 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16148 (define_insn "*mindf_nonieee"
16149 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16150 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16151 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16154 (clobber (reg:CC 17))]
16155 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16156 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16160 [(set (match_operand:DF 0 "register_operand" "")
16161 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16162 (match_operand:DF 2 "nonimmediate_operand" ""))
16163 (match_operand:DF 3 "register_operand" "")
16164 (match_operand:DF 4 "nonimmediate_operand" "")))
16165 (clobber (reg:CC 17))]
16166 "SSE_REG_P (operands[0]) && reload_completed
16167 && ((operands_match_p (operands[1], operands[3])
16168 && operands_match_p (operands[2], operands[4]))
16169 || (operands_match_p (operands[1], operands[4])
16170 && operands_match_p (operands[2], operands[3])))"
16171 [(set (match_dup 0)
16172 (if_then_else:DF (lt (match_dup 1)
16177 ;; We can't represent the LT test directly. Do this by swapping the operands.
16179 [(set (match_operand:DF 0 "fp_register_operand" "")
16180 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16181 (match_operand:DF 2 "register_operand" ""))
16182 (match_operand:DF 3 "register_operand" "")
16183 (match_operand:DF 4 "register_operand" "")))
16184 (clobber (reg:CC 17))]
16186 && ((operands_match_p (operands[1], operands[3])
16187 && operands_match_p (operands[2], operands[4]))
16188 || (operands_match_p (operands[1], operands[4])
16189 && operands_match_p (operands[2], operands[3])))"
16190 [(set (reg:CCFP 17)
16191 (compare:CCFP (match_dup 2)
16194 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
16198 (define_insn "*mindf_sse"
16199 [(set (match_operand:DF 0 "register_operand" "=Y")
16200 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
16201 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16204 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16205 "minsd\t{%2, %0|%0, %2}"
16206 [(set_attr "type" "sse")
16207 (set_attr "mode" "DF")])
16209 (define_expand "maxsf3"
16211 (set (match_operand:SF 0 "register_operand" "")
16212 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16213 (match_operand:SF 2 "nonimmediate_operand" ""))
16216 (clobber (reg:CC 17))])]
16220 (define_insn "*maxsf"
16221 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16222 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
16223 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16226 (clobber (reg:CC 17))]
16227 "TARGET_SSE && TARGET_IEEE_FP"
16230 (define_insn "*maxsf_nonieee"
16231 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16232 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16233 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16236 (clobber (reg:CC 17))]
16237 "TARGET_SSE && !TARGET_IEEE_FP
16238 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16242 [(set (match_operand:SF 0 "register_operand" "")
16243 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16244 (match_operand:SF 2 "nonimmediate_operand" ""))
16245 (match_operand:SF 3 "register_operand" "")
16246 (match_operand:SF 4 "nonimmediate_operand" "")))
16247 (clobber (reg:CC 17))]
16248 "SSE_REG_P (operands[0]) && reload_completed
16249 && ((operands_match_p (operands[1], operands[3])
16250 && operands_match_p (operands[2], operands[4]))
16251 || (operands_match_p (operands[1], operands[4])
16252 && operands_match_p (operands[2], operands[3])))"
16253 [(set (match_dup 0)
16254 (if_then_else:SF (gt (match_dup 1)
16260 [(set (match_operand:SF 0 "fp_register_operand" "")
16261 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16262 (match_operand:SF 2 "register_operand" ""))
16263 (match_operand:SF 3 "register_operand" "")
16264 (match_operand:SF 4 "register_operand" "")))
16265 (clobber (reg:CC 17))]
16267 && ((operands_match_p (operands[1], operands[3])
16268 && operands_match_p (operands[2], operands[4]))
16269 || (operands_match_p (operands[1], operands[4])
16270 && operands_match_p (operands[2], operands[3])))"
16271 [(set (reg:CCFP 17)
16272 (compare:CCFP (match_dup 1)
16275 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
16279 (define_insn "*maxsf_sse"
16280 [(set (match_operand:SF 0 "register_operand" "=x")
16281 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
16282 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16285 "TARGET_SSE && reload_completed"
16286 "maxss\t{%2, %0|%0, %2}"
16287 [(set_attr "type" "sse")
16288 (set_attr "mode" "SF")])
16290 (define_expand "maxdf3"
16292 (set (match_operand:DF 0 "register_operand" "")
16293 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16294 (match_operand:DF 2 "nonimmediate_operand" ""))
16297 (clobber (reg:CC 17))])]
16298 "TARGET_SSE2 && TARGET_SSE_MATH"
16301 (define_insn "*maxdf"
16302 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16303 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16304 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16307 (clobber (reg:CC 17))]
16308 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16311 (define_insn "*maxdf_nonieee"
16312 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16313 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16314 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16317 (clobber (reg:CC 17))]
16318 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16319 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16323 [(set (match_operand:DF 0 "register_operand" "")
16324 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16325 (match_operand:DF 2 "nonimmediate_operand" ""))
16326 (match_operand:DF 3 "register_operand" "")
16327 (match_operand:DF 4 "nonimmediate_operand" "")))
16328 (clobber (reg:CC 17))]
16329 "SSE_REG_P (operands[0]) && reload_completed
16330 && ((operands_match_p (operands[1], operands[3])
16331 && operands_match_p (operands[2], operands[4]))
16332 || (operands_match_p (operands[1], operands[4])
16333 && operands_match_p (operands[2], operands[3])))"
16334 [(set (match_dup 0)
16335 (if_then_else:DF (gt (match_dup 1)
16341 [(set (match_operand:DF 0 "fp_register_operand" "")
16342 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16343 (match_operand:DF 2 "register_operand" ""))
16344 (match_operand:DF 3 "register_operand" "")
16345 (match_operand:DF 4 "register_operand" "")))
16346 (clobber (reg:CC 17))]
16348 && ((operands_match_p (operands[1], operands[3])
16349 && operands_match_p (operands[2], operands[4]))
16350 || (operands_match_p (operands[1], operands[4])
16351 && operands_match_p (operands[2], operands[3])))"
16352 [(set (reg:CCFP 17)
16353 (compare:CCFP (match_dup 1)
16356 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16360 (define_insn "*maxdf_sse"
16361 [(set (match_operand:DF 0 "register_operand" "=Y")
16362 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16363 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16366 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16367 "maxsd\t{%2, %0|%0, %2}"
16368 [(set_attr "type" "sse")
16369 (set_attr "mode" "DF")])
16371 ;; Misc patterns (?)
16373 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
16374 ;; Otherwise there will be nothing to keep
16376 ;; [(set (reg ebp) (reg esp))]
16377 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16378 ;; (clobber (eflags)]
16379 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16381 ;; in proper program order.
16382 (define_expand "pro_epilogue_adjust_stack"
16383 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
16384 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16385 (match_operand:SI 2 "immediate_operand" "i,i")))
16386 (clobber (reg:CC 17))
16387 (clobber (mem:BLK (scratch)))])]
16392 emit_insn (gen_pro_epilogue_adjust_stack_rex64
16393 (operands[0], operands[1], operands[2]));
16398 (define_insn "*pro_epilogue_adjust_stack_1"
16399 [(set (match_operand:SI 0 "register_operand" "=r,r")
16400 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16401 (match_operand:SI 2 "immediate_operand" "i,i")))
16402 (clobber (reg:CC 17))
16403 (clobber (mem:BLK (scratch)))]
16406 switch (get_attr_type (insn))
16409 return "mov{l}\t{%1, %0|%0, %1}";
16412 if (GET_CODE (operands[2]) == CONST_INT
16413 && (INTVAL (operands[2]) == 128
16414 || (INTVAL (operands[2]) < 0
16415 && INTVAL (operands[2]) != -128)))
16417 operands[2] = GEN_INT (-INTVAL (operands[2]));
16418 return "sub{l}\t{%2, %0|%0, %2}";
16420 return "add{l}\t{%2, %0|%0, %2}";
16423 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16424 return "lea{l}\t{%a2, %0|%0, %a2}";
16430 [(set (attr "type")
16431 (cond [(eq_attr "alternative" "0")
16432 (const_string "alu")
16433 (match_operand:SI 2 "const0_operand" "")
16434 (const_string "imov")
16436 (const_string "lea")))
16437 (set_attr "mode" "SI")])
16439 (define_insn "pro_epilogue_adjust_stack_rex64"
16440 [(set (match_operand:DI 0 "register_operand" "=r,r")
16441 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16442 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16443 (clobber (reg:CC 17))
16444 (clobber (mem:BLK (scratch)))]
16447 switch (get_attr_type (insn))
16450 return "mov{q}\t{%1, %0|%0, %1}";
16453 if (GET_CODE (operands[2]) == CONST_INT
16454 && (INTVAL (operands[2]) == 128
16455 || (INTVAL (operands[2]) < 0
16456 && INTVAL (operands[2]) != -128)))
16458 operands[2] = GEN_INT (-INTVAL (operands[2]));
16459 return "sub{q}\t{%2, %0|%0, %2}";
16461 return "add{q}\t{%2, %0|%0, %2}";
16464 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16465 return "lea{q}\t{%a2, %0|%0, %a2}";
16471 [(set (attr "type")
16472 (cond [(eq_attr "alternative" "0")
16473 (const_string "alu")
16474 (match_operand:DI 2 "const0_operand" "")
16475 (const_string "imov")
16477 (const_string "lea")))
16478 (set_attr "mode" "DI")])
16481 ;; Placeholder for the conditional moves. This one is split either to SSE
16482 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16483 ;; fact is that compares supported by the cmp??ss instructions are exactly
16484 ;; swapped of those supported by cmove sequence.
16485 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16486 ;; supported by i387 comparisons and we do need to emit two conditional moves
16489 (define_insn "sse_movsfcc"
16490 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16491 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16492 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16493 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16494 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16495 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16496 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16497 (clobber (reg:CC 17))]
16499 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16500 && (!TARGET_IEEE_FP
16501 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16504 (define_insn "sse_movsfcc_eq"
16505 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16506 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16507 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16508 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16509 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16510 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16511 (clobber (reg:CC 17))]
16513 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16516 (define_insn "sse_movdfcc"
16517 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
16518 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16519 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
16520 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
16521 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
16522 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
16523 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16524 (clobber (reg:CC 17))]
16526 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16527 && (!TARGET_IEEE_FP
16528 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16531 (define_insn "sse_movdfcc_eq"
16532 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
16533 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
16534 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
16535 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
16536 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
16537 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16538 (clobber (reg:CC 17))]
16540 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16543 ;; For non-sse moves just expand the usual cmove sequence.
16545 [(set (match_operand 0 "register_operand" "")
16546 (if_then_else (match_operator 1 "comparison_operator"
16547 [(match_operand 4 "nonimmediate_operand" "")
16548 (match_operand 5 "register_operand" "")])
16549 (match_operand 2 "nonimmediate_operand" "")
16550 (match_operand 3 "nonimmediate_operand" "")))
16551 (clobber (match_operand 6 "" ""))
16552 (clobber (reg:CC 17))]
16553 "!SSE_REG_P (operands[0]) && reload_completed
16554 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
16557 ix86_compare_op0 = operands[5];
16558 ix86_compare_op1 = operands[4];
16559 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
16560 VOIDmode, operands[5], operands[4]);
16561 ix86_expand_fp_movcc (operands);
16565 ;; Split SSE based conditional move into seqence:
16566 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
16567 ;; and op2, op0 - zero op2 if comparison was false
16568 ;; nand op0, op3 - load op3 to op0 if comparison was false
16569 ;; or op2, op0 - get the nonzero one into the result.
16571 [(set (match_operand 0 "register_operand" "")
16572 (if_then_else (match_operator 1 "sse_comparison_operator"
16573 [(match_operand 4 "register_operand" "")
16574 (match_operand 5 "nonimmediate_operand" "")])
16575 (match_operand 2 "register_operand" "")
16576 (match_operand 3 "register_operand" "")))
16577 (clobber (match_operand 6 "" ""))
16578 (clobber (reg:CC 17))]
16579 "SSE_REG_P (operands[0]) && reload_completed"
16580 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
16581 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
16582 (subreg:TI (match_dup 4) 0)))
16583 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
16584 (subreg:TI (match_dup 3) 0)))
16585 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
16586 (subreg:TI (match_dup 7) 0)))]
16588 /* If op2 == op3, op3 will be clobbered before it is used.
16589 This should be optimized out though. */
16590 if (operands_match_p (operands[2], operands[3]))
16592 PUT_MODE (operands[1], GET_MODE (operands[0]));
16593 if (operands_match_p (operands[0], operands[4]))
16594 operands[6] = operands[4], operands[7] = operands[2];
16596 operands[6] = operands[2], operands[7] = operands[4];
16599 ;; Special case of conditional move we can handle effectivly.
16600 ;; Do not brother with the integer/floating point case, since these are
16601 ;; bot considerably slower, unlike in the generic case.
16602 (define_insn "*sse_movsfcc_const0_1"
16603 [(set (match_operand:SF 0 "register_operand" "=&x")
16604 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16605 [(match_operand:SF 4 "register_operand" "0")
16606 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16607 (match_operand:SF 2 "register_operand" "x")
16608 (match_operand:SF 3 "const0_operand" "X")))]
16612 (define_insn "*sse_movsfcc_const0_2"
16613 [(set (match_operand:SF 0 "register_operand" "=&x")
16614 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16615 [(match_operand:SF 4 "register_operand" "0")
16616 (match_operand:SF 5 "nonimmediate_operand" "xm")])
16617 (match_operand:SF 2 "const0_operand" "X")
16618 (match_operand:SF 3 "register_operand" "x")))]
16622 (define_insn "*sse_movsfcc_const0_3"
16623 [(set (match_operand:SF 0 "register_operand" "=&x")
16624 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16625 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16626 (match_operand:SF 5 "register_operand" "0")])
16627 (match_operand:SF 2 "register_operand" "x")
16628 (match_operand:SF 3 "const0_operand" "X")))]
16632 (define_insn "*sse_movsfcc_const0_4"
16633 [(set (match_operand:SF 0 "register_operand" "=&x")
16634 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16635 [(match_operand:SF 4 "nonimmediate_operand" "xm")
16636 (match_operand:SF 5 "register_operand" "0")])
16637 (match_operand:SF 2 "const0_operand" "X")
16638 (match_operand:SF 3 "register_operand" "x")))]
16642 (define_insn "*sse_movdfcc_const0_1"
16643 [(set (match_operand:DF 0 "register_operand" "=&Y")
16644 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16645 [(match_operand:DF 4 "register_operand" "0")
16646 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
16647 (match_operand:DF 2 "register_operand" "Y")
16648 (match_operand:DF 3 "const0_operand" "X")))]
16652 (define_insn "*sse_movdfcc_const0_2"
16653 [(set (match_operand:DF 0 "register_operand" "=&Y")
16654 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16655 [(match_operand:DF 4 "register_operand" "0")
16656 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
16657 (match_operand:DF 2 "const0_operand" "X")
16658 (match_operand:DF 3 "register_operand" "Y")))]
16662 (define_insn "*sse_movdfcc_const0_3"
16663 [(set (match_operand:DF 0 "register_operand" "=&Y")
16664 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16665 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
16666 (match_operand:DF 5 "register_operand" "0")])
16667 (match_operand:DF 2 "register_operand" "Y")
16668 (match_operand:DF 3 "const0_operand" "X")))]
16672 (define_insn "*sse_movdfcc_const0_4"
16673 [(set (match_operand:DF 0 "register_operand" "=&Y")
16674 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16675 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
16676 (match_operand:DF 5 "register_operand" "0")])
16677 (match_operand:DF 2 "const0_operand" "X")
16678 (match_operand:DF 3 "register_operand" "Y")))]
16683 [(set (match_operand 0 "register_operand" "")
16684 (if_then_else (match_operator 1 "comparison_operator"
16685 [(match_operand 4 "register_operand" "")
16686 (match_operand 5 "nonimmediate_operand" "")])
16687 (match_operand 2 "nonmemory_operand" "")
16688 (match_operand 3 "nonmemory_operand" "")))]
16689 "SSE_REG_P (operands[0]) && reload_completed
16690 && (const0_operand (operands[2], GET_MODE (operands[0]))
16691 || const0_operand (operands[3], GET_MODE (operands[0])))"
16692 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
16693 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
16694 (subreg:TI (match_dup 7) 0)))]
16696 PUT_MODE (operands[1], GET_MODE (operands[0]));
16697 if (!sse_comparison_operator (operands[1], VOIDmode))
16699 rtx tmp = operands[5];
16700 operands[5] = operands[4];
16702 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
16704 if (const0_operand (operands[2], GET_MODE (operands[0])))
16706 operands[7] = operands[3];
16707 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
16712 operands[7] = operands[2];
16713 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
16717 (define_expand "allocate_stack_worker"
16718 [(match_operand:SI 0 "register_operand" "")]
16719 "TARGET_STACK_PROBE"
16722 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
16724 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
16728 (define_insn "allocate_stack_worker_1"
16729 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
16730 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
16731 (clobber (match_dup 0))
16732 (clobber (reg:CC 17))]
16733 "!TARGET_64BIT && TARGET_STACK_PROBE"
16735 [(set_attr "type" "multi")
16736 (set_attr "length" "5")])
16738 (define_insn "allocate_stack_worker_rex64"
16739 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
16740 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
16741 (clobber (match_dup 0))
16742 (clobber (reg:CC 17))]
16743 "TARGET_64BIT && TARGET_STACK_PROBE"
16745 [(set_attr "type" "multi")
16746 (set_attr "length" "5")])
16748 (define_expand "allocate_stack"
16749 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
16750 (minus:SI (reg:SI 7)
16751 (match_operand:SI 1 "general_operand" "")))
16752 (clobber (reg:CC 17))])
16753 (parallel [(set (reg:SI 7)
16754 (minus:SI (reg:SI 7) (match_dup 1)))
16755 (clobber (reg:CC 17))])]
16756 "TARGET_STACK_PROBE"
16758 #ifdef CHECK_STACK_LIMIT
16759 if (GET_CODE (operands[1]) == CONST_INT
16760 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
16761 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
16765 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
16768 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
16772 (define_expand "builtin_setjmp_receiver"
16773 [(label_ref (match_operand 0 "" ""))]
16774 "!TARGET_64BIT && flag_pic"
16776 emit_insn (gen_set_got (pic_offset_table_rtx));
16780 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
16783 [(set (match_operand 0 "register_operand" "")
16784 (match_operator 3 "promotable_binary_operator"
16785 [(match_operand 1 "register_operand" "")
16786 (match_operand 2 "aligned_operand" "")]))
16787 (clobber (reg:CC 17))]
16788 "! TARGET_PARTIAL_REG_STALL && reload_completed
16789 && ((GET_MODE (operands[0]) == HImode
16790 && ((!optimize_size && !TARGET_FAST_PREFIX)
16791 || GET_CODE (operands[2]) != CONST_INT
16792 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
16793 || (GET_MODE (operands[0]) == QImode
16794 && (TARGET_PROMOTE_QImode || optimize_size)))"
16795 [(parallel [(set (match_dup 0)
16796 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
16797 (clobber (reg:CC 17))])]
16798 "operands[0] = gen_lowpart (SImode, operands[0]);
16799 operands[1] = gen_lowpart (SImode, operands[1]);
16800 if (GET_CODE (operands[3]) != ASHIFT)
16801 operands[2] = gen_lowpart (SImode, operands[2]);
16802 PUT_MODE (operands[3], SImode);")
16806 (compare (and (match_operand 1 "aligned_operand" "")
16807 (match_operand 2 "const_int_operand" ""))
16809 (set (match_operand 0 "register_operand" "")
16810 (and (match_dup 1) (match_dup 2)))]
16811 "! TARGET_PARTIAL_REG_STALL && reload_completed
16812 && ix86_match_ccmode (insn, CCNOmode)
16813 && (GET_MODE (operands[0]) == HImode
16814 || (GET_MODE (operands[0]) == QImode
16815 /* Ensure that the operand will remain sign extended immedaite. */
16816 && INTVAL (operands[2]) >= 0
16817 && (TARGET_PROMOTE_QImode || optimize_size)))"
16818 [(parallel [(set (reg:CCNO 17)
16819 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
16822 (and:SI (match_dup 1) (match_dup 2)))])]
16824 = gen_int_mode (INTVAL (operands[2])
16825 & GET_MODE_MASK (GET_MODE (operands[0])),
16827 operands[0] = gen_lowpart (SImode, operands[0]);
16828 operands[1] = gen_lowpart (SImode, operands[1]);")
16830 ; Don't promote the QImode tests, as i386 don't have encoding of
16831 ; the test instruction with 32bit sign extended immediate and thus
16835 (compare (and (match_operand:HI 0 "aligned_operand" "")
16836 (match_operand:HI 1 "const_int_operand" ""))
16838 "! TARGET_PARTIAL_REG_STALL && reload_completed
16839 && ix86_match_ccmode (insn, CCNOmode)
16840 && GET_MODE (operands[0]) == HImode"
16841 [(set (reg:CCNO 17)
16842 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
16845 = gen_int_mode (INTVAL (operands[1])
16846 & GET_MODE_MASK (GET_MODE (operands[0])),
16848 operands[0] = gen_lowpart (SImode, operands[0]);")
16851 [(set (match_operand 0 "register_operand" "")
16852 (neg (match_operand 1 "register_operand" "")))
16853 (clobber (reg:CC 17))]
16854 "! TARGET_PARTIAL_REG_STALL && reload_completed
16855 && (GET_MODE (operands[0]) == HImode
16856 || (GET_MODE (operands[0]) == QImode
16857 && (TARGET_PROMOTE_QImode || optimize_size)))"
16858 [(parallel [(set (match_dup 0)
16859 (neg:SI (match_dup 1)))
16860 (clobber (reg:CC 17))])]
16861 "operands[0] = gen_lowpart (SImode, operands[0]);
16862 operands[1] = gen_lowpart (SImode, operands[1]);")
16865 [(set (match_operand 0 "register_operand" "")
16866 (not (match_operand 1 "register_operand" "")))]
16867 "! TARGET_PARTIAL_REG_STALL && reload_completed
16868 && (GET_MODE (operands[0]) == HImode
16869 || (GET_MODE (operands[0]) == QImode
16870 && (TARGET_PROMOTE_QImode || optimize_size)))"
16871 [(set (match_dup 0)
16872 (not:SI (match_dup 1)))]
16873 "operands[0] = gen_lowpart (SImode, operands[0]);
16874 operands[1] = gen_lowpart (SImode, operands[1]);")
16877 [(set (match_operand 0 "register_operand" "")
16878 (if_then_else (match_operator 1 "comparison_operator"
16879 [(reg 17) (const_int 0)])
16880 (match_operand 2 "register_operand" "")
16881 (match_operand 3 "register_operand" "")))]
16882 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
16883 && (GET_MODE (operands[0]) == HImode
16884 || (GET_MODE (operands[0]) == QImode
16885 && (TARGET_PROMOTE_QImode || optimize_size)))"
16886 [(set (match_dup 0)
16887 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
16888 "operands[0] = gen_lowpart (SImode, operands[0]);
16889 operands[2] = gen_lowpart (SImode, operands[2]);
16890 operands[3] = gen_lowpart (SImode, operands[3]);")
16893 ;; RTL Peephole optimizations, run before sched2. These primarily look to
16894 ;; transform a complex memory operation into two memory to register operations.
16896 ;; Don't push memory operands
16898 [(set (match_operand:SI 0 "push_operand" "")
16899 (match_operand:SI 1 "memory_operand" ""))
16900 (match_scratch:SI 2 "r")]
16901 "! optimize_size && ! TARGET_PUSH_MEMORY"
16902 [(set (match_dup 2) (match_dup 1))
16903 (set (match_dup 0) (match_dup 2))]
16907 [(set (match_operand:DI 0 "push_operand" "")
16908 (match_operand:DI 1 "memory_operand" ""))
16909 (match_scratch:DI 2 "r")]
16910 "! optimize_size && ! TARGET_PUSH_MEMORY"
16911 [(set (match_dup 2) (match_dup 1))
16912 (set (match_dup 0) (match_dup 2))]
16915 ;; We need to handle SFmode only, because DFmode and XFmode is split to
16918 [(set (match_operand:SF 0 "push_operand" "")
16919 (match_operand:SF 1 "memory_operand" ""))
16920 (match_scratch:SF 2 "r")]
16921 "! optimize_size && ! TARGET_PUSH_MEMORY"
16922 [(set (match_dup 2) (match_dup 1))
16923 (set (match_dup 0) (match_dup 2))]
16927 [(set (match_operand:HI 0 "push_operand" "")
16928 (match_operand:HI 1 "memory_operand" ""))
16929 (match_scratch:HI 2 "r")]
16930 "! optimize_size && ! TARGET_PUSH_MEMORY"
16931 [(set (match_dup 2) (match_dup 1))
16932 (set (match_dup 0) (match_dup 2))]
16936 [(set (match_operand:QI 0 "push_operand" "")
16937 (match_operand:QI 1 "memory_operand" ""))
16938 (match_scratch:QI 2 "q")]
16939 "! optimize_size && ! TARGET_PUSH_MEMORY"
16940 [(set (match_dup 2) (match_dup 1))
16941 (set (match_dup 0) (match_dup 2))]
16944 ;; Don't move an immediate directly to memory when the instruction
16947 [(match_scratch:SI 1 "r")
16948 (set (match_operand:SI 0 "memory_operand" "")
16951 && ! TARGET_USE_MOV0
16952 && TARGET_SPLIT_LONG_MOVES
16953 && get_attr_length (insn) >= ix86_cost->large_insn
16954 && peep2_regno_dead_p (0, FLAGS_REG)"
16955 [(parallel [(set (match_dup 1) (const_int 0))
16956 (clobber (reg:CC 17))])
16957 (set (match_dup 0) (match_dup 1))]
16961 [(match_scratch:HI 1 "r")
16962 (set (match_operand:HI 0 "memory_operand" "")
16965 && ! TARGET_USE_MOV0
16966 && TARGET_SPLIT_LONG_MOVES
16967 && get_attr_length (insn) >= ix86_cost->large_insn
16968 && peep2_regno_dead_p (0, FLAGS_REG)"
16969 [(parallel [(set (match_dup 2) (const_int 0))
16970 (clobber (reg:CC 17))])
16971 (set (match_dup 0) (match_dup 1))]
16972 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16975 [(match_scratch:QI 1 "q")
16976 (set (match_operand:QI 0 "memory_operand" "")
16979 && ! TARGET_USE_MOV0
16980 && TARGET_SPLIT_LONG_MOVES
16981 && get_attr_length (insn) >= ix86_cost->large_insn
16982 && peep2_regno_dead_p (0, FLAGS_REG)"
16983 [(parallel [(set (match_dup 2) (const_int 0))
16984 (clobber (reg:CC 17))])
16985 (set (match_dup 0) (match_dup 1))]
16986 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
16989 [(match_scratch:SI 2 "r")
16990 (set (match_operand:SI 0 "memory_operand" "")
16991 (match_operand:SI 1 "immediate_operand" ""))]
16993 && get_attr_length (insn) >= ix86_cost->large_insn
16994 && TARGET_SPLIT_LONG_MOVES"
16995 [(set (match_dup 2) (match_dup 1))
16996 (set (match_dup 0) (match_dup 2))]
17000 [(match_scratch:HI 2 "r")
17001 (set (match_operand:HI 0 "memory_operand" "")
17002 (match_operand:HI 1 "immediate_operand" ""))]
17003 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17004 && TARGET_SPLIT_LONG_MOVES"
17005 [(set (match_dup 2) (match_dup 1))
17006 (set (match_dup 0) (match_dup 2))]
17010 [(match_scratch:QI 2 "q")
17011 (set (match_operand:QI 0 "memory_operand" "")
17012 (match_operand:QI 1 "immediate_operand" ""))]
17013 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17014 && TARGET_SPLIT_LONG_MOVES"
17015 [(set (match_dup 2) (match_dup 1))
17016 (set (match_dup 0) (match_dup 2))]
17019 ;; Don't compare memory with zero, load and use a test instead.
17022 (compare (match_operand:SI 0 "memory_operand" "")
17024 (match_scratch:SI 3 "r")]
17025 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17026 [(set (match_dup 3) (match_dup 0))
17027 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
17030 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17031 ;; Don't split NOTs with a displacement operand, because resulting XOR
17032 ;; will not be pariable anyway.
17034 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
17035 ;; represented using a modRM byte. The XOR replacement is long decoded,
17036 ;; so this split helps here as well.
17038 ;; Note: Can't do this as a regular split because we can't get proper
17039 ;; lifetime information then.
17042 [(set (match_operand:SI 0 "nonimmediate_operand" "")
17043 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
17045 && peep2_regno_dead_p (0, FLAGS_REG)
17046 && ((TARGET_PENTIUM
17047 && (GET_CODE (operands[0]) != MEM
17048 || !memory_displacement_operand (operands[0], SImode)))
17049 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
17050 [(parallel [(set (match_dup 0)
17051 (xor:SI (match_dup 1) (const_int -1)))
17052 (clobber (reg:CC 17))])]
17056 [(set (match_operand:HI 0 "nonimmediate_operand" "")
17057 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
17059 && peep2_regno_dead_p (0, FLAGS_REG)
17060 && ((TARGET_PENTIUM
17061 && (GET_CODE (operands[0]) != MEM
17062 || !memory_displacement_operand (operands[0], HImode)))
17063 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
17064 [(parallel [(set (match_dup 0)
17065 (xor:HI (match_dup 1) (const_int -1)))
17066 (clobber (reg:CC 17))])]
17070 [(set (match_operand:QI 0 "nonimmediate_operand" "")
17071 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
17073 && peep2_regno_dead_p (0, FLAGS_REG)
17074 && ((TARGET_PENTIUM
17075 && (GET_CODE (operands[0]) != MEM
17076 || !memory_displacement_operand (operands[0], QImode)))
17077 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
17078 [(parallel [(set (match_dup 0)
17079 (xor:QI (match_dup 1) (const_int -1)))
17080 (clobber (reg:CC 17))])]
17083 ;; Non pairable "test imm, reg" instructions can be translated to
17084 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17085 ;; byte opcode instead of two, have a short form for byte operands),
17086 ;; so do it for other CPUs as well. Given that the value was dead,
17087 ;; this should not create any new dependencies. Pass on the sub-word
17088 ;; versions if we're concerned about partial register stalls.
17092 (compare (and:SI (match_operand:SI 0 "register_operand" "")
17093 (match_operand:SI 1 "immediate_operand" ""))
17095 "ix86_match_ccmode (insn, CCNOmode)
17096 && (true_regnum (operands[0]) != 0
17097 || (GET_CODE (operands[1]) == CONST_INT
17098 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
17099 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17101 [(set (reg:CCNO 17)
17102 (compare:CCNO (and:SI (match_dup 0)
17106 (and:SI (match_dup 0) (match_dup 1)))])]
17109 ;; We don't need to handle HImode case, because it will be promoted to SImode
17110 ;; on ! TARGET_PARTIAL_REG_STALL
17114 (compare (and:QI (match_operand:QI 0 "register_operand" "")
17115 (match_operand:QI 1 "immediate_operand" ""))
17117 "! TARGET_PARTIAL_REG_STALL
17118 && ix86_match_ccmode (insn, CCNOmode)
17119 && true_regnum (operands[0]) != 0
17120 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17122 [(set (reg:CCNO 17)
17123 (compare:CCNO (and:QI (match_dup 0)
17127 (and:QI (match_dup 0) (match_dup 1)))])]
17135 (match_operand 0 "ext_register_operand" "")
17138 (match_operand 1 "const_int_operand" ""))
17140 "! TARGET_PARTIAL_REG_STALL
17141 && ix86_match_ccmode (insn, CCNOmode)
17142 && true_regnum (operands[0]) != 0
17143 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17144 [(parallel [(set (reg:CCNO 17)
17153 (set (zero_extract:SI (match_dup 0)
17164 ;; Don't do logical operations with memory inputs.
17166 [(match_scratch:SI 2 "r")
17167 (parallel [(set (match_operand:SI 0 "register_operand" "")
17168 (match_operator:SI 3 "arith_or_logical_operator"
17170 (match_operand:SI 1 "memory_operand" "")]))
17171 (clobber (reg:CC 17))])]
17172 "! optimize_size && ! TARGET_READ_MODIFY"
17173 [(set (match_dup 2) (match_dup 1))
17174 (parallel [(set (match_dup 0)
17175 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
17176 (clobber (reg:CC 17))])]
17180 [(match_scratch:SI 2 "r")
17181 (parallel [(set (match_operand:SI 0 "register_operand" "")
17182 (match_operator:SI 3 "arith_or_logical_operator"
17183 [(match_operand:SI 1 "memory_operand" "")
17185 (clobber (reg:CC 17))])]
17186 "! optimize_size && ! TARGET_READ_MODIFY"
17187 [(set (match_dup 2) (match_dup 1))
17188 (parallel [(set (match_dup 0)
17189 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
17190 (clobber (reg:CC 17))])]
17193 ; Don't do logical operations with memory outputs
17195 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
17196 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
17197 ; the same decoder scheduling characteristics as the original.
17200 [(match_scratch:SI 2 "r")
17201 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17202 (match_operator:SI 3 "arith_or_logical_operator"
17204 (match_operand:SI 1 "nonmemory_operand" "")]))
17205 (clobber (reg:CC 17))])]
17206 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17207 [(set (match_dup 2) (match_dup 0))
17208 (parallel [(set (match_dup 2)
17209 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
17210 (clobber (reg:CC 17))])
17211 (set (match_dup 0) (match_dup 2))]
17215 [(match_scratch:SI 2 "r")
17216 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17217 (match_operator:SI 3 "arith_or_logical_operator"
17218 [(match_operand:SI 1 "nonmemory_operand" "")
17220 (clobber (reg:CC 17))])]
17221 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17222 [(set (match_dup 2) (match_dup 0))
17223 (parallel [(set (match_dup 2)
17224 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17225 (clobber (reg:CC 17))])
17226 (set (match_dup 0) (match_dup 2))]
17229 ;; Attempt to always use XOR for zeroing registers.
17231 [(set (match_operand 0 "register_operand" "")
17233 "(GET_MODE (operands[0]) == QImode
17234 || GET_MODE (operands[0]) == HImode
17235 || GET_MODE (operands[0]) == SImode
17236 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17237 && (! TARGET_USE_MOV0 || optimize_size)
17238 && peep2_regno_dead_p (0, FLAGS_REG)"
17239 [(parallel [(set (match_dup 0) (const_int 0))
17240 (clobber (reg:CC 17))])]
17241 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17242 true_regnum (operands[0]));")
17245 [(set (strict_low_part (match_operand 0 "register_operand" ""))
17247 "(GET_MODE (operands[0]) == QImode
17248 || GET_MODE (operands[0]) == HImode)
17249 && (! TARGET_USE_MOV0 || optimize_size)
17250 && peep2_regno_dead_p (0, FLAGS_REG)"
17251 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
17252 (clobber (reg:CC 17))])])
17254 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
17256 [(set (match_operand 0 "register_operand" "")
17258 "(GET_MODE (operands[0]) == HImode
17259 || GET_MODE (operands[0]) == SImode
17260 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17261 && (optimize_size || TARGET_PENTIUM)
17262 && peep2_regno_dead_p (0, FLAGS_REG)"
17263 [(parallel [(set (match_dup 0) (const_int -1))
17264 (clobber (reg:CC 17))])]
17265 "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17266 true_regnum (operands[0]));")
17268 ;; Attempt to convert simple leas to adds. These can be created by
17271 [(set (match_operand:SI 0 "register_operand" "")
17272 (plus:SI (match_dup 0)
17273 (match_operand:SI 1 "nonmemory_operand" "")))]
17274 "peep2_regno_dead_p (0, FLAGS_REG)"
17275 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
17276 (clobber (reg:CC 17))])]
17280 [(set (match_operand:SI 0 "register_operand" "")
17281 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
17282 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
17283 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
17284 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
17285 (clobber (reg:CC 17))])]
17286 "operands[2] = gen_lowpart (SImode, operands[2]);")
17289 [(set (match_operand:DI 0 "register_operand" "")
17290 (plus:DI (match_dup 0)
17291 (match_operand:DI 1 "x86_64_general_operand" "")))]
17292 "peep2_regno_dead_p (0, FLAGS_REG)"
17293 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
17294 (clobber (reg:CC 17))])]
17298 [(set (match_operand:SI 0 "register_operand" "")
17299 (mult:SI (match_dup 0)
17300 (match_operand:SI 1 "const_int_operand" "")))]
17301 "exact_log2 (INTVAL (operands[1])) >= 0
17302 && peep2_regno_dead_p (0, FLAGS_REG)"
17303 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17304 (clobber (reg:CC 17))])]
17305 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17308 [(set (match_operand:DI 0 "register_operand" "")
17309 (mult:DI (match_dup 0)
17310 (match_operand:DI 1 "const_int_operand" "")))]
17311 "exact_log2 (INTVAL (operands[1])) >= 0
17312 && peep2_regno_dead_p (0, FLAGS_REG)"
17313 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17314 (clobber (reg:CC 17))])]
17315 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17318 [(set (match_operand:SI 0 "register_operand" "")
17319 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17320 (match_operand:DI 2 "const_int_operand" "")) 0))]
17321 "exact_log2 (INTVAL (operands[1])) >= 0
17322 && REGNO (operands[0]) == REGNO (operands[1])
17323 && peep2_regno_dead_p (0, FLAGS_REG)"
17324 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17325 (clobber (reg:CC 17))])]
17326 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17328 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17329 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17330 ;; many CPUs it is also faster, since special hardware to avoid esp
17331 ;; dependencies is present.
17333 ;; While some of these conversions may be done using splitters, we use peepholes
17334 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17336 ;; Convert prologue esp subtractions to push.
17337 ;; We need register to push. In order to keep verify_flow_info happy we have
17339 ;; - use scratch and clobber it in order to avoid dependencies
17340 ;; - use already live register
17341 ;; We can't use the second way right now, since there is no reliable way how to
17342 ;; verify that given register is live. First choice will also most likely in
17343 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17344 ;; call clobbered registers are dead. We may want to use base pointer as an
17345 ;; alternative when no register is available later.
17348 [(match_scratch:SI 0 "r")
17349 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17350 (clobber (reg:CC 17))
17351 (clobber (mem:BLK (scratch)))])]
17352 "optimize_size || !TARGET_SUB_ESP_4"
17353 [(clobber (match_dup 0))
17354 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17355 (clobber (mem:BLK (scratch)))])])
17358 [(match_scratch:SI 0 "r")
17359 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17360 (clobber (reg:CC 17))
17361 (clobber (mem:BLK (scratch)))])]
17362 "optimize_size || !TARGET_SUB_ESP_8"
17363 [(clobber (match_dup 0))
17364 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17365 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17366 (clobber (mem:BLK (scratch)))])])
17368 ;; Convert esp subtractions to push.
17370 [(match_scratch:SI 0 "r")
17371 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17372 (clobber (reg:CC 17))])]
17373 "optimize_size || !TARGET_SUB_ESP_4"
17374 [(clobber (match_dup 0))
17375 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17378 [(match_scratch:SI 0 "r")
17379 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17380 (clobber (reg:CC 17))])]
17381 "optimize_size || !TARGET_SUB_ESP_8"
17382 [(clobber (match_dup 0))
17383 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17384 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17386 ;; Convert epilogue deallocator to pop.
17388 [(match_scratch:SI 0 "r")
17389 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17390 (clobber (reg:CC 17))
17391 (clobber (mem:BLK (scratch)))])]
17392 "optimize_size || !TARGET_ADD_ESP_4"
17393 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17394 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17395 (clobber (mem:BLK (scratch)))])]
17398 ;; Two pops case is tricky, since pop causes dependency on destination register.
17399 ;; We use two registers if available.
17401 [(match_scratch:SI 0 "r")
17402 (match_scratch:SI 1 "r")
17403 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17404 (clobber (reg:CC 17))
17405 (clobber (mem:BLK (scratch)))])]
17406 "optimize_size || !TARGET_ADD_ESP_8"
17407 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17408 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17409 (clobber (mem:BLK (scratch)))])
17410 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17411 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17415 [(match_scratch:SI 0 "r")
17416 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17417 (clobber (reg:CC 17))
17418 (clobber (mem:BLK (scratch)))])]
17420 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17421 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17422 (clobber (mem:BLK (scratch)))])
17423 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17424 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17427 ;; Convert esp additions to pop.
17429 [(match_scratch:SI 0 "r")
17430 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17431 (clobber (reg:CC 17))])]
17433 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17434 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17437 ;; Two pops case is tricky, since pop causes dependency on destination register.
17438 ;; We use two registers if available.
17440 [(match_scratch:SI 0 "r")
17441 (match_scratch:SI 1 "r")
17442 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17443 (clobber (reg:CC 17))])]
17445 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17446 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17447 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17448 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17452 [(match_scratch:SI 0 "r")
17453 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17454 (clobber (reg:CC 17))])]
17456 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17457 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17458 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17459 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17462 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17463 ;; required and register dies.
17466 (compare (match_operand:SI 0 "register_operand" "")
17467 (match_operand:SI 1 "incdec_operand" "")))]
17468 "ix86_match_ccmode (insn, CCGCmode)
17469 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17470 [(parallel [(set (reg:CCGC 17)
17471 (compare:CCGC (match_dup 0)
17473 (clobber (match_dup 0))])]
17478 (compare (match_operand:HI 0 "register_operand" "")
17479 (match_operand:HI 1 "incdec_operand" "")))]
17480 "ix86_match_ccmode (insn, CCGCmode)
17481 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17482 [(parallel [(set (reg:CCGC 17)
17483 (compare:CCGC (match_dup 0)
17485 (clobber (match_dup 0))])]
17490 (compare (match_operand:QI 0 "register_operand" "")
17491 (match_operand:QI 1 "incdec_operand" "")))]
17492 "ix86_match_ccmode (insn, CCGCmode)
17493 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17494 [(parallel [(set (reg:CCGC 17)
17495 (compare:CCGC (match_dup 0)
17497 (clobber (match_dup 0))])]
17500 ;; Convert compares with 128 to shorter add -128
17503 (compare (match_operand:SI 0 "register_operand" "")
17505 "ix86_match_ccmode (insn, CCGCmode)
17506 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17507 [(parallel [(set (reg:CCGC 17)
17508 (compare:CCGC (match_dup 0)
17510 (clobber (match_dup 0))])]
17515 (compare (match_operand:HI 0 "register_operand" "")
17517 "ix86_match_ccmode (insn, CCGCmode)
17518 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17519 [(parallel [(set (reg:CCGC 17)
17520 (compare:CCGC (match_dup 0)
17522 (clobber (match_dup 0))])]
17526 [(match_scratch:DI 0 "r")
17527 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17528 (clobber (reg:CC 17))
17529 (clobber (mem:BLK (scratch)))])]
17530 "optimize_size || !TARGET_SUB_ESP_4"
17531 [(clobber (match_dup 0))
17532 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17533 (clobber (mem:BLK (scratch)))])])
17536 [(match_scratch:DI 0 "r")
17537 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17538 (clobber (reg:CC 17))
17539 (clobber (mem:BLK (scratch)))])]
17540 "optimize_size || !TARGET_SUB_ESP_8"
17541 [(clobber (match_dup 0))
17542 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17543 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17544 (clobber (mem:BLK (scratch)))])])
17546 ;; Convert esp subtractions to push.
17548 [(match_scratch:DI 0 "r")
17549 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
17550 (clobber (reg:CC 17))])]
17551 "optimize_size || !TARGET_SUB_ESP_4"
17552 [(clobber (match_dup 0))
17553 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17556 [(match_scratch:DI 0 "r")
17557 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
17558 (clobber (reg:CC 17))])]
17559 "optimize_size || !TARGET_SUB_ESP_8"
17560 [(clobber (match_dup 0))
17561 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
17562 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
17564 ;; Convert epilogue deallocator to pop.
17566 [(match_scratch:DI 0 "r")
17567 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17568 (clobber (reg:CC 17))
17569 (clobber (mem:BLK (scratch)))])]
17570 "optimize_size || !TARGET_ADD_ESP_4"
17571 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17572 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17573 (clobber (mem:BLK (scratch)))])]
17576 ;; Two pops case is tricky, since pop causes dependency on destination register.
17577 ;; We use two registers if available.
17579 [(match_scratch:DI 0 "r")
17580 (match_scratch:DI 1 "r")
17581 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17582 (clobber (reg:CC 17))
17583 (clobber (mem:BLK (scratch)))])]
17584 "optimize_size || !TARGET_ADD_ESP_8"
17585 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17586 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17587 (clobber (mem:BLK (scratch)))])
17588 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17589 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17593 [(match_scratch:DI 0 "r")
17594 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17595 (clobber (reg:CC 17))
17596 (clobber (mem:BLK (scratch)))])]
17598 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17599 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17600 (clobber (mem:BLK (scratch)))])
17601 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17602 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17605 ;; Convert esp additions to pop.
17607 [(match_scratch:DI 0 "r")
17608 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
17609 (clobber (reg:CC 17))])]
17611 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17612 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17615 ;; Two pops case is tricky, since pop causes dependency on destination register.
17616 ;; We use two registers if available.
17618 [(match_scratch:DI 0 "r")
17619 (match_scratch:DI 1 "r")
17620 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17621 (clobber (reg:CC 17))])]
17623 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17624 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17625 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
17626 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17630 [(match_scratch:DI 0 "r")
17631 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
17632 (clobber (reg:CC 17))])]
17634 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17635 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
17636 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
17637 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
17640 ;; Call-value patterns last so that the wildcard operand does not
17641 ;; disrupt insn-recog's switch tables.
17643 (define_insn "*call_value_pop_0"
17644 [(set (match_operand 0 "" "")
17645 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17646 (match_operand:SI 2 "" "")))
17647 (set (reg:SI 7) (plus:SI (reg:SI 7)
17648 (match_operand:SI 3 "immediate_operand" "")))]
17651 if (SIBLING_CALL_P (insn))
17654 return "call\t%P1";
17656 [(set_attr "type" "callv")])
17658 (define_insn "*call_value_pop_1"
17659 [(set (match_operand 0 "" "")
17660 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17661 (match_operand:SI 2 "" "")))
17662 (set (reg:SI 7) (plus:SI (reg:SI 7)
17663 (match_operand:SI 3 "immediate_operand" "i")))]
17666 if (constant_call_address_operand (operands[1], QImode))
17668 if (SIBLING_CALL_P (insn))
17671 return "call\t%P1";
17673 if (SIBLING_CALL_P (insn))
17676 return "call\t%A1";
17678 [(set_attr "type" "callv")])
17680 (define_insn "*call_value_0"
17681 [(set (match_operand 0 "" "")
17682 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
17683 (match_operand:SI 2 "" "")))]
17686 if (SIBLING_CALL_P (insn))
17689 return "call\t%P1";
17691 [(set_attr "type" "callv")])
17693 (define_insn "*call_value_0_rex64"
17694 [(set (match_operand 0 "" "")
17695 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
17696 (match_operand:DI 2 "const_int_operand" "")))]
17699 if (SIBLING_CALL_P (insn))
17702 return "call\t%P1";
17704 [(set_attr "type" "callv")])
17706 (define_insn "*call_value_1"
17707 [(set (match_operand 0 "" "")
17708 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
17709 (match_operand:SI 2 "" "")))]
17712 if (constant_call_address_operand (operands[1], QImode))
17714 if (SIBLING_CALL_P (insn))
17717 return "call\t%P1";
17719 if (SIBLING_CALL_P (insn))
17720 return "jmp\t%*%1";
17722 return "call\t%*%1";
17724 [(set_attr "type" "callv")])
17726 (define_insn "*call_value_1_rex64"
17727 [(set (match_operand 0 "" "")
17728 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
17729 (match_operand:DI 2 "" "")))]
17732 if (constant_call_address_operand (operands[1], QImode))
17734 if (SIBLING_CALL_P (insn))
17737 return "call\t%P1";
17739 if (SIBLING_CALL_P (insn))
17742 return "call\t%A1";
17744 [(set_attr "type" "callv")])
17746 (define_insn "trap"
17747 [(trap_if (const_int 1) (const_int 5))]
17751 ;;; ix86 doesn't have conditional trap instructions, but we fake them
17752 ;;; for the sake of bounds checking. By emitting bounds checks as
17753 ;;; conditional traps rather than as conditional jumps around
17754 ;;; unconditional traps we avoid introducing spurious basic-block
17755 ;;; boundaries and facilitate elimination of redundant checks. In
17756 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
17759 ;;; FIXME: Static branch prediction rules for ix86 are such that
17760 ;;; forward conditional branches predict as untaken. As implemented
17761 ;;; below, pseudo conditional traps violate that rule. We should use
17762 ;;; .pushsection/.popsection to place all of the `int 5's in a special
17763 ;;; section loaded at the end of the text segment and branch forward
17764 ;;; there on bounds-failure, and then jump back immediately (in case
17765 ;;; the system chooses to ignore bounds violations, or to report
17766 ;;; violations and continue execution).
17768 (define_expand "conditional_trap"
17769 [(trap_if (match_operator 0 "comparison_operator"
17770 [(match_dup 2) (const_int 0)])
17771 (match_operand 1 "const_int_operand" ""))]
17774 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
17775 ix86_expand_compare (GET_CODE (operands[0]),
17781 (define_insn "*conditional_trap_1"
17782 [(trap_if (match_operator 0 "comparison_operator"
17783 [(reg 17) (const_int 0)])
17784 (match_operand 1 "const_int_operand" ""))]
17787 operands[2] = gen_label_rtx ();
17788 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
17789 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
17790 CODE_LABEL_NUMBER (operands[2]));
17794 ;; Pentium III SIMD instructions.
17796 ;; Moves for SSE/MMX regs.
17798 (define_insn "movv4sf_internal"
17799 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
17800 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x"))]
17802 ;; @@@ let's try to use movaps here.
17803 "movaps\t{%1, %0|%0, %1}"
17804 [(set_attr "type" "ssemov")
17805 (set_attr "mode" "V4SF")])
17807 (define_insn "movv4si_internal"
17808 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
17809 (match_operand:V4SI 1 "nonimmediate_operand" "xm,x"))]
17811 ;; @@@ let's try to use movaps here.
17812 "movaps\t{%1, %0|%0, %1}"
17813 [(set_attr "type" "ssemov")
17814 (set_attr "mode" "V4SF")])
17816 (define_insn "movv8qi_internal"
17817 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
17818 (match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
17820 "movq\t{%1, %0|%0, %1}"
17821 [(set_attr "type" "mmxmov")
17822 (set_attr "mode" "DI")])
17824 (define_insn "movv4hi_internal"
17825 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
17826 (match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
17828 "movq\t{%1, %0|%0, %1}"
17829 [(set_attr "type" "mmxmov")
17830 (set_attr "mode" "DI")])
17832 (define_insn "movv2si_internal"
17833 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
17834 (match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
17836 "movq\t{%1, %0|%0, %1}"
17837 [(set_attr "type" "mmxcvt")
17838 (set_attr "mode" "DI")])
17840 (define_insn "movv2sf_internal"
17841 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
17842 (match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
17844 "movq\\t{%1, %0|%0, %1}"
17845 [(set_attr "type" "mmxcvt")
17846 (set_attr "mode" "DI")])
17848 (define_expand "movti"
17849 [(set (match_operand:TI 0 "general_operand" "")
17850 (match_operand:TI 1 "general_operand" ""))]
17851 "TARGET_SSE || TARGET_64BIT"
17854 ix86_expand_move (TImode, operands);
17856 ix86_expand_vector_move (TImode, operands);
17860 (define_insn "movv2df_internal"
17861 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
17862 (match_operand:V2DF 1 "general_operand" "xm,x"))]
17864 ;; @@@ let's try to use movaps here.
17865 "movapd\t{%1, %0|%0, %1}"
17866 [(set_attr "type" "ssemov")
17867 (set_attr "mode" "V2DF")])
17869 (define_insn "movv8hi_internal"
17870 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
17871 (match_operand:V8HI 1 "general_operand" "xm,x"))]
17873 ;; @@@ let's try to use movaps here.
17874 "movaps\t{%1, %0|%0, %1}"
17875 [(set_attr "type" "ssemov")
17876 (set_attr "mode" "V4SF")])
17878 (define_insn "movv16qi_internal"
17879 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
17880 (match_operand:V16QI 1 "general_operand" "xm,x"))]
17882 ;; @@@ let's try to use movaps here.
17883 "movaps\t{%1, %0|%0, %1}"
17884 [(set_attr "type" "ssemov")
17885 (set_attr "mode" "V4SF")])
17887 (define_expand "movv2df"
17888 [(set (match_operand:V2DF 0 "general_operand" "")
17889 (match_operand:V2DF 1 "general_operand" ""))]
17892 ix86_expand_vector_move (V2DFmode, operands);
17896 (define_expand "movv8hi"
17897 [(set (match_operand:V8HI 0 "general_operand" "")
17898 (match_operand:V8HI 1 "general_operand" ""))]
17901 ix86_expand_vector_move (V8HImode, operands);
17905 (define_expand "movv16qi"
17906 [(set (match_operand:V16QI 0 "general_operand" "")
17907 (match_operand:V16QI 1 "general_operand" ""))]
17910 ix86_expand_vector_move (V16QImode, operands);
17914 (define_expand "movv4sf"
17915 [(set (match_operand:V4SF 0 "general_operand" "")
17916 (match_operand:V4SF 1 "general_operand" ""))]
17919 ix86_expand_vector_move (V4SFmode, operands);
17923 (define_expand "movv4si"
17924 [(set (match_operand:V4SI 0 "general_operand" "")
17925 (match_operand:V4SI 1 "general_operand" ""))]
17928 ix86_expand_vector_move (V4SImode, operands);
17932 (define_expand "movv2si"
17933 [(set (match_operand:V2SI 0 "general_operand" "")
17934 (match_operand:V2SI 1 "general_operand" ""))]
17937 ix86_expand_vector_move (V2SImode, operands);
17941 (define_expand "movv4hi"
17942 [(set (match_operand:V4HI 0 "general_operand" "")
17943 (match_operand:V4HI 1 "general_operand" ""))]
17946 ix86_expand_vector_move (V4HImode, operands);
17950 (define_expand "movv8qi"
17951 [(set (match_operand:V8QI 0 "general_operand" "")
17952 (match_operand:V8QI 1 "general_operand" ""))]
17955 ix86_expand_vector_move (V8QImode, operands);
17959 (define_expand "movv2sf"
17960 [(set (match_operand:V2SF 0 "general_operand" "")
17961 (match_operand:V2SF 1 "general_operand" ""))]
17964 ix86_expand_vector_move (V2SFmode, operands);
17968 (define_insn_and_split "*pushti"
17969 [(set (match_operand:TI 0 "push_operand" "=<")
17970 (match_operand:TI 1 "nonmemory_operand" "x"))]
17974 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17975 (set (mem:TI (reg:SI 7)) (match_dup 1))]
17977 [(set_attr "type" "multi")])
17979 (define_insn_and_split "*pushv2df"
17980 [(set (match_operand:V2DF 0 "push_operand" "=<")
17981 (match_operand:V2DF 1 "nonmemory_operand" "x"))]
17985 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17986 (set (mem:V2DF (reg:SI 7)) (match_dup 1))]
17988 [(set_attr "type" "multi")])
17990 (define_insn_and_split "*pushv8hi"
17991 [(set (match_operand:V8HI 0 "push_operand" "=<")
17992 (match_operand:V8HI 1 "nonmemory_operand" "x"))]
17996 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
17997 (set (mem:V8HI (reg:SI 7)) (match_dup 1))]
17999 [(set_attr "type" "multi")])
18001 (define_insn_and_split "*pushv16qi"
18002 [(set (match_operand:V16QI 0 "push_operand" "=<")
18003 (match_operand:V16QI 1 "nonmemory_operand" "x"))]
18007 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18008 (set (mem:V16QI (reg:SI 7)) (match_dup 1))]
18010 [(set_attr "type" "multi")])
18012 (define_insn_and_split "*pushv4sf"
18013 [(set (match_operand:V4SF 0 "push_operand" "=<")
18014 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
18018 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18019 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
18021 [(set_attr "type" "multi")])
18023 (define_insn_and_split "*pushv4si"
18024 [(set (match_operand:V4SI 0 "push_operand" "=<")
18025 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
18029 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
18030 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
18032 [(set_attr "type" "multi")])
18034 (define_insn_and_split "*pushv2si"
18035 [(set (match_operand:V2SI 0 "push_operand" "=<")
18036 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
18040 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18041 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
18043 [(set_attr "type" "mmx")])
18045 (define_insn_and_split "*pushv4hi"
18046 [(set (match_operand:V4HI 0 "push_operand" "=<")
18047 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
18051 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18052 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
18054 [(set_attr "type" "mmx")])
18056 (define_insn_and_split "*pushv8qi"
18057 [(set (match_operand:V8QI 0 "push_operand" "=<")
18058 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
18062 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18063 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
18065 [(set_attr "type" "mmx")])
18067 (define_insn_and_split "*pushv2sf"
18068 [(set (match_operand:V2SF 0 "push_operand" "=<")
18069 (match_operand:V2SF 1 "nonmemory_operand" "y"))]
18073 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18074 (set (mem:V2SF (reg:SI 7)) (match_dup 1))]
18076 [(set_attr "type" "mmx")])
18078 (define_insn "movti_internal"
18079 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
18080 (match_operand:TI 1 "general_operand" "O,xm,x"))]
18081 "TARGET_SSE && !TARGET_64BIT"
18084 movaps\t{%1, %0|%0, %1}
18085 movaps\t{%1, %0|%0, %1}"
18086 [(set_attr "type" "ssemov,ssemov,ssemov")
18087 (set_attr "mode" "V4SF")])
18089 (define_insn "*movti_rex64"
18090 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x")
18091 (match_operand:TI 1 "general_operand" "riFo,riF,O,x,m"))]
18093 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18098 movaps\\t{%1, %0|%0, %1}
18099 movaps\\t{%1, %0|%0, %1}"
18100 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
18101 (set_attr "mode" "V4SF")])
18104 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18105 (match_operand:TI 1 "general_operand" ""))]
18106 "reload_completed && !SSE_REG_P (operands[0])
18107 && !SSE_REG_P (operands[1])"
18109 "ix86_split_long_move (operands); DONE;")
18111 ;; These two patterns are useful for specifying exactly whether to use
18112 ;; movaps or movups
18113 (define_insn "sse_movaps"
18114 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18115 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
18119 movaps\t{%1, %0|%0, %1}
18120 movaps\t{%1, %0|%0, %1}"
18121 [(set_attr "type" "ssemov,ssemov")
18122 (set_attr "mode" "V4SF")])
18124 (define_insn "sse_movups"
18125 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18126 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
18130 movups\t{%1, %0|%0, %1}
18131 movups\t{%1, %0|%0, %1}"
18132 [(set_attr "type" "ssecvt,ssecvt")
18133 (set_attr "mode" "V4SF")])
18136 ;; SSE Strange Moves.
18138 (define_insn "sse_movmskps"
18139 [(set (match_operand:SI 0 "register_operand" "=r")
18140 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
18143 "movmskps\t{%1, %0|%0, %1}"
18144 [(set_attr "type" "ssecvt")
18145 (set_attr "mode" "V4SF")])
18147 (define_insn "mmx_pmovmskb"
18148 [(set (match_operand:SI 0 "register_operand" "=r")
18149 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
18151 "TARGET_SSE || TARGET_3DNOW_A"
18152 "pmovmskb\t{%1, %0|%0, %1}"
18153 [(set_attr "type" "ssecvt")
18154 (set_attr "mode" "V4SF")])
18157 (define_insn "mmx_maskmovq"
18158 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
18159 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18160 (match_operand:V8QI 2 "register_operand" "y")]
18162 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
18163 ;; @@@ check ordering of operands in intel/nonintel syntax
18164 "maskmovq\t{%2, %1|%1, %2}"
18165 [(set_attr "type" "mmxcvt")
18166 (set_attr "mode" "DI")])
18168 (define_insn "mmx_maskmovq_rex"
18169 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
18170 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
18171 (match_operand:V8QI 2 "register_operand" "y")]
18173 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
18174 ;; @@@ check ordering of operands in intel/nonintel syntax
18175 "maskmovq\t{%2, %1|%1, %2}"
18176 [(set_attr "type" "mmxcvt")
18177 (set_attr "mode" "DI")])
18179 (define_insn "sse_movntv4sf"
18180 [(set (match_operand:V4SF 0 "memory_operand" "=m")
18181 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
18184 "movntps\t{%1, %0|%0, %1}"
18185 [(set_attr "type" "ssemov")
18186 (set_attr "mode" "V4SF")])
18188 (define_insn "sse_movntdi"
18189 [(set (match_operand:DI 0 "memory_operand" "=m")
18190 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
18192 "TARGET_SSE || TARGET_3DNOW_A"
18193 "movntq\t{%1, %0|%0, %1}"
18194 [(set_attr "type" "mmxmov")
18195 (set_attr "mode" "DI")])
18197 (define_insn "sse_movhlps"
18198 [(set (match_operand:V4SF 0 "register_operand" "=x")
18200 (match_operand:V4SF 1 "register_operand" "0")
18201 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18202 (parallel [(const_int 2)
18208 "movhlps\t{%2, %0|%0, %2}"
18209 [(set_attr "type" "ssecvt")
18210 (set_attr "mode" "V4SF")])
18212 (define_insn "sse_movlhps"
18213 [(set (match_operand:V4SF 0 "register_operand" "=x")
18215 (match_operand:V4SF 1 "register_operand" "0")
18216 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18217 (parallel [(const_int 2)
18223 "movlhps\t{%2, %0|%0, %2}"
18224 [(set_attr "type" "ssecvt")
18225 (set_attr "mode" "V4SF")])
18227 (define_insn "sse_movhps"
18228 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18230 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
18231 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
18234 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
18235 "movhps\t{%2, %0|%0, %2}"
18236 [(set_attr "type" "ssecvt")
18237 (set_attr "mode" "V4SF")])
18239 (define_insn "sse_movlps"
18240 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
18242 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
18243 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
18246 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
18247 "movlps\t{%2, %0|%0, %2}"
18248 [(set_attr "type" "ssecvt")
18249 (set_attr "mode" "V4SF")])
18251 (define_insn "sse_loadss"
18252 [(set (match_operand:V4SF 0 "register_operand" "=x")
18254 (match_operand:V4SF 1 "memory_operand" "m")
18255 (vec_duplicate:V4SF (float:SF (const_int 0)))
18258 "movss\t{%1, %0|%0, %1}"
18259 [(set_attr "type" "ssemov")
18260 (set_attr "mode" "SF")])
18262 (define_insn "sse_movss"
18263 [(set (match_operand:V4SF 0 "register_operand" "=x")
18265 (match_operand:V4SF 1 "register_operand" "0")
18266 (match_operand:V4SF 2 "register_operand" "x")
18269 "movss\t{%2, %0|%0, %2}"
18270 [(set_attr "type" "ssemov")
18271 (set_attr "mode" "SF")])
18273 (define_insn "sse_storess"
18274 [(set (match_operand:SF 0 "memory_operand" "=m")
18276 (match_operand:V4SF 1 "register_operand" "x")
18277 (parallel [(const_int 0)])))]
18279 "movss\t{%1, %0|%0, %1}"
18280 [(set_attr "type" "ssemov")
18281 (set_attr "mode" "SF")])
18283 (define_insn "sse_shufps"
18284 [(set (match_operand:V4SF 0 "register_operand" "=x")
18285 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
18286 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
18287 (match_operand:SI 3 "immediate_operand" "i")]
18290 ;; @@@ check operand order for intel/nonintel syntax
18291 "shufps\t{%3, %2, %0|%0, %2, %3}"
18292 [(set_attr "type" "ssecvt")
18293 (set_attr "mode" "V4SF")])
18298 (define_insn "addv4sf3"
18299 [(set (match_operand:V4SF 0 "register_operand" "=x")
18300 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18301 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18303 "addps\t{%2, %0|%0, %2}"
18304 [(set_attr "type" "sseadd")
18305 (set_attr "mode" "V4SF")])
18307 (define_insn "vmaddv4sf3"
18308 [(set (match_operand:V4SF 0 "register_operand" "=x")
18310 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18311 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18315 "addss\t{%2, %0|%0, %2}"
18316 [(set_attr "type" "sseadd")
18317 (set_attr "mode" "SF")])
18319 (define_insn "subv4sf3"
18320 [(set (match_operand:V4SF 0 "register_operand" "=x")
18321 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18322 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18324 "subps\t{%2, %0|%0, %2}"
18325 [(set_attr "type" "sseadd")
18326 (set_attr "mode" "V4SF")])
18328 (define_insn "vmsubv4sf3"
18329 [(set (match_operand:V4SF 0 "register_operand" "=x")
18331 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
18332 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18336 "subss\t{%2, %0|%0, %2}"
18337 [(set_attr "type" "sseadd")
18338 (set_attr "mode" "SF")])
18340 (define_insn "mulv4sf3"
18341 [(set (match_operand:V4SF 0 "register_operand" "=x")
18342 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18343 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18345 "mulps\t{%2, %0|%0, %2}"
18346 [(set_attr "type" "ssemul")
18347 (set_attr "mode" "V4SF")])
18349 (define_insn "vmmulv4sf3"
18350 [(set (match_operand:V4SF 0 "register_operand" "=x")
18352 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
18353 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18357 "mulss\t{%2, %0|%0, %2}"
18358 [(set_attr "type" "ssemul")
18359 (set_attr "mode" "SF")])
18361 (define_insn "divv4sf3"
18362 [(set (match_operand:V4SF 0 "register_operand" "=x")
18363 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18364 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18366 "divps\t{%2, %0|%0, %2}"
18367 [(set_attr "type" "ssediv")
18368 (set_attr "mode" "V4SF")])
18370 (define_insn "vmdivv4sf3"
18371 [(set (match_operand:V4SF 0 "register_operand" "=x")
18373 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
18374 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18378 "divss\t{%2, %0|%0, %2}"
18379 [(set_attr "type" "ssediv")
18380 (set_attr "mode" "SF")])
18383 ;; SSE square root/reciprocal
18385 (define_insn "rcpv4sf2"
18386 [(set (match_operand:V4SF 0 "register_operand" "=x")
18388 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
18390 "rcpps\t{%1, %0|%0, %1}"
18391 [(set_attr "type" "sse")
18392 (set_attr "mode" "V4SF")])
18394 (define_insn "vmrcpv4sf2"
18395 [(set (match_operand:V4SF 0 "register_operand" "=x")
18397 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18399 (match_operand:V4SF 2 "register_operand" "0")
18402 "rcpss\t{%1, %0|%0, %1}"
18403 [(set_attr "type" "sse")
18404 (set_attr "mode" "SF")])
18406 (define_insn "rsqrtv4sf2"
18407 [(set (match_operand:V4SF 0 "register_operand" "=x")
18409 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
18411 "rsqrtps\t{%1, %0|%0, %1}"
18412 [(set_attr "type" "sse")
18413 (set_attr "mode" "V4SF")])
18415 (define_insn "vmrsqrtv4sf2"
18416 [(set (match_operand:V4SF 0 "register_operand" "=x")
18418 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18420 (match_operand:V4SF 2 "register_operand" "0")
18423 "rsqrtss\t{%1, %0|%0, %1}"
18424 [(set_attr "type" "sse")
18425 (set_attr "mode" "SF")])
18427 (define_insn "sqrtv4sf2"
18428 [(set (match_operand:V4SF 0 "register_operand" "=x")
18429 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
18431 "sqrtps\t{%1, %0|%0, %1}"
18432 [(set_attr "type" "sse")
18433 (set_attr "mode" "V4SF")])
18435 (define_insn "vmsqrtv4sf2"
18436 [(set (match_operand:V4SF 0 "register_operand" "=x")
18438 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18439 (match_operand:V4SF 2 "register_operand" "0")
18442 "sqrtss\t{%1, %0|%0, %1}"
18443 [(set_attr "type" "sse")
18444 (set_attr "mode" "SF")])
18446 ;; SSE logical operations.
18448 ;; These are not called andti3 etc. because we really really don't want
18449 ;; the compiler to widen DImode ands to TImode ands and then try to move
18450 ;; into DImode subregs of SSE registers, and them together, and move out
18451 ;; of DImode subregs again!
18453 (define_insn "*sse_andti3_df_1"
18454 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18455 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18456 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18458 "andpd\t{%2, %0|%0, %2}"
18459 [(set_attr "type" "sselog")
18460 (set_attr "mode" "V2DF")])
18462 (define_insn "*sse_andti3_df_2"
18463 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18464 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18465 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18467 "andpd\t{%2, %0|%0, %2}"
18468 [(set_attr "type" "sselog")
18469 (set_attr "mode" "V2DF")])
18471 (define_insn "*sse_andti3_sf_1"
18472 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18473 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18474 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18476 "andps\t{%2, %0|%0, %2}"
18477 [(set_attr "type" "sselog")
18478 (set_attr "mode" "V4SF")])
18480 (define_insn "*sse_andti3_sf_2"
18481 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18482 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18483 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18485 "andps\t{%2, %0|%0, %2}"
18486 [(set_attr "type" "sselog")
18487 (set_attr "mode" "V4SF")])
18489 (define_insn "sse_andti3"
18490 [(set (match_operand:TI 0 "register_operand" "=x")
18491 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18492 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18493 "TARGET_SSE && !TARGET_SSE2
18494 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18495 "andps\t{%2, %0|%0, %2}"
18496 [(set_attr "type" "sselog")
18497 (set_attr "mode" "V4SF")])
18499 (define_insn "sse2_andti3"
18500 [(set (match_operand:TI 0 "register_operand" "=x")
18501 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18502 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18504 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18505 "pand\t{%2, %0|%0, %2}"
18506 [(set_attr "type" "sselog")
18507 (set_attr "mode" "TI")])
18509 (define_insn "sse2_andv2di3"
18510 [(set (match_operand:V2DI 0 "register_operand" "=x")
18511 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18512 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18514 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18515 "pand\t{%2, %0|%0, %2}"
18516 [(set_attr "type" "sselog")
18517 (set_attr "mode" "TI")])
18519 (define_insn "*sse_nandti3_df"
18520 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18521 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
18522 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18524 "andnpd\t{%2, %0|%0, %2}"
18525 [(set_attr "type" "sselog")
18526 (set_attr "mode" "V2DF")])
18528 (define_insn "*sse_nandti3_sf"
18529 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18530 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
18531 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18533 "andnps\t{%2, %0|%0, %2}"
18534 [(set_attr "type" "sselog")
18535 (set_attr "mode" "V4SF")])
18537 (define_insn "sse_nandti3"
18538 [(set (match_operand:TI 0 "register_operand" "=x")
18539 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18540 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18541 "TARGET_SSE && !TARGET_SSE2"
18542 "andnps\t{%2, %0|%0, %2}"
18543 [(set_attr "type" "sselog")
18544 (set_attr "mode" "V4SF")])
18546 (define_insn "sse2_nandti3"
18547 [(set (match_operand:TI 0 "register_operand" "=x")
18548 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
18549 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18551 "pandn\t{%2, %0|%0, %2}"
18552 [(set_attr "type" "sselog")
18553 (set_attr "mode" "TI")])
18555 (define_insn "sse2_nandv2di3"
18556 [(set (match_operand:V2DI 0 "register_operand" "=x")
18557 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0"))
18558 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18560 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18561 "pandn\t{%2, %0|%0, %2}"
18562 [(set_attr "type" "sselog")
18563 (set_attr "mode" "TI")])
18565 (define_insn "*sse_iorti3_df_1"
18566 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18567 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18568 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18570 "orpd\t{%2, %0|%0, %2}"
18571 [(set_attr "type" "sselog")
18572 (set_attr "mode" "V2DF")])
18574 (define_insn "*sse_iorti3_df_2"
18575 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18576 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18577 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18579 "orpd\t{%2, %0|%0, %2}"
18580 [(set_attr "type" "sselog")
18581 (set_attr "mode" "V2DF")])
18583 (define_insn "*sse_iorti3_sf_1"
18584 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18585 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18586 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18588 "orps\t{%2, %0|%0, %2}"
18589 [(set_attr "type" "sselog")
18590 (set_attr "mode" "V4SF")])
18592 (define_insn "*sse_iorti3_sf_2"
18593 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18594 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18595 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18597 "orps\t{%2, %0|%0, %2}"
18598 [(set_attr "type" "sselog")
18599 (set_attr "mode" "V4SF")])
18601 (define_insn "sse_iorti3"
18602 [(set (match_operand:TI 0 "register_operand" "=x")
18603 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18604 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18605 "TARGET_SSE && !TARGET_SSE2
18606 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18607 "orps\t{%2, %0|%0, %2}"
18608 [(set_attr "type" "sselog")
18609 (set_attr "mode" "V4SF")])
18611 (define_insn "sse2_iorti3"
18612 [(set (match_operand:TI 0 "register_operand" "=x")
18613 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18614 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18616 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18617 "por\t{%2, %0|%0, %2}"
18618 [(set_attr "type" "sselog")
18619 (set_attr "mode" "TI")])
18621 (define_insn "sse2_iorv2di3"
18622 [(set (match_operand:V2DI 0 "register_operand" "=x")
18623 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18624 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18626 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18627 "por\t{%2, %0|%0, %2}"
18628 [(set_attr "type" "sselog")
18629 (set_attr "mode" "TI")])
18631 (define_insn "*sse_xorti3_df_1"
18632 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18633 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
18634 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
18636 "xorpd\t{%2, %0|%0, %2}"
18637 [(set_attr "type" "sselog")
18638 (set_attr "mode" "V2DF")])
18640 (define_insn "*sse_xorti3_df_2"
18641 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
18642 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
18643 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
18645 "xorpd\t{%2, %0|%0, %2}"
18646 [(set_attr "type" "sselog")
18647 (set_attr "mode" "V2DF")])
18649 (define_insn "*sse_xorti3_sf_1"
18650 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18651 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
18652 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
18654 "xorps\t{%2, %0|%0, %2}"
18655 [(set_attr "type" "sselog")
18656 (set_attr "mode" "V4SF")])
18658 (define_insn "*sse_xorti3_sf_2"
18659 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
18660 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
18661 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18663 "xorps\t{%2, %0|%0, %2}"
18664 [(set_attr "type" "sselog")
18665 (set_attr "mode" "V4SF")])
18667 (define_insn "sse_xorti3"
18668 [(set (match_operand:TI 0 "register_operand" "=x")
18669 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18670 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18671 "TARGET_SSE && !TARGET_SSE2
18672 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18673 "xorps\t{%2, %0|%0, %2}"
18674 [(set_attr "type" "sselog")
18675 (set_attr "mode" "V4SF")])
18677 (define_insn "sse2_xorti3"
18678 [(set (match_operand:TI 0 "register_operand" "=x")
18679 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
18680 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
18682 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18683 "pxor\t{%2, %0|%0, %2}"
18684 [(set_attr "type" "sselog")
18685 (set_attr "mode" "TI")])
18687 (define_insn "sse2_xorv2di3"
18688 [(set (match_operand:V2DI 0 "register_operand" "=x")
18689 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
18690 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
18692 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
18693 "pxor\t{%2, %0|%0, %2}"
18694 [(set_attr "type" "sselog")
18695 (set_attr "mode" "TI")])
18697 ;; Use xor, but don't show input operands so they aren't live before
18699 (define_insn "sse_clrv4sf"
18700 [(set (match_operand:V4SF 0 "register_operand" "=x")
18701 (unspec:V4SF [(const_int 0)] UNSPEC_NOP))]
18703 "xorps\t{%0, %0|%0, %0}"
18704 [(set_attr "type" "sselog")
18705 (set_attr "memory" "none")
18706 (set_attr "mode" "V4SF")])
18708 ;; SSE mask-generating compares
18710 (define_insn "maskcmpv4sf3"
18711 [(set (match_operand:V4SI 0 "register_operand" "=x")
18712 (match_operator:V4SI 3 "sse_comparison_operator"
18713 [(match_operand:V4SF 1 "register_operand" "0")
18714 (match_operand:V4SF 2 "register_operand" "x")]))]
18716 "cmp%D3ps\t{%2, %0|%0, %2}"
18717 [(set_attr "type" "ssecmp")
18718 (set_attr "mode" "V4SF")])
18720 (define_insn "maskncmpv4sf3"
18721 [(set (match_operand:V4SI 0 "register_operand" "=x")
18723 (match_operator:V4SI 3 "sse_comparison_operator"
18724 [(match_operand:V4SF 1 "register_operand" "0")
18725 (match_operand:V4SF 2 "register_operand" "x")])))]
18728 if (GET_CODE (operands[3]) == UNORDERED)
18729 return "cmpordps\t{%2, %0|%0, %2}";
18731 return "cmpn%D3ps\t{%2, %0|%0, %2}";
18733 [(set_attr "type" "ssecmp")
18734 (set_attr "mode" "V4SF")])
18736 (define_insn "vmmaskcmpv4sf3"
18737 [(set (match_operand:V4SI 0 "register_operand" "=x")
18739 (match_operator:V4SI 3 "sse_comparison_operator"
18740 [(match_operand:V4SF 1 "register_operand" "0")
18741 (match_operand:V4SF 2 "register_operand" "x")])
18745 "cmp%D3ss\t{%2, %0|%0, %2}"
18746 [(set_attr "type" "ssecmp")
18747 (set_attr "mode" "SF")])
18749 (define_insn "vmmaskncmpv4sf3"
18750 [(set (match_operand:V4SI 0 "register_operand" "=x")
18753 (match_operator:V4SI 3 "sse_comparison_operator"
18754 [(match_operand:V4SF 1 "register_operand" "0")
18755 (match_operand:V4SF 2 "register_operand" "x")]))
18756 (subreg:V4SI (match_dup 1) 0)
18760 if (GET_CODE (operands[3]) == UNORDERED)
18761 return "cmpordss\t{%2, %0|%0, %2}";
18763 return "cmpn%D3ss\t{%2, %0|%0, %2}";
18765 [(set_attr "type" "ssecmp")
18766 (set_attr "mode" "SF")])
18768 (define_insn "sse_comi"
18769 [(set (reg:CCFP 17)
18770 (match_operator:CCFP 2 "sse_comparison_operator"
18772 (match_operand:V4SF 0 "register_operand" "x")
18773 (parallel [(const_int 0)]))
18775 (match_operand:V4SF 1 "register_operand" "x")
18776 (parallel [(const_int 0)]))]))]
18778 "comiss\t{%1, %0|%0, %1}"
18779 [(set_attr "type" "ssecmp")
18780 (set_attr "mode" "SF")])
18782 (define_insn "sse_ucomi"
18783 [(set (reg:CCFPU 17)
18784 (match_operator:CCFPU 2 "sse_comparison_operator"
18786 (match_operand:V4SF 0 "register_operand" "x")
18787 (parallel [(const_int 0)]))
18789 (match_operand:V4SF 1 "register_operand" "x")
18790 (parallel [(const_int 0)]))]))]
18792 "ucomiss\t{%1, %0|%0, %1}"
18793 [(set_attr "type" "ssecmp")
18794 (set_attr "mode" "SF")])
18799 (define_insn "sse_unpckhps"
18800 [(set (match_operand:V4SF 0 "register_operand" "=x")
18802 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18803 (parallel [(const_int 2)
18807 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18808 (parallel [(const_int 0)
18814 "unpckhps\t{%2, %0|%0, %2}"
18815 [(set_attr "type" "ssecvt")
18816 (set_attr "mode" "V4SF")])
18818 (define_insn "sse_unpcklps"
18819 [(set (match_operand:V4SF 0 "register_operand" "=x")
18821 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
18822 (parallel [(const_int 0)
18826 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
18827 (parallel [(const_int 2)
18833 "unpcklps\t{%2, %0|%0, %2}"
18834 [(set_attr "type" "ssecvt")
18835 (set_attr "mode" "V4SF")])
18840 (define_insn "smaxv4sf3"
18841 [(set (match_operand:V4SF 0 "register_operand" "=x")
18842 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18843 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18845 "maxps\t{%2, %0|%0, %2}"
18846 [(set_attr "type" "sse")
18847 (set_attr "mode" "V4SF")])
18849 (define_insn "vmsmaxv4sf3"
18850 [(set (match_operand:V4SF 0 "register_operand" "=x")
18852 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
18853 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18857 "maxss\t{%2, %0|%0, %2}"
18858 [(set_attr "type" "sse")
18859 (set_attr "mode" "SF")])
18861 (define_insn "sminv4sf3"
18862 [(set (match_operand:V4SF 0 "register_operand" "=x")
18863 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18864 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
18866 "minps\t{%2, %0|%0, %2}"
18867 [(set_attr "type" "sse")
18868 (set_attr "mode" "V4SF")])
18870 (define_insn "vmsminv4sf3"
18871 [(set (match_operand:V4SF 0 "register_operand" "=x")
18873 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
18874 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
18878 "minss\t{%2, %0|%0, %2}"
18879 [(set_attr "type" "sse")
18880 (set_attr "mode" "SF")])
18883 ;; SSE <-> integer/MMX conversions
18885 (define_insn "cvtpi2ps"
18886 [(set (match_operand:V4SF 0 "register_operand" "=x")
18888 (match_operand:V4SF 1 "register_operand" "0")
18889 (vec_duplicate:V4SF
18890 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
18893 "cvtpi2ps\t{%2, %0|%0, %2}"
18894 [(set_attr "type" "ssecvt")
18895 (set_attr "mode" "V4SF")])
18897 (define_insn "cvtps2pi"
18898 [(set (match_operand:V2SI 0 "register_operand" "=y")
18900 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18901 (parallel [(const_int 0) (const_int 1)])))]
18903 "cvtps2pi\t{%1, %0|%0, %1}"
18904 [(set_attr "type" "ssecvt")
18905 (set_attr "mode" "V4SF")])
18907 (define_insn "cvttps2pi"
18908 [(set (match_operand:V2SI 0 "register_operand" "=y")
18910 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18912 (parallel [(const_int 0) (const_int 1)])))]
18914 "cvttps2pi\t{%1, %0|%0, %1}"
18915 [(set_attr "type" "ssecvt")
18916 (set_attr "mode" "SF")])
18918 (define_insn "cvtsi2ss"
18919 [(set (match_operand:V4SF 0 "register_operand" "=x")
18921 (match_operand:V4SF 1 "register_operand" "0")
18922 (vec_duplicate:V4SF
18923 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm")))
18926 "cvtsi2ss\t{%2, %0|%0, %2}"
18927 [(set_attr "type" "ssecvt")
18928 (set_attr "mode" "SF")])
18930 (define_insn "cvtss2si"
18931 [(set (match_operand:SI 0 "register_operand" "=r")
18933 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
18934 (parallel [(const_int 0)])))]
18936 "cvtss2si\t{%1, %0|%0, %1}"
18937 [(set_attr "type" "ssecvt")
18938 (set_attr "mode" "SF")])
18940 (define_insn "cvttss2si"
18941 [(set (match_operand:SI 0 "register_operand" "=r")
18943 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
18945 (parallel [(const_int 0)])))]
18947 "cvttss2si\t{%1, %0|%0, %1}"
18948 [(set_attr "type" "ssecvt")
18949 (set_attr "mode" "SF")])
18956 (define_insn "addv8qi3"
18957 [(set (match_operand:V8QI 0 "register_operand" "=y")
18958 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18959 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18961 "paddb\t{%2, %0|%0, %2}"
18962 [(set_attr "type" "mmxadd")
18963 (set_attr "mode" "DI")])
18965 (define_insn "addv4hi3"
18966 [(set (match_operand:V4HI 0 "register_operand" "=y")
18967 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18968 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18970 "paddw\t{%2, %0|%0, %2}"
18971 [(set_attr "type" "mmxadd")
18972 (set_attr "mode" "DI")])
18974 (define_insn "addv2si3"
18975 [(set (match_operand:V2SI 0 "register_operand" "=y")
18976 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
18977 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
18979 "paddd\t{%2, %0|%0, %2}"
18980 [(set_attr "type" "mmxadd")
18981 (set_attr "mode" "DI")])
18983 (define_insn "ssaddv8qi3"
18984 [(set (match_operand:V8QI 0 "register_operand" "=y")
18985 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
18986 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
18988 "paddsb\t{%2, %0|%0, %2}"
18989 [(set_attr "type" "mmxadd")
18990 (set_attr "mode" "DI")])
18992 (define_insn "ssaddv4hi3"
18993 [(set (match_operand:V4HI 0 "register_operand" "=y")
18994 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
18995 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
18997 "paddsw\t{%2, %0|%0, %2}"
18998 [(set_attr "type" "mmxadd")
18999 (set_attr "mode" "DI")])
19001 (define_insn "usaddv8qi3"
19002 [(set (match_operand:V8QI 0 "register_operand" "=y")
19003 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19004 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19006 "paddusb\t{%2, %0|%0, %2}"
19007 [(set_attr "type" "mmxadd")
19008 (set_attr "mode" "DI")])
19010 (define_insn "usaddv4hi3"
19011 [(set (match_operand:V4HI 0 "register_operand" "=y")
19012 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19013 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19015 "paddusw\t{%2, %0|%0, %2}"
19016 [(set_attr "type" "mmxadd")
19017 (set_attr "mode" "DI")])
19019 (define_insn "subv8qi3"
19020 [(set (match_operand:V8QI 0 "register_operand" "=y")
19021 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19022 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19024 "psubb\t{%2, %0|%0, %2}"
19025 [(set_attr "type" "mmxadd")
19026 (set_attr "mode" "DI")])
19028 (define_insn "subv4hi3"
19029 [(set (match_operand:V4HI 0 "register_operand" "=y")
19030 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19031 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19033 "psubw\t{%2, %0|%0, %2}"
19034 [(set_attr "type" "mmxadd")
19035 (set_attr "mode" "DI")])
19037 (define_insn "subv2si3"
19038 [(set (match_operand:V2SI 0 "register_operand" "=y")
19039 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
19040 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19042 "psubd\t{%2, %0|%0, %2}"
19043 [(set_attr "type" "mmxadd")
19044 (set_attr "mode" "DI")])
19046 (define_insn "sssubv8qi3"
19047 [(set (match_operand:V8QI 0 "register_operand" "=y")
19048 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19049 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19051 "psubsb\t{%2, %0|%0, %2}"
19052 [(set_attr "type" "mmxadd")
19053 (set_attr "mode" "DI")])
19055 (define_insn "sssubv4hi3"
19056 [(set (match_operand:V4HI 0 "register_operand" "=y")
19057 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19058 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19060 "psubsw\t{%2, %0|%0, %2}"
19061 [(set_attr "type" "mmxadd")
19062 (set_attr "mode" "DI")])
19064 (define_insn "ussubv8qi3"
19065 [(set (match_operand:V8QI 0 "register_operand" "=y")
19066 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
19067 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19069 "psubusb\t{%2, %0|%0, %2}"
19070 [(set_attr "type" "mmxadd")
19071 (set_attr "mode" "DI")])
19073 (define_insn "ussubv4hi3"
19074 [(set (match_operand:V4HI 0 "register_operand" "=y")
19075 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
19076 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19078 "psubusw\t{%2, %0|%0, %2}"
19079 [(set_attr "type" "mmxadd")
19080 (set_attr "mode" "DI")])
19082 (define_insn "mulv4hi3"
19083 [(set (match_operand:V4HI 0 "register_operand" "=y")
19084 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
19085 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19087 "pmullw\t{%2, %0|%0, %2}"
19088 [(set_attr "type" "mmxmul")
19089 (set_attr "mode" "DI")])
19091 (define_insn "smulv4hi3_highpart"
19092 [(set (match_operand:V4HI 0 "register_operand" "=y")
19095 (mult:V4SI (sign_extend:V4SI
19096 (match_operand:V4HI 1 "register_operand" "0"))
19098 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19101 "pmulhw\t{%2, %0|%0, %2}"
19102 [(set_attr "type" "mmxmul")
19103 (set_attr "mode" "DI")])
19105 (define_insn "umulv4hi3_highpart"
19106 [(set (match_operand:V4HI 0 "register_operand" "=y")
19109 (mult:V4SI (zero_extend:V4SI
19110 (match_operand:V4HI 1 "register_operand" "0"))
19112 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
19114 "TARGET_SSE || TARGET_3DNOW_A"
19115 "pmulhuw\t{%2, %0|%0, %2}"
19116 [(set_attr "type" "mmxmul")
19117 (set_attr "mode" "DI")])
19119 (define_insn "mmx_pmaddwd"
19120 [(set (match_operand:V2SI 0 "register_operand" "=y")
19124 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
19125 (parallel [(const_int 0) (const_int 2)])))
19127 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
19128 (parallel [(const_int 0) (const_int 2)]))))
19130 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
19131 (parallel [(const_int 1)
19133 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
19134 (parallel [(const_int 1)
19135 (const_int 3)]))))))]
19137 "pmaddwd\t{%2, %0|%0, %2}"
19138 [(set_attr "type" "mmxmul")
19139 (set_attr "mode" "DI")])
19142 ;; MMX logical operations
19143 ;; Note we don't want to declare these as regular iordi3 insns to prevent
19144 ;; normal code that also wants to use the FPU from getting broken.
19145 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
19146 (define_insn "mmx_iordi3"
19147 [(set (match_operand:DI 0 "register_operand" "=y")
19149 [(ior:DI (match_operand:DI 1 "register_operand" "0")
19150 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19153 "por\t{%2, %0|%0, %2}"
19154 [(set_attr "type" "mmxadd")
19155 (set_attr "mode" "DI")])
19157 (define_insn "mmx_xordi3"
19158 [(set (match_operand:DI 0 "register_operand" "=y")
19160 [(xor:DI (match_operand:DI 1 "register_operand" "0")
19161 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19164 "pxor\t{%2, %0|%0, %2}"
19165 [(set_attr "type" "mmxadd")
19166 (set_attr "mode" "DI")
19167 (set_attr "memory" "none")])
19169 ;; Same as pxor, but don't show input operands so that we don't think
19171 (define_insn "mmx_clrdi"
19172 [(set (match_operand:DI 0 "register_operand" "=y")
19173 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
19175 "pxor\t{%0, %0|%0, %0}"
19176 [(set_attr "type" "mmxadd")
19177 (set_attr "mode" "DI")
19178 (set_attr "memory" "none")])
19180 (define_insn "mmx_anddi3"
19181 [(set (match_operand:DI 0 "register_operand" "=y")
19183 [(and:DI (match_operand:DI 1 "register_operand" "0")
19184 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19187 "pand\t{%2, %0|%0, %2}"
19188 [(set_attr "type" "mmxadd")
19189 (set_attr "mode" "DI")])
19191 (define_insn "mmx_nanddi3"
19192 [(set (match_operand:DI 0 "register_operand" "=y")
19194 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
19195 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
19198 "pandn\t{%2, %0|%0, %2}"
19199 [(set_attr "type" "mmxadd")
19200 (set_attr "mode" "DI")])
19203 ;; MMX unsigned averages/sum of absolute differences
19205 (define_insn "mmx_uavgv8qi3"
19206 [(set (match_operand:V8QI 0 "register_operand" "=y")
19208 (plus:V8QI (plus:V8QI
19209 (match_operand:V8QI 1 "register_operand" "0")
19210 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
19211 (const_vector:V8QI [(const_int 1)
19220 "TARGET_SSE || TARGET_3DNOW_A"
19221 "pavgb\t{%2, %0|%0, %2}"
19222 [(set_attr "type" "mmxshft")
19223 (set_attr "mode" "DI")])
19225 (define_insn "mmx_uavgv4hi3"
19226 [(set (match_operand:V4HI 0 "register_operand" "=y")
19228 (plus:V4HI (plus:V4HI
19229 (match_operand:V4HI 1 "register_operand" "0")
19230 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
19231 (const_vector:V4HI [(const_int 1)
19236 "TARGET_SSE || TARGET_3DNOW_A"
19237 "pavgw\t{%2, %0|%0, %2}"
19238 [(set_attr "type" "mmxshft")
19239 (set_attr "mode" "DI")])
19241 (define_insn "mmx_psadbw"
19242 [(set (match_operand:DI 0 "register_operand" "=y")
19243 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
19244 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
19246 "TARGET_SSE || TARGET_3DNOW_A"
19247 "psadbw\t{%2, %0|%0, %2}"
19248 [(set_attr "type" "mmxshft")
19249 (set_attr "mode" "DI")])
19252 ;; MMX insert/extract/shuffle
19254 (define_insn "mmx_pinsrw"
19255 [(set (match_operand:V4HI 0 "register_operand" "=y")
19256 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
19257 (vec_duplicate:V4HI
19258 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
19259 (match_operand:SI 3 "immediate_operand" "i")))]
19260 "TARGET_SSE || TARGET_3DNOW_A"
19261 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
19262 [(set_attr "type" "mmxcvt")
19263 (set_attr "mode" "DI")])
19265 (define_insn "mmx_pextrw"
19266 [(set (match_operand:SI 0 "register_operand" "=r")
19267 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
19269 [(match_operand:SI 2 "immediate_operand" "i")]))))]
19270 "TARGET_SSE || TARGET_3DNOW_A"
19271 "pextrw\t{%2, %1, %0|%0, %1, %2}"
19272 [(set_attr "type" "mmxcvt")
19273 (set_attr "mode" "DI")])
19275 (define_insn "mmx_pshufw"
19276 [(set (match_operand:V4HI 0 "register_operand" "=y")
19277 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
19278 (match_operand:SI 2 "immediate_operand" "i")]
19280 "TARGET_SSE || TARGET_3DNOW_A"
19281 "pshufw\t{%2, %1, %0|%0, %1, %2}"
19282 [(set_attr "type" "mmxcvt")
19283 (set_attr "mode" "DI")])
19286 ;; MMX mask-generating comparisons
19288 (define_insn "eqv8qi3"
19289 [(set (match_operand:V8QI 0 "register_operand" "=y")
19290 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
19291 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19293 "pcmpeqb\t{%2, %0|%0, %2}"
19294 [(set_attr "type" "mmxcmp")
19295 (set_attr "mode" "DI")])
19297 (define_insn "eqv4hi3"
19298 [(set (match_operand:V4HI 0 "register_operand" "=y")
19299 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
19300 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19302 "pcmpeqw\t{%2, %0|%0, %2}"
19303 [(set_attr "type" "mmxcmp")
19304 (set_attr "mode" "DI")])
19306 (define_insn "eqv2si3"
19307 [(set (match_operand:V2SI 0 "register_operand" "=y")
19308 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
19309 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19311 "pcmpeqd\t{%2, %0|%0, %2}"
19312 [(set_attr "type" "mmxcmp")
19313 (set_attr "mode" "DI")])
19315 (define_insn "gtv8qi3"
19316 [(set (match_operand:V8QI 0 "register_operand" "=y")
19317 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
19318 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19320 "pcmpgtb\t{%2, %0|%0, %2}"
19321 [(set_attr "type" "mmxcmp")
19322 (set_attr "mode" "DI")])
19324 (define_insn "gtv4hi3"
19325 [(set (match_operand:V4HI 0 "register_operand" "=y")
19326 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19327 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19329 "pcmpgtw\t{%2, %0|%0, %2}"
19330 [(set_attr "type" "mmxcmp")
19331 (set_attr "mode" "DI")])
19333 (define_insn "gtv2si3"
19334 [(set (match_operand:V2SI 0 "register_operand" "=y")
19335 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19336 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
19338 "pcmpgtd\t{%2, %0|%0, %2}"
19339 [(set_attr "type" "mmxcmp")
19340 (set_attr "mode" "DI")])
19343 ;; MMX max/min insns
19345 (define_insn "umaxv8qi3"
19346 [(set (match_operand:V8QI 0 "register_operand" "=y")
19347 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
19348 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19349 "TARGET_SSE || TARGET_3DNOW_A"
19350 "pmaxub\t{%2, %0|%0, %2}"
19351 [(set_attr "type" "mmxadd")
19352 (set_attr "mode" "DI")])
19354 (define_insn "smaxv4hi3"
19355 [(set (match_operand:V4HI 0 "register_operand" "=y")
19356 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
19357 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19358 "TARGET_SSE || TARGET_3DNOW_A"
19359 "pmaxsw\t{%2, %0|%0, %2}"
19360 [(set_attr "type" "mmxadd")
19361 (set_attr "mode" "DI")])
19363 (define_insn "uminv8qi3"
19364 [(set (match_operand:V8QI 0 "register_operand" "=y")
19365 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
19366 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
19367 "TARGET_SSE || TARGET_3DNOW_A"
19368 "pminub\t{%2, %0|%0, %2}"
19369 [(set_attr "type" "mmxadd")
19370 (set_attr "mode" "DI")])
19372 (define_insn "sminv4hi3"
19373 [(set (match_operand:V4HI 0 "register_operand" "=y")
19374 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
19375 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
19376 "TARGET_SSE || TARGET_3DNOW_A"
19377 "pminsw\t{%2, %0|%0, %2}"
19378 [(set_attr "type" "mmxadd")
19379 (set_attr "mode" "DI")])
19384 (define_insn "ashrv4hi3"
19385 [(set (match_operand:V4HI 0 "register_operand" "=y")
19386 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19387 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19389 "psraw\t{%2, %0|%0, %2}"
19390 [(set_attr "type" "mmxshft")
19391 (set_attr "mode" "DI")])
19393 (define_insn "ashrv2si3"
19394 [(set (match_operand:V2SI 0 "register_operand" "=y")
19395 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19396 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19398 "psrad\t{%2, %0|%0, %2}"
19399 [(set_attr "type" "mmxshft")
19400 (set_attr "mode" "DI")])
19402 (define_insn "lshrv4hi3"
19403 [(set (match_operand:V4HI 0 "register_operand" "=y")
19404 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
19405 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19407 "psrlw\t{%2, %0|%0, %2}"
19408 [(set_attr "type" "mmxshft")
19409 (set_attr "mode" "DI")])
19411 (define_insn "lshrv2si3"
19412 [(set (match_operand:V2SI 0 "register_operand" "=y")
19413 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
19414 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19416 "psrld\t{%2, %0|%0, %2}"
19417 [(set_attr "type" "mmxshft")
19418 (set_attr "mode" "DI")])
19420 ;; See logical MMX insns.
19421 (define_insn "mmx_lshrdi3"
19422 [(set (match_operand:DI 0 "register_operand" "=y")
19424 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
19425 (match_operand:DI 2 "nonmemory_operand" "yi"))]
19428 "psrlq\t{%2, %0|%0, %2}"
19429 [(set_attr "type" "mmxshft")
19430 (set_attr "mode" "DI")])
19432 (define_insn "ashlv4hi3"
19433 [(set (match_operand:V4HI 0 "register_operand" "=y")
19434 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
19435 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19437 "psllw\t{%2, %0|%0, %2}"
19438 [(set_attr "type" "mmxshft")
19439 (set_attr "mode" "DI")])
19441 (define_insn "ashlv2si3"
19442 [(set (match_operand:V2SI 0 "register_operand" "=y")
19443 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
19444 (match_operand:DI 2 "nonmemory_operand" "yi")))]
19446 "pslld\t{%2, %0|%0, %2}"
19447 [(set_attr "type" "mmxshft")
19448 (set_attr "mode" "DI")])
19450 ;; See logical MMX insns.
19451 (define_insn "mmx_ashldi3"
19452 [(set (match_operand:DI 0 "register_operand" "=y")
19454 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
19455 (match_operand:DI 2 "nonmemory_operand" "yi"))]
19458 "psllq\t{%2, %0|%0, %2}"
19459 [(set_attr "type" "mmxshft")
19460 (set_attr "mode" "DI")])
19463 ;; MMX pack/unpack insns.
19465 (define_insn "mmx_packsswb"
19466 [(set (match_operand:V8QI 0 "register_operand" "=y")
19468 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19469 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19471 "packsswb\t{%2, %0|%0, %2}"
19472 [(set_attr "type" "mmxshft")
19473 (set_attr "mode" "DI")])
19475 (define_insn "mmx_packssdw"
19476 [(set (match_operand:V4HI 0 "register_operand" "=y")
19478 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
19479 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
19481 "packssdw\t{%2, %0|%0, %2}"
19482 [(set_attr "type" "mmxshft")
19483 (set_attr "mode" "DI")])
19485 (define_insn "mmx_packuswb"
19486 [(set (match_operand:V8QI 0 "register_operand" "=y")
19488 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
19489 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
19491 "packuswb\t{%2, %0|%0, %2}"
19492 [(set_attr "type" "mmxshft")
19493 (set_attr "mode" "DI")])
19495 (define_insn "mmx_punpckhbw"
19496 [(set (match_operand:V8QI 0 "register_operand" "=y")
19498 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19499 (parallel [(const_int 4)
19507 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19508 (parallel [(const_int 0)
19518 "punpckhbw\t{%2, %0|%0, %2}"
19519 [(set_attr "type" "mmxcvt")
19520 (set_attr "mode" "DI")])
19522 (define_insn "mmx_punpckhwd"
19523 [(set (match_operand:V4HI 0 "register_operand" "=y")
19525 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19526 (parallel [(const_int 0)
19530 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19531 (parallel [(const_int 2)
19537 "punpckhwd\t{%2, %0|%0, %2}"
19538 [(set_attr "type" "mmxcvt")
19539 (set_attr "mode" "DI")])
19541 (define_insn "mmx_punpckhdq"
19542 [(set (match_operand:V2SI 0 "register_operand" "=y")
19544 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19545 (parallel [(const_int 0)
19547 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19548 (parallel [(const_int 1)
19552 "punpckhdq\t{%2, %0|%0, %2}"
19553 [(set_attr "type" "mmxcvt")
19554 (set_attr "mode" "DI")])
19556 (define_insn "mmx_punpcklbw"
19557 [(set (match_operand:V8QI 0 "register_operand" "=y")
19559 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
19560 (parallel [(const_int 0)
19568 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
19569 (parallel [(const_int 4)
19579 "punpcklbw\t{%2, %0|%0, %2}"
19580 [(set_attr "type" "mmxcvt")
19581 (set_attr "mode" "DI")])
19583 (define_insn "mmx_punpcklwd"
19584 [(set (match_operand:V4HI 0 "register_operand" "=y")
19586 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
19587 (parallel [(const_int 2)
19591 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
19592 (parallel [(const_int 0)
19598 "punpcklwd\t{%2, %0|%0, %2}"
19599 [(set_attr "type" "mmxcvt")
19600 (set_attr "mode" "DI")])
19602 (define_insn "mmx_punpckldq"
19603 [(set (match_operand:V2SI 0 "register_operand" "=y")
19605 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
19606 (parallel [(const_int 1)
19608 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
19609 (parallel [(const_int 0)
19613 "punpckldq\t{%2, %0|%0, %2}"
19614 [(set_attr "type" "mmxcvt")
19615 (set_attr "mode" "DI")])
19618 ;; Miscellaneous stuff
19620 (define_insn "emms"
19621 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
19622 (clobber (reg:XF 8))
19623 (clobber (reg:XF 9))
19624 (clobber (reg:XF 10))
19625 (clobber (reg:XF 11))
19626 (clobber (reg:XF 12))
19627 (clobber (reg:XF 13))
19628 (clobber (reg:XF 14))
19629 (clobber (reg:XF 15))
19630 (clobber (reg:DI 29))
19631 (clobber (reg:DI 30))
19632 (clobber (reg:DI 31))
19633 (clobber (reg:DI 32))
19634 (clobber (reg:DI 33))
19635 (clobber (reg:DI 34))
19636 (clobber (reg:DI 35))
19637 (clobber (reg:DI 36))]
19640 [(set_attr "type" "mmx")
19641 (set_attr "memory" "unknown")])
19643 (define_insn "ldmxcsr"
19644 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
19648 [(set_attr "type" "mmx")
19649 (set_attr "memory" "load")])
19651 (define_insn "stmxcsr"
19652 [(set (match_operand:SI 0 "memory_operand" "=m")
19653 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
19656 [(set_attr "type" "mmx")
19657 (set_attr "memory" "store")])
19659 (define_expand "sfence"
19660 [(set (match_dup 0)
19661 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
19662 "TARGET_SSE || TARGET_3DNOW_A"
19664 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
19665 MEM_VOLATILE_P (operands[0]) = 1;
19668 (define_insn "*sfence_insn"
19669 [(set (match_operand:BLK 0 "" "")
19670 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
19671 "TARGET_SSE || TARGET_3DNOW_A"
19673 [(set_attr "type" "sse")
19674 (set_attr "memory" "unknown")])
19676 (define_expand "sse_prologue_save"
19677 [(parallel [(set (match_operand:BLK 0 "" "")
19678 (unspec:BLK [(reg:DI 21)
19685 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
19686 (use (match_operand:DI 1 "register_operand" ""))
19687 (use (match_operand:DI 2 "immediate_operand" ""))
19688 (use (label_ref:DI (match_operand 3 "" "")))])]
19692 (define_insn "*sse_prologue_save_insn"
19693 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
19694 (match_operand:DI 4 "const_int_operand" "n")))
19695 (unspec:BLK [(reg:DI 21)
19702 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
19703 (use (match_operand:DI 1 "register_operand" "r"))
19704 (use (match_operand:DI 2 "const_int_operand" "i"))
19705 (use (label_ref:DI (match_operand 3 "" "X")))]
19707 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
19708 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
19712 operands[0] = gen_rtx_MEM (Pmode,
19713 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
19714 output_asm_insn (\"jmp\\t%A1\", operands);
19715 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
19717 operands[4] = adjust_address (operands[0], DImode, i*16);
19718 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
19719 PUT_MODE (operands[4], TImode);
19720 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
19721 output_asm_insn (\"rex\", operands);
19722 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
19724 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
19725 CODE_LABEL_NUMBER (operands[3]));
19729 [(set_attr "type" "other")
19730 (set_attr "length_immediate" "0")
19731 (set_attr "length_address" "0")
19732 (set_attr "length" "135")
19733 (set_attr "memory" "store")
19734 (set_attr "modrm" "0")
19735 (set_attr "mode" "DI")])
19737 ;; 3Dnow! instructions
19739 (define_insn "addv2sf3"
19740 [(set (match_operand:V2SF 0 "register_operand" "=y")
19741 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
19742 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19744 "pfadd\\t{%2, %0|%0, %2}"
19745 [(set_attr "type" "mmxadd")
19746 (set_attr "mode" "V2SF")])
19748 (define_insn "subv2sf3"
19749 [(set (match_operand:V2SF 0 "register_operand" "=y")
19750 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
19751 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19753 "pfsub\\t{%2, %0|%0, %2}"
19754 [(set_attr "type" "mmxadd")
19755 (set_attr "mode" "V2SF")])
19757 (define_insn "subrv2sf3"
19758 [(set (match_operand:V2SF 0 "register_operand" "=y")
19759 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
19760 (match_operand:V2SF 1 "register_operand" "0")))]
19762 "pfsubr\\t{%2, %0|%0, %2}"
19763 [(set_attr "type" "mmxadd")
19764 (set_attr "mode" "V2SF")])
19766 (define_insn "gtv2sf3"
19767 [(set (match_operand:V2SI 0 "register_operand" "=y")
19768 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
19769 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19771 "pfcmpgt\\t{%2, %0|%0, %2}"
19772 [(set_attr "type" "mmxcmp")
19773 (set_attr "mode" "V2SF")])
19775 (define_insn "gev2sf3"
19776 [(set (match_operand:V2SI 0 "register_operand" "=y")
19777 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
19778 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19780 "pfcmpge\\t{%2, %0|%0, %2}"
19781 [(set_attr "type" "mmxcmp")
19782 (set_attr "mode" "V2SF")])
19784 (define_insn "eqv2sf3"
19785 [(set (match_operand:V2SI 0 "register_operand" "=y")
19786 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
19787 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19789 "pfcmpeq\\t{%2, %0|%0, %2}"
19790 [(set_attr "type" "mmxcmp")
19791 (set_attr "mode" "V2SF")])
19793 (define_insn "pfmaxv2sf3"
19794 [(set (match_operand:V2SF 0 "register_operand" "=y")
19795 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
19796 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19798 "pfmax\\t{%2, %0|%0, %2}"
19799 [(set_attr "type" "mmxadd")
19800 (set_attr "mode" "V2SF")])
19802 (define_insn "pfminv2sf3"
19803 [(set (match_operand:V2SF 0 "register_operand" "=y")
19804 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
19805 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19807 "pfmin\\t{%2, %0|%0, %2}"
19808 [(set_attr "type" "mmxadd")
19809 (set_attr "mode" "V2SF")])
19811 (define_insn "mulv2sf3"
19812 [(set (match_operand:V2SF 0 "register_operand" "=y")
19813 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
19814 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
19816 "pfmul\\t{%2, %0|%0, %2}"
19817 [(set_attr "type" "mmxmul")
19818 (set_attr "mode" "V2SF")])
19820 (define_insn "femms"
19821 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
19822 (clobber (reg:XF 8))
19823 (clobber (reg:XF 9))
19824 (clobber (reg:XF 10))
19825 (clobber (reg:XF 11))
19826 (clobber (reg:XF 12))
19827 (clobber (reg:XF 13))
19828 (clobber (reg:XF 14))
19829 (clobber (reg:XF 15))
19830 (clobber (reg:DI 29))
19831 (clobber (reg:DI 30))
19832 (clobber (reg:DI 31))
19833 (clobber (reg:DI 32))
19834 (clobber (reg:DI 33))
19835 (clobber (reg:DI 34))
19836 (clobber (reg:DI 35))
19837 (clobber (reg:DI 36))]
19840 [(set_attr "type" "mmx")
19841 (set_attr "memory" "none")])
19843 (define_insn "pf2id"
19844 [(set (match_operand:V2SI 0 "register_operand" "=y")
19845 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
19847 "pf2id\\t{%1, %0|%0, %1}"
19848 [(set_attr "type" "mmxcvt")
19849 (set_attr "mode" "V2SF")])
19851 (define_insn "pf2iw"
19852 [(set (match_operand:V2SI 0 "register_operand" "=y")
19855 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
19857 "pf2iw\\t{%1, %0|%0, %1}"
19858 [(set_attr "type" "mmxcvt")
19859 (set_attr "mode" "V2SF")])
19861 (define_insn "pfacc"
19862 [(set (match_operand:V2SF 0 "register_operand" "=y")
19865 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19866 (parallel [(const_int 0)]))
19867 (vec_select:SF (match_dup 1)
19868 (parallel [(const_int 1)])))
19870 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19871 (parallel [(const_int 0)]))
19872 (vec_select:SF (match_dup 2)
19873 (parallel [(const_int 1)])))))]
19875 "pfacc\\t{%2, %0|%0, %2}"
19876 [(set_attr "type" "mmxadd")
19877 (set_attr "mode" "V2SF")])
19879 (define_insn "pfnacc"
19880 [(set (match_operand:V2SF 0 "register_operand" "=y")
19883 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19884 (parallel [(const_int 0)]))
19885 (vec_select:SF (match_dup 1)
19886 (parallel [(const_int 1)])))
19888 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19889 (parallel [(const_int 0)]))
19890 (vec_select:SF (match_dup 2)
19891 (parallel [(const_int 1)])))))]
19893 "pfnacc\\t{%2, %0|%0, %2}"
19894 [(set_attr "type" "mmxadd")
19895 (set_attr "mode" "V2SF")])
19897 (define_insn "pfpnacc"
19898 [(set (match_operand:V2SF 0 "register_operand" "=y")
19901 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
19902 (parallel [(const_int 0)]))
19903 (vec_select:SF (match_dup 1)
19904 (parallel [(const_int 1)])))
19906 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
19907 (parallel [(const_int 0)]))
19908 (vec_select:SF (match_dup 2)
19909 (parallel [(const_int 1)])))))]
19911 "pfpnacc\\t{%2, %0|%0, %2}"
19912 [(set_attr "type" "mmxadd")
19913 (set_attr "mode" "V2SF")])
19915 (define_insn "pi2fw"
19916 [(set (match_operand:V2SF 0 "register_operand" "=y")
19921 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
19922 (parallel [(const_int 0)]))))
19925 (vec_select:SI (match_dup 1)
19926 (parallel [(const_int 1)])))))))]
19928 "pi2fw\\t{%1, %0|%0, %1}"
19929 [(set_attr "type" "mmxcvt")
19930 (set_attr "mode" "V2SF")])
19932 (define_insn "floatv2si2"
19933 [(set (match_operand:V2SF 0 "register_operand" "=y")
19934 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
19936 "pi2fd\\t{%1, %0|%0, %1}"
19937 [(set_attr "type" "mmxcvt")
19938 (set_attr "mode" "V2SF")])
19940 ;; This insn is identical to pavgb in operation, but the opcode is
19941 ;; different. To avoid accidentally matching pavgb, use an unspec.
19943 (define_insn "pavgusb"
19944 [(set (match_operand:V8QI 0 "register_operand" "=y")
19946 [(match_operand:V8QI 1 "register_operand" "0")
19947 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
19950 "pavgusb\\t{%2, %0|%0, %2}"
19951 [(set_attr "type" "mmxshft")
19952 (set_attr "mode" "TI")])
19954 ;; 3DNow reciprical and sqrt
19956 (define_insn "pfrcpv2sf2"
19957 [(set (match_operand:V2SF 0 "register_operand" "=y")
19958 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
19961 "pfrcp\\t{%1, %0|%0, %1}"
19962 [(set_attr "type" "mmx")
19963 (set_attr "mode" "TI")])
19965 (define_insn "pfrcpit1v2sf3"
19966 [(set (match_operand:V2SF 0 "register_operand" "=y")
19967 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19968 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
19971 "pfrcpit1\\t{%2, %0|%0, %2}"
19972 [(set_attr "type" "mmx")
19973 (set_attr "mode" "TI")])
19975 (define_insn "pfrcpit2v2sf3"
19976 [(set (match_operand:V2SF 0 "register_operand" "=y")
19977 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19978 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
19981 "pfrcpit2\\t{%2, %0|%0, %2}"
19982 [(set_attr "type" "mmx")
19983 (set_attr "mode" "TI")])
19985 (define_insn "pfrsqrtv2sf2"
19986 [(set (match_operand:V2SF 0 "register_operand" "=y")
19987 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
19990 "pfrsqrt\\t{%1, %0|%0, %1}"
19991 [(set_attr "type" "mmx")
19992 (set_attr "mode" "TI")])
19994 (define_insn "pfrsqit1v2sf3"
19995 [(set (match_operand:V2SF 0 "register_operand" "=y")
19996 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
19997 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
20000 "pfrsqit1\\t{%2, %0|%0, %2}"
20001 [(set_attr "type" "mmx")
20002 (set_attr "mode" "TI")])
20004 (define_insn "pmulhrwv4hi3"
20005 [(set (match_operand:V4HI 0 "register_operand" "=y")
20011 (match_operand:V4HI 1 "register_operand" "0"))
20013 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20014 (const_vector:V4SI [(const_int 32768)
20017 (const_int 32768)]))
20020 "pmulhrw\\t{%2, %0|%0, %2}"
20021 [(set_attr "type" "mmxmul")
20022 (set_attr "mode" "TI")])
20024 (define_insn "pswapdv2si2"
20025 [(set (match_operand:V2SI 0 "register_operand" "=y")
20026 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
20027 (parallel [(const_int 1) (const_int 0)])))]
20029 "pswapd\\t{%1, %0|%0, %1}"
20030 [(set_attr "type" "mmxcvt")
20031 (set_attr "mode" "TI")])
20033 (define_insn "pswapdv2sf2"
20034 [(set (match_operand:V2SF 0 "register_operand" "=y")
20035 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
20036 (parallel [(const_int 1) (const_int 0)])))]
20038 "pswapd\\t{%1, %0|%0, %1}"
20039 [(set_attr "type" "mmxcvt")
20040 (set_attr "mode" "TI")])
20042 (define_expand "prefetch"
20043 [(prefetch (match_operand 0 "address_operand" "")
20044 (match_operand:SI 1 "const_int_operand" "")
20045 (match_operand:SI 2 "const_int_operand" ""))]
20046 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
20048 int rw = INTVAL (operands[1]);
20049 int locality = INTVAL (operands[2]);
20051 if (rw != 0 && rw != 1)
20053 if (locality < 0 || locality > 3)
20055 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
20058 /* Use 3dNOW prefetch in case we are asking for write prefetch not
20059 suported by SSE counterpart or the SSE prefetch is not available
20060 (K6 machines). Otherwise use SSE prefetch as it allows specifying
20062 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
20063 operands[2] = GEN_INT (3);
20065 operands[1] = const0_rtx;
20068 (define_insn "*prefetch_sse"
20069 [(prefetch (match_operand:SI 0 "address_operand" "p")
20071 (match_operand:SI 1 "const_int_operand" ""))]
20072 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
20074 static const char * const patterns[4] = {
20075 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
20078 int locality = INTVAL (operands[1]);
20079 if (locality < 0 || locality > 3)
20082 return patterns[locality];
20084 [(set_attr "type" "sse")
20085 (set_attr "memory" "none")])
20087 (define_insn "*prefetch_sse_rex"
20088 [(prefetch (match_operand:DI 0 "address_operand" "p")
20090 (match_operand:SI 1 "const_int_operand" ""))]
20091 "TARGET_PREFETCH_SSE && TARGET_64BIT"
20093 static const char * const patterns[4] = {
20094 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
20097 int locality = INTVAL (operands[1]);
20098 if (locality < 0 || locality > 3)
20101 return patterns[locality];
20103 [(set_attr "type" "sse")
20104 (set_attr "memory" "none")])
20106 (define_insn "*prefetch_3dnow"
20107 [(prefetch (match_operand:SI 0 "address_operand" "p")
20108 (match_operand:SI 1 "const_int_operand" "n")
20110 "TARGET_3DNOW && !TARGET_64BIT"
20112 if (INTVAL (operands[1]) == 0)
20113 return "prefetch\t%a0";
20115 return "prefetchw\t%a0";
20117 [(set_attr "type" "mmx")
20118 (set_attr "memory" "none")])
20120 (define_insn "*prefetch_3dnow_rex"
20121 [(prefetch (match_operand:DI 0 "address_operand" "p")
20122 (match_operand:SI 1 "const_int_operand" "n")
20124 "TARGET_3DNOW && TARGET_64BIT"
20126 if (INTVAL (operands[1]) == 0)
20127 return "prefetch\t%a0";
20129 return "prefetchw\t%a0";
20131 [(set_attr "type" "mmx")
20132 (set_attr "memory" "none")])
20136 (define_insn "addv2df3"
20137 [(set (match_operand:V2DF 0 "register_operand" "=x")
20138 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20139 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20141 "addpd\t{%2, %0|%0, %2}"
20142 [(set_attr "type" "sseadd")
20143 (set_attr "mode" "V2DF")])
20145 (define_insn "vmaddv2df3"
20146 [(set (match_operand:V2DF 0 "register_operand" "=x")
20147 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20148 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20152 "addsd\t{%2, %0|%0, %2}"
20153 [(set_attr "type" "sseadd")
20154 (set_attr "mode" "DF")])
20156 (define_insn "subv2df3"
20157 [(set (match_operand:V2DF 0 "register_operand" "=x")
20158 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20159 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20161 "subpd\t{%2, %0|%0, %2}"
20162 [(set_attr "type" "sseadd")
20163 (set_attr "mode" "V2DF")])
20165 (define_insn "vmsubv2df3"
20166 [(set (match_operand:V2DF 0 "register_operand" "=x")
20167 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
20168 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20172 "subsd\t{%2, %0|%0, %2}"
20173 [(set_attr "type" "sseadd")
20174 (set_attr "mode" "DF")])
20176 (define_insn "mulv2df3"
20177 [(set (match_operand:V2DF 0 "register_operand" "=x")
20178 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
20179 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20181 "mulpd\t{%2, %0|%0, %2}"
20182 [(set_attr "type" "ssemul")
20183 (set_attr "mode" "V2DF")])
20185 (define_insn "vmmulv2df3"
20186 [(set (match_operand:V2DF 0 "register_operand" "=x")
20187 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
20188 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20192 "mulsd\t{%2, %0|%0, %2}"
20193 [(set_attr "type" "ssemul")
20194 (set_attr "mode" "DF")])
20196 (define_insn "divv2df3"
20197 [(set (match_operand:V2DF 0 "register_operand" "=x")
20198 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
20199 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20201 "divpd\t{%2, %0|%0, %2}"
20202 [(set_attr "type" "ssediv")
20203 (set_attr "mode" "V2DF")])
20205 (define_insn "vmdivv2df3"
20206 [(set (match_operand:V2DF 0 "register_operand" "=x")
20207 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
20208 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20212 "divsd\t{%2, %0|%0, %2}"
20213 [(set_attr "type" "ssediv")
20214 (set_attr "mode" "DF")])
20218 (define_insn "smaxv2df3"
20219 [(set (match_operand:V2DF 0 "register_operand" "=x")
20220 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
20221 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20223 "maxpd\t{%2, %0|%0, %2}"
20224 [(set_attr "type" "sseadd")
20225 (set_attr "mode" "V2DF")])
20227 (define_insn "vmsmaxv2df3"
20228 [(set (match_operand:V2DF 0 "register_operand" "=x")
20229 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
20230 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20234 "maxsd\t{%2, %0|%0, %2}"
20235 [(set_attr "type" "sseadd")
20236 (set_attr "mode" "DF")])
20238 (define_insn "sminv2df3"
20239 [(set (match_operand:V2DF 0 "register_operand" "=x")
20240 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
20241 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20243 "minpd\t{%2, %0|%0, %2}"
20244 [(set_attr "type" "sseadd")
20245 (set_attr "mode" "V2DF")])
20247 (define_insn "vmsminv2df3"
20248 [(set (match_operand:V2DF 0 "register_operand" "=x")
20249 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
20250 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
20254 "minsd\t{%2, %0|%0, %2}"
20255 [(set_attr "type" "sseadd")
20256 (set_attr "mode" "DF")])
20258 (define_insn "sse2_anddf3"
20259 [(set (match_operand:V2DF 0 "register_operand" "=x")
20260 (subreg:V2DF (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
20261 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
20263 "andpd\t{%2, %0|%0, %2}"
20264 [(set_attr "type" "sselog")
20265 (set_attr "mode" "V2DF")])
20267 (define_insn "sse2_nanddf3"
20268 [(set (match_operand:V2DF 0 "register_operand" "=x")
20269 (subreg:V2DF (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "0") 0))
20270 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
20272 "andnpd\t{%2, %0|%0, %2}"
20273 [(set_attr "type" "sselog")
20274 (set_attr "mode" "V2DF")])
20276 (define_insn "sse2_iordf3"
20277 [(set (match_operand:V2DF 0 "register_operand" "=x")
20278 (subreg:V2DF (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
20279 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
20281 "orpd\t{%2, %0|%0, %2}"
20282 [(set_attr "type" "sselog")
20283 (set_attr "mode" "V2DF")])
20285 (define_insn "sse2_xordf3"
20286 [(set (match_operand:V2DF 0 "register_operand" "=x")
20287 (subreg:V2DF (xor:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0)
20288 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))]
20290 "xorpd\t{%2, %0|%0, %2}"
20291 [(set_attr "type" "sselog")
20292 (set_attr "mode" "V2DF")])
20293 ;; SSE2 square root. There doesn't appear to be an extension for the
20294 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
20296 (define_insn "sqrtv2df2"
20297 [(set (match_operand:V2DF 0 "register_operand" "=x")
20298 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
20300 "sqrtpd\t{%1, %0|%0, %1}"
20301 [(set_attr "type" "sse")
20302 (set_attr "mode" "V2DF")])
20304 (define_insn "vmsqrtv2df2"
20305 [(set (match_operand:V2DF 0 "register_operand" "=x")
20306 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
20307 (match_operand:V2DF 2 "register_operand" "0")
20310 "sqrtsd\t{%1, %0|%0, %1}"
20311 [(set_attr "type" "sse")
20312 (set_attr "mode" "SF")])
20314 ;; SSE mask-generating compares
20316 (define_insn "maskcmpv2df3"
20317 [(set (match_operand:V2DI 0 "register_operand" "=x")
20318 (match_operator:V2DI 3 "sse_comparison_operator"
20319 [(match_operand:V2DF 1 "register_operand" "0")
20320 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
20322 "cmp%D3pd\t{%2, %0|%0, %2}"
20323 [(set_attr "type" "ssecmp")
20324 (set_attr "mode" "V2DF")])
20326 (define_insn "maskncmpv2df3"
20327 [(set (match_operand:V2DI 0 "register_operand" "=x")
20329 (match_operator:V2DI 3 "sse_comparison_operator"
20330 [(match_operand:V2DF 1 "register_operand" "0")
20331 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
20333 "cmpn%D3pd\t{%2, %0|%0, %2}"
20334 [(set_attr "type" "ssecmp")
20335 (set_attr "mode" "V2DF")])
20337 (define_insn "vmmaskcmpv2df3"
20338 [(set (match_operand:V2DI 0 "register_operand" "=x")
20340 (match_operator:V2DI 3 "sse_comparison_operator"
20341 [(match_operand:V2DF 1 "register_operand" "0")
20342 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
20346 "cmp%D3sd\t{%2, %0|%0, %2}"
20347 [(set_attr "type" "ssecmp")
20348 (set_attr "mode" "DF")])
20350 (define_insn "vmmaskncmpv2df3"
20351 [(set (match_operand:V2DI 0 "register_operand" "=x")
20354 (match_operator:V2DI 3 "sse_comparison_operator"
20355 [(match_operand:V2DF 1 "register_operand" "0")
20356 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
20357 (subreg:V2DI (match_dup 1) 0)
20360 "cmp%D3sd\t{%2, %0|%0, %2}"
20361 [(set_attr "type" "ssecmp")
20362 (set_attr "mode" "DF")])
20364 (define_insn "sse2_comi"
20365 [(set (reg:CCFP 17)
20366 (match_operator:CCFP 2 "sse_comparison_operator"
20368 (match_operand:V2DF 0 "register_operand" "x")
20369 (parallel [(const_int 0)]))
20371 (match_operand:V2DF 1 "register_operand" "x")
20372 (parallel [(const_int 0)]))]))]
20374 "comisd\t{%1, %0|%0, %1}"
20375 [(set_attr "type" "ssecmp")
20376 (set_attr "mode" "DF")])
20378 (define_insn "sse2_ucomi"
20379 [(set (reg:CCFPU 17)
20380 (match_operator:CCFPU 2 "sse_comparison_operator"
20382 (match_operand:V2DF 0 "register_operand" "x")
20383 (parallel [(const_int 0)]))
20385 (match_operand:V2DF 1 "register_operand" "x")
20386 (parallel [(const_int 0)]))]))]
20388 "ucomisd\t{%1, %0|%0, %1}"
20389 [(set_attr "type" "ssecmp")
20390 (set_attr "mode" "DF")])
20392 ;; SSE Strange Moves.
20394 (define_insn "sse2_movmskpd"
20395 [(set (match_operand:SI 0 "register_operand" "=r")
20396 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
20399 "movmskpd\t{%1, %0|%0, %1}"
20400 [(set_attr "type" "ssecvt")
20401 (set_attr "mode" "V2DF")])
20403 (define_insn "sse2_pmovmskb"
20404 [(set (match_operand:SI 0 "register_operand" "=r")
20405 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
20408 "pmovmskb\t{%1, %0|%0, %1}"
20409 [(set_attr "type" "ssecvt")
20410 (set_attr "mode" "V2DF")])
20412 (define_insn "sse2_maskmovdqu"
20413 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
20414 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
20415 (match_operand:V16QI 2 "register_operand" "x")]
20418 ;; @@@ check ordering of operands in intel/nonintel syntax
20419 "maskmovdqu\t{%2, %1|%1, %2}"
20420 [(set_attr "type" "ssecvt")
20421 (set_attr "mode" "TI")])
20423 (define_insn "sse2_movntv2df"
20424 [(set (match_operand:V2DF 0 "memory_operand" "=m")
20425 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
20428 "movntpd\t{%1, %0|%0, %1}"
20429 [(set_attr "type" "ssecvt")
20430 (set_attr "mode" "V2DF")])
20432 (define_insn "sse2_movntv2di"
20433 [(set (match_operand:V2DI 0 "memory_operand" "=m")
20434 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
20437 "movntdq\t{%1, %0|%0, %1}"
20438 [(set_attr "type" "ssecvt")
20439 (set_attr "mode" "TI")])
20441 (define_insn "sse2_movntsi"
20442 [(set (match_operand:SI 0 "memory_operand" "=m")
20443 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
20446 "movnti\t{%1, %0|%0, %1}"
20447 [(set_attr "type" "ssecvt")
20448 (set_attr "mode" "V2DF")])
20450 ;; SSE <-> integer/MMX conversions
20452 ;; Conversions between SI and SF
20454 (define_insn "cvtdq2ps"
20455 [(set (match_operand:V4SF 0 "register_operand" "=x")
20456 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
20458 "cvtdq2ps\t{%1, %0|%0, %1}"
20459 [(set_attr "type" "ssecvt")
20460 (set_attr "mode" "V2DF")])
20462 (define_insn "cvtps2dq"
20463 [(set (match_operand:V4SI 0 "register_operand" "=x")
20464 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
20466 "cvtps2dq\t{%1, %0|%0, %1}"
20467 [(set_attr "type" "ssecvt")
20468 (set_attr "mode" "TI")])
20470 (define_insn "cvttps2dq"
20471 [(set (match_operand:V4SI 0 "register_operand" "=x")
20472 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20475 "cvttps2dq\t{%1, %0|%0, %1}"
20476 [(set_attr "type" "ssecvt")
20477 (set_attr "mode" "TI")])
20479 ;; Conversions between SI and DF
20481 (define_insn "cvtdq2pd"
20482 [(set (match_operand:V2DF 0 "register_operand" "=x")
20483 (float:V2DF (vec_select:V2SI
20484 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
20487 (const_int 1)]))))]
20489 "cvtdq2pd\t{%1, %0|%0, %1}"
20490 [(set_attr "type" "ssecvt")
20491 (set_attr "mode" "V2DF")])
20493 (define_insn "cvtpd2dq"
20494 [(set (match_operand:V4SI 0 "register_operand" "=x")
20496 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
20497 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
20499 "cvtpd2dq\t{%1, %0|%0, %1}"
20500 [(set_attr "type" "ssecvt")
20501 (set_attr "mode" "TI")])
20503 (define_insn "cvttpd2dq"
20504 [(set (match_operand:V4SI 0 "register_operand" "=x")
20506 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
20508 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
20510 "cvttpd2dq\t{%1, %0|%0, %1}"
20511 [(set_attr "type" "ssecvt")
20512 (set_attr "mode" "TI")])
20514 (define_insn "cvtpd2pi"
20515 [(set (match_operand:V2SI 0 "register_operand" "=y")
20516 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
20518 "cvtpd2pi\t{%1, %0|%0, %1}"
20519 [(set_attr "type" "ssecvt")
20520 (set_attr "mode" "TI")])
20522 (define_insn "cvttpd2pi"
20523 [(set (match_operand:V2SI 0 "register_operand" "=y")
20524 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
20527 "cvttpd2pi\t{%1, %0|%0, %1}"
20528 [(set_attr "type" "ssecvt")
20529 (set_attr "mode" "TI")])
20531 (define_insn "cvtpi2pd"
20532 [(set (match_operand:V2DF 0 "register_operand" "=x")
20533 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
20535 "cvtpi2pd\t{%1, %0|%0, %1}"
20536 [(set_attr "type" "ssecvt")
20537 (set_attr "mode" "TI")])
20539 ;; Conversions between SI and DF
20541 (define_insn "cvtsd2si"
20542 [(set (match_operand:SI 0 "register_operand" "=r")
20543 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20544 (parallel [(const_int 0)]))))]
20546 "cvtsd2si\t{%1, %0|%0, %1}"
20547 [(set_attr "type" "ssecvt")
20548 (set_attr "mode" "SI")])
20550 (define_insn "cvttsd2si"
20551 [(set (match_operand:SI 0 "register_operand" "=r")
20552 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm")
20553 (parallel [(const_int 0)]))] UNSPEC_FIX))]
20555 "cvttsd2si\t{%1, %0|%0, %1}"
20556 [(set_attr "type" "ssecvt")
20557 (set_attr "mode" "SI")])
20559 (define_insn "cvtsi2sd"
20560 [(set (match_operand:V2DF 0 "register_operand" "=x")
20561 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
20562 (vec_duplicate:V2DF
20564 (match_operand:SI 2 "nonimmediate_operand" "rm")))
20567 "cvtsd2si\t{%2, %0|%0, %2}"
20568 [(set_attr "type" "ssecvt")
20569 (set_attr "mode" "DF")])
20571 ;; Conversions between SF and DF
20573 (define_insn "cvtsd2ss"
20574 [(set (match_operand:V4SF 0 "register_operand" "=x")
20575 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
20576 (vec_duplicate:V4SF
20577 (float_truncate:V2SF
20578 (match_operand:V2DF 2 "register_operand" "xm")))
20581 "cvtsd2ss\t{%2, %0|%0, %2}"
20582 [(set_attr "type" "ssecvt")
20583 (set_attr "mode" "SF")])
20585 (define_insn "cvtss2sd"
20586 [(set (match_operand:V2DF 0 "register_operand" "=x")
20587 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
20590 (match_operand:V4SF 2 "register_operand" "xm")
20591 (parallel [(const_int 0)
20595 "cvtss2sd\t{%2, %0|%0, %2}"
20596 [(set_attr "type" "ssecvt")
20597 (set_attr "mode" "DF")])
20599 (define_insn "cvtpd2ps"
20600 [(set (match_operand:V4SF 0 "register_operand" "=x")
20603 (subreg:V2SI (float_truncate:V2SF
20604 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
20605 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
20607 "cvtpd2ps\t{%1, %0|%0, %1}"
20608 [(set_attr "type" "ssecvt")
20609 (set_attr "mode" "V4SF")])
20611 (define_insn "cvtps2pd"
20612 [(set (match_operand:V2DF 0 "register_operand" "=x")
20614 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
20615 (parallel [(const_int 0)
20616 (const_int 1)]))))]
20618 "cvtps2pd\t{%1, %0|%0, %1}"
20619 [(set_attr "type" "ssecvt")
20620 (set_attr "mode" "V2DF")])
20622 ;; SSE2 variants of MMX insns
20626 (define_insn "addv16qi3"
20627 [(set (match_operand:V16QI 0 "register_operand" "=x")
20628 (plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20629 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20631 "paddb\t{%2, %0|%0, %2}"
20632 [(set_attr "type" "sseiadd")
20633 (set_attr "mode" "TI")])
20635 (define_insn "addv8hi3"
20636 [(set (match_operand:V8HI 0 "register_operand" "=x")
20637 (plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20638 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20640 "paddw\t{%2, %0|%0, %2}"
20641 [(set_attr "type" "sseiadd")
20642 (set_attr "mode" "TI")])
20644 (define_insn "addv4si3"
20645 [(set (match_operand:V4SI 0 "register_operand" "=x")
20646 (plus:V4SI (match_operand:V4SI 1 "register_operand" "0")
20647 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20649 "paddd\t{%2, %0|%0, %2}"
20650 [(set_attr "type" "sseiadd")
20651 (set_attr "mode" "TI")])
20653 (define_insn "addv2di3"
20654 [(set (match_operand:V2DI 0 "register_operand" "=x")
20655 (plus:V2DI (match_operand:V2DI 1 "register_operand" "0")
20656 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20658 "paddq\t{%2, %0|%0, %2}"
20659 [(set_attr "type" "sseiadd")
20660 (set_attr "mode" "TI")])
20662 (define_insn "ssaddv16qi3"
20663 [(set (match_operand:V16QI 0 "register_operand" "=x")
20664 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20665 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20667 "paddsb\t{%2, %0|%0, %2}"
20668 [(set_attr "type" "sseiadd")
20669 (set_attr "mode" "TI")])
20671 (define_insn "ssaddv8hi3"
20672 [(set (match_operand:V8HI 0 "register_operand" "=x")
20673 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20674 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20676 "paddsw\t{%2, %0|%0, %2}"
20677 [(set_attr "type" "sseiadd")
20678 (set_attr "mode" "TI")])
20680 (define_insn "usaddv16qi3"
20681 [(set (match_operand:V16QI 0 "register_operand" "=x")
20682 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20683 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20685 "paddusb\t{%2, %0|%0, %2}"
20686 [(set_attr "type" "sseiadd")
20687 (set_attr "mode" "TI")])
20689 (define_insn "usaddv8hi3"
20690 [(set (match_operand:V8HI 0 "register_operand" "=x")
20691 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20692 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20694 "paddusw\t{%2, %0|%0, %2}"
20695 [(set_attr "type" "sseiadd")
20696 (set_attr "mode" "TI")])
20698 (define_insn "subv16qi3"
20699 [(set (match_operand:V16QI 0 "register_operand" "=x")
20700 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20701 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20703 "psubb\t{%2, %0|%0, %2}"
20704 [(set_attr "type" "sseiadd")
20705 (set_attr "mode" "TI")])
20707 (define_insn "subv8hi3"
20708 [(set (match_operand:V8HI 0 "register_operand" "=x")
20709 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20710 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20712 "psubw\t{%2, %0|%0, %2}"
20713 [(set_attr "type" "sseiadd")
20714 (set_attr "mode" "TI")])
20716 (define_insn "subv4si3"
20717 [(set (match_operand:V4SI 0 "register_operand" "=x")
20718 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
20719 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
20721 "psubd\t{%2, %0|%0, %2}"
20722 [(set_attr "type" "sseiadd")
20723 (set_attr "mode" "TI")])
20725 (define_insn "subv2di3"
20726 [(set (match_operand:V2DI 0 "register_operand" "=x")
20727 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
20728 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20730 "psubq\t{%2, %0|%0, %2}"
20731 [(set_attr "type" "sseiadd")
20732 (set_attr "mode" "TI")])
20734 (define_insn "sssubv16qi3"
20735 [(set (match_operand:V16QI 0 "register_operand" "=x")
20736 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20737 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20739 "psubsb\t{%2, %0|%0, %2}"
20740 [(set_attr "type" "sseiadd")
20741 (set_attr "mode" "TI")])
20743 (define_insn "sssubv8hi3"
20744 [(set (match_operand:V8HI 0 "register_operand" "=x")
20745 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20746 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20748 "psubsw\t{%2, %0|%0, %2}"
20749 [(set_attr "type" "sseiadd")
20750 (set_attr "mode" "TI")])
20752 (define_insn "ussubv16qi3"
20753 [(set (match_operand:V16QI 0 "register_operand" "=x")
20754 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
20755 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20757 "psubusb\t{%2, %0|%0, %2}"
20758 [(set_attr "type" "sseiadd")
20759 (set_attr "mode" "TI")])
20761 (define_insn "ussubv8hi3"
20762 [(set (match_operand:V8HI 0 "register_operand" "=x")
20763 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
20764 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20766 "psubusw\t{%2, %0|%0, %2}"
20767 [(set_attr "type" "sseiadd")
20768 (set_attr "mode" "TI")])
20770 (define_insn "mulv8hi3"
20771 [(set (match_operand:V8HI 0 "register_operand" "=x")
20772 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
20773 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20775 "pmullw\t{%2, %0|%0, %2}"
20776 [(set_attr "type" "sseimul")
20777 (set_attr "mode" "TI")])
20779 (define_insn "smulv8hi3_highpart"
20780 [(set (match_operand:V8HI 0 "register_operand" "=x")
20783 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
20784 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
20787 "pmulhw\t{%2, %0|%0, %2}"
20788 [(set_attr "type" "sseimul")
20789 (set_attr "mode" "TI")])
20791 (define_insn "umulv8hi3_highpart"
20792 [(set (match_operand:V8HI 0 "register_operand" "=x")
20795 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
20796 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
20799 "pmulhuw\t{%2, %0|%0, %2}"
20800 [(set_attr "type" "sseimul")
20801 (set_attr "mode" "TI")])
20803 (define_insn "sse2_umulsidi3"
20804 [(set (match_operand:DI 0 "register_operand" "=y")
20805 (mult:DI (zero_extend:DI (vec_select:SI
20806 (match_operand:V2SI 1 "register_operand" "0")
20807 (parallel [(const_int 0)])))
20808 (zero_extend:DI (vec_select:SI
20809 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
20810 (parallel [(const_int 0)])))))]
20812 "pmuludq\t{%2, %0|%0, %2}"
20813 [(set_attr "type" "sseimul")
20814 (set_attr "mode" "TI")])
20816 (define_insn "sse2_umulv2siv2di3"
20817 [(set (match_operand:V2DI 0 "register_operand" "=y")
20818 (mult:V2DI (zero_extend:V2DI
20820 (match_operand:V4SI 1 "register_operand" "0")
20821 (parallel [(const_int 0) (const_int 2)])))
20824 (match_operand:V4SI 2 "nonimmediate_operand" "ym")
20825 (parallel [(const_int 0) (const_int 2)])))))]
20827 "pmuludq\t{%2, %0|%0, %2}"
20828 [(set_attr "type" "sseimul")
20829 (set_attr "mode" "TI")])
20831 (define_insn "sse2_pmaddwd"
20832 [(set (match_operand:V4SI 0 "register_operand" "=x")
20835 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
20836 (parallel [(const_int 0)
20840 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
20841 (parallel [(const_int 0)
20846 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
20847 (parallel [(const_int 1)
20851 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
20852 (parallel [(const_int 1)
20855 (const_int 7)]))))))]
20857 "pmaddwd\t{%2, %0|%0, %2}"
20858 [(set_attr "type" "sseiadd")
20859 (set_attr "mode" "TI")])
20861 ;; Same as pxor, but don't show input operands so that we don't think
20863 (define_insn "sse2_clrti"
20864 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
20866 "pxor\t{%0, %0|%0, %0}"
20867 [(set_attr "type" "sseiadd")
20868 (set_attr "memory" "none")
20869 (set_attr "mode" "TI")])
20871 ;; MMX unsigned averages/sum of absolute differences
20873 (define_insn "sse2_uavgv16qi3"
20874 [(set (match_operand:V16QI 0 "register_operand" "=x")
20876 (plus:V16QI (plus:V16QI
20877 (match_operand:V16QI 1 "register_operand" "0")
20878 (match_operand:V16QI 2 "nonimmediate_operand" "ym"))
20879 (const_vector:V16QI [(const_int 1) (const_int 1)
20880 (const_int 1) (const_int 1)
20881 (const_int 1) (const_int 1)
20882 (const_int 1) (const_int 1)
20883 (const_int 1) (const_int 1)
20884 (const_int 1) (const_int 1)
20885 (const_int 1) (const_int 1)
20886 (const_int 1) (const_int 1)]))
20889 "pavgb\t{%2, %0|%0, %2}"
20890 [(set_attr "type" "sseiadd")
20891 (set_attr "mode" "TI")])
20893 (define_insn "sse2_uavgv8hi3"
20894 [(set (match_operand:V8HI 0 "register_operand" "=x")
20896 (plus:V8HI (plus:V8HI
20897 (match_operand:V8HI 1 "register_operand" "0")
20898 (match_operand:V8HI 2 "nonimmediate_operand" "ym"))
20899 (const_vector:V8HI [(const_int 1) (const_int 1)
20900 (const_int 1) (const_int 1)
20901 (const_int 1) (const_int 1)
20902 (const_int 1) (const_int 1)]))
20905 "pavgw\t{%2, %0|%0, %2}"
20906 [(set_attr "type" "sseiadd")
20907 (set_attr "mode" "TI")])
20909 ;; @@@ this isn't the right representation.
20910 (define_insn "sse2_psadbw"
20911 [(set (match_operand:V2DI 0 "register_operand" "=x")
20912 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
20913 (match_operand:V16QI 2 "nonimmediate_operand" "ym")]
20916 "psadbw\t{%2, %0|%0, %2}"
20917 [(set_attr "type" "sseiadd")
20918 (set_attr "mode" "TI")])
20921 ;; MMX insert/extract/shuffle
20923 (define_insn "sse2_pinsrw"
20924 [(set (match_operand:V8HI 0 "register_operand" "=x")
20925 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
20926 (vec_duplicate:V8HI
20927 (match_operand:SI 2 "nonimmediate_operand" "rm"))
20928 (match_operand:SI 3 "immediate_operand" "i")))]
20930 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20931 [(set_attr "type" "ssecvt")
20932 (set_attr "mode" "TI")])
20934 (define_insn "sse2_pextrw"
20935 [(set (match_operand:SI 0 "register_operand" "=r")
20937 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
20939 [(match_operand:SI 2 "immediate_operand" "i")]))))]
20941 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20942 [(set_attr "type" "ssecvt")
20943 (set_attr "mode" "TI")])
20945 (define_insn "sse2_pshufd"
20946 [(set (match_operand:V4SI 0 "register_operand" "=x")
20947 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
20948 (match_operand:SI 2 "immediate_operand" "i")]
20951 "pshufd\t{%2, %1, %0|%0, %1, %2}"
20952 [(set_attr "type" "ssecvt")
20953 (set_attr "mode" "TI")])
20955 (define_insn "sse2_pshuflw"
20956 [(set (match_operand:V8HI 0 "register_operand" "=x")
20957 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
20958 (match_operand:SI 2 "immediate_operand" "i")]
20961 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
20962 [(set_attr "type" "ssecvt")
20963 (set_attr "mode" "TI")])
20965 (define_insn "sse2_pshufhw"
20966 [(set (match_operand:V8HI 0 "register_operand" "=x")
20967 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
20968 (match_operand:SI 2 "immediate_operand" "i")]
20971 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
20972 [(set_attr "type" "ssecvt")
20973 (set_attr "mode" "TI")])
20975 ;; MMX mask-generating comparisons
20977 (define_insn "eqv16qi3"
20978 [(set (match_operand:V16QI 0 "register_operand" "=x")
20979 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
20980 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
20982 "pcmpeqb\t{%2, %0|%0, %2}"
20983 [(set_attr "type" "ssecmp")
20984 (set_attr "mode" "TI")])
20986 (define_insn "eqv8hi3"
20987 [(set (match_operand:V8HI 0 "register_operand" "=x")
20988 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
20989 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
20991 "pcmpeqw\t{%2, %0|%0, %2}"
20992 [(set_attr "type" "ssecmp")
20993 (set_attr "mode" "TI")])
20995 (define_insn "eqv4si3"
20996 [(set (match_operand:V4SI 0 "register_operand" "=x")
20997 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
20998 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21000 "pcmpeqd\t{%2, %0|%0, %2}"
21001 [(set_attr "type" "ssecmp")
21002 (set_attr "mode" "TI")])
21004 (define_insn "gtv16qi3"
21005 [(set (match_operand:V16QI 0 "register_operand" "=x")
21006 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
21007 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21009 "pcmpgtb\t{%2, %0|%0, %2}"
21010 [(set_attr "type" "ssecmp")
21011 (set_attr "mode" "TI")])
21013 (define_insn "gtv8hi3"
21014 [(set (match_operand:V8HI 0 "register_operand" "=x")
21015 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21016 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21018 "pcmpgtw\t{%2, %0|%0, %2}"
21019 [(set_attr "type" "ssecmp")
21020 (set_attr "mode" "TI")])
21022 (define_insn "gtv4si3"
21023 [(set (match_operand:V4SI 0 "register_operand" "=x")
21024 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21025 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21027 "pcmpgtd\t{%2, %0|%0, %2}"
21028 [(set_attr "type" "ssecmp")
21029 (set_attr "mode" "TI")])
21032 ;; MMX max/min insns
21034 (define_insn "umaxv16qi3"
21035 [(set (match_operand:V16QI 0 "register_operand" "=x")
21036 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
21037 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21039 "pmaxub\t{%2, %0|%0, %2}"
21040 [(set_attr "type" "sseiadd")
21041 (set_attr "mode" "TI")])
21043 (define_insn "smaxv8hi3"
21044 [(set (match_operand:V8HI 0 "register_operand" "=x")
21045 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
21046 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21048 "pmaxsw\t{%2, %0|%0, %2}"
21049 [(set_attr "type" "sseiadd")
21050 (set_attr "mode" "TI")])
21052 (define_insn "uminv16qi3"
21053 [(set (match_operand:V16QI 0 "register_operand" "=x")
21054 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
21055 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21057 "pminub\t{%2, %0|%0, %2}"
21058 [(set_attr "type" "sseiadd")
21059 (set_attr "mode" "TI")])
21061 (define_insn "sminv8hi3"
21062 [(set (match_operand:V8HI 0 "register_operand" "=x")
21063 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
21064 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21066 "pminsw\t{%2, %0|%0, %2}"
21067 [(set_attr "type" "sseiadd")
21068 (set_attr "mode" "TI")])
21073 (define_insn "ashrv8hi3"
21074 [(set (match_operand:V8HI 0 "register_operand" "=x")
21075 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21076 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21078 "psraw\t{%2, %0|%0, %2}"
21079 [(set_attr "type" "sseishft")
21080 (set_attr "mode" "TI")])
21082 (define_insn "ashrv4si3"
21083 [(set (match_operand:V4SI 0 "register_operand" "=x")
21084 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21085 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21087 "psrad\t{%2, %0|%0, %2}"
21088 [(set_attr "type" "sseishft")
21089 (set_attr "mode" "TI")])
21091 (define_insn "lshrv8hi3"
21092 [(set (match_operand:V8HI 0 "register_operand" "=x")
21093 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21094 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21096 "psrlw\t{%2, %0|%0, %2}"
21097 [(set_attr "type" "sseishft")
21098 (set_attr "mode" "TI")])
21100 (define_insn "lshrv4si3"
21101 [(set (match_operand:V4SI 0 "register_operand" "=x")
21102 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21103 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21105 "psrld\t{%2, %0|%0, %2}"
21106 [(set_attr "type" "sseishft")
21107 (set_attr "mode" "TI")])
21109 (define_insn "lshrv2di3"
21110 [(set (match_operand:V2DI 0 "register_operand" "=x")
21111 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
21112 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21114 "psrlq\t{%2, %0|%0, %2}"
21115 [(set_attr "type" "sseishft")
21116 (set_attr "mode" "TI")])
21118 (define_insn "ashlv8hi3"
21119 [(set (match_operand:V8HI 0 "register_operand" "=x")
21120 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
21121 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21123 "psllw\t{%2, %0|%0, %2}"
21124 [(set_attr "type" "sseishft")
21125 (set_attr "mode" "TI")])
21127 (define_insn "ashlv4si3"
21128 [(set (match_operand:V4SI 0 "register_operand" "=x")
21129 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
21130 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21132 "pslld\t{%2, %0|%0, %2}"
21133 [(set_attr "type" "sseishft")
21134 (set_attr "mode" "TI")])
21136 (define_insn "ashlv2di3"
21137 [(set (match_operand:V2DI 0 "register_operand" "=x")
21138 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
21139 (match_operand:SI 2 "nonmemory_operand" "ri")))]
21141 "psllq\t{%2, %0|%0, %2}"
21142 [(set_attr "type" "sseishft")
21143 (set_attr "mode" "TI")])
21145 (define_insn "ashrv8hi3_ti"
21146 [(set (match_operand:V8HI 0 "register_operand" "=x")
21147 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21148 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21150 "psraw\t{%2, %0|%0, %2}"
21151 [(set_attr "type" "sseishft")
21152 (set_attr "mode" "TI")])
21154 (define_insn "ashrv4si3_ti"
21155 [(set (match_operand:V4SI 0 "register_operand" "=x")
21156 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21157 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21159 "psrad\t{%2, %0|%0, %2}"
21160 [(set_attr "type" "sseishft")
21161 (set_attr "mode" "TI")])
21163 (define_insn "lshrv8hi3_ti"
21164 [(set (match_operand:V8HI 0 "register_operand" "=x")
21165 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
21166 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21168 "psrlw\t{%2, %0|%0, %2}"
21169 [(set_attr "type" "sseishft")
21170 (set_attr "mode" "TI")])
21172 (define_insn "lshrv4si3_ti"
21173 [(set (match_operand:V4SI 0 "register_operand" "=x")
21174 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
21175 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21177 "psrld\t{%2, %0|%0, %2}"
21178 [(set_attr "type" "sseishft")
21179 (set_attr "mode" "TI")])
21181 (define_insn "lshrv2di3_ti"
21182 [(set (match_operand:V2DI 0 "register_operand" "=x")
21183 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
21184 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21186 "psrlq\t{%2, %0|%0, %2}"
21187 [(set_attr "type" "sseishft")
21188 (set_attr "mode" "TI")])
21190 (define_insn "ashlv8hi3_ti"
21191 [(set (match_operand:V8HI 0 "register_operand" "=x")
21192 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
21193 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21195 "psllw\t{%2, %0|%0, %2}"
21196 [(set_attr "type" "sseishft")
21197 (set_attr "mode" "TI")])
21199 (define_insn "ashlv4si3_ti"
21200 [(set (match_operand:V4SI 0 "register_operand" "=x")
21201 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
21202 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21204 "pslld\t{%2, %0|%0, %2}"
21205 [(set_attr "type" "sseishft")
21206 (set_attr "mode" "TI")])
21208 (define_insn "ashlv2di3_ti"
21209 [(set (match_operand:V2DI 0 "register_operand" "=x")
21210 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
21211 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
21213 "psllq\t{%2, %0|%0, %2}"
21214 [(set_attr "type" "sseishft")
21215 (set_attr "mode" "TI")])
21217 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
21218 ;; we wouldn't need here it since we never generate TImode arithmetic.
21220 ;; There has to be some kind of prize for the weirdest new instruction...
21221 (define_insn "sse2_ashlti3"
21222 [(set (match_operand:TI 0 "register_operand" "=x")
21224 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
21225 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
21226 (const_int 8)))] UNSPEC_NOP))]
21228 "pslldq\t{%2, %0|%0, %2}"
21229 [(set_attr "type" "sseishft")
21230 (set_attr "mode" "TI")])
21232 (define_insn "sse2_lshrti3"
21233 [(set (match_operand:TI 0 "register_operand" "=x")
21235 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
21236 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
21237 (const_int 8)))] UNSPEC_NOP))]
21239 "pslrdq\t{%2, %0|%0, %2}"
21240 [(set_attr "type" "sseishft")
21241 (set_attr "mode" "TI")])
21245 (define_insn "sse2_unpckhpd"
21246 [(set (match_operand:V2DF 0 "register_operand" "=x")
21248 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0")
21249 (parallel [(const_int 1)]))
21250 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x")
21251 (parallel [(const_int 0)]))))]
21253 "unpckhpd\t{%2, %0|%0, %2}"
21254 [(set_attr "type" "ssecvt")
21255 (set_attr "mode" "TI")])
21257 (define_insn "sse2_unpcklpd"
21258 [(set (match_operand:V2DF 0 "register_operand" "=x")
21260 (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0")
21261 (parallel [(const_int 0)]))
21262 (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x")
21263 (parallel [(const_int 1)]))))]
21265 "unpcklpd\t{%2, %0|%0, %2}"
21266 [(set_attr "type" "ssecvt")
21267 (set_attr "mode" "TI")])
21269 ;; MMX pack/unpack insns.
21271 (define_insn "sse2_packsswb"
21272 [(set (match_operand:V16QI 0 "register_operand" "=x")
21274 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
21275 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
21277 "packsswb\t{%2, %0|%0, %2}"
21278 [(set_attr "type" "ssecvt")
21279 (set_attr "mode" "TI")])
21281 (define_insn "sse2_packssdw"
21282 [(set (match_operand:V8HI 0 "register_operand" "=x")
21284 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
21285 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
21287 "packssdw\t{%2, %0|%0, %2}"
21288 [(set_attr "type" "ssecvt")
21289 (set_attr "mode" "TI")])
21291 (define_insn "sse2_packuswb"
21292 [(set (match_operand:V16QI 0 "register_operand" "=x")
21294 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
21295 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
21297 "packuswb\t{%2, %0|%0, %2}"
21298 [(set_attr "type" "ssecvt")
21299 (set_attr "mode" "TI")])
21301 (define_insn "sse2_punpckhbw"
21302 [(set (match_operand:V16QI 0 "register_operand" "=x")
21304 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
21305 (parallel [(const_int 8) (const_int 0)
21306 (const_int 9) (const_int 1)
21307 (const_int 10) (const_int 2)
21308 (const_int 11) (const_int 3)
21309 (const_int 12) (const_int 4)
21310 (const_int 13) (const_int 5)
21311 (const_int 14) (const_int 6)
21312 (const_int 15) (const_int 7)]))
21313 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
21314 (parallel [(const_int 0) (const_int 8)
21315 (const_int 1) (const_int 9)
21316 (const_int 2) (const_int 10)
21317 (const_int 3) (const_int 11)
21318 (const_int 4) (const_int 12)
21319 (const_int 5) (const_int 13)
21320 (const_int 6) (const_int 14)
21321 (const_int 7) (const_int 15)]))
21322 (const_int 21845)))]
21324 "punpckhbw\t{%2, %0|%0, %2}"
21325 [(set_attr "type" "ssecvt")
21326 (set_attr "mode" "TI")])
21328 (define_insn "sse2_punpckhwd"
21329 [(set (match_operand:V8HI 0 "register_operand" "=x")
21331 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
21332 (parallel [(const_int 4) (const_int 0)
21333 (const_int 5) (const_int 1)
21334 (const_int 6) (const_int 2)
21335 (const_int 7) (const_int 3)]))
21336 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
21337 (parallel [(const_int 0) (const_int 4)
21338 (const_int 1) (const_int 5)
21339 (const_int 2) (const_int 6)
21340 (const_int 3) (const_int 7)]))
21343 "punpckhwd\t{%2, %0|%0, %2}"
21344 [(set_attr "type" "ssecvt")
21345 (set_attr "mode" "TI")])
21347 (define_insn "sse2_punpckhdq"
21348 [(set (match_operand:V4SI 0 "register_operand" "=x")
21350 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
21351 (parallel [(const_int 2) (const_int 0)
21352 (const_int 3) (const_int 1)]))
21353 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
21354 (parallel [(const_int 0) (const_int 2)
21355 (const_int 1) (const_int 3)]))
21358 "punpckhdq\t{%2, %0|%0, %2}"
21359 [(set_attr "type" "ssecvt")
21360 (set_attr "mode" "TI")])
21362 (define_insn "sse2_punpcklbw"
21363 [(set (match_operand:V16QI 0 "register_operand" "=x")
21365 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
21366 (parallel [(const_int 0) (const_int 8)
21367 (const_int 1) (const_int 9)
21368 (const_int 2) (const_int 10)
21369 (const_int 3) (const_int 11)
21370 (const_int 4) (const_int 12)
21371 (const_int 5) (const_int 13)
21372 (const_int 6) (const_int 14)
21373 (const_int 7) (const_int 15)]))
21374 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
21375 (parallel [(const_int 8) (const_int 0)
21376 (const_int 9) (const_int 1)
21377 (const_int 10) (const_int 2)
21378 (const_int 11) (const_int 3)
21379 (const_int 12) (const_int 4)
21380 (const_int 13) (const_int 5)
21381 (const_int 14) (const_int 6)
21382 (const_int 15) (const_int 7)]))
21383 (const_int 21845)))]
21385 "punpcklbw\t{%2, %0|%0, %2}"
21386 [(set_attr "type" "ssecvt")
21387 (set_attr "mode" "TI")])
21389 (define_insn "sse2_punpcklwd"
21390 [(set (match_operand:V8HI 0 "register_operand" "=x")
21392 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
21393 (parallel [(const_int 0) (const_int 4)
21394 (const_int 1) (const_int 5)
21395 (const_int 2) (const_int 6)
21396 (const_int 3) (const_int 7)]))
21397 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
21398 (parallel [(const_int 4) (const_int 0)
21399 (const_int 5) (const_int 1)
21400 (const_int 6) (const_int 2)
21401 (const_int 7) (const_int 3)]))
21404 "punpcklwd\t{%2, %0|%0, %2}"
21405 [(set_attr "type" "ssecvt")
21406 (set_attr "mode" "TI")])
21408 (define_insn "sse2_punpckldq"
21409 [(set (match_operand:V4SI 0 "register_operand" "=x")
21411 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
21412 (parallel [(const_int 0) (const_int 2)
21413 (const_int 1) (const_int 3)]))
21414 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
21415 (parallel [(const_int 2) (const_int 0)
21416 (const_int 3) (const_int 1)]))
21419 "punpckldq\t{%2, %0|%0, %2}"
21420 [(set_attr "type" "ssecvt")
21421 (set_attr "mode" "TI")])
21425 (define_insn "sse2_movapd"
21426 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21427 (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
21431 movapd\t{%1, %0|%0, %1}
21432 movapd\t{%1, %0|%0, %1}"
21433 [(set_attr "type" "ssemov")
21434 (set_attr "mode" "V2DF")])
21436 (define_insn "sse2_movupd"
21437 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21438 (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")]
21442 movupd\t{%1, %0|%0, %1}
21443 movupd\t{%1, %0|%0, %1}"
21444 [(set_attr "type" "ssecvt")
21445 (set_attr "mode" "V2DF")])
21447 (define_insn "sse2_movdqa"
21448 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
21449 (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
21453 movdqa\t{%1, %0|%0, %1}
21454 movdqa\t{%1, %0|%0, %1}"
21455 [(set_attr "type" "ssemov")
21456 (set_attr "mode" "TI")])
21458 (define_insn "sse2_movdqu"
21459 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
21460 (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")]
21464 movdqu\t{%1, %0|%0, %1}
21465 movdqu\t{%1, %0|%0, %1}"
21466 [(set_attr "type" "ssecvt")
21467 (set_attr "mode" "TI")])
21469 (define_insn "sse2_movdq2q"
21470 [(set (match_operand:DI 0 "nonimmediate_operand" "=y")
21471 (vec_select:DI (match_operand:V2DI 1 "general_operand" "x")
21472 (parallel [(const_int 0)])))]
21474 "movdq2q\t{%1, %0|%0, %1}"
21475 [(set_attr "type" "ssecvt")
21476 (set_attr "mode" "TI")])
21478 (define_insn "sse2_movq2dq"
21479 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x")
21480 (vec_concat:V2DI (match_operand:DI 1 "general_operand" "y")
21481 (const_vector:DI [(const_int 0)])))]
21483 "movq2dq\t{%1, %0|%0, %1}"
21484 [(set_attr "type" "ssecvt")
21485 (set_attr "mode" "TI")])
21487 (define_insn "sse2_movhpd"
21488 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21490 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
21491 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
21493 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
21494 "movhpd\t{%2, %0|%0, %2}"
21495 [(set_attr "type" "ssecvt")
21496 (set_attr "mode" "V2DF")])
21498 (define_insn "sse2_movlpd"
21499 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
21501 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
21502 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
21504 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
21505 "movlpd\t{%2, %0|%0, %2}"
21506 [(set_attr "type" "ssecvt")
21507 (set_attr "mode" "V2DF")])
21509 (define_insn "sse2_loadsd"
21510 [(set (match_operand:V2DF 0 "register_operand" "=x")
21512 (match_operand:DF 1 "memory_operand" "m")
21513 (vec_duplicate:DF (float:DF (const_int 0)))
21516 "movsd\t{%1, %0|%0, %1}"
21517 [(set_attr "type" "ssecvt")
21518 (set_attr "mode" "DF")])
21520 (define_insn "sse2_movsd"
21521 [(set (match_operand:V2DF 0 "register_operand" "=x")
21523 (match_operand:V2DF 1 "register_operand" "0")
21524 (match_operand:V2DF 2 "register_operand" "x")
21527 "movsd\t{%2, %0|%0, %2}"
21528 [(set_attr "type" "ssecvt")
21529 (set_attr "mode" "DF")])
21531 (define_insn "sse2_storesd"
21532 [(set (match_operand:DF 0 "memory_operand" "=m")
21534 (match_operand:V2DF 1 "register_operand" "x")
21535 (parallel [(const_int 0)])))]
21537 "movsd\t{%1, %0|%0, %1}"
21538 [(set_attr "type" "ssecvt")
21539 (set_attr "mode" "DF")])
21541 (define_insn "sse2_shufpd"
21542 [(set (match_operand:V2DF 0 "register_operand" "=x")
21543 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
21544 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
21545 (match_operand:SI 3 "immediate_operand" "i")]
21548 ;; @@@ check operand order for intel/nonintel syntax
21549 "shufpd\t{%3, %2, %0|%0, %2, %3}"
21550 [(set_attr "type" "ssecvt")
21551 (set_attr "mode" "V2DF")])
21553 (define_insn "sse2_clflush"
21554 [(unspec_volatile [(match_operand:SI 0 "address_operand" "p")]
21558 [(set_attr "type" "sse")
21559 (set_attr "memory" "unknown")])
21561 (define_expand "sse2_mfence"
21562 [(set (match_dup 0)
21563 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
21566 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21567 MEM_VOLATILE_P (operands[0]) = 1;
21570 (define_insn "*mfence_insn"
21571 [(set (match_operand:BLK 0 "" "")
21572 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
21575 [(set_attr "type" "sse")
21576 (set_attr "memory" "unknown")])
21578 (define_expand "sse2_lfence"
21579 [(set (match_dup 0)
21580 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
21583 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21584 MEM_VOLATILE_P (operands[0]) = 1;
21587 (define_insn "*lfence_insn"
21588 [(set (match_operand:BLK 0 "" "")
21589 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
21592 [(set_attr "type" "sse")
21593 (set_attr "memory" "unknown")])