1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
91 extern const struct processor_costs *ix86_cost;
93 /* Run-time compilation parameters selecting different hardware subsets. */
95 extern int target_flags;
97 /* Macros used in the machine description to test the flags. */
99 /* configure can arrange to make this 2, to force a 486. */
101 #ifndef TARGET_CPU_DEFAULT
102 #define TARGET_CPU_DEFAULT 0
105 /* Masks for the -m switches */
106 #define MASK_80387 0x00000001 /* Hardware floating point */
107 #define MASK_RTD 0x00000002 /* Use ret that pops args */
108 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
109 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
110 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
111 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
112 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
113 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
114 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
115 #define MASK_NO_ALIGN_STROPS 0x00001000 /* Enable aligning of string ops. */
116 #define MASK_INLINE_ALL_STROPS 0x00002000 /* Inline stringops in all cases */
117 #define MASK_NO_PUSH_ARGS 0x00004000 /* Use push instructions */
118 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00008000/* Accumulate outgoing args */
119 #define MASK_NO_ACCUMULATE_OUTGOING_ARGS 0x00010000
120 #define MASK_MMX 0x00020000 /* Support MMX regs/builtins */
121 #define MASK_SSE 0x00040000 /* Support SSE regs/builtins */
122 #define MASK_SSE2 0x00080000 /* Support SSE2 regs/builtins */
123 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
124 #define MASK_3DNOW_A 0x00200000 /* Support Athlon 3Dnow builtins */
125 #define MASK_128BIT_LONG_DOUBLE 0x00400000 /* long double size is 128bit */
126 #define MASK_MIX_SSE_I387 0x00800000 /* Mix SSE and i387 instructions */
127 #define MASK_64BIT 0x01000000 /* Produce 64bit code */
128 #define MASK_NO_RED_ZONE 0x02000000 /* Do not use red zone */
130 /* Temporary codegen switches */
131 #define MASK_INTEL_SYNTAX 0x00000200
132 #define MASK_DEBUG_ARG 0x00000400 /* function_arg */
133 #define MASK_DEBUG_ADDR 0x00000800 /* GO_IF_LEGITIMATE_ADDRESS */
135 /* Use the floating point instructions */
136 #define TARGET_80387 (target_flags & MASK_80387)
138 /* Compile using ret insn that pops args.
139 This will not work unless you use prototypes at least
140 for all functions that can take varying numbers of args. */
141 #define TARGET_RTD (target_flags & MASK_RTD)
143 /* Align doubles to a two word boundary. This breaks compatibility with
144 the published ABI's for structures containing doubles, but produces
145 faster code on the pentium. */
146 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
148 /* Use push instructions to save outgoing args. */
149 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
151 /* Accumulate stack adjustments to prologue/epilogue. */
152 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
153 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
155 /* Put uninitialized locals into bss, not data.
156 Meaningful only on svr3. */
157 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
159 /* Use IEEE floating point comparisons. These handle correctly the cases
160 where the result of a comparison is unordered. Normally SIGFPE is
161 generated in such cases, in which case this isn't needed. */
162 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
164 /* Functions that return a floating point value may return that value
165 in the 387 FPU or in 386 integer registers. If set, this flag causes
166 the 387 to be used, which is compatible with most calling conventions. */
167 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
169 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
170 This mode wastes cache, but avoid missaligned data accesses and simplifies
171 address calculations. */
172 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
174 /* Disable generation of FP sin, cos and sqrt operations for 387.
175 This is because FreeBSD lacks these in the math-emulator-code */
176 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
178 /* Don't create frame pointers for leaf functions */
179 #define TARGET_OMIT_LEAF_FRAME_POINTER \
180 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
182 /* Debug GO_IF_LEGITIMATE_ADDRESS */
183 #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
185 /* Debug FUNCTION_ARG macros */
186 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
188 /* 64bit Sledgehammer mode */
189 #ifdef TARGET_BI_ARCH
190 #define TARGET_64BIT (target_flags & MASK_64BIT)
192 #ifdef TARGET_64BIT_DEFAULT
193 #define TARGET_64BIT 1
195 #define TARGET_64BIT 0
199 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
200 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
201 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
202 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
203 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
204 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
205 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
207 #define CPUMASK (1 << ix86_cpu)
208 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
209 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
210 extern const int x86_branch_hints, x86_unroll_strlen;
211 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
212 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
213 extern const int x86_use_cltd, x86_read_modify_write;
214 extern const int x86_read_modify, x86_split_long_moves;
215 extern const int x86_promote_QImode, x86_single_stringop;
216 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
217 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
218 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
219 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
220 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
221 extern const int x86_epilogue_using_move;
223 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
224 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
225 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
226 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
227 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
228 /* For sane SSE instruction set generation we need fcomi instruction. It is
229 safe to enable all CMOVE instructions. */
230 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
231 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
232 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
233 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
234 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
235 #define TARGET_MOVX (x86_movx & CPUMASK)
236 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
237 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
238 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
239 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
240 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
241 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
242 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
243 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
244 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
245 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
246 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
247 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
248 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
249 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
250 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
251 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
252 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
253 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
254 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
255 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
256 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
257 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
258 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
260 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
262 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
263 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
265 #define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
267 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
268 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
269 #define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
270 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
271 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
272 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
274 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
276 #define TARGET_SWITCHES \
277 { { "80387", MASK_80387, N_("Use hardware fp") }, \
278 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
279 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
280 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
281 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
282 { "386", 0, N_("Same as -mcpu=i386") }, \
283 { "486", 0, N_("Same as -mcpu=i486") }, \
284 { "pentium", 0, N_("Same as -mcpu=pentium") }, \
285 { "pentiumpro", 0, N_("Same as -mcpu=pentiumpro") }, \
287 N_("Alternate calling convention") }, \
288 { "no-rtd", -MASK_RTD, \
289 N_("Use normal calling convention") }, \
290 { "align-double", MASK_ALIGN_DOUBLE, \
291 N_("Align some doubles on dword boundary") }, \
292 { "no-align-double", -MASK_ALIGN_DOUBLE, \
293 N_("Align doubles on word boundary") }, \
294 { "svr3-shlib", MASK_SVR3_SHLIB, \
295 N_("Uninitialized locals in .bss") }, \
296 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
297 N_("Uninitialized locals in .data") }, \
298 { "ieee-fp", MASK_IEEE_FP, \
299 N_("Use IEEE math for fp comparisons") }, \
300 { "no-ieee-fp", -MASK_IEEE_FP, \
301 N_("Do not use IEEE math for fp comparisons") }, \
302 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
303 N_("Return values of functions in FPU registers") }, \
304 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
305 N_("Do not return values of functions in FPU registers")}, \
306 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
307 N_("Do not generate sin, cos, sqrt for FPU") }, \
308 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
309 N_("Generate sin, cos, sqrt for FPU")}, \
310 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
311 N_("Omit the frame pointer in leaf functions") }, \
312 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
313 { "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
314 { "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
315 { "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \
316 { "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \
317 { "stack-arg-probe", MASK_STACK_PROBE, \
318 N_("Enable stack probing") }, \
319 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
320 { "windows", 0, 0 /* undocumented */ }, \
321 { "dll", 0, 0 /* undocumented */ }, \
322 { "intel-syntax", MASK_INTEL_SYNTAX, \
323 N_("Emit Intel syntax assembler opcodes") }, \
324 { "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
325 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
326 N_("Align destination of the string operations") }, \
327 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
328 N_("Do not align destination of the string operations") }, \
329 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
330 N_("Inline all known string operations") }, \
331 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
332 N_("Do not inline all known string operations") }, \
333 { "push-args", -MASK_NO_PUSH_ARGS, \
334 N_("Use push instructions to save outgoing arguments") }, \
335 { "no-push-args", MASK_NO_PUSH_ARGS, \
336 N_("Do not use push instructions to save outgoing arguments") }, \
337 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
338 N_("Use push instructions to save outgoing arguments") }, \
339 { "no-accumulate-outgoing-args",MASK_NO_ACCUMULATE_OUTGOING_ARGS, \
340 N_("Do not use push instructions to save outgoing arguments") }, \
341 { "mmx", MASK_MMX, N_("Support MMX builtins") }, \
342 { "no-mmx", -MASK_MMX, \
343 N_("Do not support MMX builtins") }, \
344 { "3dnow", MASK_3DNOW, \
345 N_("Support 3DNow! builtins") }, \
346 { "no-3dnow", -MASK_3DNOW, \
347 N_("Do not support 3DNow! builtins") }, \
349 N_("Support MMX and SSE builtins and code generation") }, \
350 { "no-sse", -MASK_SSE, \
351 N_("Do not support MMX and SSE builtins and code generation") }, \
352 { "sse2", MASK_SSE2, \
353 N_("Support MMX, SSE and SSE2 builtins and code generation") }, \
354 { "no-sse2", -MASK_SSE2, \
355 N_("Do not support MMX, SSE and SSE2 builtins and code generation") }, \
356 { "mix-sse-i387", MASK_MIX_SSE_I387, \
357 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
358 { "no-mix-sse-i387", -MASK_MIX_SSE_I387, \
359 N_("Do not use both SSE and i387 instruction sets for floating point arithmetics") },\
360 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
361 N_("sizeof(long double) is 16.") }, \
362 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
363 N_("sizeof(long double) is 12.") }, \
364 { "64", MASK_64BIT, \
365 N_("Generate 64bit x86-64 code") }, \
366 { "32", -MASK_64BIT, \
367 N_("Generate 32bit i386 code") }, \
368 { "red-zone", -MASK_NO_RED_ZONE, \
369 N_("Use red-zone in the x86-64 code") }, \
370 { "no-red-zone", MASK_NO_RED_ZONE, \
371 N_("Do not use red-zone in the x86-64 code") }, \
373 { "", TARGET_DEFAULT, 0 }}
375 #ifdef TARGET_64BIT_DEFAULT
376 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
378 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
381 /* Which processor to schedule for. The cpu attribute defines a list that
382 mirrors this list, so changes to i386.md must be made at the same time. */
386 PROCESSOR_I386, /* 80386 */
387 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
389 PROCESSOR_PENTIUMPRO,
396 extern enum processor_type ix86_cpu;
398 extern int ix86_arch;
400 /* This macro is similar to `TARGET_SWITCHES' but defines names of
401 command options that have values. Its definition is an
402 initializer with a subgrouping for each command option.
404 Each subgrouping contains a string constant, that defines the
405 fixed part of the option name, and the address of a variable. The
406 variable, type `char *', is set to the variable part of the given
407 option if the fixed part matches. The actual option name is made
408 by appending `-m' to the specified name. */
409 #define TARGET_OPTIONS \
410 { { "cpu=", &ix86_cpu_string, \
411 N_("Schedule code for given CPU")}, \
412 { "arch=", &ix86_arch_string, \
413 N_("Generate code for given CPU")}, \
414 { "regparm=", &ix86_regparm_string, \
415 N_("Number of registers used to pass integer arguments") }, \
416 { "align-loops=", &ix86_align_loops_string, \
417 N_("Loop code aligned to this power of 2") }, \
418 { "align-jumps=", &ix86_align_jumps_string, \
419 N_("Jump targets are aligned to this power of 2") }, \
420 { "align-functions=", &ix86_align_funcs_string, \
421 N_("Function starts are aligned to this power of 2") }, \
422 { "preferred-stack-boundary=", \
423 &ix86_preferred_stack_boundary_string, \
424 N_("Attempt to keep stack aligned to this power of 2") }, \
425 { "branch-cost=", &ix86_branch_cost_string, \
426 N_("Branches are this expensive (1-5, arbitrary units)") }, \
427 { "cmodel=", &ix86_cmodel_string, \
428 N_("Use given x86-64 code model") }, \
432 /* Sometimes certain combinations of command options do not make
433 sense on a particular target machine. You can define a macro
434 `OVERRIDE_OPTIONS' to take account of this. This macro, if
435 defined, is executed once just after all the command options have
438 Don't use this macro to turn on various extra optimizations for
439 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
441 #define OVERRIDE_OPTIONS override_options ()
443 /* These are meant to be redefined in the host dependent files */
444 #define SUBTARGET_SWITCHES
445 #define SUBTARGET_OPTIONS
447 /* Define this to change the optimizations performed by default. */
448 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
450 /* Specs for the compiler proper */
453 #define CC1_CPU_SPEC "\
456 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
458 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
459 %{mpentium:-mcpu=pentium \
460 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
461 %{mpentiumpro:-mcpu=pentiumpro \
462 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}}"
465 #ifndef CPP_CPU_DEFAULT_SPEC
466 #if TARGET_CPU_DEFAULT == 1
467 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
469 #if TARGET_CPU_DEFAULT == 2
470 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
472 #if TARGET_CPU_DEFAULT == 3
473 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
475 #if TARGET_CPU_DEFAULT == 4
476 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
478 #if TARGET_CPU_DEFAULT == 5
479 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
481 #if TARGET_CPU_DEFAULT == 6
482 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
484 #ifndef CPP_CPU_DEFAULT_SPEC
485 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
487 #endif /* CPP_CPU_DEFAULT_SPEC */
489 #ifdef TARGET_BI_ARCH
490 #define NO_BUILTIN_SIZE_TYPE
491 #define NO_BUILTIN_PTRDIFF_TYPE
494 #ifdef NO_BUILTIN_SIZE_TYPE
495 #define CPP_CPU32_SIZE_TYPE_SPEC \
496 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
497 #define CPP_CPU64_SIZE_TYPE_SPEC \
498 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
500 #define CPP_CPU32_SIZE_TYPE_SPEC ""
501 #define CPP_CPU64_SIZE_TYPE_SPEC ""
504 #define CPP_CPU32_SPEC \
505 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
506 -D__i386__ %(cpp_cpu32sizet)"
508 #define CPP_CPU64_SPEC \
509 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
511 #define CPP_CPUCOMMON_SPEC "\
512 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
513 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
514 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
515 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
516 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
517 -D__pentiumpro -D__pentiumpro__ \
518 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
519 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
520 %{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
521 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
522 %{m386|mcpu=i386:-D__tune_i386__ }\
523 %{m486|mcpu=i486:-D__tune_i486__ }\
524 %{mpentium|mcpu=pentium|mcpu=i586:-D__tune_i586__ -D__tune_pentium__ }\
525 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_i686__ -D__tune_pentiumpro__ }\
526 %{mcpu=k6:-D__tune_k6__ }\
527 %{mcpu=athlon:-D__tune_athlon__ }\
528 %{mcpu=pentium4:-D__tune_pentium4__ }\
529 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
532 #ifdef TARGET_BI_ARCH
533 #ifdef TARGET_64BIT_DEFAULT
534 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
536 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
539 #ifdef TARGET_64BIT_DEFAULT
540 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
542 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
548 #define CC1_SPEC "%(cc1_cpu) "
551 /* This macro defines names of additional specifications to put in the
552 specs that can be used in various specifications like CC1_SPEC. Its
553 definition is an initializer with a subgrouping for each command option.
555 Each subgrouping contains a string constant, that defines the
556 specification name, and a string constant that used by the GNU CC driver
559 Do not define this macro if it does not need to do anything. */
561 #ifndef SUBTARGET_EXTRA_SPECS
562 #define SUBTARGET_EXTRA_SPECS
565 #define EXTRA_SPECS \
566 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
567 { "cpp_cpu", CPP_CPU_SPEC }, \
568 { "cpp_cpu32", CPP_CPU32_SPEC }, \
569 { "cpp_cpu64", CPP_CPU64_SPEC }, \
570 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
571 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
572 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
573 { "cc1_cpu", CC1_CPU_SPEC }, \
574 SUBTARGET_EXTRA_SPECS
576 /* target machine storage layout */
578 /* Define for XFmode or TFmode extended real floating point support.
579 This will automatically cause REAL_ARITHMETIC to be defined.
581 The XFmode is specified by i386 ABI, while TFmode may be faster
582 due to alignment and simplifications in the address calculations.
584 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
585 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
587 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
589 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
591 /* Tell real.c that this is the 80-bit Intel extended float format
592 packaged in a 128-bit or 96bit entity. */
593 #define INTEL_EXTENDED_IEEE_FORMAT 1
596 #define SHORT_TYPE_SIZE 16
597 #define INT_TYPE_SIZE 32
598 #define FLOAT_TYPE_SIZE 32
599 #define LONG_TYPE_SIZE BITS_PER_WORD
600 #define MAX_WCHAR_TYPE_SIZE 32
601 #define DOUBLE_TYPE_SIZE 64
602 #define LONG_LONG_TYPE_SIZE 64
604 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
605 #define MAX_BITS_PER_WORD 64
606 #define MAX_LONG_TYPE_SIZE 64
608 #define MAX_BITS_PER_WORD 32
609 #define MAX_LONG_TYPE_SIZE 32
612 /* Define if you don't want extended real, but do want to use the
613 software floating point emulator for REAL_ARITHMETIC and
614 decimal <-> binary conversion. */
615 /* #define REAL_ARITHMETIC */
617 /* Define this if most significant byte of a word is the lowest numbered. */
618 /* That is true on the 80386. */
620 #define BITS_BIG_ENDIAN 0
622 /* Define this if most significant byte of a word is the lowest numbered. */
623 /* That is not true on the 80386. */
624 #define BYTES_BIG_ENDIAN 0
626 /* Define this if most significant word of a multiword number is the lowest
628 /* Not true for 80386 */
629 #define WORDS_BIG_ENDIAN 0
631 /* number of bits in an addressable storage unit */
632 #define BITS_PER_UNIT 8
634 /* Width in bits of a "word", which is the contents of a machine register.
635 Note that this is not necessarily the width of data type `int';
636 if using 16-bit ints on a 80386, this would still be 32.
637 But on a machine with 16-bit registers, this would be 16. */
638 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
640 /* Width of a word, in units (bytes). */
641 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
642 #define MIN_UNITS_PER_WORD 4
644 /* Width in bits of a pointer.
645 See also the macro `Pmode' defined below. */
646 #define POINTER_SIZE BITS_PER_WORD
648 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
649 #define PARM_BOUNDARY BITS_PER_WORD
651 /* Boundary (in *bits*) on which stack pointer should be aligned. */
652 #define STACK_BOUNDARY BITS_PER_WORD
654 /* Boundary (in *bits*) on which the stack pointer preferrs to be
655 aligned; the compiler cannot rely on having this alignment. */
656 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
658 /* As of July 2001, many runtimes to not align the stack properly when
659 entering main. This causes expand_main_function to forcably align
660 the stack, which results in aligned frames for functions called from
661 main, though it does nothing for the alignment of main itself. */
662 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
663 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
665 /* Allocation boundary for the code of a function. */
666 #define FUNCTION_BOUNDARY 16
668 /* Alignment of field after `int : 0' in a structure. */
670 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
672 /* Minimum size in bits of the largest boundary to which any
673 and all fundamental data types supported by the hardware
674 might need to be aligned. No data type wants to be aligned
677 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
678 and Pentium Pro XFmode values at 128 bit boundaries. */
680 #define BIGGEST_ALIGNMENT 128
682 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
683 #define ALIGN_MODE_128(MODE) \
684 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
685 || (MODE) == V4SFmode || (MODE) == V4SImode)
687 /* The published ABIs say that doubles should be aligned on word
688 boundaries, so lower the aligment for structure fields unless
689 -malign-double is set. */
690 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
691 constant. Use the smaller value in that context. */
692 #ifndef IN_TARGET_LIBS
693 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
695 #define BIGGEST_FIELD_ALIGNMENT 32
698 /* If defined, a C expression to compute the alignment given to a
699 constant that is being placed in memory. EXP is the constant
700 and ALIGN is the alignment that the object would ordinarily have.
701 The value of this macro is used instead of that alignment to align
704 If this macro is not defined, then ALIGN is used.
706 The typical use of this macro is to increase alignment for string
707 constants to be word aligned so that `strcpy' calls that copy
708 constants can be done inline. */
710 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
712 /* If defined, a C expression to compute the alignment for a static
713 variable. TYPE is the data type, and ALIGN is the alignment that
714 the object would ordinarily have. The value of this macro is used
715 instead of that alignment to align the object.
717 If this macro is not defined, then ALIGN is used.
719 One use of this macro is to increase alignment of medium-size
720 data to make it all fit in fewer cache lines. Another is to
721 cause character arrays to be word-aligned so that `strcpy' calls
722 that copy constants to character arrays can be done inline. */
724 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
726 /* If defined, a C expression to compute the alignment for a local
727 variable. TYPE is the data type, and ALIGN is the alignment that
728 the object would ordinarily have. The value of this macro is used
729 instead of that alignment to align the object.
731 If this macro is not defined, then ALIGN is used.
733 One use of this macro is to increase alignment of medium-size
734 data to make it all fit in fewer cache lines. */
736 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
738 /* If defined, a C expression that gives the alignment boundary, in
739 bits, of an argument with the specified mode and type. If it is
740 not defined, `PARM_BOUNDARY' is used for all arguments. */
742 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) ix86_function_arg_boundary (MODE, TYPE)
744 /* Set this non-zero if move instructions will actually fail to work
745 when given unaligned data. */
746 #define STRICT_ALIGNMENT 0
748 /* If bit field type is int, don't let it cross an int,
749 and give entire struct the alignment of an int. */
750 /* Required on the 386 since it doesn't have bitfield insns. */
751 #define PCC_BITFIELD_TYPE_MATTERS 1
753 /* Standard register usage. */
755 /* This processor has special stack-like registers. See reg-stack.c
759 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode \
760 || mode==XFmode || mode==TFmode)
762 /* Number of actual hardware registers.
763 The hardware registers are assigned numbers for the compiler
764 from 0 to just below FIRST_PSEUDO_REGISTER.
765 All registers that the compiler knows about must be given numbers,
766 even those that are not normally considered general registers.
768 In the 80386 we give the 8 general purpose registers the numbers 0-7.
769 We number the floating point registers 8-15.
770 Note that registers 0-7 can be accessed as a short or int,
771 while only 0-3 may be used with byte `mov' instructions.
773 Reg 16 does not correspond to any hardware register, but instead
774 appears in the RTL as an argument pointer prior to reload, and is
775 eliminated during reloading in favor of either the stack or frame
778 #define FIRST_PSEUDO_REGISTER 53
780 /* Number of hardware registers that go into the DWARF-2 unwind info.
781 If not defined, equals FIRST_PSEUDO_REGISTER. */
783 #define DWARF_FRAME_REGISTERS 17
785 /* 1 for registers that have pervasive standard uses
786 and are not available for the register allocator.
787 On the 80386, the stack pointer is such, as is the arg pointer.
789 The value is an mask - bit 1 is set for fixed registers
790 for 32bit target, while 2 is set for fixed registers for 64bit.
791 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
793 #define FIXED_REGISTERS \
794 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
795 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
796 /*arg,flags,fpsr,dir,frame*/ \
798 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
799 0, 0, 0, 0, 0, 0, 0, 0, \
800 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
801 0, 0, 0, 0, 0, 0, 0, 0, \
802 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
803 1, 1, 1, 1, 1, 1, 1, 1, \
804 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
805 1, 1, 1, 1, 1, 1, 1, 1}
808 /* 1 for registers not available across function calls.
809 These must include the FIXED_REGISTERS and also any
810 registers that can be used without being saved.
811 The latter must include the registers where values are returned
812 and the register where structure-value addresses are passed.
813 Aside from that, you can include as many other registers as you like.
815 The value is an mask - bit 1 is set for call used
816 for 32bit target, while 2 is set for call used for 64bit.
817 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
819 #define CALL_USED_REGISTERS \
820 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
821 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
822 /*arg,flags,fpsr,dir,frame*/ \
824 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
825 3, 3, 3, 3, 3, 3, 3, 3, \
826 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
827 3, 3, 3, 3, 3, 3, 3, 3, \
828 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
829 3, 3, 3, 3, 1, 1, 1, 1, \
830 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
831 3, 3, 3, 3, 3, 3, 3, 3} \
833 /* Order in which to allocate registers. Each register must be
834 listed once, even those in FIXED_REGISTERS. List frame pointer
835 late and fixed registers last. Note that, in general, we prefer
836 registers listed in CALL_USED_REGISTERS, keeping the others
837 available for storage of persistent values.
839 Three different versions of REG_ALLOC_ORDER have been tried:
841 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
842 but slower code on simple functions returning values in eax.
844 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
845 perl 4.036 due to not being able to create a DImode register (to hold a 2
848 If the order is eax, edx, ecx, ... it produces better code for simple
849 functions, and a slightly slower compiler. Users complained about the code
850 generated by allocating edx first, so restore the 'natural' order of things. */
852 #define REG_ALLOC_ORDER \
855 /* bx,si,di,bp,sp,*/ \
859 /*r12,r15,r14,r13*/ \
861 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
862 21, 22, 23, 24, 25, 26, 27, 28, \
863 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
864 45, 46, 47, 48, 49, 50, 51, 52, \
865 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
866 8, 9, 10, 11, 12, 13, 14, 15, \
867 /*,arg,cc,fpsr,dir,frame*/ \
869 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
870 29, 30, 31, 32, 33, 34, 35, 36 }
872 /* Macro to conditionally modify fixed_regs/call_used_regs. */
873 #define CONDITIONAL_REGISTER_USAGE \
876 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
878 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
879 call_used_regs[i] = (call_used_regs[i] \
880 & (TARGET_64BIT ? 2 : 1)) != 0; \
884 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
885 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
890 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
891 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
892 fixed_regs[i] = call_used_regs[i] = 1; \
897 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
898 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
899 fixed_regs[i] = call_used_regs[i] = 1; \
901 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
905 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
906 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
907 if (TEST_HARD_REG_BIT (x, i)) \
908 fixed_regs[i] = call_used_regs[i] = 1; \
912 /* Return number of consecutive hard regs needed starting at reg REGNO
913 to hold something of mode MODE.
914 This is ordinarily the length in words of a value of mode MODE
915 but can be less for certain modes in special long registers.
917 Actually there are no two word move instructions for consecutive
918 registers. And only registers 0-3 may have mov byte instructions
922 #define HARD_REGNO_NREGS(REGNO, MODE) \
923 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
924 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
926 ? (TARGET_64BIT ? 2 : 3) \
928 ? (TARGET_64BIT ? 4 : 6) \
929 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
931 #define VALID_SSE_REG_MODE(MODE) \
932 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
933 || (MODE) == SFmode \
934 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
936 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
937 ((MODE) == V2SFmode || (MODE) == SFmode)
939 #define VALID_MMX_REG_MODE(MODE) \
940 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
941 || (MODE) == V2SImode || (MODE) == SImode)
943 #define VECTOR_MODE_SUPPORTED_P(MODE) \
944 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
945 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
946 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
948 #define VALID_FP_MODE_P(mode) \
949 ((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
950 || (!TARGET_64BIT && (mode) == XFmode) \
951 || (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
952 || (!TARGET_64BIT && (mode) == XCmode))
954 #define VALID_INT_MODE_P(mode) \
955 ((mode) == QImode || (mode) == HImode || (mode) == SImode \
956 || (mode) == DImode \
957 || (mode) == CQImode || (mode) == CHImode || (mode) == CSImode \
958 || (mode) == CDImode \
959 || (TARGET_64BIT && ((mode) == TImode || (mode) == CTImode)))
961 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
963 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
964 ix86_hard_regno_mode_ok (REGNO, MODE)
966 /* Value is 1 if it is a good idea to tie two pseudo registers
967 when one has mode MODE1 and one has mode MODE2.
968 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
969 for any hard reg, then this must be 0 for correct output. */
971 #define MODES_TIEABLE_P(MODE1, MODE2) \
972 ((MODE1) == (MODE2) \
973 || (((MODE1) == HImode || (MODE1) == SImode \
974 || ((MODE1) == QImode \
975 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
976 || ((MODE1) == DImode && TARGET_64BIT)) \
977 && ((MODE2) == HImode || (MODE2) == SImode \
978 || ((MODE1) == QImode \
979 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
980 || ((MODE2) == DImode && TARGET_64BIT))))
983 /* Specify the modes required to caller save a given hard regno.
984 We do this on i386 to prevent flags from being saved at all.
986 Kill any attempts to combine saving of modes. */
988 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
989 (CC_REGNO_P (REGNO) ? VOIDmode \
990 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
991 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
992 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
993 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
995 /* Specify the registers used for certain standard purposes.
996 The values of these macros are register numbers. */
998 /* on the 386 the pc register is %eip, and is not usable as a general
999 register. The ordinary mov instructions won't work */
1000 /* #define PC_REGNUM */
1002 /* Register to use for pushing function arguments. */
1003 #define STACK_POINTER_REGNUM 7
1005 /* Base register for access to local variables of the function. */
1006 #define HARD_FRAME_POINTER_REGNUM 6
1008 /* Base register for access to local variables of the function. */
1009 #define FRAME_POINTER_REGNUM 20
1011 /* First floating point reg */
1012 #define FIRST_FLOAT_REG 8
1014 /* First & last stack-like regs */
1015 #define FIRST_STACK_REG FIRST_FLOAT_REG
1016 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1018 #define FLAGS_REG 17
1020 #define DIRFLAG_REG 19
1022 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1023 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1025 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1026 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1028 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1029 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1031 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1032 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1034 /* Value should be nonzero if functions must have frame pointers.
1035 Zero means the frame pointer need not be set up (and parms
1036 may be accessed via the stack pointer) in functions that seem suitable.
1037 This is computed in `reload', in reload1.c. */
1038 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1040 /* Override this in other tm.h files to cope with various OS losage
1041 requiring a frame pointer. */
1042 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1043 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1046 /* Make sure we can access arbitrary call frames. */
1047 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1049 /* Base register for access to arguments of the function. */
1050 #define ARG_POINTER_REGNUM 16
1052 /* Register in which static-chain is passed to a function.
1053 We do use ECX as static chain register for 32 bit ABI. On the
1054 64bit ABI, ECX is an argument register, so we use R10 instead. */
1055 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1057 /* Register to hold the addressing base for position independent
1058 code access to data items.
1059 We don't use PIC pointer for 64bit mode. Define the regnum to
1060 dummy value to prevent gcc from pesimizing code dealing with EBX.
1062 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
1064 /* Register in which address to store a structure value
1065 arrives in the function. On the 386, the prologue
1066 copies this from the stack to register %eax. */
1067 #define STRUCT_VALUE_INCOMING 0
1069 /* Place in which caller passes the structure value address.
1070 0 means push the value on the stack like an argument. */
1071 #define STRUCT_VALUE 0
1073 /* A C expression which can inhibit the returning of certain function
1074 values in registers, based on the type of value. A nonzero value
1075 says to return the function value in memory, just as large
1076 structures are always returned. Here TYPE will be a C expression
1077 of type `tree', representing the data type of the value.
1079 Note that values of mode `BLKmode' must be explicitly handled by
1080 this macro. Also, the option `-fpcc-struct-return' takes effect
1081 regardless of this macro. On most systems, it is possible to
1082 leave the macro undefined; this causes a default definition to be
1083 used, whose value is the constant 1 for `BLKmode' values, and 0
1086 Do not use this macro to indicate that structures and unions
1087 should always be returned in memory. You should instead use
1088 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1090 #define RETURN_IN_MEMORY(TYPE) \
1091 ix86_return_in_memory (TYPE)
1094 /* Define the classes of registers for register constraints in the
1095 machine description. Also define ranges of constants.
1097 One of the classes must always be named ALL_REGS and include all hard regs.
1098 If there is more than one class, another class must be named NO_REGS
1099 and contain no registers.
1101 The name GENERAL_REGS must be the name of a class (or an alias for
1102 another name such as ALL_REGS). This is the class of registers
1103 that is allowed by "g" or "r" in a register constraint.
1104 Also, registers outside this class are allocated only when
1105 instructions express preferences for them.
1107 The classes must be numbered in nondecreasing order; that is,
1108 a larger-numbered class must never be contained completely
1109 in a smaller-numbered class.
1111 For any two classes, it is very desirable that there be another
1112 class that represents their union.
1114 It might seem that class BREG is unnecessary, since no useful 386
1115 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1116 and the "b" register constraint is useful in asms for syscalls.
1118 The flags and fpsr registers are in no class. */
1123 AREG, DREG, CREG, BREG, SIREG, DIREG,
1124 AD_REGS, /* %eax/%edx for DImode */
1125 Q_REGS, /* %eax %ebx %ecx %edx */
1126 NON_Q_REGS, /* %esi %edi %ebp %esp */
1127 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1128 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1129 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1130 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1140 ALL_REGS, LIM_REG_CLASSES
1143 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1145 #define INTEGER_CLASS_P(CLASS) (reg_class_subset_p (CLASS, GENERAL_REGS))
1146 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
1147 #define SSE_CLASS_P(CLASS) (reg_class_subset_p (CLASS, SSE_REGS))
1148 #define MMX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, MMX_REGS))
1149 #define MAYBE_INTEGER_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, GENERAL_REGS))
1150 #define MAYBE_FLOAT_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, FLOAT_REGS))
1151 #define MAYBE_SSE_CLASS_P(CLASS) (reg_classes_intersect_p (SSE_REGS, CLASS))
1152 #define MAYBE_MMX_CLASS_P(CLASS) (reg_classes_intersect_p (MMX_REGS, CLASS))
1154 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
1156 /* Give names of register classes as strings for dump file. */
1158 #define REG_CLASS_NAMES \
1160 "AREG", "DREG", "CREG", "BREG", \
1163 "Q_REGS", "NON_Q_REGS", \
1167 "FP_TOP_REG", "FP_SECOND_REG", \
1171 "FP_TOP_SSE_REGS", \
1172 "FP_SECOND_SSE_REGS", \
1176 "FLOAT_INT_SSE_REGS", \
1179 /* Define which registers fit in which classes.
1180 This is an initializer for a vector of HARD_REG_SET
1181 of length N_REG_CLASSES. */
1183 #define REG_CLASS_CONTENTS \
1185 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1186 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1187 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1188 { 0x03, 0x0 }, /* AD_REGS */ \
1189 { 0x0f, 0x0 }, /* Q_REGS */ \
1190 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1191 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1192 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1193 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1194 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1195 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1196 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1197 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1198 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1199 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1200 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1201 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1202 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1203 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1204 { 0xffffffff,0x1fffff } \
1207 /* The same information, inverted:
1208 Return the class number of the smallest class containing
1209 reg number REGNO. This could be a conditional expression
1210 or could index an array. */
1212 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1214 /* When defined, the compiler allows registers explicitly used in the
1215 rtl to be used as spill registers but prevents the compiler from
1216 extending the lifetime of these registers. */
1218 #define SMALL_REGISTER_CLASSES 1
1220 #define QI_REG_P(X) \
1221 (REG_P (X) && REGNO (X) < 4)
1223 #define GENERAL_REGNO_P(n) \
1224 ((n) < 8 || REX_INT_REGNO_P (n))
1226 #define GENERAL_REG_P(X) \
1227 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1229 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1231 #define NON_QI_REG_P(X) \
1232 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1234 #define REX_INT_REGNO_P(n) ((n) >= FIRST_REX_INT_REG && (n) <= LAST_REX_INT_REG)
1235 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1237 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1238 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
1239 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1240 #define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
1242 #define SSE_REGNO_P(n) \
1243 (((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG) \
1244 || ((n) >= FIRST_REX_SSE_REG && (n) <= LAST_REX_SSE_REG))
1246 #define SSE_REGNO(n) \
1247 ((n) < 8 ? FIRST_SSE_REG + (n) : FIRST_REX_SSE_REG + (n) - 8)
1248 #define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
1250 #define SSE_FLOAT_MODE_P(m) \
1251 ((TARGET_SSE && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
1253 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
1254 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
1256 #define STACK_REG_P(xop) (REG_P (xop) && \
1257 REGNO (xop) >= FIRST_STACK_REG && \
1258 REGNO (xop) <= LAST_STACK_REG)
1260 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
1262 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
1264 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1265 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1267 /* Indicate whether hard register numbered REG_NO should be converted
1269 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1270 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1272 /* The class value for index registers, and the one for base regs. */
1274 #define INDEX_REG_CLASS INDEX_REGS
1275 #define BASE_REG_CLASS GENERAL_REGS
1277 /* Get reg_class from a letter such as appears in the machine description. */
1279 #define REG_CLASS_FROM_LETTER(C) \
1280 ((C) == 'r' ? GENERAL_REGS : \
1281 (C) == 'R' ? LEGACY_REGS : \
1282 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1283 (C) == 'Q' ? Q_REGS : \
1284 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1287 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1290 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1293 (C) == 'a' ? AREG : \
1294 (C) == 'b' ? BREG : \
1295 (C) == 'c' ? CREG : \
1296 (C) == 'd' ? DREG : \
1297 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1298 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1299 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1300 (C) == 'A' ? AD_REGS : \
1301 (C) == 'D' ? DIREG : \
1302 (C) == 'S' ? SIREG : NO_REGS)
1304 /* The letters I, J, K, L and M in a register constraint string
1305 can be used to stand for particular ranges of immediate operands.
1306 This macro defines what the ranges are.
1307 C is the letter, and VALUE is a constant value.
1308 Return 1 if VALUE is in the range specified by C.
1310 I is for non-DImode shifts.
1311 J is for DImode shifts.
1312 K is for signed imm8 operands.
1313 L is for andsi as zero-extending move.
1314 M is for shifts that can be executed by the "lea" opcode.
1315 N is for immedaite operands for out/in instructions (0-255)
1318 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1319 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1320 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1321 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1322 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1323 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1324 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1327 /* Similar, but for floating constants, and defining letters G and H.
1328 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1329 TARGET_387 isn't set, because the stack register converter may need to
1330 load 0.0 into the function value register. */
1332 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1333 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1334 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1336 /* A C expression that defines the optional machine-dependent
1337 constraint letters that can be used to segregate specific types of
1338 operands, usually memory references, for the target machine. Any
1339 letter that is not elsewhere defined and not matched by
1340 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1343 If it is required for a particular target machine, it should
1344 return 1 if VALUE corresponds to the operand type represented by
1345 the constraint letter C. If C is not defined as an extra
1346 constraint, the value returned should be 0 regardless of VALUE. */
1348 #define EXTRA_CONSTRAINT(VALUE, C) \
1349 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1350 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1353 /* Place additional restrictions on the register class to use when it
1354 is necessary to be able to hold a value of mode MODE in a reload
1355 register for which class CLASS would ordinarily be used. */
1357 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1358 ((MODE) == QImode && !TARGET_64BIT \
1359 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1362 /* Given an rtx X being reloaded into a reg required to be
1363 in class CLASS, return the class of reg to actually use.
1364 In general this is just CLASS; but on some machines
1365 in some cases it is preferable to use a more restrictive class.
1366 On the 80386 series, we prevent floating constants from being
1367 reloaded into floating registers (since no move-insn can do that)
1368 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1370 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1371 QImode must go into class Q_REGS.
1372 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1373 movdf to do mem-to-mem moves through integer regs. */
1375 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1376 ix86_preferred_reload_class (X, CLASS)
1378 /* If we are copying between general and FP registers, we need a memory
1379 location. The same is true for SSE and MMX registers. */
1380 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1381 ix86_secondary_memory_needed (CLASS1, CLASS2, MODE, 1)
1383 /* QImode spills from non-QI registers need a scratch. This does not
1384 happen often -- the only example so far requires an uninitialized
1387 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1388 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1391 /* Return the maximum number of consecutive registers
1392 needed to represent mode MODE in a register of class CLASS. */
1393 /* On the 80386, this is the size of MODE in words,
1394 except in the FP regs, where a single reg is always enough.
1395 The TFmodes are really just 80bit values, so we use only 3 registers
1396 to hold them, instead of 4, as the size would suggest.
1398 #define CLASS_MAX_NREGS(CLASS, MODE) \
1399 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1400 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1401 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1402 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1404 /* A C expression whose value is nonzero if pseudos that have been
1405 assigned to registers of class CLASS would likely be spilled
1406 because registers of CLASS are needed for spill registers.
1408 The default value of this macro returns 1 if CLASS has exactly one
1409 register and zero otherwise. On most machines, this default
1410 should be used. Only define this macro to some other expression
1411 if pseudo allocated by `local-alloc.c' end up in memory because
1412 their hard registers were needed for spill registers. If this
1413 macro returns nonzero for those classes, those pseudos will only
1414 be allocated by `global.c', which knows how to reallocate the
1415 pseudo to another register. If there would not be another
1416 register available for reallocation, you should not change the
1417 definition of this macro since the only effect of such a
1418 definition would be to slow down register allocation. */
1420 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1421 (((CLASS) == AREG) \
1422 || ((CLASS) == DREG) \
1423 || ((CLASS) == CREG) \
1424 || ((CLASS) == BREG) \
1425 || ((CLASS) == AD_REGS) \
1426 || ((CLASS) == SIREG) \
1427 || ((CLASS) == DIREG))
1429 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1430 to automatically clobber for all asms.
1432 We do this in the new i386 backend to maintain source compatibility
1433 with the old cc0-based compiler. */
1435 #define MD_ASM_CLOBBERS(CLOBBERS) \
1437 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1438 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1439 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1442 /* Stack layout; function entry, exit and calling. */
1444 /* Define this if pushing a word on the stack
1445 makes the stack pointer a smaller address. */
1446 #define STACK_GROWS_DOWNWARD
1448 /* Define this if the nominal address of the stack frame
1449 is at the high-address end of the local variables;
1450 that is, each additional local variable allocated
1451 goes at a more negative offset in the frame. */
1452 #define FRAME_GROWS_DOWNWARD
1454 /* Offset within stack frame to start allocating local variables at.
1455 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1456 first local allocated. Otherwise, it is the offset to the BEGINNING
1457 of the first local allocated. */
1458 #define STARTING_FRAME_OFFSET 0
1460 /* If we generate an insn to push BYTES bytes,
1461 this says how many the stack pointer really advances by.
1462 On 386 pushw decrements by exactly 2 no matter what the position was.
1463 On the 386 there is no pushb; we use pushw instead, and this
1464 has the effect of rounding up to 2.
1466 For 64bit ABI we round up to 8 bytes.
1469 #define PUSH_ROUNDING(BYTES) \
1471 ? (((BYTES) + 7) & (-8)) \
1472 : (((BYTES) + 1) & (-2)))
1474 /* If defined, the maximum amount of space required for outgoing arguments will
1475 be computed and placed into the variable
1476 `current_function_outgoing_args_size'. No space will be pushed onto the
1477 stack for each call; instead, the function prologue should increase the stack
1478 frame size by this amount. */
1480 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1482 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1483 instructions to pass outgoing arguments. */
1485 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1487 /* Offset of first parameter from the argument pointer register value. */
1488 #define FIRST_PARM_OFFSET(FNDECL) 0
1490 /* Define this macro if functions should assume that stack space has been
1491 allocated for arguments even when their values are passed in registers.
1493 The value of this macro is the size, in bytes, of the area reserved for
1494 arguments passed in registers for the function represented by FNDECL.
1496 This space can be allocated by the caller, or be a part of the
1497 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1499 #define REG_PARM_STACK_SPACE(FNDECL) 0
1501 /* Define as a C expression that evaluates to nonzero if we do not know how
1502 to pass TYPE solely in registers. The file expr.h defines a
1503 definition that is usually appropriate, refer to expr.h for additional
1504 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1505 computed in the stack and then loaded into a register. */
1506 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1508 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1509 || TREE_ADDRESSABLE (TYPE) \
1510 || ((MODE) == TImode) \
1511 || ((MODE) == BLKmode \
1512 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1513 && 0 == (int_size_in_bytes (TYPE) \
1514 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1515 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1516 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1518 /* Value is the number of bytes of arguments automatically
1519 popped when returning from a subroutine call.
1520 FUNDECL is the declaration node of the function (as a tree),
1521 FUNTYPE is the data type of the function (as a tree),
1522 or for a library call it is an identifier node for the subroutine name.
1523 SIZE is the number of bytes of arguments passed on the stack.
1525 On the 80386, the RTD insn may be used to pop them if the number
1526 of args is fixed, but if the number is variable then the caller
1527 must pop them all. RTD can't be used for library calls now
1528 because the library is compiled with the Unix compiler.
1529 Use of RTD is a selectable option, since it is incompatible with
1530 standard Unix calling sequences. If the option is not selected,
1531 the caller must always pop the args.
1533 The attribute stdcall is equivalent to RTD on a per module basis. */
1535 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1536 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1538 /* Define how to find the value returned by a function.
1539 VALTYPE is the data type of the value (as a tree).
1540 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1541 otherwise, FUNC is 0. */
1542 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1543 ix86_function_value (VALTYPE)
1545 #define FUNCTION_VALUE_REGNO_P(N) \
1546 ix86_function_value_regno_p (N)
1548 /* Define how to find the value returned by a library function
1549 assuming the value has mode MODE. */
1551 #define LIBCALL_VALUE(MODE) \
1552 ix86_libcall_value (MODE)
1554 /* Define the size of the result block used for communication between
1555 untyped_call and untyped_return. The block contains a DImode value
1556 followed by the block used by fnsave and frstor. */
1558 #define APPLY_RESULT_SIZE (8+108)
1560 /* 1 if N is a possible register number for function argument passing. */
1561 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1563 /* Define a data type for recording info about an argument list
1564 during the scan of that argument list. This data type should
1565 hold all necessary information about the function itself
1566 and about the args processed so far, enough to enable macros
1567 such as FUNCTION_ARG to determine where the next arg should go. */
1569 typedef struct ix86_args {
1570 int words; /* # words passed so far */
1571 int nregs; /* # registers available for passing */
1572 int regno; /* next available register number */
1573 int sse_words; /* # sse words passed so far */
1574 int sse_nregs; /* # sse registers available for passing */
1575 int sse_regno; /* next available sse register number */
1576 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1579 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1580 for a call to a function whose data type is FNTYPE.
1581 For a library call, FNTYPE is 0. */
1583 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1584 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1586 /* Update the data in CUM to advance over an argument
1587 of mode MODE and data type TYPE.
1588 (TYPE is null for libcalls where that information may not be available.) */
1590 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1591 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1593 /* Define where to put the arguments to a function.
1594 Value is zero to push the argument on the stack,
1595 or a hard register in which to store the argument.
1597 MODE is the argument's machine mode.
1598 TYPE is the data type of the argument (as a tree).
1599 This is null for libcalls where that information may
1601 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1602 the preceding args and about the function being called.
1603 NAMED is nonzero if this argument is a named parameter
1604 (otherwise it is an extra parameter matching an ellipsis). */
1606 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1607 (function_arg (&CUM, MODE, TYPE, NAMED))
1609 /* For an arg passed partly in registers and partly in memory,
1610 this is the number of registers used.
1611 For args passed entirely in registers or entirely in memory, zero. */
1613 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1615 /* If PIC, we cannot make sibling calls to global functions
1616 because the PLT requires %ebx live.
1617 If we are returning floats on the register stack, we cannot make
1618 sibling calls to functions that return floats. (The stack adjust
1619 instruction will wind up after the sibcall jump, and not be executed.) */
1620 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1622 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1623 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1624 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1625 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1627 /* Perform any needed actions needed for a function that is receiving a
1628 variable number of arguments.
1632 MODE and TYPE are the mode and type of the current parameter.
1634 PRETEND_SIZE is a variable that should be set to the amount of stack
1635 that must be pushed by the prolog to pretend that our caller pushed
1638 Normally, this macro will push all remaining incoming registers on the
1639 stack and set PRETEND_SIZE to the length of the registers pushed. */
1641 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1642 ix86_setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1644 /* Define the `__builtin_va_list' type for the ABI. */
1645 #define BUILD_VA_LIST_TYPE(VALIST) \
1646 (VALIST) = ix86_build_va_list ()
1648 /* Implement `va_start' for varargs and stdarg. */
1649 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1650 ix86_va_start (stdarg, valist, nextarg)
1652 /* Implement `va_arg'. */
1653 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1654 ix86_va_arg (valist, type)
1656 /* This macro is invoked at the end of compilation. It is used here to
1657 output code for -fpic that will load the return address into %ebx. */
1660 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1662 /* Output assembler code to FILE to increment profiler label # LABELNO
1663 for profiling a function entry. */
1665 #define FUNCTION_PROFILER(FILE, LABELNO) \
1669 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1670 LPREFIX, (LABELNO)); \
1671 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1675 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1676 fprintf (FILE, "\tcall\t_mcount\n"); \
1681 /* There are three profiling modes for basic blocks available.
1682 The modes are selected at compile time by using the options
1683 -a or -ax of the gnu compiler.
1684 The variable `profile_block_flag' will be set according to the
1687 profile_block_flag == 0, no option used:
1691 profile_block_flag == 1, -a option used.
1693 Count frequency of execution of every basic block.
1695 profile_block_flag == 2, -ax option used.
1697 Generate code to allow several different profiling modes at run time.
1698 Available modes are:
1699 Produce a trace of all basic blocks.
1700 Count frequency of jump instructions executed.
1701 In every mode it is possible to start profiling upon entering
1702 certain functions and to disable profiling of some other functions.
1704 The result of basic-block profiling will be written to a file `bb.out'.
1705 If the -ax option is used parameters for the profiling will be read
1710 /* The following macro shall output assembler code to FILE
1711 to initialize basic-block profiling. */
1713 #undef FUNCTION_BLOCK_PROFILER
1714 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1715 ix86_output_function_block_profiler (FILE, BLOCK_OR_LABEL)
1717 /* The following macro shall output assembler code to FILE
1718 to increment a counter associated with basic block number BLOCKNO. */
1720 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1721 ix86_output_block_profiler (FILE, BLOCKNO)
1723 /* The following macro shall output rtl for the epilogue
1724 to indicate a return from function during basic-block profiling.
1726 If profiling_block_flag == 2:
1728 Output assembler code to call function `__bb_trace_ret'.
1730 Note that function `__bb_trace_ret' must not change the
1731 machine state, especially the flag register. To grant
1732 this, you must output code to save and restore registers
1733 either in this macro or in the macros MACHINE_STATE_SAVE
1734 and MACHINE_STATE_RESTORE. The last two macros will be
1735 used in the function `__bb_trace_ret', so you must make
1736 sure that the function prologue does not change any
1737 register prior to saving it with MACHINE_STATE_SAVE.
1739 else if profiling_block_flag != 0:
1741 The macro will not be used, so it need not distinguish
1745 #define FUNCTION_BLOCK_PROFILER_EXIT \
1746 emit_call_insn (gen_call (gen_rtx_MEM (QImode, \
1747 gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")), \
1748 const0_rtx, constm1_rtx))
1750 /* The function `__bb_trace_func' is called in every basic block
1751 and is not allowed to change the machine state. Saving (restoring)
1752 the state can either be done in the BLOCK_PROFILER macro,
1753 before calling function (rsp. after returning from function)
1754 `__bb_trace_func', or it can be done inside the function by
1755 defining the macros:
1757 MACHINE_STATE_SAVE(ID)
1758 MACHINE_STATE_RESTORE(ID)
1760 In the latter case care must be taken, that the prologue code
1761 of function `__bb_trace_func' does not already change the
1762 state prior to saving it with MACHINE_STATE_SAVE.
1764 The parameter `ID' is a string identifying a unique macro use.
1766 On the i386 the initialization code at the begin of
1767 function `__bb_trace_func' contains a `sub' instruction
1768 therefore we handle save and restore of the flag register
1769 in the BLOCK_PROFILER macro.
1771 Note that ebx, esi, and edi are callee-save, so we don't have to
1772 preserve them explicitly. */
1774 #define MACHINE_STATE_SAVE(ID) \
1776 register int eax_ __asm__("eax"); \
1777 register int ecx_ __asm__("ecx"); \
1778 register int edx_ __asm__("edx"); \
1779 __asm__ __volatile__ ("\
1783 : : "r"(eax_), "r"(ecx_), "r"(edx_)); \
1786 #define MACHINE_STATE_RESTORE(ID) \
1788 register int eax_ __asm__("eax"); \
1789 register int ecx_ __asm__("ecx"); \
1790 register int edx_ __asm__("edx"); \
1791 __asm__ __volatile__ ("\
1795 : "=r"(eax_), "=r"(ecx_), "=r"(edx_)); \
1798 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1799 the stack pointer does not matter. The value is tested only in
1800 functions that have frame pointers.
1801 No definition is equivalent to always zero. */
1802 /* Note on the 386 it might be more efficient not to define this since
1803 we have to restore it ourselves from the frame pointer, in order to
1806 #define EXIT_IGNORE_STACK 1
1808 /* Output assembler code for a block containing the constant parts
1809 of a trampoline, leaving space for the variable parts. */
1811 /* On the 386, the trampoline contains two instructions:
1814 The trampoline is generated entirely at runtime. The operand of JMP
1815 is the address of FUNCTION relative to the instruction following the
1816 JMP (which is 5 bytes long). */
1818 /* Length in units of the trampoline for entering a nested function. */
1820 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1822 /* Emit RTL insns to initialize the variable parts of a trampoline.
1823 FNADDR is an RTX for the address of the function's pure code.
1824 CXT is an RTX for the static chain value for the function. */
1826 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1827 x86_initialize_trampoline (TRAMP, FNADDR, CXT)
1829 /* Definitions for register eliminations.
1831 This is an array of structures. Each structure initializes one pair
1832 of eliminable registers. The "from" register number is given first,
1833 followed by "to". Eliminations of the same "from" register are listed
1834 in order of preference.
1836 There are two registers that can always be eliminated on the i386.
1837 The frame pointer and the arg pointer can be replaced by either the
1838 hard frame pointer or to the stack pointer, depending upon the
1839 circumstances. The hard frame pointer is not used before reload and
1840 so it is not eligible for elimination. */
1842 #define ELIMINABLE_REGS \
1843 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1844 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1845 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1846 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1848 /* Given FROM and TO register numbers, say whether this elimination is
1849 allowed. Frame pointer elimination is automatically handled.
1851 All other eliminations are valid. */
1853 #define CAN_ELIMINATE(FROM, TO) \
1854 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1856 /* Define the offset between two registers, one to be eliminated, and the other
1857 its replacement, at the start of a routine. */
1859 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1860 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1862 /* Addressing modes, and classification of registers for them. */
1864 /* #define HAVE_POST_INCREMENT 0 */
1865 /* #define HAVE_POST_DECREMENT 0 */
1867 /* #define HAVE_PRE_DECREMENT 0 */
1868 /* #define HAVE_PRE_INCREMENT 0 */
1870 /* Macros to check register numbers against specific register classes. */
1872 /* These assume that REGNO is a hard or pseudo reg number.
1873 They give nonzero only if REGNO is a hard reg of the suitable class
1874 or a pseudo reg currently allocated to a suitable hard reg.
1875 Since they use reg_renumber, they are safe only once reg_renumber
1876 has been allocated, which happens in local-alloc.c. */
1878 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1879 ((REGNO) < STACK_POINTER_REGNUM \
1880 || (REGNO >= FIRST_REX_INT_REG \
1881 && (REGNO) <= LAST_REX_INT_REG) \
1882 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1883 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1884 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1886 #define REGNO_OK_FOR_BASE_P(REGNO) \
1887 ((REGNO) <= STACK_POINTER_REGNUM \
1888 || (REGNO) == ARG_POINTER_REGNUM \
1889 || (REGNO) == FRAME_POINTER_REGNUM \
1890 || (REGNO >= FIRST_REX_INT_REG \
1891 && (REGNO) <= LAST_REX_INT_REG) \
1892 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1893 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1894 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1896 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1897 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1899 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1900 and check its validity for a certain class.
1901 We have two alternate definitions for each of them.
1902 The usual definition accepts all pseudo regs; the other rejects
1903 them unless they have been allocated suitable hard regs.
1904 The symbol REG_OK_STRICT causes the latter definition to be used.
1906 Most source files want to accept pseudo regs in the hope that
1907 they will get allocated to the class that the insn wants them to be in.
1908 Source files for reload pass need to be strict.
1909 After reload, it makes no difference, since pseudo regs have
1910 been eliminated by then. */
1913 /* Non strict versions, pseudos are ok */
1914 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1915 (REGNO (X) < STACK_POINTER_REGNUM \
1916 || (REGNO (X) >= FIRST_REX_INT_REG \
1917 && REGNO (X) <= LAST_REX_INT_REG) \
1918 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1920 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1921 (REGNO (X) <= STACK_POINTER_REGNUM \
1922 || REGNO (X) == ARG_POINTER_REGNUM \
1923 || REGNO (X) == FRAME_POINTER_REGNUM \
1924 || (REGNO (X) >= FIRST_REX_INT_REG \
1925 && REGNO (X) <= LAST_REX_INT_REG) \
1926 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1928 /* Strict versions, hard registers only */
1929 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1930 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1932 #ifndef REG_OK_STRICT
1933 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1934 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1937 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1938 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1941 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1942 that is a valid memory address for an instruction.
1943 The MODE argument is the machine mode for the MEM expression
1944 that wants to use this address.
1946 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1947 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1949 See legitimize_pic_address in i386.c for details as to what
1950 constitutes a legitimate address when -fpic is used. */
1952 #define MAX_REGS_PER_ADDRESS 2
1954 #define CONSTANT_ADDRESS_P(X) \
1955 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1956 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1957 || GET_CODE (X) == CONST_DOUBLE)
1959 /* Nonzero if the constant value X is a legitimate general operand.
1960 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1962 #define LEGITIMATE_CONSTANT_P(X) 1
1964 #ifdef REG_OK_STRICT
1965 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1967 if (legitimate_address_p (MODE, X, 1)) \
1972 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1974 if (legitimate_address_p (MODE, X, 0)) \
1980 /* If defined, a C expression to determine the base term of address X.
1981 This macro is used in only one place: `find_base_term' in alias.c.
1983 It is always safe for this macro to not be defined. It exists so
1984 that alias analysis can understand machine-dependent addresses.
1986 The typical use of this macro is to handle addresses containing
1987 a label_ref or symbol_ref within an UNSPEC. */
1989 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1991 /* Try machine-dependent ways of modifying an illegitimate address
1992 to be legitimate. If we find one, return the new, valid address.
1993 This macro is used in only one place: `memory_address' in explow.c.
1995 OLDX is the address as it was before break_out_memory_refs was called.
1996 In some cases it is useful to look at this to decide what needs to be done.
1998 MODE and WIN are passed so that this macro can use
1999 GO_IF_LEGITIMATE_ADDRESS.
2001 It is always safe for this macro to do nothing. It exists to recognize
2002 opportunities to optimize the output.
2004 For the 80386, we handle X+REG by loading X into a register R and
2005 using R+REG. R will go in a general reg and indexing will be used.
2006 However, if REG is a broken-out memory address or multiplication,
2007 nothing needs to be done because REG can certainly go in a general reg.
2009 When -fpic is used, special handling is needed for symbolic references.
2010 See comments by legitimize_pic_address in i386.c for details. */
2012 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2014 (X) = legitimize_address (X, OLDX, MODE); \
2015 if (memory_address_p (MODE, X)) \
2019 #define REWRITE_ADDRESS(x) rewrite_address(x)
2021 /* Nonzero if the constant value X is a legitimate general operand
2022 when generating PIC code. It is given that flag_pic is on and
2023 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2025 #define LEGITIMATE_PIC_OPERAND_P(X) \
2026 (! SYMBOLIC_CONST (X) \
2027 || legitimate_pic_address_disp_p (X))
2029 #define SYMBOLIC_CONST(X) \
2030 (GET_CODE (X) == SYMBOL_REF \
2031 || GET_CODE (X) == LABEL_REF \
2032 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2034 /* Go to LABEL if ADDR (a legitimate address expression)
2035 has an effect that depends on the machine mode it is used for.
2036 On the 80386, only postdecrement and postincrement address depend thus
2037 (the amount of decrement or increment being the length of the operand). */
2038 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2039 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
2041 /* Codes for all the SSE/MMX builtins. */
2053 IX86_BUILTIN_CMPEQPS,
2054 IX86_BUILTIN_CMPLTPS,
2055 IX86_BUILTIN_CMPLEPS,
2056 IX86_BUILTIN_CMPGTPS,
2057 IX86_BUILTIN_CMPGEPS,
2058 IX86_BUILTIN_CMPNEQPS,
2059 IX86_BUILTIN_CMPNLTPS,
2060 IX86_BUILTIN_CMPNLEPS,
2061 IX86_BUILTIN_CMPNGTPS,
2062 IX86_BUILTIN_CMPNGEPS,
2063 IX86_BUILTIN_CMPORDPS,
2064 IX86_BUILTIN_CMPUNORDPS,
2065 IX86_BUILTIN_CMPNEPS,
2066 IX86_BUILTIN_CMPEQSS,
2067 IX86_BUILTIN_CMPLTSS,
2068 IX86_BUILTIN_CMPLESS,
2069 IX86_BUILTIN_CMPGTSS,
2070 IX86_BUILTIN_CMPGESS,
2071 IX86_BUILTIN_CMPNEQSS,
2072 IX86_BUILTIN_CMPNLTSS,
2073 IX86_BUILTIN_CMPNLESS,
2074 IX86_BUILTIN_CMPNGTSS,
2075 IX86_BUILTIN_CMPNGESS,
2076 IX86_BUILTIN_CMPORDSS,
2077 IX86_BUILTIN_CMPUNORDSS,
2078 IX86_BUILTIN_CMPNESS,
2080 IX86_BUILTIN_COMIEQSS,
2081 IX86_BUILTIN_COMILTSS,
2082 IX86_BUILTIN_COMILESS,
2083 IX86_BUILTIN_COMIGTSS,
2084 IX86_BUILTIN_COMIGESS,
2085 IX86_BUILTIN_COMINEQSS,
2086 IX86_BUILTIN_UCOMIEQSS,
2087 IX86_BUILTIN_UCOMILTSS,
2088 IX86_BUILTIN_UCOMILESS,
2089 IX86_BUILTIN_UCOMIGTSS,
2090 IX86_BUILTIN_UCOMIGESS,
2091 IX86_BUILTIN_UCOMINEQSS,
2093 IX86_BUILTIN_CVTPI2PS,
2094 IX86_BUILTIN_CVTPS2PI,
2095 IX86_BUILTIN_CVTSI2SS,
2096 IX86_BUILTIN_CVTSS2SI,
2097 IX86_BUILTIN_CVTTPS2PI,
2098 IX86_BUILTIN_CVTTSS2SI,
2099 IX86_BUILTIN_M_FROM_INT,
2100 IX86_BUILTIN_M_TO_INT,
2107 IX86_BUILTIN_LOADAPS,
2108 IX86_BUILTIN_LOADUPS,
2109 IX86_BUILTIN_STOREAPS,
2110 IX86_BUILTIN_STOREUPS,
2111 IX86_BUILTIN_LOADSS,
2112 IX86_BUILTIN_STORESS,
2115 IX86_BUILTIN_MOVHLPS,
2116 IX86_BUILTIN_MOVLHPS,
2117 IX86_BUILTIN_LOADHPS,
2118 IX86_BUILTIN_LOADLPS,
2119 IX86_BUILTIN_STOREHPS,
2120 IX86_BUILTIN_STORELPS,
2122 IX86_BUILTIN_MASKMOVQ,
2123 IX86_BUILTIN_MOVMSKPS,
2124 IX86_BUILTIN_PMOVMSKB,
2126 IX86_BUILTIN_MOVNTPS,
2127 IX86_BUILTIN_MOVNTQ,
2129 IX86_BUILTIN_PACKSSWB,
2130 IX86_BUILTIN_PACKSSDW,
2131 IX86_BUILTIN_PACKUSWB,
2136 IX86_BUILTIN_PADDSB,
2137 IX86_BUILTIN_PADDSW,
2138 IX86_BUILTIN_PADDUSB,
2139 IX86_BUILTIN_PADDUSW,
2143 IX86_BUILTIN_PSUBSB,
2144 IX86_BUILTIN_PSUBSW,
2145 IX86_BUILTIN_PSUBUSB,
2146 IX86_BUILTIN_PSUBUSW,
2156 IX86_BUILTIN_PCMPEQB,
2157 IX86_BUILTIN_PCMPEQW,
2158 IX86_BUILTIN_PCMPEQD,
2159 IX86_BUILTIN_PCMPGTB,
2160 IX86_BUILTIN_PCMPGTW,
2161 IX86_BUILTIN_PCMPGTD,
2163 IX86_BUILTIN_PEXTRW,
2164 IX86_BUILTIN_PINSRW,
2166 IX86_BUILTIN_PMADDWD,
2168 IX86_BUILTIN_PMAXSW,
2169 IX86_BUILTIN_PMAXUB,
2170 IX86_BUILTIN_PMINSW,
2171 IX86_BUILTIN_PMINUB,
2173 IX86_BUILTIN_PMULHUW,
2174 IX86_BUILTIN_PMULHW,
2175 IX86_BUILTIN_PMULLW,
2177 IX86_BUILTIN_PSADBW,
2178 IX86_BUILTIN_PSHUFW,
2188 IX86_BUILTIN_PSLLWI,
2189 IX86_BUILTIN_PSLLDI,
2190 IX86_BUILTIN_PSLLQI,
2191 IX86_BUILTIN_PSRAWI,
2192 IX86_BUILTIN_PSRADI,
2193 IX86_BUILTIN_PSRLWI,
2194 IX86_BUILTIN_PSRLDI,
2195 IX86_BUILTIN_PSRLQI,
2197 IX86_BUILTIN_PUNPCKHBW,
2198 IX86_BUILTIN_PUNPCKHWD,
2199 IX86_BUILTIN_PUNPCKHDQ,
2200 IX86_BUILTIN_PUNPCKLBW,
2201 IX86_BUILTIN_PUNPCKLWD,
2202 IX86_BUILTIN_PUNPCKLDQ,
2204 IX86_BUILTIN_SHUFPS,
2208 IX86_BUILTIN_RSQRTPS,
2209 IX86_BUILTIN_RSQRTSS,
2210 IX86_BUILTIN_SQRTPS,
2211 IX86_BUILTIN_SQRTSS,
2213 IX86_BUILTIN_UNPCKHPS,
2214 IX86_BUILTIN_UNPCKLPS,
2217 IX86_BUILTIN_ANDNPS,
2222 IX86_BUILTIN_LDMXCSR,
2223 IX86_BUILTIN_STMXCSR,
2224 IX86_BUILTIN_SFENCE,
2225 IX86_BUILTIN_PREFETCH,
2227 /* 3DNow! Original */
2229 IX86_BUILTIN_PAVGUSB,
2233 IX86_BUILTIN_PFCMPEQ,
2234 IX86_BUILTIN_PFCMPGE,
2235 IX86_BUILTIN_PFCMPGT,
2240 IX86_BUILTIN_PFRCPIT1,
2241 IX86_BUILTIN_PFRCPIT2,
2242 IX86_BUILTIN_PFRSQIT1,
2243 IX86_BUILTIN_PFRSQRT,
2245 IX86_BUILTIN_PFSUBR,
2247 IX86_BUILTIN_PMULHRW,
2248 IX86_BUILTIN_PREFETCH_3DNOW, /* PREFETCH already used */
2249 IX86_BUILTIN_PREFETCHW,
2251 /* 3DNow! Athlon Extensions */
2253 IX86_BUILTIN_PFNACC,
2254 IX86_BUILTIN_PFPNACC,
2256 IX86_BUILTIN_PSWAPDSI,
2257 IX86_BUILTIN_PSWAPDSF,
2259 /* Composite builtins, expand to more than one insn. */
2260 IX86_BUILTIN_SETPS1,
2263 IX86_BUILTIN_SETRPS,
2264 IX86_BUILTIN_LOADPS1,
2265 IX86_BUILTIN_LOADRPS,
2266 IX86_BUILTIN_STOREPS1,
2267 IX86_BUILTIN_STORERPS,
2269 IX86_BUILTIN_MMX_ZERO,
2274 /* Define this macro if references to a symbol must be treated
2275 differently depending on something about the variable or
2276 function named by the symbol (such as what section it is in).
2278 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2279 so that we may access it directly in the GOT. */
2281 #define ENCODE_SECTION_INFO(DECL) \
2286 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2287 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2289 if (GET_CODE (rtl) == MEM) \
2291 if (TARGET_DEBUG_ADDR \
2292 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2294 fprintf (stderr, "Encode %s, public = %d\n", \
2295 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2296 TREE_PUBLIC (DECL)); \
2299 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2300 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2301 || ! TREE_PUBLIC (DECL)); \
2307 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2308 codes once the function is being compiled into assembly code, but
2309 not before. (It is not done before, because in the case of
2310 compiling an inline function, it would lead to multiple PIC
2311 prologues being included in functions which used inline functions
2312 and were compiled to assembly language.) */
2314 #define FINALIZE_PIC \
2317 current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \
2322 /* Max number of args passed in registers. If this is more than 3, we will
2323 have problems with ebx (register #4), since it is a caller save register and
2324 is also used as the pic register in ELF. So for now, don't allow more than
2325 3 registers to be passed in registers. */
2327 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2329 #define SSE_REGPARM_MAX (TARGET_64BIT ? 16 : 0)
2332 /* Specify the machine mode that this machine uses
2333 for the index in the tablejump instruction. */
2334 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2336 /* Define as C expression which evaluates to nonzero if the tablejump
2337 instruction expects the table to contain offsets from the address of the
2339 Do not define this if the table should contain absolute addresses. */
2340 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2342 /* Specify the tree operation to be used to convert reals to integers.
2343 This should be changed to take advantage of fist --wfs ??
2345 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2347 /* This is the kind of divide that is easiest to do in the general case. */
2348 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2350 /* Define this as 1 if `char' should by default be signed; else as 0. */
2351 #define DEFAULT_SIGNED_CHAR 1
2353 /* Max number of bytes we can move from memory to memory
2354 in one reasonably fast instruction. */
2357 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2358 move efficiently, as opposed to MOVE_MAX which is the maximum
2359 number of bytes we can move with a single instruction. */
2360 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2362 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2363 move-instruction pairs, we will do a movstr or libcall instead.
2364 Increasing the value will always make code faster, but eventually
2365 incurs high cost in increased code size.
2367 If you don't define this, a reasonable default is used. */
2369 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2371 /* Define if shifts truncate the shift count
2372 which implies one can omit a sign-extension or zero-extension
2373 of a shift count. */
2374 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2376 /* #define SHIFT_COUNT_TRUNCATED */
2378 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2379 is done just by pretending it is already truncated. */
2380 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2382 /* We assume that the store-condition-codes instructions store 0 for false
2383 and some other value for true. This is the value stored for true. */
2385 #define STORE_FLAG_VALUE 1
2387 /* When a prototype says `char' or `short', really pass an `int'.
2388 (The 386 can't easily push less than an int.) */
2390 #define PROMOTE_PROTOTYPES 1
2392 /* A macro to update M and UNSIGNEDP when an object whose type is
2393 TYPE and which has the specified mode and signedness is to be
2394 stored in a register. This macro is only called when TYPE is a
2397 On i386 it is sometimes usefull to promote HImode and QImode
2398 quantities to SImode. The choice depends on target type. */
2400 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2401 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2402 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2405 /* Specify the machine mode that pointers have.
2406 After generation of rtl, the compiler makes no further distinction
2407 between pointers and any other objects of this machine mode. */
2408 #define Pmode (TARGET_64BIT ? DImode : SImode)
2410 /* A function address in a call instruction
2411 is a byte address (for indexing purposes)
2412 so give the MEM rtx a byte's mode. */
2413 #define FUNCTION_MODE QImode
2415 /* A part of a C `switch' statement that describes the relative costs
2416 of constant RTL expressions. It must contain `case' labels for
2417 expression codes `const_int', `const', `symbol_ref', `label_ref'
2418 and `const_double'. Each case must ultimately reach a `return'
2419 statement to return the relative cost of the use of that kind of
2420 constant value in an expression. The cost may depend on the
2421 precise value of the constant, which is available for examination
2422 in X, and the rtx code of the expression in which it is contained,
2423 found in OUTER_CODE.
2425 CODE is the expression code--redundant, since it can be obtained
2426 with `GET_CODE (X)'. */
2428 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2433 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2435 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2437 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2439 case CONST_DOUBLE: \
2442 if (GET_MODE (RTX) == VOIDmode) \
2445 code = standard_80387_constant_p (RTX); \
2446 return code == 1 ? 1 : \
2451 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2452 #define TOPLEVEL_COSTS_N_INSNS(N) \
2453 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2455 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2456 This can be used, for example, to indicate how costly a multiply
2457 instruction is. In writing this macro, you can use the construct
2458 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2459 instructions. OUTER_CODE is the code of the expression in which X
2462 This macro is optional; do not define it if the default cost
2463 assumptions are adequate for the target machine. */
2465 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2467 /* The zero extensions is often completely free on x86_64, so make \
2468 it as cheap as possible. */ \
2469 if (TARGET_64BIT && GET_MODE (X) == DImode \
2470 && GET_MODE (XEXP (X, 0)) == SImode) \
2472 total = 1; goto egress_rtx_costs; \
2475 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2476 ix86_cost->add : ix86_cost->movzx); \
2479 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2482 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2483 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2485 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2487 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2488 if (value == 2 || value == 3) \
2489 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2491 /* fall through */ \
2497 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2499 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2501 if (INTVAL (XEXP (X, 1)) > 32) \
2502 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2504 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2508 if (GET_CODE (XEXP (X, 1)) == AND) \
2509 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2511 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2516 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2517 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2519 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2524 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2526 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2529 while (value != 0) \
2535 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2536 + nbits * ix86_cost->mult_bit); \
2538 else /* This is arbitrary */ \
2539 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2540 + 7 * ix86_cost->mult_bit); \
2546 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2549 if (GET_CODE (XEXP (X, 0)) == PLUS \
2550 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2551 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2552 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2554 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1)); \
2555 if (val == 2 || val == 4 || val == 8) \
2557 return (COSTS_N_INSNS (ix86_cost->lea) \
2558 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2559 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2560 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2563 else if (GET_CODE (XEXP (X, 0)) == MULT \
2564 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2566 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2567 if (val == 2 || val == 4 || val == 8) \
2569 return (COSTS_N_INSNS (ix86_cost->lea) \
2570 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2571 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2574 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2576 return (COSTS_N_INSNS (ix86_cost->lea) \
2577 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2578 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2579 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2582 /* fall through */ \
2587 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2588 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2589 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2590 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2591 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2592 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2594 /* fall through */ \
2597 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2598 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2599 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2605 /* An expression giving the cost of an addressing mode that contains
2606 ADDRESS. If not defined, the cost is computed from the ADDRESS
2607 expression and the `CONST_COSTS' values.
2609 For most CISC machines, the default cost is a good approximation
2610 of the true cost of the addressing mode. However, on RISC
2611 machines, all instructions normally have the same length and
2612 execution time. Hence all addresses will have equal costs.
2614 In cases where more than one form of an address is known, the form
2615 with the lowest cost will be used. If multiple forms have the
2616 same, lowest, cost, the one that is the most complex will be used.
2618 For example, suppose an address that is equal to the sum of a
2619 register and a constant is used twice in the same basic block.
2620 When this macro is not defined, the address will be computed in a
2621 register and memory references will be indirect through that
2622 register. On machines where the cost of the addressing mode
2623 containing the sum is no higher than that of a simple indirect
2624 reference, this will produce an additional instruction and
2625 possibly require an additional register. Proper specification of
2626 this macro eliminates this overhead for such machines.
2628 Similar use of this macro is made in strength reduction of loops.
2630 ADDRESS need not be valid as an address. In such a case, the cost
2631 is not relevant and can be any value; invalid addresses need not be
2632 assigned a different cost.
2634 On machines where an address involving more than one register is as
2635 cheap as an address computation involving only one register,
2636 defining `ADDRESS_COST' to reflect this can cause two registers to
2637 be live over a region of code where only one would have been if
2638 `ADDRESS_COST' were not defined in that manner. This effect should
2639 be considered in the definition of this macro. Equivalent costs
2640 should probably only be given to addresses with different numbers
2641 of registers on machines with lots of registers.
2643 This macro will normally either not be defined or be defined as a
2646 For i386, it is better to use a complex address than let gcc copy
2647 the address into a reg and make a new pseudo. But not if the address
2648 requires to two regs - that would mean more pseudos with longer
2651 #define ADDRESS_COST(RTX) \
2652 ix86_address_cost (RTX)
2654 /* A C expression for the cost of moving data from a register in class FROM to
2655 one in class TO. The classes are expressed using the enumeration values
2656 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2657 interpreted relative to that.
2659 It is not required that the cost always equal 2 when FROM is the same as TO;
2660 on some machines it is expensive to move between registers if they are not
2661 general registers. */
2663 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2664 ix86_register_move_cost (MODE, CLASS1, CLASS2)
2666 /* A C expression for the cost of moving data of mode M between a
2667 register and memory. A value of 2 is the default; this cost is
2668 relative to those in `REGISTER_MOVE_COST'.
2670 If moving between registers and memory is more expensive than
2671 between two registers, you should define this macro to express the
2674 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2675 ix86_memory_move_cost (MODE, CLASS, IN)
2677 /* A C expression for the cost of a branch instruction. A value of 1
2678 is the default; other values are interpreted relative to that. */
2680 #define BRANCH_COST ix86_branch_cost
2682 /* Define this macro as a C expression which is nonzero if accessing
2683 less than a word of memory (i.e. a `char' or a `short') is no
2684 faster than accessing a word of memory, i.e., if such access
2685 require more than one instruction or if there is no difference in
2686 cost between byte and (aligned) word loads.
2688 When this macro is not defined, the compiler will access a field by
2689 finding the smallest containing object; when it is defined, a
2690 fullword load will be used if alignment permits. Unless bytes
2691 accesses are faster than word accesses, using word accesses is
2692 preferable since it may eliminate subsequent memory access if
2693 subsequent accesses occur to other fields in the same word of the
2694 structure, but to different bytes. */
2696 #define SLOW_BYTE_ACCESS 0
2698 /* Nonzero if access to memory by shorts is slow and undesirable. */
2699 #define SLOW_SHORT_ACCESS 0
2701 /* Define this macro if zero-extension (of a `char' or `short' to an
2702 `int') can be done faster if the destination is a register that is
2705 If you define this macro, you must have instruction patterns that
2706 recognize RTL structures like this:
2708 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2710 and likewise for `HImode'. */
2712 /* #define SLOW_ZERO_EXTEND */
2714 /* Define this macro to be the value 1 if unaligned accesses have a
2715 cost many times greater than aligned accesses, for example if they
2716 are emulated in a trap handler.
2718 When this macro is non-zero, the compiler will act as if
2719 `STRICT_ALIGNMENT' were non-zero when generating code for block
2720 moves. This can cause significantly more instructions to be
2721 produced. Therefore, do not set this macro non-zero if unaligned
2722 accesses only add a cycle or two to the time for a memory access.
2724 If the value of this macro is always zero, it need not be defined. */
2726 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2728 /* Define this macro to inhibit strength reduction of memory
2729 addresses. (On some machines, such strength reduction seems to do
2730 harm rather than good.) */
2732 /* #define DONT_REDUCE_ADDR */
2734 /* Define this macro if it is as good or better to call a constant
2735 function address than to call an address kept in a register.
2737 Desirable on the 386 because a CALL with a constant address is
2738 faster than one with a register address. */
2740 #define NO_FUNCTION_CSE
2742 /* Define this macro if it is as good or better for a function to call
2743 itself with an explicit address than to call an address kept in a
2746 #define NO_RECURSIVE_FUNCTION_CSE
2748 /* Add any extra modes needed to represent the condition code.
2750 For the i386, we need separate modes when floating-point
2751 equality comparisons are being done.
2753 Add CCNO to indicate comparisons against zero that requires
2754 Overflow flag to be unset. Sign bit test is used instead and
2755 thus can be used to form "a&b>0" type of tests.
2757 Add CCGC to indicate comparisons agains zero that allows
2758 unspecified garbage in the Carry flag. This mode is used
2759 by inc/dec instructions.
2761 Add CCGOC to indicate comparisons agains zero that allows
2762 unspecified garbage in the Carry and Overflow flag. This
2763 mode is used to simulate comparisons of (a-b) and (a+b)
2764 against zero using sub/cmp/add operations.
2766 Add CCZ to indicate that only the Zero flag is valid. */
2768 #define EXTRA_CC_MODES \
2769 CC(CCGCmode, "CCGC") \
2770 CC(CCGOCmode, "CCGOC") \
2771 CC(CCNOmode, "CCNO") \
2772 CC(CCZmode, "CCZ") \
2773 CC(CCFPmode, "CCFP") \
2774 CC(CCFPUmode, "CCFPU")
2776 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2777 return the mode to be used for the comparison.
2779 For floating-point equality comparisons, CCFPEQmode should be used.
2780 VOIDmode should be used in all other cases.
2782 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2783 possible, to allow for more combinations. */
2785 #define SELECT_CC_MODE(OP,X,Y) ix86_cc_mode (OP, X, Y)
2787 /* Return non-zero if MODE implies a floating point inequality can be
2790 #define REVERSIBLE_CC_MODE(MODE) 1
2792 /* A C expression whose value is reversed condition code of the CODE for
2793 comparison done in CC_MODE mode. */
2794 #define REVERSE_CONDITION(CODE, MODE) \
2795 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2796 : reverse_condition_maybe_unordered (CODE))
2799 /* Control the assembler format that we output, to the extent
2800 this does not vary between assemblers. */
2802 /* How to refer to registers in assembler output.
2803 This sequence is indexed by compiler's hard-register-number (see above). */
2805 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2806 For non floating point regs, the following are the HImode names.
2808 For float regs, the stack top is sometimes referred to as "%st(0)"
2809 instead of just "%st". PRINT_REG handles this with the "y" code. */
2811 #undef HI_REGISTER_NAMES
2812 #define HI_REGISTER_NAMES \
2813 {"ax","dx","cx","bx","si","di","bp","sp", \
2814 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2815 "flags","fpsr", "dirflag", "frame", \
2816 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2817 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2818 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2819 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2821 #define REGISTER_NAMES HI_REGISTER_NAMES
2823 /* Table of additional register names to use in user input. */
2825 #define ADDITIONAL_REGISTER_NAMES \
2826 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2827 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2828 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2829 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2830 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2831 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2832 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2833 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2835 /* Note we are omitting these since currently I don't know how
2836 to get gcc to use these, since they want the same but different
2837 number as al, and ax.
2840 #define QI_REGISTER_NAMES \
2841 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2843 /* These parallel the array above, and can be used to access bits 8:15
2844 of regs 0 through 3. */
2846 #define QI_HIGH_REGISTER_NAMES \
2847 {"ah", "dh", "ch", "bh", }
2849 /* How to renumber registers for dbx and gdb. */
2851 #define DBX_REGISTER_NUMBER(n) \
2852 (TARGET_64BIT ? dbx64_register_map[n] : dbx_register_map[n])
2854 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2855 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2856 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2858 /* Before the prologue, RA is at 0(%esp). */
2859 #define INCOMING_RETURN_ADDR_RTX \
2860 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2862 /* After the prologue, RA is at -4(AP) in the current frame. */
2863 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2865 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2866 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2868 /* PC is dbx register 8; let's use that column for RA. */
2869 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2871 /* Before the prologue, the top of the frame is at 4(%esp). */
2872 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2874 /* Describe how we implement __builtin_eh_return. */
2875 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2876 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2879 /* Select a format to encode pointers in exception handling data. CODE
2880 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2881 true if the symbol may be affected by dynamic relocations.
2883 ??? All x86 object file formats are capable of representing this.
2884 After all, the relocation needed is the same as for the call insn.
2885 Whether or not a particular assembler allows us to enter such, I
2886 guess we'll have to see. */
2887 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2888 (flag_pic ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel \
2891 /* This is how to output the definition of a user-level label named NAME,
2892 such as the label on a static function or variable NAME. */
2894 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2895 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2897 /* This is how to output an assembler line defining a `double' constant. */
2899 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2901 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2902 fprintf (FILE, "%s0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
2905 /* This is how to output a `long double' extended real constant. */
2907 #undef ASM_OUTPUT_LONG_DOUBLE
2908 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2910 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
2911 if (TARGET_128BIT_LONG_DOUBLE) \
2912 fprintf (FILE, "%s0x%lx,0x%lx,0x%lx,0x0\n", ASM_LONG, l[0], l[1], l[2]); \
2914 fprintf (FILE, "%s0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
2917 /* This is how to output an assembler line defining a `float' constant. */
2919 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2921 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2922 fprintf ((FILE), "%s0x%lx\n", ASM_LONG, l); \
2925 /* Store in OUTPUT a string (made with alloca) containing
2926 an assembler-name for a local static variable named NAME.
2927 LABELNO is an integer which is different for each call. */
2929 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2930 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2931 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2933 /* This is how to output an assembler line defining an `int' constant. */
2935 #define ASM_OUTPUT_INT(FILE,VALUE) \
2936 ( fputs (ASM_LONG, FILE), \
2937 output_addr_const (FILE,(VALUE)), \
2940 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2941 ( fprintf (FILE, "%s\t", ASM_QUAD), \
2942 output_addr_const (FILE,(VALUE)), \
2945 /* Likewise for `char' and `short' constants. */
2947 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2948 ( fputs (ASM_SHORT, FILE), \
2949 output_addr_const (FILE,(VALUE)), \
2952 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2953 ( fputs (ASM_BYTE_OP, FILE), \
2954 output_addr_const (FILE, (VALUE)), \
2957 /* Given that x86 natively supports unaligned data, it's reasonable to
2958 assume that all x86 assemblers don't auto-align data. Thus the
2959 unaligned output macros required by dwarf2 frame unwind information
2960 degenerate to the macros used above. */
2961 #define UNALIGNED_SHORT_ASM_OP ASM_SHORT
2962 #define UNALIGNED_INT_ASM_OP ASM_LONG
2963 #define INT_ASM_OP ASM_LONG
2965 /* This is how to output an assembler line for a numeric constant byte. */
2967 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2968 asm_fprintf ((FILE), "%s0x%x\n", ASM_BYTE_OP, (VALUE))
2970 /* This is how to output an insn to push a register on the stack.
2971 It need not be very fast code. */
2973 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2974 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2976 /* This is how to output an insn to pop a register from the stack.
2977 It need not be very fast code. */
2979 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2980 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2982 /* This is how to output an element of a case-vector that is absolute.
2985 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2986 fprintf (FILE, "%s%s%d\n", TARGET_64BIT ? ASM_QUAD : ASM_LONG, LPREFIX, VALUE)
2988 /* This is how to output an element of a case-vector that is relative.
2989 We don't use these on the 386 yet, because the ATT assembler can't do
2990 forward reference the differences.
2993 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2994 fprintf (FILE, "%s%s%d-%s%d\n",ASM_LONG, LPREFIX, VALUE, LPREFIX, REL)
2996 /* A C statement that outputs an address constant appropriate to
2997 for DWARF debugging. */
2999 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
3000 i386_dwarf_output_addr_const((FILE),(X))
3002 /* Either simplify a location expression, or return the original. */
3004 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
3005 i386_simplify_dwarf_addr(X)
3007 /* Print operand X (an rtx) in assembler syntax to file FILE.
3008 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3009 Effect of various CODE letters is described in i386.c near
3010 print_operand function. */
3012 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
3013 ((CODE) == '*' || (CODE) == '+')
3015 /* Print the name of a register based on its machine mode and number.
3016 If CODE is 'w', pretend the mode is HImode.
3017 If CODE is 'b', pretend the mode is QImode.
3018 If CODE is 'k', pretend the mode is SImode.
3019 If CODE is 'q', pretend the mode is DImode.
3020 If CODE is 'h', pretend the reg is the `high' byte register.
3021 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
3023 #define PRINT_REG(X, CODE, FILE) \
3024 print_reg (X, CODE, FILE)
3026 #define PRINT_OPERAND(FILE, X, CODE) \
3027 print_operand (FILE, X, CODE)
3029 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3030 print_operand_address (FILE, ADDR)
3032 /* Print the name of a register for based on its machine mode and number.
3033 This macro is used to print debugging output.
3034 This macro is different from PRINT_REG in that it may be used in
3035 programs that are not linked with aux-output.o. */
3037 #define DEBUG_PRINT_REG(X, CODE, FILE) \
3038 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
3039 static const char * const qi_name[] = QI_REGISTER_NAMES; \
3040 fprintf (FILE, "%d ", REGNO (X)); \
3041 if (REGNO (X) == FLAGS_REG) \
3042 { fputs ("flags", FILE); break; } \
3043 if (REGNO (X) == DIRFLAG_REG) \
3044 { fputs ("dirflag", FILE); break; } \
3045 if (REGNO (X) == FPSR_REG) \
3046 { fputs ("fpsr", FILE); break; } \
3047 if (REGNO (X) == ARG_POINTER_REGNUM) \
3048 { fputs ("argp", FILE); break; } \
3049 if (REGNO (X) == FRAME_POINTER_REGNUM) \
3050 { fputs ("frame", FILE); break; } \
3051 if (STACK_TOP_P (X)) \
3052 { fputs ("st(0)", FILE); break; } \
3054 { fputs (hi_name[REGNO(X)], FILE); break; } \
3055 if (REX_INT_REG_P (X)) \
3057 switch (GET_MODE_SIZE (GET_MODE (X))) \
3061 fprintf (FILE, "r%i", REGNO (X) \
3062 - FIRST_REX_INT_REG + 8); \
3065 fprintf (FILE, "r%id", REGNO (X) \
3066 - FIRST_REX_INT_REG + 8); \
3069 fprintf (FILE, "r%iw", REGNO (X) \
3070 - FIRST_REX_INT_REG + 8); \
3073 fprintf (FILE, "r%ib", REGNO (X) \
3074 - FIRST_REX_INT_REG + 8); \
3079 switch (GET_MODE_SIZE (GET_MODE (X))) \
3082 fputs ("r", FILE); \
3083 fputs (hi_name[REGNO (X)], FILE); \
3086 fputs ("e", FILE); \
3088 fputs (hi_name[REGNO (X)], FILE); \
3091 fputs (qi_name[REGNO (X)], FILE); \
3096 /* a letter which is not needed by the normal asm syntax, which
3097 we can use for operand syntax in the extended asm */
3099 #define ASM_OPERAND_LETTER '#'
3100 #define RET return ""
3101 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
3103 /* Define the codes that are matched by predicates in i386.c. */
3105 #define PREDICATE_CODES \
3106 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3107 SYMBOL_REF, LABEL_REF, CONST}}, \
3108 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3109 SYMBOL_REF, LABEL_REF, CONST}}, \
3110 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3111 SYMBOL_REF, LABEL_REF, CONST}}, \
3112 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3113 SYMBOL_REF, LABEL_REF, CONST}}, \
3114 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3115 SYMBOL_REF, LABEL_REF, CONST}}, \
3116 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3117 SYMBOL_REF, LABEL_REF, CONST}}, \
3118 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3119 SYMBOL_REF, LABEL_REF}}, \
3120 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3121 {"const_int_1_operand", {CONST_INT}}, \
3122 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3123 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3124 LABEL_REF, SUBREG, REG, MEM}}, \
3125 {"pic_symbolic_operand", {CONST}}, \
3126 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3127 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3128 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3129 {"const1_operand", {CONST_INT}}, \
3130 {"const248_operand", {CONST_INT}}, \
3131 {"incdec_operand", {CONST_INT}}, \
3132 {"mmx_reg_operand", {REG}}, \
3133 {"reg_no_sp_operand", {SUBREG, REG}}, \
3134 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3135 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3136 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3137 {"q_regs_operand", {SUBREG, REG}}, \
3138 {"non_q_regs_operand", {SUBREG, REG}}, \
3139 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3140 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3141 GE, UNGE, LTGT, UNEQ}}, \
3142 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3143 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3145 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3146 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3147 UNGE, UNGT, LTGT, UNEQ }}, \
3148 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3149 {"ext_register_operand", {SUBREG, REG}}, \
3150 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3151 {"mult_operator", {MULT}}, \
3152 {"div_operator", {DIV}}, \
3153 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3154 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3155 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3156 LSHIFTRT, ROTATERT}}, \
3157 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3158 {"memory_displacement_operand", {MEM}}, \
3159 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3160 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3161 {"long_memory_operand", {MEM}},
3163 /* A list of predicates that do special things with modes, and so
3164 should not elicit warnings for VOIDmode match_operand. */
3166 #define SPECIAL_MODE_PREDICATES \
3167 "ext_register_operand",
3169 /* CM_32 is used by 32bit ABI
3170 CM_SMALL is small model assuming that all code and data fits in the first
3171 31bits of address space.
3172 CM_KERNEL is model assuming that all code and data fits in the negative
3173 31bits of address space.
3174 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3175 space. Size of data is unlimited.
3176 CM_LARGE is model making no assumptions about size of particular sections.
3178 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3179 tables first in 31bits of address space.
3190 /* Size of the RED_ZONE area. */
3191 #define RED_ZONE_SIZE 128
3192 /* Reserved area of the red zone for temporaries. */
3193 #define RED_ZONE_RESERVE 8
3194 /* Valud of -mcmodel specified by user. */
3195 extern const char *ix86_cmodel_string;
3196 extern enum cmodel ix86_cmodel;
3198 /* Variables in i386.c */
3199 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3200 extern const char *ix86_arch_string; /* for -march=<xxx> */
3201 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3202 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3203 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3204 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3205 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3206 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3207 extern int ix86_regparm; /* ix86_regparm_string as a number */
3208 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3209 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3210 extern enum reg_class const regclass_map[]; /* smalled class containing REGNO */
3211 extern struct rtx_def *ix86_compare_op0; /* operand 0 for comparisons */
3212 extern struct rtx_def *ix86_compare_op1; /* operand 1 for comparisons */
3214 /* To properly truncate FP values into integers, we need to set i387 control
3215 word. We can't emit proper mode switching code before reload, as spills
3216 generated by reload may truncate values incorrectly, but we still can avoid
3217 redundant computation of new control word by the mode switching pass.
3218 The fldcw instructions are still emitted redundantly, but this is probably
3219 not going to be noticeable problem, as most CPUs do have fast path for
3222 The machinery is to emit simple truncation instructions and split them
3223 before reload to instructions having USEs of two memory locations that
3224 are filled by this code to old and new control word.
3226 Post-reload pass may be later used to eliminate the redundant fildcw if
3229 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3231 /* Define this macro if the port needs extra instructions inserted
3232 for mode switching in an optimizing compilation. */
3234 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3236 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3237 initializer for an array of integers. Each initializer element N
3238 refers to an entity that needs mode switching, and specifies the
3239 number of different modes that might need to be set for this
3240 entity. The position of the initializer in the initializer -
3241 starting counting at zero - determines the integer that is used to
3242 refer to the mode-switched entity in question. */
3244 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3246 /* ENTITY is an integer specifying a mode-switched entity. If
3247 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3248 return an integer value not larger than the corresponding element
3249 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3250 must be switched into prior to the execution of INSN. */
3252 #define MODE_NEEDED(ENTITY, I) \
3253 (GET_CODE (I) == CALL_INSN \
3254 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3255 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3256 ? FP_CW_UNINITIALIZED \
3257 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3261 /* This macro specifies the order in which modes for ENTITY are
3262 processed. 0 is the highest priority. */
3264 #define MODE_PRIORITY_TO_MODE(ENTITY, N) N
3266 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3267 is the set of hard registers live at the point where the insn(s)
3268 are to be inserted. */
3270 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3271 (MODE == FP_CW_STORED \
3272 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3273 assign_386_stack_local (HImode, 2)), 0\
3276 /* Avoid renaming of stack registers, as doing so in combination with
3277 scheduling just increases amount of live registers at time and in
3278 the turn amount of fxch instructions needed.
3280 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3282 #define HARD_REGNO_RENAME_OK(src,target) \
3283 ((src) < FIRST_STACK_REG || (src) > LAST_STACK_REG)
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