1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 /* The purpose of this file is to define the characteristics of the i386,
24 independent of assembler syntax or operating system.
26 Three other files build on this one to describe a specific assembler syntax:
27 bsd386.h, att386.h, and sun386.h.
29 The actual tm.h file for a particular system should include
30 this file, and then the file for the appropriate assembler syntax.
32 Many macros that specify assembler syntax are omitted entirely from
33 this file because they really belong in the files for particular
34 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
35 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
36 that start with ASM_ or end in ASM_OP. */
38 /* Redefines for option macros. */
40 #define TARGET_64BIT OPTION_ISA_64BIT
41 #define TARGET_MMX OPTION_ISA_MMX
42 #define TARGET_3DNOW OPTION_ISA_3DNOW
43 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
44 #define TARGET_SSE OPTION_ISA_SSE
45 #define TARGET_SSE2 OPTION_ISA_SSE2
46 #define TARGET_SSE3 OPTION_ISA_SSE3
47 #define TARGET_SSSE3 OPTION_ISA_SSSE3
48 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
49 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
50 #define TARGET_SSE4A OPTION_ISA_SSE4A
52 #include "config/vxworks-dummy.h"
54 /* Algorithm to expand string function with. */
67 #define NAX_STRINGOP_ALGS 4
69 /* Specify what algorithm to use for stringops on known size.
70 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
71 known at compile time or estimated via feedback, the SIZE array
72 is walked in order until MAX is greater then the estimate (or -1
73 means infinity). Corresponding ALG is used then.
74 For example initializer:
75 {{256, loop}, {-1, rep_prefix_4_byte}}
76 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
80 const enum stringop_alg unknown_size;
81 const struct stringop_strategy {
83 const enum stringop_alg alg;
84 } size [NAX_STRINGOP_ALGS];
87 /* Define the specific costs for a given cpu */
89 struct processor_costs {
90 const int add; /* cost of an add instruction */
91 const int lea; /* cost of a lea instruction */
92 const int shift_var; /* variable shift costs */
93 const int shift_const; /* constant shift costs */
94 const int mult_init[5]; /* cost of starting a multiply
95 in QImode, HImode, SImode, DImode, TImode*/
96 const int mult_bit; /* cost of multiply per each bit set */
97 const int divide[5]; /* cost of a divide/mod
98 in QImode, HImode, SImode, DImode, TImode*/
99 int movsx; /* The cost of movsx operation. */
100 int movzx; /* The cost of movzx operation. */
101 const int large_insn; /* insns larger than this cost more */
102 const int move_ratio; /* The threshold of number of scalar
103 memory-to-memory move insns. */
104 const int movzbl_load; /* cost of loading using movzbl */
105 const int int_load[3]; /* cost of loading integer registers
106 in QImode, HImode and SImode relative
107 to reg-reg move (2). */
108 const int int_store[3]; /* cost of storing integer register
109 in QImode, HImode and SImode */
110 const int fp_move; /* cost of reg,reg fld/fst */
111 const int fp_load[3]; /* cost of loading FP register
112 in SFmode, DFmode and XFmode */
113 const int fp_store[3]; /* cost of storing FP register
114 in SFmode, DFmode and XFmode */
115 const int mmx_move; /* cost of moving MMX register. */
116 const int mmx_load[2]; /* cost of loading MMX register
117 in SImode and DImode */
118 const int mmx_store[2]; /* cost of storing MMX register
119 in SImode and DImode */
120 const int sse_move; /* cost of moving SSE register. */
121 const int sse_load[3]; /* cost of loading SSE register
122 in SImode, DImode and TImode*/
123 const int sse_store[3]; /* cost of storing SSE register
124 in SImode, DImode and TImode*/
125 const int mmxsse_to_integer; /* cost of moving mmxsse register to
126 integer and vice versa. */
127 const int prefetch_block; /* bytes moved to cache for prefetch. */
128 const int simultaneous_prefetches; /* number of parallel prefetch
130 const int branch_cost; /* Default value for BRANCH_COST. */
131 const int fadd; /* cost of FADD and FSUB instructions. */
132 const int fmul; /* cost of FMUL instruction. */
133 const int fdiv; /* cost of FDIV instruction. */
134 const int fabs; /* cost of FABS instruction. */
135 const int fchs; /* cost of FCHS instruction. */
136 const int fsqrt; /* cost of FSQRT instruction. */
137 /* Specify what algorithm
138 to use for stringops on unknown size. */
139 struct stringop_algs memcpy[2], memset[2];
142 extern const struct processor_costs *ix86_cost;
144 /* Macros used in the machine description to test the flags. */
146 /* configure can arrange to make this 2, to force a 486. */
148 #ifndef TARGET_CPU_DEFAULT
149 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
152 #ifndef TARGET_FPMATH_DEFAULT
153 #define TARGET_FPMATH_DEFAULT \
154 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
157 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
159 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
160 compile-time constant. */
164 #define TARGET_64BIT 1
166 #define TARGET_64BIT 0
169 #ifndef TARGET_BI_ARCH
171 #if TARGET_64BIT_DEFAULT
172 #define TARGET_64BIT 1
174 #define TARGET_64BIT 0
179 #define HAS_LONG_COND_BRANCH 1
180 #define HAS_LONG_UNCOND_BRANCH 1
182 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
183 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
184 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
185 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
186 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
187 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
188 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
189 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
190 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
191 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
192 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
193 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
194 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
195 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
196 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
197 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
199 /* Feature tests against the various tunings. */
200 enum ix86_tune_indices {
202 X86_TUNE_PUSH_MEMORY,
203 X86_TUNE_ZERO_EXTEND_WITH_AND,
204 X86_TUNE_USE_BIT_TEST,
205 X86_TUNE_UNROLL_STRLEN,
206 X86_TUNE_DEEP_BRANCH_PREDICTION,
207 X86_TUNE_BRANCH_PREDICTION_HINTS,
208 X86_TUNE_DOUBLE_WITH_ADD,
211 X86_TUNE_PARTIAL_REG_STALL,
212 X86_TUNE_PARTIAL_FLAG_REG_STALL,
213 X86_TUNE_USE_HIMODE_FIOP,
214 X86_TUNE_USE_SIMODE_FIOP,
218 X86_TUNE_SPLIT_LONG_MOVES,
219 X86_TUNE_READ_MODIFY_WRITE,
220 X86_TUNE_READ_MODIFY,
221 X86_TUNE_PROMOTE_QIMODE,
222 X86_TUNE_FAST_PREFIX,
223 X86_TUNE_SINGLE_STRINGOP,
224 X86_TUNE_QIMODE_MATH,
225 X86_TUNE_HIMODE_MATH,
226 X86_TUNE_PROMOTE_QI_REGS,
227 X86_TUNE_PROMOTE_HI_REGS,
232 X86_TUNE_INTEGER_DFMODE_MOVES,
233 X86_TUNE_PARTIAL_REG_DEPENDENCY,
234 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
235 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
236 X86_TUNE_SSE_SPLIT_REGS,
237 X86_TUNE_SSE_TYPELESS_STORES,
238 X86_TUNE_SSE_LOAD0_BY_PXOR,
239 X86_TUNE_MEMORY_MISMATCH_STALL,
240 X86_TUNE_PROLOGUE_USING_MOVE,
241 X86_TUNE_EPILOGUE_USING_MOVE,
244 X86_TUNE_INTER_UNIT_MOVES,
245 X86_TUNE_FOUR_JUMP_LIMIT,
249 X86_TUNE_PAD_RETURNS,
250 X86_TUNE_EXT_80387_CONSTANTS,
251 X86_TUNE_SHORTEN_X87_SSE,
252 X86_TUNE_AVOID_VECTOR_DECODE,
253 X86_TUNE_PROMOTE_HIMODE_IMUL,
254 X86_TUNE_SLOW_IMUL_IMM32_MEM,
255 X86_TUNE_SLOW_IMUL_IMM8,
256 X86_TUNE_MOVE_M1_VIA_OR,
257 X86_TUNE_NOT_UNPAIRABLE,
258 X86_TUNE_NOT_VECTORMODE,
263 extern unsigned int ix86_tune_features[X86_TUNE_LAST];
265 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
266 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
267 #define TARGET_ZERO_EXTEND_WITH_AND \
268 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
269 #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
270 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
271 #define TARGET_DEEP_BRANCH_PREDICTION \
272 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
273 #define TARGET_BRANCH_PREDICTION_HINTS \
274 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
275 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
276 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
277 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
278 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
279 #define TARGET_PARTIAL_FLAG_REG_STALL \
280 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
281 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
282 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
283 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
284 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
285 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
286 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
287 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
288 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
289 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
290 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
291 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
292 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
293 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
294 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
295 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
296 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
297 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
298 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
299 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
300 #define TARGET_INTEGER_DFMODE_MOVES \
301 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
302 #define TARGET_PARTIAL_REG_DEPENDENCY \
303 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
304 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
305 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
306 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
307 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
308 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
309 #define TARGET_SSE_TYPELESS_STORES \
310 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
311 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
312 #define TARGET_MEMORY_MISMATCH_STALL \
313 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
314 #define TARGET_PROLOGUE_USING_MOVE \
315 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
316 #define TARGET_EPILOGUE_USING_MOVE \
317 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
318 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
319 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
320 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
321 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
322 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
323 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
324 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
325 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
326 #define TARGET_EXT_80387_CONSTANTS \
327 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
328 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
329 #define TARGET_AVOID_VECTOR_DECODE \
330 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
331 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
332 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
333 #define TARGET_SLOW_IMUL_IMM32_MEM \
334 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
335 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
336 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
337 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
338 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
340 /* Feature tests against the various architecture variations. */
341 enum ix86_arch_indices {
342 X86_ARCH_CMOVE, /* || TARGET_SSE */
351 extern unsigned int ix86_arch_features[X86_ARCH_LAST];
353 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
354 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
355 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
356 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
357 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
359 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
361 extern int x86_prefetch_sse;
363 #define TARGET_ABM x86_abm
364 #define TARGET_CMPXCHG16B x86_cmpxchg16b
365 #define TARGET_POPCNT x86_popcnt
366 #define TARGET_PREFETCH_SSE x86_prefetch_sse
367 #define TARGET_SAHF x86_sahf
368 #define TARGET_RECIP x86_recip
370 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
372 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
373 #define TARGET_MIX_SSE_I387 \
374 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
376 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
377 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
378 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
379 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
381 extern int ix86_isa_flags;
383 #ifndef TARGET_64BIT_DEFAULT
384 #define TARGET_64BIT_DEFAULT 0
386 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
387 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
390 /* Fence to use after loop using storent. */
392 extern tree x86_mfence;
393 #define FENCE_FOLLOWING_MOVNT x86_mfence
395 /* Once GDB has been enhanced to deal with functions without frame
396 pointers, we can change this to allow for elimination of
397 the frame pointer in leaf functions. */
398 #define TARGET_DEFAULT 0
400 /* Extra bits to force. */
401 #define TARGET_SUBTARGET_DEFAULT 0
402 #define TARGET_SUBTARGET_ISA_DEFAULT 0
404 /* Extra bits to force on w/ 32-bit mode. */
405 #define TARGET_SUBTARGET32_DEFAULT 0
406 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
408 /* Extra bits to force on w/ 64-bit mode. */
409 #define TARGET_SUBTARGET64_DEFAULT 0
410 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
412 /* This is not really a target flag, but is done this way so that
413 it's analogous to similar code for Mach-O on PowerPC. darwin.h
414 redefines this to 1. */
415 #define TARGET_MACHO 0
417 /* Likewise, for the Windows 64-bit ABI. */
418 #define TARGET_64BIT_MS_ABI 0
420 /* Subtargets may reset this to 1 in order to enable 96-bit long double
421 with the rounding mode forced to 53 bits. */
422 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
424 /* Sometimes certain combinations of command options do not make
425 sense on a particular target machine. You can define a macro
426 `OVERRIDE_OPTIONS' to take account of this. This macro, if
427 defined, is executed once just after all the command options have
430 Don't use this macro to turn on various extra optimizations for
431 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
433 #define OVERRIDE_OPTIONS override_options ()
435 /* Define this to change the optimizations performed by default. */
436 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
437 optimization_options ((LEVEL), (SIZE))
439 /* -march=native handling only makes sense with compiler running on
440 an x86 or x86_64 chip. If changing this condition, also change
441 the condition in driver-i386.c. */
442 #if defined(__i386__) || defined(__x86_64__)
443 /* In driver-i386.c. */
444 extern const char *host_detect_local_cpu (int argc, const char **argv);
445 #define EXTRA_SPEC_FUNCTIONS \
446 { "local_cpu_detect", host_detect_local_cpu },
447 #define HAVE_LOCAL_CPU_DETECT
450 /* Support for configure-time defaults of some command line options.
451 The order here is important so that -march doesn't squash the
452 tune or cpu values. */
453 #define OPTION_DEFAULT_SPECS \
454 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
455 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
456 {"arch", "%{!march=*:-march=%(VALUE)}"}
458 /* Specs for the compiler proper */
461 #define CC1_CPU_SPEC_1 "\
463 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
465 %{mintel-syntax:-masm=intel \
466 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
467 %{mno-intel-syntax:-masm=att \
468 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
470 #ifndef HAVE_LOCAL_CPU_DETECT
471 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
473 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
474 "%{march=native:%<march=native %:local_cpu_detect(arch) \
475 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
476 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
480 /* Target CPU builtins. */
481 #define TARGET_CPU_CPP_BUILTINS() \
484 size_t arch_len = strlen (ix86_arch_string); \
485 size_t tune_len = strlen (ix86_tune_string); \
486 int last_arch_char = ix86_arch_string[arch_len - 1]; \
487 int last_tune_char = ix86_tune_string[tune_len - 1]; \
491 builtin_assert ("cpu=x86_64"); \
492 builtin_assert ("machine=x86_64"); \
493 builtin_define ("__amd64"); \
494 builtin_define ("__amd64__"); \
495 builtin_define ("__x86_64"); \
496 builtin_define ("__x86_64__"); \
500 builtin_assert ("cpu=i386"); \
501 builtin_assert ("machine=i386"); \
502 builtin_define_std ("i386"); \
505 /* Built-ins based on -mtune= (or -march= if no \
508 builtin_define ("__tune_i386__"); \
509 else if (TARGET_486) \
510 builtin_define ("__tune_i486__"); \
511 else if (TARGET_PENTIUM) \
513 builtin_define ("__tune_i586__"); \
514 builtin_define ("__tune_pentium__"); \
515 if (last_tune_char == 'x') \
516 builtin_define ("__tune_pentium_mmx__"); \
518 else if (TARGET_PENTIUMPRO) \
520 builtin_define ("__tune_i686__"); \
521 builtin_define ("__tune_pentiumpro__"); \
522 switch (last_tune_char) \
525 builtin_define ("__tune_pentium3__"); \
528 builtin_define ("__tune_pentium2__"); \
532 else if (TARGET_GEODE) \
534 builtin_define ("__tune_geode__"); \
536 else if (TARGET_K6) \
538 builtin_define ("__tune_k6__"); \
539 if (last_tune_char == '2') \
540 builtin_define ("__tune_k6_2__"); \
541 else if (last_tune_char == '3') \
542 builtin_define ("__tune_k6_3__"); \
544 else if (TARGET_ATHLON) \
546 builtin_define ("__tune_athlon__"); \
547 /* Only plain "athlon" lacks SSE. */ \
548 if (last_tune_char != 'n') \
549 builtin_define ("__tune_athlon_sse__"); \
551 else if (TARGET_K8) \
552 builtin_define ("__tune_k8__"); \
553 else if (TARGET_AMDFAM10) \
554 builtin_define ("__tune_amdfam10__"); \
555 else if (TARGET_PENTIUM4) \
556 builtin_define ("__tune_pentium4__"); \
557 else if (TARGET_NOCONA) \
558 builtin_define ("__tune_nocona__"); \
559 else if (TARGET_CORE2) \
560 builtin_define ("__tune_core2__"); \
563 builtin_define ("__MMX__"); \
565 builtin_define ("__3dNOW__"); \
566 if (TARGET_3DNOW_A) \
567 builtin_define ("__3dNOW_A__"); \
569 builtin_define ("__SSE__"); \
571 builtin_define ("__SSE2__"); \
573 builtin_define ("__SSE3__"); \
575 builtin_define ("__SSSE3__"); \
577 builtin_define ("__SSE4_1__"); \
579 builtin_define ("__SSE4_2__"); \
581 builtin_define ("__SSE4A__"); \
582 if (TARGET_SSE_MATH && TARGET_SSE) \
583 builtin_define ("__SSE_MATH__"); \
584 if (TARGET_SSE_MATH && TARGET_SSE2) \
585 builtin_define ("__SSE2_MATH__"); \
587 /* Built-ins based on -march=. */ \
588 if (ix86_arch == PROCESSOR_I486) \
590 builtin_define ("__i486"); \
591 builtin_define ("__i486__"); \
593 else if (ix86_arch == PROCESSOR_PENTIUM) \
595 builtin_define ("__i586"); \
596 builtin_define ("__i586__"); \
597 builtin_define ("__pentium"); \
598 builtin_define ("__pentium__"); \
599 if (last_arch_char == 'x') \
600 builtin_define ("__pentium_mmx__"); \
602 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
604 builtin_define ("__i686"); \
605 builtin_define ("__i686__"); \
606 builtin_define ("__pentiumpro"); \
607 builtin_define ("__pentiumpro__"); \
609 else if (ix86_arch == PROCESSOR_GEODE) \
611 builtin_define ("__geode"); \
612 builtin_define ("__geode__"); \
614 else if (ix86_arch == PROCESSOR_K6) \
617 builtin_define ("__k6"); \
618 builtin_define ("__k6__"); \
619 if (last_arch_char == '2') \
620 builtin_define ("__k6_2__"); \
621 else if (last_arch_char == '3') \
622 builtin_define ("__k6_3__"); \
624 else if (ix86_arch == PROCESSOR_ATHLON) \
626 builtin_define ("__athlon"); \
627 builtin_define ("__athlon__"); \
628 /* Only plain "athlon" lacks SSE. */ \
629 if (last_arch_char != 'n') \
630 builtin_define ("__athlon_sse__"); \
632 else if (ix86_arch == PROCESSOR_K8) \
634 builtin_define ("__k8"); \
635 builtin_define ("__k8__"); \
637 else if (ix86_arch == PROCESSOR_AMDFAM10) \
639 builtin_define ("__amdfam10"); \
640 builtin_define ("__amdfam10__"); \
642 else if (ix86_arch == PROCESSOR_PENTIUM4) \
644 builtin_define ("__pentium4"); \
645 builtin_define ("__pentium4__"); \
647 else if (ix86_arch == PROCESSOR_NOCONA) \
649 builtin_define ("__nocona"); \
650 builtin_define ("__nocona__"); \
652 else if (ix86_arch == PROCESSOR_CORE2) \
654 builtin_define ("__core2"); \
655 builtin_define ("__core2__"); \
660 #define TARGET_CPU_DEFAULT_i386 0
661 #define TARGET_CPU_DEFAULT_i486 1
662 #define TARGET_CPU_DEFAULT_pentium 2
663 #define TARGET_CPU_DEFAULT_pentium_mmx 3
664 #define TARGET_CPU_DEFAULT_pentiumpro 4
665 #define TARGET_CPU_DEFAULT_pentium2 5
666 #define TARGET_CPU_DEFAULT_pentium3 6
667 #define TARGET_CPU_DEFAULT_pentium4 7
668 #define TARGET_CPU_DEFAULT_geode 8
669 #define TARGET_CPU_DEFAULT_k6 9
670 #define TARGET_CPU_DEFAULT_k6_2 10
671 #define TARGET_CPU_DEFAULT_k6_3 11
672 #define TARGET_CPU_DEFAULT_athlon 12
673 #define TARGET_CPU_DEFAULT_athlon_sse 13
674 #define TARGET_CPU_DEFAULT_k8 14
675 #define TARGET_CPU_DEFAULT_pentium_m 15
676 #define TARGET_CPU_DEFAULT_prescott 16
677 #define TARGET_CPU_DEFAULT_nocona 17
678 #define TARGET_CPU_DEFAULT_core2 18
679 #define TARGET_CPU_DEFAULT_generic 19
680 #define TARGET_CPU_DEFAULT_amdfam10 20
682 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
683 "pentiumpro", "pentium2", "pentium3", \
684 "pentium4", "geode", "k6", "k6-2", "k6-3", \
685 "athlon", "athlon-4", "k8", \
686 "pentium-m", "prescott", "nocona", \
687 "core2", "generic", "amdfam10"}
690 #define CC1_SPEC "%(cc1_cpu) "
693 /* This macro defines names of additional specifications to put in the
694 specs that can be used in various specifications like CC1_SPEC. Its
695 definition is an initializer with a subgrouping for each command option.
697 Each subgrouping contains a string constant, that defines the
698 specification name, and a string constant that used by the GCC driver
701 Do not define this macro if it does not need to do anything. */
703 #ifndef SUBTARGET_EXTRA_SPECS
704 #define SUBTARGET_EXTRA_SPECS
707 #define EXTRA_SPECS \
708 { "cc1_cpu", CC1_CPU_SPEC }, \
709 SUBTARGET_EXTRA_SPECS
711 /* target machine storage layout */
713 #define LONG_DOUBLE_TYPE_SIZE 80
715 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
716 FPU, assume that the fpcw is set to extended precision; when using
717 only SSE, rounding is correct; when using both SSE and the FPU,
718 the rounding precision is indeterminate, since either may be chosen
719 apparently at random. */
720 #define TARGET_FLT_EVAL_METHOD \
721 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
723 #define SHORT_TYPE_SIZE 16
724 #define INT_TYPE_SIZE 32
725 #define FLOAT_TYPE_SIZE 32
726 #define LONG_TYPE_SIZE BITS_PER_WORD
727 #define DOUBLE_TYPE_SIZE 64
728 #define LONG_LONG_TYPE_SIZE 64
730 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
731 #define MAX_BITS_PER_WORD 64
733 #define MAX_BITS_PER_WORD 32
736 /* Define this if most significant byte of a word is the lowest numbered. */
737 /* That is true on the 80386. */
739 #define BITS_BIG_ENDIAN 0
741 /* Define this if most significant byte of a word is the lowest numbered. */
742 /* That is not true on the 80386. */
743 #define BYTES_BIG_ENDIAN 0
745 /* Define this if most significant word of a multiword number is the lowest
747 /* Not true for 80386 */
748 #define WORDS_BIG_ENDIAN 0
750 /* Width of a word, in units (bytes). */
751 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
753 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
755 #define MIN_UNITS_PER_WORD 4
758 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
759 #define PARM_BOUNDARY BITS_PER_WORD
761 /* Boundary (in *bits*) on which stack pointer should be aligned. */
762 #define STACK_BOUNDARY BITS_PER_WORD
764 /* Boundary (in *bits*) on which the stack pointer prefers to be
765 aligned; the compiler cannot rely on having this alignment. */
766 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
768 /* As of July 2001, many runtimes do not align the stack properly when
769 entering main. This causes expand_main_function to forcibly align
770 the stack, which results in aligned frames for functions called from
771 main, though it does nothing for the alignment of main itself. */
772 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
773 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
775 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
776 mandatory for the 64-bit ABI, and may or may not be true for other
777 operating systems. */
778 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
780 /* Minimum allocation boundary for the code of a function. */
781 #define FUNCTION_BOUNDARY 8
783 /* C++ stores the virtual bit in the lowest bit of function pointers. */
784 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
786 /* Alignment of field after `int : 0' in a structure. */
788 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
790 /* Minimum size in bits of the largest boundary to which any
791 and all fundamental data types supported by the hardware
792 might need to be aligned. No data type wants to be aligned
795 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
796 and Pentium Pro XFmode values at 128 bit boundaries. */
798 #define BIGGEST_ALIGNMENT 128
800 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
801 #define ALIGN_MODE_128(MODE) \
802 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
804 /* The published ABIs say that doubles should be aligned on word
805 boundaries, so lower the alignment for structure fields unless
806 -malign-double is set. */
808 /* ??? Blah -- this macro is used directly by libobjc. Since it
809 supports no vector modes, cut out the complexity and fall back
810 on BIGGEST_FIELD_ALIGNMENT. */
811 #ifdef IN_TARGET_LIBS
813 #define BIGGEST_FIELD_ALIGNMENT 128
815 #define BIGGEST_FIELD_ALIGNMENT 32
818 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
819 x86_field_alignment (FIELD, COMPUTED)
822 /* If defined, a C expression to compute the alignment given to a
823 constant that is being placed in memory. EXP is the constant
824 and ALIGN is the alignment that the object would ordinarily have.
825 The value of this macro is used instead of that alignment to align
828 If this macro is not defined, then ALIGN is used.
830 The typical use of this macro is to increase alignment for string
831 constants to be word aligned so that `strcpy' calls that copy
832 constants can be done inline. */
834 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
836 /* If defined, a C expression to compute the alignment for a static
837 variable. TYPE is the data type, and ALIGN is the alignment that
838 the object would ordinarily have. The value of this macro is used
839 instead of that alignment to align the object.
841 If this macro is not defined, then ALIGN is used.
843 One use of this macro is to increase alignment of medium-size
844 data to make it all fit in fewer cache lines. Another is to
845 cause character arrays to be word-aligned so that `strcpy' calls
846 that copy constants to character arrays can be done inline. */
848 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
850 /* If defined, a C expression to compute the alignment for a local
851 variable. TYPE is the data type, and ALIGN is the alignment that
852 the object would ordinarily have. The value of this macro is used
853 instead of that alignment to align the object.
855 If this macro is not defined, then ALIGN is used.
857 One use of this macro is to increase alignment of medium-size
858 data to make it all fit in fewer cache lines. */
860 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
862 /* If defined, a C expression that gives the alignment boundary, in
863 bits, of an argument with the specified mode and type. If it is
864 not defined, `PARM_BOUNDARY' is used for all arguments. */
866 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
867 ix86_function_arg_boundary ((MODE), (TYPE))
869 /* Set this nonzero if move instructions will actually fail to work
870 when given unaligned data. */
871 #define STRICT_ALIGNMENT 0
873 /* If bit field type is int, don't let it cross an int,
874 and give entire struct the alignment of an int. */
875 /* Required on the 386 since it doesn't have bit-field insns. */
876 #define PCC_BITFIELD_TYPE_MATTERS 1
878 /* Standard register usage. */
880 /* This processor has special stack-like registers. See reg-stack.c
884 #define IS_STACK_MODE(MODE) \
885 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
886 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
889 /* Number of actual hardware registers.
890 The hardware registers are assigned numbers for the compiler
891 from 0 to just below FIRST_PSEUDO_REGISTER.
892 All registers that the compiler knows about must be given numbers,
893 even those that are not normally considered general registers.
895 In the 80386 we give the 8 general purpose registers the numbers 0-7.
896 We number the floating point registers 8-15.
897 Note that registers 0-7 can be accessed as a short or int,
898 while only 0-3 may be used with byte `mov' instructions.
900 Reg 16 does not correspond to any hardware register, but instead
901 appears in the RTL as an argument pointer prior to reload, and is
902 eliminated during reloading in favor of either the stack or frame
905 #define FIRST_PSEUDO_REGISTER 53
907 /* Number of hardware registers that go into the DWARF-2 unwind info.
908 If not defined, equals FIRST_PSEUDO_REGISTER. */
910 #define DWARF_FRAME_REGISTERS 17
912 /* 1 for registers that have pervasive standard uses
913 and are not available for the register allocator.
914 On the 80386, the stack pointer is such, as is the arg pointer.
916 The value is zero if the register is not fixed on either 32 or
917 64 bit targets, one if the register if fixed on both 32 and 64
918 bit targets, two if it is only fixed on 32bit targets and three
919 if its only fixed on 64bit targets.
920 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
922 #define FIXED_REGISTERS \
923 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
924 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
925 /*arg,flags,fpsr,fpcr,frame*/ \
927 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
928 0, 0, 0, 0, 0, 0, 0, 0, \
929 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
930 0, 0, 0, 0, 0, 0, 0, 0, \
931 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
932 2, 2, 2, 2, 2, 2, 2, 2, \
933 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
934 2, 2, 2, 2, 2, 2, 2, 2}
937 /* 1 for registers not available across function calls.
938 These must include the FIXED_REGISTERS and also any
939 registers that can be used without being saved.
940 The latter must include the registers where values are returned
941 and the register where structure-value addresses are passed.
942 Aside from that, you can include as many other registers as you like.
944 The value is zero if the register is not call used on either 32 or
945 64 bit targets, one if the register if call used on both 32 and 64
946 bit targets, two if it is only call used on 32bit targets and three
947 if its only call used on 64bit targets.
948 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
950 #define CALL_USED_REGISTERS \
951 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
952 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
953 /*arg,flags,fpsr,fpcr,frame*/ \
955 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
956 1, 1, 1, 1, 1, 1, 1, 1, \
957 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
958 1, 1, 1, 1, 1, 1, 1, 1, \
959 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
960 1, 1, 1, 1, 2, 2, 2, 2, \
961 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
962 1, 1, 1, 1, 1, 1, 1, 1} \
964 /* Order in which to allocate registers. Each register must be
965 listed once, even those in FIXED_REGISTERS. List frame pointer
966 late and fixed registers last. Note that, in general, we prefer
967 registers listed in CALL_USED_REGISTERS, keeping the others
968 available for storage of persistent values.
970 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
971 so this is just empty initializer for array. */
973 #define REG_ALLOC_ORDER \
974 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
975 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
976 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
979 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
980 to be rearranged based on a particular function. When using sse math,
981 we want to allocate SSE before x87 registers and vice versa. */
983 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
986 /* Macro to conditionally modify fixed_regs/call_used_regs. */
987 #define CONDITIONAL_REGISTER_USAGE \
991 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
993 if (fixed_regs[i] > 1) \
994 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
995 if (call_used_regs[i] > 1) \
996 call_used_regs[i] = (call_used_regs[i] \
997 == (TARGET_64BIT ? 3 : 2)); \
999 j = PIC_OFFSET_TABLE_REGNUM; \
1000 if (j != INVALID_REGNUM) \
1002 fixed_regs[j] = 1; \
1003 call_used_regs[j] = 1; \
1008 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1009 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
1010 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1015 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1016 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
1017 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1019 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
1023 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
1024 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1025 if (TEST_HARD_REG_BIT (x, i)) \
1026 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1028 if (! TARGET_64BIT) \
1031 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
1032 reg_names[i] = ""; \
1033 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
1034 reg_names[i] = ""; \
1036 if (TARGET_64BIT_MS_ABI) \
1038 call_used_regs[4 /*RSI*/] = 0; \
1039 call_used_regs[5 /*RDI*/] = 0; \
1043 /* Return number of consecutive hard regs needed starting at reg REGNO
1044 to hold something of mode MODE.
1045 This is ordinarily the length in words of a value of mode MODE
1046 but can be less for certain modes in special long registers.
1048 Actually there are no two word move instructions for consecutive
1049 registers. And only registers 0-3 may have mov byte instructions
1053 #define HARD_REGNO_NREGS(REGNO, MODE) \
1054 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1055 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1056 : ((MODE) == XFmode \
1057 ? (TARGET_64BIT ? 2 : 3) \
1058 : (MODE) == XCmode \
1059 ? (TARGET_64BIT ? 4 : 6) \
1060 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1062 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1063 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1064 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1066 : ((MODE) == XFmode || (MODE) == XCmode)) \
1069 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1071 #define VALID_SSE2_REG_MODE(MODE) \
1072 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1073 || (MODE) == V2DImode || (MODE) == DFmode)
1075 #define VALID_SSE_REG_MODE(MODE) \
1076 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1077 || (MODE) == SFmode || (MODE) == TFmode)
1079 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1080 ((MODE) == V2SFmode || (MODE) == SFmode)
1082 #define VALID_MMX_REG_MODE(MODE) \
1083 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1084 || (MODE) == V2SImode || (MODE) == SImode)
1086 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1087 place emms and femms instructions. */
1088 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
1090 #define VALID_FP_MODE_P(MODE) \
1091 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1092 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1094 #define VALID_INT_MODE_P(MODE) \
1095 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1096 || (MODE) == DImode \
1097 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1098 || (MODE) == CDImode \
1099 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1100 || (MODE) == TFmode || (MODE) == TCmode)))
1102 /* Return true for modes passed in SSE registers. */
1103 #define SSE_REG_MODE_P(MODE) \
1104 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1105 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1106 || (MODE) == V4SFmode || (MODE) == V4SImode)
1108 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1110 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1111 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1113 /* Value is 1 if it is a good idea to tie two pseudo registers
1114 when one has mode MODE1 and one has mode MODE2.
1115 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1116 for any hard reg, then this must be 0 for correct output. */
1118 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1120 /* It is possible to write patterns to move flags; but until someone
1122 #define AVOID_CCMODE_COPIES
1124 /* Specify the modes required to caller save a given hard regno.
1125 We do this on i386 to prevent flags from being saved at all.
1127 Kill any attempts to combine saving of modes. */
1129 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1130 (CC_REGNO_P (REGNO) ? VOIDmode \
1131 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1132 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1133 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1134 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1136 /* Specify the registers used for certain standard purposes.
1137 The values of these macros are register numbers. */
1139 /* on the 386 the pc register is %eip, and is not usable as a general
1140 register. The ordinary mov instructions won't work */
1141 /* #define PC_REGNUM */
1143 /* Register to use for pushing function arguments. */
1144 #define STACK_POINTER_REGNUM 7
1146 /* Base register for access to local variables of the function. */
1147 #define HARD_FRAME_POINTER_REGNUM 6
1149 /* Base register for access to local variables of the function. */
1150 #define FRAME_POINTER_REGNUM 20
1152 /* First floating point reg */
1153 #define FIRST_FLOAT_REG 8
1155 /* First & last stack-like regs */
1156 #define FIRST_STACK_REG FIRST_FLOAT_REG
1157 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1159 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1160 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1162 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1163 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1165 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1166 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1168 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1169 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1171 /* Value should be nonzero if functions must have frame pointers.
1172 Zero means the frame pointer need not be set up (and parms
1173 may be accessed via the stack pointer) in functions that seem suitable.
1174 This is computed in `reload', in reload1.c. */
1175 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1177 /* Override this in other tm.h files to cope with various OS lossage
1178 requiring a frame pointer. */
1179 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1180 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1183 /* Make sure we can access arbitrary call frames. */
1184 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1186 /* Base register for access to arguments of the function. */
1187 #define ARG_POINTER_REGNUM 16
1189 /* Register in which static-chain is passed to a function.
1190 We do use ECX as static chain register for 32 bit ABI. On the
1191 64bit ABI, ECX is an argument register, so we use R10 instead. */
1192 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1194 /* Register to hold the addressing base for position independent
1195 code access to data items. We don't use PIC pointer for 64bit
1196 mode. Define the regnum to dummy value to prevent gcc from
1197 pessimizing code dealing with EBX.
1199 To avoid clobbering a call-saved register unnecessarily, we renumber
1200 the pic register when possible. The change is visible after the
1201 prologue has been emitted. */
1203 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1205 #define PIC_OFFSET_TABLE_REGNUM \
1206 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1207 || !flag_pic ? INVALID_REGNUM \
1208 : reload_completed ? REGNO (pic_offset_table_rtx) \
1209 : REAL_PIC_OFFSET_TABLE_REGNUM)
1211 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1213 /* A C expression which can inhibit the returning of certain function
1214 values in registers, based on the type of value. A nonzero value
1215 says to return the function value in memory, just as large
1216 structures are always returned. Here TYPE will be a C expression
1217 of type `tree', representing the data type of the value.
1219 Note that values of mode `BLKmode' must be explicitly handled by
1220 this macro. Also, the option `-fpcc-struct-return' takes effect
1221 regardless of this macro. On most systems, it is possible to
1222 leave the macro undefined; this causes a default definition to be
1223 used, whose value is the constant 1 for `BLKmode' values, and 0
1226 Do not use this macro to indicate that structures and unions
1227 should always be returned in memory. You should instead use
1228 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1230 #define RETURN_IN_MEMORY(TYPE) \
1231 ix86_return_in_memory (TYPE)
1233 /* This is overridden by <cygwin.h>. */
1234 #define MS_AGGREGATE_RETURN 0
1236 /* This is overridden by <netware.h>. */
1237 #define KEEP_AGGREGATE_RETURN_POINTER 0
1239 /* Define the classes of registers for register constraints in the
1240 machine description. Also define ranges of constants.
1242 One of the classes must always be named ALL_REGS and include all hard regs.
1243 If there is more than one class, another class must be named NO_REGS
1244 and contain no registers.
1246 The name GENERAL_REGS must be the name of a class (or an alias for
1247 another name such as ALL_REGS). This is the class of registers
1248 that is allowed by "g" or "r" in a register constraint.
1249 Also, registers outside this class are allocated only when
1250 instructions express preferences for them.
1252 The classes must be numbered in nondecreasing order; that is,
1253 a larger-numbered class must never be contained completely
1254 in a smaller-numbered class.
1256 For any two classes, it is very desirable that there be another
1257 class that represents their union.
1259 It might seem that class BREG is unnecessary, since no useful 386
1260 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1261 and the "b" register constraint is useful in asms for syscalls.
1263 The flags, fpsr and fpcr registers are in no class. */
1268 AREG, DREG, CREG, BREG, SIREG, DIREG,
1269 AD_REGS, /* %eax/%edx for DImode */
1270 Q_REGS, /* %eax %ebx %ecx %edx */
1271 NON_Q_REGS, /* %esi %edi %ebp %esp */
1272 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1273 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1274 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1275 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1286 ALL_REGS, LIM_REG_CLASSES
1289 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1291 #define INTEGER_CLASS_P(CLASS) \
1292 reg_class_subset_p ((CLASS), GENERAL_REGS)
1293 #define FLOAT_CLASS_P(CLASS) \
1294 reg_class_subset_p ((CLASS), FLOAT_REGS)
1295 #define SSE_CLASS_P(CLASS) \
1296 reg_class_subset_p ((CLASS), SSE_REGS)
1297 #define MMX_CLASS_P(CLASS) \
1298 ((CLASS) == MMX_REGS)
1299 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1300 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1301 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1302 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1303 #define MAYBE_SSE_CLASS_P(CLASS) \
1304 reg_classes_intersect_p (SSE_REGS, (CLASS))
1305 #define MAYBE_MMX_CLASS_P(CLASS) \
1306 reg_classes_intersect_p (MMX_REGS, (CLASS))
1308 #define Q_CLASS_P(CLASS) \
1309 reg_class_subset_p ((CLASS), Q_REGS)
1311 /* Give names of register classes as strings for dump file. */
1313 #define REG_CLASS_NAMES \
1315 "AREG", "DREG", "CREG", "BREG", \
1318 "Q_REGS", "NON_Q_REGS", \
1322 "FP_TOP_REG", "FP_SECOND_REG", \
1327 "FP_TOP_SSE_REGS", \
1328 "FP_SECOND_SSE_REGS", \
1332 "FLOAT_INT_SSE_REGS", \
1335 /* Define which registers fit in which classes.
1336 This is an initializer for a vector of HARD_REG_SET
1337 of length N_REG_CLASSES. */
1339 #define REG_CLASS_CONTENTS \
1341 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1342 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1343 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1344 { 0x03, 0x0 }, /* AD_REGS */ \
1345 { 0x0f, 0x0 }, /* Q_REGS */ \
1346 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1347 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1348 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1349 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1350 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1351 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1352 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1353 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1354 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1355 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1356 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1357 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1358 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1359 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1360 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1361 { 0xffffffff,0x1fffff } \
1364 /* The same information, inverted:
1365 Return the class number of the smallest class containing
1366 reg number REGNO. This could be a conditional expression
1367 or could index an array. */
1369 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1371 /* When defined, the compiler allows registers explicitly used in the
1372 rtl to be used as spill registers but prevents the compiler from
1373 extending the lifetime of these registers. */
1375 #define SMALL_REGISTER_CLASSES 1
1377 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1379 #define GENERAL_REGNO_P(N) \
1380 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1382 #define GENERAL_REG_P(X) \
1383 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1385 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1387 #define REX_INT_REGNO_P(N) \
1388 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1389 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1391 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1392 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1393 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1394 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1396 #define X87_FLOAT_MODE_P(MODE) \
1397 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1399 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1400 #define SSE_REGNO_P(N) \
1401 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1402 || REX_SSE_REGNO_P (N))
1404 #define REX_SSE_REGNO_P(N) \
1405 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1407 #define SSE_REGNO(N) \
1408 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1410 #define SSE_FLOAT_MODE_P(MODE) \
1411 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1413 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1414 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1416 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1417 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1419 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1421 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1422 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1424 /* The class value for index registers, and the one for base regs. */
1426 #define INDEX_REG_CLASS INDEX_REGS
1427 #define BASE_REG_CLASS GENERAL_REGS
1429 /* Place additional restrictions on the register class to use when it
1430 is necessary to be able to hold a value of mode MODE in a reload
1431 register for which class CLASS would ordinarily be used. */
1433 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1434 ((MODE) == QImode && !TARGET_64BIT \
1435 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1436 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1439 /* Given an rtx X being reloaded into a reg required to be
1440 in class CLASS, return the class of reg to actually use.
1441 In general this is just CLASS; but on some machines
1442 in some cases it is preferable to use a more restrictive class.
1443 On the 80386 series, we prevent floating constants from being
1444 reloaded into floating registers (since no move-insn can do that)
1445 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1447 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1448 QImode must go into class Q_REGS.
1449 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1450 movdf to do mem-to-mem moves through integer regs. */
1452 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1453 ix86_preferred_reload_class ((X), (CLASS))
1455 /* Discourage putting floating-point values in SSE registers unless
1456 SSE math is being used, and likewise for the 387 registers. */
1458 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1459 ix86_preferred_output_reload_class ((X), (CLASS))
1461 /* If we are copying between general and FP registers, we need a memory
1462 location. The same is true for SSE and MMX registers. */
1463 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1464 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1466 /* QImode spills from non-QI registers need a scratch. This does not
1467 happen often -- the only example so far requires an uninitialized
1470 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1471 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1472 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1475 /* Return the maximum number of consecutive registers
1476 needed to represent mode MODE in a register of class CLASS. */
1477 /* On the 80386, this is the size of MODE in words,
1478 except in the FP regs, where a single reg is always enough. */
1479 #define CLASS_MAX_NREGS(CLASS, MODE) \
1480 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1481 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1482 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1483 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1485 /* A C expression whose value is nonzero if pseudos that have been
1486 assigned to registers of class CLASS would likely be spilled
1487 because registers of CLASS are needed for spill registers.
1489 The default value of this macro returns 1 if CLASS has exactly one
1490 register and zero otherwise. On most machines, this default
1491 should be used. Only define this macro to some other expression
1492 if pseudo allocated by `local-alloc.c' end up in memory because
1493 their hard registers were needed for spill registers. If this
1494 macro returns nonzero for those classes, those pseudos will only
1495 be allocated by `global.c', which knows how to reallocate the
1496 pseudo to another register. If there would not be another
1497 register available for reallocation, you should not change the
1498 definition of this macro since the only effect of such a
1499 definition would be to slow down register allocation. */
1501 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1502 (((CLASS) == AREG) \
1503 || ((CLASS) == DREG) \
1504 || ((CLASS) == CREG) \
1505 || ((CLASS) == BREG) \
1506 || ((CLASS) == AD_REGS) \
1507 || ((CLASS) == SIREG) \
1508 || ((CLASS) == DIREG) \
1509 || ((CLASS) == FP_TOP_REG) \
1510 || ((CLASS) == FP_SECOND_REG))
1512 /* Return a class of registers that cannot change FROM mode to TO mode. */
1514 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1515 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1517 /* Stack layout; function entry, exit and calling. */
1519 /* Define this if pushing a word on the stack
1520 makes the stack pointer a smaller address. */
1521 #define STACK_GROWS_DOWNWARD
1523 /* Define this to nonzero if the nominal address of the stack frame
1524 is at the high-address end of the local variables;
1525 that is, each additional local variable allocated
1526 goes at a more negative offset in the frame. */
1527 #define FRAME_GROWS_DOWNWARD 1
1529 /* Offset within stack frame to start allocating local variables at.
1530 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1531 first local allocated. Otherwise, it is the offset to the BEGINNING
1532 of the first local allocated. */
1533 #define STARTING_FRAME_OFFSET 0
1535 /* If we generate an insn to push BYTES bytes,
1536 this says how many the stack pointer really advances by.
1537 On 386, we have pushw instruction that decrements by exactly 2 no
1538 matter what the position was, there is no pushb.
1539 But as CIE data alignment factor on this arch is -4, we need to make
1540 sure all stack pointer adjustments are in multiple of 4.
1542 For 64bit ABI we round up to 8 bytes.
1545 #define PUSH_ROUNDING(BYTES) \
1547 ? (((BYTES) + 7) & (-8)) \
1548 : (((BYTES) + 3) & (-4)))
1550 /* If defined, the maximum amount of space required for outgoing arguments will
1551 be computed and placed into the variable
1552 `current_function_outgoing_args_size'. No space will be pushed onto the
1553 stack for each call; instead, the function prologue should increase the stack
1554 frame size by this amount. */
1556 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1558 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1559 instructions to pass outgoing arguments. */
1561 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1563 /* We want the stack and args grow in opposite directions, even if
1565 #define PUSH_ARGS_REVERSED 1
1567 /* Offset of first parameter from the argument pointer register value. */
1568 #define FIRST_PARM_OFFSET(FNDECL) 0
1570 /* Define this macro if functions should assume that stack space has been
1571 allocated for arguments even when their values are passed in registers.
1573 The value of this macro is the size, in bytes, of the area reserved for
1574 arguments passed in registers for the function represented by FNDECL.
1576 This space can be allocated by the caller, or be a part of the
1577 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1579 #define REG_PARM_STACK_SPACE(FNDECL) 0
1581 /* Value is the number of bytes of arguments automatically
1582 popped when returning from a subroutine call.
1583 FUNDECL is the declaration node of the function (as a tree),
1584 FUNTYPE is the data type of the function (as a tree),
1585 or for a library call it is an identifier node for the subroutine name.
1586 SIZE is the number of bytes of arguments passed on the stack.
1588 On the 80386, the RTD insn may be used to pop them if the number
1589 of args is fixed, but if the number is variable then the caller
1590 must pop them all. RTD can't be used for library calls now
1591 because the library is compiled with the Unix compiler.
1592 Use of RTD is a selectable option, since it is incompatible with
1593 standard Unix calling sequences. If the option is not selected,
1594 the caller must always pop the args.
1596 The attribute stdcall is equivalent to RTD on a per module basis. */
1598 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1599 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1601 #define FUNCTION_VALUE_REGNO_P(N) \
1602 ix86_function_value_regno_p (N)
1604 /* Define how to find the value returned by a library function
1605 assuming the value has mode MODE. */
1607 #define LIBCALL_VALUE(MODE) \
1608 ix86_libcall_value (MODE)
1610 /* Define the size of the result block used for communication between
1611 untyped_call and untyped_return. The block contains a DImode value
1612 followed by the block used by fnsave and frstor. */
1614 #define APPLY_RESULT_SIZE (8+108)
1616 /* 1 if N is a possible register number for function argument passing. */
1617 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1619 /* Define a data type for recording info about an argument list
1620 during the scan of that argument list. This data type should
1621 hold all necessary information about the function itself
1622 and about the args processed so far, enough to enable macros
1623 such as FUNCTION_ARG to determine where the next arg should go. */
1625 typedef struct ix86_args {
1626 int words; /* # words passed so far */
1627 int nregs; /* # registers available for passing */
1628 int regno; /* next available register number */
1629 int fastcall; /* fastcall calling convention is used */
1630 int sse_words; /* # sse words passed so far */
1631 int sse_nregs; /* # sse registers available for passing */
1632 int warn_sse; /* True when we want to warn about SSE ABI. */
1633 int warn_mmx; /* True when we want to warn about MMX ABI. */
1634 int sse_regno; /* next available sse register number */
1635 int mmx_words; /* # mmx words passed so far */
1636 int mmx_nregs; /* # mmx registers available for passing */
1637 int mmx_regno; /* next available mmx register number */
1638 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1639 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1640 be passed in SSE registers. Otherwise 0. */
1643 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1644 for a call to a function whose data type is FNTYPE.
1645 For a library call, FNTYPE is 0. */
1647 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1648 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1650 /* Update the data in CUM to advance over an argument
1651 of mode MODE and data type TYPE.
1652 (TYPE is null for libcalls where that information may not be available.) */
1654 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1655 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1657 /* Define where to put the arguments to a function.
1658 Value is zero to push the argument on the stack,
1659 or a hard register in which to store the argument.
1661 MODE is the argument's machine mode.
1662 TYPE is the data type of the argument (as a tree).
1663 This is null for libcalls where that information may
1665 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1666 the preceding args and about the function being called.
1667 NAMED is nonzero if this argument is a named parameter
1668 (otherwise it is an extra parameter matching an ellipsis). */
1670 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1671 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1673 /* Implement `va_start' for varargs and stdarg. */
1674 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1675 ix86_va_start (VALIST, NEXTARG)
1677 #define TARGET_ASM_FILE_END ix86_file_end
1678 #define NEED_INDICATE_EXEC_STACK 0
1680 /* Output assembler code to FILE to increment profiler label # LABELNO
1681 for profiling a function entry. */
1683 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1685 #define MCOUNT_NAME "_mcount"
1687 #define PROFILE_COUNT_REGISTER "edx"
1689 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1690 the stack pointer does not matter. The value is tested only in
1691 functions that have frame pointers.
1692 No definition is equivalent to always zero. */
1693 /* Note on the 386 it might be more efficient not to define this since
1694 we have to restore it ourselves from the frame pointer, in order to
1697 #define EXIT_IGNORE_STACK 1
1699 /* Output assembler code for a block containing the constant parts
1700 of a trampoline, leaving space for the variable parts. */
1702 /* On the 386, the trampoline contains two instructions:
1705 The trampoline is generated entirely at runtime. The operand of JMP
1706 is the address of FUNCTION relative to the instruction following the
1707 JMP (which is 5 bytes long). */
1709 /* Length in units of the trampoline for entering a nested function. */
1711 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1713 /* Emit RTL insns to initialize the variable parts of a trampoline.
1714 FNADDR is an RTX for the address of the function's pure code.
1715 CXT is an RTX for the static chain value for the function. */
1717 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1718 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1720 /* Definitions for register eliminations.
1722 This is an array of structures. Each structure initializes one pair
1723 of eliminable registers. The "from" register number is given first,
1724 followed by "to". Eliminations of the same "from" register are listed
1725 in order of preference.
1727 There are two registers that can always be eliminated on the i386.
1728 The frame pointer and the arg pointer can be replaced by either the
1729 hard frame pointer or to the stack pointer, depending upon the
1730 circumstances. The hard frame pointer is not used before reload and
1731 so it is not eligible for elimination. */
1733 #define ELIMINABLE_REGS \
1734 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1735 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1736 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1737 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1739 /* Given FROM and TO register numbers, say whether this elimination is
1740 allowed. Frame pointer elimination is automatically handled.
1742 All other eliminations are valid. */
1744 #define CAN_ELIMINATE(FROM, TO) \
1745 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1747 /* Define the offset between two registers, one to be eliminated, and the other
1748 its replacement, at the start of a routine. */
1750 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1751 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1753 /* Addressing modes, and classification of registers for them. */
1755 /* Macros to check register numbers against specific register classes. */
1757 /* These assume that REGNO is a hard or pseudo reg number.
1758 They give nonzero only if REGNO is a hard reg of the suitable class
1759 or a pseudo reg currently allocated to a suitable hard reg.
1760 Since they use reg_renumber, they are safe only once reg_renumber
1761 has been allocated, which happens in local-alloc.c. */
1763 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1764 ((REGNO) < STACK_POINTER_REGNUM \
1765 || REX_INT_REGNO_P (REGNO) \
1766 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1767 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1769 #define REGNO_OK_FOR_BASE_P(REGNO) \
1770 (GENERAL_REGNO_P (REGNO) \
1771 || (REGNO) == ARG_POINTER_REGNUM \
1772 || (REGNO) == FRAME_POINTER_REGNUM \
1773 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1775 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1776 and check its validity for a certain class.
1777 We have two alternate definitions for each of them.
1778 The usual definition accepts all pseudo regs; the other rejects
1779 them unless they have been allocated suitable hard regs.
1780 The symbol REG_OK_STRICT causes the latter definition to be used.
1782 Most source files want to accept pseudo regs in the hope that
1783 they will get allocated to the class that the insn wants them to be in.
1784 Source files for reload pass need to be strict.
1785 After reload, it makes no difference, since pseudo regs have
1786 been eliminated by then. */
1789 /* Non strict versions, pseudos are ok. */
1790 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1791 (REGNO (X) < STACK_POINTER_REGNUM \
1792 || REX_INT_REGNO_P (REGNO (X)) \
1793 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1795 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1796 (GENERAL_REGNO_P (REGNO (X)) \
1797 || REGNO (X) == ARG_POINTER_REGNUM \
1798 || REGNO (X) == FRAME_POINTER_REGNUM \
1799 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1801 /* Strict versions, hard registers only */
1802 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1803 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1805 #ifndef REG_OK_STRICT
1806 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1807 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1810 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1811 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1814 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1815 that is a valid memory address for an instruction.
1816 The MODE argument is the machine mode for the MEM expression
1817 that wants to use this address.
1819 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1820 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1822 See legitimize_pic_address in i386.c for details as to what
1823 constitutes a legitimate address when -fpic is used. */
1825 #define MAX_REGS_PER_ADDRESS 2
1827 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1829 /* Nonzero if the constant value X is a legitimate general operand.
1830 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1832 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1834 #ifdef REG_OK_STRICT
1835 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1837 if (legitimate_address_p ((MODE), (X), 1)) \
1842 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1844 if (legitimate_address_p ((MODE), (X), 0)) \
1850 /* If defined, a C expression to determine the base term of address X.
1851 This macro is used in only one place: `find_base_term' in alias.c.
1853 It is always safe for this macro to not be defined. It exists so
1854 that alias analysis can understand machine-dependent addresses.
1856 The typical use of this macro is to handle addresses containing
1857 a label_ref or symbol_ref within an UNSPEC. */
1859 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1861 /* Try machine-dependent ways of modifying an illegitimate address
1862 to be legitimate. If we find one, return the new, valid address.
1863 This macro is used in only one place: `memory_address' in explow.c.
1865 OLDX is the address as it was before break_out_memory_refs was called.
1866 In some cases it is useful to look at this to decide what needs to be done.
1868 MODE and WIN are passed so that this macro can use
1869 GO_IF_LEGITIMATE_ADDRESS.
1871 It is always safe for this macro to do nothing. It exists to recognize
1872 opportunities to optimize the output.
1874 For the 80386, we handle X+REG by loading X into a register R and
1875 using R+REG. R will go in a general reg and indexing will be used.
1876 However, if REG is a broken-out memory address or multiplication,
1877 nothing needs to be done because REG can certainly go in a general reg.
1879 When -fpic is used, special handling is needed for symbolic references.
1880 See comments by legitimize_pic_address in i386.c for details. */
1882 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1884 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1885 if (memory_address_p ((MODE), (X))) \
1889 /* Nonzero if the constant value X is a legitimate general operand
1890 when generating PIC code. It is given that flag_pic is on and
1891 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1893 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1895 #define SYMBOLIC_CONST(X) \
1896 (GET_CODE (X) == SYMBOL_REF \
1897 || GET_CODE (X) == LABEL_REF \
1898 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1900 /* Go to LABEL if ADDR (a legitimate address expression)
1901 has an effect that depends on the machine mode it is used for.
1902 On the 80386, only postdecrement and postincrement address depend thus
1903 (the amount of decrement or increment being the length of the operand).
1904 These are now caught in recog.c. */
1905 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1907 /* Max number of args passed in registers. If this is more than 3, we will
1908 have problems with ebx (register #4), since it is a caller save register and
1909 is also used as the pic register in ELF. So for now, don't allow more than
1910 3 registers to be passed in registers. */
1912 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1914 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1916 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1919 /* Specify the machine mode that this machine uses
1920 for the index in the tablejump instruction. */
1921 #define CASE_VECTOR_MODE \
1922 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1924 /* Define this as 1 if `char' should by default be signed; else as 0. */
1925 #define DEFAULT_SIGNED_CHAR 1
1927 /* Max number of bytes we can move from memory to memory
1928 in one reasonably fast instruction. */
1931 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1932 move efficiently, as opposed to MOVE_MAX which is the maximum
1933 number of bytes we can move with a single instruction. */
1934 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1936 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1937 move-instruction pairs, we will do a movmem or libcall instead.
1938 Increasing the value will always make code faster, but eventually
1939 incurs high cost in increased code size.
1941 If you don't define this, a reasonable default is used. */
1943 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1945 /* If a clear memory operation would take CLEAR_RATIO or more simple
1946 move-instruction sequences, we will do a clrmem or libcall instead. */
1948 #define CLEAR_RATIO (optimize_size ? 2 \
1949 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1951 /* Define if shifts truncate the shift count
1952 which implies one can omit a sign-extension or zero-extension
1953 of a shift count. */
1954 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1956 /* #define SHIFT_COUNT_TRUNCATED */
1958 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1959 is done just by pretending it is already truncated. */
1960 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1962 /* A macro to update M and UNSIGNEDP when an object whose type is
1963 TYPE and which has the specified mode and signedness is to be
1964 stored in a register. This macro is only called when TYPE is a
1967 On i386 it is sometimes useful to promote HImode and QImode
1968 quantities to SImode. The choice depends on target type. */
1970 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1972 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1973 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1977 /* Specify the machine mode that pointers have.
1978 After generation of rtl, the compiler makes no further distinction
1979 between pointers and any other objects of this machine mode. */
1980 #define Pmode (TARGET_64BIT ? DImode : SImode)
1982 /* A function address in a call instruction
1983 is a byte address (for indexing purposes)
1984 so give the MEM rtx a byte's mode. */
1985 #define FUNCTION_MODE QImode
1987 /* A C expression for the cost of moving data from a register in class FROM to
1988 one in class TO. The classes are expressed using the enumeration values
1989 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1990 interpreted relative to that.
1992 It is not required that the cost always equal 2 when FROM is the same as TO;
1993 on some machines it is expensive to move between registers if they are not
1994 general registers. */
1996 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1997 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1999 /* A C expression for the cost of moving data of mode M between a
2000 register and memory. A value of 2 is the default; this cost is
2001 relative to those in `REGISTER_MOVE_COST'.
2003 If moving between registers and memory is more expensive than
2004 between two registers, you should define this macro to express the
2007 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2008 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2010 /* A C expression for the cost of a branch instruction. A value of 1
2011 is the default; other values are interpreted relative to that. */
2013 #define BRANCH_COST ix86_branch_cost
2015 /* Define this macro as a C expression which is nonzero if accessing
2016 less than a word of memory (i.e. a `char' or a `short') is no
2017 faster than accessing a word of memory, i.e., if such access
2018 require more than one instruction or if there is no difference in
2019 cost between byte and (aligned) word loads.
2021 When this macro is not defined, the compiler will access a field by
2022 finding the smallest containing object; when it is defined, a
2023 fullword load will be used if alignment permits. Unless bytes
2024 accesses are faster than word accesses, using word accesses is
2025 preferable since it may eliminate subsequent memory access if
2026 subsequent accesses occur to other fields in the same word of the
2027 structure, but to different bytes. */
2029 #define SLOW_BYTE_ACCESS 0
2031 /* Nonzero if access to memory by shorts is slow and undesirable. */
2032 #define SLOW_SHORT_ACCESS 0
2034 /* Define this macro to be the value 1 if unaligned accesses have a
2035 cost many times greater than aligned accesses, for example if they
2036 are emulated in a trap handler.
2038 When this macro is nonzero, the compiler will act as if
2039 `STRICT_ALIGNMENT' were nonzero when generating code for block
2040 moves. This can cause significantly more instructions to be
2041 produced. Therefore, do not set this macro nonzero if unaligned
2042 accesses only add a cycle or two to the time for a memory access.
2044 If the value of this macro is always zero, it need not be defined. */
2046 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2048 /* Define this macro if it is as good or better to call a constant
2049 function address than to call an address kept in a register.
2051 Desirable on the 386 because a CALL with a constant address is
2052 faster than one with a register address. */
2054 #define NO_FUNCTION_CSE
2056 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2057 return the mode to be used for the comparison.
2059 For floating-point equality comparisons, CCFPEQmode should be used.
2060 VOIDmode should be used in all other cases.
2062 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2063 possible, to allow for more combinations. */
2065 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2067 /* Return nonzero if MODE implies a floating point inequality can be
2070 #define REVERSIBLE_CC_MODE(MODE) 1
2072 /* A C expression whose value is reversed condition code of the CODE for
2073 comparison done in CC_MODE mode. */
2074 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2077 /* Control the assembler format that we output, to the extent
2078 this does not vary between assemblers. */
2080 /* How to refer to registers in assembler output.
2081 This sequence is indexed by compiler's hard-register-number (see above). */
2083 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2084 For non floating point regs, the following are the HImode names.
2086 For float regs, the stack top is sometimes referred to as "%st(0)"
2087 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2089 #define HI_REGISTER_NAMES \
2090 {"ax","dx","cx","bx","si","di","bp","sp", \
2091 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2092 "argp", "flags", "fpsr", "fpcr", "frame", \
2093 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2094 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2095 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2096 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2098 #define REGISTER_NAMES HI_REGISTER_NAMES
2100 /* Table of additional register names to use in user input. */
2102 #define ADDITIONAL_REGISTER_NAMES \
2103 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2104 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2105 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2106 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2107 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2108 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2110 /* Note we are omitting these since currently I don't know how
2111 to get gcc to use these, since they want the same but different
2112 number as al, and ax.
2115 #define QI_REGISTER_NAMES \
2116 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2118 /* These parallel the array above, and can be used to access bits 8:15
2119 of regs 0 through 3. */
2121 #define QI_HIGH_REGISTER_NAMES \
2122 {"ah", "dh", "ch", "bh", }
2124 /* How to renumber registers for dbx and gdb. */
2126 #define DBX_REGISTER_NUMBER(N) \
2127 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2129 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2130 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2131 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2133 /* Before the prologue, RA is at 0(%esp). */
2134 #define INCOMING_RETURN_ADDR_RTX \
2135 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2137 /* After the prologue, RA is at -4(AP) in the current frame. */
2138 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2140 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2141 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2143 /* PC is dbx register 8; let's use that column for RA. */
2144 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2146 /* Before the prologue, the top of the frame is at 4(%esp). */
2147 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2149 /* Describe how we implement __builtin_eh_return. */
2150 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2151 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2154 /* Select a format to encode pointers in exception handling data. CODE
2155 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2156 true if the symbol may be affected by dynamic relocations.
2158 ??? All x86 object file formats are capable of representing this.
2159 After all, the relocation needed is the same as for the call insn.
2160 Whether or not a particular assembler allows us to enter such, I
2161 guess we'll have to see. */
2162 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2163 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2165 /* This is how to output an insn to push a register on the stack.
2166 It need not be very fast code. */
2168 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2171 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2172 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2174 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2177 /* This is how to output an insn to pop a register from the stack.
2178 It need not be very fast code. */
2180 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2183 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2184 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2186 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2189 /* This is how to output an element of a case-vector that is absolute. */
2191 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2192 ix86_output_addr_vec_elt ((FILE), (VALUE))
2194 /* This is how to output an element of a case-vector that is relative. */
2196 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2197 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2199 /* Under some conditions we need jump tables in the text section,
2200 because the assembler cannot handle label differences between
2201 sections. This is the case for x86_64 on Mach-O for example. */
2203 #define JUMP_TABLES_IN_TEXT_SECTION \
2204 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2205 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2207 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2208 and switch back. For x86 we do this only to save a few bytes that
2209 would otherwise be unused in the text section. */
2210 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2211 asm (SECTION_OP "\n\t" \
2212 "call " USER_LABEL_PREFIX #FUNC "\n" \
2213 TEXT_SECTION_ASM_OP);
2215 /* Print operand X (an rtx) in assembler syntax to file FILE.
2216 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2217 Effect of various CODE letters is described in i386.c near
2218 print_operand function. */
2220 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2221 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2223 #define PRINT_OPERAND(FILE, X, CODE) \
2224 print_operand ((FILE), (X), (CODE))
2226 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2227 print_operand_address ((FILE), (ADDR))
2229 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2231 if (! output_addr_const_extra (FILE, (X))) \
2235 /* Which processor to schedule for. The cpu attribute defines a list that
2236 mirrors this list, so changes to i386.md must be made at the same time. */
2240 PROCESSOR_I386, /* 80386 */
2241 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2243 PROCESSOR_PENTIUMPRO,
2251 PROCESSOR_GENERIC32,
2252 PROCESSOR_GENERIC64,
2257 extern enum processor_type ix86_tune;
2258 extern enum processor_type ix86_arch;
2266 extern enum fpmath_unit ix86_fpmath;
2275 extern enum tls_dialect ix86_tls_dialect;
2278 CM_32, /* The traditional 32-bit ABI. */
2279 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2280 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2281 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2282 CM_LARGE, /* No assumptions. */
2283 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2284 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2285 CM_LARGE_PIC /* No assumptions. */
2288 extern enum cmodel ix86_cmodel;
2290 /* Size of the RED_ZONE area. */
2291 #define RED_ZONE_SIZE 128
2292 /* Reserved area of the red zone for temporaries. */
2293 #define RED_ZONE_RESERVE 8
2300 extern enum asm_dialect ix86_asm_dialect;
2301 extern unsigned int ix86_preferred_stack_boundary;
2302 extern int ix86_branch_cost, ix86_section_threshold;
2304 /* Smallest class containing REGNO. */
2305 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2307 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2308 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2309 extern rtx ix86_compare_emitted;
2311 /* To properly truncate FP values into integers, we need to set i387 control
2312 word. We can't emit proper mode switching code before reload, as spills
2313 generated by reload may truncate values incorrectly, but we still can avoid
2314 redundant computation of new control word by the mode switching pass.
2315 The fldcw instructions are still emitted redundantly, but this is probably
2316 not going to be noticeable problem, as most CPUs do have fast path for
2319 The machinery is to emit simple truncation instructions and split them
2320 before reload to instructions having USEs of two memory locations that
2321 are filled by this code to old and new control word.
2323 Post-reload pass may be later used to eliminate the redundant fildcw if
2335 enum ix86_stack_slot
2344 MAX_386_STACK_LOCALS
2347 /* Define this macro if the port needs extra instructions inserted
2348 for mode switching in an optimizing compilation. */
2350 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2351 ix86_optimize_mode_switching[(ENTITY)]
2353 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2354 initializer for an array of integers. Each initializer element N
2355 refers to an entity that needs mode switching, and specifies the
2356 number of different modes that might need to be set for this
2357 entity. The position of the initializer in the initializer -
2358 starting counting at zero - determines the integer that is used to
2359 refer to the mode-switched entity in question. */
2361 #define NUM_MODES_FOR_MODE_SWITCHING \
2362 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2364 /* ENTITY is an integer specifying a mode-switched entity. If
2365 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2366 return an integer value not larger than the corresponding element
2367 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2368 must be switched into prior to the execution of INSN. */
2370 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2372 /* This macro specifies the order in which modes for ENTITY are
2373 processed. 0 is the highest priority. */
2375 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2377 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2378 is the set of hard registers live at the point where the insn(s)
2379 are to be inserted. */
2381 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2382 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2383 ? emit_i387_cw_initialization (MODE), 0 \
2387 /* Avoid renaming of stack registers, as doing so in combination with
2388 scheduling just increases amount of live registers at time and in
2389 the turn amount of fxch instructions needed.
2391 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2393 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2394 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2397 #define FASTCALL_PREFIX '@'
2399 struct machine_function GTY(())
2401 struct stack_local_entry *stack_locals;
2402 const char *some_ld_name;
2403 rtx force_align_arg_pointer;
2404 int save_varrargs_registers;
2405 int accesses_prev_frame;
2406 int optimize_mode_switching[MAX_386_ENTITIES];
2407 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2408 determine the style used. */
2409 int use_fast_prologue_epilogue;
2410 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2412 int use_fast_prologue_epilogue_nregs;
2413 /* If true, the current function needs the default PIC register, not
2414 an alternate register (on x86) and must not use the red zone (on
2415 x86_64), even if it's a leaf function. We don't want the
2416 function to be regarded as non-leaf because TLS calls need not
2417 affect register allocation. This flag is set when a TLS call
2418 instruction is expanded within a function, and never reset, even
2419 if all such instructions are optimized away. Use the
2420 ix86_current_function_calls_tls_descriptor macro for a better
2422 int tls_descriptor_call_expanded_p;
2425 #define ix86_stack_locals (cfun->machine->stack_locals)
2426 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2427 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2428 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2429 (cfun->machine->tls_descriptor_call_expanded_p)
2430 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2431 calls are optimized away, we try to detect cases in which it was
2432 optimized away. Since such instructions (use (reg REG_SP)), we can
2433 verify whether there's any such instruction live by testing that
2435 #define ix86_current_function_calls_tls_descriptor \
2436 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2438 /* Control behavior of x86_file_start. */
2439 #define X86_FILE_START_VERSION_DIRECTIVE false
2440 #define X86_FILE_START_FLTUSED false
2442 /* Flag to mark data that is in the large address area. */
2443 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2444 #define SYMBOL_REF_FAR_ADDR_P(X) \
2445 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2447 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2448 have defined always, to avoid ifdefing. */
2449 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2450 #define SYMBOL_REF_DLLIMPORT_P(X) \
2451 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2453 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2454 #define SYMBOL_REF_DLLEXPORT_P(X) \
2455 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
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