1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs {
54 int add; /* cost of an add instruction */
55 int lea; /* cost of a lea instruction */
56 int shift_var; /* variable shift costs */
57 int shift_const; /* constant shift costs */
58 int mult_init; /* cost of starting a multiply */
59 int mult_bit; /* cost of multiply per each bit set */
60 int divide; /* cost of a divide/mod */
61 int large_insn; /* insns larger than this cost more */
62 int move_ratio; /* The threshold of number of scalar
63 memory-to-memory move insns. */
64 int movzbl_load; /* cost of loading using movzbl */
65 int int_load[3]; /* cost of loading integer registers
66 in QImode, HImode and SImode relative
67 to reg-reg move (2). */
68 int int_store[3]; /* cost of storing integer register
69 in QImode, HImode and SImode */
70 int fp_move; /* cost of reg,reg fld/fst */
71 int fp_load[3]; /* cost of loading FP register
72 in SFmode, DFmode and XFmode */
73 int fp_store[3]; /* cost of storing FP register
74 in SFmode, DFmode and XFmode */
75 int mmx_move; /* cost of moving MMX register. */
76 int mmx_load[2]; /* cost of loading MMX register
77 in SImode and DImode */
78 int mmx_store[2]; /* cost of storing MMX register
79 in SImode and DImode */
80 int sse_move; /* cost of moving SSE register. */
81 int sse_load[3]; /* cost of loading SSE register
82 in SImode, DImode and TImode*/
83 int sse_store[3]; /* cost of storing SSE register
84 in SImode, DImode and TImode*/
85 int mmxsse_to_integer; /* cost of moving mmxsse register to
86 integer and vice versa. */
89 extern struct processor_costs *ix86_cost;
91 /* Run-time compilation parameters selecting different hardware subsets. */
93 extern int target_flags;
95 /* Macros used in the machine description to test the flags. */
97 /* configure can arrange to make this 2, to force a 486. */
99 #ifndef TARGET_CPU_DEFAULT
100 #define TARGET_CPU_DEFAULT 0
103 /* Masks for the -m switches */
104 #define MASK_80387 0x00000001 /* Hardware floating point */
105 #define MASK_RTD 0x00000002 /* Use ret that pops args */
106 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
107 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
108 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
109 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
110 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
111 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
112 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
113 #define MASK_NO_ALIGN_STROPS 0x00001000 /* Enable aligning of string ops. */
114 #define MASK_INLINE_ALL_STROPS 0x00002000 /* Inline stringops in all cases */
115 #define MASK_NO_PUSH_ARGS 0x00004000 /* Use push instructions */
116 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00008000/* Accumulate outgoing args */
117 #define MASK_MMX 0x00010000 /* Support MMX regs/builtins */
118 #define MASK_SSE 0x00020000 /* Support SSE regs/builtins */
119 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
120 #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
121 #define MASK_MIX_SSE_I387 0x00100000 /* Mix SSE and i387 instructions */
122 #define MASK_64BIT 0x00200000 /* Produce 64bit code */
123 #define MASK_NO_RED_ZONE 0x00400000 /* Do not use red zone */
125 /* Temporary codegen switches */
126 #define MASK_INTEL_SYNTAX 0x00000200
127 #define MASK_DEBUG_ARG 0x00000400 /* function_arg */
128 #define MASK_DEBUG_ADDR 0x00000800 /* GO_IF_LEGITIMATE_ADDRESS */
130 /* Use the floating point instructions */
131 #define TARGET_80387 (target_flags & MASK_80387)
133 /* Compile using ret insn that pops args.
134 This will not work unless you use prototypes at least
135 for all functions that can take varying numbers of args. */
136 #define TARGET_RTD (target_flags & MASK_RTD)
138 /* Align doubles to a two word boundary. This breaks compatibility with
139 the published ABI's for structures containing doubles, but produces
140 faster code on the pentium. */
141 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
143 /* Use push instructions to save outgoing args. */
144 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
146 /* Accumulate stack adjustments to prologue/epilogue. */
147 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
148 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
150 /* Put uninitialized locals into bss, not data.
151 Meaningful only on svr3. */
152 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
154 /* Use IEEE floating point comparisons. These handle correctly the cases
155 where the result of a comparison is unordered. Normally SIGFPE is
156 generated in such cases, in which case this isn't needed. */
157 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
159 /* Functions that return a floating point value may return that value
160 in the 387 FPU or in 386 integer registers. If set, this flag causes
161 the 387 to be used, which is compatible with most calling conventions. */
162 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
164 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
165 This mode wastes cache, but avoid missaligned data accesses and simplifies
166 address calculations. */
167 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
169 /* Disable generation of FP sin, cos and sqrt operations for 387.
170 This is because FreeBSD lacks these in the math-emulator-code */
171 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
173 /* Don't create frame pointers for leaf functions */
174 #define TARGET_OMIT_LEAF_FRAME_POINTER \
175 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
177 /* Debug GO_IF_LEGITIMATE_ADDRESS */
178 #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
180 /* Debug FUNCTION_ARG macros */
181 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
183 /* 64bit Sledgehammer mode */
184 #ifdef TARGET_BI_ARCH
185 #define TARGET_64BIT (target_flags & MASK_64BIT)
187 #ifdef TARGET_64BIT_DEFAULT
188 #define TARGET_64BIT 1
190 #define TARGET_64BIT 0
194 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
195 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
196 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
197 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
198 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
199 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
200 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
202 #define CPUMASK (1 << ix86_cpu)
203 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
204 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
205 extern const int x86_branch_hints, x86_unroll_strlen;
206 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
207 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
208 extern const int x86_use_cltd, x86_read_modify_write;
209 extern const int x86_read_modify, x86_split_long_moves;
210 extern const int x86_promote_QImode, x86_single_stringop;
211 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
212 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
213 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
214 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
216 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
217 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
218 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
219 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
220 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
221 /* For sane SSE instruction set generation we need fcomi instruction. It is
222 safe to enable all CMOVE instructions. */
223 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
224 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
225 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
226 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
227 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
228 #define TARGET_MOVX (x86_movx & CPUMASK)
229 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
230 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
231 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
232 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
233 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
234 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
235 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
236 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
237 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
238 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
239 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
240 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
241 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
242 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
243 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
244 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
245 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
246 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
247 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
248 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
249 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
251 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
253 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
254 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
256 #define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
258 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
259 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
260 #define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
261 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
263 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
265 #define TARGET_SWITCHES \
266 { { "80387", MASK_80387, N_("Use hardware fp") }, \
267 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
268 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
269 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
270 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
271 { "386", 0, N_("Same as -mcpu=i386") }, \
272 { "486", 0, N_("Same as -mcpu=i486") }, \
273 { "pentium", 0, N_("Same as -mcpu=pentium") }, \
274 { "pentiumpro", 0, N_("Same as -mcpu=pentiumpro") }, \
276 N_("Alternate calling convention") }, \
277 { "no-rtd", -MASK_RTD, \
278 N_("Use normal calling convention") }, \
279 { "align-double", MASK_ALIGN_DOUBLE, \
280 N_("Align some doubles on dword boundary") }, \
281 { "no-align-double", -MASK_ALIGN_DOUBLE, \
282 N_("Align doubles on word boundary") }, \
283 { "svr3-shlib", MASK_SVR3_SHLIB, \
284 N_("Uninitialized locals in .bss") }, \
285 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
286 N_("Uninitialized locals in .data") }, \
287 { "ieee-fp", MASK_IEEE_FP, \
288 N_("Use IEEE math for fp comparisons") }, \
289 { "no-ieee-fp", -MASK_IEEE_FP, \
290 N_("Do not use IEEE math for fp comparisons") }, \
291 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
292 N_("Return values of functions in FPU registers") }, \
293 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
294 N_("Do not return values of functions in FPU registers")}, \
295 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
296 N_("Do not generate sin, cos, sqrt for FPU") }, \
297 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
298 N_("Generate sin, cos, sqrt for FPU")}, \
299 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
300 N_("Omit the frame pointer in leaf functions") }, \
301 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
302 { "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
303 { "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
304 { "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \
305 { "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \
306 { "stack-arg-probe", MASK_STACK_PROBE, \
307 N_("Enable stack probing") }, \
308 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
309 { "windows", 0, 0 /* undocumented */ }, \
310 { "dll", 0, 0 /* undocumented */ }, \
311 { "intel-syntax", MASK_INTEL_SYNTAX, \
312 N_("Emit Intel syntax assembler opcodes") }, \
313 { "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
314 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
315 N_("Align destination of the string operations") }, \
316 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
317 N_("Do not align destination of the string operations") }, \
318 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
319 N_("Inline all known string operations") }, \
320 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
321 N_("Do not inline all known string operations") }, \
322 { "push-args", -MASK_NO_PUSH_ARGS, \
323 N_("Use push instructions to save outgoing arguments") }, \
324 { "no-push-args", MASK_NO_PUSH_ARGS, \
325 N_("Do not use push instructions to save outgoing arguments") }, \
326 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
327 N_("Use push instructions to save outgoing arguments") }, \
328 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
329 N_("Do not use push instructions to save outgoing arguments") }, \
330 { "mmx", MASK_MMX, N_("Support MMX builtins") }, \
331 { "no-mmx", -MASK_MMX, \
332 N_("Do not support MMX builtins") }, \
334 N_("Support MMX and SSE builtins and code generation") }, \
335 { "no-sse", -MASK_SSE, \
336 N_("Do not support MMX and SSE builtins and code generation") }, \
337 { "sse2", MASK_SSE2, \
338 N_("Support MMX, SSE and SSE2 builtins and code generation") }, \
339 { "no-sse2", -MASK_SSE2, \
340 N_("Do not support MMX, SSE and SSE2 builtins and code generation") }, \
341 { "mix-sse-i387", MASK_MIX_SSE_I387, \
342 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
343 { "nomix-sse-i387", -MASK_MIX_SSE_I387, \
344 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
345 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
346 N_("sizeof(long double) is 16.") }, \
347 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
348 N_("sizeof(long double) is 12.") }, \
349 { "64", MASK_64BIT, \
350 N_("Generate 64bit x86-64 code") }, \
351 { "32", -MASK_64BIT, \
352 N_("Generate 32bit i386 code") }, \
353 { "red-zone", -MASK_NO_RED_ZONE, \
354 N_("Use red-zone in the x86-64 code") }, \
355 { "no-red-zone", MASK_NO_RED_ZONE, \
356 N_("do not use red-zone in the x86-64 code") }, \
358 { "", TARGET_DEFAULT, 0 }}
360 #ifdef TARGET_64BIT_DEFAULT
361 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
363 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
366 /* Which processor to schedule for. The cpu attribute defines a list that
367 mirrors this list, so changes to i386.md must be made at the same time. */
371 PROCESSOR_I386, /* 80386 */
372 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
374 PROCESSOR_PENTIUMPRO,
381 extern enum processor_type ix86_cpu;
383 extern int ix86_arch;
385 /* This macro is similar to `TARGET_SWITCHES' but defines names of
386 command options that have values. Its definition is an
387 initializer with a subgrouping for each command option.
389 Each subgrouping contains a string constant, that defines the
390 fixed part of the option name, and the address of a variable. The
391 variable, type `char *', is set to the variable part of the given
392 option if the fixed part matches. The actual option name is made
393 by appending `-m' to the specified name. */
394 #define TARGET_OPTIONS \
395 { { "cpu=", &ix86_cpu_string, \
396 N_("Schedule code for given CPU")}, \
397 { "arch=", &ix86_arch_string, \
398 N_("Generate code for given CPU")}, \
399 { "regparm=", &ix86_regparm_string, \
400 N_("Number of registers used to pass integer arguments") }, \
401 { "align-loops=", &ix86_align_loops_string, \
402 N_("Loop code aligned to this power of 2") }, \
403 { "align-jumps=", &ix86_align_jumps_string, \
404 N_("Jump targets are aligned to this power of 2") }, \
405 { "align-functions=", &ix86_align_funcs_string, \
406 N_("Function starts are aligned to this power of 2") }, \
407 { "preferred-stack-boundary=", \
408 &ix86_preferred_stack_boundary_string, \
409 N_("Attempt to keep stack aligned to this power of 2") }, \
410 { "branch-cost=", &ix86_branch_cost_string, \
411 N_("Branches are this expensive (1-5, arbitrary units)") }, \
412 { "cmodel=", &ix86_cmodel_string, \
413 N_("Use given x86-64 code model") }, \
417 /* Sometimes certain combinations of command options do not make
418 sense on a particular target machine. You can define a macro
419 `OVERRIDE_OPTIONS' to take account of this. This macro, if
420 defined, is executed once just after all the command options have
423 Don't use this macro to turn on various extra optimizations for
424 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
426 #define OVERRIDE_OPTIONS override_options ()
428 /* These are meant to be redefined in the host dependent files */
429 #define SUBTARGET_SWITCHES
430 #define SUBTARGET_OPTIONS
432 /* Define this to change the optimizations performed by default. */
433 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
435 /* Specs for the compiler proper */
438 #define CC1_CPU_SPEC "\
441 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
443 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
444 %{mpentium:-mcpu=pentium \
445 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
446 %{mpentiumpro:-mcpu=pentiumpro \
447 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}}"
450 #ifndef CPP_CPU_DEFAULT_SPEC
451 #if TARGET_CPU_DEFAULT == 1
452 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
454 #if TARGET_CPU_DEFAULT == 2
455 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
457 #if TARGET_CPU_DEFAULT == 3
458 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
460 #if TARGET_CPU_DEFAULT == 4
461 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
463 #if TARGET_CPU_DEFAULT == 5
464 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
466 #if TARGET_CPU_DEFAULT == 6
467 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
469 #ifndef CPP_CPU_DEFAULT_SPEC
470 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
472 #endif /* CPP_CPU_DEFAULT_SPEC */
474 #ifdef NO_BUILTIN_SIZE_TYPE
475 #define CPP_CPU32_SIZE_TYPE_SPEC \
476 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
477 #define CPP_CPU64_SIZE_TYPE_SPEC \
478 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
480 #define CPP_CPU32_SIZE_TYPE_SPEC ""
481 #define CPP_CPU64_SIZE_TYPE_SPEC ""
484 #define CPP_CPU32_SPEC \
485 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
486 -D__i386__ %(cpp_cpu32sizet)"
488 #define CPP_CPU64_SPEC \
489 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
491 #define CPP_CPUCOMMON_SPEC "\
492 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
493 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
494 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
495 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
496 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
497 -D__pentiumpro -D__pentiumpro__ \
498 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
499 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
500 %{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
501 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
502 %{m386|mcpu=i386:-D__tune_i386__ }\
503 %{m486|mcpu=i486:-D__tune_i486__ }\
504 %{mpentium|mcpu=pentium|mcpu=i586:-D__tune_i586__ -D__tune_pentium__ }\
505 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_i686__ -D__tune_pentiumpro__ }\
506 %{mcpu=k6:-D__tune_k6__ }\
507 %{mcpu=athlon:-D__tune_athlon__ }\
508 %{mcpu=pentium4:-D__tune_pentium4__ }\
509 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
512 #ifdef TARGET_BI_ARCH
513 #ifdef TARGET_64BIT_DEFAULT
514 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
516 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
519 #ifdef TARGET_64BIT_DEFAULT
520 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
522 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
528 #define CC1_SPEC "%(cc1_cpu) "
531 /* This macro defines names of additional specifications to put in the
532 specs that can be used in various specifications like CC1_SPEC. Its
533 definition is an initializer with a subgrouping for each command option.
535 Each subgrouping contains a string constant, that defines the
536 specification name, and a string constant that used by the GNU CC driver
539 Do not define this macro if it does not need to do anything. */
541 #ifndef SUBTARGET_EXTRA_SPECS
542 #define SUBTARGET_EXTRA_SPECS
545 #define EXTRA_SPECS \
546 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
547 { "cpp_cpu", CPP_CPU_SPEC }, \
548 { "cpp_cpu32", CPP_CPU32_SPEC }, \
549 { "cpp_cpu64", CPP_CPU64_SPEC }, \
550 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
551 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
552 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
553 { "cc1_cpu", CC1_CPU_SPEC }, \
554 SUBTARGET_EXTRA_SPECS
556 /* target machine storage layout */
558 /* Define for XFmode or TFmode extended real floating point support.
559 This will automatically cause REAL_ARITHMETIC to be defined.
561 The XFmode is specified by i386 ABI, while TFmode may be faster
562 due to alignment and simplifications in the address calculations.
564 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
565 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
567 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
569 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
571 /* Tell real.c that this is the 80-bit Intel extended float format
572 packaged in a 128-bit or 96bit entity. */
573 #define INTEL_EXTENDED_IEEE_FORMAT
576 #define SHORT_TYPE_SIZE 16
577 #define INT_TYPE_SIZE 32
578 #define FLOAT_TYPE_SIZE 32
579 #define LONG_TYPE_SIZE BITS_PER_WORD
580 #define MAX_WCHAR_TYPE_SIZE 32
581 #define DOUBLE_TYPE_SIZE 64
582 #define LONG_LONG_TYPE_SIZE 64
584 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
585 #define MAX_BITS_PER_WORD 64
586 #define MAX_LONG_TYPE_SIZE 64
588 #define MAX_BITS_PER_WORD 32
589 #define MAX_LONG_TYPE_SIZE 32
592 /* Define if you don't want extended real, but do want to use the
593 software floating point emulator for REAL_ARITHMETIC and
594 decimal <-> binary conversion. */
595 /* #define REAL_ARITHMETIC */
597 /* Define this if most significant byte of a word is the lowest numbered. */
598 /* That is true on the 80386. */
600 #define BITS_BIG_ENDIAN 0
602 /* Define this if most significant byte of a word is the lowest numbered. */
603 /* That is not true on the 80386. */
604 #define BYTES_BIG_ENDIAN 0
606 /* Define this if most significant word of a multiword number is the lowest
608 /* Not true for 80386 */
609 #define WORDS_BIG_ENDIAN 0
611 /* number of bits in an addressable storage unit */
612 #define BITS_PER_UNIT 8
614 /* Width in bits of a "word", which is the contents of a machine register.
615 Note that this is not necessarily the width of data type `int';
616 if using 16-bit ints on a 80386, this would still be 32.
617 But on a machine with 16-bit registers, this would be 16. */
618 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
620 /* Width of a word, in units (bytes). */
621 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
622 #define MIN_UNITS_PER_WORD 4
624 /* Width in bits of a pointer.
625 See also the macro `Pmode' defined below. */
626 #define POINTER_SIZE BITS_PER_WORD
628 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
629 #define PARM_BOUNDARY BITS_PER_WORD
631 /* Boundary (in *bits*) on which stack pointer should be aligned. */
632 #define STACK_BOUNDARY BITS_PER_WORD
634 /* Boundary (in *bits*) on which the stack pointer preferrs to be
635 aligned; the compiler cannot rely on having this alignment. */
636 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
638 /* Allocation boundary for the code of a function. */
639 #define FUNCTION_BOUNDARY 16
641 /* Alignment of field after `int : 0' in a structure. */
643 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
645 /* Minimum size in bits of the largest boundary to which any
646 and all fundamental data types supported by the hardware
647 might need to be aligned. No data type wants to be aligned
650 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
651 and Pentium Pro XFmode values at 128 bit boundaries. */
653 #define BIGGEST_ALIGNMENT 128
655 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
656 #define ALIGN_MODE_128(MODE) \
657 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
658 || (MODE) == V4SFmode || (MODE) == V4SImode)
660 /* The published ABIs say that doubles should be aligned on word
661 boundaries, so lower the aligment for structure fields unless
662 -malign-double is set. */
663 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
664 constant. Use the smaller value in that context. */
665 #ifndef IN_TARGET_LIBS
666 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
668 #define BIGGEST_FIELD_ALIGNMENT 32
671 /* If defined, a C expression to compute the alignment given to a
672 constant that is being placed in memory. EXP is the constant
673 and ALIGN is the alignment that the object would ordinarily have.
674 The value of this macro is used instead of that alignment to align
677 If this macro is not defined, then ALIGN is used.
679 The typical use of this macro is to increase alignment for string
680 constants to be word aligned so that `strcpy' calls that copy
681 constants can be done inline. */
683 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
685 /* If defined, a C expression to compute the alignment for a static
686 variable. TYPE is the data type, and ALIGN is the alignment that
687 the object would ordinarily have. The value of this macro is used
688 instead of that alignment to align the object.
690 If this macro is not defined, then ALIGN is used.
692 One use of this macro is to increase alignment of medium-size
693 data to make it all fit in fewer cache lines. Another is to
694 cause character arrays to be word-aligned so that `strcpy' calls
695 that copy constants to character arrays can be done inline. */
697 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
699 /* If defined, a C expression to compute the alignment for a local
700 variable. TYPE is the data type, and ALIGN is the alignment that
701 the object would ordinarily have. The value of this macro is used
702 instead of that alignment to align the object.
704 If this macro is not defined, then ALIGN is used.
706 One use of this macro is to increase alignment of medium-size
707 data to make it all fit in fewer cache lines. */
709 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
711 /* Set this non-zero if move instructions will actually fail to work
712 when given unaligned data. */
713 #define STRICT_ALIGNMENT 0
715 /* If bit field type is int, don't let it cross an int,
716 and give entire struct the alignment of an int. */
717 /* Required on the 386 since it doesn't have bitfield insns. */
718 #define PCC_BITFIELD_TYPE_MATTERS 1
720 /* Standard register usage. */
722 /* This processor has special stack-like registers. See reg-stack.c
726 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode \
727 || mode==XFmode || mode==TFmode)
729 /* Number of actual hardware registers.
730 The hardware registers are assigned numbers for the compiler
731 from 0 to just below FIRST_PSEUDO_REGISTER.
732 All registers that the compiler knows about must be given numbers,
733 even those that are not normally considered general registers.
735 In the 80386 we give the 8 general purpose registers the numbers 0-7.
736 We number the floating point registers 8-15.
737 Note that registers 0-7 can be accessed as a short or int,
738 while only 0-3 may be used with byte `mov' instructions.
740 Reg 16 does not correspond to any hardware register, but instead
741 appears in the RTL as an argument pointer prior to reload, and is
742 eliminated during reloading in favor of either the stack or frame
745 #define FIRST_PSEUDO_REGISTER 53
747 /* Number of hardware registers that go into the DWARF-2 unwind info.
748 If not defined, equals FIRST_PSEUDO_REGISTER. */
750 #define DWARF_FRAME_REGISTERS 17
752 /* 1 for registers that have pervasive standard uses
753 and are not available for the register allocator.
754 On the 80386, the stack pointer is such, as is the arg pointer.
756 The value is an mask - bit 1 is set for fixed registers
757 for 32bit target, while 2 is set for fixed registers for 64bit.
758 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
760 #define FIXED_REGISTERS \
761 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
762 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
763 /*arg,flags,fpsr,dir,frame*/ \
765 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
766 0, 0, 0, 0, 0, 0, 0, 0, \
767 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
768 0, 0, 0, 0, 0, 0, 0, 0, \
769 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
770 1, 1, 1, 1, 1, 1, 1, 1, \
771 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
772 1, 1, 1, 1, 1, 1, 1, 1}
775 /* 1 for registers not available across function calls.
776 These must include the FIXED_REGISTERS and also any
777 registers that can be used without being saved.
778 The latter must include the registers where values are returned
779 and the register where structure-value addresses are passed.
780 Aside from that, you can include as many other registers as you like.
782 The value is an mask - bit 1 is set for call used
783 for 32bit target, while 2 is set for call used for 64bit.
784 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
786 #define CALL_USED_REGISTERS \
787 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
788 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
789 /*arg,flags,fpsr,dir,frame*/ \
791 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
792 3, 3, 3, 3, 3, 3, 3, 3, \
793 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
794 3, 3, 3, 3, 3, 3, 3, 3, \
795 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
796 3, 3, 3, 3, 1, 1, 1, 1, \
797 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
798 3, 3, 3, 3, 3, 3, 3, 3} \
800 /* Order in which to allocate registers. Each register must be
801 listed once, even those in FIXED_REGISTERS. List frame pointer
802 late and fixed registers last. Note that, in general, we prefer
803 registers listed in CALL_USED_REGISTERS, keeping the others
804 available for storage of persistent values.
806 Three different versions of REG_ALLOC_ORDER have been tried:
808 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
809 but slower code on simple functions returning values in eax.
811 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
812 perl 4.036 due to not being able to create a DImode register (to hold a 2
815 If the order is eax, edx, ecx, ... it produces better code for simple
816 functions, and a slightly slower compiler. Users complained about the code
817 generated by allocating edx first, so restore the 'natural' order of things. */
819 #define REG_ALLOC_ORDER \
822 /* bx,si,di,bp,sp,*/ \
826 /*r12,r15,r14,r13*/ \
828 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
829 21, 22, 23, 24, 25, 26, 27, 28, \
830 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
831 45, 46, 47, 48, 49, 50, 51, 52, \
832 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
833 8, 9, 10, 11, 12, 13, 14, 15, \
834 /*,arg,cc,fpsr,dir,frame*/ \
836 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
837 29, 30, 31, 32, 33, 34, 35, 36 }
839 /* Macro to conditionally modify fixed_regs/call_used_regs. */
840 #define CONDITIONAL_REGISTER_USAGE \
843 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
845 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
846 call_used_regs[i] = (call_used_regs[i] \
847 & (TARGET_64BIT ? 2 : 1)) != 0; \
851 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
852 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
857 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
858 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
859 fixed_regs[i] = call_used_regs[i] = 1; \
864 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
865 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
866 fixed_regs[i] = call_used_regs[i] = 1; \
868 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
872 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
873 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
874 if (TEST_HARD_REG_BIT (x, i)) \
875 fixed_regs[i] = call_used_regs[i] = 1; \
879 /* Return number of consecutive hard regs needed starting at reg REGNO
880 to hold something of mode MODE.
881 This is ordinarily the length in words of a value of mode MODE
882 but can be less for certain modes in special long registers.
884 Actually there are no two word move instructions for consecutive
885 registers. And only registers 0-3 may have mov byte instructions
889 #define HARD_REGNO_NREGS(REGNO, MODE) \
890 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
891 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
893 ? (TARGET_64BIT ? 2 : 3) \
895 ? (TARGET_64BIT ? 4 : 6) \
896 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
898 #define VALID_SSE_REG_MODE(MODE) \
899 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
900 || (MODE) == SFmode \
901 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
903 #define VALID_MMX_REG_MODE(MODE) \
904 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
905 || (MODE) == V2SImode || (MODE) == SImode)
907 #define VECTOR_MODE_SUPPORTED_P(MODE) \
908 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
909 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 : 0)
911 #define VALID_FP_MODE_P(mode) \
912 ((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
913 || (!TARGET_64BIT && (mode) == XFmode) \
914 || (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
915 || (!TARGET_64BIT && (mode) == XCmode))
917 #define VALID_INT_MODE_P(mode) \
918 ((mode) == QImode || (mode) == HImode || (mode) == SImode \
919 || (mode) == DImode \
920 || (mode) == CQImode || (mode) == CHImode || (mode) == CSImode \
921 || (mode) == CDImode)
923 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
925 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
926 ix86_hard_regno_mode_ok (REGNO, MODE)
928 /* Value is 1 if it is a good idea to tie two pseudo registers
929 when one has mode MODE1 and one has mode MODE2.
930 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
931 for any hard reg, then this must be 0 for correct output. */
933 #define MODES_TIEABLE_P(MODE1, MODE2) \
934 ((MODE1) == (MODE2) \
935 || (((MODE1) == HImode || (MODE1) == SImode \
936 || ((MODE1) == QImode \
937 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
938 || ((MODE1) == DImode && TARGET_64BIT)) \
939 && ((MODE2) == HImode || (MODE2) == SImode \
940 || ((MODE1) == QImode \
941 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
942 || ((MODE2) == DImode && TARGET_64BIT))))
945 /* Specify the modes required to caller save a given hard regno.
946 We do this on i386 to prevent flags from being saved at all.
948 Kill any attempts to combine saving of modes. */
950 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
951 (CC_REGNO_P (REGNO) ? VOIDmode \
952 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
953 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
954 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
955 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
957 /* Specify the registers used for certain standard purposes.
958 The values of these macros are register numbers. */
960 /* on the 386 the pc register is %eip, and is not usable as a general
961 register. The ordinary mov instructions won't work */
962 /* #define PC_REGNUM */
964 /* Register to use for pushing function arguments. */
965 #define STACK_POINTER_REGNUM 7
967 /* Base register for access to local variables of the function. */
968 #define HARD_FRAME_POINTER_REGNUM 6
970 /* Base register for access to local variables of the function. */
971 #define FRAME_POINTER_REGNUM 20
973 /* First floating point reg */
974 #define FIRST_FLOAT_REG 8
976 /* First & last stack-like regs */
977 #define FIRST_STACK_REG FIRST_FLOAT_REG
978 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
982 #define DIRFLAG_REG 19
984 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
985 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
987 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
988 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
990 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
991 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
993 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
994 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
996 /* Value should be nonzero if functions must have frame pointers.
997 Zero means the frame pointer need not be set up (and parms
998 may be accessed via the stack pointer) in functions that seem suitable.
999 This is computed in `reload', in reload1.c. */
1000 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1002 /* Override this in other tm.h files to cope with various OS losage
1003 requiring a frame pointer. */
1004 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1005 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1008 /* Make sure we can access arbitrary call frames. */
1009 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1011 /* Base register for access to arguments of the function. */
1012 #define ARG_POINTER_REGNUM 16
1014 /* Register in which static-chain is passed to a function.
1015 We do use ECX as static chain register for 32 bit ABI. On the
1016 64bit ABI, ECX is an argument register, so we use R10 instead. */
1017 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1019 /* Register to hold the addressing base for position independent
1020 code access to data items.
1021 We don't use PIC pointer for 64bit mode. Define the regnum to
1022 dummy value to prevent gcc from pesimizing code dealing with EBX.
1024 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
1026 /* Register in which address to store a structure value
1027 arrives in the function. On the 386, the prologue
1028 copies this from the stack to register %eax. */
1029 #define STRUCT_VALUE_INCOMING 0
1031 /* Place in which caller passes the structure value address.
1032 0 means push the value on the stack like an argument. */
1033 #define STRUCT_VALUE 0
1035 /* A C expression which can inhibit the returning of certain function
1036 values in registers, based on the type of value. A nonzero value
1037 says to return the function value in memory, just as large
1038 structures are always returned. Here TYPE will be a C expression
1039 of type `tree', representing the data type of the value.
1041 Note that values of mode `BLKmode' must be explicitly handled by
1042 this macro. Also, the option `-fpcc-struct-return' takes effect
1043 regardless of this macro. On most systems, it is possible to
1044 leave the macro undefined; this causes a default definition to be
1045 used, whose value is the constant 1 for `BLKmode' values, and 0
1048 Do not use this macro to indicate that structures and unions
1049 should always be returned in memory. You should instead use
1050 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1052 #define RETURN_IN_MEMORY(TYPE) \
1053 ((TYPE_MODE (TYPE) == BLKmode) \
1054 || (VECTOR_MODE_P (TYPE_MODE (TYPE)) && int_size_in_bytes (TYPE) == 8)\
1055 || (int_size_in_bytes (TYPE) > 12 && TYPE_MODE (TYPE) != TImode \
1056 && TYPE_MODE (TYPE) != TFmode && ! VECTOR_MODE_P (TYPE_MODE (TYPE))))
1059 /* Define the classes of registers for register constraints in the
1060 machine description. Also define ranges of constants.
1062 One of the classes must always be named ALL_REGS and include all hard regs.
1063 If there is more than one class, another class must be named NO_REGS
1064 and contain no registers.
1066 The name GENERAL_REGS must be the name of a class (or an alias for
1067 another name such as ALL_REGS). This is the class of registers
1068 that is allowed by "g" or "r" in a register constraint.
1069 Also, registers outside this class are allocated only when
1070 instructions express preferences for them.
1072 The classes must be numbered in nondecreasing order; that is,
1073 a larger-numbered class must never be contained completely
1074 in a smaller-numbered class.
1076 For any two classes, it is very desirable that there be another
1077 class that represents their union.
1079 It might seem that class BREG is unnecessary, since no useful 386
1080 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1081 and the "b" register constraint is useful in asms for syscalls.
1083 The flags and fpsr registers are in no class. */
1088 AREG, DREG, CREG, BREG, SIREG, DIREG,
1089 AD_REGS, /* %eax/%edx for DImode */
1090 Q_REGS, /* %eax %ebx %ecx %edx */
1091 NON_Q_REGS, /* %esi %edi %ebp %esp */
1092 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1093 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1094 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1095 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1105 ALL_REGS, LIM_REG_CLASSES
1108 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1110 #define INTEGER_CLASS_P(CLASS) (reg_class_subset_p (CLASS, GENERAL_REGS))
1111 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
1112 #define SSE_CLASS_P(CLASS) (reg_class_subset_p (CLASS, SSE_REGS))
1113 #define MMX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, MMX_REGS))
1114 #define MAYBE_INTEGER_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, GENERAL_REGS))
1115 #define MAYBE_FLOAT_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, FLOAT_REGS))
1116 #define MAYBE_SSE_CLASS_P(CLASS) (reg_classes_intersect_p (SSE_REGS, CLASS))
1117 #define MAYBE_MMX_CLASS_P(CLASS) (reg_classes_intersect_p (MMX_REGS, CLASS))
1119 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
1121 /* Give names of register classes as strings for dump file. */
1123 #define REG_CLASS_NAMES \
1125 "AREG", "DREG", "CREG", "BREG", \
1128 "Q_REGS", "NON_Q_REGS", \
1132 "FP_TOP_REG", "FP_SECOND_REG", \
1136 "FP_TOP_SSE_REGS", \
1137 "FP_SECOND_SSE_REGS", \
1141 "FLOAT_INT_SSE_REGS", \
1144 /* Define which registers fit in which classes.
1145 This is an initializer for a vector of HARD_REG_SET
1146 of length N_REG_CLASSES. */
1148 #define REG_CLASS_CONTENTS \
1150 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1151 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1152 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1153 { 0x03, 0x0 }, /* AD_REGS */ \
1154 { 0x0f, 0x0 }, /* Q_REGS */ \
1155 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1156 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1157 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1158 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1159 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1160 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1161 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1162 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1163 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1164 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1165 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1166 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1167 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1168 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1169 { 0xffffffff,0x1fffff } \
1172 /* The same information, inverted:
1173 Return the class number of the smallest class containing
1174 reg number REGNO. This could be a conditional expression
1175 or could index an array. */
1177 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1179 /* When defined, the compiler allows registers explicitly used in the
1180 rtl to be used as spill registers but prevents the compiler from
1181 extending the lifetime of these registers. */
1183 #define SMALL_REGISTER_CLASSES 1
1185 #define QI_REG_P(X) \
1186 (REG_P (X) && REGNO (X) < 4)
1188 #define GENERAL_REGNO_P(n) \
1189 ((n) < 8 || REX_INT_REGNO_P (n))
1191 #define GENERAL_REG_P(X) \
1192 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1194 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1196 #define NON_QI_REG_P(X) \
1197 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1199 #define REX_INT_REGNO_P(n) ((n) >= FIRST_REX_INT_REG && (n) <= LAST_REX_INT_REG)
1200 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1202 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1203 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
1204 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1205 #define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
1207 #define SSE_REGNO_P(n) \
1208 (((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG) \
1209 || ((n) >= FIRST_REX_SSE_REG && (n) <= LAST_REX_SSE_REG))
1211 #define SSE_REGNO(n) \
1212 ((n) < 8 ? FIRST_SSE_REG + (n) : FIRST_REX_SSE_REG + (n) - 8)
1213 #define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
1215 #define SSE_FLOAT_MODE_P(m) \
1216 ((TARGET_SSE && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
1218 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
1219 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
1221 #define STACK_REG_P(xop) (REG_P (xop) && \
1222 REGNO (xop) >= FIRST_STACK_REG && \
1223 REGNO (xop) <= LAST_STACK_REG)
1225 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
1227 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
1229 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1230 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1232 /* Indicate whether hard register numbered REG_NO should be converted
1234 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1235 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1237 /* The class value for index registers, and the one for base regs. */
1239 #define INDEX_REG_CLASS INDEX_REGS
1240 #define BASE_REG_CLASS GENERAL_REGS
1242 /* Get reg_class from a letter such as appears in the machine description. */
1244 #define REG_CLASS_FROM_LETTER(C) \
1245 ((C) == 'r' ? GENERAL_REGS : \
1246 (C) == 'R' ? LEGACY_REGS : \
1247 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1248 (C) == 'Q' ? Q_REGS : \
1249 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1252 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1255 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1258 (C) == 'a' ? AREG : \
1259 (C) == 'b' ? BREG : \
1260 (C) == 'c' ? CREG : \
1261 (C) == 'd' ? DREG : \
1262 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1263 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1264 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1265 (C) == 'A' ? AD_REGS : \
1266 (C) == 'D' ? DIREG : \
1267 (C) == 'S' ? SIREG : NO_REGS)
1269 /* The letters I, J, K, L and M in a register constraint string
1270 can be used to stand for particular ranges of immediate operands.
1271 This macro defines what the ranges are.
1272 C is the letter, and VALUE is a constant value.
1273 Return 1 if VALUE is in the range specified by C.
1275 I is for non-DImode shifts.
1276 J is for DImode shifts.
1277 K is for signed imm8 operands.
1278 L is for andsi as zero-extending move.
1279 M is for shifts that can be executed by the "lea" opcode.
1280 N is for immedaite operands for out/in instructions (0-255)
1283 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1284 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1285 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1286 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1287 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1288 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1289 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1292 /* Similar, but for floating constants, and defining letters G and H.
1293 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1294 TARGET_387 isn't set, because the stack register converter may need to
1295 load 0.0 into the function value register. */
1297 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1298 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1299 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1301 /* A C expression that defines the optional machine-dependent
1302 constraint letters that can be used to segregate specific types of
1303 operands, usually memory references, for the target machine. Any
1304 letter that is not elsewhere defined and not matched by
1305 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1308 If it is required for a particular target machine, it should
1309 return 1 if VALUE corresponds to the operand type represented by
1310 the constraint letter C. If C is not defined as an extra
1311 constraint, the value returned should be 0 regardless of VALUE. */
1313 #define EXTRA_CONSTRAINT(VALUE, C) \
1314 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1315 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1318 /* Place additional restrictions on the register class to use when it
1319 is necessary to be able to hold a value of mode MODE in a reload
1320 register for which class CLASS would ordinarily be used. */
1322 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1323 ((MODE) == QImode && !TARGET_64BIT \
1324 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1327 /* Given an rtx X being reloaded into a reg required to be
1328 in class CLASS, return the class of reg to actually use.
1329 In general this is just CLASS; but on some machines
1330 in some cases it is preferable to use a more restrictive class.
1331 On the 80386 series, we prevent floating constants from being
1332 reloaded into floating registers (since no move-insn can do that)
1333 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1335 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1336 QImode must go into class Q_REGS.
1337 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1338 movdf to do mem-to-mem moves through integer regs. */
1340 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1341 ix86_preferred_reload_class (X, CLASS)
1343 /* If we are copying between general and FP registers, we need a memory
1344 location. The same is true for SSE and MMX registers. */
1345 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1346 ix86_secondary_memory_needed (CLASS1, CLASS2, MODE, 1)
1348 /* QImode spills from non-QI registers need a scratch. This does not
1349 happen often -- the only example so far requires an uninitialized
1352 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1353 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1356 /* Return the maximum number of consecutive registers
1357 needed to represent mode MODE in a register of class CLASS. */
1358 /* On the 80386, this is the size of MODE in words,
1359 except in the FP regs, where a single reg is always enough.
1360 The TFmodes are really just 80bit values, so we use only 3 registers
1361 to hold them, instead of 4, as the size would suggest.
1363 #define CLASS_MAX_NREGS(CLASS, MODE) \
1364 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1365 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1366 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1367 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1369 /* A C expression whose value is nonzero if pseudos that have been
1370 assigned to registers of class CLASS would likely be spilled
1371 because registers of CLASS are needed for spill registers.
1373 The default value of this macro returns 1 if CLASS has exactly one
1374 register and zero otherwise. On most machines, this default
1375 should be used. Only define this macro to some other expression
1376 if pseudo allocated by `local-alloc.c' end up in memory because
1377 their hard registers were needed for spill registers. If this
1378 macro returns nonzero for those classes, those pseudos will only
1379 be allocated by `global.c', which knows how to reallocate the
1380 pseudo to another register. If there would not be another
1381 register available for reallocation, you should not change the
1382 definition of this macro since the only effect of such a
1383 definition would be to slow down register allocation. */
1385 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1386 (((CLASS) == AREG) \
1387 || ((CLASS) == DREG) \
1388 || ((CLASS) == CREG) \
1389 || ((CLASS) == BREG) \
1390 || ((CLASS) == AD_REGS) \
1391 || ((CLASS) == SIREG) \
1392 || ((CLASS) == DIREG))
1394 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1395 to automatically clobber for all asms.
1397 We do this in the new i386 backend to maintain source compatibility
1398 with the old cc0-based compiler. */
1400 #define MD_ASM_CLOBBERS(CLOBBERS) \
1402 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1403 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1404 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1407 /* Stack layout; function entry, exit and calling. */
1409 /* Define this if pushing a word on the stack
1410 makes the stack pointer a smaller address. */
1411 #define STACK_GROWS_DOWNWARD
1413 /* Define this if the nominal address of the stack frame
1414 is at the high-address end of the local variables;
1415 that is, each additional local variable allocated
1416 goes at a more negative offset in the frame. */
1417 #define FRAME_GROWS_DOWNWARD
1419 /* Offset within stack frame to start allocating local variables at.
1420 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1421 first local allocated. Otherwise, it is the offset to the BEGINNING
1422 of the first local allocated. */
1423 #define STARTING_FRAME_OFFSET 0
1425 /* If we generate an insn to push BYTES bytes,
1426 this says how many the stack pointer really advances by.
1427 On 386 pushw decrements by exactly 2 no matter what the position was.
1428 On the 386 there is no pushb; we use pushw instead, and this
1429 has the effect of rounding up to 2.
1431 For 64bit ABI we round up to 8 bytes.
1434 #define PUSH_ROUNDING(BYTES) \
1436 ? (((BYTES) + 7) & (-8)) \
1437 : (((BYTES) + 1) & (-2)))
1439 /* If defined, the maximum amount of space required for outgoing arguments will
1440 be computed and placed into the variable
1441 `current_function_outgoing_args_size'. No space will be pushed onto the
1442 stack for each call; instead, the function prologue should increase the stack
1443 frame size by this amount. */
1445 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1447 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1448 instructions to pass outgoing arguments. */
1450 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1452 /* Offset of first parameter from the argument pointer register value. */
1453 #define FIRST_PARM_OFFSET(FNDECL) 0
1455 /* Define this macro if functions should assume that stack space has been
1456 allocated for arguments even when their values are passed in registers.
1458 The value of this macro is the size, in bytes, of the area reserved for
1459 arguments passed in registers for the function represented by FNDECL.
1461 This space can be allocated by the caller, or be a part of the
1462 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1464 #define REG_PARM_STACK_SPACE(FNDECL) 0
1466 /* Define as a C expression that evaluates to nonzero if we do not know how
1467 to pass TYPE solely in registers. The file expr.h defines a
1468 definition that is usually appropriate, refer to expr.h for additional
1469 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1470 computed in the stack and then loaded into a register. */
1471 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1473 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1474 || TREE_ADDRESSABLE (TYPE) \
1475 || ((MODE) == TImode) \
1476 || ((MODE) == BLKmode \
1477 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1478 && 0 == (int_size_in_bytes (TYPE) \
1479 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1480 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1481 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1483 /* Value is the number of bytes of arguments automatically
1484 popped when returning from a subroutine call.
1485 FUNDECL is the declaration node of the function (as a tree),
1486 FUNTYPE is the data type of the function (as a tree),
1487 or for a library call it is an identifier node for the subroutine name.
1488 SIZE is the number of bytes of arguments passed on the stack.
1490 On the 80386, the RTD insn may be used to pop them if the number
1491 of args is fixed, but if the number is variable then the caller
1492 must pop them all. RTD can't be used for library calls now
1493 because the library is compiled with the Unix compiler.
1494 Use of RTD is a selectable option, since it is incompatible with
1495 standard Unix calling sequences. If the option is not selected,
1496 the caller must always pop the args.
1498 The attribute stdcall is equivalent to RTD on a per module basis. */
1500 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1501 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1503 /* Define how to find the value returned by a function.
1504 VALTYPE is the data type of the value (as a tree).
1505 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1506 otherwise, FUNC is 0. */
1507 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1508 gen_rtx_REG (TYPE_MODE (VALTYPE), \
1509 VALUE_REGNO (TYPE_MODE (VALTYPE)))
1511 /* Define how to find the value returned by a library function
1512 assuming the value has mode MODE. */
1514 #define LIBCALL_VALUE(MODE) \
1515 gen_rtx_REG (MODE, VALUE_REGNO (MODE))
1517 /* Define the size of the result block used for communication between
1518 untyped_call and untyped_return. The block contains a DImode value
1519 followed by the block used by fnsave and frstor. */
1521 #define APPLY_RESULT_SIZE (8+108)
1523 /* 1 if N is a possible register number for function argument passing. */
1524 #define FUNCTION_ARG_REGNO_P(N) ((N) < REGPARM_MAX)
1526 /* Define a data type for recording info about an argument list
1527 during the scan of that argument list. This data type should
1528 hold all necessary information about the function itself
1529 and about the args processed so far, enough to enable macros
1530 such as FUNCTION_ARG to determine where the next arg should go. */
1532 typedef struct ix86_args {
1533 int words; /* # words passed so far */
1534 int nregs; /* # registers available for passing */
1535 int regno; /* next available register number */
1536 int sse_words; /* # sse words passed so far */
1537 int sse_nregs; /* # sse registers available for passing */
1538 int sse_regno; /* next available sse register number */
1541 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1542 for a call to a function whose data type is FNTYPE.
1543 For a library call, FNTYPE is 0. */
1545 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1546 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1548 /* Update the data in CUM to advance over an argument
1549 of mode MODE and data type TYPE.
1550 (TYPE is null for libcalls where that information may not be available.) */
1552 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1553 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1555 /* Define where to put the arguments to a function.
1556 Value is zero to push the argument on the stack,
1557 or a hard register in which to store the argument.
1559 MODE is the argument's machine mode.
1560 TYPE is the data type of the argument (as a tree).
1561 This is null for libcalls where that information may
1563 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1564 the preceding args and about the function being called.
1565 NAMED is nonzero if this argument is a named parameter
1566 (otherwise it is an extra parameter matching an ellipsis). */
1568 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1569 (function_arg (&CUM, MODE, TYPE, NAMED))
1571 /* For an arg passed partly in registers and partly in memory,
1572 this is the number of registers used.
1573 For args passed entirely in registers or entirely in memory, zero. */
1575 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1577 /* If PIC, we cannot make sibling calls to global functions
1578 because the PLT requires %ebx live.
1579 If we are returning floats on the register stack, we cannot make
1580 sibling calls to functions that return floats. (The stack adjust
1581 instruction will wind up after the sibcall jump, and not be executed.) */
1582 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1584 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1585 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1586 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1587 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1589 /* This macro is invoked at the end of compilation. It is used here to
1590 output code for -fpic that will load the return address into %ebx. */
1593 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1595 /* Output assembler code to FILE to increment profiler label # LABELNO
1596 for profiling a function entry. */
1598 #define FUNCTION_PROFILER(FILE, LABELNO) \
1602 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1603 LPREFIX, (LABELNO)); \
1604 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1608 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1609 fprintf (FILE, "\tcall\t_mcount\n"); \
1614 /* There are three profiling modes for basic blocks available.
1615 The modes are selected at compile time by using the options
1616 -a or -ax of the gnu compiler.
1617 The variable `profile_block_flag' will be set according to the
1620 profile_block_flag == 0, no option used:
1624 profile_block_flag == 1, -a option used.
1626 Count frequency of execution of every basic block.
1628 profile_block_flag == 2, -ax option used.
1630 Generate code to allow several different profiling modes at run time.
1631 Available modes are:
1632 Produce a trace of all basic blocks.
1633 Count frequency of jump instructions executed.
1634 In every mode it is possible to start profiling upon entering
1635 certain functions and to disable profiling of some other functions.
1637 The result of basic-block profiling will be written to a file `bb.out'.
1638 If the -ax option is used parameters for the profiling will be read
1643 /* The following macro shall output assembler code to FILE
1644 to initialize basic-block profiling. */
1646 #undef FUNCTION_BLOCK_PROFILER
1647 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1648 ix86_output_function_block_profiler (FILE, BLOCK_OR_LABEL)
1650 /* The following macro shall output assembler code to FILE
1651 to increment a counter associated with basic block number BLOCKNO. */
1653 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1654 ix86_output_block_profiler (FILE, BLOCKNO)
1656 /* The following macro shall output rtl for the epilogue
1657 to indicate a return from function during basic-block profiling.
1659 If profiling_block_flag == 2:
1661 Output assembler code to call function `__bb_trace_ret'.
1663 Note that function `__bb_trace_ret' must not change the
1664 machine state, especially the flag register. To grant
1665 this, you must output code to save and restore registers
1666 either in this macro or in the macros MACHINE_STATE_SAVE
1667 and MACHINE_STATE_RESTORE. The last two macros will be
1668 used in the function `__bb_trace_ret', so you must make
1669 sure that the function prologue does not change any
1670 register prior to saving it with MACHINE_STATE_SAVE.
1672 else if profiling_block_flag != 0:
1674 The macro will not be used, so it need not distinguish
1678 #define FUNCTION_BLOCK_PROFILER_EXIT \
1679 emit_call_insn (gen_call (gen_rtx_MEM (QImode, \
1680 gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")), \
1681 const0_rtx, constm1_rtx))
1683 /* The function `__bb_trace_func' is called in every basic block
1684 and is not allowed to change the machine state. Saving (restoring)
1685 the state can either be done in the BLOCK_PROFILER macro,
1686 before calling function (rsp. after returning from function)
1687 `__bb_trace_func', or it can be done inside the function by
1688 defining the macros:
1690 MACHINE_STATE_SAVE(ID)
1691 MACHINE_STATE_RESTORE(ID)
1693 In the latter case care must be taken, that the prologue code
1694 of function `__bb_trace_func' does not already change the
1695 state prior to saving it with MACHINE_STATE_SAVE.
1697 The parameter `ID' is a string identifying a unique macro use.
1699 On the i386 the initialization code at the begin of
1700 function `__bb_trace_func' contains a `sub' instruction
1701 therefore we handle save and restore of the flag register
1702 in the BLOCK_PROFILER macro.
1704 Note that ebx, esi, and edi are callee-save, so we don't have to
1705 preserve them explicitly. */
1707 #define MACHINE_STATE_SAVE(ID) \
1709 register int eax_ __asm__("eax"); \
1710 register int ecx_ __asm__("ecx"); \
1711 register int edx_ __asm__("edx"); \
1712 __asm__ __volatile__ ("\
1716 : : "r"(eax_), "r"(ecx_), "r"(edx_)); \
1719 #define MACHINE_STATE_RESTORE(ID) \
1721 register int eax_ __asm__("eax"); \
1722 register int ecx_ __asm__("ecx"); \
1723 register int edx_ __asm__("edx"); \
1724 __asm__ __volatile__ ("\
1728 : "=r"(eax_), "=r"(ecx_), "=r"(edx_)); \
1731 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1732 the stack pointer does not matter. The value is tested only in
1733 functions that have frame pointers.
1734 No definition is equivalent to always zero. */
1735 /* Note on the 386 it might be more efficient not to define this since
1736 we have to restore it ourselves from the frame pointer, in order to
1739 #define EXIT_IGNORE_STACK 1
1741 /* Output assembler code for a block containing the constant parts
1742 of a trampoline, leaving space for the variable parts. */
1744 /* On the 386, the trampoline contains two instructions:
1747 The trampoline is generated entirely at runtime. The operand of JMP
1748 is the address of FUNCTION relative to the instruction following the
1749 JMP (which is 5 bytes long). */
1751 /* Length in units of the trampoline for entering a nested function. */
1753 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1755 /* Emit RTL insns to initialize the variable parts of a trampoline.
1756 FNADDR is an RTX for the address of the function's pure code.
1757 CXT is an RTX for the static chain value for the function. */
1759 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1760 x86_initialize_trampoline (TRAMP, FNADDR, CXT)
1762 /* Definitions for register eliminations.
1764 This is an array of structures. Each structure initializes one pair
1765 of eliminable registers. The "from" register number is given first,
1766 followed by "to". Eliminations of the same "from" register are listed
1767 in order of preference.
1769 There are two registers that can always be eliminated on the i386.
1770 The frame pointer and the arg pointer can be replaced by either the
1771 hard frame pointer or to the stack pointer, depending upon the
1772 circumstances. The hard frame pointer is not used before reload and
1773 so it is not eligible for elimination. */
1775 #define ELIMINABLE_REGS \
1776 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1777 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1778 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1779 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1781 /* Given FROM and TO register numbers, say whether this elimination is
1782 allowed. Frame pointer elimination is automatically handled.
1784 All other eliminations are valid. */
1786 #define CAN_ELIMINATE(FROM, TO) \
1787 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1789 /* Define the offset between two registers, one to be eliminated, and the other
1790 its replacement, at the start of a routine. */
1792 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1793 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1795 /* Addressing modes, and classification of registers for them. */
1797 /* #define HAVE_POST_INCREMENT 0 */
1798 /* #define HAVE_POST_DECREMENT 0 */
1800 /* #define HAVE_PRE_DECREMENT 0 */
1801 /* #define HAVE_PRE_INCREMENT 0 */
1803 /* Macros to check register numbers against specific register classes. */
1805 /* These assume that REGNO is a hard or pseudo reg number.
1806 They give nonzero only if REGNO is a hard reg of the suitable class
1807 or a pseudo reg currently allocated to a suitable hard reg.
1808 Since they use reg_renumber, they are safe only once reg_renumber
1809 has been allocated, which happens in local-alloc.c. */
1811 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1812 ((REGNO) < STACK_POINTER_REGNUM \
1813 || (REGNO >= FIRST_REX_INT_REG \
1814 && (REGNO) <= LAST_REX_INT_REG) \
1815 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1816 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1817 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1819 #define REGNO_OK_FOR_BASE_P(REGNO) \
1820 ((REGNO) <= STACK_POINTER_REGNUM \
1821 || (REGNO) == ARG_POINTER_REGNUM \
1822 || (REGNO) == FRAME_POINTER_REGNUM \
1823 || (REGNO >= FIRST_REX_INT_REG \
1824 && (REGNO) <= LAST_REX_INT_REG) \
1825 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1826 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1827 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1829 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1830 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1832 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1833 and check its validity for a certain class.
1834 We have two alternate definitions for each of them.
1835 The usual definition accepts all pseudo regs; the other rejects
1836 them unless they have been allocated suitable hard regs.
1837 The symbol REG_OK_STRICT causes the latter definition to be used.
1839 Most source files want to accept pseudo regs in the hope that
1840 they will get allocated to the class that the insn wants them to be in.
1841 Source files for reload pass need to be strict.
1842 After reload, it makes no difference, since pseudo regs have
1843 been eliminated by then. */
1846 /* Non strict versions, pseudos are ok */
1847 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1848 (REGNO (X) < STACK_POINTER_REGNUM \
1849 || (REGNO (X) >= FIRST_REX_INT_REG \
1850 && REGNO (X) <= LAST_REX_INT_REG) \
1851 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1853 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1854 (REGNO (X) <= STACK_POINTER_REGNUM \
1855 || REGNO (X) == ARG_POINTER_REGNUM \
1856 || REGNO (X) == FRAME_POINTER_REGNUM \
1857 || (REGNO (X) >= FIRST_REX_INT_REG \
1858 && REGNO (X) <= LAST_REX_INT_REG) \
1859 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1861 /* Strict versions, hard registers only */
1862 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1863 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1865 #ifndef REG_OK_STRICT
1866 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1867 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1870 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1871 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1874 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1875 that is a valid memory address for an instruction.
1876 The MODE argument is the machine mode for the MEM expression
1877 that wants to use this address.
1879 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1880 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1882 See legitimize_pic_address in i386.c for details as to what
1883 constitutes a legitimate address when -fpic is used. */
1885 #define MAX_REGS_PER_ADDRESS 2
1887 #define CONSTANT_ADDRESS_P(X) \
1888 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1889 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1890 || GET_CODE (X) == CONST_DOUBLE)
1892 /* Nonzero if the constant value X is a legitimate general operand.
1893 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1895 #define LEGITIMATE_CONSTANT_P(X) 1
1897 #ifdef REG_OK_STRICT
1898 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1900 if (legitimate_address_p (MODE, X, 1)) \
1905 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1907 if (legitimate_address_p (MODE, X, 0)) \
1913 /* If defined, a C expression to determine the base term of address X.
1914 This macro is used in only one place: `find_base_term' in alias.c.
1916 It is always safe for this macro to not be defined. It exists so
1917 that alias analysis can understand machine-dependent addresses.
1919 The typical use of this macro is to handle addresses containing
1920 a label_ref or symbol_ref within an UNSPEC. */
1922 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1924 /* Try machine-dependent ways of modifying an illegitimate address
1925 to be legitimate. If we find one, return the new, valid address.
1926 This macro is used in only one place: `memory_address' in explow.c.
1928 OLDX is the address as it was before break_out_memory_refs was called.
1929 In some cases it is useful to look at this to decide what needs to be done.
1931 MODE and WIN are passed so that this macro can use
1932 GO_IF_LEGITIMATE_ADDRESS.
1934 It is always safe for this macro to do nothing. It exists to recognize
1935 opportunities to optimize the output.
1937 For the 80386, we handle X+REG by loading X into a register R and
1938 using R+REG. R will go in a general reg and indexing will be used.
1939 However, if REG is a broken-out memory address or multiplication,
1940 nothing needs to be done because REG can certainly go in a general reg.
1942 When -fpic is used, special handling is needed for symbolic references.
1943 See comments by legitimize_pic_address in i386.c for details. */
1945 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1947 (X) = legitimize_address (X, OLDX, MODE); \
1948 if (memory_address_p (MODE, X)) \
1952 #define REWRITE_ADDRESS(x) rewrite_address(x)
1954 /* Nonzero if the constant value X is a legitimate general operand
1955 when generating PIC code. It is given that flag_pic is on and
1956 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1958 #define LEGITIMATE_PIC_OPERAND_P(X) \
1959 (! SYMBOLIC_CONST (X) \
1960 || legitimate_pic_address_disp_p (X))
1962 #define SYMBOLIC_CONST(X) \
1963 (GET_CODE (X) == SYMBOL_REF \
1964 || GET_CODE (X) == LABEL_REF \
1965 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1967 /* Go to LABEL if ADDR (a legitimate address expression)
1968 has an effect that depends on the machine mode it is used for.
1969 On the 80386, only postdecrement and postincrement address depend thus
1970 (the amount of decrement or increment being the length of the operand). */
1971 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1972 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
1974 /* Codes for all the SSE/MMX builtins. */
1986 IX86_BUILTIN_CMPEQPS,
1987 IX86_BUILTIN_CMPLTPS,
1988 IX86_BUILTIN_CMPLEPS,
1989 IX86_BUILTIN_CMPGTPS,
1990 IX86_BUILTIN_CMPGEPS,
1991 IX86_BUILTIN_CMPNEQPS,
1992 IX86_BUILTIN_CMPNLTPS,
1993 IX86_BUILTIN_CMPNLEPS,
1994 IX86_BUILTIN_CMPNGTPS,
1995 IX86_BUILTIN_CMPNGEPS,
1996 IX86_BUILTIN_CMPORDPS,
1997 IX86_BUILTIN_CMPUNORDPS,
1998 IX86_BUILTIN_CMPNEPS,
1999 IX86_BUILTIN_CMPEQSS,
2000 IX86_BUILTIN_CMPLTSS,
2001 IX86_BUILTIN_CMPLESS,
2002 IX86_BUILTIN_CMPGTSS,
2003 IX86_BUILTIN_CMPGESS,
2004 IX86_BUILTIN_CMPNEQSS,
2005 IX86_BUILTIN_CMPNLTSS,
2006 IX86_BUILTIN_CMPNLESS,
2007 IX86_BUILTIN_CMPNGTSS,
2008 IX86_BUILTIN_CMPNGESS,
2009 IX86_BUILTIN_CMPORDSS,
2010 IX86_BUILTIN_CMPUNORDSS,
2011 IX86_BUILTIN_CMPNESS,
2013 IX86_BUILTIN_COMIEQSS,
2014 IX86_BUILTIN_COMILTSS,
2015 IX86_BUILTIN_COMILESS,
2016 IX86_BUILTIN_COMIGTSS,
2017 IX86_BUILTIN_COMIGESS,
2018 IX86_BUILTIN_COMINEQSS,
2019 IX86_BUILTIN_UCOMIEQSS,
2020 IX86_BUILTIN_UCOMILTSS,
2021 IX86_BUILTIN_UCOMILESS,
2022 IX86_BUILTIN_UCOMIGTSS,
2023 IX86_BUILTIN_UCOMIGESS,
2024 IX86_BUILTIN_UCOMINEQSS,
2026 IX86_BUILTIN_CVTPI2PS,
2027 IX86_BUILTIN_CVTPS2PI,
2028 IX86_BUILTIN_CVTSI2SS,
2029 IX86_BUILTIN_CVTSS2SI,
2030 IX86_BUILTIN_CVTTPS2PI,
2031 IX86_BUILTIN_CVTTSS2SI,
2032 IX86_BUILTIN_M_FROM_INT,
2033 IX86_BUILTIN_M_TO_INT,
2040 IX86_BUILTIN_LOADAPS,
2041 IX86_BUILTIN_LOADUPS,
2042 IX86_BUILTIN_STOREAPS,
2043 IX86_BUILTIN_STOREUPS,
2044 IX86_BUILTIN_LOADSS,
2045 IX86_BUILTIN_STORESS,
2048 IX86_BUILTIN_MOVHLPS,
2049 IX86_BUILTIN_MOVLHPS,
2050 IX86_BUILTIN_LOADHPS,
2051 IX86_BUILTIN_LOADLPS,
2052 IX86_BUILTIN_STOREHPS,
2053 IX86_BUILTIN_STORELPS,
2055 IX86_BUILTIN_MASKMOVQ,
2056 IX86_BUILTIN_MOVMSKPS,
2057 IX86_BUILTIN_PMOVMSKB,
2059 IX86_BUILTIN_MOVNTPS,
2060 IX86_BUILTIN_MOVNTQ,
2062 IX86_BUILTIN_PACKSSWB,
2063 IX86_BUILTIN_PACKSSDW,
2064 IX86_BUILTIN_PACKUSWB,
2069 IX86_BUILTIN_PADDSB,
2070 IX86_BUILTIN_PADDSW,
2071 IX86_BUILTIN_PADDUSB,
2072 IX86_BUILTIN_PADDUSW,
2076 IX86_BUILTIN_PSUBSB,
2077 IX86_BUILTIN_PSUBSW,
2078 IX86_BUILTIN_PSUBUSB,
2079 IX86_BUILTIN_PSUBUSW,
2089 IX86_BUILTIN_PCMPEQB,
2090 IX86_BUILTIN_PCMPEQW,
2091 IX86_BUILTIN_PCMPEQD,
2092 IX86_BUILTIN_PCMPGTB,
2093 IX86_BUILTIN_PCMPGTW,
2094 IX86_BUILTIN_PCMPGTD,
2096 IX86_BUILTIN_PEXTRW,
2097 IX86_BUILTIN_PINSRW,
2099 IX86_BUILTIN_PMADDWD,
2101 IX86_BUILTIN_PMAXSW,
2102 IX86_BUILTIN_PMAXUB,
2103 IX86_BUILTIN_PMINSW,
2104 IX86_BUILTIN_PMINUB,
2106 IX86_BUILTIN_PMULHUW,
2107 IX86_BUILTIN_PMULHW,
2108 IX86_BUILTIN_PMULLW,
2110 IX86_BUILTIN_PSADBW,
2111 IX86_BUILTIN_PSHUFW,
2121 IX86_BUILTIN_PSLLWI,
2122 IX86_BUILTIN_PSLLDI,
2123 IX86_BUILTIN_PSLLQI,
2124 IX86_BUILTIN_PSRAWI,
2125 IX86_BUILTIN_PSRADI,
2126 IX86_BUILTIN_PSRLWI,
2127 IX86_BUILTIN_PSRLDI,
2128 IX86_BUILTIN_PSRLQI,
2130 IX86_BUILTIN_PUNPCKHBW,
2131 IX86_BUILTIN_PUNPCKHWD,
2132 IX86_BUILTIN_PUNPCKHDQ,
2133 IX86_BUILTIN_PUNPCKLBW,
2134 IX86_BUILTIN_PUNPCKLWD,
2135 IX86_BUILTIN_PUNPCKLDQ,
2137 IX86_BUILTIN_SHUFPS,
2141 IX86_BUILTIN_RSQRTPS,
2142 IX86_BUILTIN_RSQRTSS,
2143 IX86_BUILTIN_SQRTPS,
2144 IX86_BUILTIN_SQRTSS,
2146 IX86_BUILTIN_UNPCKHPS,
2147 IX86_BUILTIN_UNPCKLPS,
2150 IX86_BUILTIN_ANDNPS,
2155 IX86_BUILTIN_LDMXCSR,
2156 IX86_BUILTIN_STMXCSR,
2157 IX86_BUILTIN_SFENCE,
2158 IX86_BUILTIN_PREFETCH,
2160 /* Composite builtins, expand to more than one insn. */
2161 IX86_BUILTIN_SETPS1,
2164 IX86_BUILTIN_SETRPS,
2165 IX86_BUILTIN_LOADPS1,
2166 IX86_BUILTIN_LOADRPS,
2167 IX86_BUILTIN_STOREPS1,
2168 IX86_BUILTIN_STORERPS,
2170 IX86_BUILTIN_MMX_ZERO,
2175 /* Initialize the target-specific builtin functions. Only do something
2176 if TARGET_MMX is nonzero; we take care in ix86_init_builtins not to
2177 enable any SSE builtins if TARGET_SSE is zero. */
2178 #define MD_INIT_BUILTINS \
2182 ix86_init_builtins (); \
2186 /* Expand a target-specific builtin function. */
2187 #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
2188 ix86_expand_builtin (EXP, TARGET, SUBTARGET, MODE, IGNORE)
2190 /* Define this macro if references to a symbol must be treated
2191 differently depending on something about the variable or
2192 function named by the symbol (such as what section it is in).
2194 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2195 so that we may access it directly in the GOT. */
2197 #define ENCODE_SECTION_INFO(DECL) \
2202 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2203 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2205 if (GET_CODE (rtl) == MEM) \
2207 if (TARGET_DEBUG_ADDR \
2208 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2210 fprintf (stderr, "Encode %s, public = %d\n", \
2211 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2212 TREE_PUBLIC (DECL)); \
2215 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2216 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2217 || ! TREE_PUBLIC (DECL)); \
2223 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2224 codes once the function is being compiled into assembly code, but
2225 not before. (It is not done before, because in the case of
2226 compiling an inline function, it would lead to multiple PIC
2227 prologues being included in functions which used inline functions
2228 and were compiled to assembly language.) */
2230 #define FINALIZE_PIC \
2233 current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \
2238 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2239 with arguments ARGS is a valid machine specific attribute for DECL.
2240 The attributes in ATTRIBUTES have previously been assigned to DECL. */
2242 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
2243 (ix86_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
2245 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2246 with arguments ARGS is a valid machine specific attribute for TYPE.
2247 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2249 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2250 (ix86_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2252 /* If defined, a C expression whose value is zero if the attributes on
2253 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2254 two if they are nearly compatible (which causes a warning to be
2257 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2258 (ix86_comp_type_attributes (TYPE1, TYPE2))
2260 /* If defined, a C statement that assigns default attributes to newly
2263 /* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */
2265 /* Max number of args passed in registers. If this is more than 3, we will
2266 have problems with ebx (register #4), since it is a caller save register and
2267 is also used as the pic register in ELF. So for now, don't allow more than
2268 3 registers to be passed in registers. */
2270 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2272 #define SSE_REGPARM_MAX (TARGET_64BIT ? 16 : 0)
2275 /* Specify the machine mode that this machine uses
2276 for the index in the tablejump instruction. */
2277 #define CASE_VECTOR_MODE Pmode
2279 /* Define as C expression which evaluates to nonzero if the tablejump
2280 instruction expects the table to contain offsets from the address of the
2282 Do not define this if the table should contain absolute addresses. */
2283 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2285 /* Specify the tree operation to be used to convert reals to integers.
2286 This should be changed to take advantage of fist --wfs ??
2288 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2290 /* This is the kind of divide that is easiest to do in the general case. */
2291 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2293 /* Define this as 1 if `char' should by default be signed; else as 0. */
2294 #define DEFAULT_SIGNED_CHAR 1
2296 /* Max number of bytes we can move from memory to memory
2297 in one reasonably fast instruction. */
2300 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2301 move efficiently, as opposed to MOVE_MAX which is the maximum
2302 number of bytes we can move with a single instruction. */
2303 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2305 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2306 move-instruction pairs, we will do a movstr or libcall instead.
2307 Increasing the value will always make code faster, but eventually
2308 incurs high cost in increased code size.
2310 If you don't define this, a reasonable default is used. */
2312 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2314 /* Define if shifts truncate the shift count
2315 which implies one can omit a sign-extension or zero-extension
2316 of a shift count. */
2317 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2319 /* #define SHIFT_COUNT_TRUNCATED */
2321 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2322 is done just by pretending it is already truncated. */
2323 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2325 /* We assume that the store-condition-codes instructions store 0 for false
2326 and some other value for true. This is the value stored for true. */
2328 #define STORE_FLAG_VALUE 1
2330 /* When a prototype says `char' or `short', really pass an `int'.
2331 (The 386 can't easily push less than an int.) */
2333 #define PROMOTE_PROTOTYPES 1
2335 /* A macro to update M and UNSIGNEDP when an object whose type is
2336 TYPE and which has the specified mode and signedness is to be
2337 stored in a register. This macro is only called when TYPE is a
2340 On i386 it is sometimes usefull to promote HImode and QImode
2341 quantities to SImode. The choice depends on target type. */
2343 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2344 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2345 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2348 /* Specify the machine mode that pointers have.
2349 After generation of rtl, the compiler makes no further distinction
2350 between pointers and any other objects of this machine mode. */
2351 #define Pmode (TARGET_64BIT ? DImode : SImode)
2353 /* A function address in a call instruction
2354 is a byte address (for indexing purposes)
2355 so give the MEM rtx a byte's mode. */
2356 #define FUNCTION_MODE QImode
2358 /* A part of a C `switch' statement that describes the relative costs
2359 of constant RTL expressions. It must contain `case' labels for
2360 expression codes `const_int', `const', `symbol_ref', `label_ref'
2361 and `const_double'. Each case must ultimately reach a `return'
2362 statement to return the relative cost of the use of that kind of
2363 constant value in an expression. The cost may depend on the
2364 precise value of the constant, which is available for examination
2365 in X, and the rtx code of the expression in which it is contained,
2366 found in OUTER_CODE.
2368 CODE is the expression code--redundant, since it can be obtained
2369 with `GET_CODE (X)'. */
2371 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2376 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2378 case CONST_DOUBLE: \
2381 if (GET_MODE (RTX) == VOIDmode) \
2384 code = standard_80387_constant_p (RTX); \
2385 return code == 1 ? 1 : \
2390 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2391 #define TOPLEVEL_COSTS_N_INSNS(N) \
2392 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2394 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2395 This can be used, for example, to indicate how costly a multiply
2396 instruction is. In writing this macro, you can use the construct
2397 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2398 instructions. OUTER_CODE is the code of the expression in which X
2401 This macro is optional; do not define it if the default cost
2402 assumptions are adequate for the target machine. */
2404 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2406 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2407 && GET_MODE (XEXP (X, 0)) == SImode) \
2409 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2411 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2412 if (value == 2 || value == 3) \
2413 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2415 /* fall through */ \
2421 if (GET_MODE (XEXP (X, 0)) == DImode) \
2423 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2425 if (INTVAL (XEXP (X, 1)) > 32) \
2426 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2428 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2432 if (GET_CODE (XEXP (X, 1)) == AND) \
2433 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2435 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2440 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2441 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2443 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2448 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2450 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2453 while (value != 0) \
2459 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2460 + nbits * ix86_cost->mult_bit); \
2462 else /* This is arbitrary */ \
2463 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2464 + 7 * ix86_cost->mult_bit); \
2470 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2473 if (GET_CODE (XEXP (X, 0)) == PLUS \
2474 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2475 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2476 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2478 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1)); \
2479 if (val == 2 || val == 4 || val == 8) \
2481 return (COSTS_N_INSNS (ix86_cost->lea) \
2482 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2483 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2484 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2487 else if (GET_CODE (XEXP (X, 0)) == MULT \
2488 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2490 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2491 if (val == 2 || val == 4 || val == 8) \
2493 return (COSTS_N_INSNS (ix86_cost->lea) \
2494 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2495 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2498 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2500 return (COSTS_N_INSNS (ix86_cost->lea) \
2501 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2502 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2503 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2506 /* fall through */ \
2511 if (GET_MODE (X) == DImode) \
2512 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2513 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2514 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2515 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2516 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2518 /* fall through */ \
2521 if (GET_MODE (X) == DImode) \
2522 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2523 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2529 /* An expression giving the cost of an addressing mode that contains
2530 ADDRESS. If not defined, the cost is computed from the ADDRESS
2531 expression and the `CONST_COSTS' values.
2533 For most CISC machines, the default cost is a good approximation
2534 of the true cost of the addressing mode. However, on RISC
2535 machines, all instructions normally have the same length and
2536 execution time. Hence all addresses will have equal costs.
2538 In cases where more than one form of an address is known, the form
2539 with the lowest cost will be used. If multiple forms have the
2540 same, lowest, cost, the one that is the most complex will be used.
2542 For example, suppose an address that is equal to the sum of a
2543 register and a constant is used twice in the same basic block.
2544 When this macro is not defined, the address will be computed in a
2545 register and memory references will be indirect through that
2546 register. On machines where the cost of the addressing mode
2547 containing the sum is no higher than that of a simple indirect
2548 reference, this will produce an additional instruction and
2549 possibly require an additional register. Proper specification of
2550 this macro eliminates this overhead for such machines.
2552 Similar use of this macro is made in strength reduction of loops.
2554 ADDRESS need not be valid as an address. In such a case, the cost
2555 is not relevant and can be any value; invalid addresses need not be
2556 assigned a different cost.
2558 On machines where an address involving more than one register is as
2559 cheap as an address computation involving only one register,
2560 defining `ADDRESS_COST' to reflect this can cause two registers to
2561 be live over a region of code where only one would have been if
2562 `ADDRESS_COST' were not defined in that manner. This effect should
2563 be considered in the definition of this macro. Equivalent costs
2564 should probably only be given to addresses with different numbers
2565 of registers on machines with lots of registers.
2567 This macro will normally either not be defined or be defined as a
2570 For i386, it is better to use a complex address than let gcc copy
2571 the address into a reg and make a new pseudo. But not if the address
2572 requires to two regs - that would mean more pseudos with longer
2575 #define ADDRESS_COST(RTX) \
2576 ix86_address_cost (RTX)
2578 /* A C expression for the cost of moving data from a register in class FROM to
2579 one in class TO. The classes are expressed using the enumeration values
2580 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2581 interpreted relative to that.
2583 It is not required that the cost always equal 2 when FROM is the same as TO;
2584 on some machines it is expensive to move between registers if they are not
2585 general registers. */
2587 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2588 ix86_register_move_cost (MODE, CLASS1, CLASS2)
2590 /* A C expression for the cost of moving data of mode M between a
2591 register and memory. A value of 2 is the default; this cost is
2592 relative to those in `REGISTER_MOVE_COST'.
2594 If moving between registers and memory is more expensive than
2595 between two registers, you should define this macro to express the
2598 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2599 ix86_memory_move_cost (MODE, CLASS, IN)
2601 /* A C expression for the cost of a branch instruction. A value of 1
2602 is the default; other values are interpreted relative to that. */
2604 #define BRANCH_COST ix86_branch_cost
2606 /* Define this macro as a C expression which is nonzero if accessing
2607 less than a word of memory (i.e. a `char' or a `short') is no
2608 faster than accessing a word of memory, i.e., if such access
2609 require more than one instruction or if there is no difference in
2610 cost between byte and (aligned) word loads.
2612 When this macro is not defined, the compiler will access a field by
2613 finding the smallest containing object; when it is defined, a
2614 fullword load will be used if alignment permits. Unless bytes
2615 accesses are faster than word accesses, using word accesses is
2616 preferable since it may eliminate subsequent memory access if
2617 subsequent accesses occur to other fields in the same word of the
2618 structure, but to different bytes. */
2620 #define SLOW_BYTE_ACCESS 0
2622 /* Nonzero if access to memory by shorts is slow and undesirable. */
2623 #define SLOW_SHORT_ACCESS 0
2625 /* Define this macro if zero-extension (of a `char' or `short' to an
2626 `int') can be done faster if the destination is a register that is
2629 If you define this macro, you must have instruction patterns that
2630 recognize RTL structures like this:
2632 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2634 and likewise for `HImode'. */
2636 /* #define SLOW_ZERO_EXTEND */
2638 /* Define this macro to be the value 1 if unaligned accesses have a
2639 cost many times greater than aligned accesses, for example if they
2640 are emulated in a trap handler.
2642 When this macro is non-zero, the compiler will act as if
2643 `STRICT_ALIGNMENT' were non-zero when generating code for block
2644 moves. This can cause significantly more instructions to be
2645 produced. Therefore, do not set this macro non-zero if unaligned
2646 accesses only add a cycle or two to the time for a memory access.
2648 If the value of this macro is always zero, it need not be defined. */
2650 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2652 /* Define this macro to inhibit strength reduction of memory
2653 addresses. (On some machines, such strength reduction seems to do
2654 harm rather than good.) */
2656 /* #define DONT_REDUCE_ADDR */
2658 /* Define this macro if it is as good or better to call a constant
2659 function address than to call an address kept in a register.
2661 Desirable on the 386 because a CALL with a constant address is
2662 faster than one with a register address. */
2664 #define NO_FUNCTION_CSE
2666 /* Define this macro if it is as good or better for a function to call
2667 itself with an explicit address than to call an address kept in a
2670 #define NO_RECURSIVE_FUNCTION_CSE
2672 /* A C statement (sans semicolon) to update the integer variable COST
2673 based on the relationship between INSN that is dependent on
2674 DEP_INSN through the dependence LINK. The default is to make no
2675 adjustment to COST. This can be used for example to specify to
2676 the scheduler that an output- or anti-dependence does not incur
2677 the same cost as a data-dependence. */
2679 #define ADJUST_COST(insn,link,dep_insn,cost) \
2680 (cost) = ix86_adjust_cost(insn, link, dep_insn, cost)
2682 #define ISSUE_RATE \
2685 #define MD_SCHED_INIT(DUMP, SCHED_VERBOSE, MAX_READY) \
2686 ix86_sched_init (DUMP, SCHED_VERBOSE)
2688 #define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \
2689 (CIM) = ix86_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK)
2691 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
2692 ((CAN_ISSUE_MORE) = \
2693 ix86_variable_issue (DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE))
2695 /* Add any extra modes needed to represent the condition code.
2697 For the i386, we need separate modes when floating-point
2698 equality comparisons are being done.
2700 Add CCNO to indicate comparisons against zero that requires
2701 Overflow flag to be unset. Sign bit test is used instead and
2702 thus can be used to form "a&b>0" type of tests.
2704 Add CCGC to indicate comparisons agains zero that allows
2705 unspecified garbage in the Carry flag. This mode is used
2706 by inc/dec instructions.
2708 Add CCGOC to indicate comparisons agains zero that allows
2709 unspecified garbage in the Carry and Overflow flag. This
2710 mode is used to simulate comparisons of (a-b) and (a+b)
2711 against zero using sub/cmp/add operations.
2713 Add CCZ to indicate that only the Zero flag is valid. */
2715 #define EXTRA_CC_MODES \
2716 CC(CCGCmode, "CCGC") \
2717 CC(CCGOCmode, "CCGOC") \
2718 CC(CCNOmode, "CCNO") \
2719 CC(CCZmode, "CCZ") \
2720 CC(CCFPmode, "CCFP") \
2721 CC(CCFPUmode, "CCFPU")
2723 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2724 return the mode to be used for the comparison.
2726 For floating-point equality comparisons, CCFPEQmode should be used.
2727 VOIDmode should be used in all other cases.
2729 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2730 possible, to allow for more combinations. */
2732 #define SELECT_CC_MODE(OP,X,Y) ix86_cc_mode (OP, X, Y)
2734 /* Return non-zero if MODE implies a floating point inequality can be
2737 #define REVERSIBLE_CC_MODE(MODE) 1
2739 /* A C expression whose value is reversed condition code of the CODE for
2740 comparison done in CC_MODE mode. */
2741 #define REVERSE_CONDITION(CODE, MODE) \
2742 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2743 : reverse_condition_maybe_unordered (CODE))
2746 /* Control the assembler format that we output, to the extent
2747 this does not vary between assemblers. */
2749 /* How to refer to registers in assembler output.
2750 This sequence is indexed by compiler's hard-register-number (see above). */
2752 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2753 For non floating point regs, the following are the HImode names.
2755 For float regs, the stack top is sometimes referred to as "%st(0)"
2756 instead of just "%st". PRINT_REG handles this with the "y" code. */
2758 #undef HI_REGISTER_NAMES
2759 #define HI_REGISTER_NAMES \
2760 {"ax","dx","cx","bx","si","di","bp","sp", \
2761 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2762 "flags","fpsr", "dirflag", "frame", \
2763 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2764 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2765 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2766 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2768 #define REGISTER_NAMES HI_REGISTER_NAMES
2770 /* Table of additional register names to use in user input. */
2772 #define ADDITIONAL_REGISTER_NAMES \
2773 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2774 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2775 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2776 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2777 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2778 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2779 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2780 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2782 /* Note we are omitting these since currently I don't know how
2783 to get gcc to use these, since they want the same but different
2784 number as al, and ax.
2787 #define QI_REGISTER_NAMES \
2788 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2790 /* These parallel the array above, and can be used to access bits 8:15
2791 of regs 0 through 3. */
2793 #define QI_HIGH_REGISTER_NAMES \
2794 {"ah", "dh", "ch", "bh", }
2796 /* How to renumber registers for dbx and gdb. */
2798 #define DBX_REGISTER_NUMBER(n) \
2799 (TARGET_64BIT ? dbx64_register_map[n] : dbx_register_map[n])
2801 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2802 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2803 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2805 /* Before the prologue, RA is at 0(%esp). */
2806 #define INCOMING_RETURN_ADDR_RTX \
2807 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2809 /* After the prologue, RA is at -4(AP) in the current frame. */
2810 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2812 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2813 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2815 /* PC is dbx register 8; let's use that column for RA. */
2816 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2818 /* Before the prologue, the top of the frame is at 4(%esp). */
2819 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2821 /* Describe how we implement __builtin_eh_return. */
2822 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2823 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2825 /* Select a format to encode pointers in exception handling data. CODE
2826 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2827 true if the symbol may be affected by dynamic relocations.
2829 ??? All x86 object file formats are capable of representing this.
2830 After all, the relocation needed is the same as for the call insn.
2831 Whether or not a particular assembler allows us to enter such, I
2832 guess we'll have to see. */
2833 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2834 (flag_pic ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel \
2837 /* This is how to output the definition of a user-level label named NAME,
2838 such as the label on a static function or variable NAME. */
2840 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2841 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2843 /* This is how to output an assembler line defining a `double' constant. */
2845 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2847 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2848 fprintf (FILE, "%s0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
2851 /* This is how to output a `long double' extended real constant. */
2853 #undef ASM_OUTPUT_LONG_DOUBLE
2854 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2856 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
2857 if (TARGET_128BIT_LONG_DOUBLE) \
2858 fprintf (FILE, "%s0x%lx,0x%lx,0x%lx,0x0\n", ASM_LONG, l[0], l[1], l[2]); \
2860 fprintf (FILE, "%s0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
2863 /* This is how to output an assembler line defining a `float' constant. */
2865 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2867 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2868 fprintf ((FILE), "%s0x%lx\n", ASM_LONG, l); \
2871 /* Store in OUTPUT a string (made with alloca) containing
2872 an assembler-name for a local static variable named NAME.
2873 LABELNO is an integer which is different for each call. */
2875 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2876 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2877 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2879 /* This is how to output an assembler line defining an `int' constant. */
2881 #define ASM_OUTPUT_INT(FILE,VALUE) \
2882 ( fputs (ASM_LONG, FILE), \
2883 output_addr_const (FILE,(VALUE)), \
2886 /* Likewise for `char' and `short' constants. */
2888 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2889 ( fputs (ASM_SHORT, FILE), \
2890 output_addr_const (FILE,(VALUE)), \
2893 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2894 ( fputs (ASM_BYTE_OP, FILE), \
2895 output_addr_const (FILE, (VALUE)), \
2898 /* Given that x86 natively supports unaligned data, it's reasonable to
2899 assume that all x86 assemblers don't auto-align data. Thus the
2900 unaligned output macros required by dwarf2 frame unwind information
2901 degenerate to the macros used above. */
2902 #define UNALIGNED_SHORT_ASM_OP ASM_SHORT
2903 #define UNALIGNED_INT_ASM_OP ASM_LONG
2904 #define INT_ASM_OP ASM_LONG
2906 /* This is how to output an assembler line for a numeric constant byte. */
2908 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2909 asm_fprintf ((FILE), "%s0x%x\n", ASM_BYTE_OP, (VALUE))
2911 /* This is how to output an insn to push a register on the stack.
2912 It need not be very fast code. */
2914 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2915 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2917 /* This is how to output an insn to pop a register from the stack.
2918 It need not be very fast code. */
2920 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2921 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2923 /* This is how to output an element of a case-vector that is absolute.
2926 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2927 fprintf (FILE, "%s%s%d\n", ASM_LONG, LPREFIX, VALUE)
2929 /* This is how to output an element of a case-vector that is relative.
2930 We don't use these on the 386 yet, because the ATT assembler can't do
2931 forward reference the differences.
2934 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2935 fprintf (FILE, "%s%s%d-%s%d\n",ASM_LONG, LPREFIX, VALUE, LPREFIX, REL)
2937 /* A C statement that outputs an address constant appropriate to
2938 for DWARF debugging. */
2940 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
2941 i386_dwarf_output_addr_const((FILE),(X))
2943 /* Either simplify a location expression, or return the original. */
2945 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2946 i386_simplify_dwarf_addr(X)
2948 /* Define the parentheses used to group arithmetic operations
2949 in assembler code. */
2951 #define ASM_OPEN_PAREN ""
2952 #define ASM_CLOSE_PAREN ""
2954 /* Define results of standard character escape sequences. */
2955 #define TARGET_BELL 007
2956 #define TARGET_BS 010
2957 #define TARGET_TAB 011
2958 #define TARGET_NEWLINE 012
2959 #define TARGET_VT 013
2960 #define TARGET_FF 014
2961 #define TARGET_CR 015
2963 /* Print operand X (an rtx) in assembler syntax to file FILE.
2964 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2965 Effect of various CODE letters is described in i386.c near
2966 print_operand function. */
2968 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2969 ((CODE) == '*' || (CODE) == '+')
2971 /* Print the name of a register based on its machine mode and number.
2972 If CODE is 'w', pretend the mode is HImode.
2973 If CODE is 'b', pretend the mode is QImode.
2974 If CODE is 'k', pretend the mode is SImode.
2975 If CODE is 'q', pretend the mode is DImode.
2976 If CODE is 'h', pretend the reg is the `high' byte register.
2977 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2979 #define PRINT_REG(X, CODE, FILE) \
2980 print_reg (X, CODE, FILE)
2982 #define PRINT_OPERAND(FILE, X, CODE) \
2983 print_operand (FILE, X, CODE)
2985 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2986 print_operand_address (FILE, ADDR)
2988 /* Print the name of a register for based on its machine mode and number.
2989 This macro is used to print debugging output.
2990 This macro is different from PRINT_REG in that it may be used in
2991 programs that are not linked with aux-output.o. */
2993 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2994 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2995 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2996 fprintf (FILE, "%d ", REGNO (X)); \
2997 if (REGNO (X) == FLAGS_REG) \
2998 { fputs ("flags", FILE); break; } \
2999 if (REGNO (X) == DIRFLAG_REG) \
3000 { fputs ("dirflag", FILE); break; } \
3001 if (REGNO (X) == FPSR_REG) \
3002 { fputs ("fpsr", FILE); break; } \
3003 if (REGNO (X) == ARG_POINTER_REGNUM) \
3004 { fputs ("argp", FILE); break; } \
3005 if (REGNO (X) == FRAME_POINTER_REGNUM) \
3006 { fputs ("frame", FILE); break; } \
3007 if (STACK_TOP_P (X)) \
3008 { fputs ("st(0)", FILE); break; } \
3010 { fputs (hi_name[REGNO(X)], FILE); break; } \
3011 if (REX_INT_REG_P (X)) \
3013 switch (GET_MODE_SIZE (GET_MODE (X))) \
3017 fprintf (FILE, "r%i", REGNO (X) \
3018 - FIRST_REX_INT_REG + 8); \
3021 fprintf (FILE, "r%id", REGNO (X) \
3022 - FIRST_REX_INT_REG + 8); \
3025 fprintf (FILE, "r%iw", REGNO (X) \
3026 - FIRST_REX_INT_REG + 8); \
3029 fprintf (FILE, "r%ib", REGNO (X) \
3030 - FIRST_REX_INT_REG + 8); \
3035 switch (GET_MODE_SIZE (GET_MODE (X))) \
3038 fputs ("r", FILE); \
3039 fputs (hi_name[REGNO (X)], FILE); \
3042 fputs ("e", FILE); \
3044 fputs (hi_name[REGNO (X)], FILE); \
3047 fputs (qi_name[REGNO (X)], FILE); \
3052 /* a letter which is not needed by the normal asm syntax, which
3053 we can use for operand syntax in the extended asm */
3055 #define ASM_OPERAND_LETTER '#'
3056 #define RET return ""
3057 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
3059 /* Define the codes that are matched by predicates in i386.c. */
3061 #define PREDICATE_CODES \
3062 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3063 SYMBOL_REF, LABEL_REF, CONST}}, \
3064 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3065 SYMBOL_REF, LABEL_REF, CONST}}, \
3066 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3067 SYMBOL_REF, LABEL_REF, CONST}}, \
3068 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3069 SYMBOL_REF, LABEL_REF, CONST}}, \
3070 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3071 SYMBOL_REF, LABEL_REF, CONST}}, \
3072 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3073 SYMBOL_REF, LABEL_REF, CONST}}, \
3074 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3075 SYMBOL_REF, LABEL_REF}}, \
3076 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3077 {"const_int_1_operand", {CONST_INT}}, \
3078 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3079 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3080 LABEL_REF, SUBREG, REG, MEM}}, \
3081 {"pic_symbolic_operand", {CONST}}, \
3082 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3083 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3084 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3085 {"const1_operand", {CONST_INT}}, \
3086 {"const248_operand", {CONST_INT}}, \
3087 {"incdec_operand", {CONST_INT}}, \
3088 {"mmx_reg_operand", {REG}}, \
3089 {"reg_no_sp_operand", {SUBREG, REG}}, \
3090 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3091 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3092 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3093 {"q_regs_operand", {SUBREG, REG}}, \
3094 {"non_q_regs_operand", {SUBREG, REG}}, \
3095 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3096 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3097 GE, UNGE, LTGT, UNEQ}}, \
3098 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3099 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3101 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3102 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3103 UNGE, UNGT, LTGT, UNEQ }}, \
3104 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3105 {"ext_register_operand", {SUBREG, REG}}, \
3106 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3107 {"mult_operator", {MULT}}, \
3108 {"div_operator", {DIV}}, \
3109 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3110 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3111 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3112 LSHIFTRT, ROTATERT}}, \
3113 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3114 {"memory_displacement_operand", {MEM}}, \
3115 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3116 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3117 {"long_memory_operand", {MEM}},
3119 /* A list of predicates that do special things with modes, and so
3120 should not elicit warnings for VOIDmode match_operand. */
3122 #define SPECIAL_MODE_PREDICATES \
3123 "ext_register_operand",
3125 /* CM_32 is used by 32bit ABI
3126 CM_SMALL is small model assuming that all code and data fits in the first
3127 31bits of address space.
3128 CM_KERNEL is model assuming that all code and data fits in the negative
3129 31bits of address space.
3130 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3131 space. Size of data is unlimited.
3132 CM_LARGE is model making no assumptions about size of particular sections.
3134 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3135 tables first in 31bits of address space.
3146 /* Size of the RED_ZONE area. */
3147 #define RED_ZONE_SIZE 128
3148 /* Reserved area of the red zone for temporaries. */
3149 #define RED_ZONE_RESERVE 8
3150 /* Valud of -mcmodel specified by user. */
3151 extern const char *ix86_cmodel_string;
3152 extern enum cmodel ix86_cmodel;
3154 /* Variables in i386.c */
3155 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3156 extern const char *ix86_arch_string; /* for -march=<xxx> */
3157 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3158 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3159 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3160 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3161 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3162 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3163 extern int ix86_regparm; /* ix86_regparm_string as a number */
3164 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3165 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3166 extern const char * const hi_reg_name[]; /* names for 16 bit regs */
3167 extern const char * const qi_reg_name[]; /* names for 8 bit regs (low) */
3168 extern const char * const qi_high_reg_name[]; /* names for 8 bit regs (high) */
3169 extern enum reg_class const regclass_map[]; /* smalled class containing REGNO */
3170 extern struct rtx_def *ix86_compare_op0; /* operand 0 for comparisons */
3171 extern struct rtx_def *ix86_compare_op1; /* operand 1 for comparisons */
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