1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
89 extern const struct processor_costs *ix86_cost;
91 /* Macros used in the machine description to test the flags. */
93 /* configure can arrange to make this 2, to force a 486. */
95 #ifndef TARGET_CPU_DEFAULT
96 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
99 #ifndef TARGET_FPMATH_DEFAULT
100 #define TARGET_FPMATH_DEFAULT \
101 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
104 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
106 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
107 compile-time constant. */
111 #define TARGET_64BIT 1
113 #define TARGET_64BIT 0
116 #ifndef TARGET_BI_ARCH
118 #if TARGET_64BIT_DEFAULT
119 #define TARGET_64BIT 1
121 #define TARGET_64BIT 0
126 #define HAS_LONG_COND_BRANCH 1
127 #define HAS_LONG_UNCOND_BRANCH 1
129 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
130 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
131 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
132 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
133 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
134 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
135 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
136 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
137 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
138 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
139 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
140 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
141 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
143 #define TUNEMASK (1 << ix86_tune)
144 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
145 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
146 extern const int x86_branch_hints, x86_unroll_strlen;
147 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
148 extern const int x86_use_himode_fiop, x86_use_simode_fiop;
149 extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
150 extern const int x86_read_modify, x86_split_long_moves;
151 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
152 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
153 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
154 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
155 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
156 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
157 extern const int x86_epilogue_using_move, x86_decompose_lea;
158 extern const int x86_arch_always_fancy_math_387, x86_shift1;
159 extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
160 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
161 extern const int x86_use_ffreep;
162 extern const int x86_inter_unit_moves, x86_schedule;
163 extern const int x86_use_bt;
164 extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
165 extern const int x86_use_incdec;
166 extern const int x86_pad_returns;
167 extern const int x86_partial_flag_reg_stall;
168 extern int x86_prefetch_sse;
170 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
171 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
172 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
173 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
174 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
175 /* For sane SSE instruction set generation we need fcomi instruction. It is
176 safe to enable all CMOVE instructions. */
177 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
178 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
179 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
180 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
181 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
182 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
183 #define TARGET_MOVX (x86_movx & TUNEMASK)
184 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
185 #define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
186 #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
187 #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
188 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
189 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
190 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
191 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
192 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
193 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
194 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
195 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
196 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
197 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
198 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
199 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
200 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
201 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
202 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
203 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
204 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
205 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
206 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
207 (x86_sse_partial_reg_dependency & TUNEMASK)
208 #define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
209 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
210 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
211 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
212 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
213 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
214 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
215 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
216 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
217 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
218 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
219 #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
220 #define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
221 #define TARGET_USE_BT (x86_use_bt & TUNEMASK)
222 #define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK)
223 #define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK)
225 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
227 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
228 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
229 && (ix86_fpmath & FPMATH_387))
231 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
232 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
233 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
234 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
236 #define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
237 #define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
238 #define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch))
239 #define TARGET_XADD (x86_xadd & (1 << ix86_arch))
241 #ifndef TARGET_64BIT_DEFAULT
242 #define TARGET_64BIT_DEFAULT 0
244 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
245 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
248 /* Once GDB has been enhanced to deal with functions without frame
249 pointers, we can change this to allow for elimination of
250 the frame pointer in leaf functions. */
251 #define TARGET_DEFAULT 0
253 /* This is not really a target flag, but is done this way so that
254 it's analogous to similar code for Mach-O on PowerPC. darwin.h
255 redefines this to 1. */
256 #define TARGET_MACHO 0
258 /* Subtargets may reset this to 1 in order to enable 96-bit long double
259 with the rounding mode forced to 53 bits. */
260 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
262 /* Sometimes certain combinations of command options do not make
263 sense on a particular target machine. You can define a macro
264 `OVERRIDE_OPTIONS' to take account of this. This macro, if
265 defined, is executed once just after all the command options have
268 Don't use this macro to turn on various extra optimizations for
269 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
271 #define OVERRIDE_OPTIONS override_options ()
273 /* Define this to change the optimizations performed by default. */
274 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
275 optimization_options ((LEVEL), (SIZE))
277 /* -march=native handling only makes sense with compiler running on
278 an x86 or x86_64 chip. If changing this condition, also change
279 the condition in driver-i386.c. */
280 #if defined(__i386__) || defined(__x86_64__)
281 /* In driver-i386.c. */
282 extern const char *host_detect_local_cpu (int argc, const char **argv);
283 #define EXTRA_SPEC_FUNCTIONS \
284 { "local_cpu_detect", host_detect_local_cpu },
285 #define HAVE_LOCAL_CPU_DETECT
288 /* Support for configure-time defaults of some command line options.
289 The order here is important so that -march doesn't squash the
290 tune or cpu values. */
291 #define OPTION_DEFAULT_SPECS \
292 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
293 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
294 {"arch", "%{!march=*:-march=%(VALUE)}"}
296 /* Specs for the compiler proper */
299 #define CC1_CPU_SPEC_1 "\
302 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
304 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
305 %{mpentium:-mtune=pentium \
306 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
307 %{mpentiumpro:-mtune=pentiumpro \
308 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
310 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
312 %{mintel-syntax:-masm=intel \
313 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
314 %{mno-intel-syntax:-masm=att \
315 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
317 #ifndef HAVE_LOCAL_CPU_DETECT
318 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
320 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
321 "%{march=native:%<march=native %:local_cpu_detect(arch)} \
322 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
326 /* Target CPU builtins. */
327 #define TARGET_CPU_CPP_BUILTINS() \
330 size_t arch_len = strlen (ix86_arch_string); \
331 size_t tune_len = strlen (ix86_tune_string); \
332 int last_arch_char = ix86_arch_string[arch_len - 1]; \
333 int last_tune_char = ix86_tune_string[tune_len - 1]; \
337 builtin_assert ("cpu=x86_64"); \
338 builtin_assert ("machine=x86_64"); \
339 builtin_define ("__amd64"); \
340 builtin_define ("__amd64__"); \
341 builtin_define ("__x86_64"); \
342 builtin_define ("__x86_64__"); \
346 builtin_assert ("cpu=i386"); \
347 builtin_assert ("machine=i386"); \
348 builtin_define_std ("i386"); \
351 /* Built-ins based on -mtune= (or -march= if no \
354 builtin_define ("__tune_i386__"); \
355 else if (TARGET_486) \
356 builtin_define ("__tune_i486__"); \
357 else if (TARGET_PENTIUM) \
359 builtin_define ("__tune_i586__"); \
360 builtin_define ("__tune_pentium__"); \
361 if (last_tune_char == 'x') \
362 builtin_define ("__tune_pentium_mmx__"); \
364 else if (TARGET_PENTIUMPRO) \
366 builtin_define ("__tune_i686__"); \
367 builtin_define ("__tune_pentiumpro__"); \
368 switch (last_tune_char) \
371 builtin_define ("__tune_pentium3__"); \
374 builtin_define ("__tune_pentium2__"); \
378 else if (TARGET_K6) \
380 builtin_define ("__tune_k6__"); \
381 if (last_tune_char == '2') \
382 builtin_define ("__tune_k6_2__"); \
383 else if (last_tune_char == '3') \
384 builtin_define ("__tune_k6_3__"); \
386 else if (TARGET_ATHLON) \
388 builtin_define ("__tune_athlon__"); \
389 /* Only plain "athlon" lacks SSE. */ \
390 if (last_tune_char != 'n') \
391 builtin_define ("__tune_athlon_sse__"); \
393 else if (TARGET_K8) \
394 builtin_define ("__tune_k8__"); \
395 else if (TARGET_PENTIUM4) \
396 builtin_define ("__tune_pentium4__"); \
397 else if (TARGET_NOCONA) \
398 builtin_define ("__tune_nocona__"); \
401 builtin_define ("__MMX__"); \
403 builtin_define ("__3dNOW__"); \
404 if (TARGET_3DNOW_A) \
405 builtin_define ("__3dNOW_A__"); \
407 builtin_define ("__SSE__"); \
409 builtin_define ("__SSE2__"); \
411 builtin_define ("__SSE3__"); \
412 if (TARGET_SSE_MATH && TARGET_SSE) \
413 builtin_define ("__SSE_MATH__"); \
414 if (TARGET_SSE_MATH && TARGET_SSE2) \
415 builtin_define ("__SSE2_MATH__"); \
417 /* Built-ins based on -march=. */ \
418 if (ix86_arch == PROCESSOR_I486) \
420 builtin_define ("__i486"); \
421 builtin_define ("__i486__"); \
423 else if (ix86_arch == PROCESSOR_PENTIUM) \
425 builtin_define ("__i586"); \
426 builtin_define ("__i586__"); \
427 builtin_define ("__pentium"); \
428 builtin_define ("__pentium__"); \
429 if (last_arch_char == 'x') \
430 builtin_define ("__pentium_mmx__"); \
432 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
434 builtin_define ("__i686"); \
435 builtin_define ("__i686__"); \
436 builtin_define ("__pentiumpro"); \
437 builtin_define ("__pentiumpro__"); \
439 else if (ix86_arch == PROCESSOR_K6) \
442 builtin_define ("__k6"); \
443 builtin_define ("__k6__"); \
444 if (last_arch_char == '2') \
445 builtin_define ("__k6_2__"); \
446 else if (last_arch_char == '3') \
447 builtin_define ("__k6_3__"); \
449 else if (ix86_arch == PROCESSOR_ATHLON) \
451 builtin_define ("__athlon"); \
452 builtin_define ("__athlon__"); \
453 /* Only plain "athlon" lacks SSE. */ \
454 if (last_arch_char != 'n') \
455 builtin_define ("__athlon_sse__"); \
457 else if (ix86_arch == PROCESSOR_K8) \
459 builtin_define ("__k8"); \
460 builtin_define ("__k8__"); \
462 else if (ix86_arch == PROCESSOR_PENTIUM4) \
464 builtin_define ("__pentium4"); \
465 builtin_define ("__pentium4__"); \
467 else if (ix86_arch == PROCESSOR_NOCONA) \
469 builtin_define ("__nocona"); \
470 builtin_define ("__nocona__"); \
475 #define TARGET_CPU_DEFAULT_i386 0
476 #define TARGET_CPU_DEFAULT_i486 1
477 #define TARGET_CPU_DEFAULT_pentium 2
478 #define TARGET_CPU_DEFAULT_pentium_mmx 3
479 #define TARGET_CPU_DEFAULT_pentiumpro 4
480 #define TARGET_CPU_DEFAULT_pentium2 5
481 #define TARGET_CPU_DEFAULT_pentium3 6
482 #define TARGET_CPU_DEFAULT_pentium4 7
483 #define TARGET_CPU_DEFAULT_k6 8
484 #define TARGET_CPU_DEFAULT_k6_2 9
485 #define TARGET_CPU_DEFAULT_k6_3 10
486 #define TARGET_CPU_DEFAULT_athlon 11
487 #define TARGET_CPU_DEFAULT_athlon_sse 12
488 #define TARGET_CPU_DEFAULT_k8 13
489 #define TARGET_CPU_DEFAULT_pentium_m 14
490 #define TARGET_CPU_DEFAULT_prescott 15
491 #define TARGET_CPU_DEFAULT_nocona 16
492 #define TARGET_CPU_DEFAULT_generic 17
494 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
495 "pentiumpro", "pentium2", "pentium3", \
496 "pentium4", "k6", "k6-2", "k6-3",\
497 "athlon", "athlon-4", "k8", \
498 "pentium-m", "prescott", "nocona", \
502 #define CC1_SPEC "%(cc1_cpu) "
505 /* This macro defines names of additional specifications to put in the
506 specs that can be used in various specifications like CC1_SPEC. Its
507 definition is an initializer with a subgrouping for each command option.
509 Each subgrouping contains a string constant, that defines the
510 specification name, and a string constant that used by the GCC driver
513 Do not define this macro if it does not need to do anything. */
515 #ifndef SUBTARGET_EXTRA_SPECS
516 #define SUBTARGET_EXTRA_SPECS
519 #define EXTRA_SPECS \
520 { "cc1_cpu", CC1_CPU_SPEC }, \
521 SUBTARGET_EXTRA_SPECS
523 /* target machine storage layout */
525 #define LONG_DOUBLE_TYPE_SIZE 80
527 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
528 FPU, assume that the fpcw is set to extended precision; when using
529 only SSE, rounding is correct; when using both SSE and the FPU,
530 the rounding precision is indeterminate, since either may be chosen
531 apparently at random. */
532 #define TARGET_FLT_EVAL_METHOD \
533 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
535 #define SHORT_TYPE_SIZE 16
536 #define INT_TYPE_SIZE 32
537 #define FLOAT_TYPE_SIZE 32
538 #define LONG_TYPE_SIZE BITS_PER_WORD
539 #define DOUBLE_TYPE_SIZE 64
540 #define LONG_LONG_TYPE_SIZE 64
542 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
543 #define MAX_BITS_PER_WORD 64
545 #define MAX_BITS_PER_WORD 32
548 /* Define this if most significant byte of a word is the lowest numbered. */
549 /* That is true on the 80386. */
551 #define BITS_BIG_ENDIAN 0
553 /* Define this if most significant byte of a word is the lowest numbered. */
554 /* That is not true on the 80386. */
555 #define BYTES_BIG_ENDIAN 0
557 /* Define this if most significant word of a multiword number is the lowest
559 /* Not true for 80386 */
560 #define WORDS_BIG_ENDIAN 0
562 /* Width of a word, in units (bytes). */
563 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
565 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
567 #define MIN_UNITS_PER_WORD 4
570 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
571 #define PARM_BOUNDARY BITS_PER_WORD
573 /* Boundary (in *bits*) on which stack pointer should be aligned. */
574 #define STACK_BOUNDARY BITS_PER_WORD
576 /* Boundary (in *bits*) on which the stack pointer prefers to be
577 aligned; the compiler cannot rely on having this alignment. */
578 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
580 /* As of July 2001, many runtimes do not align the stack properly when
581 entering main. This causes expand_main_function to forcibly align
582 the stack, which results in aligned frames for functions called from
583 main, though it does nothing for the alignment of main itself. */
584 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
585 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
587 /* Minimum allocation boundary for the code of a function. */
588 #define FUNCTION_BOUNDARY 8
590 /* C++ stores the virtual bit in the lowest bit of function pointers. */
591 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
593 /* Alignment of field after `int : 0' in a structure. */
595 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
597 /* Minimum size in bits of the largest boundary to which any
598 and all fundamental data types supported by the hardware
599 might need to be aligned. No data type wants to be aligned
602 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
603 and Pentium Pro XFmode values at 128 bit boundaries. */
605 #define BIGGEST_ALIGNMENT 128
607 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
608 #define ALIGN_MODE_128(MODE) \
609 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
611 /* The published ABIs say that doubles should be aligned on word
612 boundaries, so lower the alignment for structure fields unless
613 -malign-double is set. */
615 /* ??? Blah -- this macro is used directly by libobjc. Since it
616 supports no vector modes, cut out the complexity and fall back
617 on BIGGEST_FIELD_ALIGNMENT. */
618 #ifdef IN_TARGET_LIBS
620 #define BIGGEST_FIELD_ALIGNMENT 128
622 #define BIGGEST_FIELD_ALIGNMENT 32
625 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
626 x86_field_alignment (FIELD, COMPUTED)
629 /* If defined, a C expression to compute the alignment given to a
630 constant that is being placed in memory. EXP is the constant
631 and ALIGN is the alignment that the object would ordinarily have.
632 The value of this macro is used instead of that alignment to align
635 If this macro is not defined, then ALIGN is used.
637 The typical use of this macro is to increase alignment for string
638 constants to be word aligned so that `strcpy' calls that copy
639 constants can be done inline. */
641 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
643 /* If defined, a C expression to compute the alignment for a static
644 variable. TYPE is the data type, and ALIGN is the alignment that
645 the object would ordinarily have. The value of this macro is used
646 instead of that alignment to align the object.
648 If this macro is not defined, then ALIGN is used.
650 One use of this macro is to increase alignment of medium-size
651 data to make it all fit in fewer cache lines. Another is to
652 cause character arrays to be word-aligned so that `strcpy' calls
653 that copy constants to character arrays can be done inline. */
655 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
657 /* If defined, a C expression to compute the alignment for a local
658 variable. TYPE is the data type, and ALIGN is the alignment that
659 the object would ordinarily have. The value of this macro is used
660 instead of that alignment to align the object.
662 If this macro is not defined, then ALIGN is used.
664 One use of this macro is to increase alignment of medium-size
665 data to make it all fit in fewer cache lines. */
667 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
669 /* If defined, a C expression that gives the alignment boundary, in
670 bits, of an argument with the specified mode and type. If it is
671 not defined, `PARM_BOUNDARY' is used for all arguments. */
673 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
674 ix86_function_arg_boundary ((MODE), (TYPE))
676 /* Set this nonzero if move instructions will actually fail to work
677 when given unaligned data. */
678 #define STRICT_ALIGNMENT 0
680 /* If bit field type is int, don't let it cross an int,
681 and give entire struct the alignment of an int. */
682 /* Required on the 386 since it doesn't have bit-field insns. */
683 #define PCC_BITFIELD_TYPE_MATTERS 1
685 /* Standard register usage. */
687 /* This processor has special stack-like registers. See reg-stack.c
691 #define IS_STACK_MODE(MODE) \
692 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
693 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
696 /* Number of actual hardware registers.
697 The hardware registers are assigned numbers for the compiler
698 from 0 to just below FIRST_PSEUDO_REGISTER.
699 All registers that the compiler knows about must be given numbers,
700 even those that are not normally considered general registers.
702 In the 80386 we give the 8 general purpose registers the numbers 0-7.
703 We number the floating point registers 8-15.
704 Note that registers 0-7 can be accessed as a short or int,
705 while only 0-3 may be used with byte `mov' instructions.
707 Reg 16 does not correspond to any hardware register, but instead
708 appears in the RTL as an argument pointer prior to reload, and is
709 eliminated during reloading in favor of either the stack or frame
712 #define FIRST_PSEUDO_REGISTER 53
714 /* Number of hardware registers that go into the DWARF-2 unwind info.
715 If not defined, equals FIRST_PSEUDO_REGISTER. */
717 #define DWARF_FRAME_REGISTERS 17
719 /* 1 for registers that have pervasive standard uses
720 and are not available for the register allocator.
721 On the 80386, the stack pointer is such, as is the arg pointer.
723 The value is zero if the register is not fixed on either 32 or
724 64 bit targets, one if the register if fixed on both 32 and 64
725 bit targets, two if it is only fixed on 32bit targets and three
726 if its only fixed on 64bit targets.
727 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
729 #define FIXED_REGISTERS \
730 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
731 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
732 /*arg,flags,fpsr,dir,frame*/ \
734 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
735 0, 0, 0, 0, 0, 0, 0, 0, \
736 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
737 0, 0, 0, 0, 0, 0, 0, 0, \
738 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
739 2, 2, 2, 2, 2, 2, 2, 2, \
740 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
741 2, 2, 2, 2, 2, 2, 2, 2}
744 /* 1 for registers not available across function calls.
745 These must include the FIXED_REGISTERS and also any
746 registers that can be used without being saved.
747 The latter must include the registers where values are returned
748 and the register where structure-value addresses are passed.
749 Aside from that, you can include as many other registers as you like.
751 The value is zero if the register is not call used on either 32 or
752 64 bit targets, one if the register if call used on both 32 and 64
753 bit targets, two if it is only call used on 32bit targets and three
754 if its only call used on 64bit targets.
755 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
757 #define CALL_USED_REGISTERS \
758 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
759 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
760 /*arg,flags,fpsr,dir,frame*/ \
762 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
763 1, 1, 1, 1, 1, 1, 1, 1, \
764 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
765 1, 1, 1, 1, 1, 1, 1, 1, \
766 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
767 1, 1, 1, 1, 2, 2, 2, 2, \
768 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
769 1, 1, 1, 1, 1, 1, 1, 1} \
771 /* Order in which to allocate registers. Each register must be
772 listed once, even those in FIXED_REGISTERS. List frame pointer
773 late and fixed registers last. Note that, in general, we prefer
774 registers listed in CALL_USED_REGISTERS, keeping the others
775 available for storage of persistent values.
777 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
778 so this is just empty initializer for array. */
780 #define REG_ALLOC_ORDER \
781 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
782 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
783 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
786 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
787 to be rearranged based on a particular function. When using sse math,
788 we want to allocate SSE before x87 registers and vice vera. */
790 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
793 /* Macro to conditionally modify fixed_regs/call_used_regs. */
794 #define CONDITIONAL_REGISTER_USAGE \
797 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
799 if (fixed_regs[i] > 1) \
800 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
801 if (call_used_regs[i] > 1) \
802 call_used_regs[i] = (call_used_regs[i] \
803 == (TARGET_64BIT ? 3 : 2)); \
805 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
807 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
808 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
813 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
814 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
815 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
820 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
821 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
822 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
824 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
828 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
829 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
830 if (TEST_HARD_REG_BIT (x, i)) \
831 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
833 if (! TARGET_64BIT) \
836 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
838 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
843 /* Return number of consecutive hard regs needed starting at reg REGNO
844 to hold something of mode MODE.
845 This is ordinarily the length in words of a value of mode MODE
846 but can be less for certain modes in special long registers.
848 Actually there are no two word move instructions for consecutive
849 registers. And only registers 0-3 may have mov byte instructions
853 #define HARD_REGNO_NREGS(REGNO, MODE) \
854 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
855 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
856 : ((MODE) == XFmode \
857 ? (TARGET_64BIT ? 2 : 3) \
859 ? (TARGET_64BIT ? 4 : 6) \
860 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
862 #define VALID_SSE2_REG_MODE(MODE) \
863 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
864 || (MODE) == V2DImode || (MODE) == DFmode)
866 #define VALID_SSE_REG_MODE(MODE) \
867 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
868 || (MODE) == SFmode || (MODE) == TFmode)
870 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
871 ((MODE) == V2SFmode || (MODE) == SFmode)
873 #define VALID_MMX_REG_MODE(MODE) \
874 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
875 || (MODE) == V2SImode || (MODE) == SImode)
877 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
878 place emms and femms instructions. */
879 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
881 #define VALID_FP_MODE_P(MODE) \
882 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
883 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
885 #define VALID_INT_MODE_P(MODE) \
886 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
887 || (MODE) == DImode \
888 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
889 || (MODE) == CDImode \
890 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
891 || (MODE) == TFmode || (MODE) == TCmode)))
893 /* Return true for modes passed in SSE registers. */
894 #define SSE_REG_MODE_P(MODE) \
895 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
896 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
897 || (MODE) == V4SFmode || (MODE) == V4SImode)
899 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
901 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
902 ix86_hard_regno_mode_ok ((REGNO), (MODE))
904 /* Value is 1 if it is a good idea to tie two pseudo registers
905 when one has mode MODE1 and one has mode MODE2.
906 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
907 for any hard reg, then this must be 0 for correct output. */
909 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
911 /* It is possible to write patterns to move flags; but until someone
913 #define AVOID_CCMODE_COPIES
915 /* Specify the modes required to caller save a given hard regno.
916 We do this on i386 to prevent flags from being saved at all.
918 Kill any attempts to combine saving of modes. */
920 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
921 (CC_REGNO_P (REGNO) ? VOIDmode \
922 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
923 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
924 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
925 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
927 /* Specify the registers used for certain standard purposes.
928 The values of these macros are register numbers. */
930 /* on the 386 the pc register is %eip, and is not usable as a general
931 register. The ordinary mov instructions won't work */
932 /* #define PC_REGNUM */
934 /* Register to use for pushing function arguments. */
935 #define STACK_POINTER_REGNUM 7
937 /* Base register for access to local variables of the function. */
938 #define HARD_FRAME_POINTER_REGNUM 6
940 /* Base register for access to local variables of the function. */
941 #define FRAME_POINTER_REGNUM 20
943 /* First floating point reg */
944 #define FIRST_FLOAT_REG 8
946 /* First & last stack-like regs */
947 #define FIRST_STACK_REG FIRST_FLOAT_REG
948 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
950 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
951 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
953 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
954 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
956 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
957 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
959 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
960 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
962 /* Value should be nonzero if functions must have frame pointers.
963 Zero means the frame pointer need not be set up (and parms
964 may be accessed via the stack pointer) in functions that seem suitable.
965 This is computed in `reload', in reload1.c. */
966 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
968 /* Override this in other tm.h files to cope with various OS lossage
969 requiring a frame pointer. */
970 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
971 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
974 /* Make sure we can access arbitrary call frames. */
975 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
977 /* Base register for access to arguments of the function. */
978 #define ARG_POINTER_REGNUM 16
980 /* Register in which static-chain is passed to a function.
981 We do use ECX as static chain register for 32 bit ABI. On the
982 64bit ABI, ECX is an argument register, so we use R10 instead. */
983 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
985 /* Register to hold the addressing base for position independent
986 code access to data items. We don't use PIC pointer for 64bit
987 mode. Define the regnum to dummy value to prevent gcc from
988 pessimizing code dealing with EBX.
990 To avoid clobbering a call-saved register unnecessarily, we renumber
991 the pic register when possible. The change is visible after the
992 prologue has been emitted. */
994 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
996 #define PIC_OFFSET_TABLE_REGNUM \
997 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
998 || !flag_pic ? INVALID_REGNUM \
999 : reload_completed ? REGNO (pic_offset_table_rtx) \
1000 : REAL_PIC_OFFSET_TABLE_REGNUM)
1002 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1004 /* A C expression which can inhibit the returning of certain function
1005 values in registers, based on the type of value. A nonzero value
1006 says to return the function value in memory, just as large
1007 structures are always returned. Here TYPE will be a C expression
1008 of type `tree', representing the data type of the value.
1010 Note that values of mode `BLKmode' must be explicitly handled by
1011 this macro. Also, the option `-fpcc-struct-return' takes effect
1012 regardless of this macro. On most systems, it is possible to
1013 leave the macro undefined; this causes a default definition to be
1014 used, whose value is the constant 1 for `BLKmode' values, and 0
1017 Do not use this macro to indicate that structures and unions
1018 should always be returned in memory. You should instead use
1019 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1021 #define RETURN_IN_MEMORY(TYPE) \
1022 ix86_return_in_memory (TYPE)
1024 /* This is overridden by <cygwin.h>. */
1025 #define MS_AGGREGATE_RETURN 0
1027 /* This is overridden by <netware.h>. */
1028 #define KEEP_AGGREGATE_RETURN_POINTER 0
1030 /* Define the classes of registers for register constraints in the
1031 machine description. Also define ranges of constants.
1033 One of the classes must always be named ALL_REGS and include all hard regs.
1034 If there is more than one class, another class must be named NO_REGS
1035 and contain no registers.
1037 The name GENERAL_REGS must be the name of a class (or an alias for
1038 another name such as ALL_REGS). This is the class of registers
1039 that is allowed by "g" or "r" in a register constraint.
1040 Also, registers outside this class are allocated only when
1041 instructions express preferences for them.
1043 The classes must be numbered in nondecreasing order; that is,
1044 a larger-numbered class must never be contained completely
1045 in a smaller-numbered class.
1047 For any two classes, it is very desirable that there be another
1048 class that represents their union.
1050 It might seem that class BREG is unnecessary, since no useful 386
1051 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1052 and the "b" register constraint is useful in asms for syscalls.
1054 The flags and fpsr registers are in no class. */
1059 AREG, DREG, CREG, BREG, SIREG, DIREG,
1060 AD_REGS, /* %eax/%edx for DImode */
1061 Q_REGS, /* %eax %ebx %ecx %edx */
1062 NON_Q_REGS, /* %esi %edi %ebp %esp */
1063 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1064 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1065 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1066 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1076 ALL_REGS, LIM_REG_CLASSES
1079 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1081 #define INTEGER_CLASS_P(CLASS) \
1082 reg_class_subset_p ((CLASS), GENERAL_REGS)
1083 #define FLOAT_CLASS_P(CLASS) \
1084 reg_class_subset_p ((CLASS), FLOAT_REGS)
1085 #define SSE_CLASS_P(CLASS) \
1086 ((CLASS) == SSE_REGS)
1087 #define MMX_CLASS_P(CLASS) \
1088 ((CLASS) == MMX_REGS)
1089 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1090 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1091 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1092 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1093 #define MAYBE_SSE_CLASS_P(CLASS) \
1094 reg_classes_intersect_p (SSE_REGS, (CLASS))
1095 #define MAYBE_MMX_CLASS_P(CLASS) \
1096 reg_classes_intersect_p (MMX_REGS, (CLASS))
1098 #define Q_CLASS_P(CLASS) \
1099 reg_class_subset_p ((CLASS), Q_REGS)
1101 /* Give names of register classes as strings for dump file. */
1103 #define REG_CLASS_NAMES \
1105 "AREG", "DREG", "CREG", "BREG", \
1108 "Q_REGS", "NON_Q_REGS", \
1112 "FP_TOP_REG", "FP_SECOND_REG", \
1116 "FP_TOP_SSE_REGS", \
1117 "FP_SECOND_SSE_REGS", \
1121 "FLOAT_INT_SSE_REGS", \
1124 /* Define which registers fit in which classes.
1125 This is an initializer for a vector of HARD_REG_SET
1126 of length N_REG_CLASSES. */
1128 #define REG_CLASS_CONTENTS \
1130 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1131 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1132 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1133 { 0x03, 0x0 }, /* AD_REGS */ \
1134 { 0x0f, 0x0 }, /* Q_REGS */ \
1135 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1136 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1137 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1138 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1139 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1140 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1141 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1142 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1143 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1144 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1145 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1146 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1147 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1148 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1149 { 0xffffffff,0x1fffff } \
1152 /* The same information, inverted:
1153 Return the class number of the smallest class containing
1154 reg number REGNO. This could be a conditional expression
1155 or could index an array. */
1157 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1159 /* When defined, the compiler allows registers explicitly used in the
1160 rtl to be used as spill registers but prevents the compiler from
1161 extending the lifetime of these registers. */
1163 #define SMALL_REGISTER_CLASSES 1
1165 #define QI_REG_P(X) \
1166 (REG_P (X) && REGNO (X) < 4)
1168 #define GENERAL_REGNO_P(N) \
1169 ((N) < 8 || REX_INT_REGNO_P (N))
1171 #define GENERAL_REG_P(X) \
1172 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1174 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1176 #define NON_QI_REG_P(X) \
1177 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1179 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1180 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1182 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1183 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1184 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1185 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1187 #define SSE_REGNO_P(N) \
1188 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1189 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1191 #define REX_SSE_REGNO_P(N) \
1192 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1194 #define SSE_REGNO(N) \
1195 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1196 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1198 #define SSE_FLOAT_MODE_P(MODE) \
1199 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1201 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1202 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1204 #define STACK_REG_P(XOP) \
1206 REGNO (XOP) >= FIRST_STACK_REG && \
1207 REGNO (XOP) <= LAST_STACK_REG)
1209 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1211 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1213 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1214 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1216 /* The class value for index registers, and the one for base regs. */
1218 #define INDEX_REG_CLASS INDEX_REGS
1219 #define BASE_REG_CLASS GENERAL_REGS
1221 /* Place additional restrictions on the register class to use when it
1222 is necessary to be able to hold a value of mode MODE in a reload
1223 register for which class CLASS would ordinarily be used. */
1225 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1226 ((MODE) == QImode && !TARGET_64BIT \
1227 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1228 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1231 /* Given an rtx X being reloaded into a reg required to be
1232 in class CLASS, return the class of reg to actually use.
1233 In general this is just CLASS; but on some machines
1234 in some cases it is preferable to use a more restrictive class.
1235 On the 80386 series, we prevent floating constants from being
1236 reloaded into floating registers (since no move-insn can do that)
1237 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1239 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1240 QImode must go into class Q_REGS.
1241 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1242 movdf to do mem-to-mem moves through integer regs. */
1244 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1245 ix86_preferred_reload_class ((X), (CLASS))
1247 /* Discourage putting floating-point values in SSE registers unless
1248 SSE math is being used, and likewise for the 387 registers. */
1250 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1251 ix86_preferred_output_reload_class ((X), (CLASS))
1253 /* If we are copying between general and FP registers, we need a memory
1254 location. The same is true for SSE and MMX registers. */
1255 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1256 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1258 /* QImode spills from non-QI registers need a scratch. This does not
1259 happen often -- the only example so far requires an uninitialized
1262 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1263 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1264 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1267 /* Return the maximum number of consecutive registers
1268 needed to represent mode MODE in a register of class CLASS. */
1269 /* On the 80386, this is the size of MODE in words,
1270 except in the FP regs, where a single reg is always enough. */
1271 #define CLASS_MAX_NREGS(CLASS, MODE) \
1272 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1273 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1274 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1275 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1277 /* A C expression whose value is nonzero if pseudos that have been
1278 assigned to registers of class CLASS would likely be spilled
1279 because registers of CLASS are needed for spill registers.
1281 The default value of this macro returns 1 if CLASS has exactly one
1282 register and zero otherwise. On most machines, this default
1283 should be used. Only define this macro to some other expression
1284 if pseudo allocated by `local-alloc.c' end up in memory because
1285 their hard registers were needed for spill registers. If this
1286 macro returns nonzero for those classes, those pseudos will only
1287 be allocated by `global.c', which knows how to reallocate the
1288 pseudo to another register. If there would not be another
1289 register available for reallocation, you should not change the
1290 definition of this macro since the only effect of such a
1291 definition would be to slow down register allocation. */
1293 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1294 (((CLASS) == AREG) \
1295 || ((CLASS) == DREG) \
1296 || ((CLASS) == CREG) \
1297 || ((CLASS) == BREG) \
1298 || ((CLASS) == AD_REGS) \
1299 || ((CLASS) == SIREG) \
1300 || ((CLASS) == DIREG) \
1301 || ((CLASS) == FP_TOP_REG) \
1302 || ((CLASS) == FP_SECOND_REG))
1304 /* Return a class of registers that cannot change FROM mode to TO mode. */
1306 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1307 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1309 /* Stack layout; function entry, exit and calling. */
1311 /* Define this if pushing a word on the stack
1312 makes the stack pointer a smaller address. */
1313 #define STACK_GROWS_DOWNWARD
1315 /* Define this to nonzero if the nominal address of the stack frame
1316 is at the high-address end of the local variables;
1317 that is, each additional local variable allocated
1318 goes at a more negative offset in the frame. */
1319 #define FRAME_GROWS_DOWNWARD 1
1321 /* Offset within stack frame to start allocating local variables at.
1322 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1323 first local allocated. Otherwise, it is the offset to the BEGINNING
1324 of the first local allocated. */
1325 #define STARTING_FRAME_OFFSET 0
1327 /* If we generate an insn to push BYTES bytes,
1328 this says how many the stack pointer really advances by.
1329 On 386, we have pushw instruction that decrements by exactly 2 no
1330 matter what the position was, there is no pushb.
1331 But as CIE data alignment factor on this arch is -4, we need to make
1332 sure all stack pointer adjustments are in multiple of 4.
1334 For 64bit ABI we round up to 8 bytes.
1337 #define PUSH_ROUNDING(BYTES) \
1339 ? (((BYTES) + 7) & (-8)) \
1340 : (((BYTES) + 3) & (-4)))
1342 /* If defined, the maximum amount of space required for outgoing arguments will
1343 be computed and placed into the variable
1344 `current_function_outgoing_args_size'. No space will be pushed onto the
1345 stack for each call; instead, the function prologue should increase the stack
1346 frame size by this amount. */
1348 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1350 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1351 instructions to pass outgoing arguments. */
1353 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1355 /* We want the stack and args grow in opposite directions, even if
1357 #define PUSH_ARGS_REVERSED 1
1359 /* Offset of first parameter from the argument pointer register value. */
1360 #define FIRST_PARM_OFFSET(FNDECL) 0
1362 /* Define this macro if functions should assume that stack space has been
1363 allocated for arguments even when their values are passed in registers.
1365 The value of this macro is the size, in bytes, of the area reserved for
1366 arguments passed in registers for the function represented by FNDECL.
1368 This space can be allocated by the caller, or be a part of the
1369 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1371 #define REG_PARM_STACK_SPACE(FNDECL) 0
1373 /* Value is the number of bytes of arguments automatically
1374 popped when returning from a subroutine call.
1375 FUNDECL is the declaration node of the function (as a tree),
1376 FUNTYPE is the data type of the function (as a tree),
1377 or for a library call it is an identifier node for the subroutine name.
1378 SIZE is the number of bytes of arguments passed on the stack.
1380 On the 80386, the RTD insn may be used to pop them if the number
1381 of args is fixed, but if the number is variable then the caller
1382 must pop them all. RTD can't be used for library calls now
1383 because the library is compiled with the Unix compiler.
1384 Use of RTD is a selectable option, since it is incompatible with
1385 standard Unix calling sequences. If the option is not selected,
1386 the caller must always pop the args.
1388 The attribute stdcall is equivalent to RTD on a per module basis. */
1390 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1391 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1393 #define FUNCTION_VALUE_REGNO_P(N) \
1394 ix86_function_value_regno_p (N)
1396 /* Define how to find the value returned by a library function
1397 assuming the value has mode MODE. */
1399 #define LIBCALL_VALUE(MODE) \
1400 ix86_libcall_value (MODE)
1402 /* Define the size of the result block used for communication between
1403 untyped_call and untyped_return. The block contains a DImode value
1404 followed by the block used by fnsave and frstor. */
1406 #define APPLY_RESULT_SIZE (8+108)
1408 /* 1 if N is a possible register number for function argument passing. */
1409 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1411 /* Define a data type for recording info about an argument list
1412 during the scan of that argument list. This data type should
1413 hold all necessary information about the function itself
1414 and about the args processed so far, enough to enable macros
1415 such as FUNCTION_ARG to determine where the next arg should go. */
1417 typedef struct ix86_args {
1418 int words; /* # words passed so far */
1419 int nregs; /* # registers available for passing */
1420 int regno; /* next available register number */
1421 int fastcall; /* fastcall calling convention is used */
1422 int sse_words; /* # sse words passed so far */
1423 int sse_nregs; /* # sse registers available for passing */
1424 int warn_sse; /* True when we want to warn about SSE ABI. */
1425 int warn_mmx; /* True when we want to warn about MMX ABI. */
1426 int sse_regno; /* next available sse register number */
1427 int mmx_words; /* # mmx words passed so far */
1428 int mmx_nregs; /* # mmx registers available for passing */
1429 int mmx_regno; /* next available mmx register number */
1430 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1431 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1432 be passed in SSE registers. Otherwise 0. */
1435 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1436 for a call to a function whose data type is FNTYPE.
1437 For a library call, FNTYPE is 0. */
1439 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1440 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1442 /* Update the data in CUM to advance over an argument
1443 of mode MODE and data type TYPE.
1444 (TYPE is null for libcalls where that information may not be available.) */
1446 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1447 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1449 /* Define where to put the arguments to a function.
1450 Value is zero to push the argument on the stack,
1451 or a hard register in which to store the argument.
1453 MODE is the argument's machine mode.
1454 TYPE is the data type of the argument (as a tree).
1455 This is null for libcalls where that information may
1457 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1458 the preceding args and about the function being called.
1459 NAMED is nonzero if this argument is a named parameter
1460 (otherwise it is an extra parameter matching an ellipsis). */
1462 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1463 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1465 /* Implement `va_start' for varargs and stdarg. */
1466 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1467 ix86_va_start (VALIST, NEXTARG)
1469 #define TARGET_ASM_FILE_END ix86_file_end
1470 #define NEED_INDICATE_EXEC_STACK 0
1472 /* Output assembler code to FILE to increment profiler label # LABELNO
1473 for profiling a function entry. */
1475 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1477 #define MCOUNT_NAME "_mcount"
1479 #define PROFILE_COUNT_REGISTER "edx"
1481 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1482 the stack pointer does not matter. The value is tested only in
1483 functions that have frame pointers.
1484 No definition is equivalent to always zero. */
1485 /* Note on the 386 it might be more efficient not to define this since
1486 we have to restore it ourselves from the frame pointer, in order to
1489 #define EXIT_IGNORE_STACK 1
1491 /* Output assembler code for a block containing the constant parts
1492 of a trampoline, leaving space for the variable parts. */
1494 /* On the 386, the trampoline contains two instructions:
1497 The trampoline is generated entirely at runtime. The operand of JMP
1498 is the address of FUNCTION relative to the instruction following the
1499 JMP (which is 5 bytes long). */
1501 /* Length in units of the trampoline for entering a nested function. */
1503 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1505 /* Emit RTL insns to initialize the variable parts of a trampoline.
1506 FNADDR is an RTX for the address of the function's pure code.
1507 CXT is an RTX for the static chain value for the function. */
1509 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1510 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1512 /* Definitions for register eliminations.
1514 This is an array of structures. Each structure initializes one pair
1515 of eliminable registers. The "from" register number is given first,
1516 followed by "to". Eliminations of the same "from" register are listed
1517 in order of preference.
1519 There are two registers that can always be eliminated on the i386.
1520 The frame pointer and the arg pointer can be replaced by either the
1521 hard frame pointer or to the stack pointer, depending upon the
1522 circumstances. The hard frame pointer is not used before reload and
1523 so it is not eligible for elimination. */
1525 #define ELIMINABLE_REGS \
1526 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1527 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1528 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1529 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1531 /* Given FROM and TO register numbers, say whether this elimination is
1532 allowed. Frame pointer elimination is automatically handled.
1534 All other eliminations are valid. */
1536 #define CAN_ELIMINATE(FROM, TO) \
1537 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1539 /* Define the offset between two registers, one to be eliminated, and the other
1540 its replacement, at the start of a routine. */
1542 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1543 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1545 /* Addressing modes, and classification of registers for them. */
1547 /* Macros to check register numbers against specific register classes. */
1549 /* These assume that REGNO is a hard or pseudo reg number.
1550 They give nonzero only if REGNO is a hard reg of the suitable class
1551 or a pseudo reg currently allocated to a suitable hard reg.
1552 Since they use reg_renumber, they are safe only once reg_renumber
1553 has been allocated, which happens in local-alloc.c. */
1555 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1556 ((REGNO) < STACK_POINTER_REGNUM \
1557 || (REGNO >= FIRST_REX_INT_REG \
1558 && (REGNO) <= LAST_REX_INT_REG) \
1559 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1560 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1561 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1563 #define REGNO_OK_FOR_BASE_P(REGNO) \
1564 ((REGNO) <= STACK_POINTER_REGNUM \
1565 || (REGNO) == ARG_POINTER_REGNUM \
1566 || (REGNO) == FRAME_POINTER_REGNUM \
1567 || (REGNO >= FIRST_REX_INT_REG \
1568 && (REGNO) <= LAST_REX_INT_REG) \
1569 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1570 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1571 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1573 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1574 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1575 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1576 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1578 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1579 and check its validity for a certain class.
1580 We have two alternate definitions for each of them.
1581 The usual definition accepts all pseudo regs; the other rejects
1582 them unless they have been allocated suitable hard regs.
1583 The symbol REG_OK_STRICT causes the latter definition to be used.
1585 Most source files want to accept pseudo regs in the hope that
1586 they will get allocated to the class that the insn wants them to be in.
1587 Source files for reload pass need to be strict.
1588 After reload, it makes no difference, since pseudo regs have
1589 been eliminated by then. */
1592 /* Non strict versions, pseudos are ok. */
1593 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1594 (REGNO (X) < STACK_POINTER_REGNUM \
1595 || (REGNO (X) >= FIRST_REX_INT_REG \
1596 && REGNO (X) <= LAST_REX_INT_REG) \
1597 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1599 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1600 (REGNO (X) <= STACK_POINTER_REGNUM \
1601 || REGNO (X) == ARG_POINTER_REGNUM \
1602 || REGNO (X) == FRAME_POINTER_REGNUM \
1603 || (REGNO (X) >= FIRST_REX_INT_REG \
1604 && REGNO (X) <= LAST_REX_INT_REG) \
1605 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1607 /* Strict versions, hard registers only */
1608 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1609 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1611 #ifndef REG_OK_STRICT
1612 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1613 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1616 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1617 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1620 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1621 that is a valid memory address for an instruction.
1622 The MODE argument is the machine mode for the MEM expression
1623 that wants to use this address.
1625 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1626 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1628 See legitimize_pic_address in i386.c for details as to what
1629 constitutes a legitimate address when -fpic is used. */
1631 #define MAX_REGS_PER_ADDRESS 2
1633 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1635 /* Nonzero if the constant value X is a legitimate general operand.
1636 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1638 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1640 #ifdef REG_OK_STRICT
1641 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1643 if (legitimate_address_p ((MODE), (X), 1)) \
1648 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1650 if (legitimate_address_p ((MODE), (X), 0)) \
1656 /* If defined, a C expression to determine the base term of address X.
1657 This macro is used in only one place: `find_base_term' in alias.c.
1659 It is always safe for this macro to not be defined. It exists so
1660 that alias analysis can understand machine-dependent addresses.
1662 The typical use of this macro is to handle addresses containing
1663 a label_ref or symbol_ref within an UNSPEC. */
1665 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1667 /* Try machine-dependent ways of modifying an illegitimate address
1668 to be legitimate. If we find one, return the new, valid address.
1669 This macro is used in only one place: `memory_address' in explow.c.
1671 OLDX is the address as it was before break_out_memory_refs was called.
1672 In some cases it is useful to look at this to decide what needs to be done.
1674 MODE and WIN are passed so that this macro can use
1675 GO_IF_LEGITIMATE_ADDRESS.
1677 It is always safe for this macro to do nothing. It exists to recognize
1678 opportunities to optimize the output.
1680 For the 80386, we handle X+REG by loading X into a register R and
1681 using R+REG. R will go in a general reg and indexing will be used.
1682 However, if REG is a broken-out memory address or multiplication,
1683 nothing needs to be done because REG can certainly go in a general reg.
1685 When -fpic is used, special handling is needed for symbolic references.
1686 See comments by legitimize_pic_address in i386.c for details. */
1688 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1690 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1691 if (memory_address_p ((MODE), (X))) \
1695 #define REWRITE_ADDRESS(X) rewrite_address (X)
1697 /* Nonzero if the constant value X is a legitimate general operand
1698 when generating PIC code. It is given that flag_pic is on and
1699 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1701 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1703 #define SYMBOLIC_CONST(X) \
1704 (GET_CODE (X) == SYMBOL_REF \
1705 || GET_CODE (X) == LABEL_REF \
1706 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1708 /* Go to LABEL if ADDR (a legitimate address expression)
1709 has an effect that depends on the machine mode it is used for.
1710 On the 80386, only postdecrement and postincrement address depend thus
1711 (the amount of decrement or increment being the length of the operand). */
1712 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1714 if (GET_CODE (ADDR) == POST_INC \
1715 || GET_CODE (ADDR) == POST_DEC) \
1719 /* Max number of args passed in registers. If this is more than 3, we will
1720 have problems with ebx (register #4), since it is a caller save register and
1721 is also used as the pic register in ELF. So for now, don't allow more than
1722 3 registers to be passed in registers. */
1724 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1726 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1728 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1731 /* Specify the machine mode that this machine uses
1732 for the index in the tablejump instruction. */
1733 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1735 /* Define this as 1 if `char' should by default be signed; else as 0. */
1736 #define DEFAULT_SIGNED_CHAR 1
1738 /* Number of bytes moved into a data cache for a single prefetch operation. */
1739 #define PREFETCH_BLOCK ix86_cost->prefetch_block
1741 /* Number of prefetch operations that can be done in parallel. */
1742 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
1744 /* Max number of bytes we can move from memory to memory
1745 in one reasonably fast instruction. */
1748 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1749 move efficiently, as opposed to MOVE_MAX which is the maximum
1750 number of bytes we can move with a single instruction. */
1751 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1753 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1754 move-instruction pairs, we will do a movmem or libcall instead.
1755 Increasing the value will always make code faster, but eventually
1756 incurs high cost in increased code size.
1758 If you don't define this, a reasonable default is used. */
1760 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1762 /* If a clear memory operation would take CLEAR_RATIO or more simple
1763 move-instruction sequences, we will do a clrmem or libcall instead. */
1765 #define CLEAR_RATIO (optimize_size ? 2 \
1766 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1768 /* Define if shifts truncate the shift count
1769 which implies one can omit a sign-extension or zero-extension
1770 of a shift count. */
1771 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1773 /* #define SHIFT_COUNT_TRUNCATED */
1775 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1776 is done just by pretending it is already truncated. */
1777 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1779 /* A macro to update M and UNSIGNEDP when an object whose type is
1780 TYPE and which has the specified mode and signedness is to be
1781 stored in a register. This macro is only called when TYPE is a
1784 On i386 it is sometimes useful to promote HImode and QImode
1785 quantities to SImode. The choice depends on target type. */
1787 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1789 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1790 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1794 /* Specify the machine mode that pointers have.
1795 After generation of rtl, the compiler makes no further distinction
1796 between pointers and any other objects of this machine mode. */
1797 #define Pmode (TARGET_64BIT ? DImode : SImode)
1799 /* A function address in a call instruction
1800 is a byte address (for indexing purposes)
1801 so give the MEM rtx a byte's mode. */
1802 #define FUNCTION_MODE QImode
1804 /* A C expression for the cost of moving data from a register in class FROM to
1805 one in class TO. The classes are expressed using the enumeration values
1806 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1807 interpreted relative to that.
1809 It is not required that the cost always equal 2 when FROM is the same as TO;
1810 on some machines it is expensive to move between registers if they are not
1811 general registers. */
1813 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1814 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1816 /* A C expression for the cost of moving data of mode M between a
1817 register and memory. A value of 2 is the default; this cost is
1818 relative to those in `REGISTER_MOVE_COST'.
1820 If moving between registers and memory is more expensive than
1821 between two registers, you should define this macro to express the
1824 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1825 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1827 /* A C expression for the cost of a branch instruction. A value of 1
1828 is the default; other values are interpreted relative to that. */
1830 #define BRANCH_COST ix86_branch_cost
1832 /* Define this macro as a C expression which is nonzero if accessing
1833 less than a word of memory (i.e. a `char' or a `short') is no
1834 faster than accessing a word of memory, i.e., if such access
1835 require more than one instruction or if there is no difference in
1836 cost between byte and (aligned) word loads.
1838 When this macro is not defined, the compiler will access a field by
1839 finding the smallest containing object; when it is defined, a
1840 fullword load will be used if alignment permits. Unless bytes
1841 accesses are faster than word accesses, using word accesses is
1842 preferable since it may eliminate subsequent memory access if
1843 subsequent accesses occur to other fields in the same word of the
1844 structure, but to different bytes. */
1846 #define SLOW_BYTE_ACCESS 0
1848 /* Nonzero if access to memory by shorts is slow and undesirable. */
1849 #define SLOW_SHORT_ACCESS 0
1851 /* Define this macro to be the value 1 if unaligned accesses have a
1852 cost many times greater than aligned accesses, for example if they
1853 are emulated in a trap handler.
1855 When this macro is nonzero, the compiler will act as if
1856 `STRICT_ALIGNMENT' were nonzero when generating code for block
1857 moves. This can cause significantly more instructions to be
1858 produced. Therefore, do not set this macro nonzero if unaligned
1859 accesses only add a cycle or two to the time for a memory access.
1861 If the value of this macro is always zero, it need not be defined. */
1863 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1865 /* Define this macro if it is as good or better to call a constant
1866 function address than to call an address kept in a register.
1868 Desirable on the 386 because a CALL with a constant address is
1869 faster than one with a register address. */
1871 #define NO_FUNCTION_CSE
1873 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1874 return the mode to be used for the comparison.
1876 For floating-point equality comparisons, CCFPEQmode should be used.
1877 VOIDmode should be used in all other cases.
1879 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1880 possible, to allow for more combinations. */
1882 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1884 /* Return nonzero if MODE implies a floating point inequality can be
1887 #define REVERSIBLE_CC_MODE(MODE) 1
1889 /* A C expression whose value is reversed condition code of the CODE for
1890 comparison done in CC_MODE mode. */
1891 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1894 /* Control the assembler format that we output, to the extent
1895 this does not vary between assemblers. */
1897 /* How to refer to registers in assembler output.
1898 This sequence is indexed by compiler's hard-register-number (see above). */
1900 /* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1901 For non floating point regs, the following are the HImode names.
1903 For float regs, the stack top is sometimes referred to as "%st(0)"
1904 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1906 #define HI_REGISTER_NAMES \
1907 {"ax","dx","cx","bx","si","di","bp","sp", \
1908 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1909 "argp", "flags", "fpsr", "dirflag", "frame", \
1910 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1911 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
1912 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1913 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1915 #define REGISTER_NAMES HI_REGISTER_NAMES
1917 /* Table of additional register names to use in user input. */
1919 #define ADDITIONAL_REGISTER_NAMES \
1920 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1921 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1922 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1923 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1924 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1925 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1927 /* Note we are omitting these since currently I don't know how
1928 to get gcc to use these, since they want the same but different
1929 number as al, and ax.
1932 #define QI_REGISTER_NAMES \
1933 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1935 /* These parallel the array above, and can be used to access bits 8:15
1936 of regs 0 through 3. */
1938 #define QI_HIGH_REGISTER_NAMES \
1939 {"ah", "dh", "ch", "bh", }
1941 /* How to renumber registers for dbx and gdb. */
1943 #define DBX_REGISTER_NUMBER(N) \
1944 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1946 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1947 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1948 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1950 /* Before the prologue, RA is at 0(%esp). */
1951 #define INCOMING_RETURN_ADDR_RTX \
1952 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1954 /* After the prologue, RA is at -4(AP) in the current frame. */
1955 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1957 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
1958 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1960 /* PC is dbx register 8; let's use that column for RA. */
1961 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1963 /* Before the prologue, the top of the frame is at 4(%esp). */
1964 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1966 /* Describe how we implement __builtin_eh_return. */
1967 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
1968 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
1971 /* Select a format to encode pointers in exception handling data. CODE
1972 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1973 true if the symbol may be affected by dynamic relocations.
1975 ??? All x86 object file formats are capable of representing this.
1976 After all, the relocation needed is the same as for the call insn.
1977 Whether or not a particular assembler allows us to enter such, I
1978 guess we'll have to see. */
1979 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1980 asm_preferred_eh_data_format ((CODE), (GLOBAL))
1982 /* This is how to output an insn to push a register on the stack.
1983 It need not be very fast code. */
1985 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1988 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
1989 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1991 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
1994 /* This is how to output an insn to pop a register from the stack.
1995 It need not be very fast code. */
1997 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2000 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2001 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2003 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2006 /* This is how to output an element of a case-vector that is absolute. */
2008 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2009 ix86_output_addr_vec_elt ((FILE), (VALUE))
2011 /* This is how to output an element of a case-vector that is relative. */
2013 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2014 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2016 /* Under some conditions we need jump tables in the text section,
2017 because the assembler cannot handle label differences between
2018 sections. This is the case for x86_64 on Mach-O for example. */
2020 #define JUMP_TABLES_IN_TEXT_SECTION \
2021 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2022 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2024 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2025 and switch back. For x86 we do this only to save a few bytes that
2026 would otherwise be unused in the text section. */
2027 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2028 asm (SECTION_OP "\n\t" \
2029 "call " USER_LABEL_PREFIX #FUNC "\n" \
2030 TEXT_SECTION_ASM_OP);
2032 /* Print operand X (an rtx) in assembler syntax to file FILE.
2033 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2034 Effect of various CODE letters is described in i386.c near
2035 print_operand function. */
2037 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2038 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2040 #define PRINT_OPERAND(FILE, X, CODE) \
2041 print_operand ((FILE), (X), (CODE))
2043 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2044 print_operand_address ((FILE), (ADDR))
2046 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2048 if (! output_addr_const_extra (FILE, (X))) \
2052 /* a letter which is not needed by the normal asm syntax, which
2053 we can use for operand syntax in the extended asm */
2055 #define ASM_OPERAND_LETTER '#'
2056 #define RET return ""
2057 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2059 /* Which processor to schedule for. The cpu attribute defines a list that
2060 mirrors this list, so changes to i386.md must be made at the same time. */
2064 PROCESSOR_I386, /* 80386 */
2065 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2067 PROCESSOR_PENTIUMPRO,
2073 PROCESSOR_GENERIC32,
2074 PROCESSOR_GENERIC64,
2078 extern enum processor_type ix86_tune;
2079 extern enum processor_type ix86_arch;
2087 extern enum fpmath_unit ix86_fpmath;
2096 extern enum tls_dialect ix86_tls_dialect;
2099 CM_32, /* The traditional 32-bit ABI. */
2100 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2101 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2102 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2103 CM_LARGE, /* No assumptions. */
2104 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2105 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2108 extern enum cmodel ix86_cmodel;
2110 /* Size of the RED_ZONE area. */
2111 #define RED_ZONE_SIZE 128
2112 /* Reserved area of the red zone for temporaries. */
2113 #define RED_ZONE_RESERVE 8
2120 extern enum asm_dialect ix86_asm_dialect;
2121 extern unsigned int ix86_preferred_stack_boundary;
2122 extern int ix86_branch_cost, ix86_section_threshold;
2124 /* Smallest class containing REGNO. */
2125 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2127 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2128 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2129 extern rtx ix86_compare_emitted;
2131 /* To properly truncate FP values into integers, we need to set i387 control
2132 word. We can't emit proper mode switching code before reload, as spills
2133 generated by reload may truncate values incorrectly, but we still can avoid
2134 redundant computation of new control word by the mode switching pass.
2135 The fldcw instructions are still emitted redundantly, but this is probably
2136 not going to be noticeable problem, as most CPUs do have fast path for
2139 The machinery is to emit simple truncation instructions and split them
2140 before reload to instructions having USEs of two memory locations that
2141 are filled by this code to old and new control word.
2143 Post-reload pass may be later used to eliminate the redundant fildcw if
2155 enum ix86_stack_slot
2163 MAX_386_STACK_LOCALS
2166 /* Define this macro if the port needs extra instructions inserted
2167 for mode switching in an optimizing compilation. */
2169 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2170 ix86_optimize_mode_switching[(ENTITY)]
2172 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2173 initializer for an array of integers. Each initializer element N
2174 refers to an entity that needs mode switching, and specifies the
2175 number of different modes that might need to be set for this
2176 entity. The position of the initializer in the initializer -
2177 starting counting at zero - determines the integer that is used to
2178 refer to the mode-switched entity in question. */
2180 #define NUM_MODES_FOR_MODE_SWITCHING \
2181 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2183 /* ENTITY is an integer specifying a mode-switched entity. If
2184 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2185 return an integer value not larger than the corresponding element
2186 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2187 must be switched into prior to the execution of INSN. */
2189 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2191 /* This macro specifies the order in which modes for ENTITY are
2192 processed. 0 is the highest priority. */
2194 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2196 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2197 is the set of hard registers live at the point where the insn(s)
2198 are to be inserted. */
2200 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2201 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2202 ? emit_i387_cw_initialization (MODE), 0 \
2206 /* Avoid renaming of stack registers, as doing so in combination with
2207 scheduling just increases amount of live registers at time and in
2208 the turn amount of fxch instructions needed.
2210 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2212 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2213 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
2216 #define DLL_IMPORT_EXPORT_PREFIX '#'
2218 #define FASTCALL_PREFIX '@'
2220 struct machine_function GTY(())
2222 struct stack_local_entry *stack_locals;
2223 const char *some_ld_name;
2224 rtx force_align_arg_pointer;
2225 int save_varrargs_registers;
2226 int accesses_prev_frame;
2227 int optimize_mode_switching[MAX_386_ENTITIES];
2228 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2229 determine the style used. */
2230 int use_fast_prologue_epilogue;
2231 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2233 int use_fast_prologue_epilogue_nregs;
2234 /* If true, the current function needs the default PIC register, not
2235 an alternate register (on x86) and must not use the red zone (on
2236 x86_64), even if it's a leaf function. We don't want the
2237 function to be regarded as non-leaf because TLS calls need not
2238 affect register allocation. This flag is set when a TLS call
2239 instruction is expanded within a function, and never reset, even
2240 if all such instructions are optimized away. Use the
2241 ix86_current_function_calls_tls_descriptor macro for a better
2243 int tls_descriptor_call_expanded_p;
2246 #define ix86_stack_locals (cfun->machine->stack_locals)
2247 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2248 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2249 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2250 (cfun->machine->tls_descriptor_call_expanded_p)
2251 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2252 calls are optimized away, we try to detect cases in which it was
2253 optimized away. Since such instructions (use (reg REG_SP)), we can
2254 verify whether there's any such instruction live by testing that
2256 #define ix86_current_function_calls_tls_descriptor \
2257 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2259 /* Control behavior of x86_file_start. */
2260 #define X86_FILE_START_VERSION_DIRECTIVE false
2261 #define X86_FILE_START_FLTUSED false
2263 /* Flag to mark data that is in the large address area. */
2264 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2265 #define SYMBOL_REF_FAR_ADDR_P(X) \
2266 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
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