1 /* Subroutines for insn-output.c for Intel X86.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
38 #ifdef EXTRA_CONSTRAINT
39 /* If EXTRA_CONSTRAINT is defined, then the 'S'
40 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
41 asm statements that need 'S' for class SIREG will break. */
42 error EXTRA_CONSTRAINT conflicts with S constraint letter
43 /* The previous line used to be #error, but some compilers barf
44 even if the conditional was untrue. */
47 enum reg_mem /* Type of an operand for ix86_{binary,unary}_operator_ok */
54 /* Processor costs (relative to an add) */
55 struct processor_costs i386_cost = { /* 386 specific costs */
56 1, /* cost of an add instruction (2 cycles) */
57 1, /* cost of a lea instruction */
58 3, /* variable shift costs */
59 2, /* constant shift costs */
60 6, /* cost of starting a multiply */
61 1, /* cost of multiply per each bit set */
62 23 /* cost of a divide/mod */
65 struct processor_costs i486_cost = { /* 486 specific costs */
66 1, /* cost of an add instruction */
67 1, /* cost of a lea instruction */
68 3, /* variable shift costs */
69 2, /* constant shift costs */
70 12, /* cost of starting a multiply */
71 1, /* cost of multiply per each bit set */
72 40 /* cost of a divide/mod */
75 struct processor_costs pentium_cost = {
76 1, /* cost of an add instruction */
77 1, /* cost of a lea instruction */
78 3, /* variable shift costs */
79 1, /* constant shift costs */
80 12, /* cost of starting a multiply */
81 1, /* cost of multiply per each bit set */
82 25 /* cost of a divide/mod */
85 struct processor_costs *ix86_cost = &pentium_cost;
87 #define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx))
89 extern FILE *asm_out_file;
90 extern char *strcat ();
92 char *singlemove_string ();
93 char *output_move_const_single ();
94 char *output_fp_cc0_set ();
96 char *hi_reg_name[] = HI_REGISTER_NAMES;
97 char *qi_reg_name[] = QI_REGISTER_NAMES;
98 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
100 /* Array of the smallest class containing reg number REGNO, indexed by
101 REGNO. Used by REGNO_REG_CLASS in i386.h. */
103 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
106 AREG, DREG, CREG, BREG,
108 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
110 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
111 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
116 /* Test and compare insns in i386.md store the information needed to
117 generate branch and scc insns here. */
119 struct rtx_def *i386_compare_op0 = NULL_RTX;
120 struct rtx_def *i386_compare_op1 = NULL_RTX;
121 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
123 /* which cpu are we scheduling for */
124 enum processor_type ix86_cpu;
126 /* which instruction set architecture to use. */
129 /* Strings to hold which cpu and instruction set architecture to use. */
130 char *ix86_cpu_string; /* for -mcpu=<xxx> */
131 char *ix86_isa_string; /* for -misa=<xxx> */
133 /* Register allocation order */
134 char *i386_reg_alloc_order;
135 static char regs_allocated[FIRST_PSEUDO_REGISTER];
137 /* # of registers to use to pass arguments. */
138 char *i386_regparm_string; /* # registers to use to pass args */
139 int i386_regparm; /* i386_regparm_string as a number */
141 /* Alignment to use for loops and jumps */
142 char *i386_align_loops_string; /* power of two alignment for loops */
143 char *i386_align_jumps_string; /* power of two alignment for non-loop jumps */
144 char *i386_align_funcs_string; /* power of two alignment for functions */
146 int i386_align_loops; /* power of two alignment for loops */
147 int i386_align_jumps; /* power of two alignment for non-loop jumps */
148 int i386_align_funcs; /* power of two alignment for functions */
150 /* Sometimes certain combinations of command options do not make
151 sense on a particular target machine. You can define a macro
152 `OVERRIDE_OPTIONS' to take account of this. This macro, if
153 defined, is executed once just after all the command options have
156 Don't use this macro to turn on various extra optimizations for
157 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
168 char *name; /* Canonical processor name. */
169 enum processor_type processor; /* Processor type enum value. */
170 struct processor_costs *cost; /* Processor costs */
171 int target_enable; /* Target flags to enable. */
172 int target_disable; /* Target flags to disable. */
173 } processor_target_table[]
174 = {{PROCESSOR_COMMON_STRING, PROCESSOR_COMMON, &i486_cost, 0, 0},
175 {PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0},
176 {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0},
177 {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
178 {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
179 {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentium_cost, 0, 0},
180 {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO, &pentium_cost, 0, 0}};
182 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
184 #ifdef SUBTARGET_OVERRIDE_OPTIONS
185 SUBTARGET_OVERRIDE_OPTIONS;
188 /* Validate registers in register allocation order */
189 if (i386_reg_alloc_order)
191 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
195 case 'a': regno = 0; break;
196 case 'd': regno = 1; break;
197 case 'c': regno = 2; break;
198 case 'b': regno = 3; break;
199 case 'S': regno = 4; break;
200 case 'D': regno = 5; break;
201 case 'B': regno = 6; break;
203 default: fatal ("Register '%c' is unknown", ch);
206 if (regs_allocated[regno])
207 fatal ("Register '%c' was already specified in the allocation order", ch);
209 regs_allocated[regno] = 1;
213 /* Get the architectural level. */
214 if (ix86_isa_string == (char *)0)
215 ix86_isa_string = PROCESSOR_DEFAULT_STRING;
217 for (i = 0; i < ptt_size; i++)
218 if (! strcmp (ix86_isa_string, processor_target_table[i].name))
220 ix86_isa = processor_target_table[i].processor;
221 if (ix86_cpu_string == (char *)0)
222 ix86_cpu_string = processor_target_table[i].name;
228 error ("bad value (%s) for -misa= switch", ix86_isa_string);
229 ix86_isa_string = PROCESSOR_DEFAULT_STRING;
230 ix86_isa = PROCESSOR_DEFAULT;
233 for (j = 0; j < ptt_size; j++)
234 if (! strcmp (ix86_cpu_string, processor_target_table[j].name))
236 ix86_cpu = processor_target_table[j].processor;
237 if (i > j && (int)ix86_isa >= (int)PROCESSOR_PENTIUMPRO)
238 error ("-mcpu=%s does not support -march=%s", ix86_cpu_string, ix86_isa_string);
240 target_flags |= processor_target_table[j].target_enable;
241 target_flags &= ~processor_target_table[j].target_disable;
247 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
248 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
249 ix86_cpu = PROCESSOR_DEFAULT;
252 /* Validate -mregparm= value */
253 if (i386_regparm_string)
255 i386_regparm = atoi (i386_regparm_string);
256 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX)
257 fatal ("-mregparm=%d is not between 0 and %d", i386_regparm, REGPARM_MAX);
260 def_align = (TARGET_386) ? 2 : 4;
262 /* Validate -malign-loops= value, or provide default */
263 if (i386_align_loops_string)
265 i386_align_loops = atoi (i386_align_loops_string);
266 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN)
267 fatal ("-malign-loops=%d is not between 0 and %d",
268 i386_align_loops, MAX_CODE_ALIGN);
271 i386_align_loops = 2;
273 /* Validate -malign-jumps= value, or provide default */
274 if (i386_align_jumps_string)
276 i386_align_jumps = atoi (i386_align_jumps_string);
277 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN)
278 fatal ("-malign-jumps=%d is not between 0 and %d",
279 i386_align_jumps, MAX_CODE_ALIGN);
282 i386_align_jumps = def_align;
284 /* Validate -malign-functions= value, or provide default */
285 if (i386_align_funcs_string)
287 i386_align_funcs = atoi (i386_align_funcs_string);
288 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN)
289 fatal ("-malign-functions=%d is not between 0 and %d",
290 i386_align_funcs, MAX_CODE_ALIGN);
293 i386_align_funcs = def_align;
295 if (TARGET_OMIT_LEAF_FRAME_POINTER) /* keep nonleaf frame pointers */
296 flag_omit_frame_pointer = 1;
299 /* A C statement (sans semicolon) to choose the order in which to
300 allocate hard registers for pseudo-registers local to a basic
303 Store the desired register order in the array `reg_alloc_order'.
304 Element 0 should be the register to allocate first; element 1, the
305 next register; and so on.
307 The macro body should not assume anything about the contents of
308 `reg_alloc_order' before execution of the macro.
310 On most machines, it is not necessary to define this macro. */
313 order_regs_for_local_alloc ()
315 int i, ch, order, regno;
317 /* User specified the register allocation order */
318 if (i386_reg_alloc_order)
320 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
324 case 'a': regno = 0; break;
325 case 'd': regno = 1; break;
326 case 'c': regno = 2; break;
327 case 'b': regno = 3; break;
328 case 'S': regno = 4; break;
329 case 'D': regno = 5; break;
330 case 'B': regno = 6; break;
333 reg_alloc_order[order++] = regno;
336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
338 if (!regs_allocated[i])
339 reg_alloc_order[order++] = i;
343 /* If users did not specify a register allocation order, use natural order */
346 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
347 reg_alloc_order[i] = i;
353 optimization_options (level)
356 /* For -O2, and beyond, turn off -fschedule-insns by default. It tends to
357 make the problem with not enough registers even worse */
358 #ifdef INSN_SCHEDULING
360 flag_schedule_insns = 0;
364 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
365 attribute for DECL. The attributes in ATTRIBUTES have previously been
369 i386_valid_decl_attribute_p (decl, attributes, identifier, args)
378 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
379 attribute for TYPE. The attributes in ATTRIBUTES have previously been
383 i386_valid_type_attribute_p (type, attributes, identifier, args)
389 if (TREE_CODE (type) != FUNCTION_TYPE
390 && TREE_CODE (type) != FIELD_DECL
391 && TREE_CODE (type) != TYPE_DECL)
394 /* Stdcall attribute says callee is responsible for popping arguments
395 if they are not variable. */
396 if (is_attribute_p ("stdcall", identifier))
397 return (args == NULL_TREE);
399 /* Cdecl attribute says the callee is a normal C declaration */
400 if (is_attribute_p ("cdecl", identifier))
401 return (args == NULL_TREE);
403 /* Regparm attribute specifies how many integer arguments are to be
404 passed in registers */
405 if (is_attribute_p ("regparm", identifier))
409 if (!args || TREE_CODE (args) != TREE_LIST
410 || TREE_CHAIN (args) != NULL_TREE
411 || TREE_VALUE (args) == NULL_TREE)
414 cst = TREE_VALUE (args);
415 if (TREE_CODE (cst) != INTEGER_CST)
418 if (TREE_INT_CST_HIGH (cst) != 0
419 || TREE_INT_CST_LOW (cst) < 0
420 || TREE_INT_CST_LOW (cst) > REGPARM_MAX)
429 /* Return 0 if the attributes for two types are incompatible, 1 if they
430 are compatible, and 2 if they are nearly compatible (which causes a
431 warning to be generated). */
434 i386_comp_type_attributes (type1, type2)
442 /* Value is the number of bytes of arguments automatically
443 popped when returning from a subroutine call.
444 FUNDECL is the declaration node of the function (as a tree),
445 FUNTYPE is the data type of the function (as a tree),
446 or for a library call it is an identifier node for the subroutine name.
447 SIZE is the number of bytes of arguments passed on the stack.
449 On the 80386, the RTD insn may be used to pop them if the number
450 of args is fixed, but if the number is variable then the caller
451 must pop them all. RTD can't be used for library calls now
452 because the library is compiled with the Unix compiler.
453 Use of RTD is a selectable option, since it is incompatible with
454 standard Unix calling sequences. If the option is not selected,
455 the caller must always pop the args.
457 The attribute stdcall is equivalent to RTD on a per module basis. */
460 i386_return_pops_args (fundecl, funtype, size)
465 int rtd = TARGET_RTD;
467 if (TREE_CODE (funtype) == IDENTIFIER_NODE)
470 /* Cdecl functions override -mrtd, and never pop the stack */
471 if (!lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
473 /* Stdcall functions will pop the stack if not variable args */
474 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
478 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
479 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype))) == void_type_node)))
483 /* Lose any fake structure return argument */
484 if (aggregate_value_p (TREE_TYPE (funtype)))
485 return GET_MODE_SIZE (Pmode);
491 /* Argument support functions. */
493 /* Initialize a variable CUM of type CUMULATIVE_ARGS
494 for a call to a function whose data type is FNTYPE.
495 For a library call, FNTYPE is 0. */
498 init_cumulative_args (cum, fntype, libname)
499 CUMULATIVE_ARGS *cum; /* argument info to initialize */
500 tree fntype; /* tree ptr for function decl */
501 rtx libname; /* SYMBOL_REF of library name or 0 */
503 static CUMULATIVE_ARGS zero_cum;
504 tree param, next_param;
506 if (TARGET_DEBUG_ARG)
508 fprintf (stderr, "\ninit_cumulative_args (");
511 tree ret_type = TREE_TYPE (fntype);
512 fprintf (stderr, "fntype code = %s, ret code = %s",
513 tree_code_name[ (int)TREE_CODE (fntype) ],
514 tree_code_name[ (int)TREE_CODE (ret_type) ]);
517 fprintf (stderr, "no fntype");
520 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
525 /* Set up the number of registers to use for passing arguments. */
526 cum->nregs = i386_regparm;
529 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
531 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
534 /* Determine if this function has variable arguments. This is
535 indicated by the last argument being 'void_type_mode' if there
536 are no variable arguments. If there are variable arguments, then
537 we won't pass anything in registers */
541 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
545 next_param = TREE_CHAIN (param);
546 if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node)
551 if (TARGET_DEBUG_ARG)
552 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
557 /* Update the data in CUM to advance over an argument
558 of mode MODE and data type TYPE.
559 (TYPE is null for libcalls where that information may not be available.) */
562 function_arg_advance (cum, mode, type, named)
563 CUMULATIVE_ARGS *cum; /* current arg information */
564 enum machine_mode mode; /* current arg mode */
565 tree type; /* type of the argument or 0 if lib support */
566 int named; /* whether or not the argument was named */
568 int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
569 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
571 if (TARGET_DEBUG_ARG)
573 "function_adv( size=%d, words=%2d, nregs=%d, mode=%4s, named=%d )\n\n",
574 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
589 /* Define where to put the arguments to a function.
590 Value is zero to push the argument on the stack,
591 or a hard register in which to store the argument.
593 MODE is the argument's machine mode.
594 TYPE is the data type of the argument (as a tree).
595 This is null for libcalls where that information may
597 CUM is a variable of type CUMULATIVE_ARGS which gives info about
598 the preceding args and about the function being called.
599 NAMED is nonzero if this argument is a named parameter
600 (otherwise it is an extra parameter matching an ellipsis). */
603 function_arg (cum, mode, type, named)
604 CUMULATIVE_ARGS *cum; /* current arg information */
605 enum machine_mode mode; /* current arg mode */
606 tree type; /* type of the argument or 0 if lib support */
607 int named; /* != 0 for normal args, == 0 for ... args */
610 int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
611 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
615 default: /* for now, pass fp/complex values on the stack */
623 if (words <= cum->nregs)
624 ret = gen_rtx (REG, mode, cum->regno);
628 if (TARGET_DEBUG_ARG)
631 "function_arg( size=%d, words=%2d, nregs=%d, mode=%4s, named=%d",
632 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
635 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]);
637 fprintf (stderr, ", stack");
639 fprintf (stderr, " )\n");
645 /* For an arg passed partly in registers and partly in memory,
646 this is the number of registers used.
647 For args passed entirely in registers or entirely in memory, zero. */
650 function_arg_partial_nregs (cum, mode, type, named)
651 CUMULATIVE_ARGS *cum; /* current arg information */
652 enum machine_mode mode; /* current arg mode */
653 tree type; /* type of the argument or 0 if lib support */
654 int named; /* != 0 for normal args, == 0 for ... args */
660 /* Output an insn whose source is a 386 integer register. SRC is the
661 rtx for the register, and TEMPLATE is the op-code template. SRC may
662 be either SImode or DImode.
664 The template will be output with operands[0] as SRC, and operands[1]
665 as a pointer to the top of the 386 stack. So a call from floatsidf2
666 would look like this:
668 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
670 where %z0 corresponds to the caller's operands[1], and is used to
671 emit the proper size suffix.
673 ??? Extend this to handle HImode - a 387 can load and store HImode
677 output_op_from_reg (src, template)
682 int size = GET_MODE_SIZE (GET_MODE (src));
685 xops[1] = AT_SP (Pmode);
686 xops[2] = GEN_INT (size);
687 xops[3] = stack_pointer_rtx;
689 if (size > UNITS_PER_WORD)
692 if (size > 2 * UNITS_PER_WORD)
694 high = gen_rtx (REG, SImode, REGNO (src) + 2);
695 output_asm_insn (AS1 (push%L0,%0), &high);
697 high = gen_rtx (REG, SImode, REGNO (src) + 1);
698 output_asm_insn (AS1 (push%L0,%0), &high);
700 output_asm_insn (AS1 (push%L0,%0), &src);
702 output_asm_insn (template, xops);
704 output_asm_insn (AS2 (add%L3,%2,%3), xops);
707 /* Output an insn to pop an value from the 387 top-of-stack to 386
708 register DEST. The 387 register stack is popped if DIES is true. If
709 the mode of DEST is an integer mode, a `fist' integer store is done,
710 otherwise a `fst' float store is done. */
713 output_to_reg (dest, dies)
718 int size = GET_MODE_SIZE (GET_MODE (dest));
720 xops[0] = AT_SP (Pmode);
721 xops[1] = stack_pointer_rtx;
722 xops[2] = GEN_INT (size);
725 output_asm_insn (AS2 (sub%L1,%2,%1), xops);
727 if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT)
730 output_asm_insn (AS1 (fistp%z3,%y0), xops);
732 output_asm_insn (AS1 (fist%z3,%y0), xops);
734 else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT)
737 output_asm_insn (AS1 (fstp%z3,%y0), xops);
740 if (GET_MODE (dest) == XFmode)
742 output_asm_insn (AS1 (fstp%z3,%y0), xops);
743 output_asm_insn (AS1 (fld%z3,%y0), xops);
746 output_asm_insn (AS1 (fst%z3,%y0), xops);
752 output_asm_insn (AS1 (pop%L0,%0), &dest);
754 if (size > UNITS_PER_WORD)
756 dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
757 output_asm_insn (AS1 (pop%L0,%0), &dest);
758 if (size > 2 * UNITS_PER_WORD)
760 dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
761 output_asm_insn (AS1 (pop%L0,%0), &dest);
767 singlemove_string (operands)
771 if (GET_CODE (operands[0]) == MEM
772 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
774 if (XEXP (x, 0) != stack_pointer_rtx)
778 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
780 return output_move_const_single (operands);
782 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
783 return AS2 (mov%L0,%1,%0);
784 else if (CONSTANT_P (operands[1]))
785 return AS2 (mov%L0,%1,%0);
788 output_asm_insn ("push%L1 %1", operands);
793 /* Return a REG that occurs in ADDR with coefficient 1.
794 ADDR can be effectively incremented by incrementing REG. */
800 while (GET_CODE (addr) == PLUS)
802 if (GET_CODE (XEXP (addr, 0)) == REG)
803 addr = XEXP (addr, 0);
804 else if (GET_CODE (XEXP (addr, 1)) == REG)
805 addr = XEXP (addr, 1);
806 else if (CONSTANT_P (XEXP (addr, 0)))
807 addr = XEXP (addr, 1);
808 else if (CONSTANT_P (XEXP (addr, 1)))
809 addr = XEXP (addr, 0);
813 if (GET_CODE (addr) == REG)
819 /* Output an insn to add the constant N to the register X. */
830 output_asm_insn (AS1 (dec%L0,%0), xops);
832 output_asm_insn (AS1 (inc%L0,%0), xops);
835 xops[1] = GEN_INT (-n);
836 output_asm_insn (AS2 (sub%L0,%1,%0), xops);
840 xops[1] = GEN_INT (n);
841 output_asm_insn (AS2 (add%L0,%1,%0), xops);
846 /* Output assembler code to perform a doubleword move insn
847 with operands OPERANDS. */
850 output_move_double (operands)
853 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
857 rtx addreg0 = 0, addreg1 = 0;
858 int dest_overlapped_low = 0;
859 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
864 /* First classify both operands. */
866 if (REG_P (operands[0]))
868 else if (offsettable_memref_p (operands[0]))
870 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
872 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
874 else if (GET_CODE (operands[0]) == MEM)
879 if (REG_P (operands[1]))
881 else if (CONSTANT_P (operands[1]))
883 else if (offsettable_memref_p (operands[1]))
885 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
887 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
889 else if (GET_CODE (operands[1]) == MEM)
894 /* Check for the cases that the operand constraints are not
895 supposed to allow to happen. Abort if we get one,
896 because generating code for these cases is painful. */
898 if (optype0 == RNDOP || optype1 == RNDOP)
901 /* If one operand is decrementing and one is incrementing
902 decrement the former register explicitly
903 and change that operand into ordinary indexing. */
905 if (optype0 == PUSHOP && optype1 == POPOP)
907 /* ??? Can this ever happen on i386? */
908 operands[0] = XEXP (XEXP (operands[0], 0), 0);
909 asm_add (-size, operands[0]);
910 if (GET_MODE (operands[1]) == XFmode)
911 operands[0] = gen_rtx (MEM, XFmode, operands[0]);
912 else if (GET_MODE (operands[0]) == DFmode)
913 operands[0] = gen_rtx (MEM, DFmode, operands[0]);
915 operands[0] = gen_rtx (MEM, DImode, operands[0]);
919 if (optype0 == POPOP && optype1 == PUSHOP)
921 /* ??? Can this ever happen on i386? */
922 operands[1] = XEXP (XEXP (operands[1], 0), 0);
923 asm_add (-size, operands[1]);
924 if (GET_MODE (operands[1]) == XFmode)
925 operands[1] = gen_rtx (MEM, XFmode, operands[1]);
926 else if (GET_MODE (operands[1]) == DFmode)
927 operands[1] = gen_rtx (MEM, DFmode, operands[1]);
929 operands[1] = gen_rtx (MEM, DImode, operands[1]);
933 /* If an operand is an unoffsettable memory ref, find a register
934 we can increment temporarily to make it refer to the second word. */
936 if (optype0 == MEMOP)
937 addreg0 = find_addr_reg (XEXP (operands[0], 0));
939 if (optype1 == MEMOP)
940 addreg1 = find_addr_reg (XEXP (operands[1], 0));
942 /* Ok, we can do one word at a time.
943 Normally we do the low-numbered word first,
944 but if either operand is autodecrementing then we
945 do the high-numbered word first.
947 In either case, set up in LATEHALF the operands to use
948 for the high-numbered word and in some cases alter the
949 operands in OPERANDS to be suitable for the low-numbered word. */
953 if (optype0 == REGOP)
955 middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
956 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
958 else if (optype0 == OFFSOP)
960 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
961 latehalf[0] = adj_offsettable_operand (operands[0], 8);
965 middlehalf[0] = operands[0];
966 latehalf[0] = operands[0];
969 if (optype1 == REGOP)
971 middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
972 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
974 else if (optype1 == OFFSOP)
976 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
977 latehalf[1] = adj_offsettable_operand (operands[1], 8);
979 else if (optype1 == CNSTOP)
981 if (GET_CODE (operands[1]) == CONST_DOUBLE)
983 REAL_VALUE_TYPE r; long l[3];
985 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
986 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
987 operands[1] = GEN_INT (l[0]);
988 middlehalf[1] = GEN_INT (l[1]);
989 latehalf[1] = GEN_INT (l[2]);
991 else if (CONSTANT_P (operands[1]))
992 /* No non-CONST_DOUBLE constant should ever appear here. */
997 middlehalf[1] = operands[1];
998 latehalf[1] = operands[1];
1001 else /* size is not 12: */
1003 if (optype0 == REGOP)
1004 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1005 else if (optype0 == OFFSOP)
1006 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1008 latehalf[0] = operands[0];
1010 if (optype1 == REGOP)
1011 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1012 else if (optype1 == OFFSOP)
1013 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1014 else if (optype1 == CNSTOP)
1015 split_double (operands[1], &operands[1], &latehalf[1]);
1017 latehalf[1] = operands[1];
1020 /* If insn is effectively movd N (sp),-(sp) then we will do the
1021 high word first. We should use the adjusted operand 1
1022 (which is N+4 (sp) or N+8 (sp))
1023 for the low word and middle word as well,
1024 to compensate for the first decrement of sp. */
1025 if (optype0 == PUSHOP
1026 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1027 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1028 middlehalf[1] = operands[1] = latehalf[1];
1030 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1031 if the upper part of reg N does not appear in the MEM, arrange to
1032 emit the move late-half first. Otherwise, compute the MEM address
1033 into the upper part of N and use that as a pointer to the memory
1035 if (optype0 == REGOP
1036 && (optype1 == OFFSOP || optype1 == MEMOP))
1038 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1039 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1041 /* If both halves of dest are used in the src memory address,
1042 compute the address into latehalf of dest. */
1044 xops[0] = latehalf[0];
1045 xops[1] = XEXP (operands[1], 0);
1046 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
1047 if( GET_MODE (operands[1]) == XFmode )
1050 operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
1051 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1052 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1056 operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
1057 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1061 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
1063 /* Check for two regs used by both source and dest. */
1064 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1065 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1068 /* JRV says this can't happen: */
1069 if (addreg0 || addreg1)
1072 /* Only the middle reg conflicts; simply put it last. */
1073 output_asm_insn (singlemove_string (operands), operands);
1074 output_asm_insn (singlemove_string (latehalf), latehalf);
1075 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1078 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
1079 /* If the low half of dest is mentioned in the source memory
1080 address, the arrange to emit the move late half first. */
1081 dest_overlapped_low = 1;
1084 /* If one or both operands autodecrementing,
1085 do the two words, high-numbered first. */
1087 /* Likewise, the first move would clobber the source of the second one,
1088 do them in the other order. This happens only for registers;
1089 such overlap can't happen in memory unless the user explicitly
1090 sets it up, and that is an undefined circumstance. */
1093 if (optype0 == PUSHOP || optype1 == PUSHOP
1094 || (optype0 == REGOP && optype1 == REGOP
1095 && REGNO (operands[0]) == REGNO (latehalf[1]))
1096 || dest_overlapped_low)
1098 if (optype0 == PUSHOP || optype1 == PUSHOP
1099 || (optype0 == REGOP && optype1 == REGOP
1100 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1101 || REGNO (operands[0]) == REGNO (latehalf[1])))
1102 || dest_overlapped_low)
1104 /* Make any unoffsettable addresses point at high-numbered word. */
1106 asm_add (size-4, addreg0);
1108 asm_add (size-4, addreg1);
1111 output_asm_insn (singlemove_string (latehalf), latehalf);
1113 /* Undo the adds we just did. */
1115 asm_add (-4, addreg0);
1117 asm_add (-4, addreg1);
1121 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1123 asm_add (-4, addreg0);
1125 asm_add (-4, addreg1);
1128 /* Do low-numbered word. */
1129 return singlemove_string (operands);
1132 /* Normal case: do the two words, low-numbered first. */
1134 output_asm_insn (singlemove_string (operands), operands);
1136 /* Do the middle one of the three words for long double */
1140 asm_add (4, addreg0);
1142 asm_add (4, addreg1);
1144 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1147 /* Make any unoffsettable addresses point at high-numbered word. */
1149 asm_add (4, addreg0);
1151 asm_add (4, addreg1);
1154 output_asm_insn (singlemove_string (latehalf), latehalf);
1156 /* Undo the adds we just did. */
1158 asm_add (4-size, addreg0);
1160 asm_add (4-size, addreg1);
1166 #define MAX_TMPS 2 /* max temporary registers used */
1168 /* Output the appropriate code to move push memory on the stack */
1171 output_move_pushmem (operands, insn, length, tmp_start, n_operands)
1183 } tmp_info[MAX_TMPS];
1185 rtx src = operands[1];
1188 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
1189 int stack_offset = 0;
1193 if (!offsettable_memref_p (src))
1194 fatal_insn ("Source is not offsettable", insn);
1196 if ((length & 3) != 0)
1197 fatal_insn ("Pushing non-word aligned size", insn);
1199 /* Figure out which temporary registers we have available */
1200 for (i = tmp_start; i < n_operands; i++)
1202 if (GET_CODE (operands[i]) == REG)
1204 if (reg_overlap_mentioned_p (operands[i], src))
1207 tmp_info[ max_tmps++ ].xops[1] = operands[i];
1208 if (max_tmps == MAX_TMPS)
1214 for (offset = length - 4; offset >= 0; offset -= 4)
1216 xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1217 output_asm_insn (AS1(push%L0,%0), xops);
1223 for (offset = length - 4; offset >= 0; )
1225 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
1227 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1);
1228 tmp_info[num_tmps].push = AS1(push%L0,%1);
1229 tmp_info[num_tmps].xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1233 for (i = 0; i < num_tmps; i++)
1234 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1236 for (i = 0; i < num_tmps; i++)
1237 output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
1240 stack_offset += 4*num_tmps;
1248 /* Output the appropriate code to move data between two memory locations */
1251 output_move_memory (operands, insn, length, tmp_start, n_operands)
1262 } tmp_info[MAX_TMPS];
1264 rtx dest = operands[0];
1265 rtx src = operands[1];
1266 rtx qi_tmp = NULL_RTX;
1272 if (GET_CODE (dest) == MEM
1273 && GET_CODE (XEXP (dest, 0)) == PRE_INC
1274 && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)
1275 return output_move_pushmem (operands, insn, length, tmp_start, n_operands);
1277 if (!offsettable_memref_p (src))
1278 fatal_insn ("Source is not offsettable", insn);
1280 if (!offsettable_memref_p (dest))
1281 fatal_insn ("Destination is not offsettable", insn);
1283 /* Figure out which temporary registers we have available */
1284 for (i = tmp_start; i < n_operands; i++)
1286 if (GET_CODE (operands[i]) == REG)
1288 if ((length & 1) != 0 && !qi_tmp && QI_REG_P (operands[i]))
1289 qi_tmp = operands[i];
1291 if (reg_overlap_mentioned_p (operands[i], dest))
1292 fatal_insn ("Temporary register overlaps the destination", insn);
1294 if (reg_overlap_mentioned_p (operands[i], src))
1295 fatal_insn ("Temporary register overlaps the source", insn);
1297 tmp_info[ max_tmps++ ].xops[2] = operands[i];
1298 if (max_tmps == MAX_TMPS)
1304 fatal_insn ("No scratch registers were found to do memory->memory moves", insn);
1306 if ((length & 1) != 0)
1309 fatal_insn ("No byte register found when moving odd # of bytes.", insn);
1314 for (num_tmps = 0; num_tmps < max_tmps; num_tmps++)
1318 tmp_info[num_tmps].load = AS2(mov%L0,%1,%2);
1319 tmp_info[num_tmps].store = AS2(mov%L0,%2,%0);
1320 tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset);
1321 tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset);
1325 else if (length >= 2)
1327 tmp_info[num_tmps].load = AS2(mov%W0,%1,%2);
1328 tmp_info[num_tmps].store = AS2(mov%W0,%2,%0);
1329 tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset);
1330 tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset);
1338 for (i = 0; i < num_tmps; i++)
1339 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1341 for (i = 0; i < num_tmps; i++)
1342 output_asm_insn (tmp_info[i].store, tmp_info[i].xops);
1347 xops[0] = adj_offsettable_operand (dest, offset);
1348 xops[1] = adj_offsettable_operand (src, offset);
1350 output_asm_insn (AS2(mov%B0,%1,%2), xops);
1351 output_asm_insn (AS2(mov%B0,%2,%0), xops);
1359 standard_80387_constant_p (x)
1362 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
1367 if (setjmp (handler))
1370 set_float_handler (handler);
1371 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1372 is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d);
1373 is1 = REAL_VALUES_EQUAL (d, dconst1);
1374 set_float_handler (NULL_PTR);
1382 /* Note that on the 80387, other constants, such as pi,
1383 are much slower to load as standard constants
1384 than to load from doubles in memory! */
1391 output_move_const_single (operands)
1394 if (FP_REG_P (operands[0]))
1396 int conval = standard_80387_constant_p (operands[1]);
1404 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1406 REAL_VALUE_TYPE r; long l;
1408 if (GET_MODE (operands[1]) == XFmode)
1411 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1412 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1413 operands[1] = GEN_INT (l);
1415 return singlemove_string (operands);
1418 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1419 reference and a constant. */
1422 symbolic_operand (op, mode)
1424 enum machine_mode mode;
1426 switch (GET_CODE (op))
1433 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1434 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1435 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1441 /* Test for a valid operand for a call instruction.
1442 Don't allow the arg pointer register or virtual regs
1443 since they may change into reg + const, which the patterns
1444 can't handle yet. */
1447 call_insn_operand (op, mode)
1449 enum machine_mode mode;
1451 if (GET_CODE (op) == MEM
1452 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
1453 /* This makes a difference for PIC. */
1454 && general_operand (XEXP (op, 0), Pmode))
1455 || (GET_CODE (XEXP (op, 0)) == REG
1456 && XEXP (op, 0) != arg_pointer_rtx
1457 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1458 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1463 /* Like call_insn_operand but allow (mem (symbol_ref ...))
1467 expander_call_insn_operand (op, mode)
1469 enum machine_mode mode;
1471 if (GET_CODE (op) == MEM
1472 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
1473 || (GET_CODE (XEXP (op, 0)) == REG
1474 && XEXP (op, 0) != arg_pointer_rtx
1475 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1476 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1481 /* Return 1 if OP is a comparison operator that can use the condition code
1482 generated by an arithmetic operation. */
1485 arithmetic_comparison_operator (op, mode)
1487 enum machine_mode mode;
1491 if (mode != VOIDmode && mode != GET_MODE (op))
1493 code = GET_CODE (op);
1494 if (GET_RTX_CLASS (code) != '<')
1497 return (code != GT && code != LE);
1500 /* Returns 1 if OP contains a symbol reference */
1503 symbolic_reference_mentioned_p (op)
1509 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1512 fmt = GET_RTX_FORMAT (GET_CODE (op));
1513 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1519 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1520 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1523 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1530 /* Attempt to expand a binary operator. Make the expansion closer to the
1531 actual machine, then just general_operand, which will allow 3 separate
1532 memory references (one output, two input) in a single insn. Return
1533 whether the insn fails, or succeeds. */
1536 ix86_expand_binary_operator (code, mode, operands)
1538 enum machine_mode mode;
1545 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
1546 if (GET_RTX_CLASS (code) == 'c'
1547 && (rtx_equal_p (operands[0], operands[2])
1548 || immediate_operand (operands[1], mode)))
1550 rtx temp = operands[1];
1551 operands[1] = operands[2];
1555 /* If optimizing, copy to regs to improve CSE */
1556 if (TARGET_PSEUDO && optimize && ((reload_in_progress | reload_completed) == 0))
1558 if (GET_CODE (operands[1]) == MEM && !rtx_equal_p (operands[0], operands[1]))
1559 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1561 if (GET_CODE (operands[2]) == MEM)
1562 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1564 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1566 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1567 emit_move_insn (temp, operands[1]);
1573 if (!ix86_binary_operator_ok (code, mode, operands))
1575 /* If not optimizing, try to make a valid insn (optimize code previously did
1576 this above to improve chances of CSE) */
1578 if ((!TARGET_PSEUDO || !optimize)
1579 && ((reload_in_progress | reload_completed) == 0)
1580 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM))
1583 if (GET_CODE (operands[1]) == MEM && !rtx_equal_p (operands[0], operands[1]))
1585 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1589 if (GET_CODE (operands[2]) == MEM)
1591 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1595 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1597 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1598 emit_move_insn (temp, operands[1]);
1603 if (modified && !ix86_binary_operator_ok (code, mode, operands))
1613 /* Return TRUE or FALSE depending on whether the binary operator meets the
1614 appropriate constraints. */
1617 ix86_binary_operator_ok (code, mode, operands)
1619 enum machine_mode mode;
1622 return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
1623 && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c');
1626 /* Attempt to expand a unary operator. Make the expansion closer to the
1627 actual machine, then just general_operand, which will allow 2 separate
1628 memory references (one output, one input) in a single insn. Return
1629 whether the insn fails, or succeeds. */
1632 ix86_expand_unary_operator (code, mode, operands)
1634 enum machine_mode mode;
1639 /* If optimizing, copy to regs to improve CSE */
1642 && ((reload_in_progress | reload_completed) == 0)
1643 && GET_CODE (operands[1]) == MEM)
1645 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1648 if (!ix86_unary_operator_ok (code, mode, operands))
1650 if ((!TARGET_PSEUDO || !optimize)
1651 && ((reload_in_progress | reload_completed) == 0)
1652 && GET_CODE (operands[1]) == MEM)
1654 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1655 if (!ix86_unary_operator_ok (code, mode, operands))
1665 /* Return TRUE or FALSE depending on whether the unary operator meets the
1666 appropriate constraints. */
1669 ix86_unary_operator_ok (code, mode, operands)
1671 enum machine_mode mode;
1679 static rtx pic_label_rtx;
1681 /* This function generates code for -fpic that loads %ebx with
1682 with the return address of the caller and then returns. */
1684 asm_output_function_prefix (file, name)
1689 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1690 || current_function_uses_const_pool);
1691 xops[0] = pic_offset_table_rtx;
1692 xops[1] = stack_pointer_rtx;
1694 /* deep branch prediction favors having a return for every call */
1695 if (pic_reg_used && TARGET_DEEP_BRANCH_PREDICTION)
1697 if (pic_label_rtx == 0)
1698 pic_label_rtx = (rtx) gen_label_rtx ();
1699 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (pic_label_rtx));
1700 output_asm_insn ("movl (%1),%0", xops);
1701 output_asm_insn ("ret", xops);
1705 /* Set up the stack and frame (if desired) for the function. */
1708 function_prologue (file, size)
1714 /* This function generates the assembly code for function entry.
1715 FILE is an stdio stream to output the code to.
1716 SIZE is an int: how many units of temporary storage to allocate. */
1719 ix86_expand_prologue ()
1724 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1725 || current_function_uses_const_pool);
1726 long tsize = get_frame_size ();
1728 xops[0] = stack_pointer_rtx;
1729 xops[1] = frame_pointer_rtx;
1730 xops[2] = GEN_INT (tsize);
1731 if (frame_pointer_needed)
1733 emit_insn (gen_rtx (SET, 0,
1734 gen_rtx (MEM, SImode,
1735 gen_rtx (PRE_DEC, SImode, stack_pointer_rtx)),
1736 frame_pointer_rtx));
1737 emit_move_insn (xops[1], xops[0]);
1738 /* output_asm_insn ("push%L1 %1", xops); */
1739 /* output_asm_insn (AS2 (mov%L0,%0,%1), xops); */
1743 emit_insn (gen_rtx (SET, SImode,
1745 gen_rtx (MINUS, SImode,
1749 /* output_asm_insn (AS2 (sub%L0,%2,%0), xops);*/
1751 /* Note If use enter it is NOT reversed args.
1752 This one is not reversed from intel!!
1753 I think enter is slower. Also sdb doesn't like it.
1754 But if you want it the code is:
1756 xops[3] = const0_rtx;
1757 output_asm_insn ("enter %2,%3", xops);
1760 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
1761 for (regno = limit - 1; regno >= 0; regno--)
1762 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1763 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1765 xops[0] = gen_rtx (REG, SImode, regno);
1766 emit_insn (gen_rtx (SET, 0,
1767 gen_rtx (MEM, SImode,
1768 gen_rtx (PRE_DEC, SImode, stack_pointer_rtx)),
1770 /* output_asm_insn ("push%L0 %0", xops);*/
1773 if (pic_reg_used && TARGET_DEEP_BRANCH_PREDICTION)
1775 xops[0] = pic_offset_table_rtx;
1776 if (pic_label_rtx == 0)
1777 pic_label_rtx = (rtx) gen_label_rtx ();
1778 xops[1] = pic_label_rtx;
1780 emit_insn (gen_prologue_get_pc (xops[0], gen_rtx (CONST_INT, Pmode, CODE_LABEL_NUMBER(xops[1]))));
1781 /* output_asm_insn (AS1 (call,%P1), xops);*/
1782 emit_insn (gen_prologue_set_got (xops[0],
1783 gen_rtx (SYMBOL_REF, Pmode, "$_GLOBAL_OFFSET_TABLE_"),
1784 gen_rtx (CONST_INT, Pmode, CODE_LABEL_NUMBER(xops[1]))));
1785 SCHED_GROUP_P (get_last_insn()) = 1;
1786 /* output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_,%0", xops);*/
1788 else if (pic_reg_used)
1790 xops[0] = pic_offset_table_rtx;
1791 xops[1] = (rtx) gen_label_rtx ();
1793 emit_insn (gen_prologue_get_pc (xops[0], gen_rtx (CONST_INT, Pmode, CODE_LABEL_NUMBER(xops[1]))));
1794 SCHED_GROUP_P (get_last_insn()) = 1;
1795 /* output_asm_insn (AS1 (call,%P1), xops);*/
1796 /* ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1]));*/
1797 emit_insn (gen_pop (xops[0]));
1798 /* output_asm_insn (AS1 (pop%L0,%0), xops);*/
1799 emit_insn (gen_prologue_set_got (xops[0],
1800 gen_rtx (SYMBOL_REF, Pmode, "$_GLOBAL_OFFSET_TABLE_"),
1801 gen_rtx (CONST_INT, Pmode, CODE_LABEL_NUMBER (xops[1]))));
1802 SCHED_GROUP_P (get_last_insn()) = 1;
1803 /* output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);*/
1807 /* Restore function stack, frame, and registers. */
1810 function_epilogue (file, size)
1816 /* Return 1 if it is appropriate to emit `ret' instructions in the
1817 body of a function. Do this only if the epilogue is simple, needing a
1818 couple of insns. Prior to reloading, we can't tell how many registers
1819 must be saved, so return 0 then. Return 0 if there is no frame
1820 marker to de-allocate.
1822 If NON_SAVING_SETJMP is defined and true, then it is not possible
1823 for the epilogue to be simple, so return 0. This is a special case
1824 since NON_SAVING_SETJMP will not cause regs_ever_live to change
1825 until final, but jump_optimize may need to know sooner if a
1829 ix86_can_use_return_insn_p ()
1833 int reglimit = (frame_pointer_needed
1834 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
1835 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1836 || current_function_uses_const_pool);
1838 #ifdef NON_SAVING_SETJMP
1839 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
1843 if (! reload_completed)
1846 for (regno = reglimit - 1; regno >= 0; regno--)
1847 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1848 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1851 return nregs == 0 || ! frame_pointer_needed;
1855 /* This function generates the assembly code for function exit.
1856 FILE is an stdio stream to output the code to.
1857 SIZE is an int: how many units of temporary storage to deallocate. */
1860 ix86_expand_epilogue ()
1863 register int nregs, limit;
1866 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1867 || current_function_uses_const_pool);
1868 long tsize = get_frame_size ();
1870 /* Compute the number of registers to pop */
1872 limit = (frame_pointer_needed
1873 ? FRAME_POINTER_REGNUM
1874 : STACK_POINTER_REGNUM);
1878 for (regno = limit - 1; regno >= 0; regno--)
1879 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1880 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1883 /* sp is often unreliable so we must go off the frame pointer,
1886 /* In reality, we may not care if sp is unreliable, because we can
1887 restore the register relative to the frame pointer. In theory,
1888 since each move is the same speed as a pop, and we don't need the
1889 leal, this is faster. For now restore multiple registers the old
1892 offset = -tsize - (nregs * UNITS_PER_WORD);
1894 xops[2] = stack_pointer_rtx;
1896 if (nregs > 1 || ! frame_pointer_needed)
1898 if (frame_pointer_needed)
1900 xops[0] = adj_offsettable_operand (AT_BP (QImode), offset);
1901 emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0)));
1902 /* output_asm_insn (AS2 (lea%L2,%0,%2), xops);*/
1905 for (regno = 0; regno < limit; regno++)
1906 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1907 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1909 xops[0] = gen_rtx (REG, SImode, regno);
1910 emit_insn (gen_pop (xops[0]));
1911 /* output_asm_insn ("pop%L0 %0", xops);*/
1915 for (regno = 0; regno < limit; regno++)
1916 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1917 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1919 xops[0] = gen_rtx (REG, SImode, regno);
1920 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
1921 emit_move_insn (xops[0], xops[1]);
1922 /* output_asm_insn (AS2 (mov%L0,%1,%0), xops);*/
1926 if (frame_pointer_needed)
1928 /* If not an i386, mov & pop is faster than "leave". */
1930 if (TARGET_USE_LEAVE)
1931 emit_insn (gen_leave());
1932 /* output_asm_insn ("leave", xops);*/
1935 xops[0] = frame_pointer_rtx;
1936 xops[1] = stack_pointer_rtx;
1937 emit_insn (gen_epilogue_set_stack_ptr());
1938 /* output_asm_insn (AS2 (mov%L2,%0,%2), xops);*/
1939 emit_insn (gen_pop (xops[0]));
1940 /* output_asm_insn ("pop%L0 %0", xops);*/
1945 /* If there is no frame pointer, we must still release the frame. */
1947 xops[0] = GEN_INT (tsize);
1948 emit_insn (gen_rtx (SET, SImode,
1950 gen_rtx (PLUS, SImode,
1953 /* output_asm_insn (AS2 (add%L2,%0,%2), xops);*/
1956 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
1957 if (profile_block_flag == 2)
1959 FUNCTION_BLOCK_PROFILER_EXIT(file);
1963 if (current_function_pops_args && current_function_args_size)
1965 xops[1] = GEN_INT (current_function_pops_args);
1967 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
1968 asked to pop more, pop return address, do explicit add, and jump
1969 indirectly to the caller. */
1971 if (current_function_pops_args >= 32768)
1973 /* ??? Which register to use here? */
1974 xops[0] = gen_rtx (REG, SImode, 2);
1975 emit_insn (gen_pop (xops[0]));
1976 /* output_asm_insn ("pop%L0 %0", xops);*/
1977 emit_insn (gen_rtx (SET, SImode,
1979 gen_rtx (PLUS, SImode,
1982 /* output_asm_insn (AS2 (add%L2,%1,%2), xops);*/
1983 emit_jump_insn (xops[0]);
1984 /* output_asm_insn ("jmp %*%0", xops);*/
1987 emit_jump_insn (gen_return_pop_internal (xops[1]));
1988 /* output_asm_insn ("ret %1", xops);*/
1991 /* output_asm_insn ("ret", xops);*/
1992 emit_jump_insn (gen_return_internal ());
1996 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1997 that is a valid memory address for an instruction.
1998 The MODE argument is the machine mode for the MEM expression
1999 that wants to use this address.
2001 On x86, legitimate addresses are:
2002 base movl (base),reg
2003 displacement movl disp,reg
2004 base + displacement movl disp(base),reg
2005 index + base movl (base,index),reg
2006 (index + base) + displacement movl disp(base,index),reg
2007 index*scale movl (,index,scale),reg
2008 index*scale + disp movl disp(,index,scale),reg
2009 index*scale + base movl (base,index,scale),reg
2010 (index*scale + base) + disp movl disp(base,index,scale),reg
2012 In each case, scale can be 1, 2, 4, 8. */
2014 /* This is exactly the same as print_operand_addr, except that
2015 it recognizes addresses instead of printing them.
2017 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2018 convert common non-canonical forms to canonical form so that they will
2021 #define ADDR_INVALID(msg,insn) \
2023 if (TARGET_DEBUG_ADDR) \
2025 fprintf (stderr, msg); \
2031 legitimate_address_p (mode, addr, strict)
2032 enum machine_mode mode;
2036 rtx base = NULL_RTX;
2037 rtx indx = NULL_RTX;
2038 rtx scale = NULL_RTX;
2039 rtx disp = NULL_RTX;
2041 if (TARGET_DEBUG_ADDR)
2044 "\n==========\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
2045 GET_MODE_NAME (mode), strict);
2050 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
2051 base = addr; /* base reg */
2053 else if (GET_CODE (addr) == PLUS)
2055 rtx op0 = XEXP (addr, 0);
2056 rtx op1 = XEXP (addr, 1);
2057 enum rtx_code code0 = GET_CODE (op0);
2058 enum rtx_code code1 = GET_CODE (op1);
2060 if (code0 == REG || code0 == SUBREG)
2062 if (code1 == REG || code1 == SUBREG)
2064 indx = op0; /* index + base */
2070 base = op0; /* base + displacement */
2075 else if (code0 == MULT)
2077 indx = XEXP (op0, 0);
2078 scale = XEXP (op0, 1);
2080 if (code1 == REG || code1 == SUBREG)
2081 base = op1; /* index*scale + base */
2084 disp = op1; /* index*scale + disp */
2087 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
2089 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */
2090 scale = XEXP (XEXP (op0, 0), 1);
2091 base = XEXP (op0, 1);
2095 else if (code0 == PLUS)
2097 indx = XEXP (op0, 0); /* index + base + disp */
2098 base = XEXP (op0, 1);
2104 ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
2109 else if (GET_CODE (addr) == MULT)
2111 indx = XEXP (addr, 0); /* index*scale */
2112 scale = XEXP (addr, 1);
2116 disp = addr; /* displacement */
2118 /* Allow arg pointer and stack pointer as index if there is not scaling */
2119 if (base && indx && !scale
2120 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
2127 /* Validate base register */
2128 /* Don't allow SUBREG's here, it can lead to spill failures when the base
2129 is one word out of a two word structure, which is represented internally
2133 if (GET_CODE (base) != REG)
2135 ADDR_INVALID ("Base is not a register.\n", base);
2139 if ((strict && !REG_OK_FOR_BASE_STRICT_P (base))
2140 || (!strict && !REG_OK_FOR_BASE_NONSTRICT_P (base)))
2142 ADDR_INVALID ("Base is not valid.\n", base);
2147 /* Validate index register */
2148 /* Don't allow SUBREG's here, it can lead to spill failures when the index
2149 is one word out of a two word structure, which is represented internally
2153 if (GET_CODE (indx) != REG)
2155 ADDR_INVALID ("Index is not a register.\n", indx);
2159 if ((strict && !REG_OK_FOR_INDEX_STRICT_P (indx))
2160 || (!strict && !REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
2162 ADDR_INVALID ("Index is not valid.\n", indx);
2167 abort (); /* scale w/o index invalid */
2169 /* Validate scale factor */
2172 HOST_WIDE_INT value;
2174 if (GET_CODE (scale) != CONST_INT)
2176 ADDR_INVALID ("Scale is not valid.\n", scale);
2180 value = INTVAL (scale);
2181 if (value != 1 && value != 2 && value != 4 && value != 8)
2183 ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
2188 /* Validate displacement
2189 Constant pool addresses must be handled special. They are
2190 considered legitimate addresses, but only if not used with regs.
2191 When printed, the output routines know to print the reference with the
2192 PIC reg, even though the PIC reg doesn't appear in the RTL. */
2195 if (GET_CODE (disp) == SYMBOL_REF
2196 && CONSTANT_POOL_ADDRESS_P (disp)
2201 else if (!CONSTANT_ADDRESS_P (disp))
2203 ADDR_INVALID ("Displacement is not valid.\n", disp);
2207 else if (GET_CODE (disp) == CONST_DOUBLE)
2209 ADDR_INVALID ("Displacement is a const_double.\n", disp);
2213 else if (flag_pic && SYMBOLIC_CONST (disp)
2214 && base != pic_offset_table_rtx
2215 && (indx != pic_offset_table_rtx || scale != NULL_RTX))
2217 ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp);
2221 else if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp)
2222 && (base != NULL_RTX || indx != NULL_RTX))
2224 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", disp);
2229 if (TARGET_DEBUG_ADDR)
2230 fprintf (stderr, "Address is valid.\n");
2232 /* Everything looks valid, return true */
2237 /* Return a legitimate reference for ORIG (an address) using the
2238 register REG. If REG is 0, a new pseudo is generated.
2240 There are three types of references that must be handled:
2242 1. Global data references must load the address from the GOT, via
2243 the PIC reg. An insn is emitted to do this load, and the reg is
2246 2. Static data references must compute the address as an offset
2247 from the GOT, whose base is in the PIC reg. An insn is emitted to
2248 compute the address into a reg, and the reg is returned. Static
2249 data objects have SYMBOL_REF_FLAG set to differentiate them from
2250 global data objects.
2252 3. Constant pool addresses must be handled special. They are
2253 considered legitimate addresses, but only if not used with regs.
2254 When printed, the output routines know to print the reference with the
2255 PIC reg, even though the PIC reg doesn't appear in the RTL.
2257 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2258 reg also appears in the address (except for constant pool references,
2261 "switch" statements also require special handling when generating
2262 PIC code. See comments by the `casesi' insn in i386.md for details. */
2265 legitimize_pic_address (orig, reg)
2272 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
2274 if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr))
2279 reg = gen_reg_rtx (Pmode);
2281 if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr))
2282 || GET_CODE (addr) == LABEL_REF)
2283 new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig);
2285 new = gen_rtx (MEM, Pmode,
2286 gen_rtx (PLUS, Pmode,
2287 pic_offset_table_rtx, orig));
2289 emit_move_insn (reg, new);
2291 current_function_uses_pic_offset_table = 1;
2294 else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
2298 if (GET_CODE (addr) == CONST)
2300 addr = XEXP (addr, 0);
2301 if (GET_CODE (addr) != PLUS)
2305 if (XEXP (addr, 0) == pic_offset_table_rtx)
2309 reg = gen_reg_rtx (Pmode);
2311 base = legitimize_pic_address (XEXP (addr, 0), reg);
2312 addr = legitimize_pic_address (XEXP (addr, 1),
2313 base == reg ? NULL_RTX : reg);
2315 if (GET_CODE (addr) == CONST_INT)
2316 return plus_constant (base, INTVAL (addr));
2318 if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
2320 base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0));
2321 addr = XEXP (addr, 1);
2323 return gen_rtx (PLUS, Pmode, base, addr);
2329 /* Emit insns to move operands[1] into operands[0]. */
2332 emit_pic_move (operands, mode)
2334 enum machine_mode mode;
2336 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
2338 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
2339 operands[1] = (rtx) force_reg (SImode, operands[1]);
2341 operands[1] = legitimize_pic_address (operands[1], temp);
2345 /* Try machine-dependent ways of modifying an illegitimate address
2346 to be legitimate. If we find one, return the new, valid address.
2347 This macro is used in only one place: `memory_address' in explow.c.
2349 OLDX is the address as it was before break_out_memory_refs was called.
2350 In some cases it is useful to look at this to decide what needs to be done.
2352 MODE and WIN are passed so that this macro can use
2353 GO_IF_LEGITIMATE_ADDRESS.
2355 It is always safe for this macro to do nothing. It exists to recognize
2356 opportunities to optimize the output.
2358 For the 80386, we handle X+REG by loading X into a register R and
2359 using R+REG. R will go in a general reg and indexing will be used.
2360 However, if REG is a broken-out memory address or multiplication,
2361 nothing needs to be done because REG can certainly go in a general reg.
2363 When -fpic is used, special handling is needed for symbolic references.
2364 See comments by legitimize_pic_address in i386.c for details. */
2367 legitimize_address (x, oldx, mode)
2370 enum machine_mode mode;
2375 if (TARGET_DEBUG_ADDR)
2377 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", GET_MODE_NAME (mode));
2381 if (flag_pic && SYMBOLIC_CONST (x))
2382 return legitimize_pic_address (x, 0);
2384 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2385 if (GET_CODE (x) == ASHIFT
2386 && GET_CODE (XEXP (x, 1)) == CONST_INT
2387 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
2390 x = gen_rtx (MULT, Pmode,
2391 force_reg (Pmode, XEXP (x, 0)),
2392 GEN_INT (1 << log));
2395 if (GET_CODE (x) == PLUS)
2397 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2398 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2399 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2400 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
2403 XEXP (x, 0) = gen_rtx (MULT, Pmode,
2404 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
2405 GEN_INT (1 << log));
2408 if (GET_CODE (XEXP (x, 1)) == ASHIFT
2409 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2410 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
2413 XEXP (x, 1) = gen_rtx (MULT, Pmode,
2414 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
2415 GEN_INT (1 << log));
2418 /* Put multiply first if it isn't already */
2419 if (GET_CODE (XEXP (x, 1)) == MULT)
2421 rtx tmp = XEXP (x, 0);
2422 XEXP (x, 0) = XEXP (x, 1);
2427 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2428 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2429 created by virtual register instantiation, register elimination, and
2430 similar optimizations. */
2431 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
2434 x = gen_rtx (PLUS, Pmode,
2435 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
2436 XEXP (XEXP (x, 1), 1));
2439 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2440 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2441 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2442 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2443 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2444 && CONSTANT_P (XEXP (x, 1)))
2446 rtx constant, other;
2448 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2450 constant = XEXP (x, 1);
2451 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2453 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2455 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2456 other = XEXP (x, 1);
2464 x = gen_rtx (PLUS, Pmode,
2465 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
2466 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2467 plus_constant (other, INTVAL (constant)));
2471 if (changed && legitimate_address_p (mode, x, FALSE))
2474 if (GET_CODE (XEXP (x, 0)) == MULT)
2477 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
2480 if (GET_CODE (XEXP (x, 1)) == MULT)
2483 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
2487 && GET_CODE (XEXP (x, 1)) == REG
2488 && GET_CODE (XEXP (x, 0)) == REG)
2491 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
2494 x = legitimize_pic_address (x, 0);
2497 if (changed && legitimate_address_p (mode, x, FALSE))
2500 if (GET_CODE (XEXP (x, 0)) == REG)
2502 register rtx temp = gen_reg_rtx (Pmode);
2503 register rtx val = force_operand (XEXP (x, 1), temp);
2505 emit_move_insn (temp, val);
2511 else if (GET_CODE (XEXP (x, 1)) == REG)
2513 register rtx temp = gen_reg_rtx (Pmode);
2514 register rtx val = force_operand (XEXP (x, 0), temp);
2516 emit_move_insn (temp, val);
2527 /* Print an integer constant expression in assembler syntax. Addition
2528 and subtraction are the only arithmetic that may appear in these
2529 expressions. FILE is the stdio stream to write to, X is the rtx, and
2530 CODE is the operand print code from the output string. */
2533 output_pic_addr_const (file, x, code)
2540 switch (GET_CODE (x))
2551 if (GET_CODE (x) == SYMBOL_REF)
2552 assemble_name (file, XSTR (x, 0));
2555 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
2556 CODE_LABEL_NUMBER (XEXP (x, 0)));
2557 assemble_name (asm_out_file, buf);
2560 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
2561 fprintf (file, "@GOTOFF(%%ebx)");
2562 else if (code == 'P')
2563 fprintf (file, "@PLT");
2564 else if (GET_CODE (x) == LABEL_REF)
2565 fprintf (file, "@GOTOFF");
2566 else if (! SYMBOL_REF_FLAG (x))
2567 fprintf (file, "@GOT");
2569 fprintf (file, "@GOTOFF");
2574 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
2575 assemble_name (asm_out_file, buf);
2579 fprintf (file, "%d", INTVAL (x));
2583 /* This used to output parentheses around the expression,
2584 but that does not work on the 386 (either ATT or BSD assembler). */
2585 output_pic_addr_const (file, XEXP (x, 0), code);
2589 if (GET_MODE (x) == VOIDmode)
2591 /* We can use %d if the number is <32 bits and positive. */
2592 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
2593 fprintf (file, "0x%x%08x",
2594 CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x));
2596 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
2599 /* We can't handle floating point constants;
2600 PRINT_OPERAND must handle them. */
2601 output_operand_lossage ("floating constant misused");
2605 /* Some assemblers need integer constants to appear last (eg masm). */
2606 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
2608 output_pic_addr_const (file, XEXP (x, 1), code);
2609 if (INTVAL (XEXP (x, 0)) >= 0)
2610 fprintf (file, "+");
2611 output_pic_addr_const (file, XEXP (x, 0), code);
2615 output_pic_addr_const (file, XEXP (x, 0), code);
2616 if (INTVAL (XEXP (x, 1)) >= 0)
2617 fprintf (file, "+");
2618 output_pic_addr_const (file, XEXP (x, 1), code);
2623 output_pic_addr_const (file, XEXP (x, 0), code);
2624 fprintf (file, "-");
2625 output_pic_addr_const (file, XEXP (x, 1), code);
2629 output_operand_lossage ("invalid expression as operand");
2634 /* Append the correct conditional move suffix which corresponds to CODE */
2637 put_condition_code (code, file)
2644 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
2650 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
2656 fputs ("ge", file); return;
2658 fputs ("g", file); return;
2660 fputs ("le", file); return;
2662 fputs ("l", file); return;
2664 fputs ("ae", file); return;
2666 fputs ("a", file); return;
2668 fputs ("be", file); return;
2670 fputs ("b", file); return;
2671 default: output_operand_lossage ("Invalid %%C operand");
2676 f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
2677 D,L,W,B,Q,S -- print the opcode suffix for specified size of operand.
2678 C -- print opcode suffix for set/cmov insn.
2679 N -- like C, but print reversed condition
2680 R -- print the prefix for register names.
2681 z -- print the opcode suffix for the size of the current operand.
2682 * -- print a star (in certain assembler syntax)
2683 w -- print the operand as if it's a "word" (HImode) even if it isn't.
2684 c -- don't print special prefixes before constant operands.
2685 J -- print the appropriate jump operand.
2686 s -- print a shift double count, followed by the assemblers argument
2691 print_operand (file, x, code)
2706 PUT_OP_SIZE (code, 'l', file);
2710 PUT_OP_SIZE (code, 'w', file);
2714 PUT_OP_SIZE (code, 'b', file);
2718 PUT_OP_SIZE (code, 'l', file);
2722 PUT_OP_SIZE (code, 's', file);
2726 PUT_OP_SIZE (code, 't', file);
2730 /* 387 opcodes don't get size suffixes if the operands are
2733 if (STACK_REG_P (x))
2736 /* this is the size of op from size of operand */
2737 switch (GET_MODE_SIZE (GET_MODE (x)))
2740 PUT_OP_SIZE ('B', 'b', file);
2744 PUT_OP_SIZE ('W', 'w', file);
2748 if (GET_MODE (x) == SFmode)
2750 PUT_OP_SIZE ('S', 's', file);
2754 PUT_OP_SIZE ('L', 'l', file);
2758 PUT_OP_SIZE ('T', 't', file);
2762 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
2764 #ifdef GAS_MNEMONICS
2765 PUT_OP_SIZE ('Q', 'q', file);
2768 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
2772 PUT_OP_SIZE ('Q', 'l', file);
2785 switch (GET_CODE (x))
2787 /* These conditions are appropriate for testing the result
2788 of an arithmetic operation, not for a compare operation.
2789 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume
2790 CC_Z_IN_NOT_C false and not floating point. */
2791 case NE: fputs ("jne", file); return;
2792 case EQ: fputs ("je", file); return;
2793 case GE: fputs ("jns", file); return;
2794 case LT: fputs ("js", file); return;
2795 case GEU: fputs ("jmp", file); return;
2796 case GTU: fputs ("jne", file); return;
2797 case LEU: fputs ("je", file); return;
2798 case LTU: fputs ("#branch never", file); return;
2800 /* no matching branches for GT nor LE */
2805 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
2807 PRINT_OPERAND (file, x, 0);
2808 fputs (AS2C (,) + 1, file);
2812 /* This is used by the conditional move instructions. */
2814 put_condition_code (GET_CODE (x), file);
2816 /* like above, but reverse condition */
2818 put_condition_code (reverse_condition (GET_CODE (x)), file);
2825 sprintf (str, "invalid operand code `%c'", code);
2826 output_operand_lossage (str);
2830 if (GET_CODE (x) == REG)
2832 PRINT_REG (x, code, file);
2834 else if (GET_CODE (x) == MEM)
2836 PRINT_PTR (x, file);
2837 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
2840 output_pic_addr_const (file, XEXP (x, 0), code);
2842 output_addr_const (file, XEXP (x, 0));
2845 output_address (XEXP (x, 0));
2847 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
2849 REAL_VALUE_TYPE r; long l;
2850 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2851 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2852 PRINT_IMMED_PREFIX (file);
2853 fprintf (file, "0x%x", l);
2855 /* These float cases don't actually occur as immediate operands. */
2856 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
2858 REAL_VALUE_TYPE r; char dstr[30];
2859 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2860 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
2861 fprintf (file, "%s", dstr);
2863 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
2865 REAL_VALUE_TYPE r; char dstr[30];
2866 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2867 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
2868 fprintf (file, "%s", dstr);
2874 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2875 PRINT_IMMED_PREFIX (file);
2876 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
2877 || GET_CODE (x) == LABEL_REF)
2878 PRINT_OFFSET_PREFIX (file);
2881 output_pic_addr_const (file, x, code);
2883 output_addr_const (file, x);
2887 /* Print a memory operand whose address is ADDR. */
2890 print_operand_address (file, addr)
2894 register rtx reg1, reg2, breg, ireg;
2897 switch (GET_CODE (addr))
2901 fprintf (file, "%se", RP);
2902 fputs (hi_reg_name[REGNO (addr)], file);
2912 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
2914 offset = XEXP (addr, 0);
2915 addr = XEXP (addr, 1);
2917 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
2919 offset = XEXP (addr, 1);
2920 addr = XEXP (addr, 0);
2922 if (GET_CODE (addr) != PLUS) ;
2923 else if (GET_CODE (XEXP (addr, 0)) == MULT)
2925 reg1 = XEXP (addr, 0);
2926 addr = XEXP (addr, 1);
2928 else if (GET_CODE (XEXP (addr, 1)) == MULT)
2930 reg1 = XEXP (addr, 1);
2931 addr = XEXP (addr, 0);
2933 else if (GET_CODE (XEXP (addr, 0)) == REG)
2935 reg1 = XEXP (addr, 0);
2936 addr = XEXP (addr, 1);
2938 else if (GET_CODE (XEXP (addr, 1)) == REG)
2940 reg1 = XEXP (addr, 1);
2941 addr = XEXP (addr, 0);
2943 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
2945 if (reg1 == 0) reg1 = addr;
2951 if (addr != 0) abort ();
2954 if ((reg1 && GET_CODE (reg1) == MULT)
2955 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
2960 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
2966 if (ireg != 0 || breg != 0)
2973 output_pic_addr_const (file, addr, 0);
2975 else if (GET_CODE (addr) == LABEL_REF)
2976 output_asm_label (addr);
2979 output_addr_const (file, addr);
2982 if (ireg != 0 && GET_CODE (ireg) == MULT)
2984 scale = INTVAL (XEXP (ireg, 1));
2985 ireg = XEXP (ireg, 0);
2988 /* The stack pointer can only appear as a base register,
2989 never an index register, so exchange the regs if it is wrong. */
2991 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
3000 /* output breg+ireg*scale */
3001 PRINT_B_I_S (breg, ireg, scale, file);
3008 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
3010 scale = INTVAL (XEXP (addr, 0));
3011 ireg = XEXP (addr, 1);
3015 scale = INTVAL (XEXP (addr, 1));
3016 ireg = XEXP (addr, 0);
3018 output_addr_const (file, const0_rtx);
3019 PRINT_B_I_S ((rtx) 0, ireg, scale, file);
3024 if (GET_CODE (addr) == CONST_INT
3025 && INTVAL (addr) < 0x8000
3026 && INTVAL (addr) >= -0x8000)
3027 fprintf (file, "%d", INTVAL (addr));
3031 output_pic_addr_const (file, addr, 0);
3033 output_addr_const (file, addr);
3038 /* Set the cc_status for the results of an insn whose pattern is EXP.
3039 On the 80386, we assume that only test and compare insns, as well
3040 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT,
3041 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
3042 Also, we assume that jumps, moves and sCOND don't affect the condition
3043 codes. All else clobbers the condition codes, by assumption.
3045 We assume that ALL integer add, minus, etc. instructions effect the
3046 condition codes. This MUST be consistent with i386.md.
3048 We don't record any float test or compare - the redundant test &
3049 compare check in final.c does not handle stack-like regs correctly. */
3052 notice_update_cc (exp)
3055 if (GET_CODE (exp) == SET)
3057 /* Jumps do not alter the cc's. */
3058 if (SET_DEST (exp) == pc_rtx)
3060 #ifdef IS_STACK_MODE
3061 /* Moving into a memory of stack_mode may have been moved
3062 in between the use and set of cc0 by loop_spl(). So
3063 old value of cc.status must be retained */
3064 if(GET_CODE(SET_DEST(exp))==MEM
3065 && IS_STACK_MODE(GET_MODE(SET_DEST(exp))))
3070 /* Moving register or memory into a register:
3071 it doesn't alter the cc's, but it might invalidate
3072 the RTX's which we remember the cc's came from.
3073 (Note that moving a constant 0 or 1 MAY set the cc's). */
3074 if (REG_P (SET_DEST (exp))
3075 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
3076 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
3078 if (cc_status.value1
3079 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3080 cc_status.value1 = 0;
3081 if (cc_status.value2
3082 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3083 cc_status.value2 = 0;
3086 /* Moving register into memory doesn't alter the cc's.
3087 It may invalidate the RTX's which we remember the cc's came from. */
3088 if (GET_CODE (SET_DEST (exp)) == MEM
3089 && (REG_P (SET_SRC (exp))
3090 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
3092 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
3093 || reg_mentioned_p (SET_DEST (exp), cc_status.value1))
3094 cc_status.value1 = 0;
3095 if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM
3096 || reg_mentioned_p (SET_DEST (exp), cc_status.value2))
3097 cc_status.value2 = 0;
3100 /* Function calls clobber the cc's. */
3101 else if (GET_CODE (SET_SRC (exp)) == CALL)
3106 /* Tests and compares set the cc's in predictable ways. */
3107 else if (SET_DEST (exp) == cc0_rtx)
3110 cc_status.value1 = SET_SRC (exp);
3113 /* Certain instructions effect the condition codes. */
3114 else if (GET_MODE (SET_SRC (exp)) == SImode
3115 || GET_MODE (SET_SRC (exp)) == HImode
3116 || GET_MODE (SET_SRC (exp)) == QImode)
3117 switch (GET_CODE (SET_SRC (exp)))
3119 case ASHIFTRT: case LSHIFTRT:
3121 /* Shifts on the 386 don't set the condition codes if the
3122 shift count is zero. */
3123 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
3128 /* We assume that the CONST_INT is non-zero (this rtx would
3129 have been deleted if it were zero. */
3131 case PLUS: case MINUS: case NEG:
3132 case AND: case IOR: case XOR:
3133 cc_status.flags = CC_NO_OVERFLOW;
3134 cc_status.value1 = SET_SRC (exp);
3135 cc_status.value2 = SET_DEST (exp);
3146 else if (GET_CODE (exp) == PARALLEL
3147 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3149 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
3151 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
3154 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
3155 cc_status.flags |= CC_IN_80387;
3157 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
3168 /* Split one or more DImode RTL references into pairs of SImode
3169 references. The RTL can be REG, offsettable MEM, integer constant, or
3170 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3171 split and "num" is its length. lo_half and hi_half are output arrays
3172 that parallel "operands". */
3175 split_di (operands, num, lo_half, hi_half)
3178 rtx lo_half[], hi_half[];
3182 if (GET_CODE (operands[num]) == REG)
3184 lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]));
3185 hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1);
3187 else if (CONSTANT_P (operands[num]))
3189 split_double (operands[num], &lo_half[num], &hi_half[num]);
3191 else if (offsettable_memref_p (operands[num]))
3193 lo_half[num] = operands[num];
3194 hi_half[num] = adj_offsettable_operand (operands[num], 4);
3201 /* Return 1 if this is a valid binary operation on a 387.
3202 OP is the expression matched, and MODE is its mode. */
3205 binary_387_op (op, mode)
3207 enum machine_mode mode;
3209 if (mode != VOIDmode && mode != GET_MODE (op))
3212 switch (GET_CODE (op))
3218 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
3226 /* Return 1 if this is a valid shift or rotate operation on a 386.
3227 OP is the expression matched, and MODE is its mode. */
3232 enum machine_mode mode;
3234 rtx operand = XEXP (op, 0);
3236 if (mode != VOIDmode && mode != GET_MODE (op))
3239 if (GET_MODE (operand) != GET_MODE (op)
3240 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
3243 return (GET_CODE (op) == ASHIFT
3244 || GET_CODE (op) == ASHIFTRT
3245 || GET_CODE (op) == LSHIFTRT
3246 || GET_CODE (op) == ROTATE
3247 || GET_CODE (op) == ROTATERT);
3250 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
3251 MODE is not used. */
3254 VOIDmode_compare_op (op, mode)
3256 enum machine_mode mode;
3258 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
3261 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
3262 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
3263 is the expression of the binary operation. The output may either be
3264 emitted here, or returned to the caller, like all output_* functions.
3266 There is no guarantee that the operands are the same mode, as they
3267 might be within FLOAT or FLOAT_EXTEND expressions. */
3270 output_387_binary_op (insn, operands)
3276 static char buf[100];
3278 switch (GET_CODE (operands[3]))
3281 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
3282 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
3289 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
3290 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
3297 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
3298 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
3305 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
3306 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
3316 strcpy (buf, base_op);
3318 switch (GET_CODE (operands[3]))
3322 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
3325 operands[2] = operands[1];
3329 if (GET_CODE (operands[2]) == MEM)
3330 return strcat (buf, AS1 (%z2,%2));
3332 if (NON_STACK_REG_P (operands[1]))
3334 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
3337 else if (NON_STACK_REG_P (operands[2]))
3339 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
3343 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3344 return strcat (buf, AS2 (p,%2,%0));
3346 if (STACK_TOP_P (operands[0]))
3347 return strcat (buf, AS2C (%y2,%0));
3349 return strcat (buf, AS2C (%2,%0));
3353 if (GET_CODE (operands[1]) == MEM)
3354 return strcat (buf, AS1 (r%z1,%1));
3356 if (GET_CODE (operands[2]) == MEM)
3357 return strcat (buf, AS1 (%z2,%2));
3359 if (NON_STACK_REG_P (operands[1]))
3361 output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
3364 else if (NON_STACK_REG_P (operands[2]))
3366 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
3370 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
3373 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3374 return strcat (buf, AS2 (rp,%2,%0));
3376 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3377 return strcat (buf, AS2 (p,%1,%0));
3379 if (STACK_TOP_P (operands[0]))
3381 if (STACK_TOP_P (operands[1]))
3382 return strcat (buf, AS2C (%y2,%0));
3384 return strcat (buf, AS2 (r,%y1,%0));
3386 else if (STACK_TOP_P (operands[1]))
3387 return strcat (buf, AS2C (%1,%0));
3389 return strcat (buf, AS2 (r,%2,%0));
3396 /* Output code for INSN to convert a float to a signed int. OPERANDS
3397 are the insn operands. The output may be SFmode or DFmode and the
3398 input operand may be SImode or DImode. As a special case, make sure
3399 that the 387 stack top dies if the output mode is DImode, because the
3400 hardware requires this. */
3403 output_fix_trunc (insn, operands)
3407 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
3410 if (! STACK_TOP_P (operands[1]) ||
3411 (GET_MODE (operands[0]) == DImode && ! stack_top_dies))
3414 xops[0] = GEN_INT (12);
3415 xops[1] = operands[4];
3417 output_asm_insn (AS1 (fnstc%W2,%2), operands);
3418 output_asm_insn (AS2 (mov%L2,%2,%4), operands);
3419 output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
3420 output_asm_insn (AS2 (mov%L4,%4,%3), operands);
3421 output_asm_insn (AS1 (fldc%W3,%3), operands);
3423 if (NON_STACK_REG_P (operands[0]))
3424 output_to_reg (operands[0], stack_top_dies);
3425 else if (GET_CODE (operands[0]) == MEM)
3428 output_asm_insn (AS1 (fistp%z0,%0), operands);
3430 output_asm_insn (AS1 (fist%z0,%0), operands);
3435 return AS1 (fldc%W2,%2);
3438 /* Output code for INSN to compare OPERANDS. The two operands might
3439 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
3440 expression. If the compare is in mode CCFPEQmode, use an opcode that
3441 will not fault if a qNaN is present. */
3444 output_float_compare (insn, operands)
3449 rtx body = XVECEXP (PATTERN (insn), 0, 0);
3450 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
3453 if (! STACK_TOP_P (operands[0]))
3456 operands[0] = operands[1];
3458 cc_status.flags |= CC_REVERSED;
3461 if (! STACK_TOP_P (operands[0]))
3464 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
3466 if (STACK_REG_P (operands[1])
3468 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3469 && REGNO (operands[1]) != FIRST_STACK_REG)
3471 /* If both the top of the 387 stack dies, and the other operand
3472 is also a stack register that dies, then this must be a
3473 `fcompp' float compare */
3475 if (unordered_compare)
3476 output_asm_insn ("fucompp", operands);
3478 output_asm_insn ("fcompp", operands);
3482 static char buf[100];
3484 /* Decide if this is the integer or float compare opcode, or the
3485 unordered float compare. */
3487 if (unordered_compare)
3488 strcpy (buf, "fucom");
3489 else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
3490 strcpy (buf, "fcom");
3492 strcpy (buf, "ficom");
3494 /* Modify the opcode if the 387 stack is to be popped. */
3499 if (NON_STACK_REG_P (operands[1]))
3500 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
3502 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
3505 /* Now retrieve the condition code. */
3507 return output_fp_cc0_set (insn);
3510 /* Output opcodes to transfer the results of FP compare or test INSN
3511 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
3512 result of the compare or test is unordered, no comparison operator
3513 succeeds except NE. Return an output template, if any. */
3516 output_fp_cc0_set (insn)
3520 rtx unordered_label;
3524 xops[0] = gen_rtx (REG, HImode, 0);
3525 output_asm_insn (AS1 (fnsts%W0,%0), xops);
3527 if (! TARGET_IEEE_FP)
3529 if (!(cc_status.flags & CC_REVERSED))
3531 next = next_cc0_user (insn);
3533 if (GET_CODE (next) == JUMP_INSN
3534 && GET_CODE (PATTERN (next)) == SET
3535 && SET_DEST (PATTERN (next)) == pc_rtx
3536 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
3538 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
3540 else if (GET_CODE (PATTERN (next)) == SET)
3542 code = GET_CODE (SET_SRC (PATTERN (next)));
3548 if (code == GT || code == LT || code == EQ || code == NE
3549 || code == LE || code == GE)
3550 { /* We will test eax directly */
3551 cc_status.flags |= CC_TEST_AX;
3558 next = next_cc0_user (insn);
3559 if (next == NULL_RTX)
3562 if (GET_CODE (next) == JUMP_INSN
3563 && GET_CODE (PATTERN (next)) == SET
3564 && SET_DEST (PATTERN (next)) == pc_rtx
3565 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
3567 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
3569 else if (GET_CODE (PATTERN (next)) == SET)
3571 code = GET_CODE (SET_SRC (PATTERN (next)));
3576 xops[0] = gen_rtx (REG, QImode, 0);
3581 xops[1] = GEN_INT (0x45);
3582 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3587 xops[1] = GEN_INT (0x45);
3588 xops[2] = GEN_INT (0x01);
3589 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3590 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
3595 xops[1] = GEN_INT (0x05);
3596 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3601 xops[1] = GEN_INT (0x45);
3602 xops[2] = GEN_INT (0x40);
3603 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3604 output_asm_insn (AS1 (dec%B0,%h0), xops);
3605 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
3610 xops[1] = GEN_INT (0x45);
3611 xops[2] = GEN_INT (0x40);
3612 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3613 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
3618 xops[1] = GEN_INT (0x44);
3619 xops[2] = GEN_INT (0x40);
3620 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3621 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
3635 #define MAX_386_STACK_LOCALS 2
3637 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
3639 /* Define the structure for the machine field in struct function. */
3640 struct machine_function
3642 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
3645 /* Functions to save and restore i386_stack_locals.
3646 These will be called, via pointer variables,
3647 from push_function_context and pop_function_context. */
3650 save_386_machine_status (p)
3653 p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals);
3654 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
3655 sizeof i386_stack_locals);
3659 restore_386_machine_status (p)
3662 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
3663 sizeof i386_stack_locals);
3667 /* Clear stack slot assignments remembered from previous functions.
3668 This is called from INIT_EXPANDERS once before RTL is emitted for each
3672 clear_386_stack_locals ()
3674 enum machine_mode mode;
3677 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
3678 mode = (enum machine_mode) ((int) mode + 1))
3679 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
3680 i386_stack_locals[(int) mode][n] = NULL_RTX;
3682 /* Arrange to save and restore i386_stack_locals around nested functions. */
3683 save_machine_status = save_386_machine_status;
3684 restore_machine_status = restore_386_machine_status;
3687 /* Return a MEM corresponding to a stack slot with mode MODE.
3688 Allocate a new slot if necessary.
3690 The RTL for a function can have several slots available: N is
3691 which slot to use. */
3694 assign_386_stack_local (mode, n)
3695 enum machine_mode mode;
3698 if (n < 0 || n >= MAX_386_STACK_LOCALS)
3701 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
3702 i386_stack_locals[(int) mode][n]
3703 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
3705 return i386_stack_locals[(int) mode][n];
3711 enum machine_mode mode;
3713 return (GET_CODE (op) == MULT);
3718 enum machine_mode mode;
3720 return (GET_CODE (op) == DIV);
3725 /* Create a new copy of an rtx.
3726 Recursively copies the operands of the rtx,
3727 except for those few rtx codes that are sharable.
3728 Doesn't share CONST */
3736 register RTX_CODE code;
3737 register char *format_ptr;
3739 code = GET_CODE (orig);
3752 /* SCRATCH must be shared because they represent distinct values. */
3757 /* CONST can be shared if it contains a SYMBOL_REF. If it contains
3758 a LABEL_REF, it isn't sharable. */
3759 if (GET_CODE (XEXP (orig, 0)) == PLUS
3760 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
3761 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
3765 /* A MEM with a constant address is not sharable. The problem is that
3766 the constant address may need to be reloaded. If the mem is shared,
3767 then reloading one copy of this mem will cause all copies to appear
3768 to have been reloaded. */
3771 copy = rtx_alloc (code);
3772 PUT_MODE (copy, GET_MODE (orig));
3773 copy->in_struct = orig->in_struct;
3774 copy->volatil = orig->volatil;
3775 copy->unchanging = orig->unchanging;
3776 copy->integrated = orig->integrated;
3778 copy->is_spill_rtx = orig->is_spill_rtx;
3780 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
3782 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
3784 switch (*format_ptr++)
3787 XEXP (copy, i) = XEXP (orig, i);
3788 if (XEXP (orig, i) != NULL)
3789 XEXP (copy, i) = copy_rtx (XEXP (orig, i));
3794 XEXP (copy, i) = XEXP (orig, i);
3799 XVEC (copy, i) = XVEC (orig, i);
3800 if (XVEC (orig, i) != NULL)
3802 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
3803 for (j = 0; j < XVECLEN (copy, i); j++)
3804 XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
3809 XWINT (copy, i) = XWINT (orig, i);
3813 XINT (copy, i) = XINT (orig, i);
3818 XSTR (copy, i) = XSTR (orig, i);
3829 /* try to rewrite a memory address to make it valid */
3831 rewrite_address (mem_rtx)
3834 rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
3836 int offset_adjust = 0;
3837 int was_only_offset = 0;
3838 rtx mem_addr = XEXP (mem_rtx, 0);
3839 char *storage = (char *) oballoc (0);
3841 int is_spill_rtx = 0;
3843 in_struct = MEM_IN_STRUCT_P (mem_rtx);
3844 is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
3846 if (GET_CODE (mem_addr) == PLUS &&
3847 GET_CODE (XEXP (mem_addr, 1)) == PLUS &&
3848 GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
3849 { /* this part is utilized by the combiner */
3851 gen_rtx (PLUS, GET_MODE (mem_addr),
3852 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
3854 XEXP (XEXP (mem_addr, 1), 0)),
3855 XEXP (XEXP (mem_addr, 1), 1));
3856 if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
3858 XEXP (mem_rtx, 0) = ret_rtx;
3859 RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
3865 /* this part is utilized by loop.c */
3866 /* If the address contains PLUS (reg,const) and this pattern is invalid
3867 in this case - try to rewrite the address to make it valid intel1
3869 storage = (char *) oballoc (0);
3870 index_rtx = base_rtx = offset_rtx = NULL;
3871 /* find the base index and offset elements of the memory address */
3872 if (GET_CODE (mem_addr) == PLUS)
3874 if (GET_CODE (XEXP (mem_addr, 0)) == REG)
3876 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
3878 base_rtx = XEXP (mem_addr, 1);
3879 index_rtx = XEXP (mem_addr, 0);
3883 base_rtx = XEXP (mem_addr, 0);
3884 offset_rtx = XEXP (mem_addr, 1);
3887 else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
3889 index_rtx = XEXP (mem_addr, 0);
3890 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
3892 base_rtx = XEXP (mem_addr, 1);
3896 offset_rtx = XEXP (mem_addr, 1);
3899 else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
3902 if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS &&
3903 GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT &&
3904 GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0)) == REG &&
3905 GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1)) == CONST_INT &&
3906 GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) == CONST_INT &&
3907 GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG &&
3908 GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
3910 index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
3911 offset_rtx = XEXP (mem_addr, 1);
3912 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
3913 offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
3917 offset_rtx = XEXP (mem_addr, 1);
3918 index_rtx = XEXP (XEXP (mem_addr, 0), 0);
3919 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
3922 else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
3924 was_only_offset = 1;
3927 offset_rtx = XEXP (mem_addr, 1);
3928 offset_adjust = INTVAL (XEXP (mem_addr, 0));
3929 if (offset_adjust == 0)
3931 XEXP (mem_rtx, 0) = offset_rtx;
3932 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
3942 else if (GET_CODE (mem_addr) == MULT)
3944 index_rtx = mem_addr;
3951 if (index_rtx && GET_CODE (index_rtx) == MULT)
3953 if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
3958 scale_rtx = XEXP (index_rtx, 1);
3959 scale = INTVAL (scale_rtx);
3960 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
3962 /* now find which of the elements are invalid and try to fix them */
3963 if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
3965 offset_adjust = INTVAL (index_rtx) * scale;
3966 if (offset_rtx && GET_CODE (offset_rtx) == CONST &&
3967 GET_CODE (XEXP (offset_rtx, 0)) == PLUS)
3969 if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF &&
3970 GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT)
3972 offset_rtx = copy_all_rtx (offset_rtx);
3973 XEXP (XEXP (offset_rtx, 0), 1) =
3974 gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust);
3975 if (!CONSTANT_P (offset_rtx))
3982 else if (offset_rtx && GET_CODE (offset_rtx) == SYMBOL_REF)
3985 gen_rtx (CONST, GET_MODE (offset_rtx),
3986 gen_rtx (PLUS, GET_MODE (offset_rtx),
3988 gen_rtx (CONST_INT, 0, offset_adjust)));
3989 if (!CONSTANT_P (offset_rtx))
3995 else if (offset_rtx && GET_CODE (offset_rtx) == CONST_INT)
3997 offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust);
3999 else if (!offset_rtx)
4001 offset_rtx = gen_rtx (CONST_INT, 0, 0);
4003 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4004 XEXP (mem_rtx, 0) = offset_rtx;
4007 if (base_rtx && GET_CODE (base_rtx) == PLUS &&
4008 GET_CODE (XEXP (base_rtx, 0)) == REG &&
4009 GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
4011 offset_adjust += INTVAL (XEXP (base_rtx, 1));
4012 base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
4014 else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
4016 offset_adjust += INTVAL (base_rtx);
4019 if (index_rtx && GET_CODE (index_rtx) == PLUS &&
4020 GET_CODE (XEXP (index_rtx, 0)) == REG &&
4021 GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
4023 offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
4024 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4028 if (!LEGITIMATE_INDEX_P (index_rtx)
4029 && !(index_rtx == stack_pointer_rtx && scale == 1 && base_rtx == NULL))
4037 if (!LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
4043 if (offset_adjust != 0)
4047 if (GET_CODE (offset_rtx) == CONST &&
4048 GET_CODE (XEXP (offset_rtx, 0)) == PLUS)
4050 if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF &&
4051 GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT)
4053 offset_rtx = copy_all_rtx (offset_rtx);
4054 XEXP (XEXP (offset_rtx, 0), 1) =
4055 gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust);
4056 if (!CONSTANT_P (offset_rtx))
4063 else if (GET_CODE (offset_rtx) == SYMBOL_REF)
4066 gen_rtx (CONST, GET_MODE (offset_rtx),
4067 gen_rtx (PLUS, GET_MODE (offset_rtx),
4069 gen_rtx (CONST_INT, 0, offset_adjust)));
4070 if (!CONSTANT_P (offset_rtx))
4076 else if (GET_CODE (offset_rtx) == CONST_INT)
4078 offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust);
4088 offset_rtx = gen_rtx (CONST_INT, 0, offset_adjust);
4096 if (GET_CODE (offset_rtx) == CONST_INT &&
4097 INTVAL (offset_rtx) == 0)
4099 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
4100 gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
4106 ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx),
4107 gen_rtx (PLUS, GET_MODE (base_rtx),
4108 gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
4116 if (GET_CODE (offset_rtx) == CONST_INT &&
4117 INTVAL (offset_rtx) == 0)
4119 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, base_rtx);
4123 ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx),
4124 gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx,
4134 if (GET_CODE (offset_rtx) == CONST_INT &&
4135 INTVAL (offset_rtx) == 0)
4137 ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, scale_rtx);
4142 gen_rtx (PLUS, GET_MODE (offset_rtx),
4143 gen_rtx (MULT, GET_MODE (index_rtx), index_rtx,
4150 if (GET_CODE (offset_rtx) == CONST_INT &&
4151 INTVAL (offset_rtx) == 0)
4153 ret_rtx = index_rtx;
4157 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, offset_rtx);
4166 if (GET_CODE (offset_rtx) == CONST_INT &&
4167 INTVAL (offset_rtx) == 0)
4173 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx, offset_rtx);
4176 else if (was_only_offset)
4178 ret_rtx = offset_rtx;
4186 XEXP (mem_rtx, 0) = ret_rtx;
4187 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4199 /* return 1 if the first insn to set cc before insn also sets the register
4200 reg_rtx - otherwise return 0 */
4202 last_to_set_cc (reg_rtx, insn)
4205 rtx prev_insn = PREV_INSN (insn);
4209 if (GET_CODE (prev_insn) == NOTE)
4212 else if (GET_CODE (prev_insn) == INSN)
4214 if (GET_CODE (PATTERN (prev_insn)) != SET)
4217 if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
4219 if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
4225 else if (!doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
4232 prev_insn = PREV_INSN (prev_insn);
4240 doesnt_set_condition_code (pat)
4243 switch (GET_CODE (pat))
4257 sets_condition_code (pat)
4260 switch (GET_CODE (pat))
4284 str_immediate_operand (op, mode)
4286 enum machine_mode mode;
4288 if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
4300 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4301 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4302 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4303 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode))
4312 Return 1 if the mode of the SET_DEST of insn is floating point
4313 and it is not an fld or a move from memory to memory.
4314 Otherwise return 0 */
4319 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4320 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4321 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4322 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
4323 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
4324 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
4325 && GET_CODE (SET_SRC (insn)) != MEM)
4334 Return 1 if the mode of the SET_DEST floating point and is memory
4335 and the source is a register.
4341 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4342 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4343 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4344 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
4345 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
4346 && GET_CODE (SET_SRC (PATTERN (insn))) == REG)
4356 Return 1 if dep_insn sets a register which insn uses as a base
4357 or index to reference memory.
4358 otherwise return 0 */
4361 agi_dependent (insn, dep_insn)
4364 if (GET_CODE (dep_insn) == INSN
4365 && GET_CODE (PATTERN (dep_insn)) == SET
4366 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG)
4368 return (reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn));
4371 if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
4372 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
4373 && push_operand (SET_DEST (PATTERN (dep_insn)),
4374 GET_MODE (SET_DEST (PATTERN (dep_insn)))))
4376 return (reg_mentioned_in_mem (stack_pointer_rtx, insn));
4384 Return 1 if reg is used in rtl as a base or index for a memory ref
4385 otherwise return 0. */
4388 reg_mentioned_in_mem (reg, rtl)
4393 register enum rtx_code code;
4398 code = GET_CODE (rtl);
4416 if (code == MEM && reg_mentioned_p (reg, rtl))
4419 fmt = GET_RTX_FORMAT (code);
4420 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4425 for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
4427 if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
4432 else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
4439 /* Output the approprate insns for doing strlen if not just doing repnz; scasb
4441 operands[0] = result, initialized with the startaddress
4442 operands[1] = alignment of the address.
4443 operands[2] = scratch register, initialized with the startaddress when
4444 not aligned, otherwise undefined
4446 This is just the body. It needs the initialisations mentioned above and
4447 some address computing at the end. These things are done in i386.md. */
4450 output_strlen_unroll (operands)
4455 xops[0] = operands[0]; /* Result */
4456 /* operands[1]; * Alignment */
4457 xops[1] = operands[2]; /* Scratch */
4458 xops[2] = GEN_INT (0);
4459 xops[3] = GEN_INT (2);
4460 xops[4] = GEN_INT (3);
4461 xops[5] = GEN_INT (4);
4462 /* xops[6] = gen_label_rtx (); * label when aligned to 3-byte */
4463 /* xops[7] = gen_label_rtx (); * label when aligned to 2-byte */
4464 xops[8] = gen_label_rtx (); /* label of main loop */
4465 if(TARGET_USE_Q_REG && QI_REG_P (xops[1]))
4466 xops[9] = gen_label_rtx (); /* pentium optimisation */
4467 xops[10] = gen_label_rtx (); /* end label 2 */
4468 xops[11] = gen_label_rtx (); /* end label 1 */
4469 xops[12] = gen_label_rtx (); /* end label */
4470 /* xops[13] * Temporary used */
4471 xops[14] = GEN_INT (0xff);
4472 xops[15] = GEN_INT (0xff00);
4473 xops[16] = GEN_INT (0xff0000);
4474 xops[17] = GEN_INT (0xff000000);
4476 /* Loop to check 1..3 bytes for null to get an aligned pointer */
4478 /* is there a known alignment and is it less then 4 */
4479 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4)
4481 /* is there a known alignment and is it not 2 */
4482 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
4484 xops[6] = gen_label_rtx (); /* label when aligned to 3-byte */
4485 xops[7] = gen_label_rtx (); /* label when aligned to 2-byte */
4487 /* leave just the 3 lower bits */
4488 /* if this is a q-register, then the high part is used later */
4489 /* therefore user andl rather than andb */
4490 output_asm_insn (AS2 (and%L1,%4,%1), xops);
4491 /* is aligned to 4-byte adress when zero */
4492 output_asm_insn (AS1 (je,%l8), xops);
4493 /* side-effect even Parity when %eax == 3 */
4494 output_asm_insn (AS1 (jp,%6), xops);
4496 /* is it aligned to 2 bytes ? */
4497 if (QI_REG_P (xops[1]))
4498 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
4500 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
4501 output_asm_insn (AS1 (je,%7), xops);
4505 /* since the alignment is 2, we have to check 2 or 0 bytes */
4507 /* check if is aligned to 4 - byte */
4508 output_asm_insn (AS2 (and%L1,%3,%1), xops);
4509 /* is aligned to 4-byte adress when zero */
4510 output_asm_insn (AS1 (je,%l8), xops);
4513 xops[13] = gen_rtx (MEM, QImode, xops[0]);
4514 /* now, compare the bytes */
4515 /* compare with the high part of a q-reg gives shorter code */
4516 if (QI_REG_P (xops[1]))
4518 /* compare the first n unaligned byte on a byte per byte basis */
4519 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
4520 /* when zero we reached the end */
4521 output_asm_insn (AS1 (je,%l12), xops);
4522 /* increment the address */
4523 output_asm_insn (AS1 (inc%L0,%0), xops);
4525 /* not needed with an alignment of 2 */
4526 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
4528 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[7]));
4529 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
4530 output_asm_insn (AS1 (je,%l12), xops);
4531 output_asm_insn (AS1 (inc%L0,%0), xops);
4533 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[6]));
4535 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
4539 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
4540 output_asm_insn (AS1 (je,%l12), xops);
4541 output_asm_insn (AS1 (inc%L0,%0), xops);
4543 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[7]));
4544 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
4545 output_asm_insn (AS1 (je,%l12), xops);
4546 output_asm_insn (AS1 (inc%L0,%0), xops);
4548 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[6]));
4549 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
4551 output_asm_insn (AS1 (je,%l12), xops);
4552 output_asm_insn (AS1 (inc%L0,%0), xops);
4555 /* Generate loop to check 4 bytes at a time */
4556 /* IMHO it is not a good idea to align this loop. It gives only */
4557 /* huge programs, but does not help to speed up */
4558 /* ASM_OUTPUT_LOOP_ALIGN (asm_out_file); */
4559 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8]));
4561 xops[13] = gen_rtx (MEM, SImode, xops[0]);
4562 output_asm_insn (AS2 (mov%L1,%13,%1), xops);
4564 if (QI_REG_P (xops[1]))
4566 /* On i586 it is faster to combine the hi- and lo- part as
4567 a kind of lookahead. If anding both yields zero, then one
4568 of both *could* be zero, otherwise none of both is zero;
4569 this saves one instruction, on i486 this is slower
4570 tested with P-90, i486DX2-66, AMD486DX2-66 */
4573 output_asm_insn (AS2 (test%B1,%h1,%b1), xops);
4574 output_asm_insn (AS1 (jne,%l9), xops);
4577 /* check first byte */
4578 output_asm_insn (AS2 (test%B1,%b1,%b1), xops);
4579 output_asm_insn (AS1 (je,%l12), xops);
4581 /* check second byte */
4582 output_asm_insn (AS2 (test%B1,%h1,%h1), xops);
4583 output_asm_insn (AS1 (je,%l11), xops);
4586 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[9]));
4590 /* check first byte */
4591 output_asm_insn (AS2 (test%L1,%14,%1), xops);
4592 output_asm_insn (AS1 (je,%l12), xops);
4594 /* check second byte */
4595 output_asm_insn (AS2 (test%L1,%15,%1), xops);
4596 output_asm_insn (AS1 (je,%l11), xops);
4599 /* check third byte */
4600 output_asm_insn (AS2 (test%L1,%16,%1), xops);
4601 output_asm_insn (AS1 (je,%l10), xops);
4603 /* check fourth byte and increment address */
4604 output_asm_insn (AS2 (add%L0,%5,%0), xops);
4605 output_asm_insn (AS2 (test%L1,%17,%1), xops);
4606 output_asm_insn (AS1 (jne,%l8), xops);
4608 /* now generate fixups when the compare stops within a 4-byte word */
4609 output_asm_insn (AS2 (sub%L0,%4,%0), xops);
4611 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10]));
4612 output_asm_insn (AS1 (inc%L0,%0), xops);
4614 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11]));
4615 output_asm_insn (AS1 (inc%L0,%0), xops);
4617 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12]));