1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
51 #include "tree-gimple.h"
54 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs size_cost = { /* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of loading integer registers */
995 2, /* cost of moving MMX register */
996 {6, 6}, /* cost of loading MMX registers
997 in SImode and DImode */
998 {4, 4}, /* cost of storing MMX registers
999 in SImode and DImode */
1000 2, /* cost of moving SSE register */
1001 {6, 6, 6}, /* cost of loading SSE registers
1002 in SImode, DImode and TImode */
1003 {4, 4, 4}, /* cost of storing SSE registers
1004 in SImode, DImode and TImode */
1005 2, /* MMX or SSE register to integer */
1006 32, /* size of l1 cache. */
1007 2048, /* size of l2 cache. */
1008 128, /* size of prefetch block */
1009 8, /* number of parallel prefetches */
1010 3, /* Branch cost */
1011 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1012 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1013 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1014 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1015 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1016 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1017 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1018 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1019 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1020 {{libcall, {{8, loop}, {15, unrolled_loop},
1021 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1022 {libcall, {{24, loop}, {32, unrolled_loop},
1023 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1024 1, /* scalar_stmt_cost. */
1025 1, /* scalar load_cost. */
1026 1, /* scalar_store_cost. */
1027 1, /* vec_stmt_cost. */
1028 1, /* vec_to_scalar_cost. */
1029 1, /* scalar_to_vec_cost. */
1030 1, /* vec_align_load_cost. */
1031 2, /* vec_unalign_load_cost. */
1032 1, /* vec_store_cost. */
1033 3, /* cond_taken_branch_cost. */
1034 1, /* cond_not_taken_branch_cost. */
1037 /* Generic64 should produce code tuned for Nocona and K8. */
1039 struct processor_costs generic64_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 /* On all chips taken into consideration lea is 2 cycles and more. With
1042 this cost however our current implementation of synth_mult results in
1043 use of unnecessary temporary registers causing regression on several
1044 SPECfp benchmarks. */
1045 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1046 COSTS_N_INSNS (1), /* variable shift costs */
1047 COSTS_N_INSNS (1), /* constant shift costs */
1048 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1049 COSTS_N_INSNS (4), /* HI */
1050 COSTS_N_INSNS (3), /* SI */
1051 COSTS_N_INSNS (4), /* DI */
1052 COSTS_N_INSNS (2)}, /* other */
1053 0, /* cost of multiply per each bit set */
1054 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1055 COSTS_N_INSNS (26), /* HI */
1056 COSTS_N_INSNS (42), /* SI */
1057 COSTS_N_INSNS (74), /* DI */
1058 COSTS_N_INSNS (74)}, /* other */
1059 COSTS_N_INSNS (1), /* cost of movsx */
1060 COSTS_N_INSNS (1), /* cost of movzx */
1061 8, /* "large" insn */
1062 17, /* MOVE_RATIO */
1063 4, /* cost for loading QImode using movzbl */
1064 {4, 4, 4}, /* cost of loading integer registers
1065 in QImode, HImode and SImode.
1066 Relative to reg-reg move (2). */
1067 {4, 4, 4}, /* cost of storing integer registers */
1068 4, /* cost of reg,reg fld/fst */
1069 {12, 12, 12}, /* cost of loading fp registers
1070 in SFmode, DFmode and XFmode */
1071 {6, 6, 8}, /* cost of storing fp registers
1072 in SFmode, DFmode and XFmode */
1073 2, /* cost of moving MMX register */
1074 {8, 8}, /* cost of loading MMX registers
1075 in SImode and DImode */
1076 {8, 8}, /* cost of storing MMX registers
1077 in SImode and DImode */
1078 2, /* cost of moving SSE register */
1079 {8, 8, 8}, /* cost of loading SSE registers
1080 in SImode, DImode and TImode */
1081 {8, 8, 8}, /* cost of storing SSE registers
1082 in SImode, DImode and TImode */
1083 5, /* MMX or SSE register to integer */
1084 32, /* size of l1 cache. */
1085 512, /* size of l2 cache. */
1086 64, /* size of prefetch block */
1087 6, /* number of parallel prefetches */
1088 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1089 is increased to perhaps more appropriate value of 5. */
1090 3, /* Branch cost */
1091 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1092 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1093 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1094 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1095 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1096 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1097 {DUMMY_STRINGOP_ALGS,
1098 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 1, /* scalar_stmt_cost. */
1102 1, /* scalar load_cost. */
1103 1, /* scalar_store_cost. */
1104 1, /* vec_stmt_cost. */
1105 1, /* vec_to_scalar_cost. */
1106 1, /* scalar_to_vec_cost. */
1107 1, /* vec_align_load_cost. */
1108 2, /* vec_unalign_load_cost. */
1109 1, /* vec_store_cost. */
1110 3, /* cond_taken_branch_cost. */
1111 1, /* cond_not_taken_branch_cost. */
1114 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1116 struct processor_costs generic32_cost = {
1117 COSTS_N_INSNS (1), /* cost of an add instruction */
1118 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1119 COSTS_N_INSNS (1), /* variable shift costs */
1120 COSTS_N_INSNS (1), /* constant shift costs */
1121 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1122 COSTS_N_INSNS (4), /* HI */
1123 COSTS_N_INSNS (3), /* SI */
1124 COSTS_N_INSNS (4), /* DI */
1125 COSTS_N_INSNS (2)}, /* other */
1126 0, /* cost of multiply per each bit set */
1127 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1128 COSTS_N_INSNS (26), /* HI */
1129 COSTS_N_INSNS (42), /* SI */
1130 COSTS_N_INSNS (74), /* DI */
1131 COSTS_N_INSNS (74)}, /* other */
1132 COSTS_N_INSNS (1), /* cost of movsx */
1133 COSTS_N_INSNS (1), /* cost of movzx */
1134 8, /* "large" insn */
1135 17, /* MOVE_RATIO */
1136 4, /* cost for loading QImode using movzbl */
1137 {4, 4, 4}, /* cost of loading integer registers
1138 in QImode, HImode and SImode.
1139 Relative to reg-reg move (2). */
1140 {4, 4, 4}, /* cost of storing integer registers */
1141 4, /* cost of reg,reg fld/fst */
1142 {12, 12, 12}, /* cost of loading fp registers
1143 in SFmode, DFmode and XFmode */
1144 {6, 6, 8}, /* cost of storing fp registers
1145 in SFmode, DFmode and XFmode */
1146 2, /* cost of moving MMX register */
1147 {8, 8}, /* cost of loading MMX registers
1148 in SImode and DImode */
1149 {8, 8}, /* cost of storing MMX registers
1150 in SImode and DImode */
1151 2, /* cost of moving SSE register */
1152 {8, 8, 8}, /* cost of loading SSE registers
1153 in SImode, DImode and TImode */
1154 {8, 8, 8}, /* cost of storing SSE registers
1155 in SImode, DImode and TImode */
1156 5, /* MMX or SSE register to integer */
1157 32, /* size of l1 cache. */
1158 256, /* size of l2 cache. */
1159 64, /* size of prefetch block */
1160 6, /* number of parallel prefetches */
1161 3, /* Branch cost */
1162 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1163 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1164 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1165 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1166 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1167 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1168 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1169 DUMMY_STRINGOP_ALGS},
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 1, /* scalar_stmt_cost. */
1173 1, /* scalar load_cost. */
1174 1, /* scalar_store_cost. */
1175 1, /* vec_stmt_cost. */
1176 1, /* vec_to_scalar_cost. */
1177 1, /* scalar_to_vec_cost. */
1178 1, /* vec_align_load_cost. */
1179 2, /* vec_unalign_load_cost. */
1180 1, /* vec_store_cost. */
1181 3, /* cond_taken_branch_cost. */
1182 1, /* cond_not_taken_branch_cost. */
1185 const struct processor_costs *ix86_cost = &pentium_cost;
1187 /* Processor feature/optimization bitmasks. */
1188 #define m_386 (1<<PROCESSOR_I386)
1189 #define m_486 (1<<PROCESSOR_I486)
1190 #define m_PENT (1<<PROCESSOR_PENTIUM)
1191 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1192 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1193 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1194 #define m_CORE2 (1<<PROCESSOR_CORE2)
1196 #define m_GEODE (1<<PROCESSOR_GEODE)
1197 #define m_K6 (1<<PROCESSOR_K6)
1198 #define m_K6_GEODE (m_K6 | m_GEODE)
1199 #define m_K8 (1<<PROCESSOR_K8)
1200 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1201 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1202 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1203 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1205 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1206 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1208 /* Generic instruction choice should be common subset of supported CPUs
1209 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1210 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1212 /* Feature tests against the various tunings. */
1213 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1214 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1215 negatively, so enabling for Generic64 seems like good code size
1216 tradeoff. We can't enable it for 32bit generic because it does not
1217 work well with PPro base chips. */
1218 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1220 /* X86_TUNE_PUSH_MEMORY */
1221 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1222 | m_NOCONA | m_CORE2 | m_GENERIC,
1224 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1227 /* X86_TUNE_USE_BIT_TEST */
1230 /* X86_TUNE_UNROLL_STRLEN */
1231 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1233 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1234 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1236 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1237 on simulation result. But after P4 was made, no performance benefit
1238 was observed with branch hints. It also increases the code size.
1239 As a result, icc never generates branch hints. */
1242 /* X86_TUNE_DOUBLE_WITH_ADD */
1245 /* X86_TUNE_USE_SAHF */
1246 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1247 | m_NOCONA | m_CORE2 | m_GENERIC,
1249 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1250 partial dependencies. */
1251 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1252 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1254 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1255 register stalls on Generic32 compilation setting as well. However
1256 in current implementation the partial register stalls are not eliminated
1257 very well - they can be introduced via subregs synthesized by combine
1258 and can happen in caller/callee saving sequences. Because this option
1259 pays back little on PPro based chips and is in conflict with partial reg
1260 dependencies used by Athlon/P4 based chips, it is better to leave it off
1261 for generic32 for now. */
1264 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1265 m_CORE2 | m_GENERIC,
1267 /* X86_TUNE_USE_HIMODE_FIOP */
1268 m_386 | m_486 | m_K6_GEODE,
1270 /* X86_TUNE_USE_SIMODE_FIOP */
1271 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1273 /* X86_TUNE_USE_MOV0 */
1276 /* X86_TUNE_USE_CLTD */
1277 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1279 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1282 /* X86_TUNE_SPLIT_LONG_MOVES */
1285 /* X86_TUNE_READ_MODIFY_WRITE */
1288 /* X86_TUNE_READ_MODIFY */
1291 /* X86_TUNE_PROMOTE_QIMODE */
1292 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1293 | m_GENERIC /* | m_PENT4 ? */,
1295 /* X86_TUNE_FAST_PREFIX */
1296 ~(m_PENT | m_486 | m_386),
1298 /* X86_TUNE_SINGLE_STRINGOP */
1299 m_386 | m_PENT4 | m_NOCONA,
1301 /* X86_TUNE_QIMODE_MATH */
1304 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1305 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1306 might be considered for Generic32 if our scheme for avoiding partial
1307 stalls was more effective. */
1310 /* X86_TUNE_PROMOTE_QI_REGS */
1313 /* X86_TUNE_PROMOTE_HI_REGS */
1316 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1317 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1319 /* X86_TUNE_ADD_ESP_8 */
1320 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1321 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1323 /* X86_TUNE_SUB_ESP_4 */
1324 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_8 */
1327 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1328 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1330 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1331 for DFmode copies */
1332 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1333 | m_GENERIC | m_GEODE),
1335 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1336 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1338 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1339 conflict here in between PPro/Pentium4 based chips that thread 128bit
1340 SSE registers as single units versus K8 based chips that divide SSE
1341 registers to two 64bit halves. This knob promotes all store destinations
1342 to be 128bit to allow register renaming on 128bit SSE units, but usually
1343 results in one extra microop on 64bit SSE units. Experimental results
1344 shows that disabling this option on P4 brings over 20% SPECfp regression,
1345 while enabling it on K8 brings roughly 2.4% regression that can be partly
1346 masked by careful scheduling of moves. */
1347 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1349 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1352 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1353 are resolved on SSE register parts instead of whole registers, so we may
1354 maintain just lower part of scalar values in proper format leaving the
1355 upper part undefined. */
1358 /* X86_TUNE_SSE_TYPELESS_STORES */
1361 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1362 m_PPRO | m_PENT4 | m_NOCONA,
1364 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1365 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1367 /* X86_TUNE_PROLOGUE_USING_MOVE */
1368 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_EPILOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_SHIFT1 */
1376 /* X86_TUNE_USE_FFREEP */
1379 /* X86_TUNE_INTER_UNIT_MOVES */
1380 ~(m_AMD_MULTIPLE | m_GENERIC),
1382 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1385 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1386 than 4 branch instructions in the 16 byte window. */
1387 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1389 /* X86_TUNE_SCHEDULE */
1390 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_USE_BT */
1395 /* X86_TUNE_USE_INCDEC */
1396 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1398 /* X86_TUNE_PAD_RETURNS */
1399 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_EXT_80387_CONSTANTS */
1402 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_SHORTEN_X87_SSE */
1407 /* X86_TUNE_AVOID_VECTOR_DECODE */
1410 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1411 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1414 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1415 vector path on AMD machines. */
1416 m_K8 | m_GENERIC64 | m_AMDFAM10,
1418 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1420 m_K8 | m_GENERIC64 | m_AMDFAM10,
1422 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1426 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1427 but one byte longer. */
1430 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1431 operand that cannot be represented using a modRM byte. The XOR
1432 replacement is long decoded, so this split helps here as well. */
1435 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1436 from integer to FP. */
1440 /* Feature tests against the various architecture variations. */
1441 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1442 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1443 ~(m_386 | m_486 | m_PENT | m_K6),
1445 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1448 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1451 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1454 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1458 static const unsigned int x86_accumulate_outgoing_args
1459 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1461 static const unsigned int x86_arch_always_fancy_math_387
1462 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1463 | m_NOCONA | m_CORE2 | m_GENERIC;
1465 static enum stringop_alg stringop_alg = no_stringop;
1467 /* In case the average insn count for single function invocation is
1468 lower than this constant, emit fast (but longer) prologue and
1470 #define FAST_PROLOGUE_INSN_COUNT 20
1472 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1473 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1474 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1475 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1477 /* Array of the smallest class containing reg number REGNO, indexed by
1478 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1480 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1482 /* ax, dx, cx, bx */
1483 AREG, DREG, CREG, BREG,
1484 /* si, di, bp, sp */
1485 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1487 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1488 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1491 /* flags, fpsr, fpcr, frame */
1492 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1494 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1497 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1500 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1501 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1502 /* SSE REX registers */
1503 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1507 /* The "default" register map used in 32bit mode. */
1509 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1511 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1512 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1513 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1514 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1515 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1516 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1517 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1520 static int const x86_64_int_parameter_registers[6] =
1522 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1523 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1526 static int const x86_64_ms_abi_int_parameter_registers[4] =
1528 2 /*RCX*/, 1 /*RDX*/,
1529 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1532 static int const x86_64_int_return_registers[4] =
1534 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1537 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Size of the register save area. */
1622 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1624 /* Define the structure for the machine field in struct function. */
1626 struct stack_local_entry GTY(())
1628 unsigned short mode;
1631 struct stack_local_entry *next;
1634 /* Structure describing stack frame layout.
1635 Stack grows downward:
1641 saved frame pointer if frame_pointer_needed
1642 <- HARD_FRAME_POINTER
1647 [va_arg registers] (
1648 > to_allocate <- FRAME_POINTER
1658 HOST_WIDE_INT frame;
1660 int outgoing_arguments_size;
1663 HOST_WIDE_INT to_allocate;
1664 /* The offsets relative to ARG_POINTER. */
1665 HOST_WIDE_INT frame_pointer_offset;
1666 HOST_WIDE_INT hard_frame_pointer_offset;
1667 HOST_WIDE_INT stack_pointer_offset;
1669 /* When save_regs_using_mov is set, emit prologue using
1670 move instead of push instructions. */
1671 bool save_regs_using_mov;
1674 /* Code model option. */
1675 enum cmodel ix86_cmodel;
1677 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1679 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1681 /* Which unit we are generating floating point math for. */
1682 enum fpmath_unit ix86_fpmath;
1684 /* Which cpu are we scheduling for. */
1685 enum processor_type ix86_tune;
1687 /* Which instruction set architecture to use. */
1688 enum processor_type ix86_arch;
1690 /* true if sse prefetch instruction is not NOOP. */
1691 int x86_prefetch_sse;
1693 /* ix86_regparm_string as a number */
1694 static int ix86_regparm;
1696 /* -mstackrealign option */
1697 extern int ix86_force_align_arg_pointer;
1698 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1700 /* Preferred alignment for stack boundary in bits. */
1701 unsigned int ix86_preferred_stack_boundary;
1703 /* Values 1-5: see jump.c */
1704 int ix86_branch_cost;
1706 /* Variables which are this size or smaller are put in the data/bss
1707 or ldata/lbss sections. */
1709 int ix86_section_threshold = 65536;
1711 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1712 char internal_label_prefix[16];
1713 int internal_label_prefix_len;
1715 /* Fence to use after loop using movnt. */
1718 /* Register class used for passing given 64bit part of the argument.
1719 These represent classes as documented by the PS ABI, with the exception
1720 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1721 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1723 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1724 whenever possible (upper half does contain padding). */
1725 enum x86_64_reg_class
1728 X86_64_INTEGER_CLASS,
1729 X86_64_INTEGERSI_CLASS,
1736 X86_64_COMPLEX_X87_CLASS,
1739 static const char * const x86_64_reg_class_name[] =
1741 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1742 "sseup", "x87", "x87up", "cplx87", "no"
1745 #define MAX_CLASSES 4
1747 /* Table of constants used by fldpi, fldln2, etc.... */
1748 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1749 static bool ext_80387_constants_init = 0;
1752 static struct machine_function * ix86_init_machine_status (void);
1753 static rtx ix86_function_value (const_tree, const_tree, bool);
1754 static int ix86_function_regparm (const_tree, const_tree);
1755 static void ix86_compute_frame_layout (struct ix86_frame *);
1756 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1760 /* The svr4 ABI for the i386 says that records and unions are returned
1762 #ifndef DEFAULT_PCC_STRUCT_RETURN
1763 #define DEFAULT_PCC_STRUCT_RETURN 1
1766 /* Bit flags that specify the ISA we are compiling for. */
1767 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1769 /* A mask of ix86_isa_flags that includes bit X if X
1770 was set or cleared on the command line. */
1771 static int ix86_isa_flags_explicit;
1773 /* Define a set of ISAs which are available when a given ISA is
1774 enabled. MMX and SSE ISAs are handled separately. */
1776 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1777 #define OPTION_MASK_ISA_3DNOW_SET \
1778 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1780 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1781 #define OPTION_MASK_ISA_SSE2_SET \
1782 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1783 #define OPTION_MASK_ISA_SSE3_SET \
1784 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1785 #define OPTION_MASK_ISA_SSSE3_SET \
1786 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1787 #define OPTION_MASK_ISA_SSE4_1_SET \
1788 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1789 #define OPTION_MASK_ISA_SSE4_2_SET \
1790 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1792 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1794 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1796 #define OPTION_MASK_ISA_SSE4A_SET \
1797 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1798 #define OPTION_MASK_ISA_SSE5_SET \
1799 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1801 /* Define a set of ISAs which aren't available when a given ISA is
1802 disabled. MMX and SSE ISAs are handled separately. */
1804 #define OPTION_MASK_ISA_MMX_UNSET \
1805 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1806 #define OPTION_MASK_ISA_3DNOW_UNSET \
1807 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1808 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1810 #define OPTION_MASK_ISA_SSE_UNSET \
1811 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1812 #define OPTION_MASK_ISA_SSE2_UNSET \
1813 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1814 #define OPTION_MASK_ISA_SSE3_UNSET \
1815 (OPTION_MASK_ISA_SSE3 \
1816 | OPTION_MASK_ISA_SSSE3_UNSET \
1817 | OPTION_MASK_ISA_SSE4A_UNSET )
1818 #define OPTION_MASK_ISA_SSSE3_UNSET \
1819 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1820 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1821 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1822 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1824 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1826 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1828 #define OPTION_MASK_ISA_SSE4A_UNSET \
1829 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1831 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1833 /* Vectorization library interface and handlers. */
1834 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1835 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1836 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1838 /* Implement TARGET_HANDLE_OPTION. */
1841 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1848 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1849 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1853 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1854 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1861 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
1862 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
1866 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1867 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
1877 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
1878 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
1882 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
1883 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
1890 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
1891 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
1895 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
1896 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
1903 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
1904 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
1908 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
1909 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
1916 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
1917 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
1921 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
1922 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
1929 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
1930 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
1934 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
1935 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
1942 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
1943 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
1947 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
1948 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
1953 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1954 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1958 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1959 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1965 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1966 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1970 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1971 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1978 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
1979 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
1983 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
1984 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
1993 /* Sometimes certain combinations of command options do not make
1994 sense on a particular target machine. You can define a macro
1995 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1996 defined, is executed once just after all the command options have
1999 Don't use this macro to turn on various extra optimizations for
2000 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2003 override_options (void)
2006 int ix86_tune_defaulted = 0;
2007 int ix86_arch_specified = 0;
2008 unsigned int ix86_arch_mask, ix86_tune_mask;
2010 /* Comes from final.c -- no real reason to change it. */
2011 #define MAX_CODE_ALIGN 16
2015 const struct processor_costs *cost; /* Processor costs */
2016 const int align_loop; /* Default alignments. */
2017 const int align_loop_max_skip;
2018 const int align_jump;
2019 const int align_jump_max_skip;
2020 const int align_func;
2022 const processor_target_table[PROCESSOR_max] =
2024 {&i386_cost, 4, 3, 4, 3, 4},
2025 {&i486_cost, 16, 15, 16, 15, 16},
2026 {&pentium_cost, 16, 7, 16, 7, 16},
2027 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2028 {&geode_cost, 0, 0, 0, 0, 0},
2029 {&k6_cost, 32, 7, 32, 7, 32},
2030 {&athlon_cost, 16, 7, 16, 7, 16},
2031 {&pentium4_cost, 0, 0, 0, 0, 0},
2032 {&k8_cost, 16, 7, 16, 7, 16},
2033 {&nocona_cost, 0, 0, 0, 0, 0},
2034 {&core2_cost, 16, 10, 16, 10, 16},
2035 {&generic32_cost, 16, 7, 16, 7, 16},
2036 {&generic64_cost, 16, 10, 16, 10, 16},
2037 {&amdfam10_cost, 32, 24, 32, 7, 32}
2040 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2071 PTA_PREFETCH_SSE = 1 << 4,
2073 PTA_3DNOW_A = 1 << 6,
2077 PTA_POPCNT = 1 << 10,
2079 PTA_SSE4A = 1 << 12,
2080 PTA_NO_SAHF = 1 << 13,
2081 PTA_SSE4_1 = 1 << 14,
2082 PTA_SSE4_2 = 1 << 15,
2085 PTA_PCLMUL = 1 << 18
2090 const char *const name; /* processor name or nickname. */
2091 const enum processor_type processor;
2092 const unsigned /*enum pta_flags*/ flags;
2094 const processor_alias_table[] =
2096 {"i386", PROCESSOR_I386, 0},
2097 {"i486", PROCESSOR_I486, 0},
2098 {"i586", PROCESSOR_PENTIUM, 0},
2099 {"pentium", PROCESSOR_PENTIUM, 0},
2100 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2101 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2102 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2103 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2104 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2105 {"i686", PROCESSOR_PENTIUMPRO, 0},
2106 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2107 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2108 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2109 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2110 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2111 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2112 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2113 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2114 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2115 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2116 | PTA_CX16 | PTA_NO_SAHF)},
2117 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2118 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2121 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2122 |PTA_PREFETCH_SSE)},
2123 {"k6", PROCESSOR_K6, PTA_MMX},
2124 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2125 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2126 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2127 | PTA_PREFETCH_SSE)},
2128 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2129 | PTA_PREFETCH_SSE)},
2130 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2132 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2134 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2136 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2137 | PTA_MMX | PTA_SSE | PTA_SSE2
2139 {"k8", PROCESSOR_K8, (PTA_64BIT
2140 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2141 | PTA_SSE | PTA_SSE2
2143 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2144 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2145 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2147 {"opteron", PROCESSOR_K8, (PTA_64BIT
2148 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2149 | PTA_SSE | PTA_SSE2
2151 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2152 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2153 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2155 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2156 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2157 | PTA_SSE | PTA_SSE2
2159 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2160 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2161 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2163 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2164 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2165 | PTA_SSE | PTA_SSE2
2167 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2168 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2169 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2171 | PTA_CX16 | PTA_ABM)},
2172 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2173 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2174 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2176 | PTA_CX16 | PTA_ABM)},
2177 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2178 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2181 int const pta_size = ARRAY_SIZE (processor_alias_table);
2183 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2184 SUBTARGET_OVERRIDE_OPTIONS;
2187 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2188 SUBSUBTARGET_OVERRIDE_OPTIONS;
2191 /* -fPIC is the default for x86_64. */
2192 if (TARGET_MACHO && TARGET_64BIT)
2195 /* Set the default values for switches whose default depends on TARGET_64BIT
2196 in case they weren't overwritten by command line options. */
2199 /* Mach-O doesn't support omitting the frame pointer for now. */
2200 if (flag_omit_frame_pointer == 2)
2201 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2202 if (flag_asynchronous_unwind_tables == 2)
2203 flag_asynchronous_unwind_tables = 1;
2204 if (flag_pcc_struct_return == 2)
2205 flag_pcc_struct_return = 0;
2209 if (flag_omit_frame_pointer == 2)
2210 flag_omit_frame_pointer = 0;
2211 if (flag_asynchronous_unwind_tables == 2)
2212 flag_asynchronous_unwind_tables = 0;
2213 if (flag_pcc_struct_return == 2)
2214 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2217 /* Need to check -mtune=generic first. */
2218 if (ix86_tune_string)
2220 if (!strcmp (ix86_tune_string, "generic")
2221 || !strcmp (ix86_tune_string, "i686")
2222 /* As special support for cross compilers we read -mtune=native
2223 as -mtune=generic. With native compilers we won't see the
2224 -mtune=native, as it was changed by the driver. */
2225 || !strcmp (ix86_tune_string, "native"))
2228 ix86_tune_string = "generic64";
2230 ix86_tune_string = "generic32";
2232 else if (!strncmp (ix86_tune_string, "generic", 7))
2233 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2237 if (ix86_arch_string)
2238 ix86_tune_string = ix86_arch_string;
2239 if (!ix86_tune_string)
2241 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2242 ix86_tune_defaulted = 1;
2245 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2246 need to use a sensible tune option. */
2247 if (!strcmp (ix86_tune_string, "generic")
2248 || !strcmp (ix86_tune_string, "x86-64")
2249 || !strcmp (ix86_tune_string, "i686"))
2252 ix86_tune_string = "generic64";
2254 ix86_tune_string = "generic32";
2257 if (ix86_stringop_string)
2259 if (!strcmp (ix86_stringop_string, "rep_byte"))
2260 stringop_alg = rep_prefix_1_byte;
2261 else if (!strcmp (ix86_stringop_string, "libcall"))
2262 stringop_alg = libcall;
2263 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2264 stringop_alg = rep_prefix_4_byte;
2265 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2266 stringop_alg = rep_prefix_8_byte;
2267 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2268 stringop_alg = loop_1_byte;
2269 else if (!strcmp (ix86_stringop_string, "loop"))
2270 stringop_alg = loop;
2271 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2272 stringop_alg = unrolled_loop;
2274 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
2276 if (!strcmp (ix86_tune_string, "x86-64"))
2277 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
2278 "-mtune=generic instead as appropriate.");
2280 if (!ix86_arch_string)
2281 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2283 ix86_arch_specified = 1;
2285 if (!strcmp (ix86_arch_string, "generic"))
2286 error ("generic CPU can be used only for -mtune= switch");
2287 if (!strncmp (ix86_arch_string, "generic", 7))
2288 error ("bad value (%s) for -march= switch", ix86_arch_string);
2290 if (ix86_cmodel_string != 0)
2292 if (!strcmp (ix86_cmodel_string, "small"))
2293 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2294 else if (!strcmp (ix86_cmodel_string, "medium"))
2295 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2296 else if (!strcmp (ix86_cmodel_string, "large"))
2297 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2299 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2300 else if (!strcmp (ix86_cmodel_string, "32"))
2301 ix86_cmodel = CM_32;
2302 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2303 ix86_cmodel = CM_KERNEL;
2305 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
2309 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
2310 use of rip-relative addressing. This eliminates fixups that
2311 would otherwise be needed if this object is to be placed in a
2312 DLL, and is essentially just as efficient as direct addressing. */
2313 if (TARGET_64BIT_MS_ABI)
2314 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2315 else if (TARGET_64BIT)
2316 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2318 ix86_cmodel = CM_32;
2320 if (ix86_asm_string != 0)
2323 && !strcmp (ix86_asm_string, "intel"))
2324 ix86_asm_dialect = ASM_INTEL;
2325 else if (!strcmp (ix86_asm_string, "att"))
2326 ix86_asm_dialect = ASM_ATT;
2328 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2330 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2331 error ("code model %qs not supported in the %s bit mode",
2332 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2333 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2334 sorry ("%i-bit mode not compiled in",
2335 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2337 for (i = 0; i < pta_size; i++)
2338 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2340 ix86_arch = processor_alias_table[i].processor;
2341 /* Default cpu tuning to the architecture. */
2342 ix86_tune = ix86_arch;
2344 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2345 error ("CPU you selected does not support x86-64 "
2348 if (processor_alias_table[i].flags & PTA_MMX
2349 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2350 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2351 if (processor_alias_table[i].flags & PTA_3DNOW
2352 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2353 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2354 if (processor_alias_table[i].flags & PTA_3DNOW_A
2355 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2356 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2357 if (processor_alias_table[i].flags & PTA_SSE
2358 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2359 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2360 if (processor_alias_table[i].flags & PTA_SSE2
2361 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2362 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2363 if (processor_alias_table[i].flags & PTA_SSE3
2364 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2365 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2366 if (processor_alias_table[i].flags & PTA_SSSE3
2367 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2368 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2369 if (processor_alias_table[i].flags & PTA_SSE4_1
2370 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2371 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2372 if (processor_alias_table[i].flags & PTA_SSE4_2
2373 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2374 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2375 if (processor_alias_table[i].flags & PTA_SSE4A
2376 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2377 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2378 if (processor_alias_table[i].flags & PTA_SSE5
2379 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2380 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2382 if (processor_alias_table[i].flags & PTA_ABM)
2384 if (processor_alias_table[i].flags & PTA_CX16)
2385 x86_cmpxchg16b = true;
2386 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
2388 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2389 x86_prefetch_sse = true;
2390 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
2392 if (processor_alias_table[i].flags & PTA_AES)
2394 if (processor_alias_table[i].flags & PTA_PCLMUL)
2401 error ("bad value (%s) for -march= switch", ix86_arch_string);
2403 ix86_arch_mask = 1u << ix86_arch;
2404 for (i = 0; i < X86_ARCH_LAST; ++i)
2405 ix86_arch_features[i] &= ix86_arch_mask;
2407 for (i = 0; i < pta_size; i++)
2408 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2410 ix86_tune = processor_alias_table[i].processor;
2411 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2413 if (ix86_tune_defaulted)
2415 ix86_tune_string = "x86-64";
2416 for (i = 0; i < pta_size; i++)
2417 if (! strcmp (ix86_tune_string,
2418 processor_alias_table[i].name))
2420 ix86_tune = processor_alias_table[i].processor;
2423 error ("CPU you selected does not support x86-64 "
2426 /* Intel CPUs have always interpreted SSE prefetch instructions as
2427 NOPs; so, we can enable SSE prefetch instructions even when
2428 -mtune (rather than -march) points us to a processor that has them.
2429 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2430 higher processors. */
2432 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2433 x86_prefetch_sse = true;
2437 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2439 /* Enable SSE2 if AES or PCLMUL is enabled. */
2440 if ((x86_aes || x86_pclmul)
2441 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2443 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2444 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2447 ix86_tune_mask = 1u << ix86_tune;
2448 for (i = 0; i < X86_TUNE_LAST; ++i)
2449 ix86_tune_features[i] &= ix86_tune_mask;
2452 ix86_cost = &size_cost;
2454 ix86_cost = processor_target_table[ix86_tune].cost;
2456 /* Arrange to set up i386_stack_locals for all functions. */
2457 init_machine_status = ix86_init_machine_status;
2459 /* Validate -mregparm= value. */
2460 if (ix86_regparm_string)
2463 warning (0, "-mregparm is ignored in 64-bit mode");
2464 i = atoi (ix86_regparm_string);
2465 if (i < 0 || i > REGPARM_MAX)
2466 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2471 ix86_regparm = REGPARM_MAX;
2473 /* If the user has provided any of the -malign-* options,
2474 warn and use that value only if -falign-* is not set.
2475 Remove this code in GCC 3.2 or later. */
2476 if (ix86_align_loops_string)
2478 warning (0, "-malign-loops is obsolete, use -falign-loops");
2479 if (align_loops == 0)
2481 i = atoi (ix86_align_loops_string);
2482 if (i < 0 || i > MAX_CODE_ALIGN)
2483 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2485 align_loops = 1 << i;
2489 if (ix86_align_jumps_string)
2491 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2492 if (align_jumps == 0)
2494 i = atoi (ix86_align_jumps_string);
2495 if (i < 0 || i > MAX_CODE_ALIGN)
2496 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2498 align_jumps = 1 << i;
2502 if (ix86_align_funcs_string)
2504 warning (0, "-malign-functions is obsolete, use -falign-functions");
2505 if (align_functions == 0)
2507 i = atoi (ix86_align_funcs_string);
2508 if (i < 0 || i > MAX_CODE_ALIGN)
2509 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2511 align_functions = 1 << i;
2515 /* Default align_* from the processor table. */
2516 if (align_loops == 0)
2518 align_loops = processor_target_table[ix86_tune].align_loop;
2519 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2521 if (align_jumps == 0)
2523 align_jumps = processor_target_table[ix86_tune].align_jump;
2524 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2526 if (align_functions == 0)
2528 align_functions = processor_target_table[ix86_tune].align_func;
2531 /* Validate -mbranch-cost= value, or provide default. */
2532 ix86_branch_cost = ix86_cost->branch_cost;
2533 if (ix86_branch_cost_string)
2535 i = atoi (ix86_branch_cost_string);
2537 error ("-mbranch-cost=%d is not between 0 and 5", i);
2539 ix86_branch_cost = i;
2541 if (ix86_section_threshold_string)
2543 i = atoi (ix86_section_threshold_string);
2545 error ("-mlarge-data-threshold=%d is negative", i);
2547 ix86_section_threshold = i;
2550 if (ix86_tls_dialect_string)
2552 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2553 ix86_tls_dialect = TLS_DIALECT_GNU;
2554 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2555 ix86_tls_dialect = TLS_DIALECT_GNU2;
2556 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2557 ix86_tls_dialect = TLS_DIALECT_SUN;
2559 error ("bad value (%s) for -mtls-dialect= switch",
2560 ix86_tls_dialect_string);
2563 if (ix87_precision_string)
2565 i = atoi (ix87_precision_string);
2566 if (i != 32 && i != 64 && i != 80)
2567 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2572 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2574 /* Enable by default the SSE and MMX builtins. Do allow the user to
2575 explicitly disable any of these. In particular, disabling SSE and
2576 MMX for kernel code is extremely useful. */
2577 if (!ix86_arch_specified)
2579 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2580 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2583 warning (0, "-mrtd is ignored in 64bit mode");
2587 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2589 if (!ix86_arch_specified)
2591 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2593 /* i386 ABI does not specify red zone. It still makes sense to use it
2594 when programmer takes care to stack from being destroyed. */
2595 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2596 target_flags |= MASK_NO_RED_ZONE;
2599 /* Keep nonleaf frame pointers. */
2600 if (flag_omit_frame_pointer)
2601 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2602 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2603 flag_omit_frame_pointer = 1;
2605 /* If we're doing fast math, we don't care about comparison order
2606 wrt NaNs. This lets us use a shorter comparison sequence. */
2607 if (flag_finite_math_only)
2608 target_flags &= ~MASK_IEEE_FP;
2610 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2611 since the insns won't need emulation. */
2612 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2613 target_flags &= ~MASK_NO_FANCY_MATH_387;
2615 /* Likewise, if the target doesn't have a 387, or we've specified
2616 software floating point, don't use 387 inline intrinsics. */
2618 target_flags |= MASK_NO_FANCY_MATH_387;
2620 /* Turn on MMX builtins for -msse. */
2623 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
2624 x86_prefetch_sse = true;
2627 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
2628 if (TARGET_SSE4_2 || TARGET_ABM)
2631 /* Validate -mpreferred-stack-boundary= value, or provide default.
2632 The default of 128 bits is for Pentium III's SSE __m128. We can't
2633 change it because of optimize_size. Otherwise, we can't mix object
2634 files compiled with -Os and -On. */
2635 ix86_preferred_stack_boundary = 128;
2636 if (ix86_preferred_stack_boundary_string)
2638 i = atoi (ix86_preferred_stack_boundary_string);
2639 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2640 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2641 TARGET_64BIT ? 4 : 2);
2643 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2646 /* Accept -msseregparm only if at least SSE support is enabled. */
2647 if (TARGET_SSEREGPARM
2649 error ("-msseregparm used without SSE enabled");
2651 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2652 if (ix86_fpmath_string != 0)
2654 if (! strcmp (ix86_fpmath_string, "387"))
2655 ix86_fpmath = FPMATH_387;
2656 else if (! strcmp (ix86_fpmath_string, "sse"))
2660 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2661 ix86_fpmath = FPMATH_387;
2664 ix86_fpmath = FPMATH_SSE;
2666 else if (! strcmp (ix86_fpmath_string, "387,sse")
2667 || ! strcmp (ix86_fpmath_string, "sse,387"))
2671 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2672 ix86_fpmath = FPMATH_387;
2674 else if (!TARGET_80387)
2676 warning (0, "387 instruction set disabled, using SSE arithmetics");
2677 ix86_fpmath = FPMATH_SSE;
2680 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
2683 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2686 /* If the i387 is disabled, then do not return values in it. */
2688 target_flags &= ~MASK_FLOAT_RETURNS;
2690 /* Use external vectorized library in vectorizing intrinsics. */
2691 if (ix86_veclibabi_string)
2693 if (strcmp (ix86_veclibabi_string, "svml") == 0)
2694 ix86_veclib_handler = ix86_veclibabi_svml;
2695 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
2696 ix86_veclib_handler = ix86_veclibabi_acml;
2698 error ("unknown vectorization library ABI type (%s) for "
2699 "-mveclibabi= switch", ix86_veclibabi_string);
2702 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2703 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2705 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2707 /* ??? Unwind info is not correct around the CFG unless either a frame
2708 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2709 unwind info generation to be aware of the CFG and propagating states
2711 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2712 || flag_exceptions || flag_non_call_exceptions)
2713 && flag_omit_frame_pointer
2714 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2716 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2717 warning (0, "unwind tables currently require either a frame pointer "
2718 "or -maccumulate-outgoing-args for correctness");
2719 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2722 /* If stack probes are required, the space used for large function
2723 arguments on the stack must also be probed, so enable
2724 -maccumulate-outgoing-args so this happens in the prologue. */
2725 if (TARGET_STACK_PROBE
2726 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2728 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2729 warning (0, "stack probing requires -maccumulate-outgoing-args "
2731 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2734 /* For sane SSE instruction set generation we need fcomi instruction.
2735 It is safe to enable all CMOVE instructions. */
2739 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2742 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2743 p = strchr (internal_label_prefix, 'X');
2744 internal_label_prefix_len = p - internal_label_prefix;
2748 /* When scheduling description is not available, disable scheduler pass
2749 so it won't slow down the compilation and make x87 code slower. */
2750 if (!TARGET_SCHEDULE)
2751 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2753 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2754 set_param_value ("simultaneous-prefetches",
2755 ix86_cost->simultaneous_prefetches);
2756 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2757 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2758 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
2759 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
2760 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
2761 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
2763 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
2764 can be optimized to ap = __builtin_next_arg (0). */
2765 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
2766 targetm.expand_builtin_va_start = NULL;
2769 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
2771 target_flags |= MASK_CLD & ~target_flags_explicit;
2775 /* Return true if this goes in large data/bss. */
2778 ix86_in_large_data_p (tree exp)
2780 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2783 /* Functions are never large data. */
2784 if (TREE_CODE (exp) == FUNCTION_DECL)
2787 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2789 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2790 if (strcmp (section, ".ldata") == 0
2791 || strcmp (section, ".lbss") == 0)
2797 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2799 /* If this is an incomplete type with size 0, then we can't put it
2800 in data because it might be too big when completed. */
2801 if (!size || size > ix86_section_threshold)
2808 /* Switch to the appropriate section for output of DECL.
2809 DECL is either a `VAR_DECL' node or a constant of some sort.
2810 RELOC indicates whether forming the initial value of DECL requires
2811 link-time relocations. */
2813 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2817 x86_64_elf_select_section (tree decl, int reloc,
2818 unsigned HOST_WIDE_INT align)
2820 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2821 && ix86_in_large_data_p (decl))
2823 const char *sname = NULL;
2824 unsigned int flags = SECTION_WRITE;
2825 switch (categorize_decl_for_section (decl, reloc))
2830 case SECCAT_DATA_REL:
2831 sname = ".ldata.rel";
2833 case SECCAT_DATA_REL_LOCAL:
2834 sname = ".ldata.rel.local";
2836 case SECCAT_DATA_REL_RO:
2837 sname = ".ldata.rel.ro";
2839 case SECCAT_DATA_REL_RO_LOCAL:
2840 sname = ".ldata.rel.ro.local";
2844 flags |= SECTION_BSS;
2847 case SECCAT_RODATA_MERGE_STR:
2848 case SECCAT_RODATA_MERGE_STR_INIT:
2849 case SECCAT_RODATA_MERGE_CONST:
2853 case SECCAT_SRODATA:
2860 /* We don't split these for medium model. Place them into
2861 default sections and hope for best. */
2863 case SECCAT_EMUTLS_VAR:
2864 case SECCAT_EMUTLS_TMPL:
2869 /* We might get called with string constants, but get_named_section
2870 doesn't like them as they are not DECLs. Also, we need to set
2871 flags in that case. */
2873 return get_section (sname, flags, NULL);
2874 return get_named_section (decl, sname, reloc);
2877 return default_elf_select_section (decl, reloc, align);
2880 /* Build up a unique section name, expressed as a
2881 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2882 RELOC indicates whether the initial value of EXP requires
2883 link-time relocations. */
2885 static void ATTRIBUTE_UNUSED
2886 x86_64_elf_unique_section (tree decl, int reloc)
2888 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2889 && ix86_in_large_data_p (decl))
2891 const char *prefix = NULL;
2892 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2893 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2895 switch (categorize_decl_for_section (decl, reloc))
2898 case SECCAT_DATA_REL:
2899 case SECCAT_DATA_REL_LOCAL:
2900 case SECCAT_DATA_REL_RO:
2901 case SECCAT_DATA_REL_RO_LOCAL:
2902 prefix = one_only ? ".ld" : ".ldata";
2905 prefix = one_only ? ".lb" : ".lbss";
2908 case SECCAT_RODATA_MERGE_STR:
2909 case SECCAT_RODATA_MERGE_STR_INIT:
2910 case SECCAT_RODATA_MERGE_CONST:
2911 prefix = one_only ? ".lr" : ".lrodata";
2913 case SECCAT_SRODATA:
2920 /* We don't split these for medium model. Place them into
2921 default sections and hope for best. */
2923 case SECCAT_EMUTLS_VAR:
2924 prefix = targetm.emutls.var_section;
2926 case SECCAT_EMUTLS_TMPL:
2927 prefix = targetm.emutls.tmpl_section;
2932 const char *name, *linkonce;
2935 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2936 name = targetm.strip_name_encoding (name);
2938 /* If we're using one_only, then there needs to be a .gnu.linkonce
2939 prefix to the section name. */
2940 linkonce = one_only ? ".gnu.linkonce" : "";
2942 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
2944 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
2948 default_unique_section (decl, reloc);
2951 #ifdef COMMON_ASM_OP
2952 /* This says how to output assembler code to declare an
2953 uninitialized external linkage data object.
2955 For medium model x86-64 we need to use .largecomm opcode for
2958 x86_elf_aligned_common (FILE *file,
2959 const char *name, unsigned HOST_WIDE_INT size,
2962 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2963 && size > (unsigned int)ix86_section_threshold)
2964 fprintf (file, ".largecomm\t");
2966 fprintf (file, "%s", COMMON_ASM_OP);
2967 assemble_name (file, name);
2968 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2969 size, align / BITS_PER_UNIT);
2973 /* Utility function for targets to use in implementing
2974 ASM_OUTPUT_ALIGNED_BSS. */
2977 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2978 const char *name, unsigned HOST_WIDE_INT size,
2981 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2982 && size > (unsigned int)ix86_section_threshold)
2983 switch_to_section (get_named_section (decl, ".lbss", 0));
2985 switch_to_section (bss_section);
2986 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2987 #ifdef ASM_DECLARE_OBJECT_NAME
2988 last_assemble_variable_decl = decl;
2989 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2991 /* Standard thing is just output label for the object. */
2992 ASM_OUTPUT_LABEL (file, name);
2993 #endif /* ASM_DECLARE_OBJECT_NAME */
2994 ASM_OUTPUT_SKIP (file, size ? size : 1);
2998 optimization_options (int level, int size ATTRIBUTE_UNUSED)
3000 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
3001 make the problem with not enough registers even worse. */
3002 #ifdef INSN_SCHEDULING
3004 flag_schedule_insns = 0;
3008 /* The Darwin libraries never set errno, so we might as well
3009 avoid calling them when that's the only reason we would. */
3010 flag_errno_math = 0;
3012 /* The default values of these switches depend on the TARGET_64BIT
3013 that is not known at this moment. Mark these values with 2 and
3014 let user the to override these. In case there is no command line option
3015 specifying them, we will set the defaults in override_options. */
3017 flag_omit_frame_pointer = 2;
3018 flag_pcc_struct_return = 2;
3019 flag_asynchronous_unwind_tables = 2;
3020 flag_vect_cost_model = 1;
3021 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
3022 SUBTARGET_OPTIMIZATION_OPTIONS;
3026 /* Decide whether we can make a sibling call to a function. DECL is the
3027 declaration of the function being targeted by the call and EXP is the
3028 CALL_EXPR representing the call. */
3031 ix86_function_ok_for_sibcall (tree decl, tree exp)
3036 /* If we are generating position-independent code, we cannot sibcall
3037 optimize any indirect call, or a direct call to a global function,
3038 as the PLT requires %ebx be live. */
3039 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
3046 func = TREE_TYPE (CALL_EXPR_FN (exp));
3047 if (POINTER_TYPE_P (func))
3048 func = TREE_TYPE (func);
3051 /* Check that the return value locations are the same. Like
3052 if we are returning floats on the 80387 register stack, we cannot
3053 make a sibcall from a function that doesn't return a float to a
3054 function that does or, conversely, from a function that does return
3055 a float to a function that doesn't; the necessary stack adjustment
3056 would not be executed. This is also the place we notice
3057 differences in the return value ABI. Note that it is ok for one
3058 of the functions to have void return type as long as the return
3059 value of the other is passed in a register. */
3060 a = ix86_function_value (TREE_TYPE (exp), func, false);
3061 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
3063 if (STACK_REG_P (a) || STACK_REG_P (b))
3065 if (!rtx_equal_p (a, b))
3068 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
3070 else if (!rtx_equal_p (a, b))
3073 /* If this call is indirect, we'll need to be able to use a call-clobbered
3074 register for the address of the target function. Make sure that all
3075 such registers are not used for passing parameters. */
3076 if (!decl && !TARGET_64BIT)
3080 /* We're looking at the CALL_EXPR, we need the type of the function. */
3081 type = CALL_EXPR_FN (exp); /* pointer expression */
3082 type = TREE_TYPE (type); /* pointer type */
3083 type = TREE_TYPE (type); /* function type */
3085 if (ix86_function_regparm (type, NULL) >= 3)
3087 /* ??? Need to count the actual number of registers to be used,
3088 not the possible number of registers. Fix later. */
3093 /* Dllimport'd functions are also called indirectly. */
3094 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
3095 && decl && DECL_DLLIMPORT_P (decl)
3096 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
3099 /* If we forced aligned the stack, then sibcalling would unalign the
3100 stack, which may break the called function. */
3101 if (cfun->machine->force_align_arg_pointer)
3104 /* Otherwise okay. That also includes certain types of indirect calls. */
3108 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
3109 calling convention attributes;
3110 arguments as in struct attribute_spec.handler. */
3113 ix86_handle_cconv_attribute (tree *node, tree name,
3115 int flags ATTRIBUTE_UNUSED,
3118 if (TREE_CODE (*node) != FUNCTION_TYPE
3119 && TREE_CODE (*node) != METHOD_TYPE
3120 && TREE_CODE (*node) != FIELD_DECL
3121 && TREE_CODE (*node) != TYPE_DECL)
3123 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3124 IDENTIFIER_POINTER (name));
3125 *no_add_attrs = true;
3129 /* Can combine regparm with all attributes but fastcall. */
3130 if (is_attribute_p ("regparm", name))
3134 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3136 error ("fastcall and regparm attributes are not compatible");
3139 cst = TREE_VALUE (args);
3140 if (TREE_CODE (cst) != INTEGER_CST)
3142 warning (OPT_Wattributes,
3143 "%qs attribute requires an integer constant argument",
3144 IDENTIFIER_POINTER (name));
3145 *no_add_attrs = true;
3147 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
3149 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
3150 IDENTIFIER_POINTER (name), REGPARM_MAX);
3151 *no_add_attrs = true;
3155 && lookup_attribute (ix86_force_align_arg_pointer_string,
3156 TYPE_ATTRIBUTES (*node))
3157 && compare_tree_int (cst, REGPARM_MAX-1))
3159 error ("%s functions limited to %d register parameters",
3160 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
3168 /* Do not warn when emulating the MS ABI. */
3169 if (!TARGET_64BIT_MS_ABI)
3170 warning (OPT_Wattributes, "%qs attribute ignored",
3171 IDENTIFIER_POINTER (name));
3172 *no_add_attrs = true;
3176 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
3177 if (is_attribute_p ("fastcall", name))
3179 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3181 error ("fastcall and cdecl attributes are not compatible");
3183 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3185 error ("fastcall and stdcall attributes are not compatible");
3187 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
3189 error ("fastcall and regparm attributes are not compatible");
3193 /* Can combine stdcall with fastcall (redundant), regparm and
3195 else if (is_attribute_p ("stdcall", name))
3197 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3199 error ("stdcall and cdecl attributes are not compatible");
3201 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3203 error ("stdcall and fastcall attributes are not compatible");
3207 /* Can combine cdecl with regparm and sseregparm. */
3208 else if (is_attribute_p ("cdecl", name))
3210 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3212 error ("stdcall and cdecl attributes are not compatible");
3214 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3216 error ("fastcall and cdecl attributes are not compatible");
3220 /* Can combine sseregparm with all attributes. */
3225 /* Return 0 if the attributes for two types are incompatible, 1 if they
3226 are compatible, and 2 if they are nearly compatible (which causes a
3227 warning to be generated). */
3230 ix86_comp_type_attributes (const_tree type1, const_tree type2)
3232 /* Check for mismatch of non-default calling convention. */
3233 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
3235 if (TREE_CODE (type1) != FUNCTION_TYPE
3236 && TREE_CODE (type1) != METHOD_TYPE)
3239 /* Check for mismatched fastcall/regparm types. */
3240 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
3241 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
3242 || (ix86_function_regparm (type1, NULL)
3243 != ix86_function_regparm (type2, NULL)))
3246 /* Check for mismatched sseregparm types. */
3247 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
3248 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
3251 /* Check for mismatched return types (cdecl vs stdcall). */
3252 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
3253 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
3259 /* Return the regparm value for a function with the indicated TYPE and DECL.
3260 DECL may be NULL when calling function indirectly
3261 or considering a libcall. */
3264 ix86_function_regparm (const_tree type, const_tree decl)
3267 int regparm = ix86_regparm;
3269 static bool error_issued;
3274 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
3278 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
3280 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
3282 /* We can't use regparm(3) for nested functions because
3283 these pass static chain pointer in %ecx register. */
3284 if (!error_issued && regparm == 3
3285 && decl_function_context (decl)
3286 && !DECL_NO_STATIC_CHAIN (decl))
3288 error ("nested functions are limited to 2 register parameters");
3289 error_issued = true;
3297 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
3300 /* Use register calling convention for local functions when possible. */
3301 if (decl && TREE_CODE (decl) == FUNCTION_DECL
3302 && flag_unit_at_a_time && !profile_flag)
3304 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3305 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3308 int local_regparm, globals = 0, regno;
3311 /* Make sure no regparm register is taken by a
3312 fixed register variable. */
3313 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
3314 if (fixed_regs[local_regparm])
3317 /* We can't use regparm(3) for nested functions as these use
3318 static chain pointer in third argument. */
3319 if (local_regparm == 3
3320 && (decl_function_context (decl)
3321 || ix86_force_align_arg_pointer)
3322 && !DECL_NO_STATIC_CHAIN (decl))
3325 /* If the function realigns its stackpointer, the prologue will
3326 clobber %ecx. If we've already generated code for the callee,
3327 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
3328 scanning the attributes for the self-realigning property. */
3329 f = DECL_STRUCT_FUNCTION (decl);
3330 if (local_regparm == 3
3331 && (f ? !!f->machine->force_align_arg_pointer
3332 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
3333 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
3336 /* Each fixed register usage increases register pressure,
3337 so less registers should be used for argument passing.
3338 This functionality can be overriden by an explicit
3340 for (regno = 0; regno <= DI_REG; regno++)
3341 if (fixed_regs[regno])
3345 = globals < local_regparm ? local_regparm - globals : 0;
3347 if (local_regparm > regparm)
3348 regparm = local_regparm;
3355 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
3356 DFmode (2) arguments in SSE registers for a function with the
3357 indicated TYPE and DECL. DECL may be NULL when calling function
3358 indirectly or considering a libcall. Otherwise return 0. */
3361 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
3363 gcc_assert (!TARGET_64BIT);
3365 /* Use SSE registers to pass SFmode and DFmode arguments if requested
3366 by the sseregparm attribute. */
3367 if (TARGET_SSEREGPARM
3368 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
3375 error ("Calling %qD with attribute sseregparm without "
3376 "SSE/SSE2 enabled", decl);
3378 error ("Calling %qT with attribute sseregparm without "
3379 "SSE/SSE2 enabled", type);
3387 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3388 (and DFmode for SSE2) arguments in SSE registers. */
3389 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
3391 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3392 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3394 return TARGET_SSE2 ? 2 : 1;
3400 /* Return true if EAX is live at the start of the function. Used by
3401 ix86_expand_prologue to determine if we need special help before
3402 calling allocate_stack_worker. */
3405 ix86_eax_live_at_start_p (void)
3407 /* Cheat. Don't bother working forward from ix86_function_regparm
3408 to the function type to whether an actual argument is located in
3409 eax. Instead just look at cfg info, which is still close enough
3410 to correct at this point. This gives false positives for broken
3411 functions that might use uninitialized data that happens to be
3412 allocated in eax, but who cares? */
3413 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
3416 /* Value is the number of bytes of arguments automatically
3417 popped when returning from a subroutine call.
3418 FUNDECL is the declaration node of the function (as a tree),
3419 FUNTYPE is the data type of the function (as a tree),
3420 or for a library call it is an identifier node for the subroutine name.
3421 SIZE is the number of bytes of arguments passed on the stack.
3423 On the 80386, the RTD insn may be used to pop them if the number
3424 of args is fixed, but if the number is variable then the caller
3425 must pop them all. RTD can't be used for library calls now
3426 because the library is compiled with the Unix compiler.
3427 Use of RTD is a selectable option, since it is incompatible with
3428 standard Unix calling sequences. If the option is not selected,
3429 the caller must always pop the args.
3431 The attribute stdcall is equivalent to RTD on a per module basis. */
3434 ix86_return_pops_args (tree fundecl, tree funtype, int size)
3438 /* None of the 64-bit ABIs pop arguments. */
3442 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
3444 /* Cdecl functions override -mrtd, and never pop the stack. */
3445 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
3447 /* Stdcall and fastcall functions will pop the stack if not
3449 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
3450 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
3453 if (rtd && ! stdarg_p (funtype))
3457 /* Lose any fake structure return argument if it is passed on the stack. */
3458 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
3459 && !KEEP_AGGREGATE_RETURN_POINTER)
3461 int nregs = ix86_function_regparm (funtype, fundecl);
3463 return GET_MODE_SIZE (Pmode);
3469 /* Argument support functions. */
3471 /* Return true when register may be used to pass function parameters. */
3473 ix86_function_arg_regno_p (int regno)
3476 const int *parm_regs;
3481 return (regno < REGPARM_MAX
3482 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3484 return (regno < REGPARM_MAX
3485 || (TARGET_MMX && MMX_REGNO_P (regno)
3486 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3487 || (TARGET_SSE && SSE_REGNO_P (regno)
3488 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3493 if (SSE_REGNO_P (regno) && TARGET_SSE)
3498 if (TARGET_SSE && SSE_REGNO_P (regno)
3499 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3503 /* RAX is used as hidden argument to va_arg functions. */
3504 if (!TARGET_64BIT_MS_ABI && regno == AX_REG)
3507 if (TARGET_64BIT_MS_ABI)
3508 parm_regs = x86_64_ms_abi_int_parameter_registers;
3510 parm_regs = x86_64_int_parameter_registers;
3511 for (i = 0; i < REGPARM_MAX; i++)
3512 if (regno == parm_regs[i])
3517 /* Return if we do not know how to pass TYPE solely in registers. */
3520 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
3522 if (must_pass_in_stack_var_size_or_pad (mode, type))
3525 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3526 The layout_type routine is crafty and tries to trick us into passing
3527 currently unsupported vector types on the stack by using TImode. */
3528 return (!TARGET_64BIT && mode == TImode
3529 && type && TREE_CODE (type) != VECTOR_TYPE);
3532 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3533 for a call to a function whose data type is FNTYPE.
3534 For a library call, FNTYPE is 0. */
3537 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3538 tree fntype, /* tree ptr for function decl */
3539 rtx libname, /* SYMBOL_REF of library name or 0 */
3542 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
3543 memset (cum, 0, sizeof (*cum));
3545 /* Set up the number of registers to use for passing arguments. */
3546 cum->nregs = ix86_regparm;
3548 cum->sse_nregs = SSE_REGPARM_MAX;
3550 cum->mmx_nregs = MMX_REGPARM_MAX;
3551 cum->warn_sse = true;
3552 cum->warn_mmx = true;
3554 /* Because type might mismatch in between caller and callee, we need to
3555 use actual type of function for local calls.
3556 FIXME: cgraph_analyze can be told to actually record if function uses
3557 va_start so for local functions maybe_vaarg can be made aggressive
3559 FIXME: once typesytem is fixed, we won't need this code anymore. */
3561 fntype = TREE_TYPE (fndecl);
3562 cum->maybe_vaarg = (fntype
3563 ? (!prototype_p (fntype) || stdarg_p (fntype))
3568 /* If there are variable arguments, then we won't pass anything
3569 in registers in 32-bit mode. */
3570 if (stdarg_p (fntype))
3580 /* Use ecx and edx registers if function has fastcall attribute,
3581 else look for regparm information. */
3584 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3590 cum->nregs = ix86_function_regparm (fntype, fndecl);
3593 /* Set up the number of SSE registers used for passing SFmode
3594 and DFmode arguments. Warn for mismatching ABI. */
3595 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
3599 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3600 But in the case of vector types, it is some vector mode.
3602 When we have only some of our vector isa extensions enabled, then there
3603 are some modes for which vector_mode_supported_p is false. For these
3604 modes, the generic vector support in gcc will choose some non-vector mode
3605 in order to implement the type. By computing the natural mode, we'll
3606 select the proper ABI location for the operand and not depend on whatever
3607 the middle-end decides to do with these vector types. */
3609 static enum machine_mode
3610 type_natural_mode (const_tree type)
3612 enum machine_mode mode = TYPE_MODE (type);
3614 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3616 HOST_WIDE_INT size = int_size_in_bytes (type);
3617 if ((size == 8 || size == 16)
3618 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3619 && TYPE_VECTOR_SUBPARTS (type) > 1)
3621 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3623 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3624 mode = MIN_MODE_VECTOR_FLOAT;
3626 mode = MIN_MODE_VECTOR_INT;
3628 /* Get the mode which has this inner mode and number of units. */
3629 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3630 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3631 && GET_MODE_INNER (mode) == innermode)
3641 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3642 this may not agree with the mode that the type system has chosen for the
3643 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3644 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3647 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3652 if (orig_mode != BLKmode)
3653 tmp = gen_rtx_REG (orig_mode, regno);
3656 tmp = gen_rtx_REG (mode, regno);
3657 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3658 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3664 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3665 of this code is to classify each 8bytes of incoming argument by the register
3666 class and assign registers accordingly. */
3668 /* Return the union class of CLASS1 and CLASS2.
3669 See the x86-64 PS ABI for details. */
3671 static enum x86_64_reg_class
3672 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3674 /* Rule #1: If both classes are equal, this is the resulting class. */
3675 if (class1 == class2)
3678 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3680 if (class1 == X86_64_NO_CLASS)
3682 if (class2 == X86_64_NO_CLASS)
3685 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3686 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3687 return X86_64_MEMORY_CLASS;
3689 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3690 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3691 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3692 return X86_64_INTEGERSI_CLASS;
3693 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3694 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3695 return X86_64_INTEGER_CLASS;
3697 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3699 if (class1 == X86_64_X87_CLASS
3700 || class1 == X86_64_X87UP_CLASS
3701 || class1 == X86_64_COMPLEX_X87_CLASS
3702 || class2 == X86_64_X87_CLASS
3703 || class2 == X86_64_X87UP_CLASS
3704 || class2 == X86_64_COMPLEX_X87_CLASS)
3705 return X86_64_MEMORY_CLASS;
3707 /* Rule #6: Otherwise class SSE is used. */
3708 return X86_64_SSE_CLASS;
3711 /* Classify the argument of type TYPE and mode MODE.
3712 CLASSES will be filled by the register class used to pass each word
3713 of the operand. The number of words is returned. In case the parameter
3714 should be passed in memory, 0 is returned. As a special case for zero
3715 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3717 BIT_OFFSET is used internally for handling records and specifies offset
3718 of the offset in bits modulo 256 to avoid overflow cases.
3720 See the x86-64 PS ABI for details.
3724 classify_argument (enum machine_mode mode, const_tree type,
3725 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3727 HOST_WIDE_INT bytes =
3728 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3729 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3731 /* Variable sized entities are always passed/returned in memory. */
3735 if (mode != VOIDmode
3736 && targetm.calls.must_pass_in_stack (mode, type))
3739 if (type && AGGREGATE_TYPE_P (type))
3743 enum x86_64_reg_class subclasses[MAX_CLASSES];
3745 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3749 for (i = 0; i < words; i++)
3750 classes[i] = X86_64_NO_CLASS;
3752 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3753 signalize memory class, so handle it as special case. */
3756 classes[0] = X86_64_NO_CLASS;
3760 /* Classify each field of record and merge classes. */
3761 switch (TREE_CODE (type))
3764 /* And now merge the fields of structure. */
3765 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3767 if (TREE_CODE (field) == FIELD_DECL)
3771 if (TREE_TYPE (field) == error_mark_node)
3774 /* Bitfields are always classified as integer. Handle them
3775 early, since later code would consider them to be
3776 misaligned integers. */
3777 if (DECL_BIT_FIELD (field))
3779 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3780 i < ((int_bit_position (field) + (bit_offset % 64))
3781 + tree_low_cst (DECL_SIZE (field), 0)
3784 merge_classes (X86_64_INTEGER_CLASS,
3789 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3790 TREE_TYPE (field), subclasses,
3791 (int_bit_position (field)
3792 + bit_offset) % 256);
3795 for (i = 0; i < num; i++)
3798 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3800 merge_classes (subclasses[i], classes[i + pos]);
3808 /* Arrays are handled as small records. */
3811 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3812 TREE_TYPE (type), subclasses, bit_offset);
3816 /* The partial classes are now full classes. */
3817 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3818 subclasses[0] = X86_64_SSE_CLASS;
3819 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3820 subclasses[0] = X86_64_INTEGER_CLASS;
3822 for (i = 0; i < words; i++)
3823 classes[i] = subclasses[i % num];
3828 case QUAL_UNION_TYPE:
3829 /* Unions are similar to RECORD_TYPE but offset is always 0.
3831 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3833 if (TREE_CODE (field) == FIELD_DECL)
3837 if (TREE_TYPE (field) == error_mark_node)
3840 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3841 TREE_TYPE (field), subclasses,
3845 for (i = 0; i < num; i++)
3846 classes[i] = merge_classes (subclasses[i], classes[i]);
3855 /* Final merger cleanup. */
3856 for (i = 0; i < words; i++)
3858 /* If one class is MEMORY, everything should be passed in
3860 if (classes[i] == X86_64_MEMORY_CLASS)
3863 /* The X86_64_SSEUP_CLASS should be always preceded by
3864 X86_64_SSE_CLASS. */
3865 if (classes[i] == X86_64_SSEUP_CLASS
3866 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3867 classes[i] = X86_64_SSE_CLASS;
3869 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3870 if (classes[i] == X86_64_X87UP_CLASS
3871 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3872 classes[i] = X86_64_SSE_CLASS;
3877 /* Compute alignment needed. We align all types to natural boundaries with
3878 exception of XFmode that is aligned to 64bits. */
3879 if (mode != VOIDmode && mode != BLKmode)
3881 int mode_alignment = GET_MODE_BITSIZE (mode);
3884 mode_alignment = 128;
3885 else if (mode == XCmode)
3886 mode_alignment = 256;
3887 if (COMPLEX_MODE_P (mode))
3888 mode_alignment /= 2;
3889 /* Misaligned fields are always returned in memory. */
3890 if (bit_offset % mode_alignment)
3894 /* for V1xx modes, just use the base mode */
3895 if (VECTOR_MODE_P (mode) && mode != V1DImode
3896 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3897 mode = GET_MODE_INNER (mode);
3899 /* Classification of atomic types. */
3904 classes[0] = X86_64_SSE_CLASS;
3907 classes[0] = X86_64_SSE_CLASS;
3908 classes[1] = X86_64_SSEUP_CLASS;
3917 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3918 classes[0] = X86_64_INTEGERSI_CLASS;
3920 classes[0] = X86_64_INTEGER_CLASS;
3924 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3929 if (!(bit_offset % 64))
3930 classes[0] = X86_64_SSESF_CLASS;
3932 classes[0] = X86_64_SSE_CLASS;
3935 classes[0] = X86_64_SSEDF_CLASS;
3938 classes[0] = X86_64_X87_CLASS;
3939 classes[1] = X86_64_X87UP_CLASS;
3942 classes[0] = X86_64_SSE_CLASS;
3943 classes[1] = X86_64_SSEUP_CLASS;
3946 classes[0] = X86_64_SSE_CLASS;
3949 classes[0] = X86_64_SSEDF_CLASS;
3950 classes[1] = X86_64_SSEDF_CLASS;
3953 classes[0] = X86_64_COMPLEX_X87_CLASS;
3956 /* This modes is larger than 16 bytes. */
3964 classes[0] = X86_64_SSE_CLASS;
3965 classes[1] = X86_64_SSEUP_CLASS;
3972 classes[0] = X86_64_SSE_CLASS;
3978 gcc_assert (VECTOR_MODE_P (mode));
3983 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3985 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3986 classes[0] = X86_64_INTEGERSI_CLASS;
3988 classes[0] = X86_64_INTEGER_CLASS;
3989 classes[1] = X86_64_INTEGER_CLASS;
3990 return 1 + (bytes > 8);
3994 /* Examine the argument and return set number of register required in each
3995 class. Return 0 iff parameter should be passed in memory. */
3997 examine_argument (enum machine_mode mode, const_tree type, int in_return,
3998 int *int_nregs, int *sse_nregs)
4000 enum x86_64_reg_class regclass[MAX_CLASSES];
4001 int n = classify_argument (mode, type, regclass, 0);
4007 for (n--; n >= 0; n--)
4008 switch (regclass[n])
4010 case X86_64_INTEGER_CLASS:
4011 case X86_64_INTEGERSI_CLASS:
4014 case X86_64_SSE_CLASS:
4015 case X86_64_SSESF_CLASS:
4016 case X86_64_SSEDF_CLASS:
4019 case X86_64_NO_CLASS:
4020 case X86_64_SSEUP_CLASS:
4022 case X86_64_X87_CLASS:
4023 case X86_64_X87UP_CLASS:
4027 case X86_64_COMPLEX_X87_CLASS:
4028 return in_return ? 2 : 0;
4029 case X86_64_MEMORY_CLASS:
4035 /* Construct container for the argument used by GCC interface. See
4036 FUNCTION_ARG for the detailed description. */
4039 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
4040 const_tree type, int in_return, int nintregs, int nsseregs,
4041 const int *intreg, int sse_regno)
4043 /* The following variables hold the static issued_error state. */
4044 static bool issued_sse_arg_error;
4045 static bool issued_sse_ret_error;
4046 static bool issued_x87_ret_error;
4048 enum machine_mode tmpmode;
4050 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4051 enum x86_64_reg_class regclass[MAX_CLASSES];
4055 int needed_sseregs, needed_intregs;
4056 rtx exp[MAX_CLASSES];
4059 n = classify_argument (mode, type, regclass, 0);
4062 if (!examine_argument (mode, type, in_return, &needed_intregs,
4065 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
4068 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
4069 some less clueful developer tries to use floating-point anyway. */
4070 if (needed_sseregs && !TARGET_SSE)
4074 if (!issued_sse_ret_error)
4076 error ("SSE register return with SSE disabled");
4077 issued_sse_ret_error = true;
4080 else if (!issued_sse_arg_error)
4082 error ("SSE register argument with SSE disabled");
4083 issued_sse_arg_error = true;
4088 /* Likewise, error if the ABI requires us to return values in the
4089 x87 registers and the user specified -mno-80387. */
4090 if (!TARGET_80387 && in_return)
4091 for (i = 0; i < n; i++)
4092 if (regclass[i] == X86_64_X87_CLASS
4093 || regclass[i] == X86_64_X87UP_CLASS
4094 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
4096 if (!issued_x87_ret_error)
4098 error ("x87 register return with x87 disabled");
4099 issued_x87_ret_error = true;
4104 /* First construct simple cases. Avoid SCmode, since we want to use
4105 single register to pass this type. */
4106 if (n == 1 && mode != SCmode)
4107 switch (regclass[0])
4109 case X86_64_INTEGER_CLASS:
4110 case X86_64_INTEGERSI_CLASS:
4111 return gen_rtx_REG (mode, intreg[0]);
4112 case X86_64_SSE_CLASS:
4113 case X86_64_SSESF_CLASS:
4114 case X86_64_SSEDF_CLASS:
4115 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
4116 case X86_64_X87_CLASS:
4117 case X86_64_COMPLEX_X87_CLASS:
4118 return gen_rtx_REG (mode, FIRST_STACK_REG);
4119 case X86_64_NO_CLASS:
4120 /* Zero sized array, struct or class. */
4125 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
4126 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
4127 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
4130 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
4131 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
4132 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
4133 && regclass[1] == X86_64_INTEGER_CLASS
4134 && (mode == CDImode || mode == TImode || mode == TFmode)
4135 && intreg[0] + 1 == intreg[1])
4136 return gen_rtx_REG (mode, intreg[0]);
4138 /* Otherwise figure out the entries of the PARALLEL. */
4139 for (i = 0; i < n; i++)
4141 switch (regclass[i])
4143 case X86_64_NO_CLASS:
4145 case X86_64_INTEGER_CLASS:
4146 case X86_64_INTEGERSI_CLASS:
4147 /* Merge TImodes on aligned occasions here too. */
4148 if (i * 8 + 8 > bytes)
4149 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
4150 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
4154 /* We've requested 24 bytes we don't have mode for. Use DImode. */
4155 if (tmpmode == BLKmode)
4157 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4158 gen_rtx_REG (tmpmode, *intreg),
4162 case X86_64_SSESF_CLASS:
4163 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4164 gen_rtx_REG (SFmode,
4165 SSE_REGNO (sse_regno)),
4169 case X86_64_SSEDF_CLASS:
4170 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4171 gen_rtx_REG (DFmode,
4172 SSE_REGNO (sse_regno)),
4176 case X86_64_SSE_CLASS:
4177 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
4181 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4182 gen_rtx_REG (tmpmode,
4183 SSE_REGNO (sse_regno)),
4185 if (tmpmode == TImode)
4194 /* Empty aligned struct, union or class. */
4198 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
4199 for (i = 0; i < nexps; i++)
4200 XVECEXP (ret, 0, i) = exp [i];
4204 /* Update the data in CUM to advance over an argument of mode MODE
4205 and data type TYPE. (TYPE is null for libcalls where that information
4206 may not be available.) */
4209 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4210 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4226 cum->words += words;
4227 cum->nregs -= words;
4228 cum->regno += words;
4230 if (cum->nregs <= 0)
4238 if (cum->float_in_sse < 2)
4241 if (cum->float_in_sse < 1)
4252 if (!type || !AGGREGATE_TYPE_P (type))
4254 cum->sse_words += words;
4255 cum->sse_nregs -= 1;
4256 cum->sse_regno += 1;
4257 if (cum->sse_nregs <= 0)
4270 if (!type || !AGGREGATE_TYPE_P (type))
4272 cum->mmx_words += words;
4273 cum->mmx_nregs -= 1;
4274 cum->mmx_regno += 1;
4275 if (cum->mmx_nregs <= 0)
4286 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4287 tree type, HOST_WIDE_INT words)
4289 int int_nregs, sse_nregs;
4291 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
4292 cum->words += words;
4293 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
4295 cum->nregs -= int_nregs;
4296 cum->sse_nregs -= sse_nregs;
4297 cum->regno += int_nregs;
4298 cum->sse_regno += sse_nregs;
4301 cum->words += words;
4305 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
4306 HOST_WIDE_INT words)
4308 /* Otherwise, this should be passed indirect. */
4309 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
4311 cum->words += words;
4320 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4321 tree type, int named ATTRIBUTE_UNUSED)
4323 HOST_WIDE_INT bytes, words;
4325 if (mode == BLKmode)
4326 bytes = int_size_in_bytes (type);
4328 bytes = GET_MODE_SIZE (mode);
4329 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4332 mode = type_natural_mode (type);
4334 if (TARGET_64BIT_MS_ABI)
4335 function_arg_advance_ms_64 (cum, bytes, words);
4336 else if (TARGET_64BIT)
4337 function_arg_advance_64 (cum, mode, type, words);
4339 function_arg_advance_32 (cum, mode, type, bytes, words);
4342 /* Define where to put the arguments to a function.
4343 Value is zero to push the argument on the stack,
4344 or a hard register in which to store the argument.
4346 MODE is the argument's machine mode.
4347 TYPE is the data type of the argument (as a tree).
4348 This is null for libcalls where that information may
4350 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4351 the preceding args and about the function being called.
4352 NAMED is nonzero if this argument is a named parameter
4353 (otherwise it is an extra parameter matching an ellipsis). */
4356 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4357 enum machine_mode orig_mode, tree type,
4358 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4360 static bool warnedsse, warnedmmx;
4362 /* Avoid the AL settings for the Unix64 ABI. */
4363 if (mode == VOIDmode)
4379 if (words <= cum->nregs)
4381 int regno = cum->regno;
4383 /* Fastcall allocates the first two DWORD (SImode) or
4384 smaller arguments to ECX and EDX if it isn't an
4390 || (type && AGGREGATE_TYPE_P (type)))
4393 /* ECX not EAX is the first allocated register. */
4394 if (regno == AX_REG)
4397 return gen_rtx_REG (mode, regno);
4402 if (cum->float_in_sse < 2)
4405 if (cum->float_in_sse < 1)
4415 if (!type || !AGGREGATE_TYPE_P (type))
4417 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
4420 warning (0, "SSE vector argument without SSE enabled "
4424 return gen_reg_or_parallel (mode, orig_mode,
4425 cum->sse_regno + FIRST_SSE_REG);
4434 if (!type || !AGGREGATE_TYPE_P (type))
4436 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
4439 warning (0, "MMX vector argument without MMX enabled "
4443 return gen_reg_or_parallel (mode, orig_mode,
4444 cum->mmx_regno + FIRST_MMX_REG);
4453 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4454 enum machine_mode orig_mode, tree type)
4456 /* Handle a hidden AL argument containing number of registers
4457 for varargs x86-64 functions. */
4458 if (mode == VOIDmode)
4459 return GEN_INT (cum->maybe_vaarg
4460 ? (cum->sse_nregs < 0
4465 return construct_container (mode, orig_mode, type, 0, cum->nregs,
4467 &x86_64_int_parameter_registers [cum->regno],
4472 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4473 enum machine_mode orig_mode, int named,
4474 HOST_WIDE_INT bytes)
4478 /* Avoid the AL settings for the Unix64 ABI. */
4479 if (mode == VOIDmode)
4482 /* If we've run out of registers, it goes on the stack. */
4483 if (cum->nregs == 0)
4486 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4488 /* Only floating point modes are passed in anything but integer regs. */
4489 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4492 regno = cum->regno + FIRST_SSE_REG;
4497 /* Unnamed floating parameters are passed in both the
4498 SSE and integer registers. */
4499 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4500 t2 = gen_rtx_REG (mode, regno);
4501 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4502 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4503 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4506 /* Handle aggregated types passed in register. */
4507 if (orig_mode == BLKmode)
4509 if (bytes > 0 && bytes <= 8)
4510 mode = (bytes > 4 ? DImode : SImode);
4511 if (mode == BLKmode)
4515 return gen_reg_or_parallel (mode, orig_mode, regno);
4519 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4520 tree type, int named)
4522 enum machine_mode mode = omode;
4523 HOST_WIDE_INT bytes, words;
4525 if (mode == BLKmode)
4526 bytes = int_size_in_bytes (type);
4528 bytes = GET_MODE_SIZE (mode);
4529 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4531 /* To simplify the code below, represent vector types with a vector mode
4532 even if MMX/SSE are not active. */
4533 if (type && TREE_CODE (type) == VECTOR_TYPE)
4534 mode = type_natural_mode (type);
4536 if (TARGET_64BIT_MS_ABI)
4537 return function_arg_ms_64 (cum, mode, omode, named, bytes);
4538 else if (TARGET_64BIT)
4539 return function_arg_64 (cum, mode, omode, type);
4541 return function_arg_32 (cum, mode, omode, type, bytes, words);
4544 /* A C expression that indicates when an argument must be passed by
4545 reference. If nonzero for an argument, a copy of that argument is
4546 made in memory and a pointer to the argument is passed instead of
4547 the argument itself. The pointer is passed in whatever way is
4548 appropriate for passing a pointer to that type. */
4551 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4552 enum machine_mode mode ATTRIBUTE_UNUSED,
4553 const_tree type, bool named ATTRIBUTE_UNUSED)
4555 /* See Windows x64 Software Convention. */
4556 if (TARGET_64BIT_MS_ABI)
4558 int msize = (int) GET_MODE_SIZE (mode);
4561 /* Arrays are passed by reference. */
4562 if (TREE_CODE (type) == ARRAY_TYPE)
4565 if (AGGREGATE_TYPE_P (type))
4567 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4568 are passed by reference. */
4569 msize = int_size_in_bytes (type);
4573 /* __m128 is passed by reference. */
4575 case 1: case 2: case 4: case 8:
4581 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4587 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4590 contains_aligned_value_p (tree type)
4592 enum machine_mode mode = TYPE_MODE (type);
4593 if (((TARGET_SSE && SSE_REG_MODE_P (mode)) || mode == TDmode)
4594 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4596 if (TYPE_ALIGN (type) < 128)
4599 if (AGGREGATE_TYPE_P (type))
4601 /* Walk the aggregates recursively. */
4602 switch (TREE_CODE (type))
4606 case QUAL_UNION_TYPE:
4610 /* Walk all the structure fields. */
4611 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4613 if (TREE_CODE (field) == FIELD_DECL
4614 && contains_aligned_value_p (TREE_TYPE (field)))
4621 /* Just for use if some languages passes arrays by value. */
4622 if (contains_aligned_value_p (TREE_TYPE (type)))
4633 /* Gives the alignment boundary, in bits, of an argument with the
4634 specified mode and type. */
4637 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4642 if (TYPE_STRUCTURAL_EQUALITY_P (type))
4643 align = TYPE_ALIGN (type);
4645 align = TYPE_ALIGN (TYPE_CANONICAL (type));
4648 align = GET_MODE_ALIGNMENT (mode);
4649 if (align < PARM_BOUNDARY)
4650 align = PARM_BOUNDARY;
4651 /* In 32bit, only _Decimal128 is aligned to its natural boundary. */
4652 if (!TARGET_64BIT && mode != TDmode)
4654 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4655 make an exception for SSE modes since these require 128bit
4658 The handling here differs from field_alignment. ICC aligns MMX
4659 arguments to 4 byte boundaries, while structure fields are aligned
4660 to 8 byte boundaries. */
4663 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)) && mode != TDmode)
4664 align = PARM_BOUNDARY;
4668 if (!contains_aligned_value_p (type))
4669 align = PARM_BOUNDARY;
4672 if (align > BIGGEST_ALIGNMENT)
4673 align = BIGGEST_ALIGNMENT;
4677 /* Return true if N is a possible register number of function value. */
4680 ix86_function_value_regno_p (int regno)
4687 case FIRST_FLOAT_REG:
4688 if (TARGET_64BIT_MS_ABI)
4690 return TARGET_FLOAT_RETURNS_IN_80387;
4696 if (TARGET_MACHO || TARGET_64BIT)
4704 /* Define how to find the value returned by a function.
4705 VALTYPE is the data type of the value (as a tree).
4706 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4707 otherwise, FUNC is 0. */
4710 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4711 const_tree fntype, const_tree fn)
4715 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4716 we normally prevent this case when mmx is not available. However
4717 some ABIs may require the result to be returned like DImode. */
4718 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4719 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4721 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4722 we prevent this case when sse is not available. However some ABIs
4723 may require the result to be returned like integer TImode. */
4724 else if (mode == TImode
4725 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4726 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4728 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4729 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4730 regno = FIRST_FLOAT_REG;
4732 /* Most things go in %eax. */
4735 /* Override FP return register with %xmm0 for local functions when
4736 SSE math is enabled or for functions with sseregparm attribute. */
4737 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4739 int sse_level = ix86_function_sseregparm (fntype, fn, false);
4740 if ((sse_level >= 1 && mode == SFmode)
4741 || (sse_level == 2 && mode == DFmode))
4742 regno = FIRST_SSE_REG;
4745 return gen_rtx_REG (orig_mode, regno);
4749 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4754 /* Handle libcalls, which don't provide a type node. */
4755 if (valtype == NULL)
4767 return gen_rtx_REG (mode, FIRST_SSE_REG);
4770 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4774 return gen_rtx_REG (mode, AX_REG);
4778 ret = construct_container (mode, orig_mode, valtype, 1,
4779 REGPARM_MAX, SSE_REGPARM_MAX,
4780 x86_64_int_return_registers, 0);
4782 /* For zero sized structures, construct_container returns NULL, but we
4783 need to keep rest of compiler happy by returning meaningful value. */
4785 ret = gen_rtx_REG (orig_mode, AX_REG);
4791 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4793 unsigned int regno = AX_REG;
4797 switch (GET_MODE_SIZE (mode))
4800 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
4801 && !COMPLEX_MODE_P (mode))
4802 regno = FIRST_SSE_REG;
4806 if (mode == SFmode || mode == DFmode)
4807 regno = FIRST_SSE_REG;
4813 return gen_rtx_REG (orig_mode, regno);
4817 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
4818 enum machine_mode orig_mode, enum machine_mode mode)
4820 const_tree fn, fntype;
4823 if (fntype_or_decl && DECL_P (fntype_or_decl))
4824 fn = fntype_or_decl;
4825 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4827 if (TARGET_64BIT_MS_ABI)
4828 return function_value_ms_64 (orig_mode, mode);
4829 else if (TARGET_64BIT)
4830 return function_value_64 (orig_mode, mode, valtype);
4832 return function_value_32 (orig_mode, mode, fntype, fn);
4836 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
4837 bool outgoing ATTRIBUTE_UNUSED)
4839 enum machine_mode mode, orig_mode;
4841 orig_mode = TYPE_MODE (valtype);
4842 mode = type_natural_mode (valtype);
4843 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
4847 ix86_libcall_value (enum machine_mode mode)
4849 return ix86_function_value_1 (NULL, NULL, mode, mode);
4852 /* Return true iff type is returned in memory. */
4854 static int ATTRIBUTE_UNUSED
4855 return_in_memory_32 (const_tree type, enum machine_mode mode)
4859 if (mode == BLKmode)
4862 size = int_size_in_bytes (type);
4864 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4867 if (VECTOR_MODE_P (mode) || mode == TImode)
4869 /* User-created vectors small enough to fit in EAX. */
4873 /* MMX/3dNow values are returned in MM0,
4874 except when it doesn't exits. */
4876 return (TARGET_MMX ? 0 : 1);
4878 /* SSE values are returned in XMM0, except when it doesn't exist. */
4880 return (TARGET_SSE ? 0 : 1);
4894 static int ATTRIBUTE_UNUSED
4895 return_in_memory_64 (const_tree type, enum machine_mode mode)
4897 int needed_intregs, needed_sseregs;
4898 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4901 static int ATTRIBUTE_UNUSED
4902 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
4904 HOST_WIDE_INT size = int_size_in_bytes (type);
4906 /* __m128 is returned in xmm0. */
4907 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
4908 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
4911 /* Otherwise, the size must be exactly in [1248]. */
4912 return (size != 1 && size != 2 && size != 4 && size != 8);
4916 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
4918 #ifdef SUBTARGET_RETURN_IN_MEMORY
4919 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
4921 const enum machine_mode mode = type_natural_mode (type);
4923 if (TARGET_64BIT_MS_ABI)
4924 return return_in_memory_ms_64 (type, mode);
4925 else if (TARGET_64BIT)
4926 return return_in_memory_64 (type, mode);
4928 return return_in_memory_32 (type, mode);
4932 /* Return false iff TYPE is returned in memory. This version is used
4933 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4934 but differs notably in that when MMX is available, 8-byte vectors
4935 are returned in memory, rather than in MMX registers. */
4938 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
4941 enum machine_mode mode = type_natural_mode (type);
4944 return return_in_memory_64 (type, mode);
4946 if (mode == BLKmode)
4949 size = int_size_in_bytes (type);
4951 if (VECTOR_MODE_P (mode))
4953 /* Return in memory only if MMX registers *are* available. This
4954 seems backwards, but it is consistent with the existing
4961 else if (mode == TImode)
4963 else if (mode == XFmode)
4969 /* When returning SSE vector types, we have a choice of either
4970 (1) being abi incompatible with a -march switch, or
4971 (2) generating an error.
4972 Given no good solution, I think the safest thing is one warning.
4973 The user won't be able to use -Werror, but....
4975 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4976 called in response to actually generating a caller or callee that
4977 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
4978 via aggregate_value_p for general type probing from tree-ssa. */
4981 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4983 static bool warnedsse, warnedmmx;
4985 if (!TARGET_64BIT && type)
4987 /* Look at the return type of the function, not the function type. */
4988 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4990 if (!TARGET_SSE && !warnedsse)
4993 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4996 warning (0, "SSE vector return without SSE enabled "
5001 if (!TARGET_MMX && !warnedmmx)
5003 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
5006 warning (0, "MMX vector return without MMX enabled "
5016 /* Create the va_list data type. */
5019 ix86_build_builtin_va_list (void)
5021 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
5023 /* For i386 we use plain pointer to argument area. */
5024 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5025 return build_pointer_type (char_type_node);
5027 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5028 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5030 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
5031 unsigned_type_node);
5032 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
5033 unsigned_type_node);
5034 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5036 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5039 va_list_gpr_counter_field = f_gpr;
5040 va_list_fpr_counter_field = f_fpr;
5042 DECL_FIELD_CONTEXT (f_gpr) = record;
5043 DECL_FIELD_CONTEXT (f_fpr) = record;
5044 DECL_FIELD_CONTEXT (f_ovf) = record;
5045 DECL_FIELD_CONTEXT (f_sav) = record;
5047 TREE_CHAIN (record) = type_decl;
5048 TYPE_NAME (record) = type_decl;
5049 TYPE_FIELDS (record) = f_gpr;
5050 TREE_CHAIN (f_gpr) = f_fpr;
5051 TREE_CHAIN (f_fpr) = f_ovf;
5052 TREE_CHAIN (f_ovf) = f_sav;
5054 layout_type (record);
5056 /* The correct type is an array type of one element. */
5057 return build_array_type (record, build_index_type (size_zero_node));
5060 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
5063 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
5073 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
5076 /* Indicate to allocate space on the stack for varargs save area. */
5077 ix86_save_varrargs_registers = 1;
5078 /* We need 16-byte stack alignment to save SSE registers. If user
5079 asked for lower preferred_stack_boundary, lets just hope that he knows
5080 what he is doing and won't varargs SSE values.
5082 We also may end up assuming that only 64bit values are stored in SSE
5083 register let some floating point program work. */
5084 if (ix86_preferred_stack_boundary >= BIGGEST_ALIGNMENT)
5085 crtl->stack_alignment_needed = BIGGEST_ALIGNMENT;
5087 save_area = frame_pointer_rtx;
5088 set = get_varargs_alias_set ();
5090 for (i = cum->regno;
5092 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
5095 mem = gen_rtx_MEM (Pmode,
5096 plus_constant (save_area, i * UNITS_PER_WORD));
5097 MEM_NOTRAP_P (mem) = 1;
5098 set_mem_alias_set (mem, set);
5099 emit_move_insn (mem, gen_rtx_REG (Pmode,
5100 x86_64_int_parameter_registers[i]));
5103 if (cum->sse_nregs && cfun->va_list_fpr_size)
5105 /* Now emit code to save SSE registers. The AX parameter contains number
5106 of SSE parameter registers used to call this function. We use
5107 sse_prologue_save insn template that produces computed jump across
5108 SSE saves. We need some preparation work to get this working. */
5110 label = gen_label_rtx ();
5111 label_ref = gen_rtx_LABEL_REF (Pmode, label);
5113 /* Compute address to jump to :
5114 label - 5*eax + nnamed_sse_arguments*5 */
5115 tmp_reg = gen_reg_rtx (Pmode);
5116 nsse_reg = gen_reg_rtx (Pmode);
5117 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
5118 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5119 gen_rtx_MULT (Pmode, nsse_reg,
5124 gen_rtx_CONST (DImode,
5125 gen_rtx_PLUS (DImode,
5127 GEN_INT (cum->sse_regno * 4))));
5129 emit_move_insn (nsse_reg, label_ref);
5130 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
5132 /* Compute address of memory block we save into. We always use pointer
5133 pointing 127 bytes after first byte to store - this is needed to keep
5134 instruction size limited by 4 bytes. */
5135 tmp_reg = gen_reg_rtx (Pmode);
5136 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5137 plus_constant (save_area,
5138 8 * REGPARM_MAX + 127)));
5139 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
5140 MEM_NOTRAP_P (mem) = 1;
5141 set_mem_alias_set (mem, set);
5142 set_mem_align (mem, BITS_PER_WORD);
5144 /* And finally do the dirty job! */
5145 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
5146 GEN_INT (cum->sse_regno), label));
5151 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
5153 alias_set_type set = get_varargs_alias_set ();
5156 for (i = cum->regno; i < REGPARM_MAX; i++)
5160 mem = gen_rtx_MEM (Pmode,
5161 plus_constant (virtual_incoming_args_rtx,
5162 i * UNITS_PER_WORD));
5163 MEM_NOTRAP_P (mem) = 1;
5164 set_mem_alias_set (mem, set);
5166 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
5167 emit_move_insn (mem, reg);
5172 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5173 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5176 CUMULATIVE_ARGS next_cum;
5179 /* This argument doesn't appear to be used anymore. Which is good,
5180 because the old code here didn't suppress rtl generation. */
5181 gcc_assert (!no_rtl);
5186 fntype = TREE_TYPE (current_function_decl);
5188 /* For varargs, we do not want to skip the dummy va_dcl argument.
5189 For stdargs, we do want to skip the last named argument. */
5191 if (stdarg_p (fntype))
5192 function_arg_advance (&next_cum, mode, type, 1);
5194 if (TARGET_64BIT_MS_ABI)
5195 setup_incoming_varargs_ms_64 (&next_cum);
5197 setup_incoming_varargs_64 (&next_cum);
5200 /* Implement va_start. */
5203 ix86_va_start (tree valist, rtx nextarg)
5205 HOST_WIDE_INT words, n_gpr, n_fpr;
5206 tree f_gpr, f_fpr, f_ovf, f_sav;
5207 tree gpr, fpr, ovf, sav, t;
5210 /* Only 64bit target needs something special. */
5211 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5213 std_expand_builtin_va_start (valist, nextarg);
5217 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5218 f_fpr = TREE_CHAIN (f_gpr);
5219 f_ovf = TREE_CHAIN (f_fpr);
5220 f_sav = TREE_CHAIN (f_ovf);
5222 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5223 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5224 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5225 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5226 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5228 /* Count number of gp and fp argument registers used. */
5229 words = crtl->args.info.words;
5230 n_gpr = crtl->args.info.regno;
5231 n_fpr = crtl->args.info.sse_regno;
5233 if (cfun->va_list_gpr_size)
5235 type = TREE_TYPE (gpr);
5236 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
5237 build_int_cst (type, n_gpr * 8));
5238 TREE_SIDE_EFFECTS (t) = 1;
5239 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5242 if (cfun->va_list_fpr_size)
5244 type = TREE_TYPE (fpr);
5245 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
5246 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
5247 TREE_SIDE_EFFECTS (t) = 1;
5248 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5251 /* Find the overflow area. */
5252 type = TREE_TYPE (ovf);
5253 t = make_tree (type, virtual_incoming_args_rtx);
5255 t = build2 (POINTER_PLUS_EXPR, type, t,
5256 size_int (words * UNITS_PER_WORD));
5257 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
5258 TREE_SIDE_EFFECTS (t) = 1;
5259 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5261 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
5263 /* Find the register save area.
5264 Prologue of the function save it right above stack frame. */
5265 type = TREE_TYPE (sav);
5266 t = make_tree (type, frame_pointer_rtx);
5267 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
5268 TREE_SIDE_EFFECTS (t) = 1;
5269 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5273 /* Implement va_arg. */
5276 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5278 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
5279 tree f_gpr, f_fpr, f_ovf, f_sav;
5280 tree gpr, fpr, ovf, sav, t;
5282 tree lab_false, lab_over = NULL_TREE;
5287 enum machine_mode nat_mode;
5289 /* Only 64bit target needs something special. */
5290 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5291 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5293 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5294 f_fpr = TREE_CHAIN (f_gpr);
5295 f_ovf = TREE_CHAIN (f_fpr);
5296 f_sav = TREE_CHAIN (f_ovf);
5298 valist = build_va_arg_indirect_ref (valist);
5299 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5300 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5301 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5302 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5304 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5306 type = build_pointer_type (type);
5307 size = int_size_in_bytes (type);
5308 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5310 nat_mode = type_natural_mode (type);
5311 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
5312 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
5314 /* Pull the value out of the saved registers. */
5316 addr = create_tmp_var (ptr_type_node, "addr");
5317 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5321 int needed_intregs, needed_sseregs;
5323 tree int_addr, sse_addr;
5325 lab_false = create_artificial_label ();
5326 lab_over = create_artificial_label ();
5328 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
5330 need_temp = (!REG_P (container)
5331 && ((needed_intregs && TYPE_ALIGN (type) > 64)
5332 || TYPE_ALIGN (type) > 128));
5334 /* In case we are passing structure, verify that it is consecutive block
5335 on the register save area. If not we need to do moves. */
5336 if (!need_temp && !REG_P (container))
5338 /* Verify that all registers are strictly consecutive */
5339 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
5343 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5345 rtx slot = XVECEXP (container, 0, i);
5346 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
5347 || INTVAL (XEXP (slot, 1)) != i * 16)
5355 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5357 rtx slot = XVECEXP (container, 0, i);
5358 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
5359 || INTVAL (XEXP (slot, 1)) != i * 8)
5371 int_addr = create_tmp_var (ptr_type_node, "int_addr");
5372 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
5373 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
5374 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
5377 /* First ensure that we fit completely in registers. */
5380 t = build_int_cst (TREE_TYPE (gpr),
5381 (REGPARM_MAX - needed_intregs + 1) * 8);
5382 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
5383 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5384 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5385 gimplify_and_add (t, pre_p);
5389 t = build_int_cst (TREE_TYPE (fpr),
5390 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
5392 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
5393 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5394 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5395 gimplify_and_add (t, pre_p);
5398 /* Compute index to start of area used for integer regs. */
5401 /* int_addr = gpr + sav; */
5402 t = fold_convert (sizetype, gpr);
5403 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5404 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
5405 gimplify_and_add (t, pre_p);
5409 /* sse_addr = fpr + sav; */
5410 t = fold_convert (sizetype, fpr);
5411 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5412 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
5413 gimplify_and_add (t, pre_p);
5418 tree temp = create_tmp_var (type, "va_arg_tmp");
5421 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
5422 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5423 gimplify_and_add (t, pre_p);
5425 for (i = 0; i < XVECLEN (container, 0); i++)
5427 rtx slot = XVECEXP (container, 0, i);
5428 rtx reg = XEXP (slot, 0);
5429 enum machine_mode mode = GET_MODE (reg);
5430 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
5431 tree addr_type = build_pointer_type (piece_type);
5434 tree dest_addr, dest;
5436 if (SSE_REGNO_P (REGNO (reg)))
5438 src_addr = sse_addr;
5439 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
5443 src_addr = int_addr;
5444 src_offset = REGNO (reg) * 8;
5446 src_addr = fold_convert (addr_type, src_addr);
5447 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
5448 size_int (src_offset));
5449 src = build_va_arg_indirect_ref (src_addr);
5451 dest_addr = fold_convert (addr_type, addr);
5452 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
5453 size_int (INTVAL (XEXP (slot, 1))));
5454 dest = build_va_arg_indirect_ref (dest_addr);
5456 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
5457 gimplify_and_add (t, pre_p);
5463 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
5464 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
5465 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
5466 gimplify_and_add (t, pre_p);
5470 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
5471 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
5472 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
5473 gimplify_and_add (t, pre_p);
5476 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5477 gimplify_and_add (t, pre_p);
5479 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5480 append_to_statement_list (t, pre_p);
5483 /* ... otherwise out of the overflow area. */
5485 /* Care for on-stack alignment if needed. */
5486 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
5487 || integer_zerop (TYPE_SIZE (type)))
5491 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
5492 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
5493 size_int (align - 1));
5494 t = fold_convert (sizetype, t);
5495 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5497 t = fold_convert (TREE_TYPE (ovf), t);
5499 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5501 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5502 gimplify_and_add (t2, pre_p);
5504 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
5505 size_int (rsize * UNITS_PER_WORD));
5506 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
5507 gimplify_and_add (t, pre_p);
5511 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5512 append_to_statement_list (t, pre_p);
5515 ptrtype = build_pointer_type (type);
5516 addr = fold_convert (ptrtype, addr);
5519 addr = build_va_arg_indirect_ref (addr);
5520 return build_va_arg_indirect_ref (addr);
5523 /* Return nonzero if OPNUM's MEM should be matched
5524 in movabs* patterns. */
5527 ix86_check_movabs (rtx insn, int opnum)
5531 set = PATTERN (insn);
5532 if (GET_CODE (set) == PARALLEL)
5533 set = XVECEXP (set, 0, 0);
5534 gcc_assert (GET_CODE (set) == SET);
5535 mem = XEXP (set, opnum);
5536 while (GET_CODE (mem) == SUBREG)
5537 mem = SUBREG_REG (mem);
5538 gcc_assert (MEM_P (mem));
5539 return (volatile_ok || !MEM_VOLATILE_P (mem));
5542 /* Initialize the table of extra 80387 mathematical constants. */
5545 init_ext_80387_constants (void)
5547 static const char * cst[5] =
5549 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5550 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5551 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5552 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5553 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5557 for (i = 0; i < 5; i++)
5559 real_from_string (&ext_80387_constants_table[i], cst[i]);
5560 /* Ensure each constant is rounded to XFmode precision. */
5561 real_convert (&ext_80387_constants_table[i],
5562 XFmode, &ext_80387_constants_table[i]);
5565 ext_80387_constants_init = 1;
5568 /* Return true if the constant is something that can be loaded with
5569 a special instruction. */
5572 standard_80387_constant_p (rtx x)
5574 enum machine_mode mode = GET_MODE (x);
5578 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5581 if (x == CONST0_RTX (mode))
5583 if (x == CONST1_RTX (mode))
5586 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5588 /* For XFmode constants, try to find a special 80387 instruction when
5589 optimizing for size or on those CPUs that benefit from them. */
5591 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5595 if (! ext_80387_constants_init)
5596 init_ext_80387_constants ();
5598 for (i = 0; i < 5; i++)
5599 if (real_identical (&r, &ext_80387_constants_table[i]))
5603 /* Load of the constant -0.0 or -1.0 will be split as
5604 fldz;fchs or fld1;fchs sequence. */
5605 if (real_isnegzero (&r))
5607 if (real_identical (&r, &dconstm1))
5613 /* Return the opcode of the special instruction to be used to load
5617 standard_80387_constant_opcode (rtx x)
5619 switch (standard_80387_constant_p (x))
5643 /* Return the CONST_DOUBLE representing the 80387 constant that is
5644 loaded by the specified special instruction. The argument IDX
5645 matches the return value from standard_80387_constant_p. */
5648 standard_80387_constant_rtx (int idx)
5652 if (! ext_80387_constants_init)
5653 init_ext_80387_constants ();
5669 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5673 /* Return 1 if mode is a valid mode for sse. */
5675 standard_sse_mode_p (enum machine_mode mode)
5692 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5695 standard_sse_constant_p (rtx x)
5697 enum machine_mode mode = GET_MODE (x);
5699 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5701 if (vector_all_ones_operand (x, mode)
5702 && standard_sse_mode_p (mode))
5703 return TARGET_SSE2 ? 2 : -1;
5708 /* Return the opcode of the special instruction to be used to load
5712 standard_sse_constant_opcode (rtx insn, rtx x)
5714 switch (standard_sse_constant_p (x))
5717 if (get_attr_mode (insn) == MODE_V4SF)
5718 return "xorps\t%0, %0";
5719 else if (get_attr_mode (insn) == MODE_V2DF)
5720 return "xorpd\t%0, %0";
5722 return "pxor\t%0, %0";
5724 return "pcmpeqd\t%0, %0";
5729 /* Returns 1 if OP contains a symbol reference */
5732 symbolic_reference_mentioned_p (rtx op)
5737 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5740 fmt = GET_RTX_FORMAT (GET_CODE (op));
5741 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5747 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5748 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5752 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5759 /* Return 1 if it is appropriate to emit `ret' instructions in the
5760 body of a function. Do this only if the epilogue is simple, needing a
5761 couple of insns. Prior to reloading, we can't tell how many registers
5762 must be saved, so return 0 then. Return 0 if there is no frame
5763 marker to de-allocate. */
5766 ix86_can_use_return_insn_p (void)
5768 struct ix86_frame frame;
5770 if (! reload_completed || frame_pointer_needed)
5773 /* Don't allow more than 32 pop, since that's all we can do
5774 with one instruction. */
5775 if (crtl->args.pops_args
5776 && crtl->args.size >= 32768)
5779 ix86_compute_frame_layout (&frame);
5780 return frame.to_allocate == 0 && frame.nregs == 0;
5783 /* Value should be nonzero if functions must have frame pointers.
5784 Zero means the frame pointer need not be set up (and parms may
5785 be accessed via the stack pointer) in functions that seem suitable. */
5788 ix86_frame_pointer_required (void)
5790 /* If we accessed previous frames, then the generated code expects
5791 to be able to access the saved ebp value in our frame. */
5792 if (cfun->machine->accesses_prev_frame)
5795 /* Several x86 os'es need a frame pointer for other reasons,
5796 usually pertaining to setjmp. */
5797 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5800 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5801 the frame pointer by default. Turn it back on now if we've not
5802 got a leaf function. */
5803 if (TARGET_OMIT_LEAF_FRAME_POINTER
5804 && (!current_function_is_leaf
5805 || ix86_current_function_calls_tls_descriptor))
5814 /* Record that the current function accesses previous call frames. */
5817 ix86_setup_frame_addresses (void)
5819 cfun->machine->accesses_prev_frame = 1;
5822 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5823 # define USE_HIDDEN_LINKONCE 1
5825 # define USE_HIDDEN_LINKONCE 0
5828 static int pic_labels_used;
5830 /* Fills in the label name that should be used for a pc thunk for
5831 the given register. */
5834 get_pc_thunk_name (char name[32], unsigned int regno)
5836 gcc_assert (!TARGET_64BIT);
5838 if (USE_HIDDEN_LINKONCE)
5839 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5841 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5845 /* This function generates code for -fpic that loads %ebx with
5846 the return address of the caller and then returns. */
5849 ix86_file_end (void)
5854 for (regno = 0; regno < 8; ++regno)
5858 if (! ((pic_labels_used >> regno) & 1))
5861 get_pc_thunk_name (name, regno);
5866 switch_to_section (darwin_sections[text_coal_section]);
5867 fputs ("\t.weak_definition\t", asm_out_file);
5868 assemble_name (asm_out_file, name);
5869 fputs ("\n\t.private_extern\t", asm_out_file);
5870 assemble_name (asm_out_file, name);
5871 fputs ("\n", asm_out_file);
5872 ASM_OUTPUT_LABEL (asm_out_file, name);
5876 if (USE_HIDDEN_LINKONCE)
5880 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5882 TREE_PUBLIC (decl) = 1;
5883 TREE_STATIC (decl) = 1;
5884 DECL_ONE_ONLY (decl) = 1;
5886 (*targetm.asm_out.unique_section) (decl, 0);
5887 switch_to_section (get_named_section (decl, NULL, 0));
5889 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5890 fputs ("\t.hidden\t", asm_out_file);
5891 assemble_name (asm_out_file, name);
5892 fputc ('\n', asm_out_file);
5893 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5897 switch_to_section (text_section);
5898 ASM_OUTPUT_LABEL (asm_out_file, name);
5901 xops[0] = gen_rtx_REG (Pmode, regno);
5902 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
5904 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
5906 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5907 output_asm_insn ("ret", xops);
5910 if (NEED_INDICATE_EXEC_STACK)
5911 file_end_indicate_exec_stack ();
5914 /* Emit code for the SET_GOT patterns. */
5917 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5923 if (TARGET_VXWORKS_RTP && flag_pic)
5925 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5926 xops[2] = gen_rtx_MEM (Pmode,
5927 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
5928 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5930 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5931 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5932 an unadorned address. */
5933 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5934 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
5935 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
5939 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5941 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5943 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5948 output_asm_insn ("mov{q}\t{%2, %0|%0, %2}", xops);
5950 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5953 output_asm_insn ("call\t%a2", xops);
5956 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5957 is what will be referenced by the Mach-O PIC subsystem. */
5959 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5962 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5963 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5968 output_asm_insn ("pop{q}\t%0", xops);
5970 output_asm_insn ("pop{l}\t%0", xops);
5976 get_pc_thunk_name (name, REGNO (dest));
5977 pic_labels_used |= 1 << REGNO (dest);
5979 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5980 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5981 output_asm_insn ("call\t%X2", xops);
5982 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5983 is what will be referenced by the Mach-O PIC subsystem. */
5986 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5988 targetm.asm_out.internal_label (asm_out_file, "L",
5989 CODE_LABEL_NUMBER (label));
5996 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5999 output_asm_insn ("add{q}\t{%1, %0|%0, %1}", xops);
6001 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
6006 output_asm_insn ("add{q}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
6008 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
6014 /* Generate an "push" pattern for input ARG. */
6019 return gen_rtx_SET (VOIDmode,
6021 gen_rtx_PRE_DEC (Pmode,
6022 stack_pointer_rtx)),
6026 /* Return >= 0 if there is an unused call-clobbered register available
6027 for the entire function. */
6030 ix86_select_alt_pic_regnum (void)
6032 if (current_function_is_leaf && !crtl->profile
6033 && !ix86_current_function_calls_tls_descriptor)
6036 for (i = 2; i >= 0; --i)
6037 if (!df_regs_ever_live_p (i))
6041 return INVALID_REGNUM;
6044 /* Return 1 if we need to save REGNO. */
6046 ix86_save_reg (unsigned int regno, int maybe_eh_return)
6048 if (pic_offset_table_rtx
6049 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
6050 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6052 || crtl->calls_eh_return
6053 || crtl->uses_const_pool))
6055 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
6060 if (crtl->calls_eh_return && maybe_eh_return)
6065 unsigned test = EH_RETURN_DATA_REGNO (i);
6066 if (test == INVALID_REGNUM)
6073 if (cfun->machine->force_align_arg_pointer
6074 && regno == REGNO (cfun->machine->force_align_arg_pointer))
6077 return (df_regs_ever_live_p (regno)
6078 && !call_used_regs[regno]
6079 && !fixed_regs[regno]
6080 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
6083 /* Return number of registers to be saved on the stack. */
6086 ix86_nsaved_regs (void)
6091 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
6092 if (ix86_save_reg (regno, true))
6097 /* Return the offset between two registers, one to be eliminated, and the other
6098 its replacement, at the start of a routine. */
6101 ix86_initial_elimination_offset (int from, int to)
6103 struct ix86_frame frame;
6104 ix86_compute_frame_layout (&frame);
6106 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
6107 return frame.hard_frame_pointer_offset;
6108 else if (from == FRAME_POINTER_REGNUM
6109 && to == HARD_FRAME_POINTER_REGNUM)
6110 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
6113 gcc_assert (to == STACK_POINTER_REGNUM);
6115 if (from == ARG_POINTER_REGNUM)
6116 return frame.stack_pointer_offset;
6118 gcc_assert (from == FRAME_POINTER_REGNUM);
6119 return frame.stack_pointer_offset - frame.frame_pointer_offset;
6123 /* Fill structure ix86_frame about frame of currently computed function. */
6126 ix86_compute_frame_layout (struct ix86_frame *frame)
6128 HOST_WIDE_INT total_size;
6129 unsigned int stack_alignment_needed;
6130 HOST_WIDE_INT offset;
6131 unsigned int preferred_alignment;
6132 HOST_WIDE_INT size = get_frame_size ();
6134 frame->nregs = ix86_nsaved_regs ();
6137 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
6138 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
6140 /* During reload iteration the amount of registers saved can change.
6141 Recompute the value as needed. Do not recompute when amount of registers
6142 didn't change as reload does multiple calls to the function and does not
6143 expect the decision to change within single iteration. */
6145 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
6147 int count = frame->nregs;
6149 cfun->machine->use_fast_prologue_epilogue_nregs = count;
6150 /* The fast prologue uses move instead of push to save registers. This
6151 is significantly longer, but also executes faster as modern hardware
6152 can execute the moves in parallel, but can't do that for push/pop.
6154 Be careful about choosing what prologue to emit: When function takes
6155 many instructions to execute we may use slow version as well as in
6156 case function is known to be outside hot spot (this is known with
6157 feedback only). Weight the size of function by number of registers
6158 to save as it is cheap to use one or two push instructions but very
6159 slow to use many of them. */
6161 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
6162 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
6163 || (flag_branch_probabilities
6164 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
6165 cfun->machine->use_fast_prologue_epilogue = false;
6167 cfun->machine->use_fast_prologue_epilogue
6168 = !expensive_function_p (count);
6170 if (TARGET_PROLOGUE_USING_MOVE
6171 && cfun->machine->use_fast_prologue_epilogue)
6172 frame->save_regs_using_mov = true;
6174 frame->save_regs_using_mov = false;
6177 /* Skip return address and saved base pointer. */
6178 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
6180 frame->hard_frame_pointer_offset = offset;
6182 /* Do some sanity checking of stack_alignment_needed and
6183 preferred_alignment, since i386 port is the only using those features
6184 that may break easily. */
6186 gcc_assert (!size || stack_alignment_needed);
6187 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
6188 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6189 gcc_assert (stack_alignment_needed
6190 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6192 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
6193 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
6195 /* Register save area */
6196 offset += frame->nregs * UNITS_PER_WORD;
6199 if (ix86_save_varrargs_registers)
6201 offset += X86_64_VARARGS_SIZE;
6202 frame->va_arg_size = X86_64_VARARGS_SIZE;
6205 frame->va_arg_size = 0;
6207 /* Align start of frame for local function. */
6208 frame->padding1 = ((offset + stack_alignment_needed - 1)
6209 & -stack_alignment_needed) - offset;
6211 offset += frame->padding1;
6213 /* Frame pointer points here. */
6214 frame->frame_pointer_offset = offset;
6218 /* Add outgoing arguments area. Can be skipped if we eliminated
6219 all the function calls as dead code.
6220 Skipping is however impossible when function calls alloca. Alloca
6221 expander assumes that last crtl->outgoing_args_size
6222 of stack frame are unused. */
6223 if (ACCUMULATE_OUTGOING_ARGS
6224 && (!current_function_is_leaf || cfun->calls_alloca
6225 || ix86_current_function_calls_tls_descriptor))
6227 offset += crtl->outgoing_args_size;
6228 frame->outgoing_arguments_size = crtl->outgoing_args_size;
6231 frame->outgoing_arguments_size = 0;
6233 /* Align stack boundary. Only needed if we're calling another function
6235 if (!current_function_is_leaf || cfun->calls_alloca
6236 || ix86_current_function_calls_tls_descriptor)
6237 frame->padding2 = ((offset + preferred_alignment - 1)
6238 & -preferred_alignment) - offset;
6240 frame->padding2 = 0;
6242 offset += frame->padding2;
6244 /* We've reached end of stack frame. */
6245 frame->stack_pointer_offset = offset;
6247 /* Size prologue needs to allocate. */
6248 frame->to_allocate =
6249 (size + frame->padding1 + frame->padding2
6250 + frame->outgoing_arguments_size + frame->va_arg_size);
6252 if ((!frame->to_allocate && frame->nregs <= 1)
6253 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
6254 frame->save_regs_using_mov = false;
6256 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
6257 && current_function_is_leaf
6258 && !ix86_current_function_calls_tls_descriptor)
6260 frame->red_zone_size = frame->to_allocate;
6261 if (frame->save_regs_using_mov)
6262 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
6263 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
6264 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
6267 frame->red_zone_size = 0;
6268 frame->to_allocate -= frame->red_zone_size;
6269 frame->stack_pointer_offset -= frame->red_zone_size;
6271 fprintf (stderr, "\n");
6272 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
6273 fprintf (stderr, "size: %ld\n", (long)size);
6274 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
6275 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
6276 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
6277 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
6278 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
6279 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
6280 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
6281 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
6282 (long)frame->hard_frame_pointer_offset);
6283 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
6284 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
6285 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
6286 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
6290 /* Emit code to save registers in the prologue. */
6293 ix86_emit_save_regs (void)
6298 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
6299 if (ix86_save_reg (regno, true))
6301 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
6302 RTX_FRAME_RELATED_P (insn) = 1;
6306 /* Emit code to save registers using MOV insns. First register
6307 is restored from POINTER + OFFSET. */
6309 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
6314 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6315 if (ix86_save_reg (regno, true))
6317 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
6319 gen_rtx_REG (Pmode, regno));
6320 RTX_FRAME_RELATED_P (insn) = 1;
6321 offset += UNITS_PER_WORD;
6325 /* Expand prologue or epilogue stack adjustment.
6326 The pattern exist to put a dependency on all ebp-based memory accesses.
6327 STYLE should be negative if instructions should be marked as frame related,
6328 zero if %r11 register is live and cannot be freely used and positive
6332 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
6337 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
6338 else if (x86_64_immediate_operand (offset, DImode))
6339 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
6343 /* r11 is used by indirect sibcall return as well, set before the
6344 epilogue and used after the epilogue. ATM indirect sibcall
6345 shouldn't be used together with huge frame sizes in one
6346 function because of the frame_size check in sibcall.c. */
6348 r11 = gen_rtx_REG (DImode, R11_REG);
6349 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
6351 RTX_FRAME_RELATED_P (insn) = 1;
6352 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
6356 RTX_FRAME_RELATED_P (insn) = 1;
6359 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
6362 ix86_internal_arg_pointer (void)
6364 bool has_force_align_arg_pointer =
6365 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
6366 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
6367 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
6368 && DECL_NAME (current_function_decl)
6369 && MAIN_NAME_P (DECL_NAME (current_function_decl))
6370 && DECL_FILE_SCOPE_P (current_function_decl))
6371 || ix86_force_align_arg_pointer
6372 || has_force_align_arg_pointer)
6374 /* Nested functions can't realign the stack due to a register
6376 if (DECL_CONTEXT (current_function_decl)
6377 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
6379 if (ix86_force_align_arg_pointer)
6380 warning (0, "-mstackrealign ignored for nested functions");
6381 if (has_force_align_arg_pointer)
6382 error ("%s not supported for nested functions",
6383 ix86_force_align_arg_pointer_string);
6384 return virtual_incoming_args_rtx;
6386 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, CX_REG);
6387 return copy_to_reg (cfun->machine->force_align_arg_pointer);
6390 return virtual_incoming_args_rtx;
6393 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
6394 This is called from dwarf2out.c to emit call frame instructions
6395 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
6397 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
6399 rtx unspec = SET_SRC (pattern);
6400 gcc_assert (GET_CODE (unspec) == UNSPEC);
6404 case UNSPEC_REG_SAVE:
6405 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
6406 SET_DEST (pattern));
6408 case UNSPEC_DEF_CFA:
6409 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
6410 INTVAL (XVECEXP (unspec, 0, 0)));
6417 /* Expand the prologue into a bunch of separate insns. */
6420 ix86_expand_prologue (void)
6424 struct ix86_frame frame;
6425 HOST_WIDE_INT allocate;
6427 ix86_compute_frame_layout (&frame);
6429 if (cfun->machine->force_align_arg_pointer)
6433 /* Grab the argument pointer. */
6434 x = plus_constant (stack_pointer_rtx, 4);
6435 y = cfun->machine->force_align_arg_pointer;
6436 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
6437 RTX_FRAME_RELATED_P (insn) = 1;
6439 /* The unwind info consists of two parts: install the fafp as the cfa,
6440 and record the fafp as the "save register" of the stack pointer.
6441 The later is there in order that the unwinder can see where it
6442 should restore the stack pointer across the and insn. */
6443 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
6444 x = gen_rtx_SET (VOIDmode, y, x);
6445 RTX_FRAME_RELATED_P (x) = 1;
6446 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
6448 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
6449 RTX_FRAME_RELATED_P (y) = 1;
6450 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
6451 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6452 REG_NOTES (insn) = x;
6454 /* Align the stack. */
6455 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
6458 /* And here we cheat like madmen with the unwind info. We force the
6459 cfa register back to sp+4, which is exactly what it was at the
6460 start of the function. Re-pushing the return address results in
6461 the return at the same spot relative to the cfa, and thus is
6462 correct wrt the unwind info. */
6463 x = cfun->machine->force_align_arg_pointer;
6464 x = gen_frame_mem (Pmode, plus_constant (x, -4));
6465 insn = emit_insn (gen_push (x));
6466 RTX_FRAME_RELATED_P (insn) = 1;
6469 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
6470 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
6471 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6472 REG_NOTES (insn) = x;
6475 /* Note: AT&T enter does NOT have reversed args. Enter is probably
6476 slower on all targets. Also sdb doesn't like it. */
6478 if (frame_pointer_needed)
6480 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
6481 RTX_FRAME_RELATED_P (insn) = 1;
6483 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6484 RTX_FRAME_RELATED_P (insn) = 1;
6487 allocate = frame.to_allocate;
6489 if (!frame.save_regs_using_mov)
6490 ix86_emit_save_regs ();
6492 allocate += frame.nregs * UNITS_PER_WORD;
6494 /* When using red zone we may start register saving before allocating
6495 the stack frame saving one cycle of the prologue. However I will
6496 avoid doing this if I am going to have to probe the stack since
6497 at least on x86_64 the stack probe can turn into a call that clobbers
6498 a red zone location */
6499 if (TARGET_RED_ZONE && frame.save_regs_using_mov
6500 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
6501 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
6502 : stack_pointer_rtx,
6503 -frame.nregs * UNITS_PER_WORD);
6507 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
6508 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6509 GEN_INT (-allocate), -1);
6512 /* Only valid for Win32. */
6513 rtx eax = gen_rtx_REG (Pmode, AX_REG);
6517 gcc_assert (!TARGET_64BIT || TARGET_64BIT_MS_ABI);
6519 if (TARGET_64BIT_MS_ABI)
6522 eax_live = ix86_eax_live_at_start_p ();
6526 emit_insn (gen_push (eax));
6527 allocate -= UNITS_PER_WORD;
6530 emit_move_insn (eax, GEN_INT (allocate));
6533 insn = gen_allocate_stack_worker_64 (eax);
6535 insn = gen_allocate_stack_worker_32 (eax);
6536 insn = emit_insn (insn);
6537 RTX_FRAME_RELATED_P (insn) = 1;
6538 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
6539 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
6540 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6541 t, REG_NOTES (insn));
6545 if (frame_pointer_needed)
6546 t = plus_constant (hard_frame_pointer_rtx,
6549 - frame.nregs * UNITS_PER_WORD);
6551 t = plus_constant (stack_pointer_rtx, allocate);
6552 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6556 if (frame.save_regs_using_mov
6557 && !(TARGET_RED_ZONE
6558 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
6560 if (!frame_pointer_needed || !frame.to_allocate)
6561 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6563 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6564 -frame.nregs * UNITS_PER_WORD);
6567 pic_reg_used = false;
6568 if (pic_offset_table_rtx
6569 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6572 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6574 if (alt_pic_reg_used != INVALID_REGNUM)
6575 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
6577 pic_reg_used = true;
6584 if (ix86_cmodel == CM_LARGE_PIC)
6586 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
6587 rtx label = gen_label_rtx ();
6589 LABEL_PRESERVE_P (label) = 1;
6590 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6591 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6592 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6593 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6594 pic_offset_table_rtx, tmp_reg));
6597 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6600 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6603 /* Prevent function calls from being scheduled before the call to mcount.
6604 In the pic_reg_used case, make sure that the got load isn't deleted. */
6608 emit_insn (gen_prologue_use (pic_offset_table_rtx));
6609 emit_insn (gen_blockage ());
6612 /* Emit cld instruction if stringops are used in the function. */
6613 if (TARGET_CLD && ix86_current_function_needs_cld)
6614 emit_insn (gen_cld ());
6617 /* Emit code to restore saved registers using MOV insns. First register
6618 is restored from POINTER + OFFSET. */
6620 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6621 int maybe_eh_return)
6624 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6626 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6627 if (ix86_save_reg (regno, maybe_eh_return))
6629 /* Ensure that adjust_address won't be forced to produce pointer
6630 out of range allowed by x86-64 instruction set. */
6631 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6635 r11 = gen_rtx_REG (DImode, R11_REG);
6636 emit_move_insn (r11, GEN_INT (offset));
6637 emit_insn (gen_adddi3 (r11, r11, pointer));
6638 base_address = gen_rtx_MEM (Pmode, r11);
6641 emit_move_insn (gen_rtx_REG (Pmode, regno),
6642 adjust_address (base_address, Pmode, offset));
6643 offset += UNITS_PER_WORD;
6647 /* Restore function stack, frame, and registers. */
6650 ix86_expand_epilogue (int style)
6653 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6654 struct ix86_frame frame;
6655 HOST_WIDE_INT offset;
6657 ix86_compute_frame_layout (&frame);
6659 /* Calculate start of saved registers relative to ebp. Special care
6660 must be taken for the normal return case of a function using
6661 eh_return: the eax and edx registers are marked as saved, but not
6662 restored along this path. */
6663 offset = frame.nregs;
6664 if (crtl->calls_eh_return && style != 2)
6666 offset *= -UNITS_PER_WORD;
6668 /* If we're only restoring one register and sp is not valid then
6669 using a move instruction to restore the register since it's
6670 less work than reloading sp and popping the register.
6672 The default code result in stack adjustment using add/lea instruction,
6673 while this code results in LEAVE instruction (or discrete equivalent),
6674 so it is profitable in some other cases as well. Especially when there
6675 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6676 and there is exactly one register to pop. This heuristic may need some
6677 tuning in future. */
6678 if ((!sp_valid && frame.nregs <= 1)
6679 || (TARGET_EPILOGUE_USING_MOVE
6680 && cfun->machine->use_fast_prologue_epilogue
6681 && (frame.nregs > 1 || frame.to_allocate))
6682 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6683 || (frame_pointer_needed && TARGET_USE_LEAVE
6684 && cfun->machine->use_fast_prologue_epilogue
6685 && frame.nregs == 1)
6686 || crtl->calls_eh_return)
6688 /* Restore registers. We can use ebp or esp to address the memory
6689 locations. If both are available, default to ebp, since offsets
6690 are known to be small. Only exception is esp pointing directly to the
6691 end of block of saved registers, where we may simplify addressing
6694 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6695 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6696 frame.to_allocate, style == 2);
6698 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6699 offset, style == 2);
6701 /* eh_return epilogues need %ecx added to the stack pointer. */
6704 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6706 if (frame_pointer_needed)
6708 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6709 tmp = plus_constant (tmp, UNITS_PER_WORD);
6710 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6712 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6713 emit_move_insn (hard_frame_pointer_rtx, tmp);
6715 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6720 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6721 tmp = plus_constant (tmp, (frame.to_allocate
6722 + frame.nregs * UNITS_PER_WORD));
6723 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6726 else if (!frame_pointer_needed)
6727 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6728 GEN_INT (frame.to_allocate
6729 + frame.nregs * UNITS_PER_WORD),
6731 /* If not an i386, mov & pop is faster than "leave". */
6732 else if (TARGET_USE_LEAVE || optimize_size
6733 || !cfun->machine->use_fast_prologue_epilogue)
6734 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6737 pro_epilogue_adjust_stack (stack_pointer_rtx,
6738 hard_frame_pointer_rtx,
6741 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6743 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6748 /* First step is to deallocate the stack frame so that we can
6749 pop the registers. */
6752 gcc_assert (frame_pointer_needed);
6753 pro_epilogue_adjust_stack (stack_pointer_rtx,
6754 hard_frame_pointer_rtx,
6755 GEN_INT (offset), style);
6757 else if (frame.to_allocate)
6758 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6759 GEN_INT (frame.to_allocate), style);
6761 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6762 if (ix86_save_reg (regno, false))
6765 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
6767 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
6769 if (frame_pointer_needed)
6771 /* Leave results in shorter dependency chains on CPUs that are
6772 able to grok it fast. */
6773 if (TARGET_USE_LEAVE)
6774 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6775 else if (TARGET_64BIT)
6776 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6778 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6782 if (cfun->machine->force_align_arg_pointer)
6784 emit_insn (gen_addsi3 (stack_pointer_rtx,
6785 cfun->machine->force_align_arg_pointer,
6789 /* Sibcall epilogues don't want a return instruction. */
6793 if (crtl->args.pops_args && crtl->args.size)
6795 rtx popc = GEN_INT (crtl->args.pops_args);
6797 /* i386 can only pop 64K bytes. If asked to pop more, pop
6798 return address, do explicit add, and jump indirectly to the
6801 if (crtl->args.pops_args >= 65536)
6803 rtx ecx = gen_rtx_REG (SImode, CX_REG);
6805 /* There is no "pascal" calling convention in any 64bit ABI. */
6806 gcc_assert (!TARGET_64BIT);
6808 emit_insn (gen_popsi1 (ecx));
6809 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6810 emit_jump_insn (gen_return_indirect_internal (ecx));
6813 emit_jump_insn (gen_return_pop_internal (popc));
6816 emit_jump_insn (gen_return_internal ());
6819 /* Reset from the function's potential modifications. */
6822 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6823 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6825 if (pic_offset_table_rtx)
6826 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
6828 /* Mach-O doesn't support labels at the end of objects, so if
6829 it looks like we might want one, insert a NOP. */
6831 rtx insn = get_last_insn ();
6834 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6835 insn = PREV_INSN (insn);
6839 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6840 fputs ("\tnop\n", file);
6846 /* Extract the parts of an RTL expression that is a valid memory address
6847 for an instruction. Return 0 if the structure of the address is
6848 grossly off. Return -1 if the address contains ASHIFT, so it is not
6849 strictly valid, but still used for computing length of lea instruction. */
6852 ix86_decompose_address (rtx addr, struct ix86_address *out)
6854 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6855 rtx base_reg, index_reg;
6856 HOST_WIDE_INT scale = 1;
6857 rtx scale_rtx = NULL_RTX;
6859 enum ix86_address_seg seg = SEG_DEFAULT;
6861 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6863 else if (GET_CODE (addr) == PLUS)
6873 addends[n++] = XEXP (op, 1);
6876 while (GET_CODE (op) == PLUS);
6881 for (i = n; i >= 0; --i)
6884 switch (GET_CODE (op))
6889 index = XEXP (op, 0);
6890 scale_rtx = XEXP (op, 1);
6894 if (XINT (op, 1) == UNSPEC_TP
6895 && TARGET_TLS_DIRECT_SEG_REFS
6896 && seg == SEG_DEFAULT)
6897 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6926 else if (GET_CODE (addr) == MULT)
6928 index = XEXP (addr, 0); /* index*scale */
6929 scale_rtx = XEXP (addr, 1);
6931 else if (GET_CODE (addr) == ASHIFT)
6935 /* We're called for lea too, which implements ashift on occasion. */
6936 index = XEXP (addr, 0);
6937 tmp = XEXP (addr, 1);
6938 if (!CONST_INT_P (tmp))
6940 scale = INTVAL (tmp);
6941 if ((unsigned HOST_WIDE_INT) scale > 3)
6947 disp = addr; /* displacement */
6949 /* Extract the integral value of scale. */
6952 if (!CONST_INT_P (scale_rtx))
6954 scale = INTVAL (scale_rtx);
6957 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6958 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6960 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6961 if (base_reg && index_reg && scale == 1
6962 && (index_reg == arg_pointer_rtx
6963 || index_reg == frame_pointer_rtx
6964 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6967 tmp = base, base = index, index = tmp;
6968 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6971 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6972 if ((base_reg == hard_frame_pointer_rtx
6973 || base_reg == frame_pointer_rtx
6974 || base_reg == arg_pointer_rtx) && !disp)
6977 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6978 Avoid this by transforming to [%esi+0]. */
6979 if (TARGET_K6 && !optimize_size
6980 && base_reg && !index_reg && !disp
6982 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6985 /* Special case: encode reg+reg instead of reg*2. */
6986 if (!base && index && scale && scale == 2)
6987 base = index, base_reg = index_reg, scale = 1;
6989 /* Special case: scaling cannot be encoded without base or displacement. */
6990 if (!base && !disp && index && scale != 1)
7002 /* Return cost of the memory address x.
7003 For i386, it is better to use a complex address than let gcc copy
7004 the address into a reg and make a new pseudo. But not if the address
7005 requires to two regs - that would mean more pseudos with longer
7008 ix86_address_cost (rtx x)
7010 struct ix86_address parts;
7012 int ok = ix86_decompose_address (x, &parts);
7016 if (parts.base && GET_CODE (parts.base) == SUBREG)
7017 parts.base = SUBREG_REG (parts.base);
7018 if (parts.index && GET_CODE (parts.index) == SUBREG)
7019 parts.index = SUBREG_REG (parts.index);
7021 /* Attempt to minimize number of registers in the address. */
7023 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
7025 && (!REG_P (parts.index)
7026 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
7030 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
7032 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
7033 && parts.base != parts.index)
7036 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
7037 since it's predecode logic can't detect the length of instructions
7038 and it degenerates to vector decoded. Increase cost of such
7039 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
7040 to split such addresses or even refuse such addresses at all.
7042 Following addressing modes are affected:
7047 The first and last case may be avoidable by explicitly coding the zero in
7048 memory address, but I don't have AMD-K6 machine handy to check this
7052 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
7053 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
7054 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
7060 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
7061 this is used for to form addresses to local data when -fPIC is in
7065 darwin_local_data_pic (rtx disp)
7067 if (GET_CODE (disp) == MINUS)
7069 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
7070 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
7071 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
7073 const char *sym_name = XSTR (XEXP (disp, 1), 0);
7074 if (! strcmp (sym_name, "<pic base>"))
7082 /* Determine if a given RTX is a valid constant. We already know this
7083 satisfies CONSTANT_P. */
7086 legitimate_constant_p (rtx x)
7088 switch (GET_CODE (x))
7093 if (GET_CODE (x) == PLUS)
7095 if (!CONST_INT_P (XEXP (x, 1)))
7100 if (TARGET_MACHO && darwin_local_data_pic (x))
7103 /* Only some unspecs are valid as "constants". */
7104 if (GET_CODE (x) == UNSPEC)
7105 switch (XINT (x, 1))
7110 return TARGET_64BIT;
7113 x = XVECEXP (x, 0, 0);
7114 return (GET_CODE (x) == SYMBOL_REF
7115 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7117 x = XVECEXP (x, 0, 0);
7118 return (GET_CODE (x) == SYMBOL_REF
7119 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
7124 /* We must have drilled down to a symbol. */
7125 if (GET_CODE (x) == LABEL_REF)
7127 if (GET_CODE (x) != SYMBOL_REF)
7132 /* TLS symbols are never valid. */
7133 if (SYMBOL_REF_TLS_MODEL (x))
7136 /* DLLIMPORT symbols are never valid. */
7137 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
7138 && SYMBOL_REF_DLLIMPORT_P (x))
7143 if (GET_MODE (x) == TImode
7144 && x != CONST0_RTX (TImode)
7150 if (x == CONST0_RTX (GET_MODE (x)))
7158 /* Otherwise we handle everything else in the move patterns. */
7162 /* Determine if it's legal to put X into the constant pool. This
7163 is not possible for the address of thread-local symbols, which
7164 is checked above. */
7167 ix86_cannot_force_const_mem (rtx x)
7169 /* We can always put integral constants and vectors in memory. */
7170 switch (GET_CODE (x))
7180 return !legitimate_constant_p (x);
7183 /* Determine if a given RTX is a valid constant address. */
7186 constant_address_p (rtx x)
7188 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
7191 /* Nonzero if the constant value X is a legitimate general operand
7192 when generating PIC code. It is given that flag_pic is on and
7193 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
7196 legitimate_pic_operand_p (rtx x)
7200 switch (GET_CODE (x))
7203 inner = XEXP (x, 0);
7204 if (GET_CODE (inner) == PLUS
7205 && CONST_INT_P (XEXP (inner, 1)))
7206 inner = XEXP (inner, 0);
7208 /* Only some unspecs are valid as "constants". */
7209 if (GET_CODE (inner) == UNSPEC)
7210 switch (XINT (inner, 1))
7215 return TARGET_64BIT;
7217 x = XVECEXP (inner, 0, 0);
7218 return (GET_CODE (x) == SYMBOL_REF
7219 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7227 return legitimate_pic_address_disp_p (x);
7234 /* Determine if a given CONST RTX is a valid memory displacement
7238 legitimate_pic_address_disp_p (rtx disp)
7242 /* In 64bit mode we can allow direct addresses of symbols and labels
7243 when they are not dynamic symbols. */
7246 rtx op0 = disp, op1;
7248 switch (GET_CODE (disp))
7254 if (GET_CODE (XEXP (disp, 0)) != PLUS)
7256 op0 = XEXP (XEXP (disp, 0), 0);
7257 op1 = XEXP (XEXP (disp, 0), 1);
7258 if (!CONST_INT_P (op1)
7259 || INTVAL (op1) >= 16*1024*1024
7260 || INTVAL (op1) < -16*1024*1024)
7262 if (GET_CODE (op0) == LABEL_REF)
7264 if (GET_CODE (op0) != SYMBOL_REF)
7269 /* TLS references should always be enclosed in UNSPEC. */
7270 if (SYMBOL_REF_TLS_MODEL (op0))
7272 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
7273 && ix86_cmodel != CM_LARGE_PIC)
7281 if (GET_CODE (disp) != CONST)
7283 disp = XEXP (disp, 0);
7287 /* We are unsafe to allow PLUS expressions. This limit allowed distance
7288 of GOT tables. We should not need these anyway. */
7289 if (GET_CODE (disp) != UNSPEC
7290 || (XINT (disp, 1) != UNSPEC_GOTPCREL
7291 && XINT (disp, 1) != UNSPEC_GOTOFF
7292 && XINT (disp, 1) != UNSPEC_PLTOFF))
7295 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
7296 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
7302 if (GET_CODE (disp) == PLUS)
7304 if (!CONST_INT_P (XEXP (disp, 1)))
7306 disp = XEXP (disp, 0);
7310 if (TARGET_MACHO && darwin_local_data_pic (disp))
7313 if (GET_CODE (disp) != UNSPEC)
7316 switch (XINT (disp, 1))
7321 /* We need to check for both symbols and labels because VxWorks loads
7322 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
7324 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7325 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
7327 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
7328 While ABI specify also 32bit relocation but we don't produce it in
7329 small PIC model at all. */
7330 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7331 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
7333 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
7335 case UNSPEC_GOTTPOFF:
7336 case UNSPEC_GOTNTPOFF:
7337 case UNSPEC_INDNTPOFF:
7340 disp = XVECEXP (disp, 0, 0);
7341 return (GET_CODE (disp) == SYMBOL_REF
7342 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
7344 disp = XVECEXP (disp, 0, 0);
7345 return (GET_CODE (disp) == SYMBOL_REF
7346 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
7348 disp = XVECEXP (disp, 0, 0);
7349 return (GET_CODE (disp) == SYMBOL_REF
7350 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
7356 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
7357 memory address for an instruction. The MODE argument is the machine mode
7358 for the MEM expression that wants to use this address.
7360 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
7361 convert common non-canonical forms to canonical form so that they will
7365 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
7366 rtx addr, int strict)
7368 struct ix86_address parts;
7369 rtx base, index, disp;
7370 HOST_WIDE_INT scale;
7371 const char *reason = NULL;
7372 rtx reason_rtx = NULL_RTX;
7374 if (ix86_decompose_address (addr, &parts) <= 0)
7376 reason = "decomposition failed";
7381 index = parts.index;
7383 scale = parts.scale;
7385 /* Validate base register.
7387 Don't allow SUBREG's that span more than a word here. It can lead to spill
7388 failures when the base is one word out of a two word structure, which is
7389 represented internally as a DImode int. */
7398 else if (GET_CODE (base) == SUBREG
7399 && REG_P (SUBREG_REG (base))
7400 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
7402 reg = SUBREG_REG (base);
7405 reason = "base is not a register";
7409 if (GET_MODE (base) != Pmode)
7411 reason = "base is not in Pmode";
7415 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
7416 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
7418 reason = "base is not valid";
7423 /* Validate index register.
7425 Don't allow SUBREG's that span more than a word here -- same as above. */
7434 else if (GET_CODE (index) == SUBREG
7435 && REG_P (SUBREG_REG (index))
7436 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
7438 reg = SUBREG_REG (index);
7441 reason = "index is not a register";
7445 if (GET_MODE (index) != Pmode)
7447 reason = "index is not in Pmode";
7451 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
7452 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
7454 reason = "index is not valid";
7459 /* Validate scale factor. */
7462 reason_rtx = GEN_INT (scale);
7465 reason = "scale without index";
7469 if (scale != 2 && scale != 4 && scale != 8)
7471 reason = "scale is not a valid multiplier";
7476 /* Validate displacement. */
7481 if (GET_CODE (disp) == CONST
7482 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
7483 switch (XINT (XEXP (disp, 0), 1))
7485 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
7486 used. While ABI specify also 32bit relocations, we don't produce
7487 them at all and use IP relative instead. */
7490 gcc_assert (flag_pic);
7492 goto is_legitimate_pic;
7493 reason = "64bit address unspec";
7496 case UNSPEC_GOTPCREL:
7497 gcc_assert (flag_pic);
7498 goto is_legitimate_pic;
7500 case UNSPEC_GOTTPOFF:
7501 case UNSPEC_GOTNTPOFF:
7502 case UNSPEC_INDNTPOFF:
7508 reason = "invalid address unspec";
7512 else if (SYMBOLIC_CONST (disp)
7516 && MACHOPIC_INDIRECT
7517 && !machopic_operand_p (disp)
7523 if (TARGET_64BIT && (index || base))
7525 /* foo@dtpoff(%rX) is ok. */
7526 if (GET_CODE (disp) != CONST
7527 || GET_CODE (XEXP (disp, 0)) != PLUS
7528 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
7529 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
7530 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
7531 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
7533 reason = "non-constant pic memory reference";
7537 else if (! legitimate_pic_address_disp_p (disp))
7539 reason = "displacement is an invalid pic construct";
7543 /* This code used to verify that a symbolic pic displacement
7544 includes the pic_offset_table_rtx register.
7546 While this is good idea, unfortunately these constructs may
7547 be created by "adds using lea" optimization for incorrect
7556 This code is nonsensical, but results in addressing
7557 GOT table with pic_offset_table_rtx base. We can't
7558 just refuse it easily, since it gets matched by
7559 "addsi3" pattern, that later gets split to lea in the
7560 case output register differs from input. While this
7561 can be handled by separate addsi pattern for this case
7562 that never results in lea, this seems to be easier and
7563 correct fix for crash to disable this test. */
7565 else if (GET_CODE (disp) != LABEL_REF
7566 && !CONST_INT_P (disp)
7567 && (GET_CODE (disp) != CONST
7568 || !legitimate_constant_p (disp))
7569 && (GET_CODE (disp) != SYMBOL_REF
7570 || !legitimate_constant_p (disp)))
7572 reason = "displacement is not constant";
7575 else if (TARGET_64BIT
7576 && !x86_64_immediate_operand (disp, VOIDmode))
7578 reason = "displacement is out of range";
7583 /* Everything looks valid. */
7590 /* Return a unique alias set for the GOT. */
7592 static alias_set_type
7593 ix86_GOT_alias_set (void)
7595 static alias_set_type set = -1;
7597 set = new_alias_set ();
7601 /* Return a legitimate reference for ORIG (an address) using the
7602 register REG. If REG is 0, a new pseudo is generated.
7604 There are two types of references that must be handled:
7606 1. Global data references must load the address from the GOT, via
7607 the PIC reg. An insn is emitted to do this load, and the reg is
7610 2. Static data references, constant pool addresses, and code labels
7611 compute the address as an offset from the GOT, whose base is in
7612 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7613 differentiate them from global data objects. The returned
7614 address is the PIC reg + an unspec constant.
7616 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7617 reg also appears in the address. */
7620 legitimize_pic_address (rtx orig, rtx reg)
7627 if (TARGET_MACHO && !TARGET_64BIT)
7630 reg = gen_reg_rtx (Pmode);
7631 /* Use the generic Mach-O PIC machinery. */
7632 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7636 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7638 else if (TARGET_64BIT
7639 && ix86_cmodel != CM_SMALL_PIC
7640 && gotoff_operand (addr, Pmode))
7643 /* This symbol may be referenced via a displacement from the PIC
7644 base address (@GOTOFF). */
7646 if (reload_in_progress)
7647 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7648 if (GET_CODE (addr) == CONST)
7649 addr = XEXP (addr, 0);
7650 if (GET_CODE (addr) == PLUS)
7652 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7654 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7657 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7658 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7660 tmpreg = gen_reg_rtx (Pmode);
7663 emit_move_insn (tmpreg, new_rtx);
7667 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7668 tmpreg, 1, OPTAB_DIRECT);
7671 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7673 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7675 /* This symbol may be referenced via a displacement from the PIC
7676 base address (@GOTOFF). */
7678 if (reload_in_progress)
7679 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7680 if (GET_CODE (addr) == CONST)
7681 addr = XEXP (addr, 0);
7682 if (GET_CODE (addr) == PLUS)
7684 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7686 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7689 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7690 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7691 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7695 emit_move_insn (reg, new_rtx);
7699 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7700 /* We can't use @GOTOFF for text labels on VxWorks;
7701 see gotoff_operand. */
7702 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7704 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
7706 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
7707 return legitimize_dllimport_symbol (addr, true);
7708 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
7709 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
7710 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
7712 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
7713 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
7717 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7719 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7720 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7721 new_rtx = gen_const_mem (Pmode, new_rtx);
7722 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7725 reg = gen_reg_rtx (Pmode);
7726 /* Use directly gen_movsi, otherwise the address is loaded
7727 into register for CSE. We don't want to CSE this addresses,
7728 instead we CSE addresses from the GOT table, so skip this. */
7729 emit_insn (gen_movsi (reg, new_rtx));
7734 /* This symbol must be referenced via a load from the
7735 Global Offset Table (@GOT). */
7737 if (reload_in_progress)
7738 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7739 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7740 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7742 new_rtx = force_reg (Pmode, new_rtx);
7743 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7744 new_rtx = gen_const_mem (Pmode, new_rtx);
7745 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7748 reg = gen_reg_rtx (Pmode);
7749 emit_move_insn (reg, new_rtx);
7755 if (CONST_INT_P (addr)
7756 && !x86_64_immediate_operand (addr, VOIDmode))
7760 emit_move_insn (reg, addr);
7764 new_rtx = force_reg (Pmode, addr);
7766 else if (GET_CODE (addr) == CONST)
7768 addr = XEXP (addr, 0);
7770 /* We must match stuff we generate before. Assume the only
7771 unspecs that can get here are ours. Not that we could do
7772 anything with them anyway.... */
7773 if (GET_CODE (addr) == UNSPEC
7774 || (GET_CODE (addr) == PLUS
7775 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7777 gcc_assert (GET_CODE (addr) == PLUS);
7779 if (GET_CODE (addr) == PLUS)
7781 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7783 /* Check first to see if this is a constant offset from a @GOTOFF
7784 symbol reference. */
7785 if (gotoff_operand (op0, Pmode)
7786 && CONST_INT_P (op1))
7790 if (reload_in_progress)
7791 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7792 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7794 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
7795 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7796 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7800 emit_move_insn (reg, new_rtx);
7806 if (INTVAL (op1) < -16*1024*1024
7807 || INTVAL (op1) >= 16*1024*1024)
7809 if (!x86_64_immediate_operand (op1, Pmode))
7810 op1 = force_reg (Pmode, op1);
7811 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7817 base = legitimize_pic_address (XEXP (addr, 0), reg);
7818 new_rtx = legitimize_pic_address (XEXP (addr, 1),
7819 base == reg ? NULL_RTX : reg);
7821 if (CONST_INT_P (new_rtx))
7822 new_rtx = plus_constant (base, INTVAL (new_rtx));
7825 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
7827 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
7828 new_rtx = XEXP (new_rtx, 1);
7830 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
7838 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7841 get_thread_pointer (int to_reg)
7845 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7849 reg = gen_reg_rtx (Pmode);
7850 insn = gen_rtx_SET (VOIDmode, reg, tp);
7851 insn = emit_insn (insn);
7856 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7857 false if we expect this to be used for a memory address and true if
7858 we expect to load the address into a register. */
7861 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7863 rtx dest, base, off, pic, tp;
7868 case TLS_MODEL_GLOBAL_DYNAMIC:
7869 dest = gen_reg_rtx (Pmode);
7870 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7872 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7874 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
7877 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7878 insns = get_insns ();
7881 RTL_CONST_CALL_P (insns) = 1;
7882 emit_libcall_block (insns, dest, rax, x);
7884 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7885 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7887 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7889 if (TARGET_GNU2_TLS)
7891 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7893 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7897 case TLS_MODEL_LOCAL_DYNAMIC:
7898 base = gen_reg_rtx (Pmode);
7899 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7901 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7903 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
7906 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7907 insns = get_insns ();
7910 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7911 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7912 RTL_CONST_CALL_P (insns) = 1;
7913 emit_libcall_block (insns, base, rax, note);
7915 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7916 emit_insn (gen_tls_local_dynamic_base_64 (base));
7918 emit_insn (gen_tls_local_dynamic_base_32 (base));
7920 if (TARGET_GNU2_TLS)
7922 rtx x = ix86_tls_module_base ();
7924 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7925 gen_rtx_MINUS (Pmode, x, tp));
7928 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7929 off = gen_rtx_CONST (Pmode, off);
7931 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7933 if (TARGET_GNU2_TLS)
7935 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7937 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7942 case TLS_MODEL_INITIAL_EXEC:
7946 type = UNSPEC_GOTNTPOFF;
7950 if (reload_in_progress)
7951 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7952 pic = pic_offset_table_rtx;
7953 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7955 else if (!TARGET_ANY_GNU_TLS)
7957 pic = gen_reg_rtx (Pmode);
7958 emit_insn (gen_set_got (pic));
7959 type = UNSPEC_GOTTPOFF;
7964 type = UNSPEC_INDNTPOFF;
7967 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7968 off = gen_rtx_CONST (Pmode, off);
7970 off = gen_rtx_PLUS (Pmode, pic, off);
7971 off = gen_const_mem (Pmode, off);
7972 set_mem_alias_set (off, ix86_GOT_alias_set ());
7974 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7976 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7977 off = force_reg (Pmode, off);
7978 return gen_rtx_PLUS (Pmode, base, off);
7982 base = get_thread_pointer (true);
7983 dest = gen_reg_rtx (Pmode);
7984 emit_insn (gen_subsi3 (dest, base, off));
7988 case TLS_MODEL_LOCAL_EXEC:
7989 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7990 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7991 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7992 off = gen_rtx_CONST (Pmode, off);
7994 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7996 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7997 return gen_rtx_PLUS (Pmode, base, off);
8001 base = get_thread_pointer (true);
8002 dest = gen_reg_rtx (Pmode);
8003 emit_insn (gen_subsi3 (dest, base, off));
8014 /* Create or return the unique __imp_DECL dllimport symbol corresponding
8017 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
8018 htab_t dllimport_map;
8021 get_dllimport_decl (tree decl)
8023 struct tree_map *h, in;
8027 size_t namelen, prefixlen;
8033 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
8035 in.hash = htab_hash_pointer (decl);
8036 in.base.from = decl;
8037 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
8038 h = (struct tree_map *) *loc;
8042 *loc = h = GGC_NEW (struct tree_map);
8044 h->base.from = decl;
8045 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
8046 DECL_ARTIFICIAL (to) = 1;
8047 DECL_IGNORED_P (to) = 1;
8048 DECL_EXTERNAL (to) = 1;
8049 TREE_READONLY (to) = 1;
8051 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
8052 name = targetm.strip_name_encoding (name);
8053 prefix = name[0] == FASTCALL_PREFIX ? "*__imp_": "*__imp__";
8054 namelen = strlen (name);
8055 prefixlen = strlen (prefix);
8056 imp_name = (char *) alloca (namelen + prefixlen + 1);
8057 memcpy (imp_name, prefix, prefixlen);
8058 memcpy (imp_name + prefixlen, name, namelen + 1);
8060 name = ggc_alloc_string (imp_name, namelen + prefixlen);
8061 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
8062 SET_SYMBOL_REF_DECL (rtl, to);
8063 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
8065 rtl = gen_const_mem (Pmode, rtl);
8066 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
8068 SET_DECL_RTL (to, rtl);
8069 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
8074 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
8075 true if we require the result be a register. */
8078 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
8083 gcc_assert (SYMBOL_REF_DECL (symbol));
8084 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
8086 x = DECL_RTL (imp_decl);
8088 x = force_reg (Pmode, x);
8092 /* Try machine-dependent ways of modifying an illegitimate address
8093 to be legitimate. If we find one, return the new, valid address.
8094 This macro is used in only one place: `memory_address' in explow.c.
8096 OLDX is the address as it was before break_out_memory_refs was called.
8097 In some cases it is useful to look at this to decide what needs to be done.
8099 MODE and WIN are passed so that this macro can use
8100 GO_IF_LEGITIMATE_ADDRESS.
8102 It is always safe for this macro to do nothing. It exists to recognize
8103 opportunities to optimize the output.
8105 For the 80386, we handle X+REG by loading X into a register R and
8106 using R+REG. R will go in a general reg and indexing will be used.
8107 However, if REG is a broken-out memory address or multiplication,
8108 nothing needs to be done because REG can certainly go in a general reg.
8110 When -fpic is used, special handling is needed for symbolic references.
8111 See comments by legitimize_pic_address in i386.c for details. */
8114 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
8119 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
8121 return legitimize_tls_address (x, (enum tls_model) log, false);
8122 if (GET_CODE (x) == CONST
8123 && GET_CODE (XEXP (x, 0)) == PLUS
8124 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8125 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
8127 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
8128 (enum tls_model) log, false);
8129 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8132 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
8134 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
8135 return legitimize_dllimport_symbol (x, true);
8136 if (GET_CODE (x) == CONST
8137 && GET_CODE (XEXP (x, 0)) == PLUS
8138 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8139 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
8141 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
8142 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8146 if (flag_pic && SYMBOLIC_CONST (x))
8147 return legitimize_pic_address (x, 0);
8149 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
8150 if (GET_CODE (x) == ASHIFT
8151 && CONST_INT_P (XEXP (x, 1))
8152 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
8155 log = INTVAL (XEXP (x, 1));
8156 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
8157 GEN_INT (1 << log));
8160 if (GET_CODE (x) == PLUS)
8162 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
8164 if (GET_CODE (XEXP (x, 0)) == ASHIFT
8165 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8166 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
8169 log = INTVAL (XEXP (XEXP (x, 0), 1));
8170 XEXP (x, 0) = gen_rtx_MULT (Pmode,
8171 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
8172 GEN_INT (1 << log));
8175 if (GET_CODE (XEXP (x, 1)) == ASHIFT
8176 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
8177 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
8180 log = INTVAL (XEXP (XEXP (x, 1), 1));
8181 XEXP (x, 1) = gen_rtx_MULT (Pmode,
8182 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
8183 GEN_INT (1 << log));
8186 /* Put multiply first if it isn't already. */
8187 if (GET_CODE (XEXP (x, 1)) == MULT)
8189 rtx tmp = XEXP (x, 0);
8190 XEXP (x, 0) = XEXP (x, 1);
8195 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
8196 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
8197 created by virtual register instantiation, register elimination, and
8198 similar optimizations. */
8199 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
8202 x = gen_rtx_PLUS (Pmode,
8203 gen_rtx_PLUS (Pmode, XEXP (x, 0),
8204 XEXP (XEXP (x, 1), 0)),
8205 XEXP (XEXP (x, 1), 1));
8209 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
8210 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
8211 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
8212 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
8213 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
8214 && CONSTANT_P (XEXP (x, 1)))
8217 rtx other = NULL_RTX;
8219 if (CONST_INT_P (XEXP (x, 1)))
8221 constant = XEXP (x, 1);
8222 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
8224 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
8226 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
8227 other = XEXP (x, 1);
8235 x = gen_rtx_PLUS (Pmode,
8236 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
8237 XEXP (XEXP (XEXP (x, 0), 1), 0)),
8238 plus_constant (other, INTVAL (constant)));
8242 if (changed && legitimate_address_p (mode, x, FALSE))
8245 if (GET_CODE (XEXP (x, 0)) == MULT)
8248 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
8251 if (GET_CODE (XEXP (x, 1)) == MULT)
8254 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
8258 && REG_P (XEXP (x, 1))
8259 && REG_P (XEXP (x, 0)))
8262 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
8265 x = legitimize_pic_address (x, 0);
8268 if (changed && legitimate_address_p (mode, x, FALSE))
8271 if (REG_P (XEXP (x, 0)))
8273 rtx temp = gen_reg_rtx (Pmode);
8274 rtx val = force_operand (XEXP (x, 1), temp);
8276 emit_move_insn (temp, val);
8282 else if (REG_P (XEXP (x, 1)))
8284 rtx temp = gen_reg_rtx (Pmode);
8285 rtx val = force_operand (XEXP (x, 0), temp);
8287 emit_move_insn (temp, val);
8297 /* Print an integer constant expression in assembler syntax. Addition
8298 and subtraction are the only arithmetic that may appear in these
8299 expressions. FILE is the stdio stream to write to, X is the rtx, and
8300 CODE is the operand print code from the output string. */
8303 output_pic_addr_const (FILE *file, rtx x, int code)
8307 switch (GET_CODE (x))
8310 gcc_assert (flag_pic);
8315 if (! TARGET_MACHO || TARGET_64BIT)
8316 output_addr_const (file, x);
8319 const char *name = XSTR (x, 0);
8321 /* Mark the decl as referenced so that cgraph will
8322 output the function. */
8323 if (SYMBOL_REF_DECL (x))
8324 mark_decl_referenced (SYMBOL_REF_DECL (x));
8327 if (MACHOPIC_INDIRECT
8328 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
8329 name = machopic_indirection_name (x, /*stub_p=*/true);
8331 assemble_name (file, name);
8333 if (!TARGET_MACHO && !TARGET_64BIT_MS_ABI
8334 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
8335 fputs ("@PLT", file);
8342 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
8343 assemble_name (asm_out_file, buf);
8347 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8351 /* This used to output parentheses around the expression,
8352 but that does not work on the 386 (either ATT or BSD assembler). */
8353 output_pic_addr_const (file, XEXP (x, 0), code);
8357 if (GET_MODE (x) == VOIDmode)
8359 /* We can use %d if the number is <32 bits and positive. */
8360 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
8361 fprintf (file, "0x%lx%08lx",
8362 (unsigned long) CONST_DOUBLE_HIGH (x),
8363 (unsigned long) CONST_DOUBLE_LOW (x));
8365 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
8368 /* We can't handle floating point constants;
8369 PRINT_OPERAND must handle them. */
8370 output_operand_lossage ("floating constant misused");
8374 /* Some assemblers need integer constants to appear first. */
8375 if (CONST_INT_P (XEXP (x, 0)))
8377 output_pic_addr_const (file, XEXP (x, 0), code);
8379 output_pic_addr_const (file, XEXP (x, 1), code);
8383 gcc_assert (CONST_INT_P (XEXP (x, 1)));
8384 output_pic_addr_const (file, XEXP (x, 1), code);
8386 output_pic_addr_const (file, XEXP (x, 0), code);
8392 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
8393 output_pic_addr_const (file, XEXP (x, 0), code);
8395 output_pic_addr_const (file, XEXP (x, 1), code);
8397 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
8401 gcc_assert (XVECLEN (x, 0) == 1);
8402 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
8403 switch (XINT (x, 1))
8406 fputs ("@GOT", file);
8409 fputs ("@GOTOFF", file);
8412 fputs ("@PLTOFF", file);
8414 case UNSPEC_GOTPCREL:
8415 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8416 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
8418 case UNSPEC_GOTTPOFF:
8419 /* FIXME: This might be @TPOFF in Sun ld too. */
8420 fputs ("@GOTTPOFF", file);
8423 fputs ("@TPOFF", file);
8427 fputs ("@TPOFF", file);
8429 fputs ("@NTPOFF", file);
8432 fputs ("@DTPOFF", file);
8434 case UNSPEC_GOTNTPOFF:
8436 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8437 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
8439 fputs ("@GOTNTPOFF", file);
8441 case UNSPEC_INDNTPOFF:
8442 fputs ("@INDNTPOFF", file);
8445 output_operand_lossage ("invalid UNSPEC as operand");
8451 output_operand_lossage ("invalid expression as operand");
8455 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8456 We need to emit DTP-relative relocations. */
8458 static void ATTRIBUTE_UNUSED
8459 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
8461 fputs (ASM_LONG, file);
8462 output_addr_const (file, x);
8463 fputs ("@DTPOFF", file);
8469 fputs (", 0", file);
8476 /* In the name of slightly smaller debug output, and to cater to
8477 general assembler lossage, recognize PIC+GOTOFF and turn it back
8478 into a direct symbol reference.
8480 On Darwin, this is necessary to avoid a crash, because Darwin
8481 has a different PIC label for each routine but the DWARF debugging
8482 information is not associated with any particular routine, so it's
8483 necessary to remove references to the PIC label from RTL stored by
8484 the DWARF output code. */
8487 ix86_delegitimize_address (rtx orig_x)
8490 /* reg_addend is NULL or a multiple of some register. */
8491 rtx reg_addend = NULL_RTX;
8492 /* const_addend is NULL or a const_int. */
8493 rtx const_addend = NULL_RTX;
8494 /* This is the result, or NULL. */
8495 rtx result = NULL_RTX;
8502 if (GET_CODE (x) != CONST
8503 || GET_CODE (XEXP (x, 0)) != UNSPEC
8504 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
8507 return XVECEXP (XEXP (x, 0), 0, 0);
8510 if (GET_CODE (x) != PLUS
8511 || GET_CODE (XEXP (x, 1)) != CONST)
8514 if (REG_P (XEXP (x, 0))
8515 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
8516 /* %ebx + GOT/GOTOFF */
8518 else if (GET_CODE (XEXP (x, 0)) == PLUS)
8520 /* %ebx + %reg * scale + GOT/GOTOFF */
8521 reg_addend = XEXP (x, 0);
8522 if (REG_P (XEXP (reg_addend, 0))
8523 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
8524 reg_addend = XEXP (reg_addend, 1);
8525 else if (REG_P (XEXP (reg_addend, 1))
8526 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
8527 reg_addend = XEXP (reg_addend, 0);
8530 if (!REG_P (reg_addend)
8531 && GET_CODE (reg_addend) != MULT
8532 && GET_CODE (reg_addend) != ASHIFT)
8538 x = XEXP (XEXP (x, 1), 0);
8539 if (GET_CODE (x) == PLUS
8540 && CONST_INT_P (XEXP (x, 1)))
8542 const_addend = XEXP (x, 1);
8546 if (GET_CODE (x) == UNSPEC
8547 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8548 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8549 result = XVECEXP (x, 0, 0);
8551 if (TARGET_MACHO && darwin_local_data_pic (x)
8553 result = XEXP (x, 0);
8559 result = gen_rtx_PLUS (Pmode, result, const_addend);
8561 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8565 /* If X is a machine specific address (i.e. a symbol or label being
8566 referenced as a displacement from the GOT implemented using an
8567 UNSPEC), then return the base term. Otherwise return X. */
8570 ix86_find_base_term (rtx x)
8576 if (GET_CODE (x) != CONST)
8579 if (GET_CODE (term) == PLUS
8580 && (CONST_INT_P (XEXP (term, 1))
8581 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8582 term = XEXP (term, 0);
8583 if (GET_CODE (term) != UNSPEC
8584 || XINT (term, 1) != UNSPEC_GOTPCREL)
8587 term = XVECEXP (term, 0, 0);
8589 if (GET_CODE (term) != SYMBOL_REF
8590 && GET_CODE (term) != LABEL_REF)
8596 term = ix86_delegitimize_address (x);
8598 if (GET_CODE (term) != SYMBOL_REF
8599 && GET_CODE (term) != LABEL_REF)
8606 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8611 if (mode == CCFPmode || mode == CCFPUmode)
8613 enum rtx_code second_code, bypass_code;
8614 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8615 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8616 code = ix86_fp_compare_code_to_integer (code);
8620 code = reverse_condition (code);
8671 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8675 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8676 Those same assemblers have the same but opposite lossage on cmov. */
8678 suffix = fp ? "nbe" : "a";
8679 else if (mode == CCCmode)
8702 gcc_assert (mode == CCmode || mode == CCCmode);
8724 gcc_assert (mode == CCmode || mode == CCCmode);
8725 suffix = fp ? "nb" : "ae";
8728 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8735 else if (mode == CCCmode)
8736 suffix = fp ? "nb" : "ae";
8741 suffix = fp ? "u" : "p";
8744 suffix = fp ? "nu" : "np";
8749 fputs (suffix, file);
8752 /* Print the name of register X to FILE based on its machine mode and number.
8753 If CODE is 'w', pretend the mode is HImode.
8754 If CODE is 'b', pretend the mode is QImode.
8755 If CODE is 'k', pretend the mode is SImode.
8756 If CODE is 'q', pretend the mode is DImode.
8757 If CODE is 'h', pretend the reg is the 'high' byte register.
8758 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8761 print_reg (rtx x, int code, FILE *file)
8763 gcc_assert (x == pc_rtx
8764 || (REGNO (x) != ARG_POINTER_REGNUM
8765 && REGNO (x) != FRAME_POINTER_REGNUM
8766 && REGNO (x) != FLAGS_REG
8767 && REGNO (x) != FPSR_REG
8768 && REGNO (x) != FPCR_REG));
8770 if (ASSEMBLER_DIALECT == ASM_ATT)
8775 gcc_assert (TARGET_64BIT);
8776 fputs ("rip", file);
8780 if (code == 'w' || MMX_REG_P (x))
8782 else if (code == 'b')
8784 else if (code == 'k')
8786 else if (code == 'q')
8788 else if (code == 'y')
8790 else if (code == 'h')
8793 code = GET_MODE_SIZE (GET_MODE (x));
8795 /* Irritatingly, AMD extended registers use different naming convention
8796 from the normal registers. */
8797 if (REX_INT_REG_P (x))
8799 gcc_assert (TARGET_64BIT);
8803 error ("extended registers have no high halves");
8806 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8809 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8812 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8815 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8818 error ("unsupported operand size for extended register");
8826 if (STACK_TOP_P (x))
8828 fputs ("st(0)", file);
8835 if (! ANY_FP_REG_P (x))
8836 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8841 fputs (hi_reg_name[REGNO (x)], file);
8844 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8846 fputs (qi_reg_name[REGNO (x)], file);
8849 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8851 fputs (qi_high_reg_name[REGNO (x)], file);
8858 /* Locate some local-dynamic symbol still in use by this function
8859 so that we can print its name in some tls_local_dynamic_base
8863 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8867 if (GET_CODE (x) == SYMBOL_REF
8868 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8870 cfun->machine->some_ld_name = XSTR (x, 0);
8878 get_some_local_dynamic_name (void)
8882 if (cfun->machine->some_ld_name)
8883 return cfun->machine->some_ld_name;
8885 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8887 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8888 return cfun->machine->some_ld_name;
8894 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8895 C -- print opcode suffix for set/cmov insn.
8896 c -- like C, but print reversed condition
8897 F,f -- likewise, but for floating-point.
8898 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8900 R -- print the prefix for register names.
8901 z -- print the opcode suffix for the size of the current operand.
8902 * -- print a star (in certain assembler syntax)
8903 A -- print an absolute memory reference.
8904 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8905 s -- print a shift double count, followed by the assemblers argument
8907 b -- print the QImode name of the register for the indicated operand.
8908 %b0 would print %al if operands[0] is reg 0.
8909 w -- likewise, print the HImode name of the register.
8910 k -- likewise, print the SImode name of the register.
8911 q -- likewise, print the DImode name of the register.
8912 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8913 y -- print "st(0)" instead of "st" as a register.
8914 D -- print condition for SSE cmp instruction.
8915 P -- if PIC, print an @PLT suffix.
8916 X -- don't print any sort of PIC '@' suffix for a symbol.
8917 & -- print some in-use local-dynamic symbol name.
8918 H -- print a memory address offset by 8; used for sse high-parts
8919 Y -- print condition for SSE5 com* instruction.
8920 + -- print a branch hint as 'cs' or 'ds' prefix
8921 ; -- print a semicolon (after prefixes due to bug in older gas).
8925 print_operand (FILE *file, rtx x, int code)
8932 if (ASSEMBLER_DIALECT == ASM_ATT)
8937 assemble_name (file, get_some_local_dynamic_name ());
8941 switch (ASSEMBLER_DIALECT)
8948 /* Intel syntax. For absolute addresses, registers should not
8949 be surrounded by braces. */
8953 PRINT_OPERAND (file, x, 0);
8963 PRINT_OPERAND (file, x, 0);
8968 if (ASSEMBLER_DIALECT == ASM_ATT)
8973 if (ASSEMBLER_DIALECT == ASM_ATT)
8978 if (ASSEMBLER_DIALECT == ASM_ATT)
8983 if (ASSEMBLER_DIALECT == ASM_ATT)
8988 if (ASSEMBLER_DIALECT == ASM_ATT)
8993 if (ASSEMBLER_DIALECT == ASM_ATT)
8998 /* 387 opcodes don't get size suffixes if the operands are
9000 if (STACK_REG_P (x))
9003 /* Likewise if using Intel opcodes. */
9004 if (ASSEMBLER_DIALECT == ASM_INTEL)
9007 /* This is the size of op from size of operand. */
9008 switch (GET_MODE_SIZE (GET_MODE (x)))
9017 #ifdef HAVE_GAS_FILDS_FISTS
9027 if (GET_MODE (x) == SFmode)
9042 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
9044 #ifdef GAS_MNEMONICS
9070 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
9072 PRINT_OPERAND (file, x, 0);
9078 /* Little bit of braindamage here. The SSE compare instructions
9079 does use completely different names for the comparisons that the
9080 fp conditional moves. */
9081 switch (GET_CODE (x))
9096 fputs ("unord", file);
9100 fputs ("neq", file);
9104 fputs ("nlt", file);
9108 fputs ("nle", file);
9111 fputs ("ord", file);
9118 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9119 if (ASSEMBLER_DIALECT == ASM_ATT)
9121 switch (GET_MODE (x))
9123 case HImode: putc ('w', file); break;
9125 case SFmode: putc ('l', file); break;
9127 case DFmode: putc ('q', file); break;
9128 default: gcc_unreachable ();
9135 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
9138 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9139 if (ASSEMBLER_DIALECT == ASM_ATT)
9142 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
9145 /* Like above, but reverse condition */
9147 /* Check to see if argument to %c is really a constant
9148 and not a condition code which needs to be reversed. */
9149 if (!COMPARISON_P (x))
9151 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
9154 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
9157 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9158 if (ASSEMBLER_DIALECT == ASM_ATT)
9161 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
9165 /* It doesn't actually matter what mode we use here, as we're
9166 only going to use this for printing. */
9167 x = adjust_address_nv (x, DImode, 8);
9174 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
9177 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
9180 int pred_val = INTVAL (XEXP (x, 0));
9182 if (pred_val < REG_BR_PROB_BASE * 45 / 100
9183 || pred_val > REG_BR_PROB_BASE * 55 / 100)
9185 int taken = pred_val > REG_BR_PROB_BASE / 2;
9186 int cputaken = final_forward_branch_p (current_output_insn) == 0;
9188 /* Emit hints only in the case default branch prediction
9189 heuristics would fail. */
9190 if (taken != cputaken)
9192 /* We use 3e (DS) prefix for taken branches and
9193 2e (CS) prefix for not taken branches. */
9195 fputs ("ds ; ", file);
9197 fputs ("cs ; ", file);
9205 switch (GET_CODE (x))
9208 fputs ("neq", file);
9215 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
9219 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
9230 fputs ("unord", file);
9233 fputs ("ord", file);
9236 fputs ("ueq", file);
9239 fputs ("nlt", file);
9242 fputs ("nle", file);
9245 fputs ("ule", file);
9248 fputs ("ult", file);
9251 fputs ("une", file);
9260 fputs (" ; ", file);
9267 output_operand_lossage ("invalid operand code '%c'", code);
9272 print_reg (x, code, file);
9276 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
9277 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
9278 && GET_MODE (x) != BLKmode)
9281 switch (GET_MODE_SIZE (GET_MODE (x)))
9283 case 1: size = "BYTE"; break;
9284 case 2: size = "WORD"; break;
9285 case 4: size = "DWORD"; break;
9286 case 8: size = "QWORD"; break;
9287 case 12: size = "XWORD"; break;
9289 if (GET_MODE (x) == XFmode)
9298 /* Check for explicit size override (codes 'b', 'w' and 'k') */
9301 else if (code == 'w')
9303 else if (code == 'k')
9307 fputs (" PTR ", file);
9311 /* Avoid (%rip) for call operands. */
9312 if (CONSTANT_ADDRESS_P (x) && code == 'P'
9313 && !CONST_INT_P (x))
9314 output_addr_const (file, x);
9315 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
9316 output_operand_lossage ("invalid constraints for operand");
9321 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9326 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9327 REAL_VALUE_TO_TARGET_SINGLE (r, l);
9329 if (ASSEMBLER_DIALECT == ASM_ATT)
9331 fprintf (file, "0x%08lx", (long unsigned int) l);
9334 /* These float cases don't actually occur as immediate operands. */
9335 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9339 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9340 fprintf (file, "%s", dstr);
9343 else if (GET_CODE (x) == CONST_DOUBLE
9344 && GET_MODE (x) == XFmode)
9348 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9349 fprintf (file, "%s", dstr);
9354 /* We have patterns that allow zero sets of memory, for instance.
9355 In 64-bit mode, we should probably support all 8-byte vectors,
9356 since we can in fact encode that into an immediate. */
9357 if (GET_CODE (x) == CONST_VECTOR)
9359 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
9365 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
9367 if (ASSEMBLER_DIALECT == ASM_ATT)
9370 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
9371 || GET_CODE (x) == LABEL_REF)
9373 if (ASSEMBLER_DIALECT == ASM_ATT)
9376 fputs ("OFFSET FLAT:", file);
9379 if (CONST_INT_P (x))
9380 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9382 output_pic_addr_const (file, x, code);
9384 output_addr_const (file, x);
9388 /* Print a memory operand whose address is ADDR. */
9391 print_operand_address (FILE *file, rtx addr)
9393 struct ix86_address parts;
9394 rtx base, index, disp;
9396 int ok = ix86_decompose_address (addr, &parts);
9401 index = parts.index;
9403 scale = parts.scale;
9411 if (ASSEMBLER_DIALECT == ASM_ATT)
9413 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
9419 /* Use one byte shorter RIP relative addressing for 64bit mode. */
9420 if (TARGET_64BIT && !base && !index)
9424 if (GET_CODE (disp) == CONST
9425 && GET_CODE (XEXP (disp, 0)) == PLUS
9426 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9427 symbol = XEXP (XEXP (disp, 0), 0);
9429 if (GET_CODE (symbol) == LABEL_REF
9430 || (GET_CODE (symbol) == SYMBOL_REF
9431 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
9434 if (!base && !index)
9436 /* Displacement only requires special attention. */
9438 if (CONST_INT_P (disp))
9440 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
9441 fputs ("ds:", file);
9442 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
9445 output_pic_addr_const (file, disp, 0);
9447 output_addr_const (file, disp);
9451 if (ASSEMBLER_DIALECT == ASM_ATT)
9456 output_pic_addr_const (file, disp, 0);
9457 else if (GET_CODE (disp) == LABEL_REF)
9458 output_asm_label (disp);
9460 output_addr_const (file, disp);
9465 print_reg (base, 0, file);
9469 print_reg (index, 0, file);
9471 fprintf (file, ",%d", scale);
9477 rtx offset = NULL_RTX;
9481 /* Pull out the offset of a symbol; print any symbol itself. */
9482 if (GET_CODE (disp) == CONST
9483 && GET_CODE (XEXP (disp, 0)) == PLUS
9484 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9486 offset = XEXP (XEXP (disp, 0), 1);
9487 disp = gen_rtx_CONST (VOIDmode,
9488 XEXP (XEXP (disp, 0), 0));
9492 output_pic_addr_const (file, disp, 0);
9493 else if (GET_CODE (disp) == LABEL_REF)
9494 output_asm_label (disp);
9495 else if (CONST_INT_P (disp))
9498 output_addr_const (file, disp);
9504 print_reg (base, 0, file);
9507 if (INTVAL (offset) >= 0)
9509 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9513 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9520 print_reg (index, 0, file);
9522 fprintf (file, "*%d", scale);
9530 output_addr_const_extra (FILE *file, rtx x)
9534 if (GET_CODE (x) != UNSPEC)
9537 op = XVECEXP (x, 0, 0);
9538 switch (XINT (x, 1))
9540 case UNSPEC_GOTTPOFF:
9541 output_addr_const (file, op);
9542 /* FIXME: This might be @TPOFF in Sun ld. */
9543 fputs ("@GOTTPOFF", file);
9546 output_addr_const (file, op);
9547 fputs ("@TPOFF", file);
9550 output_addr_const (file, op);
9552 fputs ("@TPOFF", file);
9554 fputs ("@NTPOFF", file);
9557 output_addr_const (file, op);
9558 fputs ("@DTPOFF", file);
9560 case UNSPEC_GOTNTPOFF:
9561 output_addr_const (file, op);
9563 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9564 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
9566 fputs ("@GOTNTPOFF", file);
9568 case UNSPEC_INDNTPOFF:
9569 output_addr_const (file, op);
9570 fputs ("@INDNTPOFF", file);
9580 /* Split one or more DImode RTL references into pairs of SImode
9581 references. The RTL can be REG, offsettable MEM, integer constant, or
9582 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9583 split and "num" is its length. lo_half and hi_half are output arrays
9584 that parallel "operands". */
9587 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9591 rtx op = operands[num];
9593 /* simplify_subreg refuse to split volatile memory addresses,
9594 but we still have to handle it. */
9597 lo_half[num] = adjust_address (op, SImode, 0);
9598 hi_half[num] = adjust_address (op, SImode, 4);
9602 lo_half[num] = simplify_gen_subreg (SImode, op,
9603 GET_MODE (op) == VOIDmode
9604 ? DImode : GET_MODE (op), 0);
9605 hi_half[num] = simplify_gen_subreg (SImode, op,
9606 GET_MODE (op) == VOIDmode
9607 ? DImode : GET_MODE (op), 4);
9611 /* Split one or more TImode RTL references into pairs of DImode
9612 references. The RTL can be REG, offsettable MEM, integer constant, or
9613 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9614 split and "num" is its length. lo_half and hi_half are output arrays
9615 that parallel "operands". */
9618 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9622 rtx op = operands[num];
9624 /* simplify_subreg refuse to split volatile memory addresses, but we
9625 still have to handle it. */
9628 lo_half[num] = adjust_address (op, DImode, 0);
9629 hi_half[num] = adjust_address (op, DImode, 8);
9633 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
9634 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
9639 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
9640 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
9641 is the expression of the binary operation. The output may either be
9642 emitted here, or returned to the caller, like all output_* functions.
9644 There is no guarantee that the operands are the same mode, as they
9645 might be within FLOAT or FLOAT_EXTEND expressions. */
9647 #ifndef SYSV386_COMPAT
9648 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
9649 wants to fix the assemblers because that causes incompatibility
9650 with gcc. No-one wants to fix gcc because that causes
9651 incompatibility with assemblers... You can use the option of
9652 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
9653 #define SYSV386_COMPAT 1
9657 output_387_binary_op (rtx insn, rtx *operands)
9659 static char buf[30];
9662 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
9664 #ifdef ENABLE_CHECKING
9665 /* Even if we do not want to check the inputs, this documents input
9666 constraints. Which helps in understanding the following code. */
9667 if (STACK_REG_P (operands[0])
9668 && ((REG_P (operands[1])
9669 && REGNO (operands[0]) == REGNO (operands[1])
9670 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
9671 || (REG_P (operands[2])
9672 && REGNO (operands[0]) == REGNO (operands[2])
9673 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9674 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9677 gcc_assert (is_sse);
9680 switch (GET_CODE (operands[3]))
9683 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9684 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9692 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9693 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9701 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9702 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9710 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9711 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9725 if (GET_MODE (operands[0]) == SFmode)
9726 strcat (buf, "ss\t{%2, %0|%0, %2}");
9728 strcat (buf, "sd\t{%2, %0|%0, %2}");
9733 switch (GET_CODE (operands[3]))
9737 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9739 rtx temp = operands[2];
9740 operands[2] = operands[1];
9744 /* know operands[0] == operands[1]. */
9746 if (MEM_P (operands[2]))
9752 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9754 if (STACK_TOP_P (operands[0]))
9755 /* How is it that we are storing to a dead operand[2]?
9756 Well, presumably operands[1] is dead too. We can't
9757 store the result to st(0) as st(0) gets popped on this
9758 instruction. Instead store to operands[2] (which I
9759 think has to be st(1)). st(1) will be popped later.
9760 gcc <= 2.8.1 didn't have this check and generated
9761 assembly code that the Unixware assembler rejected. */
9762 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9764 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9768 if (STACK_TOP_P (operands[0]))
9769 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9771 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9776 if (MEM_P (operands[1]))
9782 if (MEM_P (operands[2]))
9788 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9791 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9792 derived assemblers, confusingly reverse the direction of
9793 the operation for fsub{r} and fdiv{r} when the
9794 destination register is not st(0). The Intel assembler
9795 doesn't have this brain damage. Read !SYSV386_COMPAT to
9796 figure out what the hardware really does. */
9797 if (STACK_TOP_P (operands[0]))
9798 p = "{p\t%0, %2|rp\t%2, %0}";
9800 p = "{rp\t%2, %0|p\t%0, %2}";
9802 if (STACK_TOP_P (operands[0]))
9803 /* As above for fmul/fadd, we can't store to st(0). */
9804 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9806 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9811 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9814 if (STACK_TOP_P (operands[0]))
9815 p = "{rp\t%0, %1|p\t%1, %0}";
9817 p = "{p\t%1, %0|rp\t%0, %1}";
9819 if (STACK_TOP_P (operands[0]))
9820 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9822 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9827 if (STACK_TOP_P (operands[0]))
9829 if (STACK_TOP_P (operands[1]))
9830 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9832 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9835 else if (STACK_TOP_P (operands[1]))
9838 p = "{\t%1, %0|r\t%0, %1}";
9840 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9846 p = "{r\t%2, %0|\t%0, %2}";
9848 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9861 /* Return needed mode for entity in optimize_mode_switching pass. */
9864 ix86_mode_needed (int entity, rtx insn)
9866 enum attr_i387_cw mode;
9868 /* The mode UNINITIALIZED is used to store control word after a
9869 function call or ASM pattern. The mode ANY specify that function
9870 has no requirements on the control word and make no changes in the
9871 bits we are interested in. */
9874 || (NONJUMP_INSN_P (insn)
9875 && (asm_noperands (PATTERN (insn)) >= 0
9876 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
9877 return I387_CW_UNINITIALIZED;
9879 if (recog_memoized (insn) < 0)
9882 mode = get_attr_i387_cw (insn);
9887 if (mode == I387_CW_TRUNC)
9892 if (mode == I387_CW_FLOOR)
9897 if (mode == I387_CW_CEIL)
9902 if (mode == I387_CW_MASK_PM)
9913 /* Output code to initialize control word copies used by trunc?f?i and
9914 rounding patterns. CURRENT_MODE is set to current control word,
9915 while NEW_MODE is set to new control word. */
9918 emit_i387_cw_initialization (int mode)
9920 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
9923 enum ix86_stack_slot slot;
9925 rtx reg = gen_reg_rtx (HImode);
9927 emit_insn (gen_x86_fnstcw_1 (stored_mode));
9928 emit_move_insn (reg, copy_rtx (stored_mode));
9930 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
9935 /* round toward zero (truncate) */
9936 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
9937 slot = SLOT_CW_TRUNC;
9941 /* round down toward -oo */
9942 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9943 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
9944 slot = SLOT_CW_FLOOR;
9948 /* round up toward +oo */
9949 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9950 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
9951 slot = SLOT_CW_CEIL;
9954 case I387_CW_MASK_PM:
9955 /* mask precision exception for nearbyint() */
9956 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9957 slot = SLOT_CW_MASK_PM;
9969 /* round toward zero (truncate) */
9970 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
9971 slot = SLOT_CW_TRUNC;
9975 /* round down toward -oo */
9976 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
9977 slot = SLOT_CW_FLOOR;
9981 /* round up toward +oo */
9982 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
9983 slot = SLOT_CW_CEIL;
9986 case I387_CW_MASK_PM:
9987 /* mask precision exception for nearbyint() */
9988 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9989 slot = SLOT_CW_MASK_PM;
9997 gcc_assert (slot < MAX_386_STACK_LOCALS);
9999 new_mode = assign_386_stack_local (HImode, slot);
10000 emit_move_insn (new_mode, reg);
10003 /* Output code for INSN to convert a float to a signed int. OPERANDS
10004 are the insn operands. The output may be [HSD]Imode and the input
10005 operand may be [SDX]Fmode. */
10008 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
10010 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
10011 int dimode_p = GET_MODE (operands[0]) == DImode;
10012 int round_mode = get_attr_i387_cw (insn);
10014 /* Jump through a hoop or two for DImode, since the hardware has no
10015 non-popping instruction. We used to do this a different way, but
10016 that was somewhat fragile and broke with post-reload splitters. */
10017 if ((dimode_p || fisttp) && !stack_top_dies)
10018 output_asm_insn ("fld\t%y1", operands);
10020 gcc_assert (STACK_TOP_P (operands[1]));
10021 gcc_assert (MEM_P (operands[0]));
10022 gcc_assert (GET_MODE (operands[1]) != TFmode);
10025 output_asm_insn ("fisttp%z0\t%0", operands);
10028 if (round_mode != I387_CW_ANY)
10029 output_asm_insn ("fldcw\t%3", operands);
10030 if (stack_top_dies || dimode_p)
10031 output_asm_insn ("fistp%z0\t%0", operands);
10033 output_asm_insn ("fist%z0\t%0", operands);
10034 if (round_mode != I387_CW_ANY)
10035 output_asm_insn ("fldcw\t%2", operands);
10041 /* Output code for x87 ffreep insn. The OPNO argument, which may only
10042 have the values zero or one, indicates the ffreep insn's operand
10043 from the OPERANDS array. */
10045 static const char *
10046 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
10048 if (TARGET_USE_FFREEP)
10049 #if HAVE_AS_IX86_FFREEP
10050 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
10053 static char retval[] = ".word\t0xc_df";
10054 int regno = REGNO (operands[opno]);
10056 gcc_assert (FP_REGNO_P (regno));
10058 retval[9] = '0' + (regno - FIRST_STACK_REG);
10063 return opno ? "fstp\t%y1" : "fstp\t%y0";
10067 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
10068 should be used. UNORDERED_P is true when fucom should be used. */
10071 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
10073 int stack_top_dies;
10074 rtx cmp_op0, cmp_op1;
10075 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
10079 cmp_op0 = operands[0];
10080 cmp_op1 = operands[1];
10084 cmp_op0 = operands[1];
10085 cmp_op1 = operands[2];
10090 if (GET_MODE (operands[0]) == SFmode)
10092 return "ucomiss\t{%1, %0|%0, %1}";
10094 return "comiss\t{%1, %0|%0, %1}";
10097 return "ucomisd\t{%1, %0|%0, %1}";
10099 return "comisd\t{%1, %0|%0, %1}";
10102 gcc_assert (STACK_TOP_P (cmp_op0));
10104 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
10106 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
10108 if (stack_top_dies)
10110 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
10111 return output_387_ffreep (operands, 1);
10114 return "ftst\n\tfnstsw\t%0";
10117 if (STACK_REG_P (cmp_op1)
10119 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
10120 && REGNO (cmp_op1) != FIRST_STACK_REG)
10122 /* If both the top of the 387 stack dies, and the other operand
10123 is also a stack register that dies, then this must be a
10124 `fcompp' float compare */
10128 /* There is no double popping fcomi variant. Fortunately,
10129 eflags is immune from the fstp's cc clobbering. */
10131 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
10133 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
10134 return output_387_ffreep (operands, 0);
10139 return "fucompp\n\tfnstsw\t%0";
10141 return "fcompp\n\tfnstsw\t%0";
10146 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
10148 static const char * const alt[16] =
10150 "fcom%z2\t%y2\n\tfnstsw\t%0",
10151 "fcomp%z2\t%y2\n\tfnstsw\t%0",
10152 "fucom%z2\t%y2\n\tfnstsw\t%0",
10153 "fucomp%z2\t%y2\n\tfnstsw\t%0",
10155 "ficom%z2\t%y2\n\tfnstsw\t%0",
10156 "ficomp%z2\t%y2\n\tfnstsw\t%0",
10160 "fcomi\t{%y1, %0|%0, %y1}",
10161 "fcomip\t{%y1, %0|%0, %y1}",
10162 "fucomi\t{%y1, %0|%0, %y1}",
10163 "fucomip\t{%y1, %0|%0, %y1}",
10174 mask = eflags_p << 3;
10175 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
10176 mask |= unordered_p << 1;
10177 mask |= stack_top_dies;
10179 gcc_assert (mask < 16);
10188 ix86_output_addr_vec_elt (FILE *file, int value)
10190 const char *directive = ASM_LONG;
10194 directive = ASM_QUAD;
10196 gcc_assert (!TARGET_64BIT);
10199 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
10203 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
10205 const char *directive = ASM_LONG;
10208 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
10209 directive = ASM_QUAD;
10211 gcc_assert (!TARGET_64BIT);
10213 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
10214 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
10215 fprintf (file, "%s%s%d-%s%d\n",
10216 directive, LPREFIX, value, LPREFIX, rel);
10217 else if (HAVE_AS_GOTOFF_IN_DATA)
10218 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
10220 else if (TARGET_MACHO)
10222 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
10223 machopic_output_function_base_name (file);
10224 fprintf(file, "\n");
10228 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
10229 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
10232 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
10236 ix86_expand_clear (rtx dest)
10240 /* We play register width games, which are only valid after reload. */
10241 gcc_assert (reload_completed);
10243 /* Avoid HImode and its attendant prefix byte. */
10244 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
10245 dest = gen_rtx_REG (SImode, REGNO (dest));
10246 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
10248 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
10249 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
10251 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10252 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
10258 /* X is an unchanging MEM. If it is a constant pool reference, return
10259 the constant pool rtx, else NULL. */
10262 maybe_get_pool_constant (rtx x)
10264 x = ix86_delegitimize_address (XEXP (x, 0));
10266 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
10267 return get_pool_constant (x);
10273 ix86_expand_move (enum machine_mode mode, rtx operands[])
10276 enum tls_model model;
10281 if (GET_CODE (op1) == SYMBOL_REF)
10283 model = SYMBOL_REF_TLS_MODEL (op1);
10286 op1 = legitimize_tls_address (op1, model, true);
10287 op1 = force_operand (op1, op0);
10291 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10292 && SYMBOL_REF_DLLIMPORT_P (op1))
10293 op1 = legitimize_dllimport_symbol (op1, false);
10295 else if (GET_CODE (op1) == CONST
10296 && GET_CODE (XEXP (op1, 0)) == PLUS
10297 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
10299 rtx addend = XEXP (XEXP (op1, 0), 1);
10300 rtx symbol = XEXP (XEXP (op1, 0), 0);
10303 model = SYMBOL_REF_TLS_MODEL (symbol);
10305 tmp = legitimize_tls_address (symbol, model, true);
10306 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10307 && SYMBOL_REF_DLLIMPORT_P (symbol))
10308 tmp = legitimize_dllimport_symbol (symbol, true);
10312 tmp = force_operand (tmp, NULL);
10313 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
10314 op0, 1, OPTAB_DIRECT);
10320 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
10322 if (TARGET_MACHO && !TARGET_64BIT)
10327 rtx temp = ((reload_in_progress
10328 || ((op0 && REG_P (op0))
10330 ? op0 : gen_reg_rtx (Pmode));
10331 op1 = machopic_indirect_data_reference (op1, temp);
10332 op1 = machopic_legitimize_pic_address (op1, mode,
10333 temp == op1 ? 0 : temp);
10335 else if (MACHOPIC_INDIRECT)
10336 op1 = machopic_indirect_data_reference (op1, 0);
10344 op1 = force_reg (Pmode, op1);
10345 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
10347 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
10348 op1 = legitimize_pic_address (op1, reg);
10357 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
10358 || !push_operand (op0, mode))
10360 op1 = force_reg (mode, op1);
10362 if (push_operand (op0, mode)
10363 && ! general_no_elim_operand (op1, mode))
10364 op1 = copy_to_mode_reg (mode, op1);
10366 /* Force large constants in 64bit compilation into register
10367 to get them CSEed. */
10368 if (can_create_pseudo_p ()
10369 && (mode == DImode) && TARGET_64BIT
10370 && immediate_operand (op1, mode)
10371 && !x86_64_zext_immediate_operand (op1, VOIDmode)
10372 && !register_operand (op0, mode)
10374 op1 = copy_to_mode_reg (mode, op1);
10376 if (can_create_pseudo_p ()
10377 && FLOAT_MODE_P (mode)
10378 && GET_CODE (op1) == CONST_DOUBLE)
10380 /* If we are loading a floating point constant to a register,
10381 force the value to memory now, since we'll get better code
10382 out the back end. */
10384 op1 = validize_mem (force_const_mem (mode, op1));
10385 if (!register_operand (op0, mode))
10387 rtx temp = gen_reg_rtx (mode);
10388 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
10389 emit_move_insn (op0, temp);
10395 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10399 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
10401 rtx op0 = operands[0], op1 = operands[1];
10402 unsigned int align = GET_MODE_ALIGNMENT (mode);
10404 /* Force constants other than zero into memory. We do not know how
10405 the instructions used to build constants modify the upper 64 bits
10406 of the register, once we have that information we may be able
10407 to handle some of them more efficiently. */
10408 if (can_create_pseudo_p ()
10409 && register_operand (op0, mode)
10410 && (CONSTANT_P (op1)
10411 || (GET_CODE (op1) == SUBREG
10412 && CONSTANT_P (SUBREG_REG (op1))))
10413 && standard_sse_constant_p (op1) <= 0)
10414 op1 = validize_mem (force_const_mem (mode, op1));
10416 /* We need to check memory alignment for SSE mode since attribute
10417 can make operands unaligned. */
10418 if (can_create_pseudo_p ()
10419 && SSE_REG_MODE_P (mode)
10420 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
10421 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
10425 /* ix86_expand_vector_move_misalign() does not like constants ... */
10426 if (CONSTANT_P (op1)
10427 || (GET_CODE (op1) == SUBREG
10428 && CONSTANT_P (SUBREG_REG (op1))))
10429 op1 = validize_mem (force_const_mem (mode, op1));
10431 /* ... nor both arguments in memory. */
10432 if (!register_operand (op0, mode)
10433 && !register_operand (op1, mode))
10434 op1 = force_reg (mode, op1);
10436 tmp[0] = op0; tmp[1] = op1;
10437 ix86_expand_vector_move_misalign (mode, tmp);
10441 /* Make operand1 a register if it isn't already. */
10442 if (can_create_pseudo_p ()
10443 && !register_operand (op0, mode)
10444 && !register_operand (op1, mode))
10446 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
10450 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10453 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
10454 straight to ix86_expand_vector_move. */
10455 /* Code generation for scalar reg-reg moves of single and double precision data:
10456 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
10460 if (x86_sse_partial_reg_dependency == true)
10465 Code generation for scalar loads of double precision data:
10466 if (x86_sse_split_regs == true)
10467 movlpd mem, reg (gas syntax)
10471 Code generation for unaligned packed loads of single precision data
10472 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
10473 if (x86_sse_unaligned_move_optimal)
10476 if (x86_sse_partial_reg_dependency == true)
10488 Code generation for unaligned packed loads of double precision data
10489 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
10490 if (x86_sse_unaligned_move_optimal)
10493 if (x86_sse_split_regs == true)
10506 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
10515 /* If we're optimizing for size, movups is the smallest. */
10518 op0 = gen_lowpart (V4SFmode, op0);
10519 op1 = gen_lowpart (V4SFmode, op1);
10520 emit_insn (gen_sse_movups (op0, op1));
10524 /* ??? If we have typed data, then it would appear that using
10525 movdqu is the only way to get unaligned data loaded with
10527 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10529 op0 = gen_lowpart (V16QImode, op0);
10530 op1 = gen_lowpart (V16QImode, op1);
10531 emit_insn (gen_sse2_movdqu (op0, op1));
10535 if (TARGET_SSE2 && mode == V2DFmode)
10539 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10541 op0 = gen_lowpart (V2DFmode, op0);
10542 op1 = gen_lowpart (V2DFmode, op1);
10543 emit_insn (gen_sse2_movupd (op0, op1));
10547 /* When SSE registers are split into halves, we can avoid
10548 writing to the top half twice. */
10549 if (TARGET_SSE_SPLIT_REGS)
10551 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10556 /* ??? Not sure about the best option for the Intel chips.
10557 The following would seem to satisfy; the register is
10558 entirely cleared, breaking the dependency chain. We
10559 then store to the upper half, with a dependency depth
10560 of one. A rumor has it that Intel recommends two movsd
10561 followed by an unpacklpd, but this is unconfirmed. And
10562 given that the dependency depth of the unpacklpd would
10563 still be one, I'm not sure why this would be better. */
10564 zero = CONST0_RTX (V2DFmode);
10567 m = adjust_address (op1, DFmode, 0);
10568 emit_insn (gen_sse2_loadlpd (op0, zero, m));
10569 m = adjust_address (op1, DFmode, 8);
10570 emit_insn (gen_sse2_loadhpd (op0, op0, m));
10574 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10576 op0 = gen_lowpart (V4SFmode, op0);
10577 op1 = gen_lowpart (V4SFmode, op1);
10578 emit_insn (gen_sse_movups (op0, op1));
10582 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
10583 emit_move_insn (op0, CONST0_RTX (mode));
10585 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10587 if (mode != V4SFmode)
10588 op0 = gen_lowpart (V4SFmode, op0);
10589 m = adjust_address (op1, V2SFmode, 0);
10590 emit_insn (gen_sse_loadlps (op0, op0, m));
10591 m = adjust_address (op1, V2SFmode, 8);
10592 emit_insn (gen_sse_loadhps (op0, op0, m));
10595 else if (MEM_P (op0))
10597 /* If we're optimizing for size, movups is the smallest. */
10600 op0 = gen_lowpart (V4SFmode, op0);
10601 op1 = gen_lowpart (V4SFmode, op1);
10602 emit_insn (gen_sse_movups (op0, op1));
10606 /* ??? Similar to above, only less clear because of quote
10607 typeless stores unquote. */
10608 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
10609 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10611 op0 = gen_lowpart (V16QImode, op0);
10612 op1 = gen_lowpart (V16QImode, op1);
10613 emit_insn (gen_sse2_movdqu (op0, op1));
10617 if (TARGET_SSE2 && mode == V2DFmode)
10619 m = adjust_address (op0, DFmode, 0);
10620 emit_insn (gen_sse2_storelpd (m, op1));
10621 m = adjust_address (op0, DFmode, 8);
10622 emit_insn (gen_sse2_storehpd (m, op1));
10626 if (mode != V4SFmode)
10627 op1 = gen_lowpart (V4SFmode, op1);
10628 m = adjust_address (op0, V2SFmode, 0);
10629 emit_insn (gen_sse_storelps (m, op1));
10630 m = adjust_address (op0, V2SFmode, 8);
10631 emit_insn (gen_sse_storehps (m, op1));
10635 gcc_unreachable ();
10638 /* Expand a push in MODE. This is some mode for which we do not support
10639 proper push instructions, at least from the registers that we expect
10640 the value to live in. */
10643 ix86_expand_push (enum machine_mode mode, rtx x)
10647 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
10648 GEN_INT (-GET_MODE_SIZE (mode)),
10649 stack_pointer_rtx, 1, OPTAB_DIRECT);
10650 if (tmp != stack_pointer_rtx)
10651 emit_move_insn (stack_pointer_rtx, tmp);
10653 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
10654 emit_move_insn (tmp, x);
10657 /* Helper function of ix86_fixup_binary_operands to canonicalize
10658 operand order. Returns true if the operands should be swapped. */
10661 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
10664 rtx dst = operands[0];
10665 rtx src1 = operands[1];
10666 rtx src2 = operands[2];
10668 /* If the operation is not commutative, we can't do anything. */
10669 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10672 /* Highest priority is that src1 should match dst. */
10673 if (rtx_equal_p (dst, src1))
10675 if (rtx_equal_p (dst, src2))
10678 /* Next highest priority is that immediate constants come second. */
10679 if (immediate_operand (src2, mode))
10681 if (immediate_operand (src1, mode))
10684 /* Lowest priority is that memory references should come second. */
10694 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10695 destination to use for the operation. If different from the true
10696 destination in operands[0], a copy operation will be required. */
10699 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10702 rtx dst = operands[0];
10703 rtx src1 = operands[1];
10704 rtx src2 = operands[2];
10706 /* Canonicalize operand order. */
10707 if (ix86_swap_binary_operands_p (code, mode, operands))
10711 /* It is invalid to swap operands of different modes. */
10712 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
10719 /* Both source operands cannot be in memory. */
10720 if (MEM_P (src1) && MEM_P (src2))
10722 /* Optimization: Only read from memory once. */
10723 if (rtx_equal_p (src1, src2))
10725 src2 = force_reg (mode, src2);
10729 src2 = force_reg (mode, src2);
10732 /* If the destination is memory, and we do not have matching source
10733 operands, do things in registers. */
10734 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10735 dst = gen_reg_rtx (mode);
10737 /* Source 1 cannot be a constant. */
10738 if (CONSTANT_P (src1))
10739 src1 = force_reg (mode, src1);
10741 /* Source 1 cannot be a non-matching memory. */
10742 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10743 src1 = force_reg (mode, src1);
10745 operands[1] = src1;
10746 operands[2] = src2;
10750 /* Similarly, but assume that the destination has already been
10751 set up properly. */
10754 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10755 enum machine_mode mode, rtx operands[])
10757 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10758 gcc_assert (dst == operands[0]);
10761 /* Attempt to expand a binary operator. Make the expansion closer to the
10762 actual machine, then just general_operand, which will allow 3 separate
10763 memory references (one output, two input) in a single insn. */
10766 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10769 rtx src1, src2, dst, op, clob;
10771 dst = ix86_fixup_binary_operands (code, mode, operands);
10772 src1 = operands[1];
10773 src2 = operands[2];
10775 /* Emit the instruction. */
10777 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10778 if (reload_in_progress)
10780 /* Reload doesn't know about the flags register, and doesn't know that
10781 it doesn't want to clobber it. We can only do this with PLUS. */
10782 gcc_assert (code == PLUS);
10787 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10788 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10791 /* Fix up the destination if needed. */
10792 if (dst != operands[0])
10793 emit_move_insn (operands[0], dst);
10796 /* Return TRUE or FALSE depending on whether the binary operator meets the
10797 appropriate constraints. */
10800 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10803 rtx dst = operands[0];
10804 rtx src1 = operands[1];
10805 rtx src2 = operands[2];
10807 /* Both source operands cannot be in memory. */
10808 if (MEM_P (src1) && MEM_P (src2))
10811 /* Canonicalize operand order for commutative operators. */
10812 if (ix86_swap_binary_operands_p (code, mode, operands))
10819 /* If the destination is memory, we must have a matching source operand. */
10820 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10823 /* Source 1 cannot be a constant. */
10824 if (CONSTANT_P (src1))
10827 /* Source 1 cannot be a non-matching memory. */
10828 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10834 /* Attempt to expand a unary operator. Make the expansion closer to the
10835 actual machine, then just general_operand, which will allow 2 separate
10836 memory references (one output, one input) in a single insn. */
10839 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10842 int matching_memory;
10843 rtx src, dst, op, clob;
10848 /* If the destination is memory, and we do not have matching source
10849 operands, do things in registers. */
10850 matching_memory = 0;
10853 if (rtx_equal_p (dst, src))
10854 matching_memory = 1;
10856 dst = gen_reg_rtx (mode);
10859 /* When source operand is memory, destination must match. */
10860 if (MEM_P (src) && !matching_memory)
10861 src = force_reg (mode, src);
10863 /* Emit the instruction. */
10865 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10866 if (reload_in_progress || code == NOT)
10868 /* Reload doesn't know about the flags register, and doesn't know that
10869 it doesn't want to clobber it. */
10870 gcc_assert (code == NOT);
10875 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10876 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10879 /* Fix up the destination if needed. */
10880 if (dst != operands[0])
10881 emit_move_insn (operands[0], dst);
10884 /* Return TRUE or FALSE depending on whether the unary operator meets the
10885 appropriate constraints. */
10888 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
10889 enum machine_mode mode ATTRIBUTE_UNUSED,
10890 rtx operands[2] ATTRIBUTE_UNUSED)
10892 /* If one of operands is memory, source and destination must match. */
10893 if ((MEM_P (operands[0])
10894 || MEM_P (operands[1]))
10895 && ! rtx_equal_p (operands[0], operands[1]))
10900 /* Post-reload splitter for converting an SF or DFmode value in an
10901 SSE register into an unsigned SImode. */
10904 ix86_split_convert_uns_si_sse (rtx operands[])
10906 enum machine_mode vecmode;
10907 rtx value, large, zero_or_two31, input, two31, x;
10909 large = operands[1];
10910 zero_or_two31 = operands[2];
10911 input = operands[3];
10912 two31 = operands[4];
10913 vecmode = GET_MODE (large);
10914 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
10916 /* Load up the value into the low element. We must ensure that the other
10917 elements are valid floats -- zero is the easiest such value. */
10920 if (vecmode == V4SFmode)
10921 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
10923 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
10927 input = gen_rtx_REG (vecmode, REGNO (input));
10928 emit_move_insn (value, CONST0_RTX (vecmode));
10929 if (vecmode == V4SFmode)
10930 emit_insn (gen_sse_movss (value, value, input));
10932 emit_insn (gen_sse2_movsd (value, value, input));
10935 emit_move_insn (large, two31);
10936 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
10938 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
10939 emit_insn (gen_rtx_SET (VOIDmode, large, x));
10941 x = gen_rtx_AND (vecmode, zero_or_two31, large);
10942 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
10944 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
10945 emit_insn (gen_rtx_SET (VOIDmode, value, x));
10947 large = gen_rtx_REG (V4SImode, REGNO (large));
10948 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
10950 x = gen_rtx_REG (V4SImode, REGNO (value));
10951 if (vecmode == V4SFmode)
10952 emit_insn (gen_sse2_cvttps2dq (x, value));
10954 emit_insn (gen_sse2_cvttpd2dq (x, value));
10957 emit_insn (gen_xorv4si3 (value, value, large));
10960 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10961 Expects the 64-bit DImode to be supplied in a pair of integral
10962 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10963 -mfpmath=sse, !optimize_size only. */
10966 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
10968 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
10969 rtx int_xmm, fp_xmm;
10970 rtx biases, exponents;
10973 int_xmm = gen_reg_rtx (V4SImode);
10974 if (TARGET_INTER_UNIT_MOVES)
10975 emit_insn (gen_movdi_to_sse (int_xmm, input));
10976 else if (TARGET_SSE_SPLIT_REGS)
10978 emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
10979 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
10983 x = gen_reg_rtx (V2DImode);
10984 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
10985 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
10988 x = gen_rtx_CONST_VECTOR (V4SImode,
10989 gen_rtvec (4, GEN_INT (0x43300000UL),
10990 GEN_INT (0x45300000UL),
10991 const0_rtx, const0_rtx));
10992 exponents = validize_mem (force_const_mem (V4SImode, x));
10994 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10995 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
10997 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10998 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10999 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
11000 (0x1.0p84 + double(fp_value_hi_xmm)).
11001 Note these exponents differ by 32. */
11003 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
11005 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
11006 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
11007 real_ldexp (&bias_lo_rvt, &dconst1, 52);
11008 real_ldexp (&bias_hi_rvt, &dconst1, 84);
11009 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
11010 x = const_double_from_real_value (bias_hi_rvt, DFmode);
11011 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
11012 biases = validize_mem (force_const_mem (V2DFmode, biases));
11013 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
11015 /* Add the upper and lower DFmode values together. */
11017 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
11020 x = copy_to_mode_reg (V2DFmode, fp_xmm);
11021 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
11022 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
11025 ix86_expand_vector_extract (false, target, fp_xmm, 0);
11028 /* Not used, but eases macroization of patterns. */
11030 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
11031 rtx input ATTRIBUTE_UNUSED)
11033 gcc_unreachable ();
11036 /* Convert an unsigned SImode value into a DFmode. Only currently used
11037 for SSE, but applicable anywhere. */
11040 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
11042 REAL_VALUE_TYPE TWO31r;
11045 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
11046 NULL, 1, OPTAB_DIRECT);
11048 fp = gen_reg_rtx (DFmode);
11049 emit_insn (gen_floatsidf2 (fp, x));
11051 real_ldexp (&TWO31r, &dconst1, 31);
11052 x = const_double_from_real_value (TWO31r, DFmode);
11054 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
11056 emit_move_insn (target, x);
11059 /* Convert a signed DImode value into a DFmode. Only used for SSE in
11060 32-bit mode; otherwise we have a direct convert instruction. */
11063 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
11065 REAL_VALUE_TYPE TWO32r;
11066 rtx fp_lo, fp_hi, x;
11068 fp_lo = gen_reg_rtx (DFmode);
11069 fp_hi = gen_reg_rtx (DFmode);
11071 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
11073 real_ldexp (&TWO32r, &dconst1, 32);
11074 x = const_double_from_real_value (TWO32r, DFmode);
11075 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
11077 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
11079 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
11082 emit_move_insn (target, x);
11085 /* Convert an unsigned SImode value into a SFmode, using only SSE.
11086 For x86_32, -mfpmath=sse, !optimize_size only. */
11088 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
11090 REAL_VALUE_TYPE ONE16r;
11091 rtx fp_hi, fp_lo, int_hi, int_lo, x;
11093 real_ldexp (&ONE16r, &dconst1, 16);
11094 x = const_double_from_real_value (ONE16r, SFmode);
11095 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
11096 NULL, 0, OPTAB_DIRECT);
11097 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
11098 NULL, 0, OPTAB_DIRECT);
11099 fp_hi = gen_reg_rtx (SFmode);
11100 fp_lo = gen_reg_rtx (SFmode);
11101 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
11102 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
11103 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
11105 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
11107 if (!rtx_equal_p (target, fp_hi))
11108 emit_move_insn (target, fp_hi);
11111 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
11112 then replicate the value for all elements of the vector
11116 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
11123 v = gen_rtvec (4, value, value, value, value);
11124 return gen_rtx_CONST_VECTOR (V4SImode, v);
11128 v = gen_rtvec (2, value, value);
11129 return gen_rtx_CONST_VECTOR (V2DImode, v);
11133 v = gen_rtvec (4, value, value, value, value);
11135 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
11136 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11137 return gen_rtx_CONST_VECTOR (V4SFmode, v);
11141 v = gen_rtvec (2, value, value);
11143 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
11144 return gen_rtx_CONST_VECTOR (V2DFmode, v);
11147 gcc_unreachable ();
11151 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
11152 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
11153 for an SSE register. If VECT is true, then replicate the mask for
11154 all elements of the vector register. If INVERT is true, then create
11155 a mask excluding the sign bit. */
11158 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
11160 enum machine_mode vec_mode, imode;
11161 HOST_WIDE_INT hi, lo;
11166 /* Find the sign bit, sign extended to 2*HWI. */
11172 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
11173 lo = 0x80000000, hi = lo < 0;
11179 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
11180 if (HOST_BITS_PER_WIDE_INT >= 64)
11181 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
11183 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
11189 vec_mode = VOIDmode;
11190 gcc_assert (HOST_BITS_PER_WIDE_INT >= 64);
11191 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
11195 gcc_unreachable ();
11199 lo = ~lo, hi = ~hi;
11201 /* Force this value into the low part of a fp vector constant. */
11202 mask = immed_double_const (lo, hi, imode);
11203 mask = gen_lowpart (mode, mask);
11205 if (vec_mode == VOIDmode)
11206 return force_reg (mode, mask);
11208 v = ix86_build_const_vector (mode, vect, mask);
11209 return force_reg (vec_mode, v);
11212 /* Generate code for floating point ABS or NEG. */
11215 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
11218 rtx mask, set, use, clob, dst, src;
11219 bool use_sse = false;
11220 bool vector_mode = VECTOR_MODE_P (mode);
11221 enum machine_mode elt_mode = mode;
11225 elt_mode = GET_MODE_INNER (mode);
11228 else if (mode == TFmode)
11230 else if (TARGET_SSE_MATH)
11231 use_sse = SSE_FLOAT_MODE_P (mode);
11233 /* NEG and ABS performed with SSE use bitwise mask operations.
11234 Create the appropriate mask now. */
11236 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
11245 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
11246 set = gen_rtx_SET (VOIDmode, dst, set);
11251 set = gen_rtx_fmt_e (code, mode, src);
11252 set = gen_rtx_SET (VOIDmode, dst, set);
11255 use = gen_rtx_USE (VOIDmode, mask);
11256 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11257 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11258 gen_rtvec (3, set, use, clob)));
11265 /* Expand a copysign operation. Special case operand 0 being a constant. */
11268 ix86_expand_copysign (rtx operands[])
11270 enum machine_mode mode;
11271 rtx dest, op0, op1, mask, nmask;
11273 dest = operands[0];
11277 mode = GET_MODE (dest);
11279 if (GET_CODE (op0) == CONST_DOUBLE)
11281 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
11283 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
11284 op0 = simplify_unary_operation (ABS, mode, op0, mode);
11286 if (mode == SFmode || mode == DFmode)
11288 enum machine_mode vmode;
11290 vmode = mode == SFmode ? V4SFmode : V2DFmode;
11292 if (op0 == CONST0_RTX (mode))
11293 op0 = CONST0_RTX (vmode);
11298 if (mode == SFmode)
11299 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
11300 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11302 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
11304 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
11307 else if (op0 != CONST0_RTX (mode))
11308 op0 = force_reg (mode, op0);
11310 mask = ix86_build_signbit_mask (mode, 0, 0);
11312 if (mode == SFmode)
11313 copysign_insn = gen_copysignsf3_const;
11314 else if (mode == DFmode)
11315 copysign_insn = gen_copysigndf3_const;
11317 copysign_insn = gen_copysigntf3_const;
11319 emit_insn (copysign_insn (dest, op0, op1, mask));
11323 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
11325 nmask = ix86_build_signbit_mask (mode, 0, 1);
11326 mask = ix86_build_signbit_mask (mode, 0, 0);
11328 if (mode == SFmode)
11329 copysign_insn = gen_copysignsf3_var;
11330 else if (mode == DFmode)
11331 copysign_insn = gen_copysigndf3_var;
11333 copysign_insn = gen_copysigntf3_var;
11335 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
11339 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
11340 be a constant, and so has already been expanded into a vector constant. */
11343 ix86_split_copysign_const (rtx operands[])
11345 enum machine_mode mode, vmode;
11346 rtx dest, op0, op1, mask, x;
11348 dest = operands[0];
11351 mask = operands[3];
11353 mode = GET_MODE (dest);
11354 vmode = GET_MODE (mask);
11356 dest = simplify_gen_subreg (vmode, dest, mode, 0);
11357 x = gen_rtx_AND (vmode, dest, mask);
11358 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11360 if (op0 != CONST0_RTX (vmode))
11362 x = gen_rtx_IOR (vmode, dest, op0);
11363 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11367 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
11368 so we have to do two masks. */
11371 ix86_split_copysign_var (rtx operands[])
11373 enum machine_mode mode, vmode;
11374 rtx dest, scratch, op0, op1, mask, nmask, x;
11376 dest = operands[0];
11377 scratch = operands[1];
11380 nmask = operands[4];
11381 mask = operands[5];
11383 mode = GET_MODE (dest);
11384 vmode = GET_MODE (mask);
11386 if (rtx_equal_p (op0, op1))
11388 /* Shouldn't happen often (it's useless, obviously), but when it does
11389 we'd generate incorrect code if we continue below. */
11390 emit_move_insn (dest, op0);
11394 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
11396 gcc_assert (REGNO (op1) == REGNO (scratch));
11398 x = gen_rtx_AND (vmode, scratch, mask);
11399 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11402 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11403 x = gen_rtx_NOT (vmode, dest);
11404 x = gen_rtx_AND (vmode, x, op0);
11405 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11409 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
11411 x = gen_rtx_AND (vmode, scratch, mask);
11413 else /* alternative 2,4 */
11415 gcc_assert (REGNO (mask) == REGNO (scratch));
11416 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
11417 x = gen_rtx_AND (vmode, scratch, op1);
11419 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11421 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
11423 dest = simplify_gen_subreg (vmode, op0, mode, 0);
11424 x = gen_rtx_AND (vmode, dest, nmask);
11426 else /* alternative 3,4 */
11428 gcc_assert (REGNO (nmask) == REGNO (dest));
11430 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11431 x = gen_rtx_AND (vmode, dest, op0);
11433 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11436 x = gen_rtx_IOR (vmode, dest, scratch);
11437 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11440 /* Return TRUE or FALSE depending on whether the first SET in INSN
11441 has source and destination with matching CC modes, and that the
11442 CC mode is at least as constrained as REQ_MODE. */
11445 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
11448 enum machine_mode set_mode;
11450 set = PATTERN (insn);
11451 if (GET_CODE (set) == PARALLEL)
11452 set = XVECEXP (set, 0, 0);
11453 gcc_assert (GET_CODE (set) == SET);
11454 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
11456 set_mode = GET_MODE (SET_DEST (set));
11460 if (req_mode != CCNOmode
11461 && (req_mode != CCmode
11462 || XEXP (SET_SRC (set), 1) != const0_rtx))
11466 if (req_mode == CCGCmode)
11470 if (req_mode == CCGOCmode || req_mode == CCNOmode)
11474 if (req_mode == CCZmode)
11481 gcc_unreachable ();
11484 return (GET_MODE (SET_SRC (set)) == set_mode);
11487 /* Generate insn patterns to do an integer compare of OPERANDS. */
11490 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
11492 enum machine_mode cmpmode;
11495 cmpmode = SELECT_CC_MODE (code, op0, op1);
11496 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
11498 /* This is very simple, but making the interface the same as in the
11499 FP case makes the rest of the code easier. */
11500 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
11501 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
11503 /* Return the test that should be put into the flags user, i.e.
11504 the bcc, scc, or cmov instruction. */
11505 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
11508 /* Figure out whether to use ordered or unordered fp comparisons.
11509 Return the appropriate mode to use. */
11512 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
11514 /* ??? In order to make all comparisons reversible, we do all comparisons
11515 non-trapping when compiling for IEEE. Once gcc is able to distinguish
11516 all forms trapping and nontrapping comparisons, we can make inequality
11517 comparisons trapping again, since it results in better code when using
11518 FCOM based compares. */
11519 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
11523 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
11525 enum machine_mode mode = GET_MODE (op0);
11527 if (SCALAR_FLOAT_MODE_P (mode))
11529 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11530 return ix86_fp_compare_mode (code);
11535 /* Only zero flag is needed. */
11536 case EQ: /* ZF=0 */
11537 case NE: /* ZF!=0 */
11539 /* Codes needing carry flag. */
11540 case GEU: /* CF=0 */
11541 case LTU: /* CF=1 */
11542 /* Detect overflow checks. They need just the carry flag. */
11543 if (GET_CODE (op0) == PLUS
11544 && rtx_equal_p (op1, XEXP (op0, 0)))
11548 case GTU: /* CF=0 & ZF=0 */
11549 case LEU: /* CF=1 | ZF=1 */
11550 /* Detect overflow checks. They need just the carry flag. */
11551 if (GET_CODE (op0) == MINUS
11552 && rtx_equal_p (op1, XEXP (op0, 0)))
11556 /* Codes possibly doable only with sign flag when
11557 comparing against zero. */
11558 case GE: /* SF=OF or SF=0 */
11559 case LT: /* SF<>OF or SF=1 */
11560 if (op1 == const0_rtx)
11563 /* For other cases Carry flag is not required. */
11565 /* Codes doable only with sign flag when comparing
11566 against zero, but we miss jump instruction for it
11567 so we need to use relational tests against overflow
11568 that thus needs to be zero. */
11569 case GT: /* ZF=0 & SF=OF */
11570 case LE: /* ZF=1 | SF<>OF */
11571 if (op1 == const0_rtx)
11575 /* strcmp pattern do (use flags) and combine may ask us for proper
11580 gcc_unreachable ();
11584 /* Return the fixed registers used for condition codes. */
11587 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
11594 /* If two condition code modes are compatible, return a condition code
11595 mode which is compatible with both. Otherwise, return
11598 static enum machine_mode
11599 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
11604 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
11607 if ((m1 == CCGCmode && m2 == CCGOCmode)
11608 || (m1 == CCGOCmode && m2 == CCGCmode))
11614 gcc_unreachable ();
11644 /* These are only compatible with themselves, which we already
11650 /* Split comparison code CODE into comparisons we can do using branch
11651 instructions. BYPASS_CODE is comparison code for branch that will
11652 branch around FIRST_CODE and SECOND_CODE. If some of branches
11653 is not required, set value to UNKNOWN.
11654 We never require more than two branches. */
11657 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
11658 enum rtx_code *first_code,
11659 enum rtx_code *second_code)
11661 *first_code = code;
11662 *bypass_code = UNKNOWN;
11663 *second_code = UNKNOWN;
11665 /* The fcomi comparison sets flags as follows:
11675 case GT: /* GTU - CF=0 & ZF=0 */
11676 case GE: /* GEU - CF=0 */
11677 case ORDERED: /* PF=0 */
11678 case UNORDERED: /* PF=1 */
11679 case UNEQ: /* EQ - ZF=1 */
11680 case UNLT: /* LTU - CF=1 */
11681 case UNLE: /* LEU - CF=1 | ZF=1 */
11682 case LTGT: /* EQ - ZF=0 */
11684 case LT: /* LTU - CF=1 - fails on unordered */
11685 *first_code = UNLT;
11686 *bypass_code = UNORDERED;
11688 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
11689 *first_code = UNLE;
11690 *bypass_code = UNORDERED;
11692 case EQ: /* EQ - ZF=1 - fails on unordered */
11693 *first_code = UNEQ;
11694 *bypass_code = UNORDERED;
11696 case NE: /* NE - ZF=0 - fails on unordered */
11697 *first_code = LTGT;
11698 *second_code = UNORDERED;
11700 case UNGE: /* GEU - CF=0 - fails on unordered */
11702 *second_code = UNORDERED;
11704 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
11706 *second_code = UNORDERED;
11709 gcc_unreachable ();
11711 if (!TARGET_IEEE_FP)
11713 *second_code = UNKNOWN;
11714 *bypass_code = UNKNOWN;
11718 /* Return cost of comparison done fcom + arithmetics operations on AX.
11719 All following functions do use number of instructions as a cost metrics.
11720 In future this should be tweaked to compute bytes for optimize_size and
11721 take into account performance of various instructions on various CPUs. */
11723 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
11725 if (!TARGET_IEEE_FP)
11727 /* The cost of code output by ix86_expand_fp_compare. */
11751 gcc_unreachable ();
11755 /* Return cost of comparison done using fcomi operation.
11756 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11758 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11760 enum rtx_code bypass_code, first_code, second_code;
11761 /* Return arbitrarily high cost when instruction is not supported - this
11762 prevents gcc from using it. */
11765 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11766 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11769 /* Return cost of comparison done using sahf operation.
11770 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11772 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11774 enum rtx_code bypass_code, first_code, second_code;
11775 /* Return arbitrarily high cost when instruction is not preferred - this
11776 avoids gcc from using it. */
11777 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11779 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11780 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11783 /* Compute cost of the comparison done using any method.
11784 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11786 ix86_fp_comparison_cost (enum rtx_code code)
11788 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11791 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11792 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11794 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11795 if (min > sahf_cost)
11797 if (min > fcomi_cost)
11802 /* Return true if we should use an FCOMI instruction for this
11806 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11808 enum rtx_code swapped_code = swap_condition (code);
11810 return ((ix86_fp_comparison_cost (code)
11811 == ix86_fp_comparison_fcomi_cost (code))
11812 || (ix86_fp_comparison_cost (swapped_code)
11813 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11816 /* Swap, force into registers, or otherwise massage the two operands
11817 to a fp comparison. The operands are updated in place; the new
11818 comparison code is returned. */
11820 static enum rtx_code
11821 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11823 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11824 rtx op0 = *pop0, op1 = *pop1;
11825 enum machine_mode op_mode = GET_MODE (op0);
11826 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11828 /* All of the unordered compare instructions only work on registers.
11829 The same is true of the fcomi compare instructions. The XFmode
11830 compare instructions require registers except when comparing
11831 against zero or when converting operand 1 from fixed point to
11835 && (fpcmp_mode == CCFPUmode
11836 || (op_mode == XFmode
11837 && ! (standard_80387_constant_p (op0) == 1
11838 || standard_80387_constant_p (op1) == 1)
11839 && GET_CODE (op1) != FLOAT)
11840 || ix86_use_fcomi_compare (code)))
11842 op0 = force_reg (op_mode, op0);
11843 op1 = force_reg (op_mode, op1);
11847 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11848 things around if they appear profitable, otherwise force op0
11849 into a register. */
11851 if (standard_80387_constant_p (op0) == 0
11853 && ! (standard_80387_constant_p (op1) == 0
11857 tmp = op0, op0 = op1, op1 = tmp;
11858 code = swap_condition (code);
11862 op0 = force_reg (op_mode, op0);
11864 if (CONSTANT_P (op1))
11866 int tmp = standard_80387_constant_p (op1);
11868 op1 = validize_mem (force_const_mem (op_mode, op1));
11872 op1 = force_reg (op_mode, op1);
11875 op1 = force_reg (op_mode, op1);
11879 /* Try to rearrange the comparison to make it cheaper. */
11880 if (ix86_fp_comparison_cost (code)
11881 > ix86_fp_comparison_cost (swap_condition (code))
11882 && (REG_P (op1) || can_create_pseudo_p ()))
11885 tmp = op0, op0 = op1, op1 = tmp;
11886 code = swap_condition (code);
11888 op0 = force_reg (op_mode, op0);
11896 /* Convert comparison codes we use to represent FP comparison to integer
11897 code that will result in proper branch. Return UNKNOWN if no such code
11901 ix86_fp_compare_code_to_integer (enum rtx_code code)
11930 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11933 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
11934 rtx *second_test, rtx *bypass_test)
11936 enum machine_mode fpcmp_mode, intcmp_mode;
11938 int cost = ix86_fp_comparison_cost (code);
11939 enum rtx_code bypass_code, first_code, second_code;
11941 fpcmp_mode = ix86_fp_compare_mode (code);
11942 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
11945 *second_test = NULL_RTX;
11947 *bypass_test = NULL_RTX;
11949 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11951 /* Do fcomi/sahf based test when profitable. */
11952 if (ix86_fp_comparison_arithmetics_cost (code) > cost
11953 && (bypass_code == UNKNOWN || bypass_test)
11954 && (second_code == UNKNOWN || second_test))
11956 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11957 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
11963 gcc_assert (TARGET_SAHF);
11966 scratch = gen_reg_rtx (HImode);
11967 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
11969 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
11972 /* The FP codes work out to act like unsigned. */
11973 intcmp_mode = fpcmp_mode;
11975 if (bypass_code != UNKNOWN)
11976 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
11977 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11979 if (second_code != UNKNOWN)
11980 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
11981 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11986 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11987 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11988 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11990 scratch = gen_reg_rtx (HImode);
11991 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11993 /* In the unordered case, we have to check C2 for NaN's, which
11994 doesn't happen to work out to anything nice combination-wise.
11995 So do some bit twiddling on the value we've got in AH to come
11996 up with an appropriate set of condition codes. */
11998 intcmp_mode = CCNOmode;
12003 if (code == GT || !TARGET_IEEE_FP)
12005 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
12010 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12011 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
12012 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
12013 intcmp_mode = CCmode;
12019 if (code == LT && TARGET_IEEE_FP)
12021 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12022 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
12023 intcmp_mode = CCmode;
12028 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
12034 if (code == GE || !TARGET_IEEE_FP)
12036 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
12041 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12042 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
12049 if (code == LE && TARGET_IEEE_FP)
12051 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12052 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
12053 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
12054 intcmp_mode = CCmode;
12059 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
12065 if (code == EQ && TARGET_IEEE_FP)
12067 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12068 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
12069 intcmp_mode = CCmode;
12074 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
12081 if (code == NE && TARGET_IEEE_FP)
12083 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12084 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
12090 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
12096 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
12100 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
12105 gcc_unreachable ();
12109 /* Return the test that should be put into the flags user, i.e.
12110 the bcc, scc, or cmov instruction. */
12111 return gen_rtx_fmt_ee (code, VOIDmode,
12112 gen_rtx_REG (intcmp_mode, FLAGS_REG),
12117 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
12120 op0 = ix86_compare_op0;
12121 op1 = ix86_compare_op1;
12124 *second_test = NULL_RTX;
12126 *bypass_test = NULL_RTX;
12128 if (ix86_compare_emitted)
12130 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
12131 ix86_compare_emitted = NULL_RTX;
12133 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
12135 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
12136 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12137 second_test, bypass_test);
12140 ret = ix86_expand_int_compare (code, op0, op1);
12145 /* Return true if the CODE will result in nontrivial jump sequence. */
12147 ix86_fp_jump_nontrivial_p (enum rtx_code code)
12149 enum rtx_code bypass_code, first_code, second_code;
12152 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12153 return bypass_code != UNKNOWN || second_code != UNKNOWN;
12157 ix86_expand_branch (enum rtx_code code, rtx label)
12161 /* If we have emitted a compare insn, go straight to simple.
12162 ix86_expand_compare won't emit anything if ix86_compare_emitted
12164 if (ix86_compare_emitted)
12167 switch (GET_MODE (ix86_compare_op0))
12173 tmp = ix86_expand_compare (code, NULL, NULL);
12174 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12175 gen_rtx_LABEL_REF (VOIDmode, label),
12177 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12186 enum rtx_code bypass_code, first_code, second_code;
12188 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
12189 &ix86_compare_op1);
12191 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12193 /* Check whether we will use the natural sequence with one jump. If
12194 so, we can expand jump early. Otherwise delay expansion by
12195 creating compound insn to not confuse optimizers. */
12196 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
12198 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
12199 gen_rtx_LABEL_REF (VOIDmode, label),
12200 pc_rtx, NULL_RTX, NULL_RTX);
12204 tmp = gen_rtx_fmt_ee (code, VOIDmode,
12205 ix86_compare_op0, ix86_compare_op1);
12206 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12207 gen_rtx_LABEL_REF (VOIDmode, label),
12209 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
12211 use_fcomi = ix86_use_fcomi_compare (code);
12212 vec = rtvec_alloc (3 + !use_fcomi);
12213 RTVEC_ELT (vec, 0) = tmp;
12215 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
12217 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
12220 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
12222 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12231 /* Expand DImode branch into multiple compare+branch. */
12233 rtx lo[2], hi[2], label2;
12234 enum rtx_code code1, code2, code3;
12235 enum machine_mode submode;
12237 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
12239 tmp = ix86_compare_op0;
12240 ix86_compare_op0 = ix86_compare_op1;
12241 ix86_compare_op1 = tmp;
12242 code = swap_condition (code);
12244 if (GET_MODE (ix86_compare_op0) == DImode)
12246 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
12247 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
12252 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
12253 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
12257 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
12258 avoid two branches. This costs one extra insn, so disable when
12259 optimizing for size. */
12261 if ((code == EQ || code == NE)
12263 || hi[1] == const0_rtx || lo[1] == const0_rtx))
12268 if (hi[1] != const0_rtx)
12269 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
12270 NULL_RTX, 0, OPTAB_WIDEN);
12273 if (lo[1] != const0_rtx)
12274 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
12275 NULL_RTX, 0, OPTAB_WIDEN);
12277 tmp = expand_binop (submode, ior_optab, xor1, xor0,
12278 NULL_RTX, 0, OPTAB_WIDEN);
12280 ix86_compare_op0 = tmp;
12281 ix86_compare_op1 = const0_rtx;
12282 ix86_expand_branch (code, label);
12286 /* Otherwise, if we are doing less-than or greater-or-equal-than,
12287 op1 is a constant and the low word is zero, then we can just
12288 examine the high word. Similarly for low word -1 and
12289 less-or-equal-than or greater-than. */
12291 if (CONST_INT_P (hi[1]))
12294 case LT: case LTU: case GE: case GEU:
12295 if (lo[1] == const0_rtx)
12297 ix86_compare_op0 = hi[0];
12298 ix86_compare_op1 = hi[1];
12299 ix86_expand_branch (code, label);
12303 case LE: case LEU: case GT: case GTU:
12304 if (lo[1] == constm1_rtx)
12306 ix86_compare_op0 = hi[0];
12307 ix86_compare_op1 = hi[1];
12308 ix86_expand_branch (code, label);
12316 /* Otherwise, we need two or three jumps. */
12318 label2 = gen_label_rtx ();
12321 code2 = swap_condition (code);
12322 code3 = unsigned_condition (code);
12326 case LT: case GT: case LTU: case GTU:
12329 case LE: code1 = LT; code2 = GT; break;
12330 case GE: code1 = GT; code2 = LT; break;
12331 case LEU: code1 = LTU; code2 = GTU; break;
12332 case GEU: code1 = GTU; code2 = LTU; break;
12334 case EQ: code1 = UNKNOWN; code2 = NE; break;
12335 case NE: code2 = UNKNOWN; break;
12338 gcc_unreachable ();
12343 * if (hi(a) < hi(b)) goto true;
12344 * if (hi(a) > hi(b)) goto false;
12345 * if (lo(a) < lo(b)) goto true;
12349 ix86_compare_op0 = hi[0];
12350 ix86_compare_op1 = hi[1];
12352 if (code1 != UNKNOWN)
12353 ix86_expand_branch (code1, label);
12354 if (code2 != UNKNOWN)
12355 ix86_expand_branch (code2, label2);
12357 ix86_compare_op0 = lo[0];
12358 ix86_compare_op1 = lo[1];
12359 ix86_expand_branch (code3, label);
12361 if (code2 != UNKNOWN)
12362 emit_label (label2);
12367 gcc_unreachable ();
12371 /* Split branch based on floating point condition. */
12373 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
12374 rtx target1, rtx target2, rtx tmp, rtx pushed)
12376 rtx second, bypass;
12377 rtx label = NULL_RTX;
12379 int bypass_probability = -1, second_probability = -1, probability = -1;
12382 if (target2 != pc_rtx)
12385 code = reverse_condition_maybe_unordered (code);
12390 condition = ix86_expand_fp_compare (code, op1, op2,
12391 tmp, &second, &bypass);
12393 /* Remove pushed operand from stack. */
12395 ix86_free_from_memory (GET_MODE (pushed));
12397 if (split_branch_probability >= 0)
12399 /* Distribute the probabilities across the jumps.
12400 Assume the BYPASS and SECOND to be always test
12402 probability = split_branch_probability;
12404 /* Value of 1 is low enough to make no need for probability
12405 to be updated. Later we may run some experiments and see
12406 if unordered values are more frequent in practice. */
12408 bypass_probability = 1;
12410 second_probability = 1;
12412 if (bypass != NULL_RTX)
12414 label = gen_label_rtx ();
12415 i = emit_jump_insn (gen_rtx_SET
12417 gen_rtx_IF_THEN_ELSE (VOIDmode,
12419 gen_rtx_LABEL_REF (VOIDmode,
12422 if (bypass_probability >= 0)
12424 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12425 GEN_INT (bypass_probability),
12428 i = emit_jump_insn (gen_rtx_SET
12430 gen_rtx_IF_THEN_ELSE (VOIDmode,
12431 condition, target1, target2)));
12432 if (probability >= 0)
12434 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12435 GEN_INT (probability),
12437 if (second != NULL_RTX)
12439 i = emit_jump_insn (gen_rtx_SET
12441 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
12443 if (second_probability >= 0)
12445 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12446 GEN_INT (second_probability),
12449 if (label != NULL_RTX)
12450 emit_label (label);
12454 ix86_expand_setcc (enum rtx_code code, rtx dest)
12456 rtx ret, tmp, tmpreg, equiv;
12457 rtx second_test, bypass_test;
12459 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
12460 return 0; /* FAIL */
12462 gcc_assert (GET_MODE (dest) == QImode);
12464 ret = ix86_expand_compare (code, &second_test, &bypass_test);
12465 PUT_MODE (ret, QImode);
12470 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
12471 if (bypass_test || second_test)
12473 rtx test = second_test;
12475 rtx tmp2 = gen_reg_rtx (QImode);
12478 gcc_assert (!second_test);
12479 test = bypass_test;
12481 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
12483 PUT_MODE (test, QImode);
12484 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
12487 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
12489 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
12492 /* Attach a REG_EQUAL note describing the comparison result. */
12493 if (ix86_compare_op0 && ix86_compare_op1)
12495 equiv = simplify_gen_relational (code, QImode,
12496 GET_MODE (ix86_compare_op0),
12497 ix86_compare_op0, ix86_compare_op1);
12498 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
12501 return 1; /* DONE */
12504 /* Expand comparison setting or clearing carry flag. Return true when
12505 successful and set pop for the operation. */
12507 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
12509 enum machine_mode mode =
12510 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
12512 /* Do not handle DImode compares that go through special path. */
12513 if (mode == (TARGET_64BIT ? TImode : DImode))
12516 if (SCALAR_FLOAT_MODE_P (mode))
12518 rtx second_test = NULL, bypass_test = NULL;
12519 rtx compare_op, compare_seq;
12521 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
12523 /* Shortcut: following common codes never translate
12524 into carry flag compares. */
12525 if (code == EQ || code == NE || code == UNEQ || code == LTGT
12526 || code == ORDERED || code == UNORDERED)
12529 /* These comparisons require zero flag; swap operands so they won't. */
12530 if ((code == GT || code == UNLE || code == LE || code == UNGT)
12531 && !TARGET_IEEE_FP)
12536 code = swap_condition (code);
12539 /* Try to expand the comparison and verify that we end up with
12540 carry flag based comparison. This fails to be true only when
12541 we decide to expand comparison using arithmetic that is not
12542 too common scenario. */
12544 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12545 &second_test, &bypass_test);
12546 compare_seq = get_insns ();
12549 if (second_test || bypass_test)
12552 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12553 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12554 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
12556 code = GET_CODE (compare_op);
12558 if (code != LTU && code != GEU)
12561 emit_insn (compare_seq);
12566 if (!INTEGRAL_MODE_P (mode))
12575 /* Convert a==0 into (unsigned)a<1. */
12578 if (op1 != const0_rtx)
12581 code = (code == EQ ? LTU : GEU);
12584 /* Convert a>b into b<a or a>=b-1. */
12587 if (CONST_INT_P (op1))
12589 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
12590 /* Bail out on overflow. We still can swap operands but that
12591 would force loading of the constant into register. */
12592 if (op1 == const0_rtx
12593 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
12595 code = (code == GTU ? GEU : LTU);
12602 code = (code == GTU ? LTU : GEU);
12606 /* Convert a>=0 into (unsigned)a<0x80000000. */
12609 if (mode == DImode || op1 != const0_rtx)
12611 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12612 code = (code == LT ? GEU : LTU);
12616 if (mode == DImode || op1 != constm1_rtx)
12618 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12619 code = (code == LE ? GEU : LTU);
12625 /* Swapping operands may cause constant to appear as first operand. */
12626 if (!nonimmediate_operand (op0, VOIDmode))
12628 if (!can_create_pseudo_p ())
12630 op0 = force_reg (mode, op0);
12632 ix86_compare_op0 = op0;
12633 ix86_compare_op1 = op1;
12634 *pop = ix86_expand_compare (code, NULL, NULL);
12635 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
12640 ix86_expand_int_movcc (rtx operands[])
12642 enum rtx_code code = GET_CODE (operands[1]), compare_code;
12643 rtx compare_seq, compare_op;
12644 rtx second_test, bypass_test;
12645 enum machine_mode mode = GET_MODE (operands[0]);
12646 bool sign_bit_compare_p = false;;
12649 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12650 compare_seq = get_insns ();
12653 compare_code = GET_CODE (compare_op);
12655 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
12656 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
12657 sign_bit_compare_p = true;
12659 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
12660 HImode insns, we'd be swallowed in word prefix ops. */
12662 if ((mode != HImode || TARGET_FAST_PREFIX)
12663 && (mode != (TARGET_64BIT ? TImode : DImode))
12664 && CONST_INT_P (operands[2])
12665 && CONST_INT_P (operands[3]))
12667 rtx out = operands[0];
12668 HOST_WIDE_INT ct = INTVAL (operands[2]);
12669 HOST_WIDE_INT cf = INTVAL (operands[3]);
12670 HOST_WIDE_INT diff;
12673 /* Sign bit compares are better done using shifts than we do by using
12675 if (sign_bit_compare_p
12676 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12677 ix86_compare_op1, &compare_op))
12679 /* Detect overlap between destination and compare sources. */
12682 if (!sign_bit_compare_p)
12684 bool fpcmp = false;
12686 compare_code = GET_CODE (compare_op);
12688 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12689 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12692 compare_code = ix86_fp_compare_code_to_integer (compare_code);
12695 /* To simplify rest of code, restrict to the GEU case. */
12696 if (compare_code == LTU)
12698 HOST_WIDE_INT tmp = ct;
12701 compare_code = reverse_condition (compare_code);
12702 code = reverse_condition (code);
12707 PUT_CODE (compare_op,
12708 reverse_condition_maybe_unordered
12709 (GET_CODE (compare_op)));
12711 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12715 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
12716 || reg_overlap_mentioned_p (out, ix86_compare_op1))
12717 tmp = gen_reg_rtx (mode);
12719 if (mode == DImode)
12720 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
12722 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
12726 if (code == GT || code == GE)
12727 code = reverse_condition (code);
12730 HOST_WIDE_INT tmp = ct;
12735 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
12736 ix86_compare_op1, VOIDmode, 0, -1);
12749 tmp = expand_simple_binop (mode, PLUS,
12751 copy_rtx (tmp), 1, OPTAB_DIRECT);
12762 tmp = expand_simple_binop (mode, IOR,
12764 copy_rtx (tmp), 1, OPTAB_DIRECT);
12766 else if (diff == -1 && ct)
12776 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12778 tmp = expand_simple_binop (mode, PLUS,
12779 copy_rtx (tmp), GEN_INT (cf),
12780 copy_rtx (tmp), 1, OPTAB_DIRECT);
12788 * andl cf - ct, dest
12798 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12801 tmp = expand_simple_binop (mode, AND,
12803 gen_int_mode (cf - ct, mode),
12804 copy_rtx (tmp), 1, OPTAB_DIRECT);
12806 tmp = expand_simple_binop (mode, PLUS,
12807 copy_rtx (tmp), GEN_INT (ct),
12808 copy_rtx (tmp), 1, OPTAB_DIRECT);
12811 if (!rtx_equal_p (tmp, out))
12812 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12814 return 1; /* DONE */
12819 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12822 tmp = ct, ct = cf, cf = tmp;
12825 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12827 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12829 /* We may be reversing unordered compare to normal compare, that
12830 is not valid in general (we may convert non-trapping condition
12831 to trapping one), however on i386 we currently emit all
12832 comparisons unordered. */
12833 compare_code = reverse_condition_maybe_unordered (compare_code);
12834 code = reverse_condition_maybe_unordered (code);
12838 compare_code = reverse_condition (compare_code);
12839 code = reverse_condition (code);
12843 compare_code = UNKNOWN;
12844 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12845 && CONST_INT_P (ix86_compare_op1))
12847 if (ix86_compare_op1 == const0_rtx
12848 && (code == LT || code == GE))
12849 compare_code = code;
12850 else if (ix86_compare_op1 == constm1_rtx)
12854 else if (code == GT)
12859 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12860 if (compare_code != UNKNOWN
12861 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12862 && (cf == -1 || ct == -1))
12864 /* If lea code below could be used, only optimize
12865 if it results in a 2 insn sequence. */
12867 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12868 || diff == 3 || diff == 5 || diff == 9)
12869 || (compare_code == LT && ct == -1)
12870 || (compare_code == GE && cf == -1))
12873 * notl op1 (if necessary)
12881 code = reverse_condition (code);
12884 out = emit_store_flag (out, code, ix86_compare_op0,
12885 ix86_compare_op1, VOIDmode, 0, -1);
12887 out = expand_simple_binop (mode, IOR,
12889 out, 1, OPTAB_DIRECT);
12890 if (out != operands[0])
12891 emit_move_insn (operands[0], out);
12893 return 1; /* DONE */
12898 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
12899 || diff == 3 || diff == 5 || diff == 9)
12900 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
12902 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
12908 * lea cf(dest*(ct-cf)),dest
12912 * This also catches the degenerate setcc-only case.
12918 out = emit_store_flag (out, code, ix86_compare_op0,
12919 ix86_compare_op1, VOIDmode, 0, 1);
12922 /* On x86_64 the lea instruction operates on Pmode, so we need
12923 to get arithmetics done in proper mode to match. */
12925 tmp = copy_rtx (out);
12929 out1 = copy_rtx (out);
12930 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
12934 tmp = gen_rtx_PLUS (mode, tmp, out1);
12940 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
12943 if (!rtx_equal_p (tmp, out))
12946 out = force_operand (tmp, copy_rtx (out));
12948 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
12950 if (!rtx_equal_p (out, operands[0]))
12951 emit_move_insn (operands[0], copy_rtx (out));
12953 return 1; /* DONE */
12957 * General case: Jumpful:
12958 * xorl dest,dest cmpl op1, op2
12959 * cmpl op1, op2 movl ct, dest
12960 * setcc dest jcc 1f
12961 * decl dest movl cf, dest
12962 * andl (cf-ct),dest 1:
12965 * Size 20. Size 14.
12967 * This is reasonably steep, but branch mispredict costs are
12968 * high on modern cpus, so consider failing only if optimizing
12972 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12973 && BRANCH_COST >= 2)
12977 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12982 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12984 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12986 /* We may be reversing unordered compare to normal compare,
12987 that is not valid in general (we may convert non-trapping
12988 condition to trapping one), however on i386 we currently
12989 emit all comparisons unordered. */
12990 code = reverse_condition_maybe_unordered (code);
12994 code = reverse_condition (code);
12995 if (compare_code != UNKNOWN)
12996 compare_code = reverse_condition (compare_code);
13000 if (compare_code != UNKNOWN)
13002 /* notl op1 (if needed)
13007 For x < 0 (resp. x <= -1) there will be no notl,
13008 so if possible swap the constants to get rid of the
13010 True/false will be -1/0 while code below (store flag
13011 followed by decrement) is 0/-1, so the constants need
13012 to be exchanged once more. */
13014 if (compare_code == GE || !cf)
13016 code = reverse_condition (code);
13021 HOST_WIDE_INT tmp = cf;
13026 out = emit_store_flag (out, code, ix86_compare_op0,
13027 ix86_compare_op1, VOIDmode, 0, -1);
13031 out = emit_store_flag (out, code, ix86_compare_op0,
13032 ix86_compare_op1, VOIDmode, 0, 1);
13034 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
13035 copy_rtx (out), 1, OPTAB_DIRECT);
13038 out = expand_simple_binop (mode, AND, copy_rtx (out),
13039 gen_int_mode (cf - ct, mode),
13040 copy_rtx (out), 1, OPTAB_DIRECT);
13042 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
13043 copy_rtx (out), 1, OPTAB_DIRECT);
13044 if (!rtx_equal_p (out, operands[0]))
13045 emit_move_insn (operands[0], copy_rtx (out));
13047 return 1; /* DONE */
13051 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
13053 /* Try a few things more with specific constants and a variable. */
13056 rtx var, orig_out, out, tmp;
13058 if (BRANCH_COST <= 2)
13059 return 0; /* FAIL */
13061 /* If one of the two operands is an interesting constant, load a
13062 constant with the above and mask it in with a logical operation. */
13064 if (CONST_INT_P (operands[2]))
13067 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
13068 operands[3] = constm1_rtx, op = and_optab;
13069 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
13070 operands[3] = const0_rtx, op = ior_optab;
13072 return 0; /* FAIL */
13074 else if (CONST_INT_P (operands[3]))
13077 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
13078 operands[2] = constm1_rtx, op = and_optab;
13079 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
13080 operands[2] = const0_rtx, op = ior_optab;
13082 return 0; /* FAIL */
13085 return 0; /* FAIL */
13087 orig_out = operands[0];
13088 tmp = gen_reg_rtx (mode);
13091 /* Recurse to get the constant loaded. */
13092 if (ix86_expand_int_movcc (operands) == 0)
13093 return 0; /* FAIL */
13095 /* Mask in the interesting variable. */
13096 out = expand_binop (mode, op, var, tmp, orig_out, 0,
13098 if (!rtx_equal_p (out, orig_out))
13099 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
13101 return 1; /* DONE */
13105 * For comparison with above,
13115 if (! nonimmediate_operand (operands[2], mode))
13116 operands[2] = force_reg (mode, operands[2]);
13117 if (! nonimmediate_operand (operands[3], mode))
13118 operands[3] = force_reg (mode, operands[3]);
13120 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13122 rtx tmp = gen_reg_rtx (mode);
13123 emit_move_insn (tmp, operands[3]);
13126 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13128 rtx tmp = gen_reg_rtx (mode);
13129 emit_move_insn (tmp, operands[2]);
13133 if (! register_operand (operands[2], VOIDmode)
13135 || ! register_operand (operands[3], VOIDmode)))
13136 operands[2] = force_reg (mode, operands[2]);
13139 && ! register_operand (operands[3], VOIDmode))
13140 operands[3] = force_reg (mode, operands[3]);
13142 emit_insn (compare_seq);
13143 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13144 gen_rtx_IF_THEN_ELSE (mode,
13145 compare_op, operands[2],
13148 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13149 gen_rtx_IF_THEN_ELSE (mode,
13151 copy_rtx (operands[3]),
13152 copy_rtx (operands[0]))));
13154 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13155 gen_rtx_IF_THEN_ELSE (mode,
13157 copy_rtx (operands[2]),
13158 copy_rtx (operands[0]))));
13160 return 1; /* DONE */
13163 /* Swap, force into registers, or otherwise massage the two operands
13164 to an sse comparison with a mask result. Thus we differ a bit from
13165 ix86_prepare_fp_compare_args which expects to produce a flags result.
13167 The DEST operand exists to help determine whether to commute commutative
13168 operators. The POP0/POP1 operands are updated in place. The new
13169 comparison code is returned, or UNKNOWN if not implementable. */
13171 static enum rtx_code
13172 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
13173 rtx *pop0, rtx *pop1)
13181 /* We have no LTGT as an operator. We could implement it with
13182 NE & ORDERED, but this requires an extra temporary. It's
13183 not clear that it's worth it. */
13190 /* These are supported directly. */
13197 /* For commutative operators, try to canonicalize the destination
13198 operand to be first in the comparison - this helps reload to
13199 avoid extra moves. */
13200 if (!dest || !rtx_equal_p (dest, *pop1))
13208 /* These are not supported directly. Swap the comparison operands
13209 to transform into something that is supported. */
13213 code = swap_condition (code);
13217 gcc_unreachable ();
13223 /* Detect conditional moves that exactly match min/max operational
13224 semantics. Note that this is IEEE safe, as long as we don't
13225 interchange the operands.
13227 Returns FALSE if this conditional move doesn't match a MIN/MAX,
13228 and TRUE if the operation is successful and instructions are emitted. */
13231 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
13232 rtx cmp_op1, rtx if_true, rtx if_false)
13234 enum machine_mode mode;
13240 else if (code == UNGE)
13243 if_true = if_false;
13249 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
13251 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
13256 mode = GET_MODE (dest);
13258 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
13259 but MODE may be a vector mode and thus not appropriate. */
13260 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
13262 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
13265 if_true = force_reg (mode, if_true);
13266 v = gen_rtvec (2, if_true, if_false);
13267 tmp = gen_rtx_UNSPEC (mode, v, u);
13271 code = is_min ? SMIN : SMAX;
13272 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
13275 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
13279 /* Expand an sse vector comparison. Return the register with the result. */
13282 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
13283 rtx op_true, rtx op_false)
13285 enum machine_mode mode = GET_MODE (dest);
13288 cmp_op0 = force_reg (mode, cmp_op0);
13289 if (!nonimmediate_operand (cmp_op1, mode))
13290 cmp_op1 = force_reg (mode, cmp_op1);
13293 || reg_overlap_mentioned_p (dest, op_true)
13294 || reg_overlap_mentioned_p (dest, op_false))
13295 dest = gen_reg_rtx (mode);
13297 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
13298 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13303 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
13304 operations. This is used for both scalar and vector conditional moves. */
13307 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
13309 enum machine_mode mode = GET_MODE (dest);
13312 if (op_false == CONST0_RTX (mode))
13314 op_true = force_reg (mode, op_true);
13315 x = gen_rtx_AND (mode, cmp, op_true);
13316 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13318 else if (op_true == CONST0_RTX (mode))
13320 op_false = force_reg (mode, op_false);
13321 x = gen_rtx_NOT (mode, cmp);
13322 x = gen_rtx_AND (mode, x, op_false);
13323 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13325 else if (TARGET_SSE5)
13327 rtx pcmov = gen_rtx_SET (mode, dest,
13328 gen_rtx_IF_THEN_ELSE (mode, cmp,
13335 op_true = force_reg (mode, op_true);
13336 op_false = force_reg (mode, op_false);
13338 t2 = gen_reg_rtx (mode);
13340 t3 = gen_reg_rtx (mode);
13344 x = gen_rtx_AND (mode, op_true, cmp);
13345 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
13347 x = gen_rtx_NOT (mode, cmp);
13348 x = gen_rtx_AND (mode, x, op_false);
13349 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
13351 x = gen_rtx_IOR (mode, t3, t2);
13352 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13356 /* Expand a floating-point conditional move. Return true if successful. */
13359 ix86_expand_fp_movcc (rtx operands[])
13361 enum machine_mode mode = GET_MODE (operands[0]);
13362 enum rtx_code code = GET_CODE (operands[1]);
13363 rtx tmp, compare_op, second_test, bypass_test;
13365 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
13367 enum machine_mode cmode;
13369 /* Since we've no cmove for sse registers, don't force bad register
13370 allocation just to gain access to it. Deny movcc when the
13371 comparison mode doesn't match the move mode. */
13372 cmode = GET_MODE (ix86_compare_op0);
13373 if (cmode == VOIDmode)
13374 cmode = GET_MODE (ix86_compare_op1);
13378 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13380 &ix86_compare_op1);
13381 if (code == UNKNOWN)
13384 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
13385 ix86_compare_op1, operands[2],
13389 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
13390 ix86_compare_op1, operands[2], operands[3]);
13391 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
13395 /* The floating point conditional move instructions don't directly
13396 support conditions resulting from a signed integer comparison. */
13398 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13400 /* The floating point conditional move instructions don't directly
13401 support signed integer comparisons. */
13403 if (!fcmov_comparison_operator (compare_op, VOIDmode))
13405 gcc_assert (!second_test && !bypass_test);
13406 tmp = gen_reg_rtx (QImode);
13407 ix86_expand_setcc (code, tmp);
13409 ix86_compare_op0 = tmp;
13410 ix86_compare_op1 = const0_rtx;
13411 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13413 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13415 tmp = gen_reg_rtx (mode);
13416 emit_move_insn (tmp, operands[3]);
13419 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13421 tmp = gen_reg_rtx (mode);
13422 emit_move_insn (tmp, operands[2]);
13426 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13427 gen_rtx_IF_THEN_ELSE (mode, compare_op,
13428 operands[2], operands[3])));
13430 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13431 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
13432 operands[3], operands[0])));
13434 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13435 gen_rtx_IF_THEN_ELSE (mode, second_test,
13436 operands[2], operands[0])));
13441 /* Expand a floating-point vector conditional move; a vcond operation
13442 rather than a movcc operation. */
13445 ix86_expand_fp_vcond (rtx operands[])
13447 enum rtx_code code = GET_CODE (operands[3]);
13450 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13451 &operands[4], &operands[5]);
13452 if (code == UNKNOWN)
13455 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
13456 operands[5], operands[1], operands[2]))
13459 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
13460 operands[1], operands[2]);
13461 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
13465 /* Expand a signed/unsigned integral vector conditional move. */
13468 ix86_expand_int_vcond (rtx operands[])
13470 enum machine_mode mode = GET_MODE (operands[0]);
13471 enum rtx_code code = GET_CODE (operands[3]);
13472 bool negate = false;
13475 cop0 = operands[4];
13476 cop1 = operands[5];
13478 /* SSE5 supports all of the comparisons on all vector int types. */
13481 /* Canonicalize the comparison to EQ, GT, GTU. */
13492 code = reverse_condition (code);
13498 code = reverse_condition (code);
13504 code = swap_condition (code);
13505 x = cop0, cop0 = cop1, cop1 = x;
13509 gcc_unreachable ();
13512 /* Only SSE4.1/SSE4.2 supports V2DImode. */
13513 if (mode == V2DImode)
13518 /* SSE4.1 supports EQ. */
13519 if (!TARGET_SSE4_1)
13525 /* SSE4.2 supports GT/GTU. */
13526 if (!TARGET_SSE4_2)
13531 gcc_unreachable ();
13535 /* Unsigned parallel compare is not supported by the hardware. Play some
13536 tricks to turn this into a signed comparison against 0. */
13539 cop0 = force_reg (mode, cop0);
13548 /* Perform a parallel modulo subtraction. */
13549 t1 = gen_reg_rtx (mode);
13550 emit_insn ((mode == V4SImode
13552 : gen_subv2di3) (t1, cop0, cop1));
13554 /* Extract the original sign bit of op0. */
13555 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
13557 t2 = gen_reg_rtx (mode);
13558 emit_insn ((mode == V4SImode
13560 : gen_andv2di3) (t2, cop0, mask));
13562 /* XOR it back into the result of the subtraction. This results
13563 in the sign bit set iff we saw unsigned underflow. */
13564 x = gen_reg_rtx (mode);
13565 emit_insn ((mode == V4SImode
13567 : gen_xorv2di3) (x, t1, t2));
13575 /* Perform a parallel unsigned saturating subtraction. */
13576 x = gen_reg_rtx (mode);
13577 emit_insn (gen_rtx_SET (VOIDmode, x,
13578 gen_rtx_US_MINUS (mode, cop0, cop1)));
13585 gcc_unreachable ();
13589 cop1 = CONST0_RTX (mode);
13593 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
13594 operands[1+negate], operands[2-negate]);
13596 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
13597 operands[2-negate]);
13601 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
13602 true if we should do zero extension, else sign extension. HIGH_P is
13603 true if we want the N/2 high elements, else the low elements. */
13606 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13608 enum machine_mode imode = GET_MODE (operands[1]);
13609 rtx (*unpack)(rtx, rtx, rtx);
13616 unpack = gen_vec_interleave_highv16qi;
13618 unpack = gen_vec_interleave_lowv16qi;
13622 unpack = gen_vec_interleave_highv8hi;
13624 unpack = gen_vec_interleave_lowv8hi;
13628 unpack = gen_vec_interleave_highv4si;
13630 unpack = gen_vec_interleave_lowv4si;
13633 gcc_unreachable ();
13636 dest = gen_lowpart (imode, operands[0]);
13639 se = force_reg (imode, CONST0_RTX (imode));
13641 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
13642 operands[1], pc_rtx, pc_rtx);
13644 emit_insn (unpack (dest, operands[1], se));
13647 /* This function performs the same task as ix86_expand_sse_unpack,
13648 but with SSE4.1 instructions. */
13651 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13653 enum machine_mode imode = GET_MODE (operands[1]);
13654 rtx (*unpack)(rtx, rtx);
13661 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
13663 unpack = gen_sse4_1_extendv8qiv8hi2;
13667 unpack = gen_sse4_1_zero_extendv4hiv4si2;
13669 unpack = gen_sse4_1_extendv4hiv4si2;
13673 unpack = gen_sse4_1_zero_extendv2siv2di2;
13675 unpack = gen_sse4_1_extendv2siv2di2;
13678 gcc_unreachable ();
13681 dest = operands[0];
13684 /* Shift higher 8 bytes to lower 8 bytes. */
13685 src = gen_reg_rtx (imode);
13686 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
13687 gen_lowpart (TImode, operands[1]),
13693 emit_insn (unpack (dest, src));
13696 /* This function performs the same task as ix86_expand_sse_unpack,
13697 but with sse5 instructions. */
13700 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13702 enum machine_mode imode = GET_MODE (operands[1]);
13703 int pperm_bytes[16];
13705 int h = (high_p) ? 8 : 0;
13708 rtvec v = rtvec_alloc (16);
13711 rtx op0 = operands[0], op1 = operands[1];
13716 vs = rtvec_alloc (8);
13717 h2 = (high_p) ? 8 : 0;
13718 for (i = 0; i < 8; i++)
13720 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
13721 pperm_bytes[2*i+1] = ((unsigned_p)
13723 : PPERM_SIGN | PPERM_SRC2 | i | h);
13726 for (i = 0; i < 16; i++)
13727 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13729 for (i = 0; i < 8; i++)
13730 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13732 p = gen_rtx_PARALLEL (VOIDmode, vs);
13733 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13735 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
13737 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
13741 vs = rtvec_alloc (4);
13742 h2 = (high_p) ? 4 : 0;
13743 for (i = 0; i < 4; i++)
13745 sign_extend = ((unsigned_p)
13747 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
13748 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
13749 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
13750 pperm_bytes[4*i+2] = sign_extend;
13751 pperm_bytes[4*i+3] = sign_extend;
13754 for (i = 0; i < 16; i++)
13755 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13757 for (i = 0; i < 4; i++)
13758 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13760 p = gen_rtx_PARALLEL (VOIDmode, vs);
13761 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13763 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
13765 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
13769 vs = rtvec_alloc (2);
13770 h2 = (high_p) ? 2 : 0;
13771 for (i = 0; i < 2; i++)
13773 sign_extend = ((unsigned_p)
13775 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
13776 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
13777 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
13778 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
13779 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
13780 pperm_bytes[8*i+4] = sign_extend;
13781 pperm_bytes[8*i+5] = sign_extend;
13782 pperm_bytes[8*i+6] = sign_extend;
13783 pperm_bytes[8*i+7] = sign_extend;
13786 for (i = 0; i < 16; i++)
13787 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13789 for (i = 0; i < 2; i++)
13790 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13792 p = gen_rtx_PARALLEL (VOIDmode, vs);
13793 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13795 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
13797 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
13801 gcc_unreachable ();
13807 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
13808 next narrower integer vector type */
13810 ix86_expand_sse5_pack (rtx operands[3])
13812 enum machine_mode imode = GET_MODE (operands[0]);
13813 int pperm_bytes[16];
13815 rtvec v = rtvec_alloc (16);
13817 rtx op0 = operands[0];
13818 rtx op1 = operands[1];
13819 rtx op2 = operands[2];
13824 for (i = 0; i < 8; i++)
13826 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
13827 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
13830 for (i = 0; i < 16; i++)
13831 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13833 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13834 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
13838 for (i = 0; i < 4; i++)
13840 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
13841 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
13842 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
13843 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
13846 for (i = 0; i < 16; i++)
13847 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13849 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13850 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
13854 for (i = 0; i < 2; i++)
13856 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
13857 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
13858 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
13859 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
13860 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
13861 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
13862 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
13863 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
13866 for (i = 0; i < 16; i++)
13867 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13869 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13870 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
13874 gcc_unreachable ();
13880 /* Expand conditional increment or decrement using adb/sbb instructions.
13881 The default case using setcc followed by the conditional move can be
13882 done by generic code. */
13884 ix86_expand_int_addcc (rtx operands[])
13886 enum rtx_code code = GET_CODE (operands[1]);
13888 rtx val = const0_rtx;
13889 bool fpcmp = false;
13890 enum machine_mode mode = GET_MODE (operands[0]);
13892 if (operands[3] != const1_rtx
13893 && operands[3] != constm1_rtx)
13895 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
13896 ix86_compare_op1, &compare_op))
13898 code = GET_CODE (compare_op);
13900 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
13901 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
13904 code = ix86_fp_compare_code_to_integer (code);
13911 PUT_CODE (compare_op,
13912 reverse_condition_maybe_unordered
13913 (GET_CODE (compare_op)));
13915 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
13917 PUT_MODE (compare_op, mode);
13919 /* Construct either adc or sbb insn. */
13920 if ((code == LTU) == (operands[3] == constm1_rtx))
13922 switch (GET_MODE (operands[0]))
13925 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
13928 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
13931 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
13934 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13937 gcc_unreachable ();
13942 switch (GET_MODE (operands[0]))
13945 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
13948 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
13951 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
13954 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13957 gcc_unreachable ();
13960 return 1; /* DONE */
13964 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
13965 works for floating pointer parameters and nonoffsetable memories.
13966 For pushes, it returns just stack offsets; the values will be saved
13967 in the right order. Maximally three parts are generated. */
13970 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
13975 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
13977 size = (GET_MODE_SIZE (mode) + 4) / 8;
13979 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
13980 gcc_assert (size >= 2 && size <= 3);
13982 /* Optimize constant pool reference to immediates. This is used by fp
13983 moves, that force all constants to memory to allow combining. */
13984 if (MEM_P (operand) && MEM_READONLY_P (operand))
13986 rtx tmp = maybe_get_pool_constant (operand);
13991 if (MEM_P (operand) && !offsettable_memref_p (operand))
13993 /* The only non-offsetable memories we handle are pushes. */
13994 int ok = push_operand (operand, VOIDmode);
13998 operand = copy_rtx (operand);
13999 PUT_MODE (operand, Pmode);
14000 parts[0] = parts[1] = parts[2] = operand;
14004 if (GET_CODE (operand) == CONST_VECTOR)
14006 enum machine_mode imode = int_mode_for_mode (mode);
14007 /* Caution: if we looked through a constant pool memory above,
14008 the operand may actually have a different mode now. That's
14009 ok, since we want to pun this all the way back to an integer. */
14010 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
14011 gcc_assert (operand != NULL);
14017 if (mode == DImode)
14018 split_di (&operand, 1, &parts[0], &parts[1]);
14021 if (REG_P (operand))
14023 gcc_assert (reload_completed);
14024 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
14025 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
14027 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
14029 else if (offsettable_memref_p (operand))
14031 operand = adjust_address (operand, SImode, 0);
14032 parts[0] = operand;
14033 parts[1] = adjust_address (operand, SImode, 4);
14035 parts[2] = adjust_address (operand, SImode, 8);
14037 else if (GET_CODE (operand) == CONST_DOUBLE)
14042 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
14046 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
14047 parts[2] = gen_int_mode (l[2], SImode);
14050 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
14053 gcc_unreachable ();
14055 parts[1] = gen_int_mode (l[1], SImode);
14056 parts[0] = gen_int_mode (l[0], SImode);
14059 gcc_unreachable ();
14064 if (mode == TImode)
14065 split_ti (&operand, 1, &parts[0], &parts[1]);
14066 if (mode == XFmode || mode == TFmode)
14068 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
14069 if (REG_P (operand))
14071 gcc_assert (reload_completed);
14072 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
14073 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
14075 else if (offsettable_memref_p (operand))
14077 operand = adjust_address (operand, DImode, 0);
14078 parts[0] = operand;
14079 parts[1] = adjust_address (operand, upper_mode, 8);
14081 else if (GET_CODE (operand) == CONST_DOUBLE)
14086 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
14087 real_to_target (l, &r, mode);
14089 /* Do not use shift by 32 to avoid warning on 32bit systems. */
14090 if (HOST_BITS_PER_WIDE_INT >= 64)
14093 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
14094 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
14097 parts[0] = immed_double_const (l[0], l[1], DImode);
14099 if (upper_mode == SImode)
14100 parts[1] = gen_int_mode (l[2], SImode);
14101 else if (HOST_BITS_PER_WIDE_INT >= 64)
14104 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
14105 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
14108 parts[1] = immed_double_const (l[2], l[3], DImode);
14111 gcc_unreachable ();
14118 /* Emit insns to perform a move or push of DI, DF, and XF values.
14119 Return false when normal moves are needed; true when all required
14120 insns have been emitted. Operands 2-4 contain the input values
14121 int the correct order; operands 5-7 contain the output values. */
14124 ix86_split_long_move (rtx operands[])
14129 int collisions = 0;
14130 enum machine_mode mode = GET_MODE (operands[0]);
14132 /* The DFmode expanders may ask us to move double.
14133 For 64bit target this is single move. By hiding the fact
14134 here we simplify i386.md splitters. */
14135 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
14137 /* Optimize constant pool reference to immediates. This is used by
14138 fp moves, that force all constants to memory to allow combining. */
14140 if (MEM_P (operands[1])
14141 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
14142 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
14143 operands[1] = get_pool_constant (XEXP (operands[1], 0));
14144 if (push_operand (operands[0], VOIDmode))
14146 operands[0] = copy_rtx (operands[0]);
14147 PUT_MODE (operands[0], Pmode);
14150 operands[0] = gen_lowpart (DImode, operands[0]);
14151 operands[1] = gen_lowpart (DImode, operands[1]);
14152 emit_move_insn (operands[0], operands[1]);
14156 /* The only non-offsettable memory we handle is push. */
14157 if (push_operand (operands[0], VOIDmode))
14160 gcc_assert (!MEM_P (operands[0])
14161 || offsettable_memref_p (operands[0]));
14163 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
14164 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
14166 /* When emitting push, take care for source operands on the stack. */
14167 if (push && MEM_P (operands[1])
14168 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
14171 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
14172 XEXP (part[1][2], 0));
14173 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
14174 XEXP (part[1][1], 0));
14177 /* We need to do copy in the right order in case an address register
14178 of the source overlaps the destination. */
14179 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
14181 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
14183 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14186 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
14189 /* Collision in the middle part can be handled by reordering. */
14190 if (collisions == 1 && nparts == 3
14191 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14194 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
14195 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
14198 /* If there are more collisions, we can't handle it by reordering.
14199 Do an lea to the last part and use only one colliding move. */
14200 else if (collisions > 1)
14206 base = part[0][nparts - 1];
14208 /* Handle the case when the last part isn't valid for lea.
14209 Happens in 64-bit mode storing the 12-byte XFmode. */
14210 if (GET_MODE (base) != Pmode)
14211 base = gen_rtx_REG (Pmode, REGNO (base));
14213 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
14214 part[1][0] = replace_equiv_address (part[1][0], base);
14215 part[1][1] = replace_equiv_address (part[1][1],
14216 plus_constant (base, UNITS_PER_WORD));
14218 part[1][2] = replace_equiv_address (part[1][2],
14219 plus_constant (base, 8));
14229 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
14230 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
14231 emit_move_insn (part[0][2], part[1][2]);
14236 /* In 64bit mode we don't have 32bit push available. In case this is
14237 register, it is OK - we will just use larger counterpart. We also
14238 retype memory - these comes from attempt to avoid REX prefix on
14239 moving of second half of TFmode value. */
14240 if (GET_MODE (part[1][1]) == SImode)
14242 switch (GET_CODE (part[1][1]))
14245 part[1][1] = adjust_address (part[1][1], DImode, 0);
14249 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
14253 gcc_unreachable ();
14256 if (GET_MODE (part[1][0]) == SImode)
14257 part[1][0] = part[1][1];
14260 emit_move_insn (part[0][1], part[1][1]);
14261 emit_move_insn (part[0][0], part[1][0]);
14265 /* Choose correct order to not overwrite the source before it is copied. */
14266 if ((REG_P (part[0][0])
14267 && REG_P (part[1][1])
14268 && (REGNO (part[0][0]) == REGNO (part[1][1])
14270 && REGNO (part[0][0]) == REGNO (part[1][2]))))
14272 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
14276 operands[2] = part[0][2];
14277 operands[3] = part[0][1];
14278 operands[4] = part[0][0];
14279 operands[5] = part[1][2];
14280 operands[6] = part[1][1];
14281 operands[7] = part[1][0];
14285 operands[2] = part[0][1];
14286 operands[3] = part[0][0];
14287 operands[5] = part[1][1];
14288 operands[6] = part[1][0];
14295 operands[2] = part[0][0];
14296 operands[3] = part[0][1];
14297 operands[4] = part[0][2];
14298 operands[5] = part[1][0];
14299 operands[6] = part[1][1];
14300 operands[7] = part[1][2];
14304 operands[2] = part[0][0];
14305 operands[3] = part[0][1];
14306 operands[5] = part[1][0];
14307 operands[6] = part[1][1];
14311 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
14314 if (CONST_INT_P (operands[5])
14315 && operands[5] != const0_rtx
14316 && REG_P (operands[2]))
14318 if (CONST_INT_P (operands[6])
14319 && INTVAL (operands[6]) == INTVAL (operands[5]))
14320 operands[6] = operands[2];
14323 && CONST_INT_P (operands[7])
14324 && INTVAL (operands[7]) == INTVAL (operands[5]))
14325 operands[7] = operands[2];
14329 && CONST_INT_P (operands[6])
14330 && operands[6] != const0_rtx
14331 && REG_P (operands[3])
14332 && CONST_INT_P (operands[7])
14333 && INTVAL (operands[7]) == INTVAL (operands[6]))
14334 operands[7] = operands[3];
14337 emit_move_insn (operands[2], operands[5]);
14338 emit_move_insn (operands[3], operands[6]);
14340 emit_move_insn (operands[4], operands[7]);
14345 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
14346 left shift by a constant, either using a single shift or
14347 a sequence of add instructions. */
14350 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
14354 emit_insn ((mode == DImode
14356 : gen_adddi3) (operand, operand, operand));
14358 else if (!optimize_size
14359 && count * ix86_cost->add <= ix86_cost->shift_const)
14362 for (i=0; i<count; i++)
14364 emit_insn ((mode == DImode
14366 : gen_adddi3) (operand, operand, operand));
14370 emit_insn ((mode == DImode
14372 : gen_ashldi3) (operand, operand, GEN_INT (count)));
14376 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
14378 rtx low[2], high[2];
14380 const int single_width = mode == DImode ? 32 : 64;
14382 if (CONST_INT_P (operands[2]))
14384 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14385 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14387 if (count >= single_width)
14389 emit_move_insn (high[0], low[1]);
14390 emit_move_insn (low[0], const0_rtx);
14392 if (count > single_width)
14393 ix86_expand_ashl_const (high[0], count - single_width, mode);
14397 if (!rtx_equal_p (operands[0], operands[1]))
14398 emit_move_insn (operands[0], operands[1]);
14399 emit_insn ((mode == DImode
14401 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
14402 ix86_expand_ashl_const (low[0], count, mode);
14407 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14409 if (operands[1] == const1_rtx)
14411 /* Assuming we've chosen a QImode capable registers, then 1 << N
14412 can be done with two 32/64-bit shifts, no branches, no cmoves. */
14413 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
14415 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
14417 ix86_expand_clear (low[0]);
14418 ix86_expand_clear (high[0]);
14419 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
14421 d = gen_lowpart (QImode, low[0]);
14422 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14423 s = gen_rtx_EQ (QImode, flags, const0_rtx);
14424 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14426 d = gen_lowpart (QImode, high[0]);
14427 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14428 s = gen_rtx_NE (QImode, flags, const0_rtx);
14429 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14432 /* Otherwise, we can get the same results by manually performing
14433 a bit extract operation on bit 5/6, and then performing the two
14434 shifts. The two methods of getting 0/1 into low/high are exactly
14435 the same size. Avoiding the shift in the bit extract case helps
14436 pentium4 a bit; no one else seems to care much either way. */
14441 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
14442 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
14444 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
14445 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
14447 emit_insn ((mode == DImode
14449 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
14450 emit_insn ((mode == DImode
14452 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
14453 emit_move_insn (low[0], high[0]);
14454 emit_insn ((mode == DImode
14456 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
14459 emit_insn ((mode == DImode
14461 : gen_ashldi3) (low[0], low[0], operands[2]));
14462 emit_insn ((mode == DImode
14464 : gen_ashldi3) (high[0], high[0], operands[2]));
14468 if (operands[1] == constm1_rtx)
14470 /* For -1 << N, we can avoid the shld instruction, because we
14471 know that we're shifting 0...31/63 ones into a -1. */
14472 emit_move_insn (low[0], constm1_rtx);
14474 emit_move_insn (high[0], low[0]);
14476 emit_move_insn (high[0], constm1_rtx);
14480 if (!rtx_equal_p (operands[0], operands[1]))
14481 emit_move_insn (operands[0], operands[1]);
14483 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14484 emit_insn ((mode == DImode
14486 : gen_x86_64_shld) (high[0], low[0], operands[2]));
14489 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
14491 if (TARGET_CMOVE && scratch)
14493 ix86_expand_clear (scratch);
14494 emit_insn ((mode == DImode
14495 ? gen_x86_shift_adj_1
14496 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
14499 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
14503 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
14505 rtx low[2], high[2];
14507 const int single_width = mode == DImode ? 32 : 64;
14509 if (CONST_INT_P (operands[2]))
14511 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14512 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14514 if (count == single_width * 2 - 1)
14516 emit_move_insn (high[0], high[1]);
14517 emit_insn ((mode == DImode
14519 : gen_ashrdi3) (high[0], high[0],
14520 GEN_INT (single_width - 1)));
14521 emit_move_insn (low[0], high[0]);
14524 else if (count >= single_width)
14526 emit_move_insn (low[0], high[1]);
14527 emit_move_insn (high[0], low[0]);
14528 emit_insn ((mode == DImode
14530 : gen_ashrdi3) (high[0], high[0],
14531 GEN_INT (single_width - 1)));
14532 if (count > single_width)
14533 emit_insn ((mode == DImode
14535 : gen_ashrdi3) (low[0], low[0],
14536 GEN_INT (count - single_width)));
14540 if (!rtx_equal_p (operands[0], operands[1]))
14541 emit_move_insn (operands[0], operands[1]);
14542 emit_insn ((mode == DImode
14544 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14545 emit_insn ((mode == DImode
14547 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
14552 if (!rtx_equal_p (operands[0], operands[1]))
14553 emit_move_insn (operands[0], operands[1]);
14555 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14557 emit_insn ((mode == DImode
14559 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14560 emit_insn ((mode == DImode
14562 : gen_ashrdi3) (high[0], high[0], operands[2]));
14564 if (TARGET_CMOVE && scratch)
14566 emit_move_insn (scratch, high[0]);
14567 emit_insn ((mode == DImode
14569 : gen_ashrdi3) (scratch, scratch,
14570 GEN_INT (single_width - 1)));
14571 emit_insn ((mode == DImode
14572 ? gen_x86_shift_adj_1
14573 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14577 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
14582 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
14584 rtx low[2], high[2];
14586 const int single_width = mode == DImode ? 32 : 64;
14588 if (CONST_INT_P (operands[2]))
14590 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14591 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14593 if (count >= single_width)
14595 emit_move_insn (low[0], high[1]);
14596 ix86_expand_clear (high[0]);
14598 if (count > single_width)
14599 emit_insn ((mode == DImode
14601 : gen_lshrdi3) (low[0], low[0],
14602 GEN_INT (count - single_width)));
14606 if (!rtx_equal_p (operands[0], operands[1]))
14607 emit_move_insn (operands[0], operands[1]);
14608 emit_insn ((mode == DImode
14610 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14611 emit_insn ((mode == DImode
14613 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
14618 if (!rtx_equal_p (operands[0], operands[1]))
14619 emit_move_insn (operands[0], operands[1]);
14621 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14623 emit_insn ((mode == DImode
14625 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14626 emit_insn ((mode == DImode
14628 : gen_lshrdi3) (high[0], high[0], operands[2]));
14630 /* Heh. By reversing the arguments, we can reuse this pattern. */
14631 if (TARGET_CMOVE && scratch)
14633 ix86_expand_clear (scratch);
14634 emit_insn ((mode == DImode
14635 ? gen_x86_shift_adj_1
14636 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14640 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
14644 /* Predict just emitted jump instruction to be taken with probability PROB. */
14646 predict_jump (int prob)
14648 rtx insn = get_last_insn ();
14649 gcc_assert (JUMP_P (insn));
14651 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14656 /* Helper function for the string operations below. Dest VARIABLE whether
14657 it is aligned to VALUE bytes. If true, jump to the label. */
14659 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
14661 rtx label = gen_label_rtx ();
14662 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
14663 if (GET_MODE (variable) == DImode)
14664 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
14666 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
14667 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
14670 predict_jump (REG_BR_PROB_BASE * 50 / 100);
14672 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14676 /* Adjust COUNTER by the VALUE. */
14678 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
14680 if (GET_MODE (countreg) == DImode)
14681 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
14683 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
14686 /* Zero extend possibly SImode EXP to Pmode register. */
14688 ix86_zero_extend_to_Pmode (rtx exp)
14691 if (GET_MODE (exp) == VOIDmode)
14692 return force_reg (Pmode, exp);
14693 if (GET_MODE (exp) == Pmode)
14694 return copy_to_mode_reg (Pmode, exp);
14695 r = gen_reg_rtx (Pmode);
14696 emit_insn (gen_zero_extendsidi2 (r, exp));
14700 /* Divide COUNTREG by SCALE. */
14702 scale_counter (rtx countreg, int scale)
14705 rtx piece_size_mask;
14709 if (CONST_INT_P (countreg))
14710 return GEN_INT (INTVAL (countreg) / scale);
14711 gcc_assert (REG_P (countreg));
14713 piece_size_mask = GEN_INT (scale - 1);
14714 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
14715 GEN_INT (exact_log2 (scale)),
14716 NULL, 1, OPTAB_DIRECT);
14720 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
14721 DImode for constant loop counts. */
14723 static enum machine_mode
14724 counter_mode (rtx count_exp)
14726 if (GET_MODE (count_exp) != VOIDmode)
14727 return GET_MODE (count_exp);
14728 if (GET_CODE (count_exp) != CONST_INT)
14730 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
14735 /* When SRCPTR is non-NULL, output simple loop to move memory
14736 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
14737 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
14738 equivalent loop to set memory by VALUE (supposed to be in MODE).
14740 The size is rounded down to whole number of chunk size moved at once.
14741 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
14745 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
14746 rtx destptr, rtx srcptr, rtx value,
14747 rtx count, enum machine_mode mode, int unroll,
14750 rtx out_label, top_label, iter, tmp;
14751 enum machine_mode iter_mode = counter_mode (count);
14752 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
14753 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
14759 top_label = gen_label_rtx ();
14760 out_label = gen_label_rtx ();
14761 iter = gen_reg_rtx (iter_mode);
14763 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
14764 NULL, 1, OPTAB_DIRECT);
14765 /* Those two should combine. */
14766 if (piece_size == const1_rtx)
14768 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
14770 predict_jump (REG_BR_PROB_BASE * 10 / 100);
14772 emit_move_insn (iter, const0_rtx);
14774 emit_label (top_label);
14776 tmp = convert_modes (Pmode, iter_mode, iter, true);
14777 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
14778 destmem = change_address (destmem, mode, x_addr);
14782 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
14783 srcmem = change_address (srcmem, mode, y_addr);
14785 /* When unrolling for chips that reorder memory reads and writes,
14786 we can save registers by using single temporary.
14787 Also using 4 temporaries is overkill in 32bit mode. */
14788 if (!TARGET_64BIT && 0)
14790 for (i = 0; i < unroll; i++)
14795 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14797 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14799 emit_move_insn (destmem, srcmem);
14805 gcc_assert (unroll <= 4);
14806 for (i = 0; i < unroll; i++)
14808 tmpreg[i] = gen_reg_rtx (mode);
14812 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14814 emit_move_insn (tmpreg[i], srcmem);
14816 for (i = 0; i < unroll; i++)
14821 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14823 emit_move_insn (destmem, tmpreg[i]);
14828 for (i = 0; i < unroll; i++)
14832 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14833 emit_move_insn (destmem, value);
14836 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
14837 true, OPTAB_LIB_WIDEN);
14839 emit_move_insn (iter, tmp);
14841 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
14843 if (expected_size != -1)
14845 expected_size /= GET_MODE_SIZE (mode) * unroll;
14846 if (expected_size == 0)
14848 else if (expected_size > REG_BR_PROB_BASE)
14849 predict_jump (REG_BR_PROB_BASE - 1);
14851 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
14854 predict_jump (REG_BR_PROB_BASE * 80 / 100);
14855 iter = ix86_zero_extend_to_Pmode (iter);
14856 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
14857 true, OPTAB_LIB_WIDEN);
14858 if (tmp != destptr)
14859 emit_move_insn (destptr, tmp);
14862 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
14863 true, OPTAB_LIB_WIDEN);
14865 emit_move_insn (srcptr, tmp);
14867 emit_label (out_label);
14870 /* Output "rep; mov" instruction.
14871 Arguments have same meaning as for previous function */
14873 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
14874 rtx destptr, rtx srcptr,
14876 enum machine_mode mode)
14882 /* If the size is known, it is shorter to use rep movs. */
14883 if (mode == QImode && CONST_INT_P (count)
14884 && !(INTVAL (count) & 3))
14887 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14888 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14889 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
14890 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
14891 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14892 if (mode != QImode)
14894 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14895 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14896 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14897 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
14898 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14899 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
14903 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14904 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
14906 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
14910 /* Output "rep; stos" instruction.
14911 Arguments have same meaning as for previous function */
14913 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
14915 enum machine_mode mode)
14920 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14921 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14922 value = force_reg (mode, gen_lowpart (mode, value));
14923 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14924 if (mode != QImode)
14926 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14927 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14928 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14931 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14932 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
14936 emit_strmov (rtx destmem, rtx srcmem,
14937 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
14939 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
14940 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
14941 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14944 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
14946 expand_movmem_epilogue (rtx destmem, rtx srcmem,
14947 rtx destptr, rtx srcptr, rtx count, int max_size)
14950 if (CONST_INT_P (count))
14952 HOST_WIDE_INT countval = INTVAL (count);
14955 if ((countval & 0x10) && max_size > 16)
14959 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14960 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
14963 gcc_unreachable ();
14966 if ((countval & 0x08) && max_size > 8)
14969 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14972 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14973 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
14977 if ((countval & 0x04) && max_size > 4)
14979 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14982 if ((countval & 0x02) && max_size > 2)
14984 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
14987 if ((countval & 0x01) && max_size > 1)
14989 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
14996 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
14997 count, 1, OPTAB_DIRECT);
14998 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
14999 count, QImode, 1, 4);
15003 /* When there are stringops, we can cheaply increase dest and src pointers.
15004 Otherwise we save code size by maintaining offset (zero is readily
15005 available from preceding rep operation) and using x86 addressing modes.
15007 if (TARGET_SINGLE_STRINGOP)
15011 rtx label = ix86_expand_aligntest (count, 4, true);
15012 src = change_address (srcmem, SImode, srcptr);
15013 dest = change_address (destmem, SImode, destptr);
15014 emit_insn (gen_strmov (destptr, dest, srcptr, src));
15015 emit_label (label);
15016 LABEL_NUSES (label) = 1;
15020 rtx label = ix86_expand_aligntest (count, 2, true);
15021 src = change_address (srcmem, HImode, srcptr);
15022 dest = change_address (destmem, HImode, destptr);
15023 emit_insn (gen_strmov (destptr, dest, srcptr, src));
15024 emit_label (label);
15025 LABEL_NUSES (label) = 1;
15029 rtx label = ix86_expand_aligntest (count, 1, true);
15030 src = change_address (srcmem, QImode, srcptr);
15031 dest = change_address (destmem, QImode, destptr);
15032 emit_insn (gen_strmov (destptr, dest, srcptr, src));
15033 emit_label (label);
15034 LABEL_NUSES (label) = 1;
15039 rtx offset = force_reg (Pmode, const0_rtx);
15044 rtx label = ix86_expand_aligntest (count, 4, true);
15045 src = change_address (srcmem, SImode, srcptr);
15046 dest = change_address (destmem, SImode, destptr);
15047 emit_move_insn (dest, src);
15048 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
15049 true, OPTAB_LIB_WIDEN);
15051 emit_move_insn (offset, tmp);
15052 emit_label (label);
15053 LABEL_NUSES (label) = 1;
15057 rtx label = ix86_expand_aligntest (count, 2, true);
15058 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
15059 src = change_address (srcmem, HImode, tmp);
15060 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
15061 dest = change_address (destmem, HImode, tmp);
15062 emit_move_insn (dest, src);
15063 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
15064 true, OPTAB_LIB_WIDEN);
15066 emit_move_insn (offset, tmp);
15067 emit_label (label);
15068 LABEL_NUSES (label) = 1;
15072 rtx label = ix86_expand_aligntest (count, 1, true);
15073 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
15074 src = change_address (srcmem, QImode, tmp);
15075 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
15076 dest = change_address (destmem, QImode, tmp);
15077 emit_move_insn (dest, src);
15078 emit_label (label);
15079 LABEL_NUSES (label) = 1;
15084 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
15086 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
15087 rtx count, int max_size)
15090 expand_simple_binop (counter_mode (count), AND, count,
15091 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
15092 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
15093 gen_lowpart (QImode, value), count, QImode,
15097 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
15099 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
15103 if (CONST_INT_P (count))
15105 HOST_WIDE_INT countval = INTVAL (count);
15108 if ((countval & 0x10) && max_size > 16)
15112 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
15113 emit_insn (gen_strset (destptr, dest, value));
15114 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
15115 emit_insn (gen_strset (destptr, dest, value));
15118 gcc_unreachable ();
15121 if ((countval & 0x08) && max_size > 8)
15125 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
15126 emit_insn (gen_strset (destptr, dest, value));
15130 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15131 emit_insn (gen_strset (destptr, dest, value));
15132 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
15133 emit_insn (gen_strset (destptr, dest, value));
15137 if ((countval & 0x04) && max_size > 4)
15139 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15140 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15143 if ((countval & 0x02) && max_size > 2)
15145 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
15146 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15149 if ((countval & 0x01) && max_size > 1)
15151 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
15152 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15159 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
15164 rtx label = ix86_expand_aligntest (count, 16, true);
15167 dest = change_address (destmem, DImode, destptr);
15168 emit_insn (gen_strset (destptr, dest, value));
15169 emit_insn (gen_strset (destptr, dest, value));
15173 dest = change_address (destmem, SImode, destptr);
15174 emit_insn (gen_strset (destptr, dest, value));
15175 emit_insn (gen_strset (destptr, dest, value));
15176 emit_insn (gen_strset (destptr, dest, value));
15177 emit_insn (gen_strset (destptr, dest, value));
15179 emit_label (label);
15180 LABEL_NUSES (label) = 1;
15184 rtx label = ix86_expand_aligntest (count, 8, true);
15187 dest = change_address (destmem, DImode, destptr);
15188 emit_insn (gen_strset (destptr, dest, value));
15192 dest = change_address (destmem, SImode, destptr);
15193 emit_insn (gen_strset (destptr, dest, value));
15194 emit_insn (gen_strset (destptr, dest, value));
15196 emit_label (label);
15197 LABEL_NUSES (label) = 1;
15201 rtx label = ix86_expand_aligntest (count, 4, true);
15202 dest = change_address (destmem, SImode, destptr);
15203 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15204 emit_label (label);
15205 LABEL_NUSES (label) = 1;
15209 rtx label = ix86_expand_aligntest (count, 2, true);
15210 dest = change_address (destmem, HImode, destptr);
15211 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15212 emit_label (label);
15213 LABEL_NUSES (label) = 1;
15217 rtx label = ix86_expand_aligntest (count, 1, true);
15218 dest = change_address (destmem, QImode, destptr);
15219 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15220 emit_label (label);
15221 LABEL_NUSES (label) = 1;
15225 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
15226 DESIRED_ALIGNMENT. */
15228 expand_movmem_prologue (rtx destmem, rtx srcmem,
15229 rtx destptr, rtx srcptr, rtx count,
15230 int align, int desired_alignment)
15232 if (align <= 1 && desired_alignment > 1)
15234 rtx label = ix86_expand_aligntest (destptr, 1, false);
15235 srcmem = change_address (srcmem, QImode, srcptr);
15236 destmem = change_address (destmem, QImode, destptr);
15237 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15238 ix86_adjust_counter (count, 1);
15239 emit_label (label);
15240 LABEL_NUSES (label) = 1;
15242 if (align <= 2 && desired_alignment > 2)
15244 rtx label = ix86_expand_aligntest (destptr, 2, false);
15245 srcmem = change_address (srcmem, HImode, srcptr);
15246 destmem = change_address (destmem, HImode, destptr);
15247 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15248 ix86_adjust_counter (count, 2);
15249 emit_label (label);
15250 LABEL_NUSES (label) = 1;
15252 if (align <= 4 && desired_alignment > 4)
15254 rtx label = ix86_expand_aligntest (destptr, 4, false);
15255 srcmem = change_address (srcmem, SImode, srcptr);
15256 destmem = change_address (destmem, SImode, destptr);
15257 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15258 ix86_adjust_counter (count, 4);
15259 emit_label (label);
15260 LABEL_NUSES (label) = 1;
15262 gcc_assert (desired_alignment <= 8);
15265 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
15266 DESIRED_ALIGNMENT. */
15268 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
15269 int align, int desired_alignment)
15271 if (align <= 1 && desired_alignment > 1)
15273 rtx label = ix86_expand_aligntest (destptr, 1, false);
15274 destmem = change_address (destmem, QImode, destptr);
15275 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
15276 ix86_adjust_counter (count, 1);
15277 emit_label (label);
15278 LABEL_NUSES (label) = 1;
15280 if (align <= 2 && desired_alignment > 2)
15282 rtx label = ix86_expand_aligntest (destptr, 2, false);
15283 destmem = change_address (destmem, HImode, destptr);
15284 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
15285 ix86_adjust_counter (count, 2);
15286 emit_label (label);
15287 LABEL_NUSES (label) = 1;
15289 if (align <= 4 && desired_alignment > 4)
15291 rtx label = ix86_expand_aligntest (destptr, 4, false);
15292 destmem = change_address (destmem, SImode, destptr);
15293 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
15294 ix86_adjust_counter (count, 4);
15295 emit_label (label);
15296 LABEL_NUSES (label) = 1;
15298 gcc_assert (desired_alignment <= 8);
15301 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
15302 static enum stringop_alg
15303 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
15304 int *dynamic_check)
15306 const struct stringop_algs * algs;
15307 /* Algorithms using the rep prefix want at least edi and ecx;
15308 additionally, memset wants eax and memcpy wants esi. Don't
15309 consider such algorithms if the user has appropriated those
15310 registers for their own purposes. */
15311 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
15313 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
15315 #define ALG_USABLE_P(alg) (rep_prefix_usable \
15316 || (alg != rep_prefix_1_byte \
15317 && alg != rep_prefix_4_byte \
15318 && alg != rep_prefix_8_byte))
15320 *dynamic_check = -1;
15322 algs = &ix86_cost->memset[TARGET_64BIT != 0];
15324 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
15325 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
15326 return stringop_alg;
15327 /* rep; movq or rep; movl is the smallest variant. */
15328 else if (optimize_size)
15330 if (!count || (count & 3))
15331 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
15333 return rep_prefix_usable ? rep_prefix_4_byte : loop;
15335 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
15337 else if (expected_size != -1 && expected_size < 4)
15338 return loop_1_byte;
15339 else if (expected_size != -1)
15342 enum stringop_alg alg = libcall;
15343 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15345 /* We get here if the algorithms that were not libcall-based
15346 were rep-prefix based and we are unable to use rep prefixes
15347 based on global register usage. Break out of the loop and
15348 use the heuristic below. */
15349 if (algs->size[i].max == 0)
15351 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
15353 enum stringop_alg candidate = algs->size[i].alg;
15355 if (candidate != libcall && ALG_USABLE_P (candidate))
15357 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
15358 last non-libcall inline algorithm. */
15359 if (TARGET_INLINE_ALL_STRINGOPS)
15361 /* When the current size is best to be copied by a libcall,
15362 but we are still forced to inline, run the heuristic below
15363 that will pick code for medium sized blocks. */
15364 if (alg != libcall)
15368 else if (ALG_USABLE_P (candidate))
15372 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
15374 /* When asked to inline the call anyway, try to pick meaningful choice.
15375 We look for maximal size of block that is faster to copy by hand and
15376 take blocks of at most of that size guessing that average size will
15377 be roughly half of the block.
15379 If this turns out to be bad, we might simply specify the preferred
15380 choice in ix86_costs. */
15381 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15382 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
15385 enum stringop_alg alg;
15387 bool any_alg_usable_p = true;
15389 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15391 enum stringop_alg candidate = algs->size[i].alg;
15392 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
15394 if (candidate != libcall && candidate
15395 && ALG_USABLE_P (candidate))
15396 max = algs->size[i].max;
15398 /* If there aren't any usable algorithms, then recursing on
15399 smaller sizes isn't going to find anything. Just return the
15400 simple byte-at-a-time copy loop. */
15401 if (!any_alg_usable_p)
15403 /* Pick something reasonable. */
15404 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15405 *dynamic_check = 128;
15406 return loop_1_byte;
15410 alg = decide_alg (count, max / 2, memset, dynamic_check);
15411 gcc_assert (*dynamic_check == -1);
15412 gcc_assert (alg != libcall);
15413 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15414 *dynamic_check = max;
15417 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
15418 #undef ALG_USABLE_P
15421 /* Decide on alignment. We know that the operand is already aligned to ALIGN
15422 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
15424 decide_alignment (int align,
15425 enum stringop_alg alg,
15428 int desired_align = 0;
15432 gcc_unreachable ();
15434 case unrolled_loop:
15435 desired_align = GET_MODE_SIZE (Pmode);
15437 case rep_prefix_8_byte:
15440 case rep_prefix_4_byte:
15441 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15442 copying whole cacheline at once. */
15443 if (TARGET_PENTIUMPRO)
15448 case rep_prefix_1_byte:
15449 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15450 copying whole cacheline at once. */
15451 if (TARGET_PENTIUMPRO)
15465 if (desired_align < align)
15466 desired_align = align;
15467 if (expected_size != -1 && expected_size < 4)
15468 desired_align = align;
15469 return desired_align;
15472 /* Return the smallest power of 2 greater than VAL. */
15474 smallest_pow2_greater_than (int val)
15482 /* Expand string move (memcpy) operation. Use i386 string operations when
15483 profitable. expand_setmem contains similar code. The code depends upon
15484 architecture, block size and alignment, but always has the same
15487 1) Prologue guard: Conditional that jumps up to epilogues for small
15488 blocks that can be handled by epilogue alone. This is faster but
15489 also needed for correctness, since prologue assume the block is larger
15490 than the desired alignment.
15492 Optional dynamic check for size and libcall for large
15493 blocks is emitted here too, with -minline-stringops-dynamically.
15495 2) Prologue: copy first few bytes in order to get destination aligned
15496 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
15497 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
15498 We emit either a jump tree on power of two sized blocks, or a byte loop.
15500 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
15501 with specified algorithm.
15503 4) Epilogue: code copying tail of the block that is too small to be
15504 handled by main body (or up to size guarded by prologue guard). */
15507 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
15508 rtx expected_align_exp, rtx expected_size_exp)
15514 rtx jump_around_label = NULL;
15515 HOST_WIDE_INT align = 1;
15516 unsigned HOST_WIDE_INT count = 0;
15517 HOST_WIDE_INT expected_size = -1;
15518 int size_needed = 0, epilogue_size_needed;
15519 int desired_align = 0;
15520 enum stringop_alg alg;
15523 if (CONST_INT_P (align_exp))
15524 align = INTVAL (align_exp);
15525 /* i386 can do misaligned access on reasonably increased cost. */
15526 if (CONST_INT_P (expected_align_exp)
15527 && INTVAL (expected_align_exp) > align)
15528 align = INTVAL (expected_align_exp);
15529 if (CONST_INT_P (count_exp))
15530 count = expected_size = INTVAL (count_exp);
15531 if (CONST_INT_P (expected_size_exp) && count == 0)
15532 expected_size = INTVAL (expected_size_exp);
15534 /* Make sure we don't need to care about overflow later on. */
15535 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15538 /* Step 0: Decide on preferred algorithm, desired alignment and
15539 size of chunks to be copied by main loop. */
15541 alg = decide_alg (count, expected_size, false, &dynamic_check);
15542 desired_align = decide_alignment (align, alg, expected_size);
15544 if (!TARGET_ALIGN_STRINGOPS)
15545 align = desired_align;
15547 if (alg == libcall)
15549 gcc_assert (alg != no_stringop);
15551 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
15552 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15553 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
15558 gcc_unreachable ();
15560 size_needed = GET_MODE_SIZE (Pmode);
15562 case unrolled_loop:
15563 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
15565 case rep_prefix_8_byte:
15568 case rep_prefix_4_byte:
15571 case rep_prefix_1_byte:
15577 epilogue_size_needed = size_needed;
15579 /* Step 1: Prologue guard. */
15581 /* Alignment code needs count to be in register. */
15582 if (CONST_INT_P (count_exp) && desired_align > align)
15583 count_exp = force_reg (counter_mode (count_exp), count_exp);
15584 gcc_assert (desired_align >= 1 && align >= 1);
15586 /* Ensure that alignment prologue won't copy past end of block. */
15587 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15589 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15590 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15591 Make sure it is power of 2. */
15592 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15594 if (CONST_INT_P (count_exp))
15596 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
15601 label = gen_label_rtx ();
15602 emit_cmp_and_jump_insns (count_exp,
15603 GEN_INT (epilogue_size_needed),
15604 LTU, 0, counter_mode (count_exp), 1, label);
15605 if (expected_size == -1 || expected_size < epilogue_size_needed)
15606 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15608 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15612 /* Emit code to decide on runtime whether library call or inline should be
15614 if (dynamic_check != -1)
15616 if (CONST_INT_P (count_exp))
15618 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
15620 emit_block_move_via_libcall (dst, src, count_exp, false);
15621 count_exp = const0_rtx;
15627 rtx hot_label = gen_label_rtx ();
15628 jump_around_label = gen_label_rtx ();
15629 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15630 LEU, 0, GET_MODE (count_exp), 1, hot_label);
15631 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15632 emit_block_move_via_libcall (dst, src, count_exp, false);
15633 emit_jump (jump_around_label);
15634 emit_label (hot_label);
15638 /* Step 2: Alignment prologue. */
15640 if (desired_align > align)
15642 /* Except for the first move in epilogue, we no longer know
15643 constant offset in aliasing info. It don't seems to worth
15644 the pain to maintain it for the first move, so throw away
15646 src = change_address (src, BLKmode, srcreg);
15647 dst = change_address (dst, BLKmode, destreg);
15648 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
15651 if (label && size_needed == 1)
15653 emit_label (label);
15654 LABEL_NUSES (label) = 1;
15658 /* Step 3: Main loop. */
15664 gcc_unreachable ();
15666 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15667 count_exp, QImode, 1, expected_size);
15670 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15671 count_exp, Pmode, 1, expected_size);
15673 case unrolled_loop:
15674 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
15675 registers for 4 temporaries anyway. */
15676 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15677 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
15680 case rep_prefix_8_byte:
15681 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15684 case rep_prefix_4_byte:
15685 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15688 case rep_prefix_1_byte:
15689 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15693 /* Adjust properly the offset of src and dest memory for aliasing. */
15694 if (CONST_INT_P (count_exp))
15696 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
15697 (count / size_needed) * size_needed);
15698 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15699 (count / size_needed) * size_needed);
15703 src = change_address (src, BLKmode, srcreg);
15704 dst = change_address (dst, BLKmode, destreg);
15707 /* Step 4: Epilogue to copy the remaining bytes. */
15711 /* When the main loop is done, COUNT_EXP might hold original count,
15712 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15713 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15714 bytes. Compensate if needed. */
15716 if (size_needed < epilogue_size_needed)
15719 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15720 GEN_INT (size_needed - 1), count_exp, 1,
15722 if (tmp != count_exp)
15723 emit_move_insn (count_exp, tmp);
15725 emit_label (label);
15726 LABEL_NUSES (label) = 1;
15729 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15730 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
15731 epilogue_size_needed);
15732 if (jump_around_label)
15733 emit_label (jump_around_label);
15737 /* Helper function for memcpy. For QImode value 0xXY produce
15738 0xXYXYXYXY of wide specified by MODE. This is essentially
15739 a * 0x10101010, but we can do slightly better than
15740 synth_mult by unwinding the sequence by hand on CPUs with
15743 promote_duplicated_reg (enum machine_mode mode, rtx val)
15745 enum machine_mode valmode = GET_MODE (val);
15747 int nops = mode == DImode ? 3 : 2;
15749 gcc_assert (mode == SImode || mode == DImode);
15750 if (val == const0_rtx)
15751 return copy_to_mode_reg (mode, const0_rtx);
15752 if (CONST_INT_P (val))
15754 HOST_WIDE_INT v = INTVAL (val) & 255;
15758 if (mode == DImode)
15759 v |= (v << 16) << 16;
15760 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
15763 if (valmode == VOIDmode)
15765 if (valmode != QImode)
15766 val = gen_lowpart (QImode, val);
15767 if (mode == QImode)
15769 if (!TARGET_PARTIAL_REG_STALL)
15771 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
15772 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
15773 <= (ix86_cost->shift_const + ix86_cost->add) * nops
15774 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
15776 rtx reg = convert_modes (mode, QImode, val, true);
15777 tmp = promote_duplicated_reg (mode, const1_rtx);
15778 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
15783 rtx reg = convert_modes (mode, QImode, val, true);
15785 if (!TARGET_PARTIAL_REG_STALL)
15786 if (mode == SImode)
15787 emit_insn (gen_movsi_insv_1 (reg, reg));
15789 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
15792 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
15793 NULL, 1, OPTAB_DIRECT);
15795 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15797 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
15798 NULL, 1, OPTAB_DIRECT);
15799 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15800 if (mode == SImode)
15802 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
15803 NULL, 1, OPTAB_DIRECT);
15804 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15809 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
15810 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
15811 alignment from ALIGN to DESIRED_ALIGN. */
15813 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
15818 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
15819 promoted_val = promote_duplicated_reg (DImode, val);
15820 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
15821 promoted_val = promote_duplicated_reg (SImode, val);
15822 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
15823 promoted_val = promote_duplicated_reg (HImode, val);
15825 promoted_val = val;
15827 return promoted_val;
15830 /* Expand string clear operation (bzero). Use i386 string operations when
15831 profitable. See expand_movmem comment for explanation of individual
15832 steps performed. */
15834 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
15835 rtx expected_align_exp, rtx expected_size_exp)
15840 rtx jump_around_label = NULL;
15841 HOST_WIDE_INT align = 1;
15842 unsigned HOST_WIDE_INT count = 0;
15843 HOST_WIDE_INT expected_size = -1;
15844 int size_needed = 0, epilogue_size_needed;
15845 int desired_align = 0;
15846 enum stringop_alg alg;
15847 rtx promoted_val = NULL;
15848 bool force_loopy_epilogue = false;
15851 if (CONST_INT_P (align_exp))
15852 align = INTVAL (align_exp);
15853 /* i386 can do misaligned access on reasonably increased cost. */
15854 if (CONST_INT_P (expected_align_exp)
15855 && INTVAL (expected_align_exp) > align)
15856 align = INTVAL (expected_align_exp);
15857 if (CONST_INT_P (count_exp))
15858 count = expected_size = INTVAL (count_exp);
15859 if (CONST_INT_P (expected_size_exp) && count == 0)
15860 expected_size = INTVAL (expected_size_exp);
15862 /* Make sure we don't need to care about overflow later on. */
15863 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15866 /* Step 0: Decide on preferred algorithm, desired alignment and
15867 size of chunks to be copied by main loop. */
15869 alg = decide_alg (count, expected_size, true, &dynamic_check);
15870 desired_align = decide_alignment (align, alg, expected_size);
15872 if (!TARGET_ALIGN_STRINGOPS)
15873 align = desired_align;
15875 if (alg == libcall)
15877 gcc_assert (alg != no_stringop);
15879 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
15880 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15885 gcc_unreachable ();
15887 size_needed = GET_MODE_SIZE (Pmode);
15889 case unrolled_loop:
15890 size_needed = GET_MODE_SIZE (Pmode) * 4;
15892 case rep_prefix_8_byte:
15895 case rep_prefix_4_byte:
15898 case rep_prefix_1_byte:
15903 epilogue_size_needed = size_needed;
15905 /* Step 1: Prologue guard. */
15907 /* Alignment code needs count to be in register. */
15908 if (CONST_INT_P (count_exp) && desired_align > align)
15910 enum machine_mode mode = SImode;
15911 if (TARGET_64BIT && (count & ~0xffffffff))
15913 count_exp = force_reg (mode, count_exp);
15915 /* Do the cheap promotion to allow better CSE across the
15916 main loop and epilogue (ie one load of the big constant in the
15917 front of all code. */
15918 if (CONST_INT_P (val_exp))
15919 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15920 desired_align, align);
15921 /* Ensure that alignment prologue won't copy past end of block. */
15922 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15924 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15925 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15926 Make sure it is power of 2. */
15927 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15929 /* To improve performance of small blocks, we jump around the VAL
15930 promoting mode. This mean that if the promoted VAL is not constant,
15931 we might not use it in the epilogue and have to use byte
15933 if (epilogue_size_needed > 2 && !promoted_val)
15934 force_loopy_epilogue = true;
15935 label = gen_label_rtx ();
15936 emit_cmp_and_jump_insns (count_exp,
15937 GEN_INT (epilogue_size_needed),
15938 LTU, 0, counter_mode (count_exp), 1, label);
15939 if (GET_CODE (count_exp) == CONST_INT)
15941 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
15942 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15944 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15946 if (dynamic_check != -1)
15948 rtx hot_label = gen_label_rtx ();
15949 jump_around_label = gen_label_rtx ();
15950 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15951 LEU, 0, counter_mode (count_exp), 1, hot_label);
15952 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15953 set_storage_via_libcall (dst, count_exp, val_exp, false);
15954 emit_jump (jump_around_label);
15955 emit_label (hot_label);
15958 /* Step 2: Alignment prologue. */
15960 /* Do the expensive promotion once we branched off the small blocks. */
15962 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15963 desired_align, align);
15964 gcc_assert (desired_align >= 1 && align >= 1);
15966 if (desired_align > align)
15968 /* Except for the first move in epilogue, we no longer know
15969 constant offset in aliasing info. It don't seems to worth
15970 the pain to maintain it for the first move, so throw away
15972 dst = change_address (dst, BLKmode, destreg);
15973 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
15976 if (label && size_needed == 1)
15978 emit_label (label);
15979 LABEL_NUSES (label) = 1;
15983 /* Step 3: Main loop. */
15989 gcc_unreachable ();
15991 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15992 count_exp, QImode, 1, expected_size);
15995 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15996 count_exp, Pmode, 1, expected_size);
15998 case unrolled_loop:
15999 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
16000 count_exp, Pmode, 4, expected_size);
16002 case rep_prefix_8_byte:
16003 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
16006 case rep_prefix_4_byte:
16007 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
16010 case rep_prefix_1_byte:
16011 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
16015 /* Adjust properly the offset of src and dest memory for aliasing. */
16016 if (CONST_INT_P (count_exp))
16017 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
16018 (count / size_needed) * size_needed);
16020 dst = change_address (dst, BLKmode, destreg);
16022 /* Step 4: Epilogue to copy the remaining bytes. */
16026 /* When the main loop is done, COUNT_EXP might hold original count,
16027 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
16028 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
16029 bytes. Compensate if needed. */
16031 if (size_needed < desired_align - align)
16034 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
16035 GEN_INT (size_needed - 1), count_exp, 1,
16037 size_needed = desired_align - align + 1;
16038 if (tmp != count_exp)
16039 emit_move_insn (count_exp, tmp);
16041 emit_label (label);
16042 LABEL_NUSES (label) = 1;
16044 if (count_exp != const0_rtx && epilogue_size_needed > 1)
16046 if (force_loopy_epilogue)
16047 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
16050 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
16053 if (jump_around_label)
16054 emit_label (jump_around_label);
16058 /* Expand the appropriate insns for doing strlen if not just doing
16061 out = result, initialized with the start address
16062 align_rtx = alignment of the address.
16063 scratch = scratch register, initialized with the startaddress when
16064 not aligned, otherwise undefined
16066 This is just the body. It needs the initializations mentioned above and
16067 some address computing at the end. These things are done in i386.md. */
16070 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
16074 rtx align_2_label = NULL_RTX;
16075 rtx align_3_label = NULL_RTX;
16076 rtx align_4_label = gen_label_rtx ();
16077 rtx end_0_label = gen_label_rtx ();
16079 rtx tmpreg = gen_reg_rtx (SImode);
16080 rtx scratch = gen_reg_rtx (SImode);
16084 if (CONST_INT_P (align_rtx))
16085 align = INTVAL (align_rtx);
16087 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
16089 /* Is there a known alignment and is it less than 4? */
16092 rtx scratch1 = gen_reg_rtx (Pmode);
16093 emit_move_insn (scratch1, out);
16094 /* Is there a known alignment and is it not 2? */
16097 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
16098 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
16100 /* Leave just the 3 lower bits. */
16101 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
16102 NULL_RTX, 0, OPTAB_WIDEN);
16104 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
16105 Pmode, 1, align_4_label);
16106 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
16107 Pmode, 1, align_2_label);
16108 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
16109 Pmode, 1, align_3_label);
16113 /* Since the alignment is 2, we have to check 2 or 0 bytes;
16114 check if is aligned to 4 - byte. */
16116 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
16117 NULL_RTX, 0, OPTAB_WIDEN);
16119 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
16120 Pmode, 1, align_4_label);
16123 mem = change_address (src, QImode, out);
16125 /* Now compare the bytes. */
16127 /* Compare the first n unaligned byte on a byte per byte basis. */
16128 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
16129 QImode, 1, end_0_label);
16131 /* Increment the address. */
16133 emit_insn (gen_adddi3 (out, out, const1_rtx));
16135 emit_insn (gen_addsi3 (out, out, const1_rtx));
16137 /* Not needed with an alignment of 2 */
16140 emit_label (align_2_label);
16142 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16146 emit_insn (gen_adddi3 (out, out, const1_rtx));
16148 emit_insn (gen_addsi3 (out, out, const1_rtx));
16150 emit_label (align_3_label);
16153 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16157 emit_insn (gen_adddi3 (out, out, const1_rtx));
16159 emit_insn (gen_addsi3 (out, out, const1_rtx));
16162 /* Generate loop to check 4 bytes at a time. It is not a good idea to
16163 align this loop. It gives only huge programs, but does not help to
16165 emit_label (align_4_label);
16167 mem = change_address (src, SImode, out);
16168 emit_move_insn (scratch, mem);
16170 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
16172 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
16174 /* This formula yields a nonzero result iff one of the bytes is zero.
16175 This saves three branches inside loop and many cycles. */
16177 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
16178 emit_insn (gen_one_cmplsi2 (scratch, scratch));
16179 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
16180 emit_insn (gen_andsi3 (tmpreg, tmpreg,
16181 gen_int_mode (0x80808080, SImode)));
16182 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
16187 rtx reg = gen_reg_rtx (SImode);
16188 rtx reg2 = gen_reg_rtx (Pmode);
16189 emit_move_insn (reg, tmpreg);
16190 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
16192 /* If zero is not in the first two bytes, move two bytes forward. */
16193 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16194 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16195 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16196 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
16197 gen_rtx_IF_THEN_ELSE (SImode, tmp,
16200 /* Emit lea manually to avoid clobbering of flags. */
16201 emit_insn (gen_rtx_SET (SImode, reg2,
16202 gen_rtx_PLUS (Pmode, out, const2_rtx)));
16204 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16205 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16206 emit_insn (gen_rtx_SET (VOIDmode, out,
16207 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
16214 rtx end_2_label = gen_label_rtx ();
16215 /* Is zero in the first two bytes? */
16217 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16218 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16219 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
16220 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
16221 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
16223 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
16224 JUMP_LABEL (tmp) = end_2_label;
16226 /* Not in the first two. Move two bytes forward. */
16227 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
16229 emit_insn (gen_adddi3 (out, out, const2_rtx));
16231 emit_insn (gen_addsi3 (out, out, const2_rtx));
16233 emit_label (end_2_label);
16237 /* Avoid branch in fixing the byte. */
16238 tmpreg = gen_lowpart (QImode, tmpreg);
16239 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
16240 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
16242 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
16244 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
16246 emit_label (end_0_label);
16249 /* Expand strlen. */
16252 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
16254 rtx addr, scratch1, scratch2, scratch3, scratch4;
16256 /* The generic case of strlen expander is long. Avoid it's
16257 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
16259 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16260 && !TARGET_INLINE_ALL_STRINGOPS
16262 && (!CONST_INT_P (align) || INTVAL (align) < 4))
16265 addr = force_reg (Pmode, XEXP (src, 0));
16266 scratch1 = gen_reg_rtx (Pmode);
16268 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16271 /* Well it seems that some optimizer does not combine a call like
16272 foo(strlen(bar), strlen(bar));
16273 when the move and the subtraction is done here. It does calculate
16274 the length just once when these instructions are done inside of
16275 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
16276 often used and I use one fewer register for the lifetime of
16277 output_strlen_unroll() this is better. */
16279 emit_move_insn (out, addr);
16281 ix86_expand_strlensi_unroll_1 (out, src, align);
16283 /* strlensi_unroll_1 returns the address of the zero at the end of
16284 the string, like memchr(), so compute the length by subtracting
16285 the start address. */
16287 emit_insn (gen_subdi3 (out, out, addr));
16289 emit_insn (gen_subsi3 (out, out, addr));
16295 /* Can't use this if the user has appropriated eax, ecx, or edi. */
16296 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
16299 scratch2 = gen_reg_rtx (Pmode);
16300 scratch3 = gen_reg_rtx (Pmode);
16301 scratch4 = force_reg (Pmode, constm1_rtx);
16303 emit_move_insn (scratch3, addr);
16304 eoschar = force_reg (QImode, eoschar);
16306 src = replace_equiv_address_nv (src, scratch3);
16308 /* If .md starts supporting :P, this can be done in .md. */
16309 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
16310 scratch4), UNSPEC_SCAS);
16311 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
16314 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
16315 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
16319 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
16320 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
16326 /* For given symbol (function) construct code to compute address of it's PLT
16327 entry in large x86-64 PIC model. */
16329 construct_plt_address (rtx symbol)
16331 rtx tmp = gen_reg_rtx (Pmode);
16332 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
16334 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16335 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
16337 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
16338 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
16343 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
16344 rtx callarg2 ATTRIBUTE_UNUSED,
16345 rtx pop, int sibcall)
16347 rtx use = NULL, call;
16349 if (pop == const0_rtx)
16351 gcc_assert (!TARGET_64BIT || !pop);
16353 if (TARGET_MACHO && !TARGET_64BIT)
16356 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
16357 fnaddr = machopic_indirect_call_target (fnaddr);
16362 /* Static functions and indirect calls don't need the pic register. */
16363 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
16364 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16365 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
16366 use_reg (&use, pic_offset_table_rtx);
16369 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
16371 rtx al = gen_rtx_REG (QImode, AX_REG);
16372 emit_move_insn (al, callarg2);
16373 use_reg (&use, al);
16376 if (ix86_cmodel == CM_LARGE_PIC
16377 && GET_CODE (fnaddr) == MEM
16378 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16379 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
16380 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
16381 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
16383 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16384 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16386 if (sibcall && TARGET_64BIT
16387 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
16390 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16391 fnaddr = gen_rtx_REG (Pmode, R11_REG);
16392 emit_move_insn (fnaddr, addr);
16393 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16396 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
16398 call = gen_rtx_SET (VOIDmode, retval, call);
16401 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
16402 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
16403 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
16406 call = emit_call_insn (call);
16408 CALL_INSN_FUNCTION_USAGE (call) = use;
16412 /* Clear stack slot assignments remembered from previous functions.
16413 This is called from INIT_EXPANDERS once before RTL is emitted for each
16416 static struct machine_function *
16417 ix86_init_machine_status (void)
16419 struct machine_function *f;
16421 f = GGC_CNEW (struct machine_function);
16422 f->use_fast_prologue_epilogue_nregs = -1;
16423 f->tls_descriptor_call_expanded_p = 0;
16428 /* Return a MEM corresponding to a stack slot with mode MODE.
16429 Allocate a new slot if necessary.
16431 The RTL for a function can have several slots available: N is
16432 which slot to use. */
16435 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
16437 struct stack_local_entry *s;
16439 gcc_assert (n < MAX_386_STACK_LOCALS);
16441 /* Virtual slot is valid only before vregs are instantiated. */
16442 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
16444 for (s = ix86_stack_locals; s; s = s->next)
16445 if (s->mode == mode && s->n == n)
16446 return copy_rtx (s->rtl);
16448 s = (struct stack_local_entry *)
16449 ggc_alloc (sizeof (struct stack_local_entry));
16452 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
16454 s->next = ix86_stack_locals;
16455 ix86_stack_locals = s;
16459 /* Construct the SYMBOL_REF for the tls_get_addr function. */
16461 static GTY(()) rtx ix86_tls_symbol;
16463 ix86_tls_get_addr (void)
16466 if (!ix86_tls_symbol)
16468 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
16469 (TARGET_ANY_GNU_TLS
16471 ? "___tls_get_addr"
16472 : "__tls_get_addr");
16475 return ix86_tls_symbol;
16478 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
16480 static GTY(()) rtx ix86_tls_module_base_symbol;
16482 ix86_tls_module_base (void)
16485 if (!ix86_tls_module_base_symbol)
16487 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
16488 "_TLS_MODULE_BASE_");
16489 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
16490 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
16493 return ix86_tls_module_base_symbol;
16496 /* Calculate the length of the memory address in the instruction
16497 encoding. Does not include the one-byte modrm, opcode, or prefix. */
16500 memory_address_length (rtx addr)
16502 struct ix86_address parts;
16503 rtx base, index, disp;
16507 if (GET_CODE (addr) == PRE_DEC
16508 || GET_CODE (addr) == POST_INC
16509 || GET_CODE (addr) == PRE_MODIFY
16510 || GET_CODE (addr) == POST_MODIFY)
16513 ok = ix86_decompose_address (addr, &parts);
16516 if (parts.base && GET_CODE (parts.base) == SUBREG)
16517 parts.base = SUBREG_REG (parts.base);
16518 if (parts.index && GET_CODE (parts.index) == SUBREG)
16519 parts.index = SUBREG_REG (parts.index);
16522 index = parts.index;
16527 - esp as the base always wants an index,
16528 - ebp as the base always wants a displacement. */
16530 /* Register Indirect. */
16531 if (base && !index && !disp)
16533 /* esp (for its index) and ebp (for its displacement) need
16534 the two-byte modrm form. */
16535 if (addr == stack_pointer_rtx
16536 || addr == arg_pointer_rtx
16537 || addr == frame_pointer_rtx
16538 || addr == hard_frame_pointer_rtx)
16542 /* Direct Addressing. */
16543 else if (disp && !base && !index)
16548 /* Find the length of the displacement constant. */
16551 if (base && satisfies_constraint_K (disp))
16556 /* ebp always wants a displacement. */
16557 else if (base == hard_frame_pointer_rtx)
16560 /* An index requires the two-byte modrm form.... */
16562 /* ...like esp, which always wants an index. */
16563 || base == stack_pointer_rtx
16564 || base == arg_pointer_rtx
16565 || base == frame_pointer_rtx)
16572 /* Compute default value for "length_immediate" attribute. When SHORTFORM
16573 is set, expect that insn have 8bit immediate alternative. */
16575 ix86_attr_length_immediate_default (rtx insn, int shortform)
16579 extract_insn_cached (insn);
16580 for (i = recog_data.n_operands - 1; i >= 0; --i)
16581 if (CONSTANT_P (recog_data.operand[i]))
16584 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
16588 switch (get_attr_mode (insn))
16599 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
16604 fatal_insn ("unknown insn mode", insn);
16610 /* Compute default value for "length_address" attribute. */
16612 ix86_attr_length_address_default (rtx insn)
16616 if (get_attr_type (insn) == TYPE_LEA)
16618 rtx set = PATTERN (insn);
16620 if (GET_CODE (set) == PARALLEL)
16621 set = XVECEXP (set, 0, 0);
16623 gcc_assert (GET_CODE (set) == SET);
16625 return memory_address_length (SET_SRC (set));
16628 extract_insn_cached (insn);
16629 for (i = recog_data.n_operands - 1; i >= 0; --i)
16630 if (MEM_P (recog_data.operand[i]))
16632 return memory_address_length (XEXP (recog_data.operand[i], 0));
16638 /* Return the maximum number of instructions a cpu can issue. */
16641 ix86_issue_rate (void)
16645 case PROCESSOR_PENTIUM:
16649 case PROCESSOR_PENTIUMPRO:
16650 case PROCESSOR_PENTIUM4:
16651 case PROCESSOR_ATHLON:
16653 case PROCESSOR_AMDFAM10:
16654 case PROCESSOR_NOCONA:
16655 case PROCESSOR_GENERIC32:
16656 case PROCESSOR_GENERIC64:
16659 case PROCESSOR_CORE2:
16667 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
16668 by DEP_INSN and nothing set by DEP_INSN. */
16671 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16675 /* Simplify the test for uninteresting insns. */
16676 if (insn_type != TYPE_SETCC
16677 && insn_type != TYPE_ICMOV
16678 && insn_type != TYPE_FCMOV
16679 && insn_type != TYPE_IBR)
16682 if ((set = single_set (dep_insn)) != 0)
16684 set = SET_DEST (set);
16687 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
16688 && XVECLEN (PATTERN (dep_insn), 0) == 2
16689 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
16690 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
16692 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16693 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16698 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
16701 /* This test is true if the dependent insn reads the flags but
16702 not any other potentially set register. */
16703 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
16706 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
16712 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
16713 address with operands set by DEP_INSN. */
16716 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16720 if (insn_type == TYPE_LEA
16723 addr = PATTERN (insn);
16725 if (GET_CODE (addr) == PARALLEL)
16726 addr = XVECEXP (addr, 0, 0);
16728 gcc_assert (GET_CODE (addr) == SET);
16730 addr = SET_SRC (addr);
16735 extract_insn_cached (insn);
16736 for (i = recog_data.n_operands - 1; i >= 0; --i)
16737 if (MEM_P (recog_data.operand[i]))
16739 addr = XEXP (recog_data.operand[i], 0);
16746 return modified_in_p (addr, dep_insn);
16750 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16752 enum attr_type insn_type, dep_insn_type;
16753 enum attr_memory memory;
16755 int dep_insn_code_number;
16757 /* Anti and output dependencies have zero cost on all CPUs. */
16758 if (REG_NOTE_KIND (link) != 0)
16761 dep_insn_code_number = recog_memoized (dep_insn);
16763 /* If we can't recognize the insns, we can't really do anything. */
16764 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
16767 insn_type = get_attr_type (insn);
16768 dep_insn_type = get_attr_type (dep_insn);
16772 case PROCESSOR_PENTIUM:
16773 /* Address Generation Interlock adds a cycle of latency. */
16774 if (ix86_agi_dependent (insn, dep_insn, insn_type))
16777 /* ??? Compares pair with jump/setcc. */
16778 if (ix86_flags_dependent (insn, dep_insn, insn_type))
16781 /* Floating point stores require value to be ready one cycle earlier. */
16782 if (insn_type == TYPE_FMOV
16783 && get_attr_memory (insn) == MEMORY_STORE
16784 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16788 case PROCESSOR_PENTIUMPRO:
16789 memory = get_attr_memory (insn);
16791 /* INT->FP conversion is expensive. */
16792 if (get_attr_fp_int_src (dep_insn))
16795 /* There is one cycle extra latency between an FP op and a store. */
16796 if (insn_type == TYPE_FMOV
16797 && (set = single_set (dep_insn)) != NULL_RTX
16798 && (set2 = single_set (insn)) != NULL_RTX
16799 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
16800 && MEM_P (SET_DEST (set2)))
16803 /* Show ability of reorder buffer to hide latency of load by executing
16804 in parallel with previous instruction in case
16805 previous instruction is not needed to compute the address. */
16806 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16807 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16809 /* Claim moves to take one cycle, as core can issue one load
16810 at time and the next load can start cycle later. */
16811 if (dep_insn_type == TYPE_IMOV
16812 || dep_insn_type == TYPE_FMOV)
16820 memory = get_attr_memory (insn);
16822 /* The esp dependency is resolved before the instruction is really
16824 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
16825 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
16828 /* INT->FP conversion is expensive. */
16829 if (get_attr_fp_int_src (dep_insn))
16832 /* Show ability of reorder buffer to hide latency of load by executing
16833 in parallel with previous instruction in case
16834 previous instruction is not needed to compute the address. */
16835 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16836 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16838 /* Claim moves to take one cycle, as core can issue one load
16839 at time and the next load can start cycle later. */
16840 if (dep_insn_type == TYPE_IMOV
16841 || dep_insn_type == TYPE_FMOV)
16850 case PROCESSOR_ATHLON:
16852 case PROCESSOR_AMDFAM10:
16853 case PROCESSOR_GENERIC32:
16854 case PROCESSOR_GENERIC64:
16855 memory = get_attr_memory (insn);
16857 /* Show ability of reorder buffer to hide latency of load by executing
16858 in parallel with previous instruction in case
16859 previous instruction is not needed to compute the address. */
16860 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16861 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16863 enum attr_unit unit = get_attr_unit (insn);
16866 /* Because of the difference between the length of integer and
16867 floating unit pipeline preparation stages, the memory operands
16868 for floating point are cheaper.
16870 ??? For Athlon it the difference is most probably 2. */
16871 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
16874 loadcost = TARGET_ATHLON ? 2 : 0;
16876 if (cost >= loadcost)
16889 /* How many alternative schedules to try. This should be as wide as the
16890 scheduling freedom in the DFA, but no wider. Making this value too
16891 large results extra work for the scheduler. */
16894 ia32_multipass_dfa_lookahead (void)
16898 case PROCESSOR_PENTIUM:
16901 case PROCESSOR_PENTIUMPRO:
16911 /* Compute the alignment given to a constant that is being placed in memory.
16912 EXP is the constant and ALIGN is the alignment that the object would
16914 The value of this function is used instead of that alignment to align
16918 ix86_constant_alignment (tree exp, int align)
16920 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
16921 || TREE_CODE (exp) == INTEGER_CST)
16923 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
16925 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
16928 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
16929 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
16930 return BITS_PER_WORD;
16935 /* Compute the alignment for a static variable.
16936 TYPE is the data type, and ALIGN is the alignment that
16937 the object would ordinarily have. The value of this function is used
16938 instead of that alignment to align the object. */
16941 ix86_data_alignment (tree type, int align)
16943 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
16945 if (AGGREGATE_TYPE_P (type)
16946 && TYPE_SIZE (type)
16947 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16948 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
16949 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
16950 && align < max_align)
16953 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16954 to 16byte boundary. */
16957 if (AGGREGATE_TYPE_P (type)
16958 && TYPE_SIZE (type)
16959 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16960 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
16961 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16965 if (TREE_CODE (type) == ARRAY_TYPE)
16967 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16969 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16972 else if (TREE_CODE (type) == COMPLEX_TYPE)
16975 if (TYPE_MODE (type) == DCmode && align < 64)
16977 if (TYPE_MODE (type) == XCmode && align < 128)
16980 else if ((TREE_CODE (type) == RECORD_TYPE
16981 || TREE_CODE (type) == UNION_TYPE
16982 || TREE_CODE (type) == QUAL_UNION_TYPE)
16983 && TYPE_FIELDS (type))
16985 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16987 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16990 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16991 || TREE_CODE (type) == INTEGER_TYPE)
16993 if (TYPE_MODE (type) == DFmode && align < 64)
16995 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
17002 /* Compute the alignment for a local variable or a stack slot. TYPE is
17003 the data type, MODE is the widest mode available and ALIGN is the
17004 alignment that the object would ordinarily have. The value of this
17005 macro is used instead of that alignment to align the object. */
17008 ix86_local_alignment (tree type, enum machine_mode mode,
17009 unsigned int align)
17011 /* If TYPE is NULL, we are allocating a stack slot for caller-save
17012 register in MODE. We will return the largest alignment of XF
17016 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
17017 align = GET_MODE_ALIGNMENT (DFmode);
17021 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
17022 to 16byte boundary. */
17025 if (AGGREGATE_TYPE_P (type)
17026 && TYPE_SIZE (type)
17027 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
17028 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
17029 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
17032 if (TREE_CODE (type) == ARRAY_TYPE)
17034 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
17036 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
17039 else if (TREE_CODE (type) == COMPLEX_TYPE)
17041 if (TYPE_MODE (type) == DCmode && align < 64)
17043 if (TYPE_MODE (type) == XCmode && align < 128)
17046 else if ((TREE_CODE (type) == RECORD_TYPE
17047 || TREE_CODE (type) == UNION_TYPE
17048 || TREE_CODE (type) == QUAL_UNION_TYPE)
17049 && TYPE_FIELDS (type))
17051 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
17053 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
17056 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
17057 || TREE_CODE (type) == INTEGER_TYPE)
17060 if (TYPE_MODE (type) == DFmode && align < 64)
17062 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
17068 /* Emit RTL insns to initialize the variable parts of a trampoline.
17069 FNADDR is an RTX for the address of the function's pure code.
17070 CXT is an RTX for the static chain value for the function. */
17072 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
17076 /* Compute offset from the end of the jmp to the target function. */
17077 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
17078 plus_constant (tramp, 10),
17079 NULL_RTX, 1, OPTAB_DIRECT);
17080 emit_move_insn (gen_rtx_MEM (QImode, tramp),
17081 gen_int_mode (0xb9, QImode));
17082 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
17083 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
17084 gen_int_mode (0xe9, QImode));
17085 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
17090 /* Try to load address using shorter movl instead of movabs.
17091 We may want to support movq for kernel mode, but kernel does not use
17092 trampolines at the moment. */
17093 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
17095 fnaddr = copy_to_mode_reg (DImode, fnaddr);
17096 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17097 gen_int_mode (0xbb41, HImode));
17098 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
17099 gen_lowpart (SImode, fnaddr));
17104 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17105 gen_int_mode (0xbb49, HImode));
17106 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
17110 /* Load static chain using movabs to r10. */
17111 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17112 gen_int_mode (0xba49, HImode));
17113 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
17116 /* Jump to the r11 */
17117 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17118 gen_int_mode (0xff49, HImode));
17119 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
17120 gen_int_mode (0xe3, QImode));
17122 gcc_assert (offset <= TRAMPOLINE_SIZE);
17125 #ifdef ENABLE_EXECUTE_STACK
17126 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
17127 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
17131 /* Codes for all the SSE/MMX builtins. */
17134 IX86_BUILTIN_ADDPS,
17135 IX86_BUILTIN_ADDSS,
17136 IX86_BUILTIN_DIVPS,
17137 IX86_BUILTIN_DIVSS,
17138 IX86_BUILTIN_MULPS,
17139 IX86_BUILTIN_MULSS,
17140 IX86_BUILTIN_SUBPS,
17141 IX86_BUILTIN_SUBSS,
17143 IX86_BUILTIN_CMPEQPS,
17144 IX86_BUILTIN_CMPLTPS,
17145 IX86_BUILTIN_CMPLEPS,
17146 IX86_BUILTIN_CMPGTPS,
17147 IX86_BUILTIN_CMPGEPS,
17148 IX86_BUILTIN_CMPNEQPS,
17149 IX86_BUILTIN_CMPNLTPS,
17150 IX86_BUILTIN_CMPNLEPS,
17151 IX86_BUILTIN_CMPNGTPS,
17152 IX86_BUILTIN_CMPNGEPS,
17153 IX86_BUILTIN_CMPORDPS,
17154 IX86_BUILTIN_CMPUNORDPS,
17155 IX86_BUILTIN_CMPEQSS,
17156 IX86_BUILTIN_CMPLTSS,
17157 IX86_BUILTIN_CMPLESS,
17158 IX86_BUILTIN_CMPNEQSS,
17159 IX86_BUILTIN_CMPNLTSS,
17160 IX86_BUILTIN_CMPNLESS,
17161 IX86_BUILTIN_CMPNGTSS,
17162 IX86_BUILTIN_CMPNGESS,
17163 IX86_BUILTIN_CMPORDSS,
17164 IX86_BUILTIN_CMPUNORDSS,
17166 IX86_BUILTIN_COMIEQSS,
17167 IX86_BUILTIN_COMILTSS,
17168 IX86_BUILTIN_COMILESS,
17169 IX86_BUILTIN_COMIGTSS,
17170 IX86_BUILTIN_COMIGESS,
17171 IX86_BUILTIN_COMINEQSS,
17172 IX86_BUILTIN_UCOMIEQSS,
17173 IX86_BUILTIN_UCOMILTSS,
17174 IX86_BUILTIN_UCOMILESS,
17175 IX86_BUILTIN_UCOMIGTSS,
17176 IX86_BUILTIN_UCOMIGESS,
17177 IX86_BUILTIN_UCOMINEQSS,
17179 IX86_BUILTIN_CVTPI2PS,
17180 IX86_BUILTIN_CVTPS2PI,
17181 IX86_BUILTIN_CVTSI2SS,
17182 IX86_BUILTIN_CVTSI642SS,
17183 IX86_BUILTIN_CVTSS2SI,
17184 IX86_BUILTIN_CVTSS2SI64,
17185 IX86_BUILTIN_CVTTPS2PI,
17186 IX86_BUILTIN_CVTTSS2SI,
17187 IX86_BUILTIN_CVTTSS2SI64,
17189 IX86_BUILTIN_MAXPS,
17190 IX86_BUILTIN_MAXSS,
17191 IX86_BUILTIN_MINPS,
17192 IX86_BUILTIN_MINSS,
17194 IX86_BUILTIN_LOADUPS,
17195 IX86_BUILTIN_STOREUPS,
17196 IX86_BUILTIN_MOVSS,
17198 IX86_BUILTIN_MOVHLPS,
17199 IX86_BUILTIN_MOVLHPS,
17200 IX86_BUILTIN_LOADHPS,
17201 IX86_BUILTIN_LOADLPS,
17202 IX86_BUILTIN_STOREHPS,
17203 IX86_BUILTIN_STORELPS,
17205 IX86_BUILTIN_MASKMOVQ,
17206 IX86_BUILTIN_MOVMSKPS,
17207 IX86_BUILTIN_PMOVMSKB,
17209 IX86_BUILTIN_MOVNTPS,
17210 IX86_BUILTIN_MOVNTQ,
17212 IX86_BUILTIN_LOADDQU,
17213 IX86_BUILTIN_STOREDQU,
17215 IX86_BUILTIN_PACKSSWB,
17216 IX86_BUILTIN_PACKSSDW,
17217 IX86_BUILTIN_PACKUSWB,
17219 IX86_BUILTIN_PADDB,
17220 IX86_BUILTIN_PADDW,
17221 IX86_BUILTIN_PADDD,
17222 IX86_BUILTIN_PADDQ,
17223 IX86_BUILTIN_PADDSB,
17224 IX86_BUILTIN_PADDSW,
17225 IX86_BUILTIN_PADDUSB,
17226 IX86_BUILTIN_PADDUSW,
17227 IX86_BUILTIN_PSUBB,
17228 IX86_BUILTIN_PSUBW,
17229 IX86_BUILTIN_PSUBD,
17230 IX86_BUILTIN_PSUBQ,
17231 IX86_BUILTIN_PSUBSB,
17232 IX86_BUILTIN_PSUBSW,
17233 IX86_BUILTIN_PSUBUSB,
17234 IX86_BUILTIN_PSUBUSW,
17237 IX86_BUILTIN_PANDN,
17241 IX86_BUILTIN_PAVGB,
17242 IX86_BUILTIN_PAVGW,
17244 IX86_BUILTIN_PCMPEQB,
17245 IX86_BUILTIN_PCMPEQW,
17246 IX86_BUILTIN_PCMPEQD,
17247 IX86_BUILTIN_PCMPGTB,
17248 IX86_BUILTIN_PCMPGTW,
17249 IX86_BUILTIN_PCMPGTD,
17251 IX86_BUILTIN_PMADDWD,
17253 IX86_BUILTIN_PMAXSW,
17254 IX86_BUILTIN_PMAXUB,
17255 IX86_BUILTIN_PMINSW,
17256 IX86_BUILTIN_PMINUB,
17258 IX86_BUILTIN_PMULHUW,
17259 IX86_BUILTIN_PMULHW,
17260 IX86_BUILTIN_PMULLW,
17262 IX86_BUILTIN_PSADBW,
17263 IX86_BUILTIN_PSHUFW,
17265 IX86_BUILTIN_PSLLW,
17266 IX86_BUILTIN_PSLLD,
17267 IX86_BUILTIN_PSLLQ,
17268 IX86_BUILTIN_PSRAW,
17269 IX86_BUILTIN_PSRAD,
17270 IX86_BUILTIN_PSRLW,
17271 IX86_BUILTIN_PSRLD,
17272 IX86_BUILTIN_PSRLQ,
17273 IX86_BUILTIN_PSLLWI,
17274 IX86_BUILTIN_PSLLDI,
17275 IX86_BUILTIN_PSLLQI,
17276 IX86_BUILTIN_PSRAWI,
17277 IX86_BUILTIN_PSRADI,
17278 IX86_BUILTIN_PSRLWI,
17279 IX86_BUILTIN_PSRLDI,
17280 IX86_BUILTIN_PSRLQI,
17282 IX86_BUILTIN_PUNPCKHBW,
17283 IX86_BUILTIN_PUNPCKHWD,
17284 IX86_BUILTIN_PUNPCKHDQ,
17285 IX86_BUILTIN_PUNPCKLBW,
17286 IX86_BUILTIN_PUNPCKLWD,
17287 IX86_BUILTIN_PUNPCKLDQ,
17289 IX86_BUILTIN_SHUFPS,
17291 IX86_BUILTIN_RCPPS,
17292 IX86_BUILTIN_RCPSS,
17293 IX86_BUILTIN_RSQRTPS,
17294 IX86_BUILTIN_RSQRTPS_NR,
17295 IX86_BUILTIN_RSQRTSS,
17296 IX86_BUILTIN_RSQRTF,
17297 IX86_BUILTIN_SQRTPS,
17298 IX86_BUILTIN_SQRTPS_NR,
17299 IX86_BUILTIN_SQRTSS,
17301 IX86_BUILTIN_UNPCKHPS,
17302 IX86_BUILTIN_UNPCKLPS,
17304 IX86_BUILTIN_ANDPS,
17305 IX86_BUILTIN_ANDNPS,
17307 IX86_BUILTIN_XORPS,
17310 IX86_BUILTIN_LDMXCSR,
17311 IX86_BUILTIN_STMXCSR,
17312 IX86_BUILTIN_SFENCE,
17314 /* 3DNow! Original */
17315 IX86_BUILTIN_FEMMS,
17316 IX86_BUILTIN_PAVGUSB,
17317 IX86_BUILTIN_PF2ID,
17318 IX86_BUILTIN_PFACC,
17319 IX86_BUILTIN_PFADD,
17320 IX86_BUILTIN_PFCMPEQ,
17321 IX86_BUILTIN_PFCMPGE,
17322 IX86_BUILTIN_PFCMPGT,
17323 IX86_BUILTIN_PFMAX,
17324 IX86_BUILTIN_PFMIN,
17325 IX86_BUILTIN_PFMUL,
17326 IX86_BUILTIN_PFRCP,
17327 IX86_BUILTIN_PFRCPIT1,
17328 IX86_BUILTIN_PFRCPIT2,
17329 IX86_BUILTIN_PFRSQIT1,
17330 IX86_BUILTIN_PFRSQRT,
17331 IX86_BUILTIN_PFSUB,
17332 IX86_BUILTIN_PFSUBR,
17333 IX86_BUILTIN_PI2FD,
17334 IX86_BUILTIN_PMULHRW,
17336 /* 3DNow! Athlon Extensions */
17337 IX86_BUILTIN_PF2IW,
17338 IX86_BUILTIN_PFNACC,
17339 IX86_BUILTIN_PFPNACC,
17340 IX86_BUILTIN_PI2FW,
17341 IX86_BUILTIN_PSWAPDSI,
17342 IX86_BUILTIN_PSWAPDSF,
17345 IX86_BUILTIN_ADDPD,
17346 IX86_BUILTIN_ADDSD,
17347 IX86_BUILTIN_DIVPD,
17348 IX86_BUILTIN_DIVSD,
17349 IX86_BUILTIN_MULPD,
17350 IX86_BUILTIN_MULSD,
17351 IX86_BUILTIN_SUBPD,
17352 IX86_BUILTIN_SUBSD,
17354 IX86_BUILTIN_CMPEQPD,
17355 IX86_BUILTIN_CMPLTPD,
17356 IX86_BUILTIN_CMPLEPD,
17357 IX86_BUILTIN_CMPGTPD,
17358 IX86_BUILTIN_CMPGEPD,
17359 IX86_BUILTIN_CMPNEQPD,
17360 IX86_BUILTIN_CMPNLTPD,
17361 IX86_BUILTIN_CMPNLEPD,
17362 IX86_BUILTIN_CMPNGTPD,
17363 IX86_BUILTIN_CMPNGEPD,
17364 IX86_BUILTIN_CMPORDPD,
17365 IX86_BUILTIN_CMPUNORDPD,
17366 IX86_BUILTIN_CMPEQSD,
17367 IX86_BUILTIN_CMPLTSD,
17368 IX86_BUILTIN_CMPLESD,
17369 IX86_BUILTIN_CMPNEQSD,
17370 IX86_BUILTIN_CMPNLTSD,
17371 IX86_BUILTIN_CMPNLESD,
17372 IX86_BUILTIN_CMPORDSD,
17373 IX86_BUILTIN_CMPUNORDSD,
17375 IX86_BUILTIN_COMIEQSD,
17376 IX86_BUILTIN_COMILTSD,
17377 IX86_BUILTIN_COMILESD,
17378 IX86_BUILTIN_COMIGTSD,
17379 IX86_BUILTIN_COMIGESD,
17380 IX86_BUILTIN_COMINEQSD,
17381 IX86_BUILTIN_UCOMIEQSD,
17382 IX86_BUILTIN_UCOMILTSD,
17383 IX86_BUILTIN_UCOMILESD,
17384 IX86_BUILTIN_UCOMIGTSD,
17385 IX86_BUILTIN_UCOMIGESD,
17386 IX86_BUILTIN_UCOMINEQSD,
17388 IX86_BUILTIN_MAXPD,
17389 IX86_BUILTIN_MAXSD,
17390 IX86_BUILTIN_MINPD,
17391 IX86_BUILTIN_MINSD,
17393 IX86_BUILTIN_ANDPD,
17394 IX86_BUILTIN_ANDNPD,
17396 IX86_BUILTIN_XORPD,
17398 IX86_BUILTIN_SQRTPD,
17399 IX86_BUILTIN_SQRTSD,
17401 IX86_BUILTIN_UNPCKHPD,
17402 IX86_BUILTIN_UNPCKLPD,
17404 IX86_BUILTIN_SHUFPD,
17406 IX86_BUILTIN_LOADUPD,
17407 IX86_BUILTIN_STOREUPD,
17408 IX86_BUILTIN_MOVSD,
17410 IX86_BUILTIN_LOADHPD,
17411 IX86_BUILTIN_LOADLPD,
17413 IX86_BUILTIN_CVTDQ2PD,
17414 IX86_BUILTIN_CVTDQ2PS,
17416 IX86_BUILTIN_CVTPD2DQ,
17417 IX86_BUILTIN_CVTPD2PI,
17418 IX86_BUILTIN_CVTPD2PS,
17419 IX86_BUILTIN_CVTTPD2DQ,
17420 IX86_BUILTIN_CVTTPD2PI,
17422 IX86_BUILTIN_CVTPI2PD,
17423 IX86_BUILTIN_CVTSI2SD,
17424 IX86_BUILTIN_CVTSI642SD,
17426 IX86_BUILTIN_CVTSD2SI,
17427 IX86_BUILTIN_CVTSD2SI64,
17428 IX86_BUILTIN_CVTSD2SS,
17429 IX86_BUILTIN_CVTSS2SD,
17430 IX86_BUILTIN_CVTTSD2SI,
17431 IX86_BUILTIN_CVTTSD2SI64,
17433 IX86_BUILTIN_CVTPS2DQ,
17434 IX86_BUILTIN_CVTPS2PD,
17435 IX86_BUILTIN_CVTTPS2DQ,
17437 IX86_BUILTIN_MOVNTI,
17438 IX86_BUILTIN_MOVNTPD,
17439 IX86_BUILTIN_MOVNTDQ,
17442 IX86_BUILTIN_MASKMOVDQU,
17443 IX86_BUILTIN_MOVMSKPD,
17444 IX86_BUILTIN_PMOVMSKB128,
17446 IX86_BUILTIN_PACKSSWB128,
17447 IX86_BUILTIN_PACKSSDW128,
17448 IX86_BUILTIN_PACKUSWB128,
17450 IX86_BUILTIN_PADDB128,
17451 IX86_BUILTIN_PADDW128,
17452 IX86_BUILTIN_PADDD128,
17453 IX86_BUILTIN_PADDQ128,
17454 IX86_BUILTIN_PADDSB128,
17455 IX86_BUILTIN_PADDSW128,
17456 IX86_BUILTIN_PADDUSB128,
17457 IX86_BUILTIN_PADDUSW128,
17458 IX86_BUILTIN_PSUBB128,
17459 IX86_BUILTIN_PSUBW128,
17460 IX86_BUILTIN_PSUBD128,
17461 IX86_BUILTIN_PSUBQ128,
17462 IX86_BUILTIN_PSUBSB128,
17463 IX86_BUILTIN_PSUBSW128,
17464 IX86_BUILTIN_PSUBUSB128,
17465 IX86_BUILTIN_PSUBUSW128,
17467 IX86_BUILTIN_PAND128,
17468 IX86_BUILTIN_PANDN128,
17469 IX86_BUILTIN_POR128,
17470 IX86_BUILTIN_PXOR128,
17472 IX86_BUILTIN_PAVGB128,
17473 IX86_BUILTIN_PAVGW128,
17475 IX86_BUILTIN_PCMPEQB128,
17476 IX86_BUILTIN_PCMPEQW128,
17477 IX86_BUILTIN_PCMPEQD128,
17478 IX86_BUILTIN_PCMPGTB128,
17479 IX86_BUILTIN_PCMPGTW128,
17480 IX86_BUILTIN_PCMPGTD128,
17482 IX86_BUILTIN_PMADDWD128,
17484 IX86_BUILTIN_PMAXSW128,
17485 IX86_BUILTIN_PMAXUB128,
17486 IX86_BUILTIN_PMINSW128,
17487 IX86_BUILTIN_PMINUB128,
17489 IX86_BUILTIN_PMULUDQ,
17490 IX86_BUILTIN_PMULUDQ128,
17491 IX86_BUILTIN_PMULHUW128,
17492 IX86_BUILTIN_PMULHW128,
17493 IX86_BUILTIN_PMULLW128,
17495 IX86_BUILTIN_PSADBW128,
17496 IX86_BUILTIN_PSHUFHW,
17497 IX86_BUILTIN_PSHUFLW,
17498 IX86_BUILTIN_PSHUFD,
17500 IX86_BUILTIN_PSLLDQI128,
17501 IX86_BUILTIN_PSLLWI128,
17502 IX86_BUILTIN_PSLLDI128,
17503 IX86_BUILTIN_PSLLQI128,
17504 IX86_BUILTIN_PSRAWI128,
17505 IX86_BUILTIN_PSRADI128,
17506 IX86_BUILTIN_PSRLDQI128,
17507 IX86_BUILTIN_PSRLWI128,
17508 IX86_BUILTIN_PSRLDI128,
17509 IX86_BUILTIN_PSRLQI128,
17511 IX86_BUILTIN_PSLLDQ128,
17512 IX86_BUILTIN_PSLLW128,
17513 IX86_BUILTIN_PSLLD128,
17514 IX86_BUILTIN_PSLLQ128,
17515 IX86_BUILTIN_PSRAW128,
17516 IX86_BUILTIN_PSRAD128,
17517 IX86_BUILTIN_PSRLW128,
17518 IX86_BUILTIN_PSRLD128,
17519 IX86_BUILTIN_PSRLQ128,
17521 IX86_BUILTIN_PUNPCKHBW128,
17522 IX86_BUILTIN_PUNPCKHWD128,
17523 IX86_BUILTIN_PUNPCKHDQ128,
17524 IX86_BUILTIN_PUNPCKHQDQ128,
17525 IX86_BUILTIN_PUNPCKLBW128,
17526 IX86_BUILTIN_PUNPCKLWD128,
17527 IX86_BUILTIN_PUNPCKLDQ128,
17528 IX86_BUILTIN_PUNPCKLQDQ128,
17530 IX86_BUILTIN_CLFLUSH,
17531 IX86_BUILTIN_MFENCE,
17532 IX86_BUILTIN_LFENCE,
17535 IX86_BUILTIN_ADDSUBPS,
17536 IX86_BUILTIN_HADDPS,
17537 IX86_BUILTIN_HSUBPS,
17538 IX86_BUILTIN_MOVSHDUP,
17539 IX86_BUILTIN_MOVSLDUP,
17540 IX86_BUILTIN_ADDSUBPD,
17541 IX86_BUILTIN_HADDPD,
17542 IX86_BUILTIN_HSUBPD,
17543 IX86_BUILTIN_LDDQU,
17545 IX86_BUILTIN_MONITOR,
17546 IX86_BUILTIN_MWAIT,
17549 IX86_BUILTIN_PHADDW,
17550 IX86_BUILTIN_PHADDD,
17551 IX86_BUILTIN_PHADDSW,
17552 IX86_BUILTIN_PHSUBW,
17553 IX86_BUILTIN_PHSUBD,
17554 IX86_BUILTIN_PHSUBSW,
17555 IX86_BUILTIN_PMADDUBSW,
17556 IX86_BUILTIN_PMULHRSW,
17557 IX86_BUILTIN_PSHUFB,
17558 IX86_BUILTIN_PSIGNB,
17559 IX86_BUILTIN_PSIGNW,
17560 IX86_BUILTIN_PSIGND,
17561 IX86_BUILTIN_PALIGNR,
17562 IX86_BUILTIN_PABSB,
17563 IX86_BUILTIN_PABSW,
17564 IX86_BUILTIN_PABSD,
17566 IX86_BUILTIN_PHADDW128,
17567 IX86_BUILTIN_PHADDD128,
17568 IX86_BUILTIN_PHADDSW128,
17569 IX86_BUILTIN_PHSUBW128,
17570 IX86_BUILTIN_PHSUBD128,
17571 IX86_BUILTIN_PHSUBSW128,
17572 IX86_BUILTIN_PMADDUBSW128,
17573 IX86_BUILTIN_PMULHRSW128,
17574 IX86_BUILTIN_PSHUFB128,
17575 IX86_BUILTIN_PSIGNB128,
17576 IX86_BUILTIN_PSIGNW128,
17577 IX86_BUILTIN_PSIGND128,
17578 IX86_BUILTIN_PALIGNR128,
17579 IX86_BUILTIN_PABSB128,
17580 IX86_BUILTIN_PABSW128,
17581 IX86_BUILTIN_PABSD128,
17583 /* AMDFAM10 - SSE4A New Instructions. */
17584 IX86_BUILTIN_MOVNTSD,
17585 IX86_BUILTIN_MOVNTSS,
17586 IX86_BUILTIN_EXTRQI,
17587 IX86_BUILTIN_EXTRQ,
17588 IX86_BUILTIN_INSERTQI,
17589 IX86_BUILTIN_INSERTQ,
17592 IX86_BUILTIN_BLENDPD,
17593 IX86_BUILTIN_BLENDPS,
17594 IX86_BUILTIN_BLENDVPD,
17595 IX86_BUILTIN_BLENDVPS,
17596 IX86_BUILTIN_PBLENDVB128,
17597 IX86_BUILTIN_PBLENDW128,
17602 IX86_BUILTIN_INSERTPS128,
17604 IX86_BUILTIN_MOVNTDQA,
17605 IX86_BUILTIN_MPSADBW128,
17606 IX86_BUILTIN_PACKUSDW128,
17607 IX86_BUILTIN_PCMPEQQ,
17608 IX86_BUILTIN_PHMINPOSUW128,
17610 IX86_BUILTIN_PMAXSB128,
17611 IX86_BUILTIN_PMAXSD128,
17612 IX86_BUILTIN_PMAXUD128,
17613 IX86_BUILTIN_PMAXUW128,
17615 IX86_BUILTIN_PMINSB128,
17616 IX86_BUILTIN_PMINSD128,
17617 IX86_BUILTIN_PMINUD128,
17618 IX86_BUILTIN_PMINUW128,
17620 IX86_BUILTIN_PMOVSXBW128,
17621 IX86_BUILTIN_PMOVSXBD128,
17622 IX86_BUILTIN_PMOVSXBQ128,
17623 IX86_BUILTIN_PMOVSXWD128,
17624 IX86_BUILTIN_PMOVSXWQ128,
17625 IX86_BUILTIN_PMOVSXDQ128,
17627 IX86_BUILTIN_PMOVZXBW128,
17628 IX86_BUILTIN_PMOVZXBD128,
17629 IX86_BUILTIN_PMOVZXBQ128,
17630 IX86_BUILTIN_PMOVZXWD128,
17631 IX86_BUILTIN_PMOVZXWQ128,
17632 IX86_BUILTIN_PMOVZXDQ128,
17634 IX86_BUILTIN_PMULDQ128,
17635 IX86_BUILTIN_PMULLD128,
17637 IX86_BUILTIN_ROUNDPD,
17638 IX86_BUILTIN_ROUNDPS,
17639 IX86_BUILTIN_ROUNDSD,
17640 IX86_BUILTIN_ROUNDSS,
17642 IX86_BUILTIN_PTESTZ,
17643 IX86_BUILTIN_PTESTC,
17644 IX86_BUILTIN_PTESTNZC,
17646 IX86_BUILTIN_VEC_INIT_V2SI,
17647 IX86_BUILTIN_VEC_INIT_V4HI,
17648 IX86_BUILTIN_VEC_INIT_V8QI,
17649 IX86_BUILTIN_VEC_EXT_V2DF,
17650 IX86_BUILTIN_VEC_EXT_V2DI,
17651 IX86_BUILTIN_VEC_EXT_V4SF,
17652 IX86_BUILTIN_VEC_EXT_V4SI,
17653 IX86_BUILTIN_VEC_EXT_V8HI,
17654 IX86_BUILTIN_VEC_EXT_V2SI,
17655 IX86_BUILTIN_VEC_EXT_V4HI,
17656 IX86_BUILTIN_VEC_EXT_V16QI,
17657 IX86_BUILTIN_VEC_SET_V2DI,
17658 IX86_BUILTIN_VEC_SET_V4SF,
17659 IX86_BUILTIN_VEC_SET_V4SI,
17660 IX86_BUILTIN_VEC_SET_V8HI,
17661 IX86_BUILTIN_VEC_SET_V4HI,
17662 IX86_BUILTIN_VEC_SET_V16QI,
17664 IX86_BUILTIN_VEC_PACK_SFIX,
17667 IX86_BUILTIN_CRC32QI,
17668 IX86_BUILTIN_CRC32HI,
17669 IX86_BUILTIN_CRC32SI,
17670 IX86_BUILTIN_CRC32DI,
17672 IX86_BUILTIN_PCMPESTRI128,
17673 IX86_BUILTIN_PCMPESTRM128,
17674 IX86_BUILTIN_PCMPESTRA128,
17675 IX86_BUILTIN_PCMPESTRC128,
17676 IX86_BUILTIN_PCMPESTRO128,
17677 IX86_BUILTIN_PCMPESTRS128,
17678 IX86_BUILTIN_PCMPESTRZ128,
17679 IX86_BUILTIN_PCMPISTRI128,
17680 IX86_BUILTIN_PCMPISTRM128,
17681 IX86_BUILTIN_PCMPISTRA128,
17682 IX86_BUILTIN_PCMPISTRC128,
17683 IX86_BUILTIN_PCMPISTRO128,
17684 IX86_BUILTIN_PCMPISTRS128,
17685 IX86_BUILTIN_PCMPISTRZ128,
17687 IX86_BUILTIN_PCMPGTQ,
17689 /* AES instructions */
17690 IX86_BUILTIN_AESENC128,
17691 IX86_BUILTIN_AESENCLAST128,
17692 IX86_BUILTIN_AESDEC128,
17693 IX86_BUILTIN_AESDECLAST128,
17694 IX86_BUILTIN_AESIMC128,
17695 IX86_BUILTIN_AESKEYGENASSIST128,
17697 /* PCLMUL instruction */
17698 IX86_BUILTIN_PCLMULQDQ128,
17700 /* TFmode support builtins. */
17702 IX86_BUILTIN_FABSQ,
17703 IX86_BUILTIN_COPYSIGNQ,
17705 /* SSE5 instructions */
17706 IX86_BUILTIN_FMADDSS,
17707 IX86_BUILTIN_FMADDSD,
17708 IX86_BUILTIN_FMADDPS,
17709 IX86_BUILTIN_FMADDPD,
17710 IX86_BUILTIN_FMSUBSS,
17711 IX86_BUILTIN_FMSUBSD,
17712 IX86_BUILTIN_FMSUBPS,
17713 IX86_BUILTIN_FMSUBPD,
17714 IX86_BUILTIN_FNMADDSS,
17715 IX86_BUILTIN_FNMADDSD,
17716 IX86_BUILTIN_FNMADDPS,
17717 IX86_BUILTIN_FNMADDPD,
17718 IX86_BUILTIN_FNMSUBSS,
17719 IX86_BUILTIN_FNMSUBSD,
17720 IX86_BUILTIN_FNMSUBPS,
17721 IX86_BUILTIN_FNMSUBPD,
17722 IX86_BUILTIN_PCMOV_V2DI,
17723 IX86_BUILTIN_PCMOV_V4SI,
17724 IX86_BUILTIN_PCMOV_V8HI,
17725 IX86_BUILTIN_PCMOV_V16QI,
17726 IX86_BUILTIN_PCMOV_V4SF,
17727 IX86_BUILTIN_PCMOV_V2DF,
17728 IX86_BUILTIN_PPERM,
17729 IX86_BUILTIN_PERMPS,
17730 IX86_BUILTIN_PERMPD,
17731 IX86_BUILTIN_PMACSSWW,
17732 IX86_BUILTIN_PMACSWW,
17733 IX86_BUILTIN_PMACSSWD,
17734 IX86_BUILTIN_PMACSWD,
17735 IX86_BUILTIN_PMACSSDD,
17736 IX86_BUILTIN_PMACSDD,
17737 IX86_BUILTIN_PMACSSDQL,
17738 IX86_BUILTIN_PMACSSDQH,
17739 IX86_BUILTIN_PMACSDQL,
17740 IX86_BUILTIN_PMACSDQH,
17741 IX86_BUILTIN_PMADCSSWD,
17742 IX86_BUILTIN_PMADCSWD,
17743 IX86_BUILTIN_PHADDBW,
17744 IX86_BUILTIN_PHADDBD,
17745 IX86_BUILTIN_PHADDBQ,
17746 IX86_BUILTIN_PHADDWD,
17747 IX86_BUILTIN_PHADDWQ,
17748 IX86_BUILTIN_PHADDDQ,
17749 IX86_BUILTIN_PHADDUBW,
17750 IX86_BUILTIN_PHADDUBD,
17751 IX86_BUILTIN_PHADDUBQ,
17752 IX86_BUILTIN_PHADDUWD,
17753 IX86_BUILTIN_PHADDUWQ,
17754 IX86_BUILTIN_PHADDUDQ,
17755 IX86_BUILTIN_PHSUBBW,
17756 IX86_BUILTIN_PHSUBWD,
17757 IX86_BUILTIN_PHSUBDQ,
17758 IX86_BUILTIN_PROTB,
17759 IX86_BUILTIN_PROTW,
17760 IX86_BUILTIN_PROTD,
17761 IX86_BUILTIN_PROTQ,
17762 IX86_BUILTIN_PROTB_IMM,
17763 IX86_BUILTIN_PROTW_IMM,
17764 IX86_BUILTIN_PROTD_IMM,
17765 IX86_BUILTIN_PROTQ_IMM,
17766 IX86_BUILTIN_PSHLB,
17767 IX86_BUILTIN_PSHLW,
17768 IX86_BUILTIN_PSHLD,
17769 IX86_BUILTIN_PSHLQ,
17770 IX86_BUILTIN_PSHAB,
17771 IX86_BUILTIN_PSHAW,
17772 IX86_BUILTIN_PSHAD,
17773 IX86_BUILTIN_PSHAQ,
17774 IX86_BUILTIN_FRCZSS,
17775 IX86_BUILTIN_FRCZSD,
17776 IX86_BUILTIN_FRCZPS,
17777 IX86_BUILTIN_FRCZPD,
17778 IX86_BUILTIN_CVTPH2PS,
17779 IX86_BUILTIN_CVTPS2PH,
17781 IX86_BUILTIN_COMEQSS,
17782 IX86_BUILTIN_COMNESS,
17783 IX86_BUILTIN_COMLTSS,
17784 IX86_BUILTIN_COMLESS,
17785 IX86_BUILTIN_COMGTSS,
17786 IX86_BUILTIN_COMGESS,
17787 IX86_BUILTIN_COMUEQSS,
17788 IX86_BUILTIN_COMUNESS,
17789 IX86_BUILTIN_COMULTSS,
17790 IX86_BUILTIN_COMULESS,
17791 IX86_BUILTIN_COMUGTSS,
17792 IX86_BUILTIN_COMUGESS,
17793 IX86_BUILTIN_COMORDSS,
17794 IX86_BUILTIN_COMUNORDSS,
17795 IX86_BUILTIN_COMFALSESS,
17796 IX86_BUILTIN_COMTRUESS,
17798 IX86_BUILTIN_COMEQSD,
17799 IX86_BUILTIN_COMNESD,
17800 IX86_BUILTIN_COMLTSD,
17801 IX86_BUILTIN_COMLESD,
17802 IX86_BUILTIN_COMGTSD,
17803 IX86_BUILTIN_COMGESD,
17804 IX86_BUILTIN_COMUEQSD,
17805 IX86_BUILTIN_COMUNESD,
17806 IX86_BUILTIN_COMULTSD,
17807 IX86_BUILTIN_COMULESD,
17808 IX86_BUILTIN_COMUGTSD,
17809 IX86_BUILTIN_COMUGESD,
17810 IX86_BUILTIN_COMORDSD,
17811 IX86_BUILTIN_COMUNORDSD,
17812 IX86_BUILTIN_COMFALSESD,
17813 IX86_BUILTIN_COMTRUESD,
17815 IX86_BUILTIN_COMEQPS,
17816 IX86_BUILTIN_COMNEPS,
17817 IX86_BUILTIN_COMLTPS,
17818 IX86_BUILTIN_COMLEPS,
17819 IX86_BUILTIN_COMGTPS,
17820 IX86_BUILTIN_COMGEPS,
17821 IX86_BUILTIN_COMUEQPS,
17822 IX86_BUILTIN_COMUNEPS,
17823 IX86_BUILTIN_COMULTPS,
17824 IX86_BUILTIN_COMULEPS,
17825 IX86_BUILTIN_COMUGTPS,
17826 IX86_BUILTIN_COMUGEPS,
17827 IX86_BUILTIN_COMORDPS,
17828 IX86_BUILTIN_COMUNORDPS,
17829 IX86_BUILTIN_COMFALSEPS,
17830 IX86_BUILTIN_COMTRUEPS,
17832 IX86_BUILTIN_COMEQPD,
17833 IX86_BUILTIN_COMNEPD,
17834 IX86_BUILTIN_COMLTPD,
17835 IX86_BUILTIN_COMLEPD,
17836 IX86_BUILTIN_COMGTPD,
17837 IX86_BUILTIN_COMGEPD,
17838 IX86_BUILTIN_COMUEQPD,
17839 IX86_BUILTIN_COMUNEPD,
17840 IX86_BUILTIN_COMULTPD,
17841 IX86_BUILTIN_COMULEPD,
17842 IX86_BUILTIN_COMUGTPD,
17843 IX86_BUILTIN_COMUGEPD,
17844 IX86_BUILTIN_COMORDPD,
17845 IX86_BUILTIN_COMUNORDPD,
17846 IX86_BUILTIN_COMFALSEPD,
17847 IX86_BUILTIN_COMTRUEPD,
17849 IX86_BUILTIN_PCOMEQUB,
17850 IX86_BUILTIN_PCOMNEUB,
17851 IX86_BUILTIN_PCOMLTUB,
17852 IX86_BUILTIN_PCOMLEUB,
17853 IX86_BUILTIN_PCOMGTUB,
17854 IX86_BUILTIN_PCOMGEUB,
17855 IX86_BUILTIN_PCOMFALSEUB,
17856 IX86_BUILTIN_PCOMTRUEUB,
17857 IX86_BUILTIN_PCOMEQUW,
17858 IX86_BUILTIN_PCOMNEUW,
17859 IX86_BUILTIN_PCOMLTUW,
17860 IX86_BUILTIN_PCOMLEUW,
17861 IX86_BUILTIN_PCOMGTUW,
17862 IX86_BUILTIN_PCOMGEUW,
17863 IX86_BUILTIN_PCOMFALSEUW,
17864 IX86_BUILTIN_PCOMTRUEUW,
17865 IX86_BUILTIN_PCOMEQUD,
17866 IX86_BUILTIN_PCOMNEUD,
17867 IX86_BUILTIN_PCOMLTUD,
17868 IX86_BUILTIN_PCOMLEUD,
17869 IX86_BUILTIN_PCOMGTUD,
17870 IX86_BUILTIN_PCOMGEUD,
17871 IX86_BUILTIN_PCOMFALSEUD,
17872 IX86_BUILTIN_PCOMTRUEUD,
17873 IX86_BUILTIN_PCOMEQUQ,
17874 IX86_BUILTIN_PCOMNEUQ,
17875 IX86_BUILTIN_PCOMLTUQ,
17876 IX86_BUILTIN_PCOMLEUQ,
17877 IX86_BUILTIN_PCOMGTUQ,
17878 IX86_BUILTIN_PCOMGEUQ,
17879 IX86_BUILTIN_PCOMFALSEUQ,
17880 IX86_BUILTIN_PCOMTRUEUQ,
17882 IX86_BUILTIN_PCOMEQB,
17883 IX86_BUILTIN_PCOMNEB,
17884 IX86_BUILTIN_PCOMLTB,
17885 IX86_BUILTIN_PCOMLEB,
17886 IX86_BUILTIN_PCOMGTB,
17887 IX86_BUILTIN_PCOMGEB,
17888 IX86_BUILTIN_PCOMFALSEB,
17889 IX86_BUILTIN_PCOMTRUEB,
17890 IX86_BUILTIN_PCOMEQW,
17891 IX86_BUILTIN_PCOMNEW,
17892 IX86_BUILTIN_PCOMLTW,
17893 IX86_BUILTIN_PCOMLEW,
17894 IX86_BUILTIN_PCOMGTW,
17895 IX86_BUILTIN_PCOMGEW,
17896 IX86_BUILTIN_PCOMFALSEW,
17897 IX86_BUILTIN_PCOMTRUEW,
17898 IX86_BUILTIN_PCOMEQD,
17899 IX86_BUILTIN_PCOMNED,
17900 IX86_BUILTIN_PCOMLTD,
17901 IX86_BUILTIN_PCOMLED,
17902 IX86_BUILTIN_PCOMGTD,
17903 IX86_BUILTIN_PCOMGED,
17904 IX86_BUILTIN_PCOMFALSED,
17905 IX86_BUILTIN_PCOMTRUED,
17906 IX86_BUILTIN_PCOMEQQ,
17907 IX86_BUILTIN_PCOMNEQ,
17908 IX86_BUILTIN_PCOMLTQ,
17909 IX86_BUILTIN_PCOMLEQ,
17910 IX86_BUILTIN_PCOMGTQ,
17911 IX86_BUILTIN_PCOMGEQ,
17912 IX86_BUILTIN_PCOMFALSEQ,
17913 IX86_BUILTIN_PCOMTRUEQ,
17918 /* Table for the ix86 builtin decls. */
17919 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
17921 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
17922 * if the target_flags include one of MASK. Stores the function decl
17923 * in the ix86_builtins array.
17924 * Returns the function decl or NULL_TREE, if the builtin was not added. */
17927 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
17929 tree decl = NULL_TREE;
17931 if (mask & ix86_isa_flags
17932 && (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT))
17934 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
17936 ix86_builtins[(int) code] = decl;
17942 /* Like def_builtin, but also marks the function decl "const". */
17945 def_builtin_const (int mask, const char *name, tree type,
17946 enum ix86_builtins code)
17948 tree decl = def_builtin (mask, name, type, code);
17950 TREE_READONLY (decl) = 1;
17954 /* Bits for builtin_description.flag. */
17956 /* Set when we don't support the comparison natively, and should
17957 swap_comparison in order to support it. */
17958 #define BUILTIN_DESC_SWAP_OPERANDS 1
17960 struct builtin_description
17962 const unsigned int mask;
17963 const enum insn_code icode;
17964 const char *const name;
17965 const enum ix86_builtins code;
17966 const enum rtx_code comparison;
17970 static const struct builtin_description bdesc_comi[] =
17972 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
17973 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
17974 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
17975 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
17976 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
17977 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
17978 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
17979 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
17980 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
17981 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
17982 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
17983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
17984 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
17985 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
17986 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
17987 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
17988 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
17989 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
17990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
17991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
17992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
17993 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
17994 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
17995 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
17998 static const struct builtin_description bdesc_pcmpestr[] =
18001 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
18002 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
18003 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
18004 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
18005 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
18006 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
18007 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
18010 static const struct builtin_description bdesc_pcmpistr[] =
18013 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
18014 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
18015 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
18016 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
18017 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
18018 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
18019 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
18022 /* Special builtin types */
18023 enum ix86_special_builtin_type
18025 SPECIAL_FTYPE_UNKNOWN,
18027 V16QI_FTYPE_PCCHAR,
18028 V4SF_FTYPE_PCFLOAT,
18029 V2DF_FTYPE_PCDOUBLE,
18030 V4SF_FTYPE_V4SF_PCV2SF,
18031 V2DF_FTYPE_V2DF_PCDOUBLE,
18033 VOID_FTYPE_PV2SF_V4SF,
18034 VOID_FTYPE_PV2DI_V2DI,
18035 VOID_FTYPE_PCHAR_V16QI,
18036 VOID_FTYPE_PFLOAT_V4SF,
18037 VOID_FTYPE_PDOUBLE_V2DF,
18039 VOID_FTYPE_PINT_INT
18042 /* Builtin types */
18043 enum ix86_builtin_type
18046 FLOAT128_FTYPE_FLOAT128,
18048 FLOAT128_FTYPE_FLOAT128_FLOAT128,
18049 INT_FTYPE_V2DI_V2DI_PTEST,
18067 V4SF_FTYPE_V4SF_VEC_MERGE,
18075 V2DF_FTYPE_V2DF_VEC_MERGE,
18085 V16QI_FTYPE_V16QI_V16QI,
18086 V16QI_FTYPE_V8HI_V8HI,
18087 V8QI_FTYPE_V8QI_V8QI,
18088 V8QI_FTYPE_V4HI_V4HI,
18089 V8HI_FTYPE_V8HI_V8HI,
18090 V8HI_FTYPE_V8HI_V8HI_COUNT,
18091 V8HI_FTYPE_V16QI_V16QI,
18092 V8HI_FTYPE_V4SI_V4SI,
18093 V8HI_FTYPE_V8HI_SI_COUNT,
18094 V4SI_FTYPE_V4SI_V4SI,
18095 V4SI_FTYPE_V4SI_V4SI_COUNT,
18096 V4SI_FTYPE_V8HI_V8HI,
18097 V4SI_FTYPE_V4SF_V4SF,
18098 V4SI_FTYPE_V2DF_V2DF,
18099 V4SI_FTYPE_V4SI_SI_COUNT,
18100 V4HI_FTYPE_V4HI_V4HI,
18101 V4HI_FTYPE_V4HI_V4HI_COUNT,
18102 V4HI_FTYPE_V8QI_V8QI,
18103 V4HI_FTYPE_V2SI_V2SI,
18104 V4HI_FTYPE_V4HI_SI_COUNT,
18105 V4SF_FTYPE_V4SF_V4SF,
18106 V4SF_FTYPE_V4SF_V4SF_SWAP,
18107 V4SF_FTYPE_V4SF_V2SI,
18108 V4SF_FTYPE_V4SF_V2DF,
18109 V4SF_FTYPE_V4SF_DI,
18110 V4SF_FTYPE_V4SF_SI,
18111 V2DI_FTYPE_V2DI_V2DI,
18112 V2DI_FTYPE_V2DI_V2DI_COUNT,
18113 V2DI_FTYPE_V16QI_V16QI,
18114 V2DI_FTYPE_V4SI_V4SI,
18115 V2DI_FTYPE_V2DI_V16QI,
18116 V2DI_FTYPE_V2DF_V2DF,
18117 V2DI_FTYPE_V2DI_SI_COUNT,
18118 V2SI_FTYPE_V2SI_V2SI,
18119 V2SI_FTYPE_V2SI_V2SI_COUNT,
18120 V2SI_FTYPE_V4HI_V4HI,
18121 V2SI_FTYPE_V2SF_V2SF,
18122 V2SI_FTYPE_V2SI_SI_COUNT,
18123 V2DF_FTYPE_V2DF_V2DF,
18124 V2DF_FTYPE_V2DF_V2DF_SWAP,
18125 V2DF_FTYPE_V2DF_V4SF,
18126 V2DF_FTYPE_V2DF_DI,
18127 V2DF_FTYPE_V2DF_SI,
18128 V2SF_FTYPE_V2SF_V2SF,
18129 V1DI_FTYPE_V1DI_V1DI,
18130 V1DI_FTYPE_V1DI_V1DI_COUNT,
18131 V1DI_FTYPE_V8QI_V8QI,
18132 V1DI_FTYPE_V2SI_V2SI,
18133 V1DI_FTYPE_V1DI_SI_COUNT,
18134 UINT64_FTYPE_UINT64_UINT64,
18135 UINT_FTYPE_UINT_UINT,
18136 UINT_FTYPE_UINT_USHORT,
18137 UINT_FTYPE_UINT_UCHAR,
18138 V8HI_FTYPE_V8HI_INT,
18139 V4SI_FTYPE_V4SI_INT,
18140 V4HI_FTYPE_V4HI_INT,
18141 V4SF_FTYPE_V4SF_INT,
18142 V2DI_FTYPE_V2DI_INT,
18143 V2DI2TI_FTYPE_V2DI_INT,
18144 V2DF_FTYPE_V2DF_INT,
18145 V16QI_FTYPE_V16QI_V16QI_V16QI,
18146 V4SF_FTYPE_V4SF_V4SF_V4SF,
18147 V2DF_FTYPE_V2DF_V2DF_V2DF,
18148 V16QI_FTYPE_V16QI_V16QI_INT,
18149 V8HI_FTYPE_V8HI_V8HI_INT,
18150 V4SI_FTYPE_V4SI_V4SI_INT,
18151 V4SF_FTYPE_V4SF_V4SF_INT,
18152 V2DI_FTYPE_V2DI_V2DI_INT,
18153 V2DI2TI_FTYPE_V2DI_V2DI_INT,
18154 V1DI2DI_FTYPE_V1DI_V1DI_INT,
18155 V2DF_FTYPE_V2DF_V2DF_INT,
18156 V2DI_FTYPE_V2DI_UINT_UINT,
18157 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
18160 /* Special builtins with variable number of arguments. */
18161 static const struct builtin_description bdesc_special_args[] =
18164 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
18167 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
18170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
18171 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
18172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
18174 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
18175 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
18176 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
18177 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
18179 /* SSE or 3DNow!A */
18180 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
18181 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
18184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
18185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
18186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
18187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
18188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
18189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
18190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
18191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
18192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
18194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
18195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
18198 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
18201 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
18204 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
18205 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
18208 /* Builtins with variable number of arguments. */
18209 static const struct builtin_description bdesc_args[] =
18212 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18213 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18214 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18215 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18216 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18217 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18219 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18220 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18221 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18222 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18223 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18224 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18225 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18226 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18228 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18231 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18232 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18233 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18234 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18236 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18237 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18240 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18241 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18243 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18244 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18245 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18246 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18247 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
18248 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
18250 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
18251 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
18252 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
18254 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
18256 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
18257 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
18258 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
18259 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
18260 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
18261 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
18263 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
18264 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
18265 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
18266 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
18267 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
18268 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
18270 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
18271 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
18272 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
18273 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
18276 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
18277 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
18278 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18279 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18281 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18282 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18283 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18284 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
18285 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
18286 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
18287 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18288 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18289 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18290 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18291 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18292 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18293 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18294 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18295 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18298 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
18299 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
18300 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
18301 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18302 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18303 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
18306 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
18307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18308 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18309 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18310 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18312 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
18313 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
18314 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
18315 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
18316 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
18317 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
18319 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18321 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18322 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18323 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18325 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18326 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18327 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18328 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18330 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
18331 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
18332 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
18333 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18334 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18335 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
18336 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
18337 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
18338 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
18339 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18340 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
18341 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
18342 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
18343 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
18344 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
18345 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
18346 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
18347 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
18348 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
18349 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18350 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
18351 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
18353 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18354 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18355 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18356 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18358 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18359 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18360 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18361 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18363 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18364 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18365 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18366 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18367 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18369 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
18370 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
18371 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
18373 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
18375 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
18376 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
18377 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
18379 /* SSE MMX or 3Dnow!A */
18380 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18381 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18382 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18384 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18385 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18386 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18387 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18389 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
18390 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
18392 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
18395 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
18398 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
18399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
18400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
18401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
18403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
18404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
18405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
18406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
18407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
18409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
18411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
18412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
18413 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
18414 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
18416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
18417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
18418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
18420 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18421 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18422 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18423 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18424 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18426 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18429 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
18430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
18431 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
18432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
18433 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
18434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
18435 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
18436 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
18437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
18438 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
18439 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
18440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
18441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
18442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
18443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
18444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
18445 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
18446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
18447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
18448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
18450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18451 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18455 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18457 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18458 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18464 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
18466 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18467 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18468 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18469 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18470 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18471 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18472 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18473 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18477 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18481 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18484 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18485 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
18487 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18489 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18490 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18502 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18503 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18504 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
18517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
18518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
18520 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
18523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
18524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
18526 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
18528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
18529 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
18530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
18531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
18533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
18534 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
18535 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
18536 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
18537 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
18538 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
18539 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
18541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
18542 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
18543 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
18544 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
18545 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
18546 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
18547 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
18549 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
18550 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
18551 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
18552 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
18554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
18555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
18556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
18558 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
18561 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
18562 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
18565 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
18566 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18568 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18569 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18570 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18571 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18572 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
18573 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
18576 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
18577 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
18578 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
18579 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
18580 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
18581 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
18583 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18584 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18585 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18586 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18587 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18588 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18589 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18590 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18591 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18592 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18593 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18594 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18595 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
18596 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
18597 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18598 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18599 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18600 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18601 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18602 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
18603 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18604 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
18605 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18606 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
18609 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
18610 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
18613 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18614 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18615 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
18616 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
18617 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18618 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18619 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18620 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
18621 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
18622 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
18624 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
18625 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
18626 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
18627 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
18628 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
18629 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
18630 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
18631 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
18632 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
18633 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
18634 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
18635 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
18636 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
18638 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
18639 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18640 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18641 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18642 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18643 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18644 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
18645 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18646 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18647 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
18648 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
18649 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
18651 /* SSE4.1 and SSE5 */
18652 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
18653 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
18654 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18655 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18657 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
18658 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
18659 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
18662 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18663 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
18664 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
18665 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
18666 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
18669 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
18670 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
18671 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
18672 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18675 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
18676 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
18678 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18679 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18680 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18681 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
18684 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
18687 { OPTION_MASK_ISA_64BIT, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
18688 { OPTION_MASK_ISA_64BIT, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
18692 enum multi_arg_type {
18702 MULTI_ARG_3_PERMPS,
18703 MULTI_ARG_3_PERMPD,
18710 MULTI_ARG_2_DI_IMM,
18711 MULTI_ARG_2_SI_IMM,
18712 MULTI_ARG_2_HI_IMM,
18713 MULTI_ARG_2_QI_IMM,
18714 MULTI_ARG_2_SF_CMP,
18715 MULTI_ARG_2_DF_CMP,
18716 MULTI_ARG_2_DI_CMP,
18717 MULTI_ARG_2_SI_CMP,
18718 MULTI_ARG_2_HI_CMP,
18719 MULTI_ARG_2_QI_CMP,
18742 static const struct builtin_description bdesc_multi_arg[] =
18744 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
18745 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
18746 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
18747 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
18748 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
18749 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
18750 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
18751 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
18752 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
18753 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
18754 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
18755 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
18756 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
18757 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
18758 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
18759 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
18760 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18761 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18762 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
18763 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
18764 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
18765 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
18766 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
18767 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
18768 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
18769 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
18770 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
18771 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
18772 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18773 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
18774 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
18775 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
18776 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18777 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18778 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18779 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18780 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18781 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
18782 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
18783 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
18784 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
18785 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
18786 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
18787 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
18788 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
18789 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
18790 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
18791 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
18792 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
18793 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
18794 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
18795 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
18796 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
18797 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
18798 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
18799 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
18800 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
18801 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
18802 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
18803 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
18804 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
18805 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
18806 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
18807 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
18808 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
18809 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
18810 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
18811 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
18812 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
18813 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
18814 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
18815 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
18816 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
18817 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
18818 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
18820 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
18821 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18822 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18823 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
18824 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
18825 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
18826 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
18827 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18828 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18829 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18830 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18831 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18832 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18833 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18834 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18835 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18837 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
18838 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18839 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18840 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
18841 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
18842 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
18843 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
18844 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18845 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18846 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18847 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18848 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18849 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18850 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18851 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18852 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18854 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
18855 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18856 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18857 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
18858 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
18859 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
18860 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
18861 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18862 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18863 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18864 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18865 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18866 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18867 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18868 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18869 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18871 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
18872 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18873 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18874 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
18875 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
18876 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
18877 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
18878 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18879 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18880 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18881 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18882 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18883 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18884 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18885 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18886 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18888 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
18889 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18890 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18891 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
18892 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
18893 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
18894 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
18896 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
18897 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18898 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18899 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
18900 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
18901 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
18902 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
18904 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
18905 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18906 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18907 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
18908 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
18909 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
18910 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
18912 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18913 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18914 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18915 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
18916 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
18917 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
18918 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
18920 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
18921 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18922 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18923 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
18924 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
18925 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
18926 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
18928 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
18929 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18930 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18931 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
18932 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
18933 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
18934 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
18936 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
18937 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18938 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18939 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
18940 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
18941 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
18942 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
18944 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18945 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18946 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18947 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
18948 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
18949 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
18950 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
18952 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
18953 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
18954 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
18955 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
18956 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
18957 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
18958 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
18959 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
18961 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18962 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18963 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18964 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18965 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18966 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18967 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18968 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18970 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18971 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18972 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18973 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18974 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18975 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18976 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18977 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18980 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
18981 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
18984 ix86_init_mmx_sse_builtins (void)
18986 const struct builtin_description * d;
18989 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
18990 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
18991 tree V1DI_type_node
18992 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
18993 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
18994 tree V2DI_type_node
18995 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
18996 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
18997 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
18998 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
18999 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
19000 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
19001 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
19003 tree pchar_type_node = build_pointer_type (char_type_node);
19004 tree pcchar_type_node
19005 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
19006 tree pfloat_type_node = build_pointer_type (float_type_node);
19007 tree pcfloat_type_node
19008 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
19009 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
19010 tree pcv2sf_type_node
19011 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
19012 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
19013 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
19016 tree int_ftype_v4sf_v4sf
19017 = build_function_type_list (integer_type_node,
19018 V4SF_type_node, V4SF_type_node, NULL_TREE);
19019 tree v4si_ftype_v4sf_v4sf
19020 = build_function_type_list (V4SI_type_node,
19021 V4SF_type_node, V4SF_type_node, NULL_TREE);
19022 /* MMX/SSE/integer conversions. */
19023 tree int_ftype_v4sf
19024 = build_function_type_list (integer_type_node,
19025 V4SF_type_node, NULL_TREE);
19026 tree int64_ftype_v4sf
19027 = build_function_type_list (long_long_integer_type_node,
19028 V4SF_type_node, NULL_TREE);
19029 tree int_ftype_v8qi
19030 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
19031 tree v4sf_ftype_v4sf_int
19032 = build_function_type_list (V4SF_type_node,
19033 V4SF_type_node, integer_type_node, NULL_TREE);
19034 tree v4sf_ftype_v4sf_int64
19035 = build_function_type_list (V4SF_type_node,
19036 V4SF_type_node, long_long_integer_type_node,
19038 tree v4sf_ftype_v4sf_v2si
19039 = build_function_type_list (V4SF_type_node,
19040 V4SF_type_node, V2SI_type_node, NULL_TREE);
19042 /* Miscellaneous. */
19043 tree v8qi_ftype_v4hi_v4hi
19044 = build_function_type_list (V8QI_type_node,
19045 V4HI_type_node, V4HI_type_node, NULL_TREE);
19046 tree v4hi_ftype_v2si_v2si
19047 = build_function_type_list (V4HI_type_node,
19048 V2SI_type_node, V2SI_type_node, NULL_TREE);
19049 tree v4sf_ftype_v4sf_v4sf_int
19050 = build_function_type_list (V4SF_type_node,
19051 V4SF_type_node, V4SF_type_node,
19052 integer_type_node, NULL_TREE);
19053 tree v2si_ftype_v4hi_v4hi
19054 = build_function_type_list (V2SI_type_node,
19055 V4HI_type_node, V4HI_type_node, NULL_TREE);
19056 tree v4hi_ftype_v4hi_int
19057 = build_function_type_list (V4HI_type_node,
19058 V4HI_type_node, integer_type_node, NULL_TREE);
19059 tree v2si_ftype_v2si_int
19060 = build_function_type_list (V2SI_type_node,
19061 V2SI_type_node, integer_type_node, NULL_TREE);
19062 tree v1di_ftype_v1di_int
19063 = build_function_type_list (V1DI_type_node,
19064 V1DI_type_node, integer_type_node, NULL_TREE);
19066 tree void_ftype_void
19067 = build_function_type (void_type_node, void_list_node);
19068 tree void_ftype_unsigned
19069 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
19070 tree void_ftype_unsigned_unsigned
19071 = build_function_type_list (void_type_node, unsigned_type_node,
19072 unsigned_type_node, NULL_TREE);
19073 tree void_ftype_pcvoid_unsigned_unsigned
19074 = build_function_type_list (void_type_node, const_ptr_type_node,
19075 unsigned_type_node, unsigned_type_node,
19077 tree unsigned_ftype_void
19078 = build_function_type (unsigned_type_node, void_list_node);
19079 tree v2si_ftype_v4sf
19080 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
19081 /* Loads/stores. */
19082 tree void_ftype_v8qi_v8qi_pchar
19083 = build_function_type_list (void_type_node,
19084 V8QI_type_node, V8QI_type_node,
19085 pchar_type_node, NULL_TREE);
19086 tree v4sf_ftype_pcfloat
19087 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
19088 tree v4sf_ftype_v4sf_pcv2sf
19089 = build_function_type_list (V4SF_type_node,
19090 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
19091 tree void_ftype_pv2sf_v4sf
19092 = build_function_type_list (void_type_node,
19093 pv2sf_type_node, V4SF_type_node, NULL_TREE);
19094 tree void_ftype_pfloat_v4sf
19095 = build_function_type_list (void_type_node,
19096 pfloat_type_node, V4SF_type_node, NULL_TREE);
19097 tree void_ftype_pdi_di
19098 = build_function_type_list (void_type_node,
19099 pdi_type_node, long_long_unsigned_type_node,
19101 tree void_ftype_pv2di_v2di
19102 = build_function_type_list (void_type_node,
19103 pv2di_type_node, V2DI_type_node, NULL_TREE);
19104 /* Normal vector unops. */
19105 tree v4sf_ftype_v4sf
19106 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
19107 tree v16qi_ftype_v16qi
19108 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
19109 tree v8hi_ftype_v8hi
19110 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
19111 tree v4si_ftype_v4si
19112 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
19113 tree v8qi_ftype_v8qi
19114 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
19115 tree v4hi_ftype_v4hi
19116 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
19118 /* Normal vector binops. */
19119 tree v4sf_ftype_v4sf_v4sf
19120 = build_function_type_list (V4SF_type_node,
19121 V4SF_type_node, V4SF_type_node, NULL_TREE);
19122 tree v8qi_ftype_v8qi_v8qi
19123 = build_function_type_list (V8QI_type_node,
19124 V8QI_type_node, V8QI_type_node, NULL_TREE);
19125 tree v4hi_ftype_v4hi_v4hi
19126 = build_function_type_list (V4HI_type_node,
19127 V4HI_type_node, V4HI_type_node, NULL_TREE);
19128 tree v2si_ftype_v2si_v2si
19129 = build_function_type_list (V2SI_type_node,
19130 V2SI_type_node, V2SI_type_node, NULL_TREE);
19131 tree v1di_ftype_v1di_v1di
19132 = build_function_type_list (V1DI_type_node,
19133 V1DI_type_node, V1DI_type_node, NULL_TREE);
19134 tree v1di_ftype_v1di_v1di_int
19135 = build_function_type_list (V1DI_type_node,
19136 V1DI_type_node, V1DI_type_node,
19137 integer_type_node, NULL_TREE);
19138 tree v2si_ftype_v2sf
19139 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
19140 tree v2sf_ftype_v2si
19141 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
19142 tree v2si_ftype_v2si
19143 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
19144 tree v2sf_ftype_v2sf
19145 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
19146 tree v2sf_ftype_v2sf_v2sf
19147 = build_function_type_list (V2SF_type_node,
19148 V2SF_type_node, V2SF_type_node, NULL_TREE);
19149 tree v2si_ftype_v2sf_v2sf
19150 = build_function_type_list (V2SI_type_node,
19151 V2SF_type_node, V2SF_type_node, NULL_TREE);
19152 tree pint_type_node = build_pointer_type (integer_type_node);
19153 tree pdouble_type_node = build_pointer_type (double_type_node);
19154 tree pcdouble_type_node = build_pointer_type (
19155 build_type_variant (double_type_node, 1, 0));
19156 tree int_ftype_v2df_v2df
19157 = build_function_type_list (integer_type_node,
19158 V2DF_type_node, V2DF_type_node, NULL_TREE);
19160 tree void_ftype_pcvoid
19161 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
19162 tree v4sf_ftype_v4si
19163 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
19164 tree v4si_ftype_v4sf
19165 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
19166 tree v2df_ftype_v4si
19167 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
19168 tree v4si_ftype_v2df
19169 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
19170 tree v4si_ftype_v2df_v2df
19171 = build_function_type_list (V4SI_type_node,
19172 V2DF_type_node, V2DF_type_node, NULL_TREE);
19173 tree v2si_ftype_v2df
19174 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
19175 tree v4sf_ftype_v2df
19176 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
19177 tree v2df_ftype_v2si
19178 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
19179 tree v2df_ftype_v4sf
19180 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
19181 tree int_ftype_v2df
19182 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
19183 tree int64_ftype_v2df
19184 = build_function_type_list (long_long_integer_type_node,
19185 V2DF_type_node, NULL_TREE);
19186 tree v2df_ftype_v2df_int
19187 = build_function_type_list (V2DF_type_node,
19188 V2DF_type_node, integer_type_node, NULL_TREE);
19189 tree v2df_ftype_v2df_int64
19190 = build_function_type_list (V2DF_type_node,
19191 V2DF_type_node, long_long_integer_type_node,
19193 tree v4sf_ftype_v4sf_v2df
19194 = build_function_type_list (V4SF_type_node,
19195 V4SF_type_node, V2DF_type_node, NULL_TREE);
19196 tree v2df_ftype_v2df_v4sf
19197 = build_function_type_list (V2DF_type_node,
19198 V2DF_type_node, V4SF_type_node, NULL_TREE);
19199 tree v2df_ftype_v2df_v2df_int
19200 = build_function_type_list (V2DF_type_node,
19201 V2DF_type_node, V2DF_type_node,
19204 tree v2df_ftype_v2df_pcdouble
19205 = build_function_type_list (V2DF_type_node,
19206 V2DF_type_node, pcdouble_type_node, NULL_TREE);
19207 tree void_ftype_pdouble_v2df
19208 = build_function_type_list (void_type_node,
19209 pdouble_type_node, V2DF_type_node, NULL_TREE);
19210 tree void_ftype_pint_int
19211 = build_function_type_list (void_type_node,
19212 pint_type_node, integer_type_node, NULL_TREE);
19213 tree void_ftype_v16qi_v16qi_pchar
19214 = build_function_type_list (void_type_node,
19215 V16QI_type_node, V16QI_type_node,
19216 pchar_type_node, NULL_TREE);
19217 tree v2df_ftype_pcdouble
19218 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
19219 tree v2df_ftype_v2df_v2df
19220 = build_function_type_list (V2DF_type_node,
19221 V2DF_type_node, V2DF_type_node, NULL_TREE);
19222 tree v16qi_ftype_v16qi_v16qi
19223 = build_function_type_list (V16QI_type_node,
19224 V16QI_type_node, V16QI_type_node, NULL_TREE);
19225 tree v8hi_ftype_v8hi_v8hi
19226 = build_function_type_list (V8HI_type_node,
19227 V8HI_type_node, V8HI_type_node, NULL_TREE);
19228 tree v4si_ftype_v4si_v4si
19229 = build_function_type_list (V4SI_type_node,
19230 V4SI_type_node, V4SI_type_node, NULL_TREE);
19231 tree v2di_ftype_v2di_v2di
19232 = build_function_type_list (V2DI_type_node,
19233 V2DI_type_node, V2DI_type_node, NULL_TREE);
19234 tree v2di_ftype_v2df_v2df
19235 = build_function_type_list (V2DI_type_node,
19236 V2DF_type_node, V2DF_type_node, NULL_TREE);
19237 tree v2df_ftype_v2df
19238 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
19239 tree v2di_ftype_v2di_int
19240 = build_function_type_list (V2DI_type_node,
19241 V2DI_type_node, integer_type_node, NULL_TREE);
19242 tree v2di_ftype_v2di_v2di_int
19243 = build_function_type_list (V2DI_type_node, V2DI_type_node,
19244 V2DI_type_node, integer_type_node, NULL_TREE);
19245 tree v4si_ftype_v4si_int
19246 = build_function_type_list (V4SI_type_node,
19247 V4SI_type_node, integer_type_node, NULL_TREE);
19248 tree v8hi_ftype_v8hi_int
19249 = build_function_type_list (V8HI_type_node,
19250 V8HI_type_node, integer_type_node, NULL_TREE);
19251 tree v4si_ftype_v8hi_v8hi
19252 = build_function_type_list (V4SI_type_node,
19253 V8HI_type_node, V8HI_type_node, NULL_TREE);
19254 tree v1di_ftype_v8qi_v8qi
19255 = build_function_type_list (V1DI_type_node,
19256 V8QI_type_node, V8QI_type_node, NULL_TREE);
19257 tree v1di_ftype_v2si_v2si
19258 = build_function_type_list (V1DI_type_node,
19259 V2SI_type_node, V2SI_type_node, NULL_TREE);
19260 tree v2di_ftype_v16qi_v16qi
19261 = build_function_type_list (V2DI_type_node,
19262 V16QI_type_node, V16QI_type_node, NULL_TREE);
19263 tree v2di_ftype_v4si_v4si
19264 = build_function_type_list (V2DI_type_node,
19265 V4SI_type_node, V4SI_type_node, NULL_TREE);
19266 tree int_ftype_v16qi
19267 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
19268 tree v16qi_ftype_pcchar
19269 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
19270 tree void_ftype_pchar_v16qi
19271 = build_function_type_list (void_type_node,
19272 pchar_type_node, V16QI_type_node, NULL_TREE);
19274 tree v2di_ftype_v2di_unsigned_unsigned
19275 = build_function_type_list (V2DI_type_node, V2DI_type_node,
19276 unsigned_type_node, unsigned_type_node,
19278 tree v2di_ftype_v2di_v2di_unsigned_unsigned
19279 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
19280 unsigned_type_node, unsigned_type_node,
19282 tree v2di_ftype_v2di_v16qi
19283 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
19285 tree v2df_ftype_v2df_v2df_v2df
19286 = build_function_type_list (V2DF_type_node,
19287 V2DF_type_node, V2DF_type_node,
19288 V2DF_type_node, NULL_TREE);
19289 tree v4sf_ftype_v4sf_v4sf_v4sf
19290 = build_function_type_list (V4SF_type_node,
19291 V4SF_type_node, V4SF_type_node,
19292 V4SF_type_node, NULL_TREE);
19293 tree v8hi_ftype_v16qi
19294 = build_function_type_list (V8HI_type_node, V16QI_type_node,
19296 tree v4si_ftype_v16qi
19297 = build_function_type_list (V4SI_type_node, V16QI_type_node,
19299 tree v2di_ftype_v16qi
19300 = build_function_type_list (V2DI_type_node, V16QI_type_node,
19302 tree v4si_ftype_v8hi
19303 = build_function_type_list (V4SI_type_node, V8HI_type_node,
19305 tree v2di_ftype_v8hi
19306 = build_function_type_list (V2DI_type_node, V8HI_type_node,
19308 tree v2di_ftype_v4si
19309 = build_function_type_list (V2DI_type_node, V4SI_type_node,
19311 tree v2di_ftype_pv2di
19312 = build_function_type_list (V2DI_type_node, pv2di_type_node,
19314 tree v16qi_ftype_v16qi_v16qi_int
19315 = build_function_type_list (V16QI_type_node, V16QI_type_node,
19316 V16QI_type_node, integer_type_node,
19318 tree v16qi_ftype_v16qi_v16qi_v16qi
19319 = build_function_type_list (V16QI_type_node, V16QI_type_node,
19320 V16QI_type_node, V16QI_type_node,
19322 tree v8hi_ftype_v8hi_v8hi_int
19323 = build_function_type_list (V8HI_type_node, V8HI_type_node,
19324 V8HI_type_node, integer_type_node,
19326 tree v4si_ftype_v4si_v4si_int
19327 = build_function_type_list (V4SI_type_node, V4SI_type_node,
19328 V4SI_type_node, integer_type_node,
19330 tree int_ftype_v2di_v2di
19331 = build_function_type_list (integer_type_node,
19332 V2DI_type_node, V2DI_type_node,
19334 tree int_ftype_v16qi_int_v16qi_int_int
19335 = build_function_type_list (integer_type_node,
19342 tree v16qi_ftype_v16qi_int_v16qi_int_int
19343 = build_function_type_list (V16QI_type_node,
19350 tree int_ftype_v16qi_v16qi_int
19351 = build_function_type_list (integer_type_node,
19357 /* SSE5 instructions */
19358 tree v2di_ftype_v2di_v2di_v2di
19359 = build_function_type_list (V2DI_type_node,
19365 tree v4si_ftype_v4si_v4si_v4si
19366 = build_function_type_list (V4SI_type_node,
19372 tree v4si_ftype_v4si_v4si_v2di
19373 = build_function_type_list (V4SI_type_node,
19379 tree v8hi_ftype_v8hi_v8hi_v8hi
19380 = build_function_type_list (V8HI_type_node,
19386 tree v8hi_ftype_v8hi_v8hi_v4si
19387 = build_function_type_list (V8HI_type_node,
19393 tree v2df_ftype_v2df_v2df_v16qi
19394 = build_function_type_list (V2DF_type_node,
19400 tree v4sf_ftype_v4sf_v4sf_v16qi
19401 = build_function_type_list (V4SF_type_node,
19407 tree v2di_ftype_v2di_si
19408 = build_function_type_list (V2DI_type_node,
19413 tree v4si_ftype_v4si_si
19414 = build_function_type_list (V4SI_type_node,
19419 tree v8hi_ftype_v8hi_si
19420 = build_function_type_list (V8HI_type_node,
19425 tree v16qi_ftype_v16qi_si
19426 = build_function_type_list (V16QI_type_node,
19430 tree v4sf_ftype_v4hi
19431 = build_function_type_list (V4SF_type_node,
19435 tree v4hi_ftype_v4sf
19436 = build_function_type_list (V4HI_type_node,
19440 tree v2di_ftype_v2di
19441 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
19443 tree v16qi_ftype_v8hi_v8hi
19444 = build_function_type_list (V16QI_type_node,
19445 V8HI_type_node, V8HI_type_node,
19447 tree v8hi_ftype_v4si_v4si
19448 = build_function_type_list (V8HI_type_node,
19449 V4SI_type_node, V4SI_type_node,
19451 tree v8hi_ftype_v16qi_v16qi
19452 = build_function_type_list (V8HI_type_node,
19453 V16QI_type_node, V16QI_type_node,
19455 tree v4hi_ftype_v8qi_v8qi
19456 = build_function_type_list (V4HI_type_node,
19457 V8QI_type_node, V8QI_type_node,
19459 tree unsigned_ftype_unsigned_uchar
19460 = build_function_type_list (unsigned_type_node,
19461 unsigned_type_node,
19462 unsigned_char_type_node,
19464 tree unsigned_ftype_unsigned_ushort
19465 = build_function_type_list (unsigned_type_node,
19466 unsigned_type_node,
19467 short_unsigned_type_node,
19469 tree unsigned_ftype_unsigned_unsigned
19470 = build_function_type_list (unsigned_type_node,
19471 unsigned_type_node,
19472 unsigned_type_node,
19474 tree uint64_ftype_uint64_uint64
19475 = build_function_type_list (long_long_unsigned_type_node,
19476 long_long_unsigned_type_node,
19477 long_long_unsigned_type_node,
19479 tree float_ftype_float
19480 = build_function_type_list (float_type_node,
19486 /* The __float80 type. */
19487 if (TYPE_MODE (long_double_type_node) == XFmode)
19488 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
19492 /* The __float80 type. */
19493 tree float80_type_node = make_node (REAL_TYPE);
19495 TYPE_PRECISION (float80_type_node) = 80;
19496 layout_type (float80_type_node);
19497 (*lang_hooks.types.register_builtin_type) (float80_type_node,
19503 tree float128_type_node = make_node (REAL_TYPE);
19505 TYPE_PRECISION (float128_type_node) = 128;
19506 layout_type (float128_type_node);
19507 (*lang_hooks.types.register_builtin_type) (float128_type_node,
19510 /* TFmode support builtins. */
19511 ftype = build_function_type (float128_type_node,
19513 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_infq", ftype, IX86_BUILTIN_INFQ);
19515 ftype = build_function_type_list (float128_type_node,
19516 float128_type_node,
19518 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_fabsq", ftype, IX86_BUILTIN_FABSQ);
19520 ftype = build_function_type_list (float128_type_node,
19521 float128_type_node,
19522 float128_type_node,
19524 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_copysignq", ftype, IX86_BUILTIN_COPYSIGNQ);
19527 /* Add all special builtins with variable number of operands. */
19528 for (i = 0, d = bdesc_special_args;
19529 i < ARRAY_SIZE (bdesc_special_args);
19537 switch ((enum ix86_special_builtin_type) d->flag)
19539 case VOID_FTYPE_VOID:
19540 type = void_ftype_void;
19542 case V16QI_FTYPE_PCCHAR:
19543 type = v16qi_ftype_pcchar;
19545 case V4SF_FTYPE_PCFLOAT:
19546 type = v4sf_ftype_pcfloat;
19548 case V2DI_FTYPE_PV2DI:
19549 type = v2di_ftype_pv2di;
19551 case V2DF_FTYPE_PCDOUBLE:
19552 type = v2df_ftype_pcdouble;
19554 case V4SF_FTYPE_V4SF_PCV2SF:
19555 type = v4sf_ftype_v4sf_pcv2sf;
19557 case V2DF_FTYPE_V2DF_PCDOUBLE:
19558 type = v2df_ftype_v2df_pcdouble;
19560 case VOID_FTYPE_PV2SF_V4SF:
19561 type = void_ftype_pv2sf_v4sf;
19563 case VOID_FTYPE_PV2DI_V2DI:
19564 type = void_ftype_pv2di_v2di;
19566 case VOID_FTYPE_PCHAR_V16QI:
19567 type = void_ftype_pchar_v16qi;
19569 case VOID_FTYPE_PFLOAT_V4SF:
19570 type = void_ftype_pfloat_v4sf;
19572 case VOID_FTYPE_PDOUBLE_V2DF:
19573 type = void_ftype_pdouble_v2df;
19575 case VOID_FTYPE_PDI_DI:
19576 type = void_ftype_pdi_di;
19578 case VOID_FTYPE_PINT_INT:
19579 type = void_ftype_pint_int;
19582 gcc_unreachable ();
19585 def_builtin (d->mask, d->name, type, d->code);
19588 /* Add all builtins with variable number of operands. */
19589 for (i = 0, d = bdesc_args;
19590 i < ARRAY_SIZE (bdesc_args);
19598 switch ((enum ix86_builtin_type) d->flag)
19600 case FLOAT_FTYPE_FLOAT:
19601 type = float_ftype_float;
19603 case INT_FTYPE_V2DI_V2DI_PTEST:
19604 type = int_ftype_v2di_v2di;
19606 case INT64_FTYPE_V4SF:
19607 type = int64_ftype_v4sf;
19609 case INT64_FTYPE_V2DF:
19610 type = int64_ftype_v2df;
19612 case INT_FTYPE_V16QI:
19613 type = int_ftype_v16qi;
19615 case INT_FTYPE_V8QI:
19616 type = int_ftype_v8qi;
19618 case INT_FTYPE_V4SF:
19619 type = int_ftype_v4sf;
19621 case INT_FTYPE_V2DF:
19622 type = int_ftype_v2df;
19624 case V16QI_FTYPE_V16QI:
19625 type = v16qi_ftype_v16qi;
19627 case V8HI_FTYPE_V8HI:
19628 type = v8hi_ftype_v8hi;
19630 case V8HI_FTYPE_V16QI:
19631 type = v8hi_ftype_v16qi;
19633 case V8QI_FTYPE_V8QI:
19634 type = v8qi_ftype_v8qi;
19636 case V4SI_FTYPE_V4SI:
19637 type = v4si_ftype_v4si;
19639 case V4SI_FTYPE_V16QI:
19640 type = v4si_ftype_v16qi;
19642 case V4SI_FTYPE_V8HI:
19643 type = v4si_ftype_v8hi;
19645 case V4SI_FTYPE_V4SF:
19646 type = v4si_ftype_v4sf;
19648 case V4SI_FTYPE_V2DF:
19649 type = v4si_ftype_v2df;
19651 case V4HI_FTYPE_V4HI:
19652 type = v4hi_ftype_v4hi;
19654 case V4SF_FTYPE_V4SF:
19655 case V4SF_FTYPE_V4SF_VEC_MERGE:
19656 type = v4sf_ftype_v4sf;
19658 case V4SF_FTYPE_V4SI:
19659 type = v4sf_ftype_v4si;
19661 case V4SF_FTYPE_V2DF:
19662 type = v4sf_ftype_v2df;
19664 case V2DI_FTYPE_V2DI:
19665 type = v2di_ftype_v2di;
19667 case V2DI_FTYPE_V16QI:
19668 type = v2di_ftype_v16qi;
19670 case V2DI_FTYPE_V8HI:
19671 type = v2di_ftype_v8hi;
19673 case V2DI_FTYPE_V4SI:
19674 type = v2di_ftype_v4si;
19676 case V2SI_FTYPE_V2SI:
19677 type = v2si_ftype_v2si;
19679 case V2SI_FTYPE_V4SF:
19680 type = v2si_ftype_v4sf;
19682 case V2SI_FTYPE_V2DF:
19683 type = v2si_ftype_v2df;
19685 case V2SI_FTYPE_V2SF:
19686 type = v2si_ftype_v2sf;
19688 case V2DF_FTYPE_V4SF:
19689 type = v2df_ftype_v4sf;
19691 case V2DF_FTYPE_V2DF:
19692 case V2DF_FTYPE_V2DF_VEC_MERGE:
19693 type = v2df_ftype_v2df;
19695 case V2DF_FTYPE_V2SI:
19696 type = v2df_ftype_v2si;
19698 case V2DF_FTYPE_V4SI:
19699 type = v2df_ftype_v4si;
19701 case V2SF_FTYPE_V2SF:
19702 type = v2sf_ftype_v2sf;
19704 case V2SF_FTYPE_V2SI:
19705 type = v2sf_ftype_v2si;
19707 case V16QI_FTYPE_V16QI_V16QI:
19708 type = v16qi_ftype_v16qi_v16qi;
19710 case V16QI_FTYPE_V8HI_V8HI:
19711 type = v16qi_ftype_v8hi_v8hi;
19713 case V8QI_FTYPE_V8QI_V8QI:
19714 type = v8qi_ftype_v8qi_v8qi;
19716 case V8QI_FTYPE_V4HI_V4HI:
19717 type = v8qi_ftype_v4hi_v4hi;
19719 case V8HI_FTYPE_V8HI_V8HI:
19720 case V8HI_FTYPE_V8HI_V8HI_COUNT:
19721 type = v8hi_ftype_v8hi_v8hi;
19723 case V8HI_FTYPE_V16QI_V16QI:
19724 type = v8hi_ftype_v16qi_v16qi;
19726 case V8HI_FTYPE_V4SI_V4SI:
19727 type = v8hi_ftype_v4si_v4si;
19729 case V8HI_FTYPE_V8HI_SI_COUNT:
19730 type = v8hi_ftype_v8hi_int;
19732 case V4SI_FTYPE_V4SI_V4SI:
19733 case V4SI_FTYPE_V4SI_V4SI_COUNT:
19734 type = v4si_ftype_v4si_v4si;
19736 case V4SI_FTYPE_V8HI_V8HI:
19737 type = v4si_ftype_v8hi_v8hi;
19739 case V4SI_FTYPE_V4SF_V4SF:
19740 type = v4si_ftype_v4sf_v4sf;
19742 case V4SI_FTYPE_V2DF_V2DF:
19743 type = v4si_ftype_v2df_v2df;
19745 case V4SI_FTYPE_V4SI_SI_COUNT:
19746 type = v4si_ftype_v4si_int;
19748 case V4HI_FTYPE_V4HI_V4HI:
19749 case V4HI_FTYPE_V4HI_V4HI_COUNT:
19750 type = v4hi_ftype_v4hi_v4hi;
19752 case V4HI_FTYPE_V8QI_V8QI:
19753 type = v4hi_ftype_v8qi_v8qi;
19755 case V4HI_FTYPE_V2SI_V2SI:
19756 type = v4hi_ftype_v2si_v2si;
19758 case V4HI_FTYPE_V4HI_SI_COUNT:
19759 type = v4hi_ftype_v4hi_int;
19761 case V4SF_FTYPE_V4SF_V4SF:
19762 case V4SF_FTYPE_V4SF_V4SF_SWAP:
19763 type = v4sf_ftype_v4sf_v4sf;
19765 case V4SF_FTYPE_V4SF_V2SI:
19766 type = v4sf_ftype_v4sf_v2si;
19768 case V4SF_FTYPE_V4SF_V2DF:
19769 type = v4sf_ftype_v4sf_v2df;
19771 case V4SF_FTYPE_V4SF_DI:
19772 type = v4sf_ftype_v4sf_int64;
19774 case V4SF_FTYPE_V4SF_SI:
19775 type = v4sf_ftype_v4sf_int;
19777 case V2DI_FTYPE_V2DI_V2DI:
19778 case V2DI_FTYPE_V2DI_V2DI_COUNT:
19779 type = v2di_ftype_v2di_v2di;
19781 case V2DI_FTYPE_V16QI_V16QI:
19782 type = v2di_ftype_v16qi_v16qi;
19784 case V2DI_FTYPE_V4SI_V4SI:
19785 type = v2di_ftype_v4si_v4si;
19787 case V2DI_FTYPE_V2DI_V16QI:
19788 type = v2di_ftype_v2di_v16qi;
19790 case V2DI_FTYPE_V2DF_V2DF:
19791 type = v2di_ftype_v2df_v2df;
19793 case V2DI_FTYPE_V2DI_SI_COUNT:
19794 type = v2di_ftype_v2di_int;
19796 case V2SI_FTYPE_V2SI_V2SI:
19797 case V2SI_FTYPE_V2SI_V2SI_COUNT:
19798 type = v2si_ftype_v2si_v2si;
19800 case V2SI_FTYPE_V4HI_V4HI:
19801 type = v2si_ftype_v4hi_v4hi;
19803 case V2SI_FTYPE_V2SF_V2SF:
19804 type = v2si_ftype_v2sf_v2sf;
19806 case V2SI_FTYPE_V2SI_SI_COUNT:
19807 type = v2si_ftype_v2si_int;
19809 case V2DF_FTYPE_V2DF_V2DF:
19810 case V2DF_FTYPE_V2DF_V2DF_SWAP:
19811 type = v2df_ftype_v2df_v2df;
19813 case V2DF_FTYPE_V2DF_V4SF:
19814 type = v2df_ftype_v2df_v4sf;
19816 case V2DF_FTYPE_V2DF_DI:
19817 type = v2df_ftype_v2df_int64;
19819 case V2DF_FTYPE_V2DF_SI:
19820 type = v2df_ftype_v2df_int;
19822 case V2SF_FTYPE_V2SF_V2SF:
19823 type = v2sf_ftype_v2sf_v2sf;
19825 case V1DI_FTYPE_V1DI_V1DI:
19826 case V1DI_FTYPE_V1DI_V1DI_COUNT:
19827 type = v1di_ftype_v1di_v1di;
19829 case V1DI_FTYPE_V8QI_V8QI:
19830 type = v1di_ftype_v8qi_v8qi;
19832 case V1DI_FTYPE_V2SI_V2SI:
19833 type = v1di_ftype_v2si_v2si;
19835 case V1DI_FTYPE_V1DI_SI_COUNT:
19836 type = v1di_ftype_v1di_int;
19838 case UINT64_FTYPE_UINT64_UINT64:
19839 type = uint64_ftype_uint64_uint64;
19841 case UINT_FTYPE_UINT_UINT:
19842 type = unsigned_ftype_unsigned_unsigned;
19844 case UINT_FTYPE_UINT_USHORT:
19845 type = unsigned_ftype_unsigned_ushort;
19847 case UINT_FTYPE_UINT_UCHAR:
19848 type = unsigned_ftype_unsigned_uchar;
19850 case V8HI_FTYPE_V8HI_INT:
19851 type = v8hi_ftype_v8hi_int;
19853 case V4SI_FTYPE_V4SI_INT:
19854 type = v4si_ftype_v4si_int;
19856 case V4HI_FTYPE_V4HI_INT:
19857 type = v4hi_ftype_v4hi_int;
19859 case V4SF_FTYPE_V4SF_INT:
19860 type = v4sf_ftype_v4sf_int;
19862 case V2DI_FTYPE_V2DI_INT:
19863 case V2DI2TI_FTYPE_V2DI_INT:
19864 type = v2di_ftype_v2di_int;
19866 case V2DF_FTYPE_V2DF_INT:
19867 type = v2df_ftype_v2df_int;
19869 case V16QI_FTYPE_V16QI_V16QI_V16QI:
19870 type = v16qi_ftype_v16qi_v16qi_v16qi;
19872 case V4SF_FTYPE_V4SF_V4SF_V4SF:
19873 type = v4sf_ftype_v4sf_v4sf_v4sf;
19875 case V2DF_FTYPE_V2DF_V2DF_V2DF:
19876 type = v2df_ftype_v2df_v2df_v2df;
19878 case V16QI_FTYPE_V16QI_V16QI_INT:
19879 type = v16qi_ftype_v16qi_v16qi_int;
19881 case V8HI_FTYPE_V8HI_V8HI_INT:
19882 type = v8hi_ftype_v8hi_v8hi_int;
19884 case V4SI_FTYPE_V4SI_V4SI_INT:
19885 type = v4si_ftype_v4si_v4si_int;
19887 case V4SF_FTYPE_V4SF_V4SF_INT:
19888 type = v4sf_ftype_v4sf_v4sf_int;
19890 case V2DI_FTYPE_V2DI_V2DI_INT:
19891 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
19892 type = v2di_ftype_v2di_v2di_int;
19894 case V2DF_FTYPE_V2DF_V2DF_INT:
19895 type = v2df_ftype_v2df_v2df_int;
19897 case V2DI_FTYPE_V2DI_UINT_UINT:
19898 type = v2di_ftype_v2di_unsigned_unsigned;
19900 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
19901 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
19903 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
19904 type = v1di_ftype_v1di_v1di_int;
19907 gcc_unreachable ();
19910 def_builtin_const (d->mask, d->name, type, d->code);
19913 /* pcmpestr[im] insns. */
19914 for (i = 0, d = bdesc_pcmpestr;
19915 i < ARRAY_SIZE (bdesc_pcmpestr);
19918 if (d->code == IX86_BUILTIN_PCMPESTRM128)
19919 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
19921 ftype = int_ftype_v16qi_int_v16qi_int_int;
19922 def_builtin_const (d->mask, d->name, ftype, d->code);
19925 /* pcmpistr[im] insns. */
19926 for (i = 0, d = bdesc_pcmpistr;
19927 i < ARRAY_SIZE (bdesc_pcmpistr);
19930 if (d->code == IX86_BUILTIN_PCMPISTRM128)
19931 ftype = v16qi_ftype_v16qi_v16qi_int;
19933 ftype = int_ftype_v16qi_v16qi_int;
19934 def_builtin_const (d->mask, d->name, ftype, d->code);
19937 /* comi/ucomi insns. */
19938 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
19939 if (d->mask == OPTION_MASK_ISA_SSE2)
19940 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
19942 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
19945 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
19946 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
19948 /* SSE or 3DNow!A */
19949 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
19952 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
19954 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
19955 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
19958 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
19959 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
19964 /* Define AES built-in functions only if AES is enabled. */
19965 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
19966 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
19967 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
19968 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
19969 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
19970 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
19976 /* Define PCLMUL built-in function only if PCLMUL is enabled. */
19977 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
19980 /* Access to the vec_init patterns. */
19981 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
19982 integer_type_node, NULL_TREE);
19983 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
19985 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
19986 short_integer_type_node,
19987 short_integer_type_node,
19988 short_integer_type_node, NULL_TREE);
19989 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
19991 ftype = build_function_type_list (V8QI_type_node, char_type_node,
19992 char_type_node, char_type_node,
19993 char_type_node, char_type_node,
19994 char_type_node, char_type_node,
19995 char_type_node, NULL_TREE);
19996 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
19998 /* Access to the vec_extract patterns. */
19999 ftype = build_function_type_list (double_type_node, V2DF_type_node,
20000 integer_type_node, NULL_TREE);
20001 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
20003 ftype = build_function_type_list (long_long_integer_type_node,
20004 V2DI_type_node, integer_type_node,
20006 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
20008 ftype = build_function_type_list (float_type_node, V4SF_type_node,
20009 integer_type_node, NULL_TREE);
20010 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
20012 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
20013 integer_type_node, NULL_TREE);
20014 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
20016 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
20017 integer_type_node, NULL_TREE);
20018 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
20020 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
20021 integer_type_node, NULL_TREE);
20022 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
20024 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
20025 integer_type_node, NULL_TREE);
20026 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
20028 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
20029 integer_type_node, NULL_TREE);
20030 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
20032 /* Access to the vec_set patterns. */
20033 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
20035 integer_type_node, NULL_TREE);
20036 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
20038 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
20040 integer_type_node, NULL_TREE);
20041 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
20043 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
20045 integer_type_node, NULL_TREE);
20046 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
20048 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
20050 integer_type_node, NULL_TREE);
20051 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
20053 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
20055 integer_type_node, NULL_TREE);
20056 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
20058 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
20060 integer_type_node, NULL_TREE);
20061 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
20063 /* Add SSE5 multi-arg argument instructions */
20064 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
20066 tree mtype = NULL_TREE;
20071 switch ((enum multi_arg_type)d->flag)
20073 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
20074 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
20075 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
20076 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
20077 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
20078 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
20079 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
20080 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
20081 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
20082 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
20083 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
20084 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
20085 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
20086 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
20087 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
20088 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
20089 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
20090 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
20091 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
20092 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
20093 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
20094 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
20095 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
20096 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
20097 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
20098 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
20099 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
20100 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
20101 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
20102 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
20103 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
20104 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
20105 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
20106 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
20107 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
20108 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
20109 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
20110 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
20111 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
20112 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
20113 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
20114 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
20115 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
20116 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
20117 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
20118 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
20119 case MULTI_ARG_UNKNOWN:
20121 gcc_unreachable ();
20125 def_builtin_const (d->mask, d->name, mtype, d->code);
20130 ix86_init_builtins (void)
20133 ix86_init_mmx_sse_builtins ();
20136 /* Errors in the source file can cause expand_expr to return const0_rtx
20137 where we expect a vector. To avoid crashing, use one of the vector
20138 clear instructions. */
20140 safe_vector_operand (rtx x, enum machine_mode mode)
20142 if (x == const0_rtx)
20143 x = CONST0_RTX (mode);
20147 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
20150 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
20153 tree arg0 = CALL_EXPR_ARG (exp, 0);
20154 tree arg1 = CALL_EXPR_ARG (exp, 1);
20155 rtx op0 = expand_normal (arg0);
20156 rtx op1 = expand_normal (arg1);
20157 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20158 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20159 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20161 if (VECTOR_MODE_P (mode0))
20162 op0 = safe_vector_operand (op0, mode0);
20163 if (VECTOR_MODE_P (mode1))
20164 op1 = safe_vector_operand (op1, mode1);
20166 if (optimize || !target
20167 || GET_MODE (target) != tmode
20168 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20169 target = gen_reg_rtx (tmode);
20171 if (GET_MODE (op1) == SImode && mode1 == TImode)
20173 rtx x = gen_reg_rtx (V4SImode);
20174 emit_insn (gen_sse2_loadd (x, op1));
20175 op1 = gen_lowpart (TImode, x);
20178 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
20179 op0 = copy_to_mode_reg (mode0, op0);
20180 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
20181 op1 = copy_to_mode_reg (mode1, op1);
20183 pat = GEN_FCN (icode) (target, op0, op1);
20192 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
20195 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
20196 enum multi_arg_type m_type,
20197 enum insn_code sub_code)
20202 bool comparison_p = false;
20204 bool last_arg_constant = false;
20205 int num_memory = 0;
20208 enum machine_mode mode;
20211 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20215 case MULTI_ARG_3_SF:
20216 case MULTI_ARG_3_DF:
20217 case MULTI_ARG_3_DI:
20218 case MULTI_ARG_3_SI:
20219 case MULTI_ARG_3_SI_DI:
20220 case MULTI_ARG_3_HI:
20221 case MULTI_ARG_3_HI_SI:
20222 case MULTI_ARG_3_QI:
20223 case MULTI_ARG_3_PERMPS:
20224 case MULTI_ARG_3_PERMPD:
20228 case MULTI_ARG_2_SF:
20229 case MULTI_ARG_2_DF:
20230 case MULTI_ARG_2_DI:
20231 case MULTI_ARG_2_SI:
20232 case MULTI_ARG_2_HI:
20233 case MULTI_ARG_2_QI:
20237 case MULTI_ARG_2_DI_IMM:
20238 case MULTI_ARG_2_SI_IMM:
20239 case MULTI_ARG_2_HI_IMM:
20240 case MULTI_ARG_2_QI_IMM:
20242 last_arg_constant = true;
20245 case MULTI_ARG_1_SF:
20246 case MULTI_ARG_1_DF:
20247 case MULTI_ARG_1_DI:
20248 case MULTI_ARG_1_SI:
20249 case MULTI_ARG_1_HI:
20250 case MULTI_ARG_1_QI:
20251 case MULTI_ARG_1_SI_DI:
20252 case MULTI_ARG_1_HI_DI:
20253 case MULTI_ARG_1_HI_SI:
20254 case MULTI_ARG_1_QI_DI:
20255 case MULTI_ARG_1_QI_SI:
20256 case MULTI_ARG_1_QI_HI:
20257 case MULTI_ARG_1_PH2PS:
20258 case MULTI_ARG_1_PS2PH:
20262 case MULTI_ARG_2_SF_CMP:
20263 case MULTI_ARG_2_DF_CMP:
20264 case MULTI_ARG_2_DI_CMP:
20265 case MULTI_ARG_2_SI_CMP:
20266 case MULTI_ARG_2_HI_CMP:
20267 case MULTI_ARG_2_QI_CMP:
20269 comparison_p = true;
20272 case MULTI_ARG_2_SF_TF:
20273 case MULTI_ARG_2_DF_TF:
20274 case MULTI_ARG_2_DI_TF:
20275 case MULTI_ARG_2_SI_TF:
20276 case MULTI_ARG_2_HI_TF:
20277 case MULTI_ARG_2_QI_TF:
20282 case MULTI_ARG_UNKNOWN:
20284 gcc_unreachable ();
20287 if (optimize || !target
20288 || GET_MODE (target) != tmode
20289 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20290 target = gen_reg_rtx (tmode);
20292 gcc_assert (nargs <= 4);
20294 for (i = 0; i < nargs; i++)
20296 tree arg = CALL_EXPR_ARG (exp, i);
20297 rtx op = expand_normal (arg);
20298 int adjust = (comparison_p) ? 1 : 0;
20299 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
20301 if (last_arg_constant && i == nargs-1)
20303 if (GET_CODE (op) != CONST_INT)
20305 error ("last argument must be an immediate");
20306 return gen_reg_rtx (tmode);
20311 if (VECTOR_MODE_P (mode))
20312 op = safe_vector_operand (op, mode);
20314 /* If we aren't optimizing, only allow one memory operand to be
20316 if (memory_operand (op, mode))
20319 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
20322 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
20324 op = force_reg (mode, op);
20328 args[i].mode = mode;
20334 pat = GEN_FCN (icode) (target, args[0].op);
20339 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
20340 GEN_INT ((int)sub_code));
20341 else if (! comparison_p)
20342 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
20345 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
20349 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
20354 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
20358 gcc_unreachable ();
20368 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
20369 insns with vec_merge. */
20372 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
20376 tree arg0 = CALL_EXPR_ARG (exp, 0);
20377 rtx op1, op0 = expand_normal (arg0);
20378 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20379 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20381 if (optimize || !target
20382 || GET_MODE (target) != tmode
20383 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20384 target = gen_reg_rtx (tmode);
20386 if (VECTOR_MODE_P (mode0))
20387 op0 = safe_vector_operand (op0, mode0);
20389 if ((optimize && !register_operand (op0, mode0))
20390 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20391 op0 = copy_to_mode_reg (mode0, op0);
20394 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
20395 op1 = copy_to_mode_reg (mode0, op1);
20397 pat = GEN_FCN (icode) (target, op0, op1);
20404 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
20407 ix86_expand_sse_compare (const struct builtin_description *d,
20408 tree exp, rtx target, bool swap)
20411 tree arg0 = CALL_EXPR_ARG (exp, 0);
20412 tree arg1 = CALL_EXPR_ARG (exp, 1);
20413 rtx op0 = expand_normal (arg0);
20414 rtx op1 = expand_normal (arg1);
20416 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
20417 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
20418 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
20419 enum rtx_code comparison = d->comparison;
20421 if (VECTOR_MODE_P (mode0))
20422 op0 = safe_vector_operand (op0, mode0);
20423 if (VECTOR_MODE_P (mode1))
20424 op1 = safe_vector_operand (op1, mode1);
20426 /* Swap operands if we have a comparison that isn't available in
20430 rtx tmp = gen_reg_rtx (mode1);
20431 emit_move_insn (tmp, op1);
20436 if (optimize || !target
20437 || GET_MODE (target) != tmode
20438 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
20439 target = gen_reg_rtx (tmode);
20441 if ((optimize && !register_operand (op0, mode0))
20442 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
20443 op0 = copy_to_mode_reg (mode0, op0);
20444 if ((optimize && !register_operand (op1, mode1))
20445 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
20446 op1 = copy_to_mode_reg (mode1, op1);
20448 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
20449 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
20456 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
20459 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
20463 tree arg0 = CALL_EXPR_ARG (exp, 0);
20464 tree arg1 = CALL_EXPR_ARG (exp, 1);
20465 rtx op0 = expand_normal (arg0);
20466 rtx op1 = expand_normal (arg1);
20467 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20468 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20469 enum rtx_code comparison = d->comparison;
20471 if (VECTOR_MODE_P (mode0))
20472 op0 = safe_vector_operand (op0, mode0);
20473 if (VECTOR_MODE_P (mode1))
20474 op1 = safe_vector_operand (op1, mode1);
20476 /* Swap operands if we have a comparison that isn't available in
20478 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20485 target = gen_reg_rtx (SImode);
20486 emit_move_insn (target, const0_rtx);
20487 target = gen_rtx_SUBREG (QImode, target, 0);
20489 if ((optimize && !register_operand (op0, mode0))
20490 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20491 op0 = copy_to_mode_reg (mode0, op0);
20492 if ((optimize && !register_operand (op1, mode1))
20493 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20494 op1 = copy_to_mode_reg (mode1, op1);
20496 pat = GEN_FCN (d->icode) (op0, op1);
20500 emit_insn (gen_rtx_SET (VOIDmode,
20501 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20502 gen_rtx_fmt_ee (comparison, QImode,
20506 return SUBREG_REG (target);
20509 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
20512 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
20516 tree arg0 = CALL_EXPR_ARG (exp, 0);
20517 tree arg1 = CALL_EXPR_ARG (exp, 1);
20518 rtx op0 = expand_normal (arg0);
20519 rtx op1 = expand_normal (arg1);
20520 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20521 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20522 enum rtx_code comparison = d->comparison;
20524 if (VECTOR_MODE_P (mode0))
20525 op0 = safe_vector_operand (op0, mode0);
20526 if (VECTOR_MODE_P (mode1))
20527 op1 = safe_vector_operand (op1, mode1);
20529 target = gen_reg_rtx (SImode);
20530 emit_move_insn (target, const0_rtx);
20531 target = gen_rtx_SUBREG (QImode, target, 0);
20533 if ((optimize && !register_operand (op0, mode0))
20534 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20535 op0 = copy_to_mode_reg (mode0, op0);
20536 if ((optimize && !register_operand (op1, mode1))
20537 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20538 op1 = copy_to_mode_reg (mode1, op1);
20540 pat = GEN_FCN (d->icode) (op0, op1);
20544 emit_insn (gen_rtx_SET (VOIDmode,
20545 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20546 gen_rtx_fmt_ee (comparison, QImode,
20550 return SUBREG_REG (target);
20553 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
20556 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
20557 tree exp, rtx target)
20560 tree arg0 = CALL_EXPR_ARG (exp, 0);
20561 tree arg1 = CALL_EXPR_ARG (exp, 1);
20562 tree arg2 = CALL_EXPR_ARG (exp, 2);
20563 tree arg3 = CALL_EXPR_ARG (exp, 3);
20564 tree arg4 = CALL_EXPR_ARG (exp, 4);
20565 rtx scratch0, scratch1;
20566 rtx op0 = expand_normal (arg0);
20567 rtx op1 = expand_normal (arg1);
20568 rtx op2 = expand_normal (arg2);
20569 rtx op3 = expand_normal (arg3);
20570 rtx op4 = expand_normal (arg4);
20571 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
20573 tmode0 = insn_data[d->icode].operand[0].mode;
20574 tmode1 = insn_data[d->icode].operand[1].mode;
20575 modev2 = insn_data[d->icode].operand[2].mode;
20576 modei3 = insn_data[d->icode].operand[3].mode;
20577 modev4 = insn_data[d->icode].operand[4].mode;
20578 modei5 = insn_data[d->icode].operand[5].mode;
20579 modeimm = insn_data[d->icode].operand[6].mode;
20581 if (VECTOR_MODE_P (modev2))
20582 op0 = safe_vector_operand (op0, modev2);
20583 if (VECTOR_MODE_P (modev4))
20584 op2 = safe_vector_operand (op2, modev4);
20586 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20587 op0 = copy_to_mode_reg (modev2, op0);
20588 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
20589 op1 = copy_to_mode_reg (modei3, op1);
20590 if ((optimize && !register_operand (op2, modev4))
20591 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
20592 op2 = copy_to_mode_reg (modev4, op2);
20593 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
20594 op3 = copy_to_mode_reg (modei5, op3);
20596 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
20598 error ("the fifth argument must be a 8-bit immediate");
20602 if (d->code == IX86_BUILTIN_PCMPESTRI128)
20604 if (optimize || !target
20605 || GET_MODE (target) != tmode0
20606 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20607 target = gen_reg_rtx (tmode0);
20609 scratch1 = gen_reg_rtx (tmode1);
20611 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
20613 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
20615 if (optimize || !target
20616 || GET_MODE (target) != tmode1
20617 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20618 target = gen_reg_rtx (tmode1);
20620 scratch0 = gen_reg_rtx (tmode0);
20622 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
20626 gcc_assert (d->flag);
20628 scratch0 = gen_reg_rtx (tmode0);
20629 scratch1 = gen_reg_rtx (tmode1);
20631 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
20641 target = gen_reg_rtx (SImode);
20642 emit_move_insn (target, const0_rtx);
20643 target = gen_rtx_SUBREG (QImode, target, 0);
20646 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20647 gen_rtx_fmt_ee (EQ, QImode,
20648 gen_rtx_REG ((enum machine_mode) d->flag,
20651 return SUBREG_REG (target);
20658 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
20661 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
20662 tree exp, rtx target)
20665 tree arg0 = CALL_EXPR_ARG (exp, 0);
20666 tree arg1 = CALL_EXPR_ARG (exp, 1);
20667 tree arg2 = CALL_EXPR_ARG (exp, 2);
20668 rtx scratch0, scratch1;
20669 rtx op0 = expand_normal (arg0);
20670 rtx op1 = expand_normal (arg1);
20671 rtx op2 = expand_normal (arg2);
20672 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
20674 tmode0 = insn_data[d->icode].operand[0].mode;
20675 tmode1 = insn_data[d->icode].operand[1].mode;
20676 modev2 = insn_data[d->icode].operand[2].mode;
20677 modev3 = insn_data[d->icode].operand[3].mode;
20678 modeimm = insn_data[d->icode].operand[4].mode;
20680 if (VECTOR_MODE_P (modev2))
20681 op0 = safe_vector_operand (op0, modev2);
20682 if (VECTOR_MODE_P (modev3))
20683 op1 = safe_vector_operand (op1, modev3);
20685 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20686 op0 = copy_to_mode_reg (modev2, op0);
20687 if ((optimize && !register_operand (op1, modev3))
20688 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
20689 op1 = copy_to_mode_reg (modev3, op1);
20691 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
20693 error ("the third argument must be a 8-bit immediate");
20697 if (d->code == IX86_BUILTIN_PCMPISTRI128)
20699 if (optimize || !target
20700 || GET_MODE (target) != tmode0
20701 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20702 target = gen_reg_rtx (tmode0);
20704 scratch1 = gen_reg_rtx (tmode1);
20706 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
20708 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
20710 if (optimize || !target
20711 || GET_MODE (target) != tmode1
20712 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20713 target = gen_reg_rtx (tmode1);
20715 scratch0 = gen_reg_rtx (tmode0);
20717 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
20721 gcc_assert (d->flag);
20723 scratch0 = gen_reg_rtx (tmode0);
20724 scratch1 = gen_reg_rtx (tmode1);
20726 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
20736 target = gen_reg_rtx (SImode);
20737 emit_move_insn (target, const0_rtx);
20738 target = gen_rtx_SUBREG (QImode, target, 0);
20741 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20742 gen_rtx_fmt_ee (EQ, QImode,
20743 gen_rtx_REG ((enum machine_mode) d->flag,
20746 return SUBREG_REG (target);
20752 /* Subroutine of ix86_expand_builtin to take care of insns with
20753 variable number of operands. */
20756 ix86_expand_args_builtin (const struct builtin_description *d,
20757 tree exp, rtx target)
20759 rtx pat, real_target;
20760 unsigned int i, nargs;
20761 unsigned int nargs_constant = 0;
20762 int num_memory = 0;
20766 enum machine_mode mode;
20768 bool last_arg_count = false;
20769 enum insn_code icode = d->icode;
20770 const struct insn_data *insn_p = &insn_data[icode];
20771 enum machine_mode tmode = insn_p->operand[0].mode;
20772 enum machine_mode rmode = VOIDmode;
20774 enum rtx_code comparison = d->comparison;
20776 switch ((enum ix86_builtin_type) d->flag)
20778 case INT_FTYPE_V2DI_V2DI_PTEST:
20779 return ix86_expand_sse_ptest (d, exp, target);
20780 case FLOAT128_FTYPE_FLOAT128:
20781 case FLOAT_FTYPE_FLOAT:
20782 case INT64_FTYPE_V4SF:
20783 case INT64_FTYPE_V2DF:
20784 case INT_FTYPE_V16QI:
20785 case INT_FTYPE_V8QI:
20786 case INT_FTYPE_V4SF:
20787 case INT_FTYPE_V2DF:
20788 case V16QI_FTYPE_V16QI:
20789 case V8HI_FTYPE_V8HI:
20790 case V8HI_FTYPE_V16QI:
20791 case V8QI_FTYPE_V8QI:
20792 case V4SI_FTYPE_V4SI:
20793 case V4SI_FTYPE_V16QI:
20794 case V4SI_FTYPE_V4SF:
20795 case V4SI_FTYPE_V8HI:
20796 case V4SI_FTYPE_V2DF:
20797 case V4HI_FTYPE_V4HI:
20798 case V4SF_FTYPE_V4SF:
20799 case V4SF_FTYPE_V4SI:
20800 case V4SF_FTYPE_V2DF:
20801 case V2DI_FTYPE_V2DI:
20802 case V2DI_FTYPE_V16QI:
20803 case V2DI_FTYPE_V8HI:
20804 case V2DI_FTYPE_V4SI:
20805 case V2DF_FTYPE_V2DF:
20806 case V2DF_FTYPE_V4SI:
20807 case V2DF_FTYPE_V4SF:
20808 case V2DF_FTYPE_V2SI:
20809 case V2SI_FTYPE_V2SI:
20810 case V2SI_FTYPE_V4SF:
20811 case V2SI_FTYPE_V2SF:
20812 case V2SI_FTYPE_V2DF:
20813 case V2SF_FTYPE_V2SF:
20814 case V2SF_FTYPE_V2SI:
20817 case V4SF_FTYPE_V4SF_VEC_MERGE:
20818 case V2DF_FTYPE_V2DF_VEC_MERGE:
20819 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
20820 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
20821 case V16QI_FTYPE_V16QI_V16QI:
20822 case V16QI_FTYPE_V8HI_V8HI:
20823 case V8QI_FTYPE_V8QI_V8QI:
20824 case V8QI_FTYPE_V4HI_V4HI:
20825 case V8HI_FTYPE_V8HI_V8HI:
20826 case V8HI_FTYPE_V16QI_V16QI:
20827 case V8HI_FTYPE_V4SI_V4SI:
20828 case V4SI_FTYPE_V4SI_V4SI:
20829 case V4SI_FTYPE_V8HI_V8HI:
20830 case V4SI_FTYPE_V4SF_V4SF:
20831 case V4SI_FTYPE_V2DF_V2DF:
20832 case V4HI_FTYPE_V4HI_V4HI:
20833 case V4HI_FTYPE_V8QI_V8QI:
20834 case V4HI_FTYPE_V2SI_V2SI:
20835 case V4SF_FTYPE_V4SF_V4SF:
20836 case V4SF_FTYPE_V4SF_V2SI:
20837 case V4SF_FTYPE_V4SF_V2DF:
20838 case V4SF_FTYPE_V4SF_DI:
20839 case V4SF_FTYPE_V4SF_SI:
20840 case V2DI_FTYPE_V2DI_V2DI:
20841 case V2DI_FTYPE_V16QI_V16QI:
20842 case V2DI_FTYPE_V4SI_V4SI:
20843 case V2DI_FTYPE_V2DI_V16QI:
20844 case V2DI_FTYPE_V2DF_V2DF:
20845 case V2SI_FTYPE_V2SI_V2SI:
20846 case V2SI_FTYPE_V4HI_V4HI:
20847 case V2SI_FTYPE_V2SF_V2SF:
20848 case V2DF_FTYPE_V2DF_V2DF:
20849 case V2DF_FTYPE_V2DF_V4SF:
20850 case V2DF_FTYPE_V2DF_DI:
20851 case V2DF_FTYPE_V2DF_SI:
20852 case V2SF_FTYPE_V2SF_V2SF:
20853 case V1DI_FTYPE_V1DI_V1DI:
20854 case V1DI_FTYPE_V8QI_V8QI:
20855 case V1DI_FTYPE_V2SI_V2SI:
20856 if (comparison == UNKNOWN)
20857 return ix86_expand_binop_builtin (icode, exp, target);
20860 case V4SF_FTYPE_V4SF_V4SF_SWAP:
20861 case V2DF_FTYPE_V2DF_V2DF_SWAP:
20862 gcc_assert (comparison != UNKNOWN);
20866 case V8HI_FTYPE_V8HI_V8HI_COUNT:
20867 case V8HI_FTYPE_V8HI_SI_COUNT:
20868 case V4SI_FTYPE_V4SI_V4SI_COUNT:
20869 case V4SI_FTYPE_V4SI_SI_COUNT:
20870 case V4HI_FTYPE_V4HI_V4HI_COUNT:
20871 case V4HI_FTYPE_V4HI_SI_COUNT:
20872 case V2DI_FTYPE_V2DI_V2DI_COUNT:
20873 case V2DI_FTYPE_V2DI_SI_COUNT:
20874 case V2SI_FTYPE_V2SI_V2SI_COUNT:
20875 case V2SI_FTYPE_V2SI_SI_COUNT:
20876 case V1DI_FTYPE_V1DI_V1DI_COUNT:
20877 case V1DI_FTYPE_V1DI_SI_COUNT:
20879 last_arg_count = true;
20881 case UINT64_FTYPE_UINT64_UINT64:
20882 case UINT_FTYPE_UINT_UINT:
20883 case UINT_FTYPE_UINT_USHORT:
20884 case UINT_FTYPE_UINT_UCHAR:
20887 case V2DI2TI_FTYPE_V2DI_INT:
20890 nargs_constant = 1;
20892 case V8HI_FTYPE_V8HI_INT:
20893 case V4SI_FTYPE_V4SI_INT:
20894 case V4HI_FTYPE_V4HI_INT:
20895 case V4SF_FTYPE_V4SF_INT:
20896 case V2DI_FTYPE_V2DI_INT:
20897 case V2DF_FTYPE_V2DF_INT:
20899 nargs_constant = 1;
20901 case V16QI_FTYPE_V16QI_V16QI_V16QI:
20902 case V4SF_FTYPE_V4SF_V4SF_V4SF:
20903 case V2DF_FTYPE_V2DF_V2DF_V2DF:
20906 case V16QI_FTYPE_V16QI_V16QI_INT:
20907 case V8HI_FTYPE_V8HI_V8HI_INT:
20908 case V4SI_FTYPE_V4SI_V4SI_INT:
20909 case V4SF_FTYPE_V4SF_V4SF_INT:
20910 case V2DI_FTYPE_V2DI_V2DI_INT:
20911 case V2DF_FTYPE_V2DF_V2DF_INT:
20913 nargs_constant = 1;
20915 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
20918 nargs_constant = 1;
20920 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
20923 nargs_constant = 1;
20925 case V2DI_FTYPE_V2DI_UINT_UINT:
20927 nargs_constant = 2;
20929 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
20931 nargs_constant = 2;
20934 gcc_unreachable ();
20937 gcc_assert (nargs <= ARRAY_SIZE (args));
20939 if (comparison != UNKNOWN)
20941 gcc_assert (nargs == 2);
20942 return ix86_expand_sse_compare (d, exp, target, swap);
20945 if (rmode == VOIDmode || rmode == tmode)
20949 || GET_MODE (target) != tmode
20950 || ! (*insn_p->operand[0].predicate) (target, tmode))
20951 target = gen_reg_rtx (tmode);
20952 real_target = target;
20956 target = gen_reg_rtx (rmode);
20957 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
20960 for (i = 0; i < nargs; i++)
20962 tree arg = CALL_EXPR_ARG (exp, i);
20963 rtx op = expand_normal (arg);
20964 enum machine_mode mode = insn_p->operand[i + 1].mode;
20965 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
20967 if (last_arg_count && (i + 1) == nargs)
20969 /* SIMD shift insns take either an 8-bit immediate or
20970 register as count. But builtin functions take int as
20971 count. If count doesn't match, we put it in register. */
20974 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
20975 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
20976 op = copy_to_reg (op);
20979 else if ((nargs - i) <= nargs_constant)
20984 case CODE_FOR_sse4_1_roundpd:
20985 case CODE_FOR_sse4_1_roundps:
20986 case CODE_FOR_sse4_1_roundsd:
20987 case CODE_FOR_sse4_1_roundss:
20988 case CODE_FOR_sse4_1_blendps:
20989 error ("the last argument must be a 4-bit immediate");
20992 case CODE_FOR_sse4_1_blendpd:
20993 error ("the last argument must be a 2-bit immediate");
20997 switch (nargs_constant)
21000 if ((nargs - i) == nargs_constant)
21002 error ("the next to last argument must be an 8-bit immediate");
21006 error ("the last argument must be an 8-bit immediate");
21009 gcc_unreachable ();
21016 if (VECTOR_MODE_P (mode))
21017 op = safe_vector_operand (op, mode);
21019 /* If we aren't optimizing, only allow one memory operand to
21021 if (memory_operand (op, mode))
21024 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
21026 if (optimize || !match || num_memory > 1)
21027 op = copy_to_mode_reg (mode, op);
21031 op = copy_to_reg (op);
21032 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
21037 args[i].mode = mode;
21043 pat = GEN_FCN (icode) (real_target, args[0].op);
21046 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
21049 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
21053 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
21054 args[2].op, args[3].op);
21057 gcc_unreachable ();
21067 /* Subroutine of ix86_expand_builtin to take care of special insns
21068 with variable number of operands. */
21071 ix86_expand_special_args_builtin (const struct builtin_description *d,
21072 tree exp, rtx target)
21076 unsigned int i, nargs, arg_adjust, memory;
21080 enum machine_mode mode;
21082 enum insn_code icode = d->icode;
21083 bool last_arg_constant = false;
21084 const struct insn_data *insn_p = &insn_data[icode];
21085 enum machine_mode tmode = insn_p->operand[0].mode;
21086 enum { load, store } class;
21088 switch ((enum ix86_special_builtin_type) d->flag)
21090 case VOID_FTYPE_VOID:
21091 emit_insn (GEN_FCN (icode) (target));
21093 case V2DI_FTYPE_PV2DI:
21094 case V16QI_FTYPE_PCCHAR:
21095 case V4SF_FTYPE_PCFLOAT:
21096 case V2DF_FTYPE_PCDOUBLE:
21101 case VOID_FTYPE_PV2SF_V4SF:
21102 case VOID_FTYPE_PV2DI_V2DI:
21103 case VOID_FTYPE_PCHAR_V16QI:
21104 case VOID_FTYPE_PFLOAT_V4SF:
21105 case VOID_FTYPE_PDOUBLE_V2DF:
21106 case VOID_FTYPE_PDI_DI:
21107 case VOID_FTYPE_PINT_INT:
21110 /* Reserve memory operand for target. */
21111 memory = ARRAY_SIZE (args);
21113 case V4SF_FTYPE_V4SF_PCV2SF:
21114 case V2DF_FTYPE_V2DF_PCDOUBLE:
21120 gcc_unreachable ();
21123 gcc_assert (nargs <= ARRAY_SIZE (args));
21125 if (class == store)
21127 arg = CALL_EXPR_ARG (exp, 0);
21128 op = expand_normal (arg);
21129 gcc_assert (target == 0);
21130 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
21138 || GET_MODE (target) != tmode
21139 || ! (*insn_p->operand[0].predicate) (target, tmode))
21140 target = gen_reg_rtx (tmode);
21143 for (i = 0; i < nargs; i++)
21145 enum machine_mode mode = insn_p->operand[i + 1].mode;
21148 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
21149 op = expand_normal (arg);
21150 match = (*insn_p->operand[i + 1].predicate) (op, mode);
21152 if (last_arg_constant && (i + 1) == nargs)
21158 error ("the last argument must be an 8-bit immediate");
21166 /* This must be the memory operand. */
21167 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
21168 gcc_assert (GET_MODE (op) == mode
21169 || GET_MODE (op) == VOIDmode);
21173 /* This must be register. */
21174 if (VECTOR_MODE_P (mode))
21175 op = safe_vector_operand (op, mode);
21177 gcc_assert (GET_MODE (op) == mode
21178 || GET_MODE (op) == VOIDmode);
21179 op = copy_to_mode_reg (mode, op);
21184 args[i].mode = mode;
21190 pat = GEN_FCN (icode) (target, args[0].op);
21193 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
21196 gcc_unreachable ();
21202 return class == store ? 0 : target;
21205 /* Return the integer constant in ARG. Constrain it to be in the range
21206 of the subparts of VEC_TYPE; issue an error if not. */
21209 get_element_number (tree vec_type, tree arg)
21211 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
21213 if (!host_integerp (arg, 1)
21214 || (elt = tree_low_cst (arg, 1), elt > max))
21216 error ("selector must be an integer constant in the range 0..%wi", max);
21223 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
21224 ix86_expand_vector_init. We DO have language-level syntax for this, in
21225 the form of (type){ init-list }. Except that since we can't place emms
21226 instructions from inside the compiler, we can't allow the use of MMX
21227 registers unless the user explicitly asks for it. So we do *not* define
21228 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
21229 we have builtins invoked by mmintrin.h that gives us license to emit
21230 these sorts of instructions. */
21233 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
21235 enum machine_mode tmode = TYPE_MODE (type);
21236 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
21237 int i, n_elt = GET_MODE_NUNITS (tmode);
21238 rtvec v = rtvec_alloc (n_elt);
21240 gcc_assert (VECTOR_MODE_P (tmode));
21241 gcc_assert (call_expr_nargs (exp) == n_elt);
21243 for (i = 0; i < n_elt; ++i)
21245 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
21246 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
21249 if (!target || !register_operand (target, tmode))
21250 target = gen_reg_rtx (tmode);
21252 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
21256 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
21257 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
21258 had a language-level syntax for referencing vector elements. */
21261 ix86_expand_vec_ext_builtin (tree exp, rtx target)
21263 enum machine_mode tmode, mode0;
21268 arg0 = CALL_EXPR_ARG (exp, 0);
21269 arg1 = CALL_EXPR_ARG (exp, 1);
21271 op0 = expand_normal (arg0);
21272 elt = get_element_number (TREE_TYPE (arg0), arg1);
21274 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
21275 mode0 = TYPE_MODE (TREE_TYPE (arg0));
21276 gcc_assert (VECTOR_MODE_P (mode0));
21278 op0 = force_reg (mode0, op0);
21280 if (optimize || !target || !register_operand (target, tmode))
21281 target = gen_reg_rtx (tmode);
21283 ix86_expand_vector_extract (true, target, op0, elt);
21288 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
21289 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
21290 a language-level syntax for referencing vector elements. */
21293 ix86_expand_vec_set_builtin (tree exp)
21295 enum machine_mode tmode, mode1;
21296 tree arg0, arg1, arg2;
21298 rtx op0, op1, target;
21300 arg0 = CALL_EXPR_ARG (exp, 0);
21301 arg1 = CALL_EXPR_ARG (exp, 1);
21302 arg2 = CALL_EXPR_ARG (exp, 2);
21304 tmode = TYPE_MODE (TREE_TYPE (arg0));
21305 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
21306 gcc_assert (VECTOR_MODE_P (tmode));
21308 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
21309 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
21310 elt = get_element_number (TREE_TYPE (arg0), arg2);
21312 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
21313 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
21315 op0 = force_reg (tmode, op0);
21316 op1 = force_reg (mode1, op1);
21318 /* OP0 is the source of these builtin functions and shouldn't be
21319 modified. Create a copy, use it and return it as target. */
21320 target = gen_reg_rtx (tmode);
21321 emit_move_insn (target, op0);
21322 ix86_expand_vector_set (true, target, op1, elt);
21327 /* Expand an expression EXP that calls a built-in function,
21328 with result going to TARGET if that's convenient
21329 (and in mode MODE if that's convenient).
21330 SUBTARGET may be used as the target for computing one of EXP's operands.
21331 IGNORE is nonzero if the value is to be ignored. */
21334 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
21335 enum machine_mode mode ATTRIBUTE_UNUSED,
21336 int ignore ATTRIBUTE_UNUSED)
21338 const struct builtin_description *d;
21340 enum insn_code icode;
21341 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
21342 tree arg0, arg1, arg2;
21343 rtx op0, op1, op2, pat;
21344 enum machine_mode mode0, mode1, mode2;
21345 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
21349 case IX86_BUILTIN_MASKMOVQ:
21350 case IX86_BUILTIN_MASKMOVDQU:
21351 icode = (fcode == IX86_BUILTIN_MASKMOVQ
21352 ? CODE_FOR_mmx_maskmovq
21353 : CODE_FOR_sse2_maskmovdqu);
21354 /* Note the arg order is different from the operand order. */
21355 arg1 = CALL_EXPR_ARG (exp, 0);
21356 arg2 = CALL_EXPR_ARG (exp, 1);
21357 arg0 = CALL_EXPR_ARG (exp, 2);
21358 op0 = expand_normal (arg0);
21359 op1 = expand_normal (arg1);
21360 op2 = expand_normal (arg2);
21361 mode0 = insn_data[icode].operand[0].mode;
21362 mode1 = insn_data[icode].operand[1].mode;
21363 mode2 = insn_data[icode].operand[2].mode;
21365 op0 = force_reg (Pmode, op0);
21366 op0 = gen_rtx_MEM (mode1, op0);
21368 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
21369 op0 = copy_to_mode_reg (mode0, op0);
21370 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
21371 op1 = copy_to_mode_reg (mode1, op1);
21372 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
21373 op2 = copy_to_mode_reg (mode2, op2);
21374 pat = GEN_FCN (icode) (op0, op1, op2);
21380 case IX86_BUILTIN_LDMXCSR:
21381 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
21382 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
21383 emit_move_insn (target, op0);
21384 emit_insn (gen_sse_ldmxcsr (target));
21387 case IX86_BUILTIN_STMXCSR:
21388 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
21389 emit_insn (gen_sse_stmxcsr (target));
21390 return copy_to_mode_reg (SImode, target);
21392 case IX86_BUILTIN_CLFLUSH:
21393 arg0 = CALL_EXPR_ARG (exp, 0);
21394 op0 = expand_normal (arg0);
21395 icode = CODE_FOR_sse2_clflush;
21396 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
21397 op0 = copy_to_mode_reg (Pmode, op0);
21399 emit_insn (gen_sse2_clflush (op0));
21402 case IX86_BUILTIN_MONITOR:
21403 arg0 = CALL_EXPR_ARG (exp, 0);
21404 arg1 = CALL_EXPR_ARG (exp, 1);
21405 arg2 = CALL_EXPR_ARG (exp, 2);
21406 op0 = expand_normal (arg0);
21407 op1 = expand_normal (arg1);
21408 op2 = expand_normal (arg2);
21410 op0 = copy_to_mode_reg (Pmode, op0);
21412 op1 = copy_to_mode_reg (SImode, op1);
21414 op2 = copy_to_mode_reg (SImode, op2);
21416 emit_insn (gen_sse3_monitor (op0, op1, op2));
21418 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
21421 case IX86_BUILTIN_MWAIT:
21422 arg0 = CALL_EXPR_ARG (exp, 0);
21423 arg1 = CALL_EXPR_ARG (exp, 1);
21424 op0 = expand_normal (arg0);
21425 op1 = expand_normal (arg1);
21427 op0 = copy_to_mode_reg (SImode, op0);
21429 op1 = copy_to_mode_reg (SImode, op1);
21430 emit_insn (gen_sse3_mwait (op0, op1));
21433 case IX86_BUILTIN_VEC_INIT_V2SI:
21434 case IX86_BUILTIN_VEC_INIT_V4HI:
21435 case IX86_BUILTIN_VEC_INIT_V8QI:
21436 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
21438 case IX86_BUILTIN_VEC_EXT_V2DF:
21439 case IX86_BUILTIN_VEC_EXT_V2DI:
21440 case IX86_BUILTIN_VEC_EXT_V4SF:
21441 case IX86_BUILTIN_VEC_EXT_V4SI:
21442 case IX86_BUILTIN_VEC_EXT_V8HI:
21443 case IX86_BUILTIN_VEC_EXT_V2SI:
21444 case IX86_BUILTIN_VEC_EXT_V4HI:
21445 case IX86_BUILTIN_VEC_EXT_V16QI:
21446 return ix86_expand_vec_ext_builtin (exp, target);
21448 case IX86_BUILTIN_VEC_SET_V2DI:
21449 case IX86_BUILTIN_VEC_SET_V4SF:
21450 case IX86_BUILTIN_VEC_SET_V4SI:
21451 case IX86_BUILTIN_VEC_SET_V8HI:
21452 case IX86_BUILTIN_VEC_SET_V4HI:
21453 case IX86_BUILTIN_VEC_SET_V16QI:
21454 return ix86_expand_vec_set_builtin (exp);
21456 case IX86_BUILTIN_INFQ:
21458 REAL_VALUE_TYPE inf;
21462 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
21464 tmp = validize_mem (force_const_mem (mode, tmp));
21467 target = gen_reg_rtx (mode);
21469 emit_move_insn (target, tmp);
21477 for (i = 0, d = bdesc_special_args;
21478 i < ARRAY_SIZE (bdesc_special_args);
21480 if (d->code == fcode)
21481 return ix86_expand_special_args_builtin (d, exp, target);
21483 for (i = 0, d = bdesc_args;
21484 i < ARRAY_SIZE (bdesc_args);
21486 if (d->code == fcode)
21487 return ix86_expand_args_builtin (d, exp, target);
21489 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
21490 if (d->code == fcode)
21491 return ix86_expand_sse_comi (d, exp, target);
21493 for (i = 0, d = bdesc_pcmpestr;
21494 i < ARRAY_SIZE (bdesc_pcmpestr);
21496 if (d->code == fcode)
21497 return ix86_expand_sse_pcmpestr (d, exp, target);
21499 for (i = 0, d = bdesc_pcmpistr;
21500 i < ARRAY_SIZE (bdesc_pcmpistr);
21502 if (d->code == fcode)
21503 return ix86_expand_sse_pcmpistr (d, exp, target);
21505 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
21506 if (d->code == fcode)
21507 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
21508 (enum multi_arg_type)d->flag,
21511 gcc_unreachable ();
21514 /* Returns a function decl for a vectorized version of the builtin function
21515 with builtin function code FN and the result vector type TYPE, or NULL_TREE
21516 if it is not available. */
21519 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
21522 enum machine_mode in_mode, out_mode;
21525 if (TREE_CODE (type_out) != VECTOR_TYPE
21526 || TREE_CODE (type_in) != VECTOR_TYPE)
21529 out_mode = TYPE_MODE (TREE_TYPE (type_out));
21530 out_n = TYPE_VECTOR_SUBPARTS (type_out);
21531 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21532 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21536 case BUILT_IN_SQRT:
21537 if (out_mode == DFmode && out_n == 2
21538 && in_mode == DFmode && in_n == 2)
21539 return ix86_builtins[IX86_BUILTIN_SQRTPD];
21542 case BUILT_IN_SQRTF:
21543 if (out_mode == SFmode && out_n == 4
21544 && in_mode == SFmode && in_n == 4)
21545 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
21548 case BUILT_IN_LRINT:
21549 if (out_mode == SImode && out_n == 4
21550 && in_mode == DFmode && in_n == 2)
21551 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
21554 case BUILT_IN_LRINTF:
21555 if (out_mode == SImode && out_n == 4
21556 && in_mode == SFmode && in_n == 4)
21557 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
21564 /* Dispatch to a handler for a vectorization library. */
21565 if (ix86_veclib_handler)
21566 return (*ix86_veclib_handler)(fn, type_out, type_in);
21571 /* Handler for an SVML-style interface to
21572 a library with vectorized intrinsics. */
21575 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
21578 tree fntype, new_fndecl, args;
21581 enum machine_mode el_mode, in_mode;
21584 /* The SVML is suitable for unsafe math only. */
21585 if (!flag_unsafe_math_optimizations)
21588 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21589 n = TYPE_VECTOR_SUBPARTS (type_out);
21590 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21591 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21592 if (el_mode != in_mode
21600 case BUILT_IN_LOG10:
21602 case BUILT_IN_TANH:
21604 case BUILT_IN_ATAN:
21605 case BUILT_IN_ATAN2:
21606 case BUILT_IN_ATANH:
21607 case BUILT_IN_CBRT:
21608 case BUILT_IN_SINH:
21610 case BUILT_IN_ASINH:
21611 case BUILT_IN_ASIN:
21612 case BUILT_IN_COSH:
21614 case BUILT_IN_ACOSH:
21615 case BUILT_IN_ACOS:
21616 if (el_mode != DFmode || n != 2)
21620 case BUILT_IN_EXPF:
21621 case BUILT_IN_LOGF:
21622 case BUILT_IN_LOG10F:
21623 case BUILT_IN_POWF:
21624 case BUILT_IN_TANHF:
21625 case BUILT_IN_TANF:
21626 case BUILT_IN_ATANF:
21627 case BUILT_IN_ATAN2F:
21628 case BUILT_IN_ATANHF:
21629 case BUILT_IN_CBRTF:
21630 case BUILT_IN_SINHF:
21631 case BUILT_IN_SINF:
21632 case BUILT_IN_ASINHF:
21633 case BUILT_IN_ASINF:
21634 case BUILT_IN_COSHF:
21635 case BUILT_IN_COSF:
21636 case BUILT_IN_ACOSHF:
21637 case BUILT_IN_ACOSF:
21638 if (el_mode != SFmode || n != 4)
21646 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21648 if (fn == BUILT_IN_LOGF)
21649 strcpy (name, "vmlsLn4");
21650 else if (fn == BUILT_IN_LOG)
21651 strcpy (name, "vmldLn2");
21654 sprintf (name, "vmls%s", bname+10);
21655 name[strlen (name)-1] = '4';
21658 sprintf (name, "vmld%s2", bname+10);
21660 /* Convert to uppercase. */
21664 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21665 args = TREE_CHAIN (args))
21669 fntype = build_function_type_list (type_out, type_in, NULL);
21671 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21673 /* Build a function declaration for the vectorized function. */
21674 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21675 TREE_PUBLIC (new_fndecl) = 1;
21676 DECL_EXTERNAL (new_fndecl) = 1;
21677 DECL_IS_NOVOPS (new_fndecl) = 1;
21678 TREE_READONLY (new_fndecl) = 1;
21683 /* Handler for an ACML-style interface to
21684 a library with vectorized intrinsics. */
21687 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
21689 char name[20] = "__vr.._";
21690 tree fntype, new_fndecl, args;
21693 enum machine_mode el_mode, in_mode;
21696 /* The ACML is 64bits only and suitable for unsafe math only as
21697 it does not correctly support parts of IEEE with the required
21698 precision such as denormals. */
21700 || !flag_unsafe_math_optimizations)
21703 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21704 n = TYPE_VECTOR_SUBPARTS (type_out);
21705 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21706 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21707 if (el_mode != in_mode
21717 case BUILT_IN_LOG2:
21718 case BUILT_IN_LOG10:
21721 if (el_mode != DFmode
21726 case BUILT_IN_SINF:
21727 case BUILT_IN_COSF:
21728 case BUILT_IN_EXPF:
21729 case BUILT_IN_POWF:
21730 case BUILT_IN_LOGF:
21731 case BUILT_IN_LOG2F:
21732 case BUILT_IN_LOG10F:
21735 if (el_mode != SFmode
21744 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21745 sprintf (name + 7, "%s", bname+10);
21748 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21749 args = TREE_CHAIN (args))
21753 fntype = build_function_type_list (type_out, type_in, NULL);
21755 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21757 /* Build a function declaration for the vectorized function. */
21758 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21759 TREE_PUBLIC (new_fndecl) = 1;
21760 DECL_EXTERNAL (new_fndecl) = 1;
21761 DECL_IS_NOVOPS (new_fndecl) = 1;
21762 TREE_READONLY (new_fndecl) = 1;
21768 /* Returns a decl of a function that implements conversion of the
21769 input vector of type TYPE, or NULL_TREE if it is not available. */
21772 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
21774 if (TREE_CODE (type) != VECTOR_TYPE)
21780 switch (TYPE_MODE (type))
21783 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
21788 case FIX_TRUNC_EXPR:
21789 switch (TYPE_MODE (type))
21792 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
21802 /* Returns a code for a target-specific builtin that implements
21803 reciprocal of the function, or NULL_TREE if not available. */
21806 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
21807 bool sqrt ATTRIBUTE_UNUSED)
21809 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
21810 && flag_finite_math_only && !flag_trapping_math
21811 && flag_unsafe_math_optimizations))
21815 /* Machine dependent builtins. */
21818 /* Vectorized version of sqrt to rsqrt conversion. */
21819 case IX86_BUILTIN_SQRTPS_NR:
21820 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
21826 /* Normal builtins. */
21829 /* Sqrt to rsqrt conversion. */
21830 case BUILT_IN_SQRTF:
21831 return ix86_builtins[IX86_BUILTIN_RSQRTF];
21838 /* Store OPERAND to the memory after reload is completed. This means
21839 that we can't easily use assign_stack_local. */
21841 ix86_force_to_memory (enum machine_mode mode, rtx operand)
21845 gcc_assert (reload_completed);
21846 if (TARGET_RED_ZONE)
21848 result = gen_rtx_MEM (mode,
21849 gen_rtx_PLUS (Pmode,
21851 GEN_INT (-RED_ZONE_SIZE)));
21852 emit_move_insn (result, operand);
21854 else if (!TARGET_RED_ZONE && TARGET_64BIT)
21860 operand = gen_lowpart (DImode, operand);
21864 gen_rtx_SET (VOIDmode,
21865 gen_rtx_MEM (DImode,
21866 gen_rtx_PRE_DEC (DImode,
21867 stack_pointer_rtx)),
21871 gcc_unreachable ();
21873 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21882 split_di (&operand, 1, operands, operands + 1);
21884 gen_rtx_SET (VOIDmode,
21885 gen_rtx_MEM (SImode,
21886 gen_rtx_PRE_DEC (Pmode,
21887 stack_pointer_rtx)),
21890 gen_rtx_SET (VOIDmode,
21891 gen_rtx_MEM (SImode,
21892 gen_rtx_PRE_DEC (Pmode,
21893 stack_pointer_rtx)),
21898 /* Store HImodes as SImodes. */
21899 operand = gen_lowpart (SImode, operand);
21903 gen_rtx_SET (VOIDmode,
21904 gen_rtx_MEM (GET_MODE (operand),
21905 gen_rtx_PRE_DEC (SImode,
21906 stack_pointer_rtx)),
21910 gcc_unreachable ();
21912 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21917 /* Free operand from the memory. */
21919 ix86_free_from_memory (enum machine_mode mode)
21921 if (!TARGET_RED_ZONE)
21925 if (mode == DImode || TARGET_64BIT)
21929 /* Use LEA to deallocate stack space. In peephole2 it will be converted
21930 to pop or add instruction if registers are available. */
21931 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
21932 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
21937 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
21938 QImode must go into class Q_REGS.
21939 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
21940 movdf to do mem-to-mem moves through integer regs. */
21942 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
21944 enum machine_mode mode = GET_MODE (x);
21946 /* We're only allowed to return a subclass of CLASS. Many of the
21947 following checks fail for NO_REGS, so eliminate that early. */
21948 if (regclass == NO_REGS)
21951 /* All classes can load zeros. */
21952 if (x == CONST0_RTX (mode))
21955 /* Force constants into memory if we are loading a (nonzero) constant into
21956 an MMX or SSE register. This is because there are no MMX/SSE instructions
21957 to load from a constant. */
21959 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
21962 /* Prefer SSE regs only, if we can use them for math. */
21963 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
21964 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
21966 /* Floating-point constants need more complex checks. */
21967 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
21969 /* General regs can load everything. */
21970 if (reg_class_subset_p (regclass, GENERAL_REGS))
21973 /* Floats can load 0 and 1 plus some others. Note that we eliminated
21974 zero above. We only want to wind up preferring 80387 registers if
21975 we plan on doing computation with them. */
21977 && standard_80387_constant_p (x))
21979 /* Limit class to non-sse. */
21980 if (regclass == FLOAT_SSE_REGS)
21982 if (regclass == FP_TOP_SSE_REGS)
21984 if (regclass == FP_SECOND_SSE_REGS)
21985 return FP_SECOND_REG;
21986 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
21993 /* Generally when we see PLUS here, it's the function invariant
21994 (plus soft-fp const_int). Which can only be computed into general
21996 if (GET_CODE (x) == PLUS)
21997 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
21999 /* QImode constants are easy to load, but non-constant QImode data
22000 must go into Q_REGS. */
22001 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
22003 if (reg_class_subset_p (regclass, Q_REGS))
22005 if (reg_class_subset_p (Q_REGS, regclass))
22013 /* Discourage putting floating-point values in SSE registers unless
22014 SSE math is being used, and likewise for the 387 registers. */
22016 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
22018 enum machine_mode mode = GET_MODE (x);
22020 /* Restrict the output reload class to the register bank that we are doing
22021 math on. If we would like not to return a subset of CLASS, reject this
22022 alternative: if reload cannot do this, it will still use its choice. */
22023 mode = GET_MODE (x);
22024 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
22025 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
22027 if (X87_FLOAT_MODE_P (mode))
22029 if (regclass == FP_TOP_SSE_REGS)
22031 else if (regclass == FP_SECOND_SSE_REGS)
22032 return FP_SECOND_REG;
22034 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
22040 static enum reg_class
22041 ix86_secondary_reload (bool in_p, rtx x, enum reg_class class,
22042 enum machine_mode mode,
22043 secondary_reload_info *sri ATTRIBUTE_UNUSED)
22045 /* QImode spills from non-QI registers require
22046 intermediate register on 32bit targets. */
22047 if (!in_p && mode == QImode && !TARGET_64BIT
22048 && (class == GENERAL_REGS
22049 || class == LEGACY_REGS
22050 || class == INDEX_REGS))
22059 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
22060 regno = true_regnum (x);
22062 /* Return Q_REGS if the operand is in memory. */
22070 /* If we are copying between general and FP registers, we need a memory
22071 location. The same is true for SSE and MMX registers.
22073 To optimize register_move_cost performance, allow inline variant.
22075 The macro can't work reliably when one of the CLASSES is class containing
22076 registers from multiple units (SSE, MMX, integer). We avoid this by never
22077 combining those units in single alternative in the machine description.
22078 Ensure that this constraint holds to avoid unexpected surprises.
22080 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
22081 enforce these sanity checks. */
22084 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
22085 enum machine_mode mode, int strict)
22087 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
22088 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
22089 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
22090 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
22091 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
22092 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
22094 gcc_assert (!strict);
22098 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
22101 /* ??? This is a lie. We do have moves between mmx/general, and for
22102 mmx/sse2. But by saying we need secondary memory we discourage the
22103 register allocator from using the mmx registers unless needed. */
22104 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
22107 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22109 /* SSE1 doesn't have any direct moves from other classes. */
22113 /* If the target says that inter-unit moves are more expensive
22114 than moving through memory, then don't generate them. */
22115 if (!TARGET_INTER_UNIT_MOVES)
22118 /* Between SSE and general, we have moves no larger than word size. */
22119 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
22127 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
22128 enum machine_mode mode, int strict)
22130 return inline_secondary_memory_needed (class1, class2, mode, strict);
22133 /* Return true if the registers in CLASS cannot represent the change from
22134 modes FROM to TO. */
22137 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
22138 enum reg_class regclass)
22143 /* x87 registers can't do subreg at all, as all values are reformatted
22144 to extended precision. */
22145 if (MAYBE_FLOAT_CLASS_P (regclass))
22148 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
22150 /* Vector registers do not support QI or HImode loads. If we don't
22151 disallow a change to these modes, reload will assume it's ok to
22152 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
22153 the vec_dupv4hi pattern. */
22154 if (GET_MODE_SIZE (from) < 4)
22157 /* Vector registers do not support subreg with nonzero offsets, which
22158 are otherwise valid for integer registers. Since we can't see
22159 whether we have a nonzero offset from here, prohibit all
22160 nonparadoxical subregs changing size. */
22161 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
22168 /* Return the cost of moving data of mode M between a
22169 register and memory. A value of 2 is the default; this cost is
22170 relative to those in `REGISTER_MOVE_COST'.
22172 This function is used extensively by register_move_cost that is used to
22173 build tables at startup. Make it inline in this case.
22174 When IN is 2, return maximum of in and out move cost.
22176 If moving between registers and memory is more expensive than
22177 between two registers, you should define this macro to express the
22180 Model also increased moving costs of QImode registers in non
22184 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
22188 if (FLOAT_CLASS_P (regclass))
22206 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
22207 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
22209 if (SSE_CLASS_P (regclass))
22212 switch (GET_MODE_SIZE (mode))
22227 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
22228 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
22230 if (MMX_CLASS_P (regclass))
22233 switch (GET_MODE_SIZE (mode))
22245 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
22246 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
22248 switch (GET_MODE_SIZE (mode))
22251 if (Q_CLASS_P (regclass) || TARGET_64BIT)
22254 return ix86_cost->int_store[0];
22255 if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
22256 cost = ix86_cost->movzbl_load;
22258 cost = ix86_cost->int_load[0];
22260 return MAX (cost, ix86_cost->int_store[0]);
22266 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
22268 return ix86_cost->movzbl_load;
22270 return ix86_cost->int_store[0] + 4;
22275 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
22276 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
22278 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
22279 if (mode == TFmode)
22282 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
22284 cost = ix86_cost->int_load[2];
22286 cost = ix86_cost->int_store[2];
22287 return (cost * (((int) GET_MODE_SIZE (mode)
22288 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
22293 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
22295 return inline_memory_move_cost (mode, regclass, in);
22299 /* Return the cost of moving data from a register in class CLASS1 to
22300 one in class CLASS2.
22302 It is not required that the cost always equal 2 when FROM is the same as TO;
22303 on some machines it is expensive to move between registers if they are not
22304 general registers. */
22307 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
22308 enum reg_class class2)
22310 /* In case we require secondary memory, compute cost of the store followed
22311 by load. In order to avoid bad register allocation choices, we need
22312 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
22314 if (inline_secondary_memory_needed (class1, class2, mode, 0))
22318 cost += inline_memory_move_cost (mode, class1, 2);
22319 cost += inline_memory_move_cost (mode, class2, 2);
22321 /* In case of copying from general_purpose_register we may emit multiple
22322 stores followed by single load causing memory size mismatch stall.
22323 Count this as arbitrarily high cost of 20. */
22324 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
22327 /* In the case of FP/MMX moves, the registers actually overlap, and we
22328 have to switch modes in order to treat them differently. */
22329 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
22330 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
22336 /* Moves between SSE/MMX and integer unit are expensive. */
22337 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
22338 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22340 /* ??? By keeping returned value relatively high, we limit the number
22341 of moves between integer and MMX/SSE registers for all targets.
22342 Additionally, high value prevents problem with x86_modes_tieable_p(),
22343 where integer modes in MMX/SSE registers are not tieable
22344 because of missing QImode and HImode moves to, from or between
22345 MMX/SSE registers. */
22346 return MAX (8, ix86_cost->mmxsse_to_integer);
22348 if (MAYBE_FLOAT_CLASS_P (class1))
22349 return ix86_cost->fp_move;
22350 if (MAYBE_SSE_CLASS_P (class1))
22351 return ix86_cost->sse_move;
22352 if (MAYBE_MMX_CLASS_P (class1))
22353 return ix86_cost->mmx_move;
22357 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
22360 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
22362 /* Flags and only flags can only hold CCmode values. */
22363 if (CC_REGNO_P (regno))
22364 return GET_MODE_CLASS (mode) == MODE_CC;
22365 if (GET_MODE_CLASS (mode) == MODE_CC
22366 || GET_MODE_CLASS (mode) == MODE_RANDOM
22367 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
22369 if (FP_REGNO_P (regno))
22370 return VALID_FP_MODE_P (mode);
22371 if (SSE_REGNO_P (regno))
22373 /* We implement the move patterns for all vector modes into and
22374 out of SSE registers, even when no operation instructions
22376 return (VALID_SSE_REG_MODE (mode)
22377 || VALID_SSE2_REG_MODE (mode)
22378 || VALID_MMX_REG_MODE (mode)
22379 || VALID_MMX_REG_MODE_3DNOW (mode));
22381 if (MMX_REGNO_P (regno))
22383 /* We implement the move patterns for 3DNOW modes even in MMX mode,
22384 so if the register is available at all, then we can move data of
22385 the given mode into or out of it. */
22386 return (VALID_MMX_REG_MODE (mode)
22387 || VALID_MMX_REG_MODE_3DNOW (mode));
22390 if (mode == QImode)
22392 /* Take care for QImode values - they can be in non-QI regs,
22393 but then they do cause partial register stalls. */
22394 if (regno < 4 || TARGET_64BIT)
22396 if (!TARGET_PARTIAL_REG_STALL)
22398 return reload_in_progress || reload_completed;
22400 /* We handle both integer and floats in the general purpose registers. */
22401 else if (VALID_INT_MODE_P (mode))
22403 else if (VALID_FP_MODE_P (mode))
22405 else if (VALID_DFP_MODE_P (mode))
22407 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
22408 on to use that value in smaller contexts, this can easily force a
22409 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
22410 supporting DImode, allow it. */
22411 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
22417 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
22418 tieable integer mode. */
22421 ix86_tieable_integer_mode_p (enum machine_mode mode)
22430 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
22433 return TARGET_64BIT;
22440 /* Return true if MODE1 is accessible in a register that can hold MODE2
22441 without copying. That is, all register classes that can hold MODE2
22442 can also hold MODE1. */
22445 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
22447 if (mode1 == mode2)
22450 if (ix86_tieable_integer_mode_p (mode1)
22451 && ix86_tieable_integer_mode_p (mode2))
22454 /* MODE2 being XFmode implies fp stack or general regs, which means we
22455 can tie any smaller floating point modes to it. Note that we do not
22456 tie this with TFmode. */
22457 if (mode2 == XFmode)
22458 return mode1 == SFmode || mode1 == DFmode;
22460 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
22461 that we can tie it with SFmode. */
22462 if (mode2 == DFmode)
22463 return mode1 == SFmode;
22465 /* If MODE2 is only appropriate for an SSE register, then tie with
22466 any other mode acceptable to SSE registers. */
22467 if (GET_MODE_SIZE (mode2) == 16
22468 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
22469 return (GET_MODE_SIZE (mode1) == 16
22470 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
22472 /* If MODE2 is appropriate for an MMX register, then tie
22473 with any other mode acceptable to MMX registers. */
22474 if (GET_MODE_SIZE (mode2) == 8
22475 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
22476 return (GET_MODE_SIZE (mode1) == 8
22477 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
22482 /* Compute a (partial) cost for rtx X. Return true if the complete
22483 cost has been computed, and false if subexpressions should be
22484 scanned. In either case, *TOTAL contains the cost result. */
22487 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
22489 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
22490 enum machine_mode mode = GET_MODE (x);
22498 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
22500 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
22502 else if (flag_pic && SYMBOLIC_CONST (x)
22504 || (!GET_CODE (x) != LABEL_REF
22505 && (GET_CODE (x) != SYMBOL_REF
22506 || !SYMBOL_REF_LOCAL_P (x)))))
22513 if (mode == VOIDmode)
22516 switch (standard_80387_constant_p (x))
22521 default: /* Other constants */
22526 /* Start with (MEM (SYMBOL_REF)), since that's where
22527 it'll probably end up. Add a penalty for size. */
22528 *total = (COSTS_N_INSNS (1)
22529 + (flag_pic != 0 && !TARGET_64BIT)
22530 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
22536 /* The zero extensions is often completely free on x86_64, so make
22537 it as cheap as possible. */
22538 if (TARGET_64BIT && mode == DImode
22539 && GET_MODE (XEXP (x, 0)) == SImode)
22541 else if (TARGET_ZERO_EXTEND_WITH_AND)
22542 *total = ix86_cost->add;
22544 *total = ix86_cost->movzx;
22548 *total = ix86_cost->movsx;
22552 if (CONST_INT_P (XEXP (x, 1))
22553 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
22555 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22558 *total = ix86_cost->add;
22561 if ((value == 2 || value == 3)
22562 && ix86_cost->lea <= ix86_cost->shift_const)
22564 *total = ix86_cost->lea;
22574 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
22576 if (CONST_INT_P (XEXP (x, 1)))
22578 if (INTVAL (XEXP (x, 1)) > 32)
22579 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
22581 *total = ix86_cost->shift_const * 2;
22585 if (GET_CODE (XEXP (x, 1)) == AND)
22586 *total = ix86_cost->shift_var * 2;
22588 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
22593 if (CONST_INT_P (XEXP (x, 1)))
22594 *total = ix86_cost->shift_const;
22596 *total = ix86_cost->shift_var;
22601 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22603 /* ??? SSE scalar cost should be used here. */
22604 *total = ix86_cost->fmul;
22607 else if (X87_FLOAT_MODE_P (mode))
22609 *total = ix86_cost->fmul;
22612 else if (FLOAT_MODE_P (mode))
22614 /* ??? SSE vector cost should be used here. */
22615 *total = ix86_cost->fmul;
22620 rtx op0 = XEXP (x, 0);
22621 rtx op1 = XEXP (x, 1);
22623 if (CONST_INT_P (XEXP (x, 1)))
22625 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22626 for (nbits = 0; value != 0; value &= value - 1)
22630 /* This is arbitrary. */
22633 /* Compute costs correctly for widening multiplication. */
22634 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
22635 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
22636 == GET_MODE_SIZE (mode))
22638 int is_mulwiden = 0;
22639 enum machine_mode inner_mode = GET_MODE (op0);
22641 if (GET_CODE (op0) == GET_CODE (op1))
22642 is_mulwiden = 1, op1 = XEXP (op1, 0);
22643 else if (CONST_INT_P (op1))
22645 if (GET_CODE (op0) == SIGN_EXTEND)
22646 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
22649 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
22653 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
22656 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
22657 + nbits * ix86_cost->mult_bit
22658 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
22667 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22668 /* ??? SSE cost should be used here. */
22669 *total = ix86_cost->fdiv;
22670 else if (X87_FLOAT_MODE_P (mode))
22671 *total = ix86_cost->fdiv;
22672 else if (FLOAT_MODE_P (mode))
22673 /* ??? SSE vector cost should be used here. */
22674 *total = ix86_cost->fdiv;
22676 *total = ix86_cost->divide[MODE_INDEX (mode)];
22680 if (GET_MODE_CLASS (mode) == MODE_INT
22681 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
22683 if (GET_CODE (XEXP (x, 0)) == PLUS
22684 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
22685 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
22686 && CONSTANT_P (XEXP (x, 1)))
22688 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
22689 if (val == 2 || val == 4 || val == 8)
22691 *total = ix86_cost->lea;
22692 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22693 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
22695 *total += rtx_cost (XEXP (x, 1), outer_code);
22699 else if (GET_CODE (XEXP (x, 0)) == MULT
22700 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
22702 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
22703 if (val == 2 || val == 4 || val == 8)
22705 *total = ix86_cost->lea;
22706 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22707 *total += rtx_cost (XEXP (x, 1), outer_code);
22711 else if (GET_CODE (XEXP (x, 0)) == PLUS)
22713 *total = ix86_cost->lea;
22714 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22715 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22716 *total += rtx_cost (XEXP (x, 1), outer_code);
22723 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22725 /* ??? SSE cost should be used here. */
22726 *total = ix86_cost->fadd;
22729 else if (X87_FLOAT_MODE_P (mode))
22731 *total = ix86_cost->fadd;
22734 else if (FLOAT_MODE_P (mode))
22736 /* ??? SSE vector cost should be used here. */
22737 *total = ix86_cost->fadd;
22745 if (!TARGET_64BIT && mode == DImode)
22747 *total = (ix86_cost->add * 2
22748 + (rtx_cost (XEXP (x, 0), outer_code)
22749 << (GET_MODE (XEXP (x, 0)) != DImode))
22750 + (rtx_cost (XEXP (x, 1), outer_code)
22751 << (GET_MODE (XEXP (x, 1)) != DImode)));
22757 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22759 /* ??? SSE cost should be used here. */
22760 *total = ix86_cost->fchs;
22763 else if (X87_FLOAT_MODE_P (mode))
22765 *total = ix86_cost->fchs;
22768 else if (FLOAT_MODE_P (mode))
22770 /* ??? SSE vector cost should be used here. */
22771 *total = ix86_cost->fchs;
22777 if (!TARGET_64BIT && mode == DImode)
22778 *total = ix86_cost->add * 2;
22780 *total = ix86_cost->add;
22784 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
22785 && XEXP (XEXP (x, 0), 1) == const1_rtx
22786 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
22787 && XEXP (x, 1) == const0_rtx)
22789 /* This kind of construct is implemented using test[bwl].
22790 Treat it as if we had an AND. */
22791 *total = (ix86_cost->add
22792 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
22793 + rtx_cost (const1_rtx, outer_code));
22799 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
22804 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22805 /* ??? SSE cost should be used here. */
22806 *total = ix86_cost->fabs;
22807 else if (X87_FLOAT_MODE_P (mode))
22808 *total = ix86_cost->fabs;
22809 else if (FLOAT_MODE_P (mode))
22810 /* ??? SSE vector cost should be used here. */
22811 *total = ix86_cost->fabs;
22815 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22816 /* ??? SSE cost should be used here. */
22817 *total = ix86_cost->fsqrt;
22818 else if (X87_FLOAT_MODE_P (mode))
22819 *total = ix86_cost->fsqrt;
22820 else if (FLOAT_MODE_P (mode))
22821 /* ??? SSE vector cost should be used here. */
22822 *total = ix86_cost->fsqrt;
22826 if (XINT (x, 1) == UNSPEC_TP)
22837 static int current_machopic_label_num;
22839 /* Given a symbol name and its associated stub, write out the
22840 definition of the stub. */
22843 machopic_output_stub (FILE *file, const char *symb, const char *stub)
22845 unsigned int length;
22846 char *binder_name, *symbol_name, lazy_ptr_name[32];
22847 int label = ++current_machopic_label_num;
22849 /* For 64-bit we shouldn't get here. */
22850 gcc_assert (!TARGET_64BIT);
22852 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
22853 symb = (*targetm.strip_name_encoding) (symb);
22855 length = strlen (stub);
22856 binder_name = alloca (length + 32);
22857 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
22859 length = strlen (symb);
22860 symbol_name = alloca (length + 32);
22861 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
22863 sprintf (lazy_ptr_name, "L%d$lz", label);
22866 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
22868 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
22870 fprintf (file, "%s:\n", stub);
22871 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22875 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
22876 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
22877 fprintf (file, "\tjmp\t*%%edx\n");
22880 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
22882 fprintf (file, "%s:\n", binder_name);
22886 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
22887 fprintf (file, "\tpushl\t%%eax\n");
22890 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
22892 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
22894 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
22895 fprintf (file, "%s:\n", lazy_ptr_name);
22896 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22897 fprintf (file, "\t.long %s\n", binder_name);
22901 darwin_x86_file_end (void)
22903 darwin_file_end ();
22906 #endif /* TARGET_MACHO */
22908 /* Order the registers for register allocator. */
22911 x86_order_regs_for_local_alloc (void)
22916 /* First allocate the local general purpose registers. */
22917 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22918 if (GENERAL_REGNO_P (i) && call_used_regs[i])
22919 reg_alloc_order [pos++] = i;
22921 /* Global general purpose registers. */
22922 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22923 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
22924 reg_alloc_order [pos++] = i;
22926 /* x87 registers come first in case we are doing FP math
22928 if (!TARGET_SSE_MATH)
22929 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22930 reg_alloc_order [pos++] = i;
22932 /* SSE registers. */
22933 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
22934 reg_alloc_order [pos++] = i;
22935 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
22936 reg_alloc_order [pos++] = i;
22938 /* x87 registers. */
22939 if (TARGET_SSE_MATH)
22940 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22941 reg_alloc_order [pos++] = i;
22943 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
22944 reg_alloc_order [pos++] = i;
22946 /* Initialize the rest of array as we do not allocate some registers
22948 while (pos < FIRST_PSEUDO_REGISTER)
22949 reg_alloc_order [pos++] = 0;
22952 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
22953 struct attribute_spec.handler. */
22955 ix86_handle_struct_attribute (tree *node, tree name,
22956 tree args ATTRIBUTE_UNUSED,
22957 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
22960 if (DECL_P (*node))
22962 if (TREE_CODE (*node) == TYPE_DECL)
22963 type = &TREE_TYPE (*node);
22968 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
22969 || TREE_CODE (*type) == UNION_TYPE)))
22971 warning (OPT_Wattributes, "%qs attribute ignored",
22972 IDENTIFIER_POINTER (name));
22973 *no_add_attrs = true;
22976 else if ((is_attribute_p ("ms_struct", name)
22977 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
22978 || ((is_attribute_p ("gcc_struct", name)
22979 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
22981 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
22982 IDENTIFIER_POINTER (name));
22983 *no_add_attrs = true;
22990 ix86_ms_bitfield_layout_p (const_tree record_type)
22992 return (TARGET_MS_BITFIELD_LAYOUT &&
22993 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
22994 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
22997 /* Returns an expression indicating where the this parameter is
22998 located on entry to the FUNCTION. */
23001 x86_this_parameter (tree function)
23003 tree type = TREE_TYPE (function);
23004 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
23009 const int *parm_regs;
23011 if (TARGET_64BIT_MS_ABI)
23012 parm_regs = x86_64_ms_abi_int_parameter_registers;
23014 parm_regs = x86_64_int_parameter_registers;
23015 return gen_rtx_REG (DImode, parm_regs[aggr]);
23018 nregs = ix86_function_regparm (type, function);
23020 if (nregs > 0 && !stdarg_p (type))
23024 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
23025 regno = aggr ? DX_REG : CX_REG;
23033 return gen_rtx_MEM (SImode,
23034 plus_constant (stack_pointer_rtx, 4));
23037 return gen_rtx_REG (SImode, regno);
23040 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
23043 /* Determine whether x86_output_mi_thunk can succeed. */
23046 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
23047 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
23048 HOST_WIDE_INT vcall_offset, const_tree function)
23050 /* 64-bit can handle anything. */
23054 /* For 32-bit, everything's fine if we have one free register. */
23055 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
23058 /* Need a free register for vcall_offset. */
23062 /* Need a free register for GOT references. */
23063 if (flag_pic && !(*targetm.binds_local_p) (function))
23066 /* Otherwise ok. */
23070 /* Output the assembler code for a thunk function. THUNK_DECL is the
23071 declaration for the thunk function itself, FUNCTION is the decl for
23072 the target function. DELTA is an immediate constant offset to be
23073 added to THIS. If VCALL_OFFSET is nonzero, the word at
23074 *(*this + vcall_offset) should be added to THIS. */
23077 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
23078 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
23079 HOST_WIDE_INT vcall_offset, tree function)
23082 rtx this_param = x86_this_parameter (function);
23085 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
23086 pull it in now and let DELTA benefit. */
23087 if (REG_P (this_param))
23088 this_reg = this_param;
23089 else if (vcall_offset)
23091 /* Put the this parameter into %eax. */
23092 xops[0] = this_param;
23093 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
23095 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
23097 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
23100 this_reg = NULL_RTX;
23102 /* Adjust the this parameter by a fixed constant. */
23105 xops[0] = GEN_INT (delta);
23106 xops[1] = this_reg ? this_reg : this_param;
23109 if (!x86_64_general_operand (xops[0], DImode))
23111 tmp = gen_rtx_REG (DImode, R10_REG);
23113 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
23115 xops[1] = this_param;
23117 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
23120 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
23123 /* Adjust the this parameter by a value stored in the vtable. */
23127 tmp = gen_rtx_REG (DImode, R10_REG);
23130 int tmp_regno = CX_REG;
23131 if (lookup_attribute ("fastcall",
23132 TYPE_ATTRIBUTES (TREE_TYPE (function))))
23133 tmp_regno = AX_REG;
23134 tmp = gen_rtx_REG (SImode, tmp_regno);
23137 xops[0] = gen_rtx_MEM (Pmode, this_reg);
23140 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
23142 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
23144 /* Adjust the this parameter. */
23145 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
23146 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
23148 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
23149 xops[0] = GEN_INT (vcall_offset);
23151 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
23152 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
23154 xops[1] = this_reg;
23156 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
23158 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
23161 /* If necessary, drop THIS back to its stack slot. */
23162 if (this_reg && this_reg != this_param)
23164 xops[0] = this_reg;
23165 xops[1] = this_param;
23167 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
23169 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
23172 xops[0] = XEXP (DECL_RTL (function), 0);
23175 if (!flag_pic || (*targetm.binds_local_p) (function))
23176 output_asm_insn ("jmp\t%P0", xops);
23177 /* All thunks should be in the same object as their target,
23178 and thus binds_local_p should be true. */
23179 else if (TARGET_64BIT_MS_ABI)
23180 gcc_unreachable ();
23183 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
23184 tmp = gen_rtx_CONST (Pmode, tmp);
23185 tmp = gen_rtx_MEM (QImode, tmp);
23187 output_asm_insn ("jmp\t%A0", xops);
23192 if (!flag_pic || (*targetm.binds_local_p) (function))
23193 output_asm_insn ("jmp\t%P0", xops);
23198 rtx sym_ref = XEXP (DECL_RTL (function), 0);
23199 tmp = (gen_rtx_SYMBOL_REF
23201 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
23202 tmp = gen_rtx_MEM (QImode, tmp);
23204 output_asm_insn ("jmp\t%0", xops);
23207 #endif /* TARGET_MACHO */
23209 tmp = gen_rtx_REG (SImode, CX_REG);
23210 output_set_got (tmp, NULL_RTX);
23213 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
23214 output_asm_insn ("jmp\t{*}%1", xops);
23220 x86_file_start (void)
23222 default_file_start ();
23224 darwin_file_start ();
23226 if (X86_FILE_START_VERSION_DIRECTIVE)
23227 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
23228 if (X86_FILE_START_FLTUSED)
23229 fputs ("\t.global\t__fltused\n", asm_out_file);
23230 if (ix86_asm_dialect == ASM_INTEL)
23231 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
23235 x86_field_alignment (tree field, int computed)
23237 enum machine_mode mode;
23238 tree type = TREE_TYPE (field);
23240 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
23242 mode = TYPE_MODE (strip_array_types (type));
23243 if (mode == DFmode || mode == DCmode
23244 || GET_MODE_CLASS (mode) == MODE_INT
23245 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
23246 return MIN (32, computed);
23250 /* Output assembler code to FILE to increment profiler label # LABELNO
23251 for profiling a function entry. */
23253 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
23257 #ifndef NO_PROFILE_COUNTERS
23258 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
23261 if (!TARGET_64BIT_MS_ABI && flag_pic)
23262 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
23264 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
23268 #ifndef NO_PROFILE_COUNTERS
23269 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
23270 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
23272 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
23276 #ifndef NO_PROFILE_COUNTERS
23277 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
23278 PROFILE_COUNT_REGISTER);
23280 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
23284 /* We don't have exact information about the insn sizes, but we may assume
23285 quite safely that we are informed about all 1 byte insns and memory
23286 address sizes. This is enough to eliminate unnecessary padding in
23290 min_insn_size (rtx insn)
23294 if (!INSN_P (insn) || !active_insn_p (insn))
23297 /* Discard alignments we've emit and jump instructions. */
23298 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
23299 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
23302 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
23303 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
23306 /* Important case - calls are always 5 bytes.
23307 It is common to have many calls in the row. */
23309 && symbolic_reference_mentioned_p (PATTERN (insn))
23310 && !SIBLING_CALL_P (insn))
23312 if (get_attr_length (insn) <= 1)
23315 /* For normal instructions we may rely on the sizes of addresses
23316 and the presence of symbol to require 4 bytes of encoding.
23317 This is not the case for jumps where references are PC relative. */
23318 if (!JUMP_P (insn))
23320 l = get_attr_length_address (insn);
23321 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
23330 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
23334 ix86_avoid_jump_misspredicts (void)
23336 rtx insn, start = get_insns ();
23337 int nbytes = 0, njumps = 0;
23340 /* Look for all minimal intervals of instructions containing 4 jumps.
23341 The intervals are bounded by START and INSN. NBYTES is the total
23342 size of instructions in the interval including INSN and not including
23343 START. When the NBYTES is smaller than 16 bytes, it is possible
23344 that the end of START and INSN ends up in the same 16byte page.
23346 The smallest offset in the page INSN can start is the case where START
23347 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
23348 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
23350 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
23353 nbytes += min_insn_size (insn);
23355 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
23356 INSN_UID (insn), min_insn_size (insn));
23358 && GET_CODE (PATTERN (insn)) != ADDR_VEC
23359 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
23367 start = NEXT_INSN (start);
23368 if ((JUMP_P (start)
23369 && GET_CODE (PATTERN (start)) != ADDR_VEC
23370 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
23372 njumps--, isjump = 1;
23375 nbytes -= min_insn_size (start);
23377 gcc_assert (njumps >= 0);
23379 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
23380 INSN_UID (start), INSN_UID (insn), nbytes);
23382 if (njumps == 3 && isjump && nbytes < 16)
23384 int padsize = 15 - nbytes + min_insn_size (insn);
23387 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
23388 INSN_UID (insn), padsize);
23389 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
23394 /* AMD Athlon works faster
23395 when RET is not destination of conditional jump or directly preceded
23396 by other jump instruction. We avoid the penalty by inserting NOP just
23397 before the RET instructions in such cases. */
23399 ix86_pad_returns (void)
23404 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
23406 basic_block bb = e->src;
23407 rtx ret = BB_END (bb);
23409 bool replace = false;
23411 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
23412 || !maybe_hot_bb_p (bb))
23414 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
23415 if (active_insn_p (prev) || LABEL_P (prev))
23417 if (prev && LABEL_P (prev))
23422 FOR_EACH_EDGE (e, ei, bb->preds)
23423 if (EDGE_FREQUENCY (e) && e->src->index >= 0
23424 && !(e->flags & EDGE_FALLTHRU))
23429 prev = prev_active_insn (ret);
23431 && ((JUMP_P (prev) && any_condjump_p (prev))
23434 /* Empty functions get branch mispredict even when the jump destination
23435 is not visible to us. */
23436 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
23441 emit_insn_before (gen_return_internal_long (), ret);
23447 /* Implement machine specific optimizations. We implement padding of returns
23448 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
23452 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
23453 ix86_pad_returns ();
23454 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
23455 ix86_avoid_jump_misspredicts ();
23458 /* Return nonzero when QImode register that must be represented via REX prefix
23461 x86_extended_QIreg_mentioned_p (rtx insn)
23464 extract_insn_cached (insn);
23465 for (i = 0; i < recog_data.n_operands; i++)
23466 if (REG_P (recog_data.operand[i])
23467 && REGNO (recog_data.operand[i]) >= 4)
23472 /* Return nonzero when P points to register encoded via REX prefix.
23473 Called via for_each_rtx. */
23475 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
23477 unsigned int regno;
23480 regno = REGNO (*p);
23481 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
23484 /* Return true when INSN mentions register that must be encoded using REX
23487 x86_extended_reg_mentioned_p (rtx insn)
23489 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
23492 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
23493 optabs would emit if we didn't have TFmode patterns. */
23496 x86_emit_floatuns (rtx operands[2])
23498 rtx neglab, donelab, i0, i1, f0, in, out;
23499 enum machine_mode mode, inmode;
23501 inmode = GET_MODE (operands[1]);
23502 gcc_assert (inmode == SImode || inmode == DImode);
23505 in = force_reg (inmode, operands[1]);
23506 mode = GET_MODE (out);
23507 neglab = gen_label_rtx ();
23508 donelab = gen_label_rtx ();
23509 f0 = gen_reg_rtx (mode);
23511 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
23513 expand_float (out, in, 0);
23515 emit_jump_insn (gen_jump (donelab));
23518 emit_label (neglab);
23520 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
23522 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
23524 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
23526 expand_float (f0, i0, 0);
23528 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
23530 emit_label (donelab);
23533 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23534 with all elements equal to VAR. Return true if successful. */
23537 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
23538 rtx target, rtx val)
23540 enum machine_mode smode, wsmode, wvmode;
23555 val = force_reg (GET_MODE_INNER (mode), val);
23556 x = gen_rtx_VEC_DUPLICATE (mode, val);
23557 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23563 if (TARGET_SSE || TARGET_3DNOW_A)
23565 val = gen_lowpart (SImode, val);
23566 x = gen_rtx_TRUNCATE (HImode, val);
23567 x = gen_rtx_VEC_DUPLICATE (mode, x);
23568 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23590 /* Extend HImode to SImode using a paradoxical SUBREG. */
23591 tmp1 = gen_reg_rtx (SImode);
23592 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23593 /* Insert the SImode value as low element of V4SImode vector. */
23594 tmp2 = gen_reg_rtx (V4SImode);
23595 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23596 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23597 CONST0_RTX (V4SImode),
23599 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23600 /* Cast the V4SImode vector back to a V8HImode vector. */
23601 tmp1 = gen_reg_rtx (V8HImode);
23602 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
23603 /* Duplicate the low short through the whole low SImode word. */
23604 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
23605 /* Cast the V8HImode vector back to a V4SImode vector. */
23606 tmp2 = gen_reg_rtx (V4SImode);
23607 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23608 /* Replicate the low element of the V4SImode vector. */
23609 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23610 /* Cast the V2SImode back to V8HImode, and store in target. */
23611 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
23622 /* Extend QImode to SImode using a paradoxical SUBREG. */
23623 tmp1 = gen_reg_rtx (SImode);
23624 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23625 /* Insert the SImode value as low element of V4SImode vector. */
23626 tmp2 = gen_reg_rtx (V4SImode);
23627 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23628 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23629 CONST0_RTX (V4SImode),
23631 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23632 /* Cast the V4SImode vector back to a V16QImode vector. */
23633 tmp1 = gen_reg_rtx (V16QImode);
23634 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
23635 /* Duplicate the low byte through the whole low SImode word. */
23636 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23637 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23638 /* Cast the V16QImode vector back to a V4SImode vector. */
23639 tmp2 = gen_reg_rtx (V4SImode);
23640 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23641 /* Replicate the low element of the V4SImode vector. */
23642 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23643 /* Cast the V2SImode back to V16QImode, and store in target. */
23644 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
23652 /* Replicate the value once into the next wider mode and recurse. */
23653 val = convert_modes (wsmode, smode, val, true);
23654 x = expand_simple_binop (wsmode, ASHIFT, val,
23655 GEN_INT (GET_MODE_BITSIZE (smode)),
23656 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23657 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
23659 x = gen_reg_rtx (wvmode);
23660 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
23661 gcc_unreachable ();
23662 emit_move_insn (target, gen_lowpart (mode, x));
23670 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23671 whose ONE_VAR element is VAR, and other elements are zero. Return true
23675 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
23676 rtx target, rtx var, int one_var)
23678 enum machine_mode vsimode;
23681 bool use_vector_set = false;
23686 use_vector_set = TARGET_64BIT && TARGET_SSE4_1;
23691 use_vector_set = TARGET_SSE4_1;
23694 use_vector_set = TARGET_SSE2;
23697 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
23703 if (use_vector_set)
23705 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
23706 var = force_reg (GET_MODE_INNER (mode), var);
23707 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23723 var = force_reg (GET_MODE_INNER (mode), var);
23724 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
23725 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23730 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
23731 new_target = gen_reg_rtx (mode);
23733 new_target = target;
23734 var = force_reg (GET_MODE_INNER (mode), var);
23735 x = gen_rtx_VEC_DUPLICATE (mode, var);
23736 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
23737 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
23740 /* We need to shuffle the value to the correct position, so
23741 create a new pseudo to store the intermediate result. */
23743 /* With SSE2, we can use the integer shuffle insns. */
23744 if (mode != V4SFmode && TARGET_SSE2)
23746 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
23748 GEN_INT (one_var == 1 ? 0 : 1),
23749 GEN_INT (one_var == 2 ? 0 : 1),
23750 GEN_INT (one_var == 3 ? 0 : 1)));
23751 if (target != new_target)
23752 emit_move_insn (target, new_target);
23756 /* Otherwise convert the intermediate result to V4SFmode and
23757 use the SSE1 shuffle instructions. */
23758 if (mode != V4SFmode)
23760 tmp = gen_reg_rtx (V4SFmode);
23761 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
23766 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
23768 GEN_INT (one_var == 1 ? 0 : 1),
23769 GEN_INT (one_var == 2 ? 0+4 : 1+4),
23770 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
23772 if (mode != V4SFmode)
23773 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
23774 else if (tmp != target)
23775 emit_move_insn (target, tmp);
23777 else if (target != new_target)
23778 emit_move_insn (target, new_target);
23783 vsimode = V4SImode;
23789 vsimode = V2SImode;
23795 /* Zero extend the variable element to SImode and recurse. */
23796 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
23798 x = gen_reg_rtx (vsimode);
23799 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
23801 gcc_unreachable ();
23803 emit_move_insn (target, gen_lowpart (mode, x));
23811 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23812 consisting of the values in VALS. It is known that all elements
23813 except ONE_VAR are constants. Return true if successful. */
23816 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
23817 rtx target, rtx vals, int one_var)
23819 rtx var = XVECEXP (vals, 0, one_var);
23820 enum machine_mode wmode;
23823 const_vec = copy_rtx (vals);
23824 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
23825 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
23833 /* For the two element vectors, it's just as easy to use
23834 the general case. */
23852 /* There's no way to set one QImode entry easily. Combine
23853 the variable value with its adjacent constant value, and
23854 promote to an HImode set. */
23855 x = XVECEXP (vals, 0, one_var ^ 1);
23858 var = convert_modes (HImode, QImode, var, true);
23859 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
23860 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23861 x = GEN_INT (INTVAL (x) & 0xff);
23865 var = convert_modes (HImode, QImode, var, true);
23866 x = gen_int_mode (INTVAL (x) << 8, HImode);
23868 if (x != const0_rtx)
23869 var = expand_simple_binop (HImode, IOR, var, x, var,
23870 1, OPTAB_LIB_WIDEN);
23872 x = gen_reg_rtx (wmode);
23873 emit_move_insn (x, gen_lowpart (wmode, const_vec));
23874 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
23876 emit_move_insn (target, gen_lowpart (mode, x));
23883 emit_move_insn (target, const_vec);
23884 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23888 /* A subroutine of ix86_expand_vector_init_general. Use vector
23889 concatenate to handle the most general case: all values variable,
23890 and none identical. */
23893 ix86_expand_vector_init_concat (enum machine_mode mode,
23894 rtx target, rtx *ops, int n)
23896 enum machine_mode cmode, hmode = VOIDmode;
23897 rtx first[4], second[2];
23925 gcc_unreachable ();
23928 if (!register_operand (ops[1], cmode))
23929 ops[1] = force_reg (cmode, ops[1]);
23930 if (!register_operand (ops[0], cmode))
23931 ops[0] = force_reg (cmode, ops[0]);
23932 emit_insn (gen_rtx_SET (VOIDmode, target,
23933 gen_rtx_VEC_CONCAT (mode, ops[0],
23947 gcc_unreachable ();
23952 /* FIXME: We process inputs backward to help RA. PR 36222. */
23955 for (; i > 0; i -= 2, j--)
23957 first[j] = gen_reg_rtx (cmode);
23958 v = gen_rtvec (2, ops[i - 1], ops[i]);
23959 ix86_expand_vector_init (false, first[j],
23960 gen_rtx_PARALLEL (cmode, v));
23966 gcc_assert (hmode != VOIDmode);
23967 for (i = j = 0; i < n; i += 2, j++)
23969 second[j] = gen_reg_rtx (hmode);
23970 ix86_expand_vector_init_concat (hmode, second [j],
23974 ix86_expand_vector_init_concat (mode, target, second, n);
23977 ix86_expand_vector_init_concat (mode, target, first, n);
23981 gcc_unreachable ();
23985 /* A subroutine of ix86_expand_vector_init_general. Use vector
23986 interleave to handle the most general case: all values variable,
23987 and none identical. */
23990 ix86_expand_vector_init_interleave (enum machine_mode mode,
23991 rtx target, rtx *ops, int n)
23993 enum machine_mode first_imode, second_imode, third_imode;
23996 rtx (*gen_load_even) (rtx, rtx, rtx);
23997 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
23998 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
24003 gen_load_even = gen_vec_setv8hi;
24004 gen_interleave_first_low = gen_vec_interleave_lowv4si;
24005 gen_interleave_second_low = gen_vec_interleave_lowv2di;
24006 first_imode = V4SImode;
24007 second_imode = V2DImode;
24008 third_imode = VOIDmode;
24011 gen_load_even = gen_vec_setv16qi;
24012 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
24013 gen_interleave_second_low = gen_vec_interleave_lowv4si;
24014 first_imode = V8HImode;
24015 second_imode = V4SImode;
24016 third_imode = V2DImode;
24019 gcc_unreachable ();
24022 for (i = 0; i < n; i++)
24024 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
24025 op0 = gen_reg_rtx (SImode);
24026 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
24028 /* Insert the SImode value as low element of V4SImode vector. */
24029 op1 = gen_reg_rtx (V4SImode);
24030 op0 = gen_rtx_VEC_MERGE (V4SImode,
24031 gen_rtx_VEC_DUPLICATE (V4SImode,
24033 CONST0_RTX (V4SImode),
24035 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
24037 /* Cast the V4SImode vector back to a vector in orignal mode. */
24038 op0 = gen_reg_rtx (mode);
24039 emit_move_insn (op0, gen_lowpart (mode, op1));
24041 /* Load even elements into the second positon. */
24042 emit_insn ((*gen_load_even) (op0, ops [i + i + 1],
24045 /* Cast vector to FIRST_IMODE vector. */
24046 ops[i] = gen_reg_rtx (first_imode);
24047 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
24050 /* Interleave low FIRST_IMODE vectors. */
24051 for (i = j = 0; i < n; i += 2, j++)
24053 op0 = gen_reg_rtx (first_imode);
24054 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
24056 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
24057 ops[j] = gen_reg_rtx (second_imode);
24058 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
24061 /* Interleave low SECOND_IMODE vectors. */
24062 switch (second_imode)
24065 for (i = j = 0; i < n / 2; i += 2, j++)
24067 op0 = gen_reg_rtx (second_imode);
24068 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
24071 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
24073 ops[j] = gen_reg_rtx (third_imode);
24074 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
24076 second_imode = V2DImode;
24077 gen_interleave_second_low = gen_vec_interleave_lowv2di;
24081 op0 = gen_reg_rtx (second_imode);
24082 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
24085 /* Cast the SECOND_IMODE vector back to a vector on original
24087 emit_insn (gen_rtx_SET (VOIDmode, target,
24088 gen_lowpart (mode, op0)));
24092 gcc_unreachable ();
24096 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
24097 all values variable, and none identical. */
24100 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
24101 rtx target, rtx vals)
24110 if (!mmx_ok && !TARGET_SSE)
24118 n = GET_MODE_NUNITS (mode);
24119 for (i = 0; i < n; i++)
24120 ops[i] = XVECEXP (vals, 0, i);
24121 ix86_expand_vector_init_concat (mode, target, ops, n);
24125 if (!TARGET_SSE4_1)
24133 n = GET_MODE_NUNITS (mode);
24134 for (i = 0; i < n; i++)
24135 ops[i] = XVECEXP (vals, 0, i);
24136 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
24144 gcc_unreachable ();
24148 int i, j, n_elts, n_words, n_elt_per_word;
24149 enum machine_mode inner_mode;
24150 rtx words[4], shift;
24152 inner_mode = GET_MODE_INNER (mode);
24153 n_elts = GET_MODE_NUNITS (mode);
24154 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
24155 n_elt_per_word = n_elts / n_words;
24156 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
24158 for (i = 0; i < n_words; ++i)
24160 rtx word = NULL_RTX;
24162 for (j = 0; j < n_elt_per_word; ++j)
24164 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
24165 elt = convert_modes (word_mode, inner_mode, elt, true);
24171 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
24172 word, 1, OPTAB_LIB_WIDEN);
24173 word = expand_simple_binop (word_mode, IOR, word, elt,
24174 word, 1, OPTAB_LIB_WIDEN);
24182 emit_move_insn (target, gen_lowpart (mode, words[0]));
24183 else if (n_words == 2)
24185 rtx tmp = gen_reg_rtx (mode);
24186 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
24187 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
24188 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
24189 emit_move_insn (target, tmp);
24191 else if (n_words == 4)
24193 rtx tmp = gen_reg_rtx (V4SImode);
24194 gcc_assert (word_mode == SImode);
24195 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
24196 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
24197 emit_move_insn (target, gen_lowpart (mode, tmp));
24200 gcc_unreachable ();
24204 /* Initialize vector TARGET via VALS. Suppress the use of MMX
24205 instructions unless MMX_OK is true. */
24208 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
24210 enum machine_mode mode = GET_MODE (target);
24211 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24212 int n_elts = GET_MODE_NUNITS (mode);
24213 int n_var = 0, one_var = -1;
24214 bool all_same = true, all_const_zero = true;
24218 for (i = 0; i < n_elts; ++i)
24220 x = XVECEXP (vals, 0, i);
24221 if (!(CONST_INT_P (x)
24222 || GET_CODE (x) == CONST_DOUBLE
24223 || GET_CODE (x) == CONST_FIXED))
24224 n_var++, one_var = i;
24225 else if (x != CONST0_RTX (inner_mode))
24226 all_const_zero = false;
24227 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
24231 /* Constants are best loaded from the constant pool. */
24234 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
24238 /* If all values are identical, broadcast the value. */
24240 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
24241 XVECEXP (vals, 0, 0)))
24244 /* Values where only one field is non-constant are best loaded from
24245 the pool and overwritten via move later. */
24249 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
24250 XVECEXP (vals, 0, one_var),
24254 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
24258 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
24262 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
24264 enum machine_mode mode = GET_MODE (target);
24265 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24266 bool use_vec_merge = false;
24275 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
24276 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
24278 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
24280 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
24281 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24287 use_vec_merge = TARGET_SSE4_1;
24295 /* For the two element vectors, we implement a VEC_CONCAT with
24296 the extraction of the other element. */
24298 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
24299 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
24302 op0 = val, op1 = tmp;
24304 op0 = tmp, op1 = val;
24306 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
24307 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24312 use_vec_merge = TARGET_SSE4_1;
24319 use_vec_merge = true;
24323 /* tmp = target = A B C D */
24324 tmp = copy_to_reg (target);
24325 /* target = A A B B */
24326 emit_insn (gen_sse_unpcklps (target, target, target));
24327 /* target = X A B B */
24328 ix86_expand_vector_set (false, target, val, 0);
24329 /* target = A X C D */
24330 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24331 GEN_INT (1), GEN_INT (0),
24332 GEN_INT (2+4), GEN_INT (3+4)));
24336 /* tmp = target = A B C D */
24337 tmp = copy_to_reg (target);
24338 /* tmp = X B C D */
24339 ix86_expand_vector_set (false, tmp, val, 0);
24340 /* target = A B X D */
24341 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24342 GEN_INT (0), GEN_INT (1),
24343 GEN_INT (0+4), GEN_INT (3+4)));
24347 /* tmp = target = A B C D */
24348 tmp = copy_to_reg (target);
24349 /* tmp = X B C D */
24350 ix86_expand_vector_set (false, tmp, val, 0);
24351 /* target = A B X D */
24352 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24353 GEN_INT (0), GEN_INT (1),
24354 GEN_INT (2+4), GEN_INT (0+4)));
24358 gcc_unreachable ();
24363 use_vec_merge = TARGET_SSE4_1;
24367 /* Element 0 handled by vec_merge below. */
24370 use_vec_merge = true;
24376 /* With SSE2, use integer shuffles to swap element 0 and ELT,
24377 store into element 0, then shuffle them back. */
24381 order[0] = GEN_INT (elt);
24382 order[1] = const1_rtx;
24383 order[2] = const2_rtx;
24384 order[3] = GEN_INT (3);
24385 order[elt] = const0_rtx;
24387 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
24388 order[1], order[2], order[3]));
24390 ix86_expand_vector_set (false, target, val, 0);
24392 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
24393 order[1], order[2], order[3]));
24397 /* For SSE1, we have to reuse the V4SF code. */
24398 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
24399 gen_lowpart (SFmode, val), elt);
24404 use_vec_merge = TARGET_SSE2;
24407 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24411 use_vec_merge = TARGET_SSE4_1;
24421 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
24422 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
24423 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24427 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24429 emit_move_insn (mem, target);
24431 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24432 emit_move_insn (tmp, val);
24434 emit_move_insn (target, mem);
24439 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
24441 enum machine_mode mode = GET_MODE (vec);
24442 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24443 bool use_vec_extr = false;
24456 use_vec_extr = true;
24460 use_vec_extr = TARGET_SSE4_1;
24472 tmp = gen_reg_rtx (mode);
24473 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
24474 GEN_INT (elt), GEN_INT (elt),
24475 GEN_INT (elt+4), GEN_INT (elt+4)));
24479 tmp = gen_reg_rtx (mode);
24480 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
24484 gcc_unreachable ();
24487 use_vec_extr = true;
24492 use_vec_extr = TARGET_SSE4_1;
24506 tmp = gen_reg_rtx (mode);
24507 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
24508 GEN_INT (elt), GEN_INT (elt),
24509 GEN_INT (elt), GEN_INT (elt)));
24513 tmp = gen_reg_rtx (mode);
24514 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
24518 gcc_unreachable ();
24521 use_vec_extr = true;
24526 /* For SSE1, we have to reuse the V4SF code. */
24527 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
24528 gen_lowpart (V4SFmode, vec), elt);
24534 use_vec_extr = TARGET_SSE2;
24537 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24541 use_vec_extr = TARGET_SSE4_1;
24545 /* ??? Could extract the appropriate HImode element and shift. */
24552 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
24553 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
24555 /* Let the rtl optimizers know about the zero extension performed. */
24556 if (inner_mode == QImode || inner_mode == HImode)
24558 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
24559 target = gen_lowpart (SImode, target);
24562 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24566 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24568 emit_move_insn (mem, vec);
24570 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24571 emit_move_insn (target, tmp);
24575 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
24576 pattern to reduce; DEST is the destination; IN is the input vector. */
24579 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
24581 rtx tmp1, tmp2, tmp3;
24583 tmp1 = gen_reg_rtx (V4SFmode);
24584 tmp2 = gen_reg_rtx (V4SFmode);
24585 tmp3 = gen_reg_rtx (V4SFmode);
24587 emit_insn (gen_sse_movhlps (tmp1, in, in));
24588 emit_insn (fn (tmp2, tmp1, in));
24590 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
24591 GEN_INT (1), GEN_INT (1),
24592 GEN_INT (1+4), GEN_INT (1+4)));
24593 emit_insn (fn (dest, tmp2, tmp3));
24596 /* Target hook for scalar_mode_supported_p. */
24598 ix86_scalar_mode_supported_p (enum machine_mode mode)
24600 if (DECIMAL_FLOAT_MODE_P (mode))
24602 else if (mode == TFmode)
24603 return TARGET_64BIT;
24605 return default_scalar_mode_supported_p (mode);
24608 /* Implements target hook vector_mode_supported_p. */
24610 ix86_vector_mode_supported_p (enum machine_mode mode)
24612 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
24614 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
24616 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
24618 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
24623 /* Target hook for c_mode_for_suffix. */
24624 static enum machine_mode
24625 ix86_c_mode_for_suffix (char suffix)
24627 if (TARGET_64BIT && suffix == 'q')
24629 if (TARGET_MMX && suffix == 'w')
24635 /* Worker function for TARGET_MD_ASM_CLOBBERS.
24637 We do this in the new i386 backend to maintain source compatibility
24638 with the old cc0-based compiler. */
24641 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
24642 tree inputs ATTRIBUTE_UNUSED,
24645 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
24647 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
24652 /* Implements target vector targetm.asm.encode_section_info. This
24653 is not used by netware. */
24655 static void ATTRIBUTE_UNUSED
24656 ix86_encode_section_info (tree decl, rtx rtl, int first)
24658 default_encode_section_info (decl, rtl, first);
24660 if (TREE_CODE (decl) == VAR_DECL
24661 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
24662 && ix86_in_large_data_p (decl))
24663 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
24666 /* Worker function for REVERSE_CONDITION. */
24669 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
24671 return (mode != CCFPmode && mode != CCFPUmode
24672 ? reverse_condition (code)
24673 : reverse_condition_maybe_unordered (code));
24676 /* Output code to perform an x87 FP register move, from OPERANDS[1]
24680 output_387_reg_move (rtx insn, rtx *operands)
24682 if (REG_P (operands[0]))
24684 if (REG_P (operands[1])
24685 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24687 if (REGNO (operands[0]) == FIRST_STACK_REG)
24688 return output_387_ffreep (operands, 0);
24689 return "fstp\t%y0";
24691 if (STACK_TOP_P (operands[0]))
24692 return "fld%z1\t%y1";
24695 else if (MEM_P (operands[0]))
24697 gcc_assert (REG_P (operands[1]));
24698 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24699 return "fstp%z0\t%y0";
24702 /* There is no non-popping store to memory for XFmode.
24703 So if we need one, follow the store with a load. */
24704 if (GET_MODE (operands[0]) == XFmode)
24705 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
24707 return "fst%z0\t%y0";
24714 /* Output code to perform a conditional jump to LABEL, if C2 flag in
24715 FP status register is set. */
24718 ix86_emit_fp_unordered_jump (rtx label)
24720 rtx reg = gen_reg_rtx (HImode);
24723 emit_insn (gen_x86_fnstsw_1 (reg));
24725 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
24727 emit_insn (gen_x86_sahf_1 (reg));
24729 temp = gen_rtx_REG (CCmode, FLAGS_REG);
24730 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
24734 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
24736 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
24737 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
24740 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
24741 gen_rtx_LABEL_REF (VOIDmode, label),
24743 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
24745 emit_jump_insn (temp);
24746 predict_jump (REG_BR_PROB_BASE * 10 / 100);
24749 /* Output code to perform a log1p XFmode calculation. */
24751 void ix86_emit_i387_log1p (rtx op0, rtx op1)
24753 rtx label1 = gen_label_rtx ();
24754 rtx label2 = gen_label_rtx ();
24756 rtx tmp = gen_reg_rtx (XFmode);
24757 rtx tmp2 = gen_reg_rtx (XFmode);
24759 emit_insn (gen_absxf2 (tmp, op1));
24760 emit_insn (gen_cmpxf (tmp,
24761 CONST_DOUBLE_FROM_REAL_VALUE (
24762 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
24764 emit_jump_insn (gen_bge (label1));
24766 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24767 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
24768 emit_jump (label2);
24770 emit_label (label1);
24771 emit_move_insn (tmp, CONST1_RTX (XFmode));
24772 emit_insn (gen_addxf3 (tmp, op1, tmp));
24773 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24774 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
24776 emit_label (label2);
24779 /* Output code to perform a Newton-Rhapson approximation of a single precision
24780 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
24782 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
24784 rtx x0, x1, e0, e1, two;
24786 x0 = gen_reg_rtx (mode);
24787 e0 = gen_reg_rtx (mode);
24788 e1 = gen_reg_rtx (mode);
24789 x1 = gen_reg_rtx (mode);
24791 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
24793 if (VECTOR_MODE_P (mode))
24794 two = ix86_build_const_vector (SFmode, true, two);
24796 two = force_reg (mode, two);
24798 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
24800 /* x0 = rcp(b) estimate */
24801 emit_insn (gen_rtx_SET (VOIDmode, x0,
24802 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
24805 emit_insn (gen_rtx_SET (VOIDmode, e0,
24806 gen_rtx_MULT (mode, x0, b)));
24808 emit_insn (gen_rtx_SET (VOIDmode, e1,
24809 gen_rtx_MINUS (mode, two, e0)));
24811 emit_insn (gen_rtx_SET (VOIDmode, x1,
24812 gen_rtx_MULT (mode, x0, e1)));
24814 emit_insn (gen_rtx_SET (VOIDmode, res,
24815 gen_rtx_MULT (mode, a, x1)));
24818 /* Output code to perform a Newton-Rhapson approximation of a
24819 single precision floating point [reciprocal] square root. */
24821 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
24824 rtx x0, e0, e1, e2, e3, mthree, mhalf;
24827 x0 = gen_reg_rtx (mode);
24828 e0 = gen_reg_rtx (mode);
24829 e1 = gen_reg_rtx (mode);
24830 e2 = gen_reg_rtx (mode);
24831 e3 = gen_reg_rtx (mode);
24833 real_from_integer (&r, VOIDmode, -3, -1, 0);
24834 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24836 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
24837 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24839 if (VECTOR_MODE_P (mode))
24841 mthree = ix86_build_const_vector (SFmode, true, mthree);
24842 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
24845 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
24846 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
24848 /* x0 = rsqrt(a) estimate */
24849 emit_insn (gen_rtx_SET (VOIDmode, x0,
24850 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
24853 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
24858 zero = gen_reg_rtx (mode);
24859 mask = gen_reg_rtx (mode);
24861 zero = force_reg (mode, CONST0_RTX(mode));
24862 emit_insn (gen_rtx_SET (VOIDmode, mask,
24863 gen_rtx_NE (mode, zero, a)));
24865 emit_insn (gen_rtx_SET (VOIDmode, x0,
24866 gen_rtx_AND (mode, x0, mask)));
24870 emit_insn (gen_rtx_SET (VOIDmode, e0,
24871 gen_rtx_MULT (mode, x0, a)));
24873 emit_insn (gen_rtx_SET (VOIDmode, e1,
24874 gen_rtx_MULT (mode, e0, x0)));
24877 mthree = force_reg (mode, mthree);
24878 emit_insn (gen_rtx_SET (VOIDmode, e2,
24879 gen_rtx_PLUS (mode, e1, mthree)));
24881 mhalf = force_reg (mode, mhalf);
24883 /* e3 = -.5 * x0 */
24884 emit_insn (gen_rtx_SET (VOIDmode, e3,
24885 gen_rtx_MULT (mode, x0, mhalf)));
24887 /* e3 = -.5 * e0 */
24888 emit_insn (gen_rtx_SET (VOIDmode, e3,
24889 gen_rtx_MULT (mode, e0, mhalf)));
24890 /* ret = e2 * e3 */
24891 emit_insn (gen_rtx_SET (VOIDmode, res,
24892 gen_rtx_MULT (mode, e2, e3)));
24895 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
24897 static void ATTRIBUTE_UNUSED
24898 i386_solaris_elf_named_section (const char *name, unsigned int flags,
24901 /* With Binutils 2.15, the "@unwind" marker must be specified on
24902 every occurrence of the ".eh_frame" section, not just the first
24905 && strcmp (name, ".eh_frame") == 0)
24907 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
24908 flags & SECTION_WRITE ? "aw" : "a");
24911 default_elf_asm_named_section (name, flags, decl);
24914 /* Return the mangling of TYPE if it is an extended fundamental type. */
24916 static const char *
24917 ix86_mangle_type (const_tree type)
24919 type = TYPE_MAIN_VARIANT (type);
24921 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24922 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24925 switch (TYPE_MODE (type))
24928 /* __float128 is "g". */
24931 /* "long double" or __float80 is "e". */
24938 /* For 32-bit code we can save PIC register setup by using
24939 __stack_chk_fail_local hidden function instead of calling
24940 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
24941 register, so it is better to call __stack_chk_fail directly. */
24944 ix86_stack_protect_fail (void)
24946 return TARGET_64BIT
24947 ? default_external_stack_protect_fail ()
24948 : default_hidden_stack_protect_fail ();
24951 /* Select a format to encode pointers in exception handling data. CODE
24952 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
24953 true if the symbol may be affected by dynamic relocations.
24955 ??? All x86 object file formats are capable of representing this.
24956 After all, the relocation needed is the same as for the call insn.
24957 Whether or not a particular assembler allows us to enter such, I
24958 guess we'll have to see. */
24960 asm_preferred_eh_data_format (int code, int global)
24964 int type = DW_EH_PE_sdata8;
24966 || ix86_cmodel == CM_SMALL_PIC
24967 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
24968 type = DW_EH_PE_sdata4;
24969 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
24971 if (ix86_cmodel == CM_SMALL
24972 || (ix86_cmodel == CM_MEDIUM && code))
24973 return DW_EH_PE_udata4;
24974 return DW_EH_PE_absptr;
24977 /* Expand copysign from SIGN to the positive value ABS_VALUE
24978 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
24981 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
24983 enum machine_mode mode = GET_MODE (sign);
24984 rtx sgn = gen_reg_rtx (mode);
24985 if (mask == NULL_RTX)
24987 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
24988 if (!VECTOR_MODE_P (mode))
24990 /* We need to generate a scalar mode mask in this case. */
24991 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24992 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24993 mask = gen_reg_rtx (mode);
24994 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24998 mask = gen_rtx_NOT (mode, mask);
24999 emit_insn (gen_rtx_SET (VOIDmode, sgn,
25000 gen_rtx_AND (mode, mask, sign)));
25001 emit_insn (gen_rtx_SET (VOIDmode, result,
25002 gen_rtx_IOR (mode, abs_value, sgn)));
25005 /* Expand fabs (OP0) and return a new rtx that holds the result. The
25006 mask for masking out the sign-bit is stored in *SMASK, if that is
25009 ix86_expand_sse_fabs (rtx op0, rtx *smask)
25011 enum machine_mode mode = GET_MODE (op0);
25014 xa = gen_reg_rtx (mode);
25015 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
25016 if (!VECTOR_MODE_P (mode))
25018 /* We need to generate a scalar mode mask in this case. */
25019 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
25020 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
25021 mask = gen_reg_rtx (mode);
25022 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
25024 emit_insn (gen_rtx_SET (VOIDmode, xa,
25025 gen_rtx_AND (mode, op0, mask)));
25033 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
25034 swapping the operands if SWAP_OPERANDS is true. The expanded
25035 code is a forward jump to a newly created label in case the
25036 comparison is true. The generated label rtx is returned. */
25038 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
25039 bool swap_operands)
25050 label = gen_label_rtx ();
25051 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
25052 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25053 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
25054 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
25055 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
25056 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
25057 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
25058 JUMP_LABEL (tmp) = label;
25063 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
25064 using comparison code CODE. Operands are swapped for the comparison if
25065 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
25067 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
25068 bool swap_operands)
25070 enum machine_mode mode = GET_MODE (op0);
25071 rtx mask = gen_reg_rtx (mode);
25080 if (mode == DFmode)
25081 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
25082 gen_rtx_fmt_ee (code, mode, op0, op1)));
25084 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
25085 gen_rtx_fmt_ee (code, mode, op0, op1)));
25090 /* Generate and return a rtx of mode MODE for 2**n where n is the number
25091 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
25093 ix86_gen_TWO52 (enum machine_mode mode)
25095 REAL_VALUE_TYPE TWO52r;
25098 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
25099 TWO52 = const_double_from_real_value (TWO52r, mode);
25100 TWO52 = force_reg (mode, TWO52);
25105 /* Expand SSE sequence for computing lround from OP1 storing
25108 ix86_expand_lround (rtx op0, rtx op1)
25110 /* C code for the stuff we're doing below:
25111 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
25114 enum machine_mode mode = GET_MODE (op1);
25115 const struct real_format *fmt;
25116 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
25119 /* load nextafter (0.5, 0.0) */
25120 fmt = REAL_MODE_FORMAT (mode);
25121 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
25122 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
25124 /* adj = copysign (0.5, op1) */
25125 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
25126 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
25128 /* adj = op1 + adj */
25129 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
25131 /* op0 = (imode)adj */
25132 expand_fix (op0, adj, 0);
25135 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
25138 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
25140 /* C code for the stuff we're doing below (for do_floor):
25142 xi -= (double)xi > op1 ? 1 : 0;
25145 enum machine_mode fmode = GET_MODE (op1);
25146 enum machine_mode imode = GET_MODE (op0);
25147 rtx ireg, freg, label, tmp;
25149 /* reg = (long)op1 */
25150 ireg = gen_reg_rtx (imode);
25151 expand_fix (ireg, op1, 0);
25153 /* freg = (double)reg */
25154 freg = gen_reg_rtx (fmode);
25155 expand_float (freg, ireg, 0);
25157 /* ireg = (freg > op1) ? ireg - 1 : ireg */
25158 label = ix86_expand_sse_compare_and_jump (UNLE,
25159 freg, op1, !do_floor);
25160 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
25161 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
25162 emit_move_insn (ireg, tmp);
25164 emit_label (label);
25165 LABEL_NUSES (label) = 1;
25167 emit_move_insn (op0, ireg);
25170 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
25171 result in OPERAND0. */
25173 ix86_expand_rint (rtx operand0, rtx operand1)
25175 /* C code for the stuff we're doing below:
25176 xa = fabs (operand1);
25177 if (!isless (xa, 2**52))
25179 xa = xa + 2**52 - 2**52;
25180 return copysign (xa, operand1);
25182 enum machine_mode mode = GET_MODE (operand0);
25183 rtx res, xa, label, TWO52, mask;
25185 res = gen_reg_rtx (mode);
25186 emit_move_insn (res, operand1);
25188 /* xa = abs (operand1) */
25189 xa = ix86_expand_sse_fabs (res, &mask);
25191 /* if (!isless (xa, TWO52)) goto label; */
25192 TWO52 = ix86_gen_TWO52 (mode);
25193 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25195 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25196 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
25198 ix86_sse_copysign_to_positive (res, xa, res, mask);
25200 emit_label (label);
25201 LABEL_NUSES (label) = 1;
25203 emit_move_insn (operand0, res);
25206 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
25209 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
25211 /* C code for the stuff we expand below.
25212 double xa = fabs (x), x2;
25213 if (!isless (xa, TWO52))
25215 xa = xa + TWO52 - TWO52;
25216 x2 = copysign (xa, x);
25225 enum machine_mode mode = GET_MODE (operand0);
25226 rtx xa, TWO52, tmp, label, one, res, mask;
25228 TWO52 = ix86_gen_TWO52 (mode);
25230 /* Temporary for holding the result, initialized to the input
25231 operand to ease control flow. */
25232 res = gen_reg_rtx (mode);
25233 emit_move_insn (res, operand1);
25235 /* xa = abs (operand1) */
25236 xa = ix86_expand_sse_fabs (res, &mask);
25238 /* if (!isless (xa, TWO52)) goto label; */
25239 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25241 /* xa = xa + TWO52 - TWO52; */
25242 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25243 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
25245 /* xa = copysign (xa, operand1) */
25246 ix86_sse_copysign_to_positive (xa, xa, res, mask);
25248 /* generate 1.0 or -1.0 */
25249 one = force_reg (mode,
25250 const_double_from_real_value (do_floor
25251 ? dconst1 : dconstm1, mode));
25253 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
25254 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
25255 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25256 gen_rtx_AND (mode, one, tmp)));
25257 /* We always need to subtract here to preserve signed zero. */
25258 tmp = expand_simple_binop (mode, MINUS,
25259 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25260 emit_move_insn (res, tmp);
25262 emit_label (label);
25263 LABEL_NUSES (label) = 1;
25265 emit_move_insn (operand0, res);
25268 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
25271 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
25273 /* C code for the stuff we expand below.
25274 double xa = fabs (x), x2;
25275 if (!isless (xa, TWO52))
25277 x2 = (double)(long)x;
25284 if (HONOR_SIGNED_ZEROS (mode))
25285 return copysign (x2, x);
25288 enum machine_mode mode = GET_MODE (operand0);
25289 rtx xa, xi, TWO52, tmp, label, one, res, mask;
25291 TWO52 = ix86_gen_TWO52 (mode);
25293 /* Temporary for holding the result, initialized to the input
25294 operand to ease control flow. */
25295 res = gen_reg_rtx (mode);
25296 emit_move_insn (res, operand1);
25298 /* xa = abs (operand1) */
25299 xa = ix86_expand_sse_fabs (res, &mask);
25301 /* if (!isless (xa, TWO52)) goto label; */
25302 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25304 /* xa = (double)(long)x */
25305 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25306 expand_fix (xi, res, 0);
25307 expand_float (xa, xi, 0);
25310 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
25312 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
25313 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
25314 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25315 gen_rtx_AND (mode, one, tmp)));
25316 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
25317 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25318 emit_move_insn (res, tmp);
25320 if (HONOR_SIGNED_ZEROS (mode))
25321 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
25323 emit_label (label);
25324 LABEL_NUSES (label) = 1;
25326 emit_move_insn (operand0, res);
25329 /* Expand SSE sequence for computing round from OPERAND1 storing
25330 into OPERAND0. Sequence that works without relying on DImode truncation
25331 via cvttsd2siq that is only available on 64bit targets. */
25333 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
25335 /* C code for the stuff we expand below.
25336 double xa = fabs (x), xa2, x2;
25337 if (!isless (xa, TWO52))
25339 Using the absolute value and copying back sign makes
25340 -0.0 -> -0.0 correct.
25341 xa2 = xa + TWO52 - TWO52;
25346 else if (dxa > 0.5)
25348 x2 = copysign (xa2, x);
25351 enum machine_mode mode = GET_MODE (operand0);
25352 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
25354 TWO52 = ix86_gen_TWO52 (mode);
25356 /* Temporary for holding the result, initialized to the input
25357 operand to ease control flow. */
25358 res = gen_reg_rtx (mode);
25359 emit_move_insn (res, operand1);
25361 /* xa = abs (operand1) */
25362 xa = ix86_expand_sse_fabs (res, &mask);
25364 /* if (!isless (xa, TWO52)) goto label; */
25365 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25367 /* xa2 = xa + TWO52 - TWO52; */
25368 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25369 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
25371 /* dxa = xa2 - xa; */
25372 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
25374 /* generate 0.5, 1.0 and -0.5 */
25375 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
25376 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
25377 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
25381 tmp = gen_reg_rtx (mode);
25382 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
25383 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
25384 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25385 gen_rtx_AND (mode, one, tmp)));
25386 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25387 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
25388 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
25389 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25390 gen_rtx_AND (mode, one, tmp)));
25391 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25393 /* res = copysign (xa2, operand1) */
25394 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
25396 emit_label (label);
25397 LABEL_NUSES (label) = 1;
25399 emit_move_insn (operand0, res);
25402 /* Expand SSE sequence for computing trunc from OPERAND1 storing
25405 ix86_expand_trunc (rtx operand0, rtx operand1)
25407 /* C code for SSE variant we expand below.
25408 double xa = fabs (x), x2;
25409 if (!isless (xa, TWO52))
25411 x2 = (double)(long)x;
25412 if (HONOR_SIGNED_ZEROS (mode))
25413 return copysign (x2, x);
25416 enum machine_mode mode = GET_MODE (operand0);
25417 rtx xa, xi, TWO52, label, res, mask;
25419 TWO52 = ix86_gen_TWO52 (mode);
25421 /* Temporary for holding the result, initialized to the input
25422 operand to ease control flow. */
25423 res = gen_reg_rtx (mode);
25424 emit_move_insn (res, operand1);
25426 /* xa = abs (operand1) */
25427 xa = ix86_expand_sse_fabs (res, &mask);
25429 /* if (!isless (xa, TWO52)) goto label; */
25430 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25432 /* x = (double)(long)x */
25433 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25434 expand_fix (xi, res, 0);
25435 expand_float (res, xi, 0);
25437 if (HONOR_SIGNED_ZEROS (mode))
25438 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
25440 emit_label (label);
25441 LABEL_NUSES (label) = 1;
25443 emit_move_insn (operand0, res);
25446 /* Expand SSE sequence for computing trunc from OPERAND1 storing
25449 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
25451 enum machine_mode mode = GET_MODE (operand0);
25452 rtx xa, mask, TWO52, label, one, res, smask, tmp;
25454 /* C code for SSE variant we expand below.
25455 double xa = fabs (x), x2;
25456 if (!isless (xa, TWO52))
25458 xa2 = xa + TWO52 - TWO52;
25462 x2 = copysign (xa2, x);
25466 TWO52 = ix86_gen_TWO52 (mode);
25468 /* Temporary for holding the result, initialized to the input
25469 operand to ease control flow. */
25470 res = gen_reg_rtx (mode);
25471 emit_move_insn (res, operand1);
25473 /* xa = abs (operand1) */
25474 xa = ix86_expand_sse_fabs (res, &smask);
25476 /* if (!isless (xa, TWO52)) goto label; */
25477 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25479 /* res = xa + TWO52 - TWO52; */
25480 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25481 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
25482 emit_move_insn (res, tmp);
25485 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
25487 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
25488 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
25489 emit_insn (gen_rtx_SET (VOIDmode, mask,
25490 gen_rtx_AND (mode, mask, one)));
25491 tmp = expand_simple_binop (mode, MINUS,
25492 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
25493 emit_move_insn (res, tmp);
25495 /* res = copysign (res, operand1) */
25496 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
25498 emit_label (label);
25499 LABEL_NUSES (label) = 1;
25501 emit_move_insn (operand0, res);
25504 /* Expand SSE sequence for computing round from OPERAND1 storing
25507 ix86_expand_round (rtx operand0, rtx operand1)
25509 /* C code for the stuff we're doing below:
25510 double xa = fabs (x);
25511 if (!isless (xa, TWO52))
25513 xa = (double)(long)(xa + nextafter (0.5, 0.0));
25514 return copysign (xa, x);
25516 enum machine_mode mode = GET_MODE (operand0);
25517 rtx res, TWO52, xa, label, xi, half, mask;
25518 const struct real_format *fmt;
25519 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
25521 /* Temporary for holding the result, initialized to the input
25522 operand to ease control flow. */
25523 res = gen_reg_rtx (mode);
25524 emit_move_insn (res, operand1);
25526 TWO52 = ix86_gen_TWO52 (mode);
25527 xa = ix86_expand_sse_fabs (res, &mask);
25528 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25530 /* load nextafter (0.5, 0.0) */
25531 fmt = REAL_MODE_FORMAT (mode);
25532 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
25533 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
25535 /* xa = xa + 0.5 */
25536 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
25537 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
25539 /* xa = (double)(int64_t)xa */
25540 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25541 expand_fix (xi, xa, 0);
25542 expand_float (xa, xi, 0);
25544 /* res = copysign (xa, operand1) */
25545 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
25547 emit_label (label);
25548 LABEL_NUSES (label) = 1;
25550 emit_move_insn (operand0, res);
25554 /* Validate whether a SSE5 instruction is valid or not.
25555 OPERANDS is the array of operands.
25556 NUM is the number of operands.
25557 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
25558 NUM_MEMORY is the maximum number of memory operands to accept. */
25561 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
25562 bool uses_oc0, int num_memory)
25568 /* Count the number of memory arguments */
25571 for (i = 0; i < num; i++)
25573 enum machine_mode mode = GET_MODE (operands[i]);
25574 if (register_operand (operands[i], mode))
25577 else if (memory_operand (operands[i], mode))
25579 mem_mask |= (1 << i);
25585 rtx pattern = PATTERN (insn);
25587 /* allow 0 for pcmov */
25588 if (GET_CODE (pattern) != SET
25589 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
25591 || operands[i] != CONST0_RTX (mode))
25596 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
25597 a memory operation. */
25598 if (num_memory < 0)
25600 num_memory = -num_memory;
25601 if ((mem_mask & (1 << (num-1))) != 0)
25603 mem_mask &= ~(1 << (num-1));
25608 /* If there were no memory operations, allow the insn */
25612 /* Do not allow the destination register to be a memory operand. */
25613 else if (mem_mask & (1 << 0))
25616 /* If there are too many memory operations, disallow the instruction. While
25617 the hardware only allows 1 memory reference, before register allocation
25618 for some insns, we allow two memory operations sometimes in order to allow
25619 code like the following to be optimized:
25621 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
25623 or similar cases that are vectorized into using the fmaddss
25625 else if (mem_count > num_memory)
25628 /* Don't allow more than one memory operation if not optimizing. */
25629 else if (mem_count > 1 && !optimize)
25632 else if (num == 4 && mem_count == 1)
25634 /* formats (destination is the first argument), example fmaddss:
25635 xmm1, xmm1, xmm2, xmm3/mem
25636 xmm1, xmm1, xmm2/mem, xmm3
25637 xmm1, xmm2, xmm3/mem, xmm1
25638 xmm1, xmm2/mem, xmm3, xmm1 */
25640 return ((mem_mask == (1 << 1))
25641 || (mem_mask == (1 << 2))
25642 || (mem_mask == (1 << 3)));
25644 /* format, example pmacsdd:
25645 xmm1, xmm2, xmm3/mem, xmm1 */
25647 return (mem_mask == (1 << 2));
25650 else if (num == 4 && num_memory == 2)
25652 /* If there are two memory operations, we can load one of the memory ops
25653 into the destination register. This is for optimizing the
25654 multiply/add ops, which the combiner has optimized both the multiply
25655 and the add insns to have a memory operation. We have to be careful
25656 that the destination doesn't overlap with the inputs. */
25657 rtx op0 = operands[0];
25659 if (reg_mentioned_p (op0, operands[1])
25660 || reg_mentioned_p (op0, operands[2])
25661 || reg_mentioned_p (op0, operands[3]))
25664 /* formats (destination is the first argument), example fmaddss:
25665 xmm1, xmm1, xmm2, xmm3/mem
25666 xmm1, xmm1, xmm2/mem, xmm3
25667 xmm1, xmm2, xmm3/mem, xmm1
25668 xmm1, xmm2/mem, xmm3, xmm1
25670 For the oc0 case, we will load either operands[1] or operands[3] into
25671 operands[0], so any combination of 2 memory operands is ok. */
25675 /* format, example pmacsdd:
25676 xmm1, xmm2, xmm3/mem, xmm1
25678 For the integer multiply/add instructions be more restrictive and
25679 require operands[2] and operands[3] to be the memory operands. */
25681 return (mem_mask == ((1 << 2) | (1 << 3)));
25684 else if (num == 3 && num_memory == 1)
25686 /* formats, example protb:
25687 xmm1, xmm2, xmm3/mem
25688 xmm1, xmm2/mem, xmm3 */
25690 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
25692 /* format, example comeq:
25693 xmm1, xmm2, xmm3/mem */
25695 return (mem_mask == (1 << 2));
25699 gcc_unreachable ();
25705 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
25706 hardware will allow by using the destination register to load one of the
25707 memory operations. Presently this is used by the multiply/add routines to
25708 allow 2 memory references. */
25711 ix86_expand_sse5_multiple_memory (rtx operands[],
25713 enum machine_mode mode)
25715 rtx op0 = operands[0];
25717 || memory_operand (op0, mode)
25718 || reg_mentioned_p (op0, operands[1])
25719 || reg_mentioned_p (op0, operands[2])
25720 || reg_mentioned_p (op0, operands[3]))
25721 gcc_unreachable ();
25723 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
25724 the destination register. */
25725 if (memory_operand (operands[1], mode))
25727 emit_move_insn (op0, operands[1]);
25730 else if (memory_operand (operands[3], mode))
25732 emit_move_insn (op0, operands[3]);
25736 gcc_unreachable ();
25742 /* Table of valid machine attributes. */
25743 static const struct attribute_spec ix86_attribute_table[] =
25745 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
25746 /* Stdcall attribute says callee is responsible for popping arguments
25747 if they are not variable. */
25748 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25749 /* Fastcall attribute says callee is responsible for popping arguments
25750 if they are not variable. */
25751 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25752 /* Cdecl attribute says the callee is a normal C declaration */
25753 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25754 /* Regparm attribute specifies how many integer arguments are to be
25755 passed in registers. */
25756 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
25757 /* Sseregparm attribute says we are using x86_64 calling conventions
25758 for FP arguments. */
25759 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25760 /* force_align_arg_pointer says this function realigns the stack at entry. */
25761 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
25762 false, true, true, ix86_handle_cconv_attribute },
25763 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25764 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
25765 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
25766 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
25768 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25769 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25770 #ifdef SUBTARGET_ATTRIBUTE_TABLE
25771 SUBTARGET_ATTRIBUTE_TABLE,
25773 { NULL, 0, 0, false, false, false, NULL }
25776 /* Implement targetm.vectorize.builtin_vectorization_cost. */
25778 x86_builtin_vectorization_cost (bool runtime_test)
25780 /* If the branch of the runtime test is taken - i.e. - the vectorized
25781 version is skipped - this incurs a misprediction cost (because the
25782 vectorized version is expected to be the fall-through). So we subtract
25783 the latency of a mispredicted branch from the costs that are incured
25784 when the vectorized version is executed.
25786 TODO: The values in individual target tables have to be tuned or new
25787 fields may be needed. For eg. on K8, the default branch path is the
25788 not-taken path. If the taken path is predicted correctly, the minimum
25789 penalty of going down the taken-path is 1 cycle. If the taken-path is
25790 not predicted correctly, then the minimum penalty is 10 cycles. */
25794 return (-(ix86_cost->cond_taken_branch_cost));
25800 /* Initialize the GCC target structure. */
25801 #undef TARGET_RETURN_IN_MEMORY
25802 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
25804 #undef TARGET_ATTRIBUTE_TABLE
25805 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
25806 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25807 # undef TARGET_MERGE_DECL_ATTRIBUTES
25808 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
25811 #undef TARGET_COMP_TYPE_ATTRIBUTES
25812 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
25814 #undef TARGET_INIT_BUILTINS
25815 #define TARGET_INIT_BUILTINS ix86_init_builtins
25816 #undef TARGET_EXPAND_BUILTIN
25817 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
25819 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
25820 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
25821 ix86_builtin_vectorized_function
25823 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
25824 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
25826 #undef TARGET_BUILTIN_RECIPROCAL
25827 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
25829 #undef TARGET_ASM_FUNCTION_EPILOGUE
25830 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
25832 #undef TARGET_ENCODE_SECTION_INFO
25833 #ifndef SUBTARGET_ENCODE_SECTION_INFO
25834 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
25836 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
25839 #undef TARGET_ASM_OPEN_PAREN
25840 #define TARGET_ASM_OPEN_PAREN ""
25841 #undef TARGET_ASM_CLOSE_PAREN
25842 #define TARGET_ASM_CLOSE_PAREN ""
25844 #undef TARGET_ASM_ALIGNED_HI_OP
25845 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
25846 #undef TARGET_ASM_ALIGNED_SI_OP
25847 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
25849 #undef TARGET_ASM_ALIGNED_DI_OP
25850 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
25853 #undef TARGET_ASM_UNALIGNED_HI_OP
25854 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
25855 #undef TARGET_ASM_UNALIGNED_SI_OP
25856 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
25857 #undef TARGET_ASM_UNALIGNED_DI_OP
25858 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
25860 #undef TARGET_SCHED_ADJUST_COST
25861 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
25862 #undef TARGET_SCHED_ISSUE_RATE
25863 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
25864 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
25865 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
25866 ia32_multipass_dfa_lookahead
25868 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
25869 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
25872 #undef TARGET_HAVE_TLS
25873 #define TARGET_HAVE_TLS true
25875 #undef TARGET_CANNOT_FORCE_CONST_MEM
25876 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
25877 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
25878 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
25880 #undef TARGET_DELEGITIMIZE_ADDRESS
25881 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
25883 #undef TARGET_MS_BITFIELD_LAYOUT_P
25884 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
25887 #undef TARGET_BINDS_LOCAL_P
25888 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
25890 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25891 #undef TARGET_BINDS_LOCAL_P
25892 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
25895 #undef TARGET_ASM_OUTPUT_MI_THUNK
25896 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
25897 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
25898 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
25900 #undef TARGET_ASM_FILE_START
25901 #define TARGET_ASM_FILE_START x86_file_start
25903 #undef TARGET_DEFAULT_TARGET_FLAGS
25904 #define TARGET_DEFAULT_TARGET_FLAGS \
25906 | TARGET_SUBTARGET_DEFAULT \
25907 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
25909 #undef TARGET_HANDLE_OPTION
25910 #define TARGET_HANDLE_OPTION ix86_handle_option
25912 #undef TARGET_RTX_COSTS
25913 #define TARGET_RTX_COSTS ix86_rtx_costs
25914 #undef TARGET_ADDRESS_COST
25915 #define TARGET_ADDRESS_COST ix86_address_cost
25917 #undef TARGET_FIXED_CONDITION_CODE_REGS
25918 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
25919 #undef TARGET_CC_MODES_COMPATIBLE
25920 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
25922 #undef TARGET_MACHINE_DEPENDENT_REORG
25923 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
25925 #undef TARGET_BUILD_BUILTIN_VA_LIST
25926 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
25928 #undef TARGET_EXPAND_BUILTIN_VA_START
25929 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
25931 #undef TARGET_MD_ASM_CLOBBERS
25932 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
25934 #undef TARGET_PROMOTE_PROTOTYPES
25935 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
25936 #undef TARGET_STRUCT_VALUE_RTX
25937 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
25938 #undef TARGET_SETUP_INCOMING_VARARGS
25939 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
25940 #undef TARGET_MUST_PASS_IN_STACK
25941 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
25942 #undef TARGET_PASS_BY_REFERENCE
25943 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
25944 #undef TARGET_INTERNAL_ARG_POINTER
25945 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
25946 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
25947 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
25948 #undef TARGET_STRICT_ARGUMENT_NAMING
25949 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
25951 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
25952 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
25954 #undef TARGET_SCALAR_MODE_SUPPORTED_P
25955 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
25957 #undef TARGET_VECTOR_MODE_SUPPORTED_P
25958 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
25960 #undef TARGET_C_MODE_FOR_SUFFIX
25961 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
25964 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
25965 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
25968 #ifdef SUBTARGET_INSERT_ATTRIBUTES
25969 #undef TARGET_INSERT_ATTRIBUTES
25970 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
25973 #undef TARGET_MANGLE_TYPE
25974 #define TARGET_MANGLE_TYPE ix86_mangle_type
25976 #undef TARGET_STACK_PROTECT_FAIL
25977 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
25979 #undef TARGET_FUNCTION_VALUE
25980 #define TARGET_FUNCTION_VALUE ix86_function_value
25982 #undef TARGET_SECONDARY_RELOAD
25983 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
25985 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
25986 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
25988 struct gcc_target targetm = TARGET_INITIALIZER;
25990 #include "gt-i386.h"
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