1 /* Subroutines for insn-output.c for Intel X86.
2 Copyright (C) 1988, 1992, 1994, 1995 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
38 #ifdef EXTRA_CONSTRAINT
39 /* If EXTRA_CONSTRAINT is defined, then the 'S'
40 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
41 asm statements that need 'S' for class SIREG will break. */
42 error EXTRA_CONSTRAINT conflicts with S constraint letter
43 /* The previous line used to be #error, but some compilers barf
44 even if the conditional was untrue. */
47 #define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx))
49 extern FILE *asm_out_file;
50 extern char *strcat ();
52 char *singlemove_string ();
53 char *output_move_const_single ();
54 char *output_fp_cc0_set ();
56 char *hi_reg_name[] = HI_REGISTER_NAMES;
57 char *qi_reg_name[] = QI_REGISTER_NAMES;
58 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
60 /* Array of the smallest class containing reg number REGNO, indexed by
61 REGNO. Used by REGNO_REG_CLASS in i386.h. */
63 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
66 AREG, DREG, CREG, BREG,
68 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
70 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
71 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
76 /* Test and compare insns in i386.md store the information needed to
77 generate branch and scc insns here. */
79 struct rtx_def *i386_compare_op0 = NULL_RTX;
80 struct rtx_def *i386_compare_op1 = NULL_RTX;
81 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
83 /* Register allocation order */
84 char *i386_reg_alloc_order;
85 static char regs_allocated[FIRST_PSEUDO_REGISTER];
87 /* # of registers to use to pass arguments. */
88 char *i386_regparm_string; /* # registers to use to pass args */
89 int i386_regparm; /* i386_regparm_string as a number */
91 /* Alignment to use for loops and jumps */
92 char *i386_align_loops_string; /* power of two alignment for loops */
93 char *i386_align_jumps_string; /* power of two alignment for non-loop jumps */
94 char *i386_align_funcs_string; /* power of two alignment for functions */
96 int i386_align_loops; /* power of two alignment for loops */
97 int i386_align_jumps; /* power of two alignment for non-loop jumps */
98 int i386_align_funcs; /* power of two alignment for functions */
101 /* Sometimes certain combinations of command options do not make
102 sense on a particular target machine. You can define a macro
103 `OVERRIDE_OPTIONS' to take account of this. This macro, if
104 defined, is executed once just after all the command options have
107 Don't use this macro to turn on various extra optimizations for
108 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
117 #ifdef SUBTARGET_OVERRIDE_OPTIONS
118 SUBTARGET_OVERRIDE_OPTIONS;
121 /* Validate registers in register allocation order */
122 if (i386_reg_alloc_order)
124 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
128 case 'a': regno = 0; break;
129 case 'd': regno = 1; break;
130 case 'c': regno = 2; break;
131 case 'b': regno = 3; break;
132 case 'S': regno = 4; break;
133 case 'D': regno = 5; break;
134 case 'B': regno = 6; break;
136 default: fatal ("Register '%c' is unknown", ch);
139 if (regs_allocated[regno])
140 fatal ("Register '%c' was already specified in the allocation order", ch);
142 regs_allocated[regno] = 1;
146 /* Validate -mregparm= value */
147 if (i386_regparm_string)
149 i386_regparm = atoi (i386_regparm_string);
150 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX)
151 fatal ("-mregparm=%d is not between 0 and %d", i386_regparm, REGPARM_MAX);
154 def_align = (TARGET_386) ? 2 : 4;
156 /* Validate -malign-loops= value, or provide default */
157 if (i386_align_loops_string)
159 i386_align_loops = atoi (i386_align_loops_string);
160 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN)
161 fatal ("-malign-loops=%d is not between 0 and %d",
162 i386_align_loops, MAX_CODE_ALIGN);
165 i386_align_loops = 2;
167 /* Validate -malign-jumps= value, or provide default */
168 if (i386_align_jumps_string)
170 i386_align_jumps = atoi (i386_align_jumps_string);
171 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN)
172 fatal ("-malign-jumps=%d is not between 0 and %d",
173 i386_align_jumps, MAX_CODE_ALIGN);
176 i386_align_jumps = def_align;
178 /* Validate -malign-functions= value, or provide default */
179 if (i386_align_funcs_string)
181 i386_align_funcs = atoi (i386_align_funcs_string);
182 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN)
183 fatal ("-malign-functions=%d is not between 0 and %d",
184 i386_align_funcs, MAX_CODE_ALIGN);
187 i386_align_funcs = def_align;
190 /* A C statement (sans semicolon) to choose the order in which to
191 allocate hard registers for pseudo-registers local to a basic
194 Store the desired register order in the array `reg_alloc_order'.
195 Element 0 should be the register to allocate first; element 1, the
196 next register; and so on.
198 The macro body should not assume anything about the contents of
199 `reg_alloc_order' before execution of the macro.
201 On most machines, it is not necessary to define this macro. */
204 order_regs_for_local_alloc ()
206 int i, ch, order, regno;
208 /* User specified the register allocation order */
209 if (i386_reg_alloc_order)
211 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
215 case 'a': regno = 0; break;
216 case 'd': regno = 1; break;
217 case 'c': regno = 2; break;
218 case 'b': regno = 3; break;
219 case 'S': regno = 4; break;
220 case 'D': regno = 5; break;
221 case 'B': regno = 6; break;
224 reg_alloc_order[order++] = regno;
227 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
229 if (!regs_allocated[i])
230 reg_alloc_order[order++] = i;
234 /* If users did not specify a register allocation order, favor eax
235 normally except if DImode variables are used, in which case
236 favor edx before eax, which seems to cause less spill register
237 not found messages. */
242 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
243 reg_alloc_order[i] = i;
249 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
251 if (GET_CODE (insn) == INSN)
254 rtx pattern = PATTERN (insn);
256 if (GET_CODE (pattern) == SET)
259 else if ((GET_CODE (pattern) == PARALLEL
260 || GET_CODE (pattern) == SEQUENCE)
261 && GET_CODE (XVECEXP (pattern, 0, 0)) == SET)
262 set = XVECEXP (pattern, 0, 0);
264 if (set && GET_MODE (SET_SRC (set)) == DImode)
274 reg_alloc_order[0] = 1; /* edx */
275 reg_alloc_order[1] = 2; /* ecx */
276 reg_alloc_order[2] = 0; /* eax */
283 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
284 attribute for DECL. The attributes in ATTRIBUTES have previously been
288 i386_valid_decl_attribute_p (decl, attributes, identifier, args)
297 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
298 attribute for TYPE. The attributes in ATTRIBUTES have previously been
302 i386_valid_type_attribute_p (type, attributes, identifier, args)
308 if (TREE_CODE (type) != FUNCTION_TYPE
309 && TREE_CODE (type) != FIELD_DECL
310 && TREE_CODE (type) != TYPE_DECL)
313 /* Stdcall attribute says callee is responsible for popping arguments
314 if they are not variable. */
315 if (is_attribute_p ("stdcall", identifier))
316 return (args == NULL_TREE);
318 /* Cdecl attribute says the callee is a normal C declaration */
319 if (is_attribute_p ("cdecl", identifier))
320 return (args == NULL_TREE);
322 /* Regparm attribute specifies how many integer arguments are to be
323 passed in registers */
324 if (is_attribute_p ("regparm", identifier))
328 if (!args || TREE_CODE (args) != TREE_LIST
329 || TREE_CHAIN (args) != NULL_TREE
330 || TREE_VALUE (args) == NULL_TREE)
333 cst = TREE_VALUE (args);
334 if (TREE_CODE (cst) != INTEGER_CST)
337 if (TREE_INT_CST_HIGH (cst) != 0
338 || TREE_INT_CST_LOW (cst) < 0
339 || TREE_INT_CST_LOW (cst) > REGPARM_MAX)
348 /* Return 0 if the attributes for two types are incompatible, 1 if they
349 are compatible, and 2 if they are nearly compatible (which causes a
350 warning to be generated). */
353 i386_comp_type_attributes (type1, type2)
361 /* Value is the number of bytes of arguments automatically
362 popped when returning from a subroutine call.
363 FUNDECL is the declaration node of the function (as a tree),
364 FUNTYPE is the data type of the function (as a tree),
365 or for a library call it is an identifier node for the subroutine name.
366 SIZE is the number of bytes of arguments passed on the stack.
368 On the 80386, the RTD insn may be used to pop them if the number
369 of args is fixed, but if the number is variable then the caller
370 must pop them all. RTD can't be used for library calls now
371 because the library is compiled with the Unix compiler.
372 Use of RTD is a selectable option, since it is incompatible with
373 standard Unix calling sequences. If the option is not selected,
374 the caller must always pop the args.
376 The attribute stdcall is equivalent to RTD on a per module basis. */
379 i386_return_pops_args (fundecl, funtype, size)
384 int rtd = TARGET_RTD;
386 if (TREE_CODE (funtype) == IDENTIFIER_NODE)
389 if (fundecl && TREE_CODE_CLASS (TREE_CODE (fundecl)) == 'd')
391 /* Cdecl functions override -mrtd, and never pop the stack */
392 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
395 /* Stdcall functions will pop the stack if not variable args */
396 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
402 if (TYPE_ARG_TYPES (funtype) == NULL_TREE
403 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype))) == void_type_node))
406 if (aggregate_value_p (TREE_TYPE (funtype)))
407 return GET_MODE_SIZE (Pmode);
414 /* Argument support functions. */
416 /* Initialize a variable CUM of type CUMULATIVE_ARGS
417 for a call to a function whose data type is FNTYPE.
418 For a library call, FNTYPE is 0. */
421 init_cumulative_args (cum, fntype, libname)
422 CUMULATIVE_ARGS *cum; /* argument info to initialize */
423 tree fntype; /* tree ptr for function decl */
424 rtx libname; /* SYMBOL_REF of library name or 0 */
426 static CUMULATIVE_ARGS zero_cum;
427 tree param, next_param;
429 if (TARGET_DEBUG_ARG)
431 fprintf (stderr, "\ninit_cumulative_args (");
434 tree ret_type = TREE_TYPE (fntype);
435 fprintf (stderr, "fntype code = %s, ret code = %s",
436 tree_code_name[ (int)TREE_CODE (fntype) ],
437 tree_code_name[ (int)TREE_CODE (ret_type) ]);
440 fprintf (stderr, "no fntype");
443 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
448 /* Set up the number of registers to use for passing arguments. */
449 cum->nregs = i386_regparm;
452 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
454 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
457 /* Determine if this function has variable arguments. This is
458 indicated by the last argument being 'void_type_mode' if there
459 are no variable arguments. If there are variable arguments, then
460 we won't pass anything in registers */
464 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
468 next_param = TREE_CHAIN (param);
469 if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node)
474 if (TARGET_DEBUG_ARG)
475 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
480 /* Update the data in CUM to advance over an argument
481 of mode MODE and data type TYPE.
482 (TYPE is null for libcalls where that information may not be available.) */
485 function_arg_advance (cum, mode, type, named)
486 CUMULATIVE_ARGS *cum; /* current arg information */
487 enum machine_mode mode; /* current arg mode */
488 tree type; /* type of the argument or 0 if lib support */
489 int named; /* whether or not the argument was named */
491 int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
492 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
494 if (TARGET_DEBUG_ARG)
496 "function_adv( size=%d, words=%2d, nregs=%d, mode=%4s, named=%d )\n\n",
497 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
512 /* Define where to put the arguments to a function.
513 Value is zero to push the argument on the stack,
514 or a hard register in which to store the argument.
516 MODE is the argument's machine mode.
517 TYPE is the data type of the argument (as a tree).
518 This is null for libcalls where that information may
520 CUM is a variable of type CUMULATIVE_ARGS which gives info about
521 the preceding args and about the function being called.
522 NAMED is nonzero if this argument is a named parameter
523 (otherwise it is an extra parameter matching an ellipsis). */
526 function_arg (cum, mode, type, named)
527 CUMULATIVE_ARGS *cum; /* current arg information */
528 enum machine_mode mode; /* current arg mode */
529 tree type; /* type of the argument or 0 if lib support */
530 int named; /* != 0 for normal args, == 0 for ... args */
533 int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
534 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
538 default: /* for now, pass fp/complex values on the stack */
546 if (words <= cum->nregs)
547 ret = gen_rtx (REG, mode, cum->regno);
551 if (TARGET_DEBUG_ARG)
554 "function_arg( size=%d, words=%2d, nregs=%d, mode=%4s, named=%d",
555 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
558 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]);
560 fprintf (stderr, ", stack");
562 fprintf (stderr, " )\n");
568 /* For an arg passed partly in registers and partly in memory,
569 this is the number of registers used.
570 For args passed entirely in registers or entirely in memory, zero. */
573 function_arg_partial_nregs (cum, mode, type, named)
574 CUMULATIVE_ARGS *cum; /* current arg information */
575 enum machine_mode mode; /* current arg mode */
576 tree type; /* type of the argument or 0 if lib support */
577 int named; /* != 0 for normal args, == 0 for ... args */
583 /* Output an insn whose source is a 386 integer register. SRC is the
584 rtx for the register, and TEMPLATE is the op-code template. SRC may
585 be either SImode or DImode.
587 The template will be output with operands[0] as SRC, and operands[1]
588 as a pointer to the top of the 386 stack. So a call from floatsidf2
589 would look like this:
591 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
593 where %z0 corresponds to the caller's operands[1], and is used to
594 emit the proper size suffix.
596 ??? Extend this to handle HImode - a 387 can load and store HImode
600 output_op_from_reg (src, template)
605 int size = GET_MODE_SIZE (GET_MODE (src));
608 xops[1] = AT_SP (Pmode);
609 xops[2] = GEN_INT (size);
610 xops[3] = stack_pointer_rtx;
612 if (size > UNITS_PER_WORD)
615 if (size > 2 * UNITS_PER_WORD)
617 high = gen_rtx (REG, SImode, REGNO (src) + 2);
618 output_asm_insn (AS1 (push%L0,%0), &high);
620 high = gen_rtx (REG, SImode, REGNO (src) + 1);
621 output_asm_insn (AS1 (push%L0,%0), &high);
623 output_asm_insn (AS1 (push%L0,%0), &src);
625 output_asm_insn (template, xops);
627 output_asm_insn (AS2 (add%L3,%2,%3), xops);
630 /* Output an insn to pop an value from the 387 top-of-stack to 386
631 register DEST. The 387 register stack is popped if DIES is true. If
632 the mode of DEST is an integer mode, a `fist' integer store is done,
633 otherwise a `fst' float store is done. */
636 output_to_reg (dest, dies)
641 int size = GET_MODE_SIZE (GET_MODE (dest));
643 xops[0] = AT_SP (Pmode);
644 xops[1] = stack_pointer_rtx;
645 xops[2] = GEN_INT (size);
648 output_asm_insn (AS2 (sub%L1,%2,%1), xops);
650 if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT)
653 output_asm_insn (AS1 (fistp%z3,%y0), xops);
655 output_asm_insn (AS1 (fist%z3,%y0), xops);
657 else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT)
660 output_asm_insn (AS1 (fstp%z3,%y0), xops);
663 if (GET_MODE (dest) == XFmode)
665 output_asm_insn (AS1 (fstp%z3,%y0), xops);
666 output_asm_insn (AS1 (fld%z3,%y0), xops);
669 output_asm_insn (AS1 (fst%z3,%y0), xops);
675 output_asm_insn (AS1 (pop%L0,%0), &dest);
677 if (size > UNITS_PER_WORD)
679 dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
680 output_asm_insn (AS1 (pop%L0,%0), &dest);
681 if (size > 2 * UNITS_PER_WORD)
683 dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
684 output_asm_insn (AS1 (pop%L0,%0), &dest);
690 singlemove_string (operands)
694 if (GET_CODE (operands[0]) == MEM
695 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
697 if (XEXP (x, 0) != stack_pointer_rtx)
701 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
703 return output_move_const_single (operands);
705 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
706 return AS2 (mov%L0,%1,%0);
707 else if (CONSTANT_P (operands[1]))
708 return AS2 (mov%L0,%1,%0);
711 output_asm_insn ("push%L1 %1", operands);
716 /* Return a REG that occurs in ADDR with coefficient 1.
717 ADDR can be effectively incremented by incrementing REG. */
723 while (GET_CODE (addr) == PLUS)
725 if (GET_CODE (XEXP (addr, 0)) == REG)
726 addr = XEXP (addr, 0);
727 else if (GET_CODE (XEXP (addr, 1)) == REG)
728 addr = XEXP (addr, 1);
729 else if (CONSTANT_P (XEXP (addr, 0)))
730 addr = XEXP (addr, 1);
731 else if (CONSTANT_P (XEXP (addr, 1)))
732 addr = XEXP (addr, 0);
736 if (GET_CODE (addr) == REG)
742 /* Output an insn to add the constant N to the register X. */
753 output_asm_insn (AS1 (dec%L0,%0), xops);
755 output_asm_insn (AS1 (inc%L0,%0), xops);
758 xops[1] = GEN_INT (-n);
759 output_asm_insn (AS2 (sub%L0,%1,%0), xops);
763 xops[1] = GEN_INT (n);
764 output_asm_insn (AS2 (add%L0,%1,%0), xops);
769 /* Output assembler code to perform a doubleword move insn
770 with operands OPERANDS. */
773 output_move_double (operands)
776 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
780 rtx addreg0 = 0, addreg1 = 0;
781 int dest_overlapped_low = 0;
782 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
787 /* First classify both operands. */
789 if (REG_P (operands[0]))
791 else if (offsettable_memref_p (operands[0]))
793 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
795 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
797 else if (GET_CODE (operands[0]) == MEM)
802 if (REG_P (operands[1]))
804 else if (CONSTANT_P (operands[1]))
806 else if (offsettable_memref_p (operands[1]))
808 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
810 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
812 else if (GET_CODE (operands[1]) == MEM)
817 /* Check for the cases that the operand constraints are not
818 supposed to allow to happen. Abort if we get one,
819 because generating code for these cases is painful. */
821 if (optype0 == RNDOP || optype1 == RNDOP)
824 /* If one operand is decrementing and one is incrementing
825 decrement the former register explicitly
826 and change that operand into ordinary indexing. */
828 if (optype0 == PUSHOP && optype1 == POPOP)
830 /* ??? Can this ever happen on i386? */
831 operands[0] = XEXP (XEXP (operands[0], 0), 0);
832 asm_add (-size, operands[0]);
833 if (GET_MODE (operands[1]) == XFmode)
834 operands[0] = gen_rtx (MEM, XFmode, operands[0]);
835 else if (GET_MODE (operands[0]) == DFmode)
836 operands[0] = gen_rtx (MEM, DFmode, operands[0]);
838 operands[0] = gen_rtx (MEM, DImode, operands[0]);
842 if (optype0 == POPOP && optype1 == PUSHOP)
844 /* ??? Can this ever happen on i386? */
845 operands[1] = XEXP (XEXP (operands[1], 0), 0);
846 asm_add (-size, operands[1]);
847 if (GET_MODE (operands[1]) == XFmode)
848 operands[1] = gen_rtx (MEM, XFmode, operands[1]);
849 else if (GET_MODE (operands[1]) == DFmode)
850 operands[1] = gen_rtx (MEM, DFmode, operands[1]);
852 operands[1] = gen_rtx (MEM, DImode, operands[1]);
856 /* If an operand is an unoffsettable memory ref, find a register
857 we can increment temporarily to make it refer to the second word. */
859 if (optype0 == MEMOP)
860 addreg0 = find_addr_reg (XEXP (operands[0], 0));
862 if (optype1 == MEMOP)
863 addreg1 = find_addr_reg (XEXP (operands[1], 0));
865 /* Ok, we can do one word at a time.
866 Normally we do the low-numbered word first,
867 but if either operand is autodecrementing then we
868 do the high-numbered word first.
870 In either case, set up in LATEHALF the operands to use
871 for the high-numbered word and in some cases alter the
872 operands in OPERANDS to be suitable for the low-numbered word. */
876 if (optype0 == REGOP)
878 middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
879 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
881 else if (optype0 == OFFSOP)
883 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
884 latehalf[0] = adj_offsettable_operand (operands[0], 8);
888 middlehalf[0] = operands[0];
889 latehalf[0] = operands[0];
892 if (optype1 == REGOP)
894 middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
895 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
897 else if (optype1 == OFFSOP)
899 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
900 latehalf[1] = adj_offsettable_operand (operands[1], 8);
902 else if (optype1 == CNSTOP)
904 if (GET_CODE (operands[1]) == CONST_DOUBLE)
906 REAL_VALUE_TYPE r; long l[3];
908 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
909 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
910 operands[1] = GEN_INT (l[0]);
911 middlehalf[1] = GEN_INT (l[1]);
912 latehalf[1] = GEN_INT (l[2]);
914 else if (CONSTANT_P (operands[1]))
915 /* No non-CONST_DOUBLE constant should ever appear here. */
920 middlehalf[1] = operands[1];
921 latehalf[1] = operands[1];
924 else /* size is not 12: */
926 if (optype0 == REGOP)
927 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
928 else if (optype0 == OFFSOP)
929 latehalf[0] = adj_offsettable_operand (operands[0], 4);
931 latehalf[0] = operands[0];
933 if (optype1 == REGOP)
934 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
935 else if (optype1 == OFFSOP)
936 latehalf[1] = adj_offsettable_operand (operands[1], 4);
937 else if (optype1 == CNSTOP)
938 split_double (operands[1], &operands[1], &latehalf[1]);
940 latehalf[1] = operands[1];
943 /* If insn is effectively movd N (sp),-(sp) then we will do the
944 high word first. We should use the adjusted operand 1
945 (which is N+4 (sp) or N+8 (sp))
946 for the low word and middle word as well,
947 to compensate for the first decrement of sp. */
948 if (optype0 == PUSHOP
949 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
950 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
951 middlehalf[1] = operands[1] = latehalf[1];
953 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
954 if the upper part of reg N does not appear in the MEM, arrange to
955 emit the move late-half first. Otherwise, compute the MEM address
956 into the upper part of N and use that as a pointer to the memory
959 && (optype1 == OFFSOP || optype1 == MEMOP))
961 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
962 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
964 /* If both halves of dest are used in the src memory address,
965 compute the address into latehalf of dest. */
967 xops[0] = latehalf[0];
968 xops[1] = XEXP (operands[1], 0);
969 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
970 if( GET_MODE (operands[1]) == XFmode )
973 operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
974 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
975 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
979 operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
980 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
984 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
986 /* Check for two regs used by both source and dest. */
987 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
988 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
991 /* JRV says this can't happen: */
992 if (addreg0 || addreg1)
995 /* Only the middle reg conflicts; simply put it last. */
996 output_asm_insn (singlemove_string (operands), operands);
997 output_asm_insn (singlemove_string (latehalf), latehalf);
998 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1001 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
1002 /* If the low half of dest is mentioned in the source memory
1003 address, the arrange to emit the move late half first. */
1004 dest_overlapped_low = 1;
1007 /* If one or both operands autodecrementing,
1008 do the two words, high-numbered first. */
1010 /* Likewise, the first move would clobber the source of the second one,
1011 do them in the other order. This happens only for registers;
1012 such overlap can't happen in memory unless the user explicitly
1013 sets it up, and that is an undefined circumstance. */
1016 if (optype0 == PUSHOP || optype1 == PUSHOP
1017 || (optype0 == REGOP && optype1 == REGOP
1018 && REGNO (operands[0]) == REGNO (latehalf[1]))
1019 || dest_overlapped_low)
1021 if (optype0 == PUSHOP || optype1 == PUSHOP
1022 || (optype0 == REGOP && optype1 == REGOP
1023 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1024 || REGNO (operands[0]) == REGNO (latehalf[1])))
1025 || dest_overlapped_low)
1027 /* Make any unoffsettable addresses point at high-numbered word. */
1029 asm_add (size-4, addreg0);
1031 asm_add (size-4, addreg1);
1034 output_asm_insn (singlemove_string (latehalf), latehalf);
1036 /* Undo the adds we just did. */
1038 asm_add (-4, addreg0);
1040 asm_add (-4, addreg1);
1044 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1046 asm_add (-4, addreg0);
1048 asm_add (-4, addreg1);
1051 /* Do low-numbered word. */
1052 return singlemove_string (operands);
1055 /* Normal case: do the two words, low-numbered first. */
1057 output_asm_insn (singlemove_string (operands), operands);
1059 /* Do the middle one of the three words for long double */
1063 asm_add (4, addreg0);
1065 asm_add (4, addreg1);
1067 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1070 /* Make any unoffsettable addresses point at high-numbered word. */
1072 asm_add (4, addreg0);
1074 asm_add (4, addreg1);
1077 output_asm_insn (singlemove_string (latehalf), latehalf);
1079 /* Undo the adds we just did. */
1081 asm_add (4-size, addreg0);
1083 asm_add (4-size, addreg1);
1089 #define MAX_TMPS 2 /* max temporary registers used */
1091 /* Output the appropriate code to move push memory on the stack */
1094 output_move_pushmem (operands, insn, length, tmp_start, n_operands)
1106 } tmp_info[MAX_TMPS];
1108 rtx src = operands[1];
1111 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
1112 int stack_offset = 0;
1116 if (!offsettable_memref_p (src))
1117 fatal_insn ("Source is not offsettable", insn);
1119 if ((length & 3) != 0)
1120 fatal_insn ("Pushing non-word aligned size", insn);
1122 /* Figure out which temporary registers we have available */
1123 for (i = tmp_start; i < n_operands; i++)
1125 if (GET_CODE (operands[i]) == REG)
1127 if (reg_overlap_mentioned_p (operands[i], src))
1130 tmp_info[ max_tmps++ ].xops[1] = operands[i];
1131 if (max_tmps == MAX_TMPS)
1137 for (offset = length - 4; offset >= 0; offset -= 4)
1139 xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1140 output_asm_insn (AS1(push%L0,%0), xops);
1146 for (offset = length - 4; offset >= 0; )
1148 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
1150 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1);
1151 tmp_info[num_tmps].push = AS1(push%L0,%1);
1152 tmp_info[num_tmps].xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1156 for (i = 0; i < num_tmps; i++)
1157 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1159 for (i = 0; i < num_tmps; i++)
1160 output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
1163 stack_offset += 4*num_tmps;
1171 /* Output the appropriate code to move data between two memory locations */
1174 output_move_memory (operands, insn, length, tmp_start, n_operands)
1185 } tmp_info[MAX_TMPS];
1187 rtx dest = operands[0];
1188 rtx src = operands[1];
1189 rtx qi_tmp = NULL_RTX;
1195 if (GET_CODE (dest) == MEM
1196 && GET_CODE (XEXP (dest, 0)) == PRE_INC
1197 && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)
1198 return output_move_pushmem (operands, insn, length, tmp_start, n_operands);
1200 if (!offsettable_memref_p (src))
1201 fatal_insn ("Source is not offsettable", insn);
1203 if (!offsettable_memref_p (dest))
1204 fatal_insn ("Destination is not offsettable", insn);
1206 /* Figure out which temporary registers we have available */
1207 for (i = tmp_start; i < n_operands; i++)
1209 if (GET_CODE (operands[i]) == REG)
1211 if ((length & 1) != 0 && !qi_tmp && QI_REG_P (operands[i]))
1212 qi_tmp = operands[i];
1214 if (reg_overlap_mentioned_p (operands[i], dest))
1215 fatal_insn ("Temporary register overlaps the destination", insn);
1217 if (reg_overlap_mentioned_p (operands[i], src))
1218 fatal_insn ("Temporary register overlaps the source", insn);
1220 tmp_info[ max_tmps++ ].xops[2] = operands[i];
1221 if (max_tmps == MAX_TMPS)
1227 fatal_insn ("No scratch registers were found to do memory->memory moves", insn);
1229 if ((length & 1) != 0)
1232 fatal_insn ("No byte register found when moving odd # of bytes.", insn);
1237 for (num_tmps = 0; num_tmps < max_tmps; num_tmps++)
1241 tmp_info[num_tmps].load = AS2(mov%L0,%1,%2);
1242 tmp_info[num_tmps].store = AS2(mov%L0,%2,%0);
1243 tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset);
1244 tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset);
1248 else if (length >= 2)
1250 tmp_info[num_tmps].load = AS2(mov%W0,%1,%2);
1251 tmp_info[num_tmps].store = AS2(mov%W0,%2,%0);
1252 tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset);
1253 tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset);
1261 for (i = 0; i < num_tmps; i++)
1262 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1264 for (i = 0; i < num_tmps; i++)
1265 output_asm_insn (tmp_info[i].store, tmp_info[i].xops);
1270 xops[0] = adj_offsettable_operand (dest, offset);
1271 xops[1] = adj_offsettable_operand (src, offset);
1273 output_asm_insn (AS2(mov%B0,%1,%2), xops);
1274 output_asm_insn (AS2(mov%B0,%2,%0), xops);
1282 standard_80387_constant_p (x)
1285 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
1290 if (setjmp (handler))
1293 set_float_handler (handler);
1294 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1295 is0 = REAL_VALUES_EQUAL (d, dconst0);
1296 is1 = REAL_VALUES_EQUAL (d, dconst1);
1297 set_float_handler (NULL_PTR);
1305 /* Note that on the 80387, other constants, such as pi,
1306 are much slower to load as standard constants
1307 than to load from doubles in memory! */
1314 output_move_const_single (operands)
1317 if (FP_REG_P (operands[0]))
1319 int conval = standard_80387_constant_p (operands[1]);
1327 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1329 REAL_VALUE_TYPE r; long l;
1331 if (GET_MODE (operands[1]) == XFmode)
1334 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1335 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1336 operands[1] = GEN_INT (l);
1338 return singlemove_string (operands);
1341 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1342 reference and a constant. */
1345 symbolic_operand (op, mode)
1347 enum machine_mode mode;
1349 switch (GET_CODE (op))
1356 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1357 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1358 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1364 /* Test for a valid operand for a call instruction.
1365 Don't allow the arg pointer register or virtual regs
1366 since they may change into reg + const, which the patterns
1367 can't handle yet. */
1370 call_insn_operand (op, mode)
1372 enum machine_mode mode;
1374 if (GET_CODE (op) == MEM
1375 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
1376 /* This makes a difference for PIC. */
1377 && general_operand (XEXP (op, 0), Pmode))
1378 || (GET_CODE (XEXP (op, 0)) == REG
1379 && XEXP (op, 0) != arg_pointer_rtx
1380 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1381 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1386 /* Like call_insn_operand but allow (mem (symbol_ref ...))
1390 expander_call_insn_operand (op, mode)
1392 enum machine_mode mode;
1394 if (GET_CODE (op) == MEM
1395 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
1396 || (GET_CODE (XEXP (op, 0)) == REG
1397 && XEXP (op, 0) != arg_pointer_rtx
1398 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1399 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1404 /* Returns 1 if OP contains a symbol reference */
1407 symbolic_reference_mentioned_p (op)
1413 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1416 fmt = GET_RTX_FORMAT (GET_CODE (op));
1417 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1423 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1424 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1427 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1434 /* This function generates the assembly code for function entry.
1435 FILE is an stdio stream to output the code to.
1436 SIZE is an int: how many units of temporary storage to allocate. */
1439 function_prologue (file, size)
1446 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1447 || current_function_uses_const_pool);
1449 xops[0] = stack_pointer_rtx;
1450 xops[1] = frame_pointer_rtx;
1451 xops[2] = GEN_INT (size);
1452 if (frame_pointer_needed)
1454 output_asm_insn ("push%L1 %1", xops);
1455 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
1459 output_asm_insn (AS2 (sub%L0,%2,%0), xops);
1461 /* Note If use enter it is NOT reversed args.
1462 This one is not reversed from intel!!
1463 I think enter is slower. Also sdb doesn't like it.
1464 But if you want it the code is:
1466 xops[3] = const0_rtx;
1467 output_asm_insn ("enter %2,%3", xops);
1470 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
1471 for (regno = limit - 1; regno >= 0; regno--)
1472 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1473 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1475 xops[0] = gen_rtx (REG, SImode, regno);
1476 output_asm_insn ("push%L0 %0", xops);
1481 xops[0] = pic_offset_table_rtx;
1482 xops[1] = (rtx) gen_label_rtx ();
1484 output_asm_insn (AS1 (call,%P1), xops);
1485 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1]));
1486 output_asm_insn (AS1 (pop%L0,%0), xops);
1487 output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
1491 /* Return 1 if it is appropriate to emit `ret' instructions in the
1492 body of a function. Do this only if the epilogue is simple, needing a
1493 couple of insns. Prior to reloading, we can't tell how many registers
1494 must be saved, so return 0 then.
1496 If NON_SAVING_SETJMP is defined and true, then it is not possible
1497 for the epilogue to be simple, so return 0. This is a special case
1498 since NON_SAVING_SETJMP will not cause regs_ever_live to change until
1499 final, but jump_optimize may need to know sooner if a `return' is OK. */
1502 simple_386_epilogue ()
1506 int reglimit = (frame_pointer_needed
1507 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
1508 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1509 || current_function_uses_const_pool);
1511 #ifdef NON_SAVING_SETJMP
1512 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
1516 if (! reload_completed)
1519 for (regno = reglimit - 1; regno >= 0; regno--)
1520 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1521 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1524 return nregs == 0 || ! frame_pointer_needed;
1528 /* This function generates the assembly code for function exit.
1529 FILE is an stdio stream to output the code to.
1530 SIZE is an int: how many units of temporary storage to deallocate. */
1533 function_epilogue (file, size)
1538 register int nregs, limit;
1541 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1542 || current_function_uses_const_pool);
1544 /* Compute the number of registers to pop */
1546 limit = (frame_pointer_needed
1547 ? FRAME_POINTER_REGNUM
1548 : STACK_POINTER_REGNUM);
1552 for (regno = limit - 1; regno >= 0; regno--)
1553 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1554 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1557 /* sp is often unreliable so we must go off the frame pointer,
1560 /* In reality, we may not care if sp is unreliable, because we can
1561 restore the register relative to the frame pointer. In theory,
1562 since each move is the same speed as a pop, and we don't need the
1563 leal, this is faster. For now restore multiple registers the old
1566 offset = -size - (nregs * UNITS_PER_WORD);
1568 xops[2] = stack_pointer_rtx;
1570 if (nregs > 1 || ! frame_pointer_needed)
1572 if (frame_pointer_needed)
1574 xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset);
1575 output_asm_insn (AS2 (lea%L2,%0,%2), xops);
1578 for (regno = 0; regno < limit; regno++)
1579 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1580 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1582 xops[0] = gen_rtx (REG, SImode, regno);
1583 output_asm_insn ("pop%L0 %0", xops);
1587 for (regno = 0; regno < limit; regno++)
1588 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1589 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1591 xops[0] = gen_rtx (REG, SImode, regno);
1592 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
1593 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
1597 if (frame_pointer_needed)
1599 /* On i486, mov & pop is faster than "leave". */
1603 xops[0] = frame_pointer_rtx;
1604 output_asm_insn (AS2 (mov%L2,%0,%2), xops);
1605 output_asm_insn ("pop%L0 %0", xops);
1608 output_asm_insn ("leave", xops);
1612 /* If there is no frame pointer, we must still release the frame. */
1614 xops[0] = GEN_INT (size);
1615 output_asm_insn (AS2 (add%L2,%0,%2), xops);
1618 if (current_function_pops_args && current_function_args_size)
1620 xops[1] = GEN_INT (current_function_pops_args);
1622 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
1623 asked to pop more, pop return address, do explicit add, and jump
1624 indirectly to the caller. */
1626 if (current_function_pops_args >= 32768)
1628 /* ??? Which register to use here? */
1629 xops[0] = gen_rtx (REG, SImode, 2);
1630 output_asm_insn ("pop%L0 %0", xops);
1631 output_asm_insn (AS2 (add%L2,%1,%2), xops);
1632 output_asm_insn ("jmp %*%0", xops);
1635 output_asm_insn ("ret %1", xops);
1638 output_asm_insn ("ret", xops);
1642 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1643 that is a valid memory address for an instruction.
1644 The MODE argument is the machine mode for the MEM expression
1645 that wants to use this address.
1647 On x86, legitimate addresses are:
1648 base movl (base),reg
1649 displacement movl disp,reg
1650 base + displacement movl disp(base),reg
1651 index + base movl (base,index),reg
1652 (index + base) + displacement movl disp(base,index),reg
1653 index*scale movl (,index,scale),reg
1654 index*scale + disp movl disp(,index,scale),reg
1655 index*scale + base movl (base,index,scale),reg
1656 (index*scale + base) + disp movl disp(base,index,scale),reg
1658 In each case, scale can be 1, 2, 4, 8. */
1660 /* This is exactly the same as print_operand_addr, except that
1661 it recognizes addresses instead of printing them.
1663 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1664 convert common non-canonical forms to canonical form so that they will
1667 #define ADDR_INVALID(msg,insn) \
1669 if (TARGET_DEBUG_ADDR) \
1671 fprintf (stderr, msg); \
1677 legitimate_address_p (mode, addr, strict)
1678 enum machine_mode mode;
1682 rtx base = NULL_RTX;
1683 rtx indx = NULL_RTX;
1684 rtx scale = NULL_RTX;
1685 rtx disp = NULL_RTX;
1687 if (TARGET_DEBUG_ADDR)
1690 "\n==========\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
1691 GET_MODE_NAME (mode), strict);
1696 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
1697 base = addr; /* base reg */
1699 else if (GET_CODE (addr) == PLUS)
1701 rtx op0 = XEXP (addr, 0);
1702 rtx op1 = XEXP (addr, 1);
1703 enum rtx_code code0 = GET_CODE (op0);
1704 enum rtx_code code1 = GET_CODE (op1);
1706 if (code0 == REG || code0 == SUBREG)
1708 if (code1 == REG || code1 == SUBREG)
1710 indx = op0; /* index + base */
1716 base = op0; /* base + displacement */
1721 else if (code0 == MULT)
1723 indx = XEXP (op0, 0);
1724 scale = XEXP (op0, 1);
1726 if (code1 == REG || code1 == SUBREG)
1727 base = op1; /* index*scale + base */
1730 disp = op1; /* index*scale + disp */
1733 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
1735 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */
1736 scale = XEXP (XEXP (op0, 0), 1);
1737 base = XEXP (op0, 1);
1741 else if (code0 == PLUS)
1743 indx = XEXP (op0, 0); /* index + base + disp */
1744 base = XEXP (op0, 1);
1750 ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
1755 else if (GET_CODE (addr) == MULT)
1757 indx = XEXP (addr, 0); /* index*scale */
1758 scale = XEXP (addr, 1);
1762 disp = addr; /* displacement */
1764 /* Allow arg pointer and stack pointer as index if there is not scaling */
1765 if (base && indx && !scale
1766 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
1773 /* Validate base register */
1774 /* Don't allow SUBREG's here, it can lead to spill failures when the base
1775 is one word out of a two word structure, which is represented internally
1779 if (GET_CODE (base) != REG)
1781 ADDR_INVALID ("Base is not a register.\n", base);
1785 if ((strict && !REG_OK_FOR_BASE_STRICT_P (base))
1786 || (!strict && !REG_OK_FOR_BASE_NONSTRICT_P (base)))
1788 ADDR_INVALID ("Base is not valid.\n", base);
1793 /* Validate index register */
1794 /* Don't allow SUBREG's here, it can lead to spill failures when the index
1795 is one word out of a two word structure, which is represented internally
1799 if (GET_CODE (indx) != REG)
1801 ADDR_INVALID ("Index is not a register.\n", indx);
1805 if ((strict && !REG_OK_FOR_INDEX_STRICT_P (indx))
1806 || (!strict && !REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
1808 ADDR_INVALID ("Index is not valid.\n", indx);
1813 abort (); /* scale w/o index invalid */
1815 /* Validate scale factor */
1818 HOST_WIDE_INT value;
1820 if (GET_CODE (scale) != CONST_INT)
1822 ADDR_INVALID ("Scale is not valid.\n", scale);
1826 value = INTVAL (scale);
1827 if (value != 1 && value != 2 && value != 4 && value != 8)
1829 ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
1834 /* Validate displacement */
1837 if (!CONSTANT_ADDRESS_P (disp))
1839 ADDR_INVALID ("Displacement is not valid.\n", disp);
1843 if (GET_CODE (disp) == CONST_DOUBLE)
1845 ADDR_INVALID ("Displacement is a const_double.\n", disp);
1849 if (flag_pic && SYMBOLIC_CONST (disp) && base != pic_offset_table_rtx
1850 && (indx != pic_offset_table_rtx || scale != NULL_RTX))
1852 ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp);
1856 if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp)
1857 && (base != NULL_RTX || indx != NULL_RTX))
1859 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", disp);
1864 if (TARGET_DEBUG_ADDR)
1865 fprintf (stderr, "Address is valid.\n");
1867 /* Everything looks valid, return true */
1872 /* Return a legitimate reference for ORIG (an address) using the
1873 register REG. If REG is 0, a new pseudo is generated.
1875 There are three types of references that must be handled:
1877 1. Global data references must load the address from the GOT, via
1878 the PIC reg. An insn is emitted to do this load, and the reg is
1881 2. Static data references must compute the address as an offset
1882 from the GOT, whose base is in the PIC reg. An insn is emitted to
1883 compute the address into a reg, and the reg is returned. Static
1884 data objects have SYMBOL_REF_FLAG set to differentiate them from
1885 global data objects.
1887 3. Constant pool addresses must be handled special. They are
1888 considered legitimate addresses, but only if not used with regs.
1889 When printed, the output routines know to print the reference with the
1890 PIC reg, even though the PIC reg doesn't appear in the RTL.
1892 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
1893 reg also appears in the address (except for constant pool references,
1896 "switch" statements also require special handling when generating
1897 PIC code. See comments by the `casesi' insn in i386.md for details. */
1900 legitimize_pic_address (orig, reg)
1907 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
1909 if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr))
1914 reg = gen_reg_rtx (Pmode);
1916 if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr))
1917 || GET_CODE (addr) == LABEL_REF)
1918 new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig);
1920 new = gen_rtx (MEM, Pmode,
1921 gen_rtx (PLUS, Pmode,
1922 pic_offset_table_rtx, orig));
1924 emit_move_insn (reg, new);
1926 current_function_uses_pic_offset_table = 1;
1929 else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
1933 if (GET_CODE (addr) == CONST)
1935 addr = XEXP (addr, 0);
1936 if (GET_CODE (addr) != PLUS)
1940 if (XEXP (addr, 0) == pic_offset_table_rtx)
1944 reg = gen_reg_rtx (Pmode);
1946 base = legitimize_pic_address (XEXP (addr, 0), reg);
1947 addr = legitimize_pic_address (XEXP (addr, 1),
1948 base == reg ? NULL_RTX : reg);
1950 if (GET_CODE (addr) == CONST_INT)
1951 return plus_constant (base, INTVAL (addr));
1953 if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
1955 base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0));
1956 addr = XEXP (addr, 1);
1958 return gen_rtx (PLUS, Pmode, base, addr);
1964 /* Emit insns to move operands[1] into operands[0]. */
1967 emit_pic_move (operands, mode)
1969 enum machine_mode mode;
1971 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
1973 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
1974 operands[1] = (rtx) force_reg (SImode, operands[1]);
1976 operands[1] = legitimize_pic_address (operands[1], temp);
1980 /* Try machine-dependent ways of modifying an illegitimate address
1981 to be legitimate. If we find one, return the new, valid address.
1982 This macro is used in only one place: `memory_address' in explow.c.
1984 OLDX is the address as it was before break_out_memory_refs was called.
1985 In some cases it is useful to look at this to decide what needs to be done.
1987 MODE and WIN are passed so that this macro can use
1988 GO_IF_LEGITIMATE_ADDRESS.
1990 It is always safe for this macro to do nothing. It exists to recognize
1991 opportunities to optimize the output.
1993 For the 80386, we handle X+REG by loading X into a register R and
1994 using R+REG. R will go in a general reg and indexing will be used.
1995 However, if REG is a broken-out memory address or multiplication,
1996 nothing needs to be done because REG can certainly go in a general reg.
1998 When -fpic is used, special handling is needed for symbolic references.
1999 See comments by legitimize_pic_address in i386.c for details. */
2002 legitimize_address (x, oldx, mode)
2005 enum machine_mode mode;
2010 if (TARGET_DEBUG_ADDR)
2012 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", GET_MODE_NAME (mode));
2016 if (flag_pic && SYMBOLIC_CONST (x))
2017 return legitimize_pic_address (x, 0);
2019 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2020 if (GET_CODE (x) == ASHIFT
2021 && GET_CODE (XEXP (x, 1)) == CONST_INT
2022 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
2025 x = gen_rtx (MULT, Pmode,
2026 force_reg (Pmode, XEXP (x, 0)),
2027 GEN_INT (1 << log));
2030 if (GET_CODE (x) == PLUS)
2032 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2033 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2034 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2035 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
2038 XEXP (x, 0) = gen_rtx (MULT, Pmode,
2039 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
2040 GEN_INT (1 << log));
2043 if (GET_CODE (XEXP (x, 1)) == ASHIFT
2044 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2045 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
2048 XEXP (x, 1) = gen_rtx (MULT, Pmode,
2049 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
2050 GEN_INT (1 << log));
2053 /* Put multiply first if it isn't already */
2054 if (GET_CODE (XEXP (x, 1)) == MULT)
2056 rtx tmp = XEXP (x, 0);
2057 XEXP (x, 0) = XEXP (x, 1);
2062 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2063 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2064 created by virtual register instantiation, register elimination, and
2065 similar optimizations. */
2066 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
2069 x = gen_rtx (PLUS, Pmode,
2070 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
2071 XEXP (XEXP (x, 1), 1));
2074 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2075 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2076 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2077 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2078 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2079 && CONSTANT_P (XEXP (x, 1)))
2081 rtx constant, other;
2083 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2085 constant = XEXP (x, 1);
2086 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2088 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2090 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2091 other = XEXP (x, 1);
2099 x = gen_rtx (PLUS, Pmode,
2100 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
2101 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2102 plus_constant (other, INTVAL (constant)));
2106 if (changed && legitimate_address_p (mode, x, FALSE))
2109 if (GET_CODE (XEXP (x, 0)) == MULT)
2112 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
2115 if (GET_CODE (XEXP (x, 1)) == MULT)
2118 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
2122 && GET_CODE (XEXP (x, 1)) == REG
2123 && GET_CODE (XEXP (x, 0)) == REG)
2126 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
2129 x = legitimize_pic_address (x, 0);
2132 if (changed && legitimate_address_p (mode, x, FALSE))
2135 if (GET_CODE (XEXP (x, 0)) == REG)
2137 register rtx temp = gen_reg_rtx (Pmode);
2138 register rtx val = force_operand (XEXP (x, 1), temp);
2140 emit_move_insn (temp, val);
2146 else if (GET_CODE (XEXP (x, 1)) == REG)
2148 register rtx temp = gen_reg_rtx (Pmode);
2149 register rtx val = force_operand (XEXP (x, 0), temp);
2151 emit_move_insn (temp, val);
2162 /* Print an integer constant expression in assembler syntax. Addition
2163 and subtraction are the only arithmetic that may appear in these
2164 expressions. FILE is the stdio stream to write to, X is the rtx, and
2165 CODE is the operand print code from the output string. */
2168 output_pic_addr_const (file, x, code)
2175 switch (GET_CODE (x))
2186 if (GET_CODE (x) == SYMBOL_REF)
2187 assemble_name (file, XSTR (x, 0));
2190 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
2191 CODE_LABEL_NUMBER (XEXP (x, 0)));
2192 assemble_name (asm_out_file, buf);
2195 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
2196 fprintf (file, "@GOTOFF(%%ebx)");
2197 else if (code == 'P')
2198 fprintf (file, "@PLT");
2199 else if (GET_CODE (x) == LABEL_REF)
2200 fprintf (file, "@GOTOFF");
2201 else if (! SYMBOL_REF_FLAG (x))
2202 fprintf (file, "@GOT");
2204 fprintf (file, "@GOTOFF");
2209 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
2210 assemble_name (asm_out_file, buf);
2214 fprintf (file, "%d", INTVAL (x));
2218 /* This used to output parentheses around the expression,
2219 but that does not work on the 386 (either ATT or BSD assembler). */
2220 output_pic_addr_const (file, XEXP (x, 0), code);
2224 if (GET_MODE (x) == VOIDmode)
2226 /* We can use %d if the number is <32 bits and positive. */
2227 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
2228 fprintf (file, "0x%x%08x",
2229 CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x));
2231 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
2234 /* We can't handle floating point constants;
2235 PRINT_OPERAND must handle them. */
2236 output_operand_lossage ("floating constant misused");
2240 /* Some assemblers need integer constants to appear last (eg masm). */
2241 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
2243 output_pic_addr_const (file, XEXP (x, 1), code);
2244 if (INTVAL (XEXP (x, 0)) >= 0)
2245 fprintf (file, "+");
2246 output_pic_addr_const (file, XEXP (x, 0), code);
2250 output_pic_addr_const (file, XEXP (x, 0), code);
2251 if (INTVAL (XEXP (x, 1)) >= 0)
2252 fprintf (file, "+");
2253 output_pic_addr_const (file, XEXP (x, 1), code);
2258 output_pic_addr_const (file, XEXP (x, 0), code);
2259 fprintf (file, "-");
2260 output_pic_addr_const (file, XEXP (x, 1), code);
2264 output_operand_lossage ("invalid expression as operand");
2269 f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
2270 D,L,W,B,Q,S -- print the opcode suffix for specified size of operand.
2271 R -- print the prefix for register names.
2272 z -- print the opcode suffix for the size of the current operand.
2273 * -- print a star (in certain assembler syntax)
2274 w -- print the operand as if it's a "word" (HImode) even if it isn't.
2275 c -- don't print special prefixes before constant operands.
2276 J -- print the appropriate jump operand.
2280 print_operand (file, x, code)
2295 PUT_OP_SIZE (code, 'l', file);
2299 PUT_OP_SIZE (code, 'w', file);
2303 PUT_OP_SIZE (code, 'b', file);
2307 PUT_OP_SIZE (code, 'l', file);
2311 PUT_OP_SIZE (code, 's', file);
2315 PUT_OP_SIZE (code, 't', file);
2319 /* 387 opcodes don't get size suffixes if the operands are
2322 if (STACK_REG_P (x))
2325 /* this is the size of op from size of operand */
2326 switch (GET_MODE_SIZE (GET_MODE (x)))
2329 PUT_OP_SIZE ('B', 'b', file);
2333 PUT_OP_SIZE ('W', 'w', file);
2337 if (GET_MODE (x) == SFmode)
2339 PUT_OP_SIZE ('S', 's', file);
2343 PUT_OP_SIZE ('L', 'l', file);
2347 PUT_OP_SIZE ('T', 't', file);
2351 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
2353 #ifdef GAS_MNEMONICS
2354 PUT_OP_SIZE ('Q', 'q', file);
2357 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
2361 PUT_OP_SIZE ('Q', 'l', file);
2374 switch (GET_CODE (x))
2376 /* These conditions are appropriate for testing the result
2377 of an arithmetic operation, not for a compare operation.
2378 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume
2379 CC_Z_IN_NOT_C false and not floating point. */
2380 case NE: fputs ("jne", file); return;
2381 case EQ: fputs ("je", file); return;
2382 case GE: fputs ("jns", file); return;
2383 case GT: fputs ("jg", file); return;
2384 case LE: fputs ("jle", file); return;
2385 case LT: fputs ("js", file); return;
2386 case GEU: fputs ("jae", file); return;
2387 case GTU: fputs ("ja", file); return;
2388 case LEU: fputs ("jbe", file); return;
2389 case LTU: fputs ("jb", file); return;
2397 sprintf (str, "invalid operand code `%c'", code);
2398 output_operand_lossage (str);
2402 if (GET_CODE (x) == REG)
2404 PRINT_REG (x, code, file);
2406 else if (GET_CODE (x) == MEM)
2408 PRINT_PTR (x, file);
2409 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
2412 output_pic_addr_const (file, XEXP (x, 0), code);
2414 output_addr_const (file, XEXP (x, 0));
2417 output_address (XEXP (x, 0));
2419 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
2421 REAL_VALUE_TYPE r; long l;
2422 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2423 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2424 PRINT_IMMED_PREFIX (file);
2425 fprintf (file, "0x%x", l);
2427 /* These float cases don't actually occur as immediate operands. */
2428 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
2430 REAL_VALUE_TYPE r; char dstr[30];
2431 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2432 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
2433 fprintf (file, "%s", dstr);
2435 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
2437 REAL_VALUE_TYPE r; char dstr[30];
2438 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2439 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
2440 fprintf (file, "%s", dstr);
2446 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2447 PRINT_IMMED_PREFIX (file);
2448 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
2449 || GET_CODE (x) == LABEL_REF)
2450 PRINT_OFFSET_PREFIX (file);
2453 output_pic_addr_const (file, x, code);
2455 output_addr_const (file, x);
2459 /* Print a memory operand whose address is ADDR. */
2462 print_operand_address (file, addr)
2466 register rtx reg1, reg2, breg, ireg;
2469 switch (GET_CODE (addr))
2473 fprintf (file, "%se", RP);
2474 fputs (hi_reg_name[REGNO (addr)], file);
2484 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
2486 offset = XEXP (addr, 0);
2487 addr = XEXP (addr, 1);
2489 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
2491 offset = XEXP (addr, 1);
2492 addr = XEXP (addr, 0);
2494 if (GET_CODE (addr) != PLUS) ;
2495 else if (GET_CODE (XEXP (addr, 0)) == MULT)
2497 reg1 = XEXP (addr, 0);
2498 addr = XEXP (addr, 1);
2500 else if (GET_CODE (XEXP (addr, 1)) == MULT)
2502 reg1 = XEXP (addr, 1);
2503 addr = XEXP (addr, 0);
2505 else if (GET_CODE (XEXP (addr, 0)) == REG)
2507 reg1 = XEXP (addr, 0);
2508 addr = XEXP (addr, 1);
2510 else if (GET_CODE (XEXP (addr, 1)) == REG)
2512 reg1 = XEXP (addr, 1);
2513 addr = XEXP (addr, 0);
2515 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
2517 if (reg1 == 0) reg1 = addr;
2523 if (addr != 0) abort ();
2526 if ((reg1 && GET_CODE (reg1) == MULT)
2527 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
2532 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
2538 if (ireg != 0 || breg != 0)
2545 output_pic_addr_const (file, addr, 0);
2547 else if (GET_CODE (addr) == LABEL_REF)
2548 output_asm_label (addr);
2551 output_addr_const (file, addr);
2554 if (ireg != 0 && GET_CODE (ireg) == MULT)
2556 scale = INTVAL (XEXP (ireg, 1));
2557 ireg = XEXP (ireg, 0);
2560 /* The stack pointer can only appear as a base register,
2561 never an index register, so exchange the regs if it is wrong. */
2563 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
2572 /* output breg+ireg*scale */
2573 PRINT_B_I_S (breg, ireg, scale, file);
2580 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2582 scale = INTVAL (XEXP (addr, 0));
2583 ireg = XEXP (addr, 1);
2587 scale = INTVAL (XEXP (addr, 1));
2588 ireg = XEXP (addr, 0);
2590 output_addr_const (file, const0_rtx);
2591 PRINT_B_I_S ((rtx) 0, ireg, scale, file);
2596 if (GET_CODE (addr) == CONST_INT
2597 && INTVAL (addr) < 0x8000
2598 && INTVAL (addr) >= -0x8000)
2599 fprintf (file, "%d", INTVAL (addr));
2603 output_pic_addr_const (file, addr, 0);
2605 output_addr_const (file, addr);
2610 /* Set the cc_status for the results of an insn whose pattern is EXP.
2611 On the 80386, we assume that only test and compare insns, as well
2612 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT,
2613 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
2614 Also, we assume that jumps, moves and sCOND don't affect the condition
2615 codes. All else clobbers the condition codes, by assumption.
2617 We assume that ALL integer add, minus, etc. instructions effect the
2618 condition codes. This MUST be consistent with i386.md.
2620 We don't record any float test or compare - the redundant test &
2621 compare check in final.c does not handle stack-like regs correctly. */
2624 notice_update_cc (exp)
2627 if (GET_CODE (exp) == SET)
2629 /* Jumps do not alter the cc's. */
2630 if (SET_DEST (exp) == pc_rtx)
2632 /* Moving register or memory into a register:
2633 it doesn't alter the cc's, but it might invalidate
2634 the RTX's which we remember the cc's came from.
2635 (Note that moving a constant 0 or 1 MAY set the cc's). */
2636 if (REG_P (SET_DEST (exp))
2637 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
2638 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
2640 if (cc_status.value1
2641 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
2642 cc_status.value1 = 0;
2643 if (cc_status.value2
2644 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
2645 cc_status.value2 = 0;
2648 /* Moving register into memory doesn't alter the cc's.
2649 It may invalidate the RTX's which we remember the cc's came from. */
2650 if (GET_CODE (SET_DEST (exp)) == MEM
2651 && (REG_P (SET_SRC (exp))
2652 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
2654 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM)
2655 cc_status.value1 = 0;
2656 if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM)
2657 cc_status.value2 = 0;
2660 /* Function calls clobber the cc's. */
2661 else if (GET_CODE (SET_SRC (exp)) == CALL)
2666 /* Tests and compares set the cc's in predictable ways. */
2667 else if (SET_DEST (exp) == cc0_rtx)
2670 cc_status.value1 = SET_SRC (exp);
2673 /* Certain instructions effect the condition codes. */
2674 else if (GET_MODE (SET_SRC (exp)) == SImode
2675 || GET_MODE (SET_SRC (exp)) == HImode
2676 || GET_MODE (SET_SRC (exp)) == QImode)
2677 switch (GET_CODE (SET_SRC (exp)))
2679 case ASHIFTRT: case LSHIFTRT:
2681 /* Shifts on the 386 don't set the condition codes if the
2682 shift count is zero. */
2683 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
2688 /* We assume that the CONST_INT is non-zero (this rtx would
2689 have been deleted if it were zero. */
2691 case PLUS: case MINUS: case NEG:
2692 case AND: case IOR: case XOR:
2693 cc_status.flags = CC_NO_OVERFLOW;
2694 cc_status.value1 = SET_SRC (exp);
2695 cc_status.value2 = SET_DEST (exp);
2706 else if (GET_CODE (exp) == PARALLEL
2707 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
2709 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
2711 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
2714 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
2715 cc_status.flags |= CC_IN_80387;
2717 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
2728 /* Split one or more DImode RTL references into pairs of SImode
2729 references. The RTL can be REG, offsettable MEM, integer constant, or
2730 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2731 split and "num" is its length. lo_half and hi_half are output arrays
2732 that parallel "operands". */
2735 split_di (operands, num, lo_half, hi_half)
2738 rtx lo_half[], hi_half[];
2742 if (GET_CODE (operands[num]) == REG)
2744 lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]));
2745 hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1);
2747 else if (CONSTANT_P (operands[num]))
2749 split_double (operands[num], &lo_half[num], &hi_half[num]);
2751 else if (offsettable_memref_p (operands[num]))
2753 lo_half[num] = operands[num];
2754 hi_half[num] = adj_offsettable_operand (operands[num], 4);
2761 /* Return 1 if this is a valid binary operation on a 387.
2762 OP is the expression matched, and MODE is its mode. */
2765 binary_387_op (op, mode)
2767 enum machine_mode mode;
2769 if (mode != VOIDmode && mode != GET_MODE (op))
2772 switch (GET_CODE (op))
2778 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
2786 /* Return 1 if this is a valid shift or rotate operation on a 386.
2787 OP is the expression matched, and MODE is its mode. */
2792 enum machine_mode mode;
2794 rtx operand = XEXP (op, 0);
2796 if (mode != VOIDmode && mode != GET_MODE (op))
2799 if (GET_MODE (operand) != GET_MODE (op)
2800 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
2803 return (GET_CODE (op) == ASHIFT
2804 || GET_CODE (op) == ASHIFTRT
2805 || GET_CODE (op) == LSHIFTRT
2806 || GET_CODE (op) == ROTATE
2807 || GET_CODE (op) == ROTATERT);
2810 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
2811 MODE is not used. */
2814 VOIDmode_compare_op (op, mode)
2816 enum machine_mode mode;
2818 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
2821 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
2822 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
2823 is the expression of the binary operation. The output may either be
2824 emitted here, or returned to the caller, like all output_* functions.
2826 There is no guarantee that the operands are the same mode, as they
2827 might be within FLOAT or FLOAT_EXTEND expressions. */
2830 output_387_binary_op (insn, operands)
2836 static char buf[100];
2838 switch (GET_CODE (operands[3]))
2841 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2842 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
2849 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2850 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
2857 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2858 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
2865 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2866 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
2876 strcpy (buf, base_op);
2878 switch (GET_CODE (operands[3]))
2882 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
2885 operands[2] = operands[1];
2889 if (GET_CODE (operands[2]) == MEM)
2890 return strcat (buf, AS1 (%z2,%2));
2892 if (NON_STACK_REG_P (operands[1]))
2894 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
2897 else if (NON_STACK_REG_P (operands[2]))
2899 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
2903 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
2904 return strcat (buf, AS2 (p,%2,%0));
2906 if (STACK_TOP_P (operands[0]))
2907 return strcat (buf, AS2C (%y2,%0));
2909 return strcat (buf, AS2C (%2,%0));
2913 if (GET_CODE (operands[1]) == MEM)
2914 return strcat (buf, AS1 (r%z1,%1));
2916 if (GET_CODE (operands[2]) == MEM)
2917 return strcat (buf, AS1 (%z2,%2));
2919 if (NON_STACK_REG_P (operands[1]))
2921 output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
2924 else if (NON_STACK_REG_P (operands[2]))
2926 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
2930 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
2933 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
2934 return strcat (buf, AS2 (rp,%2,%0));
2936 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2937 return strcat (buf, AS2 (p,%1,%0));
2939 if (STACK_TOP_P (operands[0]))
2941 if (STACK_TOP_P (operands[1]))
2942 return strcat (buf, AS2C (%y2,%0));
2944 return strcat (buf, AS2 (r,%y1,%0));
2946 else if (STACK_TOP_P (operands[1]))
2947 return strcat (buf, AS2C (%1,%0));
2949 return strcat (buf, AS2 (r,%2,%0));
2956 /* Output code for INSN to convert a float to a signed int. OPERANDS
2957 are the insn operands. The output may be SFmode or DFmode and the
2958 input operand may be SImode or DImode. As a special case, make sure
2959 that the 387 stack top dies if the output mode is DImode, because the
2960 hardware requires this. */
2963 output_fix_trunc (insn, operands)
2967 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2970 if (! STACK_TOP_P (operands[1]) ||
2971 (GET_MODE (operands[0]) == DImode && ! stack_top_dies))
2974 xops[0] = GEN_INT (12);
2975 xops[1] = operands[4];
2977 output_asm_insn (AS1 (fnstc%W2,%2), operands);
2978 output_asm_insn (AS2 (mov%L2,%2,%4), operands);
2979 output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
2980 output_asm_insn (AS2 (mov%L4,%4,%3), operands);
2981 output_asm_insn (AS1 (fldc%W3,%3), operands);
2983 if (NON_STACK_REG_P (operands[0]))
2984 output_to_reg (operands[0], stack_top_dies);
2985 else if (GET_CODE (operands[0]) == MEM)
2988 output_asm_insn (AS1 (fistp%z0,%0), operands);
2990 output_asm_insn (AS1 (fist%z0,%0), operands);
2995 return AS1 (fldc%W2,%2);
2998 /* Output code for INSN to compare OPERANDS. The two operands might
2999 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
3000 expression. If the compare is in mode CCFPEQmode, use an opcode that
3001 will not fault if a qNaN is present. */
3004 output_float_compare (insn, operands)
3009 rtx body = XVECEXP (PATTERN (insn), 0, 0);
3010 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
3012 if (! STACK_TOP_P (operands[0]))
3015 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
3017 if (STACK_REG_P (operands[1])
3019 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3020 && REGNO (operands[1]) != FIRST_STACK_REG)
3022 /* If both the top of the 387 stack dies, and the other operand
3023 is also a stack register that dies, then this must be a
3024 `fcompp' float compare */
3026 if (unordered_compare)
3027 output_asm_insn ("fucompp", operands);
3029 output_asm_insn ("fcompp", operands);
3033 static char buf[100];
3035 /* Decide if this is the integer or float compare opcode, or the
3036 unordered float compare. */
3038 if (unordered_compare)
3039 strcpy (buf, "fucom");
3040 else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
3041 strcpy (buf, "fcom");
3043 strcpy (buf, "ficom");
3045 /* Modify the opcode if the 387 stack is to be popped. */
3050 if (NON_STACK_REG_P (operands[1]))
3051 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
3053 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
3056 /* Now retrieve the condition code. */
3058 return output_fp_cc0_set (insn);
3061 /* Output opcodes to transfer the results of FP compare or test INSN
3062 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
3063 result of the compare or test is unordered, no comparison operator
3064 succeeds except NE. Return an output template, if any. */
3067 output_fp_cc0_set (insn)
3071 rtx unordered_label;
3075 xops[0] = gen_rtx (REG, HImode, 0);
3076 output_asm_insn (AS1 (fnsts%W0,%0), xops);
3078 if (! TARGET_IEEE_FP)
3081 next = next_cc0_user (insn);
3082 if (next == NULL_RTX)
3085 if (GET_CODE (next) == JUMP_INSN
3086 && GET_CODE (PATTERN (next)) == SET
3087 && SET_DEST (PATTERN (next)) == pc_rtx
3088 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
3090 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
3092 else if (GET_CODE (PATTERN (next)) == SET)
3094 code = GET_CODE (SET_SRC (PATTERN (next)));
3099 xops[0] = gen_rtx (REG, QImode, 0);
3104 xops[1] = GEN_INT (0x45);
3105 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3110 xops[1] = GEN_INT (0x45);
3111 xops[2] = GEN_INT (0x01);
3112 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3113 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
3118 xops[1] = GEN_INT (0x05);
3119 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3124 xops[1] = GEN_INT (0x45);
3125 xops[2] = GEN_INT (0x40);
3126 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3127 output_asm_insn (AS1 (dec%B0,%h0), xops);
3128 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
3133 xops[1] = GEN_INT (0x45);
3134 xops[2] = GEN_INT (0x40);
3135 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3136 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
3141 xops[1] = GEN_INT (0x44);
3142 xops[2] = GEN_INT (0x40);
3143 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
3144 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
3158 #define MAX_386_STACK_LOCALS 2
3160 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
3162 /* Define the structure for the machine field in struct function. */
3163 struct machine_function
3165 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
3168 /* Functions to save and restore i386_stack_locals.
3169 These will be called, via pointer variables,
3170 from push_function_context and pop_function_context. */
3173 save_386_machine_status (p)
3176 p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals);
3177 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
3178 sizeof i386_stack_locals);
3182 restore_386_machine_status (p)
3185 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
3186 sizeof i386_stack_locals);
3190 /* Clear stack slot assignments remembered from previous functions.
3191 This is called from INIT_EXPANDERS once before RTL is emitted for each
3195 clear_386_stack_locals ()
3197 enum machine_mode mode;
3200 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
3201 mode = (enum machine_mode) ((int) mode + 1))
3202 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
3203 i386_stack_locals[(int) mode][n] = NULL_RTX;
3205 /* Arrange to save and restore i386_stack_locals around nested functions. */
3206 save_machine_status = save_386_machine_status;
3207 restore_machine_status = restore_386_machine_status;
3210 /* Return a MEM corresponding to a stack slot with mode MODE.
3211 Allocate a new slot if necessary.
3213 The RTL for a function can have several slots available: N is
3214 which slot to use. */
3217 assign_386_stack_local (mode, n)
3218 enum machine_mode mode;
3221 if (n < 0 || n >= MAX_386_STACK_LOCALS)
3224 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
3225 i386_stack_locals[(int) mode][n]
3226 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
3228 return i386_stack_locals[(int) mode][n];