1 /* Subroutines for insn-output.c for Intel X86.
2 Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
36 #ifdef EXTRA_CONSTRAINT
37 /* If EXTRA_CONSTRAINT is defined, then the 'S'
38 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
39 asm statements that need 'S' for class SIREG will break. */
40 error EXTRA_CONSTRAINT conflicts with S constraint letter
41 /* The previous line used to be #error, but some compilers barf
42 even if the conditional was untrue. */
45 #define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx))
47 extern FILE *asm_out_file;
48 extern char *strcat ();
50 char *singlemove_string ();
51 char *output_move_const_single ();
52 char *output_fp_cc0_set ();
54 char *hi_reg_name[] = HI_REGISTER_NAMES;
55 char *qi_reg_name[] = QI_REGISTER_NAMES;
56 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
58 /* Array of the smallest class containing reg number REGNO, indexed by
59 REGNO. Used by REGNO_REG_CLASS in i386.h. */
61 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
64 AREG, DREG, CREG, BREG,
66 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
68 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
69 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
74 /* Test and compare insns in i386.md store the information needed to
75 generate branch and scc insns here. */
77 struct rtx_def *i386_compare_op0 = NULL_RTX;
78 struct rtx_def *i386_compare_op1 = NULL_RTX;
79 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
81 /* Register allocation order */
82 char *i386_reg_alloc_order = (char *)0;
83 static char regs_allocated[FIRST_PSEUDO_REGISTER];
86 /* Sometimes certain combinations of command options do not make
87 sense on a particular target machine. You can define a macro
88 `OVERRIDE_OPTIONS' to take account of this. This macro, if
89 defined, is executed once just after all the command options have
92 Don't use this macro to turn on various extra optimizations for
93 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
100 #ifdef SUBTARGET_OVERRIDE_OPTIONS
101 SUBTARGET_OVERRIDE_OPTIONS;
104 /* Validate registers in register allocation order */
105 if (i386_reg_alloc_order)
107 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
111 case 'a': regno = 0; break;
112 case 'd': regno = 1; break;
113 case 'c': regno = 2; break;
114 case 'b': regno = 3; break;
115 case 'S': regno = 4; break;
116 case 'D': regno = 5; break;
117 case 'B': regno = 6; break;
119 default: fatal ("Register '%c' is unknown", ch);
122 if (regs_allocated[regno])
123 fatal ("Register '%c' was already specified in the allocation order", ch);
125 regs_allocated[regno] = 1;
130 /* A C statement (sans semicolon) to choose the order in which to
131 allocate hard registers for pseudo-registers local to a basic
134 Store the desired register order in the array `reg_alloc_order'.
135 Element 0 should be the register to allocate first; element 1, the
136 next register; and so on.
138 The macro body should not assume anything about the contents of
139 `reg_alloc_order' before execution of the macro.
141 On most machines, it is not necessary to define this macro. */
144 order_regs_for_local_alloc ()
146 int i, ch, order, regno;
148 /* User specified the register allocation order */
149 if (i386_reg_alloc_order)
151 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
155 case 'a': regno = 0; break;
156 case 'd': regno = 1; break;
157 case 'c': regno = 2; break;
158 case 'b': regno = 3; break;
159 case 'S': regno = 4; break;
160 case 'D': regno = 5; break;
161 case 'B': regno = 6; break;
164 reg_alloc_order[order++] = regno;
167 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
169 if (!regs_allocated[i])
170 reg_alloc_order[order++] = i;
174 /* If users did not specify a register allocation order, favor eax
175 normally except if cse is following jumps, then favor edx so
176 that function returns are cse'ed */
179 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
180 reg_alloc_order[i] = i;
182 if (optimize && flag_cse_follow_jumps && !leaf_function_p ())
184 reg_alloc_order[0] = 1; /* edx */
185 reg_alloc_order[1] = 2; /* ecx */
186 reg_alloc_order[2] = 0; /* eax */
192 /* Output an insn whose source is a 386 integer register. SRC is the
193 rtx for the register, and TEMPLATE is the op-code template. SRC may
194 be either SImode or DImode.
196 The template will be output with operands[0] as SRC, and operands[1]
197 as a pointer to the top of the 386 stack. So a call from floatsidf2
198 would look like this:
200 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
202 where %z0 corresponds to the caller's operands[1], and is used to
203 emit the proper size suffix.
205 ??? Extend this to handle HImode - a 387 can load and store HImode
209 output_op_from_reg (src, template)
214 int size = GET_MODE_SIZE (GET_MODE (src));
217 xops[1] = AT_SP (Pmode);
218 xops[2] = GEN_INT (size);
219 xops[3] = stack_pointer_rtx;
221 if (size > UNITS_PER_WORD)
224 if (size > 2 * UNITS_PER_WORD)
226 high = gen_rtx (REG, SImode, REGNO (src) + 2);
227 output_asm_insn (AS1 (push%L0,%0), &high);
229 high = gen_rtx (REG, SImode, REGNO (src) + 1);
230 output_asm_insn (AS1 (push%L0,%0), &high);
232 output_asm_insn (AS1 (push%L0,%0), &src);
234 output_asm_insn (template, xops);
236 output_asm_insn (AS2 (add%L3,%2,%3), xops);
239 /* Output an insn to pop an value from the 387 top-of-stack to 386
240 register DEST. The 387 register stack is popped if DIES is true. If
241 the mode of DEST is an integer mode, a `fist' integer store is done,
242 otherwise a `fst' float store is done. */
245 output_to_reg (dest, dies)
250 int size = GET_MODE_SIZE (GET_MODE (dest));
252 xops[0] = AT_SP (Pmode);
253 xops[1] = stack_pointer_rtx;
254 xops[2] = GEN_INT (size);
257 output_asm_insn (AS2 (sub%L1,%2,%1), xops);
259 if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT)
262 output_asm_insn (AS1 (fistp%z3,%y0), xops);
264 output_asm_insn (AS1 (fist%z3,%y0), xops);
266 else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT)
269 output_asm_insn (AS1 (fstp%z3,%y0), xops);
272 if (GET_MODE (dest) == XFmode)
274 output_asm_insn (AS1 (fstp%z3,%y0), xops);
275 output_asm_insn (AS1 (fld%z3,%y0), xops);
278 output_asm_insn (AS1 (fst%z3,%y0), xops);
284 output_asm_insn (AS1 (pop%L0,%0), &dest);
286 if (size > UNITS_PER_WORD)
288 dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
289 output_asm_insn (AS1 (pop%L0,%0), &dest);
290 if (size > 2 * UNITS_PER_WORD)
292 dest = gen_rtx (REG, SImode, REGNO (dest) + 1);
293 output_asm_insn (AS1 (pop%L0,%0), &dest);
299 singlemove_string (operands)
303 if (GET_CODE (operands[0]) == MEM
304 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
306 if (XEXP (x, 0) != stack_pointer_rtx)
310 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
312 return output_move_const_single (operands);
314 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
315 return AS2 (mov%L0,%1,%0);
316 else if (CONSTANT_P (operands[1]))
317 return AS2 (mov%L0,%1,%0);
320 output_asm_insn ("push%L1 %1", operands);
325 /* Return a REG that occurs in ADDR with coefficient 1.
326 ADDR can be effectively incremented by incrementing REG. */
332 while (GET_CODE (addr) == PLUS)
334 if (GET_CODE (XEXP (addr, 0)) == REG)
335 addr = XEXP (addr, 0);
336 else if (GET_CODE (XEXP (addr, 1)) == REG)
337 addr = XEXP (addr, 1);
338 else if (CONSTANT_P (XEXP (addr, 0)))
339 addr = XEXP (addr, 1);
340 else if (CONSTANT_P (XEXP (addr, 1)))
341 addr = XEXP (addr, 0);
345 if (GET_CODE (addr) == REG)
350 /* Output an insn to add the constant N to the register X. */
361 output_asm_insn (AS1 (dec%L0,%0), xops);
363 output_asm_insn (AS1 (inc%L0,%0), xops);
366 xops[1] = GEN_INT (-n);
367 output_asm_insn (AS2 (sub%L0,%1,%0), xops);
371 xops[1] = GEN_INT (n);
372 output_asm_insn (AS2 (add%L0,%1,%0), xops);
376 /* Output assembler code to perform a doubleword move insn
377 with operands OPERANDS. */
380 output_move_double (operands)
383 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
387 rtx addreg0 = 0, addreg1 = 0;
388 int dest_overlapped_low = 0;
389 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
394 /* First classify both operands. */
396 if (REG_P (operands[0]))
398 else if (offsettable_memref_p (operands[0]))
400 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
402 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
404 else if (GET_CODE (operands[0]) == MEM)
409 if (REG_P (operands[1]))
411 else if (CONSTANT_P (operands[1]))
413 else if (offsettable_memref_p (operands[1]))
415 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
417 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
419 else if (GET_CODE (operands[1]) == MEM)
424 /* Check for the cases that the operand constraints are not
425 supposed to allow to happen. Abort if we get one,
426 because generating code for these cases is painful. */
428 if (optype0 == RNDOP || optype1 == RNDOP)
431 /* If one operand is decrementing and one is incrementing
432 decrement the former register explicitly
433 and change that operand into ordinary indexing. */
435 if (optype0 == PUSHOP && optype1 == POPOP)
437 /* ??? Can this ever happen on i386? */
438 operands[0] = XEXP (XEXP (operands[0], 0), 0);
439 asm_add (-size, operands[0]);
440 if (GET_MODE (operands[1]) == XFmode)
441 operands[0] = gen_rtx (MEM, XFmode, operands[0]);
442 else if (GET_MODE (operands[0]) == DFmode)
443 operands[0] = gen_rtx (MEM, DFmode, operands[0]);
445 operands[0] = gen_rtx (MEM, DImode, operands[0]);
449 if (optype0 == POPOP && optype1 == PUSHOP)
451 /* ??? Can this ever happen on i386? */
452 operands[1] = XEXP (XEXP (operands[1], 0), 0);
453 asm_add (-size, operands[1]);
454 if (GET_MODE (operands[1]) == XFmode)
455 operands[1] = gen_rtx (MEM, XFmode, operands[1]);
456 else if (GET_MODE (operands[1]) == DFmode)
457 operands[1] = gen_rtx (MEM, DFmode, operands[1]);
459 operands[1] = gen_rtx (MEM, DImode, operands[1]);
463 /* If an operand is an unoffsettable memory ref, find a register
464 we can increment temporarily to make it refer to the second word. */
466 if (optype0 == MEMOP)
467 addreg0 = find_addr_reg (XEXP (operands[0], 0));
469 if (optype1 == MEMOP)
470 addreg1 = find_addr_reg (XEXP (operands[1], 0));
472 /* Ok, we can do one word at a time.
473 Normally we do the low-numbered word first,
474 but if either operand is autodecrementing then we
475 do the high-numbered word first.
477 In either case, set up in LATEHALF the operands to use
478 for the high-numbered word and in some cases alter the
479 operands in OPERANDS to be suitable for the low-numbered word. */
483 if (optype0 == REGOP)
485 middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
486 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
488 else if (optype0 == OFFSOP)
490 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
491 latehalf[0] = adj_offsettable_operand (operands[0], 8);
495 middlehalf[0] = operands[0];
496 latehalf[0] = operands[0];
499 if (optype1 == REGOP)
501 middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
502 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
504 else if (optype1 == OFFSOP)
506 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
507 latehalf[1] = adj_offsettable_operand (operands[1], 8);
509 else if (optype1 == CNSTOP)
511 if (GET_CODE (operands[1]) == CONST_DOUBLE)
513 REAL_VALUE_TYPE r; long l[3];
515 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
516 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
517 operands[1] = GEN_INT (l[0]);
518 middlehalf[1] = GEN_INT (l[1]);
519 latehalf[1] = GEN_INT (l[2]);
521 else if (CONSTANT_P (operands[1]))
522 /* No non-CONST_DOUBLE constant should ever appear here. */
527 middlehalf[1] = operands[1];
528 latehalf[1] = operands[1];
531 else /* size is not 12: */
533 if (optype0 == REGOP)
534 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
535 else if (optype0 == OFFSOP)
536 latehalf[0] = adj_offsettable_operand (operands[0], 4);
538 latehalf[0] = operands[0];
540 if (optype1 == REGOP)
541 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
542 else if (optype1 == OFFSOP)
543 latehalf[1] = adj_offsettable_operand (operands[1], 4);
544 else if (optype1 == CNSTOP)
546 if (GET_CODE (operands[1]) == CONST_DOUBLE)
547 split_double (operands[1], &operands[1], &latehalf[1]);
548 else if (CONSTANT_P (operands[1]))
550 /* ??? jrv: Can this really happen? A DImode constant
551 that isn't a CONST_DOUBLE? */
552 if (GET_CODE (operands[1]) == CONST_INT
553 && INTVAL (operands[1]) < 0)
554 latehalf[1] = constm1_rtx;
556 latehalf[1] = const0_rtx;
560 latehalf[1] = operands[1];
563 /* If insn is effectively movd N (sp),-(sp) then we will do the
564 high word first. We should use the adjusted operand 1
565 (which is N+4 (sp) or N+8 (sp))
566 for the low word and middle word as well,
567 to compensate for the first decrement of sp. */
568 if (optype0 == PUSHOP
569 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
570 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
571 middlehalf[1] = operands[1] = latehalf[1];
573 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
574 if the upper part of reg N does not appear in the MEM, arrange to
575 emit the move late-half first. Otherwise, compute the MEM address
576 into the upper part of N and use that as a pointer to the memory
579 && (optype1 == OFFSOP || optype1 == MEMOP))
581 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
582 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
584 /* If both halves of dest are used in the src memory address,
585 compute the address into latehalf of dest. */
587 xops[0] = latehalf[0];
588 xops[1] = XEXP (operands[1], 0);
589 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
590 if( GET_MODE (operands[1]) == XFmode )
593 operands[1] = gen_rtx (MEM, XFmode, latehalf[0]);
594 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
595 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
599 operands[1] = gen_rtx (MEM, DImode, latehalf[0]);
600 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
604 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
606 /* Check for two regs used by both source and dest. */
607 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
608 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
611 /* JRV says this can't happen: */
612 if (addreg0 || addreg1)
615 /* Only the middle reg conflicts; simply put it last. */
616 output_asm_insn (singlemove_string (operands), operands);
617 output_asm_insn (singlemove_string (latehalf), latehalf);
618 output_asm_insn (singlemove_string (middlehalf), middlehalf);
621 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
622 /* If the low half of dest is mentioned in the source memory
623 address, the arrange to emit the move late half first. */
624 dest_overlapped_low = 1;
627 /* If one or both operands autodecrementing,
628 do the two words, high-numbered first. */
630 /* Likewise, the first move would clobber the source of the second one,
631 do them in the other order. This happens only for registers;
632 such overlap can't happen in memory unless the user explicitly
633 sets it up, and that is an undefined circumstance. */
636 if (optype0 == PUSHOP || optype1 == PUSHOP
637 || (optype0 == REGOP && optype1 == REGOP
638 && REGNO (operands[0]) == REGNO (latehalf[1]))
639 || dest_overlapped_low)
641 if (optype0 == PUSHOP || optype1 == PUSHOP
642 || (optype0 == REGOP && optype1 == REGOP
643 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
644 || REGNO (operands[0]) == REGNO (latehalf[1])))
645 || dest_overlapped_low)
647 /* Make any unoffsettable addresses point at high-numbered word. */
649 asm_add (size-4, addreg0);
651 asm_add (size-4, addreg1);
654 output_asm_insn (singlemove_string (latehalf), latehalf);
656 /* Undo the adds we just did. */
658 asm_add (-4, addreg0);
660 asm_add (-4, addreg1);
664 output_asm_insn (singlemove_string (middlehalf), middlehalf);
666 asm_add (-4, addreg0);
668 asm_add (-4, addreg1);
671 /* Do low-numbered word. */
672 return singlemove_string (operands);
675 /* Normal case: do the two words, low-numbered first. */
677 output_asm_insn (singlemove_string (operands), operands);
679 /* Do the middle one of the three words for long double */
683 asm_add (4, addreg0);
685 asm_add (4, addreg1);
687 output_asm_insn (singlemove_string (middlehalf), middlehalf);
690 /* Make any unoffsettable addresses point at high-numbered word. */
692 asm_add (4, addreg0);
694 asm_add (4, addreg1);
697 output_asm_insn (singlemove_string (latehalf), latehalf);
699 /* Undo the adds we just did. */
701 asm_add (4-size, addreg0);
703 asm_add (4-size, addreg1);
709 standard_80387_constant_p (x)
712 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
717 if (setjmp (handler))
720 set_float_handler (handler);
721 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
722 is0 = REAL_VALUES_EQUAL (d, dconst0);
723 is1 = REAL_VALUES_EQUAL (d, dconst1);
724 set_float_handler (NULL_PTR);
732 /* Note that on the 80387, other constants, such as pi,
733 are much slower to load as standard constants
734 than to load from doubles in memory! */
741 output_move_const_single (operands)
744 if (FP_REG_P (operands[0]))
746 int conval = standard_80387_constant_p (operands[1]);
754 if (GET_CODE (operands[1]) == CONST_DOUBLE)
756 REAL_VALUE_TYPE r; long l;
758 if (GET_MODE (operands[1]) == XFmode)
761 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
762 REAL_VALUE_TO_TARGET_SINGLE (r, l);
763 operands[1] = GEN_INT (l);
765 return singlemove_string (operands);
768 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
769 reference and a constant. */
772 symbolic_operand (op, mode)
774 enum machine_mode mode;
776 switch (GET_CODE (op))
783 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
784 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
785 && GET_CODE (XEXP (op, 1)) == CONST_INT);
791 /* Test for a valid operand for a call instruction.
792 Don't allow the arg pointer register or virtual regs
793 since they may change into reg + const, which the patterns
797 call_insn_operand (op, mode)
799 enum machine_mode mode;
801 if (GET_CODE (op) == MEM
802 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
803 /* This makes a difference for PIC. */
804 && general_operand (XEXP (op, 0), Pmode))
805 || (GET_CODE (XEXP (op, 0)) == REG
806 && XEXP (op, 0) != arg_pointer_rtx
807 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
808 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
813 /* Like call_insn_operand but allow (mem (symbol_ref ...))
817 expander_call_insn_operand (op, mode)
819 enum machine_mode mode;
821 if (GET_CODE (op) == MEM
822 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
823 || (GET_CODE (XEXP (op, 0)) == REG
824 && XEXP (op, 0) != arg_pointer_rtx
825 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
826 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
831 /* Returns 1 if OP contains a symbol reference */
834 symbolic_reference_mentioned_p (op)
840 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
843 fmt = GET_RTX_FORMAT (GET_CODE (op));
844 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
850 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
851 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
854 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
861 /* This function generates the assembly code for function entry.
862 FILE is an stdio stream to output the code to.
863 SIZE is an int: how many units of temporary storage to allocate. */
866 function_prologue (file, size)
873 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
874 || current_function_uses_const_pool);
876 xops[0] = stack_pointer_rtx;
877 xops[1] = frame_pointer_rtx;
878 xops[2] = GEN_INT (size);
879 if (frame_pointer_needed)
881 output_asm_insn ("push%L1 %1", xops);
882 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
886 output_asm_insn (AS2 (sub%L0,%2,%0), xops);
888 /* Note If use enter it is NOT reversed args.
889 This one is not reversed from intel!!
890 I think enter is slower. Also sdb doesn't like it.
891 But if you want it the code is:
893 xops[3] = const0_rtx;
894 output_asm_insn ("enter %2,%3", xops);
897 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
898 for (regno = limit - 1; regno >= 0; regno--)
899 if ((regs_ever_live[regno] && ! call_used_regs[regno])
900 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
902 xops[0] = gen_rtx (REG, SImode, regno);
903 output_asm_insn ("push%L0 %0", xops);
908 xops[0] = pic_offset_table_rtx;
909 xops[1] = (rtx) gen_label_rtx ();
911 output_asm_insn (AS1 (call,%P1), xops);
912 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1]));
913 output_asm_insn (AS1 (pop%L0,%0), xops);
914 output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
918 /* Return 1 if it is appropriate to emit `ret' instructions in the
919 body of a function. Do this only if the epilogue is simple, needing a
920 couple of insns. Prior to reloading, we can't tell how many registers
921 must be saved, so return 0 then.
923 If NON_SAVING_SETJMP is defined and true, then it is not possible
924 for the epilogue to be simple, so return 0. This is a special case
925 since NON_SAVING_SETJMP will not cause regs_ever_live to change until
926 final, but jump_optimize may need to know sooner if a `return' is OK. */
929 simple_386_epilogue ()
933 int reglimit = (frame_pointer_needed
934 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
935 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
936 || current_function_uses_const_pool);
938 #ifdef NON_SAVING_SETJMP
939 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
943 if (! reload_completed)
946 for (regno = reglimit - 1; regno >= 0; regno--)
947 if ((regs_ever_live[regno] && ! call_used_regs[regno])
948 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
951 return nregs == 0 || ! frame_pointer_needed;
955 /* This function generates the assembly code for function exit.
956 FILE is an stdio stream to output the code to.
957 SIZE is an int: how many units of temporary storage to deallocate. */
960 function_epilogue (file, size)
965 register int nregs, limit;
968 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
969 || current_function_uses_const_pool);
971 /* Compute the number of registers to pop */
973 limit = (frame_pointer_needed
974 ? FRAME_POINTER_REGNUM
975 : STACK_POINTER_REGNUM);
979 for (regno = limit - 1; regno >= 0; regno--)
980 if ((regs_ever_live[regno] && ! call_used_regs[regno])
981 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
984 /* sp is often unreliable so we must go off the frame pointer,
987 /* In reality, we may not care if sp is unreliable, because we can
988 restore the register relative to the frame pointer. In theory,
989 since each move is the same speed as a pop, and we don't need the
990 leal, this is faster. For now restore multiple registers the old
993 offset = -size - (nregs * UNITS_PER_WORD);
995 xops[2] = stack_pointer_rtx;
997 if (nregs > 1 || ! frame_pointer_needed)
999 if (frame_pointer_needed)
1001 xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset);
1002 output_asm_insn (AS2 (lea%L2,%0,%2), xops);
1005 for (regno = 0; regno < limit; regno++)
1006 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1007 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1009 xops[0] = gen_rtx (REG, SImode, regno);
1010 output_asm_insn ("pop%L0 %0", xops);
1014 for (regno = 0; regno < limit; regno++)
1015 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1016 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1018 xops[0] = gen_rtx (REG, SImode, regno);
1019 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
1020 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
1024 if (frame_pointer_needed)
1026 /* On i486, mov & pop is faster than "leave". */
1030 xops[0] = frame_pointer_rtx;
1031 output_asm_insn (AS2 (mov%L2,%0,%2), xops);
1032 output_asm_insn ("pop%L0 %0", xops);
1035 output_asm_insn ("leave", xops);
1039 /* If there is no frame pointer, we must still release the frame. */
1041 xops[0] = GEN_INT (size);
1042 output_asm_insn (AS2 (add%L2,%0,%2), xops);
1045 if (current_function_pops_args && current_function_args_size)
1047 xops[1] = GEN_INT (current_function_pops_args);
1049 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
1050 asked to pop more, pop return address, do explicit add, and jump
1051 indirectly to the caller. */
1053 if (current_function_pops_args >= 32768)
1055 /* ??? Which register to use here? */
1056 xops[0] = gen_rtx (REG, SImode, 2);
1057 output_asm_insn ("pop%L0 %0", xops);
1058 output_asm_insn (AS2 (add%L2,%1,%2), xops);
1059 output_asm_insn ("jmp %*%0", xops);
1062 output_asm_insn ("ret %1", xops);
1065 output_asm_insn ("ret", xops);
1069 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1070 that is a valid memory address for an instruction.
1071 The MODE argument is the machine mode for the MEM expression
1072 that wants to use this address.
1074 On x86, legitimate addresses are:
1075 base movl (base),reg
1076 displacement movl disp,reg
1077 base + displacement movl disp(base),reg
1078 index + base movl (base,index),reg
1079 (index + base) + displacement movl disp(base,index),reg
1080 index*scale movl (,index,scale),reg
1081 index*scale + disp movl disp(,index,scale),reg
1082 index*scale + base movl (base,index,scale),reg
1083 (index*scale + base) + disp movl disp(base,index,scale),reg
1085 In each case, scale can be 1, 2, 4, 8. */
1087 /* This is exactly the same as print_operand_addr, except that
1088 it recognizes addresses instead of printing them.
1090 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1091 convert common non-canonical forms to canonical form so that they will
1094 #define ADDR_INVALID(msg,insn) \
1096 if (TARGET_DEBUG_ADDR) \
1098 fprintf (stderr, msg); \
1104 legitimate_address_p (mode, addr, strict)
1105 enum machine_mode mode;
1109 rtx base = NULL_RTX;
1110 rtx indx = NULL_RTX;
1111 rtx scale = NULL_RTX;
1112 rtx disp = NULL_RTX;
1114 if (TARGET_DEBUG_ADDR)
1117 "\n==========\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
1118 GET_MODE_NAME (mode), strict);
1123 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
1124 base = addr; /* base reg */
1126 else if (GET_CODE (addr) == PLUS)
1128 rtx op0 = XEXP (addr, 0);
1129 rtx op1 = XEXP (addr, 1);
1130 enum rtx_code code0 = GET_CODE (op0);
1131 enum rtx_code code1 = GET_CODE (op1);
1133 if (code0 == REG || code0 == SUBREG)
1135 if (code1 == REG || code1 == SUBREG)
1137 indx = op0; /* index + base */
1143 base = op0; /* base + displacement */
1148 else if (code0 == MULT)
1150 indx = XEXP (op0, 0);
1151 scale = XEXP (op0, 1);
1153 if (code1 == REG || code1 == SUBREG)
1154 base = op1; /* index*scale + base */
1157 disp = op1; /* index*scale + disp */
1160 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
1162 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */
1163 scale = XEXP (XEXP (op0, 0), 1);
1164 base = XEXP (op0, 1);
1168 else if (code0 == PLUS)
1170 indx = XEXP (op0, 0); /* index + base + disp */
1171 base = XEXP (op0, 1);
1177 ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
1182 else if (GET_CODE (addr) == MULT)
1184 indx = XEXP (addr, 0); /* index*scale */
1185 scale = XEXP (addr, 1);
1189 disp = addr; /* displacement */
1191 /* Allow arg pointer and stack pointer as index if there is not scaling */
1192 if (base && indx && !scale
1193 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
1200 /* Validate base register */
1203 if (GET_CODE (base) == SUBREG)
1205 if (GET_CODE (SUBREG_REG (base)) != REG || SUBREG_WORD (base) != 0)
1207 ADDR_INVALID ("Base SUBREG is not of a REG.\n", base);
1211 base = SUBREG_REG (base);
1214 if (GET_CODE (base) != REG
1215 || ( strict && !REG_OK_FOR_BASE_STRICT_P (base))
1216 || (!strict && !REG_OK_FOR_BASE_NONSTRICT_P (base)))
1218 ADDR_INVALID ("Base is not valid.\n", base);
1223 /* Validate index register */
1226 if (GET_CODE (indx) == SUBREG)
1228 if (GET_CODE (SUBREG_REG (indx)) != REG || SUBREG_WORD (indx) != 0)
1230 ADDR_INVALID ("Index SUBREG is not of a REG.", indx);
1234 indx = SUBREG_REG (indx);
1237 if (GET_CODE (indx) != REG
1238 || ( strict && !REG_OK_FOR_INDEX_STRICT_P (indx))
1239 || (!strict && !REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
1241 ADDR_INVALID ("Index is not valid.\n", indx);
1246 abort (); /* scale w/o index illegal */
1248 /* Validate scale factor */
1251 HOST_WIDE_INT value;
1253 if (GET_CODE (scale) != CONST_INT)
1255 ADDR_INVALID ("Scale is not valid.\n", scale);
1259 value = INTVAL (scale);
1260 if (value != 1 && value != 2 && value != 4 && value != 8)
1262 ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
1267 /* Validate displacement */
1270 if (!CONSTANT_ADDRESS_P (disp))
1272 ADDR_INVALID ("Displacement is not valid.\n", disp);
1276 if (GET_CODE (disp) == CONST_DOUBLE)
1278 ADDR_INVALID ("Displacement is a const_double.\n", disp);
1282 if (flag_pic && SYMBOLIC_CONST (disp) && base != pic_offset_table_rtx
1283 && (indx != pic_offset_table_rtx || scale != NULL_RTX))
1285 ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp);
1289 if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp)
1290 && (base != NULL_RTX || indx != NULL_RTX))
1292 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", disp);
1297 if (TARGET_DEBUG_ADDR)
1298 fprintf (stderr, "Address is valid.\n");
1300 /* Everything looks valid, return true */
1305 /* Return a legitimate reference for ORIG (an address) using the
1306 register REG. If REG is 0, a new pseudo is generated.
1308 There are three types of references that must be handled:
1310 1. Global data references must load the address from the GOT, via
1311 the PIC reg. An insn is emitted to do this load, and the reg is
1314 2. Static data references must compute the address as an offset
1315 from the GOT, whose base is in the PIC reg. An insn is emitted to
1316 compute the address into a reg, and the reg is returned. Static
1317 data objects have SYMBOL_REF_FLAG set to differentiate them from
1318 global data objects.
1320 3. Constant pool addresses must be handled special. They are
1321 considered legitimate addresses, but only if not used with regs.
1322 When printed, the output routines know to print the reference with the
1323 PIC reg, even though the PIC reg doesn't appear in the RTL.
1325 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
1326 reg also appears in the address (except for constant pool references,
1329 "switch" statements also require special handling when generating
1330 PIC code. See comments by the `casesi' insn in i386.md for details. */
1333 legitimize_pic_address (orig, reg)
1340 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
1342 if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr))
1347 reg = gen_reg_rtx (Pmode);
1349 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr))
1350 new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig);
1352 new = gen_rtx (MEM, Pmode,
1353 gen_rtx (PLUS, Pmode,
1354 pic_offset_table_rtx, orig));
1356 emit_move_insn (reg, new);
1358 current_function_uses_pic_offset_table = 1;
1361 else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
1365 if (GET_CODE (addr) == CONST)
1367 addr = XEXP (addr, 0);
1368 if (GET_CODE (addr) != PLUS)
1372 if (XEXP (addr, 0) == pic_offset_table_rtx)
1376 reg = gen_reg_rtx (Pmode);
1378 base = legitimize_pic_address (XEXP (addr, 0), reg);
1379 addr = legitimize_pic_address (XEXP (addr, 1),
1380 base == reg ? NULL_RTX : reg);
1382 if (GET_CODE (addr) == CONST_INT)
1383 return plus_constant (base, INTVAL (addr));
1385 if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
1387 base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0));
1388 addr = XEXP (addr, 1);
1390 return gen_rtx (PLUS, Pmode, base, addr);
1396 /* Emit insns to move operands[1] into operands[0]. */
1399 emit_pic_move (operands, mode)
1401 enum machine_mode mode;
1403 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
1405 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
1406 operands[1] = (rtx) force_reg (SImode, operands[1]);
1408 operands[1] = legitimize_pic_address (operands[1], temp);
1412 /* Try machine-dependent ways of modifying an illegitimate address
1413 to be legitimate. If we find one, return the new, valid address.
1414 This macro is used in only one place: `memory_address' in explow.c.
1416 OLDX is the address as it was before break_out_memory_refs was called.
1417 In some cases it is useful to look at this to decide what needs to be done.
1419 MODE and WIN are passed so that this macro can use
1420 GO_IF_LEGITIMATE_ADDRESS.
1422 It is always safe for this macro to do nothing. It exists to recognize
1423 opportunities to optimize the output.
1425 For the 80386, we handle X+REG by loading X into a register R and
1426 using R+REG. R will go in a general reg and indexing will be used.
1427 However, if REG is a broken-out memory address or multiplication,
1428 nothing needs to be done because REG can certainly go in a general reg.
1430 When -fpic is used, special handling is needed for symbolic references.
1431 See comments by legitimize_pic_address in i386.c for details. */
1434 legitimize_address (x, oldx, mode)
1437 enum machine_mode mode;
1442 if (TARGET_DEBUG_ADDR)
1444 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", GET_MODE_NAME (mode));
1448 if (flag_pic && SYMBOLIC_CONST (x))
1449 return legitimize_pic_address (x, 0);
1451 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
1452 if (GET_CODE (x) == ASHIFT
1453 && GET_CODE (XEXP (x, 1)) == CONST_INT
1454 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
1457 x = gen_rtx (MULT, Pmode,
1458 force_reg (Pmode, XEXP (x, 0)),
1459 GEN_INT (1 << log));
1462 if (GET_CODE (x) == PLUS)
1464 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
1465 if (GET_CODE (XEXP (x, 0)) == ASHIFT
1466 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1467 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
1470 XEXP (x, 0) = gen_rtx (MULT, Pmode,
1471 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
1472 GEN_INT (1 << log));
1475 if (GET_CODE (XEXP (x, 1)) == ASHIFT
1476 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1477 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
1480 XEXP (x, 1) = gen_rtx (MULT, Pmode,
1481 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
1482 GEN_INT (1 << log));
1485 /* Put multiply first if it isn't already */
1486 if (GET_CODE (XEXP (x, 1)) == MULT)
1488 rtx tmp = XEXP (x, 0);
1489 XEXP (x, 0) = XEXP (x, 1);
1494 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1495 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1496 created by virtual register instantiation, register elimination, and
1497 similar optimizations. */
1498 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
1501 x = gen_rtx (PLUS, Pmode,
1502 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
1503 XEXP (XEXP (x, 1), 1));
1506 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1507 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1508 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
1509 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1510 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
1511 && CONSTANT_P (XEXP (x, 1)))
1513 rtx constant, other;
1515 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1517 constant = XEXP (x, 1);
1518 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
1520 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
1522 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
1523 other = XEXP (x, 1);
1531 x = gen_rtx (PLUS, Pmode,
1532 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
1533 XEXP (XEXP (XEXP (x, 0), 1), 0)),
1534 plus_constant (other, INTVAL (constant)));
1538 if (changed && legitimate_address_p (mode, x, FALSE))
1541 if (GET_CODE (XEXP (x, 0)) == MULT)
1544 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
1547 if (GET_CODE (XEXP (x, 1)) == MULT)
1550 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
1554 && GET_CODE (XEXP (x, 1)) == REG
1555 && GET_CODE (XEXP (x, 0)) == REG)
1558 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
1561 x = legitimize_pic_address (x, 0);
1564 if (changed && legitimate_address_p (mode, x, FALSE))
1567 if (GET_CODE (XEXP (x, 0)) == REG)
1569 register rtx temp = gen_reg_rtx (Pmode);
1570 register rtx val = force_operand (XEXP (x, 1), temp);
1572 emit_move_insn (temp, val);
1578 else if (GET_CODE (XEXP (x, 1)) == REG)
1580 register rtx temp = gen_reg_rtx (Pmode);
1581 register rtx val = force_operand (XEXP (x, 0), temp);
1583 emit_move_insn (temp, val);
1594 /* Print an integer constant expression in assembler syntax. Addition
1595 and subtraction are the only arithmetic that may appear in these
1596 expressions. FILE is the stdio stream to write to, X is the rtx, and
1597 CODE is the operand print code from the output string. */
1600 output_pic_addr_const (file, x, code)
1607 switch (GET_CODE (x))
1618 if (GET_CODE (x) == SYMBOL_REF)
1619 assemble_name (file, XSTR (x, 0));
1622 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
1623 CODE_LABEL_NUMBER (XEXP (x, 0)));
1624 assemble_name (asm_out_file, buf);
1627 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
1628 fprintf (file, "@GOTOFF(%%ebx)");
1629 else if (code == 'P')
1630 fprintf (file, "@PLT");
1631 else if (GET_CODE (x) == LABEL_REF || ! SYMBOL_REF_FLAG (x))
1632 fprintf (file, "@GOT");
1634 fprintf (file, "@GOTOFF");
1639 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
1640 assemble_name (asm_out_file, buf);
1644 fprintf (file, "%d", INTVAL (x));
1648 /* This used to output parentheses around the expression,
1649 but that does not work on the 386 (either ATT or BSD assembler). */
1650 output_pic_addr_const (file, XEXP (x, 0), code);
1654 if (GET_MODE (x) == VOIDmode)
1656 /* We can use %d if the number is <32 bits and positive. */
1657 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
1658 fprintf (file, "0x%x%08x",
1659 CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x));
1661 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
1664 /* We can't handle floating point constants;
1665 PRINT_OPERAND must handle them. */
1666 output_operand_lossage ("floating constant misused");
1670 /* Some assemblers need integer constants to appear last (eg masm). */
1671 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
1673 output_pic_addr_const (file, XEXP (x, 1), code);
1674 if (INTVAL (XEXP (x, 0)) >= 0)
1675 fprintf (file, "+");
1676 output_pic_addr_const (file, XEXP (x, 0), code);
1680 output_pic_addr_const (file, XEXP (x, 0), code);
1681 if (INTVAL (XEXP (x, 1)) >= 0)
1682 fprintf (file, "+");
1683 output_pic_addr_const (file, XEXP (x, 1), code);
1688 output_pic_addr_const (file, XEXP (x, 0), code);
1689 fprintf (file, "-");
1690 output_pic_addr_const (file, XEXP (x, 1), code);
1694 output_operand_lossage ("invalid expression as operand");
1699 f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
1700 D,L,W,B,Q,S -- print the opcode suffix for specified size of operand.
1701 R -- print the prefix for register names.
1702 z -- print the opcode suffix for the size of the current operand.
1703 * -- print a star (in certain assembler syntax)
1704 w -- print the operand as if it's a "word" (HImode) even if it isn't.
1705 c -- don't print special prefixes before constant operands.
1709 print_operand (file, x, code)
1724 PUT_OP_SIZE (code, 'l', file);
1728 PUT_OP_SIZE (code, 'w', file);
1732 PUT_OP_SIZE (code, 'b', file);
1736 PUT_OP_SIZE (code, 'l', file);
1740 PUT_OP_SIZE (code, 's', file);
1744 PUT_OP_SIZE (code, 't', file);
1748 /* 387 opcodes don't get size suffixes if the operands are
1751 if (STACK_REG_P (x))
1754 /* this is the size of op from size of operand */
1755 switch (GET_MODE_SIZE (GET_MODE (x)))
1758 PUT_OP_SIZE ('B', 'b', file);
1762 PUT_OP_SIZE ('W', 'w', file);
1766 if (GET_MODE (x) == SFmode)
1768 PUT_OP_SIZE ('S', 's', file);
1772 PUT_OP_SIZE ('L', 'l', file);
1776 PUT_OP_SIZE ('T', 't', file);
1780 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
1782 #ifdef GAS_MNEMONICS
1783 PUT_OP_SIZE ('Q', 'q', file);
1786 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
1790 PUT_OP_SIZE ('Q', 'l', file);
1806 sprintf (str, "invalid operand code `%c'", code);
1807 output_operand_lossage (str);
1811 if (GET_CODE (x) == REG)
1813 PRINT_REG (x, code, file);
1815 else if (GET_CODE (x) == MEM)
1817 PRINT_PTR (x, file);
1818 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
1821 output_pic_addr_const (file, XEXP (x, 0), code);
1823 output_addr_const (file, XEXP (x, 0));
1826 output_address (XEXP (x, 0));
1828 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
1830 REAL_VALUE_TYPE r; long l;
1831 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1832 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1833 PRINT_IMMED_PREFIX (file);
1834 fprintf (file, "0x%x", l);
1836 /* These float cases don't actually occur as immediate operands. */
1837 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
1839 REAL_VALUE_TYPE r; char dstr[30];
1840 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1841 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
1842 fprintf (file, "%s", dstr);
1844 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
1846 REAL_VALUE_TYPE r; char dstr[30];
1847 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1848 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
1849 fprintf (file, "%s", dstr);
1855 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
1856 PRINT_IMMED_PREFIX (file);
1857 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
1858 || GET_CODE (x) == LABEL_REF)
1859 PRINT_OFFSET_PREFIX (file);
1862 output_pic_addr_const (file, x, code);
1864 output_addr_const (file, x);
1868 /* Print a memory operand whose address is ADDR. */
1871 print_operand_address (file, addr)
1875 register rtx reg1, reg2, breg, ireg;
1878 switch (GET_CODE (addr))
1882 fprintf (file, "%se", RP);
1883 fputs (hi_reg_name[REGNO (addr)], file);
1893 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
1895 offset = XEXP (addr, 0);
1896 addr = XEXP (addr, 1);
1898 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
1900 offset = XEXP (addr, 1);
1901 addr = XEXP (addr, 0);
1903 if (GET_CODE (addr) != PLUS) ;
1904 else if (GET_CODE (XEXP (addr, 0)) == MULT)
1906 reg1 = XEXP (addr, 0);
1907 addr = XEXP (addr, 1);
1909 else if (GET_CODE (XEXP (addr, 1)) == MULT)
1911 reg1 = XEXP (addr, 1);
1912 addr = XEXP (addr, 0);
1914 else if (GET_CODE (XEXP (addr, 0)) == REG)
1916 reg1 = XEXP (addr, 0);
1917 addr = XEXP (addr, 1);
1919 else if (GET_CODE (XEXP (addr, 1)) == REG)
1921 reg1 = XEXP (addr, 1);
1922 addr = XEXP (addr, 0);
1924 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
1926 if (reg1 == 0) reg1 = addr;
1932 if (addr != 0) abort ();
1935 if ((reg1 && GET_CODE (reg1) == MULT)
1936 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
1941 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
1947 if (ireg != 0 || breg != 0)
1953 if (GET_CODE (addr) == LABEL_REF)
1954 output_asm_label (addr);
1958 output_pic_addr_const (file, addr, 0);
1960 output_addr_const (file, addr);
1964 if (ireg != 0 && GET_CODE (ireg) == MULT)
1966 scale = INTVAL (XEXP (ireg, 1));
1967 ireg = XEXP (ireg, 0);
1970 /* The stack pointer can only appear as a base register,
1971 never an index register, so exchange the regs if it is wrong. */
1973 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
1982 /* output breg+ireg*scale */
1983 PRINT_B_I_S (breg, ireg, scale, file);
1990 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
1992 scale = INTVAL (XEXP (addr, 0));
1993 ireg = XEXP (addr, 1);
1997 scale = INTVAL (XEXP (addr, 1));
1998 ireg = XEXP (addr, 0);
2000 output_addr_const (file, const0_rtx);
2001 PRINT_B_I_S ((rtx) 0, ireg, scale, file);
2006 if (GET_CODE (addr) == CONST_INT
2007 && INTVAL (addr) < 0x8000
2008 && INTVAL (addr) >= -0x8000)
2009 fprintf (file, "%d", INTVAL (addr));
2013 output_pic_addr_const (file, addr, 0);
2015 output_addr_const (file, addr);
2020 /* Set the cc_status for the results of an insn whose pattern is EXP.
2021 On the 80386, we assume that only test and compare insns, as well
2022 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT,
2023 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
2024 Also, we assume that jumps, moves and sCOND don't affect the condition
2025 codes. All else clobbers the condition codes, by assumption.
2027 We assume that ALL integer add, minus, etc. instructions effect the
2028 condition codes. This MUST be consistent with i386.md.
2030 We don't record any float test or compare - the redundant test &
2031 compare check in final.c does not handle stack-like regs correctly. */
2034 notice_update_cc (exp)
2037 if (GET_CODE (exp) == SET)
2039 /* Jumps do not alter the cc's. */
2040 if (SET_DEST (exp) == pc_rtx)
2042 /* Moving register or memory into a register:
2043 it doesn't alter the cc's, but it might invalidate
2044 the RTX's which we remember the cc's came from.
2045 (Note that moving a constant 0 or 1 MAY set the cc's). */
2046 if (REG_P (SET_DEST (exp))
2047 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
2048 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
2050 if (cc_status.value1
2051 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
2052 cc_status.value1 = 0;
2053 if (cc_status.value2
2054 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
2055 cc_status.value2 = 0;
2058 /* Moving register into memory doesn't alter the cc's.
2059 It may invalidate the RTX's which we remember the cc's came from. */
2060 if (GET_CODE (SET_DEST (exp)) == MEM
2061 && (REG_P (SET_SRC (exp))
2062 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
2064 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM)
2065 cc_status.value1 = 0;
2066 if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM)
2067 cc_status.value2 = 0;
2070 /* Function calls clobber the cc's. */
2071 else if (GET_CODE (SET_SRC (exp)) == CALL)
2076 /* Tests and compares set the cc's in predictable ways. */
2077 else if (SET_DEST (exp) == cc0_rtx)
2080 cc_status.value1 = SET_SRC (exp);
2083 /* Certain instructions effect the condition codes. */
2084 else if (GET_MODE (SET_SRC (exp)) == SImode
2085 || GET_MODE (SET_SRC (exp)) == HImode
2086 || GET_MODE (SET_SRC (exp)) == QImode)
2087 switch (GET_CODE (SET_SRC (exp)))
2089 case ASHIFTRT: case LSHIFTRT:
2091 /* Shifts on the 386 don't set the condition codes if the
2092 shift count is zero. */
2093 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
2098 /* We assume that the CONST_INT is non-zero (this rtx would
2099 have been deleted if it were zero. */
2101 case PLUS: case MINUS: case NEG:
2102 case AND: case IOR: case XOR:
2103 cc_status.flags = CC_NO_OVERFLOW;
2104 cc_status.value1 = SET_SRC (exp);
2105 cc_status.value2 = SET_DEST (exp);
2116 else if (GET_CODE (exp) == PARALLEL
2117 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
2119 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
2121 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
2124 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
2125 cc_status.flags |= CC_IN_80387;
2127 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
2138 /* Split one or more DImode RTL references into pairs of SImode
2139 references. The RTL can be REG, offsettable MEM, integer constant, or
2140 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2141 split and "num" is its length. lo_half and hi_half are output arrays
2142 that parallel "operands". */
2145 split_di (operands, num, lo_half, hi_half)
2148 rtx lo_half[], hi_half[];
2152 if (GET_CODE (operands[num]) == REG)
2154 lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]));
2155 hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1);
2157 else if (CONSTANT_P (operands[num]))
2159 split_double (operands[num], &lo_half[num], &hi_half[num]);
2161 else if (offsettable_memref_p (operands[num]))
2163 lo_half[num] = operands[num];
2164 hi_half[num] = adj_offsettable_operand (operands[num], 4);
2171 /* Return 1 if this is a valid binary operation on a 387.
2172 OP is the expression matched, and MODE is its mode. */
2175 binary_387_op (op, mode)
2177 enum machine_mode mode;
2179 if (mode != VOIDmode && mode != GET_MODE (op))
2182 switch (GET_CODE (op))
2188 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
2196 /* Return 1 if this is a valid shift or rotate operation on a 386.
2197 OP is the expression matched, and MODE is its mode. */
2202 enum machine_mode mode;
2204 rtx operand = XEXP (op, 0);
2206 if (mode != VOIDmode && mode != GET_MODE (op))
2209 if (GET_MODE (operand) != GET_MODE (op)
2210 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
2213 return (GET_CODE (op) == ASHIFT
2214 || GET_CODE (op) == ASHIFTRT
2215 || GET_CODE (op) == LSHIFTRT
2216 || GET_CODE (op) == ROTATE
2217 || GET_CODE (op) == ROTATERT);
2220 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
2221 MODE is not used. */
2224 VOIDmode_compare_op (op, mode)
2226 enum machine_mode mode;
2228 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
2231 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
2232 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
2233 is the expression of the binary operation. The output may either be
2234 emitted here, or returned to the caller, like all output_* functions.
2236 There is no guarantee that the operands are the same mode, as they
2237 might be within FLOAT or FLOAT_EXTEND expressions. */
2240 output_387_binary_op (insn, operands)
2246 static char buf[100];
2248 switch (GET_CODE (operands[3]))
2251 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2252 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
2259 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2260 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
2267 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2268 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
2275 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2276 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
2286 strcpy (buf, base_op);
2288 switch (GET_CODE (operands[3]))
2292 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
2295 operands[2] = operands[1];
2299 if (GET_CODE (operands[2]) == MEM)
2300 return strcat (buf, AS1 (%z2,%2));
2302 if (NON_STACK_REG_P (operands[1]))
2304 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
2307 else if (NON_STACK_REG_P (operands[2]))
2309 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
2313 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
2314 return strcat (buf, AS2 (p,%2,%0));
2316 if (STACK_TOP_P (operands[0]))
2317 return strcat (buf, AS2 (,%y2,%0));
2319 return strcat (buf, AS2 (,%2,%0));
2323 if (GET_CODE (operands[1]) == MEM)
2324 return strcat (buf, AS1 (r%z1,%1));
2326 if (GET_CODE (operands[2]) == MEM)
2327 return strcat (buf, AS1 (%z2,%2));
2329 if (NON_STACK_REG_P (operands[1]))
2331 output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
2334 else if (NON_STACK_REG_P (operands[2]))
2336 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
2340 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
2343 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
2344 return strcat (buf, AS2 (rp,%2,%0));
2346 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2347 return strcat (buf, AS2 (p,%1,%0));
2349 if (STACK_TOP_P (operands[0]))
2351 if (STACK_TOP_P (operands[1]))
2352 return strcat (buf, AS2 (,%y2,%0));
2354 return strcat (buf, AS2 (r,%y1,%0));
2356 else if (STACK_TOP_P (operands[1]))
2357 return strcat (buf, AS2 (,%1,%0));
2359 return strcat (buf, AS2 (r,%2,%0));
2366 /* Output code for INSN to convert a float to a signed int. OPERANDS
2367 are the insn operands. The output may be SFmode or DFmode and the
2368 input operand may be SImode or DImode. As a special case, make sure
2369 that the 387 stack top dies if the output mode is DImode, because the
2370 hardware requires this. */
2373 output_fix_trunc (insn, operands)
2377 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2380 if (! STACK_TOP_P (operands[1]) ||
2381 (GET_MODE (operands[0]) == DImode && ! stack_top_dies))
2384 xops[0] = GEN_INT (12);
2385 xops[1] = operands[4];
2387 output_asm_insn (AS1 (fnstc%W2,%2), operands);
2388 output_asm_insn (AS2 (mov%L2,%2,%4), operands);
2389 output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
2390 output_asm_insn (AS2 (mov%L4,%4,%3), operands);
2391 output_asm_insn (AS1 (fldc%W3,%3), operands);
2393 if (NON_STACK_REG_P (operands[0]))
2394 output_to_reg (operands[0], stack_top_dies);
2395 else if (GET_CODE (operands[0]) == MEM)
2398 output_asm_insn (AS1 (fistp%z0,%0), operands);
2400 output_asm_insn (AS1 (fist%z0,%0), operands);
2405 return AS1 (fldc%W2,%2);
2408 /* Output code for INSN to compare OPERANDS. The two operands might
2409 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
2410 expression. If the compare is in mode CCFPEQmode, use an opcode that
2411 will not fault if a qNaN is present. */
2414 output_float_compare (insn, operands)
2419 rtx body = XVECEXP (PATTERN (insn), 0, 0);
2420 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
2422 if (! STACK_TOP_P (operands[0]))
2425 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
2427 if (STACK_REG_P (operands[1])
2429 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
2430 && REGNO (operands[1]) != FIRST_STACK_REG)
2432 /* If both the top of the 387 stack dies, and the other operand
2433 is also a stack register that dies, then this must be a
2434 `fcompp' float compare */
2436 if (unordered_compare)
2437 output_asm_insn ("fucompp", operands);
2439 output_asm_insn ("fcompp", operands);
2443 static char buf[100];
2445 /* Decide if this is the integer or float compare opcode, or the
2446 unordered float compare. */
2448 if (unordered_compare)
2449 strcpy (buf, "fucom");
2450 else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
2451 strcpy (buf, "fcom");
2453 strcpy (buf, "ficom");
2455 /* Modify the opcode if the 387 stack is to be popped. */
2460 if (NON_STACK_REG_P (operands[1]))
2461 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
2463 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
2466 /* Now retrieve the condition code. */
2468 return output_fp_cc0_set (insn);
2471 /* Output opcodes to transfer the results of FP compare or test INSN
2472 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
2473 result of the compare or test is unordered, no comparison operator
2474 succeeds except NE. Return an output template, if any. */
2477 output_fp_cc0_set (insn)
2481 rtx unordered_label;
2485 xops[0] = gen_rtx (REG, HImode, 0);
2486 output_asm_insn (AS1 (fnsts%W0,%0), xops);
2488 if (! TARGET_IEEE_FP)
2491 next = next_cc0_user (insn);
2492 if (next == NULL_RTX)
2495 if (GET_CODE (next) == JUMP_INSN
2496 && GET_CODE (PATTERN (next)) == SET
2497 && SET_DEST (PATTERN (next)) == pc_rtx
2498 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
2500 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
2502 else if (GET_CODE (PATTERN (next)) == SET)
2504 code = GET_CODE (SET_SRC (PATTERN (next)));
2509 xops[0] = gen_rtx (REG, QImode, 0);
2514 xops[1] = GEN_INT (0x45);
2515 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2520 xops[1] = GEN_INT (0x45);
2521 xops[2] = GEN_INT (0x01);
2522 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2523 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
2528 xops[1] = GEN_INT (0x05);
2529 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2534 xops[1] = GEN_INT (0x45);
2535 xops[2] = GEN_INT (0x40);
2536 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2537 output_asm_insn (AS1 (dec%B0,%h0), xops);
2538 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
2543 xops[1] = GEN_INT (0x45);
2544 xops[2] = GEN_INT (0x40);
2545 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2546 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
2551 xops[1] = GEN_INT (0x44);
2552 xops[2] = GEN_INT (0x40);
2553 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
2554 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
2568 #define MAX_386_STACK_LOCALS 2
2570 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
2572 /* Define the structure for the machine field in struct function. */
2573 struct machine_function
2575 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
2578 /* Functions to save and restore i386_stack_locals.
2579 These will be called, via pointer variables,
2580 from push_function_context and pop_function_context. */
2583 save_386_machine_status (p)
2586 p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals);
2587 bcopy (i386_stack_locals, p->machine->i386_stack_locals,
2588 sizeof i386_stack_locals);
2592 restore_386_machine_status (p)
2595 bcopy (p->machine->i386_stack_locals, i386_stack_locals,
2596 sizeof i386_stack_locals);
2600 /* Clear stack slot assignments remembered from previous functions.
2601 This is called from INIT_EXPANDERS once before RTL is emitted for each
2605 clear_386_stack_locals ()
2607 enum machine_mode mode;
2610 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
2611 mode = (enum machine_mode) ((int) mode + 1))
2612 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
2613 i386_stack_locals[(int) mode][n] = NULL_RTX;
2615 /* Arrange to save and restore i386_stack_locals around nested functions. */
2616 save_machine_status = save_386_machine_status;
2617 restore_machine_status = restore_386_machine_status;
2620 /* Return a MEM corresponding to a stack slot with mode MODE.
2621 Allocate a new slot if necessary.
2623 The RTL for a function can have several slots available: N is
2624 which slot to use. */
2627 assign_386_stack_local (mode, n)
2628 enum machine_mode mode;
2631 if (n < 0 || n >= MAX_386_STACK_LOCALS)
2634 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
2635 i386_stack_locals[(int) mode][n]
2636 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
2638 return i386_stack_locals[(int) mode][n];