1 /* Subroutines for insn-output.c for Intel X86.
2 Copyright (C) 1988, 92, 94-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
52 #ifdef EXTRA_CONSTRAINT
53 /* If EXTRA_CONSTRAINT is defined, then the 'S'
54 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
55 asm statements that need 'S' for class SIREG will break. */
56 error EXTRA_CONSTRAINT conflicts with S constraint letter
57 /* The previous line used to be #error, but some compilers barf
58 even if the conditional was untrue. */
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT -1
65 /* Type of an operand for ix86_{binary,unary}_operator_ok */
73 /* Processor costs (relative to an add) */
74 struct processor_costs i386_cost = { /* 386 specific costs */
75 1, /* cost of an add instruction */
76 1, /* cost of a lea instruction */
77 3, /* variable shift costs */
78 2, /* constant shift costs */
79 6, /* cost of starting a multiply */
80 1, /* cost of multiply per each bit set */
81 23 /* cost of a divide/mod */
84 struct processor_costs i486_cost = { /* 486 specific costs */
85 1, /* cost of an add instruction */
86 1, /* cost of a lea instruction */
87 3, /* variable shift costs */
88 2, /* constant shift costs */
89 12, /* cost of starting a multiply */
90 1, /* cost of multiply per each bit set */
91 40 /* cost of a divide/mod */
94 struct processor_costs pentium_cost = {
95 1, /* cost of an add instruction */
96 1, /* cost of a lea instruction */
97 4, /* variable shift costs */
98 1, /* constant shift costs */
99 11, /* cost of starting a multiply */
100 0, /* cost of multiply per each bit set */
101 25 /* cost of a divide/mod */
104 struct processor_costs pentiumpro_cost = {
105 1, /* cost of an add instruction */
106 1, /* cost of a lea instruction */
107 3, /* variable shift costs */
108 1, /* constant shift costs */
109 4, /* cost of starting a multiply */
110 0, /* cost of multiply per each bit set */
111 17 /* cost of a divide/mod */
114 struct processor_costs *ix86_cost = &pentium_cost;
116 #define AT_BP(mode) (gen_rtx_MEM ((mode), frame_pointer_rtx))
118 extern FILE *asm_out_file;
119 extern char *strcat ();
121 static void ix86_epilogue PROTO((int));
122 static void ix86_prologue PROTO((int));
124 char *singlemove_string ();
125 char *output_move_const_single ();
126 char *output_fp_cc0_set ();
128 char *hi_reg_name[] = HI_REGISTER_NAMES;
129 char *qi_reg_name[] = QI_REGISTER_NAMES;
130 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
132 /* Array of the smallest class containing reg number REGNO, indexed by
133 REGNO. Used by REGNO_REG_CLASS in i386.h. */
135 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
138 AREG, DREG, CREG, BREG,
140 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
142 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
143 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
148 /* Test and compare insns in i386.md store the information needed to
149 generate branch and scc insns here. */
151 struct rtx_def *i386_compare_op0 = NULL_RTX;
152 struct rtx_def *i386_compare_op1 = NULL_RTX;
153 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
155 /* which cpu are we scheduling for */
156 enum processor_type ix86_cpu;
158 /* which instruction set architecture to use. */
161 /* Strings to hold which cpu and instruction set architecture to use. */
162 char *ix86_cpu_string; /* for -mcpu=<xxx> */
163 char *ix86_arch_string; /* for -march=<xxx> */
165 /* Register allocation order */
166 char *i386_reg_alloc_order;
167 static char regs_allocated[FIRST_PSEUDO_REGISTER];
169 /* # of registers to use to pass arguments. */
170 char *i386_regparm_string;
172 /* i386_regparm_string as a number */
175 /* Alignment to use for loops and jumps: */
177 /* Power of two alignment for loops. */
178 char *i386_align_loops_string;
180 /* Power of two alignment for non-loop jumps. */
181 char *i386_align_jumps_string;
183 /* Values 1-5: see jump.c */
184 int i386_branch_cost;
185 char *i386_branch_cost_string;
187 /* Power of two alignment for functions. */
188 int i386_align_funcs;
189 char *i386_align_funcs_string;
191 /* Power of two alignment for loops. */
192 int i386_align_loops;
194 /* Power of two alignment for non-loop jumps. */
195 int i386_align_jumps;
197 /* Sometimes certain combinations of command options do not make
198 sense on a particular target machine. You can define a macro
199 `OVERRIDE_OPTIONS' to take account of this. This macro, if
200 defined, is executed once just after all the command options have
203 Don't use this macro to turn on various extra optimizations for
204 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
214 char *name; /* Canonical processor name. */
215 enum processor_type processor; /* Processor type enum value. */
216 struct processor_costs *cost; /* Processor costs */
217 int target_enable; /* Target flags to enable. */
218 int target_disable; /* Target flags to disable. */
219 } processor_target_table[]
220 = {{PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0},
221 {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0},
222 {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
223 {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
224 {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentiumpro_cost,
226 {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO,
227 &pentiumpro_cost, 0, 0}};
229 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
231 #ifdef SUBTARGET_OVERRIDE_OPTIONS
232 SUBTARGET_OVERRIDE_OPTIONS;
235 /* Validate registers in register allocation order. */
236 if (i386_reg_alloc_order)
238 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
244 case 'a': regno = 0; break;
245 case 'd': regno = 1; break;
246 case 'c': regno = 2; break;
247 case 'b': regno = 3; break;
248 case 'S': regno = 4; break;
249 case 'D': regno = 5; break;
250 case 'B': regno = 6; break;
252 default: fatal ("Register '%c' is unknown", ch);
255 if (regs_allocated[regno])
256 fatal ("Register '%c' already specified in allocation order", ch);
258 regs_allocated[regno] = 1;
262 if (ix86_arch_string == 0)
264 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
265 if (ix86_cpu_string == 0)
266 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
269 for (i = 0; i < ptt_size; i++)
270 if (! strcmp (ix86_arch_string, processor_target_table[i].name))
272 ix86_arch = processor_target_table[i].processor;
273 if (ix86_cpu_string == 0)
274 ix86_cpu_string = processor_target_table[i].name;
280 error ("bad value (%s) for -march= switch", ix86_arch_string);
281 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
282 ix86_arch = PROCESSOR_DEFAULT;
285 if (ix86_cpu_string == 0)
286 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
288 for (j = 0; j < ptt_size; j++)
289 if (! strcmp (ix86_cpu_string, processor_target_table[j].name))
291 ix86_cpu = processor_target_table[j].processor;
292 ix86_cost = processor_target_table[j].cost;
293 if (i > j && (int) ix86_arch >= (int) PROCESSOR_PENTIUMPRO)
294 error ("-mcpu=%s does not support -march=%s",
295 ix86_cpu_string, ix86_arch_string);
297 target_flags |= processor_target_table[j].target_enable;
298 target_flags &= ~processor_target_table[j].target_disable;
304 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
305 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
306 ix86_cpu = PROCESSOR_DEFAULT;
309 /* Validate -mregparm= value. */
310 if (i386_regparm_string)
312 i386_regparm = atoi (i386_regparm_string);
313 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX)
314 fatal ("-mregparm=%d is not between 0 and %d",
315 i386_regparm, REGPARM_MAX);
318 /* The 486 suffers more from non-aligned cache line fills, and the
319 larger code size results in a larger cache foot-print and more misses.
320 The 486 has a 16 byte cache line, pentium and pentiumpro have a 32 byte
322 def_align = (TARGET_486) ? 4 : 2;
324 /* Validate -malign-loops= value, or provide default. */
325 if (i386_align_loops_string)
327 i386_align_loops = atoi (i386_align_loops_string);
328 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN)
329 fatal ("-malign-loops=%d is not between 0 and %d",
330 i386_align_loops, MAX_CODE_ALIGN);
333 i386_align_loops = 2;
335 /* Validate -malign-jumps= value, or provide default. */
336 if (i386_align_jumps_string)
338 i386_align_jumps = atoi (i386_align_jumps_string);
339 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN)
340 fatal ("-malign-jumps=%d is not between 0 and %d",
341 i386_align_jumps, MAX_CODE_ALIGN);
344 i386_align_jumps = def_align;
346 /* Validate -malign-functions= value, or provide default. */
347 if (i386_align_funcs_string)
349 i386_align_funcs = atoi (i386_align_funcs_string);
350 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN)
351 fatal ("-malign-functions=%d is not between 0 and %d",
352 i386_align_funcs, MAX_CODE_ALIGN);
355 i386_align_funcs = def_align;
357 /* Validate -mbranch-cost= value, or provide default. */
358 if (i386_branch_cost_string)
360 i386_branch_cost = atoi (i386_branch_cost_string);
361 if (i386_branch_cost < 0 || i386_branch_cost > 5)
362 fatal ("-mbranch-cost=%d is not between 0 and 5",
366 i386_branch_cost = 1;
368 /* Keep nonleaf frame pointers. */
369 if (TARGET_OMIT_LEAF_FRAME_POINTER)
370 flag_omit_frame_pointer = 1;
373 /* A C statement (sans semicolon) to choose the order in which to
374 allocate hard registers for pseudo-registers local to a basic
377 Store the desired register order in the array `reg_alloc_order'.
378 Element 0 should be the register to allocate first; element 1, the
379 next register; and so on.
381 The macro body should not assume anything about the contents of
382 `reg_alloc_order' before execution of the macro.
384 On most machines, it is not necessary to define this macro. */
387 order_regs_for_local_alloc ()
391 /* User specified the register allocation order. */
393 if (i386_reg_alloc_order)
395 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
401 case 'a': regno = 0; break;
402 case 'd': regno = 1; break;
403 case 'c': regno = 2; break;
404 case 'b': regno = 3; break;
405 case 'S': regno = 4; break;
406 case 'D': regno = 5; break;
407 case 'B': regno = 6; break;
410 reg_alloc_order[order++] = regno;
413 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
415 if (! regs_allocated[i])
416 reg_alloc_order[order++] = i;
420 /* If user did not specify a register allocation order, use natural order. */
423 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
424 reg_alloc_order[i] = i;
429 optimization_options (level, size)
433 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
434 make the problem with not enough registers even worse. */
435 #ifdef INSN_SCHEDULING
437 flag_schedule_insns = 0;
441 /* Sign-extend a 16-bit constant */
444 i386_sext16_if_const (op)
447 if (GET_CODE (op) == CONST_INT)
449 HOST_WIDE_INT val = INTVAL (op);
450 HOST_WIDE_INT sext_val;
452 sext_val = val | ~0xffff;
454 sext_val = val & 0xffff;
456 op = GEN_INT (sext_val);
461 /* Return nonzero if the rtx is aligned */
464 i386_aligned_reg_p (regno)
467 return (regno == STACK_POINTER_REGNUM
468 || (! flag_omit_frame_pointer && regno == FRAME_POINTER_REGNUM));
475 /* Registers and immediate operands are always "aligned". */
476 if (GET_CODE (op) != MEM)
479 /* Don't even try to do any aligned optimizations with volatiles. */
480 if (MEM_VOLATILE_P (op))
483 /* Get address of memory operand. */
486 switch (GET_CODE (op))
493 /* Match "reg + offset" */
495 if (GET_CODE (XEXP (op, 1)) != CONST_INT)
497 if (INTVAL (XEXP (op, 1)) & 3)
501 if (GET_CODE (op) != REG)
504 /* ... fall through ... */
507 return i386_aligned_reg_p (REGNO (op));
516 /* Return nonzero if INSN looks like it won't compute useful cc bits
517 as a side effect. This information is only a hint. */
520 i386_cc_probably_useless_p (insn)
523 return ! next_cc0_user (insn);
526 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
527 attribute for DECL. The attributes in ATTRIBUTES have previously been
531 i386_valid_decl_attribute_p (decl, attributes, identifier, args)
540 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
541 attribute for TYPE. The attributes in ATTRIBUTES have previously been
545 i386_valid_type_attribute_p (type, attributes, identifier, args)
551 if (TREE_CODE (type) != FUNCTION_TYPE
552 && TREE_CODE (type) != FIELD_DECL
553 && TREE_CODE (type) != TYPE_DECL)
556 /* Stdcall attribute says callee is responsible for popping arguments
557 if they are not variable. */
558 if (is_attribute_p ("stdcall", identifier))
559 return (args == NULL_TREE);
561 /* Cdecl attribute says the callee is a normal C declaration. */
562 if (is_attribute_p ("cdecl", identifier))
563 return (args == NULL_TREE);
565 /* Regparm attribute specifies how many integer arguments are to be
566 passed in registers. */
567 if (is_attribute_p ("regparm", identifier))
571 if (! args || TREE_CODE (args) != TREE_LIST
572 || TREE_CHAIN (args) != NULL_TREE
573 || TREE_VALUE (args) == NULL_TREE)
576 cst = TREE_VALUE (args);
577 if (TREE_CODE (cst) != INTEGER_CST)
580 if (TREE_INT_CST_HIGH (cst) != 0
581 || TREE_INT_CST_LOW (cst) < 0
582 || TREE_INT_CST_LOW (cst) > REGPARM_MAX)
591 /* Return 0 if the attributes for two types are incompatible, 1 if they
592 are compatible, and 2 if they are nearly compatible (which causes a
593 warning to be generated). */
596 i386_comp_type_attributes (type1, type2)
604 /* Value is the number of bytes of arguments automatically
605 popped when returning from a subroutine call.
606 FUNDECL is the declaration node of the function (as a tree),
607 FUNTYPE is the data type of the function (as a tree),
608 or for a library call it is an identifier node for the subroutine name.
609 SIZE is the number of bytes of arguments passed on the stack.
611 On the 80386, the RTD insn may be used to pop them if the number
612 of args is fixed, but if the number is variable then the caller
613 must pop them all. RTD can't be used for library calls now
614 because the library is compiled with the Unix compiler.
615 Use of RTD is a selectable option, since it is incompatible with
616 standard Unix calling sequences. If the option is not selected,
617 the caller must always pop the args.
619 The attribute stdcall is equivalent to RTD on a per module basis. */
622 i386_return_pops_args (fundecl, funtype, size)
627 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
629 /* Cdecl functions override -mrtd, and never pop the stack. */
630 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
632 /* Stdcall functions will pop the stack if not variable args. */
633 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
637 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
638 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
643 /* Lose any fake structure return argument. */
644 if (aggregate_value_p (TREE_TYPE (funtype)))
645 return GET_MODE_SIZE (Pmode);
651 /* Argument support functions. */
653 /* Initialize a variable CUM of type CUMULATIVE_ARGS
654 for a call to a function whose data type is FNTYPE.
655 For a library call, FNTYPE is 0. */
658 init_cumulative_args (cum, fntype, libname)
659 CUMULATIVE_ARGS *cum; /* Argument info to initialize */
660 tree fntype; /* tree ptr for function decl */
661 rtx libname; /* SYMBOL_REF of library name or 0 */
663 static CUMULATIVE_ARGS zero_cum;
664 tree param, next_param;
666 if (TARGET_DEBUG_ARG)
668 fprintf (stderr, "\ninit_cumulative_args (");
670 fprintf (stderr, "fntype code = %s, ret code = %s",
671 tree_code_name[(int) TREE_CODE (fntype)],
672 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
674 fprintf (stderr, "no fntype");
677 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
682 /* Set up the number of registers to use for passing arguments. */
683 cum->nregs = i386_regparm;
686 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
689 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
692 /* Determine if this function has variable arguments. This is
693 indicated by the last argument being 'void_type_mode' if there
694 are no variable arguments. If there are variable arguments, then
695 we won't pass anything in registers */
699 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
700 param != 0; param = next_param)
702 next_param = TREE_CHAIN (param);
703 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
708 if (TARGET_DEBUG_ARG)
709 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
714 /* Update the data in CUM to advance over an argument
715 of mode MODE and data type TYPE.
716 (TYPE is null for libcalls where that information may not be available.) */
719 function_arg_advance (cum, mode, type, named)
720 CUMULATIVE_ARGS *cum; /* current arg information */
721 enum machine_mode mode; /* current arg mode */
722 tree type; /* type of the argument or 0 if lib support */
723 int named; /* whether or not the argument was named */
726 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
727 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
729 if (TARGET_DEBUG_ARG)
731 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
732 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
747 /* Define where to put the arguments to a function.
748 Value is zero to push the argument on the stack,
749 or a hard register in which to store the argument.
751 MODE is the argument's machine mode.
752 TYPE is the data type of the argument (as a tree).
753 This is null for libcalls where that information may
755 CUM is a variable of type CUMULATIVE_ARGS which gives info about
756 the preceding args and about the function being called.
757 NAMED is nonzero if this argument is a named parameter
758 (otherwise it is an extra parameter matching an ellipsis). */
761 function_arg (cum, mode, type, named)
762 CUMULATIVE_ARGS *cum; /* current arg information */
763 enum machine_mode mode; /* current arg mode */
764 tree type; /* type of the argument or 0 if lib support */
765 int named; /* != 0 for normal args, == 0 for ... args */
769 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
770 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
774 /* For now, pass fp/complex values on the stack. */
783 if (words <= cum->nregs)
784 ret = gen_rtx_REG (mode, cum->regno);
788 if (TARGET_DEBUG_ARG)
791 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
792 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
795 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]);
797 fprintf (stderr, ", stack");
799 fprintf (stderr, " )\n");
805 /* For an arg passed partly in registers and partly in memory,
806 this is the number of registers used.
807 For args passed entirely in registers or entirely in memory, zero. */
810 function_arg_partial_nregs (cum, mode, type, named)
811 CUMULATIVE_ARGS *cum; /* current arg information */
812 enum machine_mode mode; /* current arg mode */
813 tree type; /* type of the argument or 0 if lib support */
814 int named; /* != 0 for normal args, == 0 for ... args */
819 /* Output an insn whose source is a 386 integer register. SRC is the
820 rtx for the register, and TEMPLATE is the op-code template. SRC may
821 be either SImode or DImode.
823 The template will be output with operands[0] as SRC, and operands[1]
824 as a pointer to the top of the 386 stack. So a call from floatsidf2
825 would look like this:
827 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
829 where %z0 corresponds to the caller's operands[1], and is used to
830 emit the proper size suffix.
832 ??? Extend this to handle HImode - a 387 can load and store HImode
836 output_op_from_reg (src, template)
841 int size = GET_MODE_SIZE (GET_MODE (src));
844 xops[1] = AT_SP (Pmode);
845 xops[2] = GEN_INT (size);
846 xops[3] = stack_pointer_rtx;
848 if (size > UNITS_PER_WORD)
852 if (size > 2 * UNITS_PER_WORD)
854 high = gen_rtx_REG (SImode, REGNO (src) + 2);
855 output_asm_insn (AS1 (push%L0,%0), &high);
858 high = gen_rtx_REG (SImode, REGNO (src) + 1);
859 output_asm_insn (AS1 (push%L0,%0), &high);
862 output_asm_insn (AS1 (push%L0,%0), &src);
863 output_asm_insn (template, xops);
864 output_asm_insn (AS2 (add%L3,%2,%3), xops);
867 /* Output an insn to pop an value from the 387 top-of-stack to 386
868 register DEST. The 387 register stack is popped if DIES is true. If
869 the mode of DEST is an integer mode, a `fist' integer store is done,
870 otherwise a `fst' float store is done. */
873 output_to_reg (dest, dies, scratch_mem)
879 int size = GET_MODE_SIZE (GET_MODE (dest));
882 xops[0] = AT_SP (Pmode);
884 xops[0] = scratch_mem;
886 xops[1] = stack_pointer_rtx;
887 xops[2] = GEN_INT (size);
891 output_asm_insn (AS2 (sub%L1,%2,%1), xops);
893 if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT)
896 output_asm_insn (AS1 (fistp%z3,%y0), xops);
898 output_asm_insn (AS1 (fist%z3,%y0), xops);
901 else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT)
904 output_asm_insn (AS1 (fstp%z3,%y0), xops);
907 if (GET_MODE (dest) == XFmode)
909 output_asm_insn (AS1 (fstp%z3,%y0), xops);
910 output_asm_insn (AS1 (fld%z3,%y0), xops);
913 output_asm_insn (AS1 (fst%z3,%y0), xops);
921 output_asm_insn (AS1 (pop%L0,%0), &dest);
923 output_asm_insn (AS2 (mov%L0,%0,%3), xops);
926 if (size > UNITS_PER_WORD)
928 dest = gen_rtx_REG (SImode, REGNO (dest) + 1);
930 output_asm_insn (AS1 (pop%L0,%0), &dest);
933 xops[0] = adj_offsettable_operand (xops[0], 4);
935 output_asm_insn (AS2 (mov%L0,%0,%3), xops);
938 if (size > 2 * UNITS_PER_WORD)
940 dest = gen_rtx_REG (SImode, REGNO (dest) + 1);
942 output_asm_insn (AS1 (pop%L0,%0), &dest);
945 xops[0] = adj_offsettable_operand (xops[0], 4);
946 output_asm_insn (AS2 (mov%L0,%0,%3), xops);
953 singlemove_string (operands)
957 if (GET_CODE (operands[0]) == MEM
958 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
960 if (XEXP (x, 0) != stack_pointer_rtx)
964 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
965 return output_move_const_single (operands);
966 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
967 return AS2 (mov%L0,%1,%0);
968 else if (CONSTANT_P (operands[1]))
969 return AS2 (mov%L0,%1,%0);
972 output_asm_insn ("push%L1 %1", operands);
977 /* Return a REG that occurs in ADDR with coefficient 1.
978 ADDR can be effectively incremented by incrementing REG. */
984 while (GET_CODE (addr) == PLUS)
986 if (GET_CODE (XEXP (addr, 0)) == REG)
987 addr = XEXP (addr, 0);
988 else if (GET_CODE (XEXP (addr, 1)) == REG)
989 addr = XEXP (addr, 1);
990 else if (CONSTANT_P (XEXP (addr, 0)))
991 addr = XEXP (addr, 1);
992 else if (CONSTANT_P (XEXP (addr, 1)))
993 addr = XEXP (addr, 0);
998 if (GET_CODE (addr) == REG)
1003 /* Output an insn to add the constant N to the register X. */
1014 output_asm_insn (AS1 (dec%L0,%0), xops);
1016 output_asm_insn (AS1 (inc%L0,%0), xops);
1017 else if (n < 0 || n == 128)
1019 xops[1] = GEN_INT (-n);
1020 output_asm_insn (AS2 (sub%L0,%1,%0), xops);
1024 xops[1] = GEN_INT (n);
1025 output_asm_insn (AS2 (add%L0,%1,%0), xops);
1029 /* Output assembler code to perform a doubleword move insn
1030 with operands OPERANDS. */
1033 output_move_double (operands)
1036 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
1040 rtx addreg0 = 0, addreg1 = 0;
1041 int dest_overlapped_low = 0;
1042 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
1047 /* First classify both operands. */
1049 if (REG_P (operands[0]))
1051 else if (offsettable_memref_p (operands[0]))
1053 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1055 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1057 else if (GET_CODE (operands[0]) == MEM)
1062 if (REG_P (operands[1]))
1064 else if (CONSTANT_P (operands[1]))
1066 else if (offsettable_memref_p (operands[1]))
1068 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
1070 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1072 else if (GET_CODE (operands[1]) == MEM)
1077 /* Check for the cases that the operand constraints are not
1078 supposed to allow to happen. Abort if we get one,
1079 because generating code for these cases is painful. */
1081 if (optype0 == RNDOP || optype1 == RNDOP)
1084 /* If one operand is decrementing and one is incrementing
1085 decrement the former register explicitly
1086 and change that operand into ordinary indexing. */
1088 if (optype0 == PUSHOP && optype1 == POPOP)
1090 /* ??? Can this ever happen on i386? */
1091 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1092 asm_add (-size, operands[0]);
1093 if (GET_MODE (operands[1]) == XFmode)
1094 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
1095 else if (GET_MODE (operands[0]) == DFmode)
1096 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
1098 operands[0] = gen_rtx_MEM (DImode, operands[0]);
1102 if (optype0 == POPOP && optype1 == PUSHOP)
1104 /* ??? Can this ever happen on i386? */
1105 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1106 asm_add (-size, operands[1]);
1107 if (GET_MODE (operands[1]) == XFmode)
1108 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
1109 else if (GET_MODE (operands[1]) == DFmode)
1110 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
1112 operands[1] = gen_rtx_MEM (DImode, operands[1]);
1116 /* If an operand is an unoffsettable memory ref, find a register
1117 we can increment temporarily to make it refer to the second word. */
1119 if (optype0 == MEMOP)
1120 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1122 if (optype1 == MEMOP)
1123 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1125 /* Ok, we can do one word at a time.
1126 Normally we do the low-numbered word first,
1127 but if either operand is autodecrementing then we
1128 do the high-numbered word first.
1130 In either case, set up in LATEHALF the operands to use
1131 for the high-numbered word and in some cases alter the
1132 operands in OPERANDS to be suitable for the low-numbered word. */
1136 if (optype0 == REGOP)
1138 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1139 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
1141 else if (optype0 == OFFSOP)
1143 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1144 latehalf[0] = adj_offsettable_operand (operands[0], 8);
1148 middlehalf[0] = operands[0];
1149 latehalf[0] = operands[0];
1152 if (optype1 == REGOP)
1154 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1155 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1157 else if (optype1 == OFFSOP)
1159 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1160 latehalf[1] = adj_offsettable_operand (operands[1], 8);
1162 else if (optype1 == CNSTOP)
1164 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1166 REAL_VALUE_TYPE r; long l[3];
1168 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1169 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1170 operands[1] = GEN_INT (l[0]);
1171 middlehalf[1] = GEN_INT (l[1]);
1172 latehalf[1] = GEN_INT (l[2]);
1174 else if (CONSTANT_P (operands[1]))
1175 /* No non-CONST_DOUBLE constant should ever appear here. */
1180 middlehalf[1] = operands[1];
1181 latehalf[1] = operands[1];
1187 /* Size is not 12. */
1189 if (optype0 == REGOP)
1190 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1191 else if (optype0 == OFFSOP)
1192 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1194 latehalf[0] = operands[0];
1196 if (optype1 == REGOP)
1197 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1198 else if (optype1 == OFFSOP)
1199 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1200 else if (optype1 == CNSTOP)
1201 split_double (operands[1], &operands[1], &latehalf[1]);
1203 latehalf[1] = operands[1];
1206 /* If insn is effectively movd N (sp),-(sp) then we will do the
1207 high word first. We should use the adjusted operand 1
1208 (which is N+4 (sp) or N+8 (sp))
1209 for the low word and middle word as well,
1210 to compensate for the first decrement of sp. */
1211 if (optype0 == PUSHOP
1212 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1213 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1214 middlehalf[1] = operands[1] = latehalf[1];
1216 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1217 if the upper part of reg N does not appear in the MEM, arrange to
1218 emit the move late-half first. Otherwise, compute the MEM address
1219 into the upper part of N and use that as a pointer to the memory
1221 if (optype0 == REGOP
1222 && (optype1 == OFFSOP || optype1 == MEMOP))
1224 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1225 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1227 /* If both halves of dest are used in the src memory address,
1228 compute the address into latehalf of dest. */
1230 xops[0] = latehalf[0];
1231 xops[1] = XEXP (operands[1], 0);
1232 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
1233 if (GET_MODE (operands[1]) == XFmode)
1235 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
1236 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1237 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1241 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
1242 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1247 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
1249 /* Check for two regs used by both source and dest. */
1250 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1251 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1254 /* JRV says this can't happen: */
1255 if (addreg0 || addreg1)
1258 /* Only the middle reg conflicts; simply put it last. */
1259 output_asm_insn (singlemove_string (operands), operands);
1260 output_asm_insn (singlemove_string (latehalf), latehalf);
1261 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1265 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
1266 /* If the low half of dest is mentioned in the source memory
1267 address, the arrange to emit the move late half first. */
1268 dest_overlapped_low = 1;
1271 /* If one or both operands autodecrementing,
1272 do the two words, high-numbered first. */
1274 /* Likewise, the first move would clobber the source of the second one,
1275 do them in the other order. This happens only for registers;
1276 such overlap can't happen in memory unless the user explicitly
1277 sets it up, and that is an undefined circumstance. */
1280 if (optype0 == PUSHOP || optype1 == PUSHOP
1281 || (optype0 == REGOP && optype1 == REGOP
1282 && REGNO (operands[0]) == REGNO (latehalf[1]))
1283 || dest_overlapped_low)
1286 if (optype0 == PUSHOP || optype1 == PUSHOP
1287 || (optype0 == REGOP && optype1 == REGOP
1288 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1289 || REGNO (operands[0]) == REGNO (latehalf[1])))
1290 || dest_overlapped_low)
1292 /* Make any unoffsettable addresses point at high-numbered word. */
1294 asm_add (size-4, addreg0);
1296 asm_add (size-4, addreg1);
1299 output_asm_insn (singlemove_string (latehalf), latehalf);
1301 /* Undo the adds we just did. */
1303 asm_add (-4, addreg0);
1305 asm_add (-4, addreg1);
1309 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1311 asm_add (-4, addreg0);
1313 asm_add (-4, addreg1);
1316 /* Do low-numbered word. */
1317 return singlemove_string (operands);
1320 /* Normal case: do the two words, low-numbered first. */
1322 output_asm_insn (singlemove_string (operands), operands);
1324 /* Do the middle one of the three words for long double */
1328 asm_add (4, addreg0);
1330 asm_add (4, addreg1);
1332 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1335 /* Make any unoffsettable addresses point at high-numbered word. */
1337 asm_add (4, addreg0);
1339 asm_add (4, addreg1);
1342 output_asm_insn (singlemove_string (latehalf), latehalf);
1344 /* Undo the adds we just did. */
1346 asm_add (4-size, addreg0);
1348 asm_add (4-size, addreg1);
1353 #define MAX_TMPS 2 /* max temporary registers used */
1355 /* Output the appropriate code to move push memory on the stack */
1358 output_move_pushmem (operands, insn, length, tmp_start, n_operands)
1370 } tmp_info[MAX_TMPS];
1372 rtx src = operands[1];
1375 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
1376 int stack_offset = 0;
1380 if (! offsettable_memref_p (src))
1381 fatal_insn ("Source is not offsettable", insn);
1383 if ((length & 3) != 0)
1384 fatal_insn ("Pushing non-word aligned size", insn);
1386 /* Figure out which temporary registers we have available */
1387 for (i = tmp_start; i < n_operands; i++)
1389 if (GET_CODE (operands[i]) == REG)
1391 if (reg_overlap_mentioned_p (operands[i], src))
1394 tmp_info[ max_tmps++ ].xops[1] = operands[i];
1395 if (max_tmps == MAX_TMPS)
1401 for (offset = length - 4; offset >= 0; offset -= 4)
1403 xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1404 output_asm_insn (AS1(push%L0,%0), xops);
1410 for (offset = length - 4; offset >= 0; )
1412 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
1414 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1);
1415 tmp_info[num_tmps].push = AS1(push%L0,%1);
1416 tmp_info[num_tmps].xops[0]
1417 = adj_offsettable_operand (src, offset + stack_offset);
1421 for (i = 0; i < num_tmps; i++)
1422 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1424 for (i = 0; i < num_tmps; i++)
1425 output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
1428 stack_offset += 4*num_tmps;
1434 /* Output the appropriate code to move data between two memory locations */
1437 output_move_memory (operands, insn, length, tmp_start, n_operands)
1449 } tmp_info[MAX_TMPS];
1451 rtx dest = operands[0];
1452 rtx src = operands[1];
1453 rtx qi_tmp = NULL_RTX;
1459 if (GET_CODE (dest) == MEM
1460 && GET_CODE (XEXP (dest, 0)) == PRE_INC
1461 && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)
1462 return output_move_pushmem (operands, insn, length, tmp_start, n_operands);
1464 if (! offsettable_memref_p (src))
1465 fatal_insn ("Source is not offsettable", insn);
1467 if (! offsettable_memref_p (dest))
1468 fatal_insn ("Destination is not offsettable", insn);
1470 /* Figure out which temporary registers we have available */
1471 for (i = tmp_start; i < n_operands; i++)
1473 if (GET_CODE (operands[i]) == REG)
1475 if ((length & 1) != 0 && qi_tmp == 0 && QI_REG_P (operands[i]))
1476 qi_tmp = operands[i];
1478 if (reg_overlap_mentioned_p (operands[i], dest))
1479 fatal_insn ("Temporary register overlaps the destination", insn);
1481 if (reg_overlap_mentioned_p (operands[i], src))
1482 fatal_insn ("Temporary register overlaps the source", insn);
1484 tmp_info[max_tmps++].xops[2] = operands[i];
1485 if (max_tmps == MAX_TMPS)
1491 fatal_insn ("No scratch registers were found to do memory->memory moves",
1494 if ((length & 1) != 0)
1497 fatal_insn ("No byte register found when moving odd # of bytes.",
1503 for (num_tmps = 0; num_tmps < max_tmps; num_tmps++)
1507 tmp_info[num_tmps].load = AS2(mov%L0,%1,%2);
1508 tmp_info[num_tmps].store = AS2(mov%L0,%2,%0);
1509 tmp_info[num_tmps].xops[0]
1510 = adj_offsettable_operand (dest, offset);
1511 tmp_info[num_tmps].xops[1]
1512 = adj_offsettable_operand (src, offset);
1518 else if (length >= 2)
1520 tmp_info[num_tmps].load = AS2(mov%W0,%1,%2);
1521 tmp_info[num_tmps].store = AS2(mov%W0,%2,%0);
1522 tmp_info[num_tmps].xops[0]
1523 = adj_offsettable_operand (dest, offset);
1524 tmp_info[num_tmps].xops[1]
1525 = adj_offsettable_operand (src, offset);
1534 for (i = 0; i < num_tmps; i++)
1535 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1537 for (i = 0; i < num_tmps; i++)
1538 output_asm_insn (tmp_info[i].store, tmp_info[i].xops);
1543 xops[0] = adj_offsettable_operand (dest, offset);
1544 xops[1] = adj_offsettable_operand (src, offset);
1546 output_asm_insn (AS2(mov%B0,%1,%2), xops);
1547 output_asm_insn (AS2(mov%B0,%2,%0), xops);
1554 standard_80387_constant_p (x)
1557 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
1562 if (setjmp (handler))
1565 set_float_handler (handler);
1566 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1567 is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d);
1568 is1 = REAL_VALUES_EQUAL (d, dconst1);
1569 set_float_handler (NULL_PTR);
1577 /* Note that on the 80387, other constants, such as pi,
1578 are much slower to load as standard constants
1579 than to load from doubles in memory! */
1586 output_move_const_single (operands)
1589 if (FP_REG_P (operands[0]))
1591 int conval = standard_80387_constant_p (operands[1]);
1600 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1602 REAL_VALUE_TYPE r; long l;
1604 if (GET_MODE (operands[1]) == XFmode)
1607 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1608 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1609 operands[1] = GEN_INT (l);
1612 return singlemove_string (operands);
1615 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1616 reference and a constant. */
1619 symbolic_operand (op, mode)
1621 enum machine_mode mode;
1623 switch (GET_CODE (op))
1631 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1632 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1633 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1640 /* Test for a valid operand for a call instruction.
1641 Don't allow the arg pointer register or virtual regs
1642 since they may change into reg + const, which the patterns
1643 can't handle yet. */
1646 call_insn_operand (op, mode)
1648 enum machine_mode mode;
1650 if (GET_CODE (op) == MEM
1651 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
1652 /* This makes a difference for PIC. */
1653 && general_operand (XEXP (op, 0), Pmode))
1654 || (GET_CODE (XEXP (op, 0)) == REG
1655 && XEXP (op, 0) != arg_pointer_rtx
1656 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1657 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1663 /* Like call_insn_operand but allow (mem (symbol_ref ...))
1667 expander_call_insn_operand (op, mode)
1669 enum machine_mode mode;
1671 if (GET_CODE (op) == MEM
1672 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
1673 || (GET_CODE (XEXP (op, 0)) == REG
1674 && XEXP (op, 0) != arg_pointer_rtx
1675 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1676 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1682 /* Return 1 if OP is a comparison operator that can use the condition code
1683 generated by an arithmetic operation. */
1686 arithmetic_comparison_operator (op, mode)
1688 enum machine_mode mode;
1692 if (mode != VOIDmode && mode != GET_MODE (op))
1695 code = GET_CODE (op);
1696 if (GET_RTX_CLASS (code) != '<')
1699 return (code != GT && code != LE);
1702 /* Returns 1 if OP contains a symbol reference */
1705 symbolic_reference_mentioned_p (op)
1711 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1714 fmt = GET_RTX_FORMAT (GET_CODE (op));
1715 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1721 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1722 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1726 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1733 /* Attempt to expand a binary operator. Make the expansion closer to the
1734 actual machine, then just general_operand, which will allow 3 separate
1735 memory references (one output, two input) in a single insn. Return
1736 whether the insn fails, or succeeds. */
1739 ix86_expand_binary_operator (code, mode, operands)
1741 enum machine_mode mode;
1746 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
1747 if (GET_RTX_CLASS (code) == 'c'
1748 && (rtx_equal_p (operands[0], operands[2])
1749 || immediate_operand (operands[1], mode)))
1751 rtx temp = operands[1];
1752 operands[1] = operands[2];
1756 /* If optimizing, copy to regs to improve CSE */
1757 if (TARGET_PSEUDO && optimize
1758 && ((reload_in_progress | reload_completed) == 0))
1760 if (GET_CODE (operands[1]) == MEM
1761 && ! rtx_equal_p (operands[0], operands[1]))
1762 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1764 if (GET_CODE (operands[2]) == MEM)
1765 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1767 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1769 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1771 emit_move_insn (temp, operands[1]);
1777 if (!ix86_binary_operator_ok (code, mode, operands))
1779 /* If not optimizing, try to make a valid insn (optimize code
1780 previously did this above to improve chances of CSE) */
1782 if ((! TARGET_PSEUDO || !optimize)
1783 && ((reload_in_progress | reload_completed) == 0)
1784 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM))
1787 if (GET_CODE (operands[1]) == MEM
1788 && ! rtx_equal_p (operands[0], operands[1]))
1790 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1794 if (GET_CODE (operands[2]) == MEM)
1796 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1800 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1802 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1804 emit_move_insn (temp, operands[1]);
1809 if (modified && ! ix86_binary_operator_ok (code, mode, operands))
1819 /* Return TRUE or FALSE depending on whether the binary operator meets the
1820 appropriate constraints. */
1823 ix86_binary_operator_ok (code, mode, operands)
1825 enum machine_mode mode;
1828 return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
1829 && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c');
1832 /* Attempt to expand a unary operator. Make the expansion closer to the
1833 actual machine, then just general_operand, which will allow 2 separate
1834 memory references (one output, one input) in a single insn. Return
1835 whether the insn fails, or succeeds. */
1838 ix86_expand_unary_operator (code, mode, operands)
1840 enum machine_mode mode;
1843 /* If optimizing, copy to regs to improve CSE */
1846 && ((reload_in_progress | reload_completed) == 0)
1847 && GET_CODE (operands[1]) == MEM)
1848 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1850 if (! ix86_unary_operator_ok (code, mode, operands))
1852 if ((! TARGET_PSEUDO || optimize == 0)
1853 && ((reload_in_progress | reload_completed) == 0)
1854 && GET_CODE (operands[1]) == MEM)
1856 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1857 if (! ix86_unary_operator_ok (code, mode, operands))
1867 /* Return TRUE or FALSE depending on whether the unary operator meets the
1868 appropriate constraints. */
1871 ix86_unary_operator_ok (code, mode, operands)
1873 enum machine_mode mode;
1879 static rtx pic_label_rtx;
1880 static char pic_label_name [256];
1881 static int pic_label_no = 0;
1883 /* This function generates code for -fpic that loads %ebx with
1884 with the return address of the caller and then returns. */
1887 asm_output_function_prefix (file, name)
1892 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1893 || current_function_uses_const_pool);
1894 xops[0] = pic_offset_table_rtx;
1895 xops[1] = stack_pointer_rtx;
1897 /* Deep branch prediction favors having a return for every call. */
1898 if (pic_reg_used && TARGET_DEEP_BRANCH_PREDICTION)
1902 if (pic_label_rtx == 0)
1904 pic_label_rtx = gen_label_rtx ();
1905 sprintf (pic_label_name, "LPR%d", pic_label_no++);
1906 LABEL_NAME (pic_label_rtx) = pic_label_name;
1909 prologue_node = make_node (FUNCTION_DECL);
1910 DECL_RESULT (prologue_node) = 0;
1911 #ifdef ASM_DECLARE_FUNCTION_NAME
1912 ASM_DECLARE_FUNCTION_NAME (file, pic_label_name, prologue_node);
1914 output_asm_insn ("movl (%1),%0", xops);
1915 output_asm_insn ("ret", xops);
1919 /* Generate the assembly code for function entry.
1920 FILE is an stdio stream to output the code to.
1921 SIZE is an int: how many units of temporary storage to allocate. */
1924 function_prologue (file, size)
1928 if (TARGET_SCHEDULE_PROLOGUE)
1937 /* Expand the prologue into a bunch of separate insns. */
1940 ix86_expand_prologue ()
1942 if (! TARGET_SCHEDULE_PROLOGUE)
1949 load_pic_register (do_rtl)
1954 if (TARGET_DEEP_BRANCH_PREDICTION)
1956 xops[0] = pic_offset_table_rtx;
1957 if (pic_label_rtx == 0)
1959 pic_label_rtx = gen_label_rtx ();
1960 sprintf (pic_label_name, "LPR%d", pic_label_no++);
1961 LABEL_NAME (pic_label_rtx) = pic_label_name;
1964 xops[1] = gen_rtx_MEM (QImode,
1965 gen_rtx (SYMBOL_REF, Pmode,
1966 LABEL_NAME (pic_label_rtx)));
1970 emit_insn (gen_prologue_get_pc (xops[0], xops[1]));
1971 emit_insn (gen_prologue_set_got (xops[0],
1972 gen_rtx (SYMBOL_REF, Pmode,
1973 "$_GLOBAL_OFFSET_TABLE_"),
1978 output_asm_insn (AS1 (call,%P1), xops);
1979 output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_,%0", xops);
1986 xops[0] = pic_offset_table_rtx;
1987 xops[1] = gen_label_rtx ();
1991 /* We can't put a raw CODE_LABEL into the RTL, and we can't emit
1992 a new CODE_LABEL after reload, so we need a single pattern to
1993 emit the 3 necessary instructions. */
1994 emit_insn (gen_prologue_get_pc_and_set_got (xops[0]));
1998 output_asm_insn (AS1 (call,%P1), xops);
1999 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
2000 CODE_LABEL_NUMBER (xops[1]));
2001 output_asm_insn (AS1 (pop%L0,%0), xops);
2002 output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
2006 /* When -fpic, we must emit a scheduling barrier, so that the instruction
2007 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
2008 moved before any instruction which implicitly uses the got. */
2011 emit_insn (gen_blockage ());
2015 ix86_prologue (do_rtl)
2021 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
2022 || current_function_uses_const_pool);
2023 long tsize = get_frame_size ();
2025 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
2027 xops[0] = stack_pointer_rtx;
2028 xops[1] = frame_pointer_rtx;
2029 xops[2] = GEN_INT (tsize);
2031 if (frame_pointer_needed)
2035 insn = emit_insn (gen_rtx (SET, VOIDmode,
2036 gen_rtx_MEM (SImode,
2037 gen_rtx (PRE_DEC, SImode,
2038 stack_pointer_rtx)),
2039 frame_pointer_rtx));
2041 RTX_FRAME_RELATED_P (insn) = 1;
2042 insn = emit_move_insn (xops[1], xops[0]);
2043 RTX_FRAME_RELATED_P (insn) = 1;
2048 output_asm_insn ("push%L1 %1", xops);
2049 #ifdef INCOMING_RETURN_ADDR_RTX
2050 if (dwarf2out_do_frame ())
2052 char *l = dwarf2out_cfi_label ();
2054 cfa_store_offset += 4;
2055 cfa_offset = cfa_store_offset;
2056 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
2057 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, - cfa_store_offset);
2061 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
2062 #ifdef INCOMING_RETURN_ADDR_RTX
2063 if (dwarf2out_do_frame ())
2064 dwarf2out_def_cfa ("", FRAME_POINTER_REGNUM, cfa_offset);
2071 else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT)
2075 insn = emit_insn (gen_prologue_set_stack_ptr (xops[2]));
2076 RTX_FRAME_RELATED_P (insn) = 1;
2080 output_asm_insn (AS2 (sub%L0,%2,%0), xops);
2081 #ifdef INCOMING_RETURN_ADDR_RTX
2082 if (dwarf2out_do_frame ())
2084 cfa_store_offset += tsize;
2085 if (! frame_pointer_needed)
2087 cfa_offset = cfa_store_offset;
2088 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
2096 xops[3] = gen_rtx_REG (SImode, 0);
2098 emit_move_insn (xops[3], xops[2]);
2100 output_asm_insn (AS2 (mov%L0,%2,%3), xops);
2102 xops[3] = gen_rtx_MEM (FUNCTION_MODE,
2103 gen_rtx (SYMBOL_REF, Pmode, "_alloca"));
2106 emit_call_insn (gen_rtx (CALL, VOIDmode, xops[3], const0_rtx));
2108 output_asm_insn (AS1 (call,%P3), xops);
2111 /* Note If use enter it is NOT reversed args.
2112 This one is not reversed from intel!!
2113 I think enter is slower. Also sdb doesn't like it.
2114 But if you want it the code is:
2116 xops[3] = const0_rtx;
2117 output_asm_insn ("enter %2,%3", xops);
2121 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
2122 for (regno = limit - 1; regno >= 0; regno--)
2123 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2124 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2126 xops[0] = gen_rtx_REG (SImode, regno);
2129 insn = emit_insn (gen_rtx (SET, VOIDmode,
2130 gen_rtx_MEM (SImode,
2131 gen_rtx (PRE_DEC, SImode,
2132 stack_pointer_rtx)),
2135 RTX_FRAME_RELATED_P (insn) = 1;
2139 output_asm_insn ("push%L0 %0", xops);
2140 #ifdef INCOMING_RETURN_ADDR_RTX
2141 if (dwarf2out_do_frame ())
2143 char *l = dwarf2out_cfi_label ();
2145 cfa_store_offset += 4;
2146 if (! frame_pointer_needed)
2148 cfa_offset = cfa_store_offset;
2149 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
2152 dwarf2out_reg_save (l, regno, - cfa_store_offset);
2159 load_pic_register (do_rtl);
2161 /* If we are profiling, make sure no instructions are scheduled before
2162 the call to mcount. However, if -fpic, the above call will have
2164 if ((profile_flag || profile_block_flag)
2165 && ! pic_reg_used && do_rtl)
2166 emit_insn (gen_blockage ());
2169 /* Return 1 if it is appropriate to emit `ret' instructions in the
2170 body of a function. Do this only if the epilogue is simple, needing a
2171 couple of insns. Prior to reloading, we can't tell how many registers
2172 must be saved, so return 0 then. Return 0 if there is no frame
2173 marker to de-allocate.
2175 If NON_SAVING_SETJMP is defined and true, then it is not possible
2176 for the epilogue to be simple, so return 0. This is a special case
2177 since NON_SAVING_SETJMP will not cause regs_ever_live to change
2178 until final, but jump_optimize may need to know sooner if a
2182 ix86_can_use_return_insn_p ()
2186 int reglimit = (frame_pointer_needed
2187 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
2188 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
2189 || current_function_uses_const_pool);
2191 #ifdef NON_SAVING_SETJMP
2192 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
2196 if (! reload_completed)
2199 for (regno = reglimit - 1; regno >= 0; regno--)
2200 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2201 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2204 return nregs == 0 || ! frame_pointer_needed;
2207 /* This function generates the assembly code for function exit.
2208 FILE is an stdio stream to output the code to.
2209 SIZE is an int: how many units of temporary storage to deallocate. */
2212 function_epilogue (file, size)
2219 /* Restore function stack, frame, and registers. */
2222 ix86_expand_epilogue ()
2228 ix86_epilogue (do_rtl)
2232 register int nregs, limit;
2235 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
2236 || current_function_uses_const_pool);
2237 long tsize = get_frame_size ();
2239 /* Compute the number of registers to pop */
2241 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
2245 for (regno = limit - 1; regno >= 0; regno--)
2246 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2247 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2250 /* sp is often unreliable so we must go off the frame pointer.
2252 In reality, we may not care if sp is unreliable, because we can restore
2253 the register relative to the frame pointer. In theory, since each move
2254 is the same speed as a pop, and we don't need the leal, this is faster.
2255 For now restore multiple registers the old way. */
2257 offset = - tsize - (nregs * UNITS_PER_WORD);
2259 xops[2] = stack_pointer_rtx;
2261 /* When -fpic, we must emit a scheduling barrier, so that the instruction
2262 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
2263 moved before any instruction which implicitly uses the got. This
2264 includes any instruction which uses a SYMBOL_REF or a LABEL_REF.
2266 Alternatively, this could be fixed by making the dependence on the
2267 PIC_OFFSET_TABLE_REGNUM explicit in the RTL. */
2269 if (flag_pic || profile_flag || profile_block_flag)
2270 emit_insn (gen_blockage ());
2272 if (nregs > 1 || ! frame_pointer_needed)
2274 if (frame_pointer_needed)
2276 xops[0] = adj_offsettable_operand (AT_BP (QImode), offset);
2278 emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0)));
2280 output_asm_insn (AS2 (lea%L2,%0,%2), xops);
2283 for (regno = 0; regno < limit; regno++)
2284 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2285 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2287 xops[0] = gen_rtx_REG (SImode, regno);
2290 emit_insn (gen_pop (xops[0]));
2292 output_asm_insn ("pop%L0 %0", xops);
2297 for (regno = 0; regno < limit; regno++)
2298 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2299 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2301 xops[0] = gen_rtx_REG (SImode, regno);
2302 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
2305 emit_move_insn (xops[0], xops[1]);
2307 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
2312 if (frame_pointer_needed)
2314 /* If not an i386, mov & pop is faster than "leave". */
2316 if (TARGET_USE_LEAVE)
2319 emit_insn (gen_leave());
2321 output_asm_insn ("leave", xops);
2325 xops[0] = frame_pointer_rtx;
2326 xops[1] = stack_pointer_rtx;
2330 emit_insn (gen_epilogue_set_stack_ptr());
2331 emit_insn (gen_pop (xops[0]));
2335 output_asm_insn (AS2 (mov%L2,%0,%2), xops);
2336 output_asm_insn ("pop%L0 %0", xops);
2343 /* If there is no frame pointer, we must still release the frame. */
2344 xops[0] = GEN_INT (tsize);
2347 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2348 gen_rtx (PLUS, SImode, xops[2], xops[0])));
2350 output_asm_insn (AS2 (add%L2,%0,%2), xops);
2353 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
2354 if (profile_block_flag == 2)
2356 FUNCTION_BLOCK_PROFILER_EXIT(file);
2360 if (current_function_pops_args && current_function_args_size)
2362 xops[1] = GEN_INT (current_function_pops_args);
2364 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
2365 asked to pop more, pop return address, do explicit add, and jump
2366 indirectly to the caller. */
2368 if (current_function_pops_args >= 32768)
2370 /* ??? Which register to use here? */
2371 xops[0] = gen_rtx_REG (SImode, 2);
2375 emit_insn (gen_pop (xops[0]));
2376 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2377 gen_rtx (PLUS, SImode, xops[1], xops[2])));
2378 emit_jump_insn (xops[0]);
2382 output_asm_insn ("pop%L0 %0", xops);
2383 output_asm_insn (AS2 (add%L2,%1,%2), xops);
2384 output_asm_insn ("jmp %*%0", xops);
2390 emit_jump_insn (gen_return_pop_internal (xops[1]));
2392 output_asm_insn ("ret %1", xops);
2398 emit_jump_insn (gen_return_internal ());
2400 output_asm_insn ("ret", xops);
2404 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2405 that is a valid memory address for an instruction.
2406 The MODE argument is the machine mode for the MEM expression
2407 that wants to use this address.
2409 On x86, legitimate addresses are:
2410 base movl (base),reg
2411 displacement movl disp,reg
2412 base + displacement movl disp(base),reg
2413 index + base movl (base,index),reg
2414 (index + base) + displacement movl disp(base,index),reg
2415 index*scale movl (,index,scale),reg
2416 index*scale + disp movl disp(,index,scale),reg
2417 index*scale + base movl (base,index,scale),reg
2418 (index*scale + base) + disp movl disp(base,index,scale),reg
2420 In each case, scale can be 1, 2, 4, 8. */
2422 /* This is exactly the same as print_operand_addr, except that
2423 it recognizes addresses instead of printing them.
2425 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2426 convert common non-canonical forms to canonical form so that they will
2429 #define ADDR_INVALID(msg,insn) \
2431 if (TARGET_DEBUG_ADDR) \
2433 fprintf (stderr, msg); \
2439 legitimate_address_p (mode, addr, strict)
2440 enum machine_mode mode;
2444 rtx base = NULL_RTX;
2445 rtx indx = NULL_RTX;
2446 rtx scale = NULL_RTX;
2447 rtx disp = NULL_RTX;
2449 if (TARGET_DEBUG_ADDR)
2452 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
2453 GET_MODE_NAME (mode), strict);
2458 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
2461 else if (GET_CODE (addr) == PLUS)
2463 rtx op0 = XEXP (addr, 0);
2464 rtx op1 = XEXP (addr, 1);
2465 enum rtx_code code0 = GET_CODE (op0);
2466 enum rtx_code code1 = GET_CODE (op1);
2468 if (code0 == REG || code0 == SUBREG)
2470 if (code1 == REG || code1 == SUBREG)
2472 indx = op0; /* index + base */
2478 base = op0; /* base + displacement */
2483 else if (code0 == MULT)
2485 indx = XEXP (op0, 0);
2486 scale = XEXP (op0, 1);
2488 if (code1 == REG || code1 == SUBREG)
2489 base = op1; /* index*scale + base */
2492 disp = op1; /* index*scale + disp */
2495 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
2497 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */
2498 scale = XEXP (XEXP (op0, 0), 1);
2499 base = XEXP (op0, 1);
2503 else if (code0 == PLUS)
2505 indx = XEXP (op0, 0); /* index + base + disp */
2506 base = XEXP (op0, 1);
2512 ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
2517 else if (GET_CODE (addr) == MULT)
2519 indx = XEXP (addr, 0); /* index*scale */
2520 scale = XEXP (addr, 1);
2524 disp = addr; /* displacement */
2526 /* Allow arg pointer and stack pointer as index if there is not scaling */
2527 if (base && indx && !scale
2528 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
2535 /* Validate base register:
2537 Don't allow SUBREG's here, it can lead to spill failures when the base
2538 is one word out of a two word structure, which is represented internally
2543 if (GET_CODE (base) != REG)
2545 ADDR_INVALID ("Base is not a register.\n", base);
2549 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base))
2550 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base)))
2552 ADDR_INVALID ("Base is not valid.\n", base);
2557 /* Validate index register:
2559 Don't allow SUBREG's here, it can lead to spill failures when the index
2560 is one word out of a two word structure, which is represented internally
2564 if (GET_CODE (indx) != REG)
2566 ADDR_INVALID ("Index is not a register.\n", indx);
2570 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (indx))
2571 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
2573 ADDR_INVALID ("Index is not valid.\n", indx);
2578 abort (); /* scale w/o index invalid */
2580 /* Validate scale factor: */
2583 HOST_WIDE_INT value;
2585 if (GET_CODE (scale) != CONST_INT)
2587 ADDR_INVALID ("Scale is not valid.\n", scale);
2591 value = INTVAL (scale);
2592 if (value != 1 && value != 2 && value != 4 && value != 8)
2594 ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
2599 /* Validate displacement
2600 Constant pool addresses must be handled special. They are
2601 considered legitimate addresses, but only if not used with regs.
2602 When printed, the output routines know to print the reference with the
2603 PIC reg, even though the PIC reg doesn't appear in the RTL. */
2606 if (GET_CODE (disp) == SYMBOL_REF
2607 && CONSTANT_POOL_ADDRESS_P (disp)
2612 else if (!CONSTANT_ADDRESS_P (disp))
2614 ADDR_INVALID ("Displacement is not valid.\n", disp);
2618 else if (GET_CODE (disp) == CONST_DOUBLE)
2620 ADDR_INVALID ("Displacement is a const_double.\n", disp);
2624 else if (flag_pic && SYMBOLIC_CONST (disp)
2625 && base != pic_offset_table_rtx
2626 && (indx != pic_offset_table_rtx || scale != NULL_RTX))
2628 ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp);
2632 else if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp)
2633 && (base != NULL_RTX || indx != NULL_RTX))
2635 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n",
2641 if (TARGET_DEBUG_ADDR)
2642 fprintf (stderr, "Address is valid.\n");
2644 /* Everything looks valid, return true */
2648 /* Return a legitimate reference for ORIG (an address) using the
2649 register REG. If REG is 0, a new pseudo is generated.
2651 There are three types of references that must be handled:
2653 1. Global data references must load the address from the GOT, via
2654 the PIC reg. An insn is emitted to do this load, and the reg is
2657 2. Static data references must compute the address as an offset
2658 from the GOT, whose base is in the PIC reg. An insn is emitted to
2659 compute the address into a reg, and the reg is returned. Static
2660 data objects have SYMBOL_REF_FLAG set to differentiate them from
2661 global data objects.
2663 3. Constant pool addresses must be handled special. They are
2664 considered legitimate addresses, but only if not used with regs.
2665 When printed, the output routines know to print the reference with the
2666 PIC reg, even though the PIC reg doesn't appear in the RTL.
2668 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2669 reg also appears in the address (except for constant pool references,
2672 "switch" statements also require special handling when generating
2673 PIC code. See comments by the `casesi' insn in i386.md for details. */
2676 legitimize_pic_address (orig, reg)
2683 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
2685 if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr))
2690 reg = gen_reg_rtx (Pmode);
2692 if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr))
2693 || GET_CODE (addr) == LABEL_REF)
2694 new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig);
2696 new = gen_rtx_MEM (Pmode,
2697 gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig));
2699 emit_move_insn (reg, new);
2701 current_function_uses_pic_offset_table = 1;
2705 else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
2709 if (GET_CODE (addr) == CONST)
2711 addr = XEXP (addr, 0);
2712 if (GET_CODE (addr) != PLUS)
2716 if (XEXP (addr, 0) == pic_offset_table_rtx)
2720 reg = gen_reg_rtx (Pmode);
2722 base = legitimize_pic_address (XEXP (addr, 0), reg);
2723 addr = legitimize_pic_address (XEXP (addr, 1),
2724 base == reg ? NULL_RTX : reg);
2726 if (GET_CODE (addr) == CONST_INT)
2727 return plus_constant (base, INTVAL (addr));
2729 if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
2731 base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0));
2732 addr = XEXP (addr, 1);
2735 return gen_rtx (PLUS, Pmode, base, addr);
2740 /* Emit insns to move operands[1] into operands[0]. */
2743 emit_pic_move (operands, mode)
2745 enum machine_mode mode;
2747 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
2749 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
2750 operands[1] = force_reg (SImode, operands[1]);
2752 operands[1] = legitimize_pic_address (operands[1], temp);
2755 /* Try machine-dependent ways of modifying an illegitimate address
2756 to be legitimate. If we find one, return the new, valid address.
2757 This macro is used in only one place: `memory_address' in explow.c.
2759 OLDX is the address as it was before break_out_memory_refs was called.
2760 In some cases it is useful to look at this to decide what needs to be done.
2762 MODE and WIN are passed so that this macro can use
2763 GO_IF_LEGITIMATE_ADDRESS.
2765 It is always safe for this macro to do nothing. It exists to recognize
2766 opportunities to optimize the output.
2768 For the 80386, we handle X+REG by loading X into a register R and
2769 using R+REG. R will go in a general reg and indexing will be used.
2770 However, if REG is a broken-out memory address or multiplication,
2771 nothing needs to be done because REG can certainly go in a general reg.
2773 When -fpic is used, special handling is needed for symbolic references.
2774 See comments by legitimize_pic_address in i386.c for details. */
2777 legitimize_address (x, oldx, mode)
2780 enum machine_mode mode;
2785 if (TARGET_DEBUG_ADDR)
2787 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
2788 GET_MODE_NAME (mode));
2792 if (flag_pic && SYMBOLIC_CONST (x))
2793 return legitimize_pic_address (x, 0);
2795 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2796 if (GET_CODE (x) == ASHIFT
2797 && GET_CODE (XEXP (x, 1)) == CONST_INT
2798 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
2801 x = gen_rtx (MULT, Pmode, force_reg (Pmode, XEXP (x, 0)),
2802 GEN_INT (1 << log));
2805 if (GET_CODE (x) == PLUS)
2807 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
2809 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2810 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2811 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
2814 XEXP (x, 0) = gen_rtx (MULT, Pmode,
2815 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
2816 GEN_INT (1 << log));
2819 if (GET_CODE (XEXP (x, 1)) == ASHIFT
2820 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2821 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
2824 XEXP (x, 1) = gen_rtx (MULT, Pmode,
2825 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
2826 GEN_INT (1 << log));
2829 /* Put multiply first if it isn't already. */
2830 if (GET_CODE (XEXP (x, 1)) == MULT)
2832 rtx tmp = XEXP (x, 0);
2833 XEXP (x, 0) = XEXP (x, 1);
2838 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2839 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2840 created by virtual register instantiation, register elimination, and
2841 similar optimizations. */
2842 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
2845 x = gen_rtx (PLUS, Pmode,
2846 gen_rtx (PLUS, Pmode, XEXP (x, 0),
2847 XEXP (XEXP (x, 1), 0)),
2848 XEXP (XEXP (x, 1), 1));
2852 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2853 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2854 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2855 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2856 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2857 && CONSTANT_P (XEXP (x, 1)))
2860 rtx other = NULL_RTX;
2862 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2864 constant = XEXP (x, 1);
2865 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2867 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2869 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2870 other = XEXP (x, 1);
2878 x = gen_rtx (PLUS, Pmode,
2879 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
2880 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2881 plus_constant (other, INTVAL (constant)));
2885 if (changed && legitimate_address_p (mode, x, FALSE))
2888 if (GET_CODE (XEXP (x, 0)) == MULT)
2891 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
2894 if (GET_CODE (XEXP (x, 1)) == MULT)
2897 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
2901 && GET_CODE (XEXP (x, 1)) == REG
2902 && GET_CODE (XEXP (x, 0)) == REG)
2905 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
2908 x = legitimize_pic_address (x, 0);
2911 if (changed && legitimate_address_p (mode, x, FALSE))
2914 if (GET_CODE (XEXP (x, 0)) == REG)
2916 register rtx temp = gen_reg_rtx (Pmode);
2917 register rtx val = force_operand (XEXP (x, 1), temp);
2919 emit_move_insn (temp, val);
2925 else if (GET_CODE (XEXP (x, 1)) == REG)
2927 register rtx temp = gen_reg_rtx (Pmode);
2928 register rtx val = force_operand (XEXP (x, 0), temp);
2930 emit_move_insn (temp, val);
2940 /* Print an integer constant expression in assembler syntax. Addition
2941 and subtraction are the only arithmetic that may appear in these
2942 expressions. FILE is the stdio stream to write to, X is the rtx, and
2943 CODE is the operand print code from the output string. */
2946 output_pic_addr_const (file, x, code)
2953 switch (GET_CODE (x))
2964 if (GET_CODE (x) == SYMBOL_REF)
2965 assemble_name (file, XSTR (x, 0));
2968 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
2969 CODE_LABEL_NUMBER (XEXP (x, 0)));
2970 assemble_name (asm_out_file, buf);
2973 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
2974 fprintf (file, "@GOTOFF(%%ebx)");
2975 else if (code == 'P')
2976 fprintf (file, "@PLT");
2977 else if (GET_CODE (x) == LABEL_REF)
2978 fprintf (file, "@GOTOFF");
2979 else if (! SYMBOL_REF_FLAG (x))
2980 fprintf (file, "@GOT");
2982 fprintf (file, "@GOTOFF");
2987 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
2988 assemble_name (asm_out_file, buf);
2992 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
2996 /* This used to output parentheses around the expression,
2997 but that does not work on the 386 (either ATT or BSD assembler). */
2998 output_pic_addr_const (file, XEXP (x, 0), code);
3002 if (GET_MODE (x) == VOIDmode)
3004 /* We can use %d if the number is <32 bits and positive. */
3005 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
3006 fprintf (file, "0x%lx%08lx",
3007 (unsigned long) CONST_DOUBLE_HIGH (x),
3008 (unsigned long) CONST_DOUBLE_LOW (x));
3010 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
3013 /* We can't handle floating point constants;
3014 PRINT_OPERAND must handle them. */
3015 output_operand_lossage ("floating constant misused");
3019 /* Some assemblers need integer constants to appear first. */
3020 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3022 output_pic_addr_const (file, XEXP (x, 0), code);
3023 if (INTVAL (XEXP (x, 1)) >= 0)
3024 fprintf (file, "+");
3025 output_pic_addr_const (file, XEXP (x, 1), code);
3029 output_pic_addr_const (file, XEXP (x, 1), code);
3030 if (INTVAL (XEXP (x, 0)) >= 0)
3031 fprintf (file, "+");
3032 output_pic_addr_const (file, XEXP (x, 0), code);
3037 output_pic_addr_const (file, XEXP (x, 0), code);
3038 fprintf (file, "-");
3039 output_pic_addr_const (file, XEXP (x, 1), code);
3043 output_operand_lossage ("invalid expression as operand");
3047 /* Append the correct conditional move suffix which corresponds to CODE. */
3050 put_condition_code (code, reverse_cc, mode, file)
3053 enum mode_class mode;
3056 int ieee = (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
3057 && ! (cc_prev_status.flags & CC_FCOMI));
3058 if (reverse_cc && ! ieee)
3059 code = reverse_condition (code);
3061 if (mode == MODE_INT)
3065 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3072 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3111 output_operand_lossage ("Invalid %%C operand");
3114 else if (mode == MODE_FLOAT)
3118 fputs (ieee ? (reverse_cc ? "ne" : "e") : "ne", file);
3121 fputs (ieee ? (reverse_cc ? "ne" : "e") : "e", file);
3124 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3127 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3130 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3133 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3136 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3139 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3142 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3145 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3148 output_operand_lossage ("Invalid %%C operand");
3153 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
3154 C -- print opcode suffix for set/cmov insn.
3155 c -- like C, but print reversed condition
3156 F -- print opcode suffix for fcmov insn.
3157 f -- like C, but print reversed condition
3158 R -- print the prefix for register names.
3159 z -- print the opcode suffix for the size of the current operand.
3160 * -- print a star (in certain assembler syntax)
3161 w -- print the operand as if it's a "word" (HImode) even if it isn't.
3162 c -- don't print special prefixes before constant operands.
3163 J -- print the appropriate jump operand.
3164 s -- print a shift double count, followed by the assemblers argument
3166 b -- print the QImode name of the register for the indicated operand.
3167 %b0 would print %al if operands[0] is reg 0.
3168 w -- likewise, print the HImode name of the register.
3169 k -- likewise, print the SImode name of the register.
3170 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
3171 y -- print "st(0)" instead of "st" as a register.
3172 P -- print as a PIC constant */
3175 print_operand (file, x, code)
3190 PUT_OP_SIZE (code, 'l', file);
3194 PUT_OP_SIZE (code, 'w', file);
3198 PUT_OP_SIZE (code, 'b', file);
3202 PUT_OP_SIZE (code, 'l', file);
3206 PUT_OP_SIZE (code, 's', file);
3210 PUT_OP_SIZE (code, 't', file);
3214 /* 387 opcodes don't get size suffixes if the operands are
3217 if (STACK_REG_P (x))
3220 /* this is the size of op from size of operand */
3221 switch (GET_MODE_SIZE (GET_MODE (x)))
3224 PUT_OP_SIZE ('B', 'b', file);
3228 PUT_OP_SIZE ('W', 'w', file);
3232 if (GET_MODE (x) == SFmode)
3234 PUT_OP_SIZE ('S', 's', file);
3238 PUT_OP_SIZE ('L', 'l', file);
3242 PUT_OP_SIZE ('T', 't', file);
3246 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
3248 #ifdef GAS_MNEMONICS
3249 PUT_OP_SIZE ('Q', 'q', file);
3252 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
3256 PUT_OP_SIZE ('Q', 'l', file);
3269 switch (GET_CODE (x))
3271 /* These conditions are appropriate for testing the result
3272 of an arithmetic operation, not for a compare operation.
3273 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume
3274 CC_Z_IN_NOT_C false and not floating point. */
3275 case NE: fputs ("jne", file); return;
3276 case EQ: fputs ("je", file); return;
3277 case GE: fputs ("jns", file); return;
3278 case LT: fputs ("js", file); return;
3279 case GEU: fputs ("jmp", file); return;
3280 case GTU: fputs ("jne", file); return;
3281 case LEU: fputs ("je", file); return;
3282 case LTU: fputs ("#branch never", file); return;
3284 /* no matching branches for GT nor LE */
3291 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
3293 PRINT_OPERAND (file, x, 0);
3294 fputs (AS2C (,) + 1, file);
3299 /* This is used by the conditional move instructions. */
3301 put_condition_code (GET_CODE (x), 0, MODE_INT, file);
3304 /* Like above, but reverse condition */
3306 put_condition_code (GET_CODE (x), 1, MODE_INT, file); return;
3309 put_condition_code (GET_CODE (x), 0, MODE_FLOAT, file);
3312 /* Like above, but reverse condition */
3314 put_condition_code (GET_CODE (x), 1, MODE_FLOAT, file);
3321 sprintf (str, "invalid operand code `%c'", code);
3322 output_operand_lossage (str);
3327 if (GET_CODE (x) == REG)
3329 PRINT_REG (x, code, file);
3332 else if (GET_CODE (x) == MEM)
3334 PRINT_PTR (x, file);
3335 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
3338 output_pic_addr_const (file, XEXP (x, 0), code);
3340 output_addr_const (file, XEXP (x, 0));
3343 output_address (XEXP (x, 0));
3346 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
3351 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3352 REAL_VALUE_TO_TARGET_SINGLE (r, l);
3353 PRINT_IMMED_PREFIX (file);
3354 fprintf (file, "0x%x", l);
3357 /* These float cases don't actually occur as immediate operands. */
3358 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
3363 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3364 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3365 fprintf (file, "%s", dstr);
3368 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
3373 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3374 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3375 fprintf (file, "%s", dstr);
3381 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3382 PRINT_IMMED_PREFIX (file);
3383 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
3384 || GET_CODE (x) == LABEL_REF)
3385 PRINT_OFFSET_PREFIX (file);
3388 output_pic_addr_const (file, x, code);
3390 output_addr_const (file, x);
3394 /* Print a memory operand whose address is ADDR. */
3397 print_operand_address (file, addr)
3401 register rtx reg1, reg2, breg, ireg;
3404 switch (GET_CODE (addr))
3408 fprintf (file, "%se", RP);
3409 fputs (hi_reg_name[REGNO (addr)], file);
3419 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
3421 offset = XEXP (addr, 0);
3422 addr = XEXP (addr, 1);
3424 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
3426 offset = XEXP (addr, 1);
3427 addr = XEXP (addr, 0);
3430 if (GET_CODE (addr) != PLUS)
3432 else if (GET_CODE (XEXP (addr, 0)) == MULT)
3433 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3434 else if (GET_CODE (XEXP (addr, 1)) == MULT)
3435 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3436 else if (GET_CODE (XEXP (addr, 0)) == REG)
3437 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3438 else if (GET_CODE (XEXP (addr, 1)) == REG)
3439 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3441 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
3458 if ((reg1 && GET_CODE (reg1) == MULT)
3459 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
3464 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
3470 if (ireg != 0 || breg != 0)
3477 output_pic_addr_const (file, addr, 0);
3478 else if (GET_CODE (addr) == LABEL_REF)
3479 output_asm_label (addr);
3481 output_addr_const (file, addr);
3484 if (ireg != 0 && GET_CODE (ireg) == MULT)
3486 scale = INTVAL (XEXP (ireg, 1));
3487 ireg = XEXP (ireg, 0);
3490 /* The stack pointer can only appear as a base register,
3491 never an index register, so exchange the regs if it is wrong. */
3493 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
3502 /* output breg+ireg*scale */
3503 PRINT_B_I_S (breg, ireg, scale, file);
3511 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
3513 scale = INTVAL (XEXP (addr, 0));
3514 ireg = XEXP (addr, 1);
3518 scale = INTVAL (XEXP (addr, 1));
3519 ireg = XEXP (addr, 0);
3522 output_addr_const (file, const0_rtx);
3523 PRINT_B_I_S (NULL_RTX, ireg, scale, file);
3528 if (GET_CODE (addr) == CONST_INT
3529 && INTVAL (addr) < 0x8000
3530 && INTVAL (addr) >= -0x8000)
3531 fprintf (file, "%d", (int) INTVAL (addr));
3535 output_pic_addr_const (file, addr, 0);
3537 output_addr_const (file, addr);
3542 /* Set the cc_status for the results of an insn whose pattern is EXP.
3543 On the 80386, we assume that only test and compare insns, as well
3544 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT,
3545 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
3546 Also, we assume that jumps, moves and sCOND don't affect the condition
3547 codes. All else clobbers the condition codes, by assumption.
3549 We assume that ALL integer add, minus, etc. instructions effect the
3550 condition codes. This MUST be consistent with i386.md.
3552 We don't record any float test or compare - the redundant test &
3553 compare check in final.c does not handle stack-like regs correctly. */
3556 notice_update_cc (exp)
3559 if (GET_CODE (exp) == SET)
3561 /* Jumps do not alter the cc's. */
3562 if (SET_DEST (exp) == pc_rtx)
3565 /* Moving register or memory into a register:
3566 it doesn't alter the cc's, but it might invalidate
3567 the RTX's which we remember the cc's came from.
3568 (Note that moving a constant 0 or 1 MAY set the cc's). */
3569 if (REG_P (SET_DEST (exp))
3570 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
3571 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
3573 if (cc_status.value1
3574 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3575 cc_status.value1 = 0;
3577 if (cc_status.value2
3578 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3579 cc_status.value2 = 0;
3584 /* Moving register into memory doesn't alter the cc's.
3585 It may invalidate the RTX's which we remember the cc's came from. */
3586 if (GET_CODE (SET_DEST (exp)) == MEM
3587 && (REG_P (SET_SRC (exp))
3588 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
3590 if (cc_status.value1
3591 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3592 cc_status.value1 = 0;
3593 if (cc_status.value2
3594 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3595 cc_status.value2 = 0;
3600 /* Function calls clobber the cc's. */
3601 else if (GET_CODE (SET_SRC (exp)) == CALL)
3607 /* Tests and compares set the cc's in predictable ways. */
3608 else if (SET_DEST (exp) == cc0_rtx)
3611 cc_status.value1 = SET_SRC (exp);
3615 /* Certain instructions effect the condition codes. */
3616 else if (GET_MODE (SET_SRC (exp)) == SImode
3617 || GET_MODE (SET_SRC (exp)) == HImode
3618 || GET_MODE (SET_SRC (exp)) == QImode)
3619 switch (GET_CODE (SET_SRC (exp)))
3621 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
3622 /* Shifts on the 386 don't set the condition codes if the
3623 shift count is zero. */
3624 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
3630 /* We assume that the CONST_INT is non-zero (this rtx would
3631 have been deleted if it were zero. */
3633 case PLUS: case MINUS: case NEG:
3634 case AND: case IOR: case XOR:
3635 cc_status.flags = CC_NO_OVERFLOW;
3636 cc_status.value1 = SET_SRC (exp);
3637 cc_status.value2 = SET_DEST (exp);
3648 else if (GET_CODE (exp) == PARALLEL
3649 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3651 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
3653 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
3657 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
3659 cc_status.flags |= CC_IN_80387;
3660 if (TARGET_CMOVE && stack_regs_mentioned_p
3661 (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1)))
3662 cc_status.flags |= CC_FCOMI;
3665 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
3677 /* Split one or more DImode RTL references into pairs of SImode
3678 references. The RTL can be REG, offsettable MEM, integer constant, or
3679 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3680 split and "num" is its length. lo_half and hi_half are output arrays
3681 that parallel "operands". */
3684 split_di (operands, num, lo_half, hi_half)
3687 rtx lo_half[], hi_half[];
3691 if (GET_CODE (operands[num]) == REG)
3693 lo_half[num] = gen_rtx_REG (SImode, REGNO (operands[num]));
3694 hi_half[num] = gen_rtx_REG (SImode, REGNO (operands[num]) + 1);
3696 else if (CONSTANT_P (operands[num]))
3697 split_double (operands[num], &lo_half[num], &hi_half[num]);
3698 else if (offsettable_memref_p (operands[num]))
3700 lo_half[num] = operands[num];
3701 hi_half[num] = adj_offsettable_operand (operands[num], 4);
3708 /* Return 1 if this is a valid binary operation on a 387.
3709 OP is the expression matched, and MODE is its mode. */
3712 binary_387_op (op, mode)
3714 enum machine_mode mode;
3716 if (mode != VOIDmode && mode != GET_MODE (op))
3719 switch (GET_CODE (op))
3725 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
3732 /* Return 1 if this is a valid shift or rotate operation on a 386.
3733 OP is the expression matched, and MODE is its mode. */
3738 enum machine_mode mode;
3740 rtx operand = XEXP (op, 0);
3742 if (mode != VOIDmode && mode != GET_MODE (op))
3745 if (GET_MODE (operand) != GET_MODE (op)
3746 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
3749 return (GET_CODE (op) == ASHIFT
3750 || GET_CODE (op) == ASHIFTRT
3751 || GET_CODE (op) == LSHIFTRT
3752 || GET_CODE (op) == ROTATE
3753 || GET_CODE (op) == ROTATERT);
3756 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
3757 MODE is not used. */
3760 VOIDmode_compare_op (op, mode)
3762 enum machine_mode mode;
3764 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
3767 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
3768 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
3769 is the expression of the binary operation. The output may either be
3770 emitted here, or returned to the caller, like all output_* functions.
3772 There is no guarantee that the operands are the same mode, as they
3773 might be within FLOAT or FLOAT_EXTEND expressions. */
3776 output_387_binary_op (insn, operands)
3782 static char buf[100];
3784 switch (GET_CODE (operands[3]))
3787 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
3788 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
3795 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
3796 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
3803 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
3804 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
3811 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
3812 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
3822 strcpy (buf, base_op);
3824 switch (GET_CODE (operands[3]))
3828 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
3831 operands[2] = operands[1];
3835 if (GET_CODE (operands[2]) == MEM)
3836 return strcat (buf, AS1 (%z2,%2));
3838 if (NON_STACK_REG_P (operands[1]))
3840 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
3844 else if (NON_STACK_REG_P (operands[2]))
3846 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
3850 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3851 return strcat (buf, AS2 (p,%2,%0));
3853 if (STACK_TOP_P (operands[0]))
3854 return strcat (buf, AS2C (%y2,%0));
3856 return strcat (buf, AS2C (%2,%0));
3860 if (GET_CODE (operands[1]) == MEM)
3861 return strcat (buf, AS1 (r%z1,%1));
3863 if (GET_CODE (operands[2]) == MEM)
3864 return strcat (buf, AS1 (%z2,%2));
3866 if (NON_STACK_REG_P (operands[1]))
3868 output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
3872 else if (NON_STACK_REG_P (operands[2]))
3874 output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
3878 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
3881 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3882 return strcat (buf, AS2 (rp,%2,%0));
3884 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3885 return strcat (buf, AS2 (p,%1,%0));
3887 if (STACK_TOP_P (operands[0]))
3889 if (STACK_TOP_P (operands[1]))
3890 return strcat (buf, AS2C (%y2,%0));
3892 return strcat (buf, AS2 (r,%y1,%0));
3894 else if (STACK_TOP_P (operands[1]))
3895 return strcat (buf, AS2C (%1,%0));
3897 return strcat (buf, AS2 (r,%2,%0));
3904 /* Output code for INSN to convert a float to a signed int. OPERANDS
3905 are the insn operands. The output may be SFmode or DFmode and the
3906 input operand may be SImode or DImode. As a special case, make sure
3907 that the 387 stack top dies if the output mode is DImode, because the
3908 hardware requires this. */
3911 output_fix_trunc (insn, operands)
3915 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
3918 if (! STACK_TOP_P (operands[1])
3919 || (GET_MODE (operands[0]) == DImode && ! stack_top_dies))
3922 xops[0] = GEN_INT (12);
3923 xops[1] = operands[4];
3925 output_asm_insn (AS1 (fnstc%W2,%2), operands);
3926 output_asm_insn (AS2 (mov%L2,%2,%4), operands);
3927 output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
3928 output_asm_insn (AS2 (mov%L4,%4,%3), operands);
3929 output_asm_insn (AS1 (fldc%W3,%3), operands);
3931 if (NON_STACK_REG_P (operands[0]))
3932 output_to_reg (operands[0], stack_top_dies, operands[3]);
3934 else if (GET_CODE (operands[0]) == MEM)
3937 output_asm_insn (AS1 (fistp%z0,%0), operands);
3939 output_asm_insn (AS1 (fist%z0,%0), operands);
3944 return AS1 (fldc%W2,%2);
3947 /* Output code for INSN to compare OPERANDS. The two operands might
3948 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
3949 expression. If the compare is in mode CCFPEQmode, use an opcode that
3950 will not fault if a qNaN is present. */
3953 output_float_compare (insn, operands)
3958 rtx body = XVECEXP (PATTERN (insn), 0, 0);
3959 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
3962 if (TARGET_CMOVE && STACK_REG_P (operands[1]))
3964 cc_status.flags |= CC_FCOMI;
3965 cc_prev_status.flags &= ~CC_TEST_AX;
3968 if (! STACK_TOP_P (operands[0]))
3971 operands[0] = operands[1];
3973 cc_status.flags |= CC_REVERSED;
3976 if (! STACK_TOP_P (operands[0]))
3979 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
3981 if (STACK_REG_P (operands[1])
3983 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3984 && REGNO (operands[1]) != FIRST_STACK_REG)
3986 /* If both the top of the 387 stack dies, and the other operand
3987 is also a stack register that dies, then this must be a
3988 `fcompp' float compare */
3990 if (unordered_compare)
3992 if (cc_status.flags & CC_FCOMI)
3994 output_asm_insn (AS2 (fucomip,%y1,%0), operands);
3995 output_asm_insn (AS1 (fstp, %y0), operands);
3999 output_asm_insn ("fucompp", operands);
4003 if (cc_status.flags & CC_FCOMI)
4005 output_asm_insn (AS2 (fcomip, %y1,%0), operands);
4006 output_asm_insn (AS1 (fstp, %y0), operands);
4010 output_asm_insn ("fcompp", operands);
4015 static char buf[100];
4017 /* Decide if this is the integer or float compare opcode, or the
4018 unordered float compare. */
4020 if (unordered_compare)
4021 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fucomi" : "fucom");
4022 else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
4023 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fcomi" : "fcom");
4025 strcpy (buf, "ficom");
4027 /* Modify the opcode if the 387 stack is to be popped. */
4032 if (NON_STACK_REG_P (operands[1]))
4033 output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
4034 else if (cc_status.flags & CC_FCOMI)
4036 output_asm_insn (strcat (buf, AS2 (%z1,%y1,%0)), operands);
4040 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
4043 /* Now retrieve the condition code. */
4045 return output_fp_cc0_set (insn);
4048 /* Output opcodes to transfer the results of FP compare or test INSN
4049 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
4050 result of the compare or test is unordered, no comparison operator
4051 succeeds except NE. Return an output template, if any. */
4054 output_fp_cc0_set (insn)
4061 xops[0] = gen_rtx_REG (HImode, 0);
4062 output_asm_insn (AS1 (fnsts%W0,%0), xops);
4064 if (! TARGET_IEEE_FP)
4066 if (!(cc_status.flags & CC_REVERSED))
4068 next = next_cc0_user (insn);
4070 if (GET_CODE (next) == JUMP_INSN
4071 && GET_CODE (PATTERN (next)) == SET
4072 && SET_DEST (PATTERN (next)) == pc_rtx
4073 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4074 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4075 else if (GET_CODE (PATTERN (next)) == SET)
4076 code = GET_CODE (SET_SRC (PATTERN (next)));
4080 if (code == GT || code == LT || code == EQ || code == NE
4081 || code == LE || code == GE)
4083 /* We will test eax directly. */
4084 cc_status.flags |= CC_TEST_AX;
4092 next = next_cc0_user (insn);
4093 if (next == NULL_RTX)
4096 if (GET_CODE (next) == JUMP_INSN
4097 && GET_CODE (PATTERN (next)) == SET
4098 && SET_DEST (PATTERN (next)) == pc_rtx
4099 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4100 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4101 else if (GET_CODE (PATTERN (next)) == SET)
4103 if (GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4104 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4106 code = GET_CODE (SET_SRC (PATTERN (next)));
4109 else if (GET_CODE (PATTERN (next)) == PARALLEL
4110 && GET_CODE (XVECEXP (PATTERN (next), 0, 0)) == SET)
4112 if (GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))) == IF_THEN_ELSE)
4113 code = GET_CODE (XEXP (SET_SRC (XVECEXP (PATTERN (next), 0, 0)), 0));
4115 code = GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0)));
4120 xops[0] = gen_rtx_REG (QImode, 0);
4125 xops[1] = GEN_INT (0x45);
4126 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4131 xops[1] = GEN_INT (0x45);
4132 xops[2] = GEN_INT (0x01);
4133 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4134 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4139 xops[1] = GEN_INT (0x05);
4140 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4145 xops[1] = GEN_INT (0x45);
4146 xops[2] = GEN_INT (0x40);
4147 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4148 output_asm_insn (AS1 (dec%B0,%h0), xops);
4149 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4154 xops[1] = GEN_INT (0x45);
4155 xops[2] = GEN_INT (0x40);
4156 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4157 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4162 xops[1] = GEN_INT (0x44);
4163 xops[2] = GEN_INT (0x40);
4164 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4165 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
4180 #define MAX_386_STACK_LOCALS 2
4182 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4184 /* Define the structure for the machine field in struct function. */
4185 struct machine_function
4187 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4189 char pic_label_name[256];
4192 /* Functions to save and restore i386_stack_locals.
4193 These will be called, via pointer variables,
4194 from push_function_context and pop_function_context. */
4197 save_386_machine_status (p)
4201 = (struct machine_function *) xmalloc (sizeof (struct machine_function));
4202 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
4203 sizeof i386_stack_locals);
4204 p->machine->pic_label_rtx = pic_label_rtx;
4205 bcopy (pic_label_name, p->machine->pic_label_name, 256);
4209 restore_386_machine_status (p)
4212 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
4213 sizeof i386_stack_locals);
4214 pic_label_rtx = p->machine->pic_label_rtx;
4215 bcopy (p->machine->pic_label_name, pic_label_name, 256);
4220 /* Clear stack slot assignments remembered from previous functions.
4221 This is called from INIT_EXPANDERS once before RTL is emitted for each
4225 clear_386_stack_locals ()
4227 enum machine_mode mode;
4230 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
4231 mode = (enum machine_mode) ((int) mode + 1))
4232 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
4233 i386_stack_locals[(int) mode][n] = NULL_RTX;
4235 pic_label_rtx = NULL_RTX;
4236 bzero (pic_label_name, 256);
4237 /* Arrange to save and restore i386_stack_locals around nested functions. */
4238 save_machine_status = save_386_machine_status;
4239 restore_machine_status = restore_386_machine_status;
4242 /* Return a MEM corresponding to a stack slot with mode MODE.
4243 Allocate a new slot if necessary.
4245 The RTL for a function can have several slots available: N is
4246 which slot to use. */
4249 assign_386_stack_local (mode, n)
4250 enum machine_mode mode;
4253 if (n < 0 || n >= MAX_386_STACK_LOCALS)
4256 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
4257 i386_stack_locals[(int) mode][n]
4258 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
4260 return i386_stack_locals[(int) mode][n];
4265 enum machine_mode mode;
4267 return (GET_CODE (op) == MULT);
4272 enum machine_mode mode;
4274 return (GET_CODE (op) == DIV);
4278 /* Create a new copy of an rtx.
4279 Recursively copies the operands of the rtx,
4280 except for those few rtx codes that are sharable.
4281 Doesn't share CONST */
4289 register RTX_CODE code;
4290 register char *format_ptr;
4292 code = GET_CODE (orig);
4305 /* SCRATCH must be shared because they represent distinct values. */
4310 /* CONST can be shared if it contains a SYMBOL_REF. If it contains
4311 a LABEL_REF, it isn't sharable. */
4312 if (GET_CODE (XEXP (orig, 0)) == PLUS
4313 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
4314 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
4318 /* A MEM with a constant address is not sharable. The problem is that
4319 the constant address may need to be reloaded. If the mem is shared,
4320 then reloading one copy of this mem will cause all copies to appear
4321 to have been reloaded. */
4324 copy = rtx_alloc (code);
4325 PUT_MODE (copy, GET_MODE (orig));
4326 copy->in_struct = orig->in_struct;
4327 copy->volatil = orig->volatil;
4328 copy->unchanging = orig->unchanging;
4329 copy->integrated = orig->integrated;
4331 copy->is_spill_rtx = orig->is_spill_rtx;
4333 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
4335 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
4337 switch (*format_ptr++)
4340 XEXP (copy, i) = XEXP (orig, i);
4341 if (XEXP (orig, i) != NULL)
4342 XEXP (copy, i) = copy_rtx (XEXP (orig, i));
4347 XEXP (copy, i) = XEXP (orig, i);
4352 XVEC (copy, i) = XVEC (orig, i);
4353 if (XVEC (orig, i) != NULL)
4355 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
4356 for (j = 0; j < XVECLEN (copy, i); j++)
4357 XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
4362 XWINT (copy, i) = XWINT (orig, i);
4366 XINT (copy, i) = XINT (orig, i);
4371 XSTR (copy, i) = XSTR (orig, i);
4382 /* Try to rewrite a memory address to make it valid */
4385 rewrite_address (mem_rtx)
4388 rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
4390 int offset_adjust = 0;
4391 int was_only_offset = 0;
4392 rtx mem_addr = XEXP (mem_rtx, 0);
4393 char *storage = oballoc (0);
4395 int is_spill_rtx = 0;
4397 in_struct = MEM_IN_STRUCT_P (mem_rtx);
4398 is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
4400 if (GET_CODE (mem_addr) == PLUS
4401 && GET_CODE (XEXP (mem_addr, 1)) == PLUS
4402 && GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
4404 /* This part is utilized by the combiner. */
4406 = gen_rtx (PLUS, GET_MODE (mem_addr),
4407 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
4408 XEXP (mem_addr, 0), XEXP (XEXP (mem_addr, 1), 0)),
4409 XEXP (XEXP (mem_addr, 1), 1));
4411 if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
4413 XEXP (mem_rtx, 0) = ret_rtx;
4414 RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
4421 /* This part is utilized by loop.c.
4422 If the address contains PLUS (reg,const) and this pattern is invalid
4423 in this case - try to rewrite the address to make it valid. */
4424 storage = oballoc (0);
4425 index_rtx = base_rtx = offset_rtx = NULL;
4427 /* Find the base index and offset elements of the memory address. */
4428 if (GET_CODE (mem_addr) == PLUS)
4430 if (GET_CODE (XEXP (mem_addr, 0)) == REG)
4432 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4433 base_rtx = XEXP (mem_addr, 1), index_rtx = XEXP (mem_addr, 0);
4435 base_rtx = XEXP (mem_addr, 0), offset_rtx = XEXP (mem_addr, 1);
4438 else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
4440 index_rtx = XEXP (mem_addr, 0);
4441 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4442 base_rtx = XEXP (mem_addr, 1);
4444 offset_rtx = XEXP (mem_addr, 1);
4447 else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
4449 if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS
4450 && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT
4451 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0))
4453 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1))
4455 && (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1))
4457 && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG
4458 && GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
4460 index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
4461 offset_rtx = XEXP (mem_addr, 1);
4462 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4463 offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
4467 offset_rtx = XEXP (mem_addr, 1);
4468 index_rtx = XEXP (XEXP (mem_addr, 0), 0);
4469 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4473 else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
4475 was_only_offset = 1;
4478 offset_rtx = XEXP (mem_addr, 1);
4479 offset_adjust = INTVAL (XEXP (mem_addr, 0));
4480 if (offset_adjust == 0)
4482 XEXP (mem_rtx, 0) = offset_rtx;
4483 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4493 else if (GET_CODE (mem_addr) == MULT)
4494 index_rtx = mem_addr;
4501 if (index_rtx != 0 && GET_CODE (index_rtx) == MULT)
4503 if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
4509 scale_rtx = XEXP (index_rtx, 1);
4510 scale = INTVAL (scale_rtx);
4511 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4514 /* Now find which of the elements are invalid and try to fix them. */
4515 if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
4517 offset_adjust = INTVAL (index_rtx) * scale;
4519 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4520 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4521 else if (offset_rtx == 0)
4522 offset_rtx = const0_rtx;
4524 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4525 XEXP (mem_rtx, 0) = offset_rtx;
4529 if (base_rtx && GET_CODE (base_rtx) == PLUS
4530 && GET_CODE (XEXP (base_rtx, 0)) == REG
4531 && GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
4533 offset_adjust += INTVAL (XEXP (base_rtx, 1));
4534 base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
4537 else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
4539 offset_adjust += INTVAL (base_rtx);
4543 if (index_rtx && GET_CODE (index_rtx) == PLUS
4544 && GET_CODE (XEXP (index_rtx, 0)) == REG
4545 && GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
4547 offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
4548 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4553 if (! LEGITIMATE_INDEX_P (index_rtx)
4554 && ! (index_rtx == stack_pointer_rtx && scale == 1
4555 && base_rtx == NULL))
4564 if (! LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
4571 if (offset_adjust != 0)
4573 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4574 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4576 offset_rtx = const0_rtx;
4584 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
4585 gen_rtx (MULT, GET_MODE (index_rtx),
4586 index_rtx, scale_rtx),
4589 if (GET_CODE (offset_rtx) != CONST_INT
4590 || INTVAL (offset_rtx) != 0)
4591 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4592 ret_rtx, offset_rtx);
4596 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4597 index_rtx, base_rtx);
4599 if (GET_CODE (offset_rtx) != CONST_INT
4600 || INTVAL (offset_rtx) != 0)
4601 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4602 ret_rtx, offset_rtx);
4609 ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx),
4610 index_rtx, scale_rtx);
4612 if (GET_CODE (offset_rtx) != CONST_INT
4613 || INTVAL (offset_rtx) != 0)
4614 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4615 ret_rtx, offset_rtx);
4619 if (GET_CODE (offset_rtx) == CONST_INT
4620 && INTVAL (offset_rtx) == 0)
4621 ret_rtx = index_rtx;
4623 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4624 index_rtx, offset_rtx);
4632 if (GET_CODE (offset_rtx) == CONST_INT
4633 && INTVAL (offset_rtx) == 0)
4636 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx,
4639 else if (was_only_offset)
4640 ret_rtx = offset_rtx;
4648 XEXP (mem_rtx, 0) = ret_rtx;
4649 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4660 /* Return 1 if the first insn to set cc before INSN also sets the register
4661 REG_RTX; otherwise return 0. */
4663 last_to_set_cc (reg_rtx, insn)
4666 rtx prev_insn = PREV_INSN (insn);
4670 if (GET_CODE (prev_insn) == NOTE)
4673 else if (GET_CODE (prev_insn) == INSN)
4675 if (GET_CODE (PATTERN (prev_insn)) != SET)
4678 if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
4680 if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
4686 else if (! doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
4693 prev_insn = PREV_INSN (prev_insn);
4700 doesnt_set_condition_code (pat)
4703 switch (GET_CODE (pat))
4716 sets_condition_code (pat)
4719 switch (GET_CODE (pat))
4741 str_immediate_operand (op, mode)
4743 enum machine_mode mode;
4745 if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
4755 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4756 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4757 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4758 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode))
4764 /* Return 1 if the mode of the SET_DEST of insn is floating point
4765 and it is not an fld or a move from memory to memory.
4766 Otherwise return 0 */
4772 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4773 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4774 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4775 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
4776 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
4777 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
4778 && GET_CODE (SET_SRC (insn)) != MEM)
4784 /* Return 1 if the mode of the SET_DEST of INSN is floating point and is
4785 memory and the source is a register. */
4791 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4792 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4793 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4794 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
4795 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
4796 && GET_CODE (SET_SRC (PATTERN (insn))) == REG)
4802 /* Return 1 if DEP_INSN sets a register which INSN uses as a base
4803 or index to reference memory.
4804 otherwise return 0 */
4807 agi_dependent (insn, dep_insn)
4810 if (GET_CODE (dep_insn) == INSN
4811 && GET_CODE (PATTERN (dep_insn)) == SET
4812 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG)
4813 return reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn);
4815 if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
4816 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
4817 && push_operand (SET_DEST (PATTERN (dep_insn)),
4818 GET_MODE (SET_DEST (PATTERN (dep_insn)))))
4819 return reg_mentioned_in_mem (stack_pointer_rtx, insn);
4824 /* Return 1 if reg is used in rtl as a base or index for a memory ref
4825 otherwise return 0. */
4828 reg_mentioned_in_mem (reg, rtl)
4833 register enum rtx_code code;
4838 code = GET_CODE (rtl);
4856 if (code == MEM && reg_mentioned_p (reg, rtl))
4859 fmt = GET_RTX_FORMAT (code);
4860 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4863 for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
4864 if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
4867 else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
4874 /* Output the appropriate insns for doing strlen if not just doing repnz; scasb
4876 operands[0] = result, initialized with the startaddress
4877 operands[1] = alignment of the address.
4878 operands[2] = scratch register, initialized with the startaddress when
4879 not aligned, otherwise undefined
4881 This is just the body. It needs the initialisations mentioned above and
4882 some address computing at the end. These things are done in i386.md. */
4885 output_strlen_unroll (operands)
4890 xops[0] = operands[0]; /* Result */
4891 /* operands[1]; * Alignment */
4892 xops[1] = operands[2]; /* Scratch */
4893 xops[2] = GEN_INT (0);
4894 xops[3] = GEN_INT (2);
4895 xops[4] = GEN_INT (3);
4896 xops[5] = GEN_INT (4);
4897 /* xops[6] = gen_label_rtx (); * label when aligned to 3-byte */
4898 /* xops[7] = gen_label_rtx (); * label when aligned to 2-byte */
4899 xops[8] = gen_label_rtx (); /* label of main loop */
4901 if (TARGET_USE_Q_REG && QI_REG_P (xops[1]))
4902 xops[9] = gen_label_rtx (); /* pentium optimisation */
4904 xops[10] = gen_label_rtx (); /* end label 2 */
4905 xops[11] = gen_label_rtx (); /* end label 1 */
4906 xops[12] = gen_label_rtx (); /* end label */
4907 /* xops[13] * Temporary used */
4908 xops[14] = GEN_INT (0xff);
4909 xops[15] = GEN_INT (0xff00);
4910 xops[16] = GEN_INT (0xff0000);
4911 xops[17] = GEN_INT (0xff000000);
4913 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
4915 /* Is there a known alignment and is it less than 4? */
4916 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4)
4918 /* Is there a known alignment and is it not 2? */
4919 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
4921 xops[6] = gen_label_rtx (); /* Label when aligned to 3-byte */
4922 xops[7] = gen_label_rtx (); /* Label when aligned to 2-byte */
4924 /* Leave just the 3 lower bits.
4925 If this is a q-register, then the high part is used later
4926 therefore use andl rather than andb. */
4927 output_asm_insn (AS2 (and%L1,%4,%1), xops);
4929 /* Is aligned to 4-byte address when zero */
4930 output_asm_insn (AS1 (je,%l8), xops);
4932 /* Side-effect even Parity when %eax == 3 */
4933 output_asm_insn (AS1 (jp,%6), xops);
4935 /* Is it aligned to 2 bytes ? */
4936 if (QI_REG_P (xops[1]))
4937 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
4939 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
4941 output_asm_insn (AS1 (je,%7), xops);
4945 /* Since the alignment is 2, we have to check 2 or 0 bytes;
4946 check if is aligned to 4 - byte. */
4947 output_asm_insn (AS2 (and%L1,%3,%1), xops);
4949 /* Is aligned to 4-byte address when zero */
4950 output_asm_insn (AS1 (je,%l8), xops);
4953 xops[13] = gen_rtx_MEM (QImode, xops[0]);
4955 /* Now compare the bytes; compare with the high part of a q-reg
4956 gives shorter code. */
4957 if (QI_REG_P (xops[1]))
4959 /* Compare the first n unaligned byte on a byte per byte basis. */
4960 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
4962 /* When zero we reached the end. */
4963 output_asm_insn (AS1 (je,%l12), xops);
4965 /* Increment the address. */
4966 output_asm_insn (AS1 (inc%L0,%0), xops);
4968 /* Not needed with an alignment of 2 */
4969 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
4971 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4972 CODE_LABEL_NUMBER (xops[7]));
4973 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
4974 output_asm_insn (AS1 (je,%l12), xops);
4975 output_asm_insn (AS1 (inc%L0,%0), xops);
4977 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4978 CODE_LABEL_NUMBER (xops[6]));
4981 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
4985 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
4986 output_asm_insn (AS1 (je,%l12), xops);
4987 output_asm_insn (AS1 (inc%L0,%0), xops);
4989 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4990 CODE_LABEL_NUMBER (xops[7]));
4991 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
4992 output_asm_insn (AS1 (je,%l12), xops);
4993 output_asm_insn (AS1 (inc%L0,%0), xops);
4995 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4996 CODE_LABEL_NUMBER (xops[6]));
4997 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5000 output_asm_insn (AS1 (je,%l12), xops);
5001 output_asm_insn (AS1 (inc%L0,%0), xops);
5004 /* Generate loop to check 4 bytes at a time. It is not a good idea to
5005 align this loop. It gives only huge programs, but does not help to
5007 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8]));
5009 xops[13] = gen_rtx_MEM (SImode, xops[0]);
5010 output_asm_insn (AS2 (mov%L1,%13,%1), xops);
5012 if (QI_REG_P (xops[1]))
5014 /* On i586 it is faster to combine the hi- and lo- part as
5015 a kind of lookahead. If anding both yields zero, then one
5016 of both *could* be zero, otherwise none of both is zero;
5017 this saves one instruction, on i486 this is slower
5018 tested with P-90, i486DX2-66, AMD486DX2-66 */
5021 output_asm_insn (AS2 (test%B1,%h1,%b1), xops);
5022 output_asm_insn (AS1 (jne,%l9), xops);
5025 /* Check first byte. */
5026 output_asm_insn (AS2 (test%B1,%b1,%b1), xops);
5027 output_asm_insn (AS1 (je,%l12), xops);
5029 /* Check second byte. */
5030 output_asm_insn (AS2 (test%B1,%h1,%h1), xops);
5031 output_asm_insn (AS1 (je,%l11), xops);
5034 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5035 CODE_LABEL_NUMBER (xops[9]));
5040 /* Check first byte. */
5041 output_asm_insn (AS2 (test%L1,%14,%1), xops);
5042 output_asm_insn (AS1 (je,%l12), xops);
5044 /* Check second byte. */
5045 output_asm_insn (AS2 (test%L1,%15,%1), xops);
5046 output_asm_insn (AS1 (je,%l11), xops);
5049 /* Check third byte. */
5050 output_asm_insn (AS2 (test%L1,%16,%1), xops);
5051 output_asm_insn (AS1 (je,%l10), xops);
5053 /* Check fourth byte and increment address. */
5054 output_asm_insn (AS2 (add%L0,%5,%0), xops);
5055 output_asm_insn (AS2 (test%L1,%17,%1), xops);
5056 output_asm_insn (AS1 (jne,%l8), xops);
5058 /* Now generate fixups when the compare stops within a 4-byte word. */
5059 output_asm_insn (AS2 (sub%L0,%4,%0), xops);
5061 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10]));
5062 output_asm_insn (AS1 (inc%L0,%0), xops);
5064 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11]));
5065 output_asm_insn (AS1 (inc%L0,%0), xops);
5067 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12]));