1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of loading integer registers */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1038 /* Generic64 should produce code tuned for Nocona and K8. */
1040 struct processor_costs generic64_cost = {
1041 COSTS_N_INSNS (1), /* cost of an add instruction */
1042 /* On all chips taken into consideration lea is 2 cycles and more. With
1043 this cost however our current implementation of synth_mult results in
1044 use of unnecessary temporary registers causing regression on several
1045 SPECfp benchmarks. */
1046 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1047 COSTS_N_INSNS (1), /* variable shift costs */
1048 COSTS_N_INSNS (1), /* constant shift costs */
1049 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1050 COSTS_N_INSNS (4), /* HI */
1051 COSTS_N_INSNS (3), /* SI */
1052 COSTS_N_INSNS (4), /* DI */
1053 COSTS_N_INSNS (2)}, /* other */
1054 0, /* cost of multiply per each bit set */
1055 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1056 COSTS_N_INSNS (26), /* HI */
1057 COSTS_N_INSNS (42), /* SI */
1058 COSTS_N_INSNS (74), /* DI */
1059 COSTS_N_INSNS (74)}, /* other */
1060 COSTS_N_INSNS (1), /* cost of movsx */
1061 COSTS_N_INSNS (1), /* cost of movzx */
1062 8, /* "large" insn */
1063 17, /* MOVE_RATIO */
1064 4, /* cost for loading QImode using movzbl */
1065 {4, 4, 4}, /* cost of loading integer registers
1066 in QImode, HImode and SImode.
1067 Relative to reg-reg move (2). */
1068 {4, 4, 4}, /* cost of storing integer registers */
1069 4, /* cost of reg,reg fld/fst */
1070 {12, 12, 12}, /* cost of loading fp registers
1071 in SFmode, DFmode and XFmode */
1072 {6, 6, 8}, /* cost of storing fp registers
1073 in SFmode, DFmode and XFmode */
1074 2, /* cost of moving MMX register */
1075 {8, 8}, /* cost of loading MMX registers
1076 in SImode and DImode */
1077 {8, 8}, /* cost of storing MMX registers
1078 in SImode and DImode */
1079 2, /* cost of moving SSE register */
1080 {8, 8, 8}, /* cost of loading SSE registers
1081 in SImode, DImode and TImode */
1082 {8, 8, 8}, /* cost of storing SSE registers
1083 in SImode, DImode and TImode */
1084 5, /* MMX or SSE register to integer */
1085 32, /* size of l1 cache. */
1086 512, /* size of l2 cache. */
1087 64, /* size of prefetch block */
1088 6, /* number of parallel prefetches */
1089 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1090 is increased to perhaps more appropriate value of 5. */
1091 3, /* Branch cost */
1092 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1093 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1094 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1095 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1096 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1097 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1098 {DUMMY_STRINGOP_ALGS,
1099 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1100 {DUMMY_STRINGOP_ALGS,
1101 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1102 1, /* scalar_stmt_cost. */
1103 1, /* scalar load_cost. */
1104 1, /* scalar_store_cost. */
1105 1, /* vec_stmt_cost. */
1106 1, /* vec_to_scalar_cost. */
1107 1, /* scalar_to_vec_cost. */
1108 1, /* vec_align_load_cost. */
1109 2, /* vec_unalign_load_cost. */
1110 1, /* vec_store_cost. */
1111 3, /* cond_taken_branch_cost. */
1112 1, /* cond_not_taken_branch_cost. */
1115 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1117 struct processor_costs generic32_cost = {
1118 COSTS_N_INSNS (1), /* cost of an add instruction */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 256, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 3, /* Branch cost */
1163 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1164 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1165 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1166 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1167 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1168 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1169 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1170 DUMMY_STRINGOP_ALGS},
1171 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1172 DUMMY_STRINGOP_ALGS},
1173 1, /* scalar_stmt_cost. */
1174 1, /* scalar load_cost. */
1175 1, /* scalar_store_cost. */
1176 1, /* vec_stmt_cost. */
1177 1, /* vec_to_scalar_cost. */
1178 1, /* scalar_to_vec_cost. */
1179 1, /* vec_align_load_cost. */
1180 2, /* vec_unalign_load_cost. */
1181 1, /* vec_store_cost. */
1182 3, /* cond_taken_branch_cost. */
1183 1, /* cond_not_taken_branch_cost. */
1186 const struct processor_costs *ix86_cost = &pentium_cost;
1188 /* Processor feature/optimization bitmasks. */
1189 #define m_386 (1<<PROCESSOR_I386)
1190 #define m_486 (1<<PROCESSOR_I486)
1191 #define m_PENT (1<<PROCESSOR_PENTIUM)
1192 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1193 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1194 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1195 #define m_CORE2 (1<<PROCESSOR_CORE2)
1197 #define m_GEODE (1<<PROCESSOR_GEODE)
1198 #define m_K6 (1<<PROCESSOR_K6)
1199 #define m_K6_GEODE (m_K6 | m_GEODE)
1200 #define m_K8 (1<<PROCESSOR_K8)
1201 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1202 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1203 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1204 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1206 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1207 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1209 /* Generic instruction choice should be common subset of supported CPUs
1210 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1211 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1213 /* Feature tests against the various tunings. */
1214 unsigned char ix86_tune_features[X86_TUNE_LAST];
1216 /* Feature tests against the various tunings used to create ix86_tune_features
1217 based on the processor mask. */
1218 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1219 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1220 negatively, so enabling for Generic64 seems like good code size
1221 tradeoff. We can't enable it for 32bit generic because it does not
1222 work well with PPro base chips. */
1223 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1225 /* X86_TUNE_PUSH_MEMORY */
1226 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1227 | m_NOCONA | m_CORE2 | m_GENERIC,
1229 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1232 /* X86_TUNE_USE_BIT_TEST */
1235 /* X86_TUNE_UNROLL_STRLEN */
1236 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1238 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1239 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1241 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1242 on simulation result. But after P4 was made, no performance benefit
1243 was observed with branch hints. It also increases the code size.
1244 As a result, icc never generates branch hints. */
1247 /* X86_TUNE_DOUBLE_WITH_ADD */
1250 /* X86_TUNE_USE_SAHF */
1251 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1252 | m_NOCONA | m_CORE2 | m_GENERIC,
1254 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1255 partial dependencies. */
1256 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1257 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1259 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1260 register stalls on Generic32 compilation setting as well. However
1261 in current implementation the partial register stalls are not eliminated
1262 very well - they can be introduced via subregs synthesized by combine
1263 and can happen in caller/callee saving sequences. Because this option
1264 pays back little on PPro based chips and is in conflict with partial reg
1265 dependencies used by Athlon/P4 based chips, it is better to leave it off
1266 for generic32 for now. */
1269 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1270 m_CORE2 | m_GENERIC,
1272 /* X86_TUNE_USE_HIMODE_FIOP */
1273 m_386 | m_486 | m_K6_GEODE,
1275 /* X86_TUNE_USE_SIMODE_FIOP */
1276 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1278 /* X86_TUNE_USE_MOV0 */
1281 /* X86_TUNE_USE_CLTD */
1282 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1284 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1287 /* X86_TUNE_SPLIT_LONG_MOVES */
1290 /* X86_TUNE_READ_MODIFY_WRITE */
1293 /* X86_TUNE_READ_MODIFY */
1296 /* X86_TUNE_PROMOTE_QIMODE */
1297 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1298 | m_GENERIC /* | m_PENT4 ? */,
1300 /* X86_TUNE_FAST_PREFIX */
1301 ~(m_PENT | m_486 | m_386),
1303 /* X86_TUNE_SINGLE_STRINGOP */
1304 m_386 | m_PENT4 | m_NOCONA,
1306 /* X86_TUNE_QIMODE_MATH */
1309 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1310 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1311 might be considered for Generic32 if our scheme for avoiding partial
1312 stalls was more effective. */
1315 /* X86_TUNE_PROMOTE_QI_REGS */
1318 /* X86_TUNE_PROMOTE_HI_REGS */
1321 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1322 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1324 /* X86_TUNE_ADD_ESP_8 */
1325 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1326 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1328 /* X86_TUNE_SUB_ESP_4 */
1329 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1331 /* X86_TUNE_SUB_ESP_8 */
1332 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1333 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1335 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1336 for DFmode copies */
1337 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1338 | m_GENERIC | m_GEODE),
1340 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1341 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1343 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1344 conflict here in between PPro/Pentium4 based chips that thread 128bit
1345 SSE registers as single units versus K8 based chips that divide SSE
1346 registers to two 64bit halves. This knob promotes all store destinations
1347 to be 128bit to allow register renaming on 128bit SSE units, but usually
1348 results in one extra microop on 64bit SSE units. Experimental results
1349 shows that disabling this option on P4 brings over 20% SPECfp regression,
1350 while enabling it on K8 brings roughly 2.4% regression that can be partly
1351 masked by careful scheduling of moves. */
1352 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1354 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1357 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1358 are resolved on SSE register parts instead of whole registers, so we may
1359 maintain just lower part of scalar values in proper format leaving the
1360 upper part undefined. */
1363 /* X86_TUNE_SSE_TYPELESS_STORES */
1366 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1367 m_PPRO | m_PENT4 | m_NOCONA,
1369 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1370 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1372 /* X86_TUNE_PROLOGUE_USING_MOVE */
1373 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1375 /* X86_TUNE_EPILOGUE_USING_MOVE */
1376 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1378 /* X86_TUNE_SHIFT1 */
1381 /* X86_TUNE_USE_FFREEP */
1384 /* X86_TUNE_INTER_UNIT_MOVES */
1385 ~(m_AMD_MULTIPLE | m_GENERIC),
1387 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1390 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1391 than 4 branch instructions in the 16 byte window. */
1392 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1394 /* X86_TUNE_SCHEDULE */
1395 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_USE_BT */
1398 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1400 /* X86_TUNE_USE_INCDEC */
1401 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1403 /* X86_TUNE_PAD_RETURNS */
1404 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1406 /* X86_TUNE_EXT_80387_CONSTANTS */
1407 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_SHORTEN_X87_SSE */
1412 /* X86_TUNE_AVOID_VECTOR_DECODE */
1415 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1416 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1419 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1420 vector path on AMD machines. */
1421 m_K8 | m_GENERIC64 | m_AMDFAM10,
1423 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1425 m_K8 | m_GENERIC64 | m_AMDFAM10,
1427 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1431 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1432 but one byte longer. */
1435 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1436 operand that cannot be represented using a modRM byte. The XOR
1437 replacement is long decoded, so this split helps here as well. */
1440 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1441 from integer to FP. */
1444 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1445 with a subsequent conditional jump instruction into a single
1446 compare-and-branch uop. */
1450 /* Feature tests against the various architecture variations. */
1451 unsigned char ix86_arch_features[X86_ARCH_LAST];
1453 /* Feature tests against the various architecture variations, used to create
1454 ix86_arch_features based on the processor mask. */
1455 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1456 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1457 ~(m_386 | m_486 | m_PENT | m_K6),
1459 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1462 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1465 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1468 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1472 static const unsigned int x86_accumulate_outgoing_args
1473 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1475 static const unsigned int x86_arch_always_fancy_math_387
1476 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1477 | m_NOCONA | m_CORE2 | m_GENERIC;
1479 static enum stringop_alg stringop_alg = no_stringop;
1481 /* In case the average insn count for single function invocation is
1482 lower than this constant, emit fast (but longer) prologue and
1484 #define FAST_PROLOGUE_INSN_COUNT 20
1486 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1487 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1488 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1489 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1491 /* Array of the smallest class containing reg number REGNO, indexed by
1492 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1494 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1496 /* ax, dx, cx, bx */
1497 AREG, DREG, CREG, BREG,
1498 /* si, di, bp, sp */
1499 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1501 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1502 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1505 /* flags, fpsr, fpcr, frame */
1506 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1508 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1511 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1514 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1515 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1516 /* SSE REX registers */
1517 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1521 /* The "default" register map used in 32bit mode. */
1523 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1525 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1526 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1527 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1528 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1529 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1530 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1531 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1534 static int const x86_64_int_parameter_registers[6] =
1536 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1537 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1540 static int const x86_64_ms_abi_int_parameter_registers[4] =
1542 2 /*RCX*/, 1 /*RDX*/,
1543 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1546 static int const x86_64_int_return_registers[4] =
1548 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1551 /* The "default" register map used in 64bit mode. */
1552 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1554 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1555 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1556 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1557 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1558 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1559 8,9,10,11,12,13,14,15, /* extended integer registers */
1560 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1563 /* Define the register numbers to be used in Dwarf debugging information.
1564 The SVR4 reference port C compiler uses the following register numbers
1565 in its Dwarf output code:
1566 0 for %eax (gcc regno = 0)
1567 1 for %ecx (gcc regno = 2)
1568 2 for %edx (gcc regno = 1)
1569 3 for %ebx (gcc regno = 3)
1570 4 for %esp (gcc regno = 7)
1571 5 for %ebp (gcc regno = 6)
1572 6 for %esi (gcc regno = 4)
1573 7 for %edi (gcc regno = 5)
1574 The following three DWARF register numbers are never generated by
1575 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1576 believes these numbers have these meanings.
1577 8 for %eip (no gcc equivalent)
1578 9 for %eflags (gcc regno = 17)
1579 10 for %trapno (no gcc equivalent)
1580 It is not at all clear how we should number the FP stack registers
1581 for the x86 architecture. If the version of SDB on x86/svr4 were
1582 a bit less brain dead with respect to floating-point then we would
1583 have a precedent to follow with respect to DWARF register numbers
1584 for x86 FP registers, but the SDB on x86/svr4 is so completely
1585 broken with respect to FP registers that it is hardly worth thinking
1586 of it as something to strive for compatibility with.
1587 The version of x86/svr4 SDB I have at the moment does (partially)
1588 seem to believe that DWARF register number 11 is associated with
1589 the x86 register %st(0), but that's about all. Higher DWARF
1590 register numbers don't seem to be associated with anything in
1591 particular, and even for DWARF regno 11, SDB only seems to under-
1592 stand that it should say that a variable lives in %st(0) (when
1593 asked via an `=' command) if we said it was in DWARF regno 11,
1594 but SDB still prints garbage when asked for the value of the
1595 variable in question (via a `/' command).
1596 (Also note that the labels SDB prints for various FP stack regs
1597 when doing an `x' command are all wrong.)
1598 Note that these problems generally don't affect the native SVR4
1599 C compiler because it doesn't allow the use of -O with -g and
1600 because when it is *not* optimizing, it allocates a memory
1601 location for each floating-point variable, and the memory
1602 location is what gets described in the DWARF AT_location
1603 attribute for the variable in question.
1604 Regardless of the severe mental illness of the x86/svr4 SDB, we
1605 do something sensible here and we use the following DWARF
1606 register numbers. Note that these are all stack-top-relative
1608 11 for %st(0) (gcc regno = 8)
1609 12 for %st(1) (gcc regno = 9)
1610 13 for %st(2) (gcc regno = 10)
1611 14 for %st(3) (gcc regno = 11)
1612 15 for %st(4) (gcc regno = 12)
1613 16 for %st(5) (gcc regno = 13)
1614 17 for %st(6) (gcc regno = 14)
1615 18 for %st(7) (gcc regno = 15)
1617 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1619 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1620 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1621 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1622 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1623 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1624 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1625 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1628 /* Test and compare insns in i386.md store the information needed to
1629 generate branch and scc insns here. */
1631 rtx ix86_compare_op0 = NULL_RTX;
1632 rtx ix86_compare_op1 = NULL_RTX;
1633 rtx ix86_compare_emitted = NULL_RTX;
1635 /* Define the structure for the machine field in struct function. */
1637 struct stack_local_entry GTY(())
1639 unsigned short mode;
1642 struct stack_local_entry *next;
1645 /* Structure describing stack frame layout.
1646 Stack grows downward:
1652 saved frame pointer if frame_pointer_needed
1653 <- HARD_FRAME_POINTER
1658 [va_arg registers] (
1659 > to_allocate <- FRAME_POINTER
1669 HOST_WIDE_INT frame;
1671 int outgoing_arguments_size;
1674 HOST_WIDE_INT to_allocate;
1675 /* The offsets relative to ARG_POINTER. */
1676 HOST_WIDE_INT frame_pointer_offset;
1677 HOST_WIDE_INT hard_frame_pointer_offset;
1678 HOST_WIDE_INT stack_pointer_offset;
1680 /* When save_regs_using_mov is set, emit prologue using
1681 move instead of push instructions. */
1682 bool save_regs_using_mov;
1685 /* Code model option. */
1686 enum cmodel ix86_cmodel;
1688 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1690 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1692 /* Which unit we are generating floating point math for. */
1693 enum fpmath_unit ix86_fpmath;
1695 /* Which cpu are we scheduling for. */
1696 enum processor_type ix86_tune;
1698 /* Which instruction set architecture to use. */
1699 enum processor_type ix86_arch;
1701 /* true if sse prefetch instruction is not NOOP. */
1702 int x86_prefetch_sse;
1704 /* ix86_regparm_string as a number */
1705 static int ix86_regparm;
1707 /* -mstackrealign option */
1708 extern int ix86_force_align_arg_pointer;
1709 static const char ix86_force_align_arg_pointer_string[]
1710 = "force_align_arg_pointer";
1712 static rtx (*ix86_gen_leave) (void);
1713 static rtx (*ix86_gen_pop1) (rtx);
1714 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1715 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1716 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1717 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1718 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1719 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1721 /* Preferred alignment for stack boundary in bits. */
1722 unsigned int ix86_preferred_stack_boundary;
1724 /* Alignment for incoming stack boundary in bits specified at
1726 static unsigned int ix86_user_incoming_stack_boundary;
1728 /* Default alignment for incoming stack boundary in bits. */
1729 static unsigned int ix86_default_incoming_stack_boundary;
1731 /* Alignment for incoming stack boundary in bits. */
1732 unsigned int ix86_incoming_stack_boundary;
1734 /* Values 1-5: see jump.c */
1735 int ix86_branch_cost;
1737 /* Calling abi specific va_list type nodes. */
1738 static GTY(()) tree sysv_va_list_type_node;
1739 static GTY(()) tree ms_va_list_type_node;
1741 /* Variables which are this size or smaller are put in the data/bss
1742 or ldata/lbss sections. */
1744 int ix86_section_threshold = 65536;
1746 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1747 char internal_label_prefix[16];
1748 int internal_label_prefix_len;
1750 /* Fence to use after loop using movnt. */
1753 /* Register class used for passing given 64bit part of the argument.
1754 These represent classes as documented by the PS ABI, with the exception
1755 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1756 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1758 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1759 whenever possible (upper half does contain padding). */
1760 enum x86_64_reg_class
1763 X86_64_INTEGER_CLASS,
1764 X86_64_INTEGERSI_CLASS,
1772 X86_64_COMPLEX_X87_CLASS,
1775 static const char * const x86_64_reg_class_name[] =
1777 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1778 "sseup", "x87", "x87up", "cplx87", "no"
1781 #define MAX_CLASSES 4
1783 /* Table of constants used by fldpi, fldln2, etc.... */
1784 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1785 static bool ext_80387_constants_init = 0;
1788 static struct machine_function * ix86_init_machine_status (void);
1789 static rtx ix86_function_value (const_tree, const_tree, bool);
1790 static int ix86_function_regparm (const_tree, const_tree);
1791 static void ix86_compute_frame_layout (struct ix86_frame *);
1792 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1794 static void ix86_add_new_builtins (int);
1796 enum ix86_function_specific_strings
1798 IX86_FUNCTION_SPECIFIC_ARCH,
1799 IX86_FUNCTION_SPECIFIC_TUNE,
1800 IX86_FUNCTION_SPECIFIC_FPMATH,
1801 IX86_FUNCTION_SPECIFIC_MAX
1804 static char *ix86_target_string (int, int, const char *, const char *,
1805 const char *, bool);
1806 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1807 static void ix86_function_specific_save (struct cl_target_option *);
1808 static void ix86_function_specific_restore (struct cl_target_option *);
1809 static void ix86_function_specific_print (FILE *, int,
1810 struct cl_target_option *);
1811 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1812 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1813 static bool ix86_can_inline_p (tree, tree);
1814 static void ix86_set_current_function (tree);
1817 /* The svr4 ABI for the i386 says that records and unions are returned
1819 #ifndef DEFAULT_PCC_STRUCT_RETURN
1820 #define DEFAULT_PCC_STRUCT_RETURN 1
1823 /* Whether -mtune= or -march= were specified */
1824 static int ix86_tune_defaulted;
1825 static int ix86_arch_specified;
1827 /* Bit flags that specify the ISA we are compiling for. */
1828 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1830 /* A mask of ix86_isa_flags that includes bit X if X
1831 was set or cleared on the command line. */
1832 static int ix86_isa_flags_explicit;
1834 /* Define a set of ISAs which are available when a given ISA is
1835 enabled. MMX and SSE ISAs are handled separately. */
1837 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1838 #define OPTION_MASK_ISA_3DNOW_SET \
1839 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1841 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1842 #define OPTION_MASK_ISA_SSE2_SET \
1843 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1844 #define OPTION_MASK_ISA_SSE3_SET \
1845 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1846 #define OPTION_MASK_ISA_SSSE3_SET \
1847 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1848 #define OPTION_MASK_ISA_SSE4_1_SET \
1849 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1850 #define OPTION_MASK_ISA_SSE4_2_SET \
1851 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1852 #define OPTION_MASK_ISA_AVX_SET \
1853 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1854 #define OPTION_MASK_ISA_FMA_SET \
1855 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1857 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1859 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1861 #define OPTION_MASK_ISA_SSE4A_SET \
1862 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1863 #define OPTION_MASK_ISA_SSE5_SET \
1864 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1866 /* AES and PCLMUL need SSE2 because they use xmm registers */
1867 #define OPTION_MASK_ISA_AES_SET \
1868 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1869 #define OPTION_MASK_ISA_PCLMUL_SET \
1870 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1872 #define OPTION_MASK_ISA_ABM_SET \
1873 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1874 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1875 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1876 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1878 /* Define a set of ISAs which aren't available when a given ISA is
1879 disabled. MMX and SSE ISAs are handled separately. */
1881 #define OPTION_MASK_ISA_MMX_UNSET \
1882 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1883 #define OPTION_MASK_ISA_3DNOW_UNSET \
1884 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1885 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1887 #define OPTION_MASK_ISA_SSE_UNSET \
1888 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1889 #define OPTION_MASK_ISA_SSE2_UNSET \
1890 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1891 #define OPTION_MASK_ISA_SSE3_UNSET \
1892 (OPTION_MASK_ISA_SSE3 \
1893 | OPTION_MASK_ISA_SSSE3_UNSET \
1894 | OPTION_MASK_ISA_SSE4A_UNSET )
1895 #define OPTION_MASK_ISA_SSSE3_UNSET \
1896 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1897 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1898 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1899 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1900 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1901 #define OPTION_MASK_ISA_AVX_UNSET \
1902 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1903 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1905 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1907 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1909 #define OPTION_MASK_ISA_SSE4A_UNSET \
1910 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1911 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1912 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1913 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1914 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1915 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1916 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1917 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1919 /* Vectorization library interface and handlers. */
1920 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1921 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1922 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1924 /* Processor target table, indexed by processor number */
1927 const struct processor_costs *cost; /* Processor costs */
1928 const int align_loop; /* Default alignments. */
1929 const int align_loop_max_skip;
1930 const int align_jump;
1931 const int align_jump_max_skip;
1932 const int align_func;
1935 static const struct ptt processor_target_table[PROCESSOR_max] =
1937 {&i386_cost, 4, 3, 4, 3, 4},
1938 {&i486_cost, 16, 15, 16, 15, 16},
1939 {&pentium_cost, 16, 7, 16, 7, 16},
1940 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1941 {&geode_cost, 0, 0, 0, 0, 0},
1942 {&k6_cost, 32, 7, 32, 7, 32},
1943 {&athlon_cost, 16, 7, 16, 7, 16},
1944 {&pentium4_cost, 0, 0, 0, 0, 0},
1945 {&k8_cost, 16, 7, 16, 7, 16},
1946 {&nocona_cost, 0, 0, 0, 0, 0},
1947 {&core2_cost, 16, 10, 16, 10, 16},
1948 {&generic32_cost, 16, 7, 16, 7, 16},
1949 {&generic64_cost, 16, 10, 16, 10, 16},
1950 {&amdfam10_cost, 32, 24, 32, 7, 32}
1953 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1978 /* Implement TARGET_HANDLE_OPTION. */
1981 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1988 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1989 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1993 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1994 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2001 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2002 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2006 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2007 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2017 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2018 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2022 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2023 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2030 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2031 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2035 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2036 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2043 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2044 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2048 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2049 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2056 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2057 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2061 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2062 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2069 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2070 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2074 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2075 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2082 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2083 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2087 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2088 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2095 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2096 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2100 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2101 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2108 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2109 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2113 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2114 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2119 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2124 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2125 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2131 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2132 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2136 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2144 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2145 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2149 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2157 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2158 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2162 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2170 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2171 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2175 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2183 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2184 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2188 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2196 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2197 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2201 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2202 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2209 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2210 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2214 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2215 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2222 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2223 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2227 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2228 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2237 /* Return a string the documents the current -m options. The caller is
2238 responsible for freeing the string. */
2241 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2242 const char *fpmath, bool add_nl_p)
2244 struct ix86_target_opts
2246 const char *option; /* option string */
2247 int mask; /* isa mask options */
2250 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2251 preceding options while match those first. */
2252 static struct ix86_target_opts isa_opts[] =
2254 { "-m64", OPTION_MASK_ISA_64BIT },
2255 { "-msse5", OPTION_MASK_ISA_SSE5 },
2256 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2257 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2258 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2259 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2260 { "-msse3", OPTION_MASK_ISA_SSE3 },
2261 { "-msse2", OPTION_MASK_ISA_SSE2 },
2262 { "-msse", OPTION_MASK_ISA_SSE },
2263 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2264 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2265 { "-mmmx", OPTION_MASK_ISA_MMX },
2266 { "-mabm", OPTION_MASK_ISA_ABM },
2267 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2268 { "-maes", OPTION_MASK_ISA_AES },
2269 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2273 static struct ix86_target_opts flag_opts[] =
2275 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2276 { "-m80387", MASK_80387 },
2277 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2278 { "-malign-double", MASK_ALIGN_DOUBLE },
2279 { "-mcld", MASK_CLD },
2280 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2281 { "-mieee-fp", MASK_IEEE_FP },
2282 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2283 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2284 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2285 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2286 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2287 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2288 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2289 { "-mno-red-zone", MASK_NO_RED_ZONE },
2290 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2291 { "-mrecip", MASK_RECIP },
2292 { "-mrtd", MASK_RTD },
2293 { "-msseregparm", MASK_SSEREGPARM },
2294 { "-mstack-arg-probe", MASK_STACK_PROBE },
2295 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2298 const char *opts[ (sizeof (isa_opts) / sizeof (isa_opts[0])
2299 + sizeof (flag_opts) / sizeof (flag_opts[0])
2303 char target_other[40];
2312 memset (opts, '\0', sizeof (opts));
2314 /* Add -march= option. */
2317 opts[num][0] = "-march=";
2318 opts[num++][1] = arch;
2321 /* Add -mtune= option. */
2324 opts[num][0] = "-mtune=";
2325 opts[num++][1] = tune;
2328 /* Pick out the options in isa options. */
2329 for (i = 0; i < sizeof (isa_opts) / sizeof (isa_opts[0]); i++)
2331 if ((isa & isa_opts[i].mask) != 0)
2333 opts[num++][0] = isa_opts[i].option;
2334 isa &= ~ isa_opts[i].mask;
2338 if (isa && add_nl_p)
2340 opts[num++][0] = isa_other;
2341 sprintf (isa_other, "(other isa: 0x%x)", isa);
2344 /* Add flag options. */
2345 for (i = 0; i < sizeof (flag_opts) / sizeof (flag_opts[0]); i++)
2347 if ((flags & flag_opts[i].mask) != 0)
2349 opts[num++][0] = flag_opts[i].option;
2350 flags &= ~ flag_opts[i].mask;
2354 if (flags && add_nl_p)
2356 opts[num++][0] = target_other;
2357 sprintf (target_other, "(other flags: 0x%x)", isa);
2360 /* Add -fpmath= option. */
2363 opts[num][0] = "-mfpmath=";
2364 opts[num++][1] = fpmath;
2371 gcc_assert (num < sizeof (opts) / sizeof (opts[0]));
2373 /* Size the string. */
2375 sep_len = (add_nl_p) ? 3 : 1;
2376 for (i = 0; i < num; i++)
2379 for (j = 0; j < 2; j++)
2381 len += strlen (opts[i][j]);
2384 /* Build the string. */
2385 ret = ptr = (char *) xmalloc (len);
2388 for (i = 0; i < num; i++)
2392 for (j = 0; j < 2; j++)
2393 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2400 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2408 for (j = 0; j < 2; j++)
2411 memcpy (ptr, opts[i][j], len2[j]);
2413 line_len += len2[j];
2418 gcc_assert (ret + len >= ptr);
2423 /* Function that is callable from the debugger to print the current
2426 ix86_debug_options (void)
2428 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2429 ix86_arch_string, ix86_tune_string,
2430 ix86_fpmath_string, true);
2434 fprintf (stderr, "%s\n\n", opts);
2438 fprintf (stderr, "<no options>\n\n");
2443 /* Sometimes certain combinations of command options do not make
2444 sense on a particular target machine. You can define a macro
2445 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2446 defined, is executed once just after all the command options have
2449 Don't use this macro to turn on various extra optimizations for
2450 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2453 override_options (bool main_args_p)
2456 unsigned int ix86_arch_mask, ix86_tune_mask;
2461 /* Comes from final.c -- no real reason to change it. */
2462 #define MAX_CODE_ALIGN 16
2470 PTA_PREFETCH_SSE = 1 << 4,
2472 PTA_3DNOW_A = 1 << 6,
2476 PTA_POPCNT = 1 << 10,
2478 PTA_SSE4A = 1 << 12,
2479 PTA_NO_SAHF = 1 << 13,
2480 PTA_SSE4_1 = 1 << 14,
2481 PTA_SSE4_2 = 1 << 15,
2484 PTA_PCLMUL = 1 << 18,
2491 const char *const name; /* processor name or nickname. */
2492 const enum processor_type processor;
2493 const unsigned /*enum pta_flags*/ flags;
2495 const processor_alias_table[] =
2497 {"i386", PROCESSOR_I386, 0},
2498 {"i486", PROCESSOR_I486, 0},
2499 {"i586", PROCESSOR_PENTIUM, 0},
2500 {"pentium", PROCESSOR_PENTIUM, 0},
2501 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2502 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2503 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2504 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2505 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2506 {"i686", PROCESSOR_PENTIUMPRO, 0},
2507 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2508 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2509 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2510 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2511 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2512 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2513 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2514 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2515 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2516 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2517 | PTA_CX16 | PTA_NO_SAHF)},
2518 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2519 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2522 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2523 |PTA_PREFETCH_SSE)},
2524 {"k6", PROCESSOR_K6, PTA_MMX},
2525 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2526 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2527 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2528 | PTA_PREFETCH_SSE)},
2529 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2530 | PTA_PREFETCH_SSE)},
2531 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2533 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2535 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2537 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2538 | PTA_MMX | PTA_SSE | PTA_SSE2
2540 {"k8", PROCESSOR_K8, (PTA_64BIT
2541 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2542 | PTA_SSE | PTA_SSE2
2544 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2545 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2546 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2548 {"opteron", PROCESSOR_K8, (PTA_64BIT
2549 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2550 | PTA_SSE | PTA_SSE2
2552 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2553 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2554 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2556 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2557 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2558 | PTA_SSE | PTA_SSE2
2560 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2561 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2562 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2564 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2565 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2566 | PTA_SSE | PTA_SSE2
2568 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2569 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2570 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2572 | PTA_CX16 | PTA_ABM)},
2573 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2574 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2575 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2577 | PTA_CX16 | PTA_ABM)},
2578 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2579 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2582 int const pta_size = ARRAY_SIZE (processor_alias_table);
2584 /* Set up prefix/suffix so the error messages refer to either the command
2585 line argument, or the attribute(target). */
2594 prefix = "option(\"";
2599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2600 SUBTARGET_OVERRIDE_OPTIONS;
2603 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2604 SUBSUBTARGET_OVERRIDE_OPTIONS;
2607 /* -fPIC is the default for x86_64. */
2608 if (TARGET_MACHO && TARGET_64BIT)
2611 /* Set the default values for switches whose default depends on TARGET_64BIT
2612 in case they weren't overwritten by command line options. */
2615 /* Mach-O doesn't support omitting the frame pointer for now. */
2616 if (flag_omit_frame_pointer == 2)
2617 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2618 if (flag_asynchronous_unwind_tables == 2)
2619 flag_asynchronous_unwind_tables = 1;
2620 if (flag_pcc_struct_return == 2)
2621 flag_pcc_struct_return = 0;
2625 if (flag_omit_frame_pointer == 2)
2626 flag_omit_frame_pointer = 0;
2627 if (flag_asynchronous_unwind_tables == 2)
2628 flag_asynchronous_unwind_tables = 0;
2629 if (flag_pcc_struct_return == 2)
2630 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2633 /* Need to check -mtune=generic first. */
2634 if (ix86_tune_string)
2636 if (!strcmp (ix86_tune_string, "generic")
2637 || !strcmp (ix86_tune_string, "i686")
2638 /* As special support for cross compilers we read -mtune=native
2639 as -mtune=generic. With native compilers we won't see the
2640 -mtune=native, as it was changed by the driver. */
2641 || !strcmp (ix86_tune_string, "native"))
2644 ix86_tune_string = "generic64";
2646 ix86_tune_string = "generic32";
2648 /* If this call is for setting the option attribute, allow the
2649 generic32/generic64 that was previously set. */
2650 else if (!main_args_p
2651 && (!strcmp (ix86_tune_string, "generic32")
2652 || !strcmp (ix86_tune_string, "generic64")))
2654 else if (!strncmp (ix86_tune_string, "generic", 7))
2655 error ("bad value (%s) for %stune=%s %s",
2656 ix86_tune_string, prefix, suffix, sw);
2660 if (ix86_arch_string)
2661 ix86_tune_string = ix86_arch_string;
2662 if (!ix86_tune_string)
2664 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2665 ix86_tune_defaulted = 1;
2668 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2669 need to use a sensible tune option. */
2670 if (!strcmp (ix86_tune_string, "generic")
2671 || !strcmp (ix86_tune_string, "x86-64")
2672 || !strcmp (ix86_tune_string, "i686"))
2675 ix86_tune_string = "generic64";
2677 ix86_tune_string = "generic32";
2680 if (ix86_stringop_string)
2682 if (!strcmp (ix86_stringop_string, "rep_byte"))
2683 stringop_alg = rep_prefix_1_byte;
2684 else if (!strcmp (ix86_stringop_string, "libcall"))
2685 stringop_alg = libcall;
2686 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2687 stringop_alg = rep_prefix_4_byte;
2688 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2689 stringop_alg = rep_prefix_8_byte;
2690 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2691 stringop_alg = loop_1_byte;
2692 else if (!strcmp (ix86_stringop_string, "loop"))
2693 stringop_alg = loop;
2694 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2695 stringop_alg = unrolled_loop;
2697 error ("bad value (%s) for %sstringop-strategy=%s %s",
2698 ix86_stringop_string, prefix, suffix, sw);
2700 if (!strcmp (ix86_tune_string, "x86-64"))
2701 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2702 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2703 prefix, suffix, prefix, suffix, prefix, suffix);
2705 if (!ix86_arch_string)
2706 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2708 ix86_arch_specified = 1;
2710 if (!strcmp (ix86_arch_string, "generic"))
2711 error ("generic CPU can be used only for %stune=%s %s",
2712 prefix, suffix, sw);
2713 if (!strncmp (ix86_arch_string, "generic", 7))
2714 error ("bad value (%s) for %sarch=%s %s",
2715 ix86_arch_string, prefix, suffix, sw);
2717 if (ix86_cmodel_string != 0)
2719 if (!strcmp (ix86_cmodel_string, "small"))
2720 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2721 else if (!strcmp (ix86_cmodel_string, "medium"))
2722 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2723 else if (!strcmp (ix86_cmodel_string, "large"))
2724 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2726 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2727 else if (!strcmp (ix86_cmodel_string, "32"))
2728 ix86_cmodel = CM_32;
2729 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2730 ix86_cmodel = CM_KERNEL;
2732 error ("bad value (%s) for %scmodel=%s %s",
2733 ix86_cmodel_string, prefix, suffix, sw);
2737 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2738 use of rip-relative addressing. This eliminates fixups that
2739 would otherwise be needed if this object is to be placed in a
2740 DLL, and is essentially just as efficient as direct addressing. */
2741 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2742 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2743 else if (TARGET_64BIT)
2744 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2746 ix86_cmodel = CM_32;
2748 if (ix86_asm_string != 0)
2751 && !strcmp (ix86_asm_string, "intel"))
2752 ix86_asm_dialect = ASM_INTEL;
2753 else if (!strcmp (ix86_asm_string, "att"))
2754 ix86_asm_dialect = ASM_ATT;
2756 error ("bad value (%s) for %sasm=%s %s",
2757 ix86_asm_string, prefix, suffix, sw);
2759 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2760 error ("code model %qs not supported in the %s bit mode",
2761 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2762 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2763 sorry ("%i-bit mode not compiled in",
2764 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2766 for (i = 0; i < pta_size; i++)
2767 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2769 ix86_arch = processor_alias_table[i].processor;
2770 /* Default cpu tuning to the architecture. */
2771 ix86_tune = ix86_arch;
2773 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2774 error ("CPU you selected does not support x86-64 "
2777 if (processor_alias_table[i].flags & PTA_MMX
2778 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2779 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2780 if (processor_alias_table[i].flags & PTA_3DNOW
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2782 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2783 if (processor_alias_table[i].flags & PTA_3DNOW_A
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2785 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2786 if (processor_alias_table[i].flags & PTA_SSE
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2788 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2789 if (processor_alias_table[i].flags & PTA_SSE2
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2791 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2792 if (processor_alias_table[i].flags & PTA_SSE3
2793 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2794 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2795 if (processor_alias_table[i].flags & PTA_SSSE3
2796 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2797 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2798 if (processor_alias_table[i].flags & PTA_SSE4_1
2799 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2800 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2801 if (processor_alias_table[i].flags & PTA_SSE4_2
2802 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2803 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2804 if (processor_alias_table[i].flags & PTA_AVX
2805 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2806 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2807 if (processor_alias_table[i].flags & PTA_FMA
2808 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2809 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2810 if (processor_alias_table[i].flags & PTA_SSE4A
2811 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2812 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2813 if (processor_alias_table[i].flags & PTA_SSE5
2814 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2815 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2816 if (processor_alias_table[i].flags & PTA_ABM
2817 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2818 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2819 if (processor_alias_table[i].flags & PTA_CX16
2820 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2821 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2822 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2823 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2824 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2825 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2826 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2827 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2828 if (processor_alias_table[i].flags & PTA_AES
2829 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2830 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2831 if (processor_alias_table[i].flags & PTA_PCLMUL
2832 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2833 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2834 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2835 x86_prefetch_sse = true;
2841 error ("bad value (%s) for %sarch=%s %s",
2842 ix86_arch_string, prefix, suffix, sw);
2844 ix86_arch_mask = 1u << ix86_arch;
2845 for (i = 0; i < X86_ARCH_LAST; ++i)
2846 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2848 for (i = 0; i < pta_size; i++)
2849 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2851 ix86_tune = processor_alias_table[i].processor;
2852 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2854 if (ix86_tune_defaulted)
2856 ix86_tune_string = "x86-64";
2857 for (i = 0; i < pta_size; i++)
2858 if (! strcmp (ix86_tune_string,
2859 processor_alias_table[i].name))
2861 ix86_tune = processor_alias_table[i].processor;
2864 error ("CPU you selected does not support x86-64 "
2867 /* Intel CPUs have always interpreted SSE prefetch instructions as
2868 NOPs; so, we can enable SSE prefetch instructions even when
2869 -mtune (rather than -march) points us to a processor that has them.
2870 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2871 higher processors. */
2873 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2874 x86_prefetch_sse = true;
2878 error ("bad value (%s) for %stune=%s %s",
2879 ix86_tune_string, prefix, suffix, sw);
2881 ix86_tune_mask = 1u << ix86_tune;
2882 for (i = 0; i < X86_TUNE_LAST; ++i)
2883 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2886 ix86_cost = &ix86_size_cost;
2888 ix86_cost = processor_target_table[ix86_tune].cost;
2890 /* Arrange to set up i386_stack_locals for all functions. */
2891 init_machine_status = ix86_init_machine_status;
2893 /* Validate -mregparm= value. */
2894 if (ix86_regparm_string)
2897 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2898 i = atoi (ix86_regparm_string);
2899 if (i < 0 || i > REGPARM_MAX)
2900 error ("%sregparm=%d%s is not between 0 and %d",
2901 prefix, i, suffix, REGPARM_MAX);
2906 ix86_regparm = REGPARM_MAX;
2908 /* If the user has provided any of the -malign-* options,
2909 warn and use that value only if -falign-* is not set.
2910 Remove this code in GCC 3.2 or later. */
2911 if (ix86_align_loops_string)
2913 warning (0, "%salign-loops%s is obsolete, use %salign-loops%s",
2914 prefix, suffix, prefix, suffix);
2915 if (align_loops == 0)
2917 i = atoi (ix86_align_loops_string);
2918 if (i < 0 || i > MAX_CODE_ALIGN)
2919 error ("%salign-loops=%d%s is not between 0 and %d",
2920 prefix, i, suffix, MAX_CODE_ALIGN);
2922 align_loops = 1 << i;
2926 if (ix86_align_jumps_string)
2928 warning (0, "%salign-jumps%s is obsolete, use %salign-jumps%s",
2929 prefix, suffix, prefix, suffix);
2930 if (align_jumps == 0)
2932 i = atoi (ix86_align_jumps_string);
2933 if (i < 0 || i > MAX_CODE_ALIGN)
2934 error ("%salign-loops=%d%s is not between 0 and %d",
2935 prefix, i, suffix, MAX_CODE_ALIGN);
2937 align_jumps = 1 << i;
2941 if (ix86_align_funcs_string)
2943 warning (0, "%salign-functions%s is obsolete, use %salign-functions%s",
2944 prefix, suffix, prefix, suffix);
2945 if (align_functions == 0)
2947 i = atoi (ix86_align_funcs_string);
2948 if (i < 0 || i > MAX_CODE_ALIGN)
2949 error ("%salign-loops=%d%s is not between 0 and %d",
2950 prefix, i, suffix, MAX_CODE_ALIGN);
2952 align_functions = 1 << i;
2956 /* Default align_* from the processor table. */
2957 if (align_loops == 0)
2959 align_loops = processor_target_table[ix86_tune].align_loop;
2960 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2962 if (align_jumps == 0)
2964 align_jumps = processor_target_table[ix86_tune].align_jump;
2965 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2967 if (align_functions == 0)
2969 align_functions = processor_target_table[ix86_tune].align_func;
2972 /* Validate -mbranch-cost= value, or provide default. */
2973 ix86_branch_cost = ix86_cost->branch_cost;
2974 if (ix86_branch_cost_string)
2976 i = atoi (ix86_branch_cost_string);
2978 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2980 ix86_branch_cost = i;
2982 if (ix86_section_threshold_string)
2984 i = atoi (ix86_section_threshold_string);
2986 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2988 ix86_section_threshold = i;
2991 if (ix86_tls_dialect_string)
2993 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2994 ix86_tls_dialect = TLS_DIALECT_GNU;
2995 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2996 ix86_tls_dialect = TLS_DIALECT_GNU2;
2997 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2998 ix86_tls_dialect = TLS_DIALECT_SUN;
3000 error ("bad value (%s) for %stls-dialect=%s %s",
3001 ix86_tls_dialect_string, prefix, suffix, sw);
3004 if (ix87_precision_string)
3006 i = atoi (ix87_precision_string);
3007 if (i != 32 && i != 64 && i != 80)
3008 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3013 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3015 /* Enable by default the SSE and MMX builtins. Do allow the user to
3016 explicitly disable any of these. In particular, disabling SSE and
3017 MMX for kernel code is extremely useful. */
3018 if (!ix86_arch_specified)
3020 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3021 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3024 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3028 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3030 if (!ix86_arch_specified)
3032 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3034 /* i386 ABI does not specify red zone. It still makes sense to use it
3035 when programmer takes care to stack from being destroyed. */
3036 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3037 target_flags |= MASK_NO_RED_ZONE;
3040 /* Keep nonleaf frame pointers. */
3041 if (flag_omit_frame_pointer)
3042 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3043 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3044 flag_omit_frame_pointer = 1;
3046 /* If we're doing fast math, we don't care about comparison order
3047 wrt NaNs. This lets us use a shorter comparison sequence. */
3048 if (flag_finite_math_only)
3049 target_flags &= ~MASK_IEEE_FP;
3051 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3052 since the insns won't need emulation. */
3053 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3054 target_flags &= ~MASK_NO_FANCY_MATH_387;
3056 /* Likewise, if the target doesn't have a 387, or we've specified
3057 software floating point, don't use 387 inline intrinsics. */
3059 target_flags |= MASK_NO_FANCY_MATH_387;
3061 /* Turn on MMX builtins for -msse. */
3064 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3065 x86_prefetch_sse = true;
3068 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3069 if (TARGET_SSE4_2 || TARGET_ABM)
3070 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3072 /* Validate -mpreferred-stack-boundary= value or default it to
3073 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3074 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3075 if (ix86_preferred_stack_boundary_string)
3077 i = atoi (ix86_preferred_stack_boundary_string);
3078 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3079 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3080 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3082 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3085 /* Set the default value for -mstackrealign. */
3086 if (ix86_force_align_arg_pointer == -1)
3087 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3089 /* Validate -mincoming-stack-boundary= value or default it to
3090 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3091 if (ix86_force_align_arg_pointer)
3092 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3094 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3095 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3096 if (ix86_incoming_stack_boundary_string)
3098 i = atoi (ix86_incoming_stack_boundary_string);
3099 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3100 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3101 i, TARGET_64BIT ? 4 : 2);
3104 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3105 ix86_incoming_stack_boundary
3106 = ix86_user_incoming_stack_boundary;
3110 /* Accept -msseregparm only if at least SSE support is enabled. */
3111 if (TARGET_SSEREGPARM
3113 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3115 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3116 if (ix86_fpmath_string != 0)
3118 if (! strcmp (ix86_fpmath_string, "387"))
3119 ix86_fpmath = FPMATH_387;
3120 else if (! strcmp (ix86_fpmath_string, "sse"))
3124 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3125 ix86_fpmath = FPMATH_387;
3128 ix86_fpmath = FPMATH_SSE;
3130 else if (! strcmp (ix86_fpmath_string, "387,sse")
3131 || ! strcmp (ix86_fpmath_string, "387+sse")
3132 || ! strcmp (ix86_fpmath_string, "sse,387")
3133 || ! strcmp (ix86_fpmath_string, "sse+387")
3134 || ! strcmp (ix86_fpmath_string, "both"))
3138 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3139 ix86_fpmath = FPMATH_387;
3141 else if (!TARGET_80387)
3143 warning (0, "387 instruction set disabled, using SSE arithmetics");
3144 ix86_fpmath = FPMATH_SSE;
3147 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3150 error ("bad value (%s) for %sfpmath=%s %s",
3151 ix86_fpmath_string, prefix, suffix, sw);
3154 /* If the i387 is disabled, then do not return values in it. */
3156 target_flags &= ~MASK_FLOAT_RETURNS;
3158 /* Use external vectorized library in vectorizing intrinsics. */
3159 if (ix86_veclibabi_string)
3161 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3162 ix86_veclib_handler = ix86_veclibabi_svml;
3163 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3164 ix86_veclib_handler = ix86_veclibabi_acml;
3166 error ("unknown vectorization library ABI type (%s) for "
3167 "%sveclibabi=%s %s", ix86_veclibabi_string,
3168 prefix, suffix, sw);
3171 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3172 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3174 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3176 /* ??? Unwind info is not correct around the CFG unless either a frame
3177 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3178 unwind info generation to be aware of the CFG and propagating states
3180 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3181 || flag_exceptions || flag_non_call_exceptions)
3182 && flag_omit_frame_pointer
3183 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3185 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3186 warning (0, "unwind tables currently require either a frame pointer "
3187 "or %saccumulate-outgoing-args%s for correctness",
3189 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3192 /* If stack probes are required, the space used for large function
3193 arguments on the stack must also be probed, so enable
3194 -maccumulate-outgoing-args so this happens in the prologue. */
3195 if (TARGET_STACK_PROBE
3196 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3198 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3199 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3200 "for correctness", prefix, suffix);
3201 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3204 /* For sane SSE instruction set generation we need fcomi instruction.
3205 It is safe to enable all CMOVE instructions. */
3209 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3212 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3213 p = strchr (internal_label_prefix, 'X');
3214 internal_label_prefix_len = p - internal_label_prefix;
3218 /* When scheduling description is not available, disable scheduler pass
3219 so it won't slow down the compilation and make x87 code slower. */
3220 if (!TARGET_SCHEDULE)
3221 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3223 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3224 set_param_value ("simultaneous-prefetches",
3225 ix86_cost->simultaneous_prefetches);
3226 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3227 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3228 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3229 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3230 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3231 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3233 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3234 can be optimized to ap = __builtin_next_arg (0). */
3236 targetm.expand_builtin_va_start = NULL;
3240 ix86_gen_leave = gen_leave_rex64;
3241 ix86_gen_pop1 = gen_popdi1;
3242 ix86_gen_add3 = gen_adddi3;
3243 ix86_gen_sub3 = gen_subdi3;
3244 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3245 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3246 ix86_gen_monitor = gen_sse3_monitor64;
3247 ix86_gen_andsp = gen_anddi3;
3251 ix86_gen_leave = gen_leave;
3252 ix86_gen_pop1 = gen_popsi1;
3253 ix86_gen_add3 = gen_addsi3;
3254 ix86_gen_sub3 = gen_subsi3;
3255 ix86_gen_sub3_carry = gen_subsi3_carry;
3256 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3257 ix86_gen_monitor = gen_sse3_monitor;
3258 ix86_gen_andsp = gen_andsi3;
3262 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3264 target_flags |= MASK_CLD & ~target_flags_explicit;
3267 /* Save the initial options in case the user does function specific options */
3269 target_option_default_node = target_option_current_node
3270 = build_target_option_node ();
3273 /* Save the current options */
3276 ix86_function_specific_save (struct cl_target_option *ptr)
3278 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3279 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3280 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3281 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3283 ptr->arch = ix86_arch;
3284 ptr->tune = ix86_tune;
3285 ptr->fpmath = ix86_fpmath;
3286 ptr->branch_cost = ix86_branch_cost;
3287 ptr->tune_defaulted = ix86_tune_defaulted;
3288 ptr->arch_specified = ix86_arch_specified;
3289 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3290 ptr->target_flags_explicit = target_flags_explicit;
3293 /* Restore the current options */
3296 ix86_function_specific_restore (struct cl_target_option *ptr)
3298 enum processor_type old_tune = ix86_tune;
3299 enum processor_type old_arch = ix86_arch;
3300 unsigned int ix86_arch_mask, ix86_tune_mask;
3303 ix86_arch = ptr->arch;
3304 ix86_tune = ptr->tune;
3305 ix86_fpmath = ptr->fpmath;
3306 ix86_branch_cost = ptr->branch_cost;
3307 ix86_tune_defaulted = ptr->tune_defaulted;
3308 ix86_arch_specified = ptr->arch_specified;
3309 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3310 target_flags_explicit = ptr->target_flags_explicit;
3312 /* Recreate the arch feature tests if the arch changed */
3313 if (old_arch != ix86_arch)
3315 ix86_arch_mask = 1u << ix86_arch;
3316 for (i = 0; i < X86_ARCH_LAST; ++i)
3317 ix86_arch_features[i]
3318 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3321 /* Recreate the tune optimization tests */
3322 if (old_tune != ix86_tune)
3324 ix86_tune_mask = 1u << ix86_tune;
3325 for (i = 0; i < X86_TUNE_LAST; ++i)
3326 ix86_tune_features[i]
3327 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3331 /* Print the current options */
3334 ix86_function_specific_print (FILE *file, int indent,
3335 struct cl_target_option *ptr)
3338 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3339 NULL, NULL, NULL, false);
3341 fprintf (file, "%*sarch = %d (%s)\n",
3344 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3345 ? cpu_names[ptr->arch]
3348 fprintf (file, "%*stune = %d (%s)\n",
3351 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3352 ? cpu_names[ptr->tune]
3355 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3356 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3357 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3358 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3362 fprintf (file, "%*s%s\n", indent, "", target_string);
3363 free (target_string);
3368 /* Inner function to process the attribute((target(...))), take an argument and
3369 set the current options from the argument. If we have a list, recursively go
3373 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3378 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3379 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3380 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3381 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3396 enum ix86_opt_type type;
3401 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3402 IX86_ATTR_ISA ("abm", OPT_mabm),
3403 IX86_ATTR_ISA ("aes", OPT_maes),
3404 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3405 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3406 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3407 IX86_ATTR_ISA ("sse", OPT_msse),
3408 IX86_ATTR_ISA ("sse2", OPT_msse2),
3409 IX86_ATTR_ISA ("sse3", OPT_msse3),
3410 IX86_ATTR_ISA ("sse4", OPT_msse4),
3411 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3412 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3413 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3414 IX86_ATTR_ISA ("sse5", OPT_msse5),
3415 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3417 /* string options */
3418 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3419 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3420 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3423 IX86_ATTR_YES ("cld",
3427 IX86_ATTR_NO ("fancy-math-387",
3428 OPT_mfancy_math_387,
3429 MASK_NO_FANCY_MATH_387),
3431 IX86_ATTR_NO ("fused-madd",
3433 MASK_NO_FUSED_MADD),
3435 IX86_ATTR_YES ("ieee-fp",
3439 IX86_ATTR_YES ("inline-all-stringops",
3440 OPT_minline_all_stringops,
3441 MASK_INLINE_ALL_STRINGOPS),
3443 IX86_ATTR_YES ("inline-stringops-dynamically",
3444 OPT_minline_stringops_dynamically,
3445 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3447 IX86_ATTR_NO ("align-stringops",
3448 OPT_mno_align_stringops,
3449 MASK_NO_ALIGN_STRINGOPS),
3451 IX86_ATTR_YES ("recip",
3457 /* If this is a list, recurse to get the options. */
3458 if (TREE_CODE (args) == TREE_LIST)
3462 for (; args; args = TREE_CHAIN (args))
3463 if (TREE_VALUE (args)
3464 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3470 else if (TREE_CODE (args) != STRING_CST)
3473 /* Handle multiple arguments separated by commas. */
3474 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3476 while (next_optstr && *next_optstr != '\0')
3478 char *p = next_optstr;
3480 char *comma = strchr (next_optstr, ',');
3481 const char *opt_string;
3482 size_t len, opt_len;
3487 enum ix86_opt_type type = ix86_opt_unknown;
3493 len = comma - next_optstr;
3494 next_optstr = comma + 1;
3502 /* Recognize no-xxx. */
3503 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3512 /* Find the option. */
3515 for (i = 0; i < sizeof (attrs) / sizeof (attrs[0]); i++)
3517 type = attrs[i].type;
3518 opt_len = attrs[i].len;
3519 if (ch == attrs[i].string[0]
3520 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3521 && memcmp (p, attrs[i].string, opt_len) == 0)
3524 mask = attrs[i].mask;
3525 opt_string = attrs[i].string;
3530 /* Process the option. */
3533 error ("attribute(target(\"%s\")) is unknown", orig_p);
3537 else if (type == ix86_opt_isa)
3538 ix86_handle_option (opt, p, opt_set_p);
3540 else if (type == ix86_opt_yes || type == ix86_opt_no)
3542 if (type == ix86_opt_no)
3543 opt_set_p = !opt_set_p;
3546 target_flags |= mask;
3548 target_flags &= ~mask;
3551 else if (type == ix86_opt_str)
3555 error ("option(\"%s\") was already specified", opt_string);
3559 p_strings[opt] = xstrdup (p + opt_len);
3569 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3572 ix86_valid_target_attribute_tree (tree args)
3574 const char *orig_arch_string = ix86_arch_string;
3575 const char *orig_tune_string = ix86_tune_string;
3576 const char *orig_fpmath_string = ix86_fpmath_string;
3577 int orig_tune_defaulted = ix86_tune_defaulted;
3578 int orig_arch_specified = ix86_arch_specified;
3579 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3582 struct cl_target_option *def
3583 = TREE_TARGET_OPTION (target_option_default_node);
3585 /* Process each of the options on the chain. */
3586 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3589 /* If the changed options are different from the default, rerun override_options,
3590 and then save the options away. The string options are are attribute options,
3591 and will be undone when we copy the save structure. */
3592 if (ix86_isa_flags != def->ix86_isa_flags
3593 || target_flags != def->target_flags
3594 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3595 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3596 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3598 /* If we are using the default tune= or arch=, undo the string assigned,
3599 and use the default. */
3600 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3601 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3602 else if (!orig_arch_specified)
3603 ix86_arch_string = NULL;
3605 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3606 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3607 else if (orig_tune_defaulted)
3608 ix86_tune_string = NULL;
3610 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3611 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3612 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3613 else if (!TARGET_64BIT && TARGET_SSE)
3614 ix86_fpmath_string = "sse,387";
3616 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3617 override_options (false);
3619 /* Add any builtin functions with the new isa if any. */
3620 ix86_add_new_builtins (ix86_isa_flags);
3622 /* Save the current options unless we are validating options for
3624 t = build_target_option_node ();
3626 ix86_arch_string = orig_arch_string;
3627 ix86_tune_string = orig_tune_string;
3628 ix86_fpmath_string = orig_fpmath_string;
3630 /* Free up memory allocated to hold the strings */
3631 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3632 if (option_strings[i])
3633 free (option_strings[i]);
3639 /* Hook to validate attribute((target("string"))). */
3642 ix86_valid_target_attribute_p (tree fndecl,
3643 tree ARG_UNUSED (name),
3645 int ARG_UNUSED (flags))
3647 struct cl_target_option cur_target;
3649 tree old_optimize = build_optimization_node ();
3650 tree new_target, new_optimize;
3651 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3653 /* If the function changed the optimization levels as well as setting target
3654 options, start with the optimizations specified. */
3655 if (func_optimize && func_optimize != old_optimize)
3656 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3658 /* The target attributes may also change some optimization flags, so update
3659 the optimization options if necessary. */
3660 cl_target_option_save (&cur_target);
3661 new_target = ix86_valid_target_attribute_tree (args);
3662 new_optimize = build_optimization_node ();
3669 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3671 if (old_optimize != new_optimize)
3672 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3675 cl_target_option_restore (&cur_target);
3677 if (old_optimize != new_optimize)
3678 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3684 /* Hook to determine if one function can safely inline another. */
3687 ix86_can_inline_p (tree caller, tree callee)
3690 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3691 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3693 /* If callee has no option attributes, then it is ok to inline. */
3697 /* If caller has no option attributes, but callee does then it is not ok to
3699 else if (!caller_tree)
3704 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3705 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3707 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3708 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3710 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3711 != callee_opts->ix86_isa_flags)
3714 /* See if we have the same non-isa options. */
3715 else if (caller_opts->target_flags != callee_opts->target_flags)
3718 /* See if arch, tune, etc. are the same. */
3719 else if (caller_opts->arch != callee_opts->arch)
3722 else if (caller_opts->tune != callee_opts->tune)
3725 else if (caller_opts->fpmath != callee_opts->fpmath)
3728 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3739 /* Remember the last target of ix86_set_current_function. */
3740 static GTY(()) tree ix86_previous_fndecl;
3742 /* Establish appropriate back-end context for processing the function
3743 FNDECL. The argument might be NULL to indicate processing at top
3744 level, outside of any function scope. */
3746 ix86_set_current_function (tree fndecl)
3748 /* Only change the context if the function changes. This hook is called
3749 several times in the course of compiling a function, and we don't want to
3750 slow things down too much or call target_reinit when it isn't safe. */
3751 if (fndecl && fndecl != ix86_previous_fndecl)
3753 tree old_tree = (ix86_previous_fndecl
3754 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3757 tree new_tree = (fndecl
3758 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3761 ix86_previous_fndecl = fndecl;
3762 if (old_tree == new_tree)
3767 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3773 struct cl_target_option *def
3774 = TREE_TARGET_OPTION (target_option_current_node);
3776 cl_target_option_restore (def);
3783 /* Return true if this goes in large data/bss. */
3786 ix86_in_large_data_p (tree exp)
3788 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3791 /* Functions are never large data. */
3792 if (TREE_CODE (exp) == FUNCTION_DECL)
3795 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3797 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3798 if (strcmp (section, ".ldata") == 0
3799 || strcmp (section, ".lbss") == 0)
3805 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3807 /* If this is an incomplete type with size 0, then we can't put it
3808 in data because it might be too big when completed. */
3809 if (!size || size > ix86_section_threshold)
3816 /* Switch to the appropriate section for output of DECL.
3817 DECL is either a `VAR_DECL' node or a constant of some sort.
3818 RELOC indicates whether forming the initial value of DECL requires
3819 link-time relocations. */
3821 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3825 x86_64_elf_select_section (tree decl, int reloc,
3826 unsigned HOST_WIDE_INT align)
3828 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3829 && ix86_in_large_data_p (decl))
3831 const char *sname = NULL;
3832 unsigned int flags = SECTION_WRITE;
3833 switch (categorize_decl_for_section (decl, reloc))
3838 case SECCAT_DATA_REL:
3839 sname = ".ldata.rel";
3841 case SECCAT_DATA_REL_LOCAL:
3842 sname = ".ldata.rel.local";
3844 case SECCAT_DATA_REL_RO:
3845 sname = ".ldata.rel.ro";
3847 case SECCAT_DATA_REL_RO_LOCAL:
3848 sname = ".ldata.rel.ro.local";
3852 flags |= SECTION_BSS;
3855 case SECCAT_RODATA_MERGE_STR:
3856 case SECCAT_RODATA_MERGE_STR_INIT:
3857 case SECCAT_RODATA_MERGE_CONST:
3861 case SECCAT_SRODATA:
3868 /* We don't split these for medium model. Place them into
3869 default sections and hope for best. */
3871 case SECCAT_EMUTLS_VAR:
3872 case SECCAT_EMUTLS_TMPL:
3877 /* We might get called with string constants, but get_named_section
3878 doesn't like them as they are not DECLs. Also, we need to set
3879 flags in that case. */
3881 return get_section (sname, flags, NULL);
3882 return get_named_section (decl, sname, reloc);
3885 return default_elf_select_section (decl, reloc, align);
3888 /* Build up a unique section name, expressed as a
3889 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3890 RELOC indicates whether the initial value of EXP requires
3891 link-time relocations. */
3893 static void ATTRIBUTE_UNUSED
3894 x86_64_elf_unique_section (tree decl, int reloc)
3896 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3897 && ix86_in_large_data_p (decl))
3899 const char *prefix = NULL;
3900 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3901 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3903 switch (categorize_decl_for_section (decl, reloc))
3906 case SECCAT_DATA_REL:
3907 case SECCAT_DATA_REL_LOCAL:
3908 case SECCAT_DATA_REL_RO:
3909 case SECCAT_DATA_REL_RO_LOCAL:
3910 prefix = one_only ? ".ld" : ".ldata";
3913 prefix = one_only ? ".lb" : ".lbss";
3916 case SECCAT_RODATA_MERGE_STR:
3917 case SECCAT_RODATA_MERGE_STR_INIT:
3918 case SECCAT_RODATA_MERGE_CONST:
3919 prefix = one_only ? ".lr" : ".lrodata";
3921 case SECCAT_SRODATA:
3928 /* We don't split these for medium model. Place them into
3929 default sections and hope for best. */
3931 case SECCAT_EMUTLS_VAR:
3932 prefix = targetm.emutls.var_section;
3934 case SECCAT_EMUTLS_TMPL:
3935 prefix = targetm.emutls.tmpl_section;
3940 const char *name, *linkonce;
3943 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3944 name = targetm.strip_name_encoding (name);
3946 /* If we're using one_only, then there needs to be a .gnu.linkonce
3947 prefix to the section name. */
3948 linkonce = one_only ? ".gnu.linkonce" : "";
3950 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3952 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
3956 default_unique_section (decl, reloc);
3959 #ifdef COMMON_ASM_OP
3960 /* This says how to output assembler code to declare an
3961 uninitialized external linkage data object.
3963 For medium model x86-64 we need to use .largecomm opcode for
3966 x86_elf_aligned_common (FILE *file,
3967 const char *name, unsigned HOST_WIDE_INT size,
3970 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3971 && size > (unsigned int)ix86_section_threshold)
3972 fprintf (file, ".largecomm\t");
3974 fprintf (file, "%s", COMMON_ASM_OP);
3975 assemble_name (file, name);
3976 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
3977 size, align / BITS_PER_UNIT);
3981 /* Utility function for targets to use in implementing
3982 ASM_OUTPUT_ALIGNED_BSS. */
3985 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
3986 const char *name, unsigned HOST_WIDE_INT size,
3989 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3990 && size > (unsigned int)ix86_section_threshold)
3991 switch_to_section (get_named_section (decl, ".lbss", 0));
3993 switch_to_section (bss_section);
3994 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
3995 #ifdef ASM_DECLARE_OBJECT_NAME
3996 last_assemble_variable_decl = decl;
3997 ASM_DECLARE_OBJECT_NAME (file, name, decl);
3999 /* Standard thing is just output label for the object. */
4000 ASM_OUTPUT_LABEL (file, name);
4001 #endif /* ASM_DECLARE_OBJECT_NAME */
4002 ASM_OUTPUT_SKIP (file, size ? size : 1);
4006 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4008 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4009 make the problem with not enough registers even worse. */
4010 #ifdef INSN_SCHEDULING
4012 flag_schedule_insns = 0;
4016 /* The Darwin libraries never set errno, so we might as well
4017 avoid calling them when that's the only reason we would. */
4018 flag_errno_math = 0;
4020 /* The default values of these switches depend on the TARGET_64BIT
4021 that is not known at this moment. Mark these values with 2 and
4022 let user the to override these. In case there is no command line option
4023 specifying them, we will set the defaults in override_options. */
4025 flag_omit_frame_pointer = 2;
4026 flag_pcc_struct_return = 2;
4027 flag_asynchronous_unwind_tables = 2;
4028 flag_vect_cost_model = 1;
4029 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4030 SUBTARGET_OPTIMIZATION_OPTIONS;
4034 /* Decide whether we can make a sibling call to a function. DECL is the
4035 declaration of the function being targeted by the call and EXP is the
4036 CALL_EXPR representing the call. */
4039 ix86_function_ok_for_sibcall (tree decl, tree exp)
4044 /* If we are generating position-independent code, we cannot sibcall
4045 optimize any indirect call, or a direct call to a global function,
4046 as the PLT requires %ebx be live. */
4047 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4054 func = TREE_TYPE (CALL_EXPR_FN (exp));
4055 if (POINTER_TYPE_P (func))
4056 func = TREE_TYPE (func);
4059 /* Check that the return value locations are the same. Like
4060 if we are returning floats on the 80387 register stack, we cannot
4061 make a sibcall from a function that doesn't return a float to a
4062 function that does or, conversely, from a function that does return
4063 a float to a function that doesn't; the necessary stack adjustment
4064 would not be executed. This is also the place we notice
4065 differences in the return value ABI. Note that it is ok for one
4066 of the functions to have void return type as long as the return
4067 value of the other is passed in a register. */
4068 a = ix86_function_value (TREE_TYPE (exp), func, false);
4069 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4071 if (STACK_REG_P (a) || STACK_REG_P (b))
4073 if (!rtx_equal_p (a, b))
4076 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4078 else if (!rtx_equal_p (a, b))
4081 /* If this call is indirect, we'll need to be able to use a call-clobbered
4082 register for the address of the target function. Make sure that all
4083 such registers are not used for passing parameters. */
4084 if (!decl && !TARGET_64BIT)
4088 /* We're looking at the CALL_EXPR, we need the type of the function. */
4089 type = CALL_EXPR_FN (exp); /* pointer expression */
4090 type = TREE_TYPE (type); /* pointer type */
4091 type = TREE_TYPE (type); /* function type */
4093 if (ix86_function_regparm (type, NULL) >= 3)
4095 /* ??? Need to count the actual number of registers to be used,
4096 not the possible number of registers. Fix later. */
4101 /* Dllimport'd functions are also called indirectly. */
4102 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4104 && decl && DECL_DLLIMPORT_P (decl)
4105 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4108 /* Otherwise okay. That also includes certain types of indirect calls. */
4112 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4113 calling convention attributes;
4114 arguments as in struct attribute_spec.handler. */
4117 ix86_handle_cconv_attribute (tree *node, tree name,
4119 int flags ATTRIBUTE_UNUSED,
4122 if (TREE_CODE (*node) != FUNCTION_TYPE
4123 && TREE_CODE (*node) != METHOD_TYPE
4124 && TREE_CODE (*node) != FIELD_DECL
4125 && TREE_CODE (*node) != TYPE_DECL)
4127 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4128 IDENTIFIER_POINTER (name));
4129 *no_add_attrs = true;
4133 /* Can combine regparm with all attributes but fastcall. */
4134 if (is_attribute_p ("regparm", name))
4138 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4140 error ("fastcall and regparm attributes are not compatible");
4143 cst = TREE_VALUE (args);
4144 if (TREE_CODE (cst) != INTEGER_CST)
4146 warning (OPT_Wattributes,
4147 "%qs attribute requires an integer constant argument",
4148 IDENTIFIER_POINTER (name));
4149 *no_add_attrs = true;
4151 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4153 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4154 IDENTIFIER_POINTER (name), REGPARM_MAX);
4155 *no_add_attrs = true;
4163 /* Do not warn when emulating the MS ABI. */
4164 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4165 warning (OPT_Wattributes, "%qs attribute ignored",
4166 IDENTIFIER_POINTER (name));
4167 *no_add_attrs = true;
4171 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4172 if (is_attribute_p ("fastcall", name))
4174 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4176 error ("fastcall and cdecl attributes are not compatible");
4178 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4180 error ("fastcall and stdcall attributes are not compatible");
4182 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4184 error ("fastcall and regparm attributes are not compatible");
4188 /* Can combine stdcall with fastcall (redundant), regparm and
4190 else if (is_attribute_p ("stdcall", name))
4192 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4194 error ("stdcall and cdecl attributes are not compatible");
4196 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4198 error ("stdcall and fastcall attributes are not compatible");
4202 /* Can combine cdecl with regparm and sseregparm. */
4203 else if (is_attribute_p ("cdecl", name))
4205 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4207 error ("stdcall and cdecl attributes are not compatible");
4209 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4211 error ("fastcall and cdecl attributes are not compatible");
4215 /* Can combine sseregparm with all attributes. */
4220 /* Return 0 if the attributes for two types are incompatible, 1 if they
4221 are compatible, and 2 if they are nearly compatible (which causes a
4222 warning to be generated). */
4225 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4227 /* Check for mismatch of non-default calling convention. */
4228 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4230 if (TREE_CODE (type1) != FUNCTION_TYPE
4231 && TREE_CODE (type1) != METHOD_TYPE)
4234 /* Check for mismatched fastcall/regparm types. */
4235 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4236 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4237 || (ix86_function_regparm (type1, NULL)
4238 != ix86_function_regparm (type2, NULL)))
4241 /* Check for mismatched sseregparm types. */
4242 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4243 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4246 /* Check for mismatched return types (cdecl vs stdcall). */
4247 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4248 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4254 /* Return the regparm value for a function with the indicated TYPE and DECL.
4255 DECL may be NULL when calling function indirectly
4256 or considering a libcall. */
4259 ix86_function_regparm (const_tree type, const_tree decl)
4262 int regparm = ix86_regparm;
4264 static bool error_issued;
4268 if (ix86_function_type_abi (type) == DEFAULT_ABI)
4270 return DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
4273 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4277 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4279 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4281 /* We can't use regparm(3) for nested functions because
4282 these pass static chain pointer in %ecx register. */
4283 if (!error_issued && regparm == 3
4284 && decl_function_context (decl)
4285 && !DECL_NO_STATIC_CHAIN (decl))
4287 error ("nested functions are limited to 2 register parameters");
4288 error_issued = true;
4296 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4299 /* Use register calling convention for local functions when possible. */
4300 if (decl && TREE_CODE (decl) == FUNCTION_DECL
4303 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4304 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4307 int local_regparm, globals = 0, regno;
4310 /* Make sure no regparm register is taken by a
4311 fixed register variable. */
4312 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4313 if (fixed_regs[local_regparm])
4316 /* We can't use regparm(3) for nested functions as these use
4317 static chain pointer in third argument. */
4318 if (local_regparm == 3
4319 && decl_function_context (decl)
4320 && !DECL_NO_STATIC_CHAIN (decl))
4323 /* If the function realigns its stackpointer, the prologue will
4324 clobber %ecx. If we've already generated code for the callee,
4325 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4326 scanning the attributes for the self-realigning property. */
4327 f = DECL_STRUCT_FUNCTION (decl);
4328 /* Since current internal arg pointer won't conflict with
4329 parameter passing regs, so no need to change stack
4330 realignment and adjust regparm number.
4332 Each fixed register usage increases register pressure,
4333 so less registers should be used for argument passing.
4334 This functionality can be overriden by an explicit
4336 for (regno = 0; regno <= DI_REG; regno++)
4337 if (fixed_regs[regno])
4341 = globals < local_regparm ? local_regparm - globals : 0;
4343 if (local_regparm > regparm)
4344 regparm = local_regparm;
4351 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4352 DFmode (2) arguments in SSE registers for a function with the
4353 indicated TYPE and DECL. DECL may be NULL when calling function
4354 indirectly or considering a libcall. Otherwise return 0. */
4357 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4359 gcc_assert (!TARGET_64BIT);
4361 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4362 by the sseregparm attribute. */
4363 if (TARGET_SSEREGPARM
4364 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4371 error ("Calling %qD with attribute sseregparm without "
4372 "SSE/SSE2 enabled", decl);
4374 error ("Calling %qT with attribute sseregparm without "
4375 "SSE/SSE2 enabled", type);
4383 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4384 (and DFmode for SSE2) arguments in SSE registers. */
4385 if (decl && TARGET_SSE_MATH && !profile_flag)
4387 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4388 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4390 return TARGET_SSE2 ? 2 : 1;
4396 /* Return true if EAX is live at the start of the function. Used by
4397 ix86_expand_prologue to determine if we need special help before
4398 calling allocate_stack_worker. */
4401 ix86_eax_live_at_start_p (void)
4403 /* Cheat. Don't bother working forward from ix86_function_regparm
4404 to the function type to whether an actual argument is located in
4405 eax. Instead just look at cfg info, which is still close enough
4406 to correct at this point. This gives false positives for broken
4407 functions that might use uninitialized data that happens to be
4408 allocated in eax, but who cares? */
4409 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4412 /* Value is the number of bytes of arguments automatically
4413 popped when returning from a subroutine call.
4414 FUNDECL is the declaration node of the function (as a tree),
4415 FUNTYPE is the data type of the function (as a tree),
4416 or for a library call it is an identifier node for the subroutine name.
4417 SIZE is the number of bytes of arguments passed on the stack.
4419 On the 80386, the RTD insn may be used to pop them if the number
4420 of args is fixed, but if the number is variable then the caller
4421 must pop them all. RTD can't be used for library calls now
4422 because the library is compiled with the Unix compiler.
4423 Use of RTD is a selectable option, since it is incompatible with
4424 standard Unix calling sequences. If the option is not selected,
4425 the caller must always pop the args.
4427 The attribute stdcall is equivalent to RTD on a per module basis. */
4430 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4434 /* None of the 64-bit ABIs pop arguments. */
4438 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4440 /* Cdecl functions override -mrtd, and never pop the stack. */
4441 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4443 /* Stdcall and fastcall functions will pop the stack if not
4445 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4446 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4449 if (rtd && ! stdarg_p (funtype))
4453 /* Lose any fake structure return argument if it is passed on the stack. */
4454 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4455 && !KEEP_AGGREGATE_RETURN_POINTER)
4457 int nregs = ix86_function_regparm (funtype, fundecl);
4459 return GET_MODE_SIZE (Pmode);
4465 /* Argument support functions. */
4467 /* Return true when register may be used to pass function parameters. */
4469 ix86_function_arg_regno_p (int regno)
4472 const int *parm_regs;
4477 return (regno < REGPARM_MAX
4478 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4480 return (regno < REGPARM_MAX
4481 || (TARGET_MMX && MMX_REGNO_P (regno)
4482 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4483 || (TARGET_SSE && SSE_REGNO_P (regno)
4484 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4489 if (SSE_REGNO_P (regno) && TARGET_SSE)
4494 if (TARGET_SSE && SSE_REGNO_P (regno)
4495 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4499 /* TODO: The function should depend on current function ABI but
4500 builtins.c would need updating then. Therefore we use the
4503 /* RAX is used as hidden argument to va_arg functions. */
4504 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4507 if (DEFAULT_ABI == MS_ABI)
4508 parm_regs = x86_64_ms_abi_int_parameter_registers;
4510 parm_regs = x86_64_int_parameter_registers;
4511 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4512 : X86_64_REGPARM_MAX); i++)
4513 if (regno == parm_regs[i])
4518 /* Return if we do not know how to pass TYPE solely in registers. */
4521 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4523 if (must_pass_in_stack_var_size_or_pad (mode, type))
4526 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4527 The layout_type routine is crafty and tries to trick us into passing
4528 currently unsupported vector types on the stack by using TImode. */
4529 return (!TARGET_64BIT && mode == TImode
4530 && type && TREE_CODE (type) != VECTOR_TYPE);
4533 /* It returns the size, in bytes, of the area reserved for arguments passed
4534 in registers for the function represented by fndecl dependent to the used
4537 ix86_reg_parm_stack_space (const_tree fndecl)
4540 /* For libcalls it is possible that there is no fndecl at hand.
4541 Therefore assume for this case the default abi of the target. */
4543 call_abi = DEFAULT_ABI;
4545 call_abi = ix86_function_abi (fndecl);
4551 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4554 ix86_function_type_abi (const_tree fntype)
4556 if (TARGET_64BIT && fntype != NULL)
4559 if (DEFAULT_ABI == SYSV_ABI)
4560 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4562 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4570 ix86_function_abi (const_tree fndecl)
4574 return ix86_function_type_abi (TREE_TYPE (fndecl));
4577 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4580 ix86_cfun_abi (void)
4582 if (! cfun || ! TARGET_64BIT)
4584 return cfun->machine->call_abi;
4588 extern void init_regs (void);
4590 /* Implementation of call abi switching target hook. Specific to FNDECL
4591 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4593 To prevent redudant calls of costy function init_regs (), it checks not to
4594 reset register usage for default abi. */
4596 ix86_call_abi_override (const_tree fndecl)
4598 if (fndecl == NULL_TREE)
4599 cfun->machine->call_abi = DEFAULT_ABI;
4601 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4602 if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
4604 if (call_used_regs[4 /*RSI*/] != 0 || call_used_regs[5 /*RDI*/] != 0)
4606 call_used_regs[4 /*RSI*/] = 0;
4607 call_used_regs[5 /*RDI*/] = 0;
4611 else if (TARGET_64BIT)
4613 if (call_used_regs[4 /*RSI*/] != 1 || call_used_regs[5 /*RDI*/] != 1)
4615 call_used_regs[4 /*RSI*/] = 1;
4616 call_used_regs[5 /*RDI*/] = 1;
4622 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4623 for a call to a function whose data type is FNTYPE.
4624 For a library call, FNTYPE is 0. */
4627 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4628 tree fntype, /* tree ptr for function decl */
4629 rtx libname, /* SYMBOL_REF of library name or 0 */
4632 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4633 memset (cum, 0, sizeof (*cum));
4635 cum->call_abi = ix86_function_type_abi (fntype);
4636 /* Set up the number of registers to use for passing arguments. */
4637 cum->nregs = ix86_regparm;
4640 if (cum->call_abi != DEFAULT_ABI)
4641 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4646 cum->sse_nregs = SSE_REGPARM_MAX;
4649 if (cum->call_abi != DEFAULT_ABI)
4650 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4651 : X64_SSE_REGPARM_MAX;
4655 cum->mmx_nregs = MMX_REGPARM_MAX;
4656 cum->warn_avx = true;
4657 cum->warn_sse = true;
4658 cum->warn_mmx = true;
4660 /* Because type might mismatch in between caller and callee, we need to
4661 use actual type of function for local calls.
4662 FIXME: cgraph_analyze can be told to actually record if function uses
4663 va_start so for local functions maybe_vaarg can be made aggressive
4665 FIXME: once typesytem is fixed, we won't need this code anymore. */
4667 fntype = TREE_TYPE (fndecl);
4668 cum->maybe_vaarg = (fntype
4669 ? (!prototype_p (fntype) || stdarg_p (fntype))
4674 /* If there are variable arguments, then we won't pass anything
4675 in registers in 32-bit mode. */
4676 if (stdarg_p (fntype))
4687 /* Use ecx and edx registers if function has fastcall attribute,
4688 else look for regparm information. */
4691 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4697 cum->nregs = ix86_function_regparm (fntype, fndecl);
4700 /* Set up the number of SSE registers used for passing SFmode
4701 and DFmode arguments. Warn for mismatching ABI. */
4702 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4706 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4707 But in the case of vector types, it is some vector mode.
4709 When we have only some of our vector isa extensions enabled, then there
4710 are some modes for which vector_mode_supported_p is false. For these
4711 modes, the generic vector support in gcc will choose some non-vector mode
4712 in order to implement the type. By computing the natural mode, we'll
4713 select the proper ABI location for the operand and not depend on whatever
4714 the middle-end decides to do with these vector types. */
4716 static enum machine_mode
4717 type_natural_mode (const_tree type)
4719 enum machine_mode mode = TYPE_MODE (type);
4721 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4723 HOST_WIDE_INT size = int_size_in_bytes (type);
4724 if ((size == 8 || size == 16)
4725 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4726 && TYPE_VECTOR_SUBPARTS (type) > 1)
4728 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4730 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4731 mode = MIN_MODE_VECTOR_FLOAT;
4733 mode = MIN_MODE_VECTOR_INT;
4735 /* Get the mode which has this inner mode and number of units. */
4736 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4737 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4738 && GET_MODE_INNER (mode) == innermode)
4748 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4749 this may not agree with the mode that the type system has chosen for the
4750 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4751 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4754 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4759 if (orig_mode != BLKmode)
4760 tmp = gen_rtx_REG (orig_mode, regno);
4763 tmp = gen_rtx_REG (mode, regno);
4764 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4765 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4771 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4772 of this code is to classify each 8bytes of incoming argument by the register
4773 class and assign registers accordingly. */
4775 /* Return the union class of CLASS1 and CLASS2.
4776 See the x86-64 PS ABI for details. */
4778 static enum x86_64_reg_class
4779 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4781 /* Rule #1: If both classes are equal, this is the resulting class. */
4782 if (class1 == class2)
4785 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4787 if (class1 == X86_64_NO_CLASS)
4789 if (class2 == X86_64_NO_CLASS)
4792 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4793 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4794 return X86_64_MEMORY_CLASS;
4796 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4797 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4798 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4799 return X86_64_INTEGERSI_CLASS;
4800 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4801 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4802 return X86_64_INTEGER_CLASS;
4804 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4806 if (class1 == X86_64_X87_CLASS
4807 || class1 == X86_64_X87UP_CLASS
4808 || class1 == X86_64_COMPLEX_X87_CLASS
4809 || class2 == X86_64_X87_CLASS
4810 || class2 == X86_64_X87UP_CLASS
4811 || class2 == X86_64_COMPLEX_X87_CLASS)
4812 return X86_64_MEMORY_CLASS;
4814 /* Rule #6: Otherwise class SSE is used. */
4815 return X86_64_SSE_CLASS;
4818 /* Classify the argument of type TYPE and mode MODE.
4819 CLASSES will be filled by the register class used to pass each word
4820 of the operand. The number of words is returned. In case the parameter
4821 should be passed in memory, 0 is returned. As a special case for zero
4822 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4824 BIT_OFFSET is used internally for handling records and specifies offset
4825 of the offset in bits modulo 256 to avoid overflow cases.
4827 See the x86-64 PS ABI for details.
4831 classify_argument (enum machine_mode mode, const_tree type,
4832 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4834 HOST_WIDE_INT bytes =
4835 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4836 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4838 /* Variable sized entities are always passed/returned in memory. */
4842 if (mode != VOIDmode
4843 && targetm.calls.must_pass_in_stack (mode, type))
4846 if (type && AGGREGATE_TYPE_P (type))
4850 enum x86_64_reg_class subclasses[MAX_CLASSES];
4852 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
4856 for (i = 0; i < words; i++)
4857 classes[i] = X86_64_NO_CLASS;
4859 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4860 signalize memory class, so handle it as special case. */
4863 classes[0] = X86_64_NO_CLASS;
4867 /* Classify each field of record and merge classes. */
4868 switch (TREE_CODE (type))
4871 /* And now merge the fields of structure. */
4872 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4874 if (TREE_CODE (field) == FIELD_DECL)
4878 if (TREE_TYPE (field) == error_mark_node)
4881 /* Bitfields are always classified as integer. Handle them
4882 early, since later code would consider them to be
4883 misaligned integers. */
4884 if (DECL_BIT_FIELD (field))
4886 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4887 i < ((int_bit_position (field) + (bit_offset % 64))
4888 + tree_low_cst (DECL_SIZE (field), 0)
4891 merge_classes (X86_64_INTEGER_CLASS,
4896 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4897 TREE_TYPE (field), subclasses,
4898 (int_bit_position (field)
4899 + bit_offset) % 256);
4902 for (i = 0; i < num; i++)
4905 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4907 merge_classes (subclasses[i], classes[i + pos]);
4915 /* Arrays are handled as small records. */
4918 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
4919 TREE_TYPE (type), subclasses, bit_offset);
4923 /* The partial classes are now full classes. */
4924 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
4925 subclasses[0] = X86_64_SSE_CLASS;
4926 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
4927 subclasses[0] = X86_64_INTEGER_CLASS;
4929 for (i = 0; i < words; i++)
4930 classes[i] = subclasses[i % num];
4935 case QUAL_UNION_TYPE:
4936 /* Unions are similar to RECORD_TYPE but offset is always 0.
4938 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4940 if (TREE_CODE (field) == FIELD_DECL)
4944 if (TREE_TYPE (field) == error_mark_node)
4947 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4948 TREE_TYPE (field), subclasses,
4952 for (i = 0; i < num; i++)
4953 classes[i] = merge_classes (subclasses[i], classes[i]);
4962 /* Final merger cleanup. */
4963 for (i = 0; i < words; i++)
4965 /* If one class is MEMORY, everything should be passed in
4967 if (classes[i] == X86_64_MEMORY_CLASS)
4970 /* The X86_64_SSEUP_CLASS should be always preceded by
4971 X86_64_SSE_CLASS. */
4972 if (classes[i] == X86_64_SSEUP_CLASS
4973 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
4974 classes[i] = X86_64_SSE_CLASS;
4976 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
4977 if (classes[i] == X86_64_X87UP_CLASS
4978 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
4979 classes[i] = X86_64_SSE_CLASS;
4984 /* Compute alignment needed. We align all types to natural boundaries with
4985 exception of XFmode that is aligned to 64bits. */
4986 if (mode != VOIDmode && mode != BLKmode)
4988 int mode_alignment = GET_MODE_BITSIZE (mode);
4991 mode_alignment = 128;
4992 else if (mode == XCmode)
4993 mode_alignment = 256;
4994 if (COMPLEX_MODE_P (mode))
4995 mode_alignment /= 2;
4996 /* Misaligned fields are always returned in memory. */
4997 if (bit_offset % mode_alignment)
5001 /* for V1xx modes, just use the base mode */
5002 if (VECTOR_MODE_P (mode) && mode != V1DImode
5003 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5004 mode = GET_MODE_INNER (mode);
5006 /* Classification of atomic types. */
5011 classes[0] = X86_64_SSE_CLASS;
5014 classes[0] = X86_64_SSE_CLASS;
5015 classes[1] = X86_64_SSEUP_CLASS;
5024 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5025 classes[0] = X86_64_INTEGERSI_CLASS;
5027 classes[0] = X86_64_INTEGER_CLASS;
5031 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5038 if (!(bit_offset % 64))
5039 classes[0] = X86_64_SSESF_CLASS;
5041 classes[0] = X86_64_SSE_CLASS;
5044 classes[0] = X86_64_SSEDF_CLASS;
5047 classes[0] = X86_64_X87_CLASS;
5048 classes[1] = X86_64_X87UP_CLASS;
5051 classes[0] = X86_64_SSE_CLASS;
5052 classes[1] = X86_64_SSEUP_CLASS;
5055 classes[0] = X86_64_SSE_CLASS;
5058 classes[0] = X86_64_SSEDF_CLASS;
5059 classes[1] = X86_64_SSEDF_CLASS;
5062 classes[0] = X86_64_COMPLEX_X87_CLASS;
5065 /* This modes is larger than 16 bytes. */
5073 classes[0] = X86_64_AVX_CLASS;
5081 classes[0] = X86_64_SSE_CLASS;
5082 classes[1] = X86_64_SSEUP_CLASS;
5089 classes[0] = X86_64_SSE_CLASS;
5095 gcc_assert (VECTOR_MODE_P (mode));
5100 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5102 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5103 classes[0] = X86_64_INTEGERSI_CLASS;
5105 classes[0] = X86_64_INTEGER_CLASS;
5106 classes[1] = X86_64_INTEGER_CLASS;
5107 return 1 + (bytes > 8);
5111 /* Examine the argument and return set number of register required in each
5112 class. Return 0 iff parameter should be passed in memory. */
5114 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5115 int *int_nregs, int *sse_nregs)
5117 enum x86_64_reg_class regclass[MAX_CLASSES];
5118 int n = classify_argument (mode, type, regclass, 0);
5124 for (n--; n >= 0; n--)
5125 switch (regclass[n])
5127 case X86_64_INTEGER_CLASS:
5128 case X86_64_INTEGERSI_CLASS:
5131 case X86_64_AVX_CLASS:
5132 case X86_64_SSE_CLASS:
5133 case X86_64_SSESF_CLASS:
5134 case X86_64_SSEDF_CLASS:
5137 case X86_64_NO_CLASS:
5138 case X86_64_SSEUP_CLASS:
5140 case X86_64_X87_CLASS:
5141 case X86_64_X87UP_CLASS:
5145 case X86_64_COMPLEX_X87_CLASS:
5146 return in_return ? 2 : 0;
5147 case X86_64_MEMORY_CLASS:
5153 /* Construct container for the argument used by GCC interface. See
5154 FUNCTION_ARG for the detailed description. */
5157 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5158 const_tree type, int in_return, int nintregs, int nsseregs,
5159 const int *intreg, int sse_regno)
5161 /* The following variables hold the static issued_error state. */
5162 static bool issued_sse_arg_error;
5163 static bool issued_sse_ret_error;
5164 static bool issued_x87_ret_error;
5166 enum machine_mode tmpmode;
5168 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5169 enum x86_64_reg_class regclass[MAX_CLASSES];
5173 int needed_sseregs, needed_intregs;
5174 rtx exp[MAX_CLASSES];
5177 n = classify_argument (mode, type, regclass, 0);
5180 if (!examine_argument (mode, type, in_return, &needed_intregs,
5183 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5186 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5187 some less clueful developer tries to use floating-point anyway. */
5188 if (needed_sseregs && !TARGET_SSE)
5192 if (!issued_sse_ret_error)
5194 error ("SSE register return with SSE disabled");
5195 issued_sse_ret_error = true;
5198 else if (!issued_sse_arg_error)
5200 error ("SSE register argument with SSE disabled");
5201 issued_sse_arg_error = true;
5206 /* Likewise, error if the ABI requires us to return values in the
5207 x87 registers and the user specified -mno-80387. */
5208 if (!TARGET_80387 && in_return)
5209 for (i = 0; i < n; i++)
5210 if (regclass[i] == X86_64_X87_CLASS
5211 || regclass[i] == X86_64_X87UP_CLASS
5212 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5214 if (!issued_x87_ret_error)
5216 error ("x87 register return with x87 disabled");
5217 issued_x87_ret_error = true;
5222 /* First construct simple cases. Avoid SCmode, since we want to use
5223 single register to pass this type. */
5224 if (n == 1 && mode != SCmode)
5225 switch (regclass[0])
5227 case X86_64_INTEGER_CLASS:
5228 case X86_64_INTEGERSI_CLASS:
5229 return gen_rtx_REG (mode, intreg[0]);
5230 case X86_64_AVX_CLASS:
5231 case X86_64_SSE_CLASS:
5232 case X86_64_SSESF_CLASS:
5233 case X86_64_SSEDF_CLASS:
5234 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
5235 case X86_64_X87_CLASS:
5236 case X86_64_COMPLEX_X87_CLASS:
5237 return gen_rtx_REG (mode, FIRST_STACK_REG);
5238 case X86_64_NO_CLASS:
5239 /* Zero sized array, struct or class. */
5244 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5245 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5246 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5249 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5250 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5251 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5252 && regclass[1] == X86_64_INTEGER_CLASS
5253 && (mode == CDImode || mode == TImode || mode == TFmode)
5254 && intreg[0] + 1 == intreg[1])
5255 return gen_rtx_REG (mode, intreg[0]);
5257 /* Otherwise figure out the entries of the PARALLEL. */
5258 for (i = 0; i < n; i++)
5260 switch (regclass[i])
5262 case X86_64_NO_CLASS:
5264 case X86_64_INTEGER_CLASS:
5265 case X86_64_INTEGERSI_CLASS:
5266 /* Merge TImodes on aligned occasions here too. */
5267 if (i * 8 + 8 > bytes)
5268 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5269 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5273 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5274 if (tmpmode == BLKmode)
5276 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5277 gen_rtx_REG (tmpmode, *intreg),
5281 case X86_64_SSESF_CLASS:
5282 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5283 gen_rtx_REG (SFmode,
5284 SSE_REGNO (sse_regno)),
5288 case X86_64_SSEDF_CLASS:
5289 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5290 gen_rtx_REG (DFmode,
5291 SSE_REGNO (sse_regno)),
5295 case X86_64_SSE_CLASS:
5296 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
5300 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5301 gen_rtx_REG (tmpmode,
5302 SSE_REGNO (sse_regno)),
5304 if (tmpmode == TImode)
5313 /* Empty aligned struct, union or class. */
5317 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5318 for (i = 0; i < nexps; i++)
5319 XVECEXP (ret, 0, i) = exp [i];
5323 /* Update the data in CUM to advance over an argument of mode MODE
5324 and data type TYPE. (TYPE is null for libcalls where that information
5325 may not be available.) */
5328 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5329 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5345 cum->words += words;
5346 cum->nregs -= words;
5347 cum->regno += words;
5349 if (cum->nregs <= 0)
5357 if (cum->float_in_sse < 2)
5360 if (cum->float_in_sse < 1)
5378 if (!type || !AGGREGATE_TYPE_P (type))
5380 cum->sse_words += words;
5381 cum->sse_nregs -= 1;
5382 cum->sse_regno += 1;
5383 if (cum->sse_nregs <= 0)
5396 if (!type || !AGGREGATE_TYPE_P (type))
5398 cum->mmx_words += words;
5399 cum->mmx_nregs -= 1;
5400 cum->mmx_regno += 1;
5401 if (cum->mmx_nregs <= 0)
5412 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5413 tree type, HOST_WIDE_INT words, int named)
5415 int int_nregs, sse_nregs;
5417 /* Unnamed 256bit vector mode parameters are passed on stack. */
5418 if (!named && VALID_AVX256_REG_MODE (mode))
5421 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5422 cum->words += words;
5423 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5425 cum->nregs -= int_nregs;
5426 cum->sse_nregs -= sse_nregs;
5427 cum->regno += int_nregs;
5428 cum->sse_regno += sse_nregs;
5431 cum->words += words;
5435 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5436 HOST_WIDE_INT words)
5438 /* Otherwise, this should be passed indirect. */
5439 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5441 cum->words += words;
5450 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5451 tree type, int named)
5453 HOST_WIDE_INT bytes, words;
5455 if (mode == BLKmode)
5456 bytes = int_size_in_bytes (type);
5458 bytes = GET_MODE_SIZE (mode);
5459 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5462 mode = type_natural_mode (type);
5464 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5465 function_arg_advance_ms_64 (cum, bytes, words);
5466 else if (TARGET_64BIT)
5467 function_arg_advance_64 (cum, mode, type, words, named);
5469 function_arg_advance_32 (cum, mode, type, bytes, words);
5472 /* Define where to put the arguments to a function.
5473 Value is zero to push the argument on the stack,
5474 or a hard register in which to store the argument.
5476 MODE is the argument's machine mode.
5477 TYPE is the data type of the argument (as a tree).
5478 This is null for libcalls where that information may
5480 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5481 the preceding args and about the function being called.
5482 NAMED is nonzero if this argument is a named parameter
5483 (otherwise it is an extra parameter matching an ellipsis). */
5486 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5487 enum machine_mode orig_mode, tree type,
5488 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5490 static bool warnedavx, warnedsse, warnedmmx;
5492 /* Avoid the AL settings for the Unix64 ABI. */
5493 if (mode == VOIDmode)
5509 if (words <= cum->nregs)
5511 int regno = cum->regno;
5513 /* Fastcall allocates the first two DWORD (SImode) or
5514 smaller arguments to ECX and EDX if it isn't an
5520 || (type && AGGREGATE_TYPE_P (type)))
5523 /* ECX not EAX is the first allocated register. */
5524 if (regno == AX_REG)
5527 return gen_rtx_REG (mode, regno);
5532 if (cum->float_in_sse < 2)
5535 if (cum->float_in_sse < 1)
5539 /* In 32bit, we pass TImode in xmm registers. */
5546 if (!type || !AGGREGATE_TYPE_P (type))
5548 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5551 warning (0, "SSE vector argument without SSE enabled "
5555 return gen_reg_or_parallel (mode, orig_mode,
5556 cum->sse_regno + FIRST_SSE_REG);
5561 /* In 32bit, we pass OImode in ymm registers. */
5568 if (!type || !AGGREGATE_TYPE_P (type))
5570 if (!TARGET_AVX && !warnedavx && cum->warn_avx)
5573 warning (0, "AVX vector argument without AVX enabled "
5577 return gen_reg_or_parallel (mode, orig_mode,
5578 cum->sse_regno + FIRST_SSE_REG);
5587 if (!type || !AGGREGATE_TYPE_P (type))
5589 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5592 warning (0, "MMX vector argument without MMX enabled "
5596 return gen_reg_or_parallel (mode, orig_mode,
5597 cum->mmx_regno + FIRST_MMX_REG);
5606 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5607 enum machine_mode orig_mode, tree type, int named)
5609 static bool warnedavx;
5611 /* Handle a hidden AL argument containing number of registers
5612 for varargs x86-64 functions. */
5613 if (mode == VOIDmode)
5614 return GEN_INT (cum->maybe_vaarg
5615 ? (cum->sse_nregs < 0
5616 ? (cum->call_abi == DEFAULT_ABI
5618 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5619 : X64_SSE_REGPARM_MAX))
5634 /* In 64bit, we pass TImode in interger registers and OImode on
5636 if (!type || !AGGREGATE_TYPE_P (type))
5638 if (!TARGET_AVX && !warnedavx && cum->warn_avx)
5641 warning (0, "AVX vector argument without AVX enabled "
5646 /* Unnamed 256bit vector mode parameters are passed on stack. */
5652 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5654 &x86_64_int_parameter_registers [cum->regno],
5659 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5660 enum machine_mode orig_mode, int named,
5661 HOST_WIDE_INT bytes)
5665 /* Avoid the AL settings for the Unix64 ABI. */
5666 if (mode == VOIDmode)
5669 /* If we've run out of registers, it goes on the stack. */
5670 if (cum->nregs == 0)
5673 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5675 /* Only floating point modes are passed in anything but integer regs. */
5676 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5679 regno = cum->regno + FIRST_SSE_REG;
5684 /* Unnamed floating parameters are passed in both the
5685 SSE and integer registers. */
5686 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5687 t2 = gen_rtx_REG (mode, regno);
5688 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5689 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5690 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5693 /* Handle aggregated types passed in register. */
5694 if (orig_mode == BLKmode)
5696 if (bytes > 0 && bytes <= 8)
5697 mode = (bytes > 4 ? DImode : SImode);
5698 if (mode == BLKmode)
5702 return gen_reg_or_parallel (mode, orig_mode, regno);
5706 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5707 tree type, int named)
5709 enum machine_mode mode = omode;
5710 HOST_WIDE_INT bytes, words;
5712 if (mode == BLKmode)
5713 bytes = int_size_in_bytes (type);
5715 bytes = GET_MODE_SIZE (mode);
5716 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5718 /* To simplify the code below, represent vector types with a vector mode
5719 even if MMX/SSE are not active. */
5720 if (type && TREE_CODE (type) == VECTOR_TYPE)
5721 mode = type_natural_mode (type);
5723 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5724 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5725 else if (TARGET_64BIT)
5726 return function_arg_64 (cum, mode, omode, type, named);
5728 return function_arg_32 (cum, mode, omode, type, bytes, words);
5731 /* A C expression that indicates when an argument must be passed by
5732 reference. If nonzero for an argument, a copy of that argument is
5733 made in memory and a pointer to the argument is passed instead of
5734 the argument itself. The pointer is passed in whatever way is
5735 appropriate for passing a pointer to that type. */
5738 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5739 enum machine_mode mode ATTRIBUTE_UNUSED,
5740 const_tree type, bool named ATTRIBUTE_UNUSED)
5742 /* See Windows x64 Software Convention. */
5743 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5745 int msize = (int) GET_MODE_SIZE (mode);
5748 /* Arrays are passed by reference. */
5749 if (TREE_CODE (type) == ARRAY_TYPE)
5752 if (AGGREGATE_TYPE_P (type))
5754 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5755 are passed by reference. */
5756 msize = int_size_in_bytes (type);
5760 /* __m128 is passed by reference. */
5762 case 1: case 2: case 4: case 8:
5768 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5774 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5777 contains_aligned_value_p (tree type)
5779 enum machine_mode mode = TYPE_MODE (type);
5780 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
5784 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
5786 if (TYPE_ALIGN (type) < 128)
5789 if (AGGREGATE_TYPE_P (type))
5791 /* Walk the aggregates recursively. */
5792 switch (TREE_CODE (type))
5796 case QUAL_UNION_TYPE:
5800 /* Walk all the structure fields. */
5801 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5803 if (TREE_CODE (field) == FIELD_DECL
5804 && contains_aligned_value_p (TREE_TYPE (field)))
5811 /* Just for use if some languages passes arrays by value. */
5812 if (contains_aligned_value_p (TREE_TYPE (type)))
5823 /* Gives the alignment boundary, in bits, of an argument with the
5824 specified mode and type. */
5827 ix86_function_arg_boundary (enum machine_mode mode, tree type)
5832 /* Since canonical type is used for call, we convert it to
5833 canonical type if needed. */
5834 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
5835 type = TYPE_CANONICAL (type);
5836 align = TYPE_ALIGN (type);
5839 align = GET_MODE_ALIGNMENT (mode);
5840 if (align < PARM_BOUNDARY)
5841 align = PARM_BOUNDARY;
5842 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5843 natural boundaries. */
5844 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
5846 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5847 make an exception for SSE modes since these require 128bit
5850 The handling here differs from field_alignment. ICC aligns MMX
5851 arguments to 4 byte boundaries, while structure fields are aligned
5852 to 8 byte boundaries. */
5855 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
5856 align = PARM_BOUNDARY;
5860 if (!contains_aligned_value_p (type))
5861 align = PARM_BOUNDARY;
5864 if (align > BIGGEST_ALIGNMENT)
5865 align = BIGGEST_ALIGNMENT;
5869 /* Return true if N is a possible register number of function value. */
5872 ix86_function_value_regno_p (int regno)
5879 case FIRST_FLOAT_REG:
5880 /* TODO: The function should depend on current function ABI but
5881 builtins.c would need updating then. Therefore we use the
5883 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
5885 return TARGET_FLOAT_RETURNS_IN_80387;
5891 if (TARGET_MACHO || TARGET_64BIT)
5899 /* Define how to find the value returned by a function.
5900 VALTYPE is the data type of the value (as a tree).
5901 If the precise function being called is known, FUNC is its FUNCTION_DECL;
5902 otherwise, FUNC is 0. */
5905 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
5906 const_tree fntype, const_tree fn)
5910 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
5911 we normally prevent this case when mmx is not available. However
5912 some ABIs may require the result to be returned like DImode. */
5913 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
5914 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
5916 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
5917 we prevent this case when sse is not available. However some ABIs
5918 may require the result to be returned like integer TImode. */
5919 else if (mode == TImode
5920 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
5921 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
5923 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
5924 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
5925 regno = FIRST_FLOAT_REG;
5927 /* Most things go in %eax. */
5930 /* Override FP return register with %xmm0 for local functions when
5931 SSE math is enabled or for functions with sseregparm attribute. */
5932 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
5934 int sse_level = ix86_function_sseregparm (fntype, fn, false);
5935 if ((sse_level >= 1 && mode == SFmode)
5936 || (sse_level == 2 && mode == DFmode))
5937 regno = FIRST_SSE_REG;
5940 return gen_rtx_REG (orig_mode, regno);
5944 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
5949 /* Handle libcalls, which don't provide a type node. */
5950 if (valtype == NULL)
5962 return gen_rtx_REG (mode, FIRST_SSE_REG);
5965 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
5969 return gen_rtx_REG (mode, AX_REG);
5973 ret = construct_container (mode, orig_mode, valtype, 1,
5974 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
5975 x86_64_int_return_registers, 0);
5977 /* For zero sized structures, construct_container returns NULL, but we
5978 need to keep rest of compiler happy by returning meaningful value. */
5980 ret = gen_rtx_REG (orig_mode, AX_REG);
5986 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
5988 unsigned int regno = AX_REG;
5992 switch (GET_MODE_SIZE (mode))
5995 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
5996 && !COMPLEX_MODE_P (mode))
5997 regno = FIRST_SSE_REG;
6001 if (mode == SFmode || mode == DFmode)
6002 regno = FIRST_SSE_REG;
6008 return gen_rtx_REG (orig_mode, regno);
6012 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6013 enum machine_mode orig_mode, enum machine_mode mode)
6015 const_tree fn, fntype;
6018 if (fntype_or_decl && DECL_P (fntype_or_decl))
6019 fn = fntype_or_decl;
6020 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6022 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6023 return function_value_ms_64 (orig_mode, mode);
6024 else if (TARGET_64BIT)
6025 return function_value_64 (orig_mode, mode, valtype);
6027 return function_value_32 (orig_mode, mode, fntype, fn);
6031 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6032 bool outgoing ATTRIBUTE_UNUSED)
6034 enum machine_mode mode, orig_mode;
6036 orig_mode = TYPE_MODE (valtype);
6037 mode = type_natural_mode (valtype);
6038 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6042 ix86_libcall_value (enum machine_mode mode)
6044 return ix86_function_value_1 (NULL, NULL, mode, mode);
6047 /* Return true iff type is returned in memory. */
6049 static int ATTRIBUTE_UNUSED
6050 return_in_memory_32 (const_tree type, enum machine_mode mode)
6054 if (mode == BLKmode)
6057 size = int_size_in_bytes (type);
6059 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6062 if (VECTOR_MODE_P (mode) || mode == TImode)
6064 /* User-created vectors small enough to fit in EAX. */
6068 /* MMX/3dNow values are returned in MM0,
6069 except when it doesn't exits. */
6071 return (TARGET_MMX ? 0 : 1);
6073 /* SSE values are returned in XMM0, except when it doesn't exist. */
6075 return (TARGET_SSE ? 0 : 1);
6086 static int ATTRIBUTE_UNUSED
6087 return_in_memory_64 (const_tree type, enum machine_mode mode)
6089 int needed_intregs, needed_sseregs;
6090 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6093 static int ATTRIBUTE_UNUSED
6094 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6096 HOST_WIDE_INT size = int_size_in_bytes (type);
6098 /* __m128 is returned in xmm0. */
6099 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6100 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6103 /* Otherwise, the size must be exactly in [1248]. */
6104 return (size != 1 && size != 2 && size != 4 && size != 8);
6108 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6110 #ifdef SUBTARGET_RETURN_IN_MEMORY
6111 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6113 const enum machine_mode mode = type_natural_mode (type);
6115 if (TARGET_64BIT_MS_ABI)
6116 return return_in_memory_ms_64 (type, mode);
6117 else if (TARGET_64BIT)
6118 return return_in_memory_64 (type, mode);
6120 return return_in_memory_32 (type, mode);
6124 /* Return false iff TYPE is returned in memory. This version is used
6125 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6126 but differs notably in that when MMX is available, 8-byte vectors
6127 are returned in memory, rather than in MMX registers. */
6130 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6133 enum machine_mode mode = type_natural_mode (type);
6136 return return_in_memory_64 (type, mode);
6138 if (mode == BLKmode)
6141 size = int_size_in_bytes (type);
6143 if (VECTOR_MODE_P (mode))
6145 /* Return in memory only if MMX registers *are* available. This
6146 seems backwards, but it is consistent with the existing
6153 else if (mode == TImode)
6155 else if (mode == XFmode)
6161 /* When returning SSE vector types, we have a choice of either
6162 (1) being abi incompatible with a -march switch, or
6163 (2) generating an error.
6164 Given no good solution, I think the safest thing is one warning.
6165 The user won't be able to use -Werror, but....
6167 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6168 called in response to actually generating a caller or callee that
6169 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6170 via aggregate_value_p for general type probing from tree-ssa. */
6173 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6175 static bool warnedsse, warnedmmx;
6177 if (!TARGET_64BIT && type)
6179 /* Look at the return type of the function, not the function type. */
6180 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6182 if (!TARGET_SSE && !warnedsse)
6185 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6188 warning (0, "SSE vector return without SSE enabled "
6193 if (!TARGET_MMX && !warnedmmx)
6195 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6198 warning (0, "MMX vector return without MMX enabled "
6208 /* Create the va_list data type. */
6210 /* Returns the calling convention specific va_list date type.
6211 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6214 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6216 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6218 /* For i386 we use plain pointer to argument area. */
6219 if (!TARGET_64BIT || abi == MS_ABI)
6220 return build_pointer_type (char_type_node);
6222 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6223 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6225 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6226 unsigned_type_node);
6227 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6228 unsigned_type_node);
6229 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6231 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6234 va_list_gpr_counter_field = f_gpr;
6235 va_list_fpr_counter_field = f_fpr;
6237 DECL_FIELD_CONTEXT (f_gpr) = record;
6238 DECL_FIELD_CONTEXT (f_fpr) = record;
6239 DECL_FIELD_CONTEXT (f_ovf) = record;
6240 DECL_FIELD_CONTEXT (f_sav) = record;
6242 TREE_CHAIN (record) = type_decl;
6243 TYPE_NAME (record) = type_decl;
6244 TYPE_FIELDS (record) = f_gpr;
6245 TREE_CHAIN (f_gpr) = f_fpr;
6246 TREE_CHAIN (f_fpr) = f_ovf;
6247 TREE_CHAIN (f_ovf) = f_sav;
6249 layout_type (record);
6251 /* The correct type is an array type of one element. */
6252 return build_array_type (record, build_index_type (size_zero_node));
6255 /* Setup the builtin va_list data type and for 64-bit the additional
6256 calling convention specific va_list data types. */
6259 ix86_build_builtin_va_list (void)
6261 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6263 /* Initialize abi specific va_list builtin types. */
6267 if (DEFAULT_ABI == MS_ABI)
6269 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6270 if (TREE_CODE (t) != RECORD_TYPE)
6271 t = build_variant_type_copy (t);
6272 sysv_va_list_type_node = t;
6277 if (TREE_CODE (t) != RECORD_TYPE)
6278 t = build_variant_type_copy (t);
6279 sysv_va_list_type_node = t;
6281 if (DEFAULT_ABI != MS_ABI)
6283 t = ix86_build_builtin_va_list_abi (MS_ABI);
6284 if (TREE_CODE (t) != RECORD_TYPE)
6285 t = build_variant_type_copy (t);
6286 ms_va_list_type_node = t;
6291 if (TREE_CODE (t) != RECORD_TYPE)
6292 t = build_variant_type_copy (t);
6293 ms_va_list_type_node = t;
6300 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6303 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6312 int regparm = ix86_regparm;
6314 if (cum->call_abi != DEFAULT_ABI)
6315 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6317 /* GPR size of varargs save area. */
6318 if (cfun->va_list_gpr_size)
6319 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6321 ix86_varargs_gpr_size = 0;
6323 /* FPR size of varargs save area. We don't need it if we don't pass
6324 anything in SSE registers. */
6325 if (cum->sse_nregs && cfun->va_list_fpr_size)
6326 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6328 ix86_varargs_fpr_size = 0;
6330 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6333 save_area = frame_pointer_rtx;
6334 set = get_varargs_alias_set ();
6336 for (i = cum->regno;
6338 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6341 mem = gen_rtx_MEM (Pmode,
6342 plus_constant (save_area, i * UNITS_PER_WORD));
6343 MEM_NOTRAP_P (mem) = 1;
6344 set_mem_alias_set (mem, set);
6345 emit_move_insn (mem, gen_rtx_REG (Pmode,
6346 x86_64_int_parameter_registers[i]));
6349 if (ix86_varargs_fpr_size)
6351 /* Now emit code to save SSE registers. The AX parameter contains number
6352 of SSE parameter registers used to call this function. We use
6353 sse_prologue_save insn template that produces computed jump across
6354 SSE saves. We need some preparation work to get this working. */
6356 label = gen_label_rtx ();
6357 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6359 /* Compute address to jump to :
6360 label - eax*4 + nnamed_sse_arguments*4 Or
6361 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6362 tmp_reg = gen_reg_rtx (Pmode);
6363 nsse_reg = gen_reg_rtx (Pmode);
6364 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6365 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6366 gen_rtx_MULT (Pmode, nsse_reg,
6369 /* vmovaps is one byte longer than movaps. */
6371 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6372 gen_rtx_PLUS (Pmode, tmp_reg,
6378 gen_rtx_CONST (DImode,
6379 gen_rtx_PLUS (DImode,
6381 GEN_INT (cum->sse_regno
6382 * (TARGET_AVX ? 5 : 4)))));
6384 emit_move_insn (nsse_reg, label_ref);
6385 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6387 /* Compute address of memory block we save into. We always use pointer
6388 pointing 127 bytes after first byte to store - this is needed to keep
6389 instruction size limited by 4 bytes (5 bytes for AVX) with one
6390 byte displacement. */
6391 tmp_reg = gen_reg_rtx (Pmode);
6392 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6393 plus_constant (save_area,
6394 ix86_varargs_gpr_size + 127)));
6395 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6396 MEM_NOTRAP_P (mem) = 1;
6397 set_mem_alias_set (mem, set);
6398 set_mem_align (mem, BITS_PER_WORD);
6400 /* And finally do the dirty job! */
6401 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6402 GEN_INT (cum->sse_regno), label));
6407 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6409 alias_set_type set = get_varargs_alias_set ();
6412 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6416 mem = gen_rtx_MEM (Pmode,
6417 plus_constant (virtual_incoming_args_rtx,
6418 i * UNITS_PER_WORD));
6419 MEM_NOTRAP_P (mem) = 1;
6420 set_mem_alias_set (mem, set);
6422 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6423 emit_move_insn (mem, reg);
6428 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6429 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6432 CUMULATIVE_ARGS next_cum;
6435 /* This argument doesn't appear to be used anymore. Which is good,
6436 because the old code here didn't suppress rtl generation. */
6437 gcc_assert (!no_rtl);
6442 fntype = TREE_TYPE (current_function_decl);
6444 /* For varargs, we do not want to skip the dummy va_dcl argument.
6445 For stdargs, we do want to skip the last named argument. */
6447 if (stdarg_p (fntype))
6448 function_arg_advance (&next_cum, mode, type, 1);
6450 if (cum->call_abi == MS_ABI)
6451 setup_incoming_varargs_ms_64 (&next_cum);
6453 setup_incoming_varargs_64 (&next_cum);
6456 /* Checks if TYPE is of kind va_list char *. */
6459 is_va_list_char_pointer (tree type)
6463 /* For 32-bit it is always true. */
6466 canonic = ix86_canonical_va_list_type (type);
6467 return (canonic == ms_va_list_type_node
6468 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6471 /* Implement va_start. */
6474 ix86_va_start (tree valist, rtx nextarg)
6476 HOST_WIDE_INT words, n_gpr, n_fpr;
6477 tree f_gpr, f_fpr, f_ovf, f_sav;
6478 tree gpr, fpr, ovf, sav, t;
6481 /* Only 64bit target needs something special. */
6482 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6484 std_expand_builtin_va_start (valist, nextarg);
6488 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6489 f_fpr = TREE_CHAIN (f_gpr);
6490 f_ovf = TREE_CHAIN (f_fpr);
6491 f_sav = TREE_CHAIN (f_ovf);
6493 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6494 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6495 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6496 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6497 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6499 /* Count number of gp and fp argument registers used. */
6500 words = crtl->args.info.words;
6501 n_gpr = crtl->args.info.regno;
6502 n_fpr = crtl->args.info.sse_regno;
6504 if (cfun->va_list_gpr_size)
6506 type = TREE_TYPE (gpr);
6507 t = build2 (MODIFY_EXPR, type,
6508 gpr, build_int_cst (type, n_gpr * 8));
6509 TREE_SIDE_EFFECTS (t) = 1;
6510 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6513 if (TARGET_SSE && cfun->va_list_fpr_size)
6515 type = TREE_TYPE (fpr);
6516 t = build2 (MODIFY_EXPR, type, fpr,
6517 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6518 TREE_SIDE_EFFECTS (t) = 1;
6519 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6522 /* Find the overflow area. */
6523 type = TREE_TYPE (ovf);
6524 t = make_tree (type, crtl->args.internal_arg_pointer);
6526 t = build2 (POINTER_PLUS_EXPR, type, t,
6527 size_int (words * UNITS_PER_WORD));
6528 t = build2 (MODIFY_EXPR, type, ovf, t);
6529 TREE_SIDE_EFFECTS (t) = 1;
6530 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6532 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6534 /* Find the register save area.
6535 Prologue of the function save it right above stack frame. */
6536 type = TREE_TYPE (sav);
6537 t = make_tree (type, frame_pointer_rtx);
6538 if (!ix86_varargs_gpr_size)
6539 t = build2 (POINTER_PLUS_EXPR, type, t,
6540 size_int (-8 * X86_64_REGPARM_MAX));
6541 t = build2 (MODIFY_EXPR, type, sav, t);
6542 TREE_SIDE_EFFECTS (t) = 1;
6543 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6547 /* Implement va_arg. */
6550 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6553 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6554 tree f_gpr, f_fpr, f_ovf, f_sav;
6555 tree gpr, fpr, ovf, sav, t;
6557 tree lab_false, lab_over = NULL_TREE;
6562 enum machine_mode nat_mode;
6565 /* Only 64bit target needs something special. */
6566 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6567 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6569 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6570 f_fpr = TREE_CHAIN (f_gpr);
6571 f_ovf = TREE_CHAIN (f_fpr);
6572 f_sav = TREE_CHAIN (f_ovf);
6574 valist = build_va_arg_indirect_ref (valist);
6575 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6576 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6577 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6578 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6580 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6582 type = build_pointer_type (type);
6583 size = int_size_in_bytes (type);
6584 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6586 nat_mode = type_natural_mode (type);
6595 /* Unnamed 256bit vector mode parameters are passed on stack. */
6596 if (ix86_cfun_abi () == SYSV_ABI)
6603 container = construct_container (nat_mode, TYPE_MODE (type),
6604 type, 0, X86_64_REGPARM_MAX,
6605 X86_64_SSE_REGPARM_MAX, intreg,
6610 /* Pull the value out of the saved registers. */
6612 addr = create_tmp_var (ptr_type_node, "addr");
6613 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6617 int needed_intregs, needed_sseregs;
6619 tree int_addr, sse_addr;
6621 lab_false = create_artificial_label ();
6622 lab_over = create_artificial_label ();
6624 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6626 need_temp = (!REG_P (container)
6627 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6628 || TYPE_ALIGN (type) > 128));
6630 /* In case we are passing structure, verify that it is consecutive block
6631 on the register save area. If not we need to do moves. */
6632 if (!need_temp && !REG_P (container))
6634 /* Verify that all registers are strictly consecutive */
6635 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6639 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6641 rtx slot = XVECEXP (container, 0, i);
6642 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6643 || INTVAL (XEXP (slot, 1)) != i * 16)
6651 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6653 rtx slot = XVECEXP (container, 0, i);
6654 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6655 || INTVAL (XEXP (slot, 1)) != i * 8)
6667 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6668 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6669 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6670 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6673 /* First ensure that we fit completely in registers. */
6676 t = build_int_cst (TREE_TYPE (gpr),
6677 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6678 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6679 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6680 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6681 gimplify_and_add (t, pre_p);
6685 t = build_int_cst (TREE_TYPE (fpr),
6686 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6687 + X86_64_REGPARM_MAX * 8);
6688 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6689 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6690 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6691 gimplify_and_add (t, pre_p);
6694 /* Compute index to start of area used for integer regs. */
6697 /* int_addr = gpr + sav; */
6698 t = fold_convert (sizetype, gpr);
6699 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6700 gimplify_assign (int_addr, t, pre_p);
6704 /* sse_addr = fpr + sav; */
6705 t = fold_convert (sizetype, fpr);
6706 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6707 gimplify_assign (sse_addr, t, pre_p);
6712 tree temp = create_tmp_var (type, "va_arg_tmp");
6715 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6716 gimplify_assign (addr, t, pre_p);
6718 for (i = 0; i < XVECLEN (container, 0); i++)
6720 rtx slot = XVECEXP (container, 0, i);
6721 rtx reg = XEXP (slot, 0);
6722 enum machine_mode mode = GET_MODE (reg);
6723 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6724 tree addr_type = build_pointer_type (piece_type);
6727 tree dest_addr, dest;
6729 if (SSE_REGNO_P (REGNO (reg)))
6731 src_addr = sse_addr;
6732 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6736 src_addr = int_addr;
6737 src_offset = REGNO (reg) * 8;
6739 src_addr = fold_convert (addr_type, src_addr);
6740 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6741 size_int (src_offset));
6742 src = build_va_arg_indirect_ref (src_addr);
6744 dest_addr = fold_convert (addr_type, addr);
6745 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
6746 size_int (INTVAL (XEXP (slot, 1))));
6747 dest = build_va_arg_indirect_ref (dest_addr);
6749 gimplify_assign (dest, src, pre_p);
6755 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6756 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
6757 gimplify_assign (gpr, t, pre_p);
6762 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
6763 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
6764 gimplify_assign (fpr, t, pre_p);
6767 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6769 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
6772 /* ... otherwise out of the overflow area. */
6774 /* When we align parameter on stack for caller, if the parameter
6775 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6776 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6777 here with caller. */
6778 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
6779 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6780 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6782 /* Care for on-stack alignment if needed. */
6783 if (arg_boundary <= 64
6784 || integer_zerop (TYPE_SIZE (type)))
6788 HOST_WIDE_INT align = arg_boundary / 8;
6789 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
6790 size_int (align - 1));
6791 t = fold_convert (sizetype, t);
6792 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6794 t = fold_convert (TREE_TYPE (ovf), t);
6796 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6797 gimplify_assign (addr, t, pre_p);
6799 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
6800 size_int (rsize * UNITS_PER_WORD));
6801 gimplify_assign (unshare_expr (ovf), t, pre_p);
6804 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
6806 ptrtype = build_pointer_type (type);
6807 addr = fold_convert (ptrtype, addr);
6810 addr = build_va_arg_indirect_ref (addr);
6811 return build_va_arg_indirect_ref (addr);
6814 /* Return nonzero if OPNUM's MEM should be matched
6815 in movabs* patterns. */
6818 ix86_check_movabs (rtx insn, int opnum)
6822 set = PATTERN (insn);
6823 if (GET_CODE (set) == PARALLEL)
6824 set = XVECEXP (set, 0, 0);
6825 gcc_assert (GET_CODE (set) == SET);
6826 mem = XEXP (set, opnum);
6827 while (GET_CODE (mem) == SUBREG)
6828 mem = SUBREG_REG (mem);
6829 gcc_assert (MEM_P (mem));
6830 return (volatile_ok || !MEM_VOLATILE_P (mem));
6833 /* Initialize the table of extra 80387 mathematical constants. */
6836 init_ext_80387_constants (void)
6838 static const char * cst[5] =
6840 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
6841 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
6842 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
6843 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
6844 "3.1415926535897932385128089594061862044", /* 4: fldpi */
6848 for (i = 0; i < 5; i++)
6850 real_from_string (&ext_80387_constants_table[i], cst[i]);
6851 /* Ensure each constant is rounded to XFmode precision. */
6852 real_convert (&ext_80387_constants_table[i],
6853 XFmode, &ext_80387_constants_table[i]);
6856 ext_80387_constants_init = 1;
6859 /* Return true if the constant is something that can be loaded with
6860 a special instruction. */
6863 standard_80387_constant_p (rtx x)
6865 enum machine_mode mode = GET_MODE (x);
6869 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
6872 if (x == CONST0_RTX (mode))
6874 if (x == CONST1_RTX (mode))
6877 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6879 /* For XFmode constants, try to find a special 80387 instruction when
6880 optimizing for size or on those CPUs that benefit from them. */
6882 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
6886 if (! ext_80387_constants_init)
6887 init_ext_80387_constants ();
6889 for (i = 0; i < 5; i++)
6890 if (real_identical (&r, &ext_80387_constants_table[i]))
6894 /* Load of the constant -0.0 or -1.0 will be split as
6895 fldz;fchs or fld1;fchs sequence. */
6896 if (real_isnegzero (&r))
6898 if (real_identical (&r, &dconstm1))
6904 /* Return the opcode of the special instruction to be used to load
6908 standard_80387_constant_opcode (rtx x)
6910 switch (standard_80387_constant_p (x))
6934 /* Return the CONST_DOUBLE representing the 80387 constant that is
6935 loaded by the specified special instruction. The argument IDX
6936 matches the return value from standard_80387_constant_p. */
6939 standard_80387_constant_rtx (int idx)
6943 if (! ext_80387_constants_init)
6944 init_ext_80387_constants ();
6960 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
6964 /* Return 1 if mode is a valid mode for sse. */
6966 standard_sse_mode_p (enum machine_mode mode)
6983 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
6984 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
6985 modes and AVX is enabled. */
6988 standard_sse_constant_p (rtx x)
6990 enum machine_mode mode = GET_MODE (x);
6992 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
6994 if (vector_all_ones_operand (x, mode))
6996 if (standard_sse_mode_p (mode))
6997 return TARGET_SSE2 ? 2 : -2;
6998 else if (VALID_AVX256_REG_MODE (mode))
6999 return TARGET_AVX ? 3 : -3;
7005 /* Return the opcode of the special instruction to be used to load
7009 standard_sse_constant_opcode (rtx insn, rtx x)
7011 switch (standard_sse_constant_p (x))
7014 switch (get_attr_mode (insn))
7017 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7019 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7021 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7023 return "vxorps\t%x0, %x0, %x0";
7025 return "vxorpd\t%x0, %x0, %x0";
7027 return "vpxor\t%x0, %x0, %x0";
7033 switch (get_attr_mode (insn))
7038 return "vpcmpeqd\t%0, %0, %0";
7044 return "pcmpeqd\t%0, %0";
7049 /* Returns 1 if OP contains a symbol reference */
7052 symbolic_reference_mentioned_p (rtx op)
7057 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7060 fmt = GET_RTX_FORMAT (GET_CODE (op));
7061 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7067 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7068 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7072 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7079 /* Return 1 if it is appropriate to emit `ret' instructions in the
7080 body of a function. Do this only if the epilogue is simple, needing a
7081 couple of insns. Prior to reloading, we can't tell how many registers
7082 must be saved, so return 0 then. Return 0 if there is no frame
7083 marker to de-allocate. */
7086 ix86_can_use_return_insn_p (void)
7088 struct ix86_frame frame;
7090 if (! reload_completed || frame_pointer_needed)
7093 /* Don't allow more than 32 pop, since that's all we can do
7094 with one instruction. */
7095 if (crtl->args.pops_args
7096 && crtl->args.size >= 32768)
7099 ix86_compute_frame_layout (&frame);
7100 return frame.to_allocate == 0 && frame.nregs == 0;
7103 /* Value should be nonzero if functions must have frame pointers.
7104 Zero means the frame pointer need not be set up (and parms may
7105 be accessed via the stack pointer) in functions that seem suitable. */
7108 ix86_frame_pointer_required (void)
7110 /* If we accessed previous frames, then the generated code expects
7111 to be able to access the saved ebp value in our frame. */
7112 if (cfun->machine->accesses_prev_frame)
7115 /* Several x86 os'es need a frame pointer for other reasons,
7116 usually pertaining to setjmp. */
7117 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7120 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7121 the frame pointer by default. Turn it back on now if we've not
7122 got a leaf function. */
7123 if (TARGET_OMIT_LEAF_FRAME_POINTER
7124 && (!current_function_is_leaf
7125 || ix86_current_function_calls_tls_descriptor))
7134 /* Record that the current function accesses previous call frames. */
7137 ix86_setup_frame_addresses (void)
7139 cfun->machine->accesses_prev_frame = 1;
7142 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7143 # define USE_HIDDEN_LINKONCE 1
7145 # define USE_HIDDEN_LINKONCE 0
7148 static int pic_labels_used;
7150 /* Fills in the label name that should be used for a pc thunk for
7151 the given register. */
7154 get_pc_thunk_name (char name[32], unsigned int regno)
7156 gcc_assert (!TARGET_64BIT);
7158 if (USE_HIDDEN_LINKONCE)
7159 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7161 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7165 /* This function generates code for -fpic that loads %ebx with
7166 the return address of the caller and then returns. */
7169 ix86_file_end (void)
7174 for (regno = 0; regno < 8; ++regno)
7178 if (! ((pic_labels_used >> regno) & 1))
7181 get_pc_thunk_name (name, regno);
7186 switch_to_section (darwin_sections[text_coal_section]);
7187 fputs ("\t.weak_definition\t", asm_out_file);
7188 assemble_name (asm_out_file, name);
7189 fputs ("\n\t.private_extern\t", asm_out_file);
7190 assemble_name (asm_out_file, name);
7191 fputs ("\n", asm_out_file);
7192 ASM_OUTPUT_LABEL (asm_out_file, name);
7196 if (USE_HIDDEN_LINKONCE)
7200 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7202 TREE_PUBLIC (decl) = 1;
7203 TREE_STATIC (decl) = 1;
7204 DECL_ONE_ONLY (decl) = 1;
7206 (*targetm.asm_out.unique_section) (decl, 0);
7207 switch_to_section (get_named_section (decl, NULL, 0));
7209 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7210 fputs ("\t.hidden\t", asm_out_file);
7211 assemble_name (asm_out_file, name);
7212 fputc ('\n', asm_out_file);
7213 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7217 switch_to_section (text_section);
7218 ASM_OUTPUT_LABEL (asm_out_file, name);
7221 xops[0] = gen_rtx_REG (Pmode, regno);
7222 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7223 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7224 output_asm_insn ("ret", xops);
7227 if (NEED_INDICATE_EXEC_STACK)
7228 file_end_indicate_exec_stack ();
7231 /* Emit code for the SET_GOT patterns. */
7234 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7240 if (TARGET_VXWORKS_RTP && flag_pic)
7242 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7243 xops[2] = gen_rtx_MEM (Pmode,
7244 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7245 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7247 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7248 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7249 an unadorned address. */
7250 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7251 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7252 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7256 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7258 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7260 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7263 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7265 output_asm_insn ("call\t%a2", xops);
7268 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7269 is what will be referenced by the Mach-O PIC subsystem. */
7271 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7274 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7275 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7278 output_asm_insn ("pop%z0\t%0", xops);
7283 get_pc_thunk_name (name, REGNO (dest));
7284 pic_labels_used |= 1 << REGNO (dest);
7286 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7287 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7288 output_asm_insn ("call\t%X2", xops);
7289 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7290 is what will be referenced by the Mach-O PIC subsystem. */
7293 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7295 targetm.asm_out.internal_label (asm_out_file, "L",
7296 CODE_LABEL_NUMBER (label));
7303 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7304 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7306 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7311 /* Generate an "push" pattern for input ARG. */
7316 return gen_rtx_SET (VOIDmode,
7318 gen_rtx_PRE_DEC (Pmode,
7319 stack_pointer_rtx)),
7323 /* Return >= 0 if there is an unused call-clobbered register available
7324 for the entire function. */
7327 ix86_select_alt_pic_regnum (void)
7329 if (current_function_is_leaf && !crtl->profile
7330 && !ix86_current_function_calls_tls_descriptor)
7333 /* Can't use the same register for both PIC and DRAP. */
7335 drap = REGNO (crtl->drap_reg);
7338 for (i = 2; i >= 0; --i)
7339 if (i != drap && !df_regs_ever_live_p (i))
7343 return INVALID_REGNUM;
7346 /* Return 1 if we need to save REGNO. */
7348 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7350 if (pic_offset_table_rtx
7351 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7352 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7354 || crtl->calls_eh_return
7355 || crtl->uses_const_pool))
7357 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7362 if (crtl->calls_eh_return && maybe_eh_return)
7367 unsigned test = EH_RETURN_DATA_REGNO (i);
7368 if (test == INVALID_REGNUM)
7376 && regno == REGNO (crtl->drap_reg))
7379 return (df_regs_ever_live_p (regno)
7380 && !call_used_regs[regno]
7381 && !fixed_regs[regno]
7382 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7385 /* Return number of registers to be saved on the stack. */
7388 ix86_nsaved_regs (void)
7393 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
7394 if (ix86_save_reg (regno, true))
7399 /* Given FROM and TO register numbers, say whether this elimination is
7400 allowed. If stack alignment is needed, we can only replace argument
7401 pointer with hard frame pointer, or replace frame pointer with stack
7402 pointer. Otherwise, frame pointer elimination is automatically
7403 handled and all other eliminations are valid. */
7406 ix86_can_eliminate (int from, int to)
7408 if (stack_realign_fp)
7409 return ((from == ARG_POINTER_REGNUM
7410 && to == HARD_FRAME_POINTER_REGNUM)
7411 || (from == FRAME_POINTER_REGNUM
7412 && to == STACK_POINTER_REGNUM));
7414 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7417 /* Return the offset between two registers, one to be eliminated, and the other
7418 its replacement, at the start of a routine. */
7421 ix86_initial_elimination_offset (int from, int to)
7423 struct ix86_frame frame;
7424 ix86_compute_frame_layout (&frame);
7426 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7427 return frame.hard_frame_pointer_offset;
7428 else if (from == FRAME_POINTER_REGNUM
7429 && to == HARD_FRAME_POINTER_REGNUM)
7430 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7433 gcc_assert (to == STACK_POINTER_REGNUM);
7435 if (from == ARG_POINTER_REGNUM)
7436 return frame.stack_pointer_offset;
7438 gcc_assert (from == FRAME_POINTER_REGNUM);
7439 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7443 /* Fill structure ix86_frame about frame of currently computed function. */
7446 ix86_compute_frame_layout (struct ix86_frame *frame)
7448 HOST_WIDE_INT total_size;
7449 unsigned int stack_alignment_needed;
7450 HOST_WIDE_INT offset;
7451 unsigned int preferred_alignment;
7452 HOST_WIDE_INT size = get_frame_size ();
7454 frame->nregs = ix86_nsaved_regs ();
7457 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7458 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7460 gcc_assert (!size || stack_alignment_needed);
7461 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7462 gcc_assert (preferred_alignment <= stack_alignment_needed);
7464 /* During reload iteration the amount of registers saved can change.
7465 Recompute the value as needed. Do not recompute when amount of registers
7466 didn't change as reload does multiple calls to the function and does not
7467 expect the decision to change within single iteration. */
7468 if (!optimize_function_for_size_p (cfun)
7469 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7471 int count = frame->nregs;
7473 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7474 /* The fast prologue uses move instead of push to save registers. This
7475 is significantly longer, but also executes faster as modern hardware
7476 can execute the moves in parallel, but can't do that for push/pop.
7478 Be careful about choosing what prologue to emit: When function takes
7479 many instructions to execute we may use slow version as well as in
7480 case function is known to be outside hot spot (this is known with
7481 feedback only). Weight the size of function by number of registers
7482 to save as it is cheap to use one or two push instructions but very
7483 slow to use many of them. */
7485 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7486 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7487 || (flag_branch_probabilities
7488 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7489 cfun->machine->use_fast_prologue_epilogue = false;
7491 cfun->machine->use_fast_prologue_epilogue
7492 = !expensive_function_p (count);
7494 if (TARGET_PROLOGUE_USING_MOVE
7495 && cfun->machine->use_fast_prologue_epilogue)
7496 frame->save_regs_using_mov = true;
7498 frame->save_regs_using_mov = false;
7501 /* Skip return address and saved base pointer. */
7502 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7504 frame->hard_frame_pointer_offset = offset;
7506 /* Set offset to aligned because the realigned frame starts from
7508 if (stack_realign_fp)
7509 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7511 /* Register save area */
7512 offset += frame->nregs * UNITS_PER_WORD;
7515 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7516 offset += frame->va_arg_size;
7518 /* Align start of frame for local function. */
7519 frame->padding1 = ((offset + stack_alignment_needed - 1)
7520 & -stack_alignment_needed) - offset;
7522 offset += frame->padding1;
7524 /* Frame pointer points here. */
7525 frame->frame_pointer_offset = offset;
7529 /* Add outgoing arguments area. Can be skipped if we eliminated
7530 all the function calls as dead code.
7531 Skipping is however impossible when function calls alloca. Alloca
7532 expander assumes that last crtl->outgoing_args_size
7533 of stack frame are unused. */
7534 if (ACCUMULATE_OUTGOING_ARGS
7535 && (!current_function_is_leaf || cfun->calls_alloca
7536 || ix86_current_function_calls_tls_descriptor))
7538 offset += crtl->outgoing_args_size;
7539 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7542 frame->outgoing_arguments_size = 0;
7544 /* Align stack boundary. Only needed if we're calling another function
7546 if (!current_function_is_leaf || cfun->calls_alloca
7547 || ix86_current_function_calls_tls_descriptor)
7548 frame->padding2 = ((offset + preferred_alignment - 1)
7549 & -preferred_alignment) - offset;
7551 frame->padding2 = 0;
7553 offset += frame->padding2;
7555 /* We've reached end of stack frame. */
7556 frame->stack_pointer_offset = offset;
7558 /* Size prologue needs to allocate. */
7559 frame->to_allocate =
7560 (size + frame->padding1 + frame->padding2
7561 + frame->outgoing_arguments_size + frame->va_arg_size);
7563 if ((!frame->to_allocate && frame->nregs <= 1)
7564 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7565 frame->save_regs_using_mov = false;
7567 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7568 && current_function_is_leaf
7569 && !ix86_current_function_calls_tls_descriptor)
7571 frame->red_zone_size = frame->to_allocate;
7572 if (frame->save_regs_using_mov)
7573 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7574 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7575 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7578 frame->red_zone_size = 0;
7579 frame->to_allocate -= frame->red_zone_size;
7580 frame->stack_pointer_offset -= frame->red_zone_size;
7582 fprintf (stderr, "\n");
7583 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7584 fprintf (stderr, "size: %ld\n", (long)size);
7585 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7586 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7587 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7588 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7589 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7590 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7591 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7592 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7593 (long)frame->hard_frame_pointer_offset);
7594 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7595 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7596 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7597 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7601 /* Emit code to save registers in the prologue. */
7604 ix86_emit_save_regs (void)
7609 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
7610 if (ix86_save_reg (regno, true))
7612 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7613 RTX_FRAME_RELATED_P (insn) = 1;
7617 /* Emit code to save registers using MOV insns. First register
7618 is restored from POINTER + OFFSET. */
7620 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7625 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7626 if (ix86_save_reg (regno, true))
7628 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7630 gen_rtx_REG (Pmode, regno));
7631 RTX_FRAME_RELATED_P (insn) = 1;
7632 offset += UNITS_PER_WORD;
7636 /* Expand prologue or epilogue stack adjustment.
7637 The pattern exist to put a dependency on all ebp-based memory accesses.
7638 STYLE should be negative if instructions should be marked as frame related,
7639 zero if %r11 register is live and cannot be freely used and positive
7643 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7648 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7649 else if (x86_64_immediate_operand (offset, DImode))
7650 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7654 /* r11 is used by indirect sibcall return as well, set before the
7655 epilogue and used after the epilogue. ATM indirect sibcall
7656 shouldn't be used together with huge frame sizes in one
7657 function because of the frame_size check in sibcall.c. */
7659 r11 = gen_rtx_REG (DImode, R11_REG);
7660 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7662 RTX_FRAME_RELATED_P (insn) = 1;
7663 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7667 RTX_FRAME_RELATED_P (insn) = 1;
7670 /* Find an available register to be used as dynamic realign argument
7671 pointer regsiter. Such a register will be written in prologue and
7672 used in begin of body, so it must not be
7673 1. parameter passing register.
7675 We reuse static-chain register if it is available. Otherwise, we
7676 use DI for i386 and R13 for x86-64. We chose R13 since it has
7679 Return: the regno of chosen register. */
7682 find_drap_reg (void)
7684 tree decl = cfun->decl;
7688 /* Use R13 for nested function or function need static chain.
7689 Since function with tail call may use any caller-saved
7690 registers in epilogue, DRAP must not use caller-saved
7691 register in such case. */
7692 if ((decl_function_context (decl)
7693 && !DECL_NO_STATIC_CHAIN (decl))
7694 || crtl->tail_call_emit)
7701 /* Use DI for nested function or function need static chain.
7702 Since function with tail call may use any caller-saved
7703 registers in epilogue, DRAP must not use caller-saved
7704 register in such case. */
7705 if ((decl_function_context (decl)
7706 && !DECL_NO_STATIC_CHAIN (decl))
7707 || crtl->tail_call_emit)
7710 /* Reuse static chain register if it isn't used for parameter
7712 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
7713 && !lookup_attribute ("fastcall",
7714 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
7721 /* Update incoming stack boundary and estimated stack alignment. */
7724 ix86_update_stack_boundary (void)
7726 /* Prefer the one specified at command line. */
7727 ix86_incoming_stack_boundary
7728 = (ix86_user_incoming_stack_boundary
7729 ? ix86_user_incoming_stack_boundary
7730 : ix86_default_incoming_stack_boundary);
7732 /* Incoming stack alignment can be changed on individual functions
7733 via force_align_arg_pointer attribute. We use the smallest
7734 incoming stack boundary. */
7735 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
7736 && lookup_attribute (ix86_force_align_arg_pointer_string,
7737 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
7738 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
7740 /* Stack at entrance of main is aligned by runtime. We use the
7741 smallest incoming stack boundary. */
7742 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
7743 && DECL_NAME (current_function_decl)
7744 && MAIN_NAME_P (DECL_NAME (current_function_decl))
7745 && DECL_FILE_SCOPE_P (current_function_decl))
7746 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
7748 /* x86_64 vararg needs 16byte stack alignment for register save
7752 && crtl->stack_alignment_estimated < 128)
7753 crtl->stack_alignment_estimated = 128;
7756 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7757 needed or an rtx for DRAP otherwise. */
7760 ix86_get_drap_rtx (void)
7762 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
7763 crtl->need_drap = true;
7765 if (stack_realign_drap)
7767 /* Assign DRAP to vDRAP and returns vDRAP */
7768 unsigned int regno = find_drap_reg ();
7773 arg_ptr = gen_rtx_REG (Pmode, regno);
7774 crtl->drap_reg = arg_ptr;
7777 drap_vreg = copy_to_reg (arg_ptr);
7781 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
7782 RTX_FRAME_RELATED_P (insn) = 1;
7789 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7792 ix86_internal_arg_pointer (void)
7794 return virtual_incoming_args_rtx;
7797 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7798 This is called from dwarf2out.c to emit call frame instructions
7799 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
7801 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
7803 rtx unspec = SET_SRC (pattern);
7804 gcc_assert (GET_CODE (unspec) == UNSPEC);
7808 case UNSPEC_REG_SAVE:
7809 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
7810 SET_DEST (pattern));
7812 case UNSPEC_DEF_CFA:
7813 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
7814 INTVAL (XVECEXP (unspec, 0, 0)));
7821 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
7822 to be generated in correct form. */
7824 ix86_finalize_stack_realign_flags (void)
7826 /* Check if stack realign is really needed after reload, and
7827 stores result in cfun */
7828 unsigned int incoming_stack_boundary
7829 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
7830 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
7831 unsigned int stack_realign = (incoming_stack_boundary
7832 < (current_function_is_leaf
7833 ? crtl->max_used_stack_slot_alignment
7834 : crtl->stack_alignment_needed));
7836 if (crtl->stack_realign_finalized)
7838 /* After stack_realign_needed is finalized, we can't no longer
7840 gcc_assert (crtl->stack_realign_needed == stack_realign);
7844 crtl->stack_realign_needed = stack_realign;
7845 crtl->stack_realign_finalized = true;
7849 /* Expand the prologue into a bunch of separate insns. */
7852 ix86_expand_prologue (void)
7856 struct ix86_frame frame;
7857 HOST_WIDE_INT allocate;
7859 ix86_finalize_stack_realign_flags ();
7861 /* DRAP should not coexist with stack_realign_fp */
7862 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
7864 ix86_compute_frame_layout (&frame);
7866 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
7867 of DRAP is needed and stack realignment is really needed after reload */
7868 if (crtl->drap_reg && crtl->stack_realign_needed)
7871 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
7872 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
7873 ? 0 : UNITS_PER_WORD);
7875 gcc_assert (stack_realign_drap);
7877 /* Grab the argument pointer. */
7878 x = plus_constant (stack_pointer_rtx,
7879 (UNITS_PER_WORD + param_ptr_offset));
7882 /* Only need to push parameter pointer reg if it is caller
7884 if (!call_used_regs[REGNO (crtl->drap_reg)])
7886 /* Push arg pointer reg */
7887 insn = emit_insn (gen_push (y));
7888 RTX_FRAME_RELATED_P (insn) = 1;
7891 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
7892 RTX_FRAME_RELATED_P (insn) = 1;
7894 /* Align the stack. */
7895 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
7897 GEN_INT (-align_bytes)));
7898 RTX_FRAME_RELATED_P (insn) = 1;
7900 /* Replicate the return address on the stack so that return
7901 address can be reached via (argp - 1) slot. This is needed
7902 to implement macro RETURN_ADDR_RTX and intrinsic function
7903 expand_builtin_return_addr etc. */
7905 x = gen_frame_mem (Pmode,
7906 plus_constant (x, -UNITS_PER_WORD));
7907 insn = emit_insn (gen_push (x));
7908 RTX_FRAME_RELATED_P (insn) = 1;
7911 /* Note: AT&T enter does NOT have reversed args. Enter is probably
7912 slower on all targets. Also sdb doesn't like it. */
7914 if (frame_pointer_needed)
7916 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
7917 RTX_FRAME_RELATED_P (insn) = 1;
7919 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7920 RTX_FRAME_RELATED_P (insn) = 1;
7923 if (stack_realign_fp)
7925 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
7926 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
7928 /* Align the stack. */
7929 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
7931 GEN_INT (-align_bytes)));
7932 RTX_FRAME_RELATED_P (insn) = 1;
7935 allocate = frame.to_allocate;
7937 if (!frame.save_regs_using_mov)
7938 ix86_emit_save_regs ();
7940 allocate += frame.nregs * UNITS_PER_WORD;
7942 /* When using red zone we may start register saving before allocating
7943 the stack frame saving one cycle of the prologue. However I will
7944 avoid doing this if I am going to have to probe the stack since
7945 at least on x86_64 the stack probe can turn into a call that clobbers
7946 a red zone location */
7947 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
7948 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
7949 ix86_emit_save_regs_using_mov ((frame_pointer_needed
7950 && !crtl->stack_realign_needed)
7951 ? hard_frame_pointer_rtx
7952 : stack_pointer_rtx,
7953 -frame.nregs * UNITS_PER_WORD);
7957 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
7958 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
7959 GEN_INT (-allocate), -1);
7962 /* Only valid for Win32. */
7963 rtx eax = gen_rtx_REG (Pmode, AX_REG);
7967 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
7969 if (cfun->machine->call_abi == MS_ABI)
7972 eax_live = ix86_eax_live_at_start_p ();
7976 emit_insn (gen_push (eax));
7977 allocate -= UNITS_PER_WORD;
7980 emit_move_insn (eax, GEN_INT (allocate));
7983 insn = gen_allocate_stack_worker_64 (eax);
7985 insn = gen_allocate_stack_worker_32 (eax);
7986 insn = emit_insn (insn);
7987 RTX_FRAME_RELATED_P (insn) = 1;
7988 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
7989 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
7990 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7991 t, REG_NOTES (insn));
7995 if (frame_pointer_needed)
7996 t = plus_constant (hard_frame_pointer_rtx,
7999 - frame.nregs * UNITS_PER_WORD);
8001 t = plus_constant (stack_pointer_rtx, allocate);
8002 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8006 if (frame.save_regs_using_mov
8007 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8008 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8010 if (!frame_pointer_needed
8011 || !frame.to_allocate
8012 || crtl->stack_realign_needed)
8013 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8016 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8017 -frame.nregs * UNITS_PER_WORD);
8020 pic_reg_used = false;
8021 if (pic_offset_table_rtx
8022 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8025 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8027 if (alt_pic_reg_used != INVALID_REGNUM)
8028 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8030 pic_reg_used = true;
8037 if (ix86_cmodel == CM_LARGE_PIC)
8039 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8040 rtx label = gen_label_rtx ();
8042 LABEL_PRESERVE_P (label) = 1;
8043 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8044 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8045 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8046 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8047 pic_offset_table_rtx, tmp_reg));
8050 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8053 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8056 /* Prevent function calls from being scheduled before the call to mcount.
8057 In the pic_reg_used case, make sure that the got load isn't deleted. */
8061 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8062 emit_insn (gen_blockage ());
8065 if (crtl->drap_reg && !crtl->stack_realign_needed)
8067 /* vDRAP is setup but after reload it turns out stack realign
8068 isn't necessary, here we will emit prologue to setup DRAP
8069 without stack realign adjustment */
8070 int drap_bp_offset = UNITS_PER_WORD * 2;
8071 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8072 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8075 /* Emit cld instruction if stringops are used in the function. */
8076 if (TARGET_CLD && ix86_current_function_needs_cld)
8077 emit_insn (gen_cld ());
8080 /* Emit code to restore saved registers using MOV insns. First register
8081 is restored from POINTER + OFFSET. */
8083 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8084 int maybe_eh_return)
8087 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8089 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8090 if (ix86_save_reg (regno, maybe_eh_return))
8092 /* Ensure that adjust_address won't be forced to produce pointer
8093 out of range allowed by x86-64 instruction set. */
8094 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8098 r11 = gen_rtx_REG (DImode, R11_REG);
8099 emit_move_insn (r11, GEN_INT (offset));
8100 emit_insn (gen_adddi3 (r11, r11, pointer));
8101 base_address = gen_rtx_MEM (Pmode, r11);
8104 emit_move_insn (gen_rtx_REG (Pmode, regno),
8105 adjust_address (base_address, Pmode, offset));
8106 offset += UNITS_PER_WORD;
8110 /* Restore function stack, frame, and registers. */
8113 ix86_expand_epilogue (int style)
8117 struct ix86_frame frame;
8118 HOST_WIDE_INT offset;
8120 ix86_finalize_stack_realign_flags ();
8122 /* When stack is realigned, SP must be valid. */
8123 sp_valid = (!frame_pointer_needed
8124 || current_function_sp_is_unchanging
8125 || stack_realign_fp);
8127 ix86_compute_frame_layout (&frame);
8129 /* Calculate start of saved registers relative to ebp. Special care
8130 must be taken for the normal return case of a function using
8131 eh_return: the eax and edx registers are marked as saved, but not
8132 restored along this path. */
8133 offset = frame.nregs;
8134 if (crtl->calls_eh_return && style != 2)
8136 offset *= -UNITS_PER_WORD;
8138 /* If we're only restoring one register and sp is not valid then
8139 using a move instruction to restore the register since it's
8140 less work than reloading sp and popping the register.
8142 The default code result in stack adjustment using add/lea instruction,
8143 while this code results in LEAVE instruction (or discrete equivalent),
8144 so it is profitable in some other cases as well. Especially when there
8145 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8146 and there is exactly one register to pop. This heuristic may need some
8147 tuning in future. */
8148 if ((!sp_valid && frame.nregs <= 1)
8149 || (TARGET_EPILOGUE_USING_MOVE
8150 && cfun->machine->use_fast_prologue_epilogue
8151 && (frame.nregs > 1 || frame.to_allocate))
8152 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
8153 || (frame_pointer_needed && TARGET_USE_LEAVE
8154 && cfun->machine->use_fast_prologue_epilogue
8155 && frame.nregs == 1)
8156 || crtl->calls_eh_return)
8158 /* Restore registers. We can use ebp or esp to address the memory
8159 locations. If both are available, default to ebp, since offsets
8160 are known to be small. Only exception is esp pointing directly
8161 to the end of block of saved registers, where we may simplify
8164 If we are realigning stack with bp and sp, regs restore can't
8165 be addressed by bp. sp must be used instead. */
8167 if (!frame_pointer_needed
8168 || (sp_valid && !frame.to_allocate)
8169 || stack_realign_fp)
8170 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8171 frame.to_allocate, style == 2);
8173 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8174 offset, style == 2);
8176 /* eh_return epilogues need %ecx added to the stack pointer. */
8179 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8181 /* Stack align doesn't work with eh_return. */
8182 gcc_assert (!crtl->stack_realign_needed);
8184 if (frame_pointer_needed)
8186 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8187 tmp = plus_constant (tmp, UNITS_PER_WORD);
8188 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8190 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8191 emit_move_insn (hard_frame_pointer_rtx, tmp);
8193 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8198 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8199 tmp = plus_constant (tmp, (frame.to_allocate
8200 + frame.nregs * UNITS_PER_WORD));
8201 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8204 else if (!frame_pointer_needed)
8205 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8206 GEN_INT (frame.to_allocate
8207 + frame.nregs * UNITS_PER_WORD),
8209 /* If not an i386, mov & pop is faster than "leave". */
8210 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8211 || !cfun->machine->use_fast_prologue_epilogue)
8212 emit_insn ((*ix86_gen_leave) ());
8215 pro_epilogue_adjust_stack (stack_pointer_rtx,
8216 hard_frame_pointer_rtx,
8219 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8224 /* First step is to deallocate the stack frame so that we can
8227 If we realign stack with frame pointer, then stack pointer
8228 won't be able to recover via lea $offset(%bp), %sp, because
8229 there is a padding area between bp and sp for realign.
8230 "add $to_allocate, %sp" must be used instead. */
8233 gcc_assert (frame_pointer_needed);
8234 gcc_assert (!stack_realign_fp);
8235 pro_epilogue_adjust_stack (stack_pointer_rtx,
8236 hard_frame_pointer_rtx,
8237 GEN_INT (offset), style);
8239 else if (frame.to_allocate)
8240 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8241 GEN_INT (frame.to_allocate), style);
8243 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8244 if (ix86_save_reg (regno, false))
8245 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8246 if (frame_pointer_needed)
8248 /* Leave results in shorter dependency chains on CPUs that are
8249 able to grok it fast. */
8250 if (TARGET_USE_LEAVE)
8251 emit_insn ((*ix86_gen_leave) ());
8254 /* For stack realigned really happens, recover stack
8255 pointer to hard frame pointer is a must, if not using
8257 if (stack_realign_fp)
8258 pro_epilogue_adjust_stack (stack_pointer_rtx,
8259 hard_frame_pointer_rtx,
8261 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8266 if (crtl->drap_reg && crtl->stack_realign_needed)
8268 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8269 ? 0 : UNITS_PER_WORD);
8270 gcc_assert (stack_realign_drap);
8271 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8273 GEN_INT (-(UNITS_PER_WORD
8274 + param_ptr_offset))));
8275 if (!call_used_regs[REGNO (crtl->drap_reg)])
8276 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8280 /* Sibcall epilogues don't want a return instruction. */
8284 if (crtl->args.pops_args && crtl->args.size)
8286 rtx popc = GEN_INT (crtl->args.pops_args);
8288 /* i386 can only pop 64K bytes. If asked to pop more, pop
8289 return address, do explicit add, and jump indirectly to the
8292 if (crtl->args.pops_args >= 65536)
8294 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8296 /* There is no "pascal" calling convention in any 64bit ABI. */
8297 gcc_assert (!TARGET_64BIT);
8299 emit_insn (gen_popsi1 (ecx));
8300 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8301 emit_jump_insn (gen_return_indirect_internal (ecx));
8304 emit_jump_insn (gen_return_pop_internal (popc));
8307 emit_jump_insn (gen_return_internal ());
8310 /* Reset from the function's potential modifications. */
8313 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8314 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8316 if (pic_offset_table_rtx)
8317 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8319 /* Mach-O doesn't support labels at the end of objects, so if
8320 it looks like we might want one, insert a NOP. */
8322 rtx insn = get_last_insn ();
8325 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8326 insn = PREV_INSN (insn);
8330 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8331 fputs ("\tnop\n", file);
8337 /* Extract the parts of an RTL expression that is a valid memory address
8338 for an instruction. Return 0 if the structure of the address is
8339 grossly off. Return -1 if the address contains ASHIFT, so it is not
8340 strictly valid, but still used for computing length of lea instruction. */
8343 ix86_decompose_address (rtx addr, struct ix86_address *out)
8345 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8346 rtx base_reg, index_reg;
8347 HOST_WIDE_INT scale = 1;
8348 rtx scale_rtx = NULL_RTX;
8350 enum ix86_address_seg seg = SEG_DEFAULT;
8352 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8354 else if (GET_CODE (addr) == PLUS)
8364 addends[n++] = XEXP (op, 1);
8367 while (GET_CODE (op) == PLUS);
8372 for (i = n; i >= 0; --i)
8375 switch (GET_CODE (op))
8380 index = XEXP (op, 0);
8381 scale_rtx = XEXP (op, 1);
8385 if (XINT (op, 1) == UNSPEC_TP
8386 && TARGET_TLS_DIRECT_SEG_REFS
8387 && seg == SEG_DEFAULT)
8388 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8417 else if (GET_CODE (addr) == MULT)
8419 index = XEXP (addr, 0); /* index*scale */
8420 scale_rtx = XEXP (addr, 1);
8422 else if (GET_CODE (addr) == ASHIFT)
8426 /* We're called for lea too, which implements ashift on occasion. */
8427 index = XEXP (addr, 0);
8428 tmp = XEXP (addr, 1);
8429 if (!CONST_INT_P (tmp))
8431 scale = INTVAL (tmp);
8432 if ((unsigned HOST_WIDE_INT) scale > 3)
8438 disp = addr; /* displacement */
8440 /* Extract the integral value of scale. */
8443 if (!CONST_INT_P (scale_rtx))
8445 scale = INTVAL (scale_rtx);
8448 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8449 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8451 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8452 if (base_reg && index_reg && scale == 1
8453 && (index_reg == arg_pointer_rtx
8454 || index_reg == frame_pointer_rtx
8455 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8458 tmp = base, base = index, index = tmp;
8459 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8462 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8463 if ((base_reg == hard_frame_pointer_rtx
8464 || base_reg == frame_pointer_rtx
8465 || base_reg == arg_pointer_rtx) && !disp)
8468 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8469 Avoid this by transforming to [%esi+0].
8470 Reload calls address legitimization without cfun defined, so we need
8471 to test cfun for being non-NULL. */
8472 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8473 && base_reg && !index_reg && !disp
8475 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8478 /* Special case: encode reg+reg instead of reg*2. */
8479 if (!base && index && scale && scale == 2)
8480 base = index, base_reg = index_reg, scale = 1;
8482 /* Special case: scaling cannot be encoded without base or displacement. */
8483 if (!base && !disp && index && scale != 1)
8495 /* Return cost of the memory address x.
8496 For i386, it is better to use a complex address than let gcc copy
8497 the address into a reg and make a new pseudo. But not if the address
8498 requires to two regs - that would mean more pseudos with longer
8501 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8503 struct ix86_address parts;
8505 int ok = ix86_decompose_address (x, &parts);
8509 if (parts.base && GET_CODE (parts.base) == SUBREG)
8510 parts.base = SUBREG_REG (parts.base);
8511 if (parts.index && GET_CODE (parts.index) == SUBREG)
8512 parts.index = SUBREG_REG (parts.index);
8514 /* Attempt to minimize number of registers in the address. */
8516 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8518 && (!REG_P (parts.index)
8519 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8523 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8525 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8526 && parts.base != parts.index)
8529 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8530 since it's predecode logic can't detect the length of instructions
8531 and it degenerates to vector decoded. Increase cost of such
8532 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8533 to split such addresses or even refuse such addresses at all.
8535 Following addressing modes are affected:
8540 The first and last case may be avoidable by explicitly coding the zero in
8541 memory address, but I don't have AMD-K6 machine handy to check this
8545 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8546 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8547 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8553 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8554 this is used for to form addresses to local data when -fPIC is in
8558 darwin_local_data_pic (rtx disp)
8560 return (GET_CODE (disp) == UNSPEC
8561 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8564 /* Determine if a given RTX is a valid constant. We already know this
8565 satisfies CONSTANT_P. */
8568 legitimate_constant_p (rtx x)
8570 switch (GET_CODE (x))
8575 if (GET_CODE (x) == PLUS)
8577 if (!CONST_INT_P (XEXP (x, 1)))
8582 if (TARGET_MACHO && darwin_local_data_pic (x))
8585 /* Only some unspecs are valid as "constants". */
8586 if (GET_CODE (x) == UNSPEC)
8587 switch (XINT (x, 1))
8592 return TARGET_64BIT;
8595 x = XVECEXP (x, 0, 0);
8596 return (GET_CODE (x) == SYMBOL_REF
8597 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8599 x = XVECEXP (x, 0, 0);
8600 return (GET_CODE (x) == SYMBOL_REF
8601 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
8606 /* We must have drilled down to a symbol. */
8607 if (GET_CODE (x) == LABEL_REF)
8609 if (GET_CODE (x) != SYMBOL_REF)
8614 /* TLS symbols are never valid. */
8615 if (SYMBOL_REF_TLS_MODEL (x))
8618 /* DLLIMPORT symbols are never valid. */
8619 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
8620 && SYMBOL_REF_DLLIMPORT_P (x))
8625 if (GET_MODE (x) == TImode
8626 && x != CONST0_RTX (TImode)
8632 if (x == CONST0_RTX (GET_MODE (x)))
8640 /* Otherwise we handle everything else in the move patterns. */
8644 /* Determine if it's legal to put X into the constant pool. This
8645 is not possible for the address of thread-local symbols, which
8646 is checked above. */
8649 ix86_cannot_force_const_mem (rtx x)
8651 /* We can always put integral constants and vectors in memory. */
8652 switch (GET_CODE (x))
8662 return !legitimate_constant_p (x);
8665 /* Determine if a given RTX is a valid constant address. */
8668 constant_address_p (rtx x)
8670 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
8673 /* Nonzero if the constant value X is a legitimate general operand
8674 when generating PIC code. It is given that flag_pic is on and
8675 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8678 legitimate_pic_operand_p (rtx x)
8682 switch (GET_CODE (x))
8685 inner = XEXP (x, 0);
8686 if (GET_CODE (inner) == PLUS
8687 && CONST_INT_P (XEXP (inner, 1)))
8688 inner = XEXP (inner, 0);
8690 /* Only some unspecs are valid as "constants". */
8691 if (GET_CODE (inner) == UNSPEC)
8692 switch (XINT (inner, 1))
8697 return TARGET_64BIT;
8699 x = XVECEXP (inner, 0, 0);
8700 return (GET_CODE (x) == SYMBOL_REF
8701 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8702 case UNSPEC_MACHOPIC_OFFSET:
8703 return legitimate_pic_address_disp_p (x);
8711 return legitimate_pic_address_disp_p (x);
8718 /* Determine if a given CONST RTX is a valid memory displacement
8722 legitimate_pic_address_disp_p (rtx disp)
8726 /* In 64bit mode we can allow direct addresses of symbols and labels
8727 when they are not dynamic symbols. */
8730 rtx op0 = disp, op1;
8732 switch (GET_CODE (disp))
8738 if (GET_CODE (XEXP (disp, 0)) != PLUS)
8740 op0 = XEXP (XEXP (disp, 0), 0);
8741 op1 = XEXP (XEXP (disp, 0), 1);
8742 if (!CONST_INT_P (op1)
8743 || INTVAL (op1) >= 16*1024*1024
8744 || INTVAL (op1) < -16*1024*1024)
8746 if (GET_CODE (op0) == LABEL_REF)
8748 if (GET_CODE (op0) != SYMBOL_REF)
8753 /* TLS references should always be enclosed in UNSPEC. */
8754 if (SYMBOL_REF_TLS_MODEL (op0))
8756 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
8757 && ix86_cmodel != CM_LARGE_PIC)
8765 if (GET_CODE (disp) != CONST)
8767 disp = XEXP (disp, 0);
8771 /* We are unsafe to allow PLUS expressions. This limit allowed distance
8772 of GOT tables. We should not need these anyway. */
8773 if (GET_CODE (disp) != UNSPEC
8774 || (XINT (disp, 1) != UNSPEC_GOTPCREL
8775 && XINT (disp, 1) != UNSPEC_GOTOFF
8776 && XINT (disp, 1) != UNSPEC_PLTOFF))
8779 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
8780 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
8786 if (GET_CODE (disp) == PLUS)
8788 if (!CONST_INT_P (XEXP (disp, 1)))
8790 disp = XEXP (disp, 0);
8794 if (TARGET_MACHO && darwin_local_data_pic (disp))
8797 if (GET_CODE (disp) != UNSPEC)
8800 switch (XINT (disp, 1))
8805 /* We need to check for both symbols and labels because VxWorks loads
8806 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
8808 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
8809 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
8811 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
8812 While ABI specify also 32bit relocation but we don't produce it in
8813 small PIC model at all. */
8814 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
8815 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
8817 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
8819 case UNSPEC_GOTTPOFF:
8820 case UNSPEC_GOTNTPOFF:
8821 case UNSPEC_INDNTPOFF:
8824 disp = XVECEXP (disp, 0, 0);
8825 return (GET_CODE (disp) == SYMBOL_REF
8826 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
8828 disp = XVECEXP (disp, 0, 0);
8829 return (GET_CODE (disp) == SYMBOL_REF
8830 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
8832 disp = XVECEXP (disp, 0, 0);
8833 return (GET_CODE (disp) == SYMBOL_REF
8834 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
8840 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
8841 memory address for an instruction. The MODE argument is the machine mode
8842 for the MEM expression that wants to use this address.
8844 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
8845 convert common non-canonical forms to canonical form so that they will
8849 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
8850 rtx addr, int strict)
8852 struct ix86_address parts;
8853 rtx base, index, disp;
8854 HOST_WIDE_INT scale;
8855 const char *reason = NULL;
8856 rtx reason_rtx = NULL_RTX;
8858 if (ix86_decompose_address (addr, &parts) <= 0)
8860 reason = "decomposition failed";
8865 index = parts.index;
8867 scale = parts.scale;
8869 /* Validate base register.
8871 Don't allow SUBREG's that span more than a word here. It can lead to spill
8872 failures when the base is one word out of a two word structure, which is
8873 represented internally as a DImode int. */
8882 else if (GET_CODE (base) == SUBREG
8883 && REG_P (SUBREG_REG (base))
8884 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
8886 reg = SUBREG_REG (base);
8889 reason = "base is not a register";
8893 if (GET_MODE (base) != Pmode)
8895 reason = "base is not in Pmode";
8899 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
8900 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
8902 reason = "base is not valid";
8907 /* Validate index register.
8909 Don't allow SUBREG's that span more than a word here -- same as above. */
8918 else if (GET_CODE (index) == SUBREG
8919 && REG_P (SUBREG_REG (index))
8920 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
8922 reg = SUBREG_REG (index);
8925 reason = "index is not a register";
8929 if (GET_MODE (index) != Pmode)
8931 reason = "index is not in Pmode";
8935 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
8936 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
8938 reason = "index is not valid";
8943 /* Validate scale factor. */
8946 reason_rtx = GEN_INT (scale);
8949 reason = "scale without index";
8953 if (scale != 2 && scale != 4 && scale != 8)
8955 reason = "scale is not a valid multiplier";
8960 /* Validate displacement. */
8965 if (GET_CODE (disp) == CONST
8966 && GET_CODE (XEXP (disp, 0)) == UNSPEC
8967 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
8968 switch (XINT (XEXP (disp, 0), 1))
8970 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
8971 used. While ABI specify also 32bit relocations, we don't produce
8972 them at all and use IP relative instead. */
8975 gcc_assert (flag_pic);
8977 goto is_legitimate_pic;
8978 reason = "64bit address unspec";
8981 case UNSPEC_GOTPCREL:
8982 gcc_assert (flag_pic);
8983 goto is_legitimate_pic;
8985 case UNSPEC_GOTTPOFF:
8986 case UNSPEC_GOTNTPOFF:
8987 case UNSPEC_INDNTPOFF:
8993 reason = "invalid address unspec";
8997 else if (SYMBOLIC_CONST (disp)
9001 && MACHOPIC_INDIRECT
9002 && !machopic_operand_p (disp)
9008 if (TARGET_64BIT && (index || base))
9010 /* foo@dtpoff(%rX) is ok. */
9011 if (GET_CODE (disp) != CONST
9012 || GET_CODE (XEXP (disp, 0)) != PLUS
9013 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9014 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9015 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9016 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9018 reason = "non-constant pic memory reference";
9022 else if (! legitimate_pic_address_disp_p (disp))
9024 reason = "displacement is an invalid pic construct";
9028 /* This code used to verify that a symbolic pic displacement
9029 includes the pic_offset_table_rtx register.
9031 While this is good idea, unfortunately these constructs may
9032 be created by "adds using lea" optimization for incorrect
9041 This code is nonsensical, but results in addressing
9042 GOT table with pic_offset_table_rtx base. We can't
9043 just refuse it easily, since it gets matched by
9044 "addsi3" pattern, that later gets split to lea in the
9045 case output register differs from input. While this
9046 can be handled by separate addsi pattern for this case
9047 that never results in lea, this seems to be easier and
9048 correct fix for crash to disable this test. */
9050 else if (GET_CODE (disp) != LABEL_REF
9051 && !CONST_INT_P (disp)
9052 && (GET_CODE (disp) != CONST
9053 || !legitimate_constant_p (disp))
9054 && (GET_CODE (disp) != SYMBOL_REF
9055 || !legitimate_constant_p (disp)))
9057 reason = "displacement is not constant";
9060 else if (TARGET_64BIT
9061 && !x86_64_immediate_operand (disp, VOIDmode))
9063 reason = "displacement is out of range";
9068 /* Everything looks valid. */
9075 /* Return a unique alias set for the GOT. */
9077 static alias_set_type
9078 ix86_GOT_alias_set (void)
9080 static alias_set_type set = -1;
9082 set = new_alias_set ();
9086 /* Return a legitimate reference for ORIG (an address) using the
9087 register REG. If REG is 0, a new pseudo is generated.
9089 There are two types of references that must be handled:
9091 1. Global data references must load the address from the GOT, via
9092 the PIC reg. An insn is emitted to do this load, and the reg is
9095 2. Static data references, constant pool addresses, and code labels
9096 compute the address as an offset from the GOT, whose base is in
9097 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9098 differentiate them from global data objects. The returned
9099 address is the PIC reg + an unspec constant.
9101 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9102 reg also appears in the address. */
9105 legitimize_pic_address (rtx orig, rtx reg)
9112 if (TARGET_MACHO && !TARGET_64BIT)
9115 reg = gen_reg_rtx (Pmode);
9116 /* Use the generic Mach-O PIC machinery. */
9117 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9121 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9123 else if (TARGET_64BIT
9124 && ix86_cmodel != CM_SMALL_PIC
9125 && gotoff_operand (addr, Pmode))
9128 /* This symbol may be referenced via a displacement from the PIC
9129 base address (@GOTOFF). */
9131 if (reload_in_progress)
9132 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9133 if (GET_CODE (addr) == CONST)
9134 addr = XEXP (addr, 0);
9135 if (GET_CODE (addr) == PLUS)
9137 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9139 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9142 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9143 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9145 tmpreg = gen_reg_rtx (Pmode);
9148 emit_move_insn (tmpreg, new_rtx);
9152 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9153 tmpreg, 1, OPTAB_DIRECT);
9156 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9158 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9160 /* This symbol may be referenced via a displacement from the PIC
9161 base address (@GOTOFF). */
9163 if (reload_in_progress)
9164 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9165 if (GET_CODE (addr) == CONST)
9166 addr = XEXP (addr, 0);
9167 if (GET_CODE (addr) == PLUS)
9169 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9171 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9174 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9175 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9176 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9180 emit_move_insn (reg, new_rtx);
9184 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9185 /* We can't use @GOTOFF for text labels on VxWorks;
9186 see gotoff_operand. */
9187 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9189 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9191 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9192 return legitimize_dllimport_symbol (addr, true);
9193 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9194 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9195 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9197 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9198 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9202 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9204 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9205 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9206 new_rtx = gen_const_mem (Pmode, new_rtx);
9207 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9210 reg = gen_reg_rtx (Pmode);
9211 /* Use directly gen_movsi, otherwise the address is loaded
9212 into register for CSE. We don't want to CSE this addresses,
9213 instead we CSE addresses from the GOT table, so skip this. */
9214 emit_insn (gen_movsi (reg, new_rtx));
9219 /* This symbol must be referenced via a load from the
9220 Global Offset Table (@GOT). */
9222 if (reload_in_progress)
9223 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9224 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9225 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9227 new_rtx = force_reg (Pmode, new_rtx);
9228 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9229 new_rtx = gen_const_mem (Pmode, new_rtx);
9230 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9233 reg = gen_reg_rtx (Pmode);
9234 emit_move_insn (reg, new_rtx);
9240 if (CONST_INT_P (addr)
9241 && !x86_64_immediate_operand (addr, VOIDmode))
9245 emit_move_insn (reg, addr);
9249 new_rtx = force_reg (Pmode, addr);
9251 else if (GET_CODE (addr) == CONST)
9253 addr = XEXP (addr, 0);
9255 /* We must match stuff we generate before. Assume the only
9256 unspecs that can get here are ours. Not that we could do
9257 anything with them anyway.... */
9258 if (GET_CODE (addr) == UNSPEC
9259 || (GET_CODE (addr) == PLUS
9260 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9262 gcc_assert (GET_CODE (addr) == PLUS);
9264 if (GET_CODE (addr) == PLUS)
9266 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9268 /* Check first to see if this is a constant offset from a @GOTOFF
9269 symbol reference. */
9270 if (gotoff_operand (op0, Pmode)
9271 && CONST_INT_P (op1))
9275 if (reload_in_progress)
9276 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9277 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9279 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9280 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9281 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9285 emit_move_insn (reg, new_rtx);
9291 if (INTVAL (op1) < -16*1024*1024
9292 || INTVAL (op1) >= 16*1024*1024)
9294 if (!x86_64_immediate_operand (op1, Pmode))
9295 op1 = force_reg (Pmode, op1);
9296 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9302 base = legitimize_pic_address (XEXP (addr, 0), reg);
9303 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9304 base == reg ? NULL_RTX : reg);
9306 if (CONST_INT_P (new_rtx))
9307 new_rtx = plus_constant (base, INTVAL (new_rtx));
9310 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9312 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9313 new_rtx = XEXP (new_rtx, 1);
9315 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9323 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9326 get_thread_pointer (int to_reg)
9330 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9334 reg = gen_reg_rtx (Pmode);
9335 insn = gen_rtx_SET (VOIDmode, reg, tp);
9336 insn = emit_insn (insn);
9341 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9342 false if we expect this to be used for a memory address and true if
9343 we expect to load the address into a register. */
9346 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9348 rtx dest, base, off, pic, tp;
9353 case TLS_MODEL_GLOBAL_DYNAMIC:
9354 dest = gen_reg_rtx (Pmode);
9355 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9357 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9359 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9362 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9363 insns = get_insns ();
9366 RTL_CONST_CALL_P (insns) = 1;
9367 emit_libcall_block (insns, dest, rax, x);
9369 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9370 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9372 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9374 if (TARGET_GNU2_TLS)
9376 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9378 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9382 case TLS_MODEL_LOCAL_DYNAMIC:
9383 base = gen_reg_rtx (Pmode);
9384 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9386 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9388 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9391 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9392 insns = get_insns ();
9395 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9396 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9397 RTL_CONST_CALL_P (insns) = 1;
9398 emit_libcall_block (insns, base, rax, note);
9400 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9401 emit_insn (gen_tls_local_dynamic_base_64 (base));
9403 emit_insn (gen_tls_local_dynamic_base_32 (base));
9405 if (TARGET_GNU2_TLS)
9407 rtx x = ix86_tls_module_base ();
9409 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9410 gen_rtx_MINUS (Pmode, x, tp));
9413 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9414 off = gen_rtx_CONST (Pmode, off);
9416 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9418 if (TARGET_GNU2_TLS)
9420 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9422 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9427 case TLS_MODEL_INITIAL_EXEC:
9431 type = UNSPEC_GOTNTPOFF;
9435 if (reload_in_progress)
9436 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9437 pic = pic_offset_table_rtx;
9438 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9440 else if (!TARGET_ANY_GNU_TLS)
9442 pic = gen_reg_rtx (Pmode);
9443 emit_insn (gen_set_got (pic));
9444 type = UNSPEC_GOTTPOFF;
9449 type = UNSPEC_INDNTPOFF;
9452 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9453 off = gen_rtx_CONST (Pmode, off);
9455 off = gen_rtx_PLUS (Pmode, pic, off);
9456 off = gen_const_mem (Pmode, off);
9457 set_mem_alias_set (off, ix86_GOT_alias_set ());
9459 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9461 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9462 off = force_reg (Pmode, off);
9463 return gen_rtx_PLUS (Pmode, base, off);
9467 base = get_thread_pointer (true);
9468 dest = gen_reg_rtx (Pmode);
9469 emit_insn (gen_subsi3 (dest, base, off));
9473 case TLS_MODEL_LOCAL_EXEC:
9474 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9475 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9476 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9477 off = gen_rtx_CONST (Pmode, off);
9479 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9481 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9482 return gen_rtx_PLUS (Pmode, base, off);
9486 base = get_thread_pointer (true);
9487 dest = gen_reg_rtx (Pmode);
9488 emit_insn (gen_subsi3 (dest, base, off));
9499 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9502 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9503 htab_t dllimport_map;
9506 get_dllimport_decl (tree decl)
9508 struct tree_map *h, in;
9512 size_t namelen, prefixlen;
9518 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9520 in.hash = htab_hash_pointer (decl);
9521 in.base.from = decl;
9522 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9523 h = (struct tree_map *) *loc;
9527 *loc = h = GGC_NEW (struct tree_map);
9529 h->base.from = decl;
9530 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9531 DECL_ARTIFICIAL (to) = 1;
9532 DECL_IGNORED_P (to) = 1;
9533 DECL_EXTERNAL (to) = 1;
9534 TREE_READONLY (to) = 1;
9536 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9537 name = targetm.strip_name_encoding (name);
9538 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9539 ? "*__imp_" : "*__imp__";
9540 namelen = strlen (name);
9541 prefixlen = strlen (prefix);
9542 imp_name = (char *) alloca (namelen + prefixlen + 1);
9543 memcpy (imp_name, prefix, prefixlen);
9544 memcpy (imp_name + prefixlen, name, namelen + 1);
9546 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9547 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9548 SET_SYMBOL_REF_DECL (rtl, to);
9549 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9551 rtl = gen_const_mem (Pmode, rtl);
9552 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9554 SET_DECL_RTL (to, rtl);
9555 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9560 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9561 true if we require the result be a register. */
9564 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9569 gcc_assert (SYMBOL_REF_DECL (symbol));
9570 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9572 x = DECL_RTL (imp_decl);
9574 x = force_reg (Pmode, x);
9578 /* Try machine-dependent ways of modifying an illegitimate address
9579 to be legitimate. If we find one, return the new, valid address.
9580 This macro is used in only one place: `memory_address' in explow.c.
9582 OLDX is the address as it was before break_out_memory_refs was called.
9583 In some cases it is useful to look at this to decide what needs to be done.
9585 MODE and WIN are passed so that this macro can use
9586 GO_IF_LEGITIMATE_ADDRESS.
9588 It is always safe for this macro to do nothing. It exists to recognize
9589 opportunities to optimize the output.
9591 For the 80386, we handle X+REG by loading X into a register R and
9592 using R+REG. R will go in a general reg and indexing will be used.
9593 However, if REG is a broken-out memory address or multiplication,
9594 nothing needs to be done because REG can certainly go in a general reg.
9596 When -fpic is used, special handling is needed for symbolic references.
9597 See comments by legitimize_pic_address in i386.c for details. */
9600 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
9605 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
9607 return legitimize_tls_address (x, (enum tls_model) log, false);
9608 if (GET_CODE (x) == CONST
9609 && GET_CODE (XEXP (x, 0)) == PLUS
9610 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9611 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
9613 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
9614 (enum tls_model) log, false);
9615 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9618 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9620 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
9621 return legitimize_dllimport_symbol (x, true);
9622 if (GET_CODE (x) == CONST
9623 && GET_CODE (XEXP (x, 0)) == PLUS
9624 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9625 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
9627 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
9628 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9632 if (flag_pic && SYMBOLIC_CONST (x))
9633 return legitimize_pic_address (x, 0);
9635 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9636 if (GET_CODE (x) == ASHIFT
9637 && CONST_INT_P (XEXP (x, 1))
9638 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
9641 log = INTVAL (XEXP (x, 1));
9642 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
9643 GEN_INT (1 << log));
9646 if (GET_CODE (x) == PLUS)
9648 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9650 if (GET_CODE (XEXP (x, 0)) == ASHIFT
9651 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9652 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
9655 log = INTVAL (XEXP (XEXP (x, 0), 1));
9656 XEXP (x, 0) = gen_rtx_MULT (Pmode,
9657 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
9658 GEN_INT (1 << log));
9661 if (GET_CODE (XEXP (x, 1)) == ASHIFT
9662 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
9663 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
9666 log = INTVAL (XEXP (XEXP (x, 1), 1));
9667 XEXP (x, 1) = gen_rtx_MULT (Pmode,
9668 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
9669 GEN_INT (1 << log));
9672 /* Put multiply first if it isn't already. */
9673 if (GET_CODE (XEXP (x, 1)) == MULT)
9675 rtx tmp = XEXP (x, 0);
9676 XEXP (x, 0) = XEXP (x, 1);
9681 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9682 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9683 created by virtual register instantiation, register elimination, and
9684 similar optimizations. */
9685 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
9688 x = gen_rtx_PLUS (Pmode,
9689 gen_rtx_PLUS (Pmode, XEXP (x, 0),
9690 XEXP (XEXP (x, 1), 0)),
9691 XEXP (XEXP (x, 1), 1));
9695 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9696 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9697 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
9698 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
9699 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
9700 && CONSTANT_P (XEXP (x, 1)))
9703 rtx other = NULL_RTX;
9705 if (CONST_INT_P (XEXP (x, 1)))
9707 constant = XEXP (x, 1);
9708 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
9710 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
9712 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
9713 other = XEXP (x, 1);
9721 x = gen_rtx_PLUS (Pmode,
9722 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
9723 XEXP (XEXP (XEXP (x, 0), 1), 0)),
9724 plus_constant (other, INTVAL (constant)));
9728 if (changed && legitimate_address_p (mode, x, FALSE))
9731 if (GET_CODE (XEXP (x, 0)) == MULT)
9734 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
9737 if (GET_CODE (XEXP (x, 1)) == MULT)
9740 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
9744 && REG_P (XEXP (x, 1))
9745 && REG_P (XEXP (x, 0)))
9748 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
9751 x = legitimize_pic_address (x, 0);
9754 if (changed && legitimate_address_p (mode, x, FALSE))
9757 if (REG_P (XEXP (x, 0)))
9759 rtx temp = gen_reg_rtx (Pmode);
9760 rtx val = force_operand (XEXP (x, 1), temp);
9762 emit_move_insn (temp, val);
9768 else if (REG_P (XEXP (x, 1)))
9770 rtx temp = gen_reg_rtx (Pmode);
9771 rtx val = force_operand (XEXP (x, 0), temp);
9773 emit_move_insn (temp, val);
9783 /* Print an integer constant expression in assembler syntax. Addition
9784 and subtraction are the only arithmetic that may appear in these
9785 expressions. FILE is the stdio stream to write to, X is the rtx, and
9786 CODE is the operand print code from the output string. */
9789 output_pic_addr_const (FILE *file, rtx x, int code)
9793 switch (GET_CODE (x))
9796 gcc_assert (flag_pic);
9801 if (! TARGET_MACHO || TARGET_64BIT)
9802 output_addr_const (file, x);
9805 const char *name = XSTR (x, 0);
9807 /* Mark the decl as referenced so that cgraph will
9808 output the function. */
9809 if (SYMBOL_REF_DECL (x))
9810 mark_decl_referenced (SYMBOL_REF_DECL (x));
9813 if (MACHOPIC_INDIRECT
9814 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9815 name = machopic_indirection_name (x, /*stub_p=*/true);
9817 assemble_name (file, name);
9819 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
9820 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
9821 fputs ("@PLT", file);
9828 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
9829 assemble_name (asm_out_file, buf);
9833 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9837 /* This used to output parentheses around the expression,
9838 but that does not work on the 386 (either ATT or BSD assembler). */
9839 output_pic_addr_const (file, XEXP (x, 0), code);
9843 if (GET_MODE (x) == VOIDmode)
9845 /* We can use %d if the number is <32 bits and positive. */
9846 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
9847 fprintf (file, "0x%lx%08lx",
9848 (unsigned long) CONST_DOUBLE_HIGH (x),
9849 (unsigned long) CONST_DOUBLE_LOW (x));
9851 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
9854 /* We can't handle floating point constants;
9855 PRINT_OPERAND must handle them. */
9856 output_operand_lossage ("floating constant misused");
9860 /* Some assemblers need integer constants to appear first. */
9861 if (CONST_INT_P (XEXP (x, 0)))
9863 output_pic_addr_const (file, XEXP (x, 0), code);
9865 output_pic_addr_const (file, XEXP (x, 1), code);
9869 gcc_assert (CONST_INT_P (XEXP (x, 1)));
9870 output_pic_addr_const (file, XEXP (x, 1), code);
9872 output_pic_addr_const (file, XEXP (x, 0), code);
9878 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
9879 output_pic_addr_const (file, XEXP (x, 0), code);
9881 output_pic_addr_const (file, XEXP (x, 1), code);
9883 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
9887 gcc_assert (XVECLEN (x, 0) == 1);
9888 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
9889 switch (XINT (x, 1))
9892 fputs ("@GOT", file);
9895 fputs ("@GOTOFF", file);
9898 fputs ("@PLTOFF", file);
9900 case UNSPEC_GOTPCREL:
9901 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9902 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
9904 case UNSPEC_GOTTPOFF:
9905 /* FIXME: This might be @TPOFF in Sun ld too. */
9906 fputs ("@GOTTPOFF", file);
9909 fputs ("@TPOFF", file);
9913 fputs ("@TPOFF", file);
9915 fputs ("@NTPOFF", file);
9918 fputs ("@DTPOFF", file);
9920 case UNSPEC_GOTNTPOFF:
9922 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9923 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
9925 fputs ("@GOTNTPOFF", file);
9927 case UNSPEC_INDNTPOFF:
9928 fputs ("@INDNTPOFF", file);
9931 case UNSPEC_MACHOPIC_OFFSET:
9933 machopic_output_function_base_name (file);
9937 output_operand_lossage ("invalid UNSPEC as operand");
9943 output_operand_lossage ("invalid expression as operand");
9947 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9948 We need to emit DTP-relative relocations. */
9950 static void ATTRIBUTE_UNUSED
9951 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
9953 fputs (ASM_LONG, file);
9954 output_addr_const (file, x);
9955 fputs ("@DTPOFF", file);
9961 fputs (", 0", file);
9968 /* Return true if X is a representation of the PIC register. This copes
9969 with calls from ix86_find_base_term, where the register might have
9970 been replaced by a cselib value. */
9973 ix86_pic_register_p (rtx x)
9975 if (GET_CODE (x) == VALUE)
9976 return (pic_offset_table_rtx
9977 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
9979 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
9982 /* In the name of slightly smaller debug output, and to cater to
9983 general assembler lossage, recognize PIC+GOTOFF and turn it back
9984 into a direct symbol reference.
9986 On Darwin, this is necessary to avoid a crash, because Darwin
9987 has a different PIC label for each routine but the DWARF debugging
9988 information is not associated with any particular routine, so it's
9989 necessary to remove references to the PIC label from RTL stored by
9990 the DWARF output code. */
9993 ix86_delegitimize_address (rtx orig_x)
9996 /* reg_addend is NULL or a multiple of some register. */
9997 rtx reg_addend = NULL_RTX;
9998 /* const_addend is NULL or a const_int. */
9999 rtx const_addend = NULL_RTX;
10000 /* This is the result, or NULL. */
10001 rtx result = NULL_RTX;
10008 if (GET_CODE (x) != CONST
10009 || GET_CODE (XEXP (x, 0)) != UNSPEC
10010 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10011 || !MEM_P (orig_x))
10013 return XVECEXP (XEXP (x, 0), 0, 0);
10016 if (GET_CODE (x) != PLUS
10017 || GET_CODE (XEXP (x, 1)) != CONST)
10020 if (ix86_pic_register_p (XEXP (x, 0)))
10021 /* %ebx + GOT/GOTOFF */
10023 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10025 /* %ebx + %reg * scale + GOT/GOTOFF */
10026 reg_addend = XEXP (x, 0);
10027 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10028 reg_addend = XEXP (reg_addend, 1);
10029 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10030 reg_addend = XEXP (reg_addend, 0);
10033 if (!REG_P (reg_addend)
10034 && GET_CODE (reg_addend) != MULT
10035 && GET_CODE (reg_addend) != ASHIFT)
10041 x = XEXP (XEXP (x, 1), 0);
10042 if (GET_CODE (x) == PLUS
10043 && CONST_INT_P (XEXP (x, 1)))
10045 const_addend = XEXP (x, 1);
10049 if (GET_CODE (x) == UNSPEC
10050 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10051 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10052 result = XVECEXP (x, 0, 0);
10054 if (TARGET_MACHO && darwin_local_data_pic (x)
10055 && !MEM_P (orig_x))
10056 result = XVECEXP (x, 0, 0);
10062 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10064 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10068 /* If X is a machine specific address (i.e. a symbol or label being
10069 referenced as a displacement from the GOT implemented using an
10070 UNSPEC), then return the base term. Otherwise return X. */
10073 ix86_find_base_term (rtx x)
10079 if (GET_CODE (x) != CONST)
10081 term = XEXP (x, 0);
10082 if (GET_CODE (term) == PLUS
10083 && (CONST_INT_P (XEXP (term, 1))
10084 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10085 term = XEXP (term, 0);
10086 if (GET_CODE (term) != UNSPEC
10087 || XINT (term, 1) != UNSPEC_GOTPCREL)
10090 return XVECEXP (term, 0, 0);
10093 return ix86_delegitimize_address (x);
10097 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10098 int fp, FILE *file)
10100 const char *suffix;
10102 if (mode == CCFPmode || mode == CCFPUmode)
10104 enum rtx_code second_code, bypass_code;
10105 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10106 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10107 code = ix86_fp_compare_code_to_integer (code);
10111 code = reverse_condition (code);
10162 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10166 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10167 Those same assemblers have the same but opposite lossage on cmov. */
10168 if (mode == CCmode)
10169 suffix = fp ? "nbe" : "a";
10170 else if (mode == CCCmode)
10173 gcc_unreachable ();
10189 gcc_unreachable ();
10193 gcc_assert (mode == CCmode || mode == CCCmode);
10210 gcc_unreachable ();
10214 /* ??? As above. */
10215 gcc_assert (mode == CCmode || mode == CCCmode);
10216 suffix = fp ? "nb" : "ae";
10219 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10223 /* ??? As above. */
10224 if (mode == CCmode)
10226 else if (mode == CCCmode)
10227 suffix = fp ? "nb" : "ae";
10229 gcc_unreachable ();
10232 suffix = fp ? "u" : "p";
10235 suffix = fp ? "nu" : "np";
10238 gcc_unreachable ();
10240 fputs (suffix, file);
10243 /* Print the name of register X to FILE based on its machine mode and number.
10244 If CODE is 'w', pretend the mode is HImode.
10245 If CODE is 'b', pretend the mode is QImode.
10246 If CODE is 'k', pretend the mode is SImode.
10247 If CODE is 'q', pretend the mode is DImode.
10248 If CODE is 'x', pretend the mode is V4SFmode.
10249 If CODE is 't', pretend the mode is V8SFmode.
10250 If CODE is 'h', pretend the reg is the 'high' byte register.
10251 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10252 If CODE is 'd', duplicate the operand for AVX instruction.
10256 print_reg (rtx x, int code, FILE *file)
10259 bool duplicated = code == 'd' && TARGET_AVX;
10261 gcc_assert (x == pc_rtx
10262 || (REGNO (x) != ARG_POINTER_REGNUM
10263 && REGNO (x) != FRAME_POINTER_REGNUM
10264 && REGNO (x) != FLAGS_REG
10265 && REGNO (x) != FPSR_REG
10266 && REGNO (x) != FPCR_REG));
10268 if (ASSEMBLER_DIALECT == ASM_ATT)
10273 gcc_assert (TARGET_64BIT);
10274 fputs ("rip", file);
10278 if (code == 'w' || MMX_REG_P (x))
10280 else if (code == 'b')
10282 else if (code == 'k')
10284 else if (code == 'q')
10286 else if (code == 'y')
10288 else if (code == 'h')
10290 else if (code == 'x')
10292 else if (code == 't')
10295 code = GET_MODE_SIZE (GET_MODE (x));
10297 /* Irritatingly, AMD extended registers use different naming convention
10298 from the normal registers. */
10299 if (REX_INT_REG_P (x))
10301 gcc_assert (TARGET_64BIT);
10305 error ("extended registers have no high halves");
10308 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10311 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10314 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10317 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10320 error ("unsupported operand size for extended register");
10330 if (STACK_TOP_P (x))
10339 if (! ANY_FP_REG_P (x))
10340 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10345 reg = hi_reg_name[REGNO (x)];
10348 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10350 reg = qi_reg_name[REGNO (x)];
10353 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10355 reg = qi_high_reg_name[REGNO (x)];
10360 gcc_assert (!duplicated);
10362 fputs (hi_reg_name[REGNO (x)] + 1, file);
10367 gcc_unreachable ();
10373 if (ASSEMBLER_DIALECT == ASM_ATT)
10374 fprintf (file, ", %%%s", reg);
10376 fprintf (file, ", %s", reg);
10380 /* Locate some local-dynamic symbol still in use by this function
10381 so that we can print its name in some tls_local_dynamic_base
10385 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10389 if (GET_CODE (x) == SYMBOL_REF
10390 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10392 cfun->machine->some_ld_name = XSTR (x, 0);
10399 static const char *
10400 get_some_local_dynamic_name (void)
10404 if (cfun->machine->some_ld_name)
10405 return cfun->machine->some_ld_name;
10407 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10409 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10410 return cfun->machine->some_ld_name;
10412 gcc_unreachable ();
10415 /* Meaning of CODE:
10416 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10417 C -- print opcode suffix for set/cmov insn.
10418 c -- like C, but print reversed condition
10419 E,e -- likewise, but for compare-and-branch fused insn.
10420 F,f -- likewise, but for floating-point.
10421 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10423 R -- print the prefix for register names.
10424 z -- print the opcode suffix for the size of the current operand.
10425 * -- print a star (in certain assembler syntax)
10426 A -- print an absolute memory reference.
10427 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10428 s -- print a shift double count, followed by the assemblers argument
10430 b -- print the QImode name of the register for the indicated operand.
10431 %b0 would print %al if operands[0] is reg 0.
10432 w -- likewise, print the HImode name of the register.
10433 k -- likewise, print the SImode name of the register.
10434 q -- likewise, print the DImode name of the register.
10435 x -- likewise, print the V4SFmode name of the register.
10436 t -- likewise, print the V8SFmode name of the register.
10437 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10438 y -- print "st(0)" instead of "st" as a register.
10439 d -- print duplicated register operand for AVX instruction.
10440 D -- print condition for SSE cmp instruction.
10441 P -- if PIC, print an @PLT suffix.
10442 X -- don't print any sort of PIC '@' suffix for a symbol.
10443 & -- print some in-use local-dynamic symbol name.
10444 H -- print a memory address offset by 8; used for sse high-parts
10445 Y -- print condition for SSE5 com* instruction.
10446 + -- print a branch hint as 'cs' or 'ds' prefix
10447 ; -- print a semicolon (after prefixes due to bug in older gas).
10451 print_operand (FILE *file, rtx x, int code)
10458 if (ASSEMBLER_DIALECT == ASM_ATT)
10463 assemble_name (file, get_some_local_dynamic_name ());
10467 switch (ASSEMBLER_DIALECT)
10474 /* Intel syntax. For absolute addresses, registers should not
10475 be surrounded by braces. */
10479 PRINT_OPERAND (file, x, 0);
10486 gcc_unreachable ();
10489 PRINT_OPERAND (file, x, 0);
10494 if (ASSEMBLER_DIALECT == ASM_ATT)
10499 if (ASSEMBLER_DIALECT == ASM_ATT)
10504 if (ASSEMBLER_DIALECT == ASM_ATT)
10509 if (ASSEMBLER_DIALECT == ASM_ATT)
10514 if (ASSEMBLER_DIALECT == ASM_ATT)
10519 if (ASSEMBLER_DIALECT == ASM_ATT)
10524 /* 387 opcodes don't get size suffixes if the operands are
10526 if (STACK_REG_P (x))
10529 /* Likewise if using Intel opcodes. */
10530 if (ASSEMBLER_DIALECT == ASM_INTEL)
10533 /* This is the size of op from size of operand. */
10534 switch (GET_MODE_SIZE (GET_MODE (x)))
10543 #ifdef HAVE_GAS_FILDS_FISTS
10553 if (GET_MODE (x) == SFmode)
10568 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10572 #ifdef GAS_MNEMONICS
10587 gcc_unreachable ();
10604 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
10606 PRINT_OPERAND (file, x, 0);
10607 fputs (", ", file);
10612 /* Little bit of braindamage here. The SSE compare instructions
10613 does use completely different names for the comparisons that the
10614 fp conditional moves. */
10617 switch (GET_CODE (x))
10620 fputs ("eq", file);
10623 fputs ("eq_us", file);
10626 fputs ("lt", file);
10629 fputs ("nge", file);
10632 fputs ("le", file);
10635 fputs ("ngt", file);
10638 fputs ("unord", file);
10641 fputs ("neq", file);
10644 fputs ("neq_oq", file);
10647 fputs ("ge", file);
10650 fputs ("nlt", file);
10653 fputs ("gt", file);
10656 fputs ("nle", file);
10659 fputs ("ord", file);
10662 gcc_unreachable ();
10667 switch (GET_CODE (x))
10671 fputs ("eq", file);
10675 fputs ("lt", file);
10679 fputs ("le", file);
10682 fputs ("unord", file);
10686 fputs ("neq", file);
10690 fputs ("nlt", file);
10694 fputs ("nle", file);
10697 fputs ("ord", file);
10700 gcc_unreachable ();
10705 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10706 if (ASSEMBLER_DIALECT == ASM_ATT)
10708 switch (GET_MODE (x))
10710 case HImode: putc ('w', file); break;
10712 case SFmode: putc ('l', file); break;
10714 case DFmode: putc ('q', file); break;
10715 default: gcc_unreachable ();
10722 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
10725 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10726 if (ASSEMBLER_DIALECT == ASM_ATT)
10729 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
10732 /* Like above, but reverse condition */
10734 /* Check to see if argument to %c is really a constant
10735 and not a condition code which needs to be reversed. */
10736 if (!COMPARISON_P (x))
10738 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
10741 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
10744 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10745 if (ASSEMBLER_DIALECT == ASM_ATT)
10748 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
10752 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
10756 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
10760 /* It doesn't actually matter what mode we use here, as we're
10761 only going to use this for printing. */
10762 x = adjust_address_nv (x, DImode, 8);
10770 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
10773 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
10776 int pred_val = INTVAL (XEXP (x, 0));
10778 if (pred_val < REG_BR_PROB_BASE * 45 / 100
10779 || pred_val > REG_BR_PROB_BASE * 55 / 100)
10781 int taken = pred_val > REG_BR_PROB_BASE / 2;
10782 int cputaken = final_forward_branch_p (current_output_insn) == 0;
10784 /* Emit hints only in the case default branch prediction
10785 heuristics would fail. */
10786 if (taken != cputaken)
10788 /* We use 3e (DS) prefix for taken branches and
10789 2e (CS) prefix for not taken branches. */
10791 fputs ("ds ; ", file);
10793 fputs ("cs ; ", file);
10801 switch (GET_CODE (x))
10804 fputs ("neq", file);
10807 fputs ("eq", file);
10811 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
10815 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
10819 fputs ("le", file);
10823 fputs ("lt", file);
10826 fputs ("unord", file);
10829 fputs ("ord", file);
10832 fputs ("ueq", file);
10835 fputs ("nlt", file);
10838 fputs ("nle", file);
10841 fputs ("ule", file);
10844 fputs ("ult", file);
10847 fputs ("une", file);
10850 gcc_unreachable ();
10856 fputs (" ; ", file);
10863 output_operand_lossage ("invalid operand code '%c'", code);
10868 print_reg (x, code, file);
10870 else if (MEM_P (x))
10872 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
10873 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
10874 && GET_MODE (x) != BLKmode)
10877 switch (GET_MODE_SIZE (GET_MODE (x)))
10879 case 1: size = "BYTE"; break;
10880 case 2: size = "WORD"; break;
10881 case 4: size = "DWORD"; break;
10882 case 8: size = "QWORD"; break;
10883 case 12: size = "XWORD"; break;
10885 if (GET_MODE (x) == XFmode)
10891 gcc_unreachable ();
10894 /* Check for explicit size override (codes 'b', 'w' and 'k') */
10897 else if (code == 'w')
10899 else if (code == 'k')
10902 fputs (size, file);
10903 fputs (" PTR ", file);
10907 /* Avoid (%rip) for call operands. */
10908 if (CONSTANT_ADDRESS_P (x) && code == 'P'
10909 && !CONST_INT_P (x))
10910 output_addr_const (file, x);
10911 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
10912 output_operand_lossage ("invalid constraints for operand");
10914 output_address (x);
10917 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
10922 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10923 REAL_VALUE_TO_TARGET_SINGLE (r, l);
10925 if (ASSEMBLER_DIALECT == ASM_ATT)
10927 fprintf (file, "0x%08lx", (long unsigned int) l);
10930 /* These float cases don't actually occur as immediate operands. */
10931 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
10935 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
10936 fprintf (file, "%s", dstr);
10939 else if (GET_CODE (x) == CONST_DOUBLE
10940 && GET_MODE (x) == XFmode)
10944 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
10945 fprintf (file, "%s", dstr);
10950 /* We have patterns that allow zero sets of memory, for instance.
10951 In 64-bit mode, we should probably support all 8-byte vectors,
10952 since we can in fact encode that into an immediate. */
10953 if (GET_CODE (x) == CONST_VECTOR)
10955 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
10961 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
10963 if (ASSEMBLER_DIALECT == ASM_ATT)
10966 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
10967 || GET_CODE (x) == LABEL_REF)
10969 if (ASSEMBLER_DIALECT == ASM_ATT)
10972 fputs ("OFFSET FLAT:", file);
10975 if (CONST_INT_P (x))
10976 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10978 output_pic_addr_const (file, x, code);
10980 output_addr_const (file, x);
10984 /* Print a memory operand whose address is ADDR. */
10987 print_operand_address (FILE *file, rtx addr)
10989 struct ix86_address parts;
10990 rtx base, index, disp;
10992 int ok = ix86_decompose_address (addr, &parts);
10997 index = parts.index;
10999 scale = parts.scale;
11007 if (ASSEMBLER_DIALECT == ASM_ATT)
11009 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11012 gcc_unreachable ();
11015 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11016 if (TARGET_64BIT && !base && !index)
11020 if (GET_CODE (disp) == CONST
11021 && GET_CODE (XEXP (disp, 0)) == PLUS
11022 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11023 symbol = XEXP (XEXP (disp, 0), 0);
11025 if (GET_CODE (symbol) == LABEL_REF
11026 || (GET_CODE (symbol) == SYMBOL_REF
11027 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11030 if (!base && !index)
11032 /* Displacement only requires special attention. */
11034 if (CONST_INT_P (disp))
11036 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11037 fputs ("ds:", file);
11038 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11041 output_pic_addr_const (file, disp, 0);
11043 output_addr_const (file, disp);
11047 if (ASSEMBLER_DIALECT == ASM_ATT)
11052 output_pic_addr_const (file, disp, 0);
11053 else if (GET_CODE (disp) == LABEL_REF)
11054 output_asm_label (disp);
11056 output_addr_const (file, disp);
11061 print_reg (base, 0, file);
11065 print_reg (index, 0, file);
11067 fprintf (file, ",%d", scale);
11073 rtx offset = NULL_RTX;
11077 /* Pull out the offset of a symbol; print any symbol itself. */
11078 if (GET_CODE (disp) == CONST
11079 && GET_CODE (XEXP (disp, 0)) == PLUS
11080 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11082 offset = XEXP (XEXP (disp, 0), 1);
11083 disp = gen_rtx_CONST (VOIDmode,
11084 XEXP (XEXP (disp, 0), 0));
11088 output_pic_addr_const (file, disp, 0);
11089 else if (GET_CODE (disp) == LABEL_REF)
11090 output_asm_label (disp);
11091 else if (CONST_INT_P (disp))
11094 output_addr_const (file, disp);
11100 print_reg (base, 0, file);
11103 if (INTVAL (offset) >= 0)
11105 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11109 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11116 print_reg (index, 0, file);
11118 fprintf (file, "*%d", scale);
11126 output_addr_const_extra (FILE *file, rtx x)
11130 if (GET_CODE (x) != UNSPEC)
11133 op = XVECEXP (x, 0, 0);
11134 switch (XINT (x, 1))
11136 case UNSPEC_GOTTPOFF:
11137 output_addr_const (file, op);
11138 /* FIXME: This might be @TPOFF in Sun ld. */
11139 fputs ("@GOTTPOFF", file);
11142 output_addr_const (file, op);
11143 fputs ("@TPOFF", file);
11145 case UNSPEC_NTPOFF:
11146 output_addr_const (file, op);
11148 fputs ("@TPOFF", file);
11150 fputs ("@NTPOFF", file);
11152 case UNSPEC_DTPOFF:
11153 output_addr_const (file, op);
11154 fputs ("@DTPOFF", file);
11156 case UNSPEC_GOTNTPOFF:
11157 output_addr_const (file, op);
11159 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11160 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11162 fputs ("@GOTNTPOFF", file);
11164 case UNSPEC_INDNTPOFF:
11165 output_addr_const (file, op);
11166 fputs ("@INDNTPOFF", file);
11169 case UNSPEC_MACHOPIC_OFFSET:
11170 output_addr_const (file, op);
11172 machopic_output_function_base_name (file);
11183 /* Split one or more DImode RTL references into pairs of SImode
11184 references. The RTL can be REG, offsettable MEM, integer constant, or
11185 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11186 split and "num" is its length. lo_half and hi_half are output arrays
11187 that parallel "operands". */
11190 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11194 rtx op = operands[num];
11196 /* simplify_subreg refuse to split volatile memory addresses,
11197 but we still have to handle it. */
11200 lo_half[num] = adjust_address (op, SImode, 0);
11201 hi_half[num] = adjust_address (op, SImode, 4);
11205 lo_half[num] = simplify_gen_subreg (SImode, op,
11206 GET_MODE (op) == VOIDmode
11207 ? DImode : GET_MODE (op), 0);
11208 hi_half[num] = simplify_gen_subreg (SImode, op,
11209 GET_MODE (op) == VOIDmode
11210 ? DImode : GET_MODE (op), 4);
11214 /* Split one or more TImode RTL references into pairs of DImode
11215 references. The RTL can be REG, offsettable MEM, integer constant, or
11216 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11217 split and "num" is its length. lo_half and hi_half are output arrays
11218 that parallel "operands". */
11221 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11225 rtx op = operands[num];
11227 /* simplify_subreg refuse to split volatile memory addresses, but we
11228 still have to handle it. */
11231 lo_half[num] = adjust_address (op, DImode, 0);
11232 hi_half[num] = adjust_address (op, DImode, 8);
11236 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11237 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11242 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11243 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11244 is the expression of the binary operation. The output may either be
11245 emitted here, or returned to the caller, like all output_* functions.
11247 There is no guarantee that the operands are the same mode, as they
11248 might be within FLOAT or FLOAT_EXTEND expressions. */
11250 #ifndef SYSV386_COMPAT
11251 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11252 wants to fix the assemblers because that causes incompatibility
11253 with gcc. No-one wants to fix gcc because that causes
11254 incompatibility with assemblers... You can use the option of
11255 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11256 #define SYSV386_COMPAT 1
11260 output_387_binary_op (rtx insn, rtx *operands)
11262 static char buf[40];
11265 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11267 #ifdef ENABLE_CHECKING
11268 /* Even if we do not want to check the inputs, this documents input
11269 constraints. Which helps in understanding the following code. */
11270 if (STACK_REG_P (operands[0])
11271 && ((REG_P (operands[1])
11272 && REGNO (operands[0]) == REGNO (operands[1])
11273 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11274 || (REG_P (operands[2])
11275 && REGNO (operands[0]) == REGNO (operands[2])
11276 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11277 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11280 gcc_assert (is_sse);
11283 switch (GET_CODE (operands[3]))
11286 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11287 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11295 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11296 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11304 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11305 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11313 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11314 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11322 gcc_unreachable ();
11329 strcpy (buf, ssep);
11330 if (GET_MODE (operands[0]) == SFmode)
11331 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11333 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11337 strcpy (buf, ssep + 1);
11338 if (GET_MODE (operands[0]) == SFmode)
11339 strcat (buf, "ss\t{%2, %0|%0, %2}");
11341 strcat (buf, "sd\t{%2, %0|%0, %2}");
11347 switch (GET_CODE (operands[3]))
11351 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11353 rtx temp = operands[2];
11354 operands[2] = operands[1];
11355 operands[1] = temp;
11358 /* know operands[0] == operands[1]. */
11360 if (MEM_P (operands[2]))
11366 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11368 if (STACK_TOP_P (operands[0]))
11369 /* How is it that we are storing to a dead operand[2]?
11370 Well, presumably operands[1] is dead too. We can't
11371 store the result to st(0) as st(0) gets popped on this
11372 instruction. Instead store to operands[2] (which I
11373 think has to be st(1)). st(1) will be popped later.
11374 gcc <= 2.8.1 didn't have this check and generated
11375 assembly code that the Unixware assembler rejected. */
11376 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11378 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11382 if (STACK_TOP_P (operands[0]))
11383 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11385 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11390 if (MEM_P (operands[1]))
11396 if (MEM_P (operands[2]))
11402 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11405 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11406 derived assemblers, confusingly reverse the direction of
11407 the operation for fsub{r} and fdiv{r} when the
11408 destination register is not st(0). The Intel assembler
11409 doesn't have this brain damage. Read !SYSV386_COMPAT to
11410 figure out what the hardware really does. */
11411 if (STACK_TOP_P (operands[0]))
11412 p = "{p\t%0, %2|rp\t%2, %0}";
11414 p = "{rp\t%2, %0|p\t%0, %2}";
11416 if (STACK_TOP_P (operands[0]))
11417 /* As above for fmul/fadd, we can't store to st(0). */
11418 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11420 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11425 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11428 if (STACK_TOP_P (operands[0]))
11429 p = "{rp\t%0, %1|p\t%1, %0}";
11431 p = "{p\t%1, %0|rp\t%0, %1}";
11433 if (STACK_TOP_P (operands[0]))
11434 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11436 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11441 if (STACK_TOP_P (operands[0]))
11443 if (STACK_TOP_P (operands[1]))
11444 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11446 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11449 else if (STACK_TOP_P (operands[1]))
11452 p = "{\t%1, %0|r\t%0, %1}";
11454 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11460 p = "{r\t%2, %0|\t%0, %2}";
11462 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11468 gcc_unreachable ();
11475 /* Return needed mode for entity in optimize_mode_switching pass. */
11478 ix86_mode_needed (int entity, rtx insn)
11480 enum attr_i387_cw mode;
11482 /* The mode UNINITIALIZED is used to store control word after a
11483 function call or ASM pattern. The mode ANY specify that function
11484 has no requirements on the control word and make no changes in the
11485 bits we are interested in. */
11488 || (NONJUMP_INSN_P (insn)
11489 && (asm_noperands (PATTERN (insn)) >= 0
11490 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11491 return I387_CW_UNINITIALIZED;
11493 if (recog_memoized (insn) < 0)
11494 return I387_CW_ANY;
11496 mode = get_attr_i387_cw (insn);
11501 if (mode == I387_CW_TRUNC)
11506 if (mode == I387_CW_FLOOR)
11511 if (mode == I387_CW_CEIL)
11516 if (mode == I387_CW_MASK_PM)
11521 gcc_unreachable ();
11524 return I387_CW_ANY;
11527 /* Output code to initialize control word copies used by trunc?f?i and
11528 rounding patterns. CURRENT_MODE is set to current control word,
11529 while NEW_MODE is set to new control word. */
11532 emit_i387_cw_initialization (int mode)
11534 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11537 enum ix86_stack_slot slot;
11539 rtx reg = gen_reg_rtx (HImode);
11541 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11542 emit_move_insn (reg, copy_rtx (stored_mode));
11544 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11545 || optimize_function_for_size_p (cfun))
11549 case I387_CW_TRUNC:
11550 /* round toward zero (truncate) */
11551 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11552 slot = SLOT_CW_TRUNC;
11555 case I387_CW_FLOOR:
11556 /* round down toward -oo */
11557 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11558 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11559 slot = SLOT_CW_FLOOR;
11563 /* round up toward +oo */
11564 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11565 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11566 slot = SLOT_CW_CEIL;
11569 case I387_CW_MASK_PM:
11570 /* mask precision exception for nearbyint() */
11571 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11572 slot = SLOT_CW_MASK_PM;
11576 gcc_unreachable ();
11583 case I387_CW_TRUNC:
11584 /* round toward zero (truncate) */
11585 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
11586 slot = SLOT_CW_TRUNC;
11589 case I387_CW_FLOOR:
11590 /* round down toward -oo */
11591 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
11592 slot = SLOT_CW_FLOOR;
11596 /* round up toward +oo */
11597 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
11598 slot = SLOT_CW_CEIL;
11601 case I387_CW_MASK_PM:
11602 /* mask precision exception for nearbyint() */
11603 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11604 slot = SLOT_CW_MASK_PM;
11608 gcc_unreachable ();
11612 gcc_assert (slot < MAX_386_STACK_LOCALS);
11614 new_mode = assign_386_stack_local (HImode, slot);
11615 emit_move_insn (new_mode, reg);
11618 /* Output code for INSN to convert a float to a signed int. OPERANDS
11619 are the insn operands. The output may be [HSD]Imode and the input
11620 operand may be [SDX]Fmode. */
11623 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
11625 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11626 int dimode_p = GET_MODE (operands[0]) == DImode;
11627 int round_mode = get_attr_i387_cw (insn);
11629 /* Jump through a hoop or two for DImode, since the hardware has no
11630 non-popping instruction. We used to do this a different way, but
11631 that was somewhat fragile and broke with post-reload splitters. */
11632 if ((dimode_p || fisttp) && !stack_top_dies)
11633 output_asm_insn ("fld\t%y1", operands);
11635 gcc_assert (STACK_TOP_P (operands[1]));
11636 gcc_assert (MEM_P (operands[0]));
11637 gcc_assert (GET_MODE (operands[1]) != TFmode);
11640 output_asm_insn ("fisttp%z0\t%0", operands);
11643 if (round_mode != I387_CW_ANY)
11644 output_asm_insn ("fldcw\t%3", operands);
11645 if (stack_top_dies || dimode_p)
11646 output_asm_insn ("fistp%z0\t%0", operands);
11648 output_asm_insn ("fist%z0\t%0", operands);
11649 if (round_mode != I387_CW_ANY)
11650 output_asm_insn ("fldcw\t%2", operands);
11656 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11657 have the values zero or one, indicates the ffreep insn's operand
11658 from the OPERANDS array. */
11660 static const char *
11661 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
11663 if (TARGET_USE_FFREEP)
11664 #if HAVE_AS_IX86_FFREEP
11665 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
11668 static char retval[] = ".word\t0xc_df";
11669 int regno = REGNO (operands[opno]);
11671 gcc_assert (FP_REGNO_P (regno));
11673 retval[9] = '0' + (regno - FIRST_STACK_REG);
11678 return opno ? "fstp\t%y1" : "fstp\t%y0";
11682 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11683 should be used. UNORDERED_P is true when fucom should be used. */
11686 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
11688 int stack_top_dies;
11689 rtx cmp_op0, cmp_op1;
11690 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
11694 cmp_op0 = operands[0];
11695 cmp_op1 = operands[1];
11699 cmp_op0 = operands[1];
11700 cmp_op1 = operands[2];
11705 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
11706 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
11707 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
11708 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
11710 if (GET_MODE (operands[0]) == SFmode)
11712 return &ucomiss[TARGET_AVX ? 0 : 1];
11714 return &comiss[TARGET_AVX ? 0 : 1];
11717 return &ucomisd[TARGET_AVX ? 0 : 1];
11719 return &comisd[TARGET_AVX ? 0 : 1];
11722 gcc_assert (STACK_TOP_P (cmp_op0));
11724 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11726 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
11728 if (stack_top_dies)
11730 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
11731 return output_387_ffreep (operands, 1);
11734 return "ftst\n\tfnstsw\t%0";
11737 if (STACK_REG_P (cmp_op1)
11739 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
11740 && REGNO (cmp_op1) != FIRST_STACK_REG)
11742 /* If both the top of the 387 stack dies, and the other operand
11743 is also a stack register that dies, then this must be a
11744 `fcompp' float compare */
11748 /* There is no double popping fcomi variant. Fortunately,
11749 eflags is immune from the fstp's cc clobbering. */
11751 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
11753 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
11754 return output_387_ffreep (operands, 0);
11759 return "fucompp\n\tfnstsw\t%0";
11761 return "fcompp\n\tfnstsw\t%0";
11766 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
11768 static const char * const alt[16] =
11770 "fcom%z2\t%y2\n\tfnstsw\t%0",
11771 "fcomp%z2\t%y2\n\tfnstsw\t%0",
11772 "fucom%z2\t%y2\n\tfnstsw\t%0",
11773 "fucomp%z2\t%y2\n\tfnstsw\t%0",
11775 "ficom%z2\t%y2\n\tfnstsw\t%0",
11776 "ficomp%z2\t%y2\n\tfnstsw\t%0",
11780 "fcomi\t{%y1, %0|%0, %y1}",
11781 "fcomip\t{%y1, %0|%0, %y1}",
11782 "fucomi\t{%y1, %0|%0, %y1}",
11783 "fucomip\t{%y1, %0|%0, %y1}",
11794 mask = eflags_p << 3;
11795 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
11796 mask |= unordered_p << 1;
11797 mask |= stack_top_dies;
11799 gcc_assert (mask < 16);
11808 ix86_output_addr_vec_elt (FILE *file, int value)
11810 const char *directive = ASM_LONG;
11814 directive = ASM_QUAD;
11816 gcc_assert (!TARGET_64BIT);
11819 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
11823 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
11825 const char *directive = ASM_LONG;
11828 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
11829 directive = ASM_QUAD;
11831 gcc_assert (!TARGET_64BIT);
11833 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
11834 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
11835 fprintf (file, "%s%s%d-%s%d\n",
11836 directive, LPREFIX, value, LPREFIX, rel);
11837 else if (HAVE_AS_GOTOFF_IN_DATA)
11838 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
11840 else if (TARGET_MACHO)
11842 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
11843 machopic_output_function_base_name (file);
11844 fprintf(file, "\n");
11848 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
11849 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
11852 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
11856 ix86_expand_clear (rtx dest)
11860 /* We play register width games, which are only valid after reload. */
11861 gcc_assert (reload_completed);
11863 /* Avoid HImode and its attendant prefix byte. */
11864 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
11865 dest = gen_rtx_REG (SImode, REGNO (dest));
11866 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
11868 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
11869 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
11871 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11872 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
11878 /* X is an unchanging MEM. If it is a constant pool reference, return
11879 the constant pool rtx, else NULL. */
11882 maybe_get_pool_constant (rtx x)
11884 x = ix86_delegitimize_address (XEXP (x, 0));
11886 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
11887 return get_pool_constant (x);
11893 ix86_expand_move (enum machine_mode mode, rtx operands[])
11896 enum tls_model model;
11901 if (GET_CODE (op1) == SYMBOL_REF)
11903 model = SYMBOL_REF_TLS_MODEL (op1);
11906 op1 = legitimize_tls_address (op1, model, true);
11907 op1 = force_operand (op1, op0);
11911 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
11912 && SYMBOL_REF_DLLIMPORT_P (op1))
11913 op1 = legitimize_dllimport_symbol (op1, false);
11915 else if (GET_CODE (op1) == CONST
11916 && GET_CODE (XEXP (op1, 0)) == PLUS
11917 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
11919 rtx addend = XEXP (XEXP (op1, 0), 1);
11920 rtx symbol = XEXP (XEXP (op1, 0), 0);
11923 model = SYMBOL_REF_TLS_MODEL (symbol);
11925 tmp = legitimize_tls_address (symbol, model, true);
11926 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
11927 && SYMBOL_REF_DLLIMPORT_P (symbol))
11928 tmp = legitimize_dllimport_symbol (symbol, true);
11932 tmp = force_operand (tmp, NULL);
11933 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
11934 op0, 1, OPTAB_DIRECT);
11940 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
11942 if (TARGET_MACHO && !TARGET_64BIT)
11947 rtx temp = ((reload_in_progress
11948 || ((op0 && REG_P (op0))
11950 ? op0 : gen_reg_rtx (Pmode));
11951 op1 = machopic_indirect_data_reference (op1, temp);
11952 op1 = machopic_legitimize_pic_address (op1, mode,
11953 temp == op1 ? 0 : temp);
11955 else if (MACHOPIC_INDIRECT)
11956 op1 = machopic_indirect_data_reference (op1, 0);
11964 op1 = force_reg (Pmode, op1);
11965 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
11967 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
11968 op1 = legitimize_pic_address (op1, reg);
11977 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
11978 || !push_operand (op0, mode))
11980 op1 = force_reg (mode, op1);
11982 if (push_operand (op0, mode)
11983 && ! general_no_elim_operand (op1, mode))
11984 op1 = copy_to_mode_reg (mode, op1);
11986 /* Force large constants in 64bit compilation into register
11987 to get them CSEed. */
11988 if (can_create_pseudo_p ()
11989 && (mode == DImode) && TARGET_64BIT
11990 && immediate_operand (op1, mode)
11991 && !x86_64_zext_immediate_operand (op1, VOIDmode)
11992 && !register_operand (op0, mode)
11994 op1 = copy_to_mode_reg (mode, op1);
11996 if (can_create_pseudo_p ()
11997 && FLOAT_MODE_P (mode)
11998 && GET_CODE (op1) == CONST_DOUBLE)
12000 /* If we are loading a floating point constant to a register,
12001 force the value to memory now, since we'll get better code
12002 out the back end. */
12004 op1 = validize_mem (force_const_mem (mode, op1));
12005 if (!register_operand (op0, mode))
12007 rtx temp = gen_reg_rtx (mode);
12008 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12009 emit_move_insn (op0, temp);
12015 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12019 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12021 rtx op0 = operands[0], op1 = operands[1];
12022 unsigned int align = GET_MODE_ALIGNMENT (mode);
12024 /* Force constants other than zero into memory. We do not know how
12025 the instructions used to build constants modify the upper 64 bits
12026 of the register, once we have that information we may be able
12027 to handle some of them more efficiently. */
12028 if (can_create_pseudo_p ()
12029 && register_operand (op0, mode)
12030 && (CONSTANT_P (op1)
12031 || (GET_CODE (op1) == SUBREG
12032 && CONSTANT_P (SUBREG_REG (op1))))
12033 && standard_sse_constant_p (op1) <= 0)
12034 op1 = validize_mem (force_const_mem (mode, op1));
12036 /* We need to check memory alignment for SSE mode since attribute
12037 can make operands unaligned. */
12038 if (can_create_pseudo_p ()
12039 && SSE_REG_MODE_P (mode)
12040 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12041 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12045 /* ix86_expand_vector_move_misalign() does not like constants ... */
12046 if (CONSTANT_P (op1)
12047 || (GET_CODE (op1) == SUBREG
12048 && CONSTANT_P (SUBREG_REG (op1))))
12049 op1 = validize_mem (force_const_mem (mode, op1));
12051 /* ... nor both arguments in memory. */
12052 if (!register_operand (op0, mode)
12053 && !register_operand (op1, mode))
12054 op1 = force_reg (mode, op1);
12056 tmp[0] = op0; tmp[1] = op1;
12057 ix86_expand_vector_move_misalign (mode, tmp);
12061 /* Make operand1 a register if it isn't already. */
12062 if (can_create_pseudo_p ()
12063 && !register_operand (op0, mode)
12064 && !register_operand (op1, mode))
12066 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12070 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12073 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12074 straight to ix86_expand_vector_move. */
12075 /* Code generation for scalar reg-reg moves of single and double precision data:
12076 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12080 if (x86_sse_partial_reg_dependency == true)
12085 Code generation for scalar loads of double precision data:
12086 if (x86_sse_split_regs == true)
12087 movlpd mem, reg (gas syntax)
12091 Code generation for unaligned packed loads of single precision data
12092 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12093 if (x86_sse_unaligned_move_optimal)
12096 if (x86_sse_partial_reg_dependency == true)
12108 Code generation for unaligned packed loads of double precision data
12109 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12110 if (x86_sse_unaligned_move_optimal)
12113 if (x86_sse_split_regs == true)
12126 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12135 switch (GET_MODE_CLASS (mode))
12137 case MODE_VECTOR_INT:
12139 switch (GET_MODE_SIZE (mode))
12142 op0 = gen_lowpart (V16QImode, op0);
12143 op1 = gen_lowpart (V16QImode, op1);
12144 emit_insn (gen_avx_movdqu (op0, op1));
12147 op0 = gen_lowpart (V32QImode, op0);
12148 op1 = gen_lowpart (V32QImode, op1);
12149 emit_insn (gen_avx_movdqu256 (op0, op1));
12152 gcc_unreachable ();
12155 case MODE_VECTOR_FLOAT:
12156 op0 = gen_lowpart (mode, op0);
12157 op1 = gen_lowpart (mode, op1);
12162 emit_insn (gen_avx_movups (op0, op1));
12165 emit_insn (gen_avx_movups256 (op0, op1));
12168 emit_insn (gen_avx_movupd (op0, op1));
12171 emit_insn (gen_avx_movupd256 (op0, op1));
12174 gcc_unreachable ();
12179 gcc_unreachable ();
12187 /* If we're optimizing for size, movups is the smallest. */
12188 if (optimize_insn_for_size_p ())
12190 op0 = gen_lowpart (V4SFmode, op0);
12191 op1 = gen_lowpart (V4SFmode, op1);
12192 emit_insn (gen_sse_movups (op0, op1));
12196 /* ??? If we have typed data, then it would appear that using
12197 movdqu is the only way to get unaligned data loaded with
12199 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12201 op0 = gen_lowpart (V16QImode, op0);
12202 op1 = gen_lowpart (V16QImode, op1);
12203 emit_insn (gen_sse2_movdqu (op0, op1));
12207 if (TARGET_SSE2 && mode == V2DFmode)
12211 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12213 op0 = gen_lowpart (V2DFmode, op0);
12214 op1 = gen_lowpart (V2DFmode, op1);
12215 emit_insn (gen_sse2_movupd (op0, op1));
12219 /* When SSE registers are split into halves, we can avoid
12220 writing to the top half twice. */
12221 if (TARGET_SSE_SPLIT_REGS)
12223 emit_clobber (op0);
12228 /* ??? Not sure about the best option for the Intel chips.
12229 The following would seem to satisfy; the register is
12230 entirely cleared, breaking the dependency chain. We
12231 then store to the upper half, with a dependency depth
12232 of one. A rumor has it that Intel recommends two movsd
12233 followed by an unpacklpd, but this is unconfirmed. And
12234 given that the dependency depth of the unpacklpd would
12235 still be one, I'm not sure why this would be better. */
12236 zero = CONST0_RTX (V2DFmode);
12239 m = adjust_address (op1, DFmode, 0);
12240 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12241 m = adjust_address (op1, DFmode, 8);
12242 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12246 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12248 op0 = gen_lowpart (V4SFmode, op0);
12249 op1 = gen_lowpart (V4SFmode, op1);
12250 emit_insn (gen_sse_movups (op0, op1));
12254 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12255 emit_move_insn (op0, CONST0_RTX (mode));
12257 emit_clobber (op0);
12259 if (mode != V4SFmode)
12260 op0 = gen_lowpart (V4SFmode, op0);
12261 m = adjust_address (op1, V2SFmode, 0);
12262 emit_insn (gen_sse_loadlps (op0, op0, m));
12263 m = adjust_address (op1, V2SFmode, 8);
12264 emit_insn (gen_sse_loadhps (op0, op0, m));
12267 else if (MEM_P (op0))
12269 /* If we're optimizing for size, movups is the smallest. */
12270 if (optimize_insn_for_size_p ())
12272 op0 = gen_lowpart (V4SFmode, op0);
12273 op1 = gen_lowpart (V4SFmode, op1);
12274 emit_insn (gen_sse_movups (op0, op1));
12278 /* ??? Similar to above, only less clear because of quote
12279 typeless stores unquote. */
12280 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12281 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12283 op0 = gen_lowpart (V16QImode, op0);
12284 op1 = gen_lowpart (V16QImode, op1);
12285 emit_insn (gen_sse2_movdqu (op0, op1));
12289 if (TARGET_SSE2 && mode == V2DFmode)
12291 m = adjust_address (op0, DFmode, 0);
12292 emit_insn (gen_sse2_storelpd (m, op1));
12293 m = adjust_address (op0, DFmode, 8);
12294 emit_insn (gen_sse2_storehpd (m, op1));
12298 if (mode != V4SFmode)
12299 op1 = gen_lowpart (V4SFmode, op1);
12300 m = adjust_address (op0, V2SFmode, 0);
12301 emit_insn (gen_sse_storelps (m, op1));
12302 m = adjust_address (op0, V2SFmode, 8);
12303 emit_insn (gen_sse_storehps (m, op1));
12307 gcc_unreachable ();
12310 /* Expand a push in MODE. This is some mode for which we do not support
12311 proper push instructions, at least from the registers that we expect
12312 the value to live in. */
12315 ix86_expand_push (enum machine_mode mode, rtx x)
12319 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12320 GEN_INT (-GET_MODE_SIZE (mode)),
12321 stack_pointer_rtx, 1, OPTAB_DIRECT);
12322 if (tmp != stack_pointer_rtx)
12323 emit_move_insn (stack_pointer_rtx, tmp);
12325 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12326 emit_move_insn (tmp, x);
12329 /* Helper function of ix86_fixup_binary_operands to canonicalize
12330 operand order. Returns true if the operands should be swapped. */
12333 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12336 rtx dst = operands[0];
12337 rtx src1 = operands[1];
12338 rtx src2 = operands[2];
12340 /* If the operation is not commutative, we can't do anything. */
12341 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12344 /* Highest priority is that src1 should match dst. */
12345 if (rtx_equal_p (dst, src1))
12347 if (rtx_equal_p (dst, src2))
12350 /* Next highest priority is that immediate constants come second. */
12351 if (immediate_operand (src2, mode))
12353 if (immediate_operand (src1, mode))
12356 /* Lowest priority is that memory references should come second. */
12366 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12367 destination to use for the operation. If different from the true
12368 destination in operands[0], a copy operation will be required. */
12371 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12374 rtx dst = operands[0];
12375 rtx src1 = operands[1];
12376 rtx src2 = operands[2];
12378 /* Canonicalize operand order. */
12379 if (ix86_swap_binary_operands_p (code, mode, operands))
12383 /* It is invalid to swap operands of different modes. */
12384 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12391 /* Both source operands cannot be in memory. */
12392 if (MEM_P (src1) && MEM_P (src2))
12394 /* Optimization: Only read from memory once. */
12395 if (rtx_equal_p (src1, src2))
12397 src2 = force_reg (mode, src2);
12401 src2 = force_reg (mode, src2);
12404 /* If the destination is memory, and we do not have matching source
12405 operands, do things in registers. */
12406 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12407 dst = gen_reg_rtx (mode);
12409 /* Source 1 cannot be a constant. */
12410 if (CONSTANT_P (src1))
12411 src1 = force_reg (mode, src1);
12413 /* Source 1 cannot be a non-matching memory. */
12414 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12415 src1 = force_reg (mode, src1);
12417 operands[1] = src1;
12418 operands[2] = src2;
12422 /* Similarly, but assume that the destination has already been
12423 set up properly. */
12426 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12427 enum machine_mode mode, rtx operands[])
12429 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12430 gcc_assert (dst == operands[0]);
12433 /* Attempt to expand a binary operator. Make the expansion closer to the
12434 actual machine, then just general_operand, which will allow 3 separate
12435 memory references (one output, two input) in a single insn. */
12438 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12441 rtx src1, src2, dst, op, clob;
12443 dst = ix86_fixup_binary_operands (code, mode, operands);
12444 src1 = operands[1];
12445 src2 = operands[2];
12447 /* Emit the instruction. */
12449 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12450 if (reload_in_progress)
12452 /* Reload doesn't know about the flags register, and doesn't know that
12453 it doesn't want to clobber it. We can only do this with PLUS. */
12454 gcc_assert (code == PLUS);
12459 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12460 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12463 /* Fix up the destination if needed. */
12464 if (dst != operands[0])
12465 emit_move_insn (operands[0], dst);
12468 /* Return TRUE or FALSE depending on whether the binary operator meets the
12469 appropriate constraints. */
12472 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12475 rtx dst = operands[0];
12476 rtx src1 = operands[1];
12477 rtx src2 = operands[2];
12479 /* Both source operands cannot be in memory. */
12480 if (MEM_P (src1) && MEM_P (src2))
12483 /* Canonicalize operand order for commutative operators. */
12484 if (ix86_swap_binary_operands_p (code, mode, operands))
12491 /* If the destination is memory, we must have a matching source operand. */
12492 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12495 /* Source 1 cannot be a constant. */
12496 if (CONSTANT_P (src1))
12499 /* Source 1 cannot be a non-matching memory. */
12500 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12506 /* Attempt to expand a unary operator. Make the expansion closer to the
12507 actual machine, then just general_operand, which will allow 2 separate
12508 memory references (one output, one input) in a single insn. */
12511 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12514 int matching_memory;
12515 rtx src, dst, op, clob;
12520 /* If the destination is memory, and we do not have matching source
12521 operands, do things in registers. */
12522 matching_memory = 0;
12525 if (rtx_equal_p (dst, src))
12526 matching_memory = 1;
12528 dst = gen_reg_rtx (mode);
12531 /* When source operand is memory, destination must match. */
12532 if (MEM_P (src) && !matching_memory)
12533 src = force_reg (mode, src);
12535 /* Emit the instruction. */
12537 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12538 if (reload_in_progress || code == NOT)
12540 /* Reload doesn't know about the flags register, and doesn't know that
12541 it doesn't want to clobber it. */
12542 gcc_assert (code == NOT);
12547 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12548 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12551 /* Fix up the destination if needed. */
12552 if (dst != operands[0])
12553 emit_move_insn (operands[0], dst);
12556 /* Return TRUE or FALSE depending on whether the unary operator meets the
12557 appropriate constraints. */
12560 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12561 enum machine_mode mode ATTRIBUTE_UNUSED,
12562 rtx operands[2] ATTRIBUTE_UNUSED)
12564 /* If one of operands is memory, source and destination must match. */
12565 if ((MEM_P (operands[0])
12566 || MEM_P (operands[1]))
12567 && ! rtx_equal_p (operands[0], operands[1]))
12572 /* Post-reload splitter for converting an SF or DFmode value in an
12573 SSE register into an unsigned SImode. */
12576 ix86_split_convert_uns_si_sse (rtx operands[])
12578 enum machine_mode vecmode;
12579 rtx value, large, zero_or_two31, input, two31, x;
12581 large = operands[1];
12582 zero_or_two31 = operands[2];
12583 input = operands[3];
12584 two31 = operands[4];
12585 vecmode = GET_MODE (large);
12586 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
12588 /* Load up the value into the low element. We must ensure that the other
12589 elements are valid floats -- zero is the easiest such value. */
12592 if (vecmode == V4SFmode)
12593 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
12595 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
12599 input = gen_rtx_REG (vecmode, REGNO (input));
12600 emit_move_insn (value, CONST0_RTX (vecmode));
12601 if (vecmode == V4SFmode)
12602 emit_insn (gen_sse_movss (value, value, input));
12604 emit_insn (gen_sse2_movsd (value, value, input));
12607 emit_move_insn (large, two31);
12608 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
12610 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
12611 emit_insn (gen_rtx_SET (VOIDmode, large, x));
12613 x = gen_rtx_AND (vecmode, zero_or_two31, large);
12614 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
12616 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
12617 emit_insn (gen_rtx_SET (VOIDmode, value, x));
12619 large = gen_rtx_REG (V4SImode, REGNO (large));
12620 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
12622 x = gen_rtx_REG (V4SImode, REGNO (value));
12623 if (vecmode == V4SFmode)
12624 emit_insn (gen_sse2_cvttps2dq (x, value));
12626 emit_insn (gen_sse2_cvttpd2dq (x, value));
12629 emit_insn (gen_xorv4si3 (value, value, large));
12632 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12633 Expects the 64-bit DImode to be supplied in a pair of integral
12634 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12635 -mfpmath=sse, !optimize_size only. */
12638 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
12640 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
12641 rtx int_xmm, fp_xmm;
12642 rtx biases, exponents;
12645 int_xmm = gen_reg_rtx (V4SImode);
12646 if (TARGET_INTER_UNIT_MOVES)
12647 emit_insn (gen_movdi_to_sse (int_xmm, input));
12648 else if (TARGET_SSE_SPLIT_REGS)
12650 emit_clobber (int_xmm);
12651 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
12655 x = gen_reg_rtx (V2DImode);
12656 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
12657 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
12660 x = gen_rtx_CONST_VECTOR (V4SImode,
12661 gen_rtvec (4, GEN_INT (0x43300000UL),
12662 GEN_INT (0x45300000UL),
12663 const0_rtx, const0_rtx));
12664 exponents = validize_mem (force_const_mem (V4SImode, x));
12666 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12667 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
12669 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12670 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12671 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12672 (0x1.0p84 + double(fp_value_hi_xmm)).
12673 Note these exponents differ by 32. */
12675 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
12677 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12678 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12679 real_ldexp (&bias_lo_rvt, &dconst1, 52);
12680 real_ldexp (&bias_hi_rvt, &dconst1, 84);
12681 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
12682 x = const_double_from_real_value (bias_hi_rvt, DFmode);
12683 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
12684 biases = validize_mem (force_const_mem (V2DFmode, biases));
12685 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
12687 /* Add the upper and lower DFmode values together. */
12689 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
12692 x = copy_to_mode_reg (V2DFmode, fp_xmm);
12693 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
12694 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
12697 ix86_expand_vector_extract (false, target, fp_xmm, 0);
12700 /* Not used, but eases macroization of patterns. */
12702 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
12703 rtx input ATTRIBUTE_UNUSED)
12705 gcc_unreachable ();
12708 /* Convert an unsigned SImode value into a DFmode. Only currently used
12709 for SSE, but applicable anywhere. */
12712 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
12714 REAL_VALUE_TYPE TWO31r;
12717 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
12718 NULL, 1, OPTAB_DIRECT);
12720 fp = gen_reg_rtx (DFmode);
12721 emit_insn (gen_floatsidf2 (fp, x));
12723 real_ldexp (&TWO31r, &dconst1, 31);
12724 x = const_double_from_real_value (TWO31r, DFmode);
12726 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
12728 emit_move_insn (target, x);
12731 /* Convert a signed DImode value into a DFmode. Only used for SSE in
12732 32-bit mode; otherwise we have a direct convert instruction. */
12735 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
12737 REAL_VALUE_TYPE TWO32r;
12738 rtx fp_lo, fp_hi, x;
12740 fp_lo = gen_reg_rtx (DFmode);
12741 fp_hi = gen_reg_rtx (DFmode);
12743 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
12745 real_ldexp (&TWO32r, &dconst1, 32);
12746 x = const_double_from_real_value (TWO32r, DFmode);
12747 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
12749 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
12751 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
12754 emit_move_insn (target, x);
12757 /* Convert an unsigned SImode value into a SFmode, using only SSE.
12758 For x86_32, -mfpmath=sse, !optimize_size only. */
12760 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
12762 REAL_VALUE_TYPE ONE16r;
12763 rtx fp_hi, fp_lo, int_hi, int_lo, x;
12765 real_ldexp (&ONE16r, &dconst1, 16);
12766 x = const_double_from_real_value (ONE16r, SFmode);
12767 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
12768 NULL, 0, OPTAB_DIRECT);
12769 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
12770 NULL, 0, OPTAB_DIRECT);
12771 fp_hi = gen_reg_rtx (SFmode);
12772 fp_lo = gen_reg_rtx (SFmode);
12773 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
12774 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
12775 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
12777 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
12779 if (!rtx_equal_p (target, fp_hi))
12780 emit_move_insn (target, fp_hi);
12783 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
12784 then replicate the value for all elements of the vector
12788 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
12795 v = gen_rtvec (4, value, value, value, value);
12796 return gen_rtx_CONST_VECTOR (V4SImode, v);
12800 v = gen_rtvec (2, value, value);
12801 return gen_rtx_CONST_VECTOR (V2DImode, v);
12805 v = gen_rtvec (4, value, value, value, value);
12807 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
12808 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
12809 return gen_rtx_CONST_VECTOR (V4SFmode, v);
12813 v = gen_rtvec (2, value, value);
12815 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
12816 return gen_rtx_CONST_VECTOR (V2DFmode, v);
12819 gcc_unreachable ();
12823 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
12824 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
12825 for an SSE register. If VECT is true, then replicate the mask for
12826 all elements of the vector register. If INVERT is true, then create
12827 a mask excluding the sign bit. */
12830 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
12832 enum machine_mode vec_mode, imode;
12833 HOST_WIDE_INT hi, lo;
12838 /* Find the sign bit, sign extended to 2*HWI. */
12844 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
12845 lo = 0x80000000, hi = lo < 0;
12851 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
12852 if (HOST_BITS_PER_WIDE_INT >= 64)
12853 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
12855 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
12860 vec_mode = VOIDmode;
12861 if (HOST_BITS_PER_WIDE_INT >= 64)
12864 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
12871 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
12875 lo = ~lo, hi = ~hi;
12881 mask = immed_double_const (lo, hi, imode);
12883 vec = gen_rtvec (2, v, mask);
12884 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
12885 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
12892 gcc_unreachable ();
12896 lo = ~lo, hi = ~hi;
12898 /* Force this value into the low part of a fp vector constant. */
12899 mask = immed_double_const (lo, hi, imode);
12900 mask = gen_lowpart (mode, mask);
12902 if (vec_mode == VOIDmode)
12903 return force_reg (mode, mask);
12905 v = ix86_build_const_vector (mode, vect, mask);
12906 return force_reg (vec_mode, v);
12909 /* Generate code for floating point ABS or NEG. */
12912 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
12915 rtx mask, set, use, clob, dst, src;
12916 bool use_sse = false;
12917 bool vector_mode = VECTOR_MODE_P (mode);
12918 enum machine_mode elt_mode = mode;
12922 elt_mode = GET_MODE_INNER (mode);
12925 else if (mode == TFmode)
12927 else if (TARGET_SSE_MATH)
12928 use_sse = SSE_FLOAT_MODE_P (mode);
12930 /* NEG and ABS performed with SSE use bitwise mask operations.
12931 Create the appropriate mask now. */
12933 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
12942 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
12943 set = gen_rtx_SET (VOIDmode, dst, set);
12948 set = gen_rtx_fmt_e (code, mode, src);
12949 set = gen_rtx_SET (VOIDmode, dst, set);
12952 use = gen_rtx_USE (VOIDmode, mask);
12953 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12954 emit_insn (gen_rtx_PARALLEL (VOIDmode,
12955 gen_rtvec (3, set, use, clob)));
12962 /* Expand a copysign operation. Special case operand 0 being a constant. */
12965 ix86_expand_copysign (rtx operands[])
12967 enum machine_mode mode;
12968 rtx dest, op0, op1, mask, nmask;
12970 dest = operands[0];
12974 mode = GET_MODE (dest);
12976 if (GET_CODE (op0) == CONST_DOUBLE)
12978 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
12980 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
12981 op0 = simplify_unary_operation (ABS, mode, op0, mode);
12983 if (mode == SFmode || mode == DFmode)
12985 enum machine_mode vmode;
12987 vmode = mode == SFmode ? V4SFmode : V2DFmode;
12989 if (op0 == CONST0_RTX (mode))
12990 op0 = CONST0_RTX (vmode);
12995 if (mode == SFmode)
12996 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
12997 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
12999 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13001 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13004 else if (op0 != CONST0_RTX (mode))
13005 op0 = force_reg (mode, op0);
13007 mask = ix86_build_signbit_mask (mode, 0, 0);
13009 if (mode == SFmode)
13010 copysign_insn = gen_copysignsf3_const;
13011 else if (mode == DFmode)
13012 copysign_insn = gen_copysigndf3_const;
13014 copysign_insn = gen_copysigntf3_const;
13016 emit_insn (copysign_insn (dest, op0, op1, mask));
13020 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13022 nmask = ix86_build_signbit_mask (mode, 0, 1);
13023 mask = ix86_build_signbit_mask (mode, 0, 0);
13025 if (mode == SFmode)
13026 copysign_insn = gen_copysignsf3_var;
13027 else if (mode == DFmode)
13028 copysign_insn = gen_copysigndf3_var;
13030 copysign_insn = gen_copysigntf3_var;
13032 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13036 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13037 be a constant, and so has already been expanded into a vector constant. */
13040 ix86_split_copysign_const (rtx operands[])
13042 enum machine_mode mode, vmode;
13043 rtx dest, op0, op1, mask, x;
13045 dest = operands[0];
13048 mask = operands[3];
13050 mode = GET_MODE (dest);
13051 vmode = GET_MODE (mask);
13053 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13054 x = gen_rtx_AND (vmode, dest, mask);
13055 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13057 if (op0 != CONST0_RTX (vmode))
13059 x = gen_rtx_IOR (vmode, dest, op0);
13060 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13064 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13065 so we have to do two masks. */
13068 ix86_split_copysign_var (rtx operands[])
13070 enum machine_mode mode, vmode;
13071 rtx dest, scratch, op0, op1, mask, nmask, x;
13073 dest = operands[0];
13074 scratch = operands[1];
13077 nmask = operands[4];
13078 mask = operands[5];
13080 mode = GET_MODE (dest);
13081 vmode = GET_MODE (mask);
13083 if (rtx_equal_p (op0, op1))
13085 /* Shouldn't happen often (it's useless, obviously), but when it does
13086 we'd generate incorrect code if we continue below. */
13087 emit_move_insn (dest, op0);
13091 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13093 gcc_assert (REGNO (op1) == REGNO (scratch));
13095 x = gen_rtx_AND (vmode, scratch, mask);
13096 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13099 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13100 x = gen_rtx_NOT (vmode, dest);
13101 x = gen_rtx_AND (vmode, x, op0);
13102 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13106 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13108 x = gen_rtx_AND (vmode, scratch, mask);
13110 else /* alternative 2,4 */
13112 gcc_assert (REGNO (mask) == REGNO (scratch));
13113 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13114 x = gen_rtx_AND (vmode, scratch, op1);
13116 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13118 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13120 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13121 x = gen_rtx_AND (vmode, dest, nmask);
13123 else /* alternative 3,4 */
13125 gcc_assert (REGNO (nmask) == REGNO (dest));
13127 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13128 x = gen_rtx_AND (vmode, dest, op0);
13130 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13133 x = gen_rtx_IOR (vmode, dest, scratch);
13134 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13137 /* Return TRUE or FALSE depending on whether the first SET in INSN
13138 has source and destination with matching CC modes, and that the
13139 CC mode is at least as constrained as REQ_MODE. */
13142 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13145 enum machine_mode set_mode;
13147 set = PATTERN (insn);
13148 if (GET_CODE (set) == PARALLEL)
13149 set = XVECEXP (set, 0, 0);
13150 gcc_assert (GET_CODE (set) == SET);
13151 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13153 set_mode = GET_MODE (SET_DEST (set));
13157 if (req_mode != CCNOmode
13158 && (req_mode != CCmode
13159 || XEXP (SET_SRC (set), 1) != const0_rtx))
13163 if (req_mode == CCGCmode)
13167 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13171 if (req_mode == CCZmode)
13182 gcc_unreachable ();
13185 return (GET_MODE (SET_SRC (set)) == set_mode);
13188 /* Generate insn patterns to do an integer compare of OPERANDS. */
13191 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13193 enum machine_mode cmpmode;
13196 cmpmode = SELECT_CC_MODE (code, op0, op1);
13197 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13199 /* This is very simple, but making the interface the same as in the
13200 FP case makes the rest of the code easier. */
13201 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13202 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13204 /* Return the test that should be put into the flags user, i.e.
13205 the bcc, scc, or cmov instruction. */
13206 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13209 /* Figure out whether to use ordered or unordered fp comparisons.
13210 Return the appropriate mode to use. */
13213 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13215 /* ??? In order to make all comparisons reversible, we do all comparisons
13216 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13217 all forms trapping and nontrapping comparisons, we can make inequality
13218 comparisons trapping again, since it results in better code when using
13219 FCOM based compares. */
13220 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13224 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13226 enum machine_mode mode = GET_MODE (op0);
13228 if (SCALAR_FLOAT_MODE_P (mode))
13230 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13231 return ix86_fp_compare_mode (code);
13236 /* Only zero flag is needed. */
13237 case EQ: /* ZF=0 */
13238 case NE: /* ZF!=0 */
13240 /* Codes needing carry flag. */
13241 case GEU: /* CF=0 */
13242 case LTU: /* CF=1 */
13243 /* Detect overflow checks. They need just the carry flag. */
13244 if (GET_CODE (op0) == PLUS
13245 && rtx_equal_p (op1, XEXP (op0, 0)))
13249 case GTU: /* CF=0 & ZF=0 */
13250 case LEU: /* CF=1 | ZF=1 */
13251 /* Detect overflow checks. They need just the carry flag. */
13252 if (GET_CODE (op0) == MINUS
13253 && rtx_equal_p (op1, XEXP (op0, 0)))
13257 /* Codes possibly doable only with sign flag when
13258 comparing against zero. */
13259 case GE: /* SF=OF or SF=0 */
13260 case LT: /* SF<>OF or SF=1 */
13261 if (op1 == const0_rtx)
13264 /* For other cases Carry flag is not required. */
13266 /* Codes doable only with sign flag when comparing
13267 against zero, but we miss jump instruction for it
13268 so we need to use relational tests against overflow
13269 that thus needs to be zero. */
13270 case GT: /* ZF=0 & SF=OF */
13271 case LE: /* ZF=1 | SF<>OF */
13272 if (op1 == const0_rtx)
13276 /* strcmp pattern do (use flags) and combine may ask us for proper
13281 gcc_unreachable ();
13285 /* Return the fixed registers used for condition codes. */
13288 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13295 /* If two condition code modes are compatible, return a condition code
13296 mode which is compatible with both. Otherwise, return
13299 static enum machine_mode
13300 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13305 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13308 if ((m1 == CCGCmode && m2 == CCGOCmode)
13309 || (m1 == CCGOCmode && m2 == CCGCmode))
13315 gcc_unreachable ();
13345 /* These are only compatible with themselves, which we already
13351 /* Split comparison code CODE into comparisons we can do using branch
13352 instructions. BYPASS_CODE is comparison code for branch that will
13353 branch around FIRST_CODE and SECOND_CODE. If some of branches
13354 is not required, set value to UNKNOWN.
13355 We never require more than two branches. */
13358 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13359 enum rtx_code *first_code,
13360 enum rtx_code *second_code)
13362 *first_code = code;
13363 *bypass_code = UNKNOWN;
13364 *second_code = UNKNOWN;
13366 /* The fcomi comparison sets flags as follows:
13376 case GT: /* GTU - CF=0 & ZF=0 */
13377 case GE: /* GEU - CF=0 */
13378 case ORDERED: /* PF=0 */
13379 case UNORDERED: /* PF=1 */
13380 case UNEQ: /* EQ - ZF=1 */
13381 case UNLT: /* LTU - CF=1 */
13382 case UNLE: /* LEU - CF=1 | ZF=1 */
13383 case LTGT: /* EQ - ZF=0 */
13385 case LT: /* LTU - CF=1 - fails on unordered */
13386 *first_code = UNLT;
13387 *bypass_code = UNORDERED;
13389 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13390 *first_code = UNLE;
13391 *bypass_code = UNORDERED;
13393 case EQ: /* EQ - ZF=1 - fails on unordered */
13394 *first_code = UNEQ;
13395 *bypass_code = UNORDERED;
13397 case NE: /* NE - ZF=0 - fails on unordered */
13398 *first_code = LTGT;
13399 *second_code = UNORDERED;
13401 case UNGE: /* GEU - CF=0 - fails on unordered */
13403 *second_code = UNORDERED;
13405 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13407 *second_code = UNORDERED;
13410 gcc_unreachable ();
13412 if (!TARGET_IEEE_FP)
13414 *second_code = UNKNOWN;
13415 *bypass_code = UNKNOWN;
13419 /* Return cost of comparison done fcom + arithmetics operations on AX.
13420 All following functions do use number of instructions as a cost metrics.
13421 In future this should be tweaked to compute bytes for optimize_size and
13422 take into account performance of various instructions on various CPUs. */
13424 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13426 if (!TARGET_IEEE_FP)
13428 /* The cost of code output by ix86_expand_fp_compare. */
13452 gcc_unreachable ();
13456 /* Return cost of comparison done using fcomi operation.
13457 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13459 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13461 enum rtx_code bypass_code, first_code, second_code;
13462 /* Return arbitrarily high cost when instruction is not supported - this
13463 prevents gcc from using it. */
13466 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13467 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13470 /* Return cost of comparison done using sahf operation.
13471 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13473 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13475 enum rtx_code bypass_code, first_code, second_code;
13476 /* Return arbitrarily high cost when instruction is not preferred - this
13477 avoids gcc from using it. */
13478 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13480 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13481 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13484 /* Compute cost of the comparison done using any method.
13485 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13487 ix86_fp_comparison_cost (enum rtx_code code)
13489 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13492 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13493 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13495 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13496 if (min > sahf_cost)
13498 if (min > fcomi_cost)
13503 /* Return true if we should use an FCOMI instruction for this
13507 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13509 enum rtx_code swapped_code = swap_condition (code);
13511 return ((ix86_fp_comparison_cost (code)
13512 == ix86_fp_comparison_fcomi_cost (code))
13513 || (ix86_fp_comparison_cost (swapped_code)
13514 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13517 /* Swap, force into registers, or otherwise massage the two operands
13518 to a fp comparison. The operands are updated in place; the new
13519 comparison code is returned. */
13521 static enum rtx_code
13522 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13524 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13525 rtx op0 = *pop0, op1 = *pop1;
13526 enum machine_mode op_mode = GET_MODE (op0);
13527 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13529 /* All of the unordered compare instructions only work on registers.
13530 The same is true of the fcomi compare instructions. The XFmode
13531 compare instructions require registers except when comparing
13532 against zero or when converting operand 1 from fixed point to
13536 && (fpcmp_mode == CCFPUmode
13537 || (op_mode == XFmode
13538 && ! (standard_80387_constant_p (op0) == 1
13539 || standard_80387_constant_p (op1) == 1)
13540 && GET_CODE (op1) != FLOAT)
13541 || ix86_use_fcomi_compare (code)))
13543 op0 = force_reg (op_mode, op0);
13544 op1 = force_reg (op_mode, op1);
13548 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13549 things around if they appear profitable, otherwise force op0
13550 into a register. */
13552 if (standard_80387_constant_p (op0) == 0
13554 && ! (standard_80387_constant_p (op1) == 0
13558 tmp = op0, op0 = op1, op1 = tmp;
13559 code = swap_condition (code);
13563 op0 = force_reg (op_mode, op0);
13565 if (CONSTANT_P (op1))
13567 int tmp = standard_80387_constant_p (op1);
13569 op1 = validize_mem (force_const_mem (op_mode, op1));
13573 op1 = force_reg (op_mode, op1);
13576 op1 = force_reg (op_mode, op1);
13580 /* Try to rearrange the comparison to make it cheaper. */
13581 if (ix86_fp_comparison_cost (code)
13582 > ix86_fp_comparison_cost (swap_condition (code))
13583 && (REG_P (op1) || can_create_pseudo_p ()))
13586 tmp = op0, op0 = op1, op1 = tmp;
13587 code = swap_condition (code);
13589 op0 = force_reg (op_mode, op0);
13597 /* Convert comparison codes we use to represent FP comparison to integer
13598 code that will result in proper branch. Return UNKNOWN if no such code
13602 ix86_fp_compare_code_to_integer (enum rtx_code code)
13631 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13634 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
13635 rtx *second_test, rtx *bypass_test)
13637 enum machine_mode fpcmp_mode, intcmp_mode;
13639 int cost = ix86_fp_comparison_cost (code);
13640 enum rtx_code bypass_code, first_code, second_code;
13642 fpcmp_mode = ix86_fp_compare_mode (code);
13643 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
13646 *second_test = NULL_RTX;
13648 *bypass_test = NULL_RTX;
13650 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13652 /* Do fcomi/sahf based test when profitable. */
13653 if (ix86_fp_comparison_arithmetics_cost (code) > cost
13654 && (bypass_code == UNKNOWN || bypass_test)
13655 && (second_code == UNKNOWN || second_test))
13657 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13658 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
13664 gcc_assert (TARGET_SAHF);
13667 scratch = gen_reg_rtx (HImode);
13668 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
13670 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
13673 /* The FP codes work out to act like unsigned. */
13674 intcmp_mode = fpcmp_mode;
13676 if (bypass_code != UNKNOWN)
13677 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
13678 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13680 if (second_code != UNKNOWN)
13681 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
13682 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13687 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
13688 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13689 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
13691 scratch = gen_reg_rtx (HImode);
13692 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
13694 /* In the unordered case, we have to check C2 for NaN's, which
13695 doesn't happen to work out to anything nice combination-wise.
13696 So do some bit twiddling on the value we've got in AH to come
13697 up with an appropriate set of condition codes. */
13699 intcmp_mode = CCNOmode;
13704 if (code == GT || !TARGET_IEEE_FP)
13706 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
13711 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13712 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
13713 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
13714 intcmp_mode = CCmode;
13720 if (code == LT && TARGET_IEEE_FP)
13722 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13723 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
13724 intcmp_mode = CCmode;
13729 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
13735 if (code == GE || !TARGET_IEEE_FP)
13737 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
13742 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13743 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
13750 if (code == LE && TARGET_IEEE_FP)
13752 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13753 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
13754 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
13755 intcmp_mode = CCmode;
13760 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
13766 if (code == EQ && TARGET_IEEE_FP)
13768 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13769 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
13770 intcmp_mode = CCmode;
13775 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
13782 if (code == NE && TARGET_IEEE_FP)
13784 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13785 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
13791 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
13797 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
13801 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
13806 gcc_unreachable ();
13810 /* Return the test that should be put into the flags user, i.e.
13811 the bcc, scc, or cmov instruction. */
13812 return gen_rtx_fmt_ee (code, VOIDmode,
13813 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13818 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
13821 op0 = ix86_compare_op0;
13822 op1 = ix86_compare_op1;
13825 *second_test = NULL_RTX;
13827 *bypass_test = NULL_RTX;
13829 if (ix86_compare_emitted)
13831 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
13832 ix86_compare_emitted = NULL_RTX;
13834 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
13836 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
13837 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
13838 second_test, bypass_test);
13841 ret = ix86_expand_int_compare (code, op0, op1);
13846 /* Return true if the CODE will result in nontrivial jump sequence. */
13848 ix86_fp_jump_nontrivial_p (enum rtx_code code)
13850 enum rtx_code bypass_code, first_code, second_code;
13853 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13854 return bypass_code != UNKNOWN || second_code != UNKNOWN;
13858 ix86_expand_branch (enum rtx_code code, rtx label)
13862 /* If we have emitted a compare insn, go straight to simple.
13863 ix86_expand_compare won't emit anything if ix86_compare_emitted
13865 if (ix86_compare_emitted)
13868 switch (GET_MODE (ix86_compare_op0))
13874 tmp = ix86_expand_compare (code, NULL, NULL);
13875 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
13876 gen_rtx_LABEL_REF (VOIDmode, label),
13878 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
13887 enum rtx_code bypass_code, first_code, second_code;
13889 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
13890 &ix86_compare_op1);
13892 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13894 /* Check whether we will use the natural sequence with one jump. If
13895 so, we can expand jump early. Otherwise delay expansion by
13896 creating compound insn to not confuse optimizers. */
13897 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
13899 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
13900 gen_rtx_LABEL_REF (VOIDmode, label),
13901 pc_rtx, NULL_RTX, NULL_RTX);
13905 tmp = gen_rtx_fmt_ee (code, VOIDmode,
13906 ix86_compare_op0, ix86_compare_op1);
13907 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
13908 gen_rtx_LABEL_REF (VOIDmode, label),
13910 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
13912 use_fcomi = ix86_use_fcomi_compare (code);
13913 vec = rtvec_alloc (3 + !use_fcomi);
13914 RTVEC_ELT (vec, 0) = tmp;
13916 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
13918 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
13921 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
13923 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
13932 /* Expand DImode branch into multiple compare+branch. */
13934 rtx lo[2], hi[2], label2;
13935 enum rtx_code code1, code2, code3;
13936 enum machine_mode submode;
13938 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
13940 tmp = ix86_compare_op0;
13941 ix86_compare_op0 = ix86_compare_op1;
13942 ix86_compare_op1 = tmp;
13943 code = swap_condition (code);
13945 if (GET_MODE (ix86_compare_op0) == DImode)
13947 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
13948 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
13953 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
13954 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
13958 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
13959 avoid two branches. This costs one extra insn, so disable when
13960 optimizing for size. */
13962 if ((code == EQ || code == NE)
13963 && (!optimize_insn_for_size_p ()
13964 || hi[1] == const0_rtx || lo[1] == const0_rtx))
13969 if (hi[1] != const0_rtx)
13970 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
13971 NULL_RTX, 0, OPTAB_WIDEN);
13974 if (lo[1] != const0_rtx)
13975 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
13976 NULL_RTX, 0, OPTAB_WIDEN);
13978 tmp = expand_binop (submode, ior_optab, xor1, xor0,
13979 NULL_RTX, 0, OPTAB_WIDEN);
13981 ix86_compare_op0 = tmp;
13982 ix86_compare_op1 = const0_rtx;
13983 ix86_expand_branch (code, label);
13987 /* Otherwise, if we are doing less-than or greater-or-equal-than,
13988 op1 is a constant and the low word is zero, then we can just
13989 examine the high word. Similarly for low word -1 and
13990 less-or-equal-than or greater-than. */
13992 if (CONST_INT_P (hi[1]))
13995 case LT: case LTU: case GE: case GEU:
13996 if (lo[1] == const0_rtx)
13998 ix86_compare_op0 = hi[0];
13999 ix86_compare_op1 = hi[1];
14000 ix86_expand_branch (code, label);
14004 case LE: case LEU: case GT: case GTU:
14005 if (lo[1] == constm1_rtx)
14007 ix86_compare_op0 = hi[0];
14008 ix86_compare_op1 = hi[1];
14009 ix86_expand_branch (code, label);
14017 /* Otherwise, we need two or three jumps. */
14019 label2 = gen_label_rtx ();
14022 code2 = swap_condition (code);
14023 code3 = unsigned_condition (code);
14027 case LT: case GT: case LTU: case GTU:
14030 case LE: code1 = LT; code2 = GT; break;
14031 case GE: code1 = GT; code2 = LT; break;
14032 case LEU: code1 = LTU; code2 = GTU; break;
14033 case GEU: code1 = GTU; code2 = LTU; break;
14035 case EQ: code1 = UNKNOWN; code2 = NE; break;
14036 case NE: code2 = UNKNOWN; break;
14039 gcc_unreachable ();
14044 * if (hi(a) < hi(b)) goto true;
14045 * if (hi(a) > hi(b)) goto false;
14046 * if (lo(a) < lo(b)) goto true;
14050 ix86_compare_op0 = hi[0];
14051 ix86_compare_op1 = hi[1];
14053 if (code1 != UNKNOWN)
14054 ix86_expand_branch (code1, label);
14055 if (code2 != UNKNOWN)
14056 ix86_expand_branch (code2, label2);
14058 ix86_compare_op0 = lo[0];
14059 ix86_compare_op1 = lo[1];
14060 ix86_expand_branch (code3, label);
14062 if (code2 != UNKNOWN)
14063 emit_label (label2);
14068 gcc_unreachable ();
14072 /* Split branch based on floating point condition. */
14074 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14075 rtx target1, rtx target2, rtx tmp, rtx pushed)
14077 rtx second, bypass;
14078 rtx label = NULL_RTX;
14080 int bypass_probability = -1, second_probability = -1, probability = -1;
14083 if (target2 != pc_rtx)
14086 code = reverse_condition_maybe_unordered (code);
14091 condition = ix86_expand_fp_compare (code, op1, op2,
14092 tmp, &second, &bypass);
14094 /* Remove pushed operand from stack. */
14096 ix86_free_from_memory (GET_MODE (pushed));
14098 if (split_branch_probability >= 0)
14100 /* Distribute the probabilities across the jumps.
14101 Assume the BYPASS and SECOND to be always test
14103 probability = split_branch_probability;
14105 /* Value of 1 is low enough to make no need for probability
14106 to be updated. Later we may run some experiments and see
14107 if unordered values are more frequent in practice. */
14109 bypass_probability = 1;
14111 second_probability = 1;
14113 if (bypass != NULL_RTX)
14115 label = gen_label_rtx ();
14116 i = emit_jump_insn (gen_rtx_SET
14118 gen_rtx_IF_THEN_ELSE (VOIDmode,
14120 gen_rtx_LABEL_REF (VOIDmode,
14123 if (bypass_probability >= 0)
14125 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14126 GEN_INT (bypass_probability),
14129 i = emit_jump_insn (gen_rtx_SET
14131 gen_rtx_IF_THEN_ELSE (VOIDmode,
14132 condition, target1, target2)));
14133 if (probability >= 0)
14135 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14136 GEN_INT (probability),
14138 if (second != NULL_RTX)
14140 i = emit_jump_insn (gen_rtx_SET
14142 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14144 if (second_probability >= 0)
14146 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14147 GEN_INT (second_probability),
14150 if (label != NULL_RTX)
14151 emit_label (label);
14155 ix86_expand_setcc (enum rtx_code code, rtx dest)
14157 rtx ret, tmp, tmpreg, equiv;
14158 rtx second_test, bypass_test;
14160 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14161 return 0; /* FAIL */
14163 gcc_assert (GET_MODE (dest) == QImode);
14165 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14166 PUT_MODE (ret, QImode);
14171 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14172 if (bypass_test || second_test)
14174 rtx test = second_test;
14176 rtx tmp2 = gen_reg_rtx (QImode);
14179 gcc_assert (!second_test);
14180 test = bypass_test;
14182 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14184 PUT_MODE (test, QImode);
14185 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14188 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14190 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14193 /* Attach a REG_EQUAL note describing the comparison result. */
14194 if (ix86_compare_op0 && ix86_compare_op1)
14196 equiv = simplify_gen_relational (code, QImode,
14197 GET_MODE (ix86_compare_op0),
14198 ix86_compare_op0, ix86_compare_op1);
14199 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14202 return 1; /* DONE */
14205 /* Expand comparison setting or clearing carry flag. Return true when
14206 successful and set pop for the operation. */
14208 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14210 enum machine_mode mode =
14211 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14213 /* Do not handle DImode compares that go through special path. */
14214 if (mode == (TARGET_64BIT ? TImode : DImode))
14217 if (SCALAR_FLOAT_MODE_P (mode))
14219 rtx second_test = NULL, bypass_test = NULL;
14220 rtx compare_op, compare_seq;
14222 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14224 /* Shortcut: following common codes never translate
14225 into carry flag compares. */
14226 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14227 || code == ORDERED || code == UNORDERED)
14230 /* These comparisons require zero flag; swap operands so they won't. */
14231 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14232 && !TARGET_IEEE_FP)
14237 code = swap_condition (code);
14240 /* Try to expand the comparison and verify that we end up with
14241 carry flag based comparison. This fails to be true only when
14242 we decide to expand comparison using arithmetic that is not
14243 too common scenario. */
14245 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14246 &second_test, &bypass_test);
14247 compare_seq = get_insns ();
14250 if (second_test || bypass_test)
14253 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14254 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14255 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14257 code = GET_CODE (compare_op);
14259 if (code != LTU && code != GEU)
14262 emit_insn (compare_seq);
14267 if (!INTEGRAL_MODE_P (mode))
14276 /* Convert a==0 into (unsigned)a<1. */
14279 if (op1 != const0_rtx)
14282 code = (code == EQ ? LTU : GEU);
14285 /* Convert a>b into b<a or a>=b-1. */
14288 if (CONST_INT_P (op1))
14290 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14291 /* Bail out on overflow. We still can swap operands but that
14292 would force loading of the constant into register. */
14293 if (op1 == const0_rtx
14294 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14296 code = (code == GTU ? GEU : LTU);
14303 code = (code == GTU ? LTU : GEU);
14307 /* Convert a>=0 into (unsigned)a<0x80000000. */
14310 if (mode == DImode || op1 != const0_rtx)
14312 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14313 code = (code == LT ? GEU : LTU);
14317 if (mode == DImode || op1 != constm1_rtx)
14319 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14320 code = (code == LE ? GEU : LTU);
14326 /* Swapping operands may cause constant to appear as first operand. */
14327 if (!nonimmediate_operand (op0, VOIDmode))
14329 if (!can_create_pseudo_p ())
14331 op0 = force_reg (mode, op0);
14333 ix86_compare_op0 = op0;
14334 ix86_compare_op1 = op1;
14335 *pop = ix86_expand_compare (code, NULL, NULL);
14336 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14341 ix86_expand_int_movcc (rtx operands[])
14343 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14344 rtx compare_seq, compare_op;
14345 rtx second_test, bypass_test;
14346 enum machine_mode mode = GET_MODE (operands[0]);
14347 bool sign_bit_compare_p = false;;
14350 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14351 compare_seq = get_insns ();
14354 compare_code = GET_CODE (compare_op);
14356 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14357 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14358 sign_bit_compare_p = true;
14360 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14361 HImode insns, we'd be swallowed in word prefix ops. */
14363 if ((mode != HImode || TARGET_FAST_PREFIX)
14364 && (mode != (TARGET_64BIT ? TImode : DImode))
14365 && CONST_INT_P (operands[2])
14366 && CONST_INT_P (operands[3]))
14368 rtx out = operands[0];
14369 HOST_WIDE_INT ct = INTVAL (operands[2]);
14370 HOST_WIDE_INT cf = INTVAL (operands[3]);
14371 HOST_WIDE_INT diff;
14374 /* Sign bit compares are better done using shifts than we do by using
14376 if (sign_bit_compare_p
14377 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14378 ix86_compare_op1, &compare_op))
14380 /* Detect overlap between destination and compare sources. */
14383 if (!sign_bit_compare_p)
14385 bool fpcmp = false;
14387 compare_code = GET_CODE (compare_op);
14389 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14390 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14393 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14396 /* To simplify rest of code, restrict to the GEU case. */
14397 if (compare_code == LTU)
14399 HOST_WIDE_INT tmp = ct;
14402 compare_code = reverse_condition (compare_code);
14403 code = reverse_condition (code);
14408 PUT_CODE (compare_op,
14409 reverse_condition_maybe_unordered
14410 (GET_CODE (compare_op)));
14412 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14416 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14417 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14418 tmp = gen_reg_rtx (mode);
14420 if (mode == DImode)
14421 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14423 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14427 if (code == GT || code == GE)
14428 code = reverse_condition (code);
14431 HOST_WIDE_INT tmp = ct;
14436 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14437 ix86_compare_op1, VOIDmode, 0, -1);
14450 tmp = expand_simple_binop (mode, PLUS,
14452 copy_rtx (tmp), 1, OPTAB_DIRECT);
14463 tmp = expand_simple_binop (mode, IOR,
14465 copy_rtx (tmp), 1, OPTAB_DIRECT);
14467 else if (diff == -1 && ct)
14477 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14479 tmp = expand_simple_binop (mode, PLUS,
14480 copy_rtx (tmp), GEN_INT (cf),
14481 copy_rtx (tmp), 1, OPTAB_DIRECT);
14489 * andl cf - ct, dest
14499 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14502 tmp = expand_simple_binop (mode, AND,
14504 gen_int_mode (cf - ct, mode),
14505 copy_rtx (tmp), 1, OPTAB_DIRECT);
14507 tmp = expand_simple_binop (mode, PLUS,
14508 copy_rtx (tmp), GEN_INT (ct),
14509 copy_rtx (tmp), 1, OPTAB_DIRECT);
14512 if (!rtx_equal_p (tmp, out))
14513 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14515 return 1; /* DONE */
14520 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14523 tmp = ct, ct = cf, cf = tmp;
14526 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14528 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14530 /* We may be reversing unordered compare to normal compare, that
14531 is not valid in general (we may convert non-trapping condition
14532 to trapping one), however on i386 we currently emit all
14533 comparisons unordered. */
14534 compare_code = reverse_condition_maybe_unordered (compare_code);
14535 code = reverse_condition_maybe_unordered (code);
14539 compare_code = reverse_condition (compare_code);
14540 code = reverse_condition (code);
14544 compare_code = UNKNOWN;
14545 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14546 && CONST_INT_P (ix86_compare_op1))
14548 if (ix86_compare_op1 == const0_rtx
14549 && (code == LT || code == GE))
14550 compare_code = code;
14551 else if (ix86_compare_op1 == constm1_rtx)
14555 else if (code == GT)
14560 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14561 if (compare_code != UNKNOWN
14562 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14563 && (cf == -1 || ct == -1))
14565 /* If lea code below could be used, only optimize
14566 if it results in a 2 insn sequence. */
14568 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
14569 || diff == 3 || diff == 5 || diff == 9)
14570 || (compare_code == LT && ct == -1)
14571 || (compare_code == GE && cf == -1))
14574 * notl op1 (if necessary)
14582 code = reverse_condition (code);
14585 out = emit_store_flag (out, code, ix86_compare_op0,
14586 ix86_compare_op1, VOIDmode, 0, -1);
14588 out = expand_simple_binop (mode, IOR,
14590 out, 1, OPTAB_DIRECT);
14591 if (out != operands[0])
14592 emit_move_insn (operands[0], out);
14594 return 1; /* DONE */
14599 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
14600 || diff == 3 || diff == 5 || diff == 9)
14601 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
14603 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
14609 * lea cf(dest*(ct-cf)),dest
14613 * This also catches the degenerate setcc-only case.
14619 out = emit_store_flag (out, code, ix86_compare_op0,
14620 ix86_compare_op1, VOIDmode, 0, 1);
14623 /* On x86_64 the lea instruction operates on Pmode, so we need
14624 to get arithmetics done in proper mode to match. */
14626 tmp = copy_rtx (out);
14630 out1 = copy_rtx (out);
14631 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
14635 tmp = gen_rtx_PLUS (mode, tmp, out1);
14641 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
14644 if (!rtx_equal_p (tmp, out))
14647 out = force_operand (tmp, copy_rtx (out));
14649 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
14651 if (!rtx_equal_p (out, operands[0]))
14652 emit_move_insn (operands[0], copy_rtx (out));
14654 return 1; /* DONE */
14658 * General case: Jumpful:
14659 * xorl dest,dest cmpl op1, op2
14660 * cmpl op1, op2 movl ct, dest
14661 * setcc dest jcc 1f
14662 * decl dest movl cf, dest
14663 * andl (cf-ct),dest 1:
14666 * Size 20. Size 14.
14668 * This is reasonably steep, but branch mispredict costs are
14669 * high on modern cpus, so consider failing only if optimizing
14673 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14674 && BRANCH_COST (optimize_insn_for_speed_p (),
14679 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14684 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14686 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14688 /* We may be reversing unordered compare to normal compare,
14689 that is not valid in general (we may convert non-trapping
14690 condition to trapping one), however on i386 we currently
14691 emit all comparisons unordered. */
14692 code = reverse_condition_maybe_unordered (code);
14696 code = reverse_condition (code);
14697 if (compare_code != UNKNOWN)
14698 compare_code = reverse_condition (compare_code);
14702 if (compare_code != UNKNOWN)
14704 /* notl op1 (if needed)
14709 For x < 0 (resp. x <= -1) there will be no notl,
14710 so if possible swap the constants to get rid of the
14712 True/false will be -1/0 while code below (store flag
14713 followed by decrement) is 0/-1, so the constants need
14714 to be exchanged once more. */
14716 if (compare_code == GE || !cf)
14718 code = reverse_condition (code);
14723 HOST_WIDE_INT tmp = cf;
14728 out = emit_store_flag (out, code, ix86_compare_op0,
14729 ix86_compare_op1, VOIDmode, 0, -1);
14733 out = emit_store_flag (out, code, ix86_compare_op0,
14734 ix86_compare_op1, VOIDmode, 0, 1);
14736 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
14737 copy_rtx (out), 1, OPTAB_DIRECT);
14740 out = expand_simple_binop (mode, AND, copy_rtx (out),
14741 gen_int_mode (cf - ct, mode),
14742 copy_rtx (out), 1, OPTAB_DIRECT);
14744 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
14745 copy_rtx (out), 1, OPTAB_DIRECT);
14746 if (!rtx_equal_p (out, operands[0]))
14747 emit_move_insn (operands[0], copy_rtx (out));
14749 return 1; /* DONE */
14753 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14755 /* Try a few things more with specific constants and a variable. */
14758 rtx var, orig_out, out, tmp;
14760 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
14761 return 0; /* FAIL */
14763 /* If one of the two operands is an interesting constant, load a
14764 constant with the above and mask it in with a logical operation. */
14766 if (CONST_INT_P (operands[2]))
14769 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
14770 operands[3] = constm1_rtx, op = and_optab;
14771 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
14772 operands[3] = const0_rtx, op = ior_optab;
14774 return 0; /* FAIL */
14776 else if (CONST_INT_P (operands[3]))
14779 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
14780 operands[2] = constm1_rtx, op = and_optab;
14781 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
14782 operands[2] = const0_rtx, op = ior_optab;
14784 return 0; /* FAIL */
14787 return 0; /* FAIL */
14789 orig_out = operands[0];
14790 tmp = gen_reg_rtx (mode);
14793 /* Recurse to get the constant loaded. */
14794 if (ix86_expand_int_movcc (operands) == 0)
14795 return 0; /* FAIL */
14797 /* Mask in the interesting variable. */
14798 out = expand_binop (mode, op, var, tmp, orig_out, 0,
14800 if (!rtx_equal_p (out, orig_out))
14801 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
14803 return 1; /* DONE */
14807 * For comparison with above,
14817 if (! nonimmediate_operand (operands[2], mode))
14818 operands[2] = force_reg (mode, operands[2]);
14819 if (! nonimmediate_operand (operands[3], mode))
14820 operands[3] = force_reg (mode, operands[3]);
14822 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
14824 rtx tmp = gen_reg_rtx (mode);
14825 emit_move_insn (tmp, operands[3]);
14828 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
14830 rtx tmp = gen_reg_rtx (mode);
14831 emit_move_insn (tmp, operands[2]);
14835 if (! register_operand (operands[2], VOIDmode)
14837 || ! register_operand (operands[3], VOIDmode)))
14838 operands[2] = force_reg (mode, operands[2]);
14841 && ! register_operand (operands[3], VOIDmode))
14842 operands[3] = force_reg (mode, operands[3]);
14844 emit_insn (compare_seq);
14845 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14846 gen_rtx_IF_THEN_ELSE (mode,
14847 compare_op, operands[2],
14850 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
14851 gen_rtx_IF_THEN_ELSE (mode,
14853 copy_rtx (operands[3]),
14854 copy_rtx (operands[0]))));
14856 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
14857 gen_rtx_IF_THEN_ELSE (mode,
14859 copy_rtx (operands[2]),
14860 copy_rtx (operands[0]))));
14862 return 1; /* DONE */
14865 /* Swap, force into registers, or otherwise massage the two operands
14866 to an sse comparison with a mask result. Thus we differ a bit from
14867 ix86_prepare_fp_compare_args which expects to produce a flags result.
14869 The DEST operand exists to help determine whether to commute commutative
14870 operators. The POP0/POP1 operands are updated in place. The new
14871 comparison code is returned, or UNKNOWN if not implementable. */
14873 static enum rtx_code
14874 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
14875 rtx *pop0, rtx *pop1)
14883 /* We have no LTGT as an operator. We could implement it with
14884 NE & ORDERED, but this requires an extra temporary. It's
14885 not clear that it's worth it. */
14892 /* These are supported directly. */
14899 /* For commutative operators, try to canonicalize the destination
14900 operand to be first in the comparison - this helps reload to
14901 avoid extra moves. */
14902 if (!dest || !rtx_equal_p (dest, *pop1))
14910 /* These are not supported directly. Swap the comparison operands
14911 to transform into something that is supported. */
14915 code = swap_condition (code);
14919 gcc_unreachable ();
14925 /* Detect conditional moves that exactly match min/max operational
14926 semantics. Note that this is IEEE safe, as long as we don't
14927 interchange the operands.
14929 Returns FALSE if this conditional move doesn't match a MIN/MAX,
14930 and TRUE if the operation is successful and instructions are emitted. */
14933 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
14934 rtx cmp_op1, rtx if_true, rtx if_false)
14936 enum machine_mode mode;
14942 else if (code == UNGE)
14945 if_true = if_false;
14951 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
14953 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
14958 mode = GET_MODE (dest);
14960 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
14961 but MODE may be a vector mode and thus not appropriate. */
14962 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
14964 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
14967 if_true = force_reg (mode, if_true);
14968 v = gen_rtvec (2, if_true, if_false);
14969 tmp = gen_rtx_UNSPEC (mode, v, u);
14973 code = is_min ? SMIN : SMAX;
14974 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
14977 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
14981 /* Expand an sse vector comparison. Return the register with the result. */
14984 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
14985 rtx op_true, rtx op_false)
14987 enum machine_mode mode = GET_MODE (dest);
14990 cmp_op0 = force_reg (mode, cmp_op0);
14991 if (!nonimmediate_operand (cmp_op1, mode))
14992 cmp_op1 = force_reg (mode, cmp_op1);
14995 || reg_overlap_mentioned_p (dest, op_true)
14996 || reg_overlap_mentioned_p (dest, op_false))
14997 dest = gen_reg_rtx (mode);
14999 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15000 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15005 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15006 operations. This is used for both scalar and vector conditional moves. */
15009 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15011 enum machine_mode mode = GET_MODE (dest);
15014 if (op_false == CONST0_RTX (mode))
15016 op_true = force_reg (mode, op_true);
15017 x = gen_rtx_AND (mode, cmp, op_true);
15018 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15020 else if (op_true == CONST0_RTX (mode))
15022 op_false = force_reg (mode, op_false);
15023 x = gen_rtx_NOT (mode, cmp);
15024 x = gen_rtx_AND (mode, x, op_false);
15025 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15027 else if (TARGET_SSE5)
15029 rtx pcmov = gen_rtx_SET (mode, dest,
15030 gen_rtx_IF_THEN_ELSE (mode, cmp,
15037 op_true = force_reg (mode, op_true);
15038 op_false = force_reg (mode, op_false);
15040 t2 = gen_reg_rtx (mode);
15042 t3 = gen_reg_rtx (mode);
15046 x = gen_rtx_AND (mode, op_true, cmp);
15047 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15049 x = gen_rtx_NOT (mode, cmp);
15050 x = gen_rtx_AND (mode, x, op_false);
15051 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15053 x = gen_rtx_IOR (mode, t3, t2);
15054 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15058 /* Expand a floating-point conditional move. Return true if successful. */
15061 ix86_expand_fp_movcc (rtx operands[])
15063 enum machine_mode mode = GET_MODE (operands[0]);
15064 enum rtx_code code = GET_CODE (operands[1]);
15065 rtx tmp, compare_op, second_test, bypass_test;
15067 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15069 enum machine_mode cmode;
15071 /* Since we've no cmove for sse registers, don't force bad register
15072 allocation just to gain access to it. Deny movcc when the
15073 comparison mode doesn't match the move mode. */
15074 cmode = GET_MODE (ix86_compare_op0);
15075 if (cmode == VOIDmode)
15076 cmode = GET_MODE (ix86_compare_op1);
15080 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15082 &ix86_compare_op1);
15083 if (code == UNKNOWN)
15086 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15087 ix86_compare_op1, operands[2],
15091 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15092 ix86_compare_op1, operands[2], operands[3]);
15093 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15097 /* The floating point conditional move instructions don't directly
15098 support conditions resulting from a signed integer comparison. */
15100 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15102 /* The floating point conditional move instructions don't directly
15103 support signed integer comparisons. */
15105 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15107 gcc_assert (!second_test && !bypass_test);
15108 tmp = gen_reg_rtx (QImode);
15109 ix86_expand_setcc (code, tmp);
15111 ix86_compare_op0 = tmp;
15112 ix86_compare_op1 = const0_rtx;
15113 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15115 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15117 tmp = gen_reg_rtx (mode);
15118 emit_move_insn (tmp, operands[3]);
15121 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15123 tmp = gen_reg_rtx (mode);
15124 emit_move_insn (tmp, operands[2]);
15128 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15129 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15130 operands[2], operands[3])));
15132 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15133 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15134 operands[3], operands[0])));
15136 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15137 gen_rtx_IF_THEN_ELSE (mode, second_test,
15138 operands[2], operands[0])));
15143 /* Expand a floating-point vector conditional move; a vcond operation
15144 rather than a movcc operation. */
15147 ix86_expand_fp_vcond (rtx operands[])
15149 enum rtx_code code = GET_CODE (operands[3]);
15152 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15153 &operands[4], &operands[5]);
15154 if (code == UNKNOWN)
15157 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15158 operands[5], operands[1], operands[2]))
15161 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15162 operands[1], operands[2]);
15163 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15167 /* Expand a signed/unsigned integral vector conditional move. */
15170 ix86_expand_int_vcond (rtx operands[])
15172 enum machine_mode mode = GET_MODE (operands[0]);
15173 enum rtx_code code = GET_CODE (operands[3]);
15174 bool negate = false;
15177 cop0 = operands[4];
15178 cop1 = operands[5];
15180 /* SSE5 supports all of the comparisons on all vector int types. */
15183 /* Canonicalize the comparison to EQ, GT, GTU. */
15194 code = reverse_condition (code);
15200 code = reverse_condition (code);
15206 code = swap_condition (code);
15207 x = cop0, cop0 = cop1, cop1 = x;
15211 gcc_unreachable ();
15214 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15215 if (mode == V2DImode)
15220 /* SSE4.1 supports EQ. */
15221 if (!TARGET_SSE4_1)
15227 /* SSE4.2 supports GT/GTU. */
15228 if (!TARGET_SSE4_2)
15233 gcc_unreachable ();
15237 /* Unsigned parallel compare is not supported by the hardware. Play some
15238 tricks to turn this into a signed comparison against 0. */
15241 cop0 = force_reg (mode, cop0);
15250 /* Perform a parallel modulo subtraction. */
15251 t1 = gen_reg_rtx (mode);
15252 emit_insn ((mode == V4SImode
15254 : gen_subv2di3) (t1, cop0, cop1));
15256 /* Extract the original sign bit of op0. */
15257 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15259 t2 = gen_reg_rtx (mode);
15260 emit_insn ((mode == V4SImode
15262 : gen_andv2di3) (t2, cop0, mask));
15264 /* XOR it back into the result of the subtraction. This results
15265 in the sign bit set iff we saw unsigned underflow. */
15266 x = gen_reg_rtx (mode);
15267 emit_insn ((mode == V4SImode
15269 : gen_xorv2di3) (x, t1, t2));
15277 /* Perform a parallel unsigned saturating subtraction. */
15278 x = gen_reg_rtx (mode);
15279 emit_insn (gen_rtx_SET (VOIDmode, x,
15280 gen_rtx_US_MINUS (mode, cop0, cop1)));
15287 gcc_unreachable ();
15291 cop1 = CONST0_RTX (mode);
15295 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15296 operands[1+negate], operands[2-negate]);
15298 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15299 operands[2-negate]);
15303 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15304 true if we should do zero extension, else sign extension. HIGH_P is
15305 true if we want the N/2 high elements, else the low elements. */
15308 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15310 enum machine_mode imode = GET_MODE (operands[1]);
15311 rtx (*unpack)(rtx, rtx, rtx);
15318 unpack = gen_vec_interleave_highv16qi;
15320 unpack = gen_vec_interleave_lowv16qi;
15324 unpack = gen_vec_interleave_highv8hi;
15326 unpack = gen_vec_interleave_lowv8hi;
15330 unpack = gen_vec_interleave_highv4si;
15332 unpack = gen_vec_interleave_lowv4si;
15335 gcc_unreachable ();
15338 dest = gen_lowpart (imode, operands[0]);
15341 se = force_reg (imode, CONST0_RTX (imode));
15343 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15344 operands[1], pc_rtx, pc_rtx);
15346 emit_insn (unpack (dest, operands[1], se));
15349 /* This function performs the same task as ix86_expand_sse_unpack,
15350 but with SSE4.1 instructions. */
15353 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15355 enum machine_mode imode = GET_MODE (operands[1]);
15356 rtx (*unpack)(rtx, rtx);
15363 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15365 unpack = gen_sse4_1_extendv8qiv8hi2;
15369 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15371 unpack = gen_sse4_1_extendv4hiv4si2;
15375 unpack = gen_sse4_1_zero_extendv2siv2di2;
15377 unpack = gen_sse4_1_extendv2siv2di2;
15380 gcc_unreachable ();
15383 dest = operands[0];
15386 /* Shift higher 8 bytes to lower 8 bytes. */
15387 src = gen_reg_rtx (imode);
15388 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15389 gen_lowpart (TImode, operands[1]),
15395 emit_insn (unpack (dest, src));
15398 /* This function performs the same task as ix86_expand_sse_unpack,
15399 but with sse5 instructions. */
15402 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15404 enum machine_mode imode = GET_MODE (operands[1]);
15405 int pperm_bytes[16];
15407 int h = (high_p) ? 8 : 0;
15410 rtvec v = rtvec_alloc (16);
15413 rtx op0 = operands[0], op1 = operands[1];
15418 vs = rtvec_alloc (8);
15419 h2 = (high_p) ? 8 : 0;
15420 for (i = 0; i < 8; i++)
15422 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15423 pperm_bytes[2*i+1] = ((unsigned_p)
15425 : PPERM_SIGN | PPERM_SRC2 | i | h);
15428 for (i = 0; i < 16; i++)
15429 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15431 for (i = 0; i < 8; i++)
15432 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15434 p = gen_rtx_PARALLEL (VOIDmode, vs);
15435 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15437 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15439 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15443 vs = rtvec_alloc (4);
15444 h2 = (high_p) ? 4 : 0;
15445 for (i = 0; i < 4; i++)
15447 sign_extend = ((unsigned_p)
15449 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15450 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15451 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15452 pperm_bytes[4*i+2] = sign_extend;
15453 pperm_bytes[4*i+3] = sign_extend;
15456 for (i = 0; i < 16; i++)
15457 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15459 for (i = 0; i < 4; i++)
15460 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15462 p = gen_rtx_PARALLEL (VOIDmode, vs);
15463 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15465 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15467 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15471 vs = rtvec_alloc (2);
15472 h2 = (high_p) ? 2 : 0;
15473 for (i = 0; i < 2; i++)
15475 sign_extend = ((unsigned_p)
15477 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15478 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15479 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15480 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15481 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15482 pperm_bytes[8*i+4] = sign_extend;
15483 pperm_bytes[8*i+5] = sign_extend;
15484 pperm_bytes[8*i+6] = sign_extend;
15485 pperm_bytes[8*i+7] = sign_extend;
15488 for (i = 0; i < 16; i++)
15489 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15491 for (i = 0; i < 2; i++)
15492 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15494 p = gen_rtx_PARALLEL (VOIDmode, vs);
15495 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15497 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15499 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15503 gcc_unreachable ();
15509 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15510 next narrower integer vector type */
15512 ix86_expand_sse5_pack (rtx operands[3])
15514 enum machine_mode imode = GET_MODE (operands[0]);
15515 int pperm_bytes[16];
15517 rtvec v = rtvec_alloc (16);
15519 rtx op0 = operands[0];
15520 rtx op1 = operands[1];
15521 rtx op2 = operands[2];
15526 for (i = 0; i < 8; i++)
15528 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15529 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15532 for (i = 0; i < 16; i++)
15533 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15535 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15536 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15540 for (i = 0; i < 4; i++)
15542 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15543 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15544 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15545 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15548 for (i = 0; i < 16; i++)
15549 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15551 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15552 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15556 for (i = 0; i < 2; i++)
15558 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15559 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15560 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15561 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15562 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15563 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15564 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15565 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15568 for (i = 0; i < 16; i++)
15569 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15571 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15572 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
15576 gcc_unreachable ();
15582 /* Expand conditional increment or decrement using adb/sbb instructions.
15583 The default case using setcc followed by the conditional move can be
15584 done by generic code. */
15586 ix86_expand_int_addcc (rtx operands[])
15588 enum rtx_code code = GET_CODE (operands[1]);
15590 rtx val = const0_rtx;
15591 bool fpcmp = false;
15592 enum machine_mode mode = GET_MODE (operands[0]);
15594 if (operands[3] != const1_rtx
15595 && operands[3] != constm1_rtx)
15597 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15598 ix86_compare_op1, &compare_op))
15600 code = GET_CODE (compare_op);
15602 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15603 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15606 code = ix86_fp_compare_code_to_integer (code);
15613 PUT_CODE (compare_op,
15614 reverse_condition_maybe_unordered
15615 (GET_CODE (compare_op)));
15617 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15619 PUT_MODE (compare_op, mode);
15621 /* Construct either adc or sbb insn. */
15622 if ((code == LTU) == (operands[3] == constm1_rtx))
15624 switch (GET_MODE (operands[0]))
15627 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
15630 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
15633 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
15636 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15639 gcc_unreachable ();
15644 switch (GET_MODE (operands[0]))
15647 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
15650 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
15653 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
15656 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15659 gcc_unreachable ();
15662 return 1; /* DONE */
15666 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15667 works for floating pointer parameters and nonoffsetable memories.
15668 For pushes, it returns just stack offsets; the values will be saved
15669 in the right order. Maximally three parts are generated. */
15672 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
15677 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
15679 size = (GET_MODE_SIZE (mode) + 4) / 8;
15681 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
15682 gcc_assert (size >= 2 && size <= 4);
15684 /* Optimize constant pool reference to immediates. This is used by fp
15685 moves, that force all constants to memory to allow combining. */
15686 if (MEM_P (operand) && MEM_READONLY_P (operand))
15688 rtx tmp = maybe_get_pool_constant (operand);
15693 if (MEM_P (operand) && !offsettable_memref_p (operand))
15695 /* The only non-offsetable memories we handle are pushes. */
15696 int ok = push_operand (operand, VOIDmode);
15700 operand = copy_rtx (operand);
15701 PUT_MODE (operand, Pmode);
15702 parts[0] = parts[1] = parts[2] = parts[3] = operand;
15706 if (GET_CODE (operand) == CONST_VECTOR)
15708 enum machine_mode imode = int_mode_for_mode (mode);
15709 /* Caution: if we looked through a constant pool memory above,
15710 the operand may actually have a different mode now. That's
15711 ok, since we want to pun this all the way back to an integer. */
15712 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
15713 gcc_assert (operand != NULL);
15719 if (mode == DImode)
15720 split_di (&operand, 1, &parts[0], &parts[1]);
15725 if (REG_P (operand))
15727 gcc_assert (reload_completed);
15728 for (i = 0; i < size; i++)
15729 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
15731 else if (offsettable_memref_p (operand))
15733 operand = adjust_address (operand, SImode, 0);
15734 parts[0] = operand;
15735 for (i = 1; i < size; i++)
15736 parts[i] = adjust_address (operand, SImode, 4 * i);
15738 else if (GET_CODE (operand) == CONST_DOUBLE)
15743 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
15747 real_to_target (l, &r, mode);
15748 parts[3] = gen_int_mode (l[3], SImode);
15749 parts[2] = gen_int_mode (l[2], SImode);
15752 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
15753 parts[2] = gen_int_mode (l[2], SImode);
15756 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
15759 gcc_unreachable ();
15761 parts[1] = gen_int_mode (l[1], SImode);
15762 parts[0] = gen_int_mode (l[0], SImode);
15765 gcc_unreachable ();
15770 if (mode == TImode)
15771 split_ti (&operand, 1, &parts[0], &parts[1]);
15772 if (mode == XFmode || mode == TFmode)
15774 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
15775 if (REG_P (operand))
15777 gcc_assert (reload_completed);
15778 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
15779 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
15781 else if (offsettable_memref_p (operand))
15783 operand = adjust_address (operand, DImode, 0);
15784 parts[0] = operand;
15785 parts[1] = adjust_address (operand, upper_mode, 8);
15787 else if (GET_CODE (operand) == CONST_DOUBLE)
15792 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
15793 real_to_target (l, &r, mode);
15795 /* Do not use shift by 32 to avoid warning on 32bit systems. */
15796 if (HOST_BITS_PER_WIDE_INT >= 64)
15799 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
15800 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
15803 parts[0] = immed_double_const (l[0], l[1], DImode);
15805 if (upper_mode == SImode)
15806 parts[1] = gen_int_mode (l[2], SImode);
15807 else if (HOST_BITS_PER_WIDE_INT >= 64)
15810 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
15811 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
15814 parts[1] = immed_double_const (l[2], l[3], DImode);
15817 gcc_unreachable ();
15824 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
15825 Return false when normal moves are needed; true when all required
15826 insns have been emitted. Operands 2-4 contain the input values
15827 int the correct order; operands 5-7 contain the output values. */
15830 ix86_split_long_move (rtx operands[])
15835 int collisions = 0;
15836 enum machine_mode mode = GET_MODE (operands[0]);
15837 bool collisionparts[4];
15839 /* The DFmode expanders may ask us to move double.
15840 For 64bit target this is single move. By hiding the fact
15841 here we simplify i386.md splitters. */
15842 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
15844 /* Optimize constant pool reference to immediates. This is used by
15845 fp moves, that force all constants to memory to allow combining. */
15847 if (MEM_P (operands[1])
15848 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
15849 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
15850 operands[1] = get_pool_constant (XEXP (operands[1], 0));
15851 if (push_operand (operands[0], VOIDmode))
15853 operands[0] = copy_rtx (operands[0]);
15854 PUT_MODE (operands[0], Pmode);
15857 operands[0] = gen_lowpart (DImode, operands[0]);
15858 operands[1] = gen_lowpart (DImode, operands[1]);
15859 emit_move_insn (operands[0], operands[1]);
15863 /* The only non-offsettable memory we handle is push. */
15864 if (push_operand (operands[0], VOIDmode))
15867 gcc_assert (!MEM_P (operands[0])
15868 || offsettable_memref_p (operands[0]));
15870 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
15871 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
15873 /* When emitting push, take care for source operands on the stack. */
15874 if (push && MEM_P (operands[1])
15875 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
15876 for (i = 0; i < nparts - 1; i++)
15877 part[1][i] = change_address (part[1][i],
15878 GET_MODE (part[1][i]),
15879 XEXP (part[1][i + 1], 0));
15881 /* We need to do copy in the right order in case an address register
15882 of the source overlaps the destination. */
15883 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
15887 for (i = 0; i < nparts; i++)
15890 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
15891 if (collisionparts[i])
15895 /* Collision in the middle part can be handled by reordering. */
15896 if (collisions == 1 && nparts == 3 && collisionparts [1])
15898 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
15899 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
15901 else if (collisions == 1
15903 && (collisionparts [1] || collisionparts [2]))
15905 if (collisionparts [1])
15907 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
15908 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
15912 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
15913 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
15917 /* If there are more collisions, we can't handle it by reordering.
15918 Do an lea to the last part and use only one colliding move. */
15919 else if (collisions > 1)
15925 base = part[0][nparts - 1];
15927 /* Handle the case when the last part isn't valid for lea.
15928 Happens in 64-bit mode storing the 12-byte XFmode. */
15929 if (GET_MODE (base) != Pmode)
15930 base = gen_rtx_REG (Pmode, REGNO (base));
15932 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
15933 part[1][0] = replace_equiv_address (part[1][0], base);
15934 for (i = 1; i < nparts; i++)
15936 tmp = plus_constant (base, UNITS_PER_WORD * i);
15937 part[1][i] = replace_equiv_address (part[1][i], tmp);
15948 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
15949 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
15950 emit_move_insn (part[0][2], part[1][2]);
15952 else if (nparts == 4)
15954 emit_move_insn (part[0][3], part[1][3]);
15955 emit_move_insn (part[0][2], part[1][2]);
15960 /* In 64bit mode we don't have 32bit push available. In case this is
15961 register, it is OK - we will just use larger counterpart. We also
15962 retype memory - these comes from attempt to avoid REX prefix on
15963 moving of second half of TFmode value. */
15964 if (GET_MODE (part[1][1]) == SImode)
15966 switch (GET_CODE (part[1][1]))
15969 part[1][1] = adjust_address (part[1][1], DImode, 0);
15973 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
15977 gcc_unreachable ();
15980 if (GET_MODE (part[1][0]) == SImode)
15981 part[1][0] = part[1][1];
15984 emit_move_insn (part[0][1], part[1][1]);
15985 emit_move_insn (part[0][0], part[1][0]);
15989 /* Choose correct order to not overwrite the source before it is copied. */
15990 if ((REG_P (part[0][0])
15991 && REG_P (part[1][1])
15992 && (REGNO (part[0][0]) == REGNO (part[1][1])
15994 && REGNO (part[0][0]) == REGNO (part[1][2]))
15996 && REGNO (part[0][0]) == REGNO (part[1][3]))))
15998 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16000 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16002 operands[2 + i] = part[0][j];
16003 operands[6 + i] = part[1][j];
16008 for (i = 0; i < nparts; i++)
16010 operands[2 + i] = part[0][i];
16011 operands[6 + i] = part[1][i];
16015 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16016 if (optimize_insn_for_size_p ())
16018 for (j = 0; j < nparts - 1; j++)
16019 if (CONST_INT_P (operands[6 + j])
16020 && operands[6 + j] != const0_rtx
16021 && REG_P (operands[2 + j]))
16022 for (i = j; i < nparts - 1; i++)
16023 if (CONST_INT_P (operands[7 + i])
16024 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16025 operands[7 + i] = operands[2 + j];
16028 for (i = 0; i < nparts; i++)
16029 emit_move_insn (operands[2 + i], operands[6 + i]);
16034 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16035 left shift by a constant, either using a single shift or
16036 a sequence of add instructions. */
16039 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16043 emit_insn ((mode == DImode
16045 : gen_adddi3) (operand, operand, operand));
16047 else if (!optimize_insn_for_size_p ()
16048 && count * ix86_cost->add <= ix86_cost->shift_const)
16051 for (i=0; i<count; i++)
16053 emit_insn ((mode == DImode
16055 : gen_adddi3) (operand, operand, operand));
16059 emit_insn ((mode == DImode
16061 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16065 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16067 rtx low[2], high[2];
16069 const int single_width = mode == DImode ? 32 : 64;
16071 if (CONST_INT_P (operands[2]))
16073 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16074 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16076 if (count >= single_width)
16078 emit_move_insn (high[0], low[1]);
16079 emit_move_insn (low[0], const0_rtx);
16081 if (count > single_width)
16082 ix86_expand_ashl_const (high[0], count - single_width, mode);
16086 if (!rtx_equal_p (operands[0], operands[1]))
16087 emit_move_insn (operands[0], operands[1]);
16088 emit_insn ((mode == DImode
16090 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16091 ix86_expand_ashl_const (low[0], count, mode);
16096 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16098 if (operands[1] == const1_rtx)
16100 /* Assuming we've chosen a QImode capable registers, then 1 << N
16101 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16102 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16104 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16106 ix86_expand_clear (low[0]);
16107 ix86_expand_clear (high[0]);
16108 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16110 d = gen_lowpart (QImode, low[0]);
16111 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16112 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16113 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16115 d = gen_lowpart (QImode, high[0]);
16116 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16117 s = gen_rtx_NE (QImode, flags, const0_rtx);
16118 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16121 /* Otherwise, we can get the same results by manually performing
16122 a bit extract operation on bit 5/6, and then performing the two
16123 shifts. The two methods of getting 0/1 into low/high are exactly
16124 the same size. Avoiding the shift in the bit extract case helps
16125 pentium4 a bit; no one else seems to care much either way. */
16130 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16131 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16133 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16134 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16136 emit_insn ((mode == DImode
16138 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16139 emit_insn ((mode == DImode
16141 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16142 emit_move_insn (low[0], high[0]);
16143 emit_insn ((mode == DImode
16145 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16148 emit_insn ((mode == DImode
16150 : gen_ashldi3) (low[0], low[0], operands[2]));
16151 emit_insn ((mode == DImode
16153 : gen_ashldi3) (high[0], high[0], operands[2]));
16157 if (operands[1] == constm1_rtx)
16159 /* For -1 << N, we can avoid the shld instruction, because we
16160 know that we're shifting 0...31/63 ones into a -1. */
16161 emit_move_insn (low[0], constm1_rtx);
16162 if (optimize_insn_for_size_p ())
16163 emit_move_insn (high[0], low[0]);
16165 emit_move_insn (high[0], constm1_rtx);
16169 if (!rtx_equal_p (operands[0], operands[1]))
16170 emit_move_insn (operands[0], operands[1]);
16172 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16173 emit_insn ((mode == DImode
16175 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16178 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16180 if (TARGET_CMOVE && scratch)
16182 ix86_expand_clear (scratch);
16183 emit_insn ((mode == DImode
16184 ? gen_x86_shift_adj_1
16185 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16189 emit_insn ((mode == DImode
16190 ? gen_x86_shift_adj_2
16191 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16195 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16197 rtx low[2], high[2];
16199 const int single_width = mode == DImode ? 32 : 64;
16201 if (CONST_INT_P (operands[2]))
16203 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16204 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16206 if (count == single_width * 2 - 1)
16208 emit_move_insn (high[0], high[1]);
16209 emit_insn ((mode == DImode
16211 : gen_ashrdi3) (high[0], high[0],
16212 GEN_INT (single_width - 1)));
16213 emit_move_insn (low[0], high[0]);
16216 else if (count >= single_width)
16218 emit_move_insn (low[0], high[1]);
16219 emit_move_insn (high[0], low[0]);
16220 emit_insn ((mode == DImode
16222 : gen_ashrdi3) (high[0], high[0],
16223 GEN_INT (single_width - 1)));
16224 if (count > single_width)
16225 emit_insn ((mode == DImode
16227 : gen_ashrdi3) (low[0], low[0],
16228 GEN_INT (count - single_width)));
16232 if (!rtx_equal_p (operands[0], operands[1]))
16233 emit_move_insn (operands[0], operands[1]);
16234 emit_insn ((mode == DImode
16236 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16237 emit_insn ((mode == DImode
16239 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16244 if (!rtx_equal_p (operands[0], operands[1]))
16245 emit_move_insn (operands[0], operands[1]);
16247 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16249 emit_insn ((mode == DImode
16251 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16252 emit_insn ((mode == DImode
16254 : gen_ashrdi3) (high[0], high[0], operands[2]));
16256 if (TARGET_CMOVE && scratch)
16258 emit_move_insn (scratch, high[0]);
16259 emit_insn ((mode == DImode
16261 : gen_ashrdi3) (scratch, scratch,
16262 GEN_INT (single_width - 1)));
16263 emit_insn ((mode == DImode
16264 ? gen_x86_shift_adj_1
16265 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16269 emit_insn ((mode == DImode
16270 ? gen_x86_shift_adj_3
16271 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16276 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16278 rtx low[2], high[2];
16280 const int single_width = mode == DImode ? 32 : 64;
16282 if (CONST_INT_P (operands[2]))
16284 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16285 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16287 if (count >= single_width)
16289 emit_move_insn (low[0], high[1]);
16290 ix86_expand_clear (high[0]);
16292 if (count > single_width)
16293 emit_insn ((mode == DImode
16295 : gen_lshrdi3) (low[0], low[0],
16296 GEN_INT (count - single_width)));
16300 if (!rtx_equal_p (operands[0], operands[1]))
16301 emit_move_insn (operands[0], operands[1]);
16302 emit_insn ((mode == DImode
16304 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16305 emit_insn ((mode == DImode
16307 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16312 if (!rtx_equal_p (operands[0], operands[1]))
16313 emit_move_insn (operands[0], operands[1]);
16315 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16317 emit_insn ((mode == DImode
16319 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16320 emit_insn ((mode == DImode
16322 : gen_lshrdi3) (high[0], high[0], operands[2]));
16324 /* Heh. By reversing the arguments, we can reuse this pattern. */
16325 if (TARGET_CMOVE && scratch)
16327 ix86_expand_clear (scratch);
16328 emit_insn ((mode == DImode
16329 ? gen_x86_shift_adj_1
16330 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16334 emit_insn ((mode == DImode
16335 ? gen_x86_shift_adj_2
16336 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16340 /* Predict just emitted jump instruction to be taken with probability PROB. */
16342 predict_jump (int prob)
16344 rtx insn = get_last_insn ();
16345 gcc_assert (JUMP_P (insn));
16347 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16352 /* Helper function for the string operations below. Dest VARIABLE whether
16353 it is aligned to VALUE bytes. If true, jump to the label. */
16355 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16357 rtx label = gen_label_rtx ();
16358 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16359 if (GET_MODE (variable) == DImode)
16360 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16362 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16363 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16366 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16368 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16372 /* Adjust COUNTER by the VALUE. */
16374 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16376 if (GET_MODE (countreg) == DImode)
16377 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16379 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16382 /* Zero extend possibly SImode EXP to Pmode register. */
16384 ix86_zero_extend_to_Pmode (rtx exp)
16387 if (GET_MODE (exp) == VOIDmode)
16388 return force_reg (Pmode, exp);
16389 if (GET_MODE (exp) == Pmode)
16390 return copy_to_mode_reg (Pmode, exp);
16391 r = gen_reg_rtx (Pmode);
16392 emit_insn (gen_zero_extendsidi2 (r, exp));
16396 /* Divide COUNTREG by SCALE. */
16398 scale_counter (rtx countreg, int scale)
16401 rtx piece_size_mask;
16405 if (CONST_INT_P (countreg))
16406 return GEN_INT (INTVAL (countreg) / scale);
16407 gcc_assert (REG_P (countreg));
16409 piece_size_mask = GEN_INT (scale - 1);
16410 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16411 GEN_INT (exact_log2 (scale)),
16412 NULL, 1, OPTAB_DIRECT);
16416 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16417 DImode for constant loop counts. */
16419 static enum machine_mode
16420 counter_mode (rtx count_exp)
16422 if (GET_MODE (count_exp) != VOIDmode)
16423 return GET_MODE (count_exp);
16424 if (GET_CODE (count_exp) != CONST_INT)
16426 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16431 /* When SRCPTR is non-NULL, output simple loop to move memory
16432 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16433 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16434 equivalent loop to set memory by VALUE (supposed to be in MODE).
16436 The size is rounded down to whole number of chunk size moved at once.
16437 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16441 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16442 rtx destptr, rtx srcptr, rtx value,
16443 rtx count, enum machine_mode mode, int unroll,
16446 rtx out_label, top_label, iter, tmp;
16447 enum machine_mode iter_mode = counter_mode (count);
16448 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16449 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16455 top_label = gen_label_rtx ();
16456 out_label = gen_label_rtx ();
16457 iter = gen_reg_rtx (iter_mode);
16459 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16460 NULL, 1, OPTAB_DIRECT);
16461 /* Those two should combine. */
16462 if (piece_size == const1_rtx)
16464 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16466 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16468 emit_move_insn (iter, const0_rtx);
16470 emit_label (top_label);
16472 tmp = convert_modes (Pmode, iter_mode, iter, true);
16473 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16474 destmem = change_address (destmem, mode, x_addr);
16478 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16479 srcmem = change_address (srcmem, mode, y_addr);
16481 /* When unrolling for chips that reorder memory reads and writes,
16482 we can save registers by using single temporary.
16483 Also using 4 temporaries is overkill in 32bit mode. */
16484 if (!TARGET_64BIT && 0)
16486 for (i = 0; i < unroll; i++)
16491 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16493 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16495 emit_move_insn (destmem, srcmem);
16501 gcc_assert (unroll <= 4);
16502 for (i = 0; i < unroll; i++)
16504 tmpreg[i] = gen_reg_rtx (mode);
16508 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16510 emit_move_insn (tmpreg[i], srcmem);
16512 for (i = 0; i < unroll; i++)
16517 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16519 emit_move_insn (destmem, tmpreg[i]);
16524 for (i = 0; i < unroll; i++)
16528 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16529 emit_move_insn (destmem, value);
16532 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16533 true, OPTAB_LIB_WIDEN);
16535 emit_move_insn (iter, tmp);
16537 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16539 if (expected_size != -1)
16541 expected_size /= GET_MODE_SIZE (mode) * unroll;
16542 if (expected_size == 0)
16544 else if (expected_size > REG_BR_PROB_BASE)
16545 predict_jump (REG_BR_PROB_BASE - 1);
16547 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16550 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16551 iter = ix86_zero_extend_to_Pmode (iter);
16552 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16553 true, OPTAB_LIB_WIDEN);
16554 if (tmp != destptr)
16555 emit_move_insn (destptr, tmp);
16558 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16559 true, OPTAB_LIB_WIDEN);
16561 emit_move_insn (srcptr, tmp);
16563 emit_label (out_label);
16566 /* Output "rep; mov" instruction.
16567 Arguments have same meaning as for previous function */
16569 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
16570 rtx destptr, rtx srcptr,
16572 enum machine_mode mode)
16578 /* If the size is known, it is shorter to use rep movs. */
16579 if (mode == QImode && CONST_INT_P (count)
16580 && !(INTVAL (count) & 3))
16583 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16584 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16585 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
16586 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
16587 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16588 if (mode != QImode)
16590 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16591 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16592 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16593 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
16594 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16595 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
16599 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16600 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
16602 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
16606 /* Output "rep; stos" instruction.
16607 Arguments have same meaning as for previous function */
16609 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
16611 enum machine_mode mode)
16616 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16617 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16618 value = force_reg (mode, gen_lowpart (mode, value));
16619 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16620 if (mode != QImode)
16622 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16623 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16624 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16627 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16628 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
16632 emit_strmov (rtx destmem, rtx srcmem,
16633 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
16635 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
16636 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
16637 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16640 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16642 expand_movmem_epilogue (rtx destmem, rtx srcmem,
16643 rtx destptr, rtx srcptr, rtx count, int max_size)
16646 if (CONST_INT_P (count))
16648 HOST_WIDE_INT countval = INTVAL (count);
16651 if ((countval & 0x10) && max_size > 16)
16655 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16656 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
16659 gcc_unreachable ();
16662 if ((countval & 0x08) && max_size > 8)
16665 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16668 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
16669 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
16673 if ((countval & 0x04) && max_size > 4)
16675 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
16678 if ((countval & 0x02) && max_size > 2)
16680 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
16683 if ((countval & 0x01) && max_size > 1)
16685 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
16692 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
16693 count, 1, OPTAB_DIRECT);
16694 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
16695 count, QImode, 1, 4);
16699 /* When there are stringops, we can cheaply increase dest and src pointers.
16700 Otherwise we save code size by maintaining offset (zero is readily
16701 available from preceding rep operation) and using x86 addressing modes.
16703 if (TARGET_SINGLE_STRINGOP)
16707 rtx label = ix86_expand_aligntest (count, 4, true);
16708 src = change_address (srcmem, SImode, srcptr);
16709 dest = change_address (destmem, SImode, destptr);
16710 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16711 emit_label (label);
16712 LABEL_NUSES (label) = 1;
16716 rtx label = ix86_expand_aligntest (count, 2, true);
16717 src = change_address (srcmem, HImode, srcptr);
16718 dest = change_address (destmem, HImode, destptr);
16719 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16720 emit_label (label);
16721 LABEL_NUSES (label) = 1;
16725 rtx label = ix86_expand_aligntest (count, 1, true);
16726 src = change_address (srcmem, QImode, srcptr);
16727 dest = change_address (destmem, QImode, destptr);
16728 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16729 emit_label (label);
16730 LABEL_NUSES (label) = 1;
16735 rtx offset = force_reg (Pmode, const0_rtx);
16740 rtx label = ix86_expand_aligntest (count, 4, true);
16741 src = change_address (srcmem, SImode, srcptr);
16742 dest = change_address (destmem, SImode, destptr);
16743 emit_move_insn (dest, src);
16744 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
16745 true, OPTAB_LIB_WIDEN);
16747 emit_move_insn (offset, tmp);
16748 emit_label (label);
16749 LABEL_NUSES (label) = 1;
16753 rtx label = ix86_expand_aligntest (count, 2, true);
16754 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
16755 src = change_address (srcmem, HImode, tmp);
16756 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
16757 dest = change_address (destmem, HImode, tmp);
16758 emit_move_insn (dest, src);
16759 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
16760 true, OPTAB_LIB_WIDEN);
16762 emit_move_insn (offset, tmp);
16763 emit_label (label);
16764 LABEL_NUSES (label) = 1;
16768 rtx label = ix86_expand_aligntest (count, 1, true);
16769 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
16770 src = change_address (srcmem, QImode, tmp);
16771 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
16772 dest = change_address (destmem, QImode, tmp);
16773 emit_move_insn (dest, src);
16774 emit_label (label);
16775 LABEL_NUSES (label) = 1;
16780 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16782 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
16783 rtx count, int max_size)
16786 expand_simple_binop (counter_mode (count), AND, count,
16787 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
16788 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
16789 gen_lowpart (QImode, value), count, QImode,
16793 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16795 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
16799 if (CONST_INT_P (count))
16801 HOST_WIDE_INT countval = INTVAL (count);
16804 if ((countval & 0x10) && max_size > 16)
16808 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
16809 emit_insn (gen_strset (destptr, dest, value));
16810 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
16811 emit_insn (gen_strset (destptr, dest, value));
16814 gcc_unreachable ();
16817 if ((countval & 0x08) && max_size > 8)
16821 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
16822 emit_insn (gen_strset (destptr, dest, value));
16826 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
16827 emit_insn (gen_strset (destptr, dest, value));
16828 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
16829 emit_insn (gen_strset (destptr, dest, value));
16833 if ((countval & 0x04) && max_size > 4)
16835 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
16836 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
16839 if ((countval & 0x02) && max_size > 2)
16841 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
16842 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
16845 if ((countval & 0x01) && max_size > 1)
16847 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
16848 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
16855 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
16860 rtx label = ix86_expand_aligntest (count, 16, true);
16863 dest = change_address (destmem, DImode, destptr);
16864 emit_insn (gen_strset (destptr, dest, value));
16865 emit_insn (gen_strset (destptr, dest, value));
16869 dest = change_address (destmem, SImode, destptr);
16870 emit_insn (gen_strset (destptr, dest, value));
16871 emit_insn (gen_strset (destptr, dest, value));
16872 emit_insn (gen_strset (destptr, dest, value));
16873 emit_insn (gen_strset (destptr, dest, value));
16875 emit_label (label);
16876 LABEL_NUSES (label) = 1;
16880 rtx label = ix86_expand_aligntest (count, 8, true);
16883 dest = change_address (destmem, DImode, destptr);
16884 emit_insn (gen_strset (destptr, dest, value));
16888 dest = change_address (destmem, SImode, destptr);
16889 emit_insn (gen_strset (destptr, dest, value));
16890 emit_insn (gen_strset (destptr, dest, value));
16892 emit_label (label);
16893 LABEL_NUSES (label) = 1;
16897 rtx label = ix86_expand_aligntest (count, 4, true);
16898 dest = change_address (destmem, SImode, destptr);
16899 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
16900 emit_label (label);
16901 LABEL_NUSES (label) = 1;
16905 rtx label = ix86_expand_aligntest (count, 2, true);
16906 dest = change_address (destmem, HImode, destptr);
16907 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
16908 emit_label (label);
16909 LABEL_NUSES (label) = 1;
16913 rtx label = ix86_expand_aligntest (count, 1, true);
16914 dest = change_address (destmem, QImode, destptr);
16915 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
16916 emit_label (label);
16917 LABEL_NUSES (label) = 1;
16921 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
16922 DESIRED_ALIGNMENT. */
16924 expand_movmem_prologue (rtx destmem, rtx srcmem,
16925 rtx destptr, rtx srcptr, rtx count,
16926 int align, int desired_alignment)
16928 if (align <= 1 && desired_alignment > 1)
16930 rtx label = ix86_expand_aligntest (destptr, 1, false);
16931 srcmem = change_address (srcmem, QImode, srcptr);
16932 destmem = change_address (destmem, QImode, destptr);
16933 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
16934 ix86_adjust_counter (count, 1);
16935 emit_label (label);
16936 LABEL_NUSES (label) = 1;
16938 if (align <= 2 && desired_alignment > 2)
16940 rtx label = ix86_expand_aligntest (destptr, 2, false);
16941 srcmem = change_address (srcmem, HImode, srcptr);
16942 destmem = change_address (destmem, HImode, destptr);
16943 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
16944 ix86_adjust_counter (count, 2);
16945 emit_label (label);
16946 LABEL_NUSES (label) = 1;
16948 if (align <= 4 && desired_alignment > 4)
16950 rtx label = ix86_expand_aligntest (destptr, 4, false);
16951 srcmem = change_address (srcmem, SImode, srcptr);
16952 destmem = change_address (destmem, SImode, destptr);
16953 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
16954 ix86_adjust_counter (count, 4);
16955 emit_label (label);
16956 LABEL_NUSES (label) = 1;
16958 gcc_assert (desired_alignment <= 8);
16961 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
16962 DESIRED_ALIGNMENT. */
16964 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
16965 int align, int desired_alignment)
16967 if (align <= 1 && desired_alignment > 1)
16969 rtx label = ix86_expand_aligntest (destptr, 1, false);
16970 destmem = change_address (destmem, QImode, destptr);
16971 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
16972 ix86_adjust_counter (count, 1);
16973 emit_label (label);
16974 LABEL_NUSES (label) = 1;
16976 if (align <= 2 && desired_alignment > 2)
16978 rtx label = ix86_expand_aligntest (destptr, 2, false);
16979 destmem = change_address (destmem, HImode, destptr);
16980 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
16981 ix86_adjust_counter (count, 2);
16982 emit_label (label);
16983 LABEL_NUSES (label) = 1;
16985 if (align <= 4 && desired_alignment > 4)
16987 rtx label = ix86_expand_aligntest (destptr, 4, false);
16988 destmem = change_address (destmem, SImode, destptr);
16989 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
16990 ix86_adjust_counter (count, 4);
16991 emit_label (label);
16992 LABEL_NUSES (label) = 1;
16994 gcc_assert (desired_alignment <= 8);
16997 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
16998 static enum stringop_alg
16999 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17000 int *dynamic_check)
17002 const struct stringop_algs * algs;
17003 bool optimize_for_speed;
17004 /* Algorithms using the rep prefix want at least edi and ecx;
17005 additionally, memset wants eax and memcpy wants esi. Don't
17006 consider such algorithms if the user has appropriated those
17007 registers for their own purposes. */
17008 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17010 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17012 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17013 || (alg != rep_prefix_1_byte \
17014 && alg != rep_prefix_4_byte \
17015 && alg != rep_prefix_8_byte))
17016 const struct processor_costs *cost;
17018 /* Even if the string operation call is cold, we still might spend a lot
17019 of time processing large blocks. */
17020 if (optimize_function_for_size_p (cfun)
17021 || (optimize_insn_for_size_p ()
17022 && expected_size != -1 && expected_size < 256))
17023 optimize_for_speed = false;
17025 optimize_for_speed = true;
17027 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17029 *dynamic_check = -1;
17031 algs = &cost->memset[TARGET_64BIT != 0];
17033 algs = &cost->memcpy[TARGET_64BIT != 0];
17034 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17035 return stringop_alg;
17036 /* rep; movq or rep; movl is the smallest variant. */
17037 else if (!optimize_for_speed)
17039 if (!count || (count & 3))
17040 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17042 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17044 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17046 else if (expected_size != -1 && expected_size < 4)
17047 return loop_1_byte;
17048 else if (expected_size != -1)
17051 enum stringop_alg alg = libcall;
17052 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17054 /* We get here if the algorithms that were not libcall-based
17055 were rep-prefix based and we are unable to use rep prefixes
17056 based on global register usage. Break out of the loop and
17057 use the heuristic below. */
17058 if (algs->size[i].max == 0)
17060 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17062 enum stringop_alg candidate = algs->size[i].alg;
17064 if (candidate != libcall && ALG_USABLE_P (candidate))
17066 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17067 last non-libcall inline algorithm. */
17068 if (TARGET_INLINE_ALL_STRINGOPS)
17070 /* When the current size is best to be copied by a libcall,
17071 but we are still forced to inline, run the heuristic below
17072 that will pick code for medium sized blocks. */
17073 if (alg != libcall)
17077 else if (ALG_USABLE_P (candidate))
17081 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17083 /* When asked to inline the call anyway, try to pick meaningful choice.
17084 We look for maximal size of block that is faster to copy by hand and
17085 take blocks of at most of that size guessing that average size will
17086 be roughly half of the block.
17088 If this turns out to be bad, we might simply specify the preferred
17089 choice in ix86_costs. */
17090 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17091 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17094 enum stringop_alg alg;
17096 bool any_alg_usable_p = true;
17098 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17100 enum stringop_alg candidate = algs->size[i].alg;
17101 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17103 if (candidate != libcall && candidate
17104 && ALG_USABLE_P (candidate))
17105 max = algs->size[i].max;
17107 /* If there aren't any usable algorithms, then recursing on
17108 smaller sizes isn't going to find anything. Just return the
17109 simple byte-at-a-time copy loop. */
17110 if (!any_alg_usable_p)
17112 /* Pick something reasonable. */
17113 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17114 *dynamic_check = 128;
17115 return loop_1_byte;
17119 alg = decide_alg (count, max / 2, memset, dynamic_check);
17120 gcc_assert (*dynamic_check == -1);
17121 gcc_assert (alg != libcall);
17122 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17123 *dynamic_check = max;
17126 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17127 #undef ALG_USABLE_P
17130 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17131 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17133 decide_alignment (int align,
17134 enum stringop_alg alg,
17137 int desired_align = 0;
17141 gcc_unreachable ();
17143 case unrolled_loop:
17144 desired_align = GET_MODE_SIZE (Pmode);
17146 case rep_prefix_8_byte:
17149 case rep_prefix_4_byte:
17150 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17151 copying whole cacheline at once. */
17152 if (TARGET_PENTIUMPRO)
17157 case rep_prefix_1_byte:
17158 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17159 copying whole cacheline at once. */
17160 if (TARGET_PENTIUMPRO)
17174 if (desired_align < align)
17175 desired_align = align;
17176 if (expected_size != -1 && expected_size < 4)
17177 desired_align = align;
17178 return desired_align;
17181 /* Return the smallest power of 2 greater than VAL. */
17183 smallest_pow2_greater_than (int val)
17191 /* Expand string move (memcpy) operation. Use i386 string operations when
17192 profitable. expand_setmem contains similar code. The code depends upon
17193 architecture, block size and alignment, but always has the same
17196 1) Prologue guard: Conditional that jumps up to epilogues for small
17197 blocks that can be handled by epilogue alone. This is faster but
17198 also needed for correctness, since prologue assume the block is larger
17199 than the desired alignment.
17201 Optional dynamic check for size and libcall for large
17202 blocks is emitted here too, with -minline-stringops-dynamically.
17204 2) Prologue: copy first few bytes in order to get destination aligned
17205 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17206 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17207 We emit either a jump tree on power of two sized blocks, or a byte loop.
17209 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17210 with specified algorithm.
17212 4) Epilogue: code copying tail of the block that is too small to be
17213 handled by main body (or up to size guarded by prologue guard). */
17216 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17217 rtx expected_align_exp, rtx expected_size_exp)
17223 rtx jump_around_label = NULL;
17224 HOST_WIDE_INT align = 1;
17225 unsigned HOST_WIDE_INT count = 0;
17226 HOST_WIDE_INT expected_size = -1;
17227 int size_needed = 0, epilogue_size_needed;
17228 int desired_align = 0;
17229 enum stringop_alg alg;
17231 bool need_zero_guard = false;
17233 if (CONST_INT_P (align_exp))
17234 align = INTVAL (align_exp);
17235 /* i386 can do misaligned access on reasonably increased cost. */
17236 if (CONST_INT_P (expected_align_exp)
17237 && INTVAL (expected_align_exp) > align)
17238 align = INTVAL (expected_align_exp);
17239 if (CONST_INT_P (count_exp))
17240 count = expected_size = INTVAL (count_exp);
17241 if (CONST_INT_P (expected_size_exp) && count == 0)
17242 expected_size = INTVAL (expected_size_exp);
17244 /* Make sure we don't need to care about overflow later on. */
17245 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17248 /* Step 0: Decide on preferred algorithm, desired alignment and
17249 size of chunks to be copied by main loop. */
17251 alg = decide_alg (count, expected_size, false, &dynamic_check);
17252 desired_align = decide_alignment (align, alg, expected_size);
17254 if (!TARGET_ALIGN_STRINGOPS)
17255 align = desired_align;
17257 if (alg == libcall)
17259 gcc_assert (alg != no_stringop);
17261 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17262 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17263 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17268 gcc_unreachable ();
17270 need_zero_guard = true;
17271 size_needed = GET_MODE_SIZE (Pmode);
17273 case unrolled_loop:
17274 need_zero_guard = true;
17275 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17277 case rep_prefix_8_byte:
17280 case rep_prefix_4_byte:
17283 case rep_prefix_1_byte:
17287 need_zero_guard = true;
17292 epilogue_size_needed = size_needed;
17294 /* Step 1: Prologue guard. */
17296 /* Alignment code needs count to be in register. */
17297 if (CONST_INT_P (count_exp) && desired_align > align)
17298 count_exp = force_reg (counter_mode (count_exp), count_exp);
17299 gcc_assert (desired_align >= 1 && align >= 1);
17301 /* Ensure that alignment prologue won't copy past end of block. */
17302 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17304 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17305 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17306 Make sure it is power of 2. */
17307 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17309 if (CONST_INT_P (count_exp))
17311 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17316 label = gen_label_rtx ();
17317 emit_cmp_and_jump_insns (count_exp,
17318 GEN_INT (epilogue_size_needed),
17319 LTU, 0, counter_mode (count_exp), 1, label);
17320 if (expected_size == -1 || expected_size < epilogue_size_needed)
17321 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17323 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17327 /* Emit code to decide on runtime whether library call or inline should be
17329 if (dynamic_check != -1)
17331 if (CONST_INT_P (count_exp))
17333 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17335 emit_block_move_via_libcall (dst, src, count_exp, false);
17336 count_exp = const0_rtx;
17342 rtx hot_label = gen_label_rtx ();
17343 jump_around_label = gen_label_rtx ();
17344 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17345 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17346 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17347 emit_block_move_via_libcall (dst, src, count_exp, false);
17348 emit_jump (jump_around_label);
17349 emit_label (hot_label);
17353 /* Step 2: Alignment prologue. */
17355 if (desired_align > align)
17357 /* Except for the first move in epilogue, we no longer know
17358 constant offset in aliasing info. It don't seems to worth
17359 the pain to maintain it for the first move, so throw away
17361 src = change_address (src, BLKmode, srcreg);
17362 dst = change_address (dst, BLKmode, destreg);
17363 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17365 if (need_zero_guard && !count)
17367 /* It is possible that we copied enough so the main loop will not
17369 emit_cmp_and_jump_insns (count_exp,
17370 GEN_INT (size_needed),
17371 LTU, 0, counter_mode (count_exp), 1, label);
17372 if (expected_size == -1
17373 || expected_size < (desired_align - align) / 2 + size_needed)
17374 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17376 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17379 if (label && size_needed == 1)
17381 emit_label (label);
17382 LABEL_NUSES (label) = 1;
17386 /* Step 3: Main loop. */
17392 gcc_unreachable ();
17394 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17395 count_exp, QImode, 1, expected_size);
17398 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17399 count_exp, Pmode, 1, expected_size);
17401 case unrolled_loop:
17402 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17403 registers for 4 temporaries anyway. */
17404 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17405 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
17408 case rep_prefix_8_byte:
17409 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17412 case rep_prefix_4_byte:
17413 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17416 case rep_prefix_1_byte:
17417 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17421 /* Adjust properly the offset of src and dest memory for aliasing. */
17422 if (CONST_INT_P (count_exp))
17424 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
17425 (count / size_needed) * size_needed);
17426 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17427 (count / size_needed) * size_needed);
17431 src = change_address (src, BLKmode, srcreg);
17432 dst = change_address (dst, BLKmode, destreg);
17435 /* Step 4: Epilogue to copy the remaining bytes. */
17439 /* When the main loop is done, COUNT_EXP might hold original count,
17440 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17441 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17442 bytes. Compensate if needed. */
17444 if (size_needed < epilogue_size_needed)
17447 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17448 GEN_INT (size_needed - 1), count_exp, 1,
17450 if (tmp != count_exp)
17451 emit_move_insn (count_exp, tmp);
17453 emit_label (label);
17454 LABEL_NUSES (label) = 1;
17457 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17458 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
17459 epilogue_size_needed);
17460 if (jump_around_label)
17461 emit_label (jump_around_label);
17465 /* Helper function for memcpy. For QImode value 0xXY produce
17466 0xXYXYXYXY of wide specified by MODE. This is essentially
17467 a * 0x10101010, but we can do slightly better than
17468 synth_mult by unwinding the sequence by hand on CPUs with
17471 promote_duplicated_reg (enum machine_mode mode, rtx val)
17473 enum machine_mode valmode = GET_MODE (val);
17475 int nops = mode == DImode ? 3 : 2;
17477 gcc_assert (mode == SImode || mode == DImode);
17478 if (val == const0_rtx)
17479 return copy_to_mode_reg (mode, const0_rtx);
17480 if (CONST_INT_P (val))
17482 HOST_WIDE_INT v = INTVAL (val) & 255;
17486 if (mode == DImode)
17487 v |= (v << 16) << 16;
17488 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
17491 if (valmode == VOIDmode)
17493 if (valmode != QImode)
17494 val = gen_lowpart (QImode, val);
17495 if (mode == QImode)
17497 if (!TARGET_PARTIAL_REG_STALL)
17499 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
17500 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
17501 <= (ix86_cost->shift_const + ix86_cost->add) * nops
17502 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
17504 rtx reg = convert_modes (mode, QImode, val, true);
17505 tmp = promote_duplicated_reg (mode, const1_rtx);
17506 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
17511 rtx reg = convert_modes (mode, QImode, val, true);
17513 if (!TARGET_PARTIAL_REG_STALL)
17514 if (mode == SImode)
17515 emit_insn (gen_movsi_insv_1 (reg, reg));
17517 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
17520 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
17521 NULL, 1, OPTAB_DIRECT);
17523 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17525 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
17526 NULL, 1, OPTAB_DIRECT);
17527 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17528 if (mode == SImode)
17530 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
17531 NULL, 1, OPTAB_DIRECT);
17532 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17537 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
17538 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
17539 alignment from ALIGN to DESIRED_ALIGN. */
17541 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
17546 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
17547 promoted_val = promote_duplicated_reg (DImode, val);
17548 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
17549 promoted_val = promote_duplicated_reg (SImode, val);
17550 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
17551 promoted_val = promote_duplicated_reg (HImode, val);
17553 promoted_val = val;
17555 return promoted_val;
17558 /* Expand string clear operation (bzero). Use i386 string operations when
17559 profitable. See expand_movmem comment for explanation of individual
17560 steps performed. */
17562 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
17563 rtx expected_align_exp, rtx expected_size_exp)
17568 rtx jump_around_label = NULL;
17569 HOST_WIDE_INT align = 1;
17570 unsigned HOST_WIDE_INT count = 0;
17571 HOST_WIDE_INT expected_size = -1;
17572 int size_needed = 0, epilogue_size_needed;
17573 int desired_align = 0;
17574 enum stringop_alg alg;
17575 rtx promoted_val = NULL;
17576 bool force_loopy_epilogue = false;
17578 bool need_zero_guard = false;
17580 if (CONST_INT_P (align_exp))
17581 align = INTVAL (align_exp);
17582 /* i386 can do misaligned access on reasonably increased cost. */
17583 if (CONST_INT_P (expected_align_exp)
17584 && INTVAL (expected_align_exp) > align)
17585 align = INTVAL (expected_align_exp);
17586 if (CONST_INT_P (count_exp))
17587 count = expected_size = INTVAL (count_exp);
17588 if (CONST_INT_P (expected_size_exp) && count == 0)
17589 expected_size = INTVAL (expected_size_exp);
17591 /* Make sure we don't need to care about overflow later on. */
17592 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17595 /* Step 0: Decide on preferred algorithm, desired alignment and
17596 size of chunks to be copied by main loop. */
17598 alg = decide_alg (count, expected_size, true, &dynamic_check);
17599 desired_align = decide_alignment (align, alg, expected_size);
17601 if (!TARGET_ALIGN_STRINGOPS)
17602 align = desired_align;
17604 if (alg == libcall)
17606 gcc_assert (alg != no_stringop);
17608 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
17609 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17614 gcc_unreachable ();
17616 need_zero_guard = true;
17617 size_needed = GET_MODE_SIZE (Pmode);
17619 case unrolled_loop:
17620 need_zero_guard = true;
17621 size_needed = GET_MODE_SIZE (Pmode) * 4;
17623 case rep_prefix_8_byte:
17626 case rep_prefix_4_byte:
17629 case rep_prefix_1_byte:
17633 need_zero_guard = true;
17637 epilogue_size_needed = size_needed;
17639 /* Step 1: Prologue guard. */
17641 /* Alignment code needs count to be in register. */
17642 if (CONST_INT_P (count_exp) && desired_align > align)
17644 enum machine_mode mode = SImode;
17645 if (TARGET_64BIT && (count & ~0xffffffff))
17647 count_exp = force_reg (mode, count_exp);
17649 /* Do the cheap promotion to allow better CSE across the
17650 main loop and epilogue (ie one load of the big constant in the
17651 front of all code. */
17652 if (CONST_INT_P (val_exp))
17653 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
17654 desired_align, align);
17655 /* Ensure that alignment prologue won't copy past end of block. */
17656 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17658 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17659 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17660 Make sure it is power of 2. */
17661 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17663 /* To improve performance of small blocks, we jump around the VAL
17664 promoting mode. This mean that if the promoted VAL is not constant,
17665 we might not use it in the epilogue and have to use byte
17667 if (epilogue_size_needed > 2 && !promoted_val)
17668 force_loopy_epilogue = true;
17669 label = gen_label_rtx ();
17670 emit_cmp_and_jump_insns (count_exp,
17671 GEN_INT (epilogue_size_needed),
17672 LTU, 0, counter_mode (count_exp), 1, label);
17673 if (GET_CODE (count_exp) == CONST_INT)
17675 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
17676 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17678 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17680 if (dynamic_check != -1)
17682 rtx hot_label = gen_label_rtx ();
17683 jump_around_label = gen_label_rtx ();
17684 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17685 LEU, 0, counter_mode (count_exp), 1, hot_label);
17686 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17687 set_storage_via_libcall (dst, count_exp, val_exp, false);
17688 emit_jump (jump_around_label);
17689 emit_label (hot_label);
17692 /* Step 2: Alignment prologue. */
17694 /* Do the expensive promotion once we branched off the small blocks. */
17696 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
17697 desired_align, align);
17698 gcc_assert (desired_align >= 1 && align >= 1);
17700 if (desired_align > align)
17702 /* Except for the first move in epilogue, we no longer know
17703 constant offset in aliasing info. It don't seems to worth
17704 the pain to maintain it for the first move, so throw away
17706 dst = change_address (dst, BLKmode, destreg);
17707 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
17709 if (need_zero_guard && !count)
17711 /* It is possible that we copied enough so the main loop will not
17713 emit_cmp_and_jump_insns (count_exp,
17714 GEN_INT (size_needed),
17715 LTU, 0, counter_mode (count_exp), 1, label);
17716 if (expected_size == -1
17717 || expected_size < (desired_align - align) / 2 + size_needed)
17718 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17720 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17723 if (label && size_needed == 1)
17725 emit_label (label);
17726 LABEL_NUSES (label) = 1;
17730 /* Step 3: Main loop. */
17736 gcc_unreachable ();
17738 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
17739 count_exp, QImode, 1, expected_size);
17742 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
17743 count_exp, Pmode, 1, expected_size);
17745 case unrolled_loop:
17746 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
17747 count_exp, Pmode, 4, expected_size);
17749 case rep_prefix_8_byte:
17750 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
17753 case rep_prefix_4_byte:
17754 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
17757 case rep_prefix_1_byte:
17758 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
17762 /* Adjust properly the offset of src and dest memory for aliasing. */
17763 if (CONST_INT_P (count_exp))
17764 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17765 (count / size_needed) * size_needed);
17767 dst = change_address (dst, BLKmode, destreg);
17769 /* Step 4: Epilogue to copy the remaining bytes. */
17773 /* When the main loop is done, COUNT_EXP might hold original count,
17774 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17775 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17776 bytes. Compensate if needed. */
17778 if (size_needed < desired_align - align)
17781 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17782 GEN_INT (size_needed - 1), count_exp, 1,
17784 size_needed = desired_align - align + 1;
17785 if (tmp != count_exp)
17786 emit_move_insn (count_exp, tmp);
17788 emit_label (label);
17789 LABEL_NUSES (label) = 1;
17791 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17793 if (force_loopy_epilogue)
17794 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
17797 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
17800 if (jump_around_label)
17801 emit_label (jump_around_label);
17805 /* Expand the appropriate insns for doing strlen if not just doing
17808 out = result, initialized with the start address
17809 align_rtx = alignment of the address.
17810 scratch = scratch register, initialized with the startaddress when
17811 not aligned, otherwise undefined
17813 This is just the body. It needs the initializations mentioned above and
17814 some address computing at the end. These things are done in i386.md. */
17817 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
17821 rtx align_2_label = NULL_RTX;
17822 rtx align_3_label = NULL_RTX;
17823 rtx align_4_label = gen_label_rtx ();
17824 rtx end_0_label = gen_label_rtx ();
17826 rtx tmpreg = gen_reg_rtx (SImode);
17827 rtx scratch = gen_reg_rtx (SImode);
17831 if (CONST_INT_P (align_rtx))
17832 align = INTVAL (align_rtx);
17834 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
17836 /* Is there a known alignment and is it less than 4? */
17839 rtx scratch1 = gen_reg_rtx (Pmode);
17840 emit_move_insn (scratch1, out);
17841 /* Is there a known alignment and is it not 2? */
17844 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
17845 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
17847 /* Leave just the 3 lower bits. */
17848 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
17849 NULL_RTX, 0, OPTAB_WIDEN);
17851 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
17852 Pmode, 1, align_4_label);
17853 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
17854 Pmode, 1, align_2_label);
17855 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
17856 Pmode, 1, align_3_label);
17860 /* Since the alignment is 2, we have to check 2 or 0 bytes;
17861 check if is aligned to 4 - byte. */
17863 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
17864 NULL_RTX, 0, OPTAB_WIDEN);
17866 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
17867 Pmode, 1, align_4_label);
17870 mem = change_address (src, QImode, out);
17872 /* Now compare the bytes. */
17874 /* Compare the first n unaligned byte on a byte per byte basis. */
17875 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
17876 QImode, 1, end_0_label);
17878 /* Increment the address. */
17879 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
17881 /* Not needed with an alignment of 2 */
17884 emit_label (align_2_label);
17886 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
17889 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
17891 emit_label (align_3_label);
17894 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
17897 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
17900 /* Generate loop to check 4 bytes at a time. It is not a good idea to
17901 align this loop. It gives only huge programs, but does not help to
17903 emit_label (align_4_label);
17905 mem = change_address (src, SImode, out);
17906 emit_move_insn (scratch, mem);
17907 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
17909 /* This formula yields a nonzero result iff one of the bytes is zero.
17910 This saves three branches inside loop and many cycles. */
17912 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
17913 emit_insn (gen_one_cmplsi2 (scratch, scratch));
17914 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
17915 emit_insn (gen_andsi3 (tmpreg, tmpreg,
17916 gen_int_mode (0x80808080, SImode)));
17917 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
17922 rtx reg = gen_reg_rtx (SImode);
17923 rtx reg2 = gen_reg_rtx (Pmode);
17924 emit_move_insn (reg, tmpreg);
17925 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
17927 /* If zero is not in the first two bytes, move two bytes forward. */
17928 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
17929 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
17930 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
17931 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
17932 gen_rtx_IF_THEN_ELSE (SImode, tmp,
17935 /* Emit lea manually to avoid clobbering of flags. */
17936 emit_insn (gen_rtx_SET (SImode, reg2,
17937 gen_rtx_PLUS (Pmode, out, const2_rtx)));
17939 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
17940 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
17941 emit_insn (gen_rtx_SET (VOIDmode, out,
17942 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
17949 rtx end_2_label = gen_label_rtx ();
17950 /* Is zero in the first two bytes? */
17952 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
17953 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
17954 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
17955 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
17956 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
17958 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
17959 JUMP_LABEL (tmp) = end_2_label;
17961 /* Not in the first two. Move two bytes forward. */
17962 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
17963 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
17965 emit_label (end_2_label);
17969 /* Avoid branch in fixing the byte. */
17970 tmpreg = gen_lowpart (QImode, tmpreg);
17971 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
17972 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
17973 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
17975 emit_label (end_0_label);
17978 /* Expand strlen. */
17981 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
17983 rtx addr, scratch1, scratch2, scratch3, scratch4;
17985 /* The generic case of strlen expander is long. Avoid it's
17986 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
17988 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
17989 && !TARGET_INLINE_ALL_STRINGOPS
17990 && !optimize_insn_for_size_p ()
17991 && (!CONST_INT_P (align) || INTVAL (align) < 4))
17994 addr = force_reg (Pmode, XEXP (src, 0));
17995 scratch1 = gen_reg_rtx (Pmode);
17997 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
17998 && !optimize_insn_for_size_p ())
18000 /* Well it seems that some optimizer does not combine a call like
18001 foo(strlen(bar), strlen(bar));
18002 when the move and the subtraction is done here. It does calculate
18003 the length just once when these instructions are done inside of
18004 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18005 often used and I use one fewer register for the lifetime of
18006 output_strlen_unroll() this is better. */
18008 emit_move_insn (out, addr);
18010 ix86_expand_strlensi_unroll_1 (out, src, align);
18012 /* strlensi_unroll_1 returns the address of the zero at the end of
18013 the string, like memchr(), so compute the length by subtracting
18014 the start address. */
18015 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18021 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18022 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18025 scratch2 = gen_reg_rtx (Pmode);
18026 scratch3 = gen_reg_rtx (Pmode);
18027 scratch4 = force_reg (Pmode, constm1_rtx);
18029 emit_move_insn (scratch3, addr);
18030 eoschar = force_reg (QImode, eoschar);
18032 src = replace_equiv_address_nv (src, scratch3);
18034 /* If .md starts supporting :P, this can be done in .md. */
18035 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18036 scratch4), UNSPEC_SCAS);
18037 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18038 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18039 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18044 /* For given symbol (function) construct code to compute address of it's PLT
18045 entry in large x86-64 PIC model. */
18047 construct_plt_address (rtx symbol)
18049 rtx tmp = gen_reg_rtx (Pmode);
18050 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18052 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18053 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18055 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18056 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18061 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18062 rtx callarg2 ATTRIBUTE_UNUSED,
18063 rtx pop, int sibcall)
18065 rtx use = NULL, call;
18067 if (pop == const0_rtx)
18069 gcc_assert (!TARGET_64BIT || !pop);
18071 if (TARGET_MACHO && !TARGET_64BIT)
18074 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18075 fnaddr = machopic_indirect_call_target (fnaddr);
18080 /* Static functions and indirect calls don't need the pic register. */
18081 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18082 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18083 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18084 use_reg (&use, pic_offset_table_rtx);
18087 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18089 rtx al = gen_rtx_REG (QImode, AX_REG);
18090 emit_move_insn (al, callarg2);
18091 use_reg (&use, al);
18094 if (ix86_cmodel == CM_LARGE_PIC
18095 && GET_CODE (fnaddr) == MEM
18096 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18097 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18098 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18099 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
18101 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18102 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18104 if (sibcall && TARGET_64BIT
18105 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
18108 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18109 fnaddr = gen_rtx_REG (Pmode, R11_REG);
18110 emit_move_insn (fnaddr, addr);
18111 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18114 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18116 call = gen_rtx_SET (VOIDmode, retval, call);
18119 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18120 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18121 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18124 call = emit_call_insn (call);
18126 CALL_INSN_FUNCTION_USAGE (call) = use;
18130 /* Clear stack slot assignments remembered from previous functions.
18131 This is called from INIT_EXPANDERS once before RTL is emitted for each
18134 static struct machine_function *
18135 ix86_init_machine_status (void)
18137 struct machine_function *f;
18139 f = GGC_CNEW (struct machine_function);
18140 f->use_fast_prologue_epilogue_nregs = -1;
18141 f->tls_descriptor_call_expanded_p = 0;
18142 f->call_abi = DEFAULT_ABI;
18147 /* Return a MEM corresponding to a stack slot with mode MODE.
18148 Allocate a new slot if necessary.
18150 The RTL for a function can have several slots available: N is
18151 which slot to use. */
18154 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18156 struct stack_local_entry *s;
18158 gcc_assert (n < MAX_386_STACK_LOCALS);
18160 /* Virtual slot is valid only before vregs are instantiated. */
18161 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18163 for (s = ix86_stack_locals; s; s = s->next)
18164 if (s->mode == mode && s->n == n)
18165 return copy_rtx (s->rtl);
18167 s = (struct stack_local_entry *)
18168 ggc_alloc (sizeof (struct stack_local_entry));
18171 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18173 s->next = ix86_stack_locals;
18174 ix86_stack_locals = s;
18178 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18180 static GTY(()) rtx ix86_tls_symbol;
18182 ix86_tls_get_addr (void)
18185 if (!ix86_tls_symbol)
18187 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18188 (TARGET_ANY_GNU_TLS
18190 ? "___tls_get_addr"
18191 : "__tls_get_addr");
18194 return ix86_tls_symbol;
18197 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18199 static GTY(()) rtx ix86_tls_module_base_symbol;
18201 ix86_tls_module_base (void)
18204 if (!ix86_tls_module_base_symbol)
18206 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18207 "_TLS_MODULE_BASE_");
18208 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18209 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18212 return ix86_tls_module_base_symbol;
18215 /* Calculate the length of the memory address in the instruction
18216 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18219 memory_address_length (rtx addr)
18221 struct ix86_address parts;
18222 rtx base, index, disp;
18226 if (GET_CODE (addr) == PRE_DEC
18227 || GET_CODE (addr) == POST_INC
18228 || GET_CODE (addr) == PRE_MODIFY
18229 || GET_CODE (addr) == POST_MODIFY)
18232 ok = ix86_decompose_address (addr, &parts);
18235 if (parts.base && GET_CODE (parts.base) == SUBREG)
18236 parts.base = SUBREG_REG (parts.base);
18237 if (parts.index && GET_CODE (parts.index) == SUBREG)
18238 parts.index = SUBREG_REG (parts.index);
18241 index = parts.index;
18246 - esp as the base always wants an index,
18247 - ebp as the base always wants a displacement. */
18249 /* Register Indirect. */
18250 if (base && !index && !disp)
18252 /* esp (for its index) and ebp (for its displacement) need
18253 the two-byte modrm form. */
18254 if (addr == stack_pointer_rtx
18255 || addr == arg_pointer_rtx
18256 || addr == frame_pointer_rtx
18257 || addr == hard_frame_pointer_rtx)
18261 /* Direct Addressing. */
18262 else if (disp && !base && !index)
18267 /* Find the length of the displacement constant. */
18270 if (base && satisfies_constraint_K (disp))
18275 /* ebp always wants a displacement. */
18276 else if (base == hard_frame_pointer_rtx)
18279 /* An index requires the two-byte modrm form.... */
18281 /* ...like esp, which always wants an index. */
18282 || base == stack_pointer_rtx
18283 || base == arg_pointer_rtx
18284 || base == frame_pointer_rtx)
18291 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18292 is set, expect that insn have 8bit immediate alternative. */
18294 ix86_attr_length_immediate_default (rtx insn, int shortform)
18298 extract_insn_cached (insn);
18299 for (i = recog_data.n_operands - 1; i >= 0; --i)
18300 if (CONSTANT_P (recog_data.operand[i]))
18303 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
18307 switch (get_attr_mode (insn))
18318 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18323 fatal_insn ("unknown insn mode", insn);
18329 /* Compute default value for "length_address" attribute. */
18331 ix86_attr_length_address_default (rtx insn)
18335 if (get_attr_type (insn) == TYPE_LEA)
18337 rtx set = PATTERN (insn);
18339 if (GET_CODE (set) == PARALLEL)
18340 set = XVECEXP (set, 0, 0);
18342 gcc_assert (GET_CODE (set) == SET);
18344 return memory_address_length (SET_SRC (set));
18347 extract_insn_cached (insn);
18348 for (i = recog_data.n_operands - 1; i >= 0; --i)
18349 if (MEM_P (recog_data.operand[i]))
18351 return memory_address_length (XEXP (recog_data.operand[i], 0));
18357 /* Compute default value for "length_vex" attribute. It includes
18358 2 or 3 byte VEX prefix and 1 opcode byte. */
18361 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
18366 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18367 byte VEX prefix. */
18368 if (!has_0f_opcode || has_vex_w)
18371 /* We can always use 2 byte VEX prefix in 32bit. */
18375 extract_insn_cached (insn);
18377 for (i = recog_data.n_operands - 1; i >= 0; --i)
18378 if (REG_P (recog_data.operand[i]))
18380 /* REX.W bit uses 3 byte VEX prefix. */
18381 if (GET_MODE (recog_data.operand[i]) == DImode)
18386 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18387 if (MEM_P (recog_data.operand[i])
18388 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
18395 /* Return the maximum number of instructions a cpu can issue. */
18398 ix86_issue_rate (void)
18402 case PROCESSOR_PENTIUM:
18406 case PROCESSOR_PENTIUMPRO:
18407 case PROCESSOR_PENTIUM4:
18408 case PROCESSOR_ATHLON:
18410 case PROCESSOR_AMDFAM10:
18411 case PROCESSOR_NOCONA:
18412 case PROCESSOR_GENERIC32:
18413 case PROCESSOR_GENERIC64:
18416 case PROCESSOR_CORE2:
18424 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
18425 by DEP_INSN and nothing set by DEP_INSN. */
18428 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
18432 /* Simplify the test for uninteresting insns. */
18433 if (insn_type != TYPE_SETCC
18434 && insn_type != TYPE_ICMOV
18435 && insn_type != TYPE_FCMOV
18436 && insn_type != TYPE_IBR)
18439 if ((set = single_set (dep_insn)) != 0)
18441 set = SET_DEST (set);
18444 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
18445 && XVECLEN (PATTERN (dep_insn), 0) == 2
18446 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
18447 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
18449 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
18450 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
18455 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
18458 /* This test is true if the dependent insn reads the flags but
18459 not any other potentially set register. */
18460 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
18463 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
18469 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
18470 address with operands set by DEP_INSN. */
18473 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
18477 if (insn_type == TYPE_LEA
18480 addr = PATTERN (insn);
18482 if (GET_CODE (addr) == PARALLEL)
18483 addr = XVECEXP (addr, 0, 0);
18485 gcc_assert (GET_CODE (addr) == SET);
18487 addr = SET_SRC (addr);
18492 extract_insn_cached (insn);
18493 for (i = recog_data.n_operands - 1; i >= 0; --i)
18494 if (MEM_P (recog_data.operand[i]))
18496 addr = XEXP (recog_data.operand[i], 0);
18503 return modified_in_p (addr, dep_insn);
18507 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
18509 enum attr_type insn_type, dep_insn_type;
18510 enum attr_memory memory;
18512 int dep_insn_code_number;
18514 /* Anti and output dependencies have zero cost on all CPUs. */
18515 if (REG_NOTE_KIND (link) != 0)
18518 dep_insn_code_number = recog_memoized (dep_insn);
18520 /* If we can't recognize the insns, we can't really do anything. */
18521 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
18524 insn_type = get_attr_type (insn);
18525 dep_insn_type = get_attr_type (dep_insn);
18529 case PROCESSOR_PENTIUM:
18530 /* Address Generation Interlock adds a cycle of latency. */
18531 if (ix86_agi_dependent (insn, dep_insn, insn_type))
18534 /* ??? Compares pair with jump/setcc. */
18535 if (ix86_flags_dependent (insn, dep_insn, insn_type))
18538 /* Floating point stores require value to be ready one cycle earlier. */
18539 if (insn_type == TYPE_FMOV
18540 && get_attr_memory (insn) == MEMORY_STORE
18541 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18545 case PROCESSOR_PENTIUMPRO:
18546 memory = get_attr_memory (insn);
18548 /* INT->FP conversion is expensive. */
18549 if (get_attr_fp_int_src (dep_insn))
18552 /* There is one cycle extra latency between an FP op and a store. */
18553 if (insn_type == TYPE_FMOV
18554 && (set = single_set (dep_insn)) != NULL_RTX
18555 && (set2 = single_set (insn)) != NULL_RTX
18556 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
18557 && MEM_P (SET_DEST (set2)))
18560 /* Show ability of reorder buffer to hide latency of load by executing
18561 in parallel with previous instruction in case
18562 previous instruction is not needed to compute the address. */
18563 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
18564 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18566 /* Claim moves to take one cycle, as core can issue one load
18567 at time and the next load can start cycle later. */
18568 if (dep_insn_type == TYPE_IMOV
18569 || dep_insn_type == TYPE_FMOV)
18577 memory = get_attr_memory (insn);
18579 /* The esp dependency is resolved before the instruction is really
18581 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
18582 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
18585 /* INT->FP conversion is expensive. */
18586 if (get_attr_fp_int_src (dep_insn))
18589 /* Show ability of reorder buffer to hide latency of load by executing
18590 in parallel with previous instruction in case
18591 previous instruction is not needed to compute the address. */
18592 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
18593 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18595 /* Claim moves to take one cycle, as core can issue one load
18596 at time and the next load can start cycle later. */
18597 if (dep_insn_type == TYPE_IMOV
18598 || dep_insn_type == TYPE_FMOV)
18607 case PROCESSOR_ATHLON:
18609 case PROCESSOR_AMDFAM10:
18610 case PROCESSOR_GENERIC32:
18611 case PROCESSOR_GENERIC64:
18612 memory = get_attr_memory (insn);
18614 /* Show ability of reorder buffer to hide latency of load by executing
18615 in parallel with previous instruction in case
18616 previous instruction is not needed to compute the address. */
18617 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
18618 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18620 enum attr_unit unit = get_attr_unit (insn);
18623 /* Because of the difference between the length of integer and
18624 floating unit pipeline preparation stages, the memory operands
18625 for floating point are cheaper.
18627 ??? For Athlon it the difference is most probably 2. */
18628 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
18631 loadcost = TARGET_ATHLON ? 2 : 0;
18633 if (cost >= loadcost)
18646 /* How many alternative schedules to try. This should be as wide as the
18647 scheduling freedom in the DFA, but no wider. Making this value too
18648 large results extra work for the scheduler. */
18651 ia32_multipass_dfa_lookahead (void)
18655 case PROCESSOR_PENTIUM:
18658 case PROCESSOR_PENTIUMPRO:
18668 /* Compute the alignment given to a constant that is being placed in memory.
18669 EXP is the constant and ALIGN is the alignment that the object would
18671 The value of this function is used instead of that alignment to align
18675 ix86_constant_alignment (tree exp, int align)
18677 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
18678 || TREE_CODE (exp) == INTEGER_CST)
18680 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
18682 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
18685 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
18686 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
18687 return BITS_PER_WORD;
18692 /* Compute the alignment for a static variable.
18693 TYPE is the data type, and ALIGN is the alignment that
18694 the object would ordinarily have. The value of this function is used
18695 instead of that alignment to align the object. */
18698 ix86_data_alignment (tree type, int align)
18700 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
18702 if (AGGREGATE_TYPE_P (type)
18703 && TYPE_SIZE (type)
18704 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
18705 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
18706 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
18707 && align < max_align)
18710 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18711 to 16byte boundary. */
18714 if (AGGREGATE_TYPE_P (type)
18715 && TYPE_SIZE (type)
18716 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
18717 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
18718 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
18722 if (TREE_CODE (type) == ARRAY_TYPE)
18724 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
18726 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
18729 else if (TREE_CODE (type) == COMPLEX_TYPE)
18732 if (TYPE_MODE (type) == DCmode && align < 64)
18734 if ((TYPE_MODE (type) == XCmode
18735 || TYPE_MODE (type) == TCmode) && align < 128)
18738 else if ((TREE_CODE (type) == RECORD_TYPE
18739 || TREE_CODE (type) == UNION_TYPE
18740 || TREE_CODE (type) == QUAL_UNION_TYPE)
18741 && TYPE_FIELDS (type))
18743 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
18745 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
18748 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
18749 || TREE_CODE (type) == INTEGER_TYPE)
18751 if (TYPE_MODE (type) == DFmode && align < 64)
18753 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
18760 /* Compute the alignment for a local variable or a stack slot. TYPE is
18761 the data type, MODE is the widest mode available and ALIGN is the
18762 alignment that the object would ordinarily have. The value of this
18763 macro is used instead of that alignment to align the object. */
18766 ix86_local_alignment (tree type, enum machine_mode mode,
18767 unsigned int align)
18769 /* If TYPE is NULL, we are allocating a stack slot for caller-save
18770 register in MODE. We will return the largest alignment of XF
18774 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
18775 align = GET_MODE_ALIGNMENT (DFmode);
18779 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18780 to 16byte boundary. */
18783 if (AGGREGATE_TYPE_P (type)
18784 && TYPE_SIZE (type)
18785 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
18786 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
18787 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
18790 if (TREE_CODE (type) == ARRAY_TYPE)
18792 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
18794 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
18797 else if (TREE_CODE (type) == COMPLEX_TYPE)
18799 if (TYPE_MODE (type) == DCmode && align < 64)
18801 if ((TYPE_MODE (type) == XCmode
18802 || TYPE_MODE (type) == TCmode) && align < 128)
18805 else if ((TREE_CODE (type) == RECORD_TYPE
18806 || TREE_CODE (type) == UNION_TYPE
18807 || TREE_CODE (type) == QUAL_UNION_TYPE)
18808 && TYPE_FIELDS (type))
18810 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
18812 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
18815 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
18816 || TREE_CODE (type) == INTEGER_TYPE)
18819 if (TYPE_MODE (type) == DFmode && align < 64)
18821 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
18827 /* Emit RTL insns to initialize the variable parts of a trampoline.
18828 FNADDR is an RTX for the address of the function's pure code.
18829 CXT is an RTX for the static chain value for the function. */
18831 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
18835 /* Compute offset from the end of the jmp to the target function. */
18836 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
18837 plus_constant (tramp, 10),
18838 NULL_RTX, 1, OPTAB_DIRECT);
18839 emit_move_insn (gen_rtx_MEM (QImode, tramp),
18840 gen_int_mode (0xb9, QImode));
18841 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
18842 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
18843 gen_int_mode (0xe9, QImode));
18844 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
18849 /* Try to load address using shorter movl instead of movabs.
18850 We may want to support movq for kernel mode, but kernel does not use
18851 trampolines at the moment. */
18852 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
18854 fnaddr = copy_to_mode_reg (DImode, fnaddr);
18855 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
18856 gen_int_mode (0xbb41, HImode));
18857 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
18858 gen_lowpart (SImode, fnaddr));
18863 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
18864 gen_int_mode (0xbb49, HImode));
18865 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
18869 /* Load static chain using movabs to r10. */
18870 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
18871 gen_int_mode (0xba49, HImode));
18872 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
18875 /* Jump to the r11 */
18876 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
18877 gen_int_mode (0xff49, HImode));
18878 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
18879 gen_int_mode (0xe3, QImode));
18881 gcc_assert (offset <= TRAMPOLINE_SIZE);
18884 #ifdef ENABLE_EXECUTE_STACK
18885 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
18886 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
18890 /* Codes for all the SSE/MMX builtins. */
18893 IX86_BUILTIN_ADDPS,
18894 IX86_BUILTIN_ADDSS,
18895 IX86_BUILTIN_DIVPS,
18896 IX86_BUILTIN_DIVSS,
18897 IX86_BUILTIN_MULPS,
18898 IX86_BUILTIN_MULSS,
18899 IX86_BUILTIN_SUBPS,
18900 IX86_BUILTIN_SUBSS,
18902 IX86_BUILTIN_CMPEQPS,
18903 IX86_BUILTIN_CMPLTPS,
18904 IX86_BUILTIN_CMPLEPS,
18905 IX86_BUILTIN_CMPGTPS,
18906 IX86_BUILTIN_CMPGEPS,
18907 IX86_BUILTIN_CMPNEQPS,
18908 IX86_BUILTIN_CMPNLTPS,
18909 IX86_BUILTIN_CMPNLEPS,
18910 IX86_BUILTIN_CMPNGTPS,
18911 IX86_BUILTIN_CMPNGEPS,
18912 IX86_BUILTIN_CMPORDPS,
18913 IX86_BUILTIN_CMPUNORDPS,
18914 IX86_BUILTIN_CMPEQSS,
18915 IX86_BUILTIN_CMPLTSS,
18916 IX86_BUILTIN_CMPLESS,
18917 IX86_BUILTIN_CMPNEQSS,
18918 IX86_BUILTIN_CMPNLTSS,
18919 IX86_BUILTIN_CMPNLESS,
18920 IX86_BUILTIN_CMPNGTSS,
18921 IX86_BUILTIN_CMPNGESS,
18922 IX86_BUILTIN_CMPORDSS,
18923 IX86_BUILTIN_CMPUNORDSS,
18925 IX86_BUILTIN_COMIEQSS,
18926 IX86_BUILTIN_COMILTSS,
18927 IX86_BUILTIN_COMILESS,
18928 IX86_BUILTIN_COMIGTSS,
18929 IX86_BUILTIN_COMIGESS,
18930 IX86_BUILTIN_COMINEQSS,
18931 IX86_BUILTIN_UCOMIEQSS,
18932 IX86_BUILTIN_UCOMILTSS,
18933 IX86_BUILTIN_UCOMILESS,
18934 IX86_BUILTIN_UCOMIGTSS,
18935 IX86_BUILTIN_UCOMIGESS,
18936 IX86_BUILTIN_UCOMINEQSS,
18938 IX86_BUILTIN_CVTPI2PS,
18939 IX86_BUILTIN_CVTPS2PI,
18940 IX86_BUILTIN_CVTSI2SS,
18941 IX86_BUILTIN_CVTSI642SS,
18942 IX86_BUILTIN_CVTSS2SI,
18943 IX86_BUILTIN_CVTSS2SI64,
18944 IX86_BUILTIN_CVTTPS2PI,
18945 IX86_BUILTIN_CVTTSS2SI,
18946 IX86_BUILTIN_CVTTSS2SI64,
18948 IX86_BUILTIN_MAXPS,
18949 IX86_BUILTIN_MAXSS,
18950 IX86_BUILTIN_MINPS,
18951 IX86_BUILTIN_MINSS,
18953 IX86_BUILTIN_LOADUPS,
18954 IX86_BUILTIN_STOREUPS,
18955 IX86_BUILTIN_MOVSS,
18957 IX86_BUILTIN_MOVHLPS,
18958 IX86_BUILTIN_MOVLHPS,
18959 IX86_BUILTIN_LOADHPS,
18960 IX86_BUILTIN_LOADLPS,
18961 IX86_BUILTIN_STOREHPS,
18962 IX86_BUILTIN_STORELPS,
18964 IX86_BUILTIN_MASKMOVQ,
18965 IX86_BUILTIN_MOVMSKPS,
18966 IX86_BUILTIN_PMOVMSKB,
18968 IX86_BUILTIN_MOVNTPS,
18969 IX86_BUILTIN_MOVNTQ,
18971 IX86_BUILTIN_LOADDQU,
18972 IX86_BUILTIN_STOREDQU,
18974 IX86_BUILTIN_PACKSSWB,
18975 IX86_BUILTIN_PACKSSDW,
18976 IX86_BUILTIN_PACKUSWB,
18978 IX86_BUILTIN_PADDB,
18979 IX86_BUILTIN_PADDW,
18980 IX86_BUILTIN_PADDD,
18981 IX86_BUILTIN_PADDQ,
18982 IX86_BUILTIN_PADDSB,
18983 IX86_BUILTIN_PADDSW,
18984 IX86_BUILTIN_PADDUSB,
18985 IX86_BUILTIN_PADDUSW,
18986 IX86_BUILTIN_PSUBB,
18987 IX86_BUILTIN_PSUBW,
18988 IX86_BUILTIN_PSUBD,
18989 IX86_BUILTIN_PSUBQ,
18990 IX86_BUILTIN_PSUBSB,
18991 IX86_BUILTIN_PSUBSW,
18992 IX86_BUILTIN_PSUBUSB,
18993 IX86_BUILTIN_PSUBUSW,
18996 IX86_BUILTIN_PANDN,
19000 IX86_BUILTIN_PAVGB,
19001 IX86_BUILTIN_PAVGW,
19003 IX86_BUILTIN_PCMPEQB,
19004 IX86_BUILTIN_PCMPEQW,
19005 IX86_BUILTIN_PCMPEQD,
19006 IX86_BUILTIN_PCMPGTB,
19007 IX86_BUILTIN_PCMPGTW,
19008 IX86_BUILTIN_PCMPGTD,
19010 IX86_BUILTIN_PMADDWD,
19012 IX86_BUILTIN_PMAXSW,
19013 IX86_BUILTIN_PMAXUB,
19014 IX86_BUILTIN_PMINSW,
19015 IX86_BUILTIN_PMINUB,
19017 IX86_BUILTIN_PMULHUW,
19018 IX86_BUILTIN_PMULHW,
19019 IX86_BUILTIN_PMULLW,
19021 IX86_BUILTIN_PSADBW,
19022 IX86_BUILTIN_PSHUFW,
19024 IX86_BUILTIN_PSLLW,
19025 IX86_BUILTIN_PSLLD,
19026 IX86_BUILTIN_PSLLQ,
19027 IX86_BUILTIN_PSRAW,
19028 IX86_BUILTIN_PSRAD,
19029 IX86_BUILTIN_PSRLW,
19030 IX86_BUILTIN_PSRLD,
19031 IX86_BUILTIN_PSRLQ,
19032 IX86_BUILTIN_PSLLWI,
19033 IX86_BUILTIN_PSLLDI,
19034 IX86_BUILTIN_PSLLQI,
19035 IX86_BUILTIN_PSRAWI,
19036 IX86_BUILTIN_PSRADI,
19037 IX86_BUILTIN_PSRLWI,
19038 IX86_BUILTIN_PSRLDI,
19039 IX86_BUILTIN_PSRLQI,
19041 IX86_BUILTIN_PUNPCKHBW,
19042 IX86_BUILTIN_PUNPCKHWD,
19043 IX86_BUILTIN_PUNPCKHDQ,
19044 IX86_BUILTIN_PUNPCKLBW,
19045 IX86_BUILTIN_PUNPCKLWD,
19046 IX86_BUILTIN_PUNPCKLDQ,
19048 IX86_BUILTIN_SHUFPS,
19050 IX86_BUILTIN_RCPPS,
19051 IX86_BUILTIN_RCPSS,
19052 IX86_BUILTIN_RSQRTPS,
19053 IX86_BUILTIN_RSQRTPS_NR,
19054 IX86_BUILTIN_RSQRTSS,
19055 IX86_BUILTIN_RSQRTF,
19056 IX86_BUILTIN_SQRTPS,
19057 IX86_BUILTIN_SQRTPS_NR,
19058 IX86_BUILTIN_SQRTSS,
19060 IX86_BUILTIN_UNPCKHPS,
19061 IX86_BUILTIN_UNPCKLPS,
19063 IX86_BUILTIN_ANDPS,
19064 IX86_BUILTIN_ANDNPS,
19066 IX86_BUILTIN_XORPS,
19069 IX86_BUILTIN_LDMXCSR,
19070 IX86_BUILTIN_STMXCSR,
19071 IX86_BUILTIN_SFENCE,
19073 /* 3DNow! Original */
19074 IX86_BUILTIN_FEMMS,
19075 IX86_BUILTIN_PAVGUSB,
19076 IX86_BUILTIN_PF2ID,
19077 IX86_BUILTIN_PFACC,
19078 IX86_BUILTIN_PFADD,
19079 IX86_BUILTIN_PFCMPEQ,
19080 IX86_BUILTIN_PFCMPGE,
19081 IX86_BUILTIN_PFCMPGT,
19082 IX86_BUILTIN_PFMAX,
19083 IX86_BUILTIN_PFMIN,
19084 IX86_BUILTIN_PFMUL,
19085 IX86_BUILTIN_PFRCP,
19086 IX86_BUILTIN_PFRCPIT1,
19087 IX86_BUILTIN_PFRCPIT2,
19088 IX86_BUILTIN_PFRSQIT1,
19089 IX86_BUILTIN_PFRSQRT,
19090 IX86_BUILTIN_PFSUB,
19091 IX86_BUILTIN_PFSUBR,
19092 IX86_BUILTIN_PI2FD,
19093 IX86_BUILTIN_PMULHRW,
19095 /* 3DNow! Athlon Extensions */
19096 IX86_BUILTIN_PF2IW,
19097 IX86_BUILTIN_PFNACC,
19098 IX86_BUILTIN_PFPNACC,
19099 IX86_BUILTIN_PI2FW,
19100 IX86_BUILTIN_PSWAPDSI,
19101 IX86_BUILTIN_PSWAPDSF,
19104 IX86_BUILTIN_ADDPD,
19105 IX86_BUILTIN_ADDSD,
19106 IX86_BUILTIN_DIVPD,
19107 IX86_BUILTIN_DIVSD,
19108 IX86_BUILTIN_MULPD,
19109 IX86_BUILTIN_MULSD,
19110 IX86_BUILTIN_SUBPD,
19111 IX86_BUILTIN_SUBSD,
19113 IX86_BUILTIN_CMPEQPD,
19114 IX86_BUILTIN_CMPLTPD,
19115 IX86_BUILTIN_CMPLEPD,
19116 IX86_BUILTIN_CMPGTPD,
19117 IX86_BUILTIN_CMPGEPD,
19118 IX86_BUILTIN_CMPNEQPD,
19119 IX86_BUILTIN_CMPNLTPD,
19120 IX86_BUILTIN_CMPNLEPD,
19121 IX86_BUILTIN_CMPNGTPD,
19122 IX86_BUILTIN_CMPNGEPD,
19123 IX86_BUILTIN_CMPORDPD,
19124 IX86_BUILTIN_CMPUNORDPD,
19125 IX86_BUILTIN_CMPEQSD,
19126 IX86_BUILTIN_CMPLTSD,
19127 IX86_BUILTIN_CMPLESD,
19128 IX86_BUILTIN_CMPNEQSD,
19129 IX86_BUILTIN_CMPNLTSD,
19130 IX86_BUILTIN_CMPNLESD,
19131 IX86_BUILTIN_CMPORDSD,
19132 IX86_BUILTIN_CMPUNORDSD,
19134 IX86_BUILTIN_COMIEQSD,
19135 IX86_BUILTIN_COMILTSD,
19136 IX86_BUILTIN_COMILESD,
19137 IX86_BUILTIN_COMIGTSD,
19138 IX86_BUILTIN_COMIGESD,
19139 IX86_BUILTIN_COMINEQSD,
19140 IX86_BUILTIN_UCOMIEQSD,
19141 IX86_BUILTIN_UCOMILTSD,
19142 IX86_BUILTIN_UCOMILESD,
19143 IX86_BUILTIN_UCOMIGTSD,
19144 IX86_BUILTIN_UCOMIGESD,
19145 IX86_BUILTIN_UCOMINEQSD,
19147 IX86_BUILTIN_MAXPD,
19148 IX86_BUILTIN_MAXSD,
19149 IX86_BUILTIN_MINPD,
19150 IX86_BUILTIN_MINSD,
19152 IX86_BUILTIN_ANDPD,
19153 IX86_BUILTIN_ANDNPD,
19155 IX86_BUILTIN_XORPD,
19157 IX86_BUILTIN_SQRTPD,
19158 IX86_BUILTIN_SQRTSD,
19160 IX86_BUILTIN_UNPCKHPD,
19161 IX86_BUILTIN_UNPCKLPD,
19163 IX86_BUILTIN_SHUFPD,
19165 IX86_BUILTIN_LOADUPD,
19166 IX86_BUILTIN_STOREUPD,
19167 IX86_BUILTIN_MOVSD,
19169 IX86_BUILTIN_LOADHPD,
19170 IX86_BUILTIN_LOADLPD,
19172 IX86_BUILTIN_CVTDQ2PD,
19173 IX86_BUILTIN_CVTDQ2PS,
19175 IX86_BUILTIN_CVTPD2DQ,
19176 IX86_BUILTIN_CVTPD2PI,
19177 IX86_BUILTIN_CVTPD2PS,
19178 IX86_BUILTIN_CVTTPD2DQ,
19179 IX86_BUILTIN_CVTTPD2PI,
19181 IX86_BUILTIN_CVTPI2PD,
19182 IX86_BUILTIN_CVTSI2SD,
19183 IX86_BUILTIN_CVTSI642SD,
19185 IX86_BUILTIN_CVTSD2SI,
19186 IX86_BUILTIN_CVTSD2SI64,
19187 IX86_BUILTIN_CVTSD2SS,
19188 IX86_BUILTIN_CVTSS2SD,
19189 IX86_BUILTIN_CVTTSD2SI,
19190 IX86_BUILTIN_CVTTSD2SI64,
19192 IX86_BUILTIN_CVTPS2DQ,
19193 IX86_BUILTIN_CVTPS2PD,
19194 IX86_BUILTIN_CVTTPS2DQ,
19196 IX86_BUILTIN_MOVNTI,
19197 IX86_BUILTIN_MOVNTPD,
19198 IX86_BUILTIN_MOVNTDQ,
19200 IX86_BUILTIN_MOVQ128,
19203 IX86_BUILTIN_MASKMOVDQU,
19204 IX86_BUILTIN_MOVMSKPD,
19205 IX86_BUILTIN_PMOVMSKB128,
19207 IX86_BUILTIN_PACKSSWB128,
19208 IX86_BUILTIN_PACKSSDW128,
19209 IX86_BUILTIN_PACKUSWB128,
19211 IX86_BUILTIN_PADDB128,
19212 IX86_BUILTIN_PADDW128,
19213 IX86_BUILTIN_PADDD128,
19214 IX86_BUILTIN_PADDQ128,
19215 IX86_BUILTIN_PADDSB128,
19216 IX86_BUILTIN_PADDSW128,
19217 IX86_BUILTIN_PADDUSB128,
19218 IX86_BUILTIN_PADDUSW128,
19219 IX86_BUILTIN_PSUBB128,
19220 IX86_BUILTIN_PSUBW128,
19221 IX86_BUILTIN_PSUBD128,
19222 IX86_BUILTIN_PSUBQ128,
19223 IX86_BUILTIN_PSUBSB128,
19224 IX86_BUILTIN_PSUBSW128,
19225 IX86_BUILTIN_PSUBUSB128,
19226 IX86_BUILTIN_PSUBUSW128,
19228 IX86_BUILTIN_PAND128,
19229 IX86_BUILTIN_PANDN128,
19230 IX86_BUILTIN_POR128,
19231 IX86_BUILTIN_PXOR128,
19233 IX86_BUILTIN_PAVGB128,
19234 IX86_BUILTIN_PAVGW128,
19236 IX86_BUILTIN_PCMPEQB128,
19237 IX86_BUILTIN_PCMPEQW128,
19238 IX86_BUILTIN_PCMPEQD128,
19239 IX86_BUILTIN_PCMPGTB128,
19240 IX86_BUILTIN_PCMPGTW128,
19241 IX86_BUILTIN_PCMPGTD128,
19243 IX86_BUILTIN_PMADDWD128,
19245 IX86_BUILTIN_PMAXSW128,
19246 IX86_BUILTIN_PMAXUB128,
19247 IX86_BUILTIN_PMINSW128,
19248 IX86_BUILTIN_PMINUB128,
19250 IX86_BUILTIN_PMULUDQ,
19251 IX86_BUILTIN_PMULUDQ128,
19252 IX86_BUILTIN_PMULHUW128,
19253 IX86_BUILTIN_PMULHW128,
19254 IX86_BUILTIN_PMULLW128,
19256 IX86_BUILTIN_PSADBW128,
19257 IX86_BUILTIN_PSHUFHW,
19258 IX86_BUILTIN_PSHUFLW,
19259 IX86_BUILTIN_PSHUFD,
19261 IX86_BUILTIN_PSLLDQI128,
19262 IX86_BUILTIN_PSLLWI128,
19263 IX86_BUILTIN_PSLLDI128,
19264 IX86_BUILTIN_PSLLQI128,
19265 IX86_BUILTIN_PSRAWI128,
19266 IX86_BUILTIN_PSRADI128,
19267 IX86_BUILTIN_PSRLDQI128,
19268 IX86_BUILTIN_PSRLWI128,
19269 IX86_BUILTIN_PSRLDI128,
19270 IX86_BUILTIN_PSRLQI128,
19272 IX86_BUILTIN_PSLLDQ128,
19273 IX86_BUILTIN_PSLLW128,
19274 IX86_BUILTIN_PSLLD128,
19275 IX86_BUILTIN_PSLLQ128,
19276 IX86_BUILTIN_PSRAW128,
19277 IX86_BUILTIN_PSRAD128,
19278 IX86_BUILTIN_PSRLW128,
19279 IX86_BUILTIN_PSRLD128,
19280 IX86_BUILTIN_PSRLQ128,
19282 IX86_BUILTIN_PUNPCKHBW128,
19283 IX86_BUILTIN_PUNPCKHWD128,
19284 IX86_BUILTIN_PUNPCKHDQ128,
19285 IX86_BUILTIN_PUNPCKHQDQ128,
19286 IX86_BUILTIN_PUNPCKLBW128,
19287 IX86_BUILTIN_PUNPCKLWD128,
19288 IX86_BUILTIN_PUNPCKLDQ128,
19289 IX86_BUILTIN_PUNPCKLQDQ128,
19291 IX86_BUILTIN_CLFLUSH,
19292 IX86_BUILTIN_MFENCE,
19293 IX86_BUILTIN_LFENCE,
19296 IX86_BUILTIN_ADDSUBPS,
19297 IX86_BUILTIN_HADDPS,
19298 IX86_BUILTIN_HSUBPS,
19299 IX86_BUILTIN_MOVSHDUP,
19300 IX86_BUILTIN_MOVSLDUP,
19301 IX86_BUILTIN_ADDSUBPD,
19302 IX86_BUILTIN_HADDPD,
19303 IX86_BUILTIN_HSUBPD,
19304 IX86_BUILTIN_LDDQU,
19306 IX86_BUILTIN_MONITOR,
19307 IX86_BUILTIN_MWAIT,
19310 IX86_BUILTIN_PHADDW,
19311 IX86_BUILTIN_PHADDD,
19312 IX86_BUILTIN_PHADDSW,
19313 IX86_BUILTIN_PHSUBW,
19314 IX86_BUILTIN_PHSUBD,
19315 IX86_BUILTIN_PHSUBSW,
19316 IX86_BUILTIN_PMADDUBSW,
19317 IX86_BUILTIN_PMULHRSW,
19318 IX86_BUILTIN_PSHUFB,
19319 IX86_BUILTIN_PSIGNB,
19320 IX86_BUILTIN_PSIGNW,
19321 IX86_BUILTIN_PSIGND,
19322 IX86_BUILTIN_PALIGNR,
19323 IX86_BUILTIN_PABSB,
19324 IX86_BUILTIN_PABSW,
19325 IX86_BUILTIN_PABSD,
19327 IX86_BUILTIN_PHADDW128,
19328 IX86_BUILTIN_PHADDD128,
19329 IX86_BUILTIN_PHADDSW128,
19330 IX86_BUILTIN_PHSUBW128,
19331 IX86_BUILTIN_PHSUBD128,
19332 IX86_BUILTIN_PHSUBSW128,
19333 IX86_BUILTIN_PMADDUBSW128,
19334 IX86_BUILTIN_PMULHRSW128,
19335 IX86_BUILTIN_PSHUFB128,
19336 IX86_BUILTIN_PSIGNB128,
19337 IX86_BUILTIN_PSIGNW128,
19338 IX86_BUILTIN_PSIGND128,
19339 IX86_BUILTIN_PALIGNR128,
19340 IX86_BUILTIN_PABSB128,
19341 IX86_BUILTIN_PABSW128,
19342 IX86_BUILTIN_PABSD128,
19344 /* AMDFAM10 - SSE4A New Instructions. */
19345 IX86_BUILTIN_MOVNTSD,
19346 IX86_BUILTIN_MOVNTSS,
19347 IX86_BUILTIN_EXTRQI,
19348 IX86_BUILTIN_EXTRQ,
19349 IX86_BUILTIN_INSERTQI,
19350 IX86_BUILTIN_INSERTQ,
19353 IX86_BUILTIN_BLENDPD,
19354 IX86_BUILTIN_BLENDPS,
19355 IX86_BUILTIN_BLENDVPD,
19356 IX86_BUILTIN_BLENDVPS,
19357 IX86_BUILTIN_PBLENDVB128,
19358 IX86_BUILTIN_PBLENDW128,
19363 IX86_BUILTIN_INSERTPS128,
19365 IX86_BUILTIN_MOVNTDQA,
19366 IX86_BUILTIN_MPSADBW128,
19367 IX86_BUILTIN_PACKUSDW128,
19368 IX86_BUILTIN_PCMPEQQ,
19369 IX86_BUILTIN_PHMINPOSUW128,
19371 IX86_BUILTIN_PMAXSB128,
19372 IX86_BUILTIN_PMAXSD128,
19373 IX86_BUILTIN_PMAXUD128,
19374 IX86_BUILTIN_PMAXUW128,
19376 IX86_BUILTIN_PMINSB128,
19377 IX86_BUILTIN_PMINSD128,
19378 IX86_BUILTIN_PMINUD128,
19379 IX86_BUILTIN_PMINUW128,
19381 IX86_BUILTIN_PMOVSXBW128,
19382 IX86_BUILTIN_PMOVSXBD128,
19383 IX86_BUILTIN_PMOVSXBQ128,
19384 IX86_BUILTIN_PMOVSXWD128,
19385 IX86_BUILTIN_PMOVSXWQ128,
19386 IX86_BUILTIN_PMOVSXDQ128,
19388 IX86_BUILTIN_PMOVZXBW128,
19389 IX86_BUILTIN_PMOVZXBD128,
19390 IX86_BUILTIN_PMOVZXBQ128,
19391 IX86_BUILTIN_PMOVZXWD128,
19392 IX86_BUILTIN_PMOVZXWQ128,
19393 IX86_BUILTIN_PMOVZXDQ128,
19395 IX86_BUILTIN_PMULDQ128,
19396 IX86_BUILTIN_PMULLD128,
19398 IX86_BUILTIN_ROUNDPD,
19399 IX86_BUILTIN_ROUNDPS,
19400 IX86_BUILTIN_ROUNDSD,
19401 IX86_BUILTIN_ROUNDSS,
19403 IX86_BUILTIN_PTESTZ,
19404 IX86_BUILTIN_PTESTC,
19405 IX86_BUILTIN_PTESTNZC,
19407 IX86_BUILTIN_VEC_INIT_V2SI,
19408 IX86_BUILTIN_VEC_INIT_V4HI,
19409 IX86_BUILTIN_VEC_INIT_V8QI,
19410 IX86_BUILTIN_VEC_EXT_V2DF,
19411 IX86_BUILTIN_VEC_EXT_V2DI,
19412 IX86_BUILTIN_VEC_EXT_V4SF,
19413 IX86_BUILTIN_VEC_EXT_V4SI,
19414 IX86_BUILTIN_VEC_EXT_V8HI,
19415 IX86_BUILTIN_VEC_EXT_V2SI,
19416 IX86_BUILTIN_VEC_EXT_V4HI,
19417 IX86_BUILTIN_VEC_EXT_V16QI,
19418 IX86_BUILTIN_VEC_SET_V2DI,
19419 IX86_BUILTIN_VEC_SET_V4SF,
19420 IX86_BUILTIN_VEC_SET_V4SI,
19421 IX86_BUILTIN_VEC_SET_V8HI,
19422 IX86_BUILTIN_VEC_SET_V4HI,
19423 IX86_BUILTIN_VEC_SET_V16QI,
19425 IX86_BUILTIN_VEC_PACK_SFIX,
19428 IX86_BUILTIN_CRC32QI,
19429 IX86_BUILTIN_CRC32HI,
19430 IX86_BUILTIN_CRC32SI,
19431 IX86_BUILTIN_CRC32DI,
19433 IX86_BUILTIN_PCMPESTRI128,
19434 IX86_BUILTIN_PCMPESTRM128,
19435 IX86_BUILTIN_PCMPESTRA128,
19436 IX86_BUILTIN_PCMPESTRC128,
19437 IX86_BUILTIN_PCMPESTRO128,
19438 IX86_BUILTIN_PCMPESTRS128,
19439 IX86_BUILTIN_PCMPESTRZ128,
19440 IX86_BUILTIN_PCMPISTRI128,
19441 IX86_BUILTIN_PCMPISTRM128,
19442 IX86_BUILTIN_PCMPISTRA128,
19443 IX86_BUILTIN_PCMPISTRC128,
19444 IX86_BUILTIN_PCMPISTRO128,
19445 IX86_BUILTIN_PCMPISTRS128,
19446 IX86_BUILTIN_PCMPISTRZ128,
19448 IX86_BUILTIN_PCMPGTQ,
19450 /* AES instructions */
19451 IX86_BUILTIN_AESENC128,
19452 IX86_BUILTIN_AESENCLAST128,
19453 IX86_BUILTIN_AESDEC128,
19454 IX86_BUILTIN_AESDECLAST128,
19455 IX86_BUILTIN_AESIMC128,
19456 IX86_BUILTIN_AESKEYGENASSIST128,
19458 /* PCLMUL instruction */
19459 IX86_BUILTIN_PCLMULQDQ128,
19462 IX86_BUILTIN_ADDPD256,
19463 IX86_BUILTIN_ADDPS256,
19464 IX86_BUILTIN_ADDSUBPD256,
19465 IX86_BUILTIN_ADDSUBPS256,
19466 IX86_BUILTIN_ANDPD256,
19467 IX86_BUILTIN_ANDPS256,
19468 IX86_BUILTIN_ANDNPD256,
19469 IX86_BUILTIN_ANDNPS256,
19470 IX86_BUILTIN_BLENDPD256,
19471 IX86_BUILTIN_BLENDPS256,
19472 IX86_BUILTIN_BLENDVPD256,
19473 IX86_BUILTIN_BLENDVPS256,
19474 IX86_BUILTIN_DIVPD256,
19475 IX86_BUILTIN_DIVPS256,
19476 IX86_BUILTIN_DPPS256,
19477 IX86_BUILTIN_HADDPD256,
19478 IX86_BUILTIN_HADDPS256,
19479 IX86_BUILTIN_HSUBPD256,
19480 IX86_BUILTIN_HSUBPS256,
19481 IX86_BUILTIN_MAXPD256,
19482 IX86_BUILTIN_MAXPS256,
19483 IX86_BUILTIN_MINPD256,
19484 IX86_BUILTIN_MINPS256,
19485 IX86_BUILTIN_MULPD256,
19486 IX86_BUILTIN_MULPS256,
19487 IX86_BUILTIN_ORPD256,
19488 IX86_BUILTIN_ORPS256,
19489 IX86_BUILTIN_SHUFPD256,
19490 IX86_BUILTIN_SHUFPS256,
19491 IX86_BUILTIN_SUBPD256,
19492 IX86_BUILTIN_SUBPS256,
19493 IX86_BUILTIN_XORPD256,
19494 IX86_BUILTIN_XORPS256,
19495 IX86_BUILTIN_CMPSD,
19496 IX86_BUILTIN_CMPSS,
19497 IX86_BUILTIN_CMPPD,
19498 IX86_BUILTIN_CMPPS,
19499 IX86_BUILTIN_CMPPD256,
19500 IX86_BUILTIN_CMPPS256,
19501 IX86_BUILTIN_CVTDQ2PD256,
19502 IX86_BUILTIN_CVTDQ2PS256,
19503 IX86_BUILTIN_CVTPD2PS256,
19504 IX86_BUILTIN_CVTPS2DQ256,
19505 IX86_BUILTIN_CVTPS2PD256,
19506 IX86_BUILTIN_CVTTPD2DQ256,
19507 IX86_BUILTIN_CVTPD2DQ256,
19508 IX86_BUILTIN_CVTTPS2DQ256,
19509 IX86_BUILTIN_EXTRACTF128PD256,
19510 IX86_BUILTIN_EXTRACTF128PS256,
19511 IX86_BUILTIN_EXTRACTF128SI256,
19512 IX86_BUILTIN_VZEROALL,
19513 IX86_BUILTIN_VZEROUPPER,
19514 IX86_BUILTIN_VZEROUPPER_REX64,
19515 IX86_BUILTIN_VPERMILVARPD,
19516 IX86_BUILTIN_VPERMILVARPS,
19517 IX86_BUILTIN_VPERMILVARPD256,
19518 IX86_BUILTIN_VPERMILVARPS256,
19519 IX86_BUILTIN_VPERMILPD,
19520 IX86_BUILTIN_VPERMILPS,
19521 IX86_BUILTIN_VPERMILPD256,
19522 IX86_BUILTIN_VPERMILPS256,
19523 IX86_BUILTIN_VPERMIL2PD,
19524 IX86_BUILTIN_VPERMIL2PS,
19525 IX86_BUILTIN_VPERMIL2PD256,
19526 IX86_BUILTIN_VPERMIL2PS256,
19527 IX86_BUILTIN_VPERM2F128PD256,
19528 IX86_BUILTIN_VPERM2F128PS256,
19529 IX86_BUILTIN_VPERM2F128SI256,
19530 IX86_BUILTIN_VBROADCASTSS,
19531 IX86_BUILTIN_VBROADCASTSD256,
19532 IX86_BUILTIN_VBROADCASTSS256,
19533 IX86_BUILTIN_VBROADCASTPD256,
19534 IX86_BUILTIN_VBROADCASTPS256,
19535 IX86_BUILTIN_VINSERTF128PD256,
19536 IX86_BUILTIN_VINSERTF128PS256,
19537 IX86_BUILTIN_VINSERTF128SI256,
19538 IX86_BUILTIN_LOADUPD256,
19539 IX86_BUILTIN_LOADUPS256,
19540 IX86_BUILTIN_STOREUPD256,
19541 IX86_BUILTIN_STOREUPS256,
19542 IX86_BUILTIN_LDDQU256,
19543 IX86_BUILTIN_LOADDQU256,
19544 IX86_BUILTIN_STOREDQU256,
19545 IX86_BUILTIN_MASKLOADPD,
19546 IX86_BUILTIN_MASKLOADPS,
19547 IX86_BUILTIN_MASKSTOREPD,
19548 IX86_BUILTIN_MASKSTOREPS,
19549 IX86_BUILTIN_MASKLOADPD256,
19550 IX86_BUILTIN_MASKLOADPS256,
19551 IX86_BUILTIN_MASKSTOREPD256,
19552 IX86_BUILTIN_MASKSTOREPS256,
19553 IX86_BUILTIN_MOVSHDUP256,
19554 IX86_BUILTIN_MOVSLDUP256,
19555 IX86_BUILTIN_MOVDDUP256,
19557 IX86_BUILTIN_SQRTPD256,
19558 IX86_BUILTIN_SQRTPS256,
19559 IX86_BUILTIN_SQRTPS_NR256,
19560 IX86_BUILTIN_RSQRTPS256,
19561 IX86_BUILTIN_RSQRTPS_NR256,
19563 IX86_BUILTIN_RCPPS256,
19565 IX86_BUILTIN_ROUNDPD256,
19566 IX86_BUILTIN_ROUNDPS256,
19568 IX86_BUILTIN_UNPCKHPD256,
19569 IX86_BUILTIN_UNPCKLPD256,
19570 IX86_BUILTIN_UNPCKHPS256,
19571 IX86_BUILTIN_UNPCKLPS256,
19573 IX86_BUILTIN_SI256_SI,
19574 IX86_BUILTIN_PS256_PS,
19575 IX86_BUILTIN_PD256_PD,
19576 IX86_BUILTIN_SI_SI256,
19577 IX86_BUILTIN_PS_PS256,
19578 IX86_BUILTIN_PD_PD256,
19580 IX86_BUILTIN_VTESTZPD,
19581 IX86_BUILTIN_VTESTCPD,
19582 IX86_BUILTIN_VTESTNZCPD,
19583 IX86_BUILTIN_VTESTZPS,
19584 IX86_BUILTIN_VTESTCPS,
19585 IX86_BUILTIN_VTESTNZCPS,
19586 IX86_BUILTIN_VTESTZPD256,
19587 IX86_BUILTIN_VTESTCPD256,
19588 IX86_BUILTIN_VTESTNZCPD256,
19589 IX86_BUILTIN_VTESTZPS256,
19590 IX86_BUILTIN_VTESTCPS256,
19591 IX86_BUILTIN_VTESTNZCPS256,
19592 IX86_BUILTIN_PTESTZ256,
19593 IX86_BUILTIN_PTESTC256,
19594 IX86_BUILTIN_PTESTNZC256,
19596 IX86_BUILTIN_MOVMSKPD256,
19597 IX86_BUILTIN_MOVMSKPS256,
19599 /* TFmode support builtins. */
19601 IX86_BUILTIN_FABSQ,
19602 IX86_BUILTIN_COPYSIGNQ,
19604 /* SSE5 instructions */
19605 IX86_BUILTIN_FMADDSS,
19606 IX86_BUILTIN_FMADDSD,
19607 IX86_BUILTIN_FMADDPS,
19608 IX86_BUILTIN_FMADDPD,
19609 IX86_BUILTIN_FMSUBSS,
19610 IX86_BUILTIN_FMSUBSD,
19611 IX86_BUILTIN_FMSUBPS,
19612 IX86_BUILTIN_FMSUBPD,
19613 IX86_BUILTIN_FNMADDSS,
19614 IX86_BUILTIN_FNMADDSD,
19615 IX86_BUILTIN_FNMADDPS,
19616 IX86_BUILTIN_FNMADDPD,
19617 IX86_BUILTIN_FNMSUBSS,
19618 IX86_BUILTIN_FNMSUBSD,
19619 IX86_BUILTIN_FNMSUBPS,
19620 IX86_BUILTIN_FNMSUBPD,
19621 IX86_BUILTIN_PCMOV,
19622 IX86_BUILTIN_PCMOV_V2DI,
19623 IX86_BUILTIN_PCMOV_V4SI,
19624 IX86_BUILTIN_PCMOV_V8HI,
19625 IX86_BUILTIN_PCMOV_V16QI,
19626 IX86_BUILTIN_PCMOV_V4SF,
19627 IX86_BUILTIN_PCMOV_V2DF,
19628 IX86_BUILTIN_PPERM,
19629 IX86_BUILTIN_PERMPS,
19630 IX86_BUILTIN_PERMPD,
19631 IX86_BUILTIN_PMACSSWW,
19632 IX86_BUILTIN_PMACSWW,
19633 IX86_BUILTIN_PMACSSWD,
19634 IX86_BUILTIN_PMACSWD,
19635 IX86_BUILTIN_PMACSSDD,
19636 IX86_BUILTIN_PMACSDD,
19637 IX86_BUILTIN_PMACSSDQL,
19638 IX86_BUILTIN_PMACSSDQH,
19639 IX86_BUILTIN_PMACSDQL,
19640 IX86_BUILTIN_PMACSDQH,
19641 IX86_BUILTIN_PMADCSSWD,
19642 IX86_BUILTIN_PMADCSWD,
19643 IX86_BUILTIN_PHADDBW,
19644 IX86_BUILTIN_PHADDBD,
19645 IX86_BUILTIN_PHADDBQ,
19646 IX86_BUILTIN_PHADDWD,
19647 IX86_BUILTIN_PHADDWQ,
19648 IX86_BUILTIN_PHADDDQ,
19649 IX86_BUILTIN_PHADDUBW,
19650 IX86_BUILTIN_PHADDUBD,
19651 IX86_BUILTIN_PHADDUBQ,
19652 IX86_BUILTIN_PHADDUWD,
19653 IX86_BUILTIN_PHADDUWQ,
19654 IX86_BUILTIN_PHADDUDQ,
19655 IX86_BUILTIN_PHSUBBW,
19656 IX86_BUILTIN_PHSUBWD,
19657 IX86_BUILTIN_PHSUBDQ,
19658 IX86_BUILTIN_PROTB,
19659 IX86_BUILTIN_PROTW,
19660 IX86_BUILTIN_PROTD,
19661 IX86_BUILTIN_PROTQ,
19662 IX86_BUILTIN_PROTB_IMM,
19663 IX86_BUILTIN_PROTW_IMM,
19664 IX86_BUILTIN_PROTD_IMM,
19665 IX86_BUILTIN_PROTQ_IMM,
19666 IX86_BUILTIN_PSHLB,
19667 IX86_BUILTIN_PSHLW,
19668 IX86_BUILTIN_PSHLD,
19669 IX86_BUILTIN_PSHLQ,
19670 IX86_BUILTIN_PSHAB,
19671 IX86_BUILTIN_PSHAW,
19672 IX86_BUILTIN_PSHAD,
19673 IX86_BUILTIN_PSHAQ,
19674 IX86_BUILTIN_FRCZSS,
19675 IX86_BUILTIN_FRCZSD,
19676 IX86_BUILTIN_FRCZPS,
19677 IX86_BUILTIN_FRCZPD,
19678 IX86_BUILTIN_CVTPH2PS,
19679 IX86_BUILTIN_CVTPS2PH,
19681 IX86_BUILTIN_COMEQSS,
19682 IX86_BUILTIN_COMNESS,
19683 IX86_BUILTIN_COMLTSS,
19684 IX86_BUILTIN_COMLESS,
19685 IX86_BUILTIN_COMGTSS,
19686 IX86_BUILTIN_COMGESS,
19687 IX86_BUILTIN_COMUEQSS,
19688 IX86_BUILTIN_COMUNESS,
19689 IX86_BUILTIN_COMULTSS,
19690 IX86_BUILTIN_COMULESS,
19691 IX86_BUILTIN_COMUGTSS,
19692 IX86_BUILTIN_COMUGESS,
19693 IX86_BUILTIN_COMORDSS,
19694 IX86_BUILTIN_COMUNORDSS,
19695 IX86_BUILTIN_COMFALSESS,
19696 IX86_BUILTIN_COMTRUESS,
19698 IX86_BUILTIN_COMEQSD,
19699 IX86_BUILTIN_COMNESD,
19700 IX86_BUILTIN_COMLTSD,
19701 IX86_BUILTIN_COMLESD,
19702 IX86_BUILTIN_COMGTSD,
19703 IX86_BUILTIN_COMGESD,
19704 IX86_BUILTIN_COMUEQSD,
19705 IX86_BUILTIN_COMUNESD,
19706 IX86_BUILTIN_COMULTSD,
19707 IX86_BUILTIN_COMULESD,
19708 IX86_BUILTIN_COMUGTSD,
19709 IX86_BUILTIN_COMUGESD,
19710 IX86_BUILTIN_COMORDSD,
19711 IX86_BUILTIN_COMUNORDSD,
19712 IX86_BUILTIN_COMFALSESD,
19713 IX86_BUILTIN_COMTRUESD,
19715 IX86_BUILTIN_COMEQPS,
19716 IX86_BUILTIN_COMNEPS,
19717 IX86_BUILTIN_COMLTPS,
19718 IX86_BUILTIN_COMLEPS,
19719 IX86_BUILTIN_COMGTPS,
19720 IX86_BUILTIN_COMGEPS,
19721 IX86_BUILTIN_COMUEQPS,
19722 IX86_BUILTIN_COMUNEPS,
19723 IX86_BUILTIN_COMULTPS,
19724 IX86_BUILTIN_COMULEPS,
19725 IX86_BUILTIN_COMUGTPS,
19726 IX86_BUILTIN_COMUGEPS,
19727 IX86_BUILTIN_COMORDPS,
19728 IX86_BUILTIN_COMUNORDPS,
19729 IX86_BUILTIN_COMFALSEPS,
19730 IX86_BUILTIN_COMTRUEPS,
19732 IX86_BUILTIN_COMEQPD,
19733 IX86_BUILTIN_COMNEPD,
19734 IX86_BUILTIN_COMLTPD,
19735 IX86_BUILTIN_COMLEPD,
19736 IX86_BUILTIN_COMGTPD,
19737 IX86_BUILTIN_COMGEPD,
19738 IX86_BUILTIN_COMUEQPD,
19739 IX86_BUILTIN_COMUNEPD,
19740 IX86_BUILTIN_COMULTPD,
19741 IX86_BUILTIN_COMULEPD,
19742 IX86_BUILTIN_COMUGTPD,
19743 IX86_BUILTIN_COMUGEPD,
19744 IX86_BUILTIN_COMORDPD,
19745 IX86_BUILTIN_COMUNORDPD,
19746 IX86_BUILTIN_COMFALSEPD,
19747 IX86_BUILTIN_COMTRUEPD,
19749 IX86_BUILTIN_PCOMEQUB,
19750 IX86_BUILTIN_PCOMNEUB,
19751 IX86_BUILTIN_PCOMLTUB,
19752 IX86_BUILTIN_PCOMLEUB,
19753 IX86_BUILTIN_PCOMGTUB,
19754 IX86_BUILTIN_PCOMGEUB,
19755 IX86_BUILTIN_PCOMFALSEUB,
19756 IX86_BUILTIN_PCOMTRUEUB,
19757 IX86_BUILTIN_PCOMEQUW,
19758 IX86_BUILTIN_PCOMNEUW,
19759 IX86_BUILTIN_PCOMLTUW,
19760 IX86_BUILTIN_PCOMLEUW,
19761 IX86_BUILTIN_PCOMGTUW,
19762 IX86_BUILTIN_PCOMGEUW,
19763 IX86_BUILTIN_PCOMFALSEUW,
19764 IX86_BUILTIN_PCOMTRUEUW,
19765 IX86_BUILTIN_PCOMEQUD,
19766 IX86_BUILTIN_PCOMNEUD,
19767 IX86_BUILTIN_PCOMLTUD,
19768 IX86_BUILTIN_PCOMLEUD,
19769 IX86_BUILTIN_PCOMGTUD,
19770 IX86_BUILTIN_PCOMGEUD,
19771 IX86_BUILTIN_PCOMFALSEUD,
19772 IX86_BUILTIN_PCOMTRUEUD,
19773 IX86_BUILTIN_PCOMEQUQ,
19774 IX86_BUILTIN_PCOMNEUQ,
19775 IX86_BUILTIN_PCOMLTUQ,
19776 IX86_BUILTIN_PCOMLEUQ,
19777 IX86_BUILTIN_PCOMGTUQ,
19778 IX86_BUILTIN_PCOMGEUQ,
19779 IX86_BUILTIN_PCOMFALSEUQ,
19780 IX86_BUILTIN_PCOMTRUEUQ,
19782 IX86_BUILTIN_PCOMEQB,
19783 IX86_BUILTIN_PCOMNEB,
19784 IX86_BUILTIN_PCOMLTB,
19785 IX86_BUILTIN_PCOMLEB,
19786 IX86_BUILTIN_PCOMGTB,
19787 IX86_BUILTIN_PCOMGEB,
19788 IX86_BUILTIN_PCOMFALSEB,
19789 IX86_BUILTIN_PCOMTRUEB,
19790 IX86_BUILTIN_PCOMEQW,
19791 IX86_BUILTIN_PCOMNEW,
19792 IX86_BUILTIN_PCOMLTW,
19793 IX86_BUILTIN_PCOMLEW,
19794 IX86_BUILTIN_PCOMGTW,
19795 IX86_BUILTIN_PCOMGEW,
19796 IX86_BUILTIN_PCOMFALSEW,
19797 IX86_BUILTIN_PCOMTRUEW,
19798 IX86_BUILTIN_PCOMEQD,
19799 IX86_BUILTIN_PCOMNED,
19800 IX86_BUILTIN_PCOMLTD,
19801 IX86_BUILTIN_PCOMLED,
19802 IX86_BUILTIN_PCOMGTD,
19803 IX86_BUILTIN_PCOMGED,
19804 IX86_BUILTIN_PCOMFALSED,
19805 IX86_BUILTIN_PCOMTRUED,
19806 IX86_BUILTIN_PCOMEQQ,
19807 IX86_BUILTIN_PCOMNEQ,
19808 IX86_BUILTIN_PCOMLTQ,
19809 IX86_BUILTIN_PCOMLEQ,
19810 IX86_BUILTIN_PCOMGTQ,
19811 IX86_BUILTIN_PCOMGEQ,
19812 IX86_BUILTIN_PCOMFALSEQ,
19813 IX86_BUILTIN_PCOMTRUEQ,
19818 /* Table for the ix86 builtin decls. */
19819 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
19821 /* Table of all of the builtin functions that are possible with different ISA's
19822 but are waiting to be built until a function is declared to use that
19824 struct builtin_isa GTY(())
19826 tree type; /* builtin type to use in the declaration */
19827 const char *name; /* function name */
19828 int isa; /* isa_flags this builtin is defined for */
19829 bool const_p; /* true if the declaration is constant */
19832 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
19835 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
19836 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
19837 * function decl in the ix86_builtins array. Returns the function decl or
19838 * NULL_TREE, if the builtin was not added.
19840 * If the front end has a special hook for builtin functions, delay adding
19841 * builtin functions that aren't in the current ISA until the ISA is changed
19842 * with function specific optimization. Doing so, can save about 300K for the
19843 * default compiler. When the builtin is expanded, check at that time whether
19846 * If the front end doesn't have a special hook, record all builtins, even if
19847 * it isn't an instruction set in the current ISA in case the user uses
19848 * function specific options for a different ISA, so that we don't get scope
19849 * errors if a builtin is added in the middle of a function scope. */
19852 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
19854 tree decl = NULL_TREE;
19856 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
19858 ix86_builtins_isa[(int) code].isa = mask;
19860 if ((mask & ix86_isa_flags) != 0
19861 || (lang_hooks.builtin_function
19862 == lang_hooks.builtin_function_ext_scope))
19865 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
19867 ix86_builtins[(int) code] = decl;
19868 ix86_builtins_isa[(int) code].type = NULL_TREE;
19872 ix86_builtins[(int) code] = NULL_TREE;
19873 ix86_builtins_isa[(int) code].const_p = false;
19874 ix86_builtins_isa[(int) code].type = type;
19875 ix86_builtins_isa[(int) code].name = name;
19882 /* Like def_builtin, but also marks the function decl "const". */
19885 def_builtin_const (int mask, const char *name, tree type,
19886 enum ix86_builtins code)
19888 tree decl = def_builtin (mask, name, type, code);
19890 TREE_READONLY (decl) = 1;
19892 ix86_builtins_isa[(int) code].const_p = true;
19897 /* Add any new builtin functions for a given ISA that may not have been
19898 declared. This saves a bit of space compared to adding all of the
19899 declarations to the tree, even if we didn't use them. */
19902 ix86_add_new_builtins (int isa)
19907 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
19909 if ((ix86_builtins_isa[i].isa & isa) != 0
19910 && ix86_builtins_isa[i].type != NULL_TREE)
19912 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
19913 ix86_builtins_isa[i].type,
19914 i, BUILT_IN_MD, NULL,
19917 ix86_builtins[i] = decl;
19918 ix86_builtins_isa[i].type = NULL_TREE;
19919 if (ix86_builtins_isa[i].const_p)
19920 TREE_READONLY (decl) = 1;
19925 /* Bits for builtin_description.flag. */
19927 /* Set when we don't support the comparison natively, and should
19928 swap_comparison in order to support it. */
19929 #define BUILTIN_DESC_SWAP_OPERANDS 1
19931 struct builtin_description
19933 const unsigned int mask;
19934 const enum insn_code icode;
19935 const char *const name;
19936 const enum ix86_builtins code;
19937 const enum rtx_code comparison;
19941 static const struct builtin_description bdesc_comi[] =
19943 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
19944 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
19945 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
19946 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
19947 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
19948 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
19949 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
19950 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
19951 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
19952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
19953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
19954 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
19955 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
19956 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
19957 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
19958 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
19959 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
19960 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
19961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
19962 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
19963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
19964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
19965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
19966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
19969 static const struct builtin_description bdesc_pcmpestr[] =
19972 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
19973 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
19974 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
19975 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
19976 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
19977 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
19978 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
19981 static const struct builtin_description bdesc_pcmpistr[] =
19984 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
19985 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
19986 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
19987 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
19988 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
19989 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
19990 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
19993 /* Special builtin types */
19994 enum ix86_special_builtin_type
19996 SPECIAL_FTYPE_UNKNOWN,
19998 V32QI_FTYPE_PCCHAR,
19999 V16QI_FTYPE_PCCHAR,
20001 V8SF_FTYPE_PCFLOAT,
20003 V4DF_FTYPE_PCDOUBLE,
20004 V4SF_FTYPE_PCFLOAT,
20005 V2DF_FTYPE_PCDOUBLE,
20006 V8SF_FTYPE_PCV8SF_V8SF,
20007 V4DF_FTYPE_PCV4DF_V4DF,
20008 V4SF_FTYPE_V4SF_PCV2SF,
20009 V4SF_FTYPE_PCV4SF_V4SF,
20010 V2DF_FTYPE_V2DF_PCDOUBLE,
20011 V2DF_FTYPE_PCV2DF_V2DF,
20013 VOID_FTYPE_PV2SF_V4SF,
20014 VOID_FTYPE_PV2DI_V2DI,
20015 VOID_FTYPE_PCHAR_V32QI,
20016 VOID_FTYPE_PCHAR_V16QI,
20017 VOID_FTYPE_PFLOAT_V8SF,
20018 VOID_FTYPE_PFLOAT_V4SF,
20019 VOID_FTYPE_PDOUBLE_V4DF,
20020 VOID_FTYPE_PDOUBLE_V2DF,
20022 VOID_FTYPE_PINT_INT,
20023 VOID_FTYPE_PV8SF_V8SF_V8SF,
20024 VOID_FTYPE_PV4DF_V4DF_V4DF,
20025 VOID_FTYPE_PV4SF_V4SF_V4SF,
20026 VOID_FTYPE_PV2DF_V2DF_V2DF
20029 /* Builtin types */
20030 enum ix86_builtin_type
20033 FLOAT128_FTYPE_FLOAT128,
20035 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20036 INT_FTYPE_V8SF_V8SF_PTEST,
20037 INT_FTYPE_V4DI_V4DI_PTEST,
20038 INT_FTYPE_V4DF_V4DF_PTEST,
20039 INT_FTYPE_V4SF_V4SF_PTEST,
20040 INT_FTYPE_V2DI_V2DI_PTEST,
20041 INT_FTYPE_V2DF_V2DF_PTEST,
20073 V4SF_FTYPE_V4SF_VEC_MERGE,
20082 V2DF_FTYPE_V2DF_VEC_MERGE,
20093 V16QI_FTYPE_V16QI_V16QI,
20094 V16QI_FTYPE_V8HI_V8HI,
20095 V8QI_FTYPE_V8QI_V8QI,
20096 V8QI_FTYPE_V4HI_V4HI,
20097 V8HI_FTYPE_V8HI_V8HI,
20098 V8HI_FTYPE_V8HI_V8HI_COUNT,
20099 V8HI_FTYPE_V16QI_V16QI,
20100 V8HI_FTYPE_V4SI_V4SI,
20101 V8HI_FTYPE_V8HI_SI_COUNT,
20102 V8SF_FTYPE_V8SF_V8SF,
20103 V8SF_FTYPE_V8SF_V8SI,
20104 V4SI_FTYPE_V4SI_V4SI,
20105 V4SI_FTYPE_V4SI_V4SI_COUNT,
20106 V4SI_FTYPE_V8HI_V8HI,
20107 V4SI_FTYPE_V4SF_V4SF,
20108 V4SI_FTYPE_V2DF_V2DF,
20109 V4SI_FTYPE_V4SI_SI_COUNT,
20110 V4HI_FTYPE_V4HI_V4HI,
20111 V4HI_FTYPE_V4HI_V4HI_COUNT,
20112 V4HI_FTYPE_V8QI_V8QI,
20113 V4HI_FTYPE_V2SI_V2SI,
20114 V4HI_FTYPE_V4HI_SI_COUNT,
20115 V4DF_FTYPE_V4DF_V4DF,
20116 V4DF_FTYPE_V4DF_V4DI,
20117 V4SF_FTYPE_V4SF_V4SF,
20118 V4SF_FTYPE_V4SF_V4SF_SWAP,
20119 V4SF_FTYPE_V4SF_V4SI,
20120 V4SF_FTYPE_V4SF_V2SI,
20121 V4SF_FTYPE_V4SF_V2DF,
20122 V4SF_FTYPE_V4SF_DI,
20123 V4SF_FTYPE_V4SF_SI,
20124 V2DI_FTYPE_V2DI_V2DI,
20125 V2DI_FTYPE_V2DI_V2DI_COUNT,
20126 V2DI_FTYPE_V16QI_V16QI,
20127 V2DI_FTYPE_V4SI_V4SI,
20128 V2DI_FTYPE_V2DI_V16QI,
20129 V2DI_FTYPE_V2DF_V2DF,
20130 V2DI_FTYPE_V2DI_SI_COUNT,
20131 V2SI_FTYPE_V2SI_V2SI,
20132 V2SI_FTYPE_V2SI_V2SI_COUNT,
20133 V2SI_FTYPE_V4HI_V4HI,
20134 V2SI_FTYPE_V2SF_V2SF,
20135 V2SI_FTYPE_V2SI_SI_COUNT,
20136 V2DF_FTYPE_V2DF_V2DF,
20137 V2DF_FTYPE_V2DF_V2DF_SWAP,
20138 V2DF_FTYPE_V2DF_V4SF,
20139 V2DF_FTYPE_V2DF_V2DI,
20140 V2DF_FTYPE_V2DF_DI,
20141 V2DF_FTYPE_V2DF_SI,
20142 V2SF_FTYPE_V2SF_V2SF,
20143 V1DI_FTYPE_V1DI_V1DI,
20144 V1DI_FTYPE_V1DI_V1DI_COUNT,
20145 V1DI_FTYPE_V8QI_V8QI,
20146 V1DI_FTYPE_V2SI_V2SI,
20147 V1DI_FTYPE_V1DI_SI_COUNT,
20148 UINT64_FTYPE_UINT64_UINT64,
20149 UINT_FTYPE_UINT_UINT,
20150 UINT_FTYPE_UINT_USHORT,
20151 UINT_FTYPE_UINT_UCHAR,
20152 V8HI_FTYPE_V8HI_INT,
20153 V4SI_FTYPE_V4SI_INT,
20154 V4HI_FTYPE_V4HI_INT,
20155 V8SF_FTYPE_V8SF_INT,
20156 V4SI_FTYPE_V8SI_INT,
20157 V4SF_FTYPE_V8SF_INT,
20158 V2DF_FTYPE_V4DF_INT,
20159 V4DF_FTYPE_V4DF_INT,
20160 V4SF_FTYPE_V4SF_INT,
20161 V2DI_FTYPE_V2DI_INT,
20162 V2DI2TI_FTYPE_V2DI_INT,
20163 V2DF_FTYPE_V2DF_INT,
20164 V16QI_FTYPE_V16QI_V16QI_V16QI,
20165 V8SF_FTYPE_V8SF_V8SF_V8SF,
20166 V4DF_FTYPE_V4DF_V4DF_V4DF,
20167 V4SF_FTYPE_V4SF_V4SF_V4SF,
20168 V2DF_FTYPE_V2DF_V2DF_V2DF,
20169 V16QI_FTYPE_V16QI_V16QI_INT,
20170 V8SI_FTYPE_V8SI_V8SI_INT,
20171 V8SI_FTYPE_V8SI_V4SI_INT,
20172 V8HI_FTYPE_V8HI_V8HI_INT,
20173 V8SF_FTYPE_V8SF_V8SF_INT,
20174 V8SF_FTYPE_V8SF_V4SF_INT,
20175 V4SI_FTYPE_V4SI_V4SI_INT,
20176 V4DF_FTYPE_V4DF_V4DF_INT,
20177 V4DF_FTYPE_V4DF_V2DF_INT,
20178 V4SF_FTYPE_V4SF_V4SF_INT,
20179 V2DI_FTYPE_V2DI_V2DI_INT,
20180 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20181 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20182 V2DF_FTYPE_V2DF_V2DF_INT,
20183 V8SF_FTYPE_V8SF_V8SF_V8SI_INT,
20184 V4DF_FTYPE_V4DF_V4DF_V4DI_INT,
20185 V4SF_FTYPE_V4SF_V4SF_V4SI_INT,
20186 V2DF_FTYPE_V2DF_V2DF_V2DI_INT,
20187 V2DI_FTYPE_V2DI_UINT_UINT,
20188 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20191 /* Special builtins with variable number of arguments. */
20192 static const struct builtin_description bdesc_special_args[] =
20195 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20198 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20201 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20202 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20203 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20205 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20206 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20207 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20210 /* SSE or 3DNow!A */
20211 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20212 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20229 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20232 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20235 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20236 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20239 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20240 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20241 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20243 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20244 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20245 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20246 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20247 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20249 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20250 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20251 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20252 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20253 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20254 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20255 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20257 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20258 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20259 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20260 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20261 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20262 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20263 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20264 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20267 /* Builtins with variable number of arguments. */
20268 static const struct builtin_description bdesc_args[] =
20271 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20272 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20273 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20274 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20275 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20276 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20278 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20279 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20280 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20281 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20282 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20283 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20284 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20285 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20287 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20288 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20291 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20292 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20293 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20295 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20296 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20297 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20298 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20299 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20300 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20302 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20303 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20304 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20305 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20306 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20307 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20309 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20310 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20311 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20313 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20315 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20317 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20322 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20323 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20326 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20327 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20330 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20331 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20332 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20335 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20336 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20337 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20338 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20340 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20341 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20342 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20343 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20344 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20345 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20346 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20347 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20348 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20349 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20350 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20351 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20352 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20353 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20354 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20357 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20358 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20359 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20360 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20361 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20362 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20365 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20366 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20367 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20368 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20369 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20370 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20371 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20372 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20373 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20374 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20375 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20376 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20378 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20380 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20381 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20382 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20383 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20385 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20386 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20389 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20390 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20391 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20392 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20393 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20394 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20395 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20396 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20397 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20398 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
20400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20401 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20402 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20403 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20404 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20407 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20408 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20412 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20413 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20414 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20417 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20418 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20419 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20420 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20422 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20423 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20424 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20425 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20426 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20428 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
20429 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
20430 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
20432 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
20434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20435 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20436 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20438 /* SSE MMX or 3Dnow!A */
20439 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20440 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20441 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20443 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20444 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20445 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20446 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20448 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
20449 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
20451 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
20454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
20457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
20458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
20459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
20460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
20462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
20463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
20464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
20465 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
20466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
20468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
20470 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
20471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
20472 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
20473 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
20475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
20476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
20477 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
20479 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20480 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20481 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20482 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
20489 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
20490 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
20491 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
20493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20494 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
20495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
20496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
20497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
20501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
20502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
20503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
20505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
20506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
20507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20510 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20514 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20516 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20517 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20523 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
20525 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20526 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20527 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20528 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20529 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20530 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20531 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20532 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20540 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20543 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20544 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
20546 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20547 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20548 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20549 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20552 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20557 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20558 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20561 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20562 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20563 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20564 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20566 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20567 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20568 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20569 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20570 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20571 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20572 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
20576 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
20577 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
20579 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
20582 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
20583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
20585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
20587 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
20588 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
20589 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
20590 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
20592 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
20593 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20594 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20595 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
20596 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20597 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20598 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
20600 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
20601 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20602 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20603 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
20604 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20605 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20606 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
20608 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20609 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20610 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20611 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
20614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
20615 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
20617 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
20619 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
20620 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
20622 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
20625 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
20626 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
20629 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
20630 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20632 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20633 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20634 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20635 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20636 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20637 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20640 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
20641 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
20642 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
20643 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
20644 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
20645 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20647 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20648 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20649 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20650 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20651 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20652 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20653 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20654 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20655 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20656 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20657 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20658 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20659 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
20660 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
20661 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20662 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20663 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20664 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20665 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20666 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20667 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20668 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20669 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20670 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20673 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
20674 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
20677 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20678 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20679 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
20680 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
20681 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20682 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20683 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20684 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
20685 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
20686 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
20688 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
20689 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
20690 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
20691 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
20692 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
20693 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
20694 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
20695 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
20696 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
20697 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
20698 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
20699 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
20700 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
20702 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
20703 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20704 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20705 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20706 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20707 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20708 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20709 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20710 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20711 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20712 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
20713 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20715 /* SSE4.1 and SSE5 */
20716 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
20717 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
20718 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20719 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20721 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20722 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20723 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20726 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20727 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
20728 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
20729 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
20730 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
20733 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
20734 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
20735 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
20736 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20739 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
20740 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
20742 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20743 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20744 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20745 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20748 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
20751 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20752 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20755 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20756 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_nandv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20758 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_nandv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20759 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20760 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20762 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20763 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20764 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20765 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20766 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20767 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20768 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20769 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20770 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20771 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20772 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20773 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20774 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20775 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20776 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
20779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
20780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
20781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
20783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
20786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
20787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20788 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
20797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
20798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
20799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
20800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
20801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
20802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
20803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
20804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
20805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
20806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
20807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
20810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
20811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
20812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
20813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
20814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT },
20815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT },
20816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT },
20817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT },
20818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
20819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
20820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
20822 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
20826 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
20827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20828 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20830 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
20835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
20837 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20839 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20842 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
20843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
20844 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
20845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
20846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
20847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
20849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20851 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20857 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20859 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20860 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20865 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
20866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
20870 enum multi_arg_type {
20880 MULTI_ARG_3_PERMPS,
20881 MULTI_ARG_3_PERMPD,
20888 MULTI_ARG_2_DI_IMM,
20889 MULTI_ARG_2_SI_IMM,
20890 MULTI_ARG_2_HI_IMM,
20891 MULTI_ARG_2_QI_IMM,
20892 MULTI_ARG_2_SF_CMP,
20893 MULTI_ARG_2_DF_CMP,
20894 MULTI_ARG_2_DI_CMP,
20895 MULTI_ARG_2_SI_CMP,
20896 MULTI_ARG_2_HI_CMP,
20897 MULTI_ARG_2_QI_CMP,
20920 static const struct builtin_description bdesc_multi_arg[] =
20922 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
20923 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
20924 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
20925 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
20926 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
20927 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
20928 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
20929 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
20930 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
20931 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
20932 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
20933 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
20934 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
20935 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
20936 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
20937 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
20938 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
20939 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
20940 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
20941 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
20942 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
20943 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
20944 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
20945 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
20946 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
20947 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
20948 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
20949 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
20950 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
20951 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
20952 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
20953 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
20954 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
20955 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
20956 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
20957 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
20958 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
20959 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
20960 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
20961 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
20962 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
20963 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
20964 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
20965 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
20966 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
20967 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
20968 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
20969 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
20970 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
20971 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
20972 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
20973 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
20974 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
20975 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
20976 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
20977 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
20978 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
20979 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
20980 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
20981 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
20982 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
20983 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
20984 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
20985 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
20986 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
20987 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
20988 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
20989 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
20990 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
20991 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
20992 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
20993 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
20994 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
20995 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
20996 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
20998 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
20999 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21000 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21001 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21002 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21003 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21004 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21005 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21006 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21007 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21008 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21009 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21010 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21011 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21012 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21013 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21015 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21016 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21017 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21018 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21019 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21020 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21021 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21022 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21023 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21024 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21025 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21026 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21027 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21028 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21029 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21030 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21032 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21033 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21034 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21035 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21036 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21037 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21038 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21039 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21040 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21041 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21042 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21043 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21044 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21045 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21046 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21047 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21049 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21050 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21051 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21052 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21053 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21054 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21055 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21056 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21057 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21058 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21059 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21060 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21061 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21062 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21063 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21064 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21066 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21067 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21068 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21069 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21070 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21071 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21072 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21074 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21075 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21076 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21077 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21078 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21079 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21080 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21082 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21083 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21084 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21085 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21086 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21087 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21088 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21090 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21091 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21092 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21093 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21094 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21095 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21096 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21098 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21099 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21100 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21101 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21102 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21103 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21104 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21106 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21107 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21108 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21109 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21110 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21111 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21112 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21114 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21115 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21116 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21117 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21118 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21119 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21120 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21122 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21123 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21124 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21125 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21126 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21127 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21128 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21130 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21131 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21132 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21133 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21134 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21135 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21136 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21137 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21139 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21140 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21141 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21142 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21143 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21144 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21145 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21146 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21148 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21149 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21150 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21151 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21152 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21153 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21154 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21155 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21158 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21159 in the current target ISA to allow the user to compile particular modules
21160 with different target specific options that differ from the command line
21163 ix86_init_mmx_sse_builtins (void)
21165 const struct builtin_description * d;
21168 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21169 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21170 tree V1DI_type_node
21171 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21172 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21173 tree V2DI_type_node
21174 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21175 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21176 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21177 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21178 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21179 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21180 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21182 tree pchar_type_node = build_pointer_type (char_type_node);
21183 tree pcchar_type_node
21184 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21185 tree pfloat_type_node = build_pointer_type (float_type_node);
21186 tree pcfloat_type_node
21187 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21188 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21189 tree pcv2sf_type_node
21190 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21191 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21192 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21195 tree int_ftype_v4sf_v4sf
21196 = build_function_type_list (integer_type_node,
21197 V4SF_type_node, V4SF_type_node, NULL_TREE);
21198 tree v4si_ftype_v4sf_v4sf
21199 = build_function_type_list (V4SI_type_node,
21200 V4SF_type_node, V4SF_type_node, NULL_TREE);
21201 /* MMX/SSE/integer conversions. */
21202 tree int_ftype_v4sf
21203 = build_function_type_list (integer_type_node,
21204 V4SF_type_node, NULL_TREE);
21205 tree int64_ftype_v4sf
21206 = build_function_type_list (long_long_integer_type_node,
21207 V4SF_type_node, NULL_TREE);
21208 tree int_ftype_v8qi
21209 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21210 tree v4sf_ftype_v4sf_int
21211 = build_function_type_list (V4SF_type_node,
21212 V4SF_type_node, integer_type_node, NULL_TREE);
21213 tree v4sf_ftype_v4sf_int64
21214 = build_function_type_list (V4SF_type_node,
21215 V4SF_type_node, long_long_integer_type_node,
21217 tree v4sf_ftype_v4sf_v2si
21218 = build_function_type_list (V4SF_type_node,
21219 V4SF_type_node, V2SI_type_node, NULL_TREE);
21221 /* Miscellaneous. */
21222 tree v8qi_ftype_v4hi_v4hi
21223 = build_function_type_list (V8QI_type_node,
21224 V4HI_type_node, V4HI_type_node, NULL_TREE);
21225 tree v4hi_ftype_v2si_v2si
21226 = build_function_type_list (V4HI_type_node,
21227 V2SI_type_node, V2SI_type_node, NULL_TREE);
21228 tree v4sf_ftype_v4sf_v4sf_int
21229 = build_function_type_list (V4SF_type_node,
21230 V4SF_type_node, V4SF_type_node,
21231 integer_type_node, NULL_TREE);
21232 tree v2si_ftype_v4hi_v4hi
21233 = build_function_type_list (V2SI_type_node,
21234 V4HI_type_node, V4HI_type_node, NULL_TREE);
21235 tree v4hi_ftype_v4hi_int
21236 = build_function_type_list (V4HI_type_node,
21237 V4HI_type_node, integer_type_node, NULL_TREE);
21238 tree v2si_ftype_v2si_int
21239 = build_function_type_list (V2SI_type_node,
21240 V2SI_type_node, integer_type_node, NULL_TREE);
21241 tree v1di_ftype_v1di_int
21242 = build_function_type_list (V1DI_type_node,
21243 V1DI_type_node, integer_type_node, NULL_TREE);
21245 tree void_ftype_void
21246 = build_function_type (void_type_node, void_list_node);
21247 tree void_ftype_unsigned
21248 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21249 tree void_ftype_unsigned_unsigned
21250 = build_function_type_list (void_type_node, unsigned_type_node,
21251 unsigned_type_node, NULL_TREE);
21252 tree void_ftype_pcvoid_unsigned_unsigned
21253 = build_function_type_list (void_type_node, const_ptr_type_node,
21254 unsigned_type_node, unsigned_type_node,
21256 tree unsigned_ftype_void
21257 = build_function_type (unsigned_type_node, void_list_node);
21258 tree v2si_ftype_v4sf
21259 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21260 /* Loads/stores. */
21261 tree void_ftype_v8qi_v8qi_pchar
21262 = build_function_type_list (void_type_node,
21263 V8QI_type_node, V8QI_type_node,
21264 pchar_type_node, NULL_TREE);
21265 tree v4sf_ftype_pcfloat
21266 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21267 tree v4sf_ftype_v4sf_pcv2sf
21268 = build_function_type_list (V4SF_type_node,
21269 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21270 tree void_ftype_pv2sf_v4sf
21271 = build_function_type_list (void_type_node,
21272 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21273 tree void_ftype_pfloat_v4sf
21274 = build_function_type_list (void_type_node,
21275 pfloat_type_node, V4SF_type_node, NULL_TREE);
21276 tree void_ftype_pdi_di
21277 = build_function_type_list (void_type_node,
21278 pdi_type_node, long_long_unsigned_type_node,
21280 tree void_ftype_pv2di_v2di
21281 = build_function_type_list (void_type_node,
21282 pv2di_type_node, V2DI_type_node, NULL_TREE);
21283 /* Normal vector unops. */
21284 tree v4sf_ftype_v4sf
21285 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21286 tree v16qi_ftype_v16qi
21287 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21288 tree v8hi_ftype_v8hi
21289 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21290 tree v4si_ftype_v4si
21291 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21292 tree v8qi_ftype_v8qi
21293 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21294 tree v4hi_ftype_v4hi
21295 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21297 /* Normal vector binops. */
21298 tree v4sf_ftype_v4sf_v4sf
21299 = build_function_type_list (V4SF_type_node,
21300 V4SF_type_node, V4SF_type_node, NULL_TREE);
21301 tree v8qi_ftype_v8qi_v8qi
21302 = build_function_type_list (V8QI_type_node,
21303 V8QI_type_node, V8QI_type_node, NULL_TREE);
21304 tree v4hi_ftype_v4hi_v4hi
21305 = build_function_type_list (V4HI_type_node,
21306 V4HI_type_node, V4HI_type_node, NULL_TREE);
21307 tree v2si_ftype_v2si_v2si
21308 = build_function_type_list (V2SI_type_node,
21309 V2SI_type_node, V2SI_type_node, NULL_TREE);
21310 tree v1di_ftype_v1di_v1di
21311 = build_function_type_list (V1DI_type_node,
21312 V1DI_type_node, V1DI_type_node, NULL_TREE);
21313 tree v1di_ftype_v1di_v1di_int
21314 = build_function_type_list (V1DI_type_node,
21315 V1DI_type_node, V1DI_type_node,
21316 integer_type_node, NULL_TREE);
21317 tree v2si_ftype_v2sf
21318 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21319 tree v2sf_ftype_v2si
21320 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21321 tree v2si_ftype_v2si
21322 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21323 tree v2sf_ftype_v2sf
21324 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21325 tree v2sf_ftype_v2sf_v2sf
21326 = build_function_type_list (V2SF_type_node,
21327 V2SF_type_node, V2SF_type_node, NULL_TREE);
21328 tree v2si_ftype_v2sf_v2sf
21329 = build_function_type_list (V2SI_type_node,
21330 V2SF_type_node, V2SF_type_node, NULL_TREE);
21331 tree pint_type_node = build_pointer_type (integer_type_node);
21332 tree pdouble_type_node = build_pointer_type (double_type_node);
21333 tree pcdouble_type_node = build_pointer_type (
21334 build_type_variant (double_type_node, 1, 0));
21335 tree int_ftype_v2df_v2df
21336 = build_function_type_list (integer_type_node,
21337 V2DF_type_node, V2DF_type_node, NULL_TREE);
21339 tree void_ftype_pcvoid
21340 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21341 tree v4sf_ftype_v4si
21342 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21343 tree v4si_ftype_v4sf
21344 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21345 tree v2df_ftype_v4si
21346 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21347 tree v4si_ftype_v2df
21348 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21349 tree v4si_ftype_v2df_v2df
21350 = build_function_type_list (V4SI_type_node,
21351 V2DF_type_node, V2DF_type_node, NULL_TREE);
21352 tree v2si_ftype_v2df
21353 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21354 tree v4sf_ftype_v2df
21355 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21356 tree v2df_ftype_v2si
21357 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21358 tree v2df_ftype_v4sf
21359 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21360 tree int_ftype_v2df
21361 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21362 tree int64_ftype_v2df
21363 = build_function_type_list (long_long_integer_type_node,
21364 V2DF_type_node, NULL_TREE);
21365 tree v2df_ftype_v2df_int
21366 = build_function_type_list (V2DF_type_node,
21367 V2DF_type_node, integer_type_node, NULL_TREE);
21368 tree v2df_ftype_v2df_int64
21369 = build_function_type_list (V2DF_type_node,
21370 V2DF_type_node, long_long_integer_type_node,
21372 tree v4sf_ftype_v4sf_v2df
21373 = build_function_type_list (V4SF_type_node,
21374 V4SF_type_node, V2DF_type_node, NULL_TREE);
21375 tree v2df_ftype_v2df_v4sf
21376 = build_function_type_list (V2DF_type_node,
21377 V2DF_type_node, V4SF_type_node, NULL_TREE);
21378 tree v2df_ftype_v2df_v2df_int
21379 = build_function_type_list (V2DF_type_node,
21380 V2DF_type_node, V2DF_type_node,
21383 tree v2df_ftype_v2df_pcdouble
21384 = build_function_type_list (V2DF_type_node,
21385 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21386 tree void_ftype_pdouble_v2df
21387 = build_function_type_list (void_type_node,
21388 pdouble_type_node, V2DF_type_node, NULL_TREE);
21389 tree void_ftype_pint_int
21390 = build_function_type_list (void_type_node,
21391 pint_type_node, integer_type_node, NULL_TREE);
21392 tree void_ftype_v16qi_v16qi_pchar
21393 = build_function_type_list (void_type_node,
21394 V16QI_type_node, V16QI_type_node,
21395 pchar_type_node, NULL_TREE);
21396 tree v2df_ftype_pcdouble
21397 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
21398 tree v2df_ftype_v2df_v2df
21399 = build_function_type_list (V2DF_type_node,
21400 V2DF_type_node, V2DF_type_node, NULL_TREE);
21401 tree v16qi_ftype_v16qi_v16qi
21402 = build_function_type_list (V16QI_type_node,
21403 V16QI_type_node, V16QI_type_node, NULL_TREE);
21404 tree v8hi_ftype_v8hi_v8hi
21405 = build_function_type_list (V8HI_type_node,
21406 V8HI_type_node, V8HI_type_node, NULL_TREE);
21407 tree v4si_ftype_v4si_v4si
21408 = build_function_type_list (V4SI_type_node,
21409 V4SI_type_node, V4SI_type_node, NULL_TREE);
21410 tree v2di_ftype_v2di_v2di
21411 = build_function_type_list (V2DI_type_node,
21412 V2DI_type_node, V2DI_type_node, NULL_TREE);
21413 tree v2di_ftype_v2df_v2df
21414 = build_function_type_list (V2DI_type_node,
21415 V2DF_type_node, V2DF_type_node, NULL_TREE);
21416 tree v2df_ftype_v2df
21417 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
21418 tree v2di_ftype_v2di_int
21419 = build_function_type_list (V2DI_type_node,
21420 V2DI_type_node, integer_type_node, NULL_TREE);
21421 tree v2di_ftype_v2di_v2di_int
21422 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21423 V2DI_type_node, integer_type_node, NULL_TREE);
21424 tree v4si_ftype_v4si_int
21425 = build_function_type_list (V4SI_type_node,
21426 V4SI_type_node, integer_type_node, NULL_TREE);
21427 tree v8hi_ftype_v8hi_int
21428 = build_function_type_list (V8HI_type_node,
21429 V8HI_type_node, integer_type_node, NULL_TREE);
21430 tree v4si_ftype_v8hi_v8hi
21431 = build_function_type_list (V4SI_type_node,
21432 V8HI_type_node, V8HI_type_node, NULL_TREE);
21433 tree v1di_ftype_v8qi_v8qi
21434 = build_function_type_list (V1DI_type_node,
21435 V8QI_type_node, V8QI_type_node, NULL_TREE);
21436 tree v1di_ftype_v2si_v2si
21437 = build_function_type_list (V1DI_type_node,
21438 V2SI_type_node, V2SI_type_node, NULL_TREE);
21439 tree v2di_ftype_v16qi_v16qi
21440 = build_function_type_list (V2DI_type_node,
21441 V16QI_type_node, V16QI_type_node, NULL_TREE);
21442 tree v2di_ftype_v4si_v4si
21443 = build_function_type_list (V2DI_type_node,
21444 V4SI_type_node, V4SI_type_node, NULL_TREE);
21445 tree int_ftype_v16qi
21446 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
21447 tree v16qi_ftype_pcchar
21448 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
21449 tree void_ftype_pchar_v16qi
21450 = build_function_type_list (void_type_node,
21451 pchar_type_node, V16QI_type_node, NULL_TREE);
21453 tree v2di_ftype_v2di_unsigned_unsigned
21454 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21455 unsigned_type_node, unsigned_type_node,
21457 tree v2di_ftype_v2di_v2di_unsigned_unsigned
21458 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
21459 unsigned_type_node, unsigned_type_node,
21461 tree v2di_ftype_v2di_v16qi
21462 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
21464 tree v2df_ftype_v2df_v2df_v2df
21465 = build_function_type_list (V2DF_type_node,
21466 V2DF_type_node, V2DF_type_node,
21467 V2DF_type_node, NULL_TREE);
21468 tree v4sf_ftype_v4sf_v4sf_v4sf
21469 = build_function_type_list (V4SF_type_node,
21470 V4SF_type_node, V4SF_type_node,
21471 V4SF_type_node, NULL_TREE);
21472 tree v8hi_ftype_v16qi
21473 = build_function_type_list (V8HI_type_node, V16QI_type_node,
21475 tree v4si_ftype_v16qi
21476 = build_function_type_list (V4SI_type_node, V16QI_type_node,
21478 tree v2di_ftype_v16qi
21479 = build_function_type_list (V2DI_type_node, V16QI_type_node,
21481 tree v4si_ftype_v8hi
21482 = build_function_type_list (V4SI_type_node, V8HI_type_node,
21484 tree v2di_ftype_v8hi
21485 = build_function_type_list (V2DI_type_node, V8HI_type_node,
21487 tree v2di_ftype_v4si
21488 = build_function_type_list (V2DI_type_node, V4SI_type_node,
21490 tree v2di_ftype_pv2di
21491 = build_function_type_list (V2DI_type_node, pv2di_type_node,
21493 tree v16qi_ftype_v16qi_v16qi_int
21494 = build_function_type_list (V16QI_type_node, V16QI_type_node,
21495 V16QI_type_node, integer_type_node,
21497 tree v16qi_ftype_v16qi_v16qi_v16qi
21498 = build_function_type_list (V16QI_type_node, V16QI_type_node,
21499 V16QI_type_node, V16QI_type_node,
21501 tree v8hi_ftype_v8hi_v8hi_int
21502 = build_function_type_list (V8HI_type_node, V8HI_type_node,
21503 V8HI_type_node, integer_type_node,
21505 tree v4si_ftype_v4si_v4si_int
21506 = build_function_type_list (V4SI_type_node, V4SI_type_node,
21507 V4SI_type_node, integer_type_node,
21509 tree int_ftype_v2di_v2di
21510 = build_function_type_list (integer_type_node,
21511 V2DI_type_node, V2DI_type_node,
21513 tree int_ftype_v16qi_int_v16qi_int_int
21514 = build_function_type_list (integer_type_node,
21521 tree v16qi_ftype_v16qi_int_v16qi_int_int
21522 = build_function_type_list (V16QI_type_node,
21529 tree int_ftype_v16qi_v16qi_int
21530 = build_function_type_list (integer_type_node,
21536 /* SSE5 instructions */
21537 tree v2di_ftype_v2di_v2di_v2di
21538 = build_function_type_list (V2DI_type_node,
21544 tree v4si_ftype_v4si_v4si_v4si
21545 = build_function_type_list (V4SI_type_node,
21551 tree v4si_ftype_v4si_v4si_v2di
21552 = build_function_type_list (V4SI_type_node,
21558 tree v8hi_ftype_v8hi_v8hi_v8hi
21559 = build_function_type_list (V8HI_type_node,
21565 tree v8hi_ftype_v8hi_v8hi_v4si
21566 = build_function_type_list (V8HI_type_node,
21572 tree v2df_ftype_v2df_v2df_v16qi
21573 = build_function_type_list (V2DF_type_node,
21579 tree v4sf_ftype_v4sf_v4sf_v16qi
21580 = build_function_type_list (V4SF_type_node,
21586 tree v2di_ftype_v2di_si
21587 = build_function_type_list (V2DI_type_node,
21592 tree v4si_ftype_v4si_si
21593 = build_function_type_list (V4SI_type_node,
21598 tree v8hi_ftype_v8hi_si
21599 = build_function_type_list (V8HI_type_node,
21604 tree v16qi_ftype_v16qi_si
21605 = build_function_type_list (V16QI_type_node,
21609 tree v4sf_ftype_v4hi
21610 = build_function_type_list (V4SF_type_node,
21614 tree v4hi_ftype_v4sf
21615 = build_function_type_list (V4HI_type_node,
21619 tree v2di_ftype_v2di
21620 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
21622 tree v16qi_ftype_v8hi_v8hi
21623 = build_function_type_list (V16QI_type_node,
21624 V8HI_type_node, V8HI_type_node,
21626 tree v8hi_ftype_v4si_v4si
21627 = build_function_type_list (V8HI_type_node,
21628 V4SI_type_node, V4SI_type_node,
21630 tree v8hi_ftype_v16qi_v16qi
21631 = build_function_type_list (V8HI_type_node,
21632 V16QI_type_node, V16QI_type_node,
21634 tree v4hi_ftype_v8qi_v8qi
21635 = build_function_type_list (V4HI_type_node,
21636 V8QI_type_node, V8QI_type_node,
21638 tree unsigned_ftype_unsigned_uchar
21639 = build_function_type_list (unsigned_type_node,
21640 unsigned_type_node,
21641 unsigned_char_type_node,
21643 tree unsigned_ftype_unsigned_ushort
21644 = build_function_type_list (unsigned_type_node,
21645 unsigned_type_node,
21646 short_unsigned_type_node,
21648 tree unsigned_ftype_unsigned_unsigned
21649 = build_function_type_list (unsigned_type_node,
21650 unsigned_type_node,
21651 unsigned_type_node,
21653 tree uint64_ftype_uint64_uint64
21654 = build_function_type_list (long_long_unsigned_type_node,
21655 long_long_unsigned_type_node,
21656 long_long_unsigned_type_node,
21658 tree float_ftype_float
21659 = build_function_type_list (float_type_node,
21664 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
21666 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
21668 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
21670 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
21672 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
21674 tree v8sf_ftype_v8sf
21675 = build_function_type_list (V8SF_type_node,
21678 tree v8si_ftype_v8sf
21679 = build_function_type_list (V8SI_type_node,
21682 tree v8sf_ftype_v8si
21683 = build_function_type_list (V8SF_type_node,
21686 tree v4si_ftype_v4df
21687 = build_function_type_list (V4SI_type_node,
21690 tree v4df_ftype_v4df
21691 = build_function_type_list (V4DF_type_node,
21694 tree v4df_ftype_v4si
21695 = build_function_type_list (V4DF_type_node,
21698 tree v4df_ftype_v4sf
21699 = build_function_type_list (V4DF_type_node,
21702 tree v4sf_ftype_v4df
21703 = build_function_type_list (V4SF_type_node,
21706 tree v8sf_ftype_v8sf_v8sf
21707 = build_function_type_list (V8SF_type_node,
21708 V8SF_type_node, V8SF_type_node,
21710 tree v4df_ftype_v4df_v4df
21711 = build_function_type_list (V4DF_type_node,
21712 V4DF_type_node, V4DF_type_node,
21714 tree v8sf_ftype_v8sf_int
21715 = build_function_type_list (V8SF_type_node,
21716 V8SF_type_node, integer_type_node,
21718 tree v4si_ftype_v8si_int
21719 = build_function_type_list (V4SI_type_node,
21720 V8SI_type_node, integer_type_node,
21722 tree v4df_ftype_v4df_int
21723 = build_function_type_list (V4DF_type_node,
21724 V4DF_type_node, integer_type_node,
21726 tree v4sf_ftype_v8sf_int
21727 = build_function_type_list (V4SF_type_node,
21728 V8SF_type_node, integer_type_node,
21730 tree v2df_ftype_v4df_int
21731 = build_function_type_list (V2DF_type_node,
21732 V4DF_type_node, integer_type_node,
21734 tree v8sf_ftype_v8sf_v8sf_int
21735 = build_function_type_list (V8SF_type_node,
21736 V8SF_type_node, V8SF_type_node,
21739 tree v8sf_ftype_v8sf_v8sf_v8sf
21740 = build_function_type_list (V8SF_type_node,
21741 V8SF_type_node, V8SF_type_node,
21744 tree v4df_ftype_v4df_v4df_v4df
21745 = build_function_type_list (V4DF_type_node,
21746 V4DF_type_node, V4DF_type_node,
21749 tree v8si_ftype_v8si_v8si_int
21750 = build_function_type_list (V8SI_type_node,
21751 V8SI_type_node, V8SI_type_node,
21754 tree v4df_ftype_v4df_v4df_int
21755 = build_function_type_list (V4DF_type_node,
21756 V4DF_type_node, V4DF_type_node,
21759 tree v8sf_ftype_v8sf_v8sf_v8si_int
21760 = build_function_type_list (V8SF_type_node,
21761 V8SF_type_node, V8SF_type_node,
21762 V8SI_type_node, integer_type_node,
21764 tree v4df_ftype_v4df_v4df_v4di_int
21765 = build_function_type_list (V4DF_type_node,
21766 V4DF_type_node, V4DF_type_node,
21767 V4DI_type_node, integer_type_node,
21769 tree v4sf_ftype_v4sf_v4sf_v4si_int
21770 = build_function_type_list (V4SF_type_node,
21771 V4SF_type_node, V4SF_type_node,
21772 V4SI_type_node, integer_type_node,
21774 tree v2df_ftype_v2df_v2df_v2di_int
21775 = build_function_type_list (V2DF_type_node,
21776 V2DF_type_node, V2DF_type_node,
21777 V2DI_type_node, integer_type_node,
21779 tree v8sf_ftype_pcfloat
21780 = build_function_type_list (V8SF_type_node,
21783 tree v4df_ftype_pcdouble
21784 = build_function_type_list (V4DF_type_node,
21785 pcdouble_type_node,
21787 tree pcv4sf_type_node
21788 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
21789 tree pcv2df_type_node
21790 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
21791 tree v8sf_ftype_pcv4sf
21792 = build_function_type_list (V8SF_type_node,
21795 tree v4df_ftype_pcv2df
21796 = build_function_type_list (V4DF_type_node,
21799 tree v32qi_ftype_pcchar
21800 = build_function_type_list (V32QI_type_node,
21803 tree void_ftype_pchar_v32qi
21804 = build_function_type_list (void_type_node,
21805 pchar_type_node, V32QI_type_node,
21807 tree v8si_ftype_v8si_v4si_int
21808 = build_function_type_list (V8SI_type_node,
21809 V8SI_type_node, V4SI_type_node,
21812 tree v8sf_ftype_v8sf_v4sf_int
21813 = build_function_type_list (V8SF_type_node,
21814 V8SF_type_node, V4SF_type_node,
21817 tree v4df_ftype_v4df_v2df_int
21818 = build_function_type_list (V4DF_type_node,
21819 V4DF_type_node, V2DF_type_node,
21822 tree void_ftype_pfloat_v8sf
21823 = build_function_type_list (void_type_node,
21824 pfloat_type_node, V8SF_type_node,
21826 tree void_ftype_pdouble_v4df
21827 = build_function_type_list (void_type_node,
21828 pdouble_type_node, V4DF_type_node,
21830 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
21831 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
21832 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
21833 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
21834 tree pcv8sf_type_node
21835 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
21836 tree pcv4df_type_node
21837 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
21838 tree v8sf_ftype_pcv8sf_v8sf
21839 = build_function_type_list (V8SF_type_node,
21840 pcv8sf_type_node, V8SF_type_node,
21842 tree v4df_ftype_pcv4df_v4df
21843 = build_function_type_list (V4DF_type_node,
21844 pcv4df_type_node, V4DF_type_node,
21846 tree v4sf_ftype_pcv4sf_v4sf
21847 = build_function_type_list (V4SF_type_node,
21848 pcv4sf_type_node, V4SF_type_node,
21850 tree v2df_ftype_pcv2df_v2df
21851 = build_function_type_list (V2DF_type_node,
21852 pcv2df_type_node, V2DF_type_node,
21854 tree void_ftype_pv8sf_v8sf_v8sf
21855 = build_function_type_list (void_type_node,
21856 pv8sf_type_node, V8SF_type_node,
21859 tree void_ftype_pv4df_v4df_v4df
21860 = build_function_type_list (void_type_node,
21861 pv4df_type_node, V4DF_type_node,
21864 tree void_ftype_pv4sf_v4sf_v4sf
21865 = build_function_type_list (void_type_node,
21866 pv4sf_type_node, V4SF_type_node,
21869 tree void_ftype_pv2df_v2df_v2df
21870 = build_function_type_list (void_type_node,
21871 pv2df_type_node, V2DF_type_node,
21874 tree v4df_ftype_v2df
21875 = build_function_type_list (V4DF_type_node,
21878 tree v8sf_ftype_v4sf
21879 = build_function_type_list (V8SF_type_node,
21882 tree v8si_ftype_v4si
21883 = build_function_type_list (V8SI_type_node,
21886 tree v2df_ftype_v4df
21887 = build_function_type_list (V2DF_type_node,
21890 tree v4sf_ftype_v8sf
21891 = build_function_type_list (V4SF_type_node,
21894 tree v4si_ftype_v8si
21895 = build_function_type_list (V4SI_type_node,
21898 tree int_ftype_v4df
21899 = build_function_type_list (integer_type_node,
21902 tree int_ftype_v8sf
21903 = build_function_type_list (integer_type_node,
21906 tree int_ftype_v8sf_v8sf
21907 = build_function_type_list (integer_type_node,
21908 V8SF_type_node, V8SF_type_node,
21910 tree int_ftype_v4di_v4di
21911 = build_function_type_list (integer_type_node,
21912 V4DI_type_node, V4DI_type_node,
21914 tree int_ftype_v4df_v4df
21915 = build_function_type_list (integer_type_node,
21916 V4DF_type_node, V4DF_type_node,
21918 tree v8sf_ftype_v8sf_v8si
21919 = build_function_type_list (V8SF_type_node,
21920 V8SF_type_node, V8SI_type_node,
21922 tree v4df_ftype_v4df_v4di
21923 = build_function_type_list (V4DF_type_node,
21924 V4DF_type_node, V4DI_type_node,
21926 tree v4sf_ftype_v4sf_v4si
21927 = build_function_type_list (V4SF_type_node,
21928 V4SF_type_node, V4SI_type_node, NULL_TREE);
21929 tree v2df_ftype_v2df_v2di
21930 = build_function_type_list (V2DF_type_node,
21931 V2DF_type_node, V2DI_type_node, NULL_TREE);
21935 /* Add all special builtins with variable number of operands. */
21936 for (i = 0, d = bdesc_special_args;
21937 i < ARRAY_SIZE (bdesc_special_args);
21945 switch ((enum ix86_special_builtin_type) d->flag)
21947 case VOID_FTYPE_VOID:
21948 type = void_ftype_void;
21950 case V32QI_FTYPE_PCCHAR:
21951 type = v32qi_ftype_pcchar;
21953 case V16QI_FTYPE_PCCHAR:
21954 type = v16qi_ftype_pcchar;
21956 case V8SF_FTYPE_PCV4SF:
21957 type = v8sf_ftype_pcv4sf;
21959 case V8SF_FTYPE_PCFLOAT:
21960 type = v8sf_ftype_pcfloat;
21962 case V4DF_FTYPE_PCV2DF:
21963 type = v4df_ftype_pcv2df;
21965 case V4DF_FTYPE_PCDOUBLE:
21966 type = v4df_ftype_pcdouble;
21968 case V4SF_FTYPE_PCFLOAT:
21969 type = v4sf_ftype_pcfloat;
21971 case V2DI_FTYPE_PV2DI:
21972 type = v2di_ftype_pv2di;
21974 case V2DF_FTYPE_PCDOUBLE:
21975 type = v2df_ftype_pcdouble;
21977 case V8SF_FTYPE_PCV8SF_V8SF:
21978 type = v8sf_ftype_pcv8sf_v8sf;
21980 case V4DF_FTYPE_PCV4DF_V4DF:
21981 type = v4df_ftype_pcv4df_v4df;
21983 case V4SF_FTYPE_V4SF_PCV2SF:
21984 type = v4sf_ftype_v4sf_pcv2sf;
21986 case V4SF_FTYPE_PCV4SF_V4SF:
21987 type = v4sf_ftype_pcv4sf_v4sf;
21989 case V2DF_FTYPE_V2DF_PCDOUBLE:
21990 type = v2df_ftype_v2df_pcdouble;
21992 case V2DF_FTYPE_PCV2DF_V2DF:
21993 type = v2df_ftype_pcv2df_v2df;
21995 case VOID_FTYPE_PV2SF_V4SF:
21996 type = void_ftype_pv2sf_v4sf;
21998 case VOID_FTYPE_PV2DI_V2DI:
21999 type = void_ftype_pv2di_v2di;
22001 case VOID_FTYPE_PCHAR_V32QI:
22002 type = void_ftype_pchar_v32qi;
22004 case VOID_FTYPE_PCHAR_V16QI:
22005 type = void_ftype_pchar_v16qi;
22007 case VOID_FTYPE_PFLOAT_V8SF:
22008 type = void_ftype_pfloat_v8sf;
22010 case VOID_FTYPE_PFLOAT_V4SF:
22011 type = void_ftype_pfloat_v4sf;
22013 case VOID_FTYPE_PDOUBLE_V4DF:
22014 type = void_ftype_pdouble_v4df;
22016 case VOID_FTYPE_PDOUBLE_V2DF:
22017 type = void_ftype_pdouble_v2df;
22019 case VOID_FTYPE_PDI_DI:
22020 type = void_ftype_pdi_di;
22022 case VOID_FTYPE_PINT_INT:
22023 type = void_ftype_pint_int;
22025 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22026 type = void_ftype_pv8sf_v8sf_v8sf;
22028 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22029 type = void_ftype_pv4df_v4df_v4df;
22031 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22032 type = void_ftype_pv4sf_v4sf_v4sf;
22034 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22035 type = void_ftype_pv2df_v2df_v2df;
22038 gcc_unreachable ();
22041 def_builtin (d->mask, d->name, type, d->code);
22044 /* Add all builtins with variable number of operands. */
22045 for (i = 0, d = bdesc_args;
22046 i < ARRAY_SIZE (bdesc_args);
22054 switch ((enum ix86_builtin_type) d->flag)
22056 case FLOAT_FTYPE_FLOAT:
22057 type = float_ftype_float;
22059 case INT_FTYPE_V8SF_V8SF_PTEST:
22060 type = int_ftype_v8sf_v8sf;
22062 case INT_FTYPE_V4DI_V4DI_PTEST:
22063 type = int_ftype_v4di_v4di;
22065 case INT_FTYPE_V4DF_V4DF_PTEST:
22066 type = int_ftype_v4df_v4df;
22068 case INT_FTYPE_V4SF_V4SF_PTEST:
22069 type = int_ftype_v4sf_v4sf;
22071 case INT_FTYPE_V2DI_V2DI_PTEST:
22072 type = int_ftype_v2di_v2di;
22074 case INT_FTYPE_V2DF_V2DF_PTEST:
22075 type = int_ftype_v2df_v2df;
22077 case INT64_FTYPE_V4SF:
22078 type = int64_ftype_v4sf;
22080 case INT64_FTYPE_V2DF:
22081 type = int64_ftype_v2df;
22083 case INT_FTYPE_V16QI:
22084 type = int_ftype_v16qi;
22086 case INT_FTYPE_V8QI:
22087 type = int_ftype_v8qi;
22089 case INT_FTYPE_V8SF:
22090 type = int_ftype_v8sf;
22092 case INT_FTYPE_V4DF:
22093 type = int_ftype_v4df;
22095 case INT_FTYPE_V4SF:
22096 type = int_ftype_v4sf;
22098 case INT_FTYPE_V2DF:
22099 type = int_ftype_v2df;
22101 case V16QI_FTYPE_V16QI:
22102 type = v16qi_ftype_v16qi;
22104 case V8SI_FTYPE_V8SF:
22105 type = v8si_ftype_v8sf;
22107 case V8SI_FTYPE_V4SI:
22108 type = v8si_ftype_v4si;
22110 case V8HI_FTYPE_V8HI:
22111 type = v8hi_ftype_v8hi;
22113 case V8HI_FTYPE_V16QI:
22114 type = v8hi_ftype_v16qi;
22116 case V8QI_FTYPE_V8QI:
22117 type = v8qi_ftype_v8qi;
22119 case V8SF_FTYPE_V8SF:
22120 type = v8sf_ftype_v8sf;
22122 case V8SF_FTYPE_V8SI:
22123 type = v8sf_ftype_v8si;
22125 case V8SF_FTYPE_V4SF:
22126 type = v8sf_ftype_v4sf;
22128 case V4SI_FTYPE_V4DF:
22129 type = v4si_ftype_v4df;
22131 case V4SI_FTYPE_V4SI:
22132 type = v4si_ftype_v4si;
22134 case V4SI_FTYPE_V16QI:
22135 type = v4si_ftype_v16qi;
22137 case V4SI_FTYPE_V8SI:
22138 type = v4si_ftype_v8si;
22140 case V4SI_FTYPE_V8HI:
22141 type = v4si_ftype_v8hi;
22143 case V4SI_FTYPE_V4SF:
22144 type = v4si_ftype_v4sf;
22146 case V4SI_FTYPE_V2DF:
22147 type = v4si_ftype_v2df;
22149 case V4HI_FTYPE_V4HI:
22150 type = v4hi_ftype_v4hi;
22152 case V4DF_FTYPE_V4DF:
22153 type = v4df_ftype_v4df;
22155 case V4DF_FTYPE_V4SI:
22156 type = v4df_ftype_v4si;
22158 case V4DF_FTYPE_V4SF:
22159 type = v4df_ftype_v4sf;
22161 case V4DF_FTYPE_V2DF:
22162 type = v4df_ftype_v2df;
22164 case V4SF_FTYPE_V4SF:
22165 case V4SF_FTYPE_V4SF_VEC_MERGE:
22166 type = v4sf_ftype_v4sf;
22168 case V4SF_FTYPE_V8SF:
22169 type = v4sf_ftype_v8sf;
22171 case V4SF_FTYPE_V4SI:
22172 type = v4sf_ftype_v4si;
22174 case V4SF_FTYPE_V4DF:
22175 type = v4sf_ftype_v4df;
22177 case V4SF_FTYPE_V2DF:
22178 type = v4sf_ftype_v2df;
22180 case V2DI_FTYPE_V2DI:
22181 type = v2di_ftype_v2di;
22183 case V2DI_FTYPE_V16QI:
22184 type = v2di_ftype_v16qi;
22186 case V2DI_FTYPE_V8HI:
22187 type = v2di_ftype_v8hi;
22189 case V2DI_FTYPE_V4SI:
22190 type = v2di_ftype_v4si;
22192 case V2SI_FTYPE_V2SI:
22193 type = v2si_ftype_v2si;
22195 case V2SI_FTYPE_V4SF:
22196 type = v2si_ftype_v4sf;
22198 case V2SI_FTYPE_V2DF:
22199 type = v2si_ftype_v2df;
22201 case V2SI_FTYPE_V2SF:
22202 type = v2si_ftype_v2sf;
22204 case V2DF_FTYPE_V4DF:
22205 type = v2df_ftype_v4df;
22207 case V2DF_FTYPE_V4SF:
22208 type = v2df_ftype_v4sf;
22210 case V2DF_FTYPE_V2DF:
22211 case V2DF_FTYPE_V2DF_VEC_MERGE:
22212 type = v2df_ftype_v2df;
22214 case V2DF_FTYPE_V2SI:
22215 type = v2df_ftype_v2si;
22217 case V2DF_FTYPE_V4SI:
22218 type = v2df_ftype_v4si;
22220 case V2SF_FTYPE_V2SF:
22221 type = v2sf_ftype_v2sf;
22223 case V2SF_FTYPE_V2SI:
22224 type = v2sf_ftype_v2si;
22226 case V16QI_FTYPE_V16QI_V16QI:
22227 type = v16qi_ftype_v16qi_v16qi;
22229 case V16QI_FTYPE_V8HI_V8HI:
22230 type = v16qi_ftype_v8hi_v8hi;
22232 case V8QI_FTYPE_V8QI_V8QI:
22233 type = v8qi_ftype_v8qi_v8qi;
22235 case V8QI_FTYPE_V4HI_V4HI:
22236 type = v8qi_ftype_v4hi_v4hi;
22238 case V8HI_FTYPE_V8HI_V8HI:
22239 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22240 type = v8hi_ftype_v8hi_v8hi;
22242 case V8HI_FTYPE_V16QI_V16QI:
22243 type = v8hi_ftype_v16qi_v16qi;
22245 case V8HI_FTYPE_V4SI_V4SI:
22246 type = v8hi_ftype_v4si_v4si;
22248 case V8HI_FTYPE_V8HI_SI_COUNT:
22249 type = v8hi_ftype_v8hi_int;
22251 case V8SF_FTYPE_V8SF_V8SF:
22252 type = v8sf_ftype_v8sf_v8sf;
22254 case V8SF_FTYPE_V8SF_V8SI:
22255 type = v8sf_ftype_v8sf_v8si;
22257 case V4SI_FTYPE_V4SI_V4SI:
22258 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22259 type = v4si_ftype_v4si_v4si;
22261 case V4SI_FTYPE_V8HI_V8HI:
22262 type = v4si_ftype_v8hi_v8hi;
22264 case V4SI_FTYPE_V4SF_V4SF:
22265 type = v4si_ftype_v4sf_v4sf;
22267 case V4SI_FTYPE_V2DF_V2DF:
22268 type = v4si_ftype_v2df_v2df;
22270 case V4SI_FTYPE_V4SI_SI_COUNT:
22271 type = v4si_ftype_v4si_int;
22273 case V4HI_FTYPE_V4HI_V4HI:
22274 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22275 type = v4hi_ftype_v4hi_v4hi;
22277 case V4HI_FTYPE_V8QI_V8QI:
22278 type = v4hi_ftype_v8qi_v8qi;
22280 case V4HI_FTYPE_V2SI_V2SI:
22281 type = v4hi_ftype_v2si_v2si;
22283 case V4HI_FTYPE_V4HI_SI_COUNT:
22284 type = v4hi_ftype_v4hi_int;
22286 case V4DF_FTYPE_V4DF_V4DF:
22287 type = v4df_ftype_v4df_v4df;
22289 case V4DF_FTYPE_V4DF_V4DI:
22290 type = v4df_ftype_v4df_v4di;
22292 case V4SF_FTYPE_V4SF_V4SF:
22293 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22294 type = v4sf_ftype_v4sf_v4sf;
22296 case V4SF_FTYPE_V4SF_V4SI:
22297 type = v4sf_ftype_v4sf_v4si;
22299 case V4SF_FTYPE_V4SF_V2SI:
22300 type = v4sf_ftype_v4sf_v2si;
22302 case V4SF_FTYPE_V4SF_V2DF:
22303 type = v4sf_ftype_v4sf_v2df;
22305 case V4SF_FTYPE_V4SF_DI:
22306 type = v4sf_ftype_v4sf_int64;
22308 case V4SF_FTYPE_V4SF_SI:
22309 type = v4sf_ftype_v4sf_int;
22311 case V2DI_FTYPE_V2DI_V2DI:
22312 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22313 type = v2di_ftype_v2di_v2di;
22315 case V2DI_FTYPE_V16QI_V16QI:
22316 type = v2di_ftype_v16qi_v16qi;
22318 case V2DI_FTYPE_V4SI_V4SI:
22319 type = v2di_ftype_v4si_v4si;
22321 case V2DI_FTYPE_V2DI_V16QI:
22322 type = v2di_ftype_v2di_v16qi;
22324 case V2DI_FTYPE_V2DF_V2DF:
22325 type = v2di_ftype_v2df_v2df;
22327 case V2DI_FTYPE_V2DI_SI_COUNT:
22328 type = v2di_ftype_v2di_int;
22330 case V2SI_FTYPE_V2SI_V2SI:
22331 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22332 type = v2si_ftype_v2si_v2si;
22334 case V2SI_FTYPE_V4HI_V4HI:
22335 type = v2si_ftype_v4hi_v4hi;
22337 case V2SI_FTYPE_V2SF_V2SF:
22338 type = v2si_ftype_v2sf_v2sf;
22340 case V2SI_FTYPE_V2SI_SI_COUNT:
22341 type = v2si_ftype_v2si_int;
22343 case V2DF_FTYPE_V2DF_V2DF:
22344 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22345 type = v2df_ftype_v2df_v2df;
22347 case V2DF_FTYPE_V2DF_V4SF:
22348 type = v2df_ftype_v2df_v4sf;
22350 case V2DF_FTYPE_V2DF_V2DI:
22351 type = v2df_ftype_v2df_v2di;
22353 case V2DF_FTYPE_V2DF_DI:
22354 type = v2df_ftype_v2df_int64;
22356 case V2DF_FTYPE_V2DF_SI:
22357 type = v2df_ftype_v2df_int;
22359 case V2SF_FTYPE_V2SF_V2SF:
22360 type = v2sf_ftype_v2sf_v2sf;
22362 case V1DI_FTYPE_V1DI_V1DI:
22363 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22364 type = v1di_ftype_v1di_v1di;
22366 case V1DI_FTYPE_V8QI_V8QI:
22367 type = v1di_ftype_v8qi_v8qi;
22369 case V1DI_FTYPE_V2SI_V2SI:
22370 type = v1di_ftype_v2si_v2si;
22372 case V1DI_FTYPE_V1DI_SI_COUNT:
22373 type = v1di_ftype_v1di_int;
22375 case UINT64_FTYPE_UINT64_UINT64:
22376 type = uint64_ftype_uint64_uint64;
22378 case UINT_FTYPE_UINT_UINT:
22379 type = unsigned_ftype_unsigned_unsigned;
22381 case UINT_FTYPE_UINT_USHORT:
22382 type = unsigned_ftype_unsigned_ushort;
22384 case UINT_FTYPE_UINT_UCHAR:
22385 type = unsigned_ftype_unsigned_uchar;
22387 case V8HI_FTYPE_V8HI_INT:
22388 type = v8hi_ftype_v8hi_int;
22390 case V8SF_FTYPE_V8SF_INT:
22391 type = v8sf_ftype_v8sf_int;
22393 case V4SI_FTYPE_V4SI_INT:
22394 type = v4si_ftype_v4si_int;
22396 case V4SI_FTYPE_V8SI_INT:
22397 type = v4si_ftype_v8si_int;
22399 case V4HI_FTYPE_V4HI_INT:
22400 type = v4hi_ftype_v4hi_int;
22402 case V4DF_FTYPE_V4DF_INT:
22403 type = v4df_ftype_v4df_int;
22405 case V4SF_FTYPE_V4SF_INT:
22406 type = v4sf_ftype_v4sf_int;
22408 case V4SF_FTYPE_V8SF_INT:
22409 type = v4sf_ftype_v8sf_int;
22411 case V2DI_FTYPE_V2DI_INT:
22412 case V2DI2TI_FTYPE_V2DI_INT:
22413 type = v2di_ftype_v2di_int;
22415 case V2DF_FTYPE_V2DF_INT:
22416 type = v2df_ftype_v2df_int;
22418 case V2DF_FTYPE_V4DF_INT:
22419 type = v2df_ftype_v4df_int;
22421 case V16QI_FTYPE_V16QI_V16QI_V16QI:
22422 type = v16qi_ftype_v16qi_v16qi_v16qi;
22424 case V8SF_FTYPE_V8SF_V8SF_V8SF:
22425 type = v8sf_ftype_v8sf_v8sf_v8sf;
22427 case V4DF_FTYPE_V4DF_V4DF_V4DF:
22428 type = v4df_ftype_v4df_v4df_v4df;
22430 case V4SF_FTYPE_V4SF_V4SF_V4SF:
22431 type = v4sf_ftype_v4sf_v4sf_v4sf;
22433 case V2DF_FTYPE_V2DF_V2DF_V2DF:
22434 type = v2df_ftype_v2df_v2df_v2df;
22436 case V16QI_FTYPE_V16QI_V16QI_INT:
22437 type = v16qi_ftype_v16qi_v16qi_int;
22439 case V8SI_FTYPE_V8SI_V8SI_INT:
22440 type = v8si_ftype_v8si_v8si_int;
22442 case V8SI_FTYPE_V8SI_V4SI_INT:
22443 type = v8si_ftype_v8si_v4si_int;
22445 case V8HI_FTYPE_V8HI_V8HI_INT:
22446 type = v8hi_ftype_v8hi_v8hi_int;
22448 case V8SF_FTYPE_V8SF_V8SF_INT:
22449 type = v8sf_ftype_v8sf_v8sf_int;
22451 case V8SF_FTYPE_V8SF_V4SF_INT:
22452 type = v8sf_ftype_v8sf_v4sf_int;
22454 case V4SI_FTYPE_V4SI_V4SI_INT:
22455 type = v4si_ftype_v4si_v4si_int;
22457 case V4DF_FTYPE_V4DF_V4DF_INT:
22458 type = v4df_ftype_v4df_v4df_int;
22460 case V4DF_FTYPE_V4DF_V2DF_INT:
22461 type = v4df_ftype_v4df_v2df_int;
22463 case V4SF_FTYPE_V4SF_V4SF_INT:
22464 type = v4sf_ftype_v4sf_v4sf_int;
22466 case V2DI_FTYPE_V2DI_V2DI_INT:
22467 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
22468 type = v2di_ftype_v2di_v2di_int;
22470 case V2DF_FTYPE_V2DF_V2DF_INT:
22471 type = v2df_ftype_v2df_v2df_int;
22473 case V2DI_FTYPE_V2DI_UINT_UINT:
22474 type = v2di_ftype_v2di_unsigned_unsigned;
22476 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
22477 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
22479 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
22480 type = v1di_ftype_v1di_v1di_int;
22482 case V8SF_FTYPE_V8SF_V8SF_V8SI_INT:
22483 type = v8sf_ftype_v8sf_v8sf_v8si_int;
22485 case V4DF_FTYPE_V4DF_V4DF_V4DI_INT:
22486 type = v4df_ftype_v4df_v4df_v4di_int;
22488 case V4SF_FTYPE_V4SF_V4SF_V4SI_INT:
22489 type = v4sf_ftype_v4sf_v4sf_v4si_int;
22491 case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
22492 type = v2df_ftype_v2df_v2df_v2di_int;
22495 gcc_unreachable ();
22498 def_builtin_const (d->mask, d->name, type, d->code);
22501 /* pcmpestr[im] insns. */
22502 for (i = 0, d = bdesc_pcmpestr;
22503 i < ARRAY_SIZE (bdesc_pcmpestr);
22506 if (d->code == IX86_BUILTIN_PCMPESTRM128)
22507 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
22509 ftype = int_ftype_v16qi_int_v16qi_int_int;
22510 def_builtin_const (d->mask, d->name, ftype, d->code);
22513 /* pcmpistr[im] insns. */
22514 for (i = 0, d = bdesc_pcmpistr;
22515 i < ARRAY_SIZE (bdesc_pcmpistr);
22518 if (d->code == IX86_BUILTIN_PCMPISTRM128)
22519 ftype = v16qi_ftype_v16qi_v16qi_int;
22521 ftype = int_ftype_v16qi_v16qi_int;
22522 def_builtin_const (d->mask, d->name, ftype, d->code);
22525 /* comi/ucomi insns. */
22526 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
22527 if (d->mask == OPTION_MASK_ISA_SSE2)
22528 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
22530 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
22533 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
22534 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
22536 /* SSE or 3DNow!A */
22537 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
22540 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
22542 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
22543 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
22546 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
22547 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
22550 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
22551 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
22552 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
22553 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
22554 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
22555 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
22558 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
22561 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
22562 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
22564 /* Access to the vec_init patterns. */
22565 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
22566 integer_type_node, NULL_TREE);
22567 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
22569 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
22570 short_integer_type_node,
22571 short_integer_type_node,
22572 short_integer_type_node, NULL_TREE);
22573 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
22575 ftype = build_function_type_list (V8QI_type_node, char_type_node,
22576 char_type_node, char_type_node,
22577 char_type_node, char_type_node,
22578 char_type_node, char_type_node,
22579 char_type_node, NULL_TREE);
22580 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
22582 /* Access to the vec_extract patterns. */
22583 ftype = build_function_type_list (double_type_node, V2DF_type_node,
22584 integer_type_node, NULL_TREE);
22585 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
22587 ftype = build_function_type_list (long_long_integer_type_node,
22588 V2DI_type_node, integer_type_node,
22590 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
22592 ftype = build_function_type_list (float_type_node, V4SF_type_node,
22593 integer_type_node, NULL_TREE);
22594 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
22596 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
22597 integer_type_node, NULL_TREE);
22598 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
22600 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
22601 integer_type_node, NULL_TREE);
22602 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
22604 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
22605 integer_type_node, NULL_TREE);
22606 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
22608 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
22609 integer_type_node, NULL_TREE);
22610 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
22612 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
22613 integer_type_node, NULL_TREE);
22614 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
22616 /* Access to the vec_set patterns. */
22617 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
22619 integer_type_node, NULL_TREE);
22620 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
22622 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
22624 integer_type_node, NULL_TREE);
22625 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
22627 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
22629 integer_type_node, NULL_TREE);
22630 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
22632 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
22634 integer_type_node, NULL_TREE);
22635 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
22637 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
22639 integer_type_node, NULL_TREE);
22640 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
22642 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
22644 integer_type_node, NULL_TREE);
22645 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
22647 /* Add SSE5 multi-arg argument instructions */
22648 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
22650 tree mtype = NULL_TREE;
22655 switch ((enum multi_arg_type)d->flag)
22657 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
22658 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
22659 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
22660 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
22661 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
22662 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
22663 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
22664 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
22665 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
22666 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
22667 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
22668 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
22669 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
22670 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
22671 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
22672 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
22673 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
22674 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
22675 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
22676 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
22677 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
22678 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
22679 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
22680 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
22681 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
22682 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
22683 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
22684 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
22685 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
22686 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
22687 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
22688 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
22689 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
22690 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
22691 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
22692 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
22693 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
22694 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
22695 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
22696 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
22697 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
22698 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
22699 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
22700 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
22701 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
22702 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
22703 case MULTI_ARG_UNKNOWN:
22705 gcc_unreachable ();
22709 def_builtin_const (d->mask, d->name, mtype, d->code);
22713 /* Internal method for ix86_init_builtins. */
22716 ix86_init_builtins_va_builtins_abi (void)
22718 tree ms_va_ref, sysv_va_ref;
22719 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
22720 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
22721 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
22722 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
22726 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
22727 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
22728 ms_va_ref = build_reference_type (ms_va_list_type_node);
22730 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
22733 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
22734 fnvoid_va_start_ms =
22735 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
22736 fnvoid_va_end_sysv =
22737 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
22738 fnvoid_va_start_sysv =
22739 build_varargs_function_type_list (void_type_node, sysv_va_ref,
22741 fnvoid_va_copy_ms =
22742 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
22744 fnvoid_va_copy_sysv =
22745 build_function_type_list (void_type_node, sysv_va_ref,
22746 sysv_va_ref, NULL_TREE);
22748 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
22749 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
22750 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
22751 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
22752 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
22753 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
22754 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
22755 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
22756 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
22757 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
22758 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
22759 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
22763 ix86_init_builtins (void)
22765 tree float128_type_node = make_node (REAL_TYPE);
22768 /* The __float80 type. */
22769 if (TYPE_MODE (long_double_type_node) == XFmode)
22770 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
22774 /* The __float80 type. */
22775 tree float80_type_node = make_node (REAL_TYPE);
22777 TYPE_PRECISION (float80_type_node) = 80;
22778 layout_type (float80_type_node);
22779 (*lang_hooks.types.register_builtin_type) (float80_type_node,
22783 /* The __float128 type. */
22784 TYPE_PRECISION (float128_type_node) = 128;
22785 layout_type (float128_type_node);
22786 (*lang_hooks.types.register_builtin_type) (float128_type_node,
22789 /* TFmode support builtins. */
22790 ftype = build_function_type (float128_type_node, void_list_node);
22791 decl = add_builtin_function ("__builtin_infq", ftype,
22792 IX86_BUILTIN_INFQ, BUILT_IN_MD,
22794 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
22796 /* We will expand them to normal call if SSE2 isn't available since
22797 they are used by libgcc. */
22798 ftype = build_function_type_list (float128_type_node,
22799 float128_type_node,
22801 decl = add_builtin_function ("__builtin_fabsq", ftype,
22802 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
22803 "__fabstf2", NULL_TREE);
22804 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
22805 TREE_READONLY (decl) = 1;
22807 ftype = build_function_type_list (float128_type_node,
22808 float128_type_node,
22809 float128_type_node,
22811 decl = add_builtin_function ("__builtin_copysignq", ftype,
22812 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
22813 "__copysigntf3", NULL_TREE);
22814 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
22815 TREE_READONLY (decl) = 1;
22817 ix86_init_mmx_sse_builtins ();
22819 ix86_init_builtins_va_builtins_abi ();
22822 /* Errors in the source file can cause expand_expr to return const0_rtx
22823 where we expect a vector. To avoid crashing, use one of the vector
22824 clear instructions. */
22826 safe_vector_operand (rtx x, enum machine_mode mode)
22828 if (x == const0_rtx)
22829 x = CONST0_RTX (mode);
22833 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
22836 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
22839 tree arg0 = CALL_EXPR_ARG (exp, 0);
22840 tree arg1 = CALL_EXPR_ARG (exp, 1);
22841 rtx op0 = expand_normal (arg0);
22842 rtx op1 = expand_normal (arg1);
22843 enum machine_mode tmode = insn_data[icode].operand[0].mode;
22844 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
22845 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
22847 if (VECTOR_MODE_P (mode0))
22848 op0 = safe_vector_operand (op0, mode0);
22849 if (VECTOR_MODE_P (mode1))
22850 op1 = safe_vector_operand (op1, mode1);
22852 if (optimize || !target
22853 || GET_MODE (target) != tmode
22854 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
22855 target = gen_reg_rtx (tmode);
22857 if (GET_MODE (op1) == SImode && mode1 == TImode)
22859 rtx x = gen_reg_rtx (V4SImode);
22860 emit_insn (gen_sse2_loadd (x, op1));
22861 op1 = gen_lowpart (TImode, x);
22864 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
22865 op0 = copy_to_mode_reg (mode0, op0);
22866 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
22867 op1 = copy_to_mode_reg (mode1, op1);
22869 pat = GEN_FCN (icode) (target, op0, op1);
22878 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
22881 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
22882 enum multi_arg_type m_type,
22883 enum insn_code sub_code)
22888 bool comparison_p = false;
22890 bool last_arg_constant = false;
22891 int num_memory = 0;
22894 enum machine_mode mode;
22897 enum machine_mode tmode = insn_data[icode].operand[0].mode;
22901 case MULTI_ARG_3_SF:
22902 case MULTI_ARG_3_DF:
22903 case MULTI_ARG_3_DI:
22904 case MULTI_ARG_3_SI:
22905 case MULTI_ARG_3_SI_DI:
22906 case MULTI_ARG_3_HI:
22907 case MULTI_ARG_3_HI_SI:
22908 case MULTI_ARG_3_QI:
22909 case MULTI_ARG_3_PERMPS:
22910 case MULTI_ARG_3_PERMPD:
22914 case MULTI_ARG_2_SF:
22915 case MULTI_ARG_2_DF:
22916 case MULTI_ARG_2_DI:
22917 case MULTI_ARG_2_SI:
22918 case MULTI_ARG_2_HI:
22919 case MULTI_ARG_2_QI:
22923 case MULTI_ARG_2_DI_IMM:
22924 case MULTI_ARG_2_SI_IMM:
22925 case MULTI_ARG_2_HI_IMM:
22926 case MULTI_ARG_2_QI_IMM:
22928 last_arg_constant = true;
22931 case MULTI_ARG_1_SF:
22932 case MULTI_ARG_1_DF:
22933 case MULTI_ARG_1_DI:
22934 case MULTI_ARG_1_SI:
22935 case MULTI_ARG_1_HI:
22936 case MULTI_ARG_1_QI:
22937 case MULTI_ARG_1_SI_DI:
22938 case MULTI_ARG_1_HI_DI:
22939 case MULTI_ARG_1_HI_SI:
22940 case MULTI_ARG_1_QI_DI:
22941 case MULTI_ARG_1_QI_SI:
22942 case MULTI_ARG_1_QI_HI:
22943 case MULTI_ARG_1_PH2PS:
22944 case MULTI_ARG_1_PS2PH:
22948 case MULTI_ARG_2_SF_CMP:
22949 case MULTI_ARG_2_DF_CMP:
22950 case MULTI_ARG_2_DI_CMP:
22951 case MULTI_ARG_2_SI_CMP:
22952 case MULTI_ARG_2_HI_CMP:
22953 case MULTI_ARG_2_QI_CMP:
22955 comparison_p = true;
22958 case MULTI_ARG_2_SF_TF:
22959 case MULTI_ARG_2_DF_TF:
22960 case MULTI_ARG_2_DI_TF:
22961 case MULTI_ARG_2_SI_TF:
22962 case MULTI_ARG_2_HI_TF:
22963 case MULTI_ARG_2_QI_TF:
22968 case MULTI_ARG_UNKNOWN:
22970 gcc_unreachable ();
22973 if (optimize || !target
22974 || GET_MODE (target) != tmode
22975 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
22976 target = gen_reg_rtx (tmode);
22978 gcc_assert (nargs <= 4);
22980 for (i = 0; i < nargs; i++)
22982 tree arg = CALL_EXPR_ARG (exp, i);
22983 rtx op = expand_normal (arg);
22984 int adjust = (comparison_p) ? 1 : 0;
22985 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
22987 if (last_arg_constant && i == nargs-1)
22989 if (GET_CODE (op) != CONST_INT)
22991 error ("last argument must be an immediate");
22992 return gen_reg_rtx (tmode);
22997 if (VECTOR_MODE_P (mode))
22998 op = safe_vector_operand (op, mode);
23000 /* If we aren't optimizing, only allow one memory operand to be
23002 if (memory_operand (op, mode))
23005 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23008 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23010 op = force_reg (mode, op);
23014 args[i].mode = mode;
23020 pat = GEN_FCN (icode) (target, args[0].op);
23025 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23026 GEN_INT ((int)sub_code));
23027 else if (! comparison_p)
23028 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23031 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23035 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23040 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23044 gcc_unreachable ();
23054 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23055 insns with vec_merge. */
23058 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23062 tree arg0 = CALL_EXPR_ARG (exp, 0);
23063 rtx op1, op0 = expand_normal (arg0);
23064 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23065 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23067 if (optimize || !target
23068 || GET_MODE (target) != tmode
23069 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23070 target = gen_reg_rtx (tmode);
23072 if (VECTOR_MODE_P (mode0))
23073 op0 = safe_vector_operand (op0, mode0);
23075 if ((optimize && !register_operand (op0, mode0))
23076 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23077 op0 = copy_to_mode_reg (mode0, op0);
23080 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23081 op1 = copy_to_mode_reg (mode0, op1);
23083 pat = GEN_FCN (icode) (target, op0, op1);
23090 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23093 ix86_expand_sse_compare (const struct builtin_description *d,
23094 tree exp, rtx target, bool swap)
23097 tree arg0 = CALL_EXPR_ARG (exp, 0);
23098 tree arg1 = CALL_EXPR_ARG (exp, 1);
23099 rtx op0 = expand_normal (arg0);
23100 rtx op1 = expand_normal (arg1);
23102 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23103 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23104 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23105 enum rtx_code comparison = d->comparison;
23107 if (VECTOR_MODE_P (mode0))
23108 op0 = safe_vector_operand (op0, mode0);
23109 if (VECTOR_MODE_P (mode1))
23110 op1 = safe_vector_operand (op1, mode1);
23112 /* Swap operands if we have a comparison that isn't available in
23116 rtx tmp = gen_reg_rtx (mode1);
23117 emit_move_insn (tmp, op1);
23122 if (optimize || !target
23123 || GET_MODE (target) != tmode
23124 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23125 target = gen_reg_rtx (tmode);
23127 if ((optimize && !register_operand (op0, mode0))
23128 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23129 op0 = copy_to_mode_reg (mode0, op0);
23130 if ((optimize && !register_operand (op1, mode1))
23131 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23132 op1 = copy_to_mode_reg (mode1, op1);
23134 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23135 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23142 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23145 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23149 tree arg0 = CALL_EXPR_ARG (exp, 0);
23150 tree arg1 = CALL_EXPR_ARG (exp, 1);
23151 rtx op0 = expand_normal (arg0);
23152 rtx op1 = expand_normal (arg1);
23153 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23154 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23155 enum rtx_code comparison = d->comparison;
23157 if (VECTOR_MODE_P (mode0))
23158 op0 = safe_vector_operand (op0, mode0);
23159 if (VECTOR_MODE_P (mode1))
23160 op1 = safe_vector_operand (op1, mode1);
23162 /* Swap operands if we have a comparison that isn't available in
23164 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23171 target = gen_reg_rtx (SImode);
23172 emit_move_insn (target, const0_rtx);
23173 target = gen_rtx_SUBREG (QImode, target, 0);
23175 if ((optimize && !register_operand (op0, mode0))
23176 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23177 op0 = copy_to_mode_reg (mode0, op0);
23178 if ((optimize && !register_operand (op1, mode1))
23179 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23180 op1 = copy_to_mode_reg (mode1, op1);
23182 pat = GEN_FCN (d->icode) (op0, op1);
23186 emit_insn (gen_rtx_SET (VOIDmode,
23187 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23188 gen_rtx_fmt_ee (comparison, QImode,
23192 return SUBREG_REG (target);
23195 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23198 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23202 tree arg0 = CALL_EXPR_ARG (exp, 0);
23203 tree arg1 = CALL_EXPR_ARG (exp, 1);
23204 rtx op0 = expand_normal (arg0);
23205 rtx op1 = expand_normal (arg1);
23206 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23207 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23208 enum rtx_code comparison = d->comparison;
23210 if (VECTOR_MODE_P (mode0))
23211 op0 = safe_vector_operand (op0, mode0);
23212 if (VECTOR_MODE_P (mode1))
23213 op1 = safe_vector_operand (op1, mode1);
23215 target = gen_reg_rtx (SImode);
23216 emit_move_insn (target, const0_rtx);
23217 target = gen_rtx_SUBREG (QImode, target, 0);
23219 if ((optimize && !register_operand (op0, mode0))
23220 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23221 op0 = copy_to_mode_reg (mode0, op0);
23222 if ((optimize && !register_operand (op1, mode1))
23223 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23224 op1 = copy_to_mode_reg (mode1, op1);
23226 pat = GEN_FCN (d->icode) (op0, op1);
23230 emit_insn (gen_rtx_SET (VOIDmode,
23231 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23232 gen_rtx_fmt_ee (comparison, QImode,
23236 return SUBREG_REG (target);
23239 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23242 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23243 tree exp, rtx target)
23246 tree arg0 = CALL_EXPR_ARG (exp, 0);
23247 tree arg1 = CALL_EXPR_ARG (exp, 1);
23248 tree arg2 = CALL_EXPR_ARG (exp, 2);
23249 tree arg3 = CALL_EXPR_ARG (exp, 3);
23250 tree arg4 = CALL_EXPR_ARG (exp, 4);
23251 rtx scratch0, scratch1;
23252 rtx op0 = expand_normal (arg0);
23253 rtx op1 = expand_normal (arg1);
23254 rtx op2 = expand_normal (arg2);
23255 rtx op3 = expand_normal (arg3);
23256 rtx op4 = expand_normal (arg4);
23257 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23259 tmode0 = insn_data[d->icode].operand[0].mode;
23260 tmode1 = insn_data[d->icode].operand[1].mode;
23261 modev2 = insn_data[d->icode].operand[2].mode;
23262 modei3 = insn_data[d->icode].operand[3].mode;
23263 modev4 = insn_data[d->icode].operand[4].mode;
23264 modei5 = insn_data[d->icode].operand[5].mode;
23265 modeimm = insn_data[d->icode].operand[6].mode;
23267 if (VECTOR_MODE_P (modev2))
23268 op0 = safe_vector_operand (op0, modev2);
23269 if (VECTOR_MODE_P (modev4))
23270 op2 = safe_vector_operand (op2, modev4);
23272 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23273 op0 = copy_to_mode_reg (modev2, op0);
23274 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23275 op1 = copy_to_mode_reg (modei3, op1);
23276 if ((optimize && !register_operand (op2, modev4))
23277 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23278 op2 = copy_to_mode_reg (modev4, op2);
23279 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23280 op3 = copy_to_mode_reg (modei5, op3);
23282 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23284 error ("the fifth argument must be a 8-bit immediate");
23288 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23290 if (optimize || !target
23291 || GET_MODE (target) != tmode0
23292 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23293 target = gen_reg_rtx (tmode0);
23295 scratch1 = gen_reg_rtx (tmode1);
23297 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23299 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23301 if (optimize || !target
23302 || GET_MODE (target) != tmode1
23303 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23304 target = gen_reg_rtx (tmode1);
23306 scratch0 = gen_reg_rtx (tmode0);
23308 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23312 gcc_assert (d->flag);
23314 scratch0 = gen_reg_rtx (tmode0);
23315 scratch1 = gen_reg_rtx (tmode1);
23317 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23327 target = gen_reg_rtx (SImode);
23328 emit_move_insn (target, const0_rtx);
23329 target = gen_rtx_SUBREG (QImode, target, 0);
23332 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23333 gen_rtx_fmt_ee (EQ, QImode,
23334 gen_rtx_REG ((enum machine_mode) d->flag,
23337 return SUBREG_REG (target);
23344 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23347 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23348 tree exp, rtx target)
23351 tree arg0 = CALL_EXPR_ARG (exp, 0);
23352 tree arg1 = CALL_EXPR_ARG (exp, 1);
23353 tree arg2 = CALL_EXPR_ARG (exp, 2);
23354 rtx scratch0, scratch1;
23355 rtx op0 = expand_normal (arg0);
23356 rtx op1 = expand_normal (arg1);
23357 rtx op2 = expand_normal (arg2);
23358 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23360 tmode0 = insn_data[d->icode].operand[0].mode;
23361 tmode1 = insn_data[d->icode].operand[1].mode;
23362 modev2 = insn_data[d->icode].operand[2].mode;
23363 modev3 = insn_data[d->icode].operand[3].mode;
23364 modeimm = insn_data[d->icode].operand[4].mode;
23366 if (VECTOR_MODE_P (modev2))
23367 op0 = safe_vector_operand (op0, modev2);
23368 if (VECTOR_MODE_P (modev3))
23369 op1 = safe_vector_operand (op1, modev3);
23371 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23372 op0 = copy_to_mode_reg (modev2, op0);
23373 if ((optimize && !register_operand (op1, modev3))
23374 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23375 op1 = copy_to_mode_reg (modev3, op1);
23377 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23379 error ("the third argument must be a 8-bit immediate");
23383 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23385 if (optimize || !target
23386 || GET_MODE (target) != tmode0
23387 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23388 target = gen_reg_rtx (tmode0);
23390 scratch1 = gen_reg_rtx (tmode1);
23392 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23394 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23396 if (optimize || !target
23397 || GET_MODE (target) != tmode1
23398 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23399 target = gen_reg_rtx (tmode1);
23401 scratch0 = gen_reg_rtx (tmode0);
23403 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23407 gcc_assert (d->flag);
23409 scratch0 = gen_reg_rtx (tmode0);
23410 scratch1 = gen_reg_rtx (tmode1);
23412 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
23422 target = gen_reg_rtx (SImode);
23423 emit_move_insn (target, const0_rtx);
23424 target = gen_rtx_SUBREG (QImode, target, 0);
23427 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23428 gen_rtx_fmt_ee (EQ, QImode,
23429 gen_rtx_REG ((enum machine_mode) d->flag,
23432 return SUBREG_REG (target);
23438 /* Subroutine of ix86_expand_builtin to take care of insns with
23439 variable number of operands. */
23442 ix86_expand_args_builtin (const struct builtin_description *d,
23443 tree exp, rtx target)
23445 rtx pat, real_target;
23446 unsigned int i, nargs;
23447 unsigned int nargs_constant = 0;
23448 int num_memory = 0;
23452 enum machine_mode mode;
23454 bool last_arg_count = false;
23455 enum insn_code icode = d->icode;
23456 const struct insn_data *insn_p = &insn_data[icode];
23457 enum machine_mode tmode = insn_p->operand[0].mode;
23458 enum machine_mode rmode = VOIDmode;
23460 enum rtx_code comparison = d->comparison;
23462 switch ((enum ix86_builtin_type) d->flag)
23464 case INT_FTYPE_V8SF_V8SF_PTEST:
23465 case INT_FTYPE_V4DI_V4DI_PTEST:
23466 case INT_FTYPE_V4DF_V4DF_PTEST:
23467 case INT_FTYPE_V4SF_V4SF_PTEST:
23468 case INT_FTYPE_V2DI_V2DI_PTEST:
23469 case INT_FTYPE_V2DF_V2DF_PTEST:
23470 return ix86_expand_sse_ptest (d, exp, target);
23471 case FLOAT128_FTYPE_FLOAT128:
23472 case FLOAT_FTYPE_FLOAT:
23473 case INT64_FTYPE_V4SF:
23474 case INT64_FTYPE_V2DF:
23475 case INT_FTYPE_V16QI:
23476 case INT_FTYPE_V8QI:
23477 case INT_FTYPE_V8SF:
23478 case INT_FTYPE_V4DF:
23479 case INT_FTYPE_V4SF:
23480 case INT_FTYPE_V2DF:
23481 case V16QI_FTYPE_V16QI:
23482 case V8SI_FTYPE_V8SF:
23483 case V8SI_FTYPE_V4SI:
23484 case V8HI_FTYPE_V8HI:
23485 case V8HI_FTYPE_V16QI:
23486 case V8QI_FTYPE_V8QI:
23487 case V8SF_FTYPE_V8SF:
23488 case V8SF_FTYPE_V8SI:
23489 case V8SF_FTYPE_V4SF:
23490 case V4SI_FTYPE_V4SI:
23491 case V4SI_FTYPE_V16QI:
23492 case V4SI_FTYPE_V4SF:
23493 case V4SI_FTYPE_V8SI:
23494 case V4SI_FTYPE_V8HI:
23495 case V4SI_FTYPE_V4DF:
23496 case V4SI_FTYPE_V2DF:
23497 case V4HI_FTYPE_V4HI:
23498 case V4DF_FTYPE_V4DF:
23499 case V4DF_FTYPE_V4SI:
23500 case V4DF_FTYPE_V4SF:
23501 case V4DF_FTYPE_V2DF:
23502 case V4SF_FTYPE_V4SF:
23503 case V4SF_FTYPE_V4SI:
23504 case V4SF_FTYPE_V8SF:
23505 case V4SF_FTYPE_V4DF:
23506 case V4SF_FTYPE_V2DF:
23507 case V2DI_FTYPE_V2DI:
23508 case V2DI_FTYPE_V16QI:
23509 case V2DI_FTYPE_V8HI:
23510 case V2DI_FTYPE_V4SI:
23511 case V2DF_FTYPE_V2DF:
23512 case V2DF_FTYPE_V4SI:
23513 case V2DF_FTYPE_V4DF:
23514 case V2DF_FTYPE_V4SF:
23515 case V2DF_FTYPE_V2SI:
23516 case V2SI_FTYPE_V2SI:
23517 case V2SI_FTYPE_V4SF:
23518 case V2SI_FTYPE_V2SF:
23519 case V2SI_FTYPE_V2DF:
23520 case V2SF_FTYPE_V2SF:
23521 case V2SF_FTYPE_V2SI:
23524 case V4SF_FTYPE_V4SF_VEC_MERGE:
23525 case V2DF_FTYPE_V2DF_VEC_MERGE:
23526 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
23527 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
23528 case V16QI_FTYPE_V16QI_V16QI:
23529 case V16QI_FTYPE_V8HI_V8HI:
23530 case V8QI_FTYPE_V8QI_V8QI:
23531 case V8QI_FTYPE_V4HI_V4HI:
23532 case V8HI_FTYPE_V8HI_V8HI:
23533 case V8HI_FTYPE_V16QI_V16QI:
23534 case V8HI_FTYPE_V4SI_V4SI:
23535 case V8SF_FTYPE_V8SF_V8SF:
23536 case V8SF_FTYPE_V8SF_V8SI:
23537 case V4SI_FTYPE_V4SI_V4SI:
23538 case V4SI_FTYPE_V8HI_V8HI:
23539 case V4SI_FTYPE_V4SF_V4SF:
23540 case V4SI_FTYPE_V2DF_V2DF:
23541 case V4HI_FTYPE_V4HI_V4HI:
23542 case V4HI_FTYPE_V8QI_V8QI:
23543 case V4HI_FTYPE_V2SI_V2SI:
23544 case V4DF_FTYPE_V4DF_V4DF:
23545 case V4DF_FTYPE_V4DF_V4DI:
23546 case V4SF_FTYPE_V4SF_V4SF:
23547 case V4SF_FTYPE_V4SF_V4SI:
23548 case V4SF_FTYPE_V4SF_V2SI:
23549 case V4SF_FTYPE_V4SF_V2DF:
23550 case V4SF_FTYPE_V4SF_DI:
23551 case V4SF_FTYPE_V4SF_SI:
23552 case V2DI_FTYPE_V2DI_V2DI:
23553 case V2DI_FTYPE_V16QI_V16QI:
23554 case V2DI_FTYPE_V4SI_V4SI:
23555 case V2DI_FTYPE_V2DI_V16QI:
23556 case V2DI_FTYPE_V2DF_V2DF:
23557 case V2SI_FTYPE_V2SI_V2SI:
23558 case V2SI_FTYPE_V4HI_V4HI:
23559 case V2SI_FTYPE_V2SF_V2SF:
23560 case V2DF_FTYPE_V2DF_V2DF:
23561 case V2DF_FTYPE_V2DF_V4SF:
23562 case V2DF_FTYPE_V2DF_V2DI:
23563 case V2DF_FTYPE_V2DF_DI:
23564 case V2DF_FTYPE_V2DF_SI:
23565 case V2SF_FTYPE_V2SF_V2SF:
23566 case V1DI_FTYPE_V1DI_V1DI:
23567 case V1DI_FTYPE_V8QI_V8QI:
23568 case V1DI_FTYPE_V2SI_V2SI:
23569 if (comparison == UNKNOWN)
23570 return ix86_expand_binop_builtin (icode, exp, target);
23573 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23574 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23575 gcc_assert (comparison != UNKNOWN);
23579 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23580 case V8HI_FTYPE_V8HI_SI_COUNT:
23581 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23582 case V4SI_FTYPE_V4SI_SI_COUNT:
23583 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23584 case V4HI_FTYPE_V4HI_SI_COUNT:
23585 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23586 case V2DI_FTYPE_V2DI_SI_COUNT:
23587 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23588 case V2SI_FTYPE_V2SI_SI_COUNT:
23589 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23590 case V1DI_FTYPE_V1DI_SI_COUNT:
23592 last_arg_count = true;
23594 case UINT64_FTYPE_UINT64_UINT64:
23595 case UINT_FTYPE_UINT_UINT:
23596 case UINT_FTYPE_UINT_USHORT:
23597 case UINT_FTYPE_UINT_UCHAR:
23600 case V2DI2TI_FTYPE_V2DI_INT:
23603 nargs_constant = 1;
23605 case V8HI_FTYPE_V8HI_INT:
23606 case V8SF_FTYPE_V8SF_INT:
23607 case V4SI_FTYPE_V4SI_INT:
23608 case V4SI_FTYPE_V8SI_INT:
23609 case V4HI_FTYPE_V4HI_INT:
23610 case V4DF_FTYPE_V4DF_INT:
23611 case V4SF_FTYPE_V4SF_INT:
23612 case V4SF_FTYPE_V8SF_INT:
23613 case V2DI_FTYPE_V2DI_INT:
23614 case V2DF_FTYPE_V2DF_INT:
23615 case V2DF_FTYPE_V4DF_INT:
23617 nargs_constant = 1;
23619 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23620 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23621 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23622 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23623 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23626 case V16QI_FTYPE_V16QI_V16QI_INT:
23627 case V8HI_FTYPE_V8HI_V8HI_INT:
23628 case V8SI_FTYPE_V8SI_V8SI_INT:
23629 case V8SI_FTYPE_V8SI_V4SI_INT:
23630 case V8SF_FTYPE_V8SF_V8SF_INT:
23631 case V8SF_FTYPE_V8SF_V4SF_INT:
23632 case V4SI_FTYPE_V4SI_V4SI_INT:
23633 case V4DF_FTYPE_V4DF_V4DF_INT:
23634 case V4DF_FTYPE_V4DF_V2DF_INT:
23635 case V4SF_FTYPE_V4SF_V4SF_INT:
23636 case V2DI_FTYPE_V2DI_V2DI_INT:
23637 case V2DF_FTYPE_V2DF_V2DF_INT:
23639 nargs_constant = 1;
23641 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23644 nargs_constant = 1;
23646 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23649 nargs_constant = 1;
23651 case V2DI_FTYPE_V2DI_UINT_UINT:
23653 nargs_constant = 2;
23655 case V8SF_FTYPE_V8SF_V8SF_V8SI_INT:
23656 case V4DF_FTYPE_V4DF_V4DF_V4DI_INT:
23657 case V4SF_FTYPE_V4SF_V4SF_V4SI_INT:
23658 case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
23660 nargs_constant = 1;
23662 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23664 nargs_constant = 2;
23667 gcc_unreachable ();
23670 gcc_assert (nargs <= ARRAY_SIZE (args));
23672 if (comparison != UNKNOWN)
23674 gcc_assert (nargs == 2);
23675 return ix86_expand_sse_compare (d, exp, target, swap);
23678 if (rmode == VOIDmode || rmode == tmode)
23682 || GET_MODE (target) != tmode
23683 || ! (*insn_p->operand[0].predicate) (target, tmode))
23684 target = gen_reg_rtx (tmode);
23685 real_target = target;
23689 target = gen_reg_rtx (rmode);
23690 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
23693 for (i = 0; i < nargs; i++)
23695 tree arg = CALL_EXPR_ARG (exp, i);
23696 rtx op = expand_normal (arg);
23697 enum machine_mode mode = insn_p->operand[i + 1].mode;
23698 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
23700 if (last_arg_count && (i + 1) == nargs)
23702 /* SIMD shift insns take either an 8-bit immediate or
23703 register as count. But builtin functions take int as
23704 count. If count doesn't match, we put it in register. */
23707 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
23708 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
23709 op = copy_to_reg (op);
23712 else if ((nargs - i) <= nargs_constant)
23717 case CODE_FOR_sse4_1_roundpd:
23718 case CODE_FOR_sse4_1_roundps:
23719 case CODE_FOR_sse4_1_roundsd:
23720 case CODE_FOR_sse4_1_roundss:
23721 case CODE_FOR_sse4_1_blendps:
23722 case CODE_FOR_avx_blendpd256:
23723 case CODE_FOR_avx_vpermilv4df:
23724 case CODE_FOR_avx_roundpd256:
23725 case CODE_FOR_avx_roundps256:
23726 error ("the last argument must be a 4-bit immediate");
23729 case CODE_FOR_sse4_1_blendpd:
23730 case CODE_FOR_avx_vpermilv2df:
23731 case CODE_FOR_avx_vpermil2v2df3:
23732 case CODE_FOR_avx_vpermil2v4sf3:
23733 case CODE_FOR_avx_vpermil2v4df3:
23734 case CODE_FOR_avx_vpermil2v8sf3:
23735 error ("the last argument must be a 2-bit immediate");
23738 case CODE_FOR_avx_vextractf128v4df:
23739 case CODE_FOR_avx_vextractf128v8sf:
23740 case CODE_FOR_avx_vextractf128v8si:
23741 case CODE_FOR_avx_vinsertf128v4df:
23742 case CODE_FOR_avx_vinsertf128v8sf:
23743 case CODE_FOR_avx_vinsertf128v8si:
23744 error ("the last argument must be a 1-bit immediate");
23747 case CODE_FOR_avx_cmpsdv2df3:
23748 case CODE_FOR_avx_cmpssv4sf3:
23749 case CODE_FOR_avx_cmppdv2df3:
23750 case CODE_FOR_avx_cmppsv4sf3:
23751 case CODE_FOR_avx_cmppdv4df3:
23752 case CODE_FOR_avx_cmppsv8sf3:
23753 error ("the last argument must be a 5-bit immediate");
23757 switch (nargs_constant)
23760 if ((nargs - i) == nargs_constant)
23762 error ("the next to last argument must be an 8-bit immediate");
23766 error ("the last argument must be an 8-bit immediate");
23769 gcc_unreachable ();
23776 if (VECTOR_MODE_P (mode))
23777 op = safe_vector_operand (op, mode);
23779 /* If we aren't optimizing, only allow one memory operand to
23781 if (memory_operand (op, mode))
23784 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
23786 if (optimize || !match || num_memory > 1)
23787 op = copy_to_mode_reg (mode, op);
23791 op = copy_to_reg (op);
23792 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
23797 args[i].mode = mode;
23803 pat = GEN_FCN (icode) (real_target, args[0].op);
23806 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
23809 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
23813 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
23814 args[2].op, args[3].op);
23817 gcc_unreachable ();
23827 /* Subroutine of ix86_expand_builtin to take care of special insns
23828 with variable number of operands. */
23831 ix86_expand_special_args_builtin (const struct builtin_description *d,
23832 tree exp, rtx target)
23836 unsigned int i, nargs, arg_adjust, memory;
23840 enum machine_mode mode;
23842 enum insn_code icode = d->icode;
23843 bool last_arg_constant = false;
23844 const struct insn_data *insn_p = &insn_data[icode];
23845 enum machine_mode tmode = insn_p->operand[0].mode;
23846 enum { load, store } klass;
23848 switch ((enum ix86_special_builtin_type) d->flag)
23850 case VOID_FTYPE_VOID:
23851 emit_insn (GEN_FCN (icode) (target));
23853 case V2DI_FTYPE_PV2DI:
23854 case V32QI_FTYPE_PCCHAR:
23855 case V16QI_FTYPE_PCCHAR:
23856 case V8SF_FTYPE_PCV4SF:
23857 case V8SF_FTYPE_PCFLOAT:
23858 case V4SF_FTYPE_PCFLOAT:
23859 case V4DF_FTYPE_PCV2DF:
23860 case V4DF_FTYPE_PCDOUBLE:
23861 case V2DF_FTYPE_PCDOUBLE:
23866 case VOID_FTYPE_PV2SF_V4SF:
23867 case VOID_FTYPE_PV2DI_V2DI:
23868 case VOID_FTYPE_PCHAR_V32QI:
23869 case VOID_FTYPE_PCHAR_V16QI:
23870 case VOID_FTYPE_PFLOAT_V8SF:
23871 case VOID_FTYPE_PFLOAT_V4SF:
23872 case VOID_FTYPE_PDOUBLE_V4DF:
23873 case VOID_FTYPE_PDOUBLE_V2DF:
23874 case VOID_FTYPE_PDI_DI:
23875 case VOID_FTYPE_PINT_INT:
23878 /* Reserve memory operand for target. */
23879 memory = ARRAY_SIZE (args);
23881 case V4SF_FTYPE_V4SF_PCV2SF:
23882 case V2DF_FTYPE_V2DF_PCDOUBLE:
23887 case V8SF_FTYPE_PCV8SF_V8SF:
23888 case V4DF_FTYPE_PCV4DF_V4DF:
23889 case V4SF_FTYPE_PCV4SF_V4SF:
23890 case V2DF_FTYPE_PCV2DF_V2DF:
23895 case VOID_FTYPE_PV8SF_V8SF_V8SF:
23896 case VOID_FTYPE_PV4DF_V4DF_V4DF:
23897 case VOID_FTYPE_PV4SF_V4SF_V4SF:
23898 case VOID_FTYPE_PV2DF_V2DF_V2DF:
23901 /* Reserve memory operand for target. */
23902 memory = ARRAY_SIZE (args);
23905 gcc_unreachable ();
23908 gcc_assert (nargs <= ARRAY_SIZE (args));
23910 if (klass == store)
23912 arg = CALL_EXPR_ARG (exp, 0);
23913 op = expand_normal (arg);
23914 gcc_assert (target == 0);
23915 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
23923 || GET_MODE (target) != tmode
23924 || ! (*insn_p->operand[0].predicate) (target, tmode))
23925 target = gen_reg_rtx (tmode);
23928 for (i = 0; i < nargs; i++)
23930 enum machine_mode mode = insn_p->operand[i + 1].mode;
23933 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
23934 op = expand_normal (arg);
23935 match = (*insn_p->operand[i + 1].predicate) (op, mode);
23937 if (last_arg_constant && (i + 1) == nargs)
23943 error ("the last argument must be an 8-bit immediate");
23951 /* This must be the memory operand. */
23952 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
23953 gcc_assert (GET_MODE (op) == mode
23954 || GET_MODE (op) == VOIDmode);
23958 /* This must be register. */
23959 if (VECTOR_MODE_P (mode))
23960 op = safe_vector_operand (op, mode);
23962 gcc_assert (GET_MODE (op) == mode
23963 || GET_MODE (op) == VOIDmode);
23964 op = copy_to_mode_reg (mode, op);
23969 args[i].mode = mode;
23975 pat = GEN_FCN (icode) (target, args[0].op);
23978 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23981 gcc_unreachable ();
23987 return klass == store ? 0 : target;
23990 /* Return the integer constant in ARG. Constrain it to be in the range
23991 of the subparts of VEC_TYPE; issue an error if not. */
23994 get_element_number (tree vec_type, tree arg)
23996 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
23998 if (!host_integerp (arg, 1)
23999 || (elt = tree_low_cst (arg, 1), elt > max))
24001 error ("selector must be an integer constant in the range 0..%wi", max);
24008 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24009 ix86_expand_vector_init. We DO have language-level syntax for this, in
24010 the form of (type){ init-list }. Except that since we can't place emms
24011 instructions from inside the compiler, we can't allow the use of MMX
24012 registers unless the user explicitly asks for it. So we do *not* define
24013 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24014 we have builtins invoked by mmintrin.h that gives us license to emit
24015 these sorts of instructions. */
24018 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24020 enum machine_mode tmode = TYPE_MODE (type);
24021 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24022 int i, n_elt = GET_MODE_NUNITS (tmode);
24023 rtvec v = rtvec_alloc (n_elt);
24025 gcc_assert (VECTOR_MODE_P (tmode));
24026 gcc_assert (call_expr_nargs (exp) == n_elt);
24028 for (i = 0; i < n_elt; ++i)
24030 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24031 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24034 if (!target || !register_operand (target, tmode))
24035 target = gen_reg_rtx (tmode);
24037 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24041 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24042 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24043 had a language-level syntax for referencing vector elements. */
24046 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24048 enum machine_mode tmode, mode0;
24053 arg0 = CALL_EXPR_ARG (exp, 0);
24054 arg1 = CALL_EXPR_ARG (exp, 1);
24056 op0 = expand_normal (arg0);
24057 elt = get_element_number (TREE_TYPE (arg0), arg1);
24059 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24060 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24061 gcc_assert (VECTOR_MODE_P (mode0));
24063 op0 = force_reg (mode0, op0);
24065 if (optimize || !target || !register_operand (target, tmode))
24066 target = gen_reg_rtx (tmode);
24068 ix86_expand_vector_extract (true, target, op0, elt);
24073 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24074 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24075 a language-level syntax for referencing vector elements. */
24078 ix86_expand_vec_set_builtin (tree exp)
24080 enum machine_mode tmode, mode1;
24081 tree arg0, arg1, arg2;
24083 rtx op0, op1, target;
24085 arg0 = CALL_EXPR_ARG (exp, 0);
24086 arg1 = CALL_EXPR_ARG (exp, 1);
24087 arg2 = CALL_EXPR_ARG (exp, 2);
24089 tmode = TYPE_MODE (TREE_TYPE (arg0));
24090 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24091 gcc_assert (VECTOR_MODE_P (tmode));
24093 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24094 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24095 elt = get_element_number (TREE_TYPE (arg0), arg2);
24097 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24098 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24100 op0 = force_reg (tmode, op0);
24101 op1 = force_reg (mode1, op1);
24103 /* OP0 is the source of these builtin functions and shouldn't be
24104 modified. Create a copy, use it and return it as target. */
24105 target = gen_reg_rtx (tmode);
24106 emit_move_insn (target, op0);
24107 ix86_expand_vector_set (true, target, op1, elt);
24112 /* Expand an expression EXP that calls a built-in function,
24113 with result going to TARGET if that's convenient
24114 (and in mode MODE if that's convenient).
24115 SUBTARGET may be used as the target for computing one of EXP's operands.
24116 IGNORE is nonzero if the value is to be ignored. */
24119 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24120 enum machine_mode mode ATTRIBUTE_UNUSED,
24121 int ignore ATTRIBUTE_UNUSED)
24123 const struct builtin_description *d;
24125 enum insn_code icode;
24126 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24127 tree arg0, arg1, arg2;
24128 rtx op0, op1, op2, pat;
24129 enum machine_mode mode0, mode1, mode2;
24130 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24132 /* Determine whether the builtin function is available under the current ISA.
24133 Originally the builtin was not created if it wasn't applicable to the
24134 current ISA based on the command line switches. With function specific
24135 options, we need to check in the context of the function making the call
24136 whether it is supported. */
24137 if (ix86_builtins_isa[fcode].isa
24138 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24140 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24141 NULL, NULL, false);
24144 error ("%qE needs unknown isa option", fndecl);
24147 gcc_assert (opts != NULL);
24148 error ("%qE needs isa option %s", fndecl, opts);
24156 case IX86_BUILTIN_MASKMOVQ:
24157 case IX86_BUILTIN_MASKMOVDQU:
24158 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24159 ? CODE_FOR_mmx_maskmovq
24160 : CODE_FOR_sse2_maskmovdqu);
24161 /* Note the arg order is different from the operand order. */
24162 arg1 = CALL_EXPR_ARG (exp, 0);
24163 arg2 = CALL_EXPR_ARG (exp, 1);
24164 arg0 = CALL_EXPR_ARG (exp, 2);
24165 op0 = expand_normal (arg0);
24166 op1 = expand_normal (arg1);
24167 op2 = expand_normal (arg2);
24168 mode0 = insn_data[icode].operand[0].mode;
24169 mode1 = insn_data[icode].operand[1].mode;
24170 mode2 = insn_data[icode].operand[2].mode;
24172 op0 = force_reg (Pmode, op0);
24173 op0 = gen_rtx_MEM (mode1, op0);
24175 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24176 op0 = copy_to_mode_reg (mode0, op0);
24177 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24178 op1 = copy_to_mode_reg (mode1, op1);
24179 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24180 op2 = copy_to_mode_reg (mode2, op2);
24181 pat = GEN_FCN (icode) (op0, op1, op2);
24187 case IX86_BUILTIN_LDMXCSR:
24188 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24189 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24190 emit_move_insn (target, op0);
24191 emit_insn (gen_sse_ldmxcsr (target));
24194 case IX86_BUILTIN_STMXCSR:
24195 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24196 emit_insn (gen_sse_stmxcsr (target));
24197 return copy_to_mode_reg (SImode, target);
24199 case IX86_BUILTIN_CLFLUSH:
24200 arg0 = CALL_EXPR_ARG (exp, 0);
24201 op0 = expand_normal (arg0);
24202 icode = CODE_FOR_sse2_clflush;
24203 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24204 op0 = copy_to_mode_reg (Pmode, op0);
24206 emit_insn (gen_sse2_clflush (op0));
24209 case IX86_BUILTIN_MONITOR:
24210 arg0 = CALL_EXPR_ARG (exp, 0);
24211 arg1 = CALL_EXPR_ARG (exp, 1);
24212 arg2 = CALL_EXPR_ARG (exp, 2);
24213 op0 = expand_normal (arg0);
24214 op1 = expand_normal (arg1);
24215 op2 = expand_normal (arg2);
24217 op0 = copy_to_mode_reg (Pmode, op0);
24219 op1 = copy_to_mode_reg (SImode, op1);
24221 op2 = copy_to_mode_reg (SImode, op2);
24222 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24225 case IX86_BUILTIN_MWAIT:
24226 arg0 = CALL_EXPR_ARG (exp, 0);
24227 arg1 = CALL_EXPR_ARG (exp, 1);
24228 op0 = expand_normal (arg0);
24229 op1 = expand_normal (arg1);
24231 op0 = copy_to_mode_reg (SImode, op0);
24233 op1 = copy_to_mode_reg (SImode, op1);
24234 emit_insn (gen_sse3_mwait (op0, op1));
24237 case IX86_BUILTIN_VEC_INIT_V2SI:
24238 case IX86_BUILTIN_VEC_INIT_V4HI:
24239 case IX86_BUILTIN_VEC_INIT_V8QI:
24240 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24242 case IX86_BUILTIN_VEC_EXT_V2DF:
24243 case IX86_BUILTIN_VEC_EXT_V2DI:
24244 case IX86_BUILTIN_VEC_EXT_V4SF:
24245 case IX86_BUILTIN_VEC_EXT_V4SI:
24246 case IX86_BUILTIN_VEC_EXT_V8HI:
24247 case IX86_BUILTIN_VEC_EXT_V2SI:
24248 case IX86_BUILTIN_VEC_EXT_V4HI:
24249 case IX86_BUILTIN_VEC_EXT_V16QI:
24250 return ix86_expand_vec_ext_builtin (exp, target);
24252 case IX86_BUILTIN_VEC_SET_V2DI:
24253 case IX86_BUILTIN_VEC_SET_V4SF:
24254 case IX86_BUILTIN_VEC_SET_V4SI:
24255 case IX86_BUILTIN_VEC_SET_V8HI:
24256 case IX86_BUILTIN_VEC_SET_V4HI:
24257 case IX86_BUILTIN_VEC_SET_V16QI:
24258 return ix86_expand_vec_set_builtin (exp);
24260 case IX86_BUILTIN_INFQ:
24262 REAL_VALUE_TYPE inf;
24266 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24268 tmp = validize_mem (force_const_mem (mode, tmp));
24271 target = gen_reg_rtx (mode);
24273 emit_move_insn (target, tmp);
24281 for (i = 0, d = bdesc_special_args;
24282 i < ARRAY_SIZE (bdesc_special_args);
24284 if (d->code == fcode)
24285 return ix86_expand_special_args_builtin (d, exp, target);
24287 for (i = 0, d = bdesc_args;
24288 i < ARRAY_SIZE (bdesc_args);
24290 if (d->code == fcode)
24293 case IX86_BUILTIN_FABSQ:
24294 case IX86_BUILTIN_COPYSIGNQ:
24296 /* Emit a normal call if SSE2 isn't available. */
24297 return expand_call (exp, target, ignore);
24299 return ix86_expand_args_builtin (d, exp, target);
24302 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24303 if (d->code == fcode)
24304 return ix86_expand_sse_comi (d, exp, target);
24306 for (i = 0, d = bdesc_pcmpestr;
24307 i < ARRAY_SIZE (bdesc_pcmpestr);
24309 if (d->code == fcode)
24310 return ix86_expand_sse_pcmpestr (d, exp, target);
24312 for (i = 0, d = bdesc_pcmpistr;
24313 i < ARRAY_SIZE (bdesc_pcmpistr);
24315 if (d->code == fcode)
24316 return ix86_expand_sse_pcmpistr (d, exp, target);
24318 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24319 if (d->code == fcode)
24320 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24321 (enum multi_arg_type)d->flag,
24324 gcc_unreachable ();
24327 /* Returns a function decl for a vectorized version of the builtin function
24328 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24329 if it is not available. */
24332 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24335 enum machine_mode in_mode, out_mode;
24338 if (TREE_CODE (type_out) != VECTOR_TYPE
24339 || TREE_CODE (type_in) != VECTOR_TYPE)
24342 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24343 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24344 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24345 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24349 case BUILT_IN_SQRT:
24350 if (out_mode == DFmode && out_n == 2
24351 && in_mode == DFmode && in_n == 2)
24352 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24355 case BUILT_IN_SQRTF:
24356 if (out_mode == SFmode && out_n == 4
24357 && in_mode == SFmode && in_n == 4)
24358 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24361 case BUILT_IN_LRINT:
24362 if (out_mode == SImode && out_n == 4
24363 && in_mode == DFmode && in_n == 2)
24364 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24367 case BUILT_IN_LRINTF:
24368 if (out_mode == SImode && out_n == 4
24369 && in_mode == SFmode && in_n == 4)
24370 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24377 /* Dispatch to a handler for a vectorization library. */
24378 if (ix86_veclib_handler)
24379 return (*ix86_veclib_handler)(fn, type_out, type_in);
24384 /* Handler for an SVML-style interface to
24385 a library with vectorized intrinsics. */
24388 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24391 tree fntype, new_fndecl, args;
24394 enum machine_mode el_mode, in_mode;
24397 /* The SVML is suitable for unsafe math only. */
24398 if (!flag_unsafe_math_optimizations)
24401 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24402 n = TYPE_VECTOR_SUBPARTS (type_out);
24403 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24404 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24405 if (el_mode != in_mode
24413 case BUILT_IN_LOG10:
24415 case BUILT_IN_TANH:
24417 case BUILT_IN_ATAN:
24418 case BUILT_IN_ATAN2:
24419 case BUILT_IN_ATANH:
24420 case BUILT_IN_CBRT:
24421 case BUILT_IN_SINH:
24423 case BUILT_IN_ASINH:
24424 case BUILT_IN_ASIN:
24425 case BUILT_IN_COSH:
24427 case BUILT_IN_ACOSH:
24428 case BUILT_IN_ACOS:
24429 if (el_mode != DFmode || n != 2)
24433 case BUILT_IN_EXPF:
24434 case BUILT_IN_LOGF:
24435 case BUILT_IN_LOG10F:
24436 case BUILT_IN_POWF:
24437 case BUILT_IN_TANHF:
24438 case BUILT_IN_TANF:
24439 case BUILT_IN_ATANF:
24440 case BUILT_IN_ATAN2F:
24441 case BUILT_IN_ATANHF:
24442 case BUILT_IN_CBRTF:
24443 case BUILT_IN_SINHF:
24444 case BUILT_IN_SINF:
24445 case BUILT_IN_ASINHF:
24446 case BUILT_IN_ASINF:
24447 case BUILT_IN_COSHF:
24448 case BUILT_IN_COSF:
24449 case BUILT_IN_ACOSHF:
24450 case BUILT_IN_ACOSF:
24451 if (el_mode != SFmode || n != 4)
24459 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24461 if (fn == BUILT_IN_LOGF)
24462 strcpy (name, "vmlsLn4");
24463 else if (fn == BUILT_IN_LOG)
24464 strcpy (name, "vmldLn2");
24467 sprintf (name, "vmls%s", bname+10);
24468 name[strlen (name)-1] = '4';
24471 sprintf (name, "vmld%s2", bname+10);
24473 /* Convert to uppercase. */
24477 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24478 args = TREE_CHAIN (args))
24482 fntype = build_function_type_list (type_out, type_in, NULL);
24484 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24486 /* Build a function declaration for the vectorized function. */
24487 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
24488 TREE_PUBLIC (new_fndecl) = 1;
24489 DECL_EXTERNAL (new_fndecl) = 1;
24490 DECL_IS_NOVOPS (new_fndecl) = 1;
24491 TREE_READONLY (new_fndecl) = 1;
24496 /* Handler for an ACML-style interface to
24497 a library with vectorized intrinsics. */
24500 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
24502 char name[20] = "__vr.._";
24503 tree fntype, new_fndecl, args;
24506 enum machine_mode el_mode, in_mode;
24509 /* The ACML is 64bits only and suitable for unsafe math only as
24510 it does not correctly support parts of IEEE with the required
24511 precision such as denormals. */
24513 || !flag_unsafe_math_optimizations)
24516 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24517 n = TYPE_VECTOR_SUBPARTS (type_out);
24518 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24519 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24520 if (el_mode != in_mode
24530 case BUILT_IN_LOG2:
24531 case BUILT_IN_LOG10:
24534 if (el_mode != DFmode
24539 case BUILT_IN_SINF:
24540 case BUILT_IN_COSF:
24541 case BUILT_IN_EXPF:
24542 case BUILT_IN_POWF:
24543 case BUILT_IN_LOGF:
24544 case BUILT_IN_LOG2F:
24545 case BUILT_IN_LOG10F:
24548 if (el_mode != SFmode
24557 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24558 sprintf (name + 7, "%s", bname+10);
24561 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24562 args = TREE_CHAIN (args))
24566 fntype = build_function_type_list (type_out, type_in, NULL);
24568 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24570 /* Build a function declaration for the vectorized function. */
24571 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
24572 TREE_PUBLIC (new_fndecl) = 1;
24573 DECL_EXTERNAL (new_fndecl) = 1;
24574 DECL_IS_NOVOPS (new_fndecl) = 1;
24575 TREE_READONLY (new_fndecl) = 1;
24581 /* Returns a decl of a function that implements conversion of an integer vector
24582 into a floating-point vector, or vice-versa. TYPE is the type of the integer
24583 side of the conversion.
24584 Return NULL_TREE if it is not available. */
24587 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
24589 if (TREE_CODE (type) != VECTOR_TYPE)
24595 switch (TYPE_MODE (type))
24598 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
24603 case FIX_TRUNC_EXPR:
24604 switch (TYPE_MODE (type))
24607 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
24617 /* Returns a code for a target-specific builtin that implements
24618 reciprocal of the function, or NULL_TREE if not available. */
24621 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
24622 bool sqrt ATTRIBUTE_UNUSED)
24624 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
24625 && flag_finite_math_only && !flag_trapping_math
24626 && flag_unsafe_math_optimizations))
24630 /* Machine dependent builtins. */
24633 /* Vectorized version of sqrt to rsqrt conversion. */
24634 case IX86_BUILTIN_SQRTPS_NR:
24635 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
24641 /* Normal builtins. */
24644 /* Sqrt to rsqrt conversion. */
24645 case BUILT_IN_SQRTF:
24646 return ix86_builtins[IX86_BUILTIN_RSQRTF];
24653 /* Store OPERAND to the memory after reload is completed. This means
24654 that we can't easily use assign_stack_local. */
24656 ix86_force_to_memory (enum machine_mode mode, rtx operand)
24660 gcc_assert (reload_completed);
24661 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
24663 result = gen_rtx_MEM (mode,
24664 gen_rtx_PLUS (Pmode,
24666 GEN_INT (-RED_ZONE_SIZE)));
24667 emit_move_insn (result, operand);
24669 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
24675 operand = gen_lowpart (DImode, operand);
24679 gen_rtx_SET (VOIDmode,
24680 gen_rtx_MEM (DImode,
24681 gen_rtx_PRE_DEC (DImode,
24682 stack_pointer_rtx)),
24686 gcc_unreachable ();
24688 result = gen_rtx_MEM (mode, stack_pointer_rtx);
24697 split_di (&operand, 1, operands, operands + 1);
24699 gen_rtx_SET (VOIDmode,
24700 gen_rtx_MEM (SImode,
24701 gen_rtx_PRE_DEC (Pmode,
24702 stack_pointer_rtx)),
24705 gen_rtx_SET (VOIDmode,
24706 gen_rtx_MEM (SImode,
24707 gen_rtx_PRE_DEC (Pmode,
24708 stack_pointer_rtx)),
24713 /* Store HImodes as SImodes. */
24714 operand = gen_lowpart (SImode, operand);
24718 gen_rtx_SET (VOIDmode,
24719 gen_rtx_MEM (GET_MODE (operand),
24720 gen_rtx_PRE_DEC (SImode,
24721 stack_pointer_rtx)),
24725 gcc_unreachable ();
24727 result = gen_rtx_MEM (mode, stack_pointer_rtx);
24732 /* Free operand from the memory. */
24734 ix86_free_from_memory (enum machine_mode mode)
24736 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
24740 if (mode == DImode || TARGET_64BIT)
24744 /* Use LEA to deallocate stack space. In peephole2 it will be converted
24745 to pop or add instruction if registers are available. */
24746 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
24747 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
24752 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
24753 QImode must go into class Q_REGS.
24754 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
24755 movdf to do mem-to-mem moves through integer regs. */
24757 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
24759 enum machine_mode mode = GET_MODE (x);
24761 /* We're only allowed to return a subclass of CLASS. Many of the
24762 following checks fail for NO_REGS, so eliminate that early. */
24763 if (regclass == NO_REGS)
24766 /* All classes can load zeros. */
24767 if (x == CONST0_RTX (mode))
24770 /* Force constants into memory if we are loading a (nonzero) constant into
24771 an MMX or SSE register. This is because there are no MMX/SSE instructions
24772 to load from a constant. */
24774 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
24777 /* Prefer SSE regs only, if we can use them for math. */
24778 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
24779 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
24781 /* Floating-point constants need more complex checks. */
24782 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
24784 /* General regs can load everything. */
24785 if (reg_class_subset_p (regclass, GENERAL_REGS))
24788 /* Floats can load 0 and 1 plus some others. Note that we eliminated
24789 zero above. We only want to wind up preferring 80387 registers if
24790 we plan on doing computation with them. */
24792 && standard_80387_constant_p (x))
24794 /* Limit class to non-sse. */
24795 if (regclass == FLOAT_SSE_REGS)
24797 if (regclass == FP_TOP_SSE_REGS)
24799 if (regclass == FP_SECOND_SSE_REGS)
24800 return FP_SECOND_REG;
24801 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
24808 /* Generally when we see PLUS here, it's the function invariant
24809 (plus soft-fp const_int). Which can only be computed into general
24811 if (GET_CODE (x) == PLUS)
24812 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
24814 /* QImode constants are easy to load, but non-constant QImode data
24815 must go into Q_REGS. */
24816 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
24818 if (reg_class_subset_p (regclass, Q_REGS))
24820 if (reg_class_subset_p (Q_REGS, regclass))
24828 /* Discourage putting floating-point values in SSE registers unless
24829 SSE math is being used, and likewise for the 387 registers. */
24831 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
24833 enum machine_mode mode = GET_MODE (x);
24835 /* Restrict the output reload class to the register bank that we are doing
24836 math on. If we would like not to return a subset of CLASS, reject this
24837 alternative: if reload cannot do this, it will still use its choice. */
24838 mode = GET_MODE (x);
24839 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
24840 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
24842 if (X87_FLOAT_MODE_P (mode))
24844 if (regclass == FP_TOP_SSE_REGS)
24846 else if (regclass == FP_SECOND_SSE_REGS)
24847 return FP_SECOND_REG;
24849 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
24855 static enum reg_class
24856 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
24857 enum machine_mode mode,
24858 secondary_reload_info *sri ATTRIBUTE_UNUSED)
24860 /* QImode spills from non-QI registers require
24861 intermediate register on 32bit targets. */
24862 if (!in_p && mode == QImode && !TARGET_64BIT
24863 && (rclass == GENERAL_REGS
24864 || rclass == LEGACY_REGS
24865 || rclass == INDEX_REGS))
24874 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
24875 regno = true_regnum (x);
24877 /* Return Q_REGS if the operand is in memory. */
24885 /* If we are copying between general and FP registers, we need a memory
24886 location. The same is true for SSE and MMX registers.
24888 To optimize register_move_cost performance, allow inline variant.
24890 The macro can't work reliably when one of the CLASSES is class containing
24891 registers from multiple units (SSE, MMX, integer). We avoid this by never
24892 combining those units in single alternative in the machine description.
24893 Ensure that this constraint holds to avoid unexpected surprises.
24895 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
24896 enforce these sanity checks. */
24899 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
24900 enum machine_mode mode, int strict)
24902 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
24903 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
24904 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
24905 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
24906 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
24907 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
24909 gcc_assert (!strict);
24913 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
24916 /* ??? This is a lie. We do have moves between mmx/general, and for
24917 mmx/sse2. But by saying we need secondary memory we discourage the
24918 register allocator from using the mmx registers unless needed. */
24919 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
24922 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
24924 /* SSE1 doesn't have any direct moves from other classes. */
24928 /* If the target says that inter-unit moves are more expensive
24929 than moving through memory, then don't generate them. */
24930 if (!TARGET_INTER_UNIT_MOVES)
24933 /* Between SSE and general, we have moves no larger than word size. */
24934 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
24942 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
24943 enum machine_mode mode, int strict)
24945 return inline_secondary_memory_needed (class1, class2, mode, strict);
24948 /* Return true if the registers in CLASS cannot represent the change from
24949 modes FROM to TO. */
24952 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
24953 enum reg_class regclass)
24958 /* x87 registers can't do subreg at all, as all values are reformatted
24959 to extended precision. */
24960 if (MAYBE_FLOAT_CLASS_P (regclass))
24963 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
24965 /* Vector registers do not support QI or HImode loads. If we don't
24966 disallow a change to these modes, reload will assume it's ok to
24967 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
24968 the vec_dupv4hi pattern. */
24969 if (GET_MODE_SIZE (from) < 4)
24972 /* Vector registers do not support subreg with nonzero offsets, which
24973 are otherwise valid for integer registers. Since we can't see
24974 whether we have a nonzero offset from here, prohibit all
24975 nonparadoxical subregs changing size. */
24976 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
24983 /* Return the cost of moving data of mode M between a
24984 register and memory. A value of 2 is the default; this cost is
24985 relative to those in `REGISTER_MOVE_COST'.
24987 This function is used extensively by register_move_cost that is used to
24988 build tables at startup. Make it inline in this case.
24989 When IN is 2, return maximum of in and out move cost.
24991 If moving between registers and memory is more expensive than
24992 between two registers, you should define this macro to express the
24995 Model also increased moving costs of QImode registers in non
24999 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25003 if (FLOAT_CLASS_P (regclass))
25021 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25022 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25024 if (SSE_CLASS_P (regclass))
25027 switch (GET_MODE_SIZE (mode))
25042 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25043 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25045 if (MMX_CLASS_P (regclass))
25048 switch (GET_MODE_SIZE (mode))
25060 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25061 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25063 switch (GET_MODE_SIZE (mode))
25066 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25069 return ix86_cost->int_store[0];
25070 if (TARGET_PARTIAL_REG_DEPENDENCY
25071 && optimize_function_for_speed_p (cfun))
25072 cost = ix86_cost->movzbl_load;
25074 cost = ix86_cost->int_load[0];
25076 return MAX (cost, ix86_cost->int_store[0]);
25082 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25084 return ix86_cost->movzbl_load;
25086 return ix86_cost->int_store[0] + 4;
25091 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25092 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25094 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25095 if (mode == TFmode)
25098 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25100 cost = ix86_cost->int_load[2];
25102 cost = ix86_cost->int_store[2];
25103 return (cost * (((int) GET_MODE_SIZE (mode)
25104 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25109 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25111 return inline_memory_move_cost (mode, regclass, in);
25115 /* Return the cost of moving data from a register in class CLASS1 to
25116 one in class CLASS2.
25118 It is not required that the cost always equal 2 when FROM is the same as TO;
25119 on some machines it is expensive to move between registers if they are not
25120 general registers. */
25123 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25124 enum reg_class class2)
25126 /* In case we require secondary memory, compute cost of the store followed
25127 by load. In order to avoid bad register allocation choices, we need
25128 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25130 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25134 cost += inline_memory_move_cost (mode, class1, 2);
25135 cost += inline_memory_move_cost (mode, class2, 2);
25137 /* In case of copying from general_purpose_register we may emit multiple
25138 stores followed by single load causing memory size mismatch stall.
25139 Count this as arbitrarily high cost of 20. */
25140 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25143 /* In the case of FP/MMX moves, the registers actually overlap, and we
25144 have to switch modes in order to treat them differently. */
25145 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25146 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25152 /* Moves between SSE/MMX and integer unit are expensive. */
25153 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25154 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25156 /* ??? By keeping returned value relatively high, we limit the number
25157 of moves between integer and MMX/SSE registers for all targets.
25158 Additionally, high value prevents problem with x86_modes_tieable_p(),
25159 where integer modes in MMX/SSE registers are not tieable
25160 because of missing QImode and HImode moves to, from or between
25161 MMX/SSE registers. */
25162 return MAX (8, ix86_cost->mmxsse_to_integer);
25164 if (MAYBE_FLOAT_CLASS_P (class1))
25165 return ix86_cost->fp_move;
25166 if (MAYBE_SSE_CLASS_P (class1))
25167 return ix86_cost->sse_move;
25168 if (MAYBE_MMX_CLASS_P (class1))
25169 return ix86_cost->mmx_move;
25173 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25176 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25178 /* Flags and only flags can only hold CCmode values. */
25179 if (CC_REGNO_P (regno))
25180 return GET_MODE_CLASS (mode) == MODE_CC;
25181 if (GET_MODE_CLASS (mode) == MODE_CC
25182 || GET_MODE_CLASS (mode) == MODE_RANDOM
25183 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25185 if (FP_REGNO_P (regno))
25186 return VALID_FP_MODE_P (mode);
25187 if (SSE_REGNO_P (regno))
25189 /* We implement the move patterns for all vector modes into and
25190 out of SSE registers, even when no operation instructions
25191 are available. OImode move is available only when AVX is
25193 return ((TARGET_AVX && mode == OImode)
25194 || VALID_AVX256_REG_MODE (mode)
25195 || VALID_SSE_REG_MODE (mode)
25196 || VALID_SSE2_REG_MODE (mode)
25197 || VALID_MMX_REG_MODE (mode)
25198 || VALID_MMX_REG_MODE_3DNOW (mode));
25200 if (MMX_REGNO_P (regno))
25202 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25203 so if the register is available at all, then we can move data of
25204 the given mode into or out of it. */
25205 return (VALID_MMX_REG_MODE (mode)
25206 || VALID_MMX_REG_MODE_3DNOW (mode));
25209 if (mode == QImode)
25211 /* Take care for QImode values - they can be in non-QI regs,
25212 but then they do cause partial register stalls. */
25213 if (regno < 4 || TARGET_64BIT)
25215 if (!TARGET_PARTIAL_REG_STALL)
25217 return reload_in_progress || reload_completed;
25219 /* We handle both integer and floats in the general purpose registers. */
25220 else if (VALID_INT_MODE_P (mode))
25222 else if (VALID_FP_MODE_P (mode))
25224 else if (VALID_DFP_MODE_P (mode))
25226 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25227 on to use that value in smaller contexts, this can easily force a
25228 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25229 supporting DImode, allow it. */
25230 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25236 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25237 tieable integer mode. */
25240 ix86_tieable_integer_mode_p (enum machine_mode mode)
25249 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25252 return TARGET_64BIT;
25259 /* Return true if MODE1 is accessible in a register that can hold MODE2
25260 without copying. That is, all register classes that can hold MODE2
25261 can also hold MODE1. */
25264 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25266 if (mode1 == mode2)
25269 if (ix86_tieable_integer_mode_p (mode1)
25270 && ix86_tieable_integer_mode_p (mode2))
25273 /* MODE2 being XFmode implies fp stack or general regs, which means we
25274 can tie any smaller floating point modes to it. Note that we do not
25275 tie this with TFmode. */
25276 if (mode2 == XFmode)
25277 return mode1 == SFmode || mode1 == DFmode;
25279 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25280 that we can tie it with SFmode. */
25281 if (mode2 == DFmode)
25282 return mode1 == SFmode;
25284 /* If MODE2 is only appropriate for an SSE register, then tie with
25285 any other mode acceptable to SSE registers. */
25286 if (GET_MODE_SIZE (mode2) == 16
25287 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25288 return (GET_MODE_SIZE (mode1) == 16
25289 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25291 /* If MODE2 is appropriate for an MMX register, then tie
25292 with any other mode acceptable to MMX registers. */
25293 if (GET_MODE_SIZE (mode2) == 8
25294 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25295 return (GET_MODE_SIZE (mode1) == 8
25296 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25301 /* Compute a (partial) cost for rtx X. Return true if the complete
25302 cost has been computed, and false if subexpressions should be
25303 scanned. In either case, *TOTAL contains the cost result. */
25306 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25308 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25309 enum machine_mode mode = GET_MODE (x);
25310 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25318 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25320 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25322 else if (flag_pic && SYMBOLIC_CONST (x)
25324 || (!GET_CODE (x) != LABEL_REF
25325 && (GET_CODE (x) != SYMBOL_REF
25326 || !SYMBOL_REF_LOCAL_P (x)))))
25333 if (mode == VOIDmode)
25336 switch (standard_80387_constant_p (x))
25341 default: /* Other constants */
25346 /* Start with (MEM (SYMBOL_REF)), since that's where
25347 it'll probably end up. Add a penalty for size. */
25348 *total = (COSTS_N_INSNS (1)
25349 + (flag_pic != 0 && !TARGET_64BIT)
25350 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25356 /* The zero extensions is often completely free on x86_64, so make
25357 it as cheap as possible. */
25358 if (TARGET_64BIT && mode == DImode
25359 && GET_MODE (XEXP (x, 0)) == SImode)
25361 else if (TARGET_ZERO_EXTEND_WITH_AND)
25362 *total = cost->add;
25364 *total = cost->movzx;
25368 *total = cost->movsx;
25372 if (CONST_INT_P (XEXP (x, 1))
25373 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25375 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25378 *total = cost->add;
25381 if ((value == 2 || value == 3)
25382 && cost->lea <= cost->shift_const)
25384 *total = cost->lea;
25394 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25396 if (CONST_INT_P (XEXP (x, 1)))
25398 if (INTVAL (XEXP (x, 1)) > 32)
25399 *total = cost->shift_const + COSTS_N_INSNS (2);
25401 *total = cost->shift_const * 2;
25405 if (GET_CODE (XEXP (x, 1)) == AND)
25406 *total = cost->shift_var * 2;
25408 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25413 if (CONST_INT_P (XEXP (x, 1)))
25414 *total = cost->shift_const;
25416 *total = cost->shift_var;
25421 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25423 /* ??? SSE scalar cost should be used here. */
25424 *total = cost->fmul;
25427 else if (X87_FLOAT_MODE_P (mode))
25429 *total = cost->fmul;
25432 else if (FLOAT_MODE_P (mode))
25434 /* ??? SSE vector cost should be used here. */
25435 *total = cost->fmul;
25440 rtx op0 = XEXP (x, 0);
25441 rtx op1 = XEXP (x, 1);
25443 if (CONST_INT_P (XEXP (x, 1)))
25445 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25446 for (nbits = 0; value != 0; value &= value - 1)
25450 /* This is arbitrary. */
25453 /* Compute costs correctly for widening multiplication. */
25454 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
25455 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
25456 == GET_MODE_SIZE (mode))
25458 int is_mulwiden = 0;
25459 enum machine_mode inner_mode = GET_MODE (op0);
25461 if (GET_CODE (op0) == GET_CODE (op1))
25462 is_mulwiden = 1, op1 = XEXP (op1, 0);
25463 else if (CONST_INT_P (op1))
25465 if (GET_CODE (op0) == SIGN_EXTEND)
25466 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
25469 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
25473 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
25476 *total = (cost->mult_init[MODE_INDEX (mode)]
25477 + nbits * cost->mult_bit
25478 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
25487 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25488 /* ??? SSE cost should be used here. */
25489 *total = cost->fdiv;
25490 else if (X87_FLOAT_MODE_P (mode))
25491 *total = cost->fdiv;
25492 else if (FLOAT_MODE_P (mode))
25493 /* ??? SSE vector cost should be used here. */
25494 *total = cost->fdiv;
25496 *total = cost->divide[MODE_INDEX (mode)];
25500 if (GET_MODE_CLASS (mode) == MODE_INT
25501 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
25503 if (GET_CODE (XEXP (x, 0)) == PLUS
25504 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
25505 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
25506 && CONSTANT_P (XEXP (x, 1)))
25508 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
25509 if (val == 2 || val == 4 || val == 8)
25511 *total = cost->lea;
25512 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25513 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
25514 outer_code, speed);
25515 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25519 else if (GET_CODE (XEXP (x, 0)) == MULT
25520 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
25522 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
25523 if (val == 2 || val == 4 || val == 8)
25525 *total = cost->lea;
25526 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25527 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25531 else if (GET_CODE (XEXP (x, 0)) == PLUS)
25533 *total = cost->lea;
25534 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25535 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25536 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25543 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25545 /* ??? SSE cost should be used here. */
25546 *total = cost->fadd;
25549 else if (X87_FLOAT_MODE_P (mode))
25551 *total = cost->fadd;
25554 else if (FLOAT_MODE_P (mode))
25556 /* ??? SSE vector cost should be used here. */
25557 *total = cost->fadd;
25565 if (!TARGET_64BIT && mode == DImode)
25567 *total = (cost->add * 2
25568 + (rtx_cost (XEXP (x, 0), outer_code, speed)
25569 << (GET_MODE (XEXP (x, 0)) != DImode))
25570 + (rtx_cost (XEXP (x, 1), outer_code, speed)
25571 << (GET_MODE (XEXP (x, 1)) != DImode)));
25577 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25579 /* ??? SSE cost should be used here. */
25580 *total = cost->fchs;
25583 else if (X87_FLOAT_MODE_P (mode))
25585 *total = cost->fchs;
25588 else if (FLOAT_MODE_P (mode))
25590 /* ??? SSE vector cost should be used here. */
25591 *total = cost->fchs;
25597 if (!TARGET_64BIT && mode == DImode)
25598 *total = cost->add * 2;
25600 *total = cost->add;
25604 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
25605 && XEXP (XEXP (x, 0), 1) == const1_rtx
25606 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
25607 && XEXP (x, 1) == const0_rtx)
25609 /* This kind of construct is implemented using test[bwl].
25610 Treat it as if we had an AND. */
25611 *total = (cost->add
25612 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
25613 + rtx_cost (const1_rtx, outer_code, speed));
25619 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
25624 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25625 /* ??? SSE cost should be used here. */
25626 *total = cost->fabs;
25627 else if (X87_FLOAT_MODE_P (mode))
25628 *total = cost->fabs;
25629 else if (FLOAT_MODE_P (mode))
25630 /* ??? SSE vector cost should be used here. */
25631 *total = cost->fabs;
25635 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25636 /* ??? SSE cost should be used here. */
25637 *total = cost->fsqrt;
25638 else if (X87_FLOAT_MODE_P (mode))
25639 *total = cost->fsqrt;
25640 else if (FLOAT_MODE_P (mode))
25641 /* ??? SSE vector cost should be used here. */
25642 *total = cost->fsqrt;
25646 if (XINT (x, 1) == UNSPEC_TP)
25657 static int current_machopic_label_num;
25659 /* Given a symbol name and its associated stub, write out the
25660 definition of the stub. */
25663 machopic_output_stub (FILE *file, const char *symb, const char *stub)
25665 unsigned int length;
25666 char *binder_name, *symbol_name, lazy_ptr_name[32];
25667 int label = ++current_machopic_label_num;
25669 /* For 64-bit we shouldn't get here. */
25670 gcc_assert (!TARGET_64BIT);
25672 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25673 symb = (*targetm.strip_name_encoding) (symb);
25675 length = strlen (stub);
25676 binder_name = XALLOCAVEC (char, length + 32);
25677 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
25679 length = strlen (symb);
25680 symbol_name = XALLOCAVEC (char, length + 32);
25681 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
25683 sprintf (lazy_ptr_name, "L%d$lz", label);
25686 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
25688 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
25690 fprintf (file, "%s:\n", stub);
25691 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25695 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
25696 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
25697 fprintf (file, "\tjmp\t*%%edx\n");
25700 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
25702 fprintf (file, "%s:\n", binder_name);
25706 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
25707 fprintf (file, "\tpushl\t%%eax\n");
25710 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
25712 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
25714 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
25715 fprintf (file, "%s:\n", lazy_ptr_name);
25716 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25717 fprintf (file, "\t.long %s\n", binder_name);
25721 darwin_x86_file_end (void)
25723 darwin_file_end ();
25726 #endif /* TARGET_MACHO */
25728 /* Order the registers for register allocator. */
25731 x86_order_regs_for_local_alloc (void)
25736 /* First allocate the local general purpose registers. */
25737 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
25738 if (GENERAL_REGNO_P (i) && call_used_regs[i])
25739 reg_alloc_order [pos++] = i;
25741 /* Global general purpose registers. */
25742 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
25743 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
25744 reg_alloc_order [pos++] = i;
25746 /* x87 registers come first in case we are doing FP math
25748 if (!TARGET_SSE_MATH)
25749 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
25750 reg_alloc_order [pos++] = i;
25752 /* SSE registers. */
25753 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
25754 reg_alloc_order [pos++] = i;
25755 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
25756 reg_alloc_order [pos++] = i;
25758 /* x87 registers. */
25759 if (TARGET_SSE_MATH)
25760 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
25761 reg_alloc_order [pos++] = i;
25763 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
25764 reg_alloc_order [pos++] = i;
25766 /* Initialize the rest of array as we do not allocate some registers
25768 while (pos < FIRST_PSEUDO_REGISTER)
25769 reg_alloc_order [pos++] = 0;
25772 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
25773 struct attribute_spec.handler. */
25775 ix86_handle_abi_attribute (tree *node, tree name,
25776 tree args ATTRIBUTE_UNUSED,
25777 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
25779 if (TREE_CODE (*node) != FUNCTION_TYPE
25780 && TREE_CODE (*node) != METHOD_TYPE
25781 && TREE_CODE (*node) != FIELD_DECL
25782 && TREE_CODE (*node) != TYPE_DECL)
25784 warning (OPT_Wattributes, "%qs attribute only applies to functions",
25785 IDENTIFIER_POINTER (name));
25786 *no_add_attrs = true;
25791 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
25792 IDENTIFIER_POINTER (name));
25793 *no_add_attrs = true;
25797 /* Can combine regparm with all attributes but fastcall. */
25798 if (is_attribute_p ("ms_abi", name))
25800 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
25802 error ("ms_abi and sysv_abi attributes are not compatible");
25807 else if (is_attribute_p ("sysv_abi", name))
25809 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
25811 error ("ms_abi and sysv_abi attributes are not compatible");
25820 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
25821 struct attribute_spec.handler. */
25823 ix86_handle_struct_attribute (tree *node, tree name,
25824 tree args ATTRIBUTE_UNUSED,
25825 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
25828 if (DECL_P (*node))
25830 if (TREE_CODE (*node) == TYPE_DECL)
25831 type = &TREE_TYPE (*node);
25836 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
25837 || TREE_CODE (*type) == UNION_TYPE)))
25839 warning (OPT_Wattributes, "%qs attribute ignored",
25840 IDENTIFIER_POINTER (name));
25841 *no_add_attrs = true;
25844 else if ((is_attribute_p ("ms_struct", name)
25845 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
25846 || ((is_attribute_p ("gcc_struct", name)
25847 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
25849 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
25850 IDENTIFIER_POINTER (name));
25851 *no_add_attrs = true;
25858 ix86_ms_bitfield_layout_p (const_tree record_type)
25860 return (TARGET_MS_BITFIELD_LAYOUT &&
25861 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
25862 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
25865 /* Returns an expression indicating where the this parameter is
25866 located on entry to the FUNCTION. */
25869 x86_this_parameter (tree function)
25871 tree type = TREE_TYPE (function);
25872 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
25877 const int *parm_regs;
25879 if (ix86_function_type_abi (type) == MS_ABI)
25880 parm_regs = x86_64_ms_abi_int_parameter_registers;
25882 parm_regs = x86_64_int_parameter_registers;
25883 return gen_rtx_REG (DImode, parm_regs[aggr]);
25886 nregs = ix86_function_regparm (type, function);
25888 if (nregs > 0 && !stdarg_p (type))
25892 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
25893 regno = aggr ? DX_REG : CX_REG;
25901 return gen_rtx_MEM (SImode,
25902 plus_constant (stack_pointer_rtx, 4));
25905 return gen_rtx_REG (SImode, regno);
25908 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
25911 /* Determine whether x86_output_mi_thunk can succeed. */
25914 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
25915 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
25916 HOST_WIDE_INT vcall_offset, const_tree function)
25918 /* 64-bit can handle anything. */
25922 /* For 32-bit, everything's fine if we have one free register. */
25923 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
25926 /* Need a free register for vcall_offset. */
25930 /* Need a free register for GOT references. */
25931 if (flag_pic && !(*targetm.binds_local_p) (function))
25934 /* Otherwise ok. */
25938 /* Output the assembler code for a thunk function. THUNK_DECL is the
25939 declaration for the thunk function itself, FUNCTION is the decl for
25940 the target function. DELTA is an immediate constant offset to be
25941 added to THIS. If VCALL_OFFSET is nonzero, the word at
25942 *(*this + vcall_offset) should be added to THIS. */
25945 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
25946 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
25947 HOST_WIDE_INT vcall_offset, tree function)
25950 rtx this_param = x86_this_parameter (function);
25953 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
25954 pull it in now and let DELTA benefit. */
25955 if (REG_P (this_param))
25956 this_reg = this_param;
25957 else if (vcall_offset)
25959 /* Put the this parameter into %eax. */
25960 xops[0] = this_param;
25961 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
25962 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
25965 this_reg = NULL_RTX;
25967 /* Adjust the this parameter by a fixed constant. */
25970 xops[0] = GEN_INT (delta);
25971 xops[1] = this_reg ? this_reg : this_param;
25974 if (!x86_64_general_operand (xops[0], DImode))
25976 tmp = gen_rtx_REG (DImode, R10_REG);
25978 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
25980 xops[1] = this_param;
25982 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
25985 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
25988 /* Adjust the this parameter by a value stored in the vtable. */
25992 tmp = gen_rtx_REG (DImode, R10_REG);
25995 int tmp_regno = CX_REG;
25996 if (lookup_attribute ("fastcall",
25997 TYPE_ATTRIBUTES (TREE_TYPE (function))))
25998 tmp_regno = AX_REG;
25999 tmp = gen_rtx_REG (SImode, tmp_regno);
26002 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26004 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26006 /* Adjust the this parameter. */
26007 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26008 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26010 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26011 xops[0] = GEN_INT (vcall_offset);
26013 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26014 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26016 xops[1] = this_reg;
26017 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26020 /* If necessary, drop THIS back to its stack slot. */
26021 if (this_reg && this_reg != this_param)
26023 xops[0] = this_reg;
26024 xops[1] = this_param;
26025 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26028 xops[0] = XEXP (DECL_RTL (function), 0);
26031 if (!flag_pic || (*targetm.binds_local_p) (function))
26032 output_asm_insn ("jmp\t%P0", xops);
26033 /* All thunks should be in the same object as their target,
26034 and thus binds_local_p should be true. */
26035 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26036 gcc_unreachable ();
26039 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26040 tmp = gen_rtx_CONST (Pmode, tmp);
26041 tmp = gen_rtx_MEM (QImode, tmp);
26043 output_asm_insn ("jmp\t%A0", xops);
26048 if (!flag_pic || (*targetm.binds_local_p) (function))
26049 output_asm_insn ("jmp\t%P0", xops);
26054 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26055 tmp = (gen_rtx_SYMBOL_REF
26057 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26058 tmp = gen_rtx_MEM (QImode, tmp);
26060 output_asm_insn ("jmp\t%0", xops);
26063 #endif /* TARGET_MACHO */
26065 tmp = gen_rtx_REG (SImode, CX_REG);
26066 output_set_got (tmp, NULL_RTX);
26069 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26070 output_asm_insn ("jmp\t{*}%1", xops);
26076 x86_file_start (void)
26078 default_file_start ();
26080 darwin_file_start ();
26082 if (X86_FILE_START_VERSION_DIRECTIVE)
26083 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26084 if (X86_FILE_START_FLTUSED)
26085 fputs ("\t.global\t__fltused\n", asm_out_file);
26086 if (ix86_asm_dialect == ASM_INTEL)
26087 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26091 x86_field_alignment (tree field, int computed)
26093 enum machine_mode mode;
26094 tree type = TREE_TYPE (field);
26096 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26098 mode = TYPE_MODE (strip_array_types (type));
26099 if (mode == DFmode || mode == DCmode
26100 || GET_MODE_CLASS (mode) == MODE_INT
26101 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26102 return MIN (32, computed);
26106 /* Output assembler code to FILE to increment profiler label # LABELNO
26107 for profiling a function entry. */
26109 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26113 #ifndef NO_PROFILE_COUNTERS
26114 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
26117 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26118 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26120 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26124 #ifndef NO_PROFILE_COUNTERS
26125 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26126 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26128 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26132 #ifndef NO_PROFILE_COUNTERS
26133 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26134 PROFILE_COUNT_REGISTER);
26136 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26140 /* We don't have exact information about the insn sizes, but we may assume
26141 quite safely that we are informed about all 1 byte insns and memory
26142 address sizes. This is enough to eliminate unnecessary padding in
26146 min_insn_size (rtx insn)
26150 if (!INSN_P (insn) || !active_insn_p (insn))
26153 /* Discard alignments we've emit and jump instructions. */
26154 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26155 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26158 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26159 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26162 /* Important case - calls are always 5 bytes.
26163 It is common to have many calls in the row. */
26165 && symbolic_reference_mentioned_p (PATTERN (insn))
26166 && !SIBLING_CALL_P (insn))
26168 if (get_attr_length (insn) <= 1)
26171 /* For normal instructions we may rely on the sizes of addresses
26172 and the presence of symbol to require 4 bytes of encoding.
26173 This is not the case for jumps where references are PC relative. */
26174 if (!JUMP_P (insn))
26176 l = get_attr_length_address (insn);
26177 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26186 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26190 ix86_avoid_jump_misspredicts (void)
26192 rtx insn, start = get_insns ();
26193 int nbytes = 0, njumps = 0;
26196 /* Look for all minimal intervals of instructions containing 4 jumps.
26197 The intervals are bounded by START and INSN. NBYTES is the total
26198 size of instructions in the interval including INSN and not including
26199 START. When the NBYTES is smaller than 16 bytes, it is possible
26200 that the end of START and INSN ends up in the same 16byte page.
26202 The smallest offset in the page INSN can start is the case where START
26203 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26204 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26206 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26209 nbytes += min_insn_size (insn);
26211 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26212 INSN_UID (insn), min_insn_size (insn));
26214 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26215 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26223 start = NEXT_INSN (start);
26224 if ((JUMP_P (start)
26225 && GET_CODE (PATTERN (start)) != ADDR_VEC
26226 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26228 njumps--, isjump = 1;
26231 nbytes -= min_insn_size (start);
26233 gcc_assert (njumps >= 0);
26235 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26236 INSN_UID (start), INSN_UID (insn), nbytes);
26238 if (njumps == 3 && isjump && nbytes < 16)
26240 int padsize = 15 - nbytes + min_insn_size (insn);
26243 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26244 INSN_UID (insn), padsize);
26245 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26250 /* AMD Athlon works faster
26251 when RET is not destination of conditional jump or directly preceded
26252 by other jump instruction. We avoid the penalty by inserting NOP just
26253 before the RET instructions in such cases. */
26255 ix86_pad_returns (void)
26260 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26262 basic_block bb = e->src;
26263 rtx ret = BB_END (bb);
26265 bool replace = false;
26267 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26268 || optimize_bb_for_size_p (bb))
26270 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26271 if (active_insn_p (prev) || LABEL_P (prev))
26273 if (prev && LABEL_P (prev))
26278 FOR_EACH_EDGE (e, ei, bb->preds)
26279 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26280 && !(e->flags & EDGE_FALLTHRU))
26285 prev = prev_active_insn (ret);
26287 && ((JUMP_P (prev) && any_condjump_p (prev))
26290 /* Empty functions get branch mispredict even when the jump destination
26291 is not visible to us. */
26292 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26297 emit_insn_before (gen_return_internal_long (), ret);
26303 /* Implement machine specific optimizations. We implement padding of returns
26304 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26308 if (TARGET_PAD_RETURNS && optimize
26309 && optimize_function_for_speed_p (cfun))
26310 ix86_pad_returns ();
26311 if (TARGET_FOUR_JUMP_LIMIT && optimize
26312 && optimize_function_for_speed_p (cfun))
26313 ix86_avoid_jump_misspredicts ();
26316 /* Return nonzero when QImode register that must be represented via REX prefix
26319 x86_extended_QIreg_mentioned_p (rtx insn)
26322 extract_insn_cached (insn);
26323 for (i = 0; i < recog_data.n_operands; i++)
26324 if (REG_P (recog_data.operand[i])
26325 && REGNO (recog_data.operand[i]) >= 4)
26330 /* Return nonzero when P points to register encoded via REX prefix.
26331 Called via for_each_rtx. */
26333 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26335 unsigned int regno;
26338 regno = REGNO (*p);
26339 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26342 /* Return true when INSN mentions register that must be encoded using REX
26345 x86_extended_reg_mentioned_p (rtx insn)
26347 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26348 extended_reg_mentioned_1, NULL);
26351 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26352 optabs would emit if we didn't have TFmode patterns. */
26355 x86_emit_floatuns (rtx operands[2])
26357 rtx neglab, donelab, i0, i1, f0, in, out;
26358 enum machine_mode mode, inmode;
26360 inmode = GET_MODE (operands[1]);
26361 gcc_assert (inmode == SImode || inmode == DImode);
26364 in = force_reg (inmode, operands[1]);
26365 mode = GET_MODE (out);
26366 neglab = gen_label_rtx ();
26367 donelab = gen_label_rtx ();
26368 f0 = gen_reg_rtx (mode);
26370 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26372 expand_float (out, in, 0);
26374 emit_jump_insn (gen_jump (donelab));
26377 emit_label (neglab);
26379 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26381 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26383 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26385 expand_float (f0, i0, 0);
26387 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26389 emit_label (donelab);
26392 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26393 with all elements equal to VAR. Return true if successful. */
26396 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26397 rtx target, rtx val)
26399 enum machine_mode hmode, smode, wsmode, wvmode;
26414 val = force_reg (GET_MODE_INNER (mode), val);
26415 x = gen_rtx_VEC_DUPLICATE (mode, val);
26416 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26422 if (TARGET_SSE || TARGET_3DNOW_A)
26424 val = gen_lowpart (SImode, val);
26425 x = gen_rtx_TRUNCATE (HImode, val);
26426 x = gen_rtx_VEC_DUPLICATE (mode, x);
26427 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26449 /* Extend HImode to SImode using a paradoxical SUBREG. */
26450 tmp1 = gen_reg_rtx (SImode);
26451 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26452 /* Insert the SImode value as low element of V4SImode vector. */
26453 tmp2 = gen_reg_rtx (V4SImode);
26454 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26455 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26456 CONST0_RTX (V4SImode),
26458 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26459 /* Cast the V4SImode vector back to a V8HImode vector. */
26460 tmp1 = gen_reg_rtx (V8HImode);
26461 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
26462 /* Duplicate the low short through the whole low SImode word. */
26463 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
26464 /* Cast the V8HImode vector back to a V4SImode vector. */
26465 tmp2 = gen_reg_rtx (V4SImode);
26466 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26467 /* Replicate the low element of the V4SImode vector. */
26468 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26469 /* Cast the V2SImode back to V8HImode, and store in target. */
26470 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
26481 /* Extend QImode to SImode using a paradoxical SUBREG. */
26482 tmp1 = gen_reg_rtx (SImode);
26483 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26484 /* Insert the SImode value as low element of V4SImode vector. */
26485 tmp2 = gen_reg_rtx (V4SImode);
26486 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26487 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26488 CONST0_RTX (V4SImode),
26490 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26491 /* Cast the V4SImode vector back to a V16QImode vector. */
26492 tmp1 = gen_reg_rtx (V16QImode);
26493 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
26494 /* Duplicate the low byte through the whole low SImode word. */
26495 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26496 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26497 /* Cast the V16QImode vector back to a V4SImode vector. */
26498 tmp2 = gen_reg_rtx (V4SImode);
26499 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26500 /* Replicate the low element of the V4SImode vector. */
26501 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26502 /* Cast the V2SImode back to V16QImode, and store in target. */
26503 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
26511 /* Replicate the value once into the next wider mode and recurse. */
26512 val = convert_modes (wsmode, smode, val, true);
26513 x = expand_simple_binop (wsmode, ASHIFT, val,
26514 GEN_INT (GET_MODE_BITSIZE (smode)),
26515 NULL_RTX, 1, OPTAB_LIB_WIDEN);
26516 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
26518 x = gen_reg_rtx (wvmode);
26519 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
26520 gcc_unreachable ();
26521 emit_move_insn (target, gen_lowpart (mode, x));
26544 rtx tmp = gen_reg_rtx (hmode);
26545 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
26546 emit_insn (gen_rtx_SET (VOIDmode, target,
26547 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
26556 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26557 whose ONE_VAR element is VAR, and other elements are zero. Return true
26561 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
26562 rtx target, rtx var, int one_var)
26564 enum machine_mode vsimode;
26567 bool use_vector_set = false;
26572 /* For SSE4.1, we normally use vector set. But if the second
26573 element is zero and inter-unit moves are OK, we use movq
26575 use_vector_set = (TARGET_64BIT
26577 && !(TARGET_INTER_UNIT_MOVES
26583 use_vector_set = TARGET_SSE4_1;
26586 use_vector_set = TARGET_SSE2;
26589 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
26597 use_vector_set = TARGET_AVX;
26603 if (use_vector_set)
26605 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
26606 var = force_reg (GET_MODE_INNER (mode), var);
26607 ix86_expand_vector_set (mmx_ok, target, var, one_var);
26623 var = force_reg (GET_MODE_INNER (mode), var);
26624 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
26625 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26630 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
26631 new_target = gen_reg_rtx (mode);
26633 new_target = target;
26634 var = force_reg (GET_MODE_INNER (mode), var);
26635 x = gen_rtx_VEC_DUPLICATE (mode, var);
26636 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
26637 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
26640 /* We need to shuffle the value to the correct position, so
26641 create a new pseudo to store the intermediate result. */
26643 /* With SSE2, we can use the integer shuffle insns. */
26644 if (mode != V4SFmode && TARGET_SSE2)
26646 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
26648 GEN_INT (one_var == 1 ? 0 : 1),
26649 GEN_INT (one_var == 2 ? 0 : 1),
26650 GEN_INT (one_var == 3 ? 0 : 1)));
26651 if (target != new_target)
26652 emit_move_insn (target, new_target);
26656 /* Otherwise convert the intermediate result to V4SFmode and
26657 use the SSE1 shuffle instructions. */
26658 if (mode != V4SFmode)
26660 tmp = gen_reg_rtx (V4SFmode);
26661 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
26666 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
26668 GEN_INT (one_var == 1 ? 0 : 1),
26669 GEN_INT (one_var == 2 ? 0+4 : 1+4),
26670 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
26672 if (mode != V4SFmode)
26673 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
26674 else if (tmp != target)
26675 emit_move_insn (target, tmp);
26677 else if (target != new_target)
26678 emit_move_insn (target, new_target);
26683 vsimode = V4SImode;
26689 vsimode = V2SImode;
26695 /* Zero extend the variable element to SImode and recurse. */
26696 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
26698 x = gen_reg_rtx (vsimode);
26699 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
26701 gcc_unreachable ();
26703 emit_move_insn (target, gen_lowpart (mode, x));
26711 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26712 consisting of the values in VALS. It is known that all elements
26713 except ONE_VAR are constants. Return true if successful. */
26716 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
26717 rtx target, rtx vals, int one_var)
26719 rtx var = XVECEXP (vals, 0, one_var);
26720 enum machine_mode wmode;
26723 const_vec = copy_rtx (vals);
26724 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
26725 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
26733 /* For the two element vectors, it's just as easy to use
26734 the general case. */
26758 /* There's no way to set one QImode entry easily. Combine
26759 the variable value with its adjacent constant value, and
26760 promote to an HImode set. */
26761 x = XVECEXP (vals, 0, one_var ^ 1);
26764 var = convert_modes (HImode, QImode, var, true);
26765 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
26766 NULL_RTX, 1, OPTAB_LIB_WIDEN);
26767 x = GEN_INT (INTVAL (x) & 0xff);
26771 var = convert_modes (HImode, QImode, var, true);
26772 x = gen_int_mode (INTVAL (x) << 8, HImode);
26774 if (x != const0_rtx)
26775 var = expand_simple_binop (HImode, IOR, var, x, var,
26776 1, OPTAB_LIB_WIDEN);
26778 x = gen_reg_rtx (wmode);
26779 emit_move_insn (x, gen_lowpart (wmode, const_vec));
26780 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
26782 emit_move_insn (target, gen_lowpart (mode, x));
26789 emit_move_insn (target, const_vec);
26790 ix86_expand_vector_set (mmx_ok, target, var, one_var);
26794 /* A subroutine of ix86_expand_vector_init_general. Use vector
26795 concatenate to handle the most general case: all values variable,
26796 and none identical. */
26799 ix86_expand_vector_init_concat (enum machine_mode mode,
26800 rtx target, rtx *ops, int n)
26802 enum machine_mode cmode, hmode = VOIDmode;
26803 rtx first[8], second[4];
26843 gcc_unreachable ();
26846 if (!register_operand (ops[1], cmode))
26847 ops[1] = force_reg (cmode, ops[1]);
26848 if (!register_operand (ops[0], cmode))
26849 ops[0] = force_reg (cmode, ops[0]);
26850 emit_insn (gen_rtx_SET (VOIDmode, target,
26851 gen_rtx_VEC_CONCAT (mode, ops[0],
26871 gcc_unreachable ();
26887 gcc_unreachable ();
26892 /* FIXME: We process inputs backward to help RA. PR 36222. */
26895 for (; i > 0; i -= 2, j--)
26897 first[j] = gen_reg_rtx (cmode);
26898 v = gen_rtvec (2, ops[i - 1], ops[i]);
26899 ix86_expand_vector_init (false, first[j],
26900 gen_rtx_PARALLEL (cmode, v));
26906 gcc_assert (hmode != VOIDmode);
26907 for (i = j = 0; i < n; i += 2, j++)
26909 second[j] = gen_reg_rtx (hmode);
26910 ix86_expand_vector_init_concat (hmode, second [j],
26914 ix86_expand_vector_init_concat (mode, target, second, n);
26917 ix86_expand_vector_init_concat (mode, target, first, n);
26921 gcc_unreachable ();
26925 /* A subroutine of ix86_expand_vector_init_general. Use vector
26926 interleave to handle the most general case: all values variable,
26927 and none identical. */
26930 ix86_expand_vector_init_interleave (enum machine_mode mode,
26931 rtx target, rtx *ops, int n)
26933 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
26936 rtx (*gen_load_even) (rtx, rtx, rtx);
26937 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
26938 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
26943 gen_load_even = gen_vec_setv8hi;
26944 gen_interleave_first_low = gen_vec_interleave_lowv4si;
26945 gen_interleave_second_low = gen_vec_interleave_lowv2di;
26946 inner_mode = HImode;
26947 first_imode = V4SImode;
26948 second_imode = V2DImode;
26949 third_imode = VOIDmode;
26952 gen_load_even = gen_vec_setv16qi;
26953 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
26954 gen_interleave_second_low = gen_vec_interleave_lowv4si;
26955 inner_mode = QImode;
26956 first_imode = V8HImode;
26957 second_imode = V4SImode;
26958 third_imode = V2DImode;
26961 gcc_unreachable ();
26964 for (i = 0; i < n; i++)
26966 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
26967 op0 = gen_reg_rtx (SImode);
26968 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
26970 /* Insert the SImode value as low element of V4SImode vector. */
26971 op1 = gen_reg_rtx (V4SImode);
26972 op0 = gen_rtx_VEC_MERGE (V4SImode,
26973 gen_rtx_VEC_DUPLICATE (V4SImode,
26975 CONST0_RTX (V4SImode),
26977 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
26979 /* Cast the V4SImode vector back to a vector in orignal mode. */
26980 op0 = gen_reg_rtx (mode);
26981 emit_move_insn (op0, gen_lowpart (mode, op1));
26983 /* Load even elements into the second positon. */
26984 emit_insn ((*gen_load_even) (op0,
26985 force_reg (inner_mode,
26989 /* Cast vector to FIRST_IMODE vector. */
26990 ops[i] = gen_reg_rtx (first_imode);
26991 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
26994 /* Interleave low FIRST_IMODE vectors. */
26995 for (i = j = 0; i < n; i += 2, j++)
26997 op0 = gen_reg_rtx (first_imode);
26998 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27000 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27001 ops[j] = gen_reg_rtx (second_imode);
27002 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27005 /* Interleave low SECOND_IMODE vectors. */
27006 switch (second_imode)
27009 for (i = j = 0; i < n / 2; i += 2, j++)
27011 op0 = gen_reg_rtx (second_imode);
27012 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27015 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27017 ops[j] = gen_reg_rtx (third_imode);
27018 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27020 second_imode = V2DImode;
27021 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27025 op0 = gen_reg_rtx (second_imode);
27026 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27029 /* Cast the SECOND_IMODE vector back to a vector on original
27031 emit_insn (gen_rtx_SET (VOIDmode, target,
27032 gen_lowpart (mode, op0)));
27036 gcc_unreachable ();
27040 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27041 all values variable, and none identical. */
27044 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27045 rtx target, rtx vals)
27047 rtx ops[32], op0, op1;
27048 enum machine_mode half_mode = VOIDmode;
27055 if (!mmx_ok && !TARGET_SSE)
27067 n = GET_MODE_NUNITS (mode);
27068 for (i = 0; i < n; i++)
27069 ops[i] = XVECEXP (vals, 0, i);
27070 ix86_expand_vector_init_concat (mode, target, ops, n);
27074 half_mode = V16QImode;
27078 half_mode = V8HImode;
27082 n = GET_MODE_NUNITS (mode);
27083 for (i = 0; i < n; i++)
27084 ops[i] = XVECEXP (vals, 0, i);
27085 op0 = gen_reg_rtx (half_mode);
27086 op1 = gen_reg_rtx (half_mode);
27087 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27089 ix86_expand_vector_init_interleave (half_mode, op1,
27090 &ops [n >> 1], n >> 2);
27091 emit_insn (gen_rtx_SET (VOIDmode, target,
27092 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27096 if (!TARGET_SSE4_1)
27104 /* Don't use ix86_expand_vector_init_interleave if we can't
27105 move from GPR to SSE register directly. */
27106 if (!TARGET_INTER_UNIT_MOVES)
27109 n = GET_MODE_NUNITS (mode);
27110 for (i = 0; i < n; i++)
27111 ops[i] = XVECEXP (vals, 0, i);
27112 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27120 gcc_unreachable ();
27124 int i, j, n_elts, n_words, n_elt_per_word;
27125 enum machine_mode inner_mode;
27126 rtx words[4], shift;
27128 inner_mode = GET_MODE_INNER (mode);
27129 n_elts = GET_MODE_NUNITS (mode);
27130 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27131 n_elt_per_word = n_elts / n_words;
27132 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27134 for (i = 0; i < n_words; ++i)
27136 rtx word = NULL_RTX;
27138 for (j = 0; j < n_elt_per_word; ++j)
27140 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27141 elt = convert_modes (word_mode, inner_mode, elt, true);
27147 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27148 word, 1, OPTAB_LIB_WIDEN);
27149 word = expand_simple_binop (word_mode, IOR, word, elt,
27150 word, 1, OPTAB_LIB_WIDEN);
27158 emit_move_insn (target, gen_lowpart (mode, words[0]));
27159 else if (n_words == 2)
27161 rtx tmp = gen_reg_rtx (mode);
27162 emit_clobber (tmp);
27163 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27164 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27165 emit_move_insn (target, tmp);
27167 else if (n_words == 4)
27169 rtx tmp = gen_reg_rtx (V4SImode);
27170 gcc_assert (word_mode == SImode);
27171 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27172 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27173 emit_move_insn (target, gen_lowpart (mode, tmp));
27176 gcc_unreachable ();
27180 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27181 instructions unless MMX_OK is true. */
27184 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27186 enum machine_mode mode = GET_MODE (target);
27187 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27188 int n_elts = GET_MODE_NUNITS (mode);
27189 int n_var = 0, one_var = -1;
27190 bool all_same = true, all_const_zero = true;
27194 for (i = 0; i < n_elts; ++i)
27196 x = XVECEXP (vals, 0, i);
27197 if (!(CONST_INT_P (x)
27198 || GET_CODE (x) == CONST_DOUBLE
27199 || GET_CODE (x) == CONST_FIXED))
27200 n_var++, one_var = i;
27201 else if (x != CONST0_RTX (inner_mode))
27202 all_const_zero = false;
27203 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27207 /* Constants are best loaded from the constant pool. */
27210 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27214 /* If all values are identical, broadcast the value. */
27216 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27217 XVECEXP (vals, 0, 0)))
27220 /* Values where only one field is non-constant are best loaded from
27221 the pool and overwritten via move later. */
27225 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27226 XVECEXP (vals, 0, one_var),
27230 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27234 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27238 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27240 enum machine_mode mode = GET_MODE (target);
27241 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27242 enum machine_mode half_mode;
27243 bool use_vec_merge = false;
27245 static rtx (*gen_extract[6][2]) (rtx, rtx)
27247 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27248 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27249 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27250 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27251 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27252 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27254 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27256 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27257 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27258 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27259 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27260 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27261 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27271 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27272 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27274 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27276 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27277 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27283 use_vec_merge = TARGET_SSE4_1;
27291 /* For the two element vectors, we implement a VEC_CONCAT with
27292 the extraction of the other element. */
27294 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27295 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27298 op0 = val, op1 = tmp;
27300 op0 = tmp, op1 = val;
27302 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27303 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27308 use_vec_merge = TARGET_SSE4_1;
27315 use_vec_merge = true;
27319 /* tmp = target = A B C D */
27320 tmp = copy_to_reg (target);
27321 /* target = A A B B */
27322 emit_insn (gen_sse_unpcklps (target, target, target));
27323 /* target = X A B B */
27324 ix86_expand_vector_set (false, target, val, 0);
27325 /* target = A X C D */
27326 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27327 GEN_INT (1), GEN_INT (0),
27328 GEN_INT (2+4), GEN_INT (3+4)));
27332 /* tmp = target = A B C D */
27333 tmp = copy_to_reg (target);
27334 /* tmp = X B C D */
27335 ix86_expand_vector_set (false, tmp, val, 0);
27336 /* target = A B X D */
27337 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27338 GEN_INT (0), GEN_INT (1),
27339 GEN_INT (0+4), GEN_INT (3+4)));
27343 /* tmp = target = A B C D */
27344 tmp = copy_to_reg (target);
27345 /* tmp = X B C D */
27346 ix86_expand_vector_set (false, tmp, val, 0);
27347 /* target = A B X D */
27348 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27349 GEN_INT (0), GEN_INT (1),
27350 GEN_INT (2+4), GEN_INT (0+4)));
27354 gcc_unreachable ();
27359 use_vec_merge = TARGET_SSE4_1;
27363 /* Element 0 handled by vec_merge below. */
27366 use_vec_merge = true;
27372 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27373 store into element 0, then shuffle them back. */
27377 order[0] = GEN_INT (elt);
27378 order[1] = const1_rtx;
27379 order[2] = const2_rtx;
27380 order[3] = GEN_INT (3);
27381 order[elt] = const0_rtx;
27383 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27384 order[1], order[2], order[3]));
27386 ix86_expand_vector_set (false, target, val, 0);
27388 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27389 order[1], order[2], order[3]));
27393 /* For SSE1, we have to reuse the V4SF code. */
27394 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27395 gen_lowpart (SFmode, val), elt);
27400 use_vec_merge = TARGET_SSE2;
27403 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27407 use_vec_merge = TARGET_SSE4_1;
27414 half_mode = V16QImode;
27420 half_mode = V8HImode;
27426 half_mode = V4SImode;
27432 half_mode = V2DImode;
27438 half_mode = V4SFmode;
27444 half_mode = V2DFmode;
27450 /* Compute offset. */
27454 gcc_assert (i <= 1);
27456 /* Extract the half. */
27457 tmp = gen_reg_rtx (half_mode);
27458 emit_insn ((*gen_extract[j][i]) (tmp, target));
27460 /* Put val in tmp at elt. */
27461 ix86_expand_vector_set (false, tmp, val, elt);
27464 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
27473 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
27474 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
27475 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27479 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27481 emit_move_insn (mem, target);
27483 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27484 emit_move_insn (tmp, val);
27486 emit_move_insn (target, mem);
27491 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
27493 enum machine_mode mode = GET_MODE (vec);
27494 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27495 bool use_vec_extr = false;
27508 use_vec_extr = true;
27512 use_vec_extr = TARGET_SSE4_1;
27524 tmp = gen_reg_rtx (mode);
27525 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
27526 GEN_INT (elt), GEN_INT (elt),
27527 GEN_INT (elt+4), GEN_INT (elt+4)));
27531 tmp = gen_reg_rtx (mode);
27532 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
27536 gcc_unreachable ();
27539 use_vec_extr = true;
27544 use_vec_extr = TARGET_SSE4_1;
27558 tmp = gen_reg_rtx (mode);
27559 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
27560 GEN_INT (elt), GEN_INT (elt),
27561 GEN_INT (elt), GEN_INT (elt)));
27565 tmp = gen_reg_rtx (mode);
27566 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
27570 gcc_unreachable ();
27573 use_vec_extr = true;
27578 /* For SSE1, we have to reuse the V4SF code. */
27579 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
27580 gen_lowpart (V4SFmode, vec), elt);
27586 use_vec_extr = TARGET_SSE2;
27589 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27593 use_vec_extr = TARGET_SSE4_1;
27597 /* ??? Could extract the appropriate HImode element and shift. */
27604 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
27605 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
27607 /* Let the rtl optimizers know about the zero extension performed. */
27608 if (inner_mode == QImode || inner_mode == HImode)
27610 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
27611 target = gen_lowpart (SImode, target);
27614 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27618 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27620 emit_move_insn (mem, vec);
27622 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27623 emit_move_insn (target, tmp);
27627 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
27628 pattern to reduce; DEST is the destination; IN is the input vector. */
27631 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
27633 rtx tmp1, tmp2, tmp3;
27635 tmp1 = gen_reg_rtx (V4SFmode);
27636 tmp2 = gen_reg_rtx (V4SFmode);
27637 tmp3 = gen_reg_rtx (V4SFmode);
27639 emit_insn (gen_sse_movhlps (tmp1, in, in));
27640 emit_insn (fn (tmp2, tmp1, in));
27642 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
27643 GEN_INT (1), GEN_INT (1),
27644 GEN_INT (1+4), GEN_INT (1+4)));
27645 emit_insn (fn (dest, tmp2, tmp3));
27648 /* Target hook for scalar_mode_supported_p. */
27650 ix86_scalar_mode_supported_p (enum machine_mode mode)
27652 if (DECIMAL_FLOAT_MODE_P (mode))
27654 else if (mode == TFmode)
27657 return default_scalar_mode_supported_p (mode);
27660 /* Implements target hook vector_mode_supported_p. */
27662 ix86_vector_mode_supported_p (enum machine_mode mode)
27664 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
27666 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
27668 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
27670 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
27672 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
27677 /* Target hook for c_mode_for_suffix. */
27678 static enum machine_mode
27679 ix86_c_mode_for_suffix (char suffix)
27689 /* Worker function for TARGET_MD_ASM_CLOBBERS.
27691 We do this in the new i386 backend to maintain source compatibility
27692 with the old cc0-based compiler. */
27695 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
27696 tree inputs ATTRIBUTE_UNUSED,
27699 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
27701 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
27706 /* Implements target vector targetm.asm.encode_section_info. This
27707 is not used by netware. */
27709 static void ATTRIBUTE_UNUSED
27710 ix86_encode_section_info (tree decl, rtx rtl, int first)
27712 default_encode_section_info (decl, rtl, first);
27714 if (TREE_CODE (decl) == VAR_DECL
27715 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
27716 && ix86_in_large_data_p (decl))
27717 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
27720 /* Worker function for REVERSE_CONDITION. */
27723 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
27725 return (mode != CCFPmode && mode != CCFPUmode
27726 ? reverse_condition (code)
27727 : reverse_condition_maybe_unordered (code));
27730 /* Output code to perform an x87 FP register move, from OPERANDS[1]
27734 output_387_reg_move (rtx insn, rtx *operands)
27736 if (REG_P (operands[0]))
27738 if (REG_P (operands[1])
27739 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
27741 if (REGNO (operands[0]) == FIRST_STACK_REG)
27742 return output_387_ffreep (operands, 0);
27743 return "fstp\t%y0";
27745 if (STACK_TOP_P (operands[0]))
27746 return "fld%z1\t%y1";
27749 else if (MEM_P (operands[0]))
27751 gcc_assert (REG_P (operands[1]));
27752 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
27753 return "fstp%z0\t%y0";
27756 /* There is no non-popping store to memory for XFmode.
27757 So if we need one, follow the store with a load. */
27758 if (GET_MODE (operands[0]) == XFmode)
27759 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
27761 return "fst%z0\t%y0";
27768 /* Output code to perform a conditional jump to LABEL, if C2 flag in
27769 FP status register is set. */
27772 ix86_emit_fp_unordered_jump (rtx label)
27774 rtx reg = gen_reg_rtx (HImode);
27777 emit_insn (gen_x86_fnstsw_1 (reg));
27779 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
27781 emit_insn (gen_x86_sahf_1 (reg));
27783 temp = gen_rtx_REG (CCmode, FLAGS_REG);
27784 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
27788 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
27790 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
27791 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
27794 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
27795 gen_rtx_LABEL_REF (VOIDmode, label),
27797 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
27799 emit_jump_insn (temp);
27800 predict_jump (REG_BR_PROB_BASE * 10 / 100);
27803 /* Output code to perform a log1p XFmode calculation. */
27805 void ix86_emit_i387_log1p (rtx op0, rtx op1)
27807 rtx label1 = gen_label_rtx ();
27808 rtx label2 = gen_label_rtx ();
27810 rtx tmp = gen_reg_rtx (XFmode);
27811 rtx tmp2 = gen_reg_rtx (XFmode);
27813 emit_insn (gen_absxf2 (tmp, op1));
27814 emit_insn (gen_cmpxf (tmp,
27815 CONST_DOUBLE_FROM_REAL_VALUE (
27816 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
27818 emit_jump_insn (gen_bge (label1));
27820 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
27821 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
27822 emit_jump (label2);
27824 emit_label (label1);
27825 emit_move_insn (tmp, CONST1_RTX (XFmode));
27826 emit_insn (gen_addxf3 (tmp, op1, tmp));
27827 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
27828 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
27830 emit_label (label2);
27833 /* Output code to perform a Newton-Rhapson approximation of a single precision
27834 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
27836 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
27838 rtx x0, x1, e0, e1, two;
27840 x0 = gen_reg_rtx (mode);
27841 e0 = gen_reg_rtx (mode);
27842 e1 = gen_reg_rtx (mode);
27843 x1 = gen_reg_rtx (mode);
27845 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
27847 if (VECTOR_MODE_P (mode))
27848 two = ix86_build_const_vector (SFmode, true, two);
27850 two = force_reg (mode, two);
27852 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
27854 /* x0 = rcp(b) estimate */
27855 emit_insn (gen_rtx_SET (VOIDmode, x0,
27856 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
27859 emit_insn (gen_rtx_SET (VOIDmode, e0,
27860 gen_rtx_MULT (mode, x0, b)));
27862 emit_insn (gen_rtx_SET (VOIDmode, e1,
27863 gen_rtx_MINUS (mode, two, e0)));
27865 emit_insn (gen_rtx_SET (VOIDmode, x1,
27866 gen_rtx_MULT (mode, x0, e1)));
27868 emit_insn (gen_rtx_SET (VOIDmode, res,
27869 gen_rtx_MULT (mode, a, x1)));
27872 /* Output code to perform a Newton-Rhapson approximation of a
27873 single precision floating point [reciprocal] square root. */
27875 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
27878 rtx x0, e0, e1, e2, e3, mthree, mhalf;
27881 x0 = gen_reg_rtx (mode);
27882 e0 = gen_reg_rtx (mode);
27883 e1 = gen_reg_rtx (mode);
27884 e2 = gen_reg_rtx (mode);
27885 e3 = gen_reg_rtx (mode);
27887 real_from_integer (&r, VOIDmode, -3, -1, 0);
27888 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
27890 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
27891 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
27893 if (VECTOR_MODE_P (mode))
27895 mthree = ix86_build_const_vector (SFmode, true, mthree);
27896 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
27899 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
27900 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
27902 /* x0 = rsqrt(a) estimate */
27903 emit_insn (gen_rtx_SET (VOIDmode, x0,
27904 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
27907 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
27912 zero = gen_reg_rtx (mode);
27913 mask = gen_reg_rtx (mode);
27915 zero = force_reg (mode, CONST0_RTX(mode));
27916 emit_insn (gen_rtx_SET (VOIDmode, mask,
27917 gen_rtx_NE (mode, zero, a)));
27919 emit_insn (gen_rtx_SET (VOIDmode, x0,
27920 gen_rtx_AND (mode, x0, mask)));
27924 emit_insn (gen_rtx_SET (VOIDmode, e0,
27925 gen_rtx_MULT (mode, x0, a)));
27927 emit_insn (gen_rtx_SET (VOIDmode, e1,
27928 gen_rtx_MULT (mode, e0, x0)));
27931 mthree = force_reg (mode, mthree);
27932 emit_insn (gen_rtx_SET (VOIDmode, e2,
27933 gen_rtx_PLUS (mode, e1, mthree)));
27935 mhalf = force_reg (mode, mhalf);
27937 /* e3 = -.5 * x0 */
27938 emit_insn (gen_rtx_SET (VOIDmode, e3,
27939 gen_rtx_MULT (mode, x0, mhalf)));
27941 /* e3 = -.5 * e0 */
27942 emit_insn (gen_rtx_SET (VOIDmode, e3,
27943 gen_rtx_MULT (mode, e0, mhalf)));
27944 /* ret = e2 * e3 */
27945 emit_insn (gen_rtx_SET (VOIDmode, res,
27946 gen_rtx_MULT (mode, e2, e3)));
27949 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
27951 static void ATTRIBUTE_UNUSED
27952 i386_solaris_elf_named_section (const char *name, unsigned int flags,
27955 /* With Binutils 2.15, the "@unwind" marker must be specified on
27956 every occurrence of the ".eh_frame" section, not just the first
27959 && strcmp (name, ".eh_frame") == 0)
27961 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
27962 flags & SECTION_WRITE ? "aw" : "a");
27965 default_elf_asm_named_section (name, flags, decl);
27968 /* Return the mangling of TYPE if it is an extended fundamental type. */
27970 static const char *
27971 ix86_mangle_type (const_tree type)
27973 type = TYPE_MAIN_VARIANT (type);
27975 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
27976 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
27979 switch (TYPE_MODE (type))
27982 /* __float128 is "g". */
27985 /* "long double" or __float80 is "e". */
27992 /* For 32-bit code we can save PIC register setup by using
27993 __stack_chk_fail_local hidden function instead of calling
27994 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
27995 register, so it is better to call __stack_chk_fail directly. */
27998 ix86_stack_protect_fail (void)
28000 return TARGET_64BIT
28001 ? default_external_stack_protect_fail ()
28002 : default_hidden_stack_protect_fail ();
28005 /* Select a format to encode pointers in exception handling data. CODE
28006 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28007 true if the symbol may be affected by dynamic relocations.
28009 ??? All x86 object file formats are capable of representing this.
28010 After all, the relocation needed is the same as for the call insn.
28011 Whether or not a particular assembler allows us to enter such, I
28012 guess we'll have to see. */
28014 asm_preferred_eh_data_format (int code, int global)
28018 int type = DW_EH_PE_sdata8;
28020 || ix86_cmodel == CM_SMALL_PIC
28021 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28022 type = DW_EH_PE_sdata4;
28023 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28025 if (ix86_cmodel == CM_SMALL
28026 || (ix86_cmodel == CM_MEDIUM && code))
28027 return DW_EH_PE_udata4;
28028 return DW_EH_PE_absptr;
28031 /* Expand copysign from SIGN to the positive value ABS_VALUE
28032 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28035 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28037 enum machine_mode mode = GET_MODE (sign);
28038 rtx sgn = gen_reg_rtx (mode);
28039 if (mask == NULL_RTX)
28041 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28042 if (!VECTOR_MODE_P (mode))
28044 /* We need to generate a scalar mode mask in this case. */
28045 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28046 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28047 mask = gen_reg_rtx (mode);
28048 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28052 mask = gen_rtx_NOT (mode, mask);
28053 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28054 gen_rtx_AND (mode, mask, sign)));
28055 emit_insn (gen_rtx_SET (VOIDmode, result,
28056 gen_rtx_IOR (mode, abs_value, sgn)));
28059 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28060 mask for masking out the sign-bit is stored in *SMASK, if that is
28063 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28065 enum machine_mode mode = GET_MODE (op0);
28068 xa = gen_reg_rtx (mode);
28069 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28070 if (!VECTOR_MODE_P (mode))
28072 /* We need to generate a scalar mode mask in this case. */
28073 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28074 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28075 mask = gen_reg_rtx (mode);
28076 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28078 emit_insn (gen_rtx_SET (VOIDmode, xa,
28079 gen_rtx_AND (mode, op0, mask)));
28087 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28088 swapping the operands if SWAP_OPERANDS is true. The expanded
28089 code is a forward jump to a newly created label in case the
28090 comparison is true. The generated label rtx is returned. */
28092 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28093 bool swap_operands)
28104 label = gen_label_rtx ();
28105 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28106 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28107 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28108 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28109 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28110 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28111 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28112 JUMP_LABEL (tmp) = label;
28117 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28118 using comparison code CODE. Operands are swapped for the comparison if
28119 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28121 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28122 bool swap_operands)
28124 enum machine_mode mode = GET_MODE (op0);
28125 rtx mask = gen_reg_rtx (mode);
28134 if (mode == DFmode)
28135 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28136 gen_rtx_fmt_ee (code, mode, op0, op1)));
28138 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28139 gen_rtx_fmt_ee (code, mode, op0, op1)));
28144 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28145 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28147 ix86_gen_TWO52 (enum machine_mode mode)
28149 REAL_VALUE_TYPE TWO52r;
28152 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28153 TWO52 = const_double_from_real_value (TWO52r, mode);
28154 TWO52 = force_reg (mode, TWO52);
28159 /* Expand SSE sequence for computing lround from OP1 storing
28162 ix86_expand_lround (rtx op0, rtx op1)
28164 /* C code for the stuff we're doing below:
28165 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28168 enum machine_mode mode = GET_MODE (op1);
28169 const struct real_format *fmt;
28170 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28173 /* load nextafter (0.5, 0.0) */
28174 fmt = REAL_MODE_FORMAT (mode);
28175 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28176 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28178 /* adj = copysign (0.5, op1) */
28179 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28180 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28182 /* adj = op1 + adj */
28183 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28185 /* op0 = (imode)adj */
28186 expand_fix (op0, adj, 0);
28189 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28192 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28194 /* C code for the stuff we're doing below (for do_floor):
28196 xi -= (double)xi > op1 ? 1 : 0;
28199 enum machine_mode fmode = GET_MODE (op1);
28200 enum machine_mode imode = GET_MODE (op0);
28201 rtx ireg, freg, label, tmp;
28203 /* reg = (long)op1 */
28204 ireg = gen_reg_rtx (imode);
28205 expand_fix (ireg, op1, 0);
28207 /* freg = (double)reg */
28208 freg = gen_reg_rtx (fmode);
28209 expand_float (freg, ireg, 0);
28211 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28212 label = ix86_expand_sse_compare_and_jump (UNLE,
28213 freg, op1, !do_floor);
28214 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28215 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28216 emit_move_insn (ireg, tmp);
28218 emit_label (label);
28219 LABEL_NUSES (label) = 1;
28221 emit_move_insn (op0, ireg);
28224 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28225 result in OPERAND0. */
28227 ix86_expand_rint (rtx operand0, rtx operand1)
28229 /* C code for the stuff we're doing below:
28230 xa = fabs (operand1);
28231 if (!isless (xa, 2**52))
28233 xa = xa + 2**52 - 2**52;
28234 return copysign (xa, operand1);
28236 enum machine_mode mode = GET_MODE (operand0);
28237 rtx res, xa, label, TWO52, mask;
28239 res = gen_reg_rtx (mode);
28240 emit_move_insn (res, operand1);
28242 /* xa = abs (operand1) */
28243 xa = ix86_expand_sse_fabs (res, &mask);
28245 /* if (!isless (xa, TWO52)) goto label; */
28246 TWO52 = ix86_gen_TWO52 (mode);
28247 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28249 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28250 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28252 ix86_sse_copysign_to_positive (res, xa, res, mask);
28254 emit_label (label);
28255 LABEL_NUSES (label) = 1;
28257 emit_move_insn (operand0, res);
28260 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28263 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28265 /* C code for the stuff we expand below.
28266 double xa = fabs (x), x2;
28267 if (!isless (xa, TWO52))
28269 xa = xa + TWO52 - TWO52;
28270 x2 = copysign (xa, x);
28279 enum machine_mode mode = GET_MODE (operand0);
28280 rtx xa, TWO52, tmp, label, one, res, mask;
28282 TWO52 = ix86_gen_TWO52 (mode);
28284 /* Temporary for holding the result, initialized to the input
28285 operand to ease control flow. */
28286 res = gen_reg_rtx (mode);
28287 emit_move_insn (res, operand1);
28289 /* xa = abs (operand1) */
28290 xa = ix86_expand_sse_fabs (res, &mask);
28292 /* if (!isless (xa, TWO52)) goto label; */
28293 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28295 /* xa = xa + TWO52 - TWO52; */
28296 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28297 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28299 /* xa = copysign (xa, operand1) */
28300 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28302 /* generate 1.0 or -1.0 */
28303 one = force_reg (mode,
28304 const_double_from_real_value (do_floor
28305 ? dconst1 : dconstm1, mode));
28307 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28308 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28309 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28310 gen_rtx_AND (mode, one, tmp)));
28311 /* We always need to subtract here to preserve signed zero. */
28312 tmp = expand_simple_binop (mode, MINUS,
28313 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28314 emit_move_insn (res, tmp);
28316 emit_label (label);
28317 LABEL_NUSES (label) = 1;
28319 emit_move_insn (operand0, res);
28322 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28325 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28327 /* C code for the stuff we expand below.
28328 double xa = fabs (x), x2;
28329 if (!isless (xa, TWO52))
28331 x2 = (double)(long)x;
28338 if (HONOR_SIGNED_ZEROS (mode))
28339 return copysign (x2, x);
28342 enum machine_mode mode = GET_MODE (operand0);
28343 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28345 TWO52 = ix86_gen_TWO52 (mode);
28347 /* Temporary for holding the result, initialized to the input
28348 operand to ease control flow. */
28349 res = gen_reg_rtx (mode);
28350 emit_move_insn (res, operand1);
28352 /* xa = abs (operand1) */
28353 xa = ix86_expand_sse_fabs (res, &mask);
28355 /* if (!isless (xa, TWO52)) goto label; */
28356 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28358 /* xa = (double)(long)x */
28359 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28360 expand_fix (xi, res, 0);
28361 expand_float (xa, xi, 0);
28364 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28366 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28367 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28368 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28369 gen_rtx_AND (mode, one, tmp)));
28370 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28371 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28372 emit_move_insn (res, tmp);
28374 if (HONOR_SIGNED_ZEROS (mode))
28375 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28377 emit_label (label);
28378 LABEL_NUSES (label) = 1;
28380 emit_move_insn (operand0, res);
28383 /* Expand SSE sequence for computing round from OPERAND1 storing
28384 into OPERAND0. Sequence that works without relying on DImode truncation
28385 via cvttsd2siq that is only available on 64bit targets. */
28387 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28389 /* C code for the stuff we expand below.
28390 double xa = fabs (x), xa2, x2;
28391 if (!isless (xa, TWO52))
28393 Using the absolute value and copying back sign makes
28394 -0.0 -> -0.0 correct.
28395 xa2 = xa + TWO52 - TWO52;
28400 else if (dxa > 0.5)
28402 x2 = copysign (xa2, x);
28405 enum machine_mode mode = GET_MODE (operand0);
28406 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28408 TWO52 = ix86_gen_TWO52 (mode);
28410 /* Temporary for holding the result, initialized to the input
28411 operand to ease control flow. */
28412 res = gen_reg_rtx (mode);
28413 emit_move_insn (res, operand1);
28415 /* xa = abs (operand1) */
28416 xa = ix86_expand_sse_fabs (res, &mask);
28418 /* if (!isless (xa, TWO52)) goto label; */
28419 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28421 /* xa2 = xa + TWO52 - TWO52; */
28422 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28423 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
28425 /* dxa = xa2 - xa; */
28426 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
28428 /* generate 0.5, 1.0 and -0.5 */
28429 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
28430 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
28431 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
28435 tmp = gen_reg_rtx (mode);
28436 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28437 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
28438 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28439 gen_rtx_AND (mode, one, tmp)));
28440 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28441 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28442 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
28443 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28444 gen_rtx_AND (mode, one, tmp)));
28445 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28447 /* res = copysign (xa2, operand1) */
28448 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
28450 emit_label (label);
28451 LABEL_NUSES (label) = 1;
28453 emit_move_insn (operand0, res);
28456 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28459 ix86_expand_trunc (rtx operand0, rtx operand1)
28461 /* C code for SSE variant we expand below.
28462 double xa = fabs (x), x2;
28463 if (!isless (xa, TWO52))
28465 x2 = (double)(long)x;
28466 if (HONOR_SIGNED_ZEROS (mode))
28467 return copysign (x2, x);
28470 enum machine_mode mode = GET_MODE (operand0);
28471 rtx xa, xi, TWO52, label, res, mask;
28473 TWO52 = ix86_gen_TWO52 (mode);
28475 /* Temporary for holding the result, initialized to the input
28476 operand to ease control flow. */
28477 res = gen_reg_rtx (mode);
28478 emit_move_insn (res, operand1);
28480 /* xa = abs (operand1) */
28481 xa = ix86_expand_sse_fabs (res, &mask);
28483 /* if (!isless (xa, TWO52)) goto label; */
28484 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28486 /* x = (double)(long)x */
28487 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28488 expand_fix (xi, res, 0);
28489 expand_float (res, xi, 0);
28491 if (HONOR_SIGNED_ZEROS (mode))
28492 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28494 emit_label (label);
28495 LABEL_NUSES (label) = 1;
28497 emit_move_insn (operand0, res);
28500 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28503 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
28505 enum machine_mode mode = GET_MODE (operand0);
28506 rtx xa, mask, TWO52, label, one, res, smask, tmp;
28508 /* C code for SSE variant we expand below.
28509 double xa = fabs (x), x2;
28510 if (!isless (xa, TWO52))
28512 xa2 = xa + TWO52 - TWO52;
28516 x2 = copysign (xa2, x);
28520 TWO52 = ix86_gen_TWO52 (mode);
28522 /* Temporary for holding the result, initialized to the input
28523 operand to ease control flow. */
28524 res = gen_reg_rtx (mode);
28525 emit_move_insn (res, operand1);
28527 /* xa = abs (operand1) */
28528 xa = ix86_expand_sse_fabs (res, &smask);
28530 /* if (!isless (xa, TWO52)) goto label; */
28531 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28533 /* res = xa + TWO52 - TWO52; */
28534 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28535 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
28536 emit_move_insn (res, tmp);
28539 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28541 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
28542 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
28543 emit_insn (gen_rtx_SET (VOIDmode, mask,
28544 gen_rtx_AND (mode, mask, one)));
28545 tmp = expand_simple_binop (mode, MINUS,
28546 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
28547 emit_move_insn (res, tmp);
28549 /* res = copysign (res, operand1) */
28550 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
28552 emit_label (label);
28553 LABEL_NUSES (label) = 1;
28555 emit_move_insn (operand0, res);
28558 /* Expand SSE sequence for computing round from OPERAND1 storing
28561 ix86_expand_round (rtx operand0, rtx operand1)
28563 /* C code for the stuff we're doing below:
28564 double xa = fabs (x);
28565 if (!isless (xa, TWO52))
28567 xa = (double)(long)(xa + nextafter (0.5, 0.0));
28568 return copysign (xa, x);
28570 enum machine_mode mode = GET_MODE (operand0);
28571 rtx res, TWO52, xa, label, xi, half, mask;
28572 const struct real_format *fmt;
28573 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28575 /* Temporary for holding the result, initialized to the input
28576 operand to ease control flow. */
28577 res = gen_reg_rtx (mode);
28578 emit_move_insn (res, operand1);
28580 TWO52 = ix86_gen_TWO52 (mode);
28581 xa = ix86_expand_sse_fabs (res, &mask);
28582 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28584 /* load nextafter (0.5, 0.0) */
28585 fmt = REAL_MODE_FORMAT (mode);
28586 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28587 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28589 /* xa = xa + 0.5 */
28590 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
28591 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
28593 /* xa = (double)(int64_t)xa */
28594 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28595 expand_fix (xi, xa, 0);
28596 expand_float (xa, xi, 0);
28598 /* res = copysign (xa, operand1) */
28599 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
28601 emit_label (label);
28602 LABEL_NUSES (label) = 1;
28604 emit_move_insn (operand0, res);
28608 /* Validate whether a SSE5 instruction is valid or not.
28609 OPERANDS is the array of operands.
28610 NUM is the number of operands.
28611 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
28612 NUM_MEMORY is the maximum number of memory operands to accept.
28613 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
28616 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
28617 bool uses_oc0, int num_memory, bool commutative)
28623 /* Count the number of memory arguments */
28626 for (i = 0; i < num; i++)
28628 enum machine_mode mode = GET_MODE (operands[i]);
28629 if (register_operand (operands[i], mode))
28632 else if (memory_operand (operands[i], mode))
28634 mem_mask |= (1 << i);
28640 rtx pattern = PATTERN (insn);
28642 /* allow 0 for pcmov */
28643 if (GET_CODE (pattern) != SET
28644 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
28646 || operands[i] != CONST0_RTX (mode))
28651 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
28652 a memory operation. */
28653 if (num_memory < 0)
28655 num_memory = -num_memory;
28656 if ((mem_mask & (1 << (num-1))) != 0)
28658 mem_mask &= ~(1 << (num-1));
28663 /* If there were no memory operations, allow the insn */
28667 /* Do not allow the destination register to be a memory operand. */
28668 else if (mem_mask & (1 << 0))
28671 /* If there are too many memory operations, disallow the instruction. While
28672 the hardware only allows 1 memory reference, before register allocation
28673 for some insns, we allow two memory operations sometimes in order to allow
28674 code like the following to be optimized:
28676 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
28678 or similar cases that are vectorized into using the fmaddss
28680 else if (mem_count > num_memory)
28683 /* Don't allow more than one memory operation if not optimizing. */
28684 else if (mem_count > 1 && !optimize)
28687 else if (num == 4 && mem_count == 1)
28689 /* formats (destination is the first argument), example fmaddss:
28690 xmm1, xmm1, xmm2, xmm3/mem
28691 xmm1, xmm1, xmm2/mem, xmm3
28692 xmm1, xmm2, xmm3/mem, xmm1
28693 xmm1, xmm2/mem, xmm3, xmm1 */
28695 return ((mem_mask == (1 << 1))
28696 || (mem_mask == (1 << 2))
28697 || (mem_mask == (1 << 3)));
28699 /* format, example pmacsdd:
28700 xmm1, xmm2, xmm3/mem, xmm1 */
28702 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
28704 return (mem_mask == (1 << 2));
28707 else if (num == 4 && num_memory == 2)
28709 /* If there are two memory operations, we can load one of the memory ops
28710 into the destination register. This is for optimizing the
28711 multiply/add ops, which the combiner has optimized both the multiply
28712 and the add insns to have a memory operation. We have to be careful
28713 that the destination doesn't overlap with the inputs. */
28714 rtx op0 = operands[0];
28716 if (reg_mentioned_p (op0, operands[1])
28717 || reg_mentioned_p (op0, operands[2])
28718 || reg_mentioned_p (op0, operands[3]))
28721 /* formats (destination is the first argument), example fmaddss:
28722 xmm1, xmm1, xmm2, xmm3/mem
28723 xmm1, xmm1, xmm2/mem, xmm3
28724 xmm1, xmm2, xmm3/mem, xmm1
28725 xmm1, xmm2/mem, xmm3, xmm1
28727 For the oc0 case, we will load either operands[1] or operands[3] into
28728 operands[0], so any combination of 2 memory operands is ok. */
28732 /* format, example pmacsdd:
28733 xmm1, xmm2, xmm3/mem, xmm1
28735 For the integer multiply/add instructions be more restrictive and
28736 require operands[2] and operands[3] to be the memory operands. */
28738 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
28740 return (mem_mask == ((1 << 2) | (1 << 3)));
28743 else if (num == 3 && num_memory == 1)
28745 /* formats, example protb:
28746 xmm1, xmm2, xmm3/mem
28747 xmm1, xmm2/mem, xmm3 */
28749 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
28751 /* format, example comeq:
28752 xmm1, xmm2, xmm3/mem */
28754 return (mem_mask == (1 << 2));
28758 gcc_unreachable ();
28764 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
28765 hardware will allow by using the destination register to load one of the
28766 memory operations. Presently this is used by the multiply/add routines to
28767 allow 2 memory references. */
28770 ix86_expand_sse5_multiple_memory (rtx operands[],
28772 enum machine_mode mode)
28774 rtx op0 = operands[0];
28776 || memory_operand (op0, mode)
28777 || reg_mentioned_p (op0, operands[1])
28778 || reg_mentioned_p (op0, operands[2])
28779 || reg_mentioned_p (op0, operands[3]))
28780 gcc_unreachable ();
28782 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
28783 the destination register. */
28784 if (memory_operand (operands[1], mode))
28786 emit_move_insn (op0, operands[1]);
28789 else if (memory_operand (operands[3], mode))
28791 emit_move_insn (op0, operands[3]);
28795 gcc_unreachable ();
28801 /* Table of valid machine attributes. */
28802 static const struct attribute_spec ix86_attribute_table[] =
28804 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
28805 /* Stdcall attribute says callee is responsible for popping arguments
28806 if they are not variable. */
28807 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28808 /* Fastcall attribute says callee is responsible for popping arguments
28809 if they are not variable. */
28810 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28811 /* Cdecl attribute says the callee is a normal C declaration */
28812 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28813 /* Regparm attribute specifies how many integer arguments are to be
28814 passed in registers. */
28815 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
28816 /* Sseregparm attribute says we are using x86_64 calling conventions
28817 for FP arguments. */
28818 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28819 /* force_align_arg_pointer says this function realigns the stack at entry. */
28820 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
28821 false, true, true, ix86_handle_cconv_attribute },
28822 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
28823 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
28824 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
28825 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
28827 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
28828 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
28829 #ifdef SUBTARGET_ATTRIBUTE_TABLE
28830 SUBTARGET_ATTRIBUTE_TABLE,
28832 /* ms_abi and sysv_abi calling convention function attributes. */
28833 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
28834 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
28836 { NULL, 0, 0, false, false, false, NULL }
28839 /* Implement targetm.vectorize.builtin_vectorization_cost. */
28841 x86_builtin_vectorization_cost (bool runtime_test)
28843 /* If the branch of the runtime test is taken - i.e. - the vectorized
28844 version is skipped - this incurs a misprediction cost (because the
28845 vectorized version is expected to be the fall-through). So we subtract
28846 the latency of a mispredicted branch from the costs that are incured
28847 when the vectorized version is executed.
28849 TODO: The values in individual target tables have to be tuned or new
28850 fields may be needed. For eg. on K8, the default branch path is the
28851 not-taken path. If the taken path is predicted correctly, the minimum
28852 penalty of going down the taken-path is 1 cycle. If the taken-path is
28853 not predicted correctly, then the minimum penalty is 10 cycles. */
28857 return (-(ix86_cost->cond_taken_branch_cost));
28863 /* This function returns the calling abi specific va_list type node.
28864 It returns the FNDECL specific va_list type. */
28867 ix86_fn_abi_va_list (tree fndecl)
28872 return va_list_type_node;
28873 gcc_assert (fndecl != NULL_TREE);
28874 abi = ix86_function_abi ((const_tree) fndecl);
28877 return ms_va_list_type_node;
28879 return sysv_va_list_type_node;
28882 /* Returns the canonical va_list type specified by TYPE. If there
28883 is no valid TYPE provided, it return NULL_TREE. */
28886 ix86_canonical_va_list_type (tree type)
28890 /* Resolve references and pointers to va_list type. */
28891 if (INDIRECT_REF_P (type))
28892 type = TREE_TYPE (type);
28893 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
28894 type = TREE_TYPE (type);
28898 wtype = va_list_type_node;
28899 gcc_assert (wtype != NULL_TREE);
28901 if (TREE_CODE (wtype) == ARRAY_TYPE)
28903 /* If va_list is an array type, the argument may have decayed
28904 to a pointer type, e.g. by being passed to another function.
28905 In that case, unwrap both types so that we can compare the
28906 underlying records. */
28907 if (TREE_CODE (htype) == ARRAY_TYPE
28908 || POINTER_TYPE_P (htype))
28910 wtype = TREE_TYPE (wtype);
28911 htype = TREE_TYPE (htype);
28914 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
28915 return va_list_type_node;
28916 wtype = sysv_va_list_type_node;
28917 gcc_assert (wtype != NULL_TREE);
28919 if (TREE_CODE (wtype) == ARRAY_TYPE)
28921 /* If va_list is an array type, the argument may have decayed
28922 to a pointer type, e.g. by being passed to another function.
28923 In that case, unwrap both types so that we can compare the
28924 underlying records. */
28925 if (TREE_CODE (htype) == ARRAY_TYPE
28926 || POINTER_TYPE_P (htype))
28928 wtype = TREE_TYPE (wtype);
28929 htype = TREE_TYPE (htype);
28932 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
28933 return sysv_va_list_type_node;
28934 wtype = ms_va_list_type_node;
28935 gcc_assert (wtype != NULL_TREE);
28937 if (TREE_CODE (wtype) == ARRAY_TYPE)
28939 /* If va_list is an array type, the argument may have decayed
28940 to a pointer type, e.g. by being passed to another function.
28941 In that case, unwrap both types so that we can compare the
28942 underlying records. */
28943 if (TREE_CODE (htype) == ARRAY_TYPE
28944 || POINTER_TYPE_P (htype))
28946 wtype = TREE_TYPE (wtype);
28947 htype = TREE_TYPE (htype);
28950 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
28951 return ms_va_list_type_node;
28954 return std_canonical_va_list_type (type);
28957 /* Iterate through the target-specific builtin types for va_list.
28958 IDX denotes the iterator, *PTREE is set to the result type of
28959 the va_list builtin, and *PNAME to its internal type.
28960 Returns zero if there is no element for this index, otherwise
28961 IDX should be increased upon the next call.
28962 Note, do not iterate a base builtin's name like __builtin_va_list.
28963 Used from c_common_nodes_and_builtins. */
28966 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
28972 *ptree = ms_va_list_type_node;
28973 *pname = "__builtin_ms_va_list";
28976 *ptree = sysv_va_list_type_node;
28977 *pname = "__builtin_sysv_va_list";
28985 /* Initialize the GCC target structure. */
28986 #undef TARGET_RETURN_IN_MEMORY
28987 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
28989 #undef TARGET_ATTRIBUTE_TABLE
28990 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
28991 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
28992 # undef TARGET_MERGE_DECL_ATTRIBUTES
28993 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
28996 #undef TARGET_COMP_TYPE_ATTRIBUTES
28997 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
28999 #undef TARGET_INIT_BUILTINS
29000 #define TARGET_INIT_BUILTINS ix86_init_builtins
29001 #undef TARGET_EXPAND_BUILTIN
29002 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29004 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29005 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29006 ix86_builtin_vectorized_function
29008 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29009 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29011 #undef TARGET_BUILTIN_RECIPROCAL
29012 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29014 #undef TARGET_ASM_FUNCTION_EPILOGUE
29015 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29017 #undef TARGET_ENCODE_SECTION_INFO
29018 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29019 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29021 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29024 #undef TARGET_ASM_OPEN_PAREN
29025 #define TARGET_ASM_OPEN_PAREN ""
29026 #undef TARGET_ASM_CLOSE_PAREN
29027 #define TARGET_ASM_CLOSE_PAREN ""
29029 #undef TARGET_ASM_ALIGNED_HI_OP
29030 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29031 #undef TARGET_ASM_ALIGNED_SI_OP
29032 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29034 #undef TARGET_ASM_ALIGNED_DI_OP
29035 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29038 #undef TARGET_ASM_UNALIGNED_HI_OP
29039 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29040 #undef TARGET_ASM_UNALIGNED_SI_OP
29041 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29042 #undef TARGET_ASM_UNALIGNED_DI_OP
29043 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29045 #undef TARGET_SCHED_ADJUST_COST
29046 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29047 #undef TARGET_SCHED_ISSUE_RATE
29048 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29049 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29050 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29051 ia32_multipass_dfa_lookahead
29053 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29054 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29057 #undef TARGET_HAVE_TLS
29058 #define TARGET_HAVE_TLS true
29060 #undef TARGET_CANNOT_FORCE_CONST_MEM
29061 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29062 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29063 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29065 #undef TARGET_DELEGITIMIZE_ADDRESS
29066 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29068 #undef TARGET_MS_BITFIELD_LAYOUT_P
29069 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29072 #undef TARGET_BINDS_LOCAL_P
29073 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29075 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29076 #undef TARGET_BINDS_LOCAL_P
29077 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29080 #undef TARGET_ASM_OUTPUT_MI_THUNK
29081 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29082 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29083 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29085 #undef TARGET_ASM_FILE_START
29086 #define TARGET_ASM_FILE_START x86_file_start
29088 #undef TARGET_DEFAULT_TARGET_FLAGS
29089 #define TARGET_DEFAULT_TARGET_FLAGS \
29091 | TARGET_SUBTARGET_DEFAULT \
29092 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29094 #undef TARGET_HANDLE_OPTION
29095 #define TARGET_HANDLE_OPTION ix86_handle_option
29097 #undef TARGET_RTX_COSTS
29098 #define TARGET_RTX_COSTS ix86_rtx_costs
29099 #undef TARGET_ADDRESS_COST
29100 #define TARGET_ADDRESS_COST ix86_address_cost
29102 #undef TARGET_FIXED_CONDITION_CODE_REGS
29103 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29104 #undef TARGET_CC_MODES_COMPATIBLE
29105 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29107 #undef TARGET_MACHINE_DEPENDENT_REORG
29108 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29110 #undef TARGET_BUILD_BUILTIN_VA_LIST
29111 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29113 #undef TARGET_FN_ABI_VA_LIST
29114 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29116 #undef TARGET_CANONICAL_VA_LIST_TYPE
29117 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29119 #undef TARGET_EXPAND_BUILTIN_VA_START
29120 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29122 #undef TARGET_MD_ASM_CLOBBERS
29123 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29125 #undef TARGET_PROMOTE_PROTOTYPES
29126 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29127 #undef TARGET_STRUCT_VALUE_RTX
29128 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29129 #undef TARGET_SETUP_INCOMING_VARARGS
29130 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29131 #undef TARGET_MUST_PASS_IN_STACK
29132 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29133 #undef TARGET_PASS_BY_REFERENCE
29134 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29135 #undef TARGET_INTERNAL_ARG_POINTER
29136 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29137 #undef TARGET_UPDATE_STACK_BOUNDARY
29138 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29139 #undef TARGET_GET_DRAP_RTX
29140 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29141 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29142 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29143 #undef TARGET_STRICT_ARGUMENT_NAMING
29144 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29146 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29147 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29149 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29150 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29152 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29153 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29155 #undef TARGET_C_MODE_FOR_SUFFIX
29156 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29159 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29160 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29163 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29164 #undef TARGET_INSERT_ATTRIBUTES
29165 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29168 #undef TARGET_MANGLE_TYPE
29169 #define TARGET_MANGLE_TYPE ix86_mangle_type
29171 #undef TARGET_STACK_PROTECT_FAIL
29172 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29174 #undef TARGET_FUNCTION_VALUE
29175 #define TARGET_FUNCTION_VALUE ix86_function_value
29177 #undef TARGET_SECONDARY_RELOAD
29178 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29180 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29181 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29183 #undef TARGET_SET_CURRENT_FUNCTION
29184 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29186 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29187 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29189 #undef TARGET_OPTION_SAVE
29190 #define TARGET_OPTION_SAVE ix86_function_specific_save
29192 #undef TARGET_OPTION_RESTORE
29193 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29195 #undef TARGET_OPTION_PRINT
29196 #define TARGET_OPTION_PRINT ix86_function_specific_print
29198 #undef TARGET_OPTION_CAN_INLINE_P
29199 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29201 struct gcc_target targetm = TARGET_INITIALIZER;
29203 #include "gt-i386.h"
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