1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (define_attr "cpu" "h8300,h8300h"
30 (const (symbol_ref "cpu_type")))
32 ;; ??? If we can remove the operand type on all the insns, do it.
33 ;; ??? Otherwise, try to have the operand type on all the insns.
34 ;; ??? Many patterns have overly conservative lengths. In particular:
36 ;; * movXX insns using register indirect addressing.
37 ;; * insns referencing the 8-bit area with an 8-bit address.
39 ;; Loading some 32bit integer constants could be done more
40 ;; efficiently. For example loading the value 4 as a 32bit
41 ;; is normally done via mov.l #4,erX. sub.l erX,erX, inc.l #4,erX
42 ;; would be more efficient time and space-wise. Similar sequences
43 ;; can be found using bit-set insns dec, etc
45 ;; Many logical operations should have "bit" variants if only one
46 ;; bit is going to be operated on.
48 ;; Should be HI & SImode tstXX insns which test one bit using btst.
50 ;; Some insns allow general operations, but lengths don't take
51 ;; into account that a general operand may be a memory reference
52 ;; with a long length. (EXTEND insns)
54 ;; On the h8300h, adds/subs operate on the 32bit "er" registers. Right
55 ;; now GCC doesn't expose the "e" half to the compiler, so using add/subs
56 ;; for addhi and subhi is safe.
57 ;; Long term, we want to expose the "e" half to the compiler (gives us
58 ;; 8 more 16bit registers). At that point addhi and subhi can't use adds/subs.
60 ;; There's currently no way to have a insv/extzv expander for the h8/300h
61 ;; because word_mode is different for the h8/300 and h8/300h.
63 ;; ??? Implement remaining bit ops available on the h8300
65 (define_attr "type" "branch,bcs,arith"
66 (const_string "arith"))
68 ;; The size of instructions in bytes.
70 (define_attr "length" ""
71 (cond [(eq_attr "type" "branch")
72 (if_then_else (and (ge (minus (pc) (match_dup 0))
74 (le (minus (pc) (match_dup 0))
77 (if_then_else (and (eq_attr "cpu" "h8300h")
78 (and (ge (minus (pc) (match_dup 0))
80 (le (minus (pc) (match_dup 0))
84 (eq_attr "type" "bcs")
85 (if_then_else (and (ge (minus (pc) (match_dup 0))
87 (le (minus (pc) (match_dup 0))
90 (match_operand 2 "register_operand" "")
93 (if_then_else (and (eq_attr "cpu" "h8300h")
94 (and (ge (minus (pc) (match_dup 0))
96 (le (minus (pc) (match_dup 0))
99 (match_operand 2 "register_operand" "")
103 (match_operand 2 "register_operand" "")
108 ;; Condition code settings.
109 ;; none - insn does not affect cc
110 ;; none_0hit - insn does not affect cc but it does modify operand 0
111 ;; This attribute is used to keep track of when operand 0 changes.
112 ;; See the description of NOTICE_UPDATE_CC for more info.
113 ;; set - insn sets flags z,n. v,c are set to 0.
114 ;; (c may not really be set to 0 but that's ok, we don't need it anyway).
115 ;; set_zn_c0 - insn sets z,n to usable values. v is unknown. c may or may not
116 ;; be known (if it isn't that's ok, we don't need it anyway).
117 ;; compare - compare instruction
118 ;; clobber - value of cc is unknown
119 (define_attr "cc" "none,none_0hit,set,set_zn_c0,compare,clobber"
120 (const_string "clobber"))
122 ;; ----------------------------------------------------------------------
124 ;; ----------------------------------------------------------------------
128 (define_insn "movqi_push"
129 [(set (match_operand:QI 0 "push_operand" "=<")
130 (match_operand:QI 1 "register_operand" "r"))]
135 return \"push.w %T1\";
137 return \"push.l %S1\";
139 [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
140 (set_attr "cc" "set")])
142 (define_insn "movqi_internal"
143 [(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,o")
144 (match_operand:QI 1 "general_operand_src" "I,r>,r,io,r"))]
145 "register_operand (operands[0],QImode)
146 || register_operand (operands[1], QImode)"
153 [(set_attr_alternative "length"
154 [(const_int 2) (const_int 2) (const_int 2)
155 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
156 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
157 (set_attr "cc" "set_zn_c0,set,set,set,set")])
159 (define_expand "movqi"
160 [(set (match_operand:QI 0 "general_operand_dst" "")
161 (match_operand:QI 1 "general_operand_src" ""))]
165 /* One of the ops has to be in a register */
166 if (!register_operand(operand0, QImode)
167 && !register_operand(operand1, QImode))
169 operands[1] = copy_to_mode_reg(QImode, operand1);
173 (define_insn "movstrictqi"
174 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r"))
175 (match_operand:QI 1 "general_operand_src" "I,r,io"))]
181 [(set_attr_alternative "length"
182 [(const_int 2) (const_int 2)
183 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
184 (set_attr "cc" "set_zn_c0,set,set")])
188 ;; ??? We use push.l on the h8300h to push a 16bit value?!? We have
190 (define_insn "movhi_push"
191 [(set (match_operand:HI 0 "push_operand" "=<")
192 (match_operand:HI 1 "register_operand" "r"))]
197 return \"push.w %T1\";
199 return \"push.l %S1\";
201 [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
202 (set_attr "cc" "set")])
204 (define_insn "movhi_internal"
205 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,o")
206 (match_operand:HI 1 "general_operand_src" "I,r>,r,ion,r"))]
207 "register_operand (operands[0],HImode)
208 || register_operand (operands[1], HImode)"
215 [(set_attr_alternative "length"
216 [(const_int 2) (const_int 2) (const_int 2)
217 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
218 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
219 (set_attr "cc" "set_zn_c0,set,set,set,set")])
221 (define_expand "movhi"
222 [(set (match_operand:HI 0 "general_operand_dst" "")
223 (match_operand:HI 1 "general_operand_src" ""))]
227 /* One of the ops has to be in a register */
228 if (!register_operand(operand1, HImode)
229 && !register_operand(operand0, HImode))
231 operands[1] = copy_to_mode_reg(HImode, operand1);
235 (define_insn "movstricthi"
236 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r"))
237 (match_operand:HI 1 "general_operand_src" "I,r,io"))]
243 [(set_attr_alternative "length"
244 [(const_int 2) (const_int 2)
245 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
246 (set_attr "cc" "set_zn_c0,set,set")])
250 (define_expand "movsi"
251 [(set (match_operand:SI 0 "general_operand_dst" "")
252 (match_operand:SI 1 "general_operand_src" ""))]
258 if (do_movsi (operands))
261 else /* TARGET_H8300H */
263 /* One of the ops has to be in a register. */
264 if (!register_operand (operand1, SImode)
265 && !register_operand (operand0, SImode))
267 operands[1] = copy_to_mode_reg (SImode, operand1);
272 (define_expand "movsf"
273 [(set (match_operand:SF 0 "general_operand_dst" "")
274 (match_operand:SF 1 "general_operand_src" ""))]
280 if (do_movsi (operands))
283 else /* TARGET_H8300H */
285 /* One of the ops has to be in a register. */
286 if (!register_operand (operand1, SFmode)
287 && !register_operand (operand0, SFmode))
289 operands[1] = copy_to_mode_reg (SFmode, operand1);
294 (define_insn "movsi_h8300"
295 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
296 (match_operand:SI 1 "general_operand_src" "I,r,ion,r,r,>"))]
298 && (register_operand (operands[0], SImode)
299 || register_operand (operands[1], SImode))"
303 switch (which_alternative)
306 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
308 if (REGNO(operands[0]) < REGNO(operands[1]))
309 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
311 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
313 /* Make sure we don't trample the register we index with. */
315 if (GET_CODE(operands[1]) == MEM)
317 rtx inside = XEXP (operands[1],0);
322 else if (GET_CODE (inside) == PLUS)
324 rtx lhs = XEXP (inside,0);
325 rtx rhs = XEXP (inside,1);
326 if (REG_P (lhs)) rn = REGNO (lhs);
327 if (REG_P (rhs)) rn = REGNO (rhs);
330 if (rn == REGNO (operands[0]))
332 /* Move the second word first. */
333 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
337 /* See if either half is zero. If so, use sub.w to clear
339 if (GET_CODE (operands[1]) == CONST_INT)
341 if ((INTVAL (operands[1]) & 0xffff) == 0)
342 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
343 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
344 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
346 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
349 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
351 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
353 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
356 [(set_attr "length" "4,4,8,8,4,4")
357 (set_attr "cc" "clobber")])
359 (define_insn "movsf_h8300"
360 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
361 (match_operand:SF 1 "general_operand_src" "I,r,ion,r,r,>"))]
363 && (register_operand (operands[0], SFmode)
364 || register_operand (operands[1], SFmode))"
367 /* Copy of the movsi stuff */
369 switch (which_alternative)
372 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
374 if (REGNO(operands[0]) < REGNO(operands[1]))
375 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
377 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
379 /* Make sure we don't trample the register we index with. */
381 if (GET_CODE (operands[1]) == MEM)
383 rtx inside = XEXP (operands[1],0);
388 else if (GET_CODE (inside) == PLUS)
390 rtx lhs = XEXP (inside,0);
391 rtx rhs = XEXP (inside,1);
392 if (REG_P (lhs)) rn = REGNO (lhs);
393 if (REG_P (rhs)) rn = REGNO (rhs);
396 if (rn == REGNO (operands[0]))
398 /* move the second word first */
399 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
403 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
407 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
409 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
411 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
415 [(set_attr "length" "4,4,8,8,4,4")
416 (set_attr "cc" "clobber")])
418 (define_insn "movsi_h8300h"
419 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
420 (match_operand:SI 1 "general_operand_src" "I,r,ion,r,r,>"))]
422 && (register_operand (operands[0], SImode)
423 || register_operand (operands[1], SImode))"
426 if (which_alternative == 0)
427 return \"sub.l %S0,%S0\";
428 if (GET_CODE (operands[1]) == CONST_INT)
430 int val = INTVAL (operands[1]);
432 /* Look for constants which can be made by adding an 8-bit
433 number to zero in one of the two low bytes. */
434 if (val == (val & 0xff))
436 operands[1] = GEN_INT ((char)val & 0xff);
437 return \"sub.l %S0,%S0\;add.b %1,%w0\";
440 if (val == (val & 0xff00))
442 operands[1] = GEN_INT ((char)(val >> 8) & 0xff);
443 return \"sub.l %S0,%S0\;add.b %1,%x0\";
446 /* Now look for small negative numbers. We can subtract them
447 from zero to get the desired constant. */
448 if (val == -4 || val == -2 || val == -1)
450 operands[1] = GEN_INT (-INTVAL (operands[1]));
451 return \"sub.l %S0,%S0\;subs %1,%S0\";
454 return \"mov.l %S1,%S0\";
456 [(set_attr "length" "2,2,10,10,4,4")
457 (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
459 (define_insn "movsf_h8300h"
460 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
461 (match_operand:SF 1 "general_operand_src" "I,r,ion,r,r,>"))]
463 && (register_operand (operands[0], SFmode)
464 || register_operand (operands[1], SFmode))"
472 [(set_attr "length" "2,2,10,10,4,4")
473 (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
475 ;; ----------------------------------------------------------------------
477 ;; ----------------------------------------------------------------------
480 [(set (cc0) (and:QI (match_operand:QI 0 "bit_operand" "Ur")
481 (match_operand:QI 1 "o_operand" "O")))]
484 [(set_attr "length" "2")
485 (set_attr "cc" "set_zn_c0")])
488 [(set (cc0) (match_operand:QI 0 "general_operand" "r"))]
491 [(set_attr "length" "2")
492 (set_attr "cc" "set")])
495 [(set (cc0) (match_operand:HI 0 "general_operand" "r"))]
498 [(set_attr "length" "2")
499 (set_attr "cc" "set")])
502 [(set (cc0) (match_operand:SI 0 "general_operand" "r"))]
505 [(set_attr "length" "2")
506 (set_attr "cc" "set")])
510 (compare:QI (match_operand:QI 0 "register_operand" "r")
511 (match_operand:QI 1 "nonmemory_operand" "ri")))]
514 [(set_attr "length" "2")
515 (set_attr "cc" "compare")])
517 (define_expand "cmphi"
519 (compare:HI (match_operand:HI 0 "register_operand" "")
520 (match_operand:HI 1 "nonmemory_operand" "")))]
524 /* Force operand1 into a register if we're compiling
526 if (GET_CODE (operands[1]) != REG && !TARGET_H8300H)
527 operands[1] = force_reg (HImode, operands[1]);
532 (compare:HI (match_operand:HI 0 "register_operand" "r")
533 (match_operand:HI 1 "register_operand" "r")))]
536 [(set_attr "length" "2")
537 (set_attr "cc" "compare")])
541 (compare:HI (match_operand:HI 0 "register_operand" "r")
542 (match_operand:HI 1 "nonmemory_operand" "ri")))]
545 [(set_attr "length" "2")
546 (set_attr "cc" "compare")])
550 (compare:SI (match_operand:SI 0 "register_operand" "r")
551 (match_operand:SI 1 "nonmemory_operand" "ri")))]
554 [(set_attr "length" "2")
555 (set_attr "cc" "compare")])
557 ;; ----------------------------------------------------------------------
559 ;; ----------------------------------------------------------------------
561 (define_insn "addqi3"
562 [(set (match_operand:QI 0 "register_operand" "=r")
563 (plus:QI (match_operand:QI 1 "register_operand" "%0")
564 (match_operand:QI 2 "nonmemory_operand" "ri")))]
567 [(set_attr "length" "2")
568 (set_attr "cc" "set_zn_c0")])
570 (define_expand "addhi3"
571 [(set (match_operand:HI 0 "register_operand" "")
572 (plus:HI (match_operand:HI 1 "register_operand" "")
573 (match_operand:HI 2 "nonmemory_operand" "")))]
577 ;; Specialized version using adds/subs. This must come before
578 ;; the more general patterns below.
580 [(set (match_operand:HI 0 "register_operand" "=r")
581 (plus:HI (match_operand:HI 1 "register_operand" "%0")
582 (match_operand:HI 2 "adds_subs_operand" "i")))]
584 "* return output_adds_subs (operands);"
585 [(set_attr "length" "4")
586 (set_attr "cc" "none_0hit")])
589 [(set (match_operand:HI 0 "register_operand" "=&r,r,&r")
590 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,g")
591 (match_operand:HI 2 "nonmemory_operand" "n,r,r")))]
594 add.b %s2,%s0\;addx %t2,%t0
596 mov.w %T1,%T0\;add.w %T2,%T0"
597 [(set_attr "length" "4,2,6")
598 (set_attr "cc" "clobber,set_zn_c0,set_zn_c0")])
601 [(set (match_operand:HI 0 "register_operand" "=r,r")
602 (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
603 (match_operand:HI 2 "nonmemory_operand" "i,r")))]
608 [(set_attr "length" "4,2")
609 (set_attr "cc" "set_zn_c0,set_zn_c0")])
611 (define_expand "addsi3"
612 [(set (match_operand:SI 0 "register_operand" "")
613 (plus:SI (match_operand:SI 1 "register_operand" "")
614 (match_operand:SI 2 "nonmemory_operand" "")))]
618 ;; Specialized version using adds/subs. This must come before
619 ;; the more general patterns below.
621 [(set (match_operand:SI 0 "register_operand" "=r")
622 (plus:SI (match_operand:SI 1 "register_operand" "%0")
623 (match_operand:SI 2 "adds_subs_operand" "i")))]
625 "* return output_adds_subs (operands);"
626 [(set_attr "length" "4")
627 (set_attr "cc" "none_0hit")])
629 (define_insn "addsi_h8300"
630 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
631 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
632 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
635 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
636 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
637 mov %f1,%f0\;mov %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
638 [(set_attr "length" "8,6,20")
639 (set_attr "cc" "clobber")])
641 (define_insn "addsi_h8300h"
642 [(set (match_operand:SI 0 "register_operand" "=r,r")
643 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
644 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
649 [(set_attr "length" "6,2")
650 (set_attr "cc" "set_zn_c0,set_zn_c0")])
652 ;; ----------------------------------------------------------------------
653 ;; SUBTRACT INSTRUCTIONS
654 ;; ----------------------------------------------------------------------
656 (define_insn "subqi3"
657 [(set (match_operand:QI 0 "register_operand" "=r,r")
658 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
659 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
664 [(set_attr "length" "2")
665 (set_attr "cc" "set_zn_c0")])
667 (define_expand "subhi3"
668 [(set (match_operand:HI 0 "register_operand" "")
669 (minus:HI (match_operand:HI 1 "general_operand" "")
670 (match_operand:HI 2 "nonmemory_operand" "")))]
674 ;; Specialized version using adds/subs. This must come before
675 ;; the more general patterns below. This may not be needed
676 ;; due to instruction canonicalization.
678 [(set (match_operand:HI 0 "register_operand" "=r")
679 (minus:HI (match_operand:HI 1 "register_operand" "r")
680 (match_operand:HI 2 "adds_subs_operand" "i")))]
684 operands[2] = GEN_INT (-INTVAL (operands[2]));
685 return output_adds_subs (operands);
687 [(set_attr "length" "4")
688 (set_attr "cc" "none_0hit")])
691 [(set (match_operand:HI 0 "register_operand" "=r,&r")
692 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
693 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
697 add.b %E2,%s0\;addx %F2,%t0 ; -%0"
698 [(set_attr "length" "2,4")
699 (set_attr "cc" "set_zn_c0,clobber")])
702 [(set (match_operand:HI 0 "register_operand" "=r,&r")
703 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
704 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
709 [(set_attr "length" "2,4")
710 (set_attr "cc" "set_zn_c0,set_zn_c0")])
712 (define_expand "subsi3"
713 [(set (match_operand:SI 0 "register_operand" "")
714 (minus:SI (match_operand:SI 1 "register_operand" "")
715 (match_operand:SI 2 "nonmemory_operand" "")))]
719 (define_insn "subsi3_h8300"
720 [(set (match_operand:SI 0 "register_operand" "=r")
721 (minus:SI (match_operand:SI 1 "register_operand" "0")
722 (match_operand:SI 2 "register_operand" "r")))]
724 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
725 [(set_attr "length" "6")
726 (set_attr "cc" "clobber")])
728 ;; Specialized version using adds/subs. This must come before
729 ;; the more general patterns below. This may not be needed
730 ;; due to instruction canonicalization.
732 [(set (match_operand:SI 0 "register_operand" "=r")
733 (minus:SI (match_operand:SI 1 "general_operand" "0")
734 (match_operand:SI 2 "adds_subs_operand" "i")))]
738 operands[2] = GEN_INT (-INTVAL (operands[2]));
739 return output_adds_subs (operands);
741 [(set_attr "length" "4")
742 (set_attr "cc" "none_0hit")])
744 (define_insn "subsi3_h8300h"
745 [(set (match_operand:SI 0 "register_operand" "=r,r")
746 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
747 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
752 [(set_attr "length" "2,6")
753 (set_attr "cc" "set_zn_c0,set_zn_c0")])
755 ;; ----------------------------------------------------------------------
756 ;; MULTIPLY INSTRUCTIONS
757 ;; ----------------------------------------------------------------------
759 ;; Note that the h8/300 can only handle umulqihi3.
761 (define_insn "mulqihi3"
762 [(set (match_operand:HI 0 "register_operand" "=r")
763 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
764 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
767 [(set_attr "length" "4")
768 (set_attr "cc" "set_zn_c0")])
770 (define_insn "mulhisi3"
771 [(set (match_operand:SI 0 "register_operand" "=r")
772 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
773 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
776 [(set_attr "length" "4")
777 (set_attr "cc" "set_zn_c0")])
779 (define_insn "umulqihi3"
780 [(set (match_operand:HI 0 "register_operand" "=r")
781 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
782 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
785 [(set_attr "length" "2")
786 (set_attr "cc" "none_0hit")])
788 (define_insn "umulhisi3"
789 [(set (match_operand:SI 0 "register_operand" "=r")
790 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
791 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
794 [(set_attr "length" "2")
795 (set_attr "cc" "none_0hit")])
797 ;; ----------------------------------------------------------------------
798 ;; DIVIDE INSTRUCTIONS
799 ;; ----------------------------------------------------------------------
801 (define_insn "udivqi3"
802 [(set (match_operand:QI 0 "register_operand" "=r")
803 (udiv:QI (match_operand:HI 1 "general_operand" "0")
804 (match_operand:QI 2 "register_operand" "r")))]
807 [(set_attr "length" "2")
808 (set_attr "cc" "clobber")])
810 ;; ??? Will divxu always work here?
812 (define_insn "divqi3"
813 [(set (match_operand:QI 0 "register_operand" "=r")
814 (div:QI (match_operand:HI 1 "general_operand" "0")
815 (match_operand:QI 2 "register_operand" "r")))]
818 [(set_attr "length" "2")
819 (set_attr "cc" "clobber")])
821 (define_insn "udivhi3"
822 [(set (match_operand:HI 0 "register_operand" "=r")
823 (udiv:HI (match_operand:SI 1 "general_operand" "0")
824 (match_operand:HI 2 "register_operand" "r")))]
827 [(set_attr "length" "2")
828 (set_attr "cc" "clobber")])
830 (define_insn "divhi3"
831 [(set (match_operand:HI 0 "register_operand" "=r")
832 (div:HI (match_operand:SI 1 "general_operand" "0")
833 (match_operand:HI 2 "register_operand" "r")))]
836 [(set_attr "length" "4")
837 (set_attr "cc" "clobber")])
839 ;; ----------------------------------------------------------------------
841 ;; ----------------------------------------------------------------------
843 (define_insn "umodqi3"
844 [(set (match_operand:QI 0 "register_operand" "=r")
845 (umod:QI (match_operand:HI 1 "general_operand" "0")
846 (match_operand:QI 2 "register_operand" "r")))]
848 "divxu %X2,%T0\;mov %t0,%s0"
849 [(set_attr "length" "4")
850 (set_attr "cc" "clobber")])
852 (define_insn "modqi3"
853 [(set (match_operand:QI 0 "register_operand" "=r")
854 (mod:QI (match_operand:HI 1 "general_operand" "0")
855 (match_operand:QI 2 "register_operand" "r")))]
857 "divxs.b %X2,%T0\;mov %t0,%s0"
858 [(set_attr "length" "6")
859 (set_attr "cc" "clobber")])
861 (define_insn "umodhi3"
862 [(set (match_operand:HI 0 "register_operand" "=r")
863 (umod:HI (match_operand:SI 1 "general_operand" "0")
864 (match_operand:HI 2 "register_operand" "r")))]
866 "divxu.w %T2,%S0\;mov %e0,%f0"
867 [(set_attr "length" "4")
868 (set_attr "cc" "clobber")])
870 (define_insn "modhi3"
871 [(set (match_operand:HI 0 "register_operand" "=r")
872 (mod:HI (match_operand:SI 1 "general_operand" "0")
873 (match_operand:HI 2 "register_operand" "r")))]
875 "divxs.w %T2,%S0\;mov %e0,%f0"
876 [(set_attr "length" "6")
877 (set_attr "cc" "clobber")])
879 ;; ----------------------------------------------------------------------
881 ;; ----------------------------------------------------------------------
883 (define_insn "andqi3_internal"
884 [(set (match_operand:QI 0 "bit_operand" "=r,U")
885 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
886 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
887 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
891 [(set_attr "length" "2,4")
892 (set_attr "cc" "set,none_0hit")])
894 (define_expand "andqi3"
895 [(set (match_operand:QI 0 "bit_operand" "=r,U")
896 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
897 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
901 if (fix_bit_operand (operands, 'O', AND))
905 (define_insn "andhi3"
906 [(set (match_operand:HI 0 "register_operand" "=r,r")
907 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
908 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
912 if (GET_CODE (operands[2]) == CONST_INT)
914 int i = INTVAL (operands[2]);
916 if ((i & 0x00ff) != 0x00ff)
917 output_asm_insn (\"and %s2,%s0\", operands);
918 if ((i & 0xff00) != 0xff00)
919 output_asm_insn (\"and %t2,%t0\", operands);
923 return \"and.w %T2,%T0\";
924 return \"and %s2,%s0\;and %t2,%t0;\";
926 [(set_attr "length" "2,4")
927 (set_attr "cc" "clobber,clobber")])
929 (define_insn "andsi3"
930 [(set (match_operand:SI 0 "register_operand" "=r,r")
931 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
932 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
936 if (GET_CODE (operands[2]) == CONST_INT)
938 int i = INTVAL (operands[2]);
940 /* ??? If we used e0..e7, then we could sub.w eX,eX to
941 clear the high word if (i & 0xffff0000) == 0. */
943 /* The h8300h can't do byte-wise operations on the
944 upper 16bits of 32bit registers. However, if
945 those bits aren't going to change, then we can
946 work on the low-order bits. */
948 && (i & 0xffff0000) != 0xffff0000)
949 return \"and.l %S2,%S0\";
951 if ((i & 0x000000ff) != 0x000000ff)
952 output_asm_insn (\"and %w2,%w0\", operands);
953 if ((i & 0x0000ff00) != 0x0000ff00)
954 output_asm_insn (\"and %x2,%x0\", operands);
955 if ((i & 0x00ff0000) != 0x00ff0000)
956 output_asm_insn (\"and %y2,%y0\", operands);
957 if ((i & 0xff000000) != 0xff000000)
958 output_asm_insn (\"and %z2,%z0\", operands);
962 return \"and.l %S2,%S0\";
963 return \"and %w2,%w0\;and %x2,%x0\;and %y2,%y0\;and %z2,%z0\;\";
965 [(set_attr "length" "2,8")
966 (set_attr "cc" "clobber,clobber")])
968 ;; ----------------------------------------------------------------------
970 ;; ----------------------------------------------------------------------
972 (define_insn "iorqi3_internal"
973 [(set (match_operand:QI 0 "bit_operand" "=r,U")
974 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
975 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
976 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
980 [(set_attr "length" "2,4")
981 (set_attr "cc" "set,none_0hit")])
983 (define_expand "iorqi3"
984 [(set (match_operand:QI 0 "bit_operand" "=r,U")
985 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
986 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
990 if (fix_bit_operand (operands, 'P', IOR))
994 (define_insn "iorhi3"
995 [(set (match_operand:HI 0 "general_operand" "=r,r")
996 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
997 (match_operand:HI 2 "general_operand" "J,rn")))]
1001 if (GET_CODE (operands[2]) == CONST_INT)
1003 int i = INTVAL (operands[2]);
1005 if ((i & 0x00ff) != 0)
1006 output_asm_insn (\"or %s2,%s0\", operands);
1007 if ((i & 0xff00) != 0)
1008 output_asm_insn (\"or %t2,%t0\", operands);
1012 return \"or.w %T2,%T0\";
1013 return \"or %s2,%s0\;or %t2,%t0; %2 or2\";
1015 [(set_attr "length" "2,4")
1016 (set_attr "cc" "clobber,clobber")])
1018 (define_insn "iorsi3"
1019 [(set (match_operand:SI 0 "register_operand" "=r,r")
1020 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1021 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1025 if (GET_CODE (operands[2]) == CONST_INT)
1027 int i = INTVAL (operands[2]);
1029 /* The h8300h can't do byte-wise operations on the
1030 upper 16bits of 32bit registers. However, if
1031 those bits aren't going to change, then we can
1032 work on the low-order bits. */
1034 && (i & 0xffff0000) != 0x00000000)
1035 return \"or.l %S2,%S0\";
1037 if ((i & 0x000000ff) != 0)
1038 output_asm_insn (\"or %w2,%w0\", operands);
1039 if ((i & 0x0000ff00) != 0)
1040 output_asm_insn (\"or %x2,%x0\", operands);
1041 if ((i & 0x00ff0000) != 0)
1042 output_asm_insn (\"or %y2,%y0\", operands);
1043 if ((i & 0xff000000) != 0)
1044 output_asm_insn (\"or %z2,%z0\", operands);
1048 return \"or.l %S2,%S0\";
1049 return \"or %w2,%w0\;or %x2,%x0\;or %y2,%y0\;or %z2,%z0\;\";
1051 [(set_attr "length" "2,8")
1052 (set_attr "cc" "clobber,clobber")])
1054 ;; ----------------------------------------------------------------------
1056 ;; ----------------------------------------------------------------------
1058 (define_insn "xorqi3_internal"
1059 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1060 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1061 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1062 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1066 [(set_attr "length" "2,4")
1067 (set_attr "cc" "set,none_0hit")])
1069 (define_expand "xorqi3"
1070 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1071 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1072 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1076 if (fix_bit_operand (operands, 'O', XOR))
1080 (define_insn "xorhi3"
1081 [(set (match_operand:HI 0 "register_operand" "=r,r")
1082 (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1083 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
1087 if (GET_CODE (operands[2]) == CONST_INT)
1089 int i = INTVAL (operands[2]);
1091 if ((i & 0x00ff) != 0)
1092 output_asm_insn (\"xor %s2,%s0\", operands);
1093 if ((i & 0xff00) != 0)
1094 output_asm_insn (\"xor %t2,%t0\", operands);
1098 return \"xor.w %T2,%T0\";
1099 return \"xor %s2,%s0\;xor %t2,%t0\";
1101 [(set_attr "length" "2,4")
1102 (set_attr "cc" "clobber,clobber")])
1104 (define_insn "xorsi3"
1105 [(set (match_operand:SI 0 "register_operand" "=r,r")
1106 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
1107 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1111 if (GET_CODE (operands[2]) == CONST_INT)
1113 int i = INTVAL (operands[2]);
1115 /* The h8300h can't do byte-wise operations on the
1116 upper 16bits of 32bit registers. However, if
1117 those bits aren't going to change, then we can
1118 work on the low-order bits. */
1120 && (i & 0xffff0000) != 0x00000000)
1121 return \"xor.l %S2,%S0\";
1123 if ((i & 0x000000ff) != 0)
1124 output_asm_insn (\"xor %w2,%w0\", operands);
1125 if ((i & 0x0000ff00) != 0)
1126 output_asm_insn (\"xor %x2,%x0\", operands);
1127 if ((i & 0x00ff0000) != 0)
1128 output_asm_insn (\"xor %y2,%y0\", operands);
1129 if ((i & 0xff000000) != 0)
1130 output_asm_insn (\"xor %z2,%z0\", operands);
1134 return \"xor.l %S2,%S0\";
1135 return \"xor %w2,%w0\;xor %x2,%x0\;xor %y2,%y0\;xor %z2,%z0\;\";
1137 [(set_attr "length" "2,8")
1138 (set_attr "cc" "clobber,clobber")])
1140 ;; ----------------------------------------------------------------------
1141 ;; NEGATION INSTRUCTIONS
1142 ;; ----------------------------------------------------------------------
1144 (define_insn "negqi2"
1145 [(set (match_operand:QI 0 "register_operand" "=r")
1146 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1149 [(set_attr "length" "2")
1150 (set_attr "cc" "set_zn_c0")])
1152 (define_expand "neghi2"
1153 [(set (match_operand:HI 0 "register_operand" "=r")
1154 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1160 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1165 (define_expand "neghi2_h8300"
1167 (not:HI (match_operand:HI 1 "register_operand" "r")))
1168 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1169 (set (match_operand:HI 0 "register_operand" "=r")
1172 "{ operands[2] = gen_reg_rtx (HImode); }")
1174 (define_insn "neghi2_h8300h"
1175 [(set (match_operand:HI 0 "register_operand" "=r")
1176 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1179 [(set_attr "length" "2")
1180 (set_attr "cc" "set_zn_c0")])
1182 (define_expand "negsi2"
1183 [(set (match_operand:SI 0 "register_operand" "=r")
1184 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1190 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1195 (define_expand "negsi2_h8300"
1197 (not:SI (match_operand:SI 1 "register_operand" "r")))
1198 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1199 (set (match_operand:SI 0 "register_operand" "=r")
1202 "{ operands[2] = gen_reg_rtx(SImode); }")
1204 (define_insn "negsi2_h8300h"
1205 [(set (match_operand:SI 0 "register_operand" "=r")
1206 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1209 [(set_attr "length" "2")
1210 (set_attr "cc" "set_zn_c0")])
1212 ;; ----------------------------------------------------------------------
1214 ;; ----------------------------------------------------------------------
1216 (define_insn "one_cmplqi2"
1217 [(set (match_operand:QI 0 "register_operand" "=r")
1218 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1221 [(set_attr "length" "2")
1222 (set_attr "cc" "set")])
1224 (define_insn "one_cmplhi2"
1225 [(set (match_operand:HI 0 "register_operand" "=r")
1226 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1231 return \"not %s0\;not %t0\";
1235 [(set_attr "cc" "clobber")
1236 (set (attr "length")
1237 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1241 (define_insn "one_cmplsi2"
1242 [(set (match_operand:SI 0 "register_operand" "=r")
1243 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1248 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1252 [(set_attr "cc" "clobber")
1253 (set (attr "length")
1254 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
1259 ;; ----------------------------------------------------------------------
1260 ;; JUMP INSTRUCTIONS
1261 ;; ----------------------------------------------------------------------
1263 ;; Conditional jump instructions
1265 (define_expand "ble"
1267 (if_then_else (le (cc0)
1269 (label_ref (match_operand 0 "" ""))
1274 (define_expand "bleu"
1276 (if_then_else (leu (cc0)
1278 (label_ref (match_operand 0 "" ""))
1283 (define_expand "bge"
1285 (if_then_else (ge (cc0)
1287 (label_ref (match_operand 0 "" ""))
1292 (define_expand "bgeu"
1294 (if_then_else (geu (cc0)
1296 (label_ref (match_operand 0 "" ""))
1301 (define_expand "blt"
1303 (if_then_else (lt (cc0)
1305 (label_ref (match_operand 0 "" ""))
1310 (define_expand "bltu"
1312 (if_then_else (ltu (cc0)
1314 (label_ref (match_operand 0 "" ""))
1319 (define_expand "bgt"
1321 (if_then_else (gt (cc0)
1323 (label_ref (match_operand 0 "" ""))
1328 (define_expand "bgtu"
1330 (if_then_else (gtu (cc0)
1332 (label_ref (match_operand 0 "" ""))
1337 (define_expand "beq"
1339 (if_then_else (eq (cc0)
1341 (label_ref (match_operand 0 "" ""))
1346 (define_expand "bne"
1348 (if_then_else (ne (cc0)
1350 (label_ref (match_operand 0 "" ""))
1355 (define_insn "branch_true"
1357 (if_then_else (match_operator 1 "comparison_operator"
1358 [(cc0) (const_int 0)])
1359 (label_ref (match_operand 0 "" ""))
1364 /* If we erroneously deleted a compare insn (which can happen if we need
1365 CC bits set that aren't), emit the compare. */
1366 if (restore_compare_p (operands[1]))
1369 if (get_attr_length (insn) == 2)
1370 return \"b%j1 %l0\";
1371 else if (get_attr_length (insn) == 4)
1372 return \"b%j1 %l0:16\";
1374 return \"b%k1 %L0\;jmp @%l0\;%L0:\";
1376 [(set_attr "type" "branch")
1377 (set_attr "cc" "none")])
1379 (define_insn "branch_false"
1381 (if_then_else (match_operator 1 "comparison_operator"
1382 [(cc0) (const_int 0)])
1384 (label_ref (match_operand 0 "" ""))))]
1388 /* If we erroneously deleted a compare insn (which can happen if we need
1389 CC bits set that aren't), emit the compare. */
1390 if (restore_compare_p (operands[1]))
1393 if (get_attr_length (insn) == 2)
1394 return \"b%k1 %l0\";
1395 else if (get_attr_length (insn) == 4)
1396 return \"b%k1 %l0:16\";
1398 return \"b%j1 %L0\;jmp @%l0\;%L0:\";
1400 [(set_attr "type" "branch")
1401 (set_attr "cc" "none")])
1403 ;; Unconditional and other jump instructions.
1407 (label_ref (match_operand 0 "" "")))]
1411 if (get_attr_length (insn) == 2)
1413 else if (get_attr_length (insn) == 4)
1414 return \"bra %l0:16\";
1416 return \"jmp @%l0\";
1418 [(set_attr "type" "branch")
1419 (set_attr "cc" "none")])
1421 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1423 (define_expand "tablejump"
1424 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1425 (use (label_ref (match_operand 1 "" "")))])]
1429 (define_insn "tablejump_h8300"
1430 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1431 (use (label_ref (match_operand 1 "" "")))]
1434 [(set_attr "cc" "none")
1435 (set_attr "length" "2")])
1437 (define_insn "tablejump_h8300h"
1438 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1439 (use (label_ref (match_operand 1 "" "")))]
1442 [(set_attr "cc" "none")
1443 (set_attr "length" "2")])
1445 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1447 (define_expand "indirect_jump"
1448 [(set (pc) (match_operand 0 "jump_address_operand" "Vr"))]
1452 (define_insn "indirect_jump_h8300"
1453 [(set (pc) (match_operand:HI 0 "jump_address_operand" "V,r"))]
1458 [(set_attr "cc" "none")
1459 (set_attr "length" "2")])
1461 (define_insn "indirect_jump_h8300h"
1462 [(set (pc) (match_operand:SI 0 "jump_address_operand" "V,r"))]
1467 [(set_attr "cc" "none")
1468 (set_attr "length" "2")])
1470 ;; Call subroutine with no return value.
1472 ;; ??? Even though we use HImode here, this works for the 300h.
1475 [(call (match_operand:QI 0 "call_insn_operand" "or")
1476 (match_operand:HI 1 "general_operand" "g"))]
1480 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1481 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1482 return \"jsr\\t\@%0:8\";
1484 return \"jsr\\t%0\";
1486 [(set_attr "cc" "clobber")
1487 (set (attr "length")
1488 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1492 ;; Call subroutine, returning value in operand 0
1493 ;; (which must be a hard register).
1495 ;; ??? Even though we use HImode here, this works on the 300h.
1497 (define_insn "call_value"
1498 [(set (match_operand 0 "" "=r")
1499 (call (match_operand:QI 1 "call_insn_operand" "or")
1500 (match_operand:HI 2 "general_operand" "g")))]
1504 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1505 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1506 return \"jsr\\t\@%1:8\";
1508 return \"jsr\\t%1\";
1510 [(set_attr "cc" "clobber")
1511 (set (attr "length")
1512 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1520 [(set_attr "cc" "none")
1521 (set_attr "length" "2")])
1523 ;; ----------------------------------------------------------------------
1524 ;; EXTEND INSTRUCTIONS
1525 ;; ----------------------------------------------------------------------
1527 (define_insn "zero_extendqihi2"
1528 [(set (match_operand:HI 0 "register_operand" "=r,r")
1529 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1533 mov.b %R1,%s0\;mov.b #0,%t0"
1534 [(set_attr "length" "2,4")
1535 (set_attr "cc" "clobber,clobber")])
1537 ;; The compiler can synthesize a 300H variant of this which is
1538 ;; just as efficient as one that we'd create
1539 (define_insn "zero_extendqisi2"
1540 [(set (match_operand:SI 0 "register_operand" "=r,r")
1541 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1544 mov.b #0,%x0\;sub.w %e0,%e0
1545 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1546 [(set_attr "length" "4,6")
1547 (set_attr "cc" "clobber,clobber")])
1549 (define_expand "zero_extendhisi2"
1550 [(set (match_operand:SI 0 "register_operand" "")
1551 (zero_extend:SI (match_operand:HI 1 "general_operand" "")))]
1555 extern int optimize;
1558 && GET_CODE (operands[1]) != CONST_INT
1561 emit_insn (gen_zero_extendhisi2_h8300 (operands[0], operands[1]));
1567 ;; I don't know why, but if I try to simplify extendhisi2 in the
1568 ;; natural way, I get about a 2X code bloat on the h8300 without
1569 ;; optimization, and a small bloat with optimization. Weird.
1570 (define_expand "zero_extendhisi2_h8300"
1571 [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
1572 (set (reg:SI 0) (zero_extend:SI (reg:HI 1)))
1573 (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
1578 [(set (match_operand:SI 0 "register_operand" "=r,r")
1579 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1583 mov.w %e1,%f0\;sub.w %e0,%e0"
1584 [(set_attr "length" "2,4")
1585 (set_attr "cc" "clobber,clobber")])
1588 [(set (match_operand:SI 0 "register_operand" "=r,r")
1589 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1593 mov.w %T1,%T0\;extu.l %S0"
1594 [(set_attr "length" "2,4")
1595 (set_attr "cc" "set,set")])
1597 (define_expand "extendqihi2"
1598 [(set (match_operand:HI 0 "register_operand" "")
1599 (sign_extend:HI (match_operand:QI 1 "general_operand" "")))]
1604 [(set (match_operand:HI 0 "register_operand" "=r,r")
1605 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1608 bld #7,%s0\;subx %t0,%t0
1609 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1610 [(set_attr "length" "4,6")
1611 (set_attr "cc" "clobber,clobber")])
1614 [(set (match_operand:HI 0 "register_operand" "=r,r")
1615 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1619 mov.b %R1,%s0\;exts.w %T0"
1620 [(set_attr "length" "2,4")
1621 (set_attr "cc" "set,set")])
1623 ;; The compiler can synthesize a 300H variant of this which is
1624 ;; just as efficient as one that we'd create
1625 (define_insn "extendqisi2"
1626 [(set (match_operand:SI 0 "register_operand" "=r,r")
1627 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1630 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1631 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1632 [(set_attr "length" "8,10")
1633 (set_attr "cc" "clobber,clobber")])
1635 (define_expand "extendhisi2"
1636 [(set (match_operand:SI 0 "register_operand" "")
1637 (sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
1641 extern int optimize;
1643 && GET_CODE (operands[1]) != CONST_INT
1646 emit_insn (gen_extendhisi2_h8300 (operands[0], operands[1]));
1651 ;; I don't know why, but if I try to simplify extendhisi2 in the
1652 ;; natural way, I get about a 2X code bloat on the h8300 without
1653 ;; optimization, and a small bloat with optimization. Weird.
1654 (define_expand "extendhisi2_h8300"
1655 [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
1656 (set (reg:SI 0) (sign_extend:SI (reg:HI 1)))
1657 (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
1662 [(set (match_operand:SI 0 "register_operand" "=r,r")
1663 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1666 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1667 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1668 [(set_attr "length" "6,8")
1669 (set_attr "cc" "clobber,clobber")])
1672 [(set (match_operand:SI 0 "register_operand" "=r,r")
1673 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1677 mov.w %T1,%T0\;exts.l %S0"
1678 [(set_attr "length" "2,4")
1679 (set_attr "cc" "set,set")])
1681 ;; ----------------------------------------------------------------------
1683 ;; ----------------------------------------------------------------------
1685 ;; We make some attempt to provide real efficient shifting. One example is
1686 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1687 ;; reg and moving 0 into the former reg.
1689 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1690 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1691 ;; give the optimizer more cracks at the code. However, we wish to do things
1692 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1693 ;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
1694 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1695 ;; to detect cases it can optimize.
1697 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1698 ;; easier "do it at insn emit time" route.
1702 (define_expand "ashlqi3"
1703 [(set (match_operand:QI 0 "register_operand" "")
1704 (ashift:QI (match_operand:QI 1 "register_operand" "")
1705 (match_operand:QI 2 "nonmemory_operand" "")))]
1707 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
1709 (define_expand "ashrqi3"
1710 [(set (match_operand:QI 0 "register_operand" "")
1711 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1712 (match_operand:QI 2 "nonmemory_operand" "")))]
1714 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
1716 (define_expand "lshrqi3"
1717 [(set (match_operand:QI 0 "register_operand" "")
1718 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1719 (match_operand:QI 2 "nonmemory_operand" "")))]
1721 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
1723 ;; WARNING: The constraints on the scratch register say one is not needed
1724 ;; for constant shifts of 1,2,3,4. Emit_a_shift() must know this.
1726 (define_insn "shiftbyn_QI"
1727 [(set (match_operand:QI 0 "register_operand" "=r,r")
1728 (match_operator:QI 3 "nshift_operator"
1729 [ (match_operand:QI 1 "register_operand" "0,0")
1730 (match_operand:QI 2 "nonmemory_operand" "IKM,rn")]))
1731 (clobber (match_scratch:QI 4 "=X,&r"))]
1733 "* return emit_a_shift (insn, operands);"
1734 [(set_attr "length" "20")
1735 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1736 ;; However, for cases that loop or are done in pieces, cc does not contain
1737 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1738 (set_attr "cc" "clobber")])
1742 (define_expand "ashlhi3"
1743 [(set (match_operand:HI 0 "register_operand" "")
1744 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1745 (match_operand:QI 2 "nonmemory_operand" "")))]
1747 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
1749 (define_expand "lshrhi3"
1750 [(set (match_operand:HI 0 "register_operand" "")
1751 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1752 (match_operand:QI 2 "nonmemory_operand" "")))]
1754 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
1756 (define_expand "ashrhi3"
1757 [(set (match_operand:HI 0 "register_operand" "")
1758 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1759 (match_operand:QI 2 "nonmemory_operand" "")))]
1761 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
1763 ;; WARNING: The constraints on the scratch register say one is not needed
1764 ;; for constant shifts of 1,2,3,4. Emit_a_shift() must know this.
1766 (define_insn "shiftbyn_HI"
1767 [(set (match_operand:HI 0 "register_operand" "=r,r")
1768 (match_operator:HI 3 "nshift_operator"
1769 [ (match_operand:HI 1 "register_operand" "0,0")
1770 (match_operand:QI 2 "nonmemory_operand" "IKM,rn")]))
1771 (clobber (match_scratch:QI 4 "=X,&r"))]
1773 "* return emit_a_shift (insn, operands);"
1774 [(set_attr "length" "20")
1775 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1776 ;; However, for cases that loop or are done in pieces, cc does not contain
1777 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1778 (set_attr "cc" "clobber")])
1782 (define_expand "ashlsi3"
1783 [(set (match_operand:SI 0 "register_operand" "")
1785 (match_operand:SI 1 "general_operand" "")
1786 (match_operand:QI 2 "nonmemory_operand" "")))]
1788 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
1790 (define_expand "lshrsi3"
1791 [(set (match_operand:SI 0 "register_operand" "")
1793 (match_operand:SI 1 "general_operand" "")
1794 (match_operand:QI 2 "nonmemory_operand" "")))]
1796 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
1798 (define_expand "ashrsi3"
1799 [(set (match_operand:SI 0 "register_operand" "")
1801 (match_operand:SI 1 "general_operand" "")
1802 (match_operand:QI 2 "nonmemory_operand" "")))]
1804 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
1806 ;; WARNING: The constraints on the scratch register say one is not needed
1807 ;; for constant shifts of 1,2. Emit_a_shift() must know this.
1809 (define_insn "shiftbyn_SI"
1810 [(set (match_operand:SI 0 "register_operand" "=r,r")
1811 (match_operator:SI 3 "nshift_operator"
1812 [ (match_operand:SI 1 "register_operand" "0,0")
1813 (match_operand:QI 2 "nonmemory_operand" "IK,rn")]))
1814 (clobber (match_scratch:QI 4 "=X,&r"))]
1816 "* return emit_a_shift (insn, operands);"
1817 [(set_attr "length" "20")
1818 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1819 ;; However, for cases that loop or are done in pieces, cc does not contain
1820 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1821 (set_attr "cc" "clobber")])
1823 ;; -----------------------------------------------------------------
1825 ;; -----------------------------------------------------------------
1826 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1827 ;; instructions so let's use them as well as we can.
1829 ;; BCC and BCS patterns.
1834 (match_operator 1 "eq_operator"
1836 (match_operand:HI 2 "register_operand" "r")
1838 (match_operand:HI 3 "immediate_operand" "i"))
1840 (label_ref (match_operand 0 "" ""))
1845 /* The length of this insn includes the bld insn below. We
1846 compute the length of the branch without the bld so we
1847 can easily choose the right branch length. */
1848 int branch_length = get_attr_length (insn);
1850 if (! register_operand (operands[2], HImode))
1855 output_asm_insn(\"bld %Z3,%Y2\", operands);
1856 if (branch_length == 2)
1858 else if (branch_length == 4)
1859 return \"%d1 %l0:16\";
1861 return \"%g1 %L0\;jmp @%l0\;%L0:\";
1863 [(set_attr "type" "bcs")
1864 (set_attr "cc" "clobber")])
1869 (match_operator 1 "eq_operator"
1871 (match_operand:HI 2 "register_operand" "r")
1873 (match_operand:HI 3 "immediate_operand" "i"))
1875 (label_ref (match_operand 0 "" ""))
1880 /* The length of this insn includes the bld insn below. We
1881 compute the length of the branch without the bld so we
1882 can easily choose the right branch length. */
1883 int branch_length = get_attr_length (insn);
1885 if (! register_operand (operands[2], HImode))
1890 output_asm_insn(\"bld %Z3,%Y2\", operands);
1891 if (branch_length == 2)
1893 else if (branch_length == 4)
1894 return \"%d1 %l0:16\";
1896 return \"%g1 %L0\;jmp @%l0\;%L0:\";
1898 [(set_attr "type" "bcs")
1899 (set_attr "cc" "clobber")])
1904 (match_operator 1 "eq_operator"
1906 (match_operand:HI 2 "register_operand" "U")
1908 (match_operand:HI 3 "immediate_operand" "i"))
1911 (label_ref (match_operand 0 "" ""))))]
1915 /* The length of this insn includes the bld insn below. We
1916 compute the length of the branch without the bld so we
1917 can easily choose the right branch length. */
1918 int branch_length = get_attr_length (insn);
1920 if (! register_operand (operands[2], HImode))
1925 output_asm_insn(\"bld %Z3,%Y2\", operands);
1926 if (branch_length == 2)
1928 else if (branch_length == 4)
1929 return \"%d1 %l0:16\";
1931 return \"%g1 %L0\;jmp @%l0\;%L0:\";
1933 [(set_attr "type" "bcs")
1934 (set_attr "cc" "clobber")])
1939 (match_operator 1 "eq_operator"
1941 (match_operand:HI 2 "register_operand" "r")
1943 (match_operand:HI 3 "immediate_operand" "i"))
1946 (label_ref (match_operand 0 "" ""))))]
1950 /* The length of this insn includes the bld insn below. We
1951 compute the length of the branch without the bld so we
1952 can easily choose the right branch length. */
1953 int branch_length = get_attr_length (insn);
1955 if (! register_operand (operands[2], HImode))
1960 output_asm_insn(\"bld %Z3,%Y2\", operands);
1961 if (branch_length == 2)
1963 else if (branch_length == 4)
1964 return \"%d1 %l0:16\";
1966 return \"%g1 %L0\;jmp @%l0\;%L0:\";
1968 [(set_attr "type" "bcs")
1969 (set_attr "cc" "clobber")])
1971 ;; You'll never believe all these patterns perform one basic action --
1972 ;; load a bit from the source, optionally invert the bit, then store it
1973 ;; in the destination (which is known to be zero)..
1975 ;; Combine obviously need some work to better identify this situation and
1976 ;; canonicalize the form better.
1979 ;; Normal loads with a 16bit destination.
1981 ;; Yes, both cases are needed.
1984 [(set (match_operand:HI 0 "register_operand" "=&r")
1985 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1987 (match_operand:HI 2 "immediate_operand" "i")))]
1989 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1990 [(set_attr "cc" "clobber")
1991 (set_attr "length" "6")])
1994 [(set (match_operand:HI 0 "register_operand" "=&r")
1995 (subreg:HI (zero_extract:SI
1996 (match_operand:HI 1 "register_operand" "r")
1998 (match_operand:HI 2 "immediate_operand" "i")) 1))]
2000 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2001 [(set_attr "cc" "clobber")
2002 (set_attr "length" "6")])
2005 ;; Inverted loads with a 16bit destination.
2007 ;; Yes, all four cases are needed.
2011 [(set (match_operand:HI 0 "register_operand" "=&r")
2012 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2013 (match_operand:HI 3 "p_operand" "P"))
2015 (match_operand:HI 2 "const_int_operand" "n")))]
2016 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2017 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2018 [(set_attr "cc" "clobber")
2019 (set_attr "length" "8")])
2022 [(set (match_operand:HI 0 "register_operand" "=&r")
2025 (match_operand:HI 1 "bit_operand" "Ur")
2026 (match_operand:HI 2 "const_int_operand" "n")))
2029 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2030 [(set_attr "cc" "clobber")
2031 (set_attr "length" "8")])
2034 [(set (match_operand:HI 0 "register_operand" "=&r")
2038 (match_operand:SI 1 "register_operand" "Ur")
2039 (match_operand:SI 2 "const_int_operand" "n")) 1))
2041 "INTVAL (operands[2]) < 16"
2042 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2043 [(set_attr "cc" "clobber")
2044 (set_attr "length" "8")])
2047 [(set (match_operand:HI 0 "register_operand" "=&r")
2051 (match_operand:SI 1 "bit_operand" "Ur")
2052 (match_operand:SI 2 "const_int_operand" "n")) 0))
2054 "TARGET_H8300H && INTVAL (operands[2]) < 16"
2055 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2056 [(set_attr "cc" "clobber")
2057 (set_attr "length" "8")])
2060 ;; Normal loads with a 32bit destination.
2062 ;; Yes, all three cases are needed.
2065 [(set (match_operand:SI 0 "register_operand" "=&r")
2066 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2068 (match_operand:HI 2 "const_int_operand" "n")))]
2070 "* return output_simode_bld (0, 0, operands);"
2071 [(set_attr "cc" "clobber")
2072 (set (attr "length")
2073 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2078 [(set (match_operand:SI 0 "register_operand" "=&r")
2079 (and:SI (zero_extend:SI
2081 (match_operand:QI 1 "bit_operand" "Ur")
2082 (match_operand:QI 2 "const_int_operand" "n")))
2085 "* return output_simode_bld (0, 0, operands);"
2086 [(set_attr "cc" "clobber")
2087 (set (attr "length")
2088 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2093 [(set (match_operand:SI 0 "register_operand" "=&r")
2094 (and:SI (zero_extend:SI
2096 (match_operand:HI 1 "bit_operand" "Ur")
2097 (match_operand:HI 2 "const_int_operand" "n")))
2100 "* return output_simode_bld (0, 0, operands);"
2101 [(set_attr "cc" "clobber")
2102 (set (attr "length")
2103 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2108 ;; Inverted loads with a 32bit destination.
2110 ;; Yes, all seven cases are needed.
2113 [(set (match_operand:SI 0 "register_operand" "=&r")
2115 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
2116 (match_operand:SI 2 "p_operand" "P")))]
2118 "* return output_simode_bld (1, 1, operands);"
2119 [(set_attr "cc" "clobber")
2120 (set (attr "length")
2121 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2125 [(set (match_operand:SI 0 "register_operand" "=&r")
2128 (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
2129 (match_operand:HI 2 "const_int_operand" "n"))))
2132 "* return output_simode_bld (1, 0, operands);"
2133 [(set_attr "cc" "clobber")
2134 (set (attr "length")
2135 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2140 [(set (match_operand:SI 0 "register_operand" "=&r")
2142 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
2143 (match_operand:SI 2 "p_operand" "P")))]
2145 "* return output_simode_bld (1, 1, operands);"
2146 [(set_attr "cc" "clobber")
2147 (set (attr "length")
2148 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2152 [(set (match_operand:SI 0 "register_operand" "=&r")
2155 (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
2156 (match_operand:QI 2 "const_int_operand" "n"))))
2159 "* return output_simode_bld (1, 0, operands);"
2160 [(set_attr "cc" "clobber")
2161 (set (attr "length")
2162 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2167 [(set (match_operand:SI 0 "register_operand" "=&r")
2171 (match_operand:HI 1 "bit_operand" "Ur")
2172 (match_operand:HI 2 "const_int_operand" "n")) 0))
2175 "* return output_simode_bld (1, 0, operands);"
2176 [(set_attr "cc" "clobber")
2177 (set (attr "length")
2178 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2183 [(set (match_operand:SI 0 "register_operand" "=&r")
2187 (match_operand:QI 1 "bit_operand" "Ur")
2188 (match_operand:QI 2 "const_int_operand" "n")) 0))
2191 "* return output_simode_bld (1, 0, operands);"
2192 [(set_attr "cc" "clobber")
2193 (set (attr "length")
2194 (if_then_else (eq (symbol_ref "TARGET_H8300H") (const_int 0))
2199 [(set (match_operand:SI 0 "register_operand" "=&r")
2200 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2201 (match_operand:HI 3 "p_operand" "P"))
2203 (match_operand:HI 2 "const_int_operand" "n")))]
2204 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2205 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2206 [(set_attr "cc" "clobber")
2207 (set_attr "length" "8")])
2209 (define_expand "insv"
2210 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2211 (match_operand:HI 1 "general_operand" "")
2212 (match_operand:HI 2 "general_operand" ""))
2213 (match_operand:HI 3 "general_operand" ""))]
2217 /* We only have single bit bitfield instructions. */
2218 if (INTVAL (operands[1]) != 1)
2221 /* For now, we don't allow memory operands. */
2222 if (GET_CODE (operands[0]) == MEM
2223 || GET_CODE (operands[3]) == MEM)
2228 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2230 (match_operand:HI 1 "immediate_operand" "i"))
2231 (match_operand:HI 2 "register_operand" "r"))]
2233 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2234 [(set_attr "cc" "clobber")
2235 (set_attr "length" "4")])
2237 (define_expand "extzv"
2238 [(set (match_operand:HI 0 "register_operand" "")
2239 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2240 (match_operand:HI 2 "general_operand" "")
2241 (match_operand:HI 3 "general_operand" "")))]
2245 /* We only have single bit bitfield instructions. */
2246 if (INTVAL (operands[2]) != 1)
2249 /* For now, we don't allow memory operands. */
2250 if (GET_CODE (operands[1]) == MEM)
2254 ;; BAND, BOR, and BXOR patterns
2257 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2258 (match_operator:HI 4 "bit_operator"
2259 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2261 (match_operand:HI 2 "immediate_operand" "i"))
2262 (match_operand:HI 3 "bit_operand" "0")]))]
2264 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2265 [(set_attr "cc" "clobber")
2266 (set_attr "length" "6")])
2269 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2270 (match_operator:HI 5 "bit_operator"
2271 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2273 (match_operand:HI 2 "immediate_operand" "i"))
2274 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2276 (match_operand:HI 4 "immediate_operand" "i"))]))]
2278 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2279 [(set_attr "cc" "clobber")
2280 (set_attr "length" "6")])
2283 ;; -------------------------------------------
2285 ;; -------------------------------------------
2287 (define_expand "movstrhi"
2288 [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
2289 (mem:BLK (match_operand:BLK 1 "general_operand" "")))
2290 (use (match_operand:HI 2 "general_operand" ""))
2291 (use (match_operand:HI 3 "immediate_operand" ""))
2292 (clobber (match_dup 3))
2297 rtx src_ptr = copy_to_mode_reg (Pmode, XEXP(operands[1], 0));
2298 rtx dst_ptr = copy_to_mode_reg (Pmode, XEXP(operands[0], 0));
2300 int max = GET_CODE (operands[2]) == CONST_INT
2301 ? MIN (INTVAL (operands[2]), INTVAL (operands[3])) : 1;
2302 enum machine_mode mode = max >= 2 ? HImode : QImode;
2303 rtx tmpreg = gen_reg_rtx (mode);
2304 rtx increment = mode == QImode ? const1_rtx : const2_rtx;
2305 rtx length = operands[2];
2306 rtx label = gen_label_rtx ();
2307 rtx end_src_ptr = gen_reg_rtx (Pmode);
2309 /* emit_move_insn (length, gen_rtx(MINUS, HImode, length, increment));*/
2311 if (Pmode == HImode)
2312 emit_insn (gen_addhi3 (end_src_ptr, src_ptr, length));
2314 emit_insn (gen_addsi3 (end_src_ptr, src_ptr, length));
2317 emit_move_insn (tmpreg, gen_rtx (MEM, mode, src_ptr));
2318 emit_move_insn (gen_rtx (MEM, mode, dst_ptr), tmpreg);
2319 emit_insn (gen_rtx (SET, VOIDmode, src_ptr,
2320 gen_rtx (PLUS, Pmode, src_ptr, increment)));
2321 emit_insn (gen_rtx (SET, VOIDmode, dst_ptr,
2322 gen_rtx (PLUS, Pmode, dst_ptr, increment)));
2324 emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx,
2325 gen_rtx (COMPARE, Pmode, src_ptr, end_src_ptr)));
2326 emit_jump_insn (gen_bne (label));
2331 ;; ----------------------------------------------
2332 ;; Peepholes go at the end.
2333 ;; ----------------------------------------------
2335 ;; Notice when two byte moves in a row could be a word move.
2338 [(set (match_operand:QI 0 "register_operand" "=r")
2339 (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r")
2340 (match_operand:HI 2 "immediate_operand" "n"))))
2341 (set (match_operand:QI 3 "register_operand" "=r")
2342 (mem:QI (plus:HI (match_dup 1)
2343 (match_operand:HI 4 "immediate_operand" "n"))))]
2344 "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
2345 "mov.w @(%u4,%T1),%T0"
2346 [(set_attr "length" "6")
2347 (set_attr "cc" "set")])
2350 [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r")
2351 (match_operand:HI 2 "immediate_operand" "n")))
2352 (match_operand:QI 0 "register_operand" "r"))
2353 (set (mem:QI (plus:HI (match_dup 1)
2354 (match_operand:HI 4 "immediate_operand" "n")))
2355 (match_operand:QI 3 "register_operand" "r"))]
2356 "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
2357 "mov.w %T0,@(%u4,%T1)"
2358 [(set_attr "length" "6")
2359 (set_attr "cc" "set")])
2361 ;; Notice a move which could be post incremented.
2364 [(set (match_operand:QI 0 "register_operand" "")
2365 (mem:QI (match_operand:HI 1 "register_operand" "")))
2366 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
2367 "REGNO(operands[1]) != REGNO(operands[0])"
2369 [(set_attr "length" "2")
2370 (set_attr "cc" "set")])
2373 [(set (match_operand:HI 0 "register_operand" "")
2374 (mem:HI (match_operand:HI 1 "register_operand" "")))
2375 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))]
2376 "REGNO(operands[1]) != REGNO(operands[0])"
2378 [(set_attr "length" "2")
2379 (set_attr "cc" "set")])
2381 ;; Notice a move which could be predecremented.
2384 [(set (match_operand:HI 1 "register_operand" "")
2385 (plus:HI (match_dup 1) (const_int -1)))
2386 (set (mem:QI (match_dup 1))
2387 (match_operand:QI 0 "register_operand" ""))]
2388 "REGNO(operands[1]) != REGNO(operands[0])"
2390 [(set_attr "length" "2")
2391 (set_attr "cc" "set")])
2394 [(set (match_operand:HI 1 "register_operand" "")
2395 (plus:HI (match_dup 1) (const_int -1)))
2396 (set (mem:HI (match_dup 1))
2397 (match_operand:HI 0 "register_operand" ""))]
2398 "REGNO(operands[1]) != REGNO(operands[0])"
2400 [(set_attr "length" "2")
2401 (set_attr "cc" "set")])
2403 (define_insn "fancybset1"
2404 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2406 (ashift:HI (const_int 1)
2407 (subreg:QI (match_operand:HI 1 "register_operand" "ri") 0)) 0)
2411 [(set_attr "length" "2")
2412 (set_attr "cc" "clobber")])
2414 (define_insn "fancybset"
2415 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2417 (ashift:HI (const_int 1)
2418 (match_operand:HI 1 "nonmemory_operand" "ri") ) 0)
2419 (match_operand:QI 2 "general_operand_src" "Ur>")))]
2421 "mov.b %R2,%R0\;bset %X1,%R0"
2422 [(set_attr "length" "4")
2423 (set_attr "cc" "clobber")])
2425 (define_insn "fancybclr4"
2426 [(set (match_operand:QI 0 "general_operand" "=Ur,Ur")
2429 (rotate:HI (const_int -2)
2430 (match_operand:HI 2 "nonmemory_operand" "ri,ri") ) 0)
2431 (match_operand:QI 1 "general_operand" "0,Ur")))
2432 (clobber (match_scratch:HI 3 "=X,&r"))]
2436 mov.b %R1,%X3\;mov.b %3,%0\;bclr %X2,%R0; l3"
2437 [(set_attr "length" "8")
2438 (set_attr "cc" "clobber")])
2440 (define_insn "fancybclr5"
2441 [(set (match_operand:QI 0 "general_operand" "=Ur,Ur")
2444 (rotate:HI (const_int -2)
2445 (match_operand:QI 2 "nonmemory_operand" "ri,ri")) 0)
2446 (match_operand:QI 1 "general_operand" "0,Ur")))
2447 (clobber (match_scratch:HI 3 "=X,&r"))]
2451 mov.b %R1,%X3\;mov.b %3,%0\;bclr %X2,%R0;l2"
2452 [(set_attr "length" "8")
2453 (set_attr "cc" "clobber")])
2455 (define_insn "fancybclr2"
2456 [(set (match_operand:QI 0 "general_operand" "=U,r")
2459 (rotate:HI (const_int -2)
2460 (match_operand:HI 2 "nonmemory_operand" "ri,ri") ) 0)
2461 (match_operand:QI 1 "general_operand" "0,0")))]
2464 [(set_attr "length" "2")
2465 (set_attr "cc" "clobber")])
2467 (define_insn "fancybclr3"
2468 [(set (match_operand:QI 0 "general_operand" "=U,r")
2471 (rotate:HI (const_int -2)
2472 (match_operand:QI 2 "nonmemory_operand" "ri,ri")) 0)
2473 (match_operand:QI 1 "general_operand" "0,0")))]
2476 [(set_attr "length" "2")
2477 (set_attr "cc" "clobber")])
2479 (define_insn "fancybsetp3"
2480 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2481 (ior:QI (subreg:QI (ashift:HI (const_int 1)
2482 (match_operand:QI 1 "register_operand" "r")) 0)
2483 (match_operand:QI 2 "bit_operand" "0")))]
2486 [(set_attr "length" "2")
2487 (set_attr "cc" "clobber")])
2489 (define_insn "fancybsetp2"
2490 [(set (match_operand:QI 0 "general_operand" "=r,U")
2491 (ior:QI (subreg:QI (ashift:HI (const_int 1)
2492 (match_operand:QI 1 "register_operand" "r,r")) 0)
2493 (match_operand:QI 2 "general_operand_src" "U,r>")))]
2495 "mov.b %R2,%R0\;bset %X1,%R0"
2496 [(set_attr "length" "4")
2497 (set_attr "cc" "clobber")])
2499 (define_insn "fancybnot"
2500 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2501 (xor:QI (subreg:QI (ashift:HI (const_int 1)
2502 (match_operand:QI 1 "register_operand" "r")) 0)
2503 (match_operand:QI 2 "bit_operand" "0")))]
2507 [(set_attr "length" "2")
2508 (set_attr "cc" "clobber")])
2511 [(set (zero_extract:QI (match_operand:HI 0 "register_operand" "=r,r")
2513 (match_operand 1 "immediate_operand" "n,n"))
2514 (and:QI (not:QI (match_operand:QI 2 "bit_operand" "r,U"))
2517 "bld #0,%R2\;bist %1,%0"
2518 [(set_attr "length" "4")
2519 (set_attr "cc" "clobber")])
2522 [(set (match_operand:QI 0 "register_operand" "=r")
2523 (and:QI (not:QI (match_operand:QI 1 "register_operand" "0"))
2524 (match_operand:QI 2 "nonmemory_operand" "rJ")))]
2526 "not.b %X0\;and.b %X2,%X0"
2527 [(set_attr "length" "4")
2528 (set_attr "cc" "clobber")])
2531 [(set (match_operand:HI 0 "register_operand" "=r")
2532 (and:HI (not:HI (match_operand:HI 1 "register_operand" "0"))
2533 (match_operand:HI 2 "nonmemory_operand" "rJ")))]
2535 "not.w %T0\;and.w %T2,%T0"
2536 [(set_attr "length" "4")
2537 (set_attr "cc" "clobber")])
2540 [(set (match_operand:SI 0 "register_operand" "=r")
2541 (and:SI (not:SI (match_operand:SI 1 "register_operand" "0"))
2542 (match_operand:QI 2 "nonmemory_operand" "rJ")))]
2544 "not.l %S0\;and.l %S2,%S0"
2545 [(set_attr "length" "4")
2546 (set_attr "cc" "clobber")])