1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8/S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have a insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
53 (define_attr "cpu" "h8300,h8300h"
54 (const (symbol_ref "cpu_type")))
56 (define_attr "type" "branch,arith"
57 (const_string "arith"))
59 ;; The size of instructions in bytes.
61 (define_attr "length" ""
62 (cond [(eq_attr "type" "branch")
63 (if_then_else (and (ge (minus (pc) (match_dup 0))
65 (le (minus (pc) (match_dup 0))
68 (if_then_else (and (eq_attr "cpu" "h8300h")
69 (and (ge (minus (pc) (match_dup 0))
71 (le (minus (pc) (match_dup 0))
77 ;; The necessity of instruction length adjustment.
79 (define_attr "adjust_length" "yes,no"
80 (cond [(eq_attr "type" "branch") (const_string "no")]
81 (const_string "yes")))
83 ;; Condition code settings.
85 ;; none - insn does not affect cc
86 ;; none_0hit - insn does not affect cc but it does modify operand 0
87 ;; This attribute is used to keep track of when operand 0 changes.
88 ;; See the description of NOTICE_UPDATE_CC for more info.
89 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
90 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
91 ;; compare - compare instruction
92 ;; clobber - value of cc is unknown
94 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
95 (const_string "clobber"))
97 ;; ----------------------------------------------------------------------
99 ;; ----------------------------------------------------------------------
103 (define_insn "pushqi1_h8300"
104 [(parallel [(set (reg:HI 7)
105 (plus:HI (reg:HI 7) (const_int -2)))
106 (set (mem:QI (plus:HI (reg:HI 7) (const_int -1)))
107 (match_operand:QI 0 "register_operand" "r"))])]
110 [(set_attr "length" "2")
111 (set_attr "cc" "clobber")])
113 (define_insn "pushqi1_h8300hs"
114 [(parallel [(set (reg:SI 7)
115 (plus:SI (reg:SI 7) (const_int -4)))
116 (set (mem:QI (plus:SI (reg:SI 7) (const_int -3)))
117 (match_operand:QI 0 "register_operand" "r"))])]
118 "TARGET_H8300H || TARGET_H8300S"
120 [(set_attr "length" "4")
121 (set_attr "cc" "clobber")])
123 (define_expand "pushqi1"
124 [(use (match_operand:QI 0 "register_operand" ""))]
129 emit_insn (gen_pushqi1_h8300 (operands[0]));
131 emit_insn (gen_pushqi1_h8300hs (operands[0]));
136 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
137 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
139 && (register_operand (operands[0], QImode)
140 || register_operand (operands[1], QImode))"
148 [(set_attr "length" "2,2,2,2,4,4")
149 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
152 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
153 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
154 "(TARGET_H8300H || TARGET_H8300S)
155 && (register_operand (operands[0], QImode)
156 || register_operand (operands[1], QImode))"
164 [(set_attr "length" "2,2,2,2,8,8")
165 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
167 (define_expand "movqi"
168 [(set (match_operand:QI 0 "general_operand_dst" "")
169 (match_operand:QI 1 "general_operand_src" ""))]
173 /* One of the ops has to be in a register. */
174 if (!register_operand (operand0, QImode)
175 && !register_operand (operand1, QImode))
177 operands[1] = copy_to_mode_reg (QImode, operand1);
181 (define_insn "movstrictqi"
182 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
183 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
190 [(set_attr_alternative "length"
191 [(const_int 2) (const_int 2) (const_int 2)
192 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
193 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
197 (define_expand "pushhi1_h8300"
198 [(set (mem:QI (pre_dec:HI (reg:HI 7)))
199 (match_operand:QI 0 "register_operand" ""))]
203 (define_insn "pushhi1_h8300hs"
204 [(parallel [(set (reg:SI 7)
205 (plus:SI (reg:SI 7) (const_int -4)))
206 (set (mem:HI (plus:SI (reg:SI 7) (const_int -2)))
207 (match_operand:HI 0 "register_operand" "r"))])]
208 "TARGET_H8300H || TARGET_H8300S"
210 [(set_attr "length" "4")
211 (set_attr "cc" "clobber")])
213 (define_expand "pushhi1"
214 [(use (match_operand:QI 0 "register_operand" ""))]
219 emit_insn (gen_pushhi1_h8300 (operands[0]));
221 emit_insn (gen_pushhi1_h8300hs (operands[0]));
226 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
227 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
229 && (register_operand (operands[0], HImode)
230 || register_operand (operands[1], HImode))
231 && !(GET_CODE (operands[0]) == MEM
232 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
233 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
234 && GET_CODE (operands[1]) == REG
235 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
243 [(set_attr "length" "2,2,2,4,4,4")
244 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
247 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
248 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
249 "(TARGET_H8300H || TARGET_H8300S)
250 && (register_operand (operands[0], HImode)
251 || register_operand (operands[1], HImode))"
259 [(set_attr "length" "2,2,2,4,8,8")
260 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
262 (define_expand "movhi"
263 [(set (match_operand:HI 0 "general_operand_dst" "")
264 (match_operand:HI 1 "general_operand_src" ""))]
268 /* One of the ops has to be in a register. */
269 if (!register_operand (operand1, HImode)
270 && !register_operand (operand0, HImode))
272 operands[1] = copy_to_mode_reg (HImode, operand1);
276 (define_insn "movstricthi"
277 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
278 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
285 [(set_attr_alternative "length"
286 [(const_int 2) (const_int 2) (const_int 4)
287 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
288 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
292 (define_expand "movsi"
293 [(set (match_operand:SI 0 "general_operand_dst" "")
294 (match_operand:SI 1 "general_operand_src" ""))]
300 if (do_movsi (operands))
305 /* One of the ops has to be in a register. */
306 if (!register_operand (operand1, SImode)
307 && !register_operand (operand0, SImode))
309 operands[1] = copy_to_mode_reg (SImode, operand1);
314 (define_expand "movsf"
315 [(set (match_operand:SF 0 "general_operand_dst" "")
316 (match_operand:SF 1 "general_operand_src" ""))]
322 if (do_movsi (operands))
327 /* One of the ops has to be in a register. */
328 if (!register_operand (operand1, SFmode)
329 && !register_operand (operand0, SFmode))
331 operands[1] = copy_to_mode_reg (SFmode, operand1);
336 (define_insn "movsi_h8300"
337 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
338 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
340 && (register_operand (operands[0], SImode)
341 || register_operand (operands[1], SImode))"
345 switch (which_alternative)
348 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
350 if (REGNO (operands[0]) < REGNO (operands[1]))
351 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
353 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
355 /* Make sure we don't trample the register we index with. */
356 if (GET_CODE (operands[1]) == MEM)
358 rtx inside = XEXP (operands[1], 0);
363 else if (GET_CODE (inside) == PLUS)
365 rtx lhs = XEXP (inside, 0);
366 rtx rhs = XEXP (inside, 1);
367 if (REG_P (lhs)) rn = REGNO (lhs);
368 if (REG_P (rhs)) rn = REGNO (rhs);
371 if (rn == REGNO (operands[0]))
373 /* Move the second word first. */
374 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
378 /* See if either half is zero. If so, use sub.w to clear
380 if (GET_CODE (operands[1]) == CONST_INT)
382 if ((INTVAL (operands[1]) & 0xffff) == 0)
383 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
384 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
385 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
387 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
390 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
392 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
394 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
399 [(set_attr "length" "4,4,8,8,4,4")
400 (set_attr "cc" "clobber")])
402 (define_insn "movsf_h8300"
403 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
404 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
406 && (register_operand (operands[0], SFmode)
407 || register_operand (operands[1], SFmode))"
410 /* Copy of the movsi stuff. */
412 switch (which_alternative)
415 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
417 if (REGNO (operands[0]) < REGNO (operands[1]))
418 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
420 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
422 /* Make sure we don't trample the register we index with. */
423 if (GET_CODE (operands[1]) == MEM)
425 rtx inside = XEXP (operands[1], 0);
430 else if (GET_CODE (inside) == PLUS)
432 rtx lhs = XEXP (inside, 0);
433 rtx rhs = XEXP (inside, 1);
434 if (REG_P (lhs)) rn = REGNO (lhs);
435 if (REG_P (rhs)) rn = REGNO (rhs);
438 if (rn == REGNO (operands[0]))
439 /* Move the second word first. */
440 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
442 /* Move the first word first. */
443 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
446 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
448 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
450 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
455 [(set_attr "length" "4,4,8,8,4,4")
456 (set_attr "cc" "clobber")])
458 (define_insn "movsi_h8300hs"
459 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
460 (match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
461 "(TARGET_H8300S || TARGET_H8300H)
462 && (register_operand (operands[0], SImode)
463 || register_operand (operands[1], SImode))
464 && !(GET_CODE (operands[0]) == MEM
465 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
466 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
467 && GET_CODE (operands[1]) == REG
468 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
471 switch (which_alternative)
474 return \"sub.l %S0,%S0\";
478 return \"clrmac\;ldmac %1,macl\";
480 return \"stmac macl,%0\";
482 if (GET_CODE (operands[1]) == CONST_INT)
484 int val = INTVAL (operands[1]);
486 /* Look for constants which can be made by adding an 8-bit
487 number to zero in one of the two low bytes. */
488 if (val == (val & 0xff))
490 operands[1] = GEN_INT ((char) val & 0xff);
491 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
494 if (val == (val & 0xff00))
496 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
497 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
500 /* Look for constants that can be obtained by subs, inc, and
502 switch (val & 0xffffffff)
505 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
507 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
509 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
512 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
514 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
517 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
519 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
522 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
524 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
528 return \"mov.l %S1,%S0\";
530 [(set_attr "length" "2,2,10,10,10,4,4,2,6,4")
531 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
533 (define_insn "movsf_h8300h"
534 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
535 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
536 "(TARGET_H8300H || TARGET_H8300S)
537 && (register_operand (operands[0], SFmode)
538 || register_operand (operands[1], SFmode))"
546 [(set_attr "length" "2,2,10,10,4,4")
547 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
549 ;; ----------------------------------------------------------------------
551 ;; ----------------------------------------------------------------------
554 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
556 (match_operand 1 "const_int_operand" "n,n")))]
559 [(set_attr "length" "2,4")
560 (set_attr "cc" "set_zn,set_zn")])
563 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
565 (match_operand 1 "const_int_operand" "n")))]
568 [(set_attr "length" "2")
569 (set_attr "cc" "set_zn")])
572 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
574 (match_operand 1 "const_int_operand" "n,n")))]
575 "TARGET_H8300H || TARGET_H8300S"
577 [(set_attr "length" "2,8")
578 (set_attr "cc" "set_zn,set_zn")])
581 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
583 (match_operand 1 "const_int_operand" "n")))]
584 "(TARGET_H8300H || TARGET_H8300S)
585 && INTVAL (operands[1]) <= 15"
587 [(set_attr "length" "2")
588 (set_attr "cc" "set_zn")])
591 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
594 [(set_attr "length" "2")
595 (set_attr "cc" "set_znv")])
598 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
601 [(set_attr "length" "2")
602 (set_attr "cc" "set_znv")])
605 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
606 "TARGET_H8300H || TARGET_H8300S"
608 [(set_attr "length" "2")
609 (set_attr "cc" "set_znv")])
613 (compare:QI (match_operand:QI 0 "register_operand" "r")
614 (match_operand:QI 1 "nonmemory_operand" "rn")))]
617 [(set_attr "length" "2")
618 (set_attr "cc" "compare")])
620 (define_expand "cmphi"
622 (compare:HI (match_operand:HI 0 "register_operand" "")
623 (match_operand:HI 1 "nonmemory_operand" "")))]
627 /* Force operand1 into a register if we're compiling
629 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
630 operands[1] = force_reg (HImode, operands[1]);
635 (compare:HI (match_operand:HI 0 "register_operand" "r")
636 (match_operand:HI 1 "register_operand" "r")))]
639 [(set_attr "length" "2")
640 (set_attr "cc" "compare")])
644 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
645 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
646 "TARGET_H8300H || TARGET_H8300S"
648 [(set_attr "length" "2,4")
649 (set_attr "cc" "compare,compare")])
653 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
654 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
655 "TARGET_H8300H || TARGET_H8300S"
657 [(set_attr "length" "2,6")
658 (set_attr "cc" "compare,compare")])
660 ;; ----------------------------------------------------------------------
662 ;; ----------------------------------------------------------------------
664 (define_insn "addqi3"
665 [(set (match_operand:QI 0 "register_operand" "=r")
666 (plus:QI (match_operand:QI 1 "register_operand" "%0")
667 (match_operand:QI 2 "nonmemory_operand" "rn")))]
670 [(set_attr "length" "2")
671 (set_attr "cc" "set_zn")])
673 (define_expand "addhi3"
674 [(set (match_operand:HI 0 "register_operand" "")
675 (plus:HI (match_operand:HI 1 "register_operand" "")
676 (match_operand:HI 2 "nonmemory_operand" "")))]
681 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
682 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
683 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
688 add.b %s2,%s0\;addx %t2,%t0
690 mov.w %T1,%T0\;add.w %T2,%T0"
691 [(set_attr "length" "2,2,4,2,6")
692 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
695 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
696 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
697 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
698 "TARGET_H8300H || TARGET_H8300S"
704 [(set_attr "length" "2,2,4,2")
705 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
708 [(set (match_operand:HI 0 "register_operand" "")
709 (plus:HI (match_dup 0)
710 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
713 "split_adds_subs (HImode, operands); DONE;")
715 (define_expand "addsi3"
716 [(set (match_operand:SI 0 "register_operand" "")
717 (plus:SI (match_operand:SI 1 "register_operand" "")
718 (match_operand:SI 2 "nonmemory_operand" "")))]
722 (define_insn "addsi_h8300"
723 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
724 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
725 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
728 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
729 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
730 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
731 [(set_attr "length" "8,6,10")
732 (set_attr "cc" "clobber")])
734 (define_insn "addsi_h8300h"
735 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
736 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
737 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
738 "TARGET_H8300H || TARGET_H8300S"
744 [(set_attr "length" "2,2,6,2")
745 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
748 [(set (match_operand:SI 0 "register_operand" "")
749 (plus:SI (match_dup 0)
750 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
751 "TARGET_H8300H || TARGET_H8300S"
753 "split_adds_subs (SImode, operands); DONE;")
755 ;; ----------------------------------------------------------------------
756 ;; SUBTRACT INSTRUCTIONS
757 ;; ----------------------------------------------------------------------
759 (define_insn "subqi3"
760 [(set (match_operand:QI 0 "register_operand" "=r,r")
761 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
762 (match_operand:QI 2 "nonmemory_operand" "r,n")))]
767 [(set_attr "length" "2")
768 (set_attr "cc" "set_zn")])
770 (define_expand "subhi3"
771 [(set (match_operand:HI 0 "register_operand" "")
772 (minus:HI (match_operand:HI 1 "general_operand" "")
773 (match_operand:HI 2 "nonmemory_operand" "")))]
778 [(set (match_operand:HI 0 "register_operand" "=r,&r")
779 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
780 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
784 add.b %E2,%s0\;addx %F2,%t0"
785 [(set_attr "length" "2,4")
786 (set_attr "cc" "set_zn,clobber")])
789 [(set (match_operand:HI 0 "register_operand" "=r,&r")
790 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
791 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
792 "TARGET_H8300H || TARGET_H8300S"
796 [(set_attr "length" "2,4")
797 (set_attr "cc" "set_zn,set_zn")])
799 (define_expand "subsi3"
800 [(set (match_operand:SI 0 "register_operand" "")
801 (minus:SI (match_operand:SI 1 "register_operand" "")
802 (match_operand:SI 2 "nonmemory_operand" "")))]
806 (define_insn "subsi3_h8300"
807 [(set (match_operand:SI 0 "register_operand" "=r")
808 (minus:SI (match_operand:SI 1 "register_operand" "0")
809 (match_operand:SI 2 "register_operand" "r")))]
811 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
812 [(set_attr "length" "6")
813 (set_attr "cc" "clobber")])
815 (define_insn "subsi3_h8300h"
816 [(set (match_operand:SI 0 "register_operand" "=r,r")
817 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
818 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
819 "TARGET_H8300H || TARGET_H8300S"
823 [(set_attr "length" "2,6")
824 (set_attr "cc" "set_zn,set_zn")])
826 ;; ----------------------------------------------------------------------
827 ;; MULTIPLY INSTRUCTIONS
828 ;; ----------------------------------------------------------------------
830 ;; Note that the H8/300 can only handle umulqihi3.
832 (define_insn "mulqihi3"
833 [(set (match_operand:HI 0 "register_operand" "=r")
834 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
835 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
836 "TARGET_H8300H || TARGET_H8300S"
838 [(set_attr "length" "4")
839 (set_attr "cc" "set_zn")])
841 (define_insn "mulhisi3"
842 [(set (match_operand:SI 0 "register_operand" "=r")
843 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
844 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
845 "TARGET_H8300H || TARGET_H8300S"
847 [(set_attr "length" "4")
848 (set_attr "cc" "set_zn")])
850 (define_insn "umulqihi3"
851 [(set (match_operand:HI 0 "register_operand" "=r")
852 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
853 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
856 [(set_attr "length" "2")
857 (set_attr "cc" "none_0hit")])
859 (define_insn "umulhisi3"
860 [(set (match_operand:SI 0 "register_operand" "=r")
861 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
862 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
863 "TARGET_H8300H || TARGET_H8300S"
865 [(set_attr "length" "2")
866 (set_attr "cc" "none_0hit")])
868 ;; This is a "bridge" instruction. Combine can't cram enough insns
869 ;; together to crate a MAC instruction directly, but it can create
870 ;; this instruction, which then allows combine to create the real
873 ;; Unfortunately, if combine doesn't create a MAC instruction, this
874 ;; insn must generate reasonably correct code. Egad.
876 [(set (match_operand:SI 0 "register_operand" "=a")
879 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
881 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
883 "clrmac\;mac @%2+,@%1+"
884 [(set_attr "length" "6")
885 (set_attr "cc" "none_0hit")])
888 [(set (match_operand:SI 0 "register_operand" "=a")
890 (sign_extend:SI (mem:HI
891 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
892 (sign_extend:SI (mem:HI
893 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
894 (match_operand:SI 3 "register_operand" "0")))]
897 [(set_attr "length" "4")
898 (set_attr "cc" "none_0hit")])
900 ;; ----------------------------------------------------------------------
901 ;; DIVIDE/MOD INSTRUCTIONS
902 ;; ----------------------------------------------------------------------
904 (define_insn "udivmodqi4"
905 [(set (match_operand:QI 0 "register_operand" "=r")
908 (match_operand:HI 1 "general_operand" "0")
909 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
910 (set (match_operand:QI 3 "register_operand" "=r")
914 (zero_extend:HI (match_dup 2)))))]
915 "TARGET_H8300H || TARGET_H8300S"
918 if (find_reg_note (insn, REG_UNUSED, operands[3]))
919 return \"divxu.b\\t%X2,%T0\";
921 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
923 [(set_attr "length" "4")
924 (set_attr "cc" "clobber")])
926 (define_insn "divmodqi4"
927 [(set (match_operand:QI 0 "register_operand" "=r")
930 (match_operand:HI 1 "general_operand" "0")
931 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
932 (set (match_operand:QI 3 "register_operand" "=r")
936 (sign_extend:HI (match_dup 2)))))]
937 "TARGET_H8300H || TARGET_H8300S"
940 if (find_reg_note (insn, REG_UNUSED, operands[3]))
941 return \"divxs.b\\t%X2,%T0\";
943 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
945 [(set_attr "length" "6")
946 (set_attr "cc" "clobber")])
948 (define_insn "udivmodhi4"
949 [(set (match_operand:HI 0 "register_operand" "=r")
952 (match_operand:SI 1 "general_operand" "0")
953 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
954 (set (match_operand:HI 3 "register_operand" "=r")
958 (zero_extend:SI (match_dup 2)))))]
959 "TARGET_H8300H || TARGET_H8300S"
962 if (find_reg_note (insn, REG_UNUSED, operands[3]))
963 return \"divxu.w\\t%T2,%S0\";
965 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
967 [(set_attr "length" "4")
968 (set_attr "cc" "clobber")])
970 (define_insn "divmodhi4"
971 [(set (match_operand:HI 0 "register_operand" "=r")
974 (match_operand:SI 1 "general_operand" "0")
975 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
976 (set (match_operand:HI 3 "register_operand" "=r")
980 (sign_extend:SI (match_dup 2)))))]
981 "TARGET_H8300H || TARGET_H8300S"
984 if (find_reg_note (insn, REG_UNUSED, operands[3]))
985 return \"divxs.w\\t%T2,%S0\";
987 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
989 [(set_attr "length" "6")
990 (set_attr "cc" "clobber")])
992 ;; ----------------------------------------------------------------------
994 ;; ----------------------------------------------------------------------
997 [(set (match_operand:QI 0 "bit_operand" "=r,U")
998 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
999 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1000 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
1004 [(set_attr "length" "2,8")
1005 (set_attr "adjust_length" "no")
1006 (set_attr "cc" "set_znv,none_0hit")])
1008 (define_expand "andqi3"
1009 [(set (match_operand:QI 0 "bit_operand" "")
1010 (and:QI (match_operand:QI 1 "bit_operand" "")
1011 (match_operand:QI 2 "nonmemory_operand" "")))]
1015 if (fix_bit_operand (operands, 'O', AND))
1019 (define_expand "andhi3"
1020 [(set (match_operand:HI 0 "register_operand" "")
1021 (and:HI (match_operand:HI 1 "register_operand" "")
1022 (match_operand:HI 2 "nonmemory_operand" "")))]
1027 [(set (match_operand:HI 0 "register_operand" "=r")
1028 (and:HI (match_operand:HI 1 "register_operand" "%0")
1029 (match_operand:HI 2 "nonmemory_operand" "rn")))]
1031 "* return output_logical_op (HImode, AND, operands);"
1032 [(set_attr "length" "4")
1033 (set_attr "cc" "clobber")])
1036 [(set (match_operand:HI 0 "register_operand" "=r,r")
1037 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
1038 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
1039 "TARGET_H8300H || TARGET_H8300S"
1040 "* return output_logical_op (HImode, AND, operands);"
1041 [(set_attr "length" "2,4")
1042 (set_attr "cc" "set_znv,clobber")])
1044 (define_insn "*andorhi3"
1045 [(set (match_operand:HI 0 "register_operand" "=r")
1046 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1047 (match_operand:HI 3 "const_int_operand" "n"))
1048 (match_operand:HI 1 "register_operand" "0")))]
1049 "exact_log2 (INTVAL (operands[3]) & 0xffff) != -1"
1052 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1053 if (INTVAL (operands[3]) > 128)
1055 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1056 return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
1058 return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
1060 [(set_attr "length" "4")
1061 (set_attr "cc" "clobber")])
1063 (define_expand "andsi3"
1064 [(set (match_operand:SI 0 "register_operand" "")
1065 (and:SI (match_operand:SI 1 "register_operand" "")
1066 (match_operand:SI 2 "nonmemory_operand" "")))]
1071 [(set (match_operand:SI 0 "register_operand" "=r")
1072 (and:SI (match_operand:SI 1 "register_operand" "%0")
1073 (match_operand:SI 2 "nonmemory_operand" "rn")))]
1075 "* return output_logical_op (SImode, AND, operands);"
1076 [(set_attr "length" "8")
1077 (set_attr "cc" "clobber")])
1080 [(set (match_operand:SI 0 "register_operand" "=r,r")
1081 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1082 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1083 "TARGET_H8300H || TARGET_H8300S"
1084 "* return output_logical_op (SImode, AND, operands);"
1085 [(set_attr "length" "4,6")
1086 (set_attr "cc" "set_znv,clobber")])
1088 ;; ----------------------------------------------------------------------
1090 ;; ----------------------------------------------------------------------
1093 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1094 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1095 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1096 "register_operand (operands[0], QImode)
1097 || (GET_CODE (operands[2]) == CONST_INT
1098 && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
1101 switch (which_alternative)
1104 return \"or\t%X2,%X0\";
1106 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1107 return \"bset\t%V2,%R0\";
1112 [(set_attr "length" "2,8")
1113 (set_attr "adjust_length" "no")
1114 (set_attr "cc" "set_znv,none_0hit")])
1116 (define_expand "iorqi3"
1117 [(set (match_operand:QI 0 "bit_operand" "")
1118 (ior:QI (match_operand:QI 1 "bit_operand" "")
1119 (match_operand:QI 2 "nonmemory_operand" "")))]
1123 if (fix_bit_operand (operands, 'P', IOR))
1127 (define_expand "iorhi3"
1128 [(set (match_operand:HI 0 "general_operand" "")
1129 (ior:HI (match_operand:HI 1 "general_operand" "")
1130 (match_operand:HI 2 "general_operand" "")))]
1135 [(set (match_operand:HI 0 "general_operand" "=r,r")
1136 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1137 (match_operand:HI 2 "general_operand" "J,rn")))]
1139 "* return output_logical_op (HImode, IOR, operands);"
1140 [(set_attr "length" "2,4")
1141 (set_attr "cc" "clobber,clobber")])
1144 [(set (match_operand:HI 0 "general_operand" "=r,r,r")
1145 (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0")
1146 (match_operand:HI 2 "general_operand" "J,r,n")))]
1147 "TARGET_H8300H || TARGET_H8300S"
1148 "* return output_logical_op (HImode, IOR, operands);"
1149 [(set_attr "length" "2,2,4")
1150 (set_attr "cc" "clobber,set_znv,clobber")])
1152 (define_expand "iorsi3"
1153 [(set (match_operand:SI 0 "register_operand" "")
1154 (ior:SI (match_operand:SI 1 "register_operand" "")
1155 (match_operand:SI 2 "nonmemory_operand" "")))]
1160 [(set (match_operand:SI 0 "register_operand" "=r,r")
1161 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1162 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1164 "* return output_logical_op (SImode, IOR, operands);"
1165 [(set_attr "length" "2,8")
1166 (set_attr "cc" "clobber,clobber")])
1169 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1170 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0")
1171 (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
1172 "TARGET_H8300H || TARGET_H8300S"
1173 "* return output_logical_op (SImode, IOR, operands);"
1174 [(set_attr "length" "2,4,6")
1175 (set_attr "cc" "clobber,set_znv,clobber")])
1177 ;; ----------------------------------------------------------------------
1179 ;; ----------------------------------------------------------------------
1182 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1183 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1184 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1185 "register_operand (operands[0], QImode)
1186 || (GET_CODE (operands[2]) == CONST_INT
1187 && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
1190 switch (which_alternative)
1193 return \"xor\t%X2,%X0\";
1195 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1196 return \"bnot\t%V2,%R0\";
1201 [(set_attr "length" "2,8")
1202 (set_attr "adjust_length" "no")
1203 (set_attr "cc" "set_znv,none_0hit")])
1205 (define_expand "xorqi3"
1206 [(set (match_operand:QI 0 "bit_operand" "")
1207 (xor:QI (match_operand:QI 1 "bit_operand" "")
1208 (match_operand:QI 2 "nonmemory_operand" "")))]
1212 if (fix_bit_operand (operands, 'O', XOR))
1216 (define_expand "xorhi3"
1217 [(set (match_operand:HI 0 "register_operand" "")
1218 (xor:HI (match_operand:HI 1 "general_operand" "")
1219 (match_operand:HI 2 "nonmemory_operand" "")))]
1224 [(set (match_operand:HI 0 "register_operand" "=r,r")
1225 (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1226 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
1228 "* return output_logical_op (HImode, XOR, operands);"
1229 [(set_attr "length" "2,4")
1230 (set_attr "cc" "clobber,clobber")])
1233 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1234 (xor:HI (match_operand:HI 1 "general_operand" "%0,0,0")
1235 (match_operand:HI 2 "nonmemory_operand" "J,r,n")))]
1236 "TARGET_H8300H || TARGET_H8300S"
1237 "* return output_logical_op (HImode, XOR, operands);"
1238 [(set_attr "length" "2,2,4")
1239 (set_attr "cc" "clobber,set_znv,clobber")])
1241 (define_expand "xorsi3"
1242 [(set (match_operand:SI 0 "register_operand" "")
1243 (xor:SI (match_operand:SI 1 "register_operand" "")
1244 (match_operand:SI 2 "nonmemory_operand" "")))]
1249 [(set (match_operand:SI 0 "register_operand" "=r,r")
1250 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
1251 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1253 "* return output_logical_op (SImode, XOR, operands);"
1254 [(set_attr "length" "2,8")
1255 (set_attr "cc" "clobber,clobber")])
1258 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1259 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0")
1260 (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
1261 "TARGET_H8300H || TARGET_H8300S"
1262 "* return output_logical_op (SImode, XOR, operands);"
1263 [(set_attr "length" "2,4,6")
1264 (set_attr "cc" "clobber,set_znv,clobber")])
1266 ;; ----------------------------------------------------------------------
1267 ;; NEGATION INSTRUCTIONS
1268 ;; ----------------------------------------------------------------------
1270 (define_insn "negqi2"
1271 [(set (match_operand:QI 0 "register_operand" "=r")
1272 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1275 [(set_attr "length" "2")
1276 (set_attr "cc" "set_zn")])
1278 (define_expand "neghi2"
1279 [(set (match_operand:HI 0 "register_operand" "")
1280 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1286 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1291 (define_expand "neghi2_h8300"
1293 (not:HI (match_operand:HI 1 "register_operand" "")))
1294 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1295 (set (match_operand:HI 0 "register_operand" "")
1298 "{ operands[2] = gen_reg_rtx (HImode); }")
1300 (define_insn "neghi2_h8300h"
1301 [(set (match_operand:HI 0 "register_operand" "=r")
1302 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1303 "TARGET_H8300H || TARGET_H8300S"
1305 [(set_attr "length" "2")
1306 (set_attr "cc" "set_zn")])
1308 (define_expand "negsi2"
1309 [(set (match_operand:SI 0 "register_operand" "")
1310 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1316 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1321 (define_expand "negsi2_h8300"
1323 (not:SI (match_operand:SI 1 "register_operand" "")))
1324 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1325 (set (match_operand:SI 0 "register_operand" "")
1328 "{ operands[2] = gen_reg_rtx(SImode); }")
1330 (define_insn "negsi2_h8300h"
1331 [(set (match_operand:SI 0 "register_operand" "=r")
1332 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1333 "TARGET_H8300H || TARGET_H8300S"
1335 [(set_attr "length" "2")
1336 (set_attr "cc" "set_zn")])
1338 ;; ----------------------------------------------------------------------
1340 ;; ----------------------------------------------------------------------
1342 (define_insn "one_cmplqi2"
1343 [(set (match_operand:QI 0 "register_operand" "=r")
1344 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1347 [(set_attr "length" "2")
1348 (set_attr "cc" "set_znv")])
1350 (define_insn "one_cmplhi2"
1351 [(set (match_operand:HI 0 "register_operand" "=r")
1352 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1357 return \"not %s0\;not %t0\";
1361 [(set_attr "cc" "clobber")
1362 (set (attr "length")
1363 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1368 (define_insn "one_cmplsi2"
1369 [(set (match_operand:SI 0 "register_operand" "=r")
1370 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1375 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1379 [(set_attr "cc" "clobber")
1380 (set (attr "length")
1381 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1386 ;; ----------------------------------------------------------------------
1387 ;; JUMP INSTRUCTIONS
1388 ;; ----------------------------------------------------------------------
1390 ;; Conditional jump instructions
1392 (define_expand "ble"
1394 (if_then_else (le (cc0)
1396 (label_ref (match_operand 0 "" ""))
1401 (define_expand "bleu"
1403 (if_then_else (leu (cc0)
1405 (label_ref (match_operand 0 "" ""))
1410 (define_expand "bge"
1412 (if_then_else (ge (cc0)
1414 (label_ref (match_operand 0 "" ""))
1419 (define_expand "bgeu"
1421 (if_then_else (geu (cc0)
1423 (label_ref (match_operand 0 "" ""))
1428 (define_expand "blt"
1430 (if_then_else (lt (cc0)
1432 (label_ref (match_operand 0 "" ""))
1437 (define_expand "bltu"
1439 (if_then_else (ltu (cc0)
1441 (label_ref (match_operand 0 "" ""))
1446 (define_expand "bgt"
1448 (if_then_else (gt (cc0)
1450 (label_ref (match_operand 0 "" ""))
1455 (define_expand "bgtu"
1457 (if_then_else (gtu (cc0)
1459 (label_ref (match_operand 0 "" ""))
1464 (define_expand "beq"
1466 (if_then_else (eq (cc0)
1468 (label_ref (match_operand 0 "" ""))
1473 (define_expand "bne"
1475 (if_then_else (ne (cc0)
1477 (label_ref (match_operand 0 "" ""))
1482 (define_insn "branch_true"
1484 (if_then_else (match_operator 1 "comparison_operator"
1485 [(cc0) (const_int 0)])
1486 (label_ref (match_operand 0 "" ""))
1491 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1492 && (GET_CODE (operands[1]) == GT
1493 || GET_CODE (operands[1]) == GE
1494 || GET_CODE (operands[1]) == LE
1495 || GET_CODE (operands[1]) == LT))
1497 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1501 if (get_attr_length (insn) == 2)
1502 return \"b%j1 %l0\";
1503 else if (get_attr_length (insn) == 4)
1504 return \"b%j1 %l0:16\";
1506 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1508 [(set_attr "type" "branch")
1509 (set_attr "cc" "none")])
1511 (define_insn "branch_false"
1513 (if_then_else (match_operator 1 "comparison_operator"
1514 [(cc0) (const_int 0)])
1516 (label_ref (match_operand 0 "" ""))))]
1520 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1521 && (GET_CODE (operands[1]) == GT
1522 || GET_CODE (operands[1]) == GE
1523 || GET_CODE (operands[1]) == LE
1524 || GET_CODE (operands[1]) == LT))
1526 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1530 if (get_attr_length (insn) == 2)
1531 return \"b%k1 %l0\";
1532 else if (get_attr_length (insn) == 4)
1533 return \"b%k1 %l0:16\";
1535 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1537 [(set_attr "type" "branch")
1538 (set_attr "cc" "none")])
1540 ;; Unconditional and other jump instructions.
1544 (label_ref (match_operand 0 "" "")))]
1548 if (get_attr_length (insn) == 2)
1550 else if (get_attr_length (insn) == 4)
1551 return \"bra %l0:16\";
1553 return \"jmp @%l0\";
1555 [(set_attr "type" "branch")
1556 (set_attr "cc" "none")])
1558 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1560 (define_expand "tablejump"
1561 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1562 (use (label_ref (match_operand 1 "" "")))])]
1566 (define_insn "tablejump_h8300"
1567 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1568 (use (label_ref (match_operand 1 "" "")))]
1571 [(set_attr "cc" "none")
1572 (set_attr "length" "2")])
1574 (define_insn "tablejump_h8300h"
1575 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1576 (use (label_ref (match_operand 1 "" "")))]
1577 "TARGET_H8300H || TARGET_H8300S"
1579 [(set_attr "cc" "none")
1580 (set_attr "length" "2")])
1582 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1584 (define_expand "indirect_jump"
1585 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1589 (define_insn "indirect_jump_h8300"
1590 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1593 [(set_attr "cc" "none")
1594 (set_attr "length" "2")])
1596 (define_insn "indirect_jump_h8300h"
1597 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1598 "TARGET_H8300H || TARGET_H8300S"
1600 [(set_attr "cc" "none")
1601 (set_attr "length" "2")])
1603 ;; Call subroutine with no return value.
1605 ;; ??? Even though we use HImode here, this works on the H8/300H and H8/S.
1608 [(call (match_operand:QI 0 "call_insn_operand" "or")
1609 (match_operand:HI 1 "general_operand" "g"))]
1613 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1614 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1615 return \"jsr\\t@%0:8\";
1617 return \"jsr\\t%0\";
1619 [(set_attr "cc" "clobber")
1620 (set (attr "length")
1621 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1625 ;; Call subroutine, returning value in operand 0
1626 ;; (which must be a hard register).
1628 ;; ??? Even though we use HImode here, this works on the H8/300H and H8/S.
1630 (define_insn "call_value"
1631 [(set (match_operand 0 "" "=r")
1632 (call (match_operand:QI 1 "call_insn_operand" "or")
1633 (match_operand:HI 2 "general_operand" "g")))]
1637 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1638 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1639 return \"jsr\\t@%1:8\";
1641 return \"jsr\\t%1\";
1643 [(set_attr "cc" "clobber")
1644 (set (attr "length")
1645 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1653 [(set_attr "cc" "none")
1654 (set_attr "length" "2")])
1656 ;; ----------------------------------------------------------------------
1657 ;; EXTEND INSTRUCTIONS
1658 ;; ----------------------------------------------------------------------
1660 (define_expand "zero_extendqihi2"
1661 [(set (match_operand:HI 0 "register_operand" "")
1662 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1667 [(set (match_operand:HI 0 "register_operand" "=r,r")
1668 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1672 mov.b %R1,%s0\;mov.b #0,%t0"
1673 [(set_attr "length" "2,10")
1674 (set_attr "cc" "clobber,clobber")])
1677 [(set (match_operand:HI 0 "register_operand" "=r,r")
1678 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1679 "TARGET_H8300H || TARGET_H8300S"
1682 mov.b %R1,%s0\;extu.w %T0"
1683 [(set_attr "length" "2,10")
1684 (set_attr "cc" "set_znv,set_znv")])
1686 ;; The compiler can synthesize a 300H variant of this which is
1687 ;; just as efficient as one that we'd create
1688 (define_insn "zero_extendqisi2"
1689 [(set (match_operand:SI 0 "register_operand" "=r,r")
1690 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1693 mov.b #0,%x0\;sub.w %e0,%e0
1694 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1695 [(set_attr "length" "4,6")
1696 (set_attr "cc" "clobber,clobber")])
1698 (define_expand "zero_extendhisi2"
1699 [(set (match_operand:SI 0 "register_operand" "")
1700 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1704 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1706 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1707 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1711 mov.w %f1,%f0\;sub.w %e0,%e0
1712 mov.w %e1,%f0\;sub.w %e0,%e0"
1713 [(set_attr "length" "2,4,4")
1714 (set_attr "cc" "clobber,clobber,clobber")])
1717 [(set (match_operand:SI 0 "register_operand" "=r")
1718 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1719 "TARGET_H8300H || TARGET_H8300S"
1721 [(set_attr "length" "2")
1722 (set_attr "cc" "set_znv")])
1724 (define_expand "extendqihi2"
1725 [(set (match_operand:HI 0 "register_operand" "")
1726 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1731 [(set (match_operand:HI 0 "register_operand" "=r,r")
1732 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1735 bld #7,%s0\;subx %t0,%t0
1736 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1737 [(set_attr "length" "4,8")
1738 (set_attr "cc" "clobber,clobber")])
1741 [(set (match_operand:HI 0 "register_operand" "=r")
1742 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1743 "TARGET_H8300H || TARGET_H8300S"
1745 [(set_attr "length" "2")
1746 (set_attr "cc" "set_znv")])
1748 ;; The compiler can synthesize a 300H variant of this which is
1749 ;; just as efficient as one that we'd create
1750 (define_insn "extendqisi2"
1751 [(set (match_operand:SI 0 "register_operand" "=r,r")
1752 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1755 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1756 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1757 [(set_attr "length" "8,10")
1758 (set_attr "cc" "clobber,clobber")])
1760 (define_expand "extendhisi2"
1761 [(set (match_operand:SI 0 "register_operand" "")
1762 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1767 [(set (match_operand:SI 0 "register_operand" "=r,r")
1768 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1771 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1772 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1773 [(set_attr "length" "6,8")
1774 (set_attr "cc" "clobber,clobber")])
1777 [(set (match_operand:SI 0 "register_operand" "=r")
1778 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1779 "TARGET_H8300H || TARGET_H8300S"
1781 [(set_attr "length" "2")
1782 (set_attr "cc" "set_znv")])
1784 ;; ----------------------------------------------------------------------
1786 ;; ----------------------------------------------------------------------
1788 ;; We make some attempt to provide real efficient shifting. One example is
1789 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1790 ;; reg and moving 0 into the former reg.
1792 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1793 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1794 ;; give the optimizer more cracks at the code. However, we wish to do things
1795 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1796 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1797 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1798 ;; to detect cases it can optimize.
1800 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1801 ;; easier "do it at insn emit time" route.
1805 (define_expand "ashlqi3"
1806 [(set (match_operand:QI 0 "register_operand" "")
1807 (ashift:QI (match_operand:QI 1 "register_operand" "")
1808 (match_operand:QI 2 "nonmemory_operand" "")))]
1810 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
1812 (define_expand "ashrqi3"
1813 [(set (match_operand:QI 0 "register_operand" "")
1814 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1815 (match_operand:QI 2 "nonmemory_operand" "")))]
1817 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
1819 (define_expand "lshrqi3"
1820 [(set (match_operand:QI 0 "register_operand" "")
1821 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1822 (match_operand:QI 2 "nonmemory_operand" "")))]
1824 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
1827 [(set (match_operand:QI 0 "register_operand" "=r,r")
1828 (match_operator:QI 3 "nshift_operator"
1829 [ (match_operand:QI 1 "register_operand" "0,0")
1830 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1831 (clobber (match_scratch:QI 4 "=X,&r"))]
1833 "* return output_a_shift (insn, operands);"
1834 [(set_attr "length" "20")
1835 (set_attr "cc" "clobber")])
1839 (define_expand "ashlhi3"
1840 [(set (match_operand:HI 0 "register_operand" "")
1841 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1842 (match_operand:QI 2 "nonmemory_operand" "")))]
1844 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
1846 (define_expand "lshrhi3"
1847 [(set (match_operand:HI 0 "register_operand" "")
1848 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1849 (match_operand:QI 2 "nonmemory_operand" "")))]
1851 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
1853 (define_expand "ashrhi3"
1854 [(set (match_operand:HI 0 "register_operand" "")
1855 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1856 (match_operand:QI 2 "nonmemory_operand" "")))]
1858 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
1861 [(set (match_operand:HI 0 "register_operand" "=r,r")
1862 (match_operator:HI 3 "nshift_operator"
1863 [ (match_operand:HI 1 "register_operand" "0,0")
1864 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1865 (clobber (match_scratch:QI 4 "=X,&r"))]
1867 "* return output_a_shift (insn, operands);"
1868 [(set_attr "length" "20")
1869 (set_attr "cc" "clobber")])
1873 (define_expand "ashlsi3"
1874 [(set (match_operand:SI 0 "register_operand" "")
1876 (match_operand:SI 1 "general_operand" "")
1877 (match_operand:QI 2 "nonmemory_operand" "")))]
1879 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
1881 (define_expand "lshrsi3"
1882 [(set (match_operand:SI 0 "register_operand" "")
1884 (match_operand:SI 1 "general_operand" "")
1885 (match_operand:QI 2 "nonmemory_operand" "")))]
1887 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
1889 (define_expand "ashrsi3"
1890 [(set (match_operand:SI 0 "register_operand" "")
1892 (match_operand:SI 1 "general_operand" "")
1893 (match_operand:QI 2 "nonmemory_operand" "")))]
1895 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
1898 [(set (match_operand:SI 0 "register_operand" "=r,r")
1899 (match_operator:SI 3 "nshift_operator"
1900 [ (match_operand:SI 1 "register_operand" "0,0")
1901 (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
1902 (clobber (match_scratch:QI 4 "=X,&r"))]
1904 "* return output_a_shift (insn, operands);"
1905 [(set_attr "length" "20")
1906 (set_attr "cc" "clobber")])
1908 ;; ----------------------------------------------------------------------
1910 ;; ----------------------------------------------------------------------
1912 (define_expand "rotlqi3"
1913 [(set (match_operand:QI 0 "register_operand" "")
1914 (rotate:QI (match_operand:QI 1 "register_operand" "")
1915 (match_operand:QI 2 "nonmemory_operand" "")))]
1917 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1919 (define_insn "*rotlqi3_1"
1920 [(set (match_operand:QI 0 "register_operand" "=r")
1921 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1922 (match_operand:QI 2 "immediate_operand" "")))]
1924 "* return emit_a_rotate (ROTATE, operands);"
1925 [(set_attr "length" "20")
1926 (set_attr "cc" "clobber")])
1928 (define_expand "rotlhi3"
1929 [(set (match_operand:HI 0 "register_operand" "")
1930 (rotate:HI (match_operand:HI 1 "register_operand" "")
1931 (match_operand:QI 2 "nonmemory_operand" "")))]
1933 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1935 (define_insn "*rotlhi3_1"
1936 [(set (match_operand:HI 0 "register_operand" "=r")
1937 (rotate:HI (match_operand:HI 1 "register_operand" "0")
1938 (match_operand:QI 2 "immediate_operand" "")))]
1940 "* return emit_a_rotate (ROTATE, operands);"
1941 [(set_attr "length" "20")
1942 (set_attr "cc" "clobber")])
1944 (define_expand "rotlsi3"
1945 [(set (match_operand:SI 0 "register_operand" "")
1946 (rotate:SI (match_operand:SI 1 "register_operand" "")
1947 (match_operand:QI 2 "nonmemory_operand" "")))]
1948 "TARGET_H8300H || TARGET_H8300S"
1949 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1951 (define_insn "*rotlsi3_1"
1952 [(set (match_operand:SI 0 "register_operand" "=r")
1953 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1954 (match_operand:QI 2 "immediate_operand" "")))]
1955 "TARGET_H8300H || TARGET_H8300S"
1956 "* return emit_a_rotate (ROTATE, operands);"
1957 [(set_attr "length" "20")
1958 (set_attr "cc" "clobber")])
1960 ;; -----------------------------------------------------------------
1962 ;; -----------------------------------------------------------------
1963 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1964 ;; instructions so let's use them as well as we can.
1966 ;; You'll never believe all these patterns perform one basic action --
1967 ;; load a bit from the source, optionally invert the bit, then store it
1968 ;; in the destination (which is known to be zero).
1970 ;; Combine obviously need some work to better identify this situation and
1971 ;; canonicalize the form better.
1974 ;; Normal loads with a 16bit destination.
1978 [(set (match_operand:HI 0 "register_operand" "=&r")
1979 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1981 (match_operand:HI 2 "immediate_operand" "n")))]
1983 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1984 [(set_attr "cc" "clobber")
1985 (set_attr "length" "6")])
1988 ;; Inverted loads with a 16bit destination.
1992 [(set (match_operand:HI 0 "register_operand" "=&r")
1993 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
1994 (match_operand:HI 3 "p_operand" "P"))
1996 (match_operand:HI 2 "const_int_operand" "n")))]
1998 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
1999 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2000 [(set_attr "cc" "clobber")
2001 (set_attr "length" "8")])
2004 ;; Normal loads with a 32bit destination.
2006 ;; Yes, all three cases are needed.
2009 [(set (match_operand:SI 0 "register_operand" "=&r")
2010 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2012 (match_operand:HI 2 "const_int_operand" "n")))]
2014 "* return output_simode_bld (0, 0, operands);"
2015 [(set_attr "cc" "clobber")
2016 (set (attr "length")
2017 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2023 [(set (match_operand:SI 0 "register_operand" "=&r")
2024 (and:SI (zero_extend:SI
2026 (match_operand:QI 1 "bit_operand" "Ur")
2027 (match_operand:QI 2 "const_int_operand" "n")))
2030 "* return output_simode_bld (0, 0, operands);"
2031 [(set_attr "cc" "clobber")
2032 (set (attr "length")
2033 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2039 [(set (match_operand:SI 0 "register_operand" "=&r")
2040 (and:SI (zero_extend:SI
2042 (match_operand:HI 1 "bit_operand" "Ur")
2043 (match_operand:HI 2 "const_int_operand" "n")))
2046 "* return output_simode_bld (0, 0, operands);"
2047 [(set_attr "cc" "clobber")
2048 (set (attr "length")
2049 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2055 ;; Inverted loads with a 32bit destination.
2057 ;; Yes, all five cases are needed.
2060 [(set (match_operand:SI 0 "register_operand" "=&r")
2063 (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
2064 (match_operand:HI 2 "const_int_operand" "n"))))
2067 "* return output_simode_bld (1, 0, operands);"
2068 [(set_attr "cc" "clobber")
2069 (set (attr "length")
2070 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2076 [(set (match_operand:SI 0 "register_operand" "=&r")
2079 (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
2080 (match_operand:QI 2 "const_int_operand" "n"))))
2083 "* return output_simode_bld (1, 0, operands);"
2084 [(set_attr "cc" "clobber")
2085 (set (attr "length")
2086 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2092 [(set (match_operand:SI 0 "register_operand" "=&r")
2096 (match_operand:HI 1 "bit_operand" "Ur")
2097 (match_operand:HI 2 "const_int_operand" "n")) 0))
2100 "* return output_simode_bld (1, 0, operands);"
2101 [(set_attr "cc" "clobber")
2102 (set (attr "length")
2103 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2109 [(set (match_operand:SI 0 "register_operand" "=&r")
2113 (match_operand:QI 1 "bit_operand" "Ur")
2114 (match_operand:QI 2 "const_int_operand" "n")) 0))
2117 "* return output_simode_bld (1, 0, operands);"
2118 [(set_attr "cc" "clobber")
2119 (set (attr "length")
2120 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2126 [(set (match_operand:SI 0 "register_operand" "=&r")
2127 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2128 (match_operand:HI 3 "p_operand" "P"))
2130 (match_operand:HI 2 "const_int_operand" "n")))]
2131 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2132 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2133 [(set_attr "cc" "clobber")
2134 (set_attr "length" "8")])
2136 (define_expand "insv"
2137 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2138 (match_operand:HI 1 "general_operand" "")
2139 (match_operand:HI 2 "general_operand" ""))
2140 (match_operand:HI 3 "general_operand" ""))]
2144 /* We only have single bit bitfield instructions. */
2145 if (INTVAL (operands[1]) != 1)
2148 /* For now, we don't allow memory operands. */
2149 if (GET_CODE (operands[0]) == MEM
2150 || GET_CODE (operands[3]) == MEM)
2155 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2157 (match_operand:HI 1 "immediate_operand" "n"))
2158 (match_operand:HI 2 "register_operand" "r"))]
2160 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2161 [(set_attr "cc" "clobber")
2162 (set_attr "length" "4")])
2164 (define_expand "extzv"
2165 [(set (match_operand:HI 0 "register_operand" "")
2166 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2167 (match_operand:HI 2 "general_operand" "")
2168 (match_operand:HI 3 "general_operand" "")))]
2172 /* We only have single bit bitfield instructions. */
2173 if (INTVAL (operands[2]) != 1)
2176 /* For now, we don't allow memory operands. */
2177 if (GET_CODE (operands[1]) == MEM)
2181 ;; BAND, BOR, and BXOR patterns
2184 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2185 (match_operator:HI 4 "bit_operator"
2186 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2188 (match_operand:HI 2 "immediate_operand" "n"))
2189 (match_operand:HI 3 "bit_operand" "0")]))]
2191 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2192 [(set_attr "cc" "clobber")
2193 (set_attr "length" "6")
2194 (set_attr "adjust_length" "no")])
2197 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2198 (match_operator:HI 5 "bit_operator"
2199 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2201 (match_operand:HI 2 "immediate_operand" "n"))
2202 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2204 (match_operand:HI 4 "immediate_operand" "n"))]))]
2206 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2207 [(set_attr "cc" "clobber")
2208 (set_attr "length" "6")
2209 (set_attr "adjust_length" "no")])
2211 ;; -----------------------------------------------------------------
2213 ;; -----------------------------------------------------------------
2216 [(set (match_operand:HI 0 "register_operand" "=r")
2218 (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2219 (match_operand:HI 2 "register_operand" "0")))]
2220 "REG_P (operands[0])
2221 && REG_P (operands[1])
2222 && REGNO (operands[0]) != REGNO (operands[1])"
2224 [(set_attr "cc" "clobber")
2225 (set_attr "length" "2")])
2228 [(set (match_operand:SI 0 "register_operand" "=r")
2230 (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2231 (match_operand:SI 2 "register_operand" "0")))]
2232 "(TARGET_H8300H || TARGET_H8300S)
2233 && REG_P (operands[0])
2234 && REG_P (operands[1])
2235 && (REGNO (operands[0]) != REGNO (operands[1]))"
2237 [(set_attr "cc" "clobber")
2238 (set_attr "length" "2")])
2241 [(set (match_operand:SI 0 "register_operand" "=r")
2243 (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2244 (match_operand:SI 2 "register_operand" "0")))]
2245 "REG_P (operands[0])
2246 && REG_P (operands[1])
2247 && REGNO (operands[0]) != REGNO (operands[1])"
2249 [(set_attr "cc" "clobber")
2250 (set_attr "length" "2")])
2253 [(set (match_operand:HI 0 "register_operand" "=r")
2255 (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2256 (match_operand:HI 2 "register_operand" "0")))]
2257 "REG_P (operands[0])
2258 && REG_P (operands[1])
2259 && REGNO (operands[0]) != REGNO (operands[1])"
2261 [(set_attr "cc" "clobber")
2262 (set_attr "length" "2")])
2265 [(set (match_operand:SI 0 "register_operand" "=r")
2267 (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2268 (match_operand:SI 2 "register_operand" "0")))]
2269 "(TARGET_H8300H || TARGET_H8300S)
2270 && REG_P (operands[0])
2271 && REG_P (operands[1])
2272 && (REGNO (operands[0]) != REGNO (operands[1]))"
2274 [(set_attr "cc" "clobber")
2275 (set_attr "length" "2")])
2278 [(set (match_operand:SI 0 "register_operand" "=r")
2280 (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2281 (match_operand:SI 2 "register_operand" "0")))]
2282 "REG_P (operands[0])
2283 && REG_P (operands[1])
2284 && REGNO (operands[0]) != REGNO (operands[1])"
2286 [(set_attr "cc" "clobber")
2287 (set_attr "length" "2")])
2290 [(set (match_operand:HI 0 "register_operand" "=r")
2292 (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2293 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2295 "REG_P (operands[0])
2296 && REG_P (operands[2])
2297 && REGNO (operands[0]) != REGNO (operands[2])"
2299 [(set_attr "cc" "clobber")
2300 (set_attr "length" "2")])
2303 [(set (match_operand:SI 0 "register_operand" "=r")
2305 (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2306 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2308 "(TARGET_H8300H || TARGET_H8300S)
2309 && REG_P (operands[0])
2310 && REG_P (operands[2])
2311 && (REGNO (operands[0]) != REGNO (operands[2]))"
2313 [(set_attr "cc" "clobber")
2314 (set_attr "length" "2")])