1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc.
6 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
7 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 3, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING3. If not see
23 ;; <http://www.gnu.org/licenses/>.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
72 ;; ----------------------------------------------------------------------
74 ;; ----------------------------------------------------------------------
76 (define_attr "cpu" "h8300,h8300h"
77 (const (symbol_ref "cpu_type")))
79 (define_attr "type" "branch,arith,bitbranch,call"
80 (const_string "arith"))
82 (define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
83 (const_string "none"))
85 ;; The size of instructions in bytes.
87 (define_attr "length" ""
88 (cond [(eq_attr "type" "branch")
89 ;; In a forward delayed branch, (pc) represents the end of the
90 ;; delay sequence, not the end of the branch itself.
91 (if_then_else (and (ge (minus (match_dup 0) (pc))
93 (le (plus (minus (match_dup 0) (pc))
94 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
97 (if_then_else (and (eq_attr "cpu" "h8300h")
98 (and (ge (minus (pc) (match_dup 0))
100 (le (minus (pc) (match_dup 0))
104 (eq_attr "type" "bitbranch")
106 (and (ge (minus (match_dup 0) (pc))
108 (le (minus (match_dup 0) (pc))
111 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
114 (and (eq_attr "cpu" "h8300h")
115 (and (ge (minus (pc) (match_dup 0))
117 (le (minus (pc) (match_dup 0))
120 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
123 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
125 (eq_attr "length_table" "!none")
126 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
129 ;; Condition code settings.
131 ;; none - insn does not affect cc
132 ;; none_0hit - insn does not affect cc but it does modify operand 0
133 ;; This attribute is used to keep track of when operand 0 changes.
134 ;; See the description of NOTICE_UPDATE_CC for more info.
135 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
136 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
137 ;; compare - compare instruction
138 ;; clobber - value of cc is unknown
140 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
141 (const_string "clobber"))
143 ;; Type of delay slot. NONE means the instruction has no delay slot.
144 ;; JUMP means it is an unconditional jump that (if short enough)
145 ;; could be implemented using bra/s.
146 (define_attr "delay_slot" "none,jump"
147 (const_string "none"))
149 ;; "yes" if the instruction can be put into a delay slot. It's not
150 ;; entirely clear that jsr is not valid in delay slots, but it
151 ;; definitely doesn't have the effect of causing the called function
152 ;; to return to the target of the delayed branch.
153 (define_attr "can_delay" "no,yes"
154 (cond [(eq_attr "type" "branch,bitbranch,call")
156 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
158 (const_string "yes")))
160 ;; Only allow jumps to have a delay slot if we think they might
161 ;; be short enough. This is just an optimization: we don't know
162 ;; for certain whether they will be or not.
163 (define_delay (and (eq_attr "delay_slot" "jump")
164 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
165 [(eq_attr "can_delay" "yes")
169 ;; Provide the maximum length of an assembly instruction in an asm
170 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
172 (define_asm_attributes
173 [(set (attr "length")
174 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
175 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
176 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
179 (include "predicates.md")
181 ;; ----------------------------------------------------------------------
183 ;; ----------------------------------------------------------------------
187 (define_insn "*movqi_h8300"
188 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
189 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
191 && (register_operand (operands[0], QImode)
192 || register_operand (operands[1], QImode))"
200 [(set_attr "length" "2,2,2,2,4,4")
201 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
203 (define_insn "*movqi_h8300hs"
204 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
205 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
206 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
207 && (register_operand (operands[0], QImode)
208 || register_operand (operands[1], QImode))"
216 [(set (attr "length")
217 (symbol_ref "compute_mov_length (operands)"))
218 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
220 (define_insn "*movqi_h8sx"
221 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
222 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
227 [(set_attr "length_table" "mov_imm4,movb")
228 (set_attr "cc" "set_znv")])
230 (define_expand "movqi"
231 [(set (match_operand:QI 0 "general_operand_dst" "")
232 (match_operand:QI 1 "general_operand_src" ""))]
236 /* One of the ops has to be in a register. */
238 && !register_operand (operand0, QImode)
239 && !register_operand (operand1, QImode))
241 operands[1] = copy_to_mode_reg (QImode, operand1);
245 (define_insn "movstrictqi"
246 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
247 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
252 [(set_attr "length" "2,*")
253 (set_attr "length_table" "*,movb")
254 (set_attr "cc" "set_zn,set_znv")])
258 (define_insn "*movhi_h8300"
259 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
260 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
262 && (register_operand (operands[0], HImode)
263 || register_operand (operands[1], HImode))
264 && !(GET_CODE (operands[0]) == MEM
265 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
266 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
267 && GET_CODE (operands[1]) == REG
268 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
276 [(set (attr "length")
277 (symbol_ref "compute_mov_length (operands)"))
278 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
280 (define_insn "*movhi_h8300hs"
281 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
282 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
283 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
284 && (register_operand (operands[0], HImode)
285 || register_operand (operands[1], HImode))"
293 [(set (attr "length")
294 (symbol_ref "compute_mov_length (operands)"))
295 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
297 (define_insn "*movhi_h8sx"
298 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
299 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
307 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
308 (set_attr "length" "2,2,*,*,*")
309 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
311 (define_expand "movhi"
312 [(set (match_operand:HI 0 "general_operand_dst" "")
313 (match_operand:HI 1 "general_operand_src" ""))]
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, HImode)
319 && !register_operand (operand0, HImode))
321 operands[1] = copy_to_mode_reg (HImode, operand1);
325 (define_insn "movstricthi"
326 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
327 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
333 [(set_attr "length" "2,2,*")
334 (set_attr "length_table" "*,*,movw")
335 (set_attr "cc" "set_zn,set_znv,set_znv")])
339 (define_expand "movsi"
340 [(set (match_operand:SI 0 "general_operand_dst" "")
341 (match_operand:SI 1 "general_operand_src" ""))]
347 if (h8300_expand_movsi (operands))
350 else if (!TARGET_H8300SX)
352 /* One of the ops has to be in a register. */
353 if (!register_operand (operand1, SImode)
354 && !register_operand (operand0, SImode))
356 operands[1] = copy_to_mode_reg (SImode, operand1);
361 (define_insn "*movsi_h8300"
362 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
363 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
365 && (register_operand (operands[0], SImode)
366 || register_operand (operands[1], SImode))"
369 unsigned int rn = -1;
370 switch (which_alternative)
373 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
375 if (REGNO (operands[0]) < REGNO (operands[1]))
376 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
378 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
380 /* Make sure we don't trample the register we index with. */
381 if (GET_CODE (operands[1]) == MEM)
383 rtx inside = XEXP (operands[1], 0);
388 else if (GET_CODE (inside) == PLUS)
390 rtx lhs = XEXP (inside, 0);
391 rtx rhs = XEXP (inside, 1);
392 if (REG_P (lhs)) rn = REGNO (lhs);
393 if (REG_P (rhs)) rn = REGNO (rhs);
396 if (rn == REGNO (operands[0]))
398 /* Move the second word first. */
399 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
403 if (GET_CODE (operands[1]) == CONST_INT)
405 /* If either half is zero, use sub.w to clear that
407 if ((INTVAL (operands[1]) & 0xffff) == 0)
408 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
409 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
410 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
411 /* If the upper half and the lower half are the same,
412 copy one half to the other. */
413 if ((INTVAL (operands[1]) & 0xffff)
414 == ((INTVAL (operands[1]) >> 16) & 0xffff))
415 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
417 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
420 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
422 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
424 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
429 [(set (attr "length")
430 (symbol_ref "compute_mov_length (operands)"))])
432 (define_insn "*movsi_h8300hs"
433 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
434 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
435 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
436 && (register_operand (operands[0], SImode)
437 || register_operand (operands[1], SImode))
438 && !(GET_CODE (operands[0]) == MEM
439 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
440 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
441 && GET_CODE (operands[1]) == REG
442 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
445 switch (which_alternative)
448 return \"sub.l %S0,%S0\";
452 return \"clrmac\;ldmac %1,macl\";
454 return \"stmac macl,%0\";
456 if (GET_CODE (operands[1]) == CONST_INT)
458 int val = INTVAL (operands[1]);
460 /* Look for constants which can be made by adding an 8-bit
461 number to zero in one of the two low bytes. */
462 if (val == (val & 0xff))
464 operands[1] = GEN_INT ((char) val & 0xff);
465 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
468 if (val == (val & 0xff00))
470 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
471 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
474 /* Look for constants that can be obtained by subs, inc, and
476 switch (val & 0xffffffff)
479 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
481 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
483 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
486 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
488 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
491 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
493 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
496 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
498 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
502 return \"mov.l %S1,%S0\";
504 [(set (attr "length")
505 (symbol_ref "compute_mov_length (operands)"))
506 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
508 (define_insn "*movsi_h8sx"
509 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
510 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
518 clrmac\;ldmac %1,macl
520 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
521 (set_attr "length" "2,2,*,*,2,6,4")
522 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
524 (define_insn "*movsf_h8sx"
525 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
526 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
531 [(set_attr "length" "2,*")
532 (set_attr "length_table" "*,movl")
533 (set_attr "cc" "set_zn,set_znv")])
535 ;; Implement block moves using movmd. Defining movmemsi allows the full
536 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
537 ;; See h8sx_emit_movmd for details.
538 (define_expand "movmemsi"
539 [(use (match_operand:BLK 0 "memory_operand" ""))
540 (use (match_operand:BLK 1 "memory_operand" ""))
541 (use (match_operand:SI 2 "" ""))
542 (use (match_operand:SI 3 "const_int_operand" ""))]
545 if (h8sx_emit_movmd (operands[0], operands[1], operands[2],
546 INTVAL (operands[3])))
552 ;; Expander for generating movmd insns. Operand 0 is the destination
553 ;; memory region, operand 1 is the source, operand 2 is the counter
554 ;; register and operand 3 is the chunk size (1, 2 or 4).
555 (define_expand "movmd"
557 [(set (match_operand:BLK 0 "memory_operand" "")
558 (match_operand:BLK 1 "memory_operand" ""))
559 (unspec [(match_operand:HI 2 "register_operand" "")
560 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
561 (clobber (match_dup 4))
562 (clobber (match_dup 5))
567 operands[4] = copy_rtx (XEXP (operands[0], 0));
568 operands[5] = copy_rtx (XEXP (operands[1], 0));
572 ;; This is a difficult instruction to reload since operand 0 must be the
573 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
574 (define_insn "movmd_internal_normal"
575 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
576 (mem:BLK (match_operand:HI 4 "register_operand" "1,1")))
577 (unspec [(match_operand:HI 5 "register_operand" "2,2")
578 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
579 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
580 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
581 (set (match_operand:HI 2 "register_operand" "=c,c")
583 "TARGET_H8300SX && TARGET_NORMAL_MODE"
587 [(set_attr "length" "2,14")
588 (set_attr "can_delay" "no")
589 (set_attr "cc" "none,clobber")])
591 (define_insn "movmd_internal"
592 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
593 (mem:BLK (match_operand:SI 4 "register_operand" "1,1")))
594 (unspec [(match_operand:HI 5 "register_operand" "2,2")
595 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
596 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
597 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
598 (set (match_operand:HI 2 "register_operand" "=c,c")
600 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
604 [(set_attr "length" "2,14")
605 (set_attr "can_delay" "no")
606 (set_attr "cc" "none,clobber")])
608 ;; Split the above instruction if the destination register isn't er6.
609 ;; We need a sequence like:
617 ;; where <dest> is the current destination register (operand 4).
618 ;; The fourth instruction will be deleted if <dest> dies here.
620 [(set (match_operand:BLK 0 "memory_operand" "")
621 (match_operand:BLK 1 "memory_operand" ""))
622 (unspec [(match_operand:HI 2 "register_operand" "")
623 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
624 (clobber (match_operand:HI 4 "register_operand" ""))
625 (clobber (match_operand:HI 5 "register_operand" ""))
628 "TARGET_H8300SX && TARGET_NORMAL_MODE
630 && REGNO (operands[4]) != DESTINATION_REG"
635 h8300_swap_into_er6 (XEXP (operands[0], 0));
636 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
637 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
638 h8300_swap_out_of_er6 (operands[4]);
643 [(set (match_operand:BLK 0 "memory_operand" "")
644 (match_operand:BLK 1 "memory_operand" ""))
645 (unspec [(match_operand:HI 2 "register_operand" "")
646 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
647 (clobber (match_operand:SI 4 "register_operand" ""))
648 (clobber (match_operand:SI 5 "register_operand" ""))
651 "TARGET_H8300SX && !TARGET_NORMAL_MODE
653 && REGNO (operands[4]) != DESTINATION_REG"
658 h8300_swap_into_er6 (XEXP (operands[0], 0));
659 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
660 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
661 h8300_swap_out_of_er6 (operands[4]);
665 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
666 ;; the final character, but movsd leaves it pointing to the character
668 (define_expand "movstr"
669 [(use (match_operand 0 "register_operand" ""))
670 (use (match_operand:BLK 1 "memory_operand" ""))
671 (use (match_operand:BLK 2 "memory_operand" ""))]
674 operands[1] = replace_equiv_address
675 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
676 operands[2] = replace_equiv_address
677 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
678 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
679 emit_insn (gen_add3_insn (operands[0],
680 XEXP (operands[1], 0),
685 ;; Expander for generating a movsd instruction. Operand 0 is the
686 ;; destination string, operand 1 is the source string and operand 2
687 ;; is a scratch register.
688 (define_expand "movsd"
690 [(set (match_operand:BLK 0 "memory_operand" "")
691 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
693 (clobber (match_dup 3))
694 (clobber (match_dup 4))
695 (clobber (match_operand 2 "register_operand" ""))])]
698 operands[3] = copy_rtx (XEXP (operands[0], 0));
699 operands[4] = copy_rtx (XEXP (operands[1], 0));
702 ;; See comments above memcpy_internal().
703 (define_insn "stpcpy_internal_normal"
704 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
705 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))]
707 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
708 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
709 (clobber (match_operand:HI 2 "register_operand" "=c,c"))]
710 "TARGET_H8300SX && TARGET_NORMAL_MODE"
712 \n1:\tmovsd\t2f\;bra\t1b\n2:
714 [(set_attr "length" "6,18")
715 (set_attr "cc" "none,clobber")])
717 (define_insn "stpcpy_internal"
718 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
719 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))]
721 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
722 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
723 (clobber (match_operand:SI 2 "register_operand" "=c,c"))]
724 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
726 \n1:\tmovsd\t2f\;bra\t1b\n2:
728 [(set_attr "length" "6,18")
729 (set_attr "cc" "none,clobber")])
731 ;; Split the above instruction if the destination isn't er6. This works
732 ;; in the same way as the movmd splitter.
734 [(set (match_operand:BLK 0 "memory_operand" "")
735 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
736 (clobber (match_operand:HI 2 "register_operand" ""))
737 (clobber (match_operand:HI 3 "register_operand" ""))
738 (clobber (match_operand:HI 4 "register_operand" ""))]
739 "TARGET_H8300SX && TARGET_NORMAL_MODE
741 && REGNO (operands[2]) != DESTINATION_REG"
746 h8300_swap_into_er6 (XEXP (operands[0], 0));
747 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
748 emit_insn (gen_movsd (dest, operands[1], operands[4]));
749 h8300_swap_out_of_er6 (operands[2]);
754 [(set (match_operand:BLK 0 "memory_operand" "")
755 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
756 (clobber (match_operand:SI 2 "register_operand" ""))
757 (clobber (match_operand:SI 3 "register_operand" ""))
758 (clobber (match_operand:SI 4 "register_operand" ""))]
759 "TARGET_H8300SX && !TARGET_NORMAL_MODE
761 && REGNO (operands[2]) != DESTINATION_REG"
766 h8300_swap_into_er6 (XEXP (operands[0], 0));
767 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
768 emit_insn (gen_movsd (dest, operands[1], operands[4]));
769 h8300_swap_out_of_er6 (operands[2]);
775 (define_expand "movsf"
776 [(set (match_operand:SF 0 "general_operand_dst" "")
777 (match_operand:SF 1 "general_operand_src" ""))]
783 if (h8300_expand_movsi (operands))
786 else if (!TARGET_H8300SX)
788 /* One of the ops has to be in a register. */
789 if (!register_operand (operand1, SFmode)
790 && !register_operand (operand0, SFmode))
792 operands[1] = copy_to_mode_reg (SFmode, operand1);
797 (define_insn "*movsf_h8300"
798 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
799 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
801 && (register_operand (operands[0], SFmode)
802 || register_operand (operands[1], SFmode))"
805 /* Copy of the movsi stuff. */
806 unsigned int rn = -1;
807 switch (which_alternative)
810 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
812 if (REGNO (operands[0]) < REGNO (operands[1]))
813 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
815 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
817 /* Make sure we don't trample the register we index with. */
818 if (GET_CODE (operands[1]) == MEM)
820 rtx inside = XEXP (operands[1], 0);
825 else if (GET_CODE (inside) == PLUS)
827 rtx lhs = XEXP (inside, 0);
828 rtx rhs = XEXP (inside, 1);
829 if (REG_P (lhs)) rn = REGNO (lhs);
830 if (REG_P (rhs)) rn = REGNO (rhs);
833 if (rn == REGNO (operands[0]))
834 /* Move the second word first. */
835 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
837 /* Move the first word first. */
838 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
841 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
843 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
845 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
850 [(set (attr "length")
851 (symbol_ref "compute_mov_length (operands)"))])
853 (define_insn "*movsf_h8300hs"
854 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
855 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
856 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
857 && (register_operand (operands[0], SFmode)
858 || register_operand (operands[1], SFmode))"
866 [(set (attr "length")
867 (symbol_ref "compute_mov_length (operands)"))
868 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
870 ;; ----------------------------------------------------------------------
872 ;; ----------------------------------------------------------------------
874 (define_insn "pushqi1_h8300"
875 [(set (reg:HI SP_REG)
876 (plus:HI (reg:HI SP_REG) (const_int -2)))
877 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
878 (match_operand:QI 0 "register_operand" "r"))]
880 && operands[0] != stack_pointer_rtx"
882 [(set_attr "length" "2")])
884 (define_insn "pushqi1_h8300hs_advanced"
885 [(set (reg:SI SP_REG)
886 (plus:SI (reg:SI SP_REG) (const_int -4)))
887 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
888 (match_operand:QI 0 "register_operand" "r"))]
889 "(TARGET_H8300H || TARGET_H8300S)
890 && operands[0] != stack_pointer_rtx"
892 [(set_attr "length" "4")])
894 (define_insn "pushqi1_h8300hs_normal"
895 [(set (reg:HI SP_REG)
896 (plus:HI (reg:HI SP_REG) (const_int -4)))
897 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
898 (match_operand:QI 0 "register_operand" "r"))]
899 "(TARGET_H8300H || TARGET_H8300S)
900 && operands[0] != stack_pointer_rtx"
902 [(set_attr "length" "4")])
904 (define_expand "pushqi1"
905 [(match_operand:QI 0 "register_operand" "")]
910 emit_insn (gen_pushqi1_h8300 (operands[0]));
911 else if (!TARGET_NORMAL_MODE)
912 emit_insn (gen_pushqi1_h8300hs_advanced (operands[0]));
914 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
918 (define_expand "pushhi1_h8300"
919 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
920 (match_operand:HI 0 "register_operand" ""))]
922 && operands[0] != stack_pointer_rtx"
925 (define_insn "pushhi1_h8300hs_advanced"
926 [(set (reg:SI SP_REG)
927 (plus:SI (reg:SI SP_REG) (const_int -4)))
928 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
929 (match_operand:HI 0 "register_operand" "r"))]
930 "(TARGET_H8300H || TARGET_H8300S)
931 && operands[0] != stack_pointer_rtx"
933 [(set_attr "length" "4")])
935 (define_insn "pushhi1_h8300hs_normal"
936 [(set (reg:HI SP_REG)
937 (plus:HI (reg:HI SP_REG) (const_int -4)))
938 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
939 (match_operand:HI 0 "register_operand" "r"))]
940 "(TARGET_H8300H || TARGET_H8300S)
941 && operands[0] != stack_pointer_rtx"
943 [(set_attr "length" "4")])
945 (define_expand "pushhi1"
946 [(match_operand:HI 0 "register_operand" "")]
951 emit_insn (gen_pushhi1_h8300 (operands[0]));
952 else if (!TARGET_NORMAL_MODE)
953 emit_insn (gen_pushhi1_h8300hs_advanced (operands[0]));
955 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
959 ;; ----------------------------------------------------------------------
961 ;; ----------------------------------------------------------------------
965 (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
967 (match_operand 1 "const_int_operand" "n,n"))
971 [(set_attr "length" "2,4")
972 (set_attr "cc" "set_zn,set_zn")])
976 (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
978 (match_operand 1 "const_int_operand" "n"))
982 [(set_attr "length" "2")
983 (set_attr "cc" "set_zn")])
985 (define_insn_and_split "*tst_extzv_1_n"
987 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
989 (match_operand 1 "const_int_operand" "n,n,n"))
991 (clobber (match_scratch:QI 2 "=X,X,&r"))]
992 "(TARGET_H8300H || TARGET_H8300S)"
998 && !OK_FOR_U (operands[0])"
1001 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2)
1005 (clobber (scratch:QI))])]
1007 [(set_attr "length" "2,8,10")
1008 (set_attr "cc" "set_zn,set_zn,set_zn")])
1011 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1013 (match_operand 1 "const_int_operand" "n"))
1015 "(TARGET_H8300H || TARGET_H8300S)
1016 && INTVAL (operands[1]) <= 15"
1018 [(set_attr "length" "2")
1019 (set_attr "cc" "set_zn")])
1021 (define_insn_and_split "*tstsi_upper_bit"
1022 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1024 (match_operand 1 "const_int_operand" "n"))
1026 (clobber (match_scratch:SI 2 "=&r"))]
1027 "(TARGET_H8300H || TARGET_H8300S)
1028 && INTVAL (operands[1]) >= 16"
1030 "&& reload_completed"
1032 (ior:SI (and:SI (match_dup 2)
1034 (lshiftrt:SI (match_dup 0)
1036 (set (cc0) (compare (zero_extract:SI (match_dup 2)
1040 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
1042 (define_insn "*tstsi_variable_bit"
1043 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1045 (and:SI (match_operand:SI 1 "register_operand" "r")
1048 "TARGET_H8300H || TARGET_H8300S"
1050 [(set_attr "length" "2")
1051 (set_attr "cc" "set_zn")])
1053 (define_insn_and_split "*tstsi_variable_bit_qi"
1056 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
1058 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
1061 (clobber (match_scratch:QI 2 "=X,X,&r"))]
1062 "(TARGET_H8300H || TARGET_H8300S)"
1067 "&& reload_completed
1068 && !OK_FOR_U (operands[0])"
1071 (parallel [(set (cc0) (compare (zero_extract:SI (zero_extend:SI (match_dup 2))
1073 (and:SI (match_dup 1)
1076 (clobber (scratch:QI))])]
1078 [(set_attr "length" "2,8,10")
1079 (set_attr "cc" "set_zn,set_zn,set_zn")])
1081 (define_insn "*tstqi"
1082 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "r")
1086 [(set_attr "length" "2")
1087 (set_attr "cc" "set_znv")])
1089 (define_insn "*tsthi"
1090 [(set (cc0) (compare (match_operand:HI 0 "register_operand" "r")
1094 [(set_attr "length" "2")
1095 (set_attr "cc" "set_znv")])
1097 (define_insn "*tsthi_upper"
1098 [(set (cc0) (compare (and:HI (match_operand:HI 0 "register_operand" "r")
1103 [(set_attr "length" "2")
1104 (set_attr "cc" "set_znv")])
1106 (define_insn "*tstsi"
1107 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "r")
1109 "TARGET_H8300H || TARGET_H8300S"
1111 [(set_attr "length" "2")
1112 (set_attr "cc" "set_znv")])
1114 (define_insn "*tstsi_upper"
1115 [(set (cc0) (compare (and:SI (match_operand:SI 0 "register_operand" "r")
1120 [(set_attr "length" "2")
1121 (set_attr "cc" "set_znv")])
1123 (define_insn "*cmpqi"
1125 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
1126 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
1129 [(set_attr "length_table" "addb")
1130 (set_attr "cc" "compare")])
1132 (define_insn "*cmphi_h8300_znvc"
1134 (compare (match_operand:HI 0 "register_operand" "r")
1135 (match_operand:HI 1 "register_operand" "r")))]
1138 [(set_attr "length" "2")
1139 (set_attr "cc" "compare")])
1141 (define_insn "*cmphi_h8300hs_znvc"
1143 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1144 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1145 "TARGET_H8300H || TARGET_H8300S"
1148 switch (which_alternative)
1151 if (!TARGET_H8300SX)
1152 return \"cmp.w %T1,%T0\";
1154 return \"cmp.w %T1:3,%T0\";
1156 return \"cmp.w %T1,%T0\";
1161 [(set_attr "length_table" "short_immediate,addw")
1162 (set_attr "cc" "compare,compare")])
1164 (define_insn "cmpsi"
1166 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1167 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1168 "TARGET_H8300H || TARGET_H8300S"
1171 switch (which_alternative)
1174 if (!TARGET_H8300SX)
1175 return \"cmp.l %S1,%S0\";
1177 return \"cmp.l %S1:3,%S0\";
1179 return \"cmp.l %S1,%S0\";
1184 [(set_attr "length" "2,*")
1185 (set_attr "length_table" "*,addl")
1186 (set_attr "cc" "compare,compare")])
1188 ;; ----------------------------------------------------------------------
1190 ;; ----------------------------------------------------------------------
1192 (define_expand "addqi3"
1193 [(set (match_operand:QI 0 "register_operand" "")
1194 (plus:QI (match_operand:QI 1 "register_operand" "")
1195 (match_operand:QI 2 "h8300_src_operand" "")))]
1199 (define_insn "*addqi3"
1200 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1201 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
1202 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
1203 "h8300_operands_match_p (operands)"
1205 [(set_attr "length_table" "addb")
1206 (set_attr "cc" "set_zn")])
1208 (define_expand "addhi3"
1209 [(set (match_operand:HI 0 "register_operand" "")
1210 (plus:HI (match_operand:HI 1 "register_operand" "")
1211 (match_operand:HI 2 "h8300_src_operand" "")))]
1215 (define_insn "*addhi3_h8300"
1216 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1217 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1218 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1224 add.b %s2,%s0\;addx %t2,%t0
1226 [(set_attr "length" "2,2,2,4,2")
1227 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1229 ;; This splitter is very important to make the stack adjustment
1230 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1232 ;; We apply this split after the peephole2 pass so that we won't end
1233 ;; up creating too many adds/subs when a scratch register is
1234 ;; available, which is actually a common case because stack unrolling
1235 ;; tends to happen immediately after a function call.
1238 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1239 (plus:HI (match_dup 0)
1240 (match_operand 1 "const_int_gt_2_operand" "")))]
1241 "TARGET_H8300 && epilogue_completed"
1243 "split_adds_subs (HImode, operands); DONE;")
1246 [(match_scratch:HI 2 "r")
1247 (set (match_operand:HI 0 "stack_pointer_operand" "")
1248 (plus:HI (match_dup 0)
1249 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1254 (plus:HI (match_dup 0)
1258 (define_insn "*addhi3_h8300hs"
1259 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1260 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1261 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1262 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1269 [(set_attr "length" "2,2,2,4,2")
1270 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1272 (define_insn "*addhi3_incdec"
1273 [(set (match_operand:HI 0 "register_operand" "=r,r")
1274 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
1275 (match_operand:HI 2 "incdec_operand" "M,O")]
1277 "TARGET_H8300H || TARGET_H8300S"
1281 [(set_attr "length" "2,2")
1282 (set_attr "cc" "set_zn,set_zn")])
1284 (define_insn "*addhi3_h8sx"
1285 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1286 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1287 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1288 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1294 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1295 (set_attr "length" "*,*,2,*")
1296 (set_attr "cc" "set_zn")])
1299 [(set (match_operand:HI 0 "register_operand" "")
1300 (plus:HI (match_dup 0)
1301 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1304 "split_adds_subs (HImode, operands); DONE;")
1306 (define_expand "addsi3"
1307 [(set (match_operand:SI 0 "register_operand" "")
1308 (plus:SI (match_operand:SI 1 "register_operand" "")
1309 (match_operand:SI 2 "h8300_src_operand" "")))]
1313 (define_insn "*addsi_h8300"
1314 [(set (match_operand:SI 0 "register_operand" "=r,r")
1315 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1316 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1318 "* return output_plussi (operands);"
1319 [(set (attr "length")
1320 (symbol_ref "compute_plussi_length (operands)"))
1322 (symbol_ref "compute_plussi_cc (operands)"))])
1324 (define_insn "*addsi_h8300hs"
1325 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1326 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1327 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1328 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1329 "* return output_plussi (operands);"
1330 [(set (attr "length")
1331 (symbol_ref "compute_plussi_length (operands)"))
1333 (symbol_ref "compute_plussi_cc (operands)"))])
1335 (define_insn "*addsi3_incdec"
1336 [(set (match_operand:SI 0 "register_operand" "=r,r")
1337 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
1338 (match_operand:SI 2 "incdec_operand" "M,O")]
1340 "TARGET_H8300H || TARGET_H8300S"
1344 [(set_attr "length" "2,2")
1345 (set_attr "cc" "set_zn,set_zn")])
1348 [(set (match_operand:SI 0 "register_operand" "")
1349 (plus:SI (match_dup 0)
1350 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1351 "TARGET_H8300H || TARGET_H8300S"
1353 "split_adds_subs (SImode, operands); DONE;")
1355 ;; ----------------------------------------------------------------------
1356 ;; SUBTRACT INSTRUCTIONS
1357 ;; ----------------------------------------------------------------------
1359 (define_expand "subqi3"
1360 [(set (match_operand:QI 0 "register_operand" "")
1361 (minus:QI (match_operand:QI 1 "register_operand" "")
1362 (match_operand:QI 2 "h8300_src_operand" "")))]
1366 (define_insn "*subqi3"
1367 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1368 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1369 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1370 "h8300_operands_match_p (operands)"
1372 [(set_attr "length_table" "addb")
1373 (set_attr "cc" "set_zn")])
1375 (define_expand "subhi3"
1376 [(set (match_operand:HI 0 "register_operand" "")
1377 (minus:HI (match_operand:HI 1 "register_operand" "")
1378 (match_operand:HI 2 "h8300_src_operand" "")))]
1382 (define_insn "*subhi3_h8300"
1383 [(set (match_operand:HI 0 "register_operand" "=r,r")
1384 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1385 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1389 add.b %E2,%s0\;addx %F2,%t0"
1390 [(set_attr "length" "2,4")
1391 (set_attr "cc" "set_zn,clobber")])
1393 (define_insn "*subhi3_h8300hs"
1394 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
1395 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
1396 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
1397 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1401 [(set_attr "length_table" "addw")
1402 (set_attr "cc" "set_zn")])
1404 (define_expand "subsi3"
1405 [(set (match_operand:SI 0 "register_operand" "")
1406 (minus:SI (match_operand:SI 1 "register_operand" "")
1407 (match_operand:SI 2 "h8300_src_operand" "")))]
1411 operands[2] = force_reg (SImode, operands[2]);
1414 (define_insn "*subsi3_h8300"
1415 [(set (match_operand:SI 0 "register_operand" "=r")
1416 (minus:SI (match_operand:SI 1 "register_operand" "0")
1417 (match_operand:SI 2 "register_operand" "r")))]
1419 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1420 [(set_attr "length" "6")])
1422 (define_insn "*subsi3_h8300hs"
1423 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1424 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
1425 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
1426 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1430 [(set_attr "length_table" "addl")
1431 (set_attr "cc" "set_zn")])
1433 ;; ----------------------------------------------------------------------
1434 ;; MULTIPLY INSTRUCTIONS
1435 ;; ----------------------------------------------------------------------
1437 ;; Note that the H8/300 can only handle umulqihi3.
1439 (define_expand "mulqihi3"
1440 [(set (match_operand:HI 0 "register_operand" "")
1441 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1442 ;; intentionally-mismatched modes
1443 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1444 "TARGET_H8300H || TARGET_H8300S"
1447 if (GET_MODE (operands[2]) != VOIDmode)
1448 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1451 (define_insn "*mulqihi3_const"
1452 [(set (match_operand:HI 0 "register_operand" "=r")
1453 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1454 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1457 [(set_attr "length" "4")
1458 (set_attr "cc" "set_zn")])
1460 (define_insn "*mulqihi3"
1461 [(set (match_operand:HI 0 "register_operand" "=r")
1462 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1463 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1464 "TARGET_H8300H || TARGET_H8300S"
1466 [(set_attr "length" "4")
1467 (set_attr "cc" "set_zn")])
1469 (define_expand "mulhisi3"
1470 [(set (match_operand:SI 0 "register_operand" "")
1471 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1472 ;; intentionally-mismatched modes
1473 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1474 "TARGET_H8300H || TARGET_H8300S"
1477 if (GET_MODE (operands[2]) != VOIDmode)
1478 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1481 (define_insn "*mulhisi3_const"
1482 [(set (match_operand:SI 0 "register_operand" "=r")
1483 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1484 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1487 [(set_attr "length" "4")
1488 (set_attr "cc" "set_zn")])
1490 (define_insn "*mulhisi3"
1491 [(set (match_operand:SI 0 "register_operand" "=r")
1492 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1493 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1494 "TARGET_H8300H || TARGET_H8300S"
1496 [(set_attr "length" "4")
1497 (set_attr "cc" "set_zn")])
1499 (define_expand "umulqihi3"
1500 [(set (match_operand:HI 0 "register_operand" "")
1501 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1502 ;; intentionally-mismatched modes
1503 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1504 "TARGET_H8300H || TARGET_H8300S"
1507 if (GET_MODE (operands[2]) != VOIDmode)
1508 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1511 (define_insn "*umulqihi3_const"
1512 [(set (match_operand:HI 0 "register_operand" "=r")
1513 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1514 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1517 [(set_attr "length" "4")
1518 (set_attr "cc" "set_zn")])
1520 (define_insn "*umulqihi3"
1521 [(set (match_operand:HI 0 "register_operand" "=r")
1522 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1523 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1526 [(set_attr "length" "2")
1527 (set_attr "cc" "none_0hit")])
1529 (define_expand "umulhisi3"
1530 [(set (match_operand:SI 0 "register_operand" "")
1531 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1532 ;; intentionally-mismatched modes
1533 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1534 "TARGET_H8300H || TARGET_H8300S"
1537 if (GET_MODE (operands[2]) != VOIDmode)
1538 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1541 (define_insn "*umulhisi3_const"
1542 [(set (match_operand:SI 0 "register_operand" "=r")
1543 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1544 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1547 [(set_attr "length" "4")
1548 (set_attr "cc" "set_zn")])
1550 (define_insn "*umulhisi3"
1551 [(set (match_operand:SI 0 "register_operand" "=r")
1552 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1553 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1554 "TARGET_H8300H || TARGET_H8300S"
1556 [(set_attr "length" "2")
1557 (set_attr "cc" "none_0hit")])
1559 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1560 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1561 ;; on all H8SX variants.
1562 (define_insn "mulhi3"
1563 [(set (match_operand:HI 0 "register_operand" "=r")
1564 (mult:HI (match_operand:HI 1 "register_operand" "%0")
1565 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1568 [(set_attr "length" "2")
1569 (set_attr "cc" "set_zn")])
1571 (define_insn "mulsi3"
1572 [(set (match_operand:SI 0 "register_operand" "=r")
1573 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1574 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1577 [(set_attr "length" "2")
1578 (set_attr "cc" "set_zn")])
1580 (define_insn "smulsi3_highpart"
1581 [(set (match_operand:SI 0 "register_operand" "=r")
1585 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1586 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1589 "muls/u.l\\t%S2,%S0"
1590 [(set_attr "length" "2")
1591 (set_attr "cc" "set_zn")])
1593 (define_insn "umulsi3_highpart"
1594 [(set (match_operand:SI 0 "register_operand" "=r")
1598 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1599 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1602 "mulu/u.l\\t%S2,%S0"
1603 [(set_attr "length" "2")
1604 (set_attr "cc" "none_0hit")])
1606 ;; This is a "bridge" instruction. Combine can't cram enough insns
1607 ;; together to crate a MAC instruction directly, but it can create
1608 ;; this instruction, which then allows combine to create the real
1611 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1612 ;; insn must generate reasonably correct code. Egad.
1614 [(set (match_operand:SI 0 "register_operand" "=a")
1617 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1619 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1621 "clrmac\;mac @%2+,@%1+"
1622 [(set_attr "length" "6")
1623 (set_attr "cc" "none_0hit")])
1626 [(set (match_operand:SI 0 "register_operand" "=a")
1628 (sign_extend:SI (mem:HI
1629 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1630 (sign_extend:SI (mem:HI
1631 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1632 (match_operand:SI 3 "register_operand" "0")))]
1635 [(set_attr "length" "4")
1636 (set_attr "cc" "none_0hit")])
1638 ;; ----------------------------------------------------------------------
1639 ;; DIVIDE/MOD INSTRUCTIONS
1640 ;; ----------------------------------------------------------------------
1642 (define_insn "udivhi3"
1643 [(set (match_operand:HI 0 "register_operand" "=r")
1645 (match_operand:HI 1 "register_operand" "0")
1646 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1649 [(set_attr "length" "2")])
1651 (define_insn "divhi3"
1652 [(set (match_operand:HI 0 "register_operand" "=r")
1654 (match_operand:HI 1 "register_operand" "0")
1655 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1658 [(set_attr "length" "2")])
1660 (define_insn "udivsi3"
1661 [(set (match_operand:SI 0 "register_operand" "=r")
1663 (match_operand:SI 1 "register_operand" "0")
1664 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1667 [(set_attr "length" "2")])
1669 (define_insn "divsi3"
1670 [(set (match_operand:SI 0 "register_operand" "=r")
1672 (match_operand:SI 1 "register_operand" "0")
1673 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1676 [(set_attr "length" "2")])
1678 (define_insn "udivmodqi4"
1679 [(set (match_operand:QI 0 "register_operand" "=r")
1682 (match_operand:HI 1 "register_operand" "0")
1683 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1684 (set (match_operand:QI 3 "register_operand" "=r")
1688 (zero_extend:HI (match_dup 2)))))]
1692 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1693 return \"divxu.b\\t%X2,%T0\";
1695 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1697 [(set_attr "length" "4")])
1699 (define_insn "divmodqi4"
1700 [(set (match_operand:QI 0 "register_operand" "=r")
1703 (match_operand:HI 1 "register_operand" "0")
1704 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1705 (set (match_operand:QI 3 "register_operand" "=r")
1709 (sign_extend:HI (match_dup 2)))))]
1710 "TARGET_H8300H || TARGET_H8300S"
1713 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1714 return \"divxs.b\\t%X2,%T0\";
1716 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1718 [(set_attr "length" "6")])
1720 (define_insn "udivmodhi4"
1721 [(set (match_operand:HI 0 "register_operand" "=r")
1724 (match_operand:SI 1 "register_operand" "0")
1725 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1726 (set (match_operand:HI 3 "register_operand" "=r")
1730 (zero_extend:SI (match_dup 2)))))]
1731 "TARGET_H8300H || TARGET_H8300S"
1734 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1735 return \"divxu.w\\t%T2,%S0\";
1737 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1739 [(set_attr "length" "4")])
1741 (define_insn "divmodhi4"
1742 [(set (match_operand:HI 0 "register_operand" "=r")
1745 (match_operand:SI 1 "register_operand" "0")
1746 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1747 (set (match_operand:HI 3 "register_operand" "=r")
1751 (sign_extend:SI (match_dup 2)))))]
1752 "TARGET_H8300H || TARGET_H8300S"
1755 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1756 return \"divxs.w\\t%T2,%S0\";
1758 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1760 [(set_attr "length" "6")])
1762 ;; ----------------------------------------------------------------------
1764 ;; ----------------------------------------------------------------------
1765 (define_insn "bclrqi_msx"
1766 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1767 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1768 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1771 [(set_attr "length" "8")])
1774 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1775 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1776 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1779 (and:QI (match_dup 1)
1782 operands[0] = adjust_address (operands[0], QImode, 1);
1783 operands[1] = adjust_address (operands[1], QImode, 1);
1786 (define_insn "bclrhi_msx"
1787 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1788 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1789 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1792 [(set_attr "length" "8")])
1793 (define_insn "*andqi3_2"
1794 [(set (match_operand:QI 0 "bit_operand" "=rQ,r")
1795 (and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
1796 (match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))]
1801 [(set_attr "length" "*,8")
1802 (set_attr "length_table" "logicb,*")
1803 (set_attr "cc" "set_znv,none_0hit")])
1805 (define_insn "andqi3_1"
1806 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1807 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1808 (match_operand:QI 2 "h8300_src_operand" "rn,n")))]
1809 "register_operand (operands[0], QImode)
1810 || single_zero_operand (operands[2], QImode)"
1814 [(set_attr "length" "2,8")
1815 (set_attr "cc" "set_znv,none_0hit")])
1817 (define_expand "andqi3"
1818 [(set (match_operand:QI 0 "register_operand" "")
1819 (and:QI (match_operand:QI 1 "register_operand" "")
1820 (match_operand:QI 2 "h8300_src_operand" "")))]
1824 (define_expand "andhi3"
1825 [(set (match_operand:HI 0 "register_operand" "")
1826 (and:HI (match_operand:HI 1 "register_operand" "")
1827 (match_operand:HI 2 "h8300_src_operand" "")))]
1831 (define_insn "*andorqi3"
1832 [(set (match_operand:QI 0 "register_operand" "=r")
1833 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1834 (match_operand:QI 3 "single_one_operand" "n"))
1835 (match_operand:QI 1 "register_operand" "0")))]
1837 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1838 [(set_attr "length" "6")])
1840 (define_insn "*andorhi3"
1841 [(set (match_operand:HI 0 "register_operand" "=r")
1842 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1843 (match_operand:HI 3 "single_one_operand" "n"))
1844 (match_operand:HI 1 "register_operand" "0")))]
1848 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1849 if (INTVAL (operands[3]) > 128)
1851 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1852 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1854 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1856 [(set_attr "length" "6")])
1858 (define_insn "*andorsi3"
1859 [(set (match_operand:SI 0 "register_operand" "=r")
1860 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1861 (match_operand:SI 3 "single_one_operand" "n"))
1862 (match_operand:SI 1 "register_operand" "0")))]
1863 "(INTVAL (operands[3]) & 0xffff) != 0"
1866 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1867 if (INTVAL (operands[3]) > 128)
1869 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1870 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1872 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1874 [(set_attr "length" "6")])
1876 (define_insn "*andorsi3_shift_8"
1877 [(set (match_operand:SI 0 "register_operand" "=r")
1878 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1881 (match_operand:SI 1 "register_operand" "0")))]
1884 [(set_attr "length" "2")])
1886 (define_expand "andsi3"
1887 [(set (match_operand:SI 0 "register_operand" "")
1888 (and:SI (match_operand:SI 1 "register_operand" "")
1889 (match_operand:SI 2 "h8300_src_operand" "")))]
1893 ;; ----------------------------------------------------------------------
1895 ;; ----------------------------------------------------------------------
1896 (define_insn "bsetqi_msx"
1897 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1898 (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1899 (match_operand:QI 2 "single_one_operand" "Y2")))]
1902 [(set_attr "length" "8")])
1905 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1906 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1907 (match_operand:HI 2 "single_one_operand" "Y2")))]
1910 (ior:QI (match_dup 1)
1913 operands[0] = adjust_address (operands[0], QImode, 1);
1914 operands[1] = adjust_address (operands[1], QImode, 1);
1917 (define_insn "bsethi_msx"
1918 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1919 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1920 (match_operand:HI 2 "single_one_operand" "Y2")))]
1923 [(set_attr "length" "8")])
1925 (define_insn "iorqi3_1"
1926 [(set (match_operand:QI 0 "bit_operand" "=rQ,U")
1927 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1928 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1929 "TARGET_H8300SX || register_operand (operands[0], QImode)
1930 || single_one_operand (operands[2], QImode)"
1934 [(set_attr "length" "*,8")
1935 (set_attr "length_table" "logicb,*")
1936 (set_attr "cc" "set_znv,none_0hit")])
1938 (define_expand "iorqi3"
1939 [(set (match_operand:QI 0 "register_operand" "")
1940 (ior:QI (match_operand:QI 1 "register_operand" "")
1941 (match_operand:QI 2 "h8300_src_operand" "")))]
1945 (define_expand "iorhi3"
1946 [(set (match_operand:HI 0 "register_operand" "")
1947 (ior:HI (match_operand:HI 1 "register_operand" "")
1948 (match_operand:HI 2 "h8300_src_operand" "")))]
1952 (define_expand "iorsi3"
1953 [(set (match_operand:SI 0 "register_operand" "")
1954 (ior:SI (match_operand:SI 1 "register_operand" "")
1955 (match_operand:SI 2 "h8300_src_operand" "")))]
1959 ;; ----------------------------------------------------------------------
1961 ;; ----------------------------------------------------------------------
1962 (define_insn "bnotqi_msx"
1963 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1964 (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1965 (match_operand:QI 2 "single_one_operand" "Y2")))]
1968 [(set_attr "length" "8")])
1971 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1972 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1973 (match_operand:HI 2 "single_one_operand" "Y2")))]
1976 (xor:QI (match_dup 1)
1979 operands[0] = adjust_address (operands[0], QImode, 1);
1980 operands[1] = adjust_address (operands[1], QImode, 1);
1983 (define_insn "bnothi_msx"
1984 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1985 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1986 (match_operand:HI 2 "single_one_operand" "Y2")))]
1989 [(set_attr "length" "8")])
1991 (define_insn "xorqi3_1"
1992 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1993 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1994 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1995 "TARGET_H8300SX || register_operand (operands[0], QImode)
1996 || single_one_operand (operands[2], QImode)"
2000 [(set_attr "length" "*,8")
2001 (set_attr "length_table" "logicb,*")
2002 (set_attr "cc" "set_znv,none_0hit")])
2004 (define_expand "xorqi3"
2005 [(set (match_operand:QI 0 "register_operand" "")
2006 (xor:QI (match_operand:QI 1 "register_operand" "")
2007 (match_operand:QI 2 "h8300_src_operand" "")))]
2011 (define_expand "xorhi3"
2012 [(set (match_operand:HI 0 "register_operand" "")
2013 (xor:HI (match_operand:HI 1 "register_operand" "")
2014 (match_operand:HI 2 "h8300_src_operand" "")))]
2018 (define_expand "xorsi3"
2019 [(set (match_operand:SI 0 "register_operand" "")
2020 (xor:SI (match_operand:SI 1 "register_operand" "")
2021 (match_operand:SI 2 "h8300_src_operand" "")))]
2025 ;; ----------------------------------------------------------------------
2026 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
2027 ;; ----------------------------------------------------------------------
2029 ;; We need a separate pattern here because machines other than the
2030 ;; original H8300 don't have to split the 16-bit operand into a pair
2031 ;; of high/low instructions, so we can accept literal addresses, that
2032 ;; have to be loaded into a register on H8300.
2033 (define_insn "*logicalhi3_sn"
2034 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2035 (match_operator:HI 3 "bit_operator"
2036 [(match_operand:HI 1 "h8300_dst_operand" "%0")
2037 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
2038 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
2039 "* return output_logical_op (HImode, operands);"
2040 [(set (attr "length")
2041 (symbol_ref "compute_logical_op_length (HImode, operands)"))
2043 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2045 (define_insn "*logicalsi3_sn"
2046 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2047 (match_operator:SI 3 "bit_operator"
2048 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2049 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2050 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
2051 "* return output_logical_op (SImode, operands);"
2052 [(set (attr "length")
2053 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2055 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2057 (define_insn "*logicalhi3"
2058 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2059 (match_operator:HI 3 "bit_operator"
2060 [(match_operand:HI 1 "h8300_dst_operand" "%0")
2061 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
2062 "h8300_operands_match_p (operands)"
2063 "* return output_logical_op (HImode, operands);"
2064 [(set (attr "length")
2065 (symbol_ref "compute_logical_op_length (HImode, operands)"))
2067 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2069 (define_insn "*logicalsi3"
2070 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2071 (match_operator:SI 3 "bit_operator"
2072 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2073 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2074 "h8300_operands_match_p (operands)"
2075 "* return output_logical_op (SImode, operands);"
2076 [(set (attr "length")
2077 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2079 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2081 ;; ----------------------------------------------------------------------
2082 ;; NEGATION INSTRUCTIONS
2083 ;; ----------------------------------------------------------------------
2085 (define_expand "negqi2"
2086 [(set (match_operand:QI 0 "register_operand" "")
2087 (neg:QI (match_operand:QI 1 "register_operand" "")))]
2091 (define_insn "*negqi2"
2092 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2093 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2096 [(set_attr "length_table" "unary")
2097 (set_attr "cc" "set_zn")])
2099 (define_expand "neghi2"
2100 [(set (match_operand:HI 0 "register_operand" "")
2101 (neg:HI (match_operand:HI 1 "register_operand" "")))]
2107 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
2112 (define_expand "neghi2_h8300"
2114 (not:HI (match_operand:HI 1 "register_operand" "")))
2115 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
2116 (set (match_operand:HI 0 "register_operand" "")
2119 "operands[2] = gen_reg_rtx (HImode);")
2121 (define_insn "*neghi2_h8300hs"
2122 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2123 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2124 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2126 [(set_attr "length_table" "unary")
2127 (set_attr "cc" "set_zn")])
2129 (define_expand "negsi2"
2130 [(set (match_operand:SI 0 "register_operand" "")
2131 (neg:SI (match_operand:SI 1 "register_operand" "")))]
2137 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
2142 (define_expand "negsi2_h8300"
2144 (not:SI (match_operand:SI 1 "register_operand" "")))
2145 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
2146 (set (match_operand:SI 0 "register_operand" "")
2149 "operands[2] = gen_reg_rtx (SImode);")
2151 (define_insn "*negsi2_h8300hs"
2152 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2153 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2154 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2156 [(set_attr "length_table" "unary")
2157 (set_attr "cc" "set_zn")])
2159 (define_expand "negsf2"
2160 [(set (match_operand:SF 0 "register_operand" "")
2161 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2165 (define_insn "*negsf2_h8300"
2166 [(set (match_operand:SF 0 "register_operand" "=r")
2167 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2170 [(set_attr "length" "2")])
2172 (define_insn "*negsf2_h8300hs"
2173 [(set (match_operand:SF 0 "register_operand" "=r")
2174 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2175 "TARGET_H8300H || TARGET_H8300S"
2176 "xor.w\\t#32768,%e0"
2177 [(set_attr "length" "4")])
2179 ;; ----------------------------------------------------------------------
2180 ;; ABSOLUTE VALUE INSTRUCTIONS
2181 ;; ----------------------------------------------------------------------
2183 (define_expand "abssf2"
2184 [(set (match_operand:SF 0 "register_operand" "")
2185 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2189 (define_insn "*abssf2_h8300"
2190 [(set (match_operand:SF 0 "register_operand" "=r")
2191 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2194 [(set_attr "length" "2")])
2196 (define_insn "*abssf2_h8300hs"
2197 [(set (match_operand:SF 0 "register_operand" "=r")
2198 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2199 "TARGET_H8300H || TARGET_H8300S"
2200 "and.w\\t#32767,%e0"
2201 [(set_attr "length" "4")])
2203 ;; ----------------------------------------------------------------------
2205 ;; ----------------------------------------------------------------------
2207 (define_expand "one_cmplqi2"
2208 [(set (match_operand:QI 0 "register_operand" "")
2209 (not:QI (match_operand:QI 1 "register_operand" "")))]
2213 (define_insn "*one_cmplqi2"
2214 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2215 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2218 [(set_attr "length_table" "unary")
2219 (set_attr "cc" "set_znv")])
2221 (define_expand "one_cmplhi2"
2222 [(set (match_operand:HI 0 "register_operand" "")
2223 (not:HI (match_operand:HI 1 "register_operand" "")))]
2227 (define_insn "*one_cmplhi2_h8300"
2228 [(set (match_operand:HI 0 "register_operand" "=r")
2229 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2232 [(set_attr "length" "4")])
2234 (define_insn "*one_cmplhi2_h8300hs"
2235 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2236 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2237 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2239 [(set_attr "cc" "set_znv")
2240 (set_attr "length_table" "unary")])
2242 (define_expand "one_cmplsi2"
2243 [(set (match_operand:SI 0 "register_operand" "")
2244 (not:SI (match_operand:SI 1 "register_operand" "")))]
2248 (define_insn "*one_cmplsi2_h8300"
2249 [(set (match_operand:SI 0 "register_operand" "=r")
2250 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2252 "not %w0\;not %x0\;not %y0\;not %z0"
2253 [(set_attr "length" "8")])
2255 (define_insn "*one_cmplsi2_h8300hs"
2256 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2257 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2258 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2260 [(set_attr "cc" "set_znv")
2261 (set_attr "length_table" "unary")])
2263 ;; ----------------------------------------------------------------------
2264 ;; JUMP INSTRUCTIONS
2265 ;; ----------------------------------------------------------------------
2267 ;; Conditional jump instructions
2269 (define_expand "cbranchqi4"
2270 [(use (match_operator 0 "ordered_comparison_operator"
2271 [(match_operand:QI 1 "h8300_dst_operand" "")
2272 (match_operand:QI 2 "h8300_src_operand" "")]))
2273 (use (match_operand 3 ""))]
2275 "h8300_expand_branch (operands); DONE;")
2277 (define_expand "cbranchhi4"
2278 [(use (match_operator 0 "ordered_comparison_operator"
2279 [(match_operand:HI 1 "h8300_dst_operand" "")
2280 (match_operand:HI 2 "h8300_src_operand" "")]))
2281 (use (match_operand 3 ""))]
2285 /* Force operand1 into a register if we're compiling
2287 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
2289 operands[2] = force_reg (HImode, operands[2]);
2290 h8300_expand_branch (operands); DONE;
2293 (define_expand "cbranchsi4"
2294 [(use (match_operator 0 "ordered_comparison_operator"
2295 [(match_operand:SI 1 "h8300_dst_operand" "")
2296 (match_operand:SI 2 "h8300_src_operand" "")]))
2297 (use (match_operand 3 ""))]
2298 "TARGET_H8300H || TARGET_H8300S"
2299 "h8300_expand_branch (operands); DONE;")
2301 (define_insn "branch_true"
2303 (if_then_else (match_operator 1 "comparison_operator"
2304 [(cc0) (const_int 0)])
2305 (label_ref (match_operand 0 "" ""))
2310 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2311 && (GET_CODE (operands[1]) == GT
2312 || GET_CODE (operands[1]) == GE
2313 || GET_CODE (operands[1]) == LE
2314 || GET_CODE (operands[1]) == LT))
2316 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2320 if (get_attr_length (insn) == 2)
2321 return \"b%j1 %l0\";
2322 else if (get_attr_length (insn) == 4)
2323 return \"b%j1 %l0:16\";
2325 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2327 [(set_attr "type" "branch")
2328 (set_attr "cc" "none")])
2330 (define_insn "branch_false"
2332 (if_then_else (match_operator 1 "comparison_operator"
2333 [(cc0) (const_int 0)])
2335 (label_ref (match_operand 0 "" ""))))]
2339 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2340 && (GET_CODE (operands[1]) == GT
2341 || GET_CODE (operands[1]) == GE
2342 || GET_CODE (operands[1]) == LE
2343 || GET_CODE (operands[1]) == LT))
2345 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2349 if (get_attr_length (insn) == 2)
2350 return \"b%k1 %l0\";
2351 else if (get_attr_length (insn) == 4)
2352 return \"b%k1 %l0:16\";
2354 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2356 [(set_attr "type" "branch")
2357 (set_attr "cc" "none")])
2359 (define_insn "*brabc"
2362 (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2364 (match_operand:QI 2 "immediate_operand" "n"))
2366 (label_ref (match_operand 0 "" ""))
2371 switch (get_attr_length (insn)
2372 - h8300_insn_length_from_table (insn, operands))
2375 return \"bra/bc %2,%R1,%l0\";
2378 return \"bra/bc %2,%R1,%l0:16\";
2381 return \"bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2384 [(set_attr "type" "bitbranch")
2385 (set_attr "length_table" "bitbranch")
2386 (set_attr "cc" "none")])
2388 (define_insn "*brabs"
2391 (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2393 (match_operand:QI 2 "immediate_operand" "n"))
2395 (label_ref (match_operand 0 "" ""))
2400 switch (get_attr_length (insn)
2401 - h8300_insn_length_from_table (insn, operands))
2404 return \"bra/bs %2,%R1,%l0\";
2407 return \"bra/bs %2,%R1,%l0:16\";
2410 return \"bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2413 [(set_attr "type" "bitbranch")
2414 (set_attr "length_table" "bitbranch")
2415 (set_attr "cc" "none")])
2417 ;; Unconditional and other jump instructions.
2421 (label_ref (match_operand 0 "" "")))]
2425 if (final_sequence != 0)
2427 if (get_attr_length (insn) == 2)
2428 return \"bra/s %l0\";
2431 /* The branch isn't short enough to use bra/s. Output the
2432 branch and delay slot in their normal order.
2434 If this is a backward branch, it will now be branching two
2435 bytes further than previously thought. The length-based
2436 test for bra vs. jump is very conservative though, so the
2437 branch will still be within range. */
2441 vec = XVEC (final_sequence, 0);
2443 final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 1, & seen);
2444 final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 1, & seen);
2445 INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1;
2449 else if (get_attr_length (insn) == 2)
2451 else if (get_attr_length (insn) == 4)
2452 return \"bra %l0:16\";
2454 return \"jmp @%l0\";
2456 [(set_attr "type" "branch")
2457 (set (attr "delay_slot")
2458 (if_then_else (ne (symbol_ref "TARGET_H8300SX") (const_int 0))
2459 (const_string "jump")
2460 (const_string "none")))
2461 (set_attr "cc" "none")])
2463 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2465 (define_expand "tablejump"
2466 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2467 (use (label_ref (match_operand 1 "" "")))])]
2471 (define_insn "*tablejump_h8300"
2472 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2473 (use (label_ref (match_operand 1 "" "")))]
2476 [(set_attr "cc" "none")
2477 (set_attr "length" "2")])
2479 (define_insn "*tablejump_h8300hs_advanced"
2480 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2481 (use (label_ref (match_operand 1 "" "")))]
2482 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2484 [(set_attr "cc" "none")
2485 (set_attr "length" "2")])
2487 (define_insn "*tablejump_h8300hs_normal"
2488 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2489 (use (label_ref (match_operand 1 "" "")))]
2490 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2492 [(set_attr "cc" "none")
2493 (set_attr "length" "2")])
2495 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2497 (define_expand "indirect_jump"
2498 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2502 (define_insn "*indirect_jump_h8300"
2503 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2506 [(set_attr "cc" "none")
2507 (set_attr "length" "2")])
2509 (define_insn "*indirect_jump_h8300hs_advanced"
2510 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2511 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2513 [(set_attr "cc" "none")
2514 (set_attr "length" "2")])
2516 (define_insn "*indirect_jump_h8300hs_normal"
2517 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2518 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2520 [(set_attr "cc" "none")
2521 (set_attr "length" "2")])
2523 ;; Call subroutine with no return value.
2525 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2528 [(call (match_operand:QI 0 "call_insn_operand" "or")
2529 (match_operand:HI 1 "general_operand" "g"))]
2533 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2534 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
2535 return \"jsr\\t@%0:8\";
2537 return \"jsr\\t%0\";
2539 [(set_attr "type" "call")
2540 (set (attr "length")
2541 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2545 ;; Call subroutine, returning value in operand 0
2546 ;; (which must be a hard register).
2548 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2550 (define_insn "call_value"
2551 [(set (match_operand 0 "" "=r")
2552 (call (match_operand:QI 1 "call_insn_operand" "or")
2553 (match_operand:HI 2 "general_operand" "g")))]
2557 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2558 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
2559 return \"jsr\\t@%1:8\";
2561 return \"jsr\\t%1\";
2563 [(set_attr "type" "call")
2564 (set (attr "length")
2565 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2573 [(set_attr "cc" "none")
2574 (set_attr "length" "2")])
2576 ;; ----------------------------------------------------------------------
2577 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2578 ;; ----------------------------------------------------------------------
2580 (define_expand "push_h8300"
2581 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2582 (match_operand:HI 0 "register_operand" ""))]
2586 (define_expand "push_h8300hs_advanced"
2587 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2588 (match_operand:SI 0 "register_operand" ""))]
2589 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2592 (define_expand "push_h8300hs_normal"
2593 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2594 (match_operand:SI 0 "register_operand" ""))]
2595 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2598 (define_expand "pop_h8300"
2599 [(set (match_operand:HI 0 "register_operand" "")
2600 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2604 (define_expand "pop_h8300hs_advanced"
2605 [(set (match_operand:SI 0 "register_operand" "")
2606 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2607 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2610 (define_expand "pop_h8300hs_normal"
2611 [(set (match_operand:SI 0 "register_operand" "")
2612 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2613 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2616 (define_insn "ldm_h8300sx"
2617 [(match_parallel 0 "h8300_ldm_parallel"
2618 [(set (match_operand:SI 1 "register_operand" "")
2619 (match_operand:SI 2 "memory_operand" ""))])]
2622 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2623 XVECLEN (operands[0], 0) - 2));
2624 return "ldm.l\t@er7+,%S1-%S3";
2626 [(set_attr "cc" "none")
2627 (set_attr "length" "4")])
2629 (define_insn "stm_h8300sx"
2630 [(match_parallel 0 "h8300_stm_parallel"
2631 [(set (match_operand:SI 1 "memory_operand" "")
2632 (match_operand:SI 2 "register_operand" ""))])]
2635 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2636 XVECLEN (operands[0], 0) - 2));
2637 return "stm.l\t%S2-%S3,@-er7";
2639 [(set_attr "cc" "none")
2640 (set_attr "length" "4")])
2642 (define_insn "return_h8sx"
2643 [(match_parallel 0 "h8300_return_parallel"
2645 (set (match_operand:SI 1 "register_operand" "")
2646 (match_operand:SI 2 "memory_operand" ""))])]
2649 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2650 XVECLEN (operands[0], 0) - 2));
2651 if (h8300_current_function_interrupt_function_p ())
2652 return "rte/l\t%S1-%S3";
2654 return "rts/l\t%S1-%S3";
2656 [(set_attr "cc" "none")
2657 (set_attr "can_delay" "no")
2658 (set_attr "length" "2")])
2660 (define_expand "return"
2662 "h8300_can_use_return_insn_p ()"
2665 (define_insn "*return_1"
2670 if (h8300_current_function_interrupt_function_p ())
2675 [(set_attr "cc" "none")
2676 (set_attr "can_delay" "no")
2677 (set_attr "length" "2")])
2679 (define_expand "prologue"
2682 "h8300_expand_prologue (); DONE;")
2684 (define_expand "epilogue"
2687 "h8300_expand_epilogue (); DONE;")
2689 (define_insn "monitor_prologue"
2690 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2695 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2696 else if (TARGET_H8300H)
2697 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2698 else if (TARGET_H8300S)
2699 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2702 [(set_attr "length" "20")])
2704 ;; ----------------------------------------------------------------------
2705 ;; EXTEND INSTRUCTIONS
2706 ;; ----------------------------------------------------------------------
2708 (define_expand "zero_extendqihi2"
2709 [(set (match_operand:HI 0 "register_operand" "")
2710 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2714 (define_insn "*zero_extendqihi2_h8300"
2715 [(set (match_operand:HI 0 "register_operand" "=r,r")
2716 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2721 [(set_attr "length" "2,10")])
2723 (define_insn "*zero_extendqihi2_h8300hs"
2724 [(set (match_operand:HI 0 "register_operand" "=r,r")
2725 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2726 "TARGET_H8300H || TARGET_H8300S"
2730 [(set_attr "length" "2,10")
2731 (set_attr "cc" "set_znv,set_znv")])
2733 ;; Split the zero extension of a general operand (actually a memory
2734 ;; operand) into a load of the operand and the actual zero extension
2735 ;; so that 1) the length will be accurate, and 2) the zero extensions
2736 ;; appearing at the end of basic blocks may be merged.
2739 [(set (match_operand:HI 0 "register_operand" "")
2740 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2745 (zero_extend:HI (match_dup 2)))]
2746 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2748 (define_expand "zero_extendqisi2"
2749 [(set (match_operand:SI 0 "register_operand" "")
2750 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2754 operands[1] = force_reg (QImode, operands[1]);
2757 (define_insn "*zero_extendqisi2_h8300"
2758 [(set (match_operand:SI 0 "register_operand" "=r,r")
2759 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2762 mov.b #0,%x0\;sub.w %e0,%e0
2763 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2764 [(set_attr "length" "4,8")])
2766 (define_insn "*zero_extendqisi2_h8300hs"
2767 [(set (match_operand:SI 0 "register_operand" "=r,r")
2768 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2769 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2773 [(set (match_operand:SI 0 "register_operand" "")
2774 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2775 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2776 && reg_overlap_mentioned_p (operands[0], operands[1])
2777 && reload_completed"
2781 (zero_extend:HI (match_dup 2)))
2783 (zero_extend:SI (match_dup 3)))]
2784 "operands[2] = gen_lowpart (QImode, operands[0]);
2785 operands[3] = gen_lowpart (HImode, operands[0]);")
2788 [(set (match_operand:SI 0 "register_operand" "")
2789 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2790 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2791 && !reg_overlap_mentioned_p (operands[0], operands[1])
2792 && reload_completed"
2795 (set (strict_low_part (match_dup 2))
2797 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2799 (define_insn "*zero_extendqisi2_h8sx"
2800 [(set (match_operand:SI 0 "register_operand" "=r")
2801 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2804 [(set_attr "length" "2")
2805 (set_attr "cc" "set_znv")])
2807 (define_expand "zero_extendhisi2"
2808 [(set (match_operand:SI 0 "register_operand" "")
2809 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2813 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2814 (define_insn "*zero_extendhisi2_h8300"
2815 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2816 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2820 mov.w %f1,%f0\;sub.w %e0,%e0
2821 mov.w %e1,%f0\;sub.w %e0,%e0"
2822 [(set_attr "length" "2,4,6")])
2824 (define_insn "*zero_extendhisi2_h8300hs"
2825 [(set (match_operand:SI 0 "register_operand" "=r")
2826 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2827 "TARGET_H8300H || TARGET_H8300S"
2829 [(set_attr "length" "2")
2830 (set_attr "cc" "set_znv")])
2832 (define_expand "extendqihi2"
2833 [(set (match_operand:HI 0 "register_operand" "")
2834 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2838 (define_insn "*extendqihi2_h8300"
2839 [(set (match_operand:HI 0 "register_operand" "=r,r")
2840 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2843 bld #7,%s0\;subx %t0,%t0
2844 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2845 [(set_attr "length" "4,8")])
2847 (define_insn "*extendqihi2_h8300hs"
2848 [(set (match_operand:HI 0 "register_operand" "=r")
2849 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2850 "TARGET_H8300H || TARGET_H8300S"
2852 [(set_attr "length" "2")
2853 (set_attr "cc" "set_znv")])
2855 (define_expand "extendqisi2"
2856 [(set (match_operand:SI 0 "register_operand" "")
2857 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2861 (define_insn "*extendqisi2_h8300"
2862 [(set (match_operand:SI 0 "register_operand" "=r,r")
2863 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2866 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2867 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2868 [(set_attr "length" "8,12")])
2870 ;; The following pattern is needed because without the pattern, the
2871 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2872 ;; shifts, one ashift and one ashiftrt.
2874 (define_insn_and_split "*extendqisi2_h8300hs"
2875 [(set (match_operand:SI 0 "register_operand" "=r")
2876 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2877 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2879 "&& reload_completed"
2881 (sign_extend:HI (match_dup 1)))
2883 (sign_extend:SI (match_dup 2)))]
2884 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2886 (define_insn "*extendqisi2_h8sx"
2887 [(set (match_operand:SI 0 "register_operand" "=r")
2888 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2891 [(set_attr "length" "2")
2892 (set_attr "cc" "set_znv")])
2894 (define_expand "extendhisi2"
2895 [(set (match_operand:SI 0 "register_operand" "")
2896 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2900 (define_insn "*extendhisi2_h8300"
2901 [(set (match_operand:SI 0 "register_operand" "=r,r")
2902 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2905 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2906 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2907 [(set_attr "length" "6,10")])
2909 (define_insn "*extendhisi2_h8300hs"
2910 [(set (match_operand:SI 0 "register_operand" "=r")
2911 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2912 "TARGET_H8300H || TARGET_H8300S"
2914 [(set_attr "length" "2")
2915 (set_attr "cc" "set_znv")])
2917 ;; ----------------------------------------------------------------------
2919 ;; ----------------------------------------------------------------------
2921 ;; We make some attempt to provide real efficient shifting. One example is
2922 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2923 ;; reg and moving 0 into the former reg.
2925 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2926 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2927 ;; give the optimizer more cracks at the code. However, we wish to do things
2928 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2929 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2930 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2931 ;; to detect cases it can optimize.
2933 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2934 ;; easier "do it at insn emit time" route.
2938 (define_expand "ashlqi3"
2939 [(set (match_operand:QI 0 "register_operand" "")
2940 (ashift:QI (match_operand:QI 1 "register_operand" "")
2941 (match_operand:QI 2 "nonmemory_operand" "")))]
2943 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;")
2945 (define_expand "ashrqi3"
2946 [(set (match_operand:QI 0 "register_operand" "")
2947 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2948 (match_operand:QI 2 "nonmemory_operand" "")))]
2950 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;")
2952 (define_expand "lshrqi3"
2953 [(set (match_operand:QI 0 "register_operand" "")
2954 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2955 (match_operand:QI 2 "nonmemory_operand" "")))]
2957 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;")
2960 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2961 (match_operator:QI 3 "h8sx_unary_shift_operator"
2962 [(match_operand:QI 1 "h8300_dst_operand" "0")
2963 (match_operand:QI 2 "const_int_operand" "")]))]
2964 "h8300_operands_match_p (operands)"
2965 { return output_h8sx_shift (operands, 'b', 'X'); }
2966 [(set_attr "length_table" "unary")
2967 (set_attr "cc" "set_znv")])
2970 [(set (match_operand:QI 0 "register_operand" "=r")
2971 (match_operator:QI 3 "h8sx_binary_shift_operator"
2972 [(match_operand:QI 1 "register_operand" "0")
2973 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2975 { return output_h8sx_shift (operands, 'b', 'X'); }
2976 [(set_attr "length" "4")
2977 (set_attr "cc" "set_znv")])
2979 (define_insn "*shiftqi"
2980 [(set (match_operand:QI 0 "register_operand" "=r,r")
2981 (match_operator:QI 3 "nshift_operator"
2982 [ (match_operand:QI 1 "register_operand" "0,0")
2983 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2984 (clobber (match_scratch:QI 4 "=X,&r"))]
2986 "* return output_a_shift (operands);"
2987 [(set (attr "length")
2988 (symbol_ref "compute_a_shift_length (insn, operands)"))
2990 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2994 (define_expand "ashlhi3"
2995 [(set (match_operand:HI 0 "register_operand" "")
2996 (ashift:HI (match_operand:HI 1 "register_operand" "")
2997 (match_operand:QI 2 "nonmemory_operand" "")))]
2999 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;")
3001 (define_expand "lshrhi3"
3002 [(set (match_operand:HI 0 "register_operand" "")
3003 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
3004 (match_operand:QI 2 "nonmemory_operand" "")))]
3006 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;")
3008 (define_expand "ashrhi3"
3009 [(set (match_operand:HI 0 "register_operand" "")
3010 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
3011 (match_operand:QI 2 "nonmemory_operand" "")))]
3013 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;")
3016 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
3017 (match_operator:HI 3 "h8sx_unary_shift_operator"
3018 [(match_operand:HI 1 "h8300_dst_operand" "0")
3019 (match_operand:QI 2 "const_int_operand" "")]))]
3020 "h8300_operands_match_p (operands)"
3021 { return output_h8sx_shift (operands, 'w', 'T'); }
3022 [(set_attr "length_table" "unary")
3023 (set_attr "cc" "set_znv")])
3026 [(set (match_operand:HI 0 "register_operand" "=r")
3027 (match_operator:HI 3 "h8sx_binary_shift_operator"
3028 [(match_operand:HI 1 "register_operand" "0")
3029 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
3031 { return output_h8sx_shift (operands, 'w', 'T'); }
3032 [(set_attr "length" "4")
3033 (set_attr "cc" "set_znv")])
3035 (define_insn "*shifthi"
3036 [(set (match_operand:HI 0 "register_operand" "=r,r")
3037 (match_operator:HI 3 "nshift_operator"
3038 [ (match_operand:HI 1 "register_operand" "0,0")
3039 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
3040 (clobber (match_scratch:QI 4 "=X,&r"))]
3042 "* return output_a_shift (operands);"
3043 [(set (attr "length")
3044 (symbol_ref "compute_a_shift_length (insn, operands)"))
3046 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3050 (define_expand "ashlsi3"
3051 [(set (match_operand:SI 0 "register_operand" "")
3052 (ashift:SI (match_operand:SI 1 "register_operand" "")
3053 (match_operand:QI 2 "nonmemory_operand" "")))]
3055 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;")
3057 (define_expand "lshrsi3"
3058 [(set (match_operand:SI 0 "register_operand" "")
3059 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
3060 (match_operand:QI 2 "nonmemory_operand" "")))]
3062 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;")
3064 (define_expand "ashrsi3"
3065 [(set (match_operand:SI 0 "register_operand" "")
3066 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
3067 (match_operand:QI 2 "nonmemory_operand" "")))]
3069 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;")
3072 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
3073 (match_operator:SI 3 "h8sx_unary_shift_operator"
3074 [(match_operand:SI 1 "h8300_dst_operand" "0")
3075 (match_operand:QI 2 "const_int_operand" "")]))]
3076 "h8300_operands_match_p (operands)"
3077 { return output_h8sx_shift (operands, 'l', 'S'); }
3078 [(set_attr "length_table" "unary")
3079 (set_attr "cc" "set_znv")])
3082 [(set (match_operand:SI 0 "register_operand" "=r")
3083 (match_operator:SI 3 "h8sx_binary_shift_operator"
3084 [(match_operand:SI 1 "register_operand" "0")
3085 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
3087 { return output_h8sx_shift (operands, 'l', 'S'); }
3088 [(set_attr "length" "4")
3089 (set_attr "cc" "set_znv")])
3091 (define_insn "*shiftsi"
3092 [(set (match_operand:SI 0 "register_operand" "=r,r")
3093 (match_operator:SI 3 "nshift_operator"
3094 [ (match_operand:SI 1 "register_operand" "0,0")
3095 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
3096 (clobber (match_scratch:QI 4 "=X,&r"))]
3098 "* return output_a_shift (operands);"
3099 [(set (attr "length")
3100 (symbol_ref "compute_a_shift_length (insn, operands)"))
3102 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3104 ;; Split a variable shift into a loop. If the register containing
3105 ;; the shift count dies, then we just use that register.
3108 [(set (match_operand 0 "register_operand" "")
3109 (match_operator 2 "nshift_operator"
3111 (match_operand:QI 1 "register_operand" "")]))
3112 (clobber (match_operand:QI 3 "register_operand" ""))]
3114 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3115 [(set (cc0) (compare (match_dup 1)
3118 (if_then_else (le (cc0) (const_int 0))
3119 (label_ref (match_dup 5))
3124 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3125 (clobber (scratch:QI))])
3127 (plus:QI (match_dup 1) (const_int -1)))
3128 (set (cc0) (compare (match_dup 1)
3131 (if_then_else (ne (cc0) (const_int 0))
3132 (label_ref (match_dup 4))
3135 "operands[4] = gen_label_rtx ();
3136 operands[5] = gen_label_rtx ();")
3139 [(set (match_operand 0 "register_operand" "")
3140 (match_operator 2 "nshift_operator"
3142 (match_operand:QI 1 "register_operand" "")]))
3143 (clobber (match_operand:QI 3 "register_operand" ""))]
3145 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3148 (set (cc0) (compare (match_dup 3)
3151 (if_then_else (le (cc0) (const_int 0))
3152 (label_ref (match_dup 5))
3157 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3158 (clobber (scratch:QI))])
3160 (plus:QI (match_dup 3) (const_int -1)))
3161 (set (cc0) (compare (match_dup 3)
3164 (if_then_else (ne (cc0) (const_int 0))
3165 (label_ref (match_dup 4))
3168 "operands[4] = gen_label_rtx ();
3169 operands[5] = gen_label_rtx ();")
3171 ;; ----------------------------------------------------------------------
3173 ;; ----------------------------------------------------------------------
3175 (define_expand "rotlqi3"
3176 [(set (match_operand:QI 0 "register_operand" "")
3177 (rotate:QI (match_operand:QI 1 "register_operand" "")
3178 (match_operand:QI 2 "nonmemory_operand" "")))]
3180 "if (expand_a_rotate (operands)) DONE;")
3182 (define_insn "rotlqi3_1"
3183 [(set (match_operand:QI 0 "register_operand" "=r")
3184 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3185 (match_operand:QI 2 "immediate_operand" "")))]
3187 "* return output_a_rotate (ROTATE, operands);"
3188 [(set (attr "length")
3189 (symbol_ref "compute_a_rotate_length (operands)"))])
3191 (define_expand "rotlhi3"
3192 [(set (match_operand:HI 0 "register_operand" "")
3193 (rotate:HI (match_operand:HI 1 "register_operand" "")
3194 (match_operand:QI 2 "nonmemory_operand" "")))]
3196 "if (expand_a_rotate (operands)) DONE;")
3198 (define_insn "rotlhi3_1"
3199 [(set (match_operand:HI 0 "register_operand" "=r")
3200 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3201 (match_operand:QI 2 "immediate_operand" "")))]
3203 "* return output_a_rotate (ROTATE, operands);"
3204 [(set (attr "length")
3205 (symbol_ref "compute_a_rotate_length (operands)"))])
3207 (define_expand "rotlsi3"
3208 [(set (match_operand:SI 0 "register_operand" "")
3209 (rotate:SI (match_operand:SI 1 "register_operand" "")
3210 (match_operand:QI 2 "nonmemory_operand" "")))]
3211 "TARGET_H8300H || TARGET_H8300S"
3212 "if (expand_a_rotate (operands)) DONE;")
3214 (define_insn "rotlsi3_1"
3215 [(set (match_operand:SI 0 "register_operand" "=r")
3216 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3217 (match_operand:QI 2 "immediate_operand" "")))]
3218 "TARGET_H8300H || TARGET_H8300S"
3219 "* return output_a_rotate (ROTATE, operands);"
3220 [(set (attr "length")
3221 (symbol_ref "compute_a_rotate_length (operands)"))])
3223 ;; -----------------------------------------------------------------
3225 ;; -----------------------------------------------------------------
3226 ;; The H8/300 has given 1/8th of its opcode space to bitfield
3227 ;; instructions so let's use them as well as we can.
3229 ;; You'll never believe all these patterns perform one basic action --
3230 ;; load a bit from the source, optionally invert the bit, then store it
3231 ;; in the destination (which is known to be zero).
3233 ;; Combine obviously need some work to better identify this situation and
3234 ;; canonicalize the form better.
3237 ;; Normal loads with a 16bit destination.
3241 [(set (match_operand:HI 0 "register_operand" "=&r")
3242 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3244 (match_operand:HI 2 "immediate_operand" "n")))]
3246 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
3247 [(set_attr "length" "6")])
3250 ;; Inverted loads with a 16bit destination.
3254 [(set (match_operand:HI 0 "register_operand" "=&r")
3255 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3256 (match_operand:HI 3 "const_int_operand" "n"))
3258 (match_operand:HI 2 "const_int_operand" "n")))]
3259 "(TARGET_H8300 || TARGET_H8300SX)
3260 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3261 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3262 [(set_attr "length" "8")])
3265 ;; Normal loads with a 32bit destination.
3268 (define_insn "*extzv_1_r_h8300"
3269 [(set (match_operand:SI 0 "register_operand" "=&r")
3270 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
3272 (match_operand 2 "const_int_operand" "n")))]
3274 && INTVAL (operands[2]) < 16"
3275 "* return output_simode_bld (0, operands);"
3276 [(set_attr "length" "8")])
3278 (define_insn "*extzv_1_r_h8300hs"
3279 [(set (match_operand:SI 0 "register_operand" "=r,r")
3280 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3282 (match_operand 2 "const_int_operand" "n,n")))]
3283 "(TARGET_H8300H || TARGET_H8300S)
3284 && INTVAL (operands[2]) < 16"
3285 "* return output_simode_bld (0, operands);"
3286 [(set_attr "cc" "set_znv,set_znv")
3287 (set_attr "length" "8,6")])
3290 ;; Inverted loads with a 32bit destination.
3293 (define_insn "*extzv_1_r_inv_h8300"
3294 [(set (match_operand:SI 0 "register_operand" "=&r")
3295 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
3296 (match_operand:HI 3 "const_int_operand" "n"))
3298 (match_operand 2 "const_int_operand" "n")))]
3300 && INTVAL (operands[2]) < 16
3301 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3302 "* return output_simode_bld (1, operands);"
3303 [(set_attr "length" "8")])
3305 (define_insn "*extzv_1_r_inv_h8300hs"
3306 [(set (match_operand:SI 0 "register_operand" "=r,r")
3307 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
3308 (match_operand 3 "const_int_operand" "n,n"))
3310 (match_operand 2 "const_int_operand" "n,n")))]
3311 "(TARGET_H8300H || TARGET_H8300S)
3312 && INTVAL (operands[2]) < 16
3313 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3314 "* return output_simode_bld (1, operands);"
3315 [(set_attr "cc" "set_znv,set_znv")
3316 (set_attr "length" "8,6")])
3318 (define_expand "insv"
3319 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3320 (match_operand:HI 1 "general_operand" "")
3321 (match_operand:HI 2 "general_operand" ""))
3322 (match_operand:HI 3 "general_operand" ""))]
3323 "TARGET_H8300 || TARGET_H8300SX"
3328 if (GET_CODE (operands[1]) == CONST_INT
3329 && GET_CODE (operands[2]) == CONST_INT
3330 && INTVAL (operands[1]) <= 8
3331 && INTVAL (operands[2]) >= 0
3332 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3333 && memory_operand (operands[0], GET_MODE (operands[0])))
3335 /* If the source operand is zero, it's better to use AND rather
3336 than BFST. Likewise OR if the operand is all ones. */
3337 if (GET_CODE (operands[3]) == CONST_INT)
3339 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3340 if ((INTVAL (operands[3]) & mask) == 0)
3342 if ((INTVAL (operands[3]) & mask) == mask)
3345 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3347 if (!can_create_pseudo_p ())
3350 replace_equiv_address (operands[0],
3352 XEXP (operands[0], 0)));
3354 operands[3] = gen_lowpart (QImode, operands[3]);
3357 if (! register_operand (operands[3], QImode))
3359 if (!can_create_pseudo_p ())
3361 operands[3] = force_reg (QImode, operands[3]);
3363 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3364 operands[3], operands[1], operands[2]));
3371 /* We only have single bit bit-field instructions. */
3372 if (INTVAL (operands[1]) != 1)
3375 /* For now, we don't allow memory operands. */
3376 if (GET_CODE (operands[0]) == MEM
3377 || GET_CODE (operands[3]) == MEM)
3380 if (GET_CODE (operands[3]) != REG)
3381 operands[3] = force_reg (HImode, operands[3]);
3385 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3387 (match_operand:HI 1 "immediate_operand" "n"))
3388 (match_operand:HI 2 "register_operand" "r"))]
3390 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3391 [(set_attr "length" "4")])
3393 (define_expand "extzv"
3394 [(set (match_operand:HI 0 "register_operand" "")
3395 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3396 (match_operand:HI 2 "general_operand" "")
3397 (match_operand:HI 3 "general_operand" "")))]
3398 "TARGET_H8300 || TARGET_H8300SX"
3403 if (GET_CODE (operands[2]) == CONST_INT
3404 && GET_CODE (operands[3]) == CONST_INT
3405 && INTVAL (operands[2]) <= 8
3406 && INTVAL (operands[3]) >= 0
3407 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3408 && memory_operand (operands[1], QImode))
3412 /* Optimize the case where we're extracting into a paradoxical
3413 subreg. It's only necessary to extend to the inner reg. */
3414 if (GET_CODE (operands[0]) == SUBREG
3415 && subreg_lowpart_p (operands[0])
3416 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3417 < GET_MODE_SIZE (GET_MODE (operands[0])))
3418 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3420 operands[0] = SUBREG_REG (operands[0]);
3422 if (!can_create_pseudo_p ())
3423 temp = gen_lowpart (QImode, operands[0]);
3425 temp = gen_reg_rtx (QImode);
3428 if (! bit_memory_operand (operands[1], QImode))
3430 if (!can_create_pseudo_p ())
3433 replace_equiv_address (operands[1],
3435 XEXP (operands[1], 0)));
3437 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3438 convert_move (operands[0], temp, 1);
3444 /* We only have single bit bit-field instructions. */
3445 if (INTVAL (operands[2]) != 1)
3448 /* For now, we don't allow memory operands. */
3449 if (GET_CODE (operands[1]) == MEM)
3453 ;; BAND, BOR, and BXOR patterns
3456 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3457 (match_operator:HI 4 "bit_operator"
3458 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3460 (match_operand:HI 2 "immediate_operand" "n"))
3461 (match_operand:HI 3 "bit_operand" "0")]))]
3463 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3464 [(set_attr "length" "6")])
3467 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3468 (match_operator:HI 5 "bit_operator"
3469 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3471 (match_operand:HI 2 "immediate_operand" "n"))
3472 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3474 (match_operand:HI 4 "immediate_operand" "n"))]))]
3476 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3477 [(set_attr "length" "6")])
3480 [(set (match_operand:QI 0 "register_operand" "=r")
3481 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3482 (match_operand:QI 2 "immediate_operand" "n")
3483 (match_operand:QI 3 "immediate_operand" "n")))]
3484 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3487 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3488 - (1 << INTVAL (operands[3])));
3489 return \"bfld %2,%1,%R0\";
3491 [(set_attr "cc" "none_0hit")
3492 (set_attr "length_table" "bitfield")])
3495 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3496 (match_operand:QI 2 "immediate_operand" "n")
3497 (match_operand:QI 3 "immediate_operand" "n"))
3498 (match_operand:QI 1 "register_operand" "r"))]
3499 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3502 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3503 - (1 << INTVAL (operands[3])));
3504 return \"bfst %R1,%2,%0\";
3506 [(set_attr "cc" "none_0hit")
3507 (set_attr "length_table" "bitfield")])
3509 (define_expand "cstoreqi4"
3510 [(use (match_operator 1 "eqne_operator"
3511 [(match_operand:QI 2 "h8300_dst_operand" "")
3512 (match_operand:QI 3 "h8300_src_operand" "")]))
3513 (clobber (match_operand:HI 0 "register_operand"))]
3515 "h8300_expand_store (operands); DONE;")
3517 (define_expand "cstorehi4"
3518 [(use (match_operator 1 "eqne_operator"
3519 [(match_operand:HI 2 "h8300_dst_operand" "")
3520 (match_operand:HI 3 "h8300_src_operand" "")]))
3521 (clobber (match_operand:HI 0 "register_operand"))]
3523 "h8300_expand_store (operands); DONE;")
3525 (define_expand "cstoresi4"
3526 [(use (match_operator 1 "eqne_operator"
3527 [(match_operand:SI 2 "h8300_dst_operand" "")
3528 (match_operand:SI 3 "h8300_src_operand" "")]))
3529 (clobber (match_operand:HI 0 "register_operand"))]
3531 "h8300_expand_store (operands); DONE;")
3533 (define_insn "*bstzhireg"
3534 [(set (match_operand:HI 0 "register_operand" "=r")
3535 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3537 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3538 [(set_attr "cc" "clobber")])
3540 (define_insn_and_split "*cmpstz"
3541 [(set (zero_extract:QI
3542 (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
3544 (match_operand:QI 1 "immediate_operand" "n,n"))
3547 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3548 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3550 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3551 || GET_CODE (operands[4]) == CONST_INT)
3552 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3553 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3556 [(set (cc0) (match_dup 5))
3557 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3558 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3559 "operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);"
3560 [(set_attr "cc" "set_znv,compare")])
3562 (define_insn "*bstz"
3563 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3565 (match_operand:QI 1 "immediate_operand" "n"))
3566 (eq:QI (cc0) (const_int 0)))]
3567 "TARGET_H8300SX && reload_completed"
3569 [(set_attr "cc" "none_0hit")
3570 (set_attr "length_table" "unary")])
3572 (define_insn "*bistz"
3573 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3575 (match_operand:QI 1 "immediate_operand" "n"))
3576 (ne:QI (cc0) (const_int 0)))]
3577 "TARGET_H8300SX && reload_completed"
3579 [(set_attr "cc" "none_0hit")
3580 (set_attr "length_table" "unary")])
3582 (define_insn_and_split "*cmpcondbset"
3583 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3587 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3588 (match_operand 3 "h8300_src_operand" "I,rQi")])
3590 (match_operand:QI 4 "bit_memory_operand" "0,0")
3591 (match_operand:QI 5 "single_one_operand" "n,n"))
3596 [(set (cc0) (match_dup 6))
3599 (match_op_dup 1 [(cc0) (const_int 0)])
3600 (ior:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3601 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3602 [(set_attr "cc" "set_znv,compare")])
3604 (define_insn "*condbset"
3605 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3607 (match_operator:QI 2 "eqne_operator"
3608 [(cc0) (const_int 0)])
3610 (match_operand:QI 3 "bit_memory_operand" "0")
3611 (match_operand:QI 1 "single_one_operand" "n"))
3613 "TARGET_H8300SX && reload_completed"
3615 [(set_attr "cc" "none_0hit")
3616 (set_attr "length_table" "logicb")])
3618 (define_insn_and_split "*cmpcondbclr"
3619 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3623 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3624 (match_operand 3 "h8300_src_operand" "I,rQi")])
3626 (match_operand:QI 4 "bit_memory_operand" "0,0")
3627 (match_operand:QI 5 "single_zero_operand" "n,n"))
3632 [(set (cc0) (match_dup 6))
3635 (match_op_dup 1 [(cc0) (const_int 0)])
3636 (and:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3637 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3638 [(set_attr "cc" "set_znv,compare")])
3640 (define_insn "*condbclr"
3641 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3643 (match_operator:QI 2 "eqne_operator"
3644 [(cc0) (const_int 0)])
3646 (match_operand:QI 3 "bit_memory_operand" "0")
3647 (match_operand:QI 1 "single_zero_operand" "n"))
3649 "TARGET_H8300SX && reload_completed"
3651 [(set_attr "cc" "none_0hit")
3652 (set_attr "length_table" "logicb")])
3654 (define_insn_and_split "*cmpcondbsetreg"
3655 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3659 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3660 (match_operand 3 "h8300_src_operand" "I,rQi")])
3662 (match_operand:QI 4 "bit_memory_operand" "0,0")
3663 (ashift:QI (const_int 1)
3664 (match_operand:QI 5 "register_operand" "r,r")))
3669 [(set (cc0) (match_dup 6))
3672 (match_op_dup 1 [(cc0) (const_int 0)])
3673 (ior:QI (match_dup 4)
3674 (ashift:QI (const_int 1)
3675 (match_operand:QI 5 "register_operand" "r,r")))
3677 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3678 [(set_attr "cc" "set_znv,compare")])
3680 (define_insn "*condbsetreg"
3681 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3683 (match_operator:QI 2 "eqne_operator"
3684 [(cc0) (const_int 0)])
3686 (match_operand:QI 3 "bit_memory_operand" "0")
3687 (ashift:QI (const_int 1)
3688 (match_operand:QI 1 "register_operand" "r")))
3690 "TARGET_H8300SX && reload_completed"
3692 [(set_attr "cc" "none_0hit")
3693 (set_attr "length_table" "logicb")])
3695 (define_insn_and_split "*cmpcondbclrreg"
3696 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3700 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3701 (match_operand 3 "h8300_src_operand" "I,rQi")])
3703 (match_operand:QI 4 "bit_memory_operand" "0,0")
3704 (ashift:QI (const_int 1)
3705 (match_operand:QI 5 "register_operand" "r,r")))
3710 [(set (cc0) (match_dup 6))
3713 (match_op_dup 1 [(cc0) (const_int 0)])
3714 (and:QI (match_dup 4)
3715 (ashift:QI (const_int 1)
3716 (match_operand:QI 5 "register_operand" "r,r")))
3718 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3719 [(set_attr "cc" "set_znv,compare")])
3721 (define_insn "*condbclrreg"
3722 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3724 (match_operator:QI 2 "eqne_operator"
3725 [(cc0) (const_int 0)])
3727 (match_operand:QI 3 "bit_memory_operand" "0")
3728 (ashift:QI (const_int 1)
3729 (match_operand:QI 1 "register_operand" "r")))
3731 "TARGET_H8300SX && reload_completed"
3733 [(set_attr "cc" "none_0hit")
3734 (set_attr "length_table" "logicb")])
3737 ;; -----------------------------------------------------------------
3739 ;; -----------------------------------------------------------------
3743 (define_insn "*insv_si_1_n"
3744 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3746 (match_operand:SI 1 "const_int_operand" "n"))
3747 (match_operand:SI 2 "register_operand" "r"))]
3748 "(TARGET_H8300H || TARGET_H8300S)
3749 && INTVAL (operands[1]) < 16"
3750 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3751 [(set_attr "length" "4")])
3753 (define_insn "*insv_si_1_n_lshiftrt"
3754 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3756 (match_operand:SI 1 "const_int_operand" "n"))
3757 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3758 (match_operand:SI 3 "const_int_operand" "n")))]
3759 "(TARGET_H8300H || TARGET_H8300S)
3760 && INTVAL (operands[1]) < 16
3761 && INTVAL (operands[3]) < 16"
3762 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3763 [(set_attr "length" "4")])
3765 (define_insn "*insv_si_1_n_lshiftrt_16"
3766 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3768 (match_operand:SI 1 "const_int_operand" "n"))
3769 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3771 "(TARGET_H8300H || TARGET_H8300S)
3772 && INTVAL (operands[1]) < 16"
3773 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3774 [(set_attr "length" "6")])
3776 (define_insn "*insv_si_8_8"
3777 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3780 (match_operand:SI 1 "register_operand" "r"))]
3781 "TARGET_H8300H || TARGET_H8300S"
3783 [(set_attr "length" "2")])
3785 (define_insn "*insv_si_8_8_lshiftrt_8"
3786 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3789 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3791 "TARGET_H8300H || TARGET_H8300S"
3793 [(set_attr "length" "2")])
3797 (define_insn "*extzv_8_8"
3798 [(set (match_operand:SI 0 "register_operand" "=r,r")
3799 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3802 "TARGET_H8300H || TARGET_H8300S"
3804 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3805 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3806 [(set_attr "cc" "set_znv,clobber")
3807 (set_attr "length" "6,4")])
3809 (define_insn "*extzv_8_16"
3810 [(set (match_operand:SI 0 "register_operand" "=r")
3811 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3814 "TARGET_H8300H || TARGET_H8300S"
3815 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3816 [(set_attr "cc" "set_znv")
3817 (set_attr "length" "6")])
3819 (define_insn "*extzv_16_8"
3820 [(set (match_operand:SI 0 "register_operand" "=r")
3821 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3824 (clobber (match_scratch:SI 2 "=&r"))]
3826 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3827 [(set_attr "length" "8")
3828 (set_attr "cc" "set_znv")])
3830 ;; Extract the exponent of a float.
3832 (define_insn_and_split "*extzv_8_23"
3833 [(set (match_operand:SI 0 "register_operand" "=r")
3834 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3837 "(TARGET_H8300H || TARGET_H8300S)"
3839 "&& reload_completed"
3840 [(parallel [(set (match_dup 0)
3841 (ashift:SI (match_dup 0)
3843 (clobber (scratch:QI))])
3844 (parallel [(set (match_dup 0)
3845 (lshiftrt:SI (match_dup 0)
3847 (clobber (scratch:QI))])]
3852 ;; ((SImode) HImode) << 15
3854 (define_insn_and_split "*twoshifts_l16_r1"
3855 [(set (match_operand:SI 0 "register_operand" "=r")
3856 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3858 (const_int 2147450880)))]
3859 "(TARGET_H8300H || TARGET_H8300S)"
3861 "&& reload_completed"
3862 [(parallel [(set (match_dup 0)
3863 (ashift:SI (match_dup 0)
3865 (clobber (scratch:QI))])
3866 (parallel [(set (match_dup 0)
3867 (lshiftrt:SI (match_dup 0)
3869 (clobber (scratch:QI))])]
3872 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3874 (define_insn_and_split "*andsi3_ashift_n_lower"
3875 [(set (match_operand:SI 0 "register_operand" "=r,r")
3876 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3877 (match_operand:QI 2 "const_int_operand" "S,n"))
3878 (match_operand:SI 3 "const_int_operand" "n,n")))
3879 (clobber (match_scratch:QI 4 "=X,&r"))]
3880 "(TARGET_H8300H || TARGET_H8300S)
3881 && INTVAL (operands[2]) <= 15
3882 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3884 "&& reload_completed"
3885 [(parallel [(set (match_dup 5)
3886 (ashift:HI (match_dup 5)
3888 (clobber (match_dup 4))])
3890 (zero_extend:SI (match_dup 5)))]
3891 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3893 ;; Accept (A >> 30) & 2 and the like.
3895 (define_insn "*andsi3_lshiftrt_n_sb"
3896 [(set (match_operand:SI 0 "register_operand" "=r")
3897 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3898 (match_operand:SI 2 "const_int_operand" "n"))
3899 (match_operand:SI 3 "single_one_operand" "n")))]
3900 "(TARGET_H8300H || TARGET_H8300S)
3901 && exact_log2 (INTVAL (operands[3])) < 16
3902 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3905 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3906 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3908 [(set_attr "length" "8")])
3910 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3911 [(set (match_operand:SI 0 "register_operand" "=r")
3912 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3914 (const_int 4194304)))]
3915 "(TARGET_H8300H || TARGET_H8300S)"
3917 "&& reload_completed"
3919 (and:SI (lshiftrt:SI (match_dup 0)
3922 (parallel [(set (match_dup 0)
3923 (ashift:SI (match_dup 0)
3925 (clobber (scratch:QI))])]
3930 (define_insn "*addsi3_upper"
3931 [(set (match_operand:SI 0 "register_operand" "=r")
3932 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3934 (match_operand:SI 2 "register_operand" "0")))]
3935 "TARGET_H8300H || TARGET_H8300S"
3937 [(set_attr "length" "2")])
3939 (define_insn "*addsi3_lshiftrt_16_zexthi"
3940 [(set (match_operand:SI 0 "register_operand" "=r")
3941 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3943 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3944 "TARGET_H8300H || TARGET_H8300S"
3945 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3946 [(set_attr "length" "6")])
3948 (define_insn_and_split "*addsi3_and_r_1"
3949 [(set (match_operand:SI 0 "register_operand" "=r")
3950 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3952 (match_operand:SI 2 "register_operand" "0")))]
3953 "(TARGET_H8300H || TARGET_H8300S)"
3955 "&& reload_completed"
3956 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3961 (if_then_else (eq (cc0)
3963 (label_ref (match_dup 3))
3966 (plus:SI (match_dup 2)
3969 "operands[3] = gen_label_rtx ();")
3971 (define_insn_and_split "*addsi3_and_not_r_1"
3972 [(set (match_operand:SI 0 "register_operand" "=r")
3973 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3975 (match_operand:SI 2 "register_operand" "0")))]
3976 "(TARGET_H8300H || TARGET_H8300S)"
3978 "&& reload_completed"
3979 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3984 (if_then_else (ne (cc0)
3986 (label_ref (match_dup 3))
3989 (plus:SI (match_dup 2)
3992 "operands[3] = gen_label_rtx ();")
3996 (define_insn "*ixorhi3_zext"
3997 [(set (match_operand:HI 0 "register_operand" "=r")
3998 (match_operator:HI 1 "iorxor_operator"
3999 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
4000 (match_operand:HI 3 "register_operand" "0")]))]
4003 [(set_attr "length" "2")])
4007 (define_insn "*ixorsi3_zext_qi"
4008 [(set (match_operand:SI 0 "register_operand" "=r")
4009 (match_operator:SI 1 "iorxor_operator"
4010 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
4011 (match_operand:SI 3 "register_operand" "0")]))]
4014 [(set_attr "length" "2")])
4016 (define_insn "*ixorsi3_zext_hi"
4017 [(set (match_operand:SI 0 "register_operand" "=r")
4018 (match_operator:SI 1 "iorxor_operator"
4019 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
4020 (match_operand:SI 3 "register_operand" "0")]))]
4021 "TARGET_H8300H || TARGET_H8300S"
4023 [(set_attr "length" "2")])
4025 (define_insn "*ixorsi3_ashift_16"
4026 [(set (match_operand:SI 0 "register_operand" "=r")
4027 (match_operator:SI 1 "iorxor_operator"
4028 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
4030 (match_operand:SI 3 "register_operand" "0")]))]
4031 "TARGET_H8300H || TARGET_H8300S"
4033 [(set_attr "length" "2")])
4035 (define_insn "*ixorsi3_lshiftrt_16"
4036 [(set (match_operand:SI 0 "register_operand" "=r")
4037 (match_operator:SI 1 "iorxor_operator"
4038 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4040 (match_operand:SI 3 "register_operand" "0")]))]
4041 "TARGET_H8300H || TARGET_H8300S"
4043 [(set_attr "length" "2")])
4047 (define_insn "*iorhi3_ashift_8"
4048 [(set (match_operand:HI 0 "register_operand" "=r")
4049 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
4051 (match_operand:HI 2 "register_operand" "0")))]
4054 [(set_attr "length" "2")])
4056 (define_insn "*iorhi3_lshiftrt_8"
4057 [(set (match_operand:HI 0 "register_operand" "=r")
4058 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4060 (match_operand:HI 2 "register_operand" "0")))]
4063 [(set_attr "length" "2")])
4065 (define_insn "*iorhi3_two_qi"
4066 [(set (match_operand:HI 0 "register_operand" "=r")
4067 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
4068 (ashift:HI (match_operand:HI 2 "register_operand" "r")
4072 [(set_attr "length" "2")])
4074 (define_insn "*iorhi3_two_qi_mem"
4075 [(set (match_operand:HI 0 "register_operand" "=&r")
4076 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
4077 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
4080 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
4081 [(set_attr "length" "16")])
4084 [(set (match_operand:HI 0 "register_operand" "")
4085 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
4086 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
4088 "(TARGET_H8300H || TARGET_H8300S)
4090 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
4093 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
4097 (define_insn "*iorsi3_two_hi"
4098 [(set (match_operand:SI 0 "register_operand" "=r")
4099 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
4100 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4102 "TARGET_H8300H || TARGET_H8300S"
4104 [(set_attr "length" "2")])
4106 (define_insn_and_split "*iorsi3_two_qi_zext"
4107 [(set (match_operand:SI 0 "register_operand" "=&r")
4108 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
4110 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4112 (const_int 65280))))]
4113 "(TARGET_H8300H || TARGET_H8300S)"
4115 "&& reload_completed"
4117 (ior:HI (zero_extend:HI (match_dup 1))
4118 (ashift:HI (subreg:HI (match_dup 2) 0)
4121 (zero_extend:SI (match_dup 3)))]
4122 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4124 (define_insn "*iorsi3_e2f"
4125 [(set (match_operand:SI 0 "register_operand" "=r")
4126 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4128 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4130 "TARGET_H8300H || TARGET_H8300S"
4132 [(set_attr "length" "2")])
4134 (define_insn_and_split "*iorsi3_two_qi_sext"
4135 [(set (match_operand:SI 0 "register_operand" "=r")
4136 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
4137 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
4139 "(TARGET_H8300H || TARGET_H8300S)"
4141 "&& reload_completed"
4143 (ior:HI (zero_extend:HI (match_dup 1))
4144 (ashift:HI (match_dup 4)
4147 (sign_extend:SI (match_dup 3)))]
4148 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4149 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4151 (define_insn "*iorsi3_w"
4152 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4153 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
4155 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
4156 "TARGET_H8300H || TARGET_H8300S"
4158 [(set_attr "length" "2,8")])
4160 (define_insn "*iorsi3_ashift_31"
4161 [(set (match_operand:SI 0 "register_operand" "=&r")
4162 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4164 (match_operand:SI 2 "register_operand" "0")))]
4165 "TARGET_H8300H || TARGET_H8300S"
4166 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
4167 [(set_attr "length" "6")
4168 (set_attr "cc" "set_znv")])
4170 (define_insn "*iorsi3_and_ashift"
4171 [(set (match_operand:SI 0 "register_operand" "=r")
4172 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4173 (match_operand:SI 2 "const_int_operand" "n"))
4174 (match_operand:SI 3 "single_one_operand" "n"))
4175 (match_operand:SI 4 "register_operand" "0")))]
4176 "(TARGET_H8300H || TARGET_H8300S)
4177 && (INTVAL (operands[3]) & ~0xffff) == 0"
4180 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4181 - INTVAL (operands[2]));
4182 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4183 operands[2] = srcpos;
4184 operands[3] = dstpos;
4185 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4187 [(set_attr "length" "6")])
4189 (define_insn "*iorsi3_and_lshiftrt"
4190 [(set (match_operand:SI 0 "register_operand" "=r")
4191 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4192 (match_operand:SI 2 "const_int_operand" "n"))
4193 (match_operand:SI 3 "single_one_operand" "n"))
4194 (match_operand:SI 4 "register_operand" "0")))]
4195 "(TARGET_H8300H || TARGET_H8300S)
4196 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
4199 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4200 + INTVAL (operands[2]));
4201 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4202 operands[2] = srcpos;
4203 operands[3] = dstpos;
4204 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4206 [(set_attr "length" "6")])
4208 (define_insn "*iorsi3_zero_extract"
4209 [(set (match_operand:SI 0 "register_operand" "=r")
4210 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
4212 (match_operand:SI 2 "const_int_operand" "n"))
4213 (match_operand:SI 3 "register_operand" "0")))]
4214 "(TARGET_H8300H || TARGET_H8300S)
4215 && INTVAL (operands[2]) < 16"
4216 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
4217 [(set_attr "length" "6")])
4219 (define_insn "*iorsi3_and_lshiftrt_n_sb"
4220 [(set (match_operand:SI 0 "register_operand" "=r")
4221 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4224 (match_operand:SI 2 "register_operand" "0")))]
4225 "(TARGET_H8300H || TARGET_H8300S)"
4226 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
4227 [(set_attr "length" "8")])
4229 (define_insn "*iorsi3_and_lshiftrt_9_sb"
4230 [(set (match_operand:SI 0 "register_operand" "=r")
4231 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4233 (const_int 4194304))
4234 (match_operand:SI 2 "register_operand" "0")))
4235 (clobber (match_scratch:HI 3 "=&r"))]
4236 "(TARGET_H8300H || TARGET_H8300S)"
4239 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4240 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4242 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4244 [(set_attr "length" "10")])
4246 ;; Used to OR the exponent of a float.
4248 (define_insn "*iorsi3_shift"
4249 [(set (match_operand:SI 0 "register_operand" "=r")
4250 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4252 (match_operand:SI 2 "register_operand" "0")))
4253 (clobber (match_scratch:SI 3 "=&r"))]
4254 "TARGET_H8300H || TARGET_H8300S"
4258 [(set (match_operand:SI 0 "register_operand" "")
4259 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4262 (clobber (match_operand:SI 2 "register_operand" ""))]
4263 "(TARGET_H8300H || TARGET_H8300S)
4264 && epilogue_completed
4265 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4266 && REGNO (operands[0]) != REGNO (operands[1])"
4267 [(parallel [(set (match_dup 3)
4268 (ashift:HI (match_dup 3)
4270 (clobber (scratch:QI))])
4272 (ior:SI (ashift:SI (match_dup 1)
4275 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4278 [(set (match_operand:SI 0 "register_operand" "")
4279 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4282 (clobber (match_operand:SI 2 "register_operand" ""))]
4283 "(TARGET_H8300H || TARGET_H8300S)
4284 && epilogue_completed
4285 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4286 && REGNO (operands[0]) != REGNO (operands[1]))"
4289 (parallel [(set (match_dup 3)
4290 (ashift:HI (match_dup 3)
4292 (clobber (scratch:QI))])
4294 (ior:SI (ashift:SI (match_dup 2)
4297 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4299 (define_insn "*iorsi2_and_1_lshiftrt_1"
4300 [(set (match_operand:SI 0 "register_operand" "=r")
4301 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4303 (lshiftrt:SI (match_dup 1)
4305 "TARGET_H8300H || TARGET_H8300S"
4306 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
4307 [(set_attr "length" "6")])
4309 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
4310 [(set (match_operand:SI 0 "register_operand" "=r")
4311 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4313 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4315 "(TARGET_H8300H || TARGET_H8300S)"
4317 "&& reload_completed"
4319 (ior:HI (ashift:HI (match_dup 4)
4322 (parallel [(set (match_dup 0)
4323 (ashift:SI (match_dup 0)
4325 (clobber (scratch:QI))])]
4326 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4327 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4329 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4330 [(set (match_operand:SI 0 "register_operand" "=&r")
4331 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4333 (const_int 16711680))
4334 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4336 "(TARGET_H8300H || TARGET_H8300S)"
4338 "&& reload_completed"
4340 (ior:HI (zero_extend:HI (match_dup 1))
4341 (ashift:HI (subreg:HI (match_dup 2) 0)
4343 (parallel [(set (match_dup 0)
4344 (ashift:SI (match_dup 0)
4346 (clobber (scratch:QI))])]
4347 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4349 ;; Used to add the exponent of a float.
4351 (define_insn "*addsi3_shift"
4352 [(set (match_operand:SI 0 "register_operand" "=r")
4353 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4354 (const_int 8388608))
4355 (match_operand:SI 2 "register_operand" "0")))
4356 (clobber (match_scratch:SI 3 "=&r"))]
4357 "TARGET_H8300H || TARGET_H8300S"
4361 [(set (match_operand:SI 0 "register_operand" "")
4362 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4363 (const_int 8388608))
4365 (clobber (match_operand:SI 2 "register_operand" ""))]
4366 "(TARGET_H8300H || TARGET_H8300S)
4367 && epilogue_completed
4368 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4369 && REGNO (operands[0]) != REGNO (operands[1])"
4370 [(parallel [(set (match_dup 3)
4371 (ashift:HI (match_dup 3)
4373 (clobber (scratch:QI))])
4375 (plus:SI (mult:SI (match_dup 1)
4378 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4381 [(set (match_operand:SI 0 "register_operand" "")
4382 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4383 (const_int 8388608))
4385 (clobber (match_operand:SI 2 "register_operand" ""))]
4386 "(TARGET_H8300H || TARGET_H8300S)
4387 && epilogue_completed
4388 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4389 && REGNO (operands[0]) != REGNO (operands[1]))"
4392 (parallel [(set (match_dup 3)
4393 (ashift:HI (match_dup 3)
4395 (clobber (scratch:QI))])
4397 (plus:SI (mult:SI (match_dup 2)
4400 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4404 (define_insn_and_split "*ashiftsi_sextqi_7"
4405 [(set (match_operand:SI 0 "register_operand" "=r")
4406 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4408 "(TARGET_H8300H || TARGET_H8300S)"
4410 "&& reload_completed"
4411 [(parallel [(set (match_dup 2)
4412 (ashift:HI (match_dup 2)
4414 (clobber (scratch:QI))])
4416 (sign_extend:SI (match_dup 2)))
4417 (parallel [(set (match_dup 0)
4418 (ashiftrt:SI (match_dup 0)
4420 (clobber (scratch:QI))])]
4421 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4423 ;; Storing a part of HImode to QImode.
4426 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4427 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4431 [(set_attr "cc" "set_znv")
4432 (set_attr "length" "8")])
4434 ;; Storing a part of SImode to QImode.
4437 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4438 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4442 [(set_attr "cc" "set_znv")
4443 (set_attr "length" "8")])
4446 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4447 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4449 (clobber (match_scratch:SI 2 "=&r"))]
4450 "TARGET_H8300H || TARGET_H8300S"
4451 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4452 [(set_attr "cc" "set_znv")
4453 (set_attr "length" "10")])
4456 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4457 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4459 (clobber (match_scratch:SI 2 "=&r"))]
4460 "TARGET_H8300H || TARGET_H8300S"
4461 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4462 [(set_attr "cc" "set_znv")
4463 (set_attr "length" "10")])
4465 (define_insn_and_split ""
4467 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4471 (label_ref (match_operand 1 "" ""))
4476 [(set (cc0) (compare (match_dup 0)
4479 (if_then_else (ge (cc0)
4481 (label_ref (match_dup 1))
4485 (define_insn_and_split ""
4487 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4491 (label_ref (match_operand 1 "" ""))
4496 [(set (cc0) (compare (match_dup 0)
4499 (if_then_else (lt (cc0)
4501 (label_ref (match_dup 1))
4505 ;; -----------------------------------------------------------------
4506 ;; PEEPHOLE PATTERNS
4507 ;; -----------------------------------------------------------------
4509 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4512 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4513 (lshiftrt:HI (match_dup 0)
4514 (match_operand:HI 1 "const_int_operand" "")))
4515 (clobber (match_operand:HI 2 "" ""))])
4517 (and:HI (match_dup 0)
4518 (match_operand:HI 3 "const_int_operand" "")))]
4519 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4521 (and:HI (match_dup 0)
4525 (lshiftrt:HI (match_dup 0)
4527 (clobber (match_dup 2))])]
4530 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4533 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4534 (ashift:HI (match_dup 0)
4535 (match_operand:HI 1 "const_int_operand" "")))
4536 (clobber (match_operand:HI 2 "" ""))])
4538 (and:HI (match_dup 0)
4539 (match_operand:HI 3 "const_int_operand" "")))]
4540 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4542 (and:HI (match_dup 0)
4546 (ashift:HI (match_dup 0)
4548 (clobber (match_dup 2))])]
4551 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4554 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4555 (lshiftrt:SI (match_dup 0)
4556 (match_operand:SI 1 "const_int_operand" "")))
4557 (clobber (match_operand:SI 2 "" ""))])
4559 (and:SI (match_dup 0)
4560 (match_operand:SI 3 "const_int_operand" "")))]
4561 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4563 (and:SI (match_dup 0)
4567 (lshiftrt:SI (match_dup 0)
4569 (clobber (match_dup 2))])]
4572 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4575 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4576 (ashift:SI (match_dup 0)
4577 (match_operand:SI 1 "const_int_operand" "")))
4578 (clobber (match_operand:SI 2 "" ""))])
4580 (and:SI (match_dup 0)
4581 (match_operand:SI 3 "const_int_operand" "")))]
4582 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4584 (and:SI (match_dup 0)
4588 (ashift:SI (match_dup 0)
4590 (clobber (match_dup 2))])]
4593 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4596 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4597 (lshiftrt:SI (match_dup 0)
4598 (match_operand:SI 1 "const_int_operand" "")))
4599 (clobber (match_operand:SI 2 "" ""))])
4601 (and:SI (match_dup 0)
4602 (match_operand:SI 3 "const_int_operand" "")))]
4603 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4605 (and:SI (match_dup 0)
4609 (lshiftrt:SI (match_dup 0)
4611 (clobber (match_dup 2))])]
4614 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4617 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4618 (ashift:SI (match_dup 0)
4619 (match_operand:SI 1 "const_int_operand" "")))
4620 (clobber (match_operand:SI 2 "" ""))])
4622 (and:SI (match_dup 0)
4623 (match_operand:SI 3 "const_int_operand" "")))]
4624 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4626 (and:SI (match_dup 0)
4630 (ashift:SI (match_dup 0)
4632 (clobber (match_dup 2))])]
4635 ;; Convert a QImode push into an SImode push so that the
4636 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4639 [(parallel [(set (reg:SI SP_REG)
4640 (plus:SI (reg:SI SP_REG) (const_int -4)))
4641 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4642 (match_operand:QI 0 "register_operand" ""))])]
4643 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4644 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4646 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4649 [(parallel [(set (reg:HI SP_REG)
4650 (plus:HI (reg:HI SP_REG) (const_int -4)))
4651 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4652 (match_operand:QI 0 "register_operand" ""))])]
4653 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4654 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4656 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4658 ;; Convert a HImode push into an SImode push so that the
4659 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4662 [(parallel [(set (reg:SI SP_REG)
4663 (plus:SI (reg:SI SP_REG) (const_int -4)))
4664 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4665 (match_operand:HI 0 "register_operand" ""))])]
4666 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4667 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4669 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4672 [(parallel [(set (reg:HI SP_REG)
4673 (plus:HI (reg:HI SP_REG) (const_int -4)))
4674 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4675 (match_operand:HI 0 "register_operand" ""))])]
4676 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4677 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4679 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4681 ;; Cram four pushes into stm.l.
4684 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4685 (match_operand:SI 0 "register_operand" ""))
4686 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4687 (match_operand:SI 1 "register_operand" ""))
4688 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4689 (match_operand:SI 2 "register_operand" ""))
4690 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4691 (match_operand:SI 3 "register_operand" ""))]
4692 "TARGET_H8300S && !TARGET_NORMAL_MODE
4693 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4694 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4695 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4696 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4697 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4698 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4700 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4702 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4704 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4706 (set (reg:SI SP_REG)
4707 (plus:SI (reg:SI SP_REG)
4708 (const_int -16)))])]
4712 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4713 (match_operand:SI 0 "register_operand" ""))
4714 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4715 (match_operand:SI 1 "register_operand" ""))
4716 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4717 (match_operand:SI 2 "register_operand" ""))
4718 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4719 (match_operand:SI 3 "register_operand" ""))]
4720 "TARGET_H8300S && TARGET_NORMAL_MODE
4721 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4722 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4723 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4724 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4725 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4726 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4728 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4730 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4732 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4734 (set (reg:HI SP_REG)
4735 (plus:HI (reg:HI SP_REG)
4736 (const_int -16)))])]
4739 ;; Cram three pushes into stm.l.
4742 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4743 (match_operand:SI 0 "register_operand" ""))
4744 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4745 (match_operand:SI 1 "register_operand" ""))
4746 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4747 (match_operand:SI 2 "register_operand" ""))]
4748 "TARGET_H8300S && !TARGET_NORMAL_MODE
4749 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4750 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4751 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4752 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4753 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4755 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4757 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4759 (set (reg:SI SP_REG)
4760 (plus:SI (reg:SI SP_REG)
4761 (const_int -12)))])]
4765 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4766 (match_operand:SI 0 "register_operand" ""))
4767 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4768 (match_operand:SI 1 "register_operand" ""))
4769 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4770 (match_operand:SI 2 "register_operand" ""))]
4771 "TARGET_H8300S && TARGET_NORMAL_MODE
4772 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4773 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4774 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4775 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4776 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4778 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4780 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4782 (set (reg:HI SP_REG)
4783 (plus:HI (reg:HI SP_REG)
4784 (const_int -12)))])]
4787 ;; Cram two pushes into stm.l.
4790 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4791 (match_operand:SI 0 "register_operand" ""))
4792 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4793 (match_operand:SI 1 "register_operand" ""))]
4794 "TARGET_H8300S && !TARGET_NORMAL_MODE
4795 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4796 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4797 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4798 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4800 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4802 (set (reg:SI SP_REG)
4803 (plus:SI (reg:SI SP_REG)
4808 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4809 (match_operand:SI 0 "register_operand" ""))
4810 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4811 (match_operand:SI 1 "register_operand" ""))]
4812 "TARGET_H8300S && TARGET_NORMAL_MODE
4813 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4814 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4815 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4816 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4818 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4820 (set (reg:HI SP_REG)
4821 (plus:HI (reg:HI SP_REG)
4828 ;; add.w r7,r0 (6 bytes)
4833 ;; adds #2,r0 (4 bytes)
4836 [(set (match_operand:HI 0 "register_operand" "")
4837 (match_operand:HI 1 "const_int_operand" ""))
4839 (plus:HI (match_dup 0)
4840 (match_operand:HI 2 "register_operand" "")))]
4841 "REG_P (operands[0]) && REG_P (operands[2])
4842 && REGNO (operands[0]) != REGNO (operands[2])
4843 && (CONST_OK_FOR_J (INTVAL (operands[1]))
4844 || CONST_OK_FOR_L (INTVAL (operands[1]))
4845 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4849 (plus:HI (match_dup 0)
4857 ;; add.l er7,er0 (6 bytes)
4862 ;; adds #4,er0 (4 bytes)
4865 [(set (match_operand:SI 0 "register_operand" "")
4866 (match_operand:SI 1 "const_int_operand" ""))
4868 (plus:SI (match_dup 0)
4869 (match_operand:SI 2 "register_operand" "")))]
4870 "(TARGET_H8300H || TARGET_H8300S)
4871 && REG_P (operands[0]) && REG_P (operands[2])
4872 && REGNO (operands[0]) != REGNO (operands[2])
4873 && (CONST_OK_FOR_L (INTVAL (operands[1]))
4874 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4878 (plus:SI (match_dup 0)
4885 ;; add.l #10,er0 (takes 8 bytes)
4891 ;; add.l er7,er0 (takes 6 bytes)
4894 [(set (match_operand:SI 0 "register_operand" "")
4895 (match_operand:SI 1 "register_operand" ""))
4897 (plus:SI (match_dup 0)
4898 (match_operand:SI 2 "const_int_operand" "")))]
4899 "(TARGET_H8300H || TARGET_H8300S)
4900 && REG_P (operands[0]) && REG_P (operands[1])
4901 && REGNO (operands[0]) != REGNO (operands[1])
4902 && !CONST_OK_FOR_L (INTVAL (operands[2]))
4903 && !CONST_OK_FOR_N (INTVAL (operands[2]))
4904 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4905 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4906 || INTVAL (operands[2]) == 0xffff
4907 || INTVAL (operands[2]) == 0xfffe)"
4911 (plus:SI (match_dup 0)
4927 [(set (match_operand:HI 0 "register_operand" "")
4928 (plus:HI (match_dup 0)
4929 (match_operand 1 "incdec_operand" "")))
4930 (set (cc0) (compare (match_dup 0)
4933 (if_then_else (match_operator 3 "eqne_operator"
4934 [(cc0) (const_int 0)])
4935 (label_ref (match_operand 2 "" ""))
4937 "TARGET_H8300H || TARGET_H8300S"
4938 [(set (match_operand:HI 0 "register_operand" "")
4939 (unspec:HI [(match_dup 0)
4942 (set (cc0) (compare (match_dup 0)
4945 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4946 (label_ref (match_dup 2))
4950 ;; The SImode version of the previous pattern.
4953 [(set (match_operand:SI 0 "register_operand" "")
4954 (plus:SI (match_dup 0)
4955 (match_operand 1 "incdec_operand" "")))
4956 (set (cc0) (compare (match_dup 0)
4959 (if_then_else (match_operator 3 "eqne_operator"
4960 [(cc0) (const_int 0)])
4961 (label_ref (match_operand 2 "" ""))
4963 "TARGET_H8300H || TARGET_H8300S"
4964 [(set (match_operand:SI 0 "register_operand" "")
4965 (unspec:SI [(match_dup 0)
4968 (set (cc0) (compare (match_dup 0)
4971 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4972 (label_ref (match_dup 2))
4977 [(parallel [(set (cc0)
4978 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4982 (clobber (scratch:QI))])
4984 (if_then_else (match_operator 1 "eqne_operator"
4985 [(cc0) (const_int 0)])
4986 (label_ref (match_operand 2 "" ""))
4988 "(TARGET_H8300H || TARGET_H8300S)"
4989 [(set (cc0) (compare (match_dup 0)
4992 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4993 (label_ref (match_dup 2))
4995 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4996 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4997 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4999 ;; The next three peephole2's will try to transform
5001 ;; mov.b A,r0l (or mov.l A,er0)
5008 ;; and.b #CST,r0l (if CST is not 255)
5011 [(set (match_operand:QI 0 "register_operand" "")
5012 (match_operand:QI 1 "general_operand" ""))
5013 (set (match_operand:SI 2 "register_operand" "")
5014 (and:SI (match_dup 2)
5016 "(TARGET_H8300H || TARGET_H8300S)
5017 && !reg_overlap_mentioned_p (operands[2], operands[1])
5018 && REGNO (operands[0]) == REGNO (operands[2])"
5021 (set (strict_low_part (match_dup 0))
5026 [(set (match_operand:SI 0 "register_operand" "")
5027 (match_operand:SI 1 "general_operand" ""))
5029 (and:SI (match_dup 0)
5031 "(TARGET_H8300H || TARGET_H8300S)
5032 && !reg_overlap_mentioned_p (operands[0], operands[1])
5033 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
5034 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
5037 (set (strict_low_part (match_dup 2))
5039 "operands[2] = gen_lowpart (QImode, operands[0]);
5040 operands[3] = gen_lowpart (QImode, operands[1]);")
5043 [(set (match_operand 0 "register_operand" "")
5044 (match_operand 1 "general_operand" ""))
5045 (set (match_operand:SI 2 "register_operand" "")
5046 (and:SI (match_dup 2)
5047 (match_operand:SI 3 "const_int_qi_operand" "")))]
5048 "(TARGET_H8300H || TARGET_H8300S)
5049 && (GET_MODE (operands[0]) == QImode
5050 || GET_MODE (operands[0]) == HImode
5051 || GET_MODE (operands[0]) == SImode)
5052 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5053 && REGNO (operands[0]) == REGNO (operands[2])
5054 && !reg_overlap_mentioned_p (operands[2], operands[1])
5055 && !(GET_MODE (operands[1]) != QImode
5056 && GET_CODE (operands[1]) == MEM
5057 && !offsettable_memref_p (operands[1]))
5058 && !(GET_MODE (operands[1]) != QImode
5059 && GET_CODE (operands[1]) == MEM
5060 && MEM_VOLATILE_P (operands[1]))"
5063 (set (strict_low_part (match_dup 4))
5066 (and:SI (match_dup 2)
5068 "operands[4] = gen_lowpart (QImode, operands[0]);
5069 operands[5] = gen_lowpart (QImode, operands[1]);
5070 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
5073 [(set (match_operand:SI 0 "register_operand" "")
5074 (match_operand:SI 1 "register_operand" ""))
5076 (and:SI (match_dup 0)
5077 (const_int 65280)))]
5078 "(TARGET_H8300H || TARGET_H8300S)
5079 && !reg_overlap_mentioned_p (operands[0], operands[1])"
5082 (set (zero_extract:SI (match_dup 0)
5085 (lshiftrt:SI (match_dup 1)
5089 ;; If a load of mem:SI is followed by an AND that turns off the upper
5090 ;; half, then we can load mem:HI instead.
5093 [(set (match_operand:SI 0 "register_operand" "")
5094 (match_operand:SI 1 "memory_operand" ""))
5096 (and:SI (match_dup 0)
5097 (match_operand:SI 2 "const_int_operand" "")))]
5098 "(TARGET_H8300H || TARGET_H8300S)
5099 && !MEM_VOLATILE_P (operands[1])
5100 && offsettable_memref_p (operands[1])
5101 && (INTVAL (operands[2]) & ~0xffff) == 0
5102 && INTVAL (operands[2]) != 255"
5106 (and:SI (match_dup 0)
5108 "operands[3] = gen_lowpart (HImode, operands[0]);
5109 operands[4] = gen_lowpart (HImode, operands[1]);")
5111 ;; Convert a memory comparison to a move if there is a scratch register.
5114 [(match_scratch:QI 1 "r")
5116 (compare (match_operand:QI 0 "memory_operand" "")
5121 (set (cc0) (compare (match_dup 1)
5126 [(match_scratch:HI 1 "r")
5128 (compare (match_operand:HI 0 "memory_operand" "")
5130 "(TARGET_H8300H || TARGET_H8300S)"
5133 (set (cc0) (compare (match_dup 1)
5138 [(match_scratch:SI 1 "r")
5140 (compare (match_operand:SI 0 "memory_operand" "")
5142 "(TARGET_H8300H || TARGET_H8300S)"
5145 (set (cc0) (compare (match_dup 1)
5150 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
5151 ;; the equivalent with shorter sequences. Here is the summary. Cases
5152 ;; are grouped for each define_peephole2.
5154 ;; reg const_int use insn
5155 ;; --------------------------------------------------------
5156 ;; dead -2 eq/ne inc.l
5157 ;; dead -1 eq/ne inc.l
5158 ;; dead 1 eq/ne dec.l
5159 ;; dead 2 eq/ne dec.l
5161 ;; dead 1 ge/lt shar.l
5162 ;; dead 3 (H8S) ge/lt shar.l
5164 ;; dead 1 geu/ltu shar.l
5165 ;; dead 3 (H8S) geu/ltu shar.l
5167 ;; ---- 255 ge/lt mov.b
5169 ;; ---- 255 geu/ltu mov.b
5183 (compare (match_operand:HI 0 "register_operand" "")
5184 (match_operand:HI 1 "incdec_operand" "")))
5186 (if_then_else (match_operator 3 "eqne_operator"
5187 [(cc0) (const_int 0)])
5188 (label_ref (match_operand 2 "" ""))
5190 "(TARGET_H8300H || TARGET_H8300S)
5191 && INTVAL (operands[1]) != 0
5192 && peep2_reg_dead_p (1, operands[0])"
5194 (unspec:HI [(match_dup 0)
5197 (set (cc0) (compare (match_dup 0)
5200 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5201 (label_ref (match_dup 2))
5203 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5217 (compare (match_operand:HI 0 "register_operand" "")
5218 (match_operand:HI 1 "const_int_operand" "")))
5220 (if_then_else (match_operator 2 "gtle_operator"
5221 [(cc0) (const_int 0)])
5222 (label_ref (match_operand 3 "" ""))
5224 "(TARGET_H8300H || TARGET_H8300S)
5225 && peep2_reg_dead_p (1, operands[0])
5226 && (INTVAL (operands[1]) == 1
5227 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5228 [(parallel [(set (match_dup 0)
5229 (ashiftrt:HI (match_dup 0)
5231 (clobber (scratch:QI))])
5232 (set (cc0) (compare (match_dup 0)
5235 (if_then_else (match_dup 2)
5236 (label_ref (match_dup 3))
5238 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5252 (compare (match_operand:HI 0 "register_operand" "")
5253 (match_operand:HI 1 "const_int_operand" "")))
5255 (if_then_else (match_operator 2 "gtuleu_operator"
5256 [(cc0) (const_int 0)])
5257 (label_ref (match_operand 3 "" ""))
5259 "(TARGET_H8300H || TARGET_H8300S)
5260 && peep2_reg_dead_p (1, operands[0])
5261 && (INTVAL (operands[1]) == 1
5262 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5263 [(parallel [(set (match_dup 0)
5264 (ashiftrt:HI (match_dup 0)
5266 (clobber (scratch:QI))])
5267 (set (cc0) (compare (match_dup 0)
5270 (if_then_else (match_dup 5)
5271 (label_ref (match_dup 3))
5274 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5275 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5293 (compare (match_operand:HI 0 "register_operand" "")
5296 (if_then_else (match_operator 1 "gtle_operator"
5297 [(cc0) (const_int 0)])
5298 (label_ref (match_operand 2 "" ""))
5300 "TARGET_H8300H || TARGET_H8300S"
5301 [(set (cc0) (compare (and:HI (match_dup 0)
5305 (if_then_else (match_dup 1)
5306 (label_ref (match_dup 2))
5322 (compare (match_operand:HI 0 "register_operand" "")
5325 (if_then_else (match_operator 1 "gtuleu_operator"
5326 [(cc0) (const_int 0)])
5327 (label_ref (match_operand 2 "" ""))
5329 "TARGET_H8300H || TARGET_H8300S"
5330 [(set (cc0) (compare (and:HI (match_dup 0)
5334 (if_then_else (match_dup 3)
5335 (label_ref (match_dup 2))
5338 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5344 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5345 ;; the equivalent with shorter sequences. Here is the summary. Cases
5346 ;; are grouped for each define_peephole2.
5348 ;; reg const_int use insn
5349 ;; --------------------------------------------------------
5350 ;; live -2 eq/ne copy and inc.l
5351 ;; live -1 eq/ne copy and inc.l
5352 ;; live 1 eq/ne copy and dec.l
5353 ;; live 2 eq/ne copy and dec.l
5355 ;; dead -2 eq/ne inc.l
5356 ;; dead -1 eq/ne inc.l
5357 ;; dead 1 eq/ne dec.l
5358 ;; dead 2 eq/ne dec.l
5360 ;; dead -131072 eq/ne inc.w and test
5361 ;; dead -65536 eq/ne inc.w and test
5362 ;; dead 65536 eq/ne dec.w and test
5363 ;; dead 131072 eq/ne dec.w and test
5365 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5366 ;; dead 0x0000??00 eq/ne xor.b and test
5367 ;; dead 0x0000ffff eq/ne not.w and test
5369 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5370 ;; dead 0xffff??ff eq/ne xor.b and not.l
5371 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5372 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5374 ;; live 1 ge/lt copy and shar.l
5375 ;; live 3 (H8S) ge/lt copy and shar.l
5377 ;; live 1 geu/ltu copy and shar.l
5378 ;; live 3 (H8S) geu/ltu copy and shar.l
5380 ;; dead 1 ge/lt shar.l
5381 ;; dead 3 (H8S) ge/lt shar.l
5383 ;; dead 1 geu/ltu shar.l
5384 ;; dead 3 (H8S) geu/ltu shar.l
5386 ;; dead 3 (H8/300H) ge/lt and.b and test
5387 ;; dead 7 ge/lt and.b and test
5388 ;; dead 15 ge/lt and.b and test
5389 ;; dead 31 ge/lt and.b and test
5390 ;; dead 63 ge/lt and.b and test
5391 ;; dead 127 ge/lt and.b and test
5392 ;; dead 255 ge/lt and.b and test
5394 ;; dead 3 (H8/300H) geu/ltu and.b and test
5395 ;; dead 7 geu/ltu and.b and test
5396 ;; dead 15 geu/ltu and.b and test
5397 ;; dead 31 geu/ltu and.b and test
5398 ;; dead 63 geu/ltu and.b and test
5399 ;; dead 127 geu/ltu and.b and test
5400 ;; dead 255 geu/ltu and.b and test
5402 ;; ---- 65535 ge/lt mov.w
5404 ;; ---- 65535 geu/ltu mov.w
5418 (compare (match_operand:SI 0 "register_operand" "")
5419 (match_operand:SI 1 "incdec_operand" "")))
5421 (if_then_else (match_operator 3 "eqne_operator"
5422 [(cc0) (const_int 0)])
5423 (label_ref (match_operand 2 "" ""))
5425 "(TARGET_H8300H || TARGET_H8300S)
5426 && INTVAL (operands[1]) != 0
5427 && peep2_reg_dead_p (1, operands[0])"
5429 (unspec:SI [(match_dup 0)
5432 (set (cc0) (compare (match_dup 0)
5435 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5436 (label_ref (match_dup 2))
5438 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5452 (compare (match_operand:SI 0 "register_operand" "")
5453 (match_operand:SI 1 "const_int_operand" "")))
5455 (if_then_else (match_operator 3 "eqne_operator"
5456 [(cc0) (const_int 0)])
5457 (label_ref (match_operand 2 "" ""))
5459 "(TARGET_H8300H || TARGET_H8300S)
5460 && peep2_reg_dead_p (1, operands[0])
5461 && (INTVAL (operands[1]) == -131072
5462 || INTVAL (operands[1]) == -65536
5463 || INTVAL (operands[1]) == 65536
5464 || INTVAL (operands[1]) == 131072)"
5466 (plus:SI (match_dup 0)
5468 (set (cc0) (compare (match_dup 0)
5471 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5472 (label_ref (match_dup 2))
5474 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5489 (compare (match_operand:SI 0 "register_operand" "")
5490 (match_operand:SI 1 "const_int_operand" "")))
5492 (if_then_else (match_operator 3 "eqne_operator"
5493 [(cc0) (const_int 0)])
5494 (label_ref (match_operand 2 "" ""))
5496 "(TARGET_H8300H || TARGET_H8300S)
5497 && peep2_reg_dead_p (1, operands[0])
5498 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5499 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5500 || INTVAL (operands[1]) == 0x0000ffff)
5501 && INTVAL (operands[1]) != 0
5502 && INTVAL (operands[1]) != 1
5503 && INTVAL (operands[1]) != 2"
5505 (xor:SI (match_dup 0)
5507 (set (cc0) (compare (match_dup 0)
5510 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5511 (label_ref (match_dup 2))
5528 (compare (match_operand:SI 0 "register_operand" "")
5529 (match_operand:SI 1 "const_int_operand" "")))
5531 (if_then_else (match_operator 3 "eqne_operator"
5532 [(cc0) (const_int 0)])
5533 (label_ref (match_operand 2 "" ""))
5535 "(TARGET_H8300H || TARGET_H8300S)
5536 && peep2_reg_dead_p (1, operands[0])
5537 && ((INTVAL (operands[1]) | 0x00ff) == -1
5538 || (INTVAL (operands[1]) | 0xff00) == -1)
5539 && INTVAL (operands[1]) != -1
5540 && INTVAL (operands[1]) != -2"
5542 (xor:SI (match_dup 0)
5545 (not:SI (match_dup 0)))
5546 (set (cc0) (compare (match_dup 0)
5549 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5550 (label_ref (match_dup 2))
5552 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
5556 ;; cmp.l #-2147483648,er0
5567 (compare (match_operand:SI 0 "register_operand" "")
5568 (match_operand:SI 1 "const_int_operand" "")))
5570 (if_then_else (match_operator 3 "eqne_operator"
5571 [(cc0) (const_int 0)])
5572 (label_ref (match_operand 2 "" ""))
5574 "(TARGET_H8300H || TARGET_H8300S)
5575 && peep2_reg_dead_p (1, operands[0])
5576 && (INTVAL (operands[1]) == -2147483647 - 1
5577 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5579 (rotate:SI (match_dup 0)
5582 (unspec:SI [(match_dup 0)
5585 (set (cc0) (compare (match_dup 0)
5588 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5589 (label_ref (match_dup 2))
5591 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
5604 ;; We avoid this transformation if we see more than one copy of the
5605 ;; same compare insn immediately before this one.
5608 [(match_scratch:SI 4 "r")
5610 (compare (match_operand:SI 0 "register_operand" "")
5611 (match_operand:SI 1 "const_int_operand" "")))
5613 (if_then_else (match_operator 2 "gtle_operator"
5614 [(cc0) (const_int 0)])
5615 (label_ref (match_operand 3 "" ""))
5617 "(TARGET_H8300H || TARGET_H8300S)
5618 && !peep2_reg_dead_p (1, operands[0])
5619 && (INTVAL (operands[1]) == 1
5620 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5621 && !same_cmp_preceding_p (insn)"
5624 (parallel [(set (match_dup 4)
5625 (ashiftrt:SI (match_dup 4)
5627 (clobber (scratch:QI))])
5628 (set (cc0) (compare (match_dup 4)
5631 (if_then_else (match_dup 2)
5632 (label_ref (match_dup 3))
5634 "operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5647 ;; We avoid this transformation if we see more than one copy of the
5648 ;; same compare insn immediately before this one.
5651 [(match_scratch:SI 4 "r")
5653 (compare (match_operand:SI 0 "register_operand" "")
5654 (match_operand:SI 1 "const_int_operand" "")))
5656 (if_then_else (match_operator 2 "gtuleu_operator"
5657 [(cc0) (const_int 0)])
5658 (label_ref (match_operand 3 "" ""))
5660 "(TARGET_H8300H || TARGET_H8300S)
5661 && !peep2_reg_dead_p (1, operands[0])
5662 && (INTVAL (operands[1]) == 1
5663 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5664 && !same_cmp_preceding_p (insn)"
5667 (parallel [(set (match_dup 4)
5668 (ashiftrt:SI (match_dup 4)
5670 (clobber (scratch:QI))])
5671 (set (cc0) (compare (match_dup 4)
5674 (if_then_else (match_dup 6)
5675 (label_ref (match_dup 3))
5678 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5679 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5697 (compare (match_operand:SI 0 "register_operand" "")
5698 (match_operand:SI 1 "const_int_operand" "")))
5700 (if_then_else (match_operator 2 "gtle_operator"
5701 [(cc0) (const_int 0)])
5702 (label_ref (match_operand 3 "" ""))
5704 "(TARGET_H8300H || TARGET_H8300S)
5705 && peep2_reg_dead_p (1, operands[0])
5706 && (INTVAL (operands[1]) == 1
5707 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5708 [(parallel [(set (match_dup 0)
5709 (ashiftrt:SI (match_dup 0)
5711 (clobber (scratch:QI))])
5712 (set (cc0) (compare (match_dup 0)
5715 (if_then_else (match_dup 2)
5716 (label_ref (match_dup 3))
5718 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5732 (compare (match_operand:SI 0 "register_operand" "")
5733 (match_operand:SI 1 "const_int_operand" "")))
5735 (if_then_else (match_operator 2 "gtuleu_operator"
5736 [(cc0) (const_int 0)])
5737 (label_ref (match_operand 3 "" ""))
5739 "(TARGET_H8300H || TARGET_H8300S)
5740 && peep2_reg_dead_p (1, operands[0])
5741 && (INTVAL (operands[1]) == 1
5742 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5743 [(parallel [(set (match_dup 0)
5744 (ashiftrt:SI (match_dup 0)
5746 (clobber (scratch:QI))])
5747 (set (cc0) (compare (match_dup 0)
5750 (if_then_else (match_dup 5)
5751 (label_ref (match_dup 3))
5754 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5755 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5774 (compare (match_operand:SI 0 "register_operand" "")
5775 (match_operand:SI 1 "const_int_operand" "")))
5777 (if_then_else (match_operator 2 "gtle_operator"
5778 [(cc0) (const_int 0)])
5779 (label_ref (match_operand 3 "" ""))
5781 "(TARGET_H8300H || TARGET_H8300S)
5782 && peep2_reg_dead_p (1, operands[0])
5783 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5784 || INTVAL (operands[1]) == 7
5785 || INTVAL (operands[1]) == 15
5786 || INTVAL (operands[1]) == 31
5787 || INTVAL (operands[1]) == 63
5788 || INTVAL (operands[1]) == 127
5789 || INTVAL (operands[1]) == 255)"
5791 (and:SI (match_dup 0)
5793 (set (cc0) (compare (match_dup 0)
5796 (if_then_else (match_dup 2)
5797 (label_ref (match_dup 3))
5799 "operands[4] = GEN_INT (~INTVAL (operands[1]));")
5814 (compare (match_operand:SI 0 "register_operand" "")
5815 (match_operand:SI 1 "const_int_operand" "")))
5817 (if_then_else (match_operator 2 "gtuleu_operator"
5818 [(cc0) (const_int 0)])
5819 (label_ref (match_operand 3 "" ""))
5821 "(TARGET_H8300H || TARGET_H8300S)
5822 && peep2_reg_dead_p (1, operands[0])
5823 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5824 || INTVAL (operands[1]) == 7
5825 || INTVAL (operands[1]) == 15
5826 || INTVAL (operands[1]) == 31
5827 || INTVAL (operands[1]) == 63
5828 || INTVAL (operands[1]) == 127
5829 || INTVAL (operands[1]) == 255)"
5831 (and:SI (match_dup 0)
5833 (set (cc0) (compare (match_dup 0)
5836 (if_then_else (match_dup 5)
5837 (label_ref (match_dup 3))
5840 operands[4] = GEN_INT (~INTVAL (operands[1]));
5841 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5859 (compare (match_operand:SI 0 "register_operand" "")
5862 (if_then_else (match_operator 1 "gtle_operator"
5863 [(cc0) (const_int 0)])
5864 (label_ref (match_operand 2 "" ""))
5866 "TARGET_H8300H || TARGET_H8300S"
5867 [(set (cc0) (compare (and:SI (match_dup 0)
5871 (if_then_else (match_dup 1)
5872 (label_ref (match_dup 2))
5888 (compare (match_operand:SI 0 "register_operand" "")
5891 (if_then_else (match_operator 1 "gtuleu_operator"
5892 [(cc0) (const_int 0)])
5893 (label_ref (match_operand 2 "" ""))
5895 "TARGET_H8300H || TARGET_H8300S"
5896 [(set (cc0) (compare (and:SI (match_dup 0)
5900 (if_then_else (match_dup 3)
5901 (label_ref (match_dup 2))
5904 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5921 ;; We avoid this transformation if we see more than one copy of the
5922 ;; same compare insn.
5925 [(match_scratch:SI 4 "r")
5927 (compare (match_operand:SI 0 "register_operand" "")
5928 (match_operand:SI 1 "incdec_operand" "")))
5930 (if_then_else (match_operator 3 "eqne_operator"
5931 [(cc0) (const_int 0)])
5932 (label_ref (match_operand 2 "" ""))
5934 "(TARGET_H8300H || TARGET_H8300S)
5935 && INTVAL (operands[1]) != 0
5936 && !peep2_reg_dead_p (1, operands[0])
5937 && !same_cmp_following_p (insn)"
5941 (unspec:SI [(match_dup 4)
5944 (set (cc0) (compare (match_dup 4)
5947 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5948 (label_ref (match_dup 2))
5950 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
5952 ;; Narrow the mode of testing if possible.
5955 [(set (match_operand:HI 0 "register_operand" "")
5956 (and:HI (match_dup 0)
5957 (match_operand:HI 1 "const_int_qi_operand" "")))
5958 (set (cc0) (compare (match_dup 0)
5961 (if_then_else (match_operator 3 "eqne_operator"
5962 [(cc0) (const_int 0)])
5963 (label_ref (match_operand 2 "" ""))
5965 "peep2_reg_dead_p (2, operands[0])"
5967 (and:QI (match_dup 4)
5969 (set (cc0) (compare (match_dup 4)
5972 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5973 (label_ref (match_dup 2))
5975 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5976 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5979 [(set (match_operand:SI 0 "register_operand" "")
5980 (and:SI (match_dup 0)
5981 (match_operand:SI 1 "const_int_qi_operand" "")))
5982 (set (cc0) (compare (match_dup 0)
5985 (if_then_else (match_operator 3 "eqne_operator"
5986 [(cc0) (const_int 0)])
5987 (label_ref (match_operand 2 "" ""))
5989 "peep2_reg_dead_p (2, operands[0])"
5991 (and:QI (match_dup 4)
5993 (set (cc0) (compare (match_dup 4)
5996 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5997 (label_ref (match_dup 2))
5999 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
6000 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
6003 [(set (match_operand:SI 0 "register_operand" "")
6004 (and:SI (match_dup 0)
6005 (match_operand:SI 1 "const_int_hi_operand" "")))
6006 (set (cc0) (compare (match_dup 0)
6009 (if_then_else (match_operator 3 "eqne_operator"
6010 [(cc0) (const_int 0)])
6011 (label_ref (match_operand 2 "" ""))
6013 "peep2_reg_dead_p (2, operands[0])"
6015 (and:HI (match_dup 4)
6017 (set (cc0) (compare (match_dup 4)
6020 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6021 (label_ref (match_dup 2))
6023 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
6024 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
6027 [(set (match_operand:SI 0 "register_operand" "")
6028 (and:SI (match_dup 0)
6029 (match_operand:SI 1 "const_int_qi_operand" "")))
6031 (xor:SI (match_dup 0)
6032 (match_operand:SI 2 "const_int_qi_operand" "")))
6033 (set (cc0) (compare (match_dup 0)
6036 (if_then_else (match_operator 4 "eqne_operator"
6037 [(cc0) (const_int 0)])
6038 (label_ref (match_operand 3 "" ""))
6040 "peep2_reg_dead_p (3, operands[0])
6041 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
6043 (and:QI (match_dup 5)
6046 (xor:QI (match_dup 5)
6048 (set (cc0) (compare (match_dup 5)
6051 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
6052 (label_ref (match_dup 3))
6054 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
6055 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
6056 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
6058 ;; These triggers right at the end of allocation of locals in the
6059 ;; prologue (and possibly at other places).
6061 ;; stack adjustment of -4, generate one push
6063 ;; before : 6 bytes, 10 clocks
6064 ;; after : 4 bytes, 10 clocks
6067 [(set (reg:SI SP_REG)
6068 (plus:SI (reg:SI SP_REG)
6070 (set (mem:SI (reg:SI SP_REG))
6071 (match_operand:SI 0 "register_operand" ""))]
6072 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6073 && REGNO (operands[0]) != SP_REG"
6074 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6078 ;; stack adjustment of -12, generate one push
6080 ;; before : 10 bytes, 14 clocks
6081 ;; after : 8 bytes, 14 clocks
6084 [(set (reg:SI SP_REG)
6085 (plus:SI (reg:SI SP_REG)
6087 (set (mem:SI (reg:SI SP_REG))
6088 (match_operand:SI 0 "register_operand" ""))]
6089 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6090 && REGNO (operands[0]) != SP_REG"
6091 [(set (reg:SI SP_REG)
6092 (plus:SI (reg:SI SP_REG)
6094 (set (reg:SI SP_REG)
6095 (plus:SI (reg:SI SP_REG)
6097 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6111 ;; if "reg" dies at the end of the sequence.
6113 [(set (match_operand 0 "register_operand" "")
6114 (match_operand 1 "memory_operand" ""))
6116 (match_operator 2 "h8sx_binary_memory_operator"
6118 (match_operand 3 "h8300_src_operand" "")]))
6119 (set (match_operand 4 "memory_operand" "")
6121 "0 /* Disable because it breaks compiling fp-bit.c. */
6123 && peep2_reg_dead_p (3, operands[0])
6124 && !reg_overlap_mentioned_p (operands[0], operands[3])
6125 && !reg_overlap_mentioned_p (operands[0], operands[4])
6126 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
6130 operands[5] = shallow_copy_rtx (operands[2]);
6131 XEXP (operands[5], 0) = operands[1];
6143 ;; if "reg" dies in the second insn.
6145 [(set (match_operand 0 "register_operand" "")
6146 (match_operand 1 "h8300_src_operand" ""))
6147 (set (match_operand 2 "h8300_dst_operand" "")
6148 (match_operator 3 "h8sx_binary_memory_operator"
6149 [(match_operand 4 "h8300_dst_operand" "")
6151 "0 /* Disable because it breaks compiling fp-bit.c. */
6153 && peep2_reg_dead_p (2, operands[0])
6154 && !reg_overlap_mentioned_p (operands[0], operands[4])"
6158 operands[5] = shallow_copy_rtx (operands[3]);
6159 XEXP (operands[5], 1) = operands[1];
6172 ;; if "reg" dies at the end of the sequence.
6174 [(set (match_operand 0 "register_operand" "")
6175 (match_operand 1 "memory_operand" ""))
6177 (match_operator 2 "h8sx_unary_memory_operator"
6179 (set (match_operand 3 "memory_operand" "")
6182 && peep2_reg_dead_p (3, operands[0])
6183 && !reg_overlap_mentioned_p (operands[0], operands[3])
6184 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
6188 operands[4] = shallow_copy_rtx (operands[2]);
6189 XEXP (operands[4], 0) = operands[1];
6201 ;; if "reg" dies in the comparison.
6203 [(set (match_operand 0 "register_operand" "")
6204 (match_operand 1 "h8300_dst_operand" ""))
6206 (compare (match_dup 0)
6207 (match_operand 2 "h8300_src_operand" "")))]
6209 && peep2_reg_dead_p (2, operands[0])
6210 && !reg_overlap_mentioned_p (operands[0], operands[2])
6211 && operands[2] != const0_rtx"
6213 (compare (match_dup 1)
6216 ;; Likewise for the second operand.
6218 [(set (match_operand 0 "register_operand" "")
6219 (match_operand 1 "h8300_src_operand" ""))
6221 (compare (match_operand 2 "h8300_dst_operand" "")
6224 && peep2_reg_dead_p (2, operands[0])
6225 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6227 (compare (match_dup 2)
6230 ;; Combine two moves.
6232 [(set (match_operand 0 "register_operand" "")
6233 (match_operand 1 "h8300_src_operand" ""))
6234 (set (match_operand 2 "h8300_dst_operand" "")
6237 && peep2_reg_dead_p (2, operands[0])
6238 && !reg_overlap_mentioned_p (operands[0], operands[2])"