1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg (rtx, int);
50 static int h8300_interrupt_function_p (tree);
51 static int h8300_monitor_function_p (tree);
52 static int h8300_os_task_function_p (tree);
53 static void dosize (int, unsigned int);
54 static int round_frame_size (int);
55 static unsigned int compute_saved_regs (void);
56 static void push (int);
57 static void pop (int);
58 static const char *cond_string (enum rtx_code);
59 static unsigned int h8300_asm_insn_count (const char *);
60 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
61 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
62 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
63 #ifndef OBJECT_FORMAT_ELF
64 static void h8300_asm_named_section (const char *, unsigned int);
66 static int h8300_and_costs (rtx);
67 static int h8300_shift_costs (rtx);
69 /* CPU_TYPE, says what cpu we're compiling for. */
72 /* True if a #pragma interrupt has been seen for the current function. */
73 static int pragma_interrupt;
75 /* True if a #pragma saveall has been seen for the current function. */
76 static int pragma_saveall;
78 static const char *const names_big[] =
79 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
81 static const char *const names_extended[] =
82 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
84 static const char *const names_upper_extended[] =
85 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
87 /* Points to one of the above. */
88 /* ??? The above could be put in an array indexed by CPU_TYPE. */
89 const char * const *h8_reg_names;
91 /* Various operations needed by the following, indexed by CPU_TYPE. */
93 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
95 /* Machine-specific symbol_ref flags. */
96 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
97 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
98 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
100 /* See below where shifts are handled for explanation of this enum. */
110 /* Symbols of the various shifts which can be used as indices. */
114 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
117 /* Macros to keep the shift algorithm tables small. */
118 #define INL SHIFT_INLINE
119 #define ROT SHIFT_ROT_AND
120 #define LOP SHIFT_LOOP
121 #define SPC SHIFT_SPECIAL
123 /* The shift algorithms for each machine, mode, shift type, and shift
124 count are defined below. The three tables below correspond to
125 QImode, HImode, and SImode, respectively. Each table is organized
126 by, in the order of indices, machine, shift type, and shift count. */
128 static enum shift_alg shift_alg_qi[3][3][8] = {
131 /* 0 1 2 3 4 5 6 7 */
132 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
133 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
134 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
138 /* 0 1 2 3 4 5 6 7 */
139 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
140 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
141 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
145 /* 0 1 2 3 4 5 6 7 */
146 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
147 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
148 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
152 static enum shift_alg shift_alg_hi[3][3][16] = {
155 /* 0 1 2 3 4 5 6 7 */
156 /* 8 9 10 11 12 13 14 15 */
157 { INL, INL, INL, INL, INL, INL, INL, SPC,
158 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
159 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
166 /* 0 1 2 3 4 5 6 7 */
167 /* 8 9 10 11 12 13 14 15 */
168 { INL, INL, INL, INL, INL, INL, INL, SPC,
169 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
177 /* 0 1 2 3 4 5 6 7 */
178 /* 8 9 10 11 12 13 14 15 */
179 { INL, INL, INL, INL, INL, INL, INL, INL,
180 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
188 static enum shift_alg shift_alg_si[3][3][32] = {
191 /* 0 1 2 3 4 5 6 7 */
192 /* 8 9 10 11 12 13 14 15 */
193 /* 16 17 18 19 20 21 22 23 */
194 /* 24 25 26 27 28 29 30 31 */
195 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
196 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
197 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
198 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
199 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
200 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
201 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
203 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
204 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
205 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
206 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
210 /* 0 1 2 3 4 5 6 7 */
211 /* 8 9 10 11 12 13 14 15 */
212 /* 16 17 18 19 20 21 22 23 */
213 /* 24 25 26 27 28 29 30 31 */
214 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
215 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
216 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
218 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
219 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
220 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
222 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
223 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
224 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
229 /* 0 1 2 3 4 5 6 7 */
230 /* 8 9 10 11 12 13 14 15 */
231 /* 16 17 18 19 20 21 22 23 */
232 /* 24 25 26 27 28 29 30 31 */
233 { INL, INL, INL, INL, INL, INL, INL, INL,
234 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
235 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
236 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
237 { INL, INL, INL, INL, INL, INL, INL, INL,
238 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
239 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
240 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
241 { INL, INL, INL, INL, INL, INL, INL, INL,
242 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
243 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
244 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
260 /* Initialize various cpu specific globals at start up. */
263 h8300_init_once (void)
265 static const char *const h8_push_ops[2] = { "push" , "push.l" };
266 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
267 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
271 cpu_type = (int) CPU_H8300;
272 h8_reg_names = names_big;
276 /* For this we treat the H8/300H and H8S the same. */
277 cpu_type = (int) CPU_H8300H;
278 h8_reg_names = names_extended;
280 h8_push_op = h8_push_ops[cpu_type];
281 h8_pop_op = h8_pop_ops[cpu_type];
282 h8_mov_op = h8_mov_ops[cpu_type];
284 if (!TARGET_H8300S && TARGET_MAC)
286 error ("-ms2600 is used without -ms");
287 target_flags |= MASK_H8300S;
290 if (TARGET_H8300 && TARGET_NORMAL_MODE)
292 error ("-mn is used without -mh or -ms");
293 target_flags ^= MASK_NORMAL_MODE;
296 /* Some of the shifts are optimized for speed by default.
297 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
298 If optimizing for size, change shift_alg for those shift to
303 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
304 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
309 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
312 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
315 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
316 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
319 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
322 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
327 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
332 byte_reg (rtx x, int b)
334 static const char *const names_small[] = {
335 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
336 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
339 return names_small[REGNO (x) * 2 + b];
342 /* REGNO must be saved/restored across calls if this macro is true. */
344 #define WORD_REG_USED(regno) \
346 /* No need to save registers if this function will not return. */ \
347 && ! TREE_THIS_VOLATILE (current_function_decl) \
349 /* Save any call saved register that was used. */ \
350 || (regs_ever_live[regno] && !call_used_regs[regno]) \
351 /* Save the frame pointer if it was used. */ \
352 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
353 /* Save any register used in an interrupt handler. */ \
354 || (h8300_current_function_interrupt_function_p () \
355 && regs_ever_live[regno]) \
356 /* Save call clobbered registers in non-leaf interrupt \
358 || (h8300_current_function_interrupt_function_p () \
359 && call_used_regs[regno] \
360 && !current_function_is_leaf)))
362 /* Output assembly language to FILE for the operation OP with operand size
363 SIZE to adjust the stack pointer. */
370 /* H8/300 cannot add/subtract a large constant with a single
371 instruction. If a temporary register is available, load the
372 constant to it and then do the addition. */
375 && !h8300_current_function_interrupt_function_p ()
376 && !(current_function_needs_context && sign < 0))
379 rtx r3 = gen_rtx_REG (Pmode, 3);
380 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
381 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
382 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
386 /* The stack adjustment made here is further optimized by the
387 splitter. In case of H8/300, the splitter always splits the
388 addition emitted here to make the adjustment
390 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
391 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
395 /* Round up frame size SIZE. */
398 round_frame_size (int size)
400 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
401 & -STACK_BOUNDARY / BITS_PER_UNIT);
404 /* Compute which registers to push/pop.
405 Return a bit vector of registers. */
408 compute_saved_regs (void)
410 unsigned int saved_regs = 0;
413 /* Construct a bit vector of registers to be pushed/popped. */
414 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
416 if (WORD_REG_USED (regno))
417 saved_regs |= 1 << regno;
420 /* Don't push/pop the frame pointer as it is treated separately. */
421 if (frame_pointer_needed)
422 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
427 /* Emit an insn to push register RN. */
432 rtx reg = gen_rtx_REG (word_mode, rn);
436 x = gen_push_h8300 (reg);
438 x = gen_push_h8300hs (reg);
440 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
443 /* Emit an insn to pop register RN. */
448 rtx reg = gen_rtx_REG (word_mode, rn);
452 x = gen_pop_h8300 (reg);
454 x = gen_pop_h8300hs (reg);
456 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
459 /* This is what the stack looks like after the prolog of
460 a function with a frame has been set up:
466 <saved registers> <- sp
468 This is what the stack looks like after the prolog of
469 a function which doesn't have a frame:
474 <saved registers> <- sp
477 /* Generate RTL code for the function prologue. */
480 h8300_expand_prologue (void)
486 /* If the current function has the OS_Task attribute set, then
487 we have a naked prologue. */
488 if (h8300_os_task_function_p (current_function_decl))
491 if (h8300_monitor_function_p (current_function_decl))
492 /* My understanding of monitor functions is they act just like
493 interrupt functions, except the prologue must mask
495 emit_insn (gen_monitor_prologue ());
497 if (frame_pointer_needed)
500 push (FRAME_POINTER_REGNUM);
501 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
504 /* Leave room for locals. */
505 dosize (-1, round_frame_size (get_frame_size ()));
507 /* Push the rest of the registers in ascending order. */
508 saved_regs = compute_saved_regs ();
509 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
512 if (saved_regs & (1 << regno))
516 /* See how many registers we can push at the same time. */
517 if ((regno == 0 || regno == 4)
518 && ((saved_regs >> regno) & 0x0f) == 0x0f)
521 else if ((regno == 0 || regno == 4)
522 && ((saved_regs >> regno) & 0x07) == 0x07)
525 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
526 && ((saved_regs >> regno) & 0x03) == 0x03)
536 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
537 gen_rtx_REG (SImode, regno + 1)));
540 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
541 gen_rtx_REG (SImode, regno + 1),
542 gen_rtx_REG (SImode, regno + 2)));
545 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
546 gen_rtx_REG (SImode, regno + 1),
547 gen_rtx_REG (SImode, regno + 2),
548 gen_rtx_REG (SImode, regno + 3)));
558 h8300_can_use_return_insn_p (void)
560 return (reload_completed
561 && !frame_pointer_needed
562 && get_frame_size () == 0
563 && compute_saved_regs () == 0);
566 /* Generate RTL code for the function epilogue. */
569 h8300_expand_epilogue (void)
575 if (h8300_os_task_function_p (current_function_decl))
576 /* OS_Task epilogues are nearly naked -- they just have an
580 /* Pop the saved registers in descending order. */
581 saved_regs = compute_saved_regs ();
582 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
585 if (saved_regs & (1 << regno))
589 /* See how many registers we can pop at the same time. */
590 if ((regno == 7 || regno == 3)
591 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
594 else if ((regno == 6 || regno == 2)
595 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
598 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
599 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
609 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
610 gen_rtx_REG (SImode, regno)));
613 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
614 gen_rtx_REG (SImode, regno - 1),
615 gen_rtx_REG (SImode, regno)));
618 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
619 gen_rtx_REG (SImode, regno - 2),
620 gen_rtx_REG (SImode, regno - 1),
621 gen_rtx_REG (SImode, regno)));
629 /* Deallocate locals. */
630 dosize (1, round_frame_size (get_frame_size ()));
632 /* Pop frame pointer if we had one. */
633 if (frame_pointer_needed)
634 pop (FRAME_POINTER_REGNUM);
637 /* Output assembly language code for the function epilogue. */
640 h8300_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
641 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
646 /* Return nonzero if the current function is an interrupt
650 h8300_current_function_interrupt_function_p (void)
652 return (h8300_interrupt_function_p (current_function_decl)
653 || h8300_monitor_function_p (current_function_decl));
656 /* Output assembly code for the start of the file. */
659 h8300_file_start (void)
661 default_file_start ();
664 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
665 else if (TARGET_H8300S)
666 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
669 /* Output assembly language code for the end of file. */
672 h8300_file_end (void)
674 fputs ("\t.end\n", asm_out_file);
677 /* Return true if OP is a valid source operand for an integer move
681 general_operand_src (rtx op, enum machine_mode mode)
683 if (GET_MODE (op) == mode
684 && GET_CODE (op) == MEM
685 && GET_CODE (XEXP (op, 0)) == POST_INC)
687 return general_operand (op, mode);
690 /* Return true if OP is a valid destination operand for an integer move
694 general_operand_dst (rtx op, enum machine_mode mode)
696 if (GET_MODE (op) == mode
697 && GET_CODE (op) == MEM
698 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
700 return general_operand (op, mode);
703 /* Return true if OP is a constant that contains only one 1 in its
704 binary representation. */
707 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
709 if (GET_CODE (operand) == CONST_INT)
711 /* We really need to do this masking because 0x80 in QImode is
712 represented as -128 for example. */
713 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
720 /* Return true if OP is a constant that contains only one 0 in its
721 binary representation. */
724 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
726 if (GET_CODE (operand) == CONST_INT)
728 /* We really need to do this masking because 0x80 in QImode is
729 represented as -128 for example. */
730 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
737 /* Return true if OP is a valid call operand. */
740 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
742 if (GET_CODE (op) == MEM)
744 rtx inside = XEXP (op, 0);
745 if (register_operand (inside, Pmode))
747 if (CONSTANT_ADDRESS_P (inside))
753 /* Return 1 if an addition/subtraction of a constant integer can be
754 transformed into two consecutive adds/subs that are faster than the
755 straightforward way. Otherwise, return 0. */
758 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
760 if (GET_CODE (op) == CONST_INT)
762 HOST_WIDE_INT value = INTVAL (op);
764 /* Force VALUE to be positive so that we do not have to consider
765 the negative case. */
768 if (TARGET_H8300H || TARGET_H8300S)
770 /* A constant addition/subtraction takes 2 states in QImode,
771 4 states in HImode, and 6 states in SImode. Thus, the
772 only case we can win is when SImode is used, in which
773 case, two adds/subs are used, taking 4 states. */
783 /* We do not profit directly by splitting addition or
784 subtraction of 3 and 4. However, since these are
785 implemented as a sequence of adds or subs, they do not
786 clobber (cc0) unlike a sequence of add.b and add.x. */
797 /* Split an add of a small constant into two adds/subs insns.
799 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
800 instead of adds/subs. */
803 split_adds_subs (enum machine_mode mode, rtx *operands)
805 HOST_WIDE_INT val = INTVAL (operands[1]);
806 rtx reg = operands[0];
807 HOST_WIDE_INT sign = 1;
808 HOST_WIDE_INT amount;
809 rtx (*gen_add) (rtx, rtx, rtx);
811 /* Force VAL to be positive so that we do not have to consider the
822 gen_add = gen_addhi3;
826 gen_add = gen_addsi3;
833 /* Try different amounts in descending order. */
834 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
838 for (; val >= amount; val -= amount)
839 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
845 /* Return true if OP is a valid call operand, and OP represents
846 an operand for a small call (4 bytes instead of 6 bytes). */
849 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
851 if (GET_CODE (op) == MEM)
853 rtx inside = XEXP (op, 0);
855 /* Register indirect is a small call. */
856 if (register_operand (inside, Pmode))
859 /* A call through the function vector is a small call too. */
860 if (GET_CODE (inside) == SYMBOL_REF
861 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
864 /* Otherwise it's a large call. */
868 /* Return true if OP is a valid jump operand. */
871 jump_address_operand (rtx op, enum machine_mode mode)
873 if (GET_CODE (op) == REG)
874 return mode == Pmode;
876 if (GET_CODE (op) == MEM)
878 rtx inside = XEXP (op, 0);
879 if (register_operand (inside, Pmode))
881 if (CONSTANT_ADDRESS_P (inside))
887 /* Recognize valid operands for bit-field instructions. */
889 extern int rtx_equal_function_value_matters;
892 bit_operand (rtx op, enum machine_mode mode)
894 /* We can accept any general operand, except that MEM operands must
895 be limited to those that use addresses valid for the 'U' constraint. */
896 if (!general_operand (op, mode))
899 /* Accept any mem during RTL generation. Otherwise, the code that does
900 insv and extzv will think that we can not handle memory. However,
901 to avoid reload problems, we only accept 'U' MEM operands after RTL
902 generation. This means that any named pattern which uses this predicate
903 must force its operands to match 'U' before emitting RTL. */
905 if (GET_CODE (op) == REG)
907 if (GET_CODE (op) == SUBREG)
909 return (GET_CODE (op) == MEM
910 && EXTRA_CONSTRAINT (op, 'U'));
914 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
916 return (GET_CODE (op) == MEM
917 && EXTRA_CONSTRAINT (op, 'U'));
920 /* Handle machine specific pragmas for compatibility with existing
921 compilers for the H8/300.
923 pragma saveall generates prologue/epilogue code which saves and
924 restores all the registers on function entry.
926 pragma interrupt saves and restores all registers, and exits with
927 an rte instruction rather than an rts. A pointer to a function
928 with this attribute may be safely used in an interrupt vector. */
931 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
933 pragma_interrupt = 1;
937 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
942 /* If the next function argument with MODE and TYPE is to be passed in
943 a register, return a reg RTX for the hard register in which to pass
944 the argument. CUM represents the state after the last argument.
945 If the argument is to be pushed, NULL_RTX is returned. */
948 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
949 tree type, int named)
951 static const char *const hand_list[] = {
970 rtx result = NULL_RTX;
974 /* Never pass unnamed arguments in registers. */
978 /* Pass 3 regs worth of data in regs when user asked on the command line. */
979 if (TARGET_QUICKCALL)
982 /* If calling hand written assembler, use 4 regs of args. */
985 const char * const *p;
987 fname = XSTR (cum->libcall, 0);
989 /* See if this libcall is one of the hand coded ones. */
990 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1001 if (mode == BLKmode)
1002 size = int_size_in_bytes (type);
1004 size = GET_MODE_SIZE (mode);
1006 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1007 && cum->nbytes / UNITS_PER_WORD <= 3)
1008 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1015 h8300_and_costs (rtx x)
1019 if (GET_MODE (x) == QImode)
1022 if (GET_MODE (x) != HImode
1023 && GET_MODE (x) != SImode)
1028 operands[2] = XEXP (x, 1);
1030 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1034 h8300_shift_costs (rtx x)
1038 if (GET_MODE (x) != QImode
1039 && GET_MODE (x) != HImode
1040 && GET_MODE (x) != SImode)
1045 operands[2] = XEXP (x, 1);
1047 return compute_a_shift_length (NULL, operands) / 2;
1051 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1057 HOST_WIDE_INT n = INTVAL (x);
1059 if (-4 <= n || n <= 4)
1070 *total = 0 + (outer_code == SET);
1074 if (TARGET_H8300H || TARGET_H8300S)
1075 *total = 0 + (outer_code == SET);
1096 *total = COSTS_N_INSNS (h8300_and_costs (x));
1099 /* We say that MOD and DIV are so expensive because otherwise we'll
1100 generate some really horrible code for division of a power of two. */
1113 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1118 if (GET_MODE (x) == HImode)
1130 /* Documentation for the machine specific operand escapes:
1132 'E' like s but negative.
1133 'F' like t but negative.
1134 'G' constant just the negative
1135 'R' print operand as a byte:8 address if appropriate, else fall back to
1137 'S' print operand as a long word
1138 'T' print operand as a word
1139 'V' find the set bit, and print its number.
1140 'W' find the clear bit, and print its number.
1141 'X' print operand as a byte
1142 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1143 If this operand isn't a register, fall back to 'R' handling.
1145 'c' print the opcode corresponding to rtl
1146 'e' first word of 32 bit value - if reg, then least reg. if mem
1147 then least. if const then most sig word
1148 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1149 then +2. if const then least sig word
1150 'j' print operand as condition code.
1151 'k' print operand as reverse condition code.
1152 's' print as low byte of 16 bit value
1153 't' print as high byte of 16 bit value
1154 'w' print as low byte of 32 bit value
1155 'x' print as 2nd byte of 32 bit value
1156 'y' print as 3rd byte of 32 bit value
1157 'z' print as msb of 32 bit value
1160 /* Return assembly language string which identifies a comparison type. */
1163 cond_string (enum rtx_code code)
1192 /* Print operand X using operand code CODE to assembly language output file
1196 print_operand (FILE *file, rtx x, int code)
1198 /* This is used for communication between codes V,W,Z and Y. */
1204 switch (GET_CODE (x))
1207 fprintf (file, "%sl", names_big[REGNO (x)]);
1210 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1217 switch (GET_CODE (x))
1220 fprintf (file, "%sh", names_big[REGNO (x)]);
1223 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1230 if (GET_CODE (x) != CONST_INT)
1232 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1235 if (GET_CODE (x) == REG)
1236 fprintf (file, "%s", names_extended[REGNO (x)]);
1241 if (GET_CODE (x) == REG)
1242 fprintf (file, "%s", names_big[REGNO (x)]);
1247 bitint = exact_log2 (INTVAL (x) & 0xff);
1250 fprintf (file, "#%d", bitint);
1253 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1256 fprintf (file, "#%d", bitint);
1260 if (GET_CODE (x) == REG)
1261 fprintf (file, "%s", byte_reg (x, 0));
1268 if (GET_CODE (x) == REG)
1269 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1271 print_operand (file, x, 'R');
1275 bitint = INTVAL (x);
1276 fprintf (file, "#%d", bitint & 7);
1279 switch (GET_CODE (x))
1282 fprintf (file, "or");
1285 fprintf (file, "xor");
1288 fprintf (file, "and");
1295 switch (GET_CODE (x))
1299 fprintf (file, "%s", names_big[REGNO (x)]);
1301 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1304 print_operand (file, x, 0);
1307 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1313 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1314 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1315 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1324 switch (GET_CODE (x))
1328 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1330 fprintf (file, "%s", names_big[REGNO (x)]);
1333 x = adjust_address (x, HImode, 2);
1334 print_operand (file, x, 0);
1337 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1343 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1344 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1345 fprintf (file, "#%ld", (val & 0xffff));
1353 fputs (cond_string (GET_CODE (x)), file);
1356 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1359 if (GET_CODE (x) == CONST_INT)
1360 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1362 fprintf (file, "%s", byte_reg (x, 0));
1365 if (GET_CODE (x) == CONST_INT)
1366 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1368 fprintf (file, "%s", byte_reg (x, 1));
1371 if (GET_CODE (x) == CONST_INT)
1372 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1374 fprintf (file, "%s",
1375 byte_reg (x, TARGET_H8300 ? 2 : 0));
1378 if (GET_CODE (x) == CONST_INT)
1379 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1381 fprintf (file, "%s",
1382 byte_reg (x, TARGET_H8300 ? 3 : 1));
1385 if (GET_CODE (x) == CONST_INT)
1386 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1388 fprintf (file, "%s", byte_reg (x, 0));
1391 if (GET_CODE (x) == CONST_INT)
1392 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1394 fprintf (file, "%s", byte_reg (x, 1));
1399 switch (GET_CODE (x))
1402 switch (GET_MODE (x))
1405 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1406 fprintf (file, "%s", byte_reg (x, 0));
1407 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1408 fprintf (file, "%s", names_big[REGNO (x)]);
1412 fprintf (file, "%s", names_big[REGNO (x)]);
1416 fprintf (file, "%s", names_extended[REGNO (x)]);
1425 rtx addr = XEXP (x, 0);
1427 fprintf (file, "@");
1428 output_address (addr);
1430 /* We fall back from smaller addressing to larger
1431 addressing in various ways depending on CODE. */
1435 /* Used for mov.b and bit operations. */
1436 if (h8300_eightbit_constant_address_p (addr))
1438 fprintf (file, ":8");
1442 /* Fall through. We should not get here if we are
1443 processing bit operations on H8/300 or H8/300H
1444 because 'U' constraint does not allow bit
1445 operations on the tiny area on these machines. */
1449 /* Used for mov.w and mov.l. */
1450 if (h8300_tiny_constant_address_p (addr))
1451 fprintf (file, ":16");
1463 fprintf (file, "#");
1464 print_operand_address (file, x);
1470 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1471 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1472 fprintf (file, "#%ld", val);
1481 /* Output assembly language output for the address ADDR to FILE. */
1484 print_operand_address (FILE *file, rtx addr)
1486 switch (GET_CODE (addr))
1489 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1493 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1497 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1501 fprintf (file, "(");
1502 if (GET_CODE (XEXP (addr, 0)) == REG)
1505 print_operand_address (file, XEXP (addr, 1));
1506 fprintf (file, ",");
1507 print_operand_address (file, XEXP (addr, 0));
1512 print_operand_address (file, XEXP (addr, 0));
1513 fprintf (file, "+");
1514 print_operand_address (file, XEXP (addr, 1));
1516 fprintf (file, ")");
1521 /* Since the H8/300 only has 16 bit pointers, negative values are also
1522 those >= 32768. This happens for example with pointer minus a
1523 constant. We don't want to turn (char *p - 2) into
1524 (char *p + 65534) because loop unrolling can build upon this
1525 (IE: char *p + 131068). */
1526 int n = INTVAL (addr);
1528 n = (int) (short) n;
1529 fprintf (file, "%d", n);
1534 output_addr_const (file, addr);
1539 /* Output all insn addresses and their sizes into the assembly language
1540 output file. This is helpful for debugging whether the length attributes
1541 in the md file are correct. This is not meant to be a user selectable
1545 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1546 int num_operands ATTRIBUTE_UNUSED)
1548 /* This holds the last insn address. */
1549 static int last_insn_address = 0;
1551 const int uid = INSN_UID (insn);
1553 if (TARGET_ADDRESSES)
1555 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1556 INSN_ADDRESSES (uid) - last_insn_address);
1557 last_insn_address = INSN_ADDRESSES (uid);
1561 /* Prepare for an SI sized move. */
1564 do_movsi (rtx operands[])
1566 rtx src = operands[1];
1567 rtx dst = operands[0];
1568 if (!reload_in_progress && !reload_completed)
1570 if (!register_operand (dst, GET_MODE (dst)))
1572 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1573 emit_move_insn (tmp, src);
1580 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1581 Define the offset between two registers, one to be eliminated, and
1582 the other its replacement, at the start of a routine. */
1585 h8300_initial_elimination_offset (int from, int to)
1588 /* The number of bytes that the return address takes on the stack. */
1589 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1591 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1592 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1593 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1594 offset = frame_pointer_needed * UNITS_PER_WORD;
1599 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1600 if (WORD_REG_USED (regno))
1601 offset += UNITS_PER_WORD;
1603 /* See the comments for get_frame_size. We need to round it up to
1606 offset += round_frame_size (get_frame_size ());
1608 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1609 /* Skip saved PC. */
1617 h8300_return_addr_rtx (int count, rtx frame)
1622 ret = gen_rtx_MEM (Pmode,
1623 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1624 else if (flag_omit_frame_pointer)
1627 ret = gen_rtx_MEM (Pmode,
1628 memory_address (Pmode,
1629 plus_constant (frame, UNITS_PER_WORD)));
1630 set_mem_alias_set (ret, get_frame_alias_set ());
1634 /* Update the condition code from the insn. */
1637 notice_update_cc (rtx body, rtx insn)
1641 switch (get_attr_cc (insn))
1644 /* Insn does not affect CC at all. */
1648 /* Insn does not change CC, but the 0'th operand has been changed. */
1649 if (cc_status.value1 != 0
1650 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1651 cc_status.value1 = 0;
1652 if (cc_status.value2 != 0
1653 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1654 cc_status.value2 = 0;
1658 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1659 The V flag is unusable. The C flag may or may not be known but
1660 that's ok because alter_cond will change tests to use EQ/NE. */
1662 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1663 set = single_set (insn);
1664 cc_status.value1 = SET_SRC (set);
1665 if (SET_DEST (set) != cc0_rtx)
1666 cc_status.value2 = SET_DEST (set);
1670 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1671 The C flag may or may not be known but that's ok because
1672 alter_cond will change tests to use EQ/NE. */
1674 cc_status.flags |= CC_NO_CARRY;
1675 set = single_set (insn);
1676 cc_status.value1 = SET_SRC (set);
1677 if (SET_DEST (set) != cc0_rtx)
1679 /* If the destination is STRICT_LOW_PART, strip off
1681 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1682 cc_status.value2 = XEXP (SET_DEST (set), 0);
1684 cc_status.value2 = SET_DEST (set);
1689 /* The insn is a compare instruction. */
1691 cc_status.value1 = SET_SRC (body);
1695 /* Insn doesn't leave CC in a usable state. */
1701 /* Return nonzero if X is a stack pointer. */
1704 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1706 return x == stack_pointer_rtx;
1709 /* Return nonzero if X is a constant whose absolute value is greater
1713 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1715 return (GET_CODE (x) == CONST_INT
1716 && abs (INTVAL (x)) > 2);
1719 /* Return nonzero if X is a constant whose absolute value is no
1723 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1725 return (GET_CODE (x) == CONST_INT
1726 && abs (INTVAL (x)) >= 8);
1729 /* Return nonzero if X is a constant expressible in QImode. */
1732 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1734 return (GET_CODE (x) == CONST_INT
1735 && (INTVAL (x) & 0xff) == INTVAL (x));
1738 /* Return nonzero if X is a constant expressible in HImode. */
1741 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1743 return (GET_CODE (x) == CONST_INT
1744 && (INTVAL (x) & 0xffff) == INTVAL (x));
1747 /* Return nonzero if X is a constant suitable for inc/dec. */
1750 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1752 return (GET_CODE (x) == CONST_INT
1753 && (CONST_OK_FOR_M (INTVAL (x))
1754 || CONST_OK_FOR_O (INTVAL (x))));
1757 /* Return nonzero if X is either EQ or NE. */
1760 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1762 enum rtx_code code = GET_CODE (x);
1764 return (code == EQ || code == NE);
1767 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1770 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1772 enum rtx_code code = GET_CODE (x);
1774 return (code == GT || code == LE || code == GTU || code == LEU);
1777 /* Return nonzero if X is either GTU or LEU. */
1780 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1782 enum rtx_code code = GET_CODE (x);
1784 return (code == GTU || code == LEU);
1787 /* Return nonzero if X is either IOR or XOR. */
1790 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1792 enum rtx_code code = GET_CODE (x);
1794 return (code == IOR || code == XOR);
1797 /* Recognize valid operators for bit instructions. */
1800 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1802 enum rtx_code code = GET_CODE (x);
1809 /* Return the length of mov instruction. */
1812 compute_mov_length (rtx *operands)
1814 /* If the mov instruction involves a memory operand, we compute the
1815 length, assuming the largest addressing mode is used, and then
1816 adjust later in the function. Otherwise, we compute and return
1817 the exact length in one step. */
1818 enum machine_mode mode = GET_MODE (operands[0]);
1819 rtx dest = operands[0];
1820 rtx src = operands[1];
1823 if (GET_CODE (src) == MEM)
1824 addr = XEXP (src, 0);
1825 else if (GET_CODE (dest) == MEM)
1826 addr = XEXP (dest, 0);
1832 unsigned int base_length;
1837 if (addr == NULL_RTX)
1840 /* The eightbit addressing is available only in QImode, so
1841 go ahead and take care of it. */
1842 if (h8300_eightbit_constant_address_p (addr))
1849 if (addr == NULL_RTX)
1854 if (src == const0_rtx)
1864 if (addr == NULL_RTX)
1869 if (GET_CODE (src) == CONST_INT)
1871 if (src == const0_rtx)
1874 if ((INTVAL (src) & 0xffff) == 0)
1877 if ((INTVAL (src) & 0xffff) == 0)
1880 if ((INTVAL (src) & 0xffff)
1881 == ((INTVAL (src) >> 16) & 0xffff))
1891 if (addr == NULL_RTX)
1896 if (src == const0_rtx)
1909 /* Adjust the length based on the addressing mode used.
1910 Specifically, we subtract the difference between the actual
1911 length and the longest one, which is @(d:16,Rs). For SImode
1912 and SFmode, we double the adjustment because two mov.w are
1913 used to do the job. */
1915 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1916 if (GET_CODE (addr) == PRE_DEC
1917 || GET_CODE (addr) == POST_INC)
1919 if (mode == QImode || mode == HImode)
1920 return base_length - 2;
1922 /* In SImode and SFmode, we use two mov.w instructions, so
1923 double the adustment. */
1924 return base_length - 4;
1927 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1928 in SImode and SFmode, the second mov.w involves an address
1929 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1931 if (GET_CODE (addr) == REG)
1932 return base_length - 2;
1938 unsigned int base_length;
1943 if (addr == NULL_RTX)
1946 /* The eightbit addressing is available only in QImode, so
1947 go ahead and take care of it. */
1948 if (h8300_eightbit_constant_address_p (addr))
1955 if (addr == NULL_RTX)
1960 if (src == const0_rtx)
1970 if (addr == NULL_RTX)
1974 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
1980 if (GET_CODE (src) == CONST_INT)
1982 int val = INTVAL (src);
1987 if (val == (val & 0x00ff) || val == (val & 0xff00))
1990 switch (val & 0xffffffff)
2011 if (addr == NULL_RTX)
2016 if (src == const0_rtx)
2028 /* Adjust the length based on the addressing mode used.
2029 Specifically, we subtract the difference between the actual
2030 length and the longest one, which is @(d:24,ERs). */
2032 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2033 if (GET_CODE (addr) == PRE_DEC
2034 || GET_CODE (addr) == POST_INC)
2035 return base_length - 6;
2037 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2038 if (GET_CODE (addr) == REG)
2039 return base_length - 6;
2041 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2043 if (GET_CODE (addr) == PLUS
2044 && GET_CODE (XEXP (addr, 0)) == REG
2045 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2046 && INTVAL (XEXP (addr, 1)) > -32768
2047 && INTVAL (XEXP (addr, 1)) < 32767)
2048 return base_length - 4;
2050 /* @aa:16 is 4 bytes shorter than the longest. */
2051 if (h8300_tiny_constant_address_p (addr))
2052 return base_length - 4;
2054 /* @aa:24 is 2 bytes shorter than the longest. */
2055 if (CONSTANT_P (addr))
2056 return base_length - 2;
2063 output_plussi (rtx *operands)
2065 enum machine_mode mode = GET_MODE (operands[0]);
2072 if (GET_CODE (operands[2]) == REG)
2073 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2075 if (GET_CODE (operands[2]) == CONST_INT)
2077 HOST_WIDE_INT n = INTVAL (operands[2]);
2079 if ((n & 0xffffff) == 0)
2080 return "add\t%z2,%z0";
2081 if ((n & 0xffff) == 0)
2082 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2083 if ((n & 0xff) == 0)
2084 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2087 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2091 if (GET_CODE (operands[2]) == REG)
2092 return "add.l\t%S2,%S0";
2094 if (GET_CODE (operands[2]) == CONST_INT)
2096 HOST_WIDE_INT intval = INTVAL (operands[2]);
2098 /* See if we can finish with 2 bytes. */
2100 switch ((unsigned int) intval & 0xffffffff)
2105 return "adds\t%2,%S0";
2110 return "subs\t%G2,%S0";
2114 operands[2] = GEN_INT (intval >> 16);
2115 return "inc.w\t%2,%e0";
2119 operands[2] = GEN_INT (intval >> 16);
2120 return "dec.w\t%G2,%e0";
2123 /* See if we can finish with 4 bytes. */
2124 if ((intval & 0xffff) == 0)
2126 operands[2] = GEN_INT (intval >> 16);
2127 return "add.w\t%2,%e0";
2131 return "add.l\t%S2,%S0";
2136 compute_plussi_length (rtx *operands)
2138 enum machine_mode mode = GET_MODE (operands[0]);
2145 if (GET_CODE (operands[2]) == REG)
2148 if (GET_CODE (operands[2]) == CONST_INT)
2150 HOST_WIDE_INT n = INTVAL (operands[2]);
2152 if ((n & 0xffffff) == 0)
2154 if ((n & 0xffff) == 0)
2156 if ((n & 0xff) == 0)
2164 if (GET_CODE (operands[2]) == REG)
2167 if (GET_CODE (operands[2]) == CONST_INT)
2169 HOST_WIDE_INT intval = INTVAL (operands[2]);
2171 /* See if we can finish with 2 bytes. */
2173 switch ((unsigned int) intval & 0xffffffff)
2194 /* See if we can finish with 4 bytes. */
2195 if ((intval & 0xffff) == 0)
2204 compute_plussi_cc (rtx *operands)
2206 enum machine_mode mode = GET_MODE (operands[0]);
2217 if (GET_CODE (operands[2]) == REG)
2220 if (GET_CODE (operands[2]) == CONST_INT)
2222 HOST_WIDE_INT intval = INTVAL (operands[2]);
2224 /* See if we can finish with 2 bytes. */
2226 switch ((unsigned int) intval & 0xffffffff)
2231 return CC_NONE_0HIT;
2236 return CC_NONE_0HIT;
2247 /* See if we can finish with 4 bytes. */
2248 if ((intval & 0xffff) == 0)
2257 output_logical_op (enum machine_mode mode, rtx *operands)
2259 /* Figure out the logical op that we need to perform. */
2260 enum rtx_code code = GET_CODE (operands[3]);
2261 /* Pretend that every byte is affected if both operands are registers. */
2262 const unsigned HOST_WIDE_INT intval =
2263 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2264 ? INTVAL (operands[2]) : 0x55555555);
2265 /* The determinant of the algorithm. If we perform an AND, 0
2266 affects a bit. Otherwise, 1 affects a bit. */
2267 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2268 /* Break up DET into pieces. */
2269 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2270 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2271 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2272 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2273 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2274 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2275 int lower_half_easy_p = 0;
2276 int upper_half_easy_p = 0;
2277 /* The name of an insn. */
2299 /* First, see if we can finish with one insn. */
2300 if ((TARGET_H8300H || TARGET_H8300S)
2304 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2305 output_asm_insn (insn_buf, operands);
2309 /* Take care of the lower byte. */
2312 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2313 output_asm_insn (insn_buf, operands);
2315 /* Take care of the upper byte. */
2318 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2319 output_asm_insn (insn_buf, operands);
2324 if (TARGET_H8300H || TARGET_H8300S)
2326 /* Determine if the lower half can be taken care of in no more
2328 lower_half_easy_p = (b0 == 0
2330 || (code != IOR && w0 == 0xffff));
2332 /* Determine if the upper half can be taken care of in no more
2334 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2335 || (code == AND && w1 == 0xff00));
2338 /* Check if doing everything with one insn is no worse than
2339 using multiple insns. */
2340 if ((TARGET_H8300H || TARGET_H8300S)
2341 && w0 != 0 && w1 != 0
2342 && !(lower_half_easy_p && upper_half_easy_p)
2343 && !(code == IOR && w1 == 0xffff
2344 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2346 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2347 output_asm_insn (insn_buf, operands);
2351 /* Take care of the lower and upper words individually. For
2352 each word, we try different methods in the order of
2354 1) the special insn (in case of AND or XOR),
2355 2) the word-wise insn, and
2356 3) The byte-wise insn. */
2358 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2359 output_asm_insn ((code == AND)
2360 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2362 else if ((TARGET_H8300H || TARGET_H8300S)
2366 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2367 output_asm_insn (insn_buf, operands);
2373 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2374 output_asm_insn (insn_buf, operands);
2378 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2379 output_asm_insn (insn_buf, operands);
2384 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2385 output_asm_insn ((code == AND)
2386 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2388 else if ((TARGET_H8300H || TARGET_H8300S)
2391 && (w0 & 0x8000) != 0)
2393 output_asm_insn ("exts.l\t%S0", operands);
2395 else if ((TARGET_H8300H || TARGET_H8300S)
2399 output_asm_insn ("extu.w\t%e0", operands);
2401 else if (TARGET_H8300H || TARGET_H8300S)
2405 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2406 output_asm_insn (insn_buf, operands);
2413 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2414 output_asm_insn (insn_buf, operands);
2418 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2419 output_asm_insn (insn_buf, operands);
2431 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2433 /* Figure out the logical op that we need to perform. */
2434 enum rtx_code code = GET_CODE (operands[3]);
2435 /* Pretend that every byte is affected if both operands are registers. */
2436 const unsigned HOST_WIDE_INT intval =
2437 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2438 ? INTVAL (operands[2]) : 0x55555555);
2439 /* The determinant of the algorithm. If we perform an AND, 0
2440 affects a bit. Otherwise, 1 affects a bit. */
2441 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2442 /* Break up DET into pieces. */
2443 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2444 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2445 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2446 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2447 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2448 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2449 int lower_half_easy_p = 0;
2450 int upper_half_easy_p = 0;
2452 unsigned int length = 0;
2457 /* First, see if we can finish with one insn. */
2458 if ((TARGET_H8300H || TARGET_H8300S)
2462 if (REG_P (operands[2]))
2469 /* Take care of the lower byte. */
2473 /* Take care of the upper byte. */
2479 if (TARGET_H8300H || TARGET_H8300S)
2481 /* Determine if the lower half can be taken care of in no more
2483 lower_half_easy_p = (b0 == 0
2485 || (code != IOR && w0 == 0xffff));
2487 /* Determine if the upper half can be taken care of in no more
2489 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2490 || (code == AND && w1 == 0xff00));
2493 /* Check if doing everything with one insn is no worse than
2494 using multiple insns. */
2495 if ((TARGET_H8300H || TARGET_H8300S)
2496 && w0 != 0 && w1 != 0
2497 && !(lower_half_easy_p && upper_half_easy_p)
2498 && !(code == IOR && w1 == 0xffff
2499 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2501 if (REG_P (operands[2]))
2508 /* Take care of the lower and upper words individually. For
2509 each word, we try different methods in the order of
2511 1) the special insn (in case of AND or XOR),
2512 2) the word-wise insn, and
2513 3) The byte-wise insn. */
2515 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2519 else if ((TARGET_H8300H || TARGET_H8300S)
2535 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2539 else if ((TARGET_H8300H || TARGET_H8300S)
2542 && (w0 & 0x8000) != 0)
2546 else if ((TARGET_H8300H || TARGET_H8300S)
2552 else if (TARGET_H8300H || TARGET_H8300S)
2574 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2576 /* Figure out the logical op that we need to perform. */
2577 enum rtx_code code = GET_CODE (operands[3]);
2578 /* Pretend that every byte is affected if both operands are registers. */
2579 const unsigned HOST_WIDE_INT intval =
2580 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2581 ? INTVAL (operands[2]) : 0x55555555);
2582 /* The determinant of the algorithm. If we perform an AND, 0
2583 affects a bit. Otherwise, 1 affects a bit. */
2584 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2585 /* Break up DET into pieces. */
2586 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2587 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2588 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2589 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2590 int lower_half_easy_p = 0;
2591 int upper_half_easy_p = 0;
2592 /* Condition code. */
2593 enum attr_cc cc = CC_CLOBBER;
2598 /* First, see if we can finish with one insn. */
2599 if ((TARGET_H8300H || TARGET_H8300S)
2607 if (TARGET_H8300H || TARGET_H8300S)
2609 /* Determine if the lower half can be taken care of in no more
2611 lower_half_easy_p = (b0 == 0
2613 || (code != IOR && w0 == 0xffff));
2615 /* Determine if the upper half can be taken care of in no more
2617 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2618 || (code == AND && w1 == 0xff00));
2621 /* Check if doing everything with one insn is no worse than
2622 using multiple insns. */
2623 if ((TARGET_H8300H || TARGET_H8300S)
2624 && w0 != 0 && w1 != 0
2625 && !(lower_half_easy_p && upper_half_easy_p)
2626 && !(code == IOR && w1 == 0xffff
2627 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2633 if ((TARGET_H8300H || TARGET_H8300S)
2636 && (w0 & 0x8000) != 0)
2650 We devote a fair bit of code to getting efficient shifts since we
2651 can only shift one bit at a time on the H8/300 and H8/300H and only
2652 one or two bits at a time on the H8S.
2654 All shift code falls into one of the following ways of
2657 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2658 when a straight line shift is about the same size or smaller than
2661 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2662 off the bits we don't need. This is used when only a few of the
2663 bits in the original value will survive in the shifted value.
2665 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2666 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2667 shifts can be added if the shift count is slightly more than 8 or
2668 16. This case also includes other oddballs that are not worth
2671 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2673 For each shift count, we try to use code that has no trade-off
2674 between code size and speed whenever possible.
2676 If the trade-off is unavoidable, we try to be reasonable.
2677 Specifically, the fastest version is one instruction longer than
2678 the shortest version, we take the fastest version. We also provide
2679 the use a way to switch back to the shortest version with -Os.
2681 For the details of the shift algorithms for various shift counts,
2682 refer to shift_alg_[qhs]i. */
2685 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2687 switch (GET_CODE (x))
2699 /* Emit code to do shifts. */
2702 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2704 emit_move_insn (operands[0], operands[1]);
2706 /* Need a loop to get all the bits we want - we generate the
2707 code at emit time, but need to allocate a scratch reg now. */
2709 emit_insn (gen_rtx_PARALLEL
2712 gen_rtx_SET (VOIDmode, operands[0],
2713 gen_rtx (code, mode, operands[0],
2715 gen_rtx_CLOBBER (VOIDmode,
2716 gen_rtx_SCRATCH (QImode)))));
2719 /* Symbols of the various modes which can be used as indices. */
2723 QIshift, HIshift, SIshift
2726 /* For single bit shift insns, record assembler and what bits of the
2727 condition code are valid afterwards (represented as various CC_FOO
2728 bits, 0 means CC isn't left in a usable state). */
2732 const char *const assembler;
2736 /* Assembler instruction shift table.
2738 These tables are used to look up the basic shifts.
2739 They are indexed by cpu, shift_type, and mode. */
2741 static const struct shift_insn shift_one[2][3][3] =
2747 { "shll\t%X0", CC_SET_ZNV },
2748 { "add.w\t%T0,%T0", CC_SET_ZN },
2749 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2751 /* SHIFT_LSHIFTRT */
2753 { "shlr\t%X0", CC_SET_ZNV },
2754 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2755 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2757 /* SHIFT_ASHIFTRT */
2759 { "shar\t%X0", CC_SET_ZNV },
2760 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2761 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2768 { "shll.b\t%X0", CC_SET_ZNV },
2769 { "shll.w\t%T0", CC_SET_ZNV },
2770 { "shll.l\t%S0", CC_SET_ZNV }
2772 /* SHIFT_LSHIFTRT */
2774 { "shlr.b\t%X0", CC_SET_ZNV },
2775 { "shlr.w\t%T0", CC_SET_ZNV },
2776 { "shlr.l\t%S0", CC_SET_ZNV }
2778 /* SHIFT_ASHIFTRT */
2780 { "shar.b\t%X0", CC_SET_ZNV },
2781 { "shar.w\t%T0", CC_SET_ZNV },
2782 { "shar.l\t%S0", CC_SET_ZNV }
2787 static const struct shift_insn shift_two[3][3] =
2791 { "shll.b\t#2,%X0", CC_SET_ZNV },
2792 { "shll.w\t#2,%T0", CC_SET_ZNV },
2793 { "shll.l\t#2,%S0", CC_SET_ZNV }
2795 /* SHIFT_LSHIFTRT */
2797 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2798 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2799 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2801 /* SHIFT_ASHIFTRT */
2803 { "shar.b\t#2,%X0", CC_SET_ZNV },
2804 { "shar.w\t#2,%T0", CC_SET_ZNV },
2805 { "shar.l\t#2,%S0", CC_SET_ZNV }
2809 /* Rotates are organized by which shift they'll be used in implementing.
2810 There's no need to record whether the cc is valid afterwards because
2811 it is the AND insn that will decide this. */
2813 static const char *const rotate_one[2][3][3] =
2820 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2823 /* SHIFT_LSHIFTRT */
2826 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2829 /* SHIFT_ASHIFTRT */
2832 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2844 /* SHIFT_LSHIFTRT */
2850 /* SHIFT_ASHIFTRT */
2859 static const char *const rotate_two[3][3] =
2867 /* SHIFT_LSHIFTRT */
2873 /* SHIFT_ASHIFTRT */
2882 /* Shift algorithm. */
2885 /* The number of bits to be shifted by shift1 and shift2. Valid
2886 when ALG is SHIFT_SPECIAL. */
2887 unsigned int remainder;
2889 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2890 const char *special;
2892 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2893 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2896 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2897 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2900 /* CC status for SHIFT_INLINE. */
2903 /* CC status for SHIFT_SPECIAL. */
2907 static void get_shift_alg (enum shift_type,
2908 enum shift_mode, unsigned int,
2909 struct shift_info *);
2911 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2912 best algorithm for doing the shift. The assembler code is stored
2913 in the pointers in INFO. We achieve the maximum efficiency in most
2914 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2915 SImode in particular have a lot of room to optimize.
2917 We first determine the strategy of the shift algorithm by a table
2918 lookup. If that tells us to use a hand crafted assembly code, we
2919 go into the big switch statement to find what that is. Otherwise,
2920 we resort to a generic way, such as inlining. In either case, the
2921 result is returned through INFO. */
2924 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2925 unsigned int count, struct shift_info *info)
2929 /* Find the target CPU. */
2932 else if (TARGET_H8300H)
2937 /* Find the shift algorithm. */
2938 info->alg = SHIFT_LOOP;
2942 if (count < GET_MODE_BITSIZE (QImode))
2943 info->alg = shift_alg_qi[cpu][shift_type][count];
2947 if (count < GET_MODE_BITSIZE (HImode))
2948 info->alg = shift_alg_hi[cpu][shift_type][count];
2952 if (count < GET_MODE_BITSIZE (SImode))
2953 info->alg = shift_alg_si[cpu][shift_type][count];
2960 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2964 info->remainder = count;
2968 /* It is up to the caller to know that looping clobbers cc. */
2969 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2970 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2971 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2975 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2976 info->shift2 = rotate_two[shift_type][shift_mode];
2977 info->cc_inline = CC_CLOBBER;
2981 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2982 info->remainder = 0;
2983 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2984 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2985 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2986 info->cc_special = CC_CLOBBER;
2990 /* Here we only deal with SHIFT_SPECIAL. */
2994 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2995 through the entire value. */
2996 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2998 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3010 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3012 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3014 case SHIFT_LSHIFTRT:
3016 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3018 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3020 case SHIFT_ASHIFTRT:
3021 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3025 else if ((8 <= count && count <= 13)
3026 || (TARGET_H8300S && count == 14))
3028 info->remainder = count - 8;
3033 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3035 case SHIFT_LSHIFTRT:
3038 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3039 info->shift1 = "shlr.b\t%s0";
3040 info->cc_inline = CC_SET_ZNV;
3044 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3045 info->cc_special = CC_SET_ZNV;
3048 case SHIFT_ASHIFTRT:
3051 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3052 info->shift1 = "shar.b\t%s0";
3056 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3057 info->cc_special = CC_SET_ZNV;
3062 else if (count == 14)
3068 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3070 case SHIFT_LSHIFTRT:
3072 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3074 case SHIFT_ASHIFTRT:
3076 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3077 else if (TARGET_H8300H)
3079 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3080 info->cc_special = CC_SET_ZNV;
3082 else /* TARGET_H8300S */
3087 else if (count == 15)
3092 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3094 case SHIFT_LSHIFTRT:
3095 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3097 case SHIFT_ASHIFTRT:
3098 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3105 if (TARGET_H8300 && 8 <= count && count <= 9)
3107 info->remainder = count - 8;
3112 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3114 case SHIFT_LSHIFTRT:
3115 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3116 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3118 case SHIFT_ASHIFTRT:
3119 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3123 else if (count == 8 && !TARGET_H8300)
3128 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3130 case SHIFT_LSHIFTRT:
3131 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3133 case SHIFT_ASHIFTRT:
3134 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3138 else if (count == 15 && TARGET_H8300)
3144 case SHIFT_LSHIFTRT:
3145 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3147 case SHIFT_ASHIFTRT:
3148 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3152 else if (count == 15 && !TARGET_H8300)
3157 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3158 info->cc_special = CC_SET_ZNV;
3160 case SHIFT_LSHIFTRT:
3161 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3162 info->cc_special = CC_SET_ZNV;
3164 case SHIFT_ASHIFTRT:
3168 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3169 || (TARGET_H8300H && 16 <= count && count <= 19)
3170 || (TARGET_H8300S && 16 <= count && count <= 21))
3172 info->remainder = count - 16;
3177 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3179 info->shift1 = "add.w\t%e0,%e0";
3181 case SHIFT_LSHIFTRT:
3184 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3185 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3189 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3190 info->cc_special = CC_SET_ZNV;
3193 case SHIFT_ASHIFTRT:
3196 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3197 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3201 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3202 info->cc_special = CC_SET_ZNV;
3207 else if (TARGET_H8300 && 24 <= count && count <= 28)
3209 info->remainder = count - 24;
3214 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3215 info->shift1 = "shll.b\t%z0";
3216 info->cc_inline = CC_SET_ZNV;
3218 case SHIFT_LSHIFTRT:
3219 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3220 info->shift1 = "shlr.b\t%w0";
3221 info->cc_inline = CC_SET_ZNV;
3223 case SHIFT_ASHIFTRT:
3224 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3225 info->shift1 = "shar.b\t%w0";
3226 info->cc_inline = CC_SET_ZNV;
3230 else if ((TARGET_H8300H && count == 24)
3231 || (TARGET_H8300S && 24 <= count && count <= 25))
3233 info->remainder = count - 24;
3238 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3240 case SHIFT_LSHIFTRT:
3241 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3242 info->cc_special = CC_SET_ZNV;
3244 case SHIFT_ASHIFTRT:
3245 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3246 info->cc_special = CC_SET_ZNV;
3250 else if (!TARGET_H8300 && count == 28)
3256 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3258 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3260 case SHIFT_LSHIFTRT:
3263 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3264 info->cc_special = CC_SET_ZNV;
3267 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3269 case SHIFT_ASHIFTRT:
3273 else if (!TARGET_H8300 && count == 29)
3279 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3281 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3283 case SHIFT_LSHIFTRT:
3286 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3287 info->cc_special = CC_SET_ZNV;
3291 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3292 info->cc_special = CC_SET_ZNV;
3295 case SHIFT_ASHIFTRT:
3299 else if (!TARGET_H8300 && count == 30)
3305 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3307 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3309 case SHIFT_LSHIFTRT:
3311 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3313 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3315 case SHIFT_ASHIFTRT:
3319 else if (count == 31)
3326 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3328 case SHIFT_LSHIFTRT:
3329 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3331 case SHIFT_ASHIFTRT:
3332 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3341 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3342 info->cc_special = CC_SET_ZNV;
3344 case SHIFT_LSHIFTRT:
3345 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3346 info->cc_special = CC_SET_ZNV;
3348 case SHIFT_ASHIFTRT:
3349 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3350 info->cc_special = CC_SET_ZNV;
3363 info->shift2 = NULL;
3366 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3367 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3370 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3375 if (GET_MODE_BITSIZE (mode) <= count)
3378 /* Find out the target CPU. */
3381 else if (TARGET_H8300H)
3386 /* Find the shift algorithm. */
3390 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3391 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3392 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3396 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3397 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3398 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3402 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3403 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3404 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3411 /* On H8/300H, count == 8 uses a scratch register. */
3412 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3413 || (TARGET_H8300H && mode == SImode && count == 8));
3416 /* Emit the assembler code for doing shifts. */
3419 output_a_shift (rtx *operands)
3421 static int loopend_lab;
3422 rtx shift = operands[3];
3423 enum machine_mode mode = GET_MODE (shift);
3424 enum rtx_code code = GET_CODE (shift);
3425 enum shift_type shift_type;
3426 enum shift_mode shift_mode;
3427 struct shift_info info;
3434 shift_mode = QIshift;
3437 shift_mode = HIshift;
3440 shift_mode = SIshift;
3449 shift_type = SHIFT_ASHIFTRT;
3452 shift_type = SHIFT_LSHIFTRT;
3455 shift_type = SHIFT_ASHIFT;
3461 if (GET_CODE (operands[2]) != CONST_INT)
3463 /* This case must be taken care of by one of the two splitters
3464 that convert a variable shift into a loop. */
3469 int n = INTVAL (operands[2]);
3471 /* If the count is negative, make it 0. */
3474 /* If the count is too big, truncate it.
3475 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3476 do the intuitive thing. */
3477 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3478 n = GET_MODE_BITSIZE (mode);
3480 get_shift_alg (shift_type, shift_mode, n, &info);
3485 output_asm_insn (info.special, operands);
3491 /* Emit two bit shifts first. */
3492 if (info.shift2 != NULL)
3494 for (; n > 1; n -= 2)
3495 output_asm_insn (info.shift2, operands);
3498 /* Now emit one bit shifts for any residual. */
3500 output_asm_insn (info.shift1, operands);
3505 int m = GET_MODE_BITSIZE (mode) - n;
3506 const int mask = (shift_type == SHIFT_ASHIFT
3507 ? ((1 << m) - 1) << n
3511 /* Not all possibilities of rotate are supported. They shouldn't
3512 be generated, but let's watch for 'em. */
3513 if (info.shift1 == 0)
3516 /* Emit two bit rotates first. */
3517 if (info.shift2 != NULL)
3519 for (; m > 1; m -= 2)
3520 output_asm_insn (info.shift2, operands);
3523 /* Now single bit rotates for any residual. */
3525 output_asm_insn (info.shift1, operands);
3527 /* Now mask off the high bits. */
3529 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3530 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3531 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3535 output_asm_insn (insn_buf, operands);
3540 /* A loop to shift by a "large" constant value.
3541 If we have shift-by-2 insns, use them. */
3542 if (info.shift2 != NULL)
3544 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3545 names_big[REGNO (operands[4])]);
3546 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3547 output_asm_insn (info.shift2, operands);
3548 output_asm_insn ("add #0xff,%X4", operands);
3549 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3551 output_asm_insn (info.shift1, operands);
3555 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3556 names_big[REGNO (operands[4])]);
3557 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3558 output_asm_insn (info.shift1, operands);
3559 output_asm_insn ("add #0xff,%X4", operands);
3560 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3571 h8300_asm_insn_count (const char *template)
3573 unsigned int count = 1;
3575 for (; *template; template++)
3576 if (*template == '\n')
3583 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3585 rtx shift = operands[3];
3586 enum machine_mode mode = GET_MODE (shift);
3587 enum rtx_code code = GET_CODE (shift);
3588 enum shift_type shift_type;
3589 enum shift_mode shift_mode;
3590 struct shift_info info;
3591 unsigned int wlength = 0;
3596 shift_mode = QIshift;
3599 shift_mode = HIshift;
3602 shift_mode = SIshift;
3611 shift_type = SHIFT_ASHIFTRT;
3614 shift_type = SHIFT_LSHIFTRT;
3617 shift_type = SHIFT_ASHIFT;
3623 if (GET_CODE (operands[2]) != CONST_INT)
3625 /* Get the assembler code to do one shift. */
3626 get_shift_alg (shift_type, shift_mode, 1, &info);
3628 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3632 int n = INTVAL (operands[2]);
3634 /* If the count is negative, make it 0. */
3637 /* If the count is too big, truncate it.
3638 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3639 do the intuitive thing. */
3640 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3641 n = GET_MODE_BITSIZE (mode);
3643 get_shift_alg (shift_type, shift_mode, n, &info);
3648 wlength += h8300_asm_insn_count (info.special);
3650 /* Every assembly instruction used in SHIFT_SPECIAL case
3651 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3652 see xor.l, we just pretend that xor.l counts as two insns
3653 so that the insn length will be computed correctly. */
3654 if (strstr (info.special, "xor.l") != NULL)
3662 if (info.shift2 != NULL)
3664 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3668 wlength += h8300_asm_insn_count (info.shift1) * n;
3674 int m = GET_MODE_BITSIZE (mode) - n;
3676 /* Not all possibilities of rotate are supported. They shouldn't
3677 be generated, but let's watch for 'em. */
3678 if (info.shift1 == 0)
3681 if (info.shift2 != NULL)
3683 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3687 wlength += h8300_asm_insn_count (info.shift1) * m;
3689 /* Now mask off the high bits. */
3710 /* A loop to shift by a "large" constant value.
3711 If we have shift-by-2 insns, use them. */
3712 if (info.shift2 != NULL)
3714 wlength += 3 + h8300_asm_insn_count (info.shift2);
3716 wlength += h8300_asm_insn_count (info.shift1);
3720 wlength += 3 + h8300_asm_insn_count (info.shift1);
3731 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3733 rtx shift = operands[3];
3734 enum machine_mode mode = GET_MODE (shift);
3735 enum rtx_code code = GET_CODE (shift);
3736 enum shift_type shift_type;
3737 enum shift_mode shift_mode;
3738 struct shift_info info;
3743 shift_mode = QIshift;
3746 shift_mode = HIshift;
3749 shift_mode = SIshift;
3758 shift_type = SHIFT_ASHIFTRT;
3761 shift_type = SHIFT_LSHIFTRT;
3764 shift_type = SHIFT_ASHIFT;
3770 if (GET_CODE (operands[2]) != CONST_INT)
3772 /* This case must be taken care of by one of the two splitters
3773 that convert a variable shift into a loop. */
3778 int n = INTVAL (operands[2]);
3780 /* If the count is negative, make it 0. */
3783 /* If the count is too big, truncate it.
3784 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3785 do the intuitive thing. */
3786 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3787 n = GET_MODE_BITSIZE (mode);
3789 get_shift_alg (shift_type, shift_mode, n, &info);
3794 if (info.remainder == 0)
3795 return info.cc_special;
3800 return info.cc_inline;
3803 /* This case always ends with an and instruction. */
3807 /* A loop to shift by a "large" constant value.
3808 If we have shift-by-2 insns, use them. */
3809 if (info.shift2 != NULL)
3812 return info.cc_inline;
3822 /* A rotation by a non-constant will cause a loop to be generated, in
3823 which a rotation by one bit is used. A rotation by a constant,
3824 including the one in the loop, will be taken care of by
3825 output_a_rotate () at the insn emit time. */
3828 expand_a_rotate (enum rtx_code code, rtx operands[])
3830 rtx dst = operands[0];
3831 rtx src = operands[1];
3832 rtx rotate_amount = operands[2];
3833 enum machine_mode mode = GET_MODE (dst);
3836 /* We rotate in place. */
3837 emit_move_insn (dst, src);
3839 if (GET_CODE (rotate_amount) != CONST_INT)
3841 rtx counter = gen_reg_rtx (QImode);
3842 rtx start_label = gen_label_rtx ();
3843 rtx end_label = gen_label_rtx ();
3845 /* If the rotate amount is less than or equal to 0,
3846 we go out of the loop. */
3847 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3848 QImode, 0, end_label);
3850 /* Initialize the loop counter. */
3851 emit_move_insn (counter, rotate_amount);
3853 emit_label (start_label);
3855 /* Rotate by one bit. */
3856 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3857 emit_insn (gen_rtx_SET (mode, dst, tmp));
3859 /* Decrement the counter by 1. */
3860 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3861 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3863 /* If the loop counter is nonzero, we go back to the beginning
3865 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3868 emit_label (end_label);
3872 /* Rotate by AMOUNT bits. */
3873 tmp = gen_rtx (code, mode, dst, rotate_amount);
3874 emit_insn (gen_rtx_SET (mode, dst, tmp));
3880 /* Output rotate insns. */
3883 output_a_rotate (enum rtx_code code, rtx *operands)
3885 rtx dst = operands[0];
3886 rtx rotate_amount = operands[2];
3887 enum shift_mode rotate_mode;
3888 enum shift_type rotate_type;
3889 const char *insn_buf;
3892 enum machine_mode mode = GET_MODE (dst);
3894 if (GET_CODE (rotate_amount) != CONST_INT)
3900 rotate_mode = QIshift;
3903 rotate_mode = HIshift;
3906 rotate_mode = SIshift;
3915 rotate_type = SHIFT_ASHIFT;
3918 rotate_type = SHIFT_LSHIFTRT;
3924 amount = INTVAL (rotate_amount);
3926 /* Clean up AMOUNT. */
3929 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3930 amount = GET_MODE_BITSIZE (mode);
3932 /* Determine the faster direction. After this phase, amount will be
3933 at most a half of GET_MODE_BITSIZE (mode). */
3934 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3936 /* Flip the direction. */
3937 amount = GET_MODE_BITSIZE (mode) - amount;
3939 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3942 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3943 boost up the rotation. */
3944 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3945 || (mode == HImode && TARGET_H8300H && amount >= 6)
3946 || (mode == HImode && TARGET_H8300S && amount == 8)
3947 || (mode == SImode && TARGET_H8300H && amount >= 10)
3948 || (mode == SImode && TARGET_H8300S && amount >= 13))
3953 /* This code works on any family. */
3954 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3955 output_asm_insn (insn_buf, operands);
3959 /* This code works on the H8/300H and H8S. */
3960 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3961 output_asm_insn (insn_buf, operands);
3968 /* Adjust AMOUNT and flip the direction. */
3969 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3971 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3974 /* Emit rotate insns. */
3975 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3978 insn_buf = rotate_two[rotate_type][rotate_mode];
3980 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3982 for (; amount >= bits; amount -= bits)
3983 output_asm_insn (insn_buf, operands);
3990 compute_a_rotate_length (rtx *operands)
3992 rtx src = operands[1];
3993 rtx amount_rtx = operands[2];
3994 enum machine_mode mode = GET_MODE (src);
3996 unsigned int length = 0;
3998 if (GET_CODE (amount_rtx) != CONST_INT)
4001 amount = INTVAL (amount_rtx);
4003 /* Clean up AMOUNT. */
4006 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4007 amount = GET_MODE_BITSIZE (mode);
4009 /* Determine the faster direction. After this phase, amount
4010 will be at most a half of GET_MODE_BITSIZE (mode). */
4011 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4012 /* Flip the direction. */
4013 amount = GET_MODE_BITSIZE (mode) - amount;
4015 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4016 boost up the rotation. */
4017 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4018 || (mode == HImode && TARGET_H8300H && amount >= 6)
4019 || (mode == HImode && TARGET_H8300S && amount == 8)
4020 || (mode == SImode && TARGET_H8300H && amount >= 10)
4021 || (mode == SImode && TARGET_H8300S && amount >= 13))
4023 /* Adjust AMOUNT and flip the direction. */
4024 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4028 /* We use 2-bit rotations on the H8S. */
4030 amount = amount / 2 + amount % 2;
4032 /* The H8/300 uses three insns to rotate one bit, taking 6
4034 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4039 /* Fix the operands of a gen_xxx so that it could become a bit
4043 fix_bit_operand (rtx *operands, int what, enum rtx_code type)
4045 /* The bit_operand predicate accepts any memory during RTL generation, but
4046 only 'U' memory afterwards, so if this is a MEM operand, we must force
4047 it to be valid for 'U' by reloading the address. */
4049 if ((what == 0 && single_zero_operand (operands[2], QImode))
4050 || (what == 1 && single_one_operand (operands[2], QImode)))
4052 /* OK to have a memory dest. */
4053 if (GET_CODE (operands[0]) == MEM
4054 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4056 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4057 copy_to_mode_reg (Pmode,
4058 XEXP (operands[0], 0)));
4059 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4063 if (GET_CODE (operands[1]) == MEM
4064 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4066 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4067 copy_to_mode_reg (Pmode,
4068 XEXP (operands[1], 0)));
4069 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4075 /* Dest and src op must be register. */
4077 operands[1] = force_reg (QImode, operands[1]);
4079 rtx res = gen_reg_rtx (QImode);
4080 emit_insn (gen_rtx_SET (VOIDmode, res,
4081 gen_rtx (type, QImode, operands[1], operands[2])));
4082 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
4087 /* Return nonzero if FUNC is an interrupt function as specified
4088 by the "interrupt" attribute. */
4091 h8300_interrupt_function_p (tree func)
4095 if (TREE_CODE (func) != FUNCTION_DECL)
4098 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4099 return a != NULL_TREE;
4102 /* Return nonzero if FUNC is an OS_Task function as specified
4103 by the "OS_Task" attribute. */
4106 h8300_os_task_function_p (tree func)
4110 if (TREE_CODE (func) != FUNCTION_DECL)
4113 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4114 return a != NULL_TREE;
4117 /* Return nonzero if FUNC is a monitor function as specified
4118 by the "monitor" attribute. */
4121 h8300_monitor_function_p (tree func)
4125 if (TREE_CODE (func) != FUNCTION_DECL)
4128 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4129 return a != NULL_TREE;
4132 /* Return nonzero if FUNC is a function that should be called
4133 through the function vector. */
4136 h8300_funcvec_function_p (tree func)
4140 if (TREE_CODE (func) != FUNCTION_DECL)
4143 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4144 return a != NULL_TREE;
4147 /* Return nonzero if DECL is a variable that's in the eight bit
4151 h8300_eightbit_data_p (tree decl)
4155 if (TREE_CODE (decl) != VAR_DECL)
4158 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4159 return a != NULL_TREE;
4162 /* Return nonzero if DECL is a variable that's in the tiny
4166 h8300_tiny_data_p (tree decl)
4170 if (TREE_CODE (decl) != VAR_DECL)
4173 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4174 return a != NULL_TREE;
4177 /* Generate an 'interrupt_handler' attribute for decls. */
4180 h8300_insert_attributes (tree node, tree *attributes)
4182 if (!pragma_interrupt
4183 || TREE_CODE (node) != FUNCTION_DECL)
4186 pragma_interrupt = 0;
4188 /* Add an 'interrupt_handler' attribute. */
4189 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4193 /* Supported attributes:
4195 interrupt_handler: output a prologue and epilogue suitable for an
4198 function_vector: This function should be called through the
4201 eightbit_data: This variable lives in the 8-bit data area and can
4202 be referenced with 8-bit absolute memory addresses.
4204 tiny_data: This variable lives in the tiny data area and can be
4205 referenced with 16-bit absolute memory references. */
4207 const struct attribute_spec h8300_attribute_table[] =
4209 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4210 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4211 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4212 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4213 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4214 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4215 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4216 { NULL, 0, 0, false, false, false, NULL }
4220 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4221 struct attribute_spec.handler. */
4223 h8300_handle_fndecl_attribute (tree *node, tree name,
4224 tree args ATTRIBUTE_UNUSED,
4225 int flags ATTRIBUTE_UNUSED,
4228 if (TREE_CODE (*node) != FUNCTION_DECL)
4230 warning ("`%s' attribute only applies to functions",
4231 IDENTIFIER_POINTER (name));
4232 *no_add_attrs = true;
4238 /* Handle an "eightbit_data" attribute; arguments as in
4239 struct attribute_spec.handler. */
4241 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4242 tree args ATTRIBUTE_UNUSED,
4243 int flags ATTRIBUTE_UNUSED,
4248 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4250 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4254 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4255 *no_add_attrs = true;
4261 /* Handle an "tiny_data" attribute; arguments as in
4262 struct attribute_spec.handler. */
4264 h8300_handle_tiny_data_attribute (tree *node, tree name,
4265 tree args ATTRIBUTE_UNUSED,
4266 int flags ATTRIBUTE_UNUSED,
4271 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4273 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4277 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4278 *no_add_attrs = true;
4284 /* Mark function vectors, and various small data objects. */
4287 h8300_encode_section_info (tree decl, rtx rtl, int first)
4289 int extra_flags = 0;
4291 default_encode_section_info (decl, rtl, first);
4293 if (TREE_CODE (decl) == FUNCTION_DECL
4294 && h8300_funcvec_function_p (decl))
4295 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4296 else if (TREE_CODE (decl) == VAR_DECL
4297 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4299 if (h8300_eightbit_data_p (decl))
4300 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4301 else if (first && h8300_tiny_data_p (decl))
4302 extra_flags = SYMBOL_FLAG_TINY_DATA;
4306 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4310 output_simode_bld (int bild, rtx operands[])
4314 /* Clear the destination register. */
4315 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4317 /* Now output the bit load or bit inverse load, and store it in
4320 output_asm_insn ("bild\t%Z2,%Y1", operands);
4322 output_asm_insn ("bld\t%Z2,%Y1", operands);
4324 output_asm_insn ("bst\t#0,%w0", operands);
4328 /* Determine if we can clear the destination first. */
4329 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4330 && REGNO (operands[0]) != REGNO (operands[1]));
4333 output_asm_insn ("sub.l\t%S0,%S0", operands);
4335 /* Output the bit load or bit inverse load. */
4337 output_asm_insn ("bild\t%Z2,%Y1", operands);
4339 output_asm_insn ("bld\t%Z2,%Y1", operands);
4342 output_asm_insn ("xor.l\t%S0,%S0", operands);
4344 /* Perform the bit store. */
4345 output_asm_insn ("rotxl.l\t%S0", operands);
4352 #ifndef OBJECT_FORMAT_ELF
4354 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4356 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4357 fprintf (asm_out_file, "\t.section %s\n", name);
4359 #endif /* ! OBJECT_FORMAT_ELF */
4361 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4362 which is a special case of the 'R' operand. */
4365 h8300_eightbit_constant_address_p (rtx x)
4367 /* The ranges of the 8-bit area. */
4368 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4369 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4370 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4371 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4372 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4373 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4375 unsigned HOST_WIDE_INT addr;
4377 /* We accept symbols declared with eightbit_data. */
4378 if (GET_CODE (x) == SYMBOL_REF)
4379 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4381 if (GET_CODE (x) != CONST_INT)
4387 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4388 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4389 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4392 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4393 on H8/300H and H8S. */
4396 h8300_tiny_constant_address_p (rtx x)
4398 /* The ranges of the 16-bit area. */
4399 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4400 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4401 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4402 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4403 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4404 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4405 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4406 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4408 unsigned HOST_WIDE_INT addr;
4410 /* We accept symbols declared with tiny_data. */
4411 if (GET_CODE (x) == SYMBOL_REF)
4412 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
4414 if (GET_CODE (x) != CONST_INT)
4420 || TARGET_NORMAL_MODE
4422 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4424 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4428 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4430 HOST_WIDE_INT offset1, offset2;
4438 else if (GET_CODE (addr1) == PLUS
4439 && REG_P (XEXP (addr1, 0))
4440 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4442 reg1 = XEXP (addr1, 0);
4443 offset1 = INTVAL (XEXP (addr1, 1));
4453 else if (GET_CODE (addr2) == PLUS
4454 && REG_P (XEXP (addr2, 0))
4455 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4457 reg2 = XEXP (addr2, 0);
4458 offset2 = INTVAL (XEXP (addr2, 1));
4463 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4464 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4466 && offset1 + 1 == offset2)
4472 /* Return nonzero if we have the same comparison insn as I3 two insns
4473 before I3. I3 is assumed to be a comparison insn. */
4476 same_cmp_preceding_p (rtx i3)
4480 /* Make sure we have a sequence of three insns. */
4481 i2 = prev_nonnote_insn (i3);
4484 i1 = prev_nonnote_insn (i2);
4488 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4489 && any_condjump_p (i2) && onlyjump_p (i2));
4492 /* Initialize the GCC target structure. */
4493 #undef TARGET_ATTRIBUTE_TABLE
4494 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4496 #undef TARGET_ASM_ALIGNED_HI_OP
4497 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4499 #undef TARGET_ASM_FUNCTION_EPILOGUE
4500 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
4502 #undef TARGET_ASM_FILE_START
4503 #define TARGET_ASM_FILE_START h8300_file_start
4504 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4505 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4507 #undef TARGET_ASM_FILE_END
4508 #define TARGET_ASM_FILE_END h8300_file_end
4510 #undef TARGET_ENCODE_SECTION_INFO
4511 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4513 #undef TARGET_INSERT_ATTRIBUTES
4514 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4516 #undef TARGET_RTX_COSTS
4517 #define TARGET_RTX_COSTS h8300_rtx_costs
4519 struct gcc_target targetm = TARGET_INITIALIZER;