1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
39 /* Forward declarations. */
40 void print_operand_address ();
43 /* CPU_TYPE, says what cpu we're compiling for. */
46 /* True if a #pragma interrupt has been seen for the current function. */
49 /* True if a #pragma saveall has been seen for the current function. */
52 static char *names_big[] =
53 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"};
55 static char *names_extended[] =
56 {"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"};
58 static char *names_upper_extended[] =
59 {"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"};
61 /* Points to one of the above. */
62 /* ??? The above could be put in an array indexed by CPU_TYPE. */
65 /* Various operations needed by the following, indexed by CPU_TYPE. */
66 /* ??? The h8/300 assembler doesn't understand pop.w (yet). */
68 static char *h8_push_ops[2] =
70 static char *h8_pop_ops[2] =
72 static char *h8_mov_ops[2] =
75 char *h8_push_op, *h8_pop_op, *h8_mov_op;
77 /* Initialize various cpu specific globals at start up. */
84 cpu_type = (int) CPU_H8300;
85 h8_reg_names = names_big;
89 cpu_type = (int) CPU_H8300H;
90 h8_reg_names = names_extended;
92 h8_push_op = h8_push_ops[cpu_type];
93 h8_pop_op = h8_pop_ops[cpu_type];
94 h8_mov_op = h8_mov_ops[cpu_type];
102 static char *names_small[] =
103 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
104 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7lBAD", "r7hBAD"};
106 return names_small[REGNO (x) * 2 + b];
109 /* REGNO must be saved/restored across calls if this macro is true. */
111 #define WORD_REG_USED(regno) \
115 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
116 || (regs_ever_live[regno] & !call_used_regs[regno])))
118 /* Output assembly language to FILE for the operation OP with operand size
119 SIZE to adjust the stack pointer. */
120 /* ??? FPED is currently unused. */
123 dosize (file, op, size, fped)
132 /* ??? TARGET_H8300H can do this in one insn. */
134 fprintf (file, "\t%ss\t#%d,sp\n", op, 2);
136 /* Fall through... */
139 fprintf (file, "\t%ss\t#%d,sp\n", op, size);
146 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
148 fprintf (file, "\t%s\t#%d,sp\n", op, size);
154 /* Output assembly language code for the function prologue. */
155 static int push_order[FIRST_PSEUDO_REGISTER] =
156 {6, 5, 4, 3, 2, 1, 0, -1, -1};
157 static int pop_order[FIRST_PSEUDO_REGISTER] =
158 {0, 1, 2, 3, 4, 5, 6, -1, -1};
160 /* This is what the stack looks like after the prolog of
161 a function with a frame has been set up:
167 <saved registers> <- sp
169 This is what the stack looks like after the prolog of
170 a function which doesn't have a frame:
175 <saved registers> <- sp
178 int current_function_anonymous_args;
180 /* Extra arguments to pop, in words (IE: 2 bytes for 300, 4 for 300h */
181 static int extra_pop;
184 function_prologue (file, size)
188 register int mask = 0;
189 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
193 if (current_function_anonymous_args && TARGET_QUICKCALL)
195 /* Push regs as if done by caller, and move around return address. */
197 switch (current_function_args_info.nbytes / UNITS_PER_WORD)
201 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[3]);
202 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[2]);
203 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[1]);
204 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[0]);
206 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[3]);
211 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[3]);
212 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[2]);
213 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[1]);
215 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[3]);
220 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[3]);
221 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[2]);
223 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[3]);
227 fprintf (file, "; varargs\n");
232 if (frame_pointer_needed)
235 fprintf (file, "\t%s\t%s\n", h8_push_op,
236 h8_reg_names[FRAME_POINTER_REGNUM]);
237 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
238 h8_reg_names[STACK_POINTER_REGNUM],
239 h8_reg_names[FRAME_POINTER_REGNUM]);
241 /* leave room for locals */
242 dosize (file, "sub", fsize, 1);
244 /* Push the rest of the registers */
245 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
247 int regno = push_order[idx];
249 if (regno >= 0 && WORD_REG_USED (regno) && regno != FRAME_POINTER_REGNUM)
250 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]);
255 dosize (file, "sub", fsize, 0);
256 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
258 int regno = push_order[idx];
260 if (regno >= 0 && WORD_REG_USED (regno))
261 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]);
266 /* Output assembly language code for the function epilogue. */
269 function_epilogue (file, size)
274 register int mask = 0;
275 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
279 rtx insn = get_last_insn ();
281 /* If the last insn was a BARRIER, we don't have to write any code. */
282 if (GET_CODE (insn) == NOTE)
283 insn = prev_nonnote_insn (insn);
284 if (insn && GET_CODE (insn) == BARRIER)
289 if (frame_pointer_needed)
291 /* Pop saved registers */
292 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
294 regno = pop_order[idx];
295 if (regno >= 0 && regno != FRAME_POINTER_REGNUM && WORD_REG_USED (regno))
296 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]);
298 /* deallocate locals */
299 dosize (file, "add", fsize, 1);
300 /* pop frame pointer */
301 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]);
305 /* pop saved registers */
306 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
308 regno = pop_order[idx];
309 if (regno >= 0 && WORD_REG_USED (regno))
310 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]);
312 /* deallocate locals */
313 dosize (file, "add", fsize, 0);
318 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[3]);
321 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[2]);
324 fprintf (file, "\tjmp @%s\n", h8_reg_names[3]);
328 if (pragma_interrupt)
329 fprintf (file, "\trte\n");
331 fprintf (file, "\trts\n");
334 pragma_interrupt = 0;
337 current_function_anonymous_args = 0;
340 /* Output assembly code for the start of the file. */
342 asm_file_start (file)
345 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
346 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
347 fprintf (file, ";\trelease F-1\n");
349 fprintf (file, "; -O%d\n", optimize);
351 fprintf (file, "\n\t.h8300h\n");
353 fprintf (file, "\n\n");
354 output_file_directive (file, main_input_filename);
357 /* Output assembly language code for the end of file. */
363 fprintf (file, "\t.end\n");
366 /* Return true if VALUE is a valid constant for constraint 'P'.
367 IE: VALUE is a power of two <= 2**15. */
370 small_power_of_two (value)
396 /* Return true if VALUE is a valid constant for constraint 'O', which
397 means that the constant would be ok to use as a bit for a bclr
404 return small_power_of_two ((~value) & 0xff);
407 /* Return true is OP is a valid source operand for an integer move
411 general_operand_src (op, mode)
413 enum machine_mode mode;
415 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
417 return general_operand (op, mode);
420 /* Return true if OP is a valid destination operand for an integer move
424 general_operand_dst (op, mode)
426 enum machine_mode mode;
428 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
430 return general_operand (op, mode);
433 /* Return true if OP is a const valid for a bit clear instruction. */
436 o_operand (operand, mode)
438 enum machine_mode mode;
440 return (GET_CODE (operand) == CONST_INT
441 && CONST_OK_FOR_O (INTVAL (operand)));
444 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
447 p_operand (operand, mode)
449 enum machine_mode mode;
451 return (GET_CODE (operand) == CONST_INT
452 && CONST_OK_FOR_P (INTVAL (operand)));
455 /* Return true if OP is a valid call operand. */
458 call_insn_operand (op, mode)
460 enum machine_mode mode;
462 if (GET_CODE (op) == MEM)
464 rtx inside = XEXP (op, 0);
465 if (register_operand (inside, Pmode))
467 if (CONSTANT_ADDRESS_P (inside))
473 /* Return true if OP is a valid jump operand. */
476 jump_address_operand (op, mode)
478 enum machine_mode mode;
480 if (GET_CODE (op) == REG)
481 return mode == Pmode;
483 if (GET_CODE (op) == MEM)
485 rtx inside = XEXP (op, 0);
486 if (register_operand (inside, Pmode))
488 if (CONSTANT_ADDRESS_P (inside))
494 /* Recognize valid operands for bitfield instructions. */
496 extern int rtx_equal_function_value_matters;
499 bit_operand (op, mode)
501 enum machine_mode mode;
503 /* We can except any general operand, expept that MEM operands must
504 be limited to those that use addresses valid for the 'U' constraint. */
505 if (!general_operand (op, mode))
508 /* Accept any mem during RTL generation. Otherwise, the code that does
509 insv and extzv will think that we can not handle memory. However,
510 to avoid reload problems, we only accept 'U' MEM operands after RTL
511 generation. This means that any named pattern which uses this predicate
512 must force its operands to match 'U' before emitting RTL. */
514 if (GET_CODE (op) == REG)
516 if (GET_CODE (op) == SUBREG)
518 if (!rtx_equal_function_value_matters)
520 /* We're building rtl */
521 return GET_CODE (op) == MEM;
525 return (GET_CODE (op) == MEM
526 && EXTRA_CONSTRAINT (op, 'U'));
530 /* Recognize valid operators for bit test. */
533 eq_operator (x, mode)
535 enum machine_mode mode;
537 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
540 /* Handle machine specific pragmas for compatibility with existing
541 compilers for the H8/300.
543 pragma saveall generates prolog/epilog code which saves and
544 restores all the registers on function entry.
546 pragma interrupt saves and restores all registers, and exits with
547 an rte instruction rather than an rts. A pointer to a function
548 with this attribute may be safely used in an interrupt vector. */
551 handle_pragma (file, c)
558 while (c == ' ' || c == '\t')
561 if (c != '\n' & c != EOF)
563 while (psize < sizeof (pbuf) - 1
571 if (strcmp (pbuf, "interrupt") == 0)
572 pragma_interrupt = 1;
573 else if (strcmp (pbuf, "saveall") == 0)
576 while (c != '\n' && c != EOF)
583 /* If the next arg with MODE and TYPE is to be passed in a register, return
584 the rtx to represent where it is passed. CUM represents the state after
585 the last argument. NAMED is not used. */
587 static char *hand_list[] =
607 /* Return an RTX to represent where a value with mode MODE will be returned
608 from a function. If the result is 0, the argument is pushed. */
611 function_arg (cum, mode, type, named)
612 CUMULATIVE_ARGS *cum;
613 enum machine_mode mode;
621 /* Pass 3 regs worth of data in regs when user asked on the command line. */
622 if (TARGET_QUICKCALL)
625 /* If calling hand written assembler, use 4 regs of args. */
631 fname = XSTR (cum->libcall, 0);
633 /* See if this libcall is one of the hand coded ones. */
635 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
647 size = int_size_in_bytes (type);
649 size = GET_MODE_SIZE (mode);
651 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
657 switch (cum->nbytes / UNITS_PER_WORD)
660 result = gen_rtx (REG, mode, 0);
663 result = gen_rtx (REG, mode, 1);
666 result = gen_rtx (REG, mode, 2);
669 result = gen_rtx (REG, mode, 3);
680 /* Return the cost of the rtx R with code CODE. */
715 /* Documentation for the machine specific operand escapes:
717 'A' print rn in h8/300 mode, erN in H8/300H mode
718 'C' print (operand - 2).
719 'E' like s but negative.
720 'F' like t but negative.
721 'G' constant just the negative
722 'L' fake label, changed after used twice.
723 'M' turn a 'M' constant into its negative mod 2.
724 'P' if operand is incing/decing sp, print .w, otherwise .b.
725 'S' print operand as a long word
726 'T' print operand as a word
727 'U' if operand is incing/decing sp, print l, otherwise nothing.
728 'V' find the set bit, and print its number.
729 'W' find the clear bit, and print its number.
730 'X' print operand as a byte
731 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
733 'b' print the bit opcode
734 'c' print the ibit opcode
735 'd' bcc if EQ, bcs if NE
736 'e' first word of 32 bit value - if reg, then least reg. if mem
737 then least. if const then most sig word
738 'f' second word of 32 bit value - if reg, then biggest reg. if mem
739 then +2. if const then least sig word
740 'g' bcs if EQ, bcc if NE
741 'j' print operand as condition code.
742 'k' print operand as reverse condition code.
743 's' print as low byte of 16 bit value
744 't' print as high byte of 16 bit value
745 'w' print as low byte of 32 bit value
746 'x' print as 2nd byte of 32 bit value
747 'y' print as 3rd byte of 32 bit value
748 'z' print as msb of 32 bit value
751 /* Return assembly language string which identifies a comparison type. */
760 if (cc_prev_status.flags & CC_DONE_CBIT)
764 if (cc_prev_status.flags & CC_DONE_CBIT)
788 /* Print operand X using operand code CODE to assembly language output file
792 print_operand (file, x, code)
797 /* This is used to general unique labels for the 'L' code. */
798 static int lab = 1000;
800 /* This is used for communication between the 'P' and 'U' codes. */
803 /* This is used for communication between the 'Z' and 'Y' codes. */
804 /* ??? 'V' and 'W' use it too. */
810 if (GET_CODE (x) == REG)
811 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
816 fprintf (file, "#%d", INTVAL (x) - 2);
819 switch (GET_CODE (x))
822 fprintf (file, "%sl", names_big[REGNO (x)]);
825 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
832 switch (GET_CODE (x))
835 fprintf (file, "%sh", names_big[REGNO (x)]);
838 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
845 if (GET_CODE (x) != CONST_INT)
847 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
850 /* 'L' must always be used twice in a single pattern. It generates
851 the same label twice, and then will generate a unique label the
852 next time it is used. */
853 asm_fprintf (file, "tl%d", (lab++) / 2);
856 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
863 fprintf (file, "#2");
869 fprintf (file, "#1");
876 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
879 fprintf (file, ".w");
884 fprintf (file, ".b");
888 if (GET_CODE (x) == REG)
889 fprintf (file, "%s", names_extended[REGNO (x)]);
894 if (GET_CODE (x) == REG)
895 fprintf (file, "%s", names_big[REGNO (x)]);
900 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
903 bitint = exact_log2 (INTVAL (x));
906 fprintf (file, "#%d", bitint & 7);
909 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
912 fprintf (file, "#%d", bitint & 7);
915 if (GET_CODE (x) == REG)
916 fprintf (file, "%s", byte_reg (x, 0));
923 if (GET_CODE (x) == REG)
924 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
926 print_operand (file, x, 0);
931 fprintf (file, "#%d", bitint & 7);
934 switch (GET_CODE (x))
937 fprintf (file, "bor");
940 fprintf (file, "bxor");
943 fprintf (file, "band");
948 switch (GET_CODE (x))
951 fprintf (file, "bior");
954 fprintf (file, "bixor");
957 fprintf (file, "biand");
962 switch (GET_CODE (x))
965 fprintf (file, "bcc");
968 fprintf (file, "bcs");
975 switch (GET_CODE (x))
979 fprintf (file, "%s", names_big[REGNO (x)]);
981 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
984 x = adj_offsettable_operand (x, 0);
985 print_operand (file, x, 0);
988 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
996 switch (GET_CODE (x))
1000 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1002 fprintf (file, "%s", names_big[REGNO (x)]);
1005 x = adj_offsettable_operand (x, 2);
1006 print_operand (file, x, 0);
1009 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1016 switch (GET_CODE (x))
1019 fprintf (file, "bcc");
1022 fprintf (file, "bcs");
1029 asm_fprintf (file, cond_string (GET_CODE (x)));
1032 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1035 if (GET_CODE (x) == CONST_INT)
1036 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1038 fprintf (file, "%s", byte_reg (x, 0));
1041 if (GET_CODE (x) == CONST_INT)
1042 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1044 fprintf (file, "%s", byte_reg (x, 1));
1047 if (GET_CODE (x) != CONST_INT)
1049 fprintf (file, "%d", INTVAL (x));
1052 if (GET_CODE (x) == CONST_INT)
1053 fprintf (file, "#%d", INTVAL (x) & 0xff);
1055 fprintf (file, "%s", byte_reg (x, TARGET_H8300 ? 2 : 0));
1058 if (GET_CODE (x) == CONST_INT)
1059 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1061 fprintf (file, "%s", byte_reg (x, TARGET_H8300 ? 3 : 1));
1064 if (GET_CODE (x) == CONST_INT)
1065 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1067 fprintf (file, "%s", byte_reg (x, 0));
1070 if (GET_CODE (x) == CONST_INT)
1071 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1073 fprintf (file, "%s", byte_reg (x, 1));
1078 switch (GET_CODE (x))
1081 switch (GET_MODE (x))
1084 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1085 fprintf (file, "%s", byte_reg (x, 0));
1086 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1087 fprintf (file, "%s", names_big[REGNO (x)]);
1091 fprintf (file, "%s", names_big[REGNO (x)]);
1095 fprintf (file, "%s", names_extended[REGNO (x)]);
1103 fprintf (file, "@");
1104 output_address (XEXP (x, 0));
1111 fprintf (file, "#");
1112 print_operand_address (file, x);
1118 /* Output assembly language output for the address ADDR to FILE. */
1121 print_operand_address (file, addr)
1125 switch (GET_CODE (addr))
1128 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1132 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1136 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1140 fprintf (file, "(");
1141 if (GET_CODE (XEXP (addr, 0)) == REG)
1144 print_operand_address (file, XEXP (addr, 1));
1145 fprintf (file, ",");
1146 print_operand_address (file, XEXP (addr, 0));
1151 print_operand_address (file, XEXP (addr, 0));
1152 fprintf (file, "+");
1153 print_operand_address (file, XEXP (addr, 1));
1155 fprintf (file, ")");
1160 /* Since the h8/300 only has 16 bit pointers, negative values are also
1161 those >= 32768. This happens for example with pointer minus a
1162 constant. We don't want to turn (char *p - 2) into
1163 (char *p + 65534) because loop unrolling can build upon this
1164 (IE: char *p + 131068). */
1165 int n = INTVAL (addr);
1167 n = (int) (short) n;
1169 /* ??? Why the special case for -ve values? */
1170 fprintf (file, "-%d", -n);
1172 fprintf (file, "%d", n);
1177 output_addr_const (file, addr);
1182 /* Output all insn addresses and their sizes into the assembly language
1183 output file. This is helpful for debugging whether the length attributes
1184 in the md file are correct. This is not meant to be a user selectable
1188 final_prescan_insn (insn, operand, num_operands)
1192 /* This holds the last insn address. */
1193 static int last_insn_address = 0;
1195 int uid = INSN_UID (insn);
1197 if (TARGET_RTL_DUMP)
1199 fprintf (asm_out_file, "\n****************");
1200 print_rtl (asm_out_file, PATTERN (insn));
1201 fprintf (asm_out_file, "\n");
1204 if (TARGET_ADDRESSES)
1206 fprintf (asm_out_file, "; 0x%x %d\n", insn_addresses[uid],
1207 insn_addresses[uid] - last_insn_address);
1208 last_insn_address = insn_addresses[uid];
1212 /* Prepare for an SI sized move. */
1218 rtx src = operands[1];
1219 rtx dst = operands[0];
1220 if (!reload_in_progress && !reload_completed)
1222 if (!register_operand (dst, GET_MODE (dst)))
1224 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1225 emit_move_insn (tmp, src);
1232 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1233 Define the offset between two registers, one to be eliminated, and the other
1234 its replacement, at the start of a routine. */
1237 initial_offset (from, to)
1241 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1242 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1247 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1248 if ((regs_ever_live[regno]
1249 && (!call_used_regs[regno] || regno == FRAME_POINTER_REGNUM)))
1250 offset += UNITS_PER_WORD;
1252 /* See the comments for get_frame_size. We need to round it up to
1255 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1256 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1258 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1259 offset += UNITS_PER_WORD; /* Skip saved PC */
1264 /* Update the condition code from the insn. */
1267 notice_update_cc (body, insn)
1271 switch (get_attr_cc (insn))
1274 /* Insn does not affect the CC at all */
1278 /* Insn does not change the CC, but the 0't operand has been changed. */
1280 if (cc_status.value1 != 0
1281 && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
1282 cc_status.value1 = 0;
1284 if (cc_status.value2 != 0
1285 && reg_overlap_mentioned_p (recog_operand[0], cc_status.value2))
1286 cc_status.value2 = 0;
1291 /* Insn sets CC to recog_operand[0], but overflow is impossible. */
1293 cc_status.flags |= CC_NO_OVERFLOW;
1294 cc_status.value1 = recog_operand[0];
1298 /* The insn is a compare instruction */
1300 cc_status.value1 = SET_SRC (body);
1305 cc_status.flags |= CC_DONE_CBIT;
1306 cc_status.value1 = 0;
1311 /* Insn clobbers CC. */
1317 /* Recognize valid operators for bit instructions */
1320 bit_operator (x, mode)
1322 enum machine_mode mode;
1324 enum rtx_code code = GET_CODE (x);
1333 We devote a fair bit of code to getting efficient shifts since we can only
1334 shift one bit at a time. See the .md file for more comments.
1336 Here are some thoughts on what the absolutely positively best code is.
1337 "Best" here means some rational trade-off between code size and speed,
1338 where speed is more preferred but not at the expense of generating 20 insns.
1340 H8/300 QImode shifts
1341 1-4 - do them inline
1342 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1344 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1345 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1347 H8/300 HImode shifts
1348 1-4 - do them inline
1350 7 - shift other way once, move byte into place, move carry bit into place
1351 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1352 9 - inline shift 1-4, move byte, set other byte
1353 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1355 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1356 - ASHIFTRT: shll, subx, set other byte
1358 H8/300 SImode shifts
1359 1-2 - do them inline
1361 7 - shift other way once, move bytes into place,
1362 move carry into place (possibly with sign extension)
1363 8 - move bytes into place, zero or sign extend other
1365 15 - shift other way once, move word into place, move carry into place
1366 16 - move word, zero or sign extend other
1368 24 - move bytes into place, zero or sign extend other
1370 28-30 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1373 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, byte byte into place,
1375 ASHIFTRT: shll top byte, subx, copy to other bytes
1377 H8/300H QImode shifts
1380 H8/300H HImode shifts
1383 H8/300H SImode shifts
1384 (These are complicated by the fact that we don't have byte level access to
1386 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1387 1-4 - do them inline
1389 15 - shift other way once, move word into place, move carry into place
1390 (with sign extension for ASHIFTRT)
1391 16 - move word into place, zero or sign extend other
1393 24 - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1394 move word 0 to word 1, zero word 0
1395 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1396 zero word 1, zero byte 1
1397 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1398 sign extend byte 0, sign extend word 0
1399 25-27 - either loop, or
1400 do 24 bit shift, inline rest
1401 28-30 - ASHIFT: rotate 4/3/2, mask
1402 LSHIFTRT: rotate 4/3/2, mask
1404 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1408 All of these haven't been implemented. I've just documented them and
1409 provided hooks so they can be.
1413 nshift_operator (x, mode)
1415 enum machine_mode mode;
1417 switch (GET_CODE (x))
1429 /* Called from the .md file to emit code to do shifts.
1430 Returns a boolean indicating success
1431 (currently this is always TRUE). */
1434 expand_a_shift (mode, code, operands)
1435 enum machine_mode mode;
1439 extern int rtx_equal_function_value_matters;
1441 emit_move_insn (operands[0], operands[1]);
1443 /* need a loop to get all the bits we want - we generate the
1444 code at emit time, but need to allocate a scratch reg now */
1447 (PARALLEL, VOIDmode,
1449 gen_rtx (SET, VOIDmode, operands[0],
1450 gen_rtx (code, mode, operands[0], operands[2])),
1451 gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, QImode, 0)))));
1456 /* Shift algorithm determination.
1458 There are various ways of doing a shift:
1459 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1461 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1462 necessary bits into position and then set the rest to zero.
1463 SHIFT_SPECIAL: Hand crafted assembler.
1464 SHIFT_LOOP: If the above methods fail, just loop. */
1475 /* Symbols of the various shifts which can be used as indices. */
1479 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1482 /* Symbols of the various modes which can be used as indices. */
1486 QIshift, HIshift, SIshift
1489 /* For single bit shift insns, record assembler and whether the condition code
1490 is valid afterwards. */
1498 /* Assembler instruction shift table.
1500 These tables are used to look up the basic shifts.
1501 They are indexed by cpu, shift_type, and mode.
1504 static const struct shift_insn shift_one[2][3][3] =
1511 { "add.w %T0,%T0\t; shal.w", 1 },
1512 { "add.w %f0,%f0\t; shal.l\n\taddx %y0,%y0\n\taddx %z0,%z0\t; end shal.l", 0 }
1514 /* SHIFT_LSHIFTRT */
1517 { "shlr %t0\t; shlr.w\n\trotxr %s0\t; end shlr.w", 0 },
1518 { "shlr %z0\t; shlr.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shlr.l", 0 }
1520 /* SHIFT_ASHIFTRT */
1523 { "shar %t0\t; shar.w\n\trotxr %s0\t; end shar.w", 0 },
1524 { "shar %z0\t; shar.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shar.l", 0 }
1531 { "shal.b %X0", 1 },
1532 { "shal.w %T0", 1 },
1535 /* SHIFT_LSHIFTRT */
1537 { "shlr.b %X0", 1 },
1538 { "shlr.w %T0", 1 },
1541 /* SHIFT_ASHIFTRT */
1543 { "shar.b %X0", 1 },
1544 { "shar.w %T0", 1 },
1550 /* Rotates are organized by which shift they'll be used in implementing.
1551 There's no need to record whether the cc is valid afterwards because
1552 it is the AND insn that will decide this. */
1554 static const char *const rotate_one[2][3][3] =
1561 "shlr %t0\t; rotr.w\n\trotxr %s0\n\tbst #7,%t0\t; end rotr.w",
1564 /* SHIFT_LSHIFTRT */
1567 "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w",
1570 /* SHIFT_ASHIFTRT */
1573 "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w",
1585 /* SHIFT_LSHIFTRT */
1591 /* SHIFT_ASHIFTRT */
1600 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
1601 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
1602 We don't achieve maximum efficiency in all cases, but the hooks are here
1605 For now we just use lots of switch statements. Since we don't even come
1606 close to supporting all the cases, this is simplest. If this function ever
1607 gets too big, perhaps resort to a more table based lookup. Of course,
1608 at this point you may just wish to do it all in rtl.
1610 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
1611 1,2,3,4 will be inlined (1,2 for SI). */
1613 static enum shift_alg
1614 get_shift_alg (cpu, shift_type, mode, count, assembler_p, cc_valid_p)
1616 enum shift_type shift_type;
1617 enum machine_mode mode;
1619 const char **assembler_p;
1622 /* The default is to loop. */
1623 enum shift_alg alg = SHIFT_LOOP;
1624 enum shift_mode shift_mode;
1626 /* We don't handle negative shifts or shifts greater than the word size,
1627 they should have been handled already. */
1629 if (count < 0 || count > GET_MODE_BITSIZE (mode))
1635 shift_mode = QIshift;
1638 shift_mode = HIshift;
1641 shift_mode = SIshift;
1647 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
1648 It is up to the caller to know that looping clobbers cc. */
1649 *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler;
1650 *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid;
1652 /* Now look for cases we want to optimize. */
1658 return SHIFT_INLINE;
1659 else if (count <= 6)
1661 if (shift_type == SHIFT_ASHIFTRT)
1667 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
1669 return SHIFT_ROT_AND;
1672 else if (count == 7)
1674 if (shift_type == SHIFT_ASHIFTRT)
1676 *assembler_p = "shll %X0\t; shar.b(7)\n\tsubx %X0,%X0\t; end shar.b(7)";
1678 return SHIFT_SPECIAL;
1682 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
1684 return SHIFT_ROT_AND;
1690 return SHIFT_INLINE;
1691 else if (count == 8)
1696 *assembler_p = "mov.b %s0,%t0\t; shal.w(8)\n\tsub.b %s0,%s0\t; end shal.w(8)";
1698 return SHIFT_SPECIAL;
1699 case SHIFT_LSHIFTRT:
1700 *assembler_p = "mov.b %t0,%s0\t; shlr.w(8)\n\tsub.b %t0,%t0\t; end shlr.w(8)";
1702 return SHIFT_SPECIAL;
1703 case SHIFT_ASHIFTRT:
1704 if (cpu == CPU_H8300)
1705 *assembler_p = "mov.b %t0,%s0\t; shar.w(8)\n\tshll %t0\n\tsubx %t0,%t0\t; end shar.w(8)";
1707 *assembler_p = "mov.b %t0,%s0\t; shar.w(8)\n\texts.w %T0\t; end shar.w(8)";
1709 return SHIFT_SPECIAL;
1713 else if (count == 15)
1715 if (shift_type == SHIFT_ASHIFTRT)
1717 *assembler_p = "shll %t0,%t0\t; shar.w(15)\n\tsubx %t0,%t0\n\tmov.b %t0,%s0\t; end shar.w(15)";
1719 return SHIFT_SPECIAL;
1723 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
1725 return SHIFT_ROT_AND;
1730 if (count <= (cpu == CPU_H8300 ? 2 : 4))
1731 return SHIFT_INLINE;
1732 else if (count == 8)
1734 if (cpu == CPU_H8300)
1739 *assembler_p = "mov.b %y0,%z0\t; shal.l(8)\n\tmov.b %x0,%y0\n\tmov.b %w0,%x0\n\tsub.b %w0,%w0\t; end shal.l(8)";
1741 return SHIFT_SPECIAL;
1742 case SHIFT_LSHIFTRT:
1743 *assembler_p = "mov.b %x0,%w0\t; shlr.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tsub.b %z0,%z0\t; end shlr.l(8)";
1745 return SHIFT_SPECIAL;
1746 case SHIFT_ASHIFTRT:
1747 *assembler_p = "mov.b %x0,%w0\t; shar.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tshll %z0\n\tsubx %z0,%z0; end shar.l(8)";
1749 return SHIFT_SPECIAL;
1752 else /* CPU_H8300H */
1753 /* We don't have byte level access to the high word so this isn't
1754 easy to do. For now, just loop. */
1757 else if (count == 16)
1762 *assembler_p = "mov.w %f0,%e0\t; shal.l(16)\n\tsub.w %f0,%f0\t; end shal.l(16)";
1764 return SHIFT_SPECIAL;
1765 case SHIFT_LSHIFTRT:
1766 *assembler_p = "mov.w %e0,%f0\t; shlr.l(16)\n\tsub.w %e0,%e0\t; end shlr.l(16)";
1768 return SHIFT_SPECIAL;
1769 case SHIFT_ASHIFTRT:
1770 if (cpu == CPU_H8300)
1771 *assembler_p = "mov.w %e0,%f0\t; shar.l(16)\n\tshll %z0\n\tsubx %z0,%z0\n\tmov.b %z0,%y0\t; end shar.l(16)";
1773 *assembler_p = "mov.w %e0,%f0\t; shar.l(16)\n\texts.l %S0\t; end shar.l(16)";
1775 return SHIFT_SPECIAL;
1778 else if (count >= 28 && count <= 30)
1780 if (shift_type == SHIFT_ASHIFTRT)
1786 if (cpu == CPU_H8300)
1790 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
1792 return SHIFT_ROT_AND;
1796 else if (count == 31)
1798 if (shift_type == SHIFT_ASHIFTRT)
1800 if (cpu == CPU_H8300)
1801 *assembler_p = "shll %z0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)";
1803 *assembler_p = "shll %e0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)";
1805 return SHIFT_SPECIAL;
1809 if (cpu == CPU_H8300)
1811 if (shift_type == SHIFT_ASHIFT)
1812 *assembler_p = "sub.w %e0,%e0\t; shal.l(31)\n\tshlr %w0\n\tmov.w %e0,%f0\n\trotxr %z0\t; end shal.l(31)";
1814 *assembler_p = "sub.w %f0,%f0\t; shlr.l(31)\n\tshll %z0\n\tmov.w %f0,%e0\n\trotxl %w0\t; end shlr.l(31)";
1816 return SHIFT_SPECIAL;
1820 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
1822 return SHIFT_ROT_AND;
1834 /* Emit the assembler code for doing shifts. */
1837 emit_a_shift (insn, operands)
1841 static int loopend_lab;
1844 rtx inside = PATTERN (insn);
1845 rtx shift = operands[3];
1846 enum machine_mode mode = GET_MODE (shift);
1847 enum rtx_code code = GET_CODE (shift);
1848 enum shift_type shift_type;
1849 enum shift_mode shift_mode;
1856 shift_mode = QIshift;
1859 shift_mode = HIshift;
1862 shift_mode = SIshift;
1871 shift_type = SHIFT_ASHIFTRT;
1874 shift_type = SHIFT_LSHIFTRT;
1877 shift_type = SHIFT_ASHIFT;
1883 if (GET_CODE (operands[2]) != CONST_INT)
1885 /* Indexing by reg, so have to loop and test at top */
1886 output_asm_insn ("mov.b %X2,%X4", operands);
1887 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
1889 /* Get the assembler code to do one shift. */
1890 get_shift_alg (cpu_type, shift_type, mode, 1, &assembler, &cc_valid);
1894 int n = INTVAL (operands[2]);
1897 /* If the count is negative, make it 0. */
1900 /* If the count is too big, truncate it.
1901 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
1902 do the intuitive thing. */
1903 else if (n > GET_MODE_BITSIZE (mode))
1904 n = GET_MODE_BITSIZE (mode);
1906 alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler, &cc_valid);
1912 output_asm_insn (assembler, operands);
1914 cc_status.value1 = operands[0];
1918 int m = GET_MODE_BITSIZE (mode) - n;
1919 int mask = (shift_type == SHIFT_ASHIFT
1920 ? ((1 << GET_MODE_BITSIZE (mode) - n) - 1) << n
1921 : (1 << GET_MODE_BITSIZE (mode) - n) - 1);
1923 /* Not all possibilities of rotate are supported. They shouldn't
1924 be generated, but let's watch for 'em. */
1928 output_asm_insn (assembler, operands);
1934 sprintf (insn_buf, "and #%d,%%X0\t; end shift %d via rotate+and",
1936 cc_status.value1 = operands[0];
1939 sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0\t; end shift %d via rotate+and",
1940 mask & 255, mask >> 8, n);
1948 sprintf (insn_buf, "and.%c #%d,%%%c0",
1949 "bwl"[shift_mode], mask,
1950 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
1951 cc_status.value1 = operands[0];
1953 output_asm_insn (insn_buf, operands);
1957 output_asm_insn (assembler, operands);
1961 /* Need a loop, move limit to tmp reg */
1962 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, names_big[REGNO (operands[4])]);
1965 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
1966 output_asm_insn (assembler, operands);
1967 output_asm_insn ("add #0xff,%X4", operands);
1968 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
1969 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
1974 /* Fix the operands of a gen_xxx so that it could become a bit
1978 fix_bit_operand (operands, what, type)
1983 /* The bit_operand predicate accepts any memory during RTL generation, but
1984 only 'U' memory afterwards, so if this is a MEM operand, we must force
1985 it to be valid for 'U' by reloading the address. */
1987 if (GET_CODE (operands[2]) == CONST_INT)
1989 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
1991 /* Ok to have a memory dest. */
1992 if (GET_CODE (operands[0]) == MEM && !EXTRA_CONSTRAINT (operands[0], 'U'))
1995 mem = gen_rtx (MEM, GET_MODE (operands[0]),
1996 copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
1997 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[0]);
1998 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[0]);
1999 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[0]);
2003 if (GET_CODE (operands[1]) == MEM && !EXTRA_CONSTRAINT (operands[1], 'U'))
2006 mem = gen_rtx (MEM, GET_MODE (operands[1]),
2007 copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
2008 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[1]);
2009 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[1]);
2010 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[1]);
2017 /* Dest and src op must be register. */
2019 operands[1] = force_reg (QImode, operands[1]);
2021 rtx res = gen_reg_rtx (QImode);
2022 emit_insn (gen_rtx (SET, VOIDmode, res, gen_rtx (type, QImode, operands[1], operands[2])));
2023 emit_insn (gen_rtx (SET, VOIDmode, operands[0], res));