1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
53 #define FRV_INLINE inline
56 /* Temporary register allocation support structure. */
57 typedef struct frv_tmp_reg_struct
59 HARD_REG_SET regs; /* possible registers to allocate */
60 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
64 /* Register state information for VLIW re-packing phase. These values must fit
65 within an unsigned char. */
66 #define REGSTATE_DEAD 0x00 /* register is currently dead */
67 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
68 #define REGSTATE_LIVE 0x08 /* register is live */
69 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
70 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
71 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
72 #define REGSTATE_UNUSED 0x80 /* bit for hire */
73 #define REGSTATE_MASK 0xff /* mask for the bits to set */
75 /* conditional expression used */
76 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
78 /* the following is not sure in the reg_state bytes, so can have a larger value
80 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
82 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
90 /* Information required by frv_frame_access. */
93 /* This field is FRV_LOAD if registers are to be loaded from the stack and
94 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
95 the move is being done by the prologue code while FRV_LOAD implies it
96 is being done by the epilogue. */
99 /* The base register to use when accessing the stack. This may be the
100 frame pointer, stack pointer, or a temporary. The choice of register
101 depends on which part of the frame is being accessed and how big the
105 /* The offset of BASE from the bottom of the current frame, in bytes. */
107 } frv_frame_accessor_t;
109 /* Define the information needed to generate branch and scc insns. This is
110 stored from the compare operation. */
114 /* Conditional execution support gathered together in one structure */
117 /* Linked list of insns to add if the conditional execution conversion was
118 successful. Each link points to an EXPR_LIST which points to the pattern
119 of the insn to add, and the insn to be inserted before. */
120 rtx added_insns_list;
122 /* Identify which registers are safe to allocate for if conversions to
123 conditional execution. We keep the last allocated register in the
124 register classes between COND_EXEC statements. This will mean we allocate
125 different registers for each different COND_EXEC group if we can. This
126 might allow the scheduler to intermix two different COND_EXEC sections. */
127 frv_tmp_reg_t tmp_reg;
129 /* For nested IFs, identify which CC registers are used outside of setting
130 via a compare isnsn, and using via a check insn. This will allow us to
131 know if we can rewrite the register to use a different register that will
132 be paired with the CR register controlling the nested IF-THEN blocks. */
133 HARD_REG_SET nested_cc_ok_rewrite;
135 /* Temporary registers allocated to hold constants during conditional
137 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
139 /* Current number of temp registers available. */
140 int cur_scratch_regs;
142 /* Number of nested conditional execution blocks */
143 int num_nested_cond_exec;
145 /* Map of insns that set up constants in scratch registers. */
146 bitmap scratch_insns_bitmap;
148 /* Conditional execution test register (CC0..CC7) */
151 /* Conditional execution compare register that is paired with cr_reg, so that
152 nested compares can be done. The csubcc and caddcc instructions don't
153 have enough bits to specify both a CC register to be set and a CR register
154 to do the test on, so the same bit number is used for both. Needless to
155 say, this is rather inconvient for GCC. */
158 /* Extra CR registers used for &&, ||. */
162 /* Previous CR used in nested if, to make sure we are dealing with the same
163 nested if as the previous statement. */
164 rtx last_nested_if_cr;
168 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
170 /* Map register number to smallest register class. */
171 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
173 /* Map class letter into register class */
174 enum reg_class reg_class_from_letter[256];
176 /* Cached value of frv_stack_info */
177 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
179 /* -mbranch-cost= support */
180 const char *frv_branch_cost_string;
181 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
184 const char *frv_cpu_string; /* -mcpu= option */
185 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
187 /* -mcond-exec-insns= support */
188 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
189 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
191 /* -mcond-exec-temps= support */
192 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
193 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
195 /* -msched-lookahead=n */
196 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
197 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
199 /* Forward references */
200 static int frv_default_flags_for_cpu PARAMS ((void));
201 static int frv_string_begins_with PARAMS ((tree, const char *));
202 static FRV_INLINE int const_small_data_p PARAMS ((rtx));
203 static FRV_INLINE int plus_small_data_p PARAMS ((rtx, rtx));
204 static void frv_print_operand_memory_reference_reg
205 PARAMS ((FILE *, rtx));
206 static void frv_print_operand_memory_reference PARAMS ((FILE *, rtx, int));
207 static int frv_print_operand_jump_hint PARAMS ((rtx));
208 static FRV_INLINE int frv_regno_ok_for_base_p PARAMS ((int, int));
209 static rtx single_set_pattern PARAMS ((rtx));
210 static int frv_function_contains_far_jump PARAMS ((void));
211 static rtx frv_alloc_temp_reg PARAMS ((frv_tmp_reg_t *,
215 static rtx frv_frame_offset_rtx PARAMS ((int));
216 static rtx frv_frame_mem PARAMS ((enum machine_mode,
218 static rtx frv_dwarf_store PARAMS ((rtx, int));
219 static void frv_frame_insn PARAMS ((rtx, rtx));
220 static void frv_frame_access PARAMS ((frv_frame_accessor_t*,
222 static void frv_frame_access_multi PARAMS ((frv_frame_accessor_t*,
223 frv_stack_t *, int));
224 static void frv_frame_access_standard_regs PARAMS ((enum frv_stack_op,
226 static struct machine_function *frv_init_machine_status PARAMS ((void));
227 static int frv_legitimate_memory_operand PARAMS ((rtx,
230 static rtx frv_int_to_acc PARAMS ((enum insn_code,
232 static enum machine_mode frv_matching_accg_mode PARAMS ((enum machine_mode));
233 static rtx frv_read_argument PARAMS ((tree *));
234 static int frv_check_constant_argument PARAMS ((enum insn_code,
236 static rtx frv_legitimize_target PARAMS ((enum insn_code, rtx));
237 static rtx frv_legitimize_argument PARAMS ((enum insn_code,
239 static rtx frv_expand_set_builtin PARAMS ((enum insn_code,
241 static rtx frv_expand_unop_builtin PARAMS ((enum insn_code,
243 static rtx frv_expand_binop_builtin PARAMS ((enum insn_code,
245 static rtx frv_expand_cut_builtin PARAMS ((enum insn_code,
247 static rtx frv_expand_binopimm_builtin PARAMS ((enum insn_code,
249 static rtx frv_expand_voidbinop_builtin PARAMS ((enum insn_code,
251 static rtx frv_expand_voidtriop_builtin PARAMS ((enum insn_code,
253 static rtx frv_expand_voidaccop_builtin PARAMS ((enum insn_code,
255 static rtx frv_expand_mclracc_builtin PARAMS ((tree));
256 static rtx frv_expand_mrdacc_builtin PARAMS ((enum insn_code,
258 static rtx frv_expand_mwtacc_builtin PARAMS ((enum insn_code,
260 static rtx frv_expand_noargs_builtin PARAMS ((enum insn_code));
261 static rtx frv_emit_comparison PARAMS ((enum rtx_code, rtx,
263 static int frv_clear_registers_used PARAMS ((rtx *, void *));
264 static void frv_ifcvt_add_insn PARAMS ((rtx, rtx, int));
265 static rtx frv_ifcvt_rewrite_mem PARAMS ((rtx,
268 static rtx frv_ifcvt_load_value PARAMS ((rtx, rtx));
269 static void frv_registers_update PARAMS ((rtx, unsigned char [],
270 int [], int *, int));
271 static int frv_registers_used_p PARAMS ((rtx, unsigned char [],
273 static int frv_registers_set_p PARAMS ((rtx, unsigned char [],
275 static int frv_use_dfa_pipeline_interface PARAMS ((void));
276 static void frv_pack_insns PARAMS ((void));
277 static void frv_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
278 static void frv_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
279 static bool frv_assemble_integer PARAMS ((rtx, unsigned, int));
280 static void frv_init_builtins PARAMS ((void));
281 static rtx frv_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
282 static void frv_init_libfuncs PARAMS ((void));
283 static bool frv_in_small_data_p PARAMS ((tree));
284 static void frv_asm_output_mi_thunk
285 PARAMS ((FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree));
286 static bool frv_rtx_costs PARAMS ((rtx, int, int, int*));
287 static void frv_asm_out_constructor PARAMS ((rtx, int));
288 static void frv_asm_out_destructor PARAMS ((rtx, int));
290 /* Initialize the GCC target structure. */
291 #undef TARGET_ASM_FUNCTION_PROLOGUE
292 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
293 #undef TARGET_ASM_FUNCTION_EPILOGUE
294 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
295 #undef TARGET_ASM_INTEGER
296 #define TARGET_ASM_INTEGER frv_assemble_integer
297 #undef TARGET_INIT_BUILTINS
298 #define TARGET_INIT_BUILTINS frv_init_builtins
299 #undef TARGET_EXPAND_BUILTIN
300 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
301 #undef TARGET_INIT_LIBFUNCS
302 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
303 #undef TARGET_IN_SMALL_DATA_P
304 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
305 #undef TARGET_RTX_COSTS
306 #define TARGET_RTX_COSTS frv_rtx_costs
307 #undef TARGET_ASM_CONSTRUCTOR
308 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
309 #undef TARGET_ASM_DESTRUCTOR
310 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
312 #undef TARGET_ASM_OUTPUT_MI_THUNK
313 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
314 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
315 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
317 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
318 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE frv_use_dfa_pipeline_interface
320 struct gcc_target targetm = TARGET_INITIALIZER;
322 /* Given a CONST, return true if the symbol_ref points to small data. */
324 static FRV_INLINE int
325 const_small_data_p (x)
330 if (GET_CODE (XEXP (x, 0)) != PLUS)
333 x0 = XEXP (XEXP (x, 0), 0);
334 if (GET_CODE (x0) != SYMBOL_REF || !SYMBOL_REF_SMALL_P (x0))
337 x1 = XEXP (XEXP (x, 0), 1);
338 if (GET_CODE (x1) != CONST_INT
339 || !IN_RANGE_P (INTVAL (x1), -2048, 2047))
345 /* Given a PLUS, return true if this is a small data reference. */
347 static FRV_INLINE int
348 plus_small_data_p (op0, op1)
352 if (GET_MODE (op0) == SImode
353 && GET_CODE (op0) == REG
354 && REGNO (op0) == SDA_BASE_REG)
356 if (GET_CODE (op1) == SYMBOL_REF)
357 return SYMBOL_REF_SMALL_P (op1);
359 if (GET_CODE (op1) == CONST)
360 return const_small_data_p (op1);
368 frv_default_flags_for_cpu ()
370 switch (frv_cpu_type)
372 case FRV_CPU_GENERIC:
373 return MASK_DEFAULT_FRV;
377 return MASK_DEFAULT_FR500;
380 return MASK_DEFAULT_FR400;
384 return MASK_DEFAULT_SIMPLE;
389 /* Sometimes certain combinations of command options do not make
390 sense on a particular target machine. You can define a macro
391 `OVERRIDE_OPTIONS' to take account of this. This macro, if
392 defined, is executed once just after all the command options have
395 Don't use this macro to turn on various extra optimizations for
396 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
399 frv_override_options ()
403 /* Set the cpu type */
406 if (strcmp (frv_cpu_string, "simple") == 0)
407 frv_cpu_type = FRV_CPU_SIMPLE;
409 else if (strcmp (frv_cpu_string, "tomcat") == 0)
410 frv_cpu_type = FRV_CPU_TOMCAT;
412 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
413 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
417 const char *p = frv_cpu_string + sizeof ("fr") - 1;
418 if (strcmp (p, "500") == 0)
419 frv_cpu_type = FRV_CPU_FR500;
421 else if (strcmp (p, "400") == 0)
422 frv_cpu_type = FRV_CPU_FR400;
424 else if (strcmp (p, "300") == 0)
425 frv_cpu_type = FRV_CPU_FR300;
427 else if (strcmp (p, "v") == 0)
428 frv_cpu_type = FRV_CPU_GENERIC;
431 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
435 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
437 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
438 linker about linking pic and non-pic code. */
441 if (!flag_pic) /* -fPIC */
444 if (! g_switch_set) /* -G0 */
451 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
453 if (write_symbols == DWARF_DEBUG && flag_pic)
454 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
456 /* Change the branch cost value */
457 if (frv_branch_cost_string)
458 frv_branch_cost_int = atoi (frv_branch_cost_string);
460 /* Change the # of insns to be converted to conditional execution */
461 if (frv_condexec_insns_str)
462 frv_condexec_insns = atoi (frv_condexec_insns_str);
464 /* Change # of temporary registers used to hold integer constants */
465 if (frv_condexec_temps_str)
466 frv_condexec_temps = atoi (frv_condexec_temps_str);
468 /* Change scheduling look ahead. */
469 if (frv_sched_lookahead_str)
470 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
472 /* A C expression whose value is a register class containing hard
473 register REGNO. In general there is more than one such class;
474 choose a class which is "minimal", meaning that no smaller class
475 also contains the register. */
477 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
479 enum reg_class class;
483 int gpr_reg = regno - GPR_FIRST;
484 if ((gpr_reg & 3) == 0)
487 else if ((gpr_reg & 1) == 0)
494 else if (FPR_P (regno))
496 int fpr_reg = regno - GPR_FIRST;
497 if ((fpr_reg & 3) == 0)
498 class = QUAD_FPR_REGS;
500 else if ((fpr_reg & 1) == 0)
507 else if (regno == LR_REGNO)
510 else if (regno == LCR_REGNO)
513 else if (ICC_P (regno))
516 else if (FCC_P (regno))
519 else if (ICR_P (regno))
522 else if (FCR_P (regno))
525 else if (ACC_P (regno))
527 int r = regno - ACC_FIRST;
529 class = QUAD_ACC_REGS;
530 else if ((r & 1) == 0)
531 class = EVEN_ACC_REGS;
536 else if (ACCG_P (regno))
542 regno_reg_class[regno] = class;
545 /* Check for small data option */
547 g_switch_value = SDATA_DEFAULT_SIZE;
549 /* A C expression which defines the machine-dependent operand
550 constraint letters for register classes. If CHAR is such a
551 letter, the value should be the register class corresponding to
552 it. Otherwise, the value should be `NO_REGS'. The register
553 letter `r', corresponding to class `GENERAL_REGS', will not be
554 passed to this macro; you do not need to handle it.
556 The following letters are unavailable, due to being used as
561 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
562 'Q', 'R', 'S', 'T', 'U'
564 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
566 for (i = 0; i < 256; i++)
567 reg_class_from_letter[i] = NO_REGS;
569 reg_class_from_letter['a'] = ACC_REGS;
570 reg_class_from_letter['b'] = EVEN_ACC_REGS;
571 reg_class_from_letter['c'] = CC_REGS;
572 reg_class_from_letter['d'] = GPR_REGS;
573 reg_class_from_letter['e'] = EVEN_REGS;
574 reg_class_from_letter['f'] = FPR_REGS;
575 reg_class_from_letter['h'] = FEVEN_REGS;
576 reg_class_from_letter['l'] = LR_REG;
577 reg_class_from_letter['q'] = QUAD_REGS;
578 reg_class_from_letter['t'] = ICC_REGS;
579 reg_class_from_letter['u'] = FCC_REGS;
580 reg_class_from_letter['v'] = ICR_REGS;
581 reg_class_from_letter['w'] = FCR_REGS;
582 reg_class_from_letter['x'] = QUAD_FPR_REGS;
583 reg_class_from_letter['y'] = LCR_REG;
584 reg_class_from_letter['z'] = SPR_REGS;
585 reg_class_from_letter['A'] = QUAD_ACC_REGS;
586 reg_class_from_letter['B'] = ACCG_REGS;
587 reg_class_from_letter['C'] = CR_REGS;
589 /* There is no single unaligned SI op for PIC code. Sometimes we
590 need to use ".4byte" and sometimes we need to use ".picptr".
591 See frv_assemble_integer for details. */
593 targetm.asm_out.unaligned_op.si = 0;
595 init_machine_status = frv_init_machine_status;
599 /* Some machines may desire to change what optimizations are performed for
600 various optimization levels. This macro, if defined, is executed once just
601 after the optimization level is determined and before the remainder of the
602 command options have been parsed. Values set in this macro are used as the
603 default values for the other command line options.
605 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
606 `-O' is specified, and 0 if neither is specified.
608 SIZE is nonzero if `-Os' is specified, 0 otherwise.
610 You should not use this macro to change options that are not
611 machine-specific. These should uniformly selected by the same optimization
612 level on all supported machines. Use this macro to enable machbine-specific
615 *Do not examine `write_symbols' in this macro!* The debugging options are
616 *not supposed to alter the generated code. */
618 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
619 scheduling pass at the current time. */
621 frv_optimization_options (level, size)
623 int size ATTRIBUTE_UNUSED;
627 #ifdef DISABLE_SCHED2
628 flag_schedule_insns_after_reload = 0;
637 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
640 frv_string_begins_with (name, prefix)
644 int prefix_len = strlen (prefix);
646 /* Remember: NAME's length includes the null terminator. */
647 return (TREE_STRING_LENGTH (name) > prefix_len
648 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
651 /* Zero or more C statements that may conditionally modify two variables
652 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
653 been initialized from the two preceding macros.
655 This is necessary in case the fixed or call-clobbered registers depend on
658 You need not define this macro if it has no work to do.
660 If the usage of an entire class of registers depends on the target flags,
661 you may indicate this to GCC by using this macro to modify `fixed_regs' and
662 `call_used_regs' to 1 for each of the registers in the classes which should
663 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
664 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
666 (However, if this class is not included in `GENERAL_REGS' and all of the
667 insn patterns whose constraints permit this class are controlled by target
668 switches, then GCC will automatically avoid using these registers when the
669 target switches are opposed to them.) */
672 frv_conditional_register_usage ()
676 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
677 fixed_regs[i] = call_used_regs[i] = 1;
679 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
680 fixed_regs[i] = call_used_regs[i] = 1;
682 for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++)
683 fixed_regs[i] = call_used_regs[i] = 1;
685 for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++)
686 fixed_regs[i] = call_used_regs[i] = 1;
688 /* Reserve the registers used for conditional execution. At present, we need
689 1 ICC and 1 ICR register. */
690 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
691 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
695 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
696 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
697 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
698 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
702 /* If -fpic, SDA_BASE_REG is the PIC register. */
703 if (g_switch_value == 0 && !flag_pic)
704 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
707 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
713 * Compute the stack frame layout
716 * +---------------+-----------------------+-----------------------+
717 * |Register |type |caller-save/callee-save|
718 * +---------------+-----------------------+-----------------------+
719 * |GR0 |Zero register | - |
720 * |GR1 |Stack pointer(SP) | - |
721 * |GR2 |Frame pointer(FP) | - |
722 * |GR3 |Hidden parameter | caller save |
723 * |GR4-GR7 | - | caller save |
724 * |GR8-GR13 |Argument register | caller save |
725 * |GR14-GR15 | - | caller save |
726 * |GR16-GR31 | - | callee save |
727 * |GR32-GR47 | - | caller save |
728 * |GR48-GR63 | - | callee save |
729 * |FR0-FR15 | - | caller save |
730 * |FR16-FR31 | - | callee save |
731 * |FR32-FR47 | - | caller save |
732 * |FR48-FR63 | - | callee save |
733 * +---------------+-----------------------+-----------------------+
737 * SP-> |-----------------------------------|
739 * |-----------------------------------|
740 * | Register save area |
741 * |-----------------------------------|
742 * | Local variable save area |
743 * FP-> |-----------------------------------|
745 * |-----------------------------------|
746 * | Hidden parameter save area |
747 * |-----------------------------------|
748 * | Return address(LR) storage area |
749 * |-----------------------------------|
750 * | Padding for alignment |
751 * |-----------------------------------|
752 * | Register argument area |
753 * OLD SP-> |-----------------------------------|
755 * |-----------------------------------|
758 * Argument area/Parameter area:
760 * When a function is called, this area is used for argument transfer. When
761 * the argument is set up by the caller function, this area is referred to as
762 * the argument area. When the argument is referenced by the callee function,
763 * this area is referred to as the parameter area. The area is allocated when
764 * all arguments cannot be placed on the argument register at the time of
767 * Register save area:
769 * This is a register save area that must be guaranteed for the caller
770 * function. This area is not secured when the register save operation is not
773 * Local variable save area:
775 * This is the area for local variables and temporary variables.
779 * This area stores the FP value of the caller function.
781 * Hidden parameter save area:
783 * This area stores the start address of the return value storage
784 * area for a struct/union return function.
785 * When a struct/union is used as the return value, the caller
786 * function stores the return value storage area start address in
787 * register GR3 and passes it to the caller function.
788 * The callee function interprets the address stored in the GR3
789 * as the return value storage area start address.
790 * When register GR3 needs to be saved into memory, the callee
791 * function saves it in the hidden parameter save area. This
792 * area is not secured when the save operation is not needed.
794 * Return address(LR) storage area:
796 * This area saves the LR. The LR stores the address of a return to the caller
797 * function for the purpose of function calling.
799 * Argument register area:
801 * This area saves the argument register. This area is not secured when the
802 * save operation is not needed.
806 * Arguments, the count of which equals the count of argument registers (6
807 * words), are positioned in registers GR8 to GR13 and delivered to the callee
808 * function. When a struct/union return function is called, the return value
809 * area address is stored in register GR3. Arguments not placed in the
810 * argument registers will be stored in the stack argument area for transfer
811 * purposes. When an 8-byte type argument is to be delivered using registers,
812 * it is divided into two and placed in two registers for transfer. When
813 * argument registers must be saved to memory, the callee function secures an
814 * argument register save area in the stack. In this case, a continuous
815 * argument register save area must be established in the parameter area. The
816 * argument register save area must be allocated as needed to cover the size of
817 * the argument register to be saved. If the function has a variable count of
818 * arguments, it saves all argument registers in the argument register save
821 * Argument Extension Format:
823 * When an argument is to be stored in the stack, its type is converted to an
824 * extended type in accordance with the individual argument type. The argument
825 * is freed by the caller function after the return from the callee function is
828 * +-----------------------+---------------+------------------------+
829 * | Argument Type |Extended Type |Stack Storage Size(byte)|
830 * +-----------------------+---------------+------------------------+
832 * |signed char |int | 4 |
833 * |unsigned char |int | 4 |
834 * |[signed] short int |int | 4 |
835 * |unsigned short int |int | 4 |
836 * |[signed] int |No extension | 4 |
837 * |unsigned int |No extension | 4 |
838 * |[signed] long int |No extension | 4 |
839 * |unsigned long int |No extension | 4 |
840 * |[signed] long long int |No extension | 8 |
841 * |unsigned long long int |No extension | 8 |
842 * |float |double | 8 |
843 * |double |No extension | 8 |
844 * |long double |No extension | 8 |
845 * |pointer |No extension | 4 |
846 * |struct/union |- | 4 (*1) |
847 * +-----------------------+---------------+------------------------+
849 * When a struct/union is to be delivered as an argument, the caller copies it
850 * to the local variable area and delivers the address of that area.
854 * +-------------------------------+----------------------+
855 * |Return Value Type |Return Value Interface|
856 * +-------------------------------+----------------------+
858 * |[signed|unsigned] char |GR8 |
859 * |[signed|unsigned] short int |GR8 |
860 * |[signed|unsigned] int |GR8 |
861 * |[signed|unsigned] long int |GR8 |
863 * |[signed|unsigned] long long int|GR8 & GR9 |
865 * |double |GR8 & GR9 |
866 * |long double |GR8 & GR9 |
867 * |struct/union |(*1) |
868 * +-------------------------------+----------------------+
870 * When a struct/union is used as the return value, the caller function stores
871 * the start address of the return value storage area into GR3 and then passes
872 * it to the callee function. The callee function interprets GR3 as the start
873 * address of the return value storage area. When this address needs to be
874 * saved in memory, the callee function secures the hidden parameter save area
875 * and saves the address in that area.
881 static frv_stack_t info, zero_info;
882 frv_stack_t *info_ptr = &info;
883 tree fndecl = current_function_decl;
891 /* If we've already calculated the values and reload is complete, just return now */
893 return frv_stack_cache;
895 /* Zero all fields */
898 /* Set up the register range information */
899 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
900 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
901 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
902 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
904 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
905 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
906 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
907 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
909 info_ptr->regs[STACK_REGS_LR].name = "lr";
910 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
911 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
912 info_ptr->regs[STACK_REGS_LR].special_p = 1;
914 info_ptr->regs[STACK_REGS_CC].name = "cc";
915 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
916 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
917 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
919 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
920 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
921 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
923 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
924 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
925 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
926 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
927 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
929 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
930 info_ptr->regs[STACK_REGS_STRUCT].first = STRUCT_VALUE_REGNUM;
931 info_ptr->regs[STACK_REGS_STRUCT].last = STRUCT_VALUE_REGNUM;
932 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
934 info_ptr->regs[STACK_REGS_FP].name = "fp";
935 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
936 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
937 info_ptr->regs[STACK_REGS_FP].special_p = 1;
939 /* Determine if this is a stdarg function. If so, allocate space to store
946 /* Find the last argument, and see if it is __builtin_va_alist. */
947 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
949 next_arg = TREE_CHAIN (cur_arg);
950 if (next_arg == (tree)0)
952 if (DECL_NAME (cur_arg)
953 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
961 /* Iterate over all of the register ranges */
962 for (range = 0; range < STACK_REGS_MAX; range++)
964 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
965 int first = reg_ptr->first;
966 int last = reg_ptr->last;
971 /* Calculate which registers need to be saved & save area size */
975 for (regno = first; regno <= last; regno++)
977 if ((regs_ever_live[regno] && !call_used_regs[regno])
978 || (current_function_calls_eh_return
979 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
980 || (flag_pic && cfun->uses_pic_offset_table && regno == PIC_REGNO))
982 info_ptr->save_p[regno] = REG_SAVE_1WORD;
983 size_1word += UNITS_PER_WORD;
988 /* Calculate whether we need to create a frame after everything else
989 has been processed. */
994 if (regs_ever_live[LR_REGNO]
996 || frame_pointer_needed
997 || (flag_pic && cfun->uses_pic_offset_table))
999 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1000 size_1word += UNITS_PER_WORD;
1004 case STACK_REGS_STDARG:
1007 /* If this is a stdarg function with a non varardic argument split
1008 between registers and the stack, adjust the saved registers
1010 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1013 for (regno = first; regno <= last; regno++)
1015 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1016 size_1word += UNITS_PER_WORD;
1019 info_ptr->stdarg_size = size_1word;
1023 case STACK_REGS_STRUCT:
1024 if (cfun->returns_struct)
1026 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1027 size_1word += UNITS_PER_WORD;
1035 /* If this is a field, it only takes one word */
1036 if (reg_ptr->field_p)
1037 size_1word = UNITS_PER_WORD;
1039 /* Determine which register pairs can be saved together */
1040 else if (reg_ptr->dword_p && TARGET_DWORD)
1042 for (regno = first; regno < last; regno += 2)
1044 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1046 size_2words += 2 * UNITS_PER_WORD;
1047 size_1word -= 2 * UNITS_PER_WORD;
1048 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1049 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1054 reg_ptr->size_1word = size_1word;
1055 reg_ptr->size_2words = size_2words;
1057 if (! reg_ptr->special_p)
1059 info_ptr->regs_size_1word += size_1word;
1060 info_ptr->regs_size_2words += size_2words;
1065 /* Set up the sizes of each each field in the frame body, making the sizes
1066 of each be divisible by the size of a dword if dword operations might
1067 be used, or the size of a word otherwise. */
1068 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1070 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1071 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1072 + info_ptr->regs_size_1word,
1074 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1076 info_ptr->pretend_size = cfun->pretend_args_size;
1078 /* Work out the size of the frame, excluding the header. Both the frame
1079 body and register parameter area will be dword-aligned. */
1080 info_ptr->total_size
1081 = (ADDR_ALIGN (info_ptr->parameter_size
1082 + info_ptr->regs_size
1083 + info_ptr->vars_size,
1085 + ADDR_ALIGN (info_ptr->pretend_size
1086 + info_ptr->stdarg_size,
1087 2 * UNITS_PER_WORD));
1089 /* See if we need to create a frame at all, if so add header area. */
1090 if (info_ptr->total_size > 0
1091 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1092 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1094 offset = info_ptr->parameter_size;
1095 info_ptr->header_size = 4 * UNITS_PER_WORD;
1096 info_ptr->total_size += 4 * UNITS_PER_WORD;
1098 /* Calculate the offsets to save normal register pairs */
1099 for (range = 0; range < STACK_REGS_MAX; range++)
1101 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1102 if (! reg_ptr->special_p)
1104 int first = reg_ptr->first;
1105 int last = reg_ptr->last;
1108 for (regno = first; regno <= last; regno++)
1109 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1110 && regno != FRAME_POINTER_REGNUM
1111 && (regno < FIRST_ARG_REGNUM
1112 || regno > LAST_ARG_REGNUM))
1114 info_ptr->reg_offset[regno] = offset;
1115 offset += 2 * UNITS_PER_WORD;
1120 /* Calculate the offsets to save normal single registers */
1121 for (range = 0; range < STACK_REGS_MAX; range++)
1123 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1124 if (! reg_ptr->special_p)
1126 int first = reg_ptr->first;
1127 int last = reg_ptr->last;
1130 for (regno = first; regno <= last; regno++)
1131 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1132 && regno != FRAME_POINTER_REGNUM
1133 && (regno < FIRST_ARG_REGNUM
1134 || regno > LAST_ARG_REGNUM))
1136 info_ptr->reg_offset[regno] = offset;
1137 offset += UNITS_PER_WORD;
1142 /* Calculate the offset to save the local variables at. */
1143 offset = ADDR_ALIGN (offset, alignment);
1144 if (info_ptr->vars_size)
1146 info_ptr->vars_offset = offset;
1147 offset += info_ptr->vars_size;
1150 /* Align header to a dword-boundary. */
1151 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1153 /* Calculate the offsets in the fixed frame. */
1154 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1155 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1156 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1158 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1159 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1160 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1162 if (cfun->returns_struct)
1164 info_ptr->save_p[STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1165 info_ptr->reg_offset[STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1166 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1169 /* Calculate the offsets to store the arguments passed in registers
1170 for stdarg functions. The register pairs are first and the single
1171 register if any is last. The register save area starts on a
1173 if (info_ptr->stdarg_size)
1175 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1176 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1179 /* Skip the header. */
1180 offset += 4 * UNITS_PER_WORD;
1181 for (regno = first; regno <= last; regno++)
1183 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1185 info_ptr->reg_offset[regno] = offset;
1186 offset += 2 * UNITS_PER_WORD;
1188 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1190 info_ptr->reg_offset[regno] = offset;
1191 offset += UNITS_PER_WORD;
1197 if (reload_completed)
1198 frv_stack_cache = info_ptr;
1204 /* Print the information about the frv stack offsets, etc. when debugging. */
1207 frv_debug_stack (info)
1213 info = frv_stack_info ();
1215 fprintf (stderr, "\nStack information for function %s:\n",
1216 ((current_function_decl && DECL_NAME (current_function_decl))
1217 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1220 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1221 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1222 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1223 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1224 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1226 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1227 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1228 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1229 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1231 for (range = 0; range < STACK_REGS_MAX; range++)
1233 frv_stack_regs_t *regs = &(info->regs[range]);
1234 if ((regs->size_1word + regs->size_2words) > 0)
1236 int first = regs->first;
1237 int last = regs->last;
1240 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1241 regs->name, regs->size_1word + regs->size_2words,
1242 regs->size_1word, regs->size_2words);
1244 for (regno = first; regno <= last; regno++)
1246 if (info->save_p[regno] == REG_SAVE_1WORD)
1247 fprintf (stderr, " %s (%d)", reg_names[regno],
1248 info->reg_offset[regno]);
1250 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1251 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1252 reg_names[regno+1], info->reg_offset[regno]);
1255 fputc ('\n', stderr);
1265 /* The following variable value is TRUE if the next output insn should
1266 finish cpu cycle. In order words the insn will have packing bit
1267 (which means absence of asm code suffix `.p' on assembler. */
1269 static int frv_insn_packing_flag;
1271 /* True if the current function contains a far jump. */
1274 frv_function_contains_far_jump ()
1276 rtx insn = get_insns ();
1278 && !(GET_CODE (insn) == JUMP_INSN
1279 /* Ignore tablejump patterns. */
1280 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1281 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1282 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1283 insn = NEXT_INSN (insn);
1284 return (insn != NULL);
1287 /* For the FRV, this function makes sure that a function with far jumps
1288 will return correctly. It also does the VLIW packing. */
1291 frv_function_prologue (file, size)
1293 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1295 /* If no frame was created, check whether the function uses a call
1296 instruction to implement a far jump. If so, save the link in gr3 and
1297 replace all returns to LR with returns to GR3. GR3 is used because it
1298 is call-clobbered, because is not available to the register allocator,
1299 and because all functions that take a hidden argument pointer will have
1301 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1305 /* Just to check that the above comment is true. */
1306 if (regs_ever_live[GPR_FIRST + 3])
1309 /* Generate the instruction that saves the link register. */
1310 fprintf (file, "\tmovsg lr,gr3\n");
1312 /* Replace the LR with GR3 in *return_internal patterns. The insn
1313 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1314 simply emit a different assembly directive because bralr and jmpl
1315 execute in different units. */
1316 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1317 if (GET_CODE (insn) == JUMP_INSN)
1319 rtx pattern = PATTERN (insn);
1320 if (GET_CODE (pattern) == PARALLEL
1321 && XVECLEN (pattern, 0) >= 2
1322 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1323 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1325 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1326 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1327 REGNO (address) = GPR_FIRST + 3;
1333 frv_insn_packing_flag = TRUE;
1337 /* Return the next available temporary register in a given class. */
1340 frv_alloc_temp_reg (info, class, mode, mark_as_used, no_abort)
1341 frv_tmp_reg_t *info; /* which registers are available */
1342 enum reg_class class; /* register class desired */
1343 enum machine_mode mode; /* mode to allocate register with */
1344 int mark_as_used; /* register not available after allocation */
1345 int no_abort; /* return NULL instead of aborting */
1347 int regno = info->next_reg[ (int)class ];
1348 int orig_regno = regno;
1349 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1354 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1355 && TEST_HARD_REG_BIT (info->regs, regno))
1358 if (++regno >= FIRST_PSEUDO_REGISTER)
1360 if (regno == orig_regno)
1369 nr = HARD_REGNO_NREGS (regno, mode);
1370 info->next_reg[ (int)class ] = regno + nr;
1373 for (i = 0; i < nr; i++)
1374 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1376 return gen_rtx_REG (mode, regno);
1380 /* Return an rtx with the value OFFSET, which will either be a register or a
1381 signed 12-bit integer. It can be used as the second operand in an "add"
1382 instruction, or as the index in a load or store.
1384 The function returns a constant rtx if OFFSET is small enough, otherwise
1385 it loads the constant into register OFFSET_REGNO and returns that. */
1387 frv_frame_offset_rtx (offset)
1390 rtx offset_rtx = GEN_INT (offset);
1391 if (IN_RANGE_P (offset, -2048, 2047))
1395 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1396 if (IN_RANGE_P (offset, -32768, 32767))
1397 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1400 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1401 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1407 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1408 prologue and epilogue uses such expressions to access the stack. */
1410 frv_frame_mem (mode, base, offset)
1411 enum machine_mode mode;
1415 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1417 frv_frame_offset_rtx (offset)));
1420 /* Generate a frame-related expression:
1422 (set REG (mem (plus (sp) (const_int OFFSET)))).
1424 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1425 instructions. Marking the expressions as frame-related is superfluous if
1426 the note contains just a single set. But if the note contains a PARALLEL
1427 or SEQUENCE that has several sets, each set must be individually marked
1428 as frame-related. */
1430 frv_dwarf_store (reg, offset)
1434 rtx set = gen_rtx_SET (VOIDmode,
1435 gen_rtx_MEM (GET_MODE (reg),
1436 plus_constant (stack_pointer_rtx,
1439 RTX_FRAME_RELATED_P (set) = 1;
1443 /* Emit a frame-related instruction whose pattern is PATTERN. The
1444 instruction is the last in a sequence that cumulatively performs the
1445 operation described by DWARF_PATTERN. The instruction is marked as
1446 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1449 frv_frame_insn (pattern, dwarf_pattern)
1453 rtx insn = emit_insn (pattern);
1454 RTX_FRAME_RELATED_P (insn) = 1;
1455 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1460 /* Emit instructions that transfer REG to or from the memory location (sp +
1461 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1462 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1463 function to store registers and only the epilogue uses it to load them.
1465 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1466 The generated instruction will use BASE as its base register. BASE may
1467 simply be the stack pointer, but if several accesses are being made to a
1468 region far away from the stack pointer, it may be more efficient to set
1469 up a temporary instead.
1471 Store instructions will be frame-related and will be annotated with the
1472 overall effect of the store. Load instructions will be followed by a
1473 (use) to prevent later optimizations from zapping them.
1475 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1476 as a temporary in such cases. */
1478 frv_frame_access (accessor, reg, stack_offset)
1479 frv_frame_accessor_t *accessor;
1483 enum machine_mode mode = GET_MODE (reg);
1484 rtx mem = frv_frame_mem (mode,
1486 stack_offset - accessor->base_offset);
1488 if (accessor->op == FRV_LOAD)
1490 if (SPR_P (REGNO (reg)))
1492 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1493 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1494 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1497 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1498 emit_insn (gen_rtx_USE (VOIDmode, reg));
1502 if (SPR_P (REGNO (reg)))
1504 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1505 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1506 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1507 frv_dwarf_store (reg, stack_offset));
1509 else if (GET_MODE (reg) == DImode)
1511 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1512 with a separate save for each register. */
1513 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1514 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1515 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1516 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1517 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1518 gen_rtx_PARALLEL (VOIDmode,
1519 gen_rtvec (2, set1, set2)));
1522 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1523 frv_dwarf_store (reg, stack_offset));
1527 /* A function that uses frv_frame_access to transfer a group of registers to
1528 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1529 is the stack information generated by frv_stack_info, and REG_SET is the
1530 number of the register set to transfer. */
1532 frv_frame_access_multi (accessor, info, reg_set)
1533 frv_frame_accessor_t *accessor;
1537 frv_stack_regs_t *regs_info;
1540 regs_info = &info->regs[reg_set];
1541 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1542 if (info->save_p[regno])
1543 frv_frame_access (accessor,
1544 info->save_p[regno] == REG_SAVE_2WORDS
1545 ? gen_rtx_REG (DImode, regno)
1546 : gen_rtx_REG (SImode, regno),
1547 info->reg_offset[regno]);
1550 /* Save or restore callee-saved registers that are kept outside the frame
1551 header. The function saves the registers if OP is FRV_STORE and restores
1552 them if OP is FRV_LOAD. INFO is the stack information generated by
1555 frv_frame_access_standard_regs (op, info)
1556 enum frv_stack_op op;
1559 frv_frame_accessor_t accessor;
1562 accessor.base = stack_pointer_rtx;
1563 accessor.base_offset = 0;
1564 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1565 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1566 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1570 /* Called after register allocation to add any instructions needed for the
1571 prologue. Using a prologue insn is favored compared to putting all of the
1572 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1573 to intermix instructions with the saves of the caller saved registers. In
1574 some cases, it might be necessary to emit a barrier instruction as the last
1575 insn to prevent such scheduling.
1577 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1578 so that the debug info generation code can handle them properly. */
1580 frv_expand_prologue ()
1582 frv_stack_t *info = frv_stack_info ();
1583 rtx sp = stack_pointer_rtx;
1584 rtx fp = frame_pointer_rtx;
1585 frv_frame_accessor_t accessor;
1587 if (TARGET_DEBUG_STACK)
1588 frv_debug_stack (info);
1590 if (info->total_size == 0)
1593 /* We're interested in three areas of the frame here:
1595 A: the register save area
1597 C: the header after B
1599 If the frame pointer isn't used, we'll have to set up A, B and C
1600 using the stack pointer. If the frame pointer is used, we'll access
1604 B: set up using sp or a temporary (see below)
1607 We set up B using the stack pointer if the frame is small enough.
1608 Otherwise, it's more efficient to copy the old stack pointer into a
1609 temporary and use that.
1611 Note that it's important to make sure the prologue and epilogue use the
1612 same registers to access A and C, since doing otherwise will confuse
1613 the aliasing code. */
1615 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1616 isn't used, the same method will serve for C. */
1617 accessor.op = FRV_STORE;
1618 if (frame_pointer_needed && info->total_size > 2048)
1622 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1623 accessor.base_offset = info->total_size;
1624 insn = emit_insn (gen_movsi (accessor.base, sp));
1628 accessor.base = stack_pointer_rtx;
1629 accessor.base_offset = 0;
1632 /* Allocate the stack space. */
1634 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1635 rtx dwarf_offset = GEN_INT (-info->total_size);
1637 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1640 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1643 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1644 and point the new one to that location. */
1645 if (frame_pointer_needed)
1647 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1649 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1650 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1652 rtx asm_src = plus_constant (accessor.base,
1653 fp_offset - accessor.base_offset);
1654 rtx dwarf_src = plus_constant (sp, fp_offset);
1656 /* Store the old frame pointer at (sp + FP_OFFSET). */
1657 frv_frame_access (&accessor, fp, fp_offset);
1659 /* Set up the new frame pointer. */
1660 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1661 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1663 /* Access region C from the frame pointer. */
1665 accessor.base_offset = fp_offset;
1668 /* Set up region C. */
1669 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1670 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1671 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1673 /* Set up region A. */
1674 frv_frame_access_standard_regs (FRV_STORE, info);
1676 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1677 scheduler from moving loads before the stores saving the registers. */
1678 if (info->stdarg_size > 0)
1679 emit_insn (gen_blockage ());
1681 /* Set up pic register/small data register for this function. */
1682 if (flag_pic && cfun->uses_pic_offset_table)
1683 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1684 gen_rtx_REG (Pmode, LR_REGNO),
1685 gen_rtx_REG (SImode, OFFSET_REGNO)));
1689 /* Under frv, all of the work is done via frv_expand_epilogue, but
1690 this function provides a convient place to do cleanup. */
1693 frv_function_epilogue (file, size)
1694 FILE *file ATTRIBUTE_UNUSED;
1695 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
1697 frv_stack_cache = (frv_stack_t *)0;
1699 /* zap last used registers for conditional execution. */
1700 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1702 /* release the bitmap of created insns. */
1703 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1707 /* Called after register allocation to add any instructions needed for the
1708 epilogue. Using an epilogue insn is favored compared to putting all of the
1709 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1710 to intermix instructions with the saves of the caller saved registers. In
1711 some cases, it might be necessary to emit a barrier instruction as the last
1712 insn to prevent such scheduling.
1714 If SIBCALL_P is true, the final branch back to the calling function is
1715 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1716 we must not clobber any arguments used for parameter passing or any stack
1717 slots for arguments passed to the current function. */
1720 frv_expand_epilogue (sibcall_p)
1723 frv_stack_t *info = frv_stack_info ();
1724 rtx fp = frame_pointer_rtx;
1725 rtx sp = stack_pointer_rtx;
1729 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1731 /* Restore the stack pointer to its original value if alloca or the like
1733 if (! current_function_sp_is_unchanging)
1734 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1736 /* Restore the callee-saved registers that were used in this function. */
1737 frv_frame_access_standard_regs (FRV_LOAD, info);
1739 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1740 no return instruction should be emitted. */
1743 else if (info->save_p[LR_REGNO])
1748 /* Use the same method to access the link register's slot as we did in
1749 the prologue. In other words, use the frame pointer if available,
1750 otherwise use the stack pointer.
1752 LR_OFFSET is the offset of the link register's slot from the start
1753 of the frame and MEM is a memory rtx for it. */
1754 lr_offset = info->reg_offset[LR_REGNO];
1755 if (frame_pointer_needed)
1756 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1758 mem = frv_frame_mem (Pmode, sp, lr_offset);
1760 /* Load the old link register into a GPR. */
1761 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1762 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1765 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1767 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1768 the load is preserved. */
1769 if (frame_pointer_needed)
1771 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1772 emit_insn (gen_rtx_USE (VOIDmode, fp));
1775 /* Deallocate the stack frame. */
1776 if (info->total_size != 0)
1778 rtx offset = frv_frame_offset_rtx (info->total_size);
1779 emit_insn (gen_stack_adjust (sp, sp, offset));
1782 /* If this function uses eh_return, add the final stack adjustment now. */
1783 if (current_function_calls_eh_return)
1784 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1787 emit_jump_insn (gen_epilogue_return (return_addr));
1791 /* A C compound statement that outputs the assembler code for a thunk function,
1792 used to implement C++ virtual function calls with multiple inheritance. The
1793 thunk acts as a wrapper around a virtual function, adjusting the implicit
1794 object parameter before handing control off to the real function.
1796 First, emit code to add the integer DELTA to the location that contains the
1797 incoming first argument. Assume that this argument contains a pointer, and
1798 is the one used to pass the `this' pointer in C++. This is the incoming
1799 argument *before* the function prologue, e.g. `%o0' on a sparc. The
1800 addition must preserve the values of all other incoming arguments.
1802 After the addition, emit code to jump to FUNCTION, which is a
1803 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
1804 the return address. Hence returning from FUNCTION will return to whoever
1805 called the current `thunk'.
1807 The effect must be as if FUNCTION had been called directly with the adjusted
1808 first argument. This macro is responsible for emitting all of the code for
1809 a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
1812 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
1813 extracted from it.) It might possibly be useful on some targets, but
1816 If you do not define this macro, the target-independent code in the C++
1817 frontend will generate a less efficient heavyweight thunk that calls
1818 FUNCTION instead of jumping to it. The generic approach does not support
1822 frv_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
1824 tree thunk_fndecl ATTRIBUTE_UNUSED;
1825 HOST_WIDE_INT delta;
1826 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
1829 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1830 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1831 const char *name_jmp = reg_names[JUMP_REGNO];
1832 const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1834 /* Do the add using an addi if possible */
1835 if (IN_RANGE_P (delta, -2048, 2047))
1836 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1839 const char *const name_add = reg_names[TEMP_REGNO];
1840 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1841 parallel, delta, name_add);
1842 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1844 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1849 fprintf (file, "\tsethi%s #hi(", parallel);
1850 assemble_name (file, name_func);
1851 fprintf (file, "),%s\n", name_jmp);
1853 fprintf (file, "\tsetlo #lo(");
1854 assemble_name (file, name_func);
1855 fprintf (file, "),%s\n", name_jmp);
1859 /* Use JUMP_REGNO as a temporary PIC register. */
1860 const char *name_lr = reg_names[LR_REGNO];
1861 const char *name_gppic = name_jmp;
1862 const char *name_tmp = reg_names[TEMP_REGNO];
1864 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
1865 fprintf (file, "\tcall 1f\n");
1866 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
1867 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
1868 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
1869 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
1870 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
1872 fprintf (file, "\tsethi%s #gprelhi(", parallel);
1873 assemble_name (file, name_func);
1874 fprintf (file, "),%s\n", name_tmp);
1876 fprintf (file, "\tsetlo #gprello(");
1877 assemble_name (file, name_func);
1878 fprintf (file, "),%s\n", name_tmp);
1880 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
1883 /* Jump to the function address */
1884 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
1888 /* A C expression which is nonzero if a function must have and use a frame
1889 pointer. This expression is evaluated in the reload pass. If its value is
1890 nonzero the function will have a frame pointer.
1892 The expression can in principle examine the current function and decide
1893 according to the facts, but on most machines the constant 0 or the constant
1894 1 suffices. Use 0 when the machine allows code to be generated with no
1895 frame pointer, and doing so saves some time or space. Use 1 when there is
1896 no possible advantage to avoiding a frame pointer.
1898 In certain cases, the compiler does not know how to produce valid code
1899 without a frame pointer. The compiler recognizes those cases and
1900 automatically gives the function a frame pointer regardless of what
1901 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1903 In a function that does not require a frame pointer, the frame pointer
1904 register can be allocated for ordinary usage, unless you mark it as a fixed
1905 register. See `FIXED_REGISTERS' for more information. */
1907 /* On frv, create a frame whenever we need to create stack */
1910 frv_frame_pointer_required ()
1912 if (! current_function_is_leaf)
1915 if (get_frame_size () != 0)
1921 if (!current_function_sp_is_unchanging)
1924 if (flag_pic && cfun->uses_pic_offset_table)
1930 if (cfun->machine->frame_needed)
1937 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1938 initial difference between the specified pair of registers. This macro must
1939 be defined if `ELIMINABLE_REGS' is defined. */
1941 /* See frv_stack_info for more details on the frv stack frame. */
1944 frv_initial_elimination_offset (from, to)
1948 frv_stack_t *info = frv_stack_info ();
1951 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
1952 ret = info->total_size - info->pretend_size;
1954 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
1955 ret = - info->reg_offset[FRAME_POINTER_REGNUM];
1957 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
1958 ret = (info->total_size
1959 - info->reg_offset[FRAME_POINTER_REGNUM]
1960 - info->pretend_size);
1965 if (TARGET_DEBUG_STACK)
1966 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
1967 reg_names [from], reg_names[to], ret);
1973 /* This macro offers an alternative to using `__builtin_saveregs' and defining
1974 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1975 arguments into the stack so that all the arguments appear to have been
1976 passed consecutively on the stack. Once this is done, you can use the
1977 standard implementation of varargs that works for machines that pass all
1978 their arguments on the stack.
1980 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
1981 the values that obtain after processing of the named arguments. The
1982 arguments MODE and TYPE describe the last named argument--its machine mode
1983 and its data type as a tree node.
1985 The macro implementation should do two things: first, push onto the stack
1986 all the argument registers *not* used for the named arguments, and second,
1987 store the size of the data thus pushed into the `int'-valued variable whose
1988 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
1989 store here will serve as additional offset for setting up the stack frame.
1991 Because you must generate code to push the anonymous arguments at compile
1992 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
1993 useful on machines that have just a single category of argument register and
1994 use it uniformly for all data types.
1996 If the argument SECOND_TIME is nonzero, it means that the arguments of the
1997 function are being analyzed for the second time. This happens for an inline
1998 function, which is not actually compiled until the end of the source file.
1999 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2003 frv_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2004 CUMULATIVE_ARGS *cum;
2005 enum machine_mode mode;
2006 tree type ATTRIBUTE_UNUSED;
2010 if (TARGET_DEBUG_ARG)
2012 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2013 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2017 /* If defined, is a C expression that produces the machine-specific code for a
2018 call to `__builtin_saveregs'. This code will be moved to the very beginning
2019 of the function, before any parameter access are made. The return value of
2020 this function should be an RTX that contains the value to use as the return
2021 of `__builtin_saveregs'.
2023 If this macro is not defined, the compiler will output an ordinary call to
2024 the library function `__builtin_saveregs'. */
2027 frv_expand_builtin_saveregs ()
2029 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2031 if (TARGET_DEBUG_ARG)
2032 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2035 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2039 /* Expand __builtin_va_start to do the va_start macro. */
2042 frv_expand_builtin_va_start (valist, nextarg)
2047 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2049 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2050 GEN_INT (UNITS_PER_WORD * num));
2052 if (TARGET_DEBUG_ARG)
2054 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2055 cfun->args_info, num);
2057 debug_rtx (nextarg);
2060 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2061 make_tree (ptr_type_node, nextarg));
2062 TREE_SIDE_EFFECTS (t) = 1;
2064 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2068 /* Expand __builtin_va_arg to do the va_arg macro. */
2071 frv_expand_builtin_va_arg(valist, type)
2079 if (TARGET_DEBUG_ARG)
2081 fprintf (stderr, "va_arg:\n");
2085 if (! AGGREGATE_TYPE_P (type))
2086 return std_expand_builtin_va_arg (valist, type);
2088 addr = std_expand_builtin_va_arg (valist, ptr_type_node);
2089 mem = gen_rtx_MEM (Pmode, addr);
2090 reg = gen_reg_rtx (Pmode);
2092 set_mem_alias_set (mem, get_varargs_alias_set ());
2093 emit_move_insn (reg, mem);
2099 /* Expand a block move operation, and return 1 if successful. Return 0
2100 if we should let the compiler generate normal code.
2102 operands[0] is the destination
2103 operands[1] is the source
2104 operands[2] is the length
2105 operands[3] is the alignment */
2107 /* Maximum number of loads to do before doing the stores */
2108 #ifndef MAX_MOVE_REG
2109 #define MAX_MOVE_REG 4
2112 /* Maximum number of total loads to do. */
2113 #ifndef TOTAL_MOVE_REG
2114 #define TOTAL_MOVE_REG 8
2118 frv_expand_block_move (operands)
2121 rtx orig_dest = operands[0];
2122 rtx orig_src = operands[1];
2123 rtx bytes_rtx = operands[2];
2124 rtx align_rtx = operands[3];
2125 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2138 rtx stores[MAX_MOVE_REG];
2140 enum machine_mode mode;
2142 /* If this is not a fixed size move, just call memcpy */
2146 /* If this is not a fixed size alignment, abort */
2147 if (GET_CODE (align_rtx) != CONST_INT)
2150 align = INTVAL (align_rtx);
2152 /* Anything to move? */
2153 bytes = INTVAL (bytes_rtx);
2157 /* Don't support real large moves. */
2158 if (bytes > TOTAL_MOVE_REG*align)
2161 /* Move the address into scratch registers. */
2162 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2163 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2165 num_reg = offset = 0;
2166 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2168 /* Calculate the correct offset for src/dest */
2172 dest_addr = dest_reg;
2176 src_addr = plus_constant (src_reg, offset);
2177 dest_addr = plus_constant (dest_reg, offset);
2180 /* Generate the appropriate load and store, saving the stores
2182 if (bytes >= 4 && align >= 4)
2184 else if (bytes >= 2 && align >= 2)
2189 move_bytes = GET_MODE_SIZE (mode);
2190 tmp_reg = gen_reg_rtx (mode);
2191 src_mem = change_address (orig_src, mode, src_addr);
2192 dest_mem = change_address (orig_dest, mode, dest_addr);
2193 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2194 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2196 if (num_reg >= MAX_MOVE_REG)
2198 for (i = 0; i < num_reg; i++)
2199 emit_insn (stores[i]);
2204 for (i = 0; i < num_reg; i++)
2205 emit_insn (stores[i]);
2211 /* Expand a block clear operation, and return 1 if successful. Return 0
2212 if we should let the compiler generate normal code.
2214 operands[0] is the destination
2215 operands[1] is the length
2216 operands[2] is the alignment */
2219 frv_expand_block_clear (operands)
2222 rtx orig_dest = operands[0];
2223 rtx bytes_rtx = operands[1];
2224 rtx align_rtx = operands[2];
2225 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2234 enum machine_mode mode;
2236 /* If this is not a fixed size move, just call memcpy */
2240 /* If this is not a fixed size alignment, abort */
2241 if (GET_CODE (align_rtx) != CONST_INT)
2244 align = INTVAL (align_rtx);
2246 /* Anything to move? */
2247 bytes = INTVAL (bytes_rtx);
2251 /* Don't support real large clears. */
2252 if (bytes > TOTAL_MOVE_REG*align)
2255 /* Move the address into a scratch register. */
2256 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2258 num_reg = offset = 0;
2259 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2261 /* Calculate the correct offset for src/dest */
2262 dest_addr = ((offset == 0)
2264 : plus_constant (dest_reg, offset));
2266 /* Generate the appropriate store of gr0 */
2267 if (bytes >= 4 && align >= 4)
2269 else if (bytes >= 2 && align >= 2)
2274 clear_bytes = GET_MODE_SIZE (mode);
2275 dest_mem = change_address (orig_dest, mode, dest_addr);
2276 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2283 /* The following variable is used to output modifiers of assembler
2284 code of the current output insn.. */
2286 static rtx *frv_insn_operands;
2288 /* The following function is used to add assembler insn code suffix .p
2289 if it is necessary. */
2292 frv_asm_output_opcode (f, ptr)
2298 if (! PACKING_FLAG_USED_P())
2301 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2304 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2305 || (*ptr >= 'A' && *ptr <= 'Z')))
2307 int letter = *ptr++;
2310 frv_print_operand (f, frv_insn_operands [c], letter);
2311 while ((c = *ptr) >= '0' && c <= '9')
2318 if (!frv_insn_packing_flag)
2324 /* The following function sets up the packing bit for the current
2325 output insn. Remember that the function is not called for asm
2329 frv_final_prescan_insn (insn, opvec, noperands)
2332 int noperands ATTRIBUTE_UNUSED;
2334 if (! PACKING_FLAG_USED_P())
2340 frv_insn_operands = opvec;
2342 /* Look for the next printable instruction. frv_pack_insns () has set
2343 things up so that any printable instruction will have TImode if it
2344 starts a new packet and VOIDmode if it should be packed with the
2345 previous instruction.
2347 Printable instructions will be asm_operands or match one of the .md
2348 patterns. Since asm instructions cannot be packed -- and will
2349 therefore have TImode -- this loop terminates on any recognizable
2350 instruction, and on any unrecognizable instruction with TImode. */
2351 for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
2355 else if (!INSN_P (insn))
2357 else if (GET_MODE (insn) == TImode || INSN_CODE (insn) != -1)
2361 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2362 be packed with this one. Set it to TRUE otherwise. If the next
2363 instruction is an asm insntruction, this statement will set the
2364 flag to TRUE, and that value will still hold when the asm operands
2365 themselves are printed. */
2366 frv_insn_packing_flag = ! (insn && INSN_P (insn)
2367 && GET_MODE (insn) != TImode);
2372 /* A C expression whose value is RTL representing the address in a stack frame
2373 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2374 an RTL expression for the address of the stack frame itself.
2376 If you don't define this macro, the default is to return the value of
2377 FRAMEADDR--that is, the stack frame address is also the address of the stack
2378 word that points to the previous frame. */
2380 /* The default is correct, but we need to make sure the frame gets created. */
2382 frv_dynamic_chain_address (frame)
2385 cfun->machine->frame_needed = 1;
2390 /* A C expression whose value is RTL representing the value of the return
2391 address for the frame COUNT steps up from the current frame, after the
2392 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2393 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2396 The value of the expression must always be the correct address when COUNT is
2397 zero, but may be `NULL_RTX' if there is not way to determine the return
2398 address of other frames. */
2401 frv_return_addr_rtx (count, frame)
2402 int count ATTRIBUTE_UNUSED;
2405 cfun->machine->frame_needed = 1;
2406 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2409 /* Given a memory reference MEMREF, interpret the referenced memory as
2410 an array of MODE values, and return a reference to the element
2411 specified by INDEX. Assume that any pre-modification implicit in
2412 MEMREF has already happened.
2414 MEMREF must be a legitimate operand for modes larger than SImode.
2415 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2416 this function cannot handle. */
2418 frv_index_memory (memref, mode, index)
2420 enum machine_mode mode;
2423 rtx base = XEXP (memref, 0);
2424 if (GET_CODE (base) == PRE_MODIFY)
2425 base = XEXP (base, 0);
2426 return change_address (memref, mode,
2427 plus_constant (base, index * GET_MODE_SIZE (mode)));
2431 /* Print a memory address as an operand to reference that memory location. */
2433 frv_print_operand_address (stream, x)
2437 if (GET_CODE (x) == MEM)
2440 switch (GET_CODE (x))
2443 fputs (reg_names [ REGNO (x)], stream);
2447 fprintf (stream, "%ld", (long) INTVAL (x));
2451 assemble_name (stream, XSTR (x, 0));
2456 output_addr_const (stream, x);
2463 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2468 frv_print_operand_memory_reference_reg (stream, x)
2472 int regno = true_regnum (x);
2474 fputs (reg_names[regno], stream);
2476 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2479 /* Print a memory reference suitable for the ld/st instructions. */
2482 frv_print_operand_memory_reference (stream, x, addr_offset)
2490 switch (GET_CODE (x))
2497 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2499 x1 = XEXP (XEXP (x, 1), 1);
2509 if (GET_CODE (x0) == CONST_INT)
2517 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2526 else if (GET_CODE (x1) != CONST_INT)
2527 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2530 fputs ("@(", stream);
2532 fputs (reg_names[GPR_R0], stream);
2533 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2534 frv_print_operand_memory_reference_reg (stream, x0);
2536 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2538 fputs (",", stream);
2540 fputs (reg_names [GPR_R0], stream);
2544 switch (GET_CODE (x1))
2548 frv_print_operand_memory_reference_reg (stream, x1);
2552 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2556 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2557 && SYMBOL_REF_SMALL_P (x1))
2559 fputs ("#gprel12(", stream);
2560 assemble_name (stream, XSTR (x1, 0));
2561 fputs (")", stream);
2564 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2568 if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG
2569 && const_small_data_p (x1))
2571 fputs ("#gprel12(", stream);
2572 assemble_name (stream, XSTR (XEXP (XEXP (x1, 0), 0), 0));
2573 fprintf (stream, "+"HOST_WIDE_INT_PRINT_DEC")",
2574 INTVAL (XEXP (XEXP (x1, 0), 1)));
2577 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2581 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2585 fputs (")", stream);
2589 /* Return 2 for likely branches and 0 for non-likely branches */
2591 #define FRV_JUMP_LIKELY 2
2592 #define FRV_JUMP_NOT_LIKELY 0
2595 frv_print_operand_jump_hint (insn)
2601 HOST_WIDE_INT prob = -1;
2602 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2604 if (GET_CODE (insn) != JUMP_INSN)
2607 /* Assume any non-conditional jump is likely. */
2608 if (! any_condjump_p (insn))
2609 ret = FRV_JUMP_LIKELY;
2613 labelref = condjump_label (insn);
2616 rtx label = XEXP (labelref, 0);
2617 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2622 note = find_reg_note (insn, REG_BR_PROB, 0);
2624 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2628 prob = INTVAL (XEXP (note, 0));
2629 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2631 : FRV_JUMP_NOT_LIKELY);
2643 case UNKNOWN: direction = "unknown jump direction"; break;
2644 case BACKWARD: direction = "jump backward"; break;
2645 case FORWARD: direction = "jump forward"; break;
2649 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2650 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2651 (long)INSN_UID (insn), direction, (long)prob,
2652 (long)REG_BR_PROB_BASE, ret);
2660 /* Print an operand to an assembler instruction.
2662 `%' followed by a letter and a digit says to output an operand in an
2663 alternate fashion. Four letters have standard, built-in meanings described
2664 below. The machine description macro `PRINT_OPERAND' can define additional
2665 letters with nonstandard meanings.
2667 `%cDIGIT' can be used to substitute an operand that is a constant value
2668 without the syntax that normally indicates an immediate operand.
2670 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2673 `%aDIGIT' can be used to substitute an operand as if it were a memory
2674 reference, with the actual operand treated as the address. This may be
2675 useful when outputting a "load address" instruction, because often the
2676 assembler syntax for such an instruction requires you to write the operand
2677 as if it were a memory reference.
2679 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2681 `%=' outputs a number which is unique to each instruction in the entire
2682 compilation. This is useful for making local labels to be referred to more
2683 than once in a single template that generates multiple assembler
2686 `%' followed by a punctuation character specifies a substitution that does
2687 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2688 assembler code. Other nonstandard cases can be defined in the
2689 `PRINT_OPERAND' macro. You must also define which punctuation characters
2690 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2693 frv_print_operand (file, x, code)
2698 HOST_WIDE_INT value;
2701 if (code != 0 && !isalpha (code))
2704 else if (GET_CODE (x) == CONST_INT)
2707 else if (GET_CODE (x) == CONST_DOUBLE)
2709 if (GET_MODE (x) == SFmode)
2714 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2715 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2719 else if (GET_MODE (x) == VOIDmode)
2720 value = CONST_DOUBLE_LOW (x);
2723 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2734 fputs (reg_names[GPR_R0], file);
2738 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2742 /* Output small data area base register (gr16). */
2743 fputs (reg_names[SDA_BASE_REG], file);
2747 /* Output pic register (gr17). */
2748 fputs (reg_names[PIC_REGNO], file);
2752 /* Output the temporary integer CCR register */
2753 fputs (reg_names[ICR_TEMP], file);
2757 /* Output the temporary integer CC register */
2758 fputs (reg_names[ICC_TEMP], file);
2761 /* case 'a': print an address */
2764 /* Print appropriate test for integer branch false operation */
2765 switch (GET_CODE (x))
2768 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
2770 case EQ: fputs ("ne", file); break;
2771 case NE: fputs ("eq", file); break;
2772 case LT: fputs ("ge", file); break;
2773 case LE: fputs ("gt", file); break;
2774 case GT: fputs ("le", file); break;
2775 case GE: fputs ("lt", file); break;
2776 case LTU: fputs ("nc", file); break;
2777 case LEU: fputs ("hi", file); break;
2778 case GTU: fputs ("ls", file); break;
2779 case GEU: fputs ("c", file); break;
2783 /* case 'c': print a constant without the constant prefix. If
2784 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2787 /* Print appropriate test for integer branch true operation */
2788 switch (GET_CODE (x))
2791 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
2793 case EQ: fputs ("eq", file); break;
2794 case NE: fputs ("ne", file); break;
2795 case LT: fputs ("lt", file); break;
2796 case LE: fputs ("le", file); break;
2797 case GT: fputs ("gt", file); break;
2798 case GE: fputs ("ge", file); break;
2799 case LTU: fputs ("c", file); break;
2800 case LEU: fputs ("ls", file); break;
2801 case GTU: fputs ("hi", file); break;
2802 case GEU: fputs ("nc", file); break;
2807 /* Print 1 for a NE and 0 for an EQ to give the final argument
2808 for a conditional instruction. */
2809 if (GET_CODE (x) == NE)
2812 else if (GET_CODE (x) == EQ)
2816 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2820 /* Print appropriate test for floating point branch false operation */
2821 switch (GET_CODE (x))
2824 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2826 case EQ: fputs ("ne", file); break;
2827 case NE: fputs ("eq", file); break;
2828 case LT: fputs ("uge", file); break;
2829 case LE: fputs ("ug", file); break;
2830 case GT: fputs ("ule", file); break;
2831 case GE: fputs ("ul", file); break;
2836 /* Print appropriate test for floating point branch true operation */
2837 switch (GET_CODE (x))
2840 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2842 case EQ: fputs ("eq", file); break;
2843 case NE: fputs ("ne", file); break;
2844 case LT: fputs ("lt", file); break;
2845 case LE: fputs ("le", file); break;
2846 case GT: fputs ("gt", file); break;
2847 case GE: fputs ("ge", file); break;
2852 /* Print 'i' if the operand is a constant, or is a memory reference that
2854 if (GET_CODE (x) == MEM)
2855 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2856 ? XEXP (XEXP (x, 0), 1)
2859 switch (GET_CODE (x))
2873 /* For jump instructions, print 'i' if the operand is a constant or
2874 is an expression that adds a constant */
2875 if (GET_CODE (x) == CONST_INT)
2880 if (GET_CODE (x) == CONST_INT
2881 || (GET_CODE (x) == PLUS
2882 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2883 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2889 /* Print the lower register of a double word register pair */
2890 if (GET_CODE (x) == REG)
2891 fputs (reg_names[ REGNO (x)+1 ], file);
2893 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2896 /* case 'l': print a LABEL_REF */
2900 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2901 for the second word of double memory operations. */
2902 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2903 switch (GET_CODE (x))
2906 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2909 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2917 frv_print_operand_memory_reference (file, x, offset);
2923 /* Print the opcode of a command. */
2924 switch (GET_CODE (x))
2927 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2929 case PLUS: fputs ("add", file); break;
2930 case MINUS: fputs ("sub", file); break;
2931 case AND: fputs ("and", file); break;
2932 case IOR: fputs ("or", file); break;
2933 case XOR: fputs ("xor", file); break;
2934 case ASHIFT: fputs ("sll", file); break;
2935 case ASHIFTRT: fputs ("sra", file); break;
2936 case LSHIFTRT: fputs ("srl", file); break;
2940 /* case 'n': negate and print a constant int */
2943 /* Print PIC label using operand as the number. */
2944 if (GET_CODE (x) != CONST_INT)
2945 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2947 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2951 /* Print 'u' if the operand is a update load/store */
2952 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2957 /* If value is 0, print gr0, otherwise it must be a register */
2958 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2959 fputs (reg_names[GPR_R0], file);
2961 else if (GET_CODE (x) == REG)
2962 fputs (reg_names [REGNO (x)], file);
2965 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2969 /* Print constant in hex */
2970 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2972 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
2979 if (GET_CODE (x) == REG)
2980 fputs (reg_names [REGNO (x)], file);
2982 else if (GET_CODE (x) == CONST_INT
2983 || GET_CODE (x) == CONST_DOUBLE)
2984 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
2986 else if (GET_CODE (x) == MEM)
2987 frv_print_operand_address (file, XEXP (x, 0));
2989 else if (CONSTANT_ADDRESS_P (x))
2990 frv_print_operand_address (file, x);
2993 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
2998 fatal_insn ("frv_print_operand: unknown code", x);
3006 /* A C statement (sans semicolon) for initializing the variable CUM for the
3007 state at the beginning of the argument list. The variable has type
3008 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3009 of the function which will receive the args, or 0 if the args are to a
3010 compiler support library function. The value of INDIRECT is nonzero when
3011 processing an indirect call, for example a call through a function pointer.
3012 The value of INDIRECT is zero for a call to an explicitly named function, a
3013 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3014 arguments for the function being compiled.
3016 When processing a call to a compiler support library function, LIBNAME
3017 identifies which one. It is a `symbol_ref' rtx which contains the name of
3018 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3019 being processed. Thus, each time this macro is called, either LIBNAME or
3020 FNTYPE is nonzero, but never both of them at once. */
3023 frv_init_cumulative_args (cum, fntype, libname, fndecl, incoming)
3024 CUMULATIVE_ARGS *cum;
3030 *cum = FIRST_ARG_REGNUM;
3032 if (TARGET_DEBUG_ARG)
3034 fprintf (stderr, "\ninit_cumulative_args:");
3035 if (!fndecl && fntype)
3036 fputs (" indirect", stderr);
3039 fputs (" incoming", stderr);
3043 tree ret_type = TREE_TYPE (fntype);
3044 fprintf (stderr, " return=%s,",
3045 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3048 if (libname && GET_CODE (libname) == SYMBOL_REF)
3049 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3051 if (cfun->returns_struct)
3052 fprintf (stderr, " return-struct");
3054 putc ('\n', stderr);
3059 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3060 argument with the specified mode and type. If it is not defined,
3061 `PARM_BOUNDARY' is used for all arguments. */
3064 frv_function_arg_boundary (mode, type)
3065 enum machine_mode mode ATTRIBUTE_UNUSED;
3066 tree type ATTRIBUTE_UNUSED;
3068 return BITS_PER_WORD;
3072 /* A C expression that controls whether a function argument is passed in a
3073 register, and which register.
3075 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
3076 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
3077 arguments so far passed in registers; MODE, the machine mode of the argument;
3078 TYPE, the data type of the argument as a tree node or 0 if that is not known
3079 (which happens for C support library functions); and NAMED, which is 1 for an
3080 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3081 called function's prototype.
3083 The value of the expression should either be a `reg' RTX for the hard
3084 register in which to pass the argument, or zero to pass the argument on the
3087 For machines like the VAX and 68000, where normally all arguments are
3088 pushed, zero suffices as a definition.
3090 The usual way to make the ANSI library `stdarg.h' work on a machine where
3091 some arguments are usually passed in registers, is to cause nameless
3092 arguments to be passed on the stack instead. This is done by making
3093 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3095 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3096 this macro to determine if this argument is of a type that must be passed in
3097 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3098 returns nonzero for such an argument, the compiler will abort. If
3099 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3100 stack and then loaded into a register. */
3103 frv_function_arg (cum, mode, type, named, incoming)
3104 CUMULATIVE_ARGS *cum;
3105 enum machine_mode mode;
3106 tree type ATTRIBUTE_UNUSED;
3108 int incoming ATTRIBUTE_UNUSED;
3110 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3115 /* Return a marker for use in the call instruction. */
3116 if (xmode == VOIDmode)
3122 else if (arg_num <= LAST_ARG_REGNUM)
3124 ret = gen_rtx (REG, xmode, arg_num);
3125 debstr = reg_names[arg_num];
3134 if (TARGET_DEBUG_ARG)
3136 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3137 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3143 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3144 advance past an argument in the argument list. The values MODE, TYPE and
3145 NAMED describe that argument. Once this is done, the variable CUM is
3146 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3148 This macro need not do anything if the argument in question was passed on
3149 the stack. The compiler knows how to track the amount of stack space used
3150 for arguments without any special help. */
3153 frv_function_arg_advance (cum, mode, type, named)
3154 CUMULATIVE_ARGS *cum;
3155 enum machine_mode mode;
3156 tree type ATTRIBUTE_UNUSED;
3159 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3160 int bytes = GET_MODE_SIZE (xmode);
3161 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3164 *cum = arg_num + words;
3166 if (TARGET_DEBUG_ARG)
3168 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3169 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3173 /* A C expression for the number of words, at the beginning of an argument,
3174 must be put in registers. The value must be zero for arguments that are
3175 passed entirely in registers or that are entirely pushed on the stack.
3177 On some machines, certain arguments must be passed partially in registers
3178 and partially in memory. On these machines, typically the first N words of
3179 arguments are passed in registers, and the rest on the stack. If a
3180 multi-word argument (a `double' or a structure) crosses that boundary, its
3181 first few words must be passed in registers and the rest must be pushed.
3182 This macro tells the compiler when this occurs, and how many of the words
3183 should go in registers.
3185 `FUNCTION_ARG' for these arguments should return the first register to be
3186 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3187 the called function. */
3190 frv_function_arg_partial_nregs (cum, mode, type, named)
3191 CUMULATIVE_ARGS *cum;
3192 enum machine_mode mode;
3193 tree type ATTRIBUTE_UNUSED;
3194 int named ATTRIBUTE_UNUSED;
3196 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3197 int bytes = GET_MODE_SIZE (xmode);
3198 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3202 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3203 ? LAST_ARG_REGNUM - arg_num + 1
3206 if (TARGET_DEBUG_ARG && ret)
3207 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3215 /* A C expression that indicates when an argument must be passed by reference.
3216 If nonzero for an argument, a copy of that argument is made in memory and a
3217 pointer to the argument is passed instead of the argument itself. The
3218 pointer is passed in whatever way is appropriate for passing a pointer to
3221 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3222 definition of this macro might be
3223 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3224 MUST_PASS_IN_STACK (MODE, TYPE) */
3227 frv_function_arg_pass_by_reference (cum, mode, type, named)
3228 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3229 enum machine_mode mode;
3231 int named ATTRIBUTE_UNUSED;
3233 return MUST_PASS_IN_STACK (mode, type);
3236 /* If defined, a C expression that indicates when it is the called function's
3237 responsibility to make a copy of arguments passed by invisible reference.
3238 Normally, the caller makes a copy and passes the address of the copy to the
3239 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3240 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3241 the "live" value. The called function must not modify this value. If it
3242 can be determined that the value won't be modified, it need not make a copy;
3243 otherwise a copy must be made. */
3246 frv_function_arg_callee_copies (cum, mode, type, named)
3247 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3248 enum machine_mode mode ATTRIBUTE_UNUSED;
3249 tree type ATTRIBUTE_UNUSED;
3250 int named ATTRIBUTE_UNUSED;
3255 /* If defined, a C expression that indicates when it is more desirable to keep
3256 an argument passed by invisible reference as a reference, rather than
3257 copying it to a pseudo register. */
3260 frv_function_arg_keep_as_reference (cum, mode, type, named)
3261 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3262 enum machine_mode mode ATTRIBUTE_UNUSED;
3263 tree type ATTRIBUTE_UNUSED;
3264 int named ATTRIBUTE_UNUSED;
3270 /* Return true if a register is ok to use as a base or index register. */
3272 static FRV_INLINE int
3273 frv_regno_ok_for_base_p (regno, strict_p)
3281 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3283 if (regno == ARG_POINTER_REGNUM)
3286 return (regno >= FIRST_PSEUDO_REGISTER);
3290 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3291 RTX) is a legitimate memory address on the target machine for a memory
3292 operand of mode MODE.
3294 It usually pays to define several simpler macros to serve as subroutines for
3295 this one. Otherwise it may be too complicated to understand.
3297 This macro must exist in two variants: a strict variant and a non-strict
3298 one. The strict variant is used in the reload pass. It must be defined so
3299 that any pseudo-register that has not been allocated a hard register is
3300 considered a memory reference. In contexts where some kind of register is
3301 required, a pseudo-register with no hard register must be rejected.
3303 The non-strict variant is used in other passes. It must be defined to
3304 accept all pseudo-registers in every context where some kind of register is
3307 Compiler source files that want to use the strict variant of this macro
3308 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3309 conditional to define the strict variant in that case and the non-strict
3312 Subroutines to check for acceptable registers for various purposes (one for
3313 base registers, one for index registers, and so on) are typically among the
3314 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3315 subroutine macros need have two variants; the higher levels of macros may be
3316 the same whether strict or not.
3318 Normally, constant addresses which are the sum of a `symbol_ref' and an
3319 integer are stored inside a `const' RTX to mark them as constant.
3320 Therefore, there is no need to recognize such sums specifically as
3321 legitimate addresses. Normally you would simply recognize any `const' as
3324 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3325 are not marked with `const'. It assumes that a naked `plus' indicates
3326 indexing. If so, then you *must* reject such naked constant sums as
3327 illegitimate addresses, so that none of them will be given to
3328 `PRINT_OPERAND_ADDRESS'.
3330 On some machines, whether a symbolic address is legitimate depends on the
3331 section that the address refers to. On these machines, define the macro
3332 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3333 then check for it here. When you see a `const', you will have to look
3334 inside it to find the `symbol_ref' in order to determine the section.
3336 The best way to modify the name string is by adding text to the beginning,
3337 with suitable punctuation to prevent any ambiguity. Allocate the new name
3338 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3339 remove and decode the added text and output the name accordingly, and define
3340 `(* targetm.strip_name_encoding)' to access the original name string.
3342 You can check the information stored here into the `symbol_ref' in the
3343 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3344 `PRINT_OPERAND_ADDRESS'. */
3347 frv_legitimate_address_p (mode, x, strict_p, condexec_p)
3348 enum machine_mode mode;
3355 HOST_WIDE_INT value;
3358 switch (GET_CODE (x))
3365 if (GET_CODE (x) != REG)
3371 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3377 if (GET_CODE (x0) != REG
3378 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3379 || GET_CODE (x1) != PLUS
3380 || ! rtx_equal_p (x0, XEXP (x1, 0))
3381 || GET_CODE (XEXP (x1, 1)) != REG
3382 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3389 /* 12 bit immediate */
3394 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3396 /* If we can't use load/store double operations, make sure we can
3397 address the second word. */
3398 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3399 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3408 if (GET_CODE (x0) == SUBREG)
3409 x0 = SUBREG_REG (x0);
3411 if (GET_CODE (x0) != REG)
3414 regno0 = REGNO (x0);
3415 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3418 switch (GET_CODE (x1))
3424 x1 = SUBREG_REG (x1);
3425 if (GET_CODE (x1) != REG)
3431 /* Do not allow reg+reg addressing for modes > 1 word if we can't depend
3432 on having move double instructions */
3433 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3436 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3440 /* 12 bit immediate */
3445 value = INTVAL (x1);
3446 ret = IN_RANGE_P (value, -2048, 2047);
3448 /* If we can't use load/store double operations, make sure we can
3449 address the second word. */
3450 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3451 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3457 && regno0 == SDA_BASE_REG
3458 && SYMBOL_REF_SMALL_P (x1))
3463 if (!condexec_p && regno0 == SDA_BASE_REG && const_small_data_p (x1))
3471 if (TARGET_DEBUG_ADDR)
3473 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3474 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3475 (condexec_p) ? ", inside conditional code" : "");
3483 /* A C compound statement that attempts to replace X with a valid memory
3484 address for an operand of mode MODE. WIN will be a C statement label
3485 elsewhere in the code; the macro definition may use
3487 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3489 to avoid further processing if the address has become legitimate.
3491 X will always be the result of a call to `break_out_memory_refs', and OLDX
3492 will be the operand that was given to that function to produce X.
3494 The code generated by this macro should not alter the substructure of X. If
3495 it transforms X into a more legitimate form, it should assign X (which will
3496 always be a C variable) a new value.
3498 It is not necessary for this macro to come up with a legitimate address.
3499 The compiler has standard ways of doing so in all cases. In fact, it is
3500 safe for this macro to do nothing. But often a machine-dependent strategy
3501 can generate better code. */
3504 frv_legitimize_address (x, oldx, mode)
3506 rtx oldx ATTRIBUTE_UNUSED;
3507 enum machine_mode mode ATTRIBUTE_UNUSED;
3511 /* Don't try to legitimize addresses if we are not optimizing, since the
3512 address we generate is not a general operand, and will horribly mess
3513 things up when force_reg is called to try and put it in a register because
3514 we aren't optimizing. */
3516 && ((GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x))
3517 || (GET_CODE (x) == CONST && const_small_data_p (x))))
3519 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, SDA_BASE_REG), x);
3521 cfun->uses_pic_offset_table = TRUE;
3524 if (TARGET_DEBUG_ADDR && ret != NULL_RTX)
3526 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3527 GET_MODE_NAME (mode));
3534 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3535 the operand is used by a predicated instruction. */
3538 frv_legitimate_memory_operand (op, mode, condexec_p)
3540 enum machine_mode mode;
3543 return ((GET_MODE (op) == mode || mode == VOIDmode)
3544 && GET_CODE (op) == MEM
3545 && frv_legitimate_address_p (mode, XEXP (op, 0),
3546 reload_completed, condexec_p));
3550 /* Return 1 is OP is a memory operand, or will be turned into one by
3553 int frv_load_operand (op, mode)
3555 enum machine_mode mode;
3557 if (GET_MODE (op) != mode && mode != VOIDmode)
3560 if (reload_in_progress)
3563 if (GET_CODE (tmp) == SUBREG)
3564 tmp = SUBREG_REG (tmp);
3565 if (GET_CODE (tmp) == REG
3566 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3567 op = reg_equiv_memory_loc[REGNO (tmp)];
3570 return op && memory_operand (op, mode);
3574 /* Return 1 if operand is a GPR register or a FPR register. */
3576 int gpr_or_fpr_operand (op, mode)
3578 enum machine_mode mode;
3582 if (GET_MODE (op) != mode && mode != VOIDmode)
3585 if (GET_CODE (op) == SUBREG)
3587 if (GET_CODE (SUBREG_REG (op)) != REG)
3588 return register_operand (op, mode);
3590 op = SUBREG_REG (op);
3593 if (GET_CODE (op) != REG)
3597 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3603 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3605 int gpr_or_int12_operand (op, mode)
3607 enum machine_mode mode;
3609 if (GET_CODE (op) == CONST_INT)
3610 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3612 if (GET_MODE (op) != mode && mode != VOIDmode)
3615 if (GET_CODE (op) == SUBREG)
3617 if (GET_CODE (SUBREG_REG (op)) != REG)
3618 return register_operand (op, mode);
3620 op = SUBREG_REG (op);
3623 if (GET_CODE (op) != REG)
3626 return GPR_OR_PSEUDO_P (REGNO (op));
3629 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3630 signed immediate. */
3632 int gpr_fpr_or_int12_operand (op, mode)
3634 enum machine_mode mode;
3638 if (GET_CODE (op) == CONST_INT)
3639 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3641 if (GET_MODE (op) != mode && mode != VOIDmode)
3644 if (GET_CODE (op) == SUBREG)
3646 if (GET_CODE (SUBREG_REG (op)) != REG)
3647 return register_operand (op, mode);
3649 op = SUBREG_REG (op);
3652 if (GET_CODE (op) != REG)
3656 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3662 /* Return 1 if operand is a register or 6 bit signed immediate. */
3664 int fpr_or_int6_operand (op, mode)
3666 enum machine_mode mode;
3668 if (GET_CODE (op) == CONST_INT)
3669 return IN_RANGE_P (INTVAL (op), -32, 31);
3671 if (GET_MODE (op) != mode && mode != VOIDmode)
3674 if (GET_CODE (op) == SUBREG)
3676 if (GET_CODE (SUBREG_REG (op)) != REG)
3677 return register_operand (op, mode);
3679 op = SUBREG_REG (op);
3682 if (GET_CODE (op) != REG)
3685 return FPR_OR_PSEUDO_P (REGNO (op));
3688 /* Return 1 if operand is a register or 10 bit signed immediate. */
3690 int gpr_or_int10_operand (op, mode)
3692 enum machine_mode mode;
3694 if (GET_CODE (op) == CONST_INT)
3695 return IN_RANGE_P (INTVAL (op), -512, 511);
3697 if (GET_MODE (op) != mode && mode != VOIDmode)
3700 if (GET_CODE (op) == SUBREG)
3702 if (GET_CODE (SUBREG_REG (op)) != REG)
3703 return register_operand (op, mode);
3705 op = SUBREG_REG (op);
3708 if (GET_CODE (op) != REG)
3711 return GPR_OR_PSEUDO_P (REGNO (op));
3714 /* Return 1 if operand is a register or an integer immediate. */
3716 int gpr_or_int_operand (op, mode)
3718 enum machine_mode mode;
3720 if (GET_CODE (op) == CONST_INT)
3723 if (GET_MODE (op) != mode && mode != VOIDmode)
3726 if (GET_CODE (op) == SUBREG)
3728 if (GET_CODE (SUBREG_REG (op)) != REG)
3729 return register_operand (op, mode);
3731 op = SUBREG_REG (op);
3734 if (GET_CODE (op) != REG)
3737 return GPR_OR_PSEUDO_P (REGNO (op));
3740 /* Return 1 if operand is a 12 bit signed immediate. */
3742 int int12_operand (op, mode)
3744 enum machine_mode mode ATTRIBUTE_UNUSED;
3746 if (GET_CODE (op) != CONST_INT)
3749 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3752 /* Return 1 if operand is a 6 bit signed immediate. */
3754 int int6_operand (op, mode)
3756 enum machine_mode mode ATTRIBUTE_UNUSED;
3758 if (GET_CODE (op) != CONST_INT)
3761 return IN_RANGE_P (INTVAL (op), -32, 31);
3764 /* Return 1 if operand is a 5 bit signed immediate. */
3766 int int5_operand (op, mode)
3768 enum machine_mode mode ATTRIBUTE_UNUSED;
3770 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3773 /* Return 1 if operand is a 5 bit unsigned immediate. */
3775 int uint5_operand (op, mode)
3777 enum machine_mode mode ATTRIBUTE_UNUSED;
3779 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3782 /* Return 1 if operand is a 4 bit unsigned immediate. */
3784 int uint4_operand (op, mode)
3786 enum machine_mode mode ATTRIBUTE_UNUSED;
3788 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3791 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3793 int uint1_operand (op, mode)
3795 enum machine_mode mode ATTRIBUTE_UNUSED;
3797 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3800 /* Return 1 if operand is an integer constant that takes 2 instructions
3801 to load up and can be split into sethi/setlo instructions.. */
3803 int int_2word_operand (op, mode)
3805 enum machine_mode mode ATTRIBUTE_UNUSED;
3807 HOST_WIDE_INT value;
3811 switch (GET_CODE (op))
3817 return (flag_pic == 0);
3820 /* small data references are already 1 word */
3821 return (flag_pic == 0) && (! const_small_data_p (op));
3824 /* small data references are already 1 word */
3825 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
3828 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3831 if (GET_MODE (op) == SFmode)
3833 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3834 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3836 return ! IN_RANGE_P (value, -32768, 32767);
3838 else if (GET_MODE (op) == VOIDmode)
3840 value = CONST_DOUBLE_LOW (op);
3841 return ! IN_RANGE_P (value, -32768, 32767);
3849 /* Return 1 if operand is the pic address register. */
3851 pic_register_operand (op, mode)
3853 enum machine_mode mode ATTRIBUTE_UNUSED;
3858 if (GET_CODE (op) != REG)
3861 if (REGNO (op) != PIC_REGNO)
3867 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3868 that takes 3 seperate instructions to form. */
3870 int pic_symbolic_operand (op, mode)
3872 enum machine_mode mode ATTRIBUTE_UNUSED;
3877 switch (GET_CODE (op))
3886 /* small data references are already 1 word */
3887 return ! SYMBOL_REF_SMALL_P (op);
3890 /* small data references are already 1 word */
3891 return ! const_small_data_p (op);
3897 /* Return 1 if operand is the small data register. */
3899 small_data_register_operand (op, mode)
3901 enum machine_mode mode ATTRIBUTE_UNUSED;
3903 if (GET_CODE (op) != REG)
3906 if (REGNO (op) != SDA_BASE_REG)
3912 /* Return 1 if operand is a symbolic reference to a small data area static or
3915 int small_data_symbolic_operand (op, mode)
3917 enum machine_mode mode ATTRIBUTE_UNUSED;
3919 switch (GET_CODE (op))
3925 return const_small_data_p (op);
3928 return SYMBOL_REF_SMALL_P (op);
3934 /* Return 1 if operand is a 16 bit unsigned immediate */
3936 int uint16_operand (op, mode)
3938 enum machine_mode mode ATTRIBUTE_UNUSED;
3940 if (GET_CODE (op) != CONST_INT)
3943 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3946 /* Return 1 if operand is an integer constant with the bottom 16 bits clear */
3948 int upper_int16_operand (op, mode)
3950 enum machine_mode mode ATTRIBUTE_UNUSED;
3952 if (GET_CODE (op) != CONST_INT)
3955 return ((INTVAL (op) & 0xffff) == 0);
3958 /* Return true if operand is a GPR register. */
3961 integer_register_operand (op, mode)
3963 enum machine_mode mode;
3965 if (GET_MODE (op) != mode && mode != VOIDmode)
3968 if (GET_CODE (op) == SUBREG)
3970 if (GET_CODE (SUBREG_REG (op)) != REG)
3971 return register_operand (op, mode);
3973 op = SUBREG_REG (op);
3976 if (GET_CODE (op) != REG)
3979 return GPR_OR_PSEUDO_P (REGNO (op));
3982 /* Return true if operand is a GPR register. Do not allow SUBREG's
3983 here, in order to prevent a combine bug. */
3986 gpr_no_subreg_operand (op, mode)
3988 enum machine_mode mode;
3990 if (GET_MODE (op) != mode && mode != VOIDmode)
3993 if (GET_CODE (op) != REG)
3996 return GPR_OR_PSEUDO_P (REGNO (op));
3999 /* Return true if operand is a FPR register. */
4002 fpr_operand (op, mode)
4004 enum machine_mode mode;
4006 if (GET_MODE (op) != mode && mode != VOIDmode)
4009 if (GET_CODE (op) == SUBREG)
4011 if (GET_CODE (SUBREG_REG (op)) != REG)
4012 return register_operand (op, mode);
4014 op = SUBREG_REG (op);
4017 if (GET_CODE (op) != REG)
4020 return FPR_OR_PSEUDO_P (REGNO (op));
4023 /* Return true if operand is an even GPR or FPR register. */
4026 even_reg_operand (op, mode)
4028 enum machine_mode mode;
4032 if (GET_MODE (op) != mode && mode != VOIDmode)
4035 if (GET_CODE (op) == SUBREG)
4037 if (GET_CODE (SUBREG_REG (op)) != REG)
4038 return register_operand (op, mode);
4040 op = SUBREG_REG (op);
4043 if (GET_CODE (op) != REG)
4047 if (regno >= FIRST_PSEUDO_REGISTER)
4051 return (((regno - GPR_FIRST) & 1) == 0);
4054 return (((regno - FPR_FIRST) & 1) == 0);
4059 /* Return true if operand is an odd GPR register. */
4062 odd_reg_operand (op, mode)
4064 enum machine_mode mode;
4068 if (GET_MODE (op) != mode && mode != VOIDmode)
4071 if (GET_CODE (op) == SUBREG)
4073 if (GET_CODE (SUBREG_REG (op)) != REG)
4074 return register_operand (op, mode);
4076 op = SUBREG_REG (op);
4079 if (GET_CODE (op) != REG)
4083 /* assume that reload will give us an even register */
4084 if (regno >= FIRST_PSEUDO_REGISTER)
4088 return (((regno - GPR_FIRST) & 1) != 0);
4091 return (((regno - FPR_FIRST) & 1) != 0);
4096 /* Return true if operand is an even GPR register. */
4099 even_gpr_operand (op, mode)
4101 enum machine_mode mode;
4105 if (GET_MODE (op) != mode && mode != VOIDmode)
4108 if (GET_CODE (op) == SUBREG)
4110 if (GET_CODE (SUBREG_REG (op)) != REG)
4111 return register_operand (op, mode);
4113 op = SUBREG_REG (op);
4116 if (GET_CODE (op) != REG)
4120 if (regno >= FIRST_PSEUDO_REGISTER)
4123 if (! GPR_P (regno))
4126 return (((regno - GPR_FIRST) & 1) == 0);
4129 /* Return true if operand is an odd GPR register. */
4132 odd_gpr_operand (op, mode)
4134 enum machine_mode mode;
4138 if (GET_MODE (op) != mode && mode != VOIDmode)
4141 if (GET_CODE (op) == SUBREG)
4143 if (GET_CODE (SUBREG_REG (op)) != REG)
4144 return register_operand (op, mode);
4146 op = SUBREG_REG (op);
4149 if (GET_CODE (op) != REG)
4153 /* assume that reload will give us an even register */
4154 if (regno >= FIRST_PSEUDO_REGISTER)
4157 if (! GPR_P (regno))
4160 return (((regno - GPR_FIRST) & 1) != 0);
4163 /* Return true if operand is a quad aligned FPR register. */
4166 quad_fpr_operand (op, mode)
4168 enum machine_mode mode;
4172 if (GET_MODE (op) != mode && mode != VOIDmode)
4175 if (GET_CODE (op) == SUBREG)
4177 if (GET_CODE (SUBREG_REG (op)) != REG)
4178 return register_operand (op, mode);
4180 op = SUBREG_REG (op);
4183 if (GET_CODE (op) != REG)
4187 if (regno >= FIRST_PSEUDO_REGISTER)
4190 if (! FPR_P (regno))
4193 return (((regno - FPR_FIRST) & 3) == 0);
4196 /* Return true if operand is an even FPR register. */
4199 even_fpr_operand (op, mode)
4201 enum machine_mode mode;
4205 if (GET_MODE (op) != mode && mode != VOIDmode)
4208 if (GET_CODE (op) == SUBREG)
4210 if (GET_CODE (SUBREG_REG (op)) != REG)
4211 return register_operand (op, mode);
4213 op = SUBREG_REG (op);
4216 if (GET_CODE (op) != REG)
4220 if (regno >= FIRST_PSEUDO_REGISTER)
4223 if (! FPR_P (regno))
4226 return (((regno - FPR_FIRST) & 1) == 0);
4229 /* Return true if operand is an odd FPR register. */
4232 odd_fpr_operand (op, mode)
4234 enum machine_mode mode;
4238 if (GET_MODE (op) != mode && mode != VOIDmode)
4241 if (GET_CODE (op) == SUBREG)
4243 if (GET_CODE (SUBREG_REG (op)) != REG)
4244 return register_operand (op, mode);
4246 op = SUBREG_REG (op);
4249 if (GET_CODE (op) != REG)
4253 /* assume that reload will give us an even register */
4254 if (regno >= FIRST_PSEUDO_REGISTER)
4257 if (! FPR_P (regno))
4260 return (((regno - FPR_FIRST) & 1) != 0);
4263 /* Return true if operand is a 2 word memory address that can be loaded in one
4264 instruction to load or store. We assume the stack and frame pointers are
4265 suitably aligned, and variables in the small data area. FIXME -- at some we
4266 should recognize other globals and statics. We can't assume that any old
4267 pointer is aligned, given that arguments could be passed on an odd word on
4268 the stack and the address taken and passed through to another function. */
4271 dbl_memory_one_insn_operand (op, mode)
4273 enum machine_mode mode;
4281 if (GET_CODE (op) != MEM)
4284 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4287 addr = XEXP (op, 0);
4288 if (GET_CODE (addr) == REG)
4291 else if (GET_CODE (addr) == PLUS)
4293 rtx addr0 = XEXP (addr, 0);
4294 rtx addr1 = XEXP (addr, 1);
4296 if (GET_CODE (addr0) != REG)
4299 if (plus_small_data_p (addr0, addr1))
4302 if (GET_CODE (addr1) != CONST_INT)
4305 if ((INTVAL (addr1) & 7) != 0)
4314 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4320 /* Return true if operand is a 2 word memory address that needs to
4321 use two instructions to load or store. */
4324 dbl_memory_two_insn_operand (op, mode)
4326 enum machine_mode mode;
4328 if (GET_CODE (op) != MEM)
4331 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4337 return ! dbl_memory_one_insn_operand (op, mode);
4340 /* Return true if operand is something that can be an output for a move
4344 move_destination_operand (op, mode)
4346 enum machine_mode mode;
4351 switch (GET_CODE (op))
4357 if (GET_MODE (op) != mode && mode != VOIDmode)
4360 subreg = SUBREG_REG (op);
4361 code = GET_CODE (subreg);
4363 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4364 reload_completed, FALSE);
4366 return (code == REG);
4369 if (GET_MODE (op) != mode && mode != VOIDmode)
4375 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4378 return frv_legitimate_memory_operand (op, mode, FALSE);
4384 /* Return true if operand is something that can be an input for a move
4388 move_source_operand (op, mode)
4390 enum machine_mode mode;
4395 switch (GET_CODE (op))
4405 return immediate_operand (op, mode);
4408 if (GET_MODE (op) != mode && mode != VOIDmode)
4411 subreg = SUBREG_REG (op);
4412 code = GET_CODE (subreg);
4414 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4415 reload_completed, FALSE);
4417 return (code == REG);
4420 if (GET_MODE (op) != mode && mode != VOIDmode)
4426 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4429 return frv_legitimate_memory_operand (op, mode, FALSE);
4435 /* Return true if operand is something that can be an output for a conditional
4439 condexec_dest_operand (op, mode)
4441 enum machine_mode mode;
4446 switch (GET_CODE (op))
4452 if (GET_MODE (op) != mode && mode != VOIDmode)
4455 subreg = SUBREG_REG (op);
4456 code = GET_CODE (subreg);
4458 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4459 reload_completed, TRUE);
4461 return (code == REG);
4464 if (GET_MODE (op) != mode && mode != VOIDmode)
4470 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4473 return frv_legitimate_memory_operand (op, mode, TRUE);
4479 /* Return true if operand is something that can be an input for a conditional
4483 condexec_source_operand (op, mode)
4485 enum machine_mode mode;
4490 switch (GET_CODE (op))
4500 if (GET_MODE (op) != mode && mode != VOIDmode)
4503 subreg = SUBREG_REG (op);
4504 code = GET_CODE (subreg);
4506 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4507 reload_completed, TRUE);
4509 return (code == REG);
4512 if (GET_MODE (op) != mode && mode != VOIDmode)
4518 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
4521 return frv_legitimate_memory_operand (op, mode, TRUE);
4527 /* Return true if operand is a register of any flavor or a 0 of the
4528 appropriate type. */
4531 reg_or_0_operand (op, mode)
4533 enum machine_mode mode;
4535 switch (GET_CODE (op))
4542 if (GET_MODE (op) != mode && mode != VOIDmode)
4545 return register_operand (op, mode);
4555 /* Return true if operand is the link register */
4558 lr_operand (op, mode)
4560 enum machine_mode mode;
4562 if (GET_CODE (op) != REG)
4565 if (GET_MODE (op) != mode && mode != VOIDmode)
4568 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4574 /* Return true if operand is a gpr register or a valid memory operation. */
4577 gpr_or_memory_operand (op, mode)
4579 enum machine_mode mode;
4581 return (integer_register_operand (op, mode)
4582 || frv_legitimate_memory_operand (op, mode, FALSE));
4585 /* Return true if operand is a fpr register or a valid memory operation. */
4588 fpr_or_memory_operand (op, mode)
4590 enum machine_mode mode;
4592 return (fpr_operand (op, mode)
4593 || frv_legitimate_memory_operand (op, mode, FALSE));
4596 /* Return true if operand is an icc register */
4599 icc_operand (op, mode)
4601 enum machine_mode mode;
4605 if (GET_MODE (op) != mode && mode != VOIDmode)
4608 if (GET_CODE (op) != REG)
4612 return ICC_OR_PSEUDO_P (regno);
4615 /* Return true if operand is an fcc register */
4618 fcc_operand (op, mode)
4620 enum machine_mode mode;
4624 if (GET_MODE (op) != mode && mode != VOIDmode)
4627 if (GET_CODE (op) != REG)
4631 return FCC_OR_PSEUDO_P (regno);
4634 /* Return true if operand is either an fcc or icc register */
4637 cc_operand (op, mode)
4639 enum machine_mode mode;
4643 if (GET_MODE (op) != mode && mode != VOIDmode)
4646 if (GET_CODE (op) != REG)
4650 if (CC_OR_PSEUDO_P (regno))
4656 /* Return true if operand is an integer CCR register */
4659 icr_operand (op, mode)
4661 enum machine_mode mode;
4665 if (GET_MODE (op) != mode && mode != VOIDmode)
4668 if (GET_CODE (op) != REG)
4672 return ICR_OR_PSEUDO_P (regno);
4675 /* Return true if operand is an fcc register */
4678 fcr_operand (op, mode)
4680 enum machine_mode mode;
4684 if (GET_MODE (op) != mode && mode != VOIDmode)
4687 if (GET_CODE (op) != REG)
4691 return FCR_OR_PSEUDO_P (regno);
4694 /* Return true if operand is either an fcc or icc register */
4697 cr_operand (op, mode)
4699 enum machine_mode mode;
4703 if (GET_MODE (op) != mode && mode != VOIDmode)
4706 if (GET_CODE (op) != REG)
4710 if (CR_OR_PSEUDO_P (regno))
4716 /* Return true if operand is a memory reference suitable for a call. */
4719 call_operand (op, mode)
4721 enum machine_mode mode;
4723 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4726 if (GET_CODE (op) == SYMBOL_REF)
4729 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4730 never occur anyway), but prevents reload from not handling the case
4731 properly of a call through a pointer on a function that calls
4732 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4733 return gpr_or_int12_operand (op, mode);
4736 /* Return true if operator is a kind of relational operator. */
4739 relational_operator (op, mode)
4741 enum machine_mode mode;
4747 if (mode != VOIDmode && mode != GET_MODE (op))
4750 switch (GET_CODE (op))
4769 if (op1 != const0_rtx)
4773 if (GET_CODE (op0) != REG)
4776 regno = REGNO (op0);
4777 switch (GET_MODE (op0))
4784 return ICC_OR_PSEUDO_P (regno);
4787 return FCC_OR_PSEUDO_P (regno);
4790 return CR_OR_PSEUDO_P (regno);
4796 /* Return true if operator is a signed integer relational operator */
4799 signed_relational_operator (op, mode)
4801 enum machine_mode mode;
4807 if (mode != VOIDmode && mode != GET_MODE (op))
4810 switch (GET_CODE (op))
4825 if (op1 != const0_rtx)
4829 if (GET_CODE (op0) != REG)
4832 regno = REGNO (op0);
4833 if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
4836 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4842 /* Return true if operator is a signed integer relational operator */
4845 unsigned_relational_operator (op, mode)
4847 enum machine_mode mode;
4853 if (mode != VOIDmode && mode != GET_MODE (op))
4856 switch (GET_CODE (op))
4869 if (op1 != const0_rtx)
4873 if (GET_CODE (op0) != REG)
4876 regno = REGNO (op0);
4877 if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
4880 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4886 /* Return true if operator is a floating point relational operator */
4889 float_relational_operator (op, mode)
4891 enum machine_mode mode;
4897 if (mode != VOIDmode && mode != GET_MODE (op))
4900 switch (GET_CODE (op))
4919 if (op1 != const0_rtx)
4923 if (GET_CODE (op0) != REG)
4926 regno = REGNO (op0);
4927 if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
4930 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4936 /* Return true if operator is EQ/NE of a conditional execution register. */
4939 ccr_eqne_operator (op, mode)
4941 enum machine_mode mode;
4943 enum machine_mode op_mode = GET_MODE (op);
4948 if (mode != VOIDmode && op_mode != mode)
4951 switch (GET_CODE (op))
4962 if (op1 != const0_rtx)
4966 if (GET_CODE (op0) != REG)
4969 regno = REGNO (op0);
4970 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4976 /* Return true if operator is a minimum or maximum operator (both signed and
4980 minmax_operator (op, mode)
4982 enum machine_mode mode;
4984 if (mode != VOIDmode && mode != GET_MODE (op))
4987 switch (GET_CODE (op))
4999 if (! integer_register_operand (XEXP (op, 0), mode))
5002 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
5008 /* Return true if operator is an integer binary operator that can executed
5009 conditionally and takes 1 cycle. */
5012 condexec_si_binary_operator (op, mode)
5014 enum machine_mode mode;
5016 enum machine_mode op_mode = GET_MODE (op);
5018 if (mode != VOIDmode && op_mode != mode)
5021 switch (GET_CODE (op))
5038 /* Return true if operator is an integer binary operator that can be
5039 executed conditionally by a media instruction. */
5042 condexec_si_media_operator (op, mode)
5044 enum machine_mode mode;
5046 enum machine_mode op_mode = GET_MODE (op);
5048 if (mode != VOIDmode && op_mode != mode)
5051 switch (GET_CODE (op))
5063 /* Return true if operator is an integer division operator that can executed
5067 condexec_si_divide_operator (op, mode)
5069 enum machine_mode mode;
5071 enum machine_mode op_mode = GET_MODE (op);
5073 if (mode != VOIDmode && op_mode != mode)
5076 switch (GET_CODE (op))
5087 /* Return true if operator is an integer unary operator that can executed
5091 condexec_si_unary_operator (op, mode)
5093 enum machine_mode mode;
5095 enum machine_mode op_mode = GET_MODE (op);
5097 if (mode != VOIDmode && op_mode != mode)
5100 switch (GET_CODE (op))
5111 /* Return true if operator is a conversion-type expression that can be
5112 evaluated conditionally by floating-point instructions. */
5115 condexec_sf_conv_operator (op, mode)
5117 enum machine_mode mode;
5119 enum machine_mode op_mode = GET_MODE (op);
5121 if (mode != VOIDmode && op_mode != mode)
5124 switch (GET_CODE (op))
5135 /* Return true if operator is an addition or subtraction expression.
5136 Such expressions can be evaluated conditionally by floating-point
5140 condexec_sf_add_operator (op, mode)
5142 enum machine_mode mode;
5144 enum machine_mode op_mode = GET_MODE (op);
5146 if (mode != VOIDmode && op_mode != mode)
5149 switch (GET_CODE (op))
5160 /* Return true if the memory operand is one that can be conditionally
5164 condexec_memory_operand (op, mode)
5166 enum machine_mode mode;
5168 enum machine_mode op_mode = GET_MODE (op);
5171 if (mode != VOIDmode && op_mode != mode)
5186 if (GET_CODE (op) != MEM)
5189 addr = XEXP (op, 0);
5190 if (GET_CODE (addr) == ADDRESSOF)
5193 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE);
5196 /* Return true if operator is an integer binary operator that can be combined
5197 with a setcc operation. Do not allow the arithmetic operations that could
5198 potentially overflow since the FR-V sets the condition code based on the
5199 "true" value of the result, not the result after truncating to a 32-bit
5203 intop_compare_operator (op, mode)
5205 enum machine_mode mode;
5207 enum machine_mode op_mode = GET_MODE (op);
5209 if (mode != VOIDmode && op_mode != mode)
5212 switch (GET_CODE (op))
5225 if (! integer_register_operand (XEXP (op, 0), SImode))
5228 if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
5234 /* Return true if operator is an integer binary operator that can be combined
5235 with a setcc operation inside of a conditional execution. */
5238 condexec_intop_cmp_operator (op, mode)
5240 enum machine_mode mode;
5242 enum machine_mode op_mode = GET_MODE (op);
5244 if (mode != VOIDmode && op_mode != mode)
5247 switch (GET_CODE (op))
5260 if (! integer_register_operand (XEXP (op, 0), SImode))
5263 if (! integer_register_operand (XEXP (op, 1), SImode))
5269 /* Return 1 if operand is a valid ACC register number */
5272 acc_operand (op, mode)
5274 enum machine_mode mode;
5278 if (GET_MODE (op) != mode && mode != VOIDmode)
5281 if (GET_CODE (op) == SUBREG)
5283 if (GET_CODE (SUBREG_REG (op)) != REG)
5284 return register_operand (op, mode);
5286 op = SUBREG_REG (op);
5289 if (GET_CODE (op) != REG)
5293 return ACC_OR_PSEUDO_P (regno);
5296 /* Return 1 if operand is a valid even ACC register number */
5299 even_acc_operand (op, mode)
5301 enum machine_mode mode;
5305 if (GET_MODE (op) != mode && mode != VOIDmode)
5308 if (GET_CODE (op) == SUBREG)
5310 if (GET_CODE (SUBREG_REG (op)) != REG)
5311 return register_operand (op, mode);
5313 op = SUBREG_REG (op);
5316 if (GET_CODE (op) != REG)
5320 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0);
5323 /* Return 1 if operand is zero or four */
5326 quad_acc_operand (op, mode)
5328 enum machine_mode mode;
5332 if (GET_MODE (op) != mode && mode != VOIDmode)
5335 if (GET_CODE (op) == SUBREG)
5337 if (GET_CODE (SUBREG_REG (op)) != REG)
5338 return register_operand (op, mode);
5340 op = SUBREG_REG (op);
5343 if (GET_CODE (op) != REG)
5347 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0);
5350 /* Return 1 if operand is a valid ACCG register number */
5353 accg_operand (op, mode)
5355 enum machine_mode mode;
5357 if (GET_MODE (op) != mode && mode != VOIDmode)
5360 if (GET_CODE (op) == SUBREG)
5362 if (GET_CODE (SUBREG_REG (op)) != REG)
5363 return register_operand (op, mode);
5365 op = SUBREG_REG (op);
5368 if (GET_CODE (op) != REG)
5371 return ACCG_OR_PSEUDO_P (REGNO (op));
5375 /* Return true if the bare return instruction can be used outside of the
5376 epilog code. For frv, we only do it if there was no stack allocation. */
5383 if (!reload_completed)
5386 info = frv_stack_info ();
5387 return (info->total_size == 0);
5391 /* Emit code to handle a MOVSI, adding in the small data register or pic
5392 register if needed to load up addresses. Return TRUE if the appropriate
5393 instructions are emitted. */
5396 frv_emit_movsi (dest, src)
5400 int base_regno = -1;
5402 if (!reload_in_progress
5403 && !reload_completed
5404 && !register_operand (dest, SImode)
5405 && (!reg_or_0_operand (src, SImode)
5406 /* Virtual registers will almost always be replaced by an
5407 add instruction, so expose this to CSE by copying to
5408 an intermediate register */
5409 || (GET_CODE (src) == REG
5410 && IN_RANGE_P (REGNO (src),
5411 FIRST_VIRTUAL_REGISTER,
5412 LAST_VIRTUAL_REGISTER))))
5414 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5418 /* Explicitly add in the PIC or small data register if needed. */
5419 switch (GET_CODE (src))
5426 base_regno = PIC_REGNO;
5431 if (const_small_data_p (src))
5432 base_regno = SDA_BASE_REG;
5435 base_regno = PIC_REGNO;
5440 if (SYMBOL_REF_SMALL_P (src))
5441 base_regno = SDA_BASE_REG;
5444 base_regno = PIC_REGNO;
5449 if (base_regno >= 0)
5451 emit_insn (gen_rtx_SET (VOIDmode, dest,
5452 gen_rtx_PLUS (Pmode,
5453 gen_rtx_REG (Pmode, base_regno),
5456 if (base_regno == PIC_REGNO)
5457 cfun->uses_pic_offset_table = TRUE;
5466 /* Return a string to output a single word move. */
5469 output_move_single (operands, insn)
5473 rtx dest = operands[0];
5474 rtx src = operands[1];
5476 if (GET_CODE (dest) == REG)
5478 int dest_regno = REGNO (dest);
5479 enum machine_mode mode = GET_MODE (dest);
5481 if (GPR_P (dest_regno))
5483 if (GET_CODE (src) == REG)
5485 /* gpr <- some sort of register */
5486 int src_regno = REGNO (src);
5488 if (GPR_P (src_regno))
5489 return "mov %1, %0";
5491 else if (FPR_P (src_regno))
5492 return "movfg %1, %0";
5494 else if (SPR_P (src_regno))
5495 return "movsg %1, %0";
5498 else if (GET_CODE (src) == MEM)
5507 return "ldsb%I1%U1 %M1,%0";
5510 return "ldsh%I1%U1 %M1,%0";
5514 return "ld%I1%U1 %M1, %0";
5518 else if (GET_CODE (src) == CONST_INT
5519 || GET_CODE (src) == CONST_DOUBLE)
5521 /* gpr <- integer/floating constant */
5522 HOST_WIDE_INT value;
5524 if (GET_CODE (src) == CONST_INT)
5525 value = INTVAL (src);
5527 else if (mode == SFmode)
5532 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5533 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5538 value = CONST_DOUBLE_LOW (src);
5540 if (IN_RANGE_P (value, -32768, 32767))
5541 return "setlos %1, %0";
5546 else if (GET_CODE (src) == SYMBOL_REF
5547 || GET_CODE (src) == LABEL_REF
5548 || GET_CODE (src) == CONST)
5550 /* Silently fix up instances where the small data pointer is not
5551 used in the address. */
5552 if (small_data_symbolic_operand (src, GET_MODE (src)))
5553 return "addi %@, #gprel12(%1), %0";
5559 else if (FPR_P (dest_regno))
5561 if (GET_CODE (src) == REG)
5563 /* fpr <- some sort of register */
5564 int src_regno = REGNO (src);
5566 if (GPR_P (src_regno))
5567 return "movgf %1, %0";
5569 else if (FPR_P (src_regno))
5571 if (TARGET_HARD_FLOAT)
5572 return "fmovs %1, %0";
5574 return "mor %1, %1, %0";
5578 else if (GET_CODE (src) == MEM)
5587 return "ldbf%I1%U1 %M1,%0";
5590 return "ldhf%I1%U1 %M1,%0";
5594 return "ldf%I1%U1 %M1, %0";
5598 else if (ZERO_P (src))
5599 return "movgf %., %0";
5602 else if (SPR_P (dest_regno))
5604 if (GET_CODE (src) == REG)
5606 /* spr <- some sort of register */
5607 int src_regno = REGNO (src);
5609 if (GPR_P (src_regno))
5610 return "movgs %1, %0";
5615 else if (GET_CODE (dest) == MEM)
5617 if (GET_CODE (src) == REG)
5619 int src_regno = REGNO (src);
5620 enum machine_mode mode = GET_MODE (dest);
5622 if (GPR_P (src_regno))
5630 return "stb%I0%U0 %1, %M0";
5633 return "sth%I0%U0 %1, %M0";
5637 return "st%I0%U0 %1, %M0";
5641 else if (FPR_P (src_regno))
5649 return "stbf%I0%U0 %1, %M0";
5652 return "sthf%I0%U0 %1, %M0";
5656 return "stf%I0%U0 %1, %M0";
5661 else if (ZERO_P (src))
5663 switch (GET_MODE (dest))
5669 return "stb%I0%U0 %., %M0";
5672 return "sth%I0%U0 %., %M0";
5676 return "st%I0%U0 %., %M0";
5681 fatal_insn ("Bad output_move_single operand", insn);
5686 /* Return a string to output a double word move. */
5689 output_move_double (operands, insn)
5693 rtx dest = operands[0];
5694 rtx src = operands[1];
5695 enum machine_mode mode = GET_MODE (dest);
5697 if (GET_CODE (dest) == REG)
5699 int dest_regno = REGNO (dest);
5701 if (GPR_P (dest_regno))
5703 if (GET_CODE (src) == REG)
5705 /* gpr <- some sort of register */
5706 int src_regno = REGNO (src);
5708 if (GPR_P (src_regno))
5711 else if (FPR_P (src_regno))
5713 if (((dest_regno - GPR_FIRST) & 1) == 0
5714 && ((src_regno - FPR_FIRST) & 1) == 0)
5715 return "movfgd %1, %0";
5721 else if (GET_CODE (src) == MEM)
5724 if (dbl_memory_one_insn_operand (src, mode))
5725 return "ldd%I1%U1 %M1, %0";
5730 else if (GET_CODE (src) == CONST_INT
5731 || GET_CODE (src) == CONST_DOUBLE)
5735 else if (FPR_P (dest_regno))
5737 if (GET_CODE (src) == REG)
5739 /* fpr <- some sort of register */
5740 int src_regno = REGNO (src);
5742 if (GPR_P (src_regno))
5744 if (((dest_regno - FPR_FIRST) & 1) == 0
5745 && ((src_regno - GPR_FIRST) & 1) == 0)
5746 return "movgfd %1, %0";
5751 else if (FPR_P (src_regno))
5754 && ((dest_regno - FPR_FIRST) & 1) == 0
5755 && ((src_regno - FPR_FIRST) & 1) == 0)
5756 return "fmovd %1, %0";
5762 else if (GET_CODE (src) == MEM)
5765 if (dbl_memory_one_insn_operand (src, mode))
5766 return "lddf%I1%U1 %M1, %0";
5771 else if (ZERO_P (src))
5776 else if (GET_CODE (dest) == MEM)
5778 if (GET_CODE (src) == REG)
5780 int src_regno = REGNO (src);
5782 if (GPR_P (src_regno))
5784 if (((src_regno - GPR_FIRST) & 1) == 0
5785 && dbl_memory_one_insn_operand (dest, mode))
5786 return "std%I0%U0 %1, %M0";
5791 if (FPR_P (src_regno))
5793 if (((src_regno - FPR_FIRST) & 1) == 0
5794 && dbl_memory_one_insn_operand (dest, mode))
5795 return "stdf%I0%U0 %1, %M0";
5801 else if (ZERO_P (src))
5803 if (dbl_memory_one_insn_operand (dest, mode))
5804 return "std%I0%U0 %., %M0";
5810 fatal_insn ("Bad output_move_double operand", insn);
5815 /* Return a string to output a single word conditional move.
5816 Operand0 -- EQ/NE of ccr register and 0
5817 Operand1 -- CCR register
5818 Operand2 -- destination
5819 Operand3 -- source */
5822 output_condmove_single (operands, insn)
5826 rtx dest = operands[2];
5827 rtx src = operands[3];
5829 if (GET_CODE (dest) == REG)
5831 int dest_regno = REGNO (dest);
5832 enum machine_mode mode = GET_MODE (dest);
5834 if (GPR_P (dest_regno))
5836 if (GET_CODE (src) == REG)
5838 /* gpr <- some sort of register */
5839 int src_regno = REGNO (src);
5841 if (GPR_P (src_regno))
5842 return "cmov %z3, %2, %1, %e0";
5844 else if (FPR_P (src_regno))
5845 return "cmovfg %3, %2, %1, %e0";
5848 else if (GET_CODE (src) == MEM)
5857 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5860 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5864 return "cld%I3%U3 %M3, %2, %1, %e0";
5868 else if (ZERO_P (src))
5869 return "cmov %., %2, %1, %e0";
5872 else if (FPR_P (dest_regno))
5874 if (GET_CODE (src) == REG)
5876 /* fpr <- some sort of register */
5877 int src_regno = REGNO (src);
5879 if (GPR_P (src_regno))
5880 return "cmovgf %3, %2, %1, %e0";
5882 else if (FPR_P (src_regno))
5884 if (TARGET_HARD_FLOAT)
5885 return "cfmovs %3,%2,%1,%e0";
5887 return "cmor %3, %3, %2, %1, %e0";
5891 else if (GET_CODE (src) == MEM)
5894 if (mode == SImode || mode == SFmode)
5895 return "cldf%I3%U3 %M3, %2, %1, %e0";
5898 else if (ZERO_P (src))
5899 return "cmovgf %., %2, %1, %e0";
5903 else if (GET_CODE (dest) == MEM)
5905 if (GET_CODE (src) == REG)
5907 int src_regno = REGNO (src);
5908 enum machine_mode mode = GET_MODE (dest);
5910 if (GPR_P (src_regno))
5918 return "cstb%I2%U2 %3, %M2, %1, %e0";
5921 return "csth%I2%U2 %3, %M2, %1, %e0";
5925 return "cst%I2%U2 %3, %M2, %1, %e0";
5929 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
5930 return "cstf%I2%U2 %3, %M2, %1, %e0";
5933 else if (ZERO_P (src))
5935 enum machine_mode mode = GET_MODE (dest);
5942 return "cstb%I2%U2 %., %M2, %1, %e0";
5945 return "csth%I2%U2 %., %M2, %1, %e0";
5949 return "cst%I2%U2 %., %M2, %1, %e0";
5954 fatal_insn ("Bad output_condmove_single operand", insn);
5959 /* Emit the appropriate code to do a comparison, returning the register the
5960 comparison was done it. */
5963 frv_emit_comparison (test, op0, op1)
5968 enum machine_mode cc_mode;
5971 /* Floating point doesn't have comparison against a constant */
5972 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
5973 op1 = force_reg (GET_MODE (op0), op1);
5975 /* Possibly disable using anything but a fixed register in order to work
5976 around cse moving comparisons past function calls. */
5977 cc_mode = SELECT_CC_MODE (test, op0, op1);
5978 cc_reg = ((TARGET_ALLOC_CC)
5979 ? gen_reg_rtx (cc_mode)
5980 : gen_rtx_REG (cc_mode,
5981 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
5983 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5984 gen_rtx_COMPARE (cc_mode, op0, op1)));
5990 /* Emit code for a conditional branch. The comparison operands were previously
5991 stored in frv_compare_op0 and frv_compare_op1.
5993 XXX: I originally wanted to add a clobber of a CCR register to use in
5994 conditional execution, but that confuses the rest of the compiler. */
5997 frv_emit_cond_branch (test, label)
6004 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6005 enum machine_mode cc_mode = GET_MODE (cc_reg);
6007 /* Branches generate:
6009 (if_then_else (<test>, <cc_reg>, (const_int 0))
6010 (label_ref <branch_label>)
6012 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6013 test_rtx = gen_rtx (test, cc_mode, cc_reg, const0_rtx);
6014 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6015 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6020 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6021 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6024 frv_emit_scc (test, target)
6032 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6034 /* SCC instructions generate:
6035 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6036 (clobber (<ccr_reg>))]) */
6037 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6038 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6040 cr_reg = ((TARGET_ALLOC_CC)
6041 ? gen_reg_rtx (CC_CCRmode)
6042 : gen_rtx_REG (CC_CCRmode,
6043 ((GET_MODE (cc_reg) == CC_FPmode)
6047 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6048 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6053 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6054 the seperate insns. */
6057 frv_split_scc (dest, test, cc_reg, cr_reg, value)
6062 HOST_WIDE_INT value;
6068 /* Set the appropriate CCR bit. */
6069 emit_insn (gen_rtx_SET (VOIDmode,
6071 gen_rtx_fmt_ee (GET_CODE (test),
6076 /* Move the value into the destination. */
6077 emit_move_insn (dest, GEN_INT (value));
6079 /* Move 0 into the destination if the test failed */
6080 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6081 gen_rtx_EQ (GET_MODE (cr_reg),
6084 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6086 /* Finish up, return sequence. */
6093 /* Emit the code for a conditional move, return TRUE if we could do the
6097 frv_emit_cond_move (dest, test_rtx, src1, src2)
6108 enum rtx_code test = GET_CODE (test_rtx);
6109 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6110 enum machine_mode cc_mode = GET_MODE (cc_reg);
6112 /* Conditional move instructions generate:
6113 (parallel [(set <target>
6114 (if_then_else (<test> <cc_reg> (const_int 0))
6117 (clobber (<ccr_reg>))]) */
6119 /* Handle various cases of conditional move involving two constants. */
6120 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6122 HOST_WIDE_INT value1 = INTVAL (src1);
6123 HOST_WIDE_INT value2 = INTVAL (src2);
6125 /* having 0 as one of the constants can be done by loading the other
6126 constant, and optionally moving in gr0. */
6127 if (value1 == 0 || value2 == 0)
6130 /* If the first value is within an addi range and also the difference
6131 between the two fits in an addi's range, load up the difference, then
6132 conditionally move in 0, and then unconditionally add the first
6134 else if (IN_RANGE_P (value1, -2048, 2047)
6135 && IN_RANGE_P (value2 - value1, -2048, 2047))
6138 /* If neither condition holds, just force the constant into a
6142 src1 = force_reg (GET_MODE (dest), src1);
6143 src2 = force_reg (GET_MODE (dest), src2);
6147 /* If one value is a register, insure the other value is either 0 or a
6151 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6152 src1 = force_reg (GET_MODE (dest), src1);
6154 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6155 src2 = force_reg (GET_MODE (dest), src2);
6158 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6159 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6161 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6163 cr_reg = ((TARGET_ALLOC_CC)
6164 ? gen_reg_rtx (CC_CCRmode)
6165 : gen_rtx_REG (CC_CCRmode,
6166 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6168 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6169 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6174 /* Split a conditonal move into constituent parts, returning a SEQUENCE
6175 containing all of the insns. */
6178 frv_split_cond_move (operands)
6181 rtx dest = operands[0];
6182 rtx test = operands[1];
6183 rtx cc_reg = operands[2];
6184 rtx src1 = operands[3];
6185 rtx src2 = operands[4];
6186 rtx cr_reg = operands[5];
6188 enum machine_mode cr_mode = GET_MODE (cr_reg);
6192 /* Set the appropriate CCR bit. */
6193 emit_insn (gen_rtx_SET (VOIDmode,
6195 gen_rtx_fmt_ee (GET_CODE (test),
6200 /* Handle various cases of conditional move involving two constants. */
6201 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6203 HOST_WIDE_INT value1 = INTVAL (src1);
6204 HOST_WIDE_INT value2 = INTVAL (src2);
6206 /* having 0 as one of the constants can be done by loading the other
6207 constant, and optionally moving in gr0. */
6210 emit_move_insn (dest, src2);
6211 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6212 gen_rtx_NE (cr_mode, cr_reg,
6214 gen_rtx_SET (VOIDmode, dest, src1)));
6217 else if (value2 == 0)
6219 emit_move_insn (dest, src1);
6220 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6221 gen_rtx_EQ (cr_mode, cr_reg,
6223 gen_rtx_SET (VOIDmode, dest, src2)));
6226 /* If the first value is within an addi range and also the difference
6227 between the two fits in an addi's range, load up the difference, then
6228 conditionally move in 0, and then unconditionally add the first
6230 else if (IN_RANGE_P (value1, -2048, 2047)
6231 && IN_RANGE_P (value2 - value1, -2048, 2047))
6233 rtx dest_si = ((GET_MODE (dest) == SImode)
6235 : gen_rtx_SUBREG (SImode, dest, 0));
6237 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6238 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6239 gen_rtx_NE (cr_mode, cr_reg,
6241 gen_rtx_SET (VOIDmode, dest_si,
6243 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6251 /* Emit the conditional move for the test being true if needed. */
6252 if (! rtx_equal_p (dest, src1))
6253 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6254 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6255 gen_rtx_SET (VOIDmode, dest, src1)));
6257 /* Emit the conditional move for the test being false if needed. */
6258 if (! rtx_equal_p (dest, src2))
6259 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6260 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6261 gen_rtx_SET (VOIDmode, dest, src2)));
6264 /* Finish up, return sequence. */
6271 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6272 memory location that is not known to be dword-aligned. */
6274 frv_split_double_load (dest, source)
6278 int regno = REGNO (dest);
6279 rtx dest1 = gen_highpart (SImode, dest);
6280 rtx dest2 = gen_lowpart (SImode, dest);
6281 rtx address = XEXP (source, 0);
6283 /* If the address is pre-modified, load the lower-numbered register
6284 first, then load the other register using an integer offset from
6285 the modified base register. This order should always be safe,
6286 since the pre-modification cannot affect the same registers as the
6289 The situation for other loads is more complicated. Loading one
6290 of the registers could affect the value of ADDRESS, so we must
6291 be careful which order we do them in. */
6292 if (GET_CODE (address) == PRE_MODIFY
6293 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6295 /* It is safe to load the lower-numbered register first. */
6296 emit_move_insn (dest1, change_address (source, SImode, NULL));
6297 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6301 /* ADDRESS is not pre-modified and the address depends on the
6302 lower-numbered register. Load the higher-numbered register
6304 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6305 emit_move_insn (dest1, change_address (source, SImode, NULL));
6309 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6310 and SOURCE is either a double register or the constant zero. */
6312 frv_split_double_store (dest, source)
6316 rtx dest1 = change_address (dest, SImode, NULL);
6317 rtx dest2 = frv_index_memory (dest, SImode, 1);
6318 if (ZERO_P (source))
6320 emit_move_insn (dest1, CONST0_RTX (SImode));
6321 emit_move_insn (dest2, CONST0_RTX (SImode));
6325 emit_move_insn (dest1, gen_highpart (SImode, source));
6326 emit_move_insn (dest2, gen_lowpart (SImode, source));
6331 /* Split a min/max operation returning a SEQUENCE containing all of the
6335 frv_split_minmax (operands)
6338 rtx dest = operands[0];
6339 rtx minmax = operands[1];
6340 rtx src1 = operands[2];
6341 rtx src2 = operands[3];
6342 rtx cc_reg = operands[4];
6343 rtx cr_reg = operands[5];
6345 enum rtx_code test_code;
6346 enum machine_mode cr_mode = GET_MODE (cr_reg);
6350 /* Figure out which test to use */
6351 switch (GET_CODE (minmax))
6356 case SMIN: test_code = LT; break;
6357 case SMAX: test_code = GT; break;
6358 case UMIN: test_code = LTU; break;
6359 case UMAX: test_code = GTU; break;
6362 /* Issue the compare instruction. */
6363 emit_insn (gen_rtx_SET (VOIDmode,
6365 gen_rtx_COMPARE (GET_MODE (cc_reg),
6368 /* Set the appropriate CCR bit. */
6369 emit_insn (gen_rtx_SET (VOIDmode,
6371 gen_rtx_fmt_ee (test_code,
6376 /* If are taking the min/max of a nonzero constant, load that first, and
6377 then do a conditional move of the other value. */
6378 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6380 if (rtx_equal_p (dest, src1))
6383 emit_move_insn (dest, src2);
6384 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6385 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6386 gen_rtx_SET (VOIDmode, dest, src1)));
6389 /* Otherwise, do each half of the move. */
6392 /* Emit the conditional move for the test being true if needed. */
6393 if (! rtx_equal_p (dest, src1))
6394 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6395 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6396 gen_rtx_SET (VOIDmode, dest, src1)));
6398 /* Emit the conditional move for the test being false if needed. */
6399 if (! rtx_equal_p (dest, src2))
6400 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6401 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6402 gen_rtx_SET (VOIDmode, dest, src2)));
6405 /* Finish up, return sequence. */
6412 /* Split an integer abs operation returning a SEQUENCE containing all of the
6416 frv_split_abs (operands)
6419 rtx dest = operands[0];
6420 rtx src = operands[1];
6421 rtx cc_reg = operands[2];
6422 rtx cr_reg = operands[3];
6427 /* Issue the compare < 0 instruction. */
6428 emit_insn (gen_rtx_SET (VOIDmode,
6430 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6432 /* Set the appropriate CCR bit. */
6433 emit_insn (gen_rtx_SET (VOIDmode,
6435 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6437 /* Emit the conditional negate if the value is negative */
6438 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6439 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6440 gen_negsi2 (dest, src)));
6442 /* Emit the conditional move for the test being false if needed. */
6443 if (! rtx_equal_p (dest, src))
6444 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6445 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6446 gen_rtx_SET (VOIDmode, dest, src)));
6448 /* Finish up, return sequence. */
6455 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6456 register used in an insn. */
6459 frv_clear_registers_used (ptr, data)
6463 if (GET_CODE (*ptr) == REG)
6465 int regno = REGNO (*ptr);
6466 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6468 if (regno < FIRST_PSEUDO_REGISTER)
6470 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6472 while (regno < reg_max)
6474 CLEAR_HARD_REG_BIT (*p_regs, regno);
6484 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6486 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6487 initialize the static storage. */
6489 frv_ifcvt_init_extra_fields (ce_info)
6490 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
6492 frv_ifcvt.added_insns_list = NULL_RTX;
6493 frv_ifcvt.cur_scratch_regs = 0;
6494 frv_ifcvt.num_nested_cond_exec = 0;
6495 frv_ifcvt.cr_reg = NULL_RTX;
6496 frv_ifcvt.nested_cc_reg = NULL_RTX;
6497 frv_ifcvt.extra_int_cr = NULL_RTX;
6498 frv_ifcvt.extra_fp_cr = NULL_RTX;
6499 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6503 /* Internal function to add a potenial insn to the list of insns to be inserted
6504 if the conditional execution conversion is successful. */
6507 frv_ifcvt_add_insn (pattern, insn, before_p)
6512 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6514 link->jump = before_p; /* mark to add this before or after insn */
6515 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6516 frv_ifcvt.added_insns_list);
6518 if (TARGET_DEBUG_COND_EXEC)
6521 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6522 (before_p) ? "before" : "after",
6523 (int)INSN_UID (insn));
6525 debug_rtx (pattern);
6530 /* A C expression to modify the code described by the conditional if
6531 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6532 FALSE_EXPR for converting if-then and if-then-else code to conditional
6533 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6534 tests cannot be converted. */
6537 frv_ifcvt_modify_tests (ce_info, p_true, p_false)
6538 ce_if_block_t *ce_info;
6542 basic_block test_bb = ce_info->test_bb; /* test basic block */
6543 basic_block then_bb = ce_info->then_bb; /* THEN */
6544 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6545 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6546 rtx true_expr = *p_true;
6550 enum machine_mode mode = GET_MODE (true_expr);
6554 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6556 rtx sub_cond_exec_reg;
6558 enum rtx_code code_true;
6559 enum rtx_code code_false;
6560 enum reg_class cc_class;
6561 enum reg_class cr_class;
6565 /* Make sure we are only dealing with hard registers. Also honor the
6566 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6568 if (!reload_completed || TARGET_NO_COND_EXEC
6569 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6572 /* Figure out which registers we can allocate for our own purposes. Only
6573 consider registers that are not preserved across function calls and are
6574 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6575 if we did not need to use them in reloading other registers. */
6576 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6577 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6578 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6579 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6580 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6582 /* If this is a nested IF, we need to discover whether the CC registers that
6583 are set/used inside of the block are used anywhere else. If not, we can
6584 change them to be the CC register that is paired with the CR register that
6585 controls the outermost IF block. */
6586 if (ce_info->pass > 1)
6588 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6589 for (j = CC_FIRST; j <= CC_LAST; j++)
6590 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6592 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6595 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6598 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6601 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6605 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6606 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6608 frv_ifcvt.added_insns_list = NULL_RTX;
6609 frv_ifcvt.cur_scratch_regs = 0;
6611 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6612 * sizeof (basic_block));
6618 /* Remove anything live at the beginning of the join block from being
6619 available for allocation. */
6620 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno,
6622 if (regno < FIRST_PSEUDO_REGISTER)
6623 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6627 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6629 if (ce_info->num_multiple_test_blocks)
6631 basic_block multiple_test_bb = ce_info->last_test_bb;
6633 while (multiple_test_bb != test_bb)
6635 bb[num_bb++] = multiple_test_bb;
6636 multiple_test_bb = multiple_test_bb->pred->src;
6640 /* Add in the THEN and ELSE blocks to be scanned. */
6641 bb[num_bb++] = then_bb;
6643 bb[num_bb++] = else_bb;
6645 sub_cond_exec_reg = NULL_RTX;
6646 frv_ifcvt.num_nested_cond_exec = 0;
6648 /* Scan all of the blocks for registers that must not be allocated. */
6649 for (j = 0; j < num_bb; j++)
6651 rtx last_insn = bb[j]->end;
6652 rtx insn = bb[j]->head;
6656 fprintf (rtl_dump_file, "Scanning %s block %d, start %d, end %d\n",
6657 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6659 (int) INSN_UID (bb[j]->head),
6660 (int) INSN_UID (bb[j]->end));
6662 /* Anything live at the beginning of the block is obviously unavailable
6664 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno,
6666 if (regno < FIRST_PSEUDO_REGISTER)
6667 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6670 /* loop through the insns in the block. */
6673 /* Mark any new registers that are created as being unavailable for
6674 allocation. Also see if the CC register used in nested IFs can be
6680 int skip_nested_if = FALSE;
6682 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6683 (void *)&tmp_reg->regs);
6685 pattern = PATTERN (insn);
6686 if (GET_CODE (pattern) == COND_EXEC)
6688 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6690 if (reg != sub_cond_exec_reg)
6692 sub_cond_exec_reg = reg;
6693 frv_ifcvt.num_nested_cond_exec++;
6697 set = single_set_pattern (pattern);
6700 rtx dest = SET_DEST (set);
6701 rtx src = SET_SRC (set);
6703 if (GET_CODE (dest) == REG)
6705 int regno = REGNO (dest);
6706 enum rtx_code src_code = GET_CODE (src);
6708 if (CC_P (regno) && src_code == COMPARE)
6709 skip_nested_if = TRUE;
6711 else if (CR_P (regno)
6712 && (src_code == IF_THEN_ELSE
6713 || GET_RTX_CLASS (src_code) == '<'))
6714 skip_nested_if = TRUE;
6718 if (! skip_nested_if)
6719 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6720 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6723 if (insn == last_insn)
6726 insn = NEXT_INSN (insn);
6730 /* If this is a nested if, rewrite the CC registers that are available to
6731 include the ones that can be rewritten, to increase the chance of being
6732 able to allocate a paired CC/CR register combination. */
6733 if (ce_info->pass > 1)
6735 for (j = CC_FIRST; j <= CC_LAST; j++)
6736 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6737 SET_HARD_REG_BIT (tmp_reg->regs, j);
6739 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6745 fprintf (rtl_dump_file, "Available GPRs: ");
6747 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6748 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6750 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6751 if (++num_gprs > GPR_TEMP_NUM+2)
6755 fprintf (rtl_dump_file, "%s\nAvailable CRs: ",
6756 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6758 for (j = CR_FIRST; j <= CR_LAST; j++)
6759 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6760 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6762 fputs ("\n", rtl_dump_file);
6764 if (ce_info->pass > 1)
6766 fprintf (rtl_dump_file, "Modifiable CCs: ");
6767 for (j = CC_FIRST; j <= CC_LAST; j++)
6768 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6769 fprintf (rtl_dump_file, " %d [%s]", j, reg_names[j]);
6771 fprintf (rtl_dump_file, "\n%d nested COND_EXEC statements\n",
6772 frv_ifcvt.num_nested_cond_exec);
6776 /* Allocate the appropriate temporary condition code register. Try to
6777 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6778 that conditional cmp's can be done. */
6779 if (mode == CCmode || mode == CC_UNSmode)
6781 cr_class = ICR_REGS;
6782 cc_class = ICC_REGS;
6783 cc_first = ICC_FIRST;
6786 else if (mode == CC_FPmode)
6788 cr_class = FCR_REGS;
6789 cc_class = FCC_REGS;
6790 cc_first = FCC_FIRST;
6795 cc_first = cc_last = 0;
6796 cr_class = cc_class = NO_REGS;
6799 cc = XEXP (true_expr, 0);
6800 nested_cc = cr = NULL_RTX;
6801 if (cc_class != NO_REGS)
6803 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6804 so we can execute a csubcc/caddcc/cfcmps instruction. */
6807 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6809 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6811 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6812 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6814 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6815 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6818 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6819 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6829 fprintf (rtl_dump_file, "Could not allocate a CR temporary register\n");
6835 fprintf (rtl_dump_file,
6836 "Will use %s for conditional execution, %s for nested comparisons\n",
6837 reg_names[ REGNO (cr)],
6838 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6840 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6841 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6842 bit being true. We don't do this for floating point, because of NaNs. */
6843 code = GET_CODE (true_expr);
6844 if (GET_MODE (cc) != CC_FPmode)
6846 code = reverse_condition (code);
6856 check_insn = gen_rtx_SET (VOIDmode, cr,
6857 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6859 /* Record the check insn to be inserted later. */
6860 frv_ifcvt_add_insn (check_insn, test_bb->end, TRUE);
6862 /* Update the tests. */
6863 frv_ifcvt.cr_reg = cr;
6864 frv_ifcvt.nested_cc_reg = nested_cc;
6865 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6866 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6869 /* Fail, don't do this conditional execution. */
6872 *p_false = NULL_RTX;
6874 fprintf (rtl_dump_file, "Disabling this conditional execution.\n");
6880 /* A C expression to modify the code described by the conditional if
6881 information CE_INFO, for the basic block BB, possibly updating the tests in
6882 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6883 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6884 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6886 /* p_true and p_false are given expressions of the form:
6888 (and (eq:CC_CCR (reg:CC_CCR)
6894 frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false)
6895 ce_if_block_t *ce_info;
6900 rtx old_true = XEXP (*p_true, 0);
6901 rtx old_false = XEXP (*p_false, 0);
6902 rtx true_expr = XEXP (*p_true, 1);
6903 rtx false_expr = XEXP (*p_false, 1);
6906 rtx cr = XEXP (old_true, 0);
6908 rtx new_cr = NULL_RTX;
6909 rtx *p_new_cr = (rtx *)0;
6913 enum reg_class cr_class;
6914 enum machine_mode mode = GET_MODE (true_expr);
6915 rtx (*logical_func)(rtx, rtx, rtx);
6917 if (TARGET_DEBUG_COND_EXEC)
6920 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6921 ce_info->and_and_p ? "&&" : "||");
6923 debug_rtx (*p_true);
6925 fputs ("\nfalse insn:\n", stderr);
6926 debug_rtx (*p_false);
6929 if (TARGET_NO_MULTI_CE)
6932 if (GET_CODE (cr) != REG)
6935 if (mode == CCmode || mode == CC_UNSmode)
6937 cr_class = ICR_REGS;
6938 p_new_cr = &frv_ifcvt.extra_int_cr;
6940 else if (mode == CC_FPmode)
6942 cr_class = FCR_REGS;
6943 p_new_cr = &frv_ifcvt.extra_fp_cr;
6948 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6949 more &&/|| tests. */
6953 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
6954 CC_CCRmode, TRUE, TRUE);
6959 if (ce_info->and_and_p)
6961 old_test = old_false;
6962 test_expr = true_expr;
6963 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
6964 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6965 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6969 old_test = old_false;
6970 test_expr = false_expr;
6971 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
6972 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6973 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6976 /* First add the andcr/andncr/orcr/orncr, which will be added after the
6977 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
6979 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), bb->end, TRUE);
6981 /* Now add the conditional check insn. */
6982 cc = XEXP (test_expr, 0);
6983 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
6984 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
6986 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
6988 /* add the new check insn to the list of check insns that need to be
6990 frv_ifcvt_add_insn (check_insn, bb->end, TRUE);
6992 if (TARGET_DEBUG_COND_EXEC)
6994 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
6997 debug_rtx (*p_true);
6999 fputs ("\nfalse insn:\n", stderr);
7000 debug_rtx (*p_false);
7006 *p_true = *p_false = NULL_RTX;
7008 /* If we allocated a CR register, release it. */
7011 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7012 *p_new_cr = NULL_RTX;
7015 if (TARGET_DEBUG_COND_EXEC)
7016 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7022 /* Return a register which will be loaded with a value if an IF block is
7023 converted to conditional execution. This is used to rewrite instructions
7024 that use constants to ones that just use registers. */
7027 frv_ifcvt_load_value (value, insn)
7029 rtx insn ATTRIBUTE_UNUSED;
7031 int num_alloc = frv_ifcvt.cur_scratch_regs;
7035 /* We know gr0 == 0, so replace any errant uses. */
7036 if (value == const0_rtx)
7037 return gen_rtx_REG (SImode, GPR_FIRST);
7039 /* First search all registers currently loaded to see if we have an
7040 applicable constant. */
7041 if (CONSTANT_P (value)
7042 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7044 for (i = 0; i < num_alloc; i++)
7046 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7047 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7051 /* Have we exhausted the number of registers available? */
7052 if (num_alloc >= GPR_TEMP_NUM)
7055 fprintf (rtl_dump_file, "Too many temporary registers allocated\n");
7060 /* Allocate the new register. */
7061 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7065 fputs ("Could not find a scratch register\n", rtl_dump_file);
7070 frv_ifcvt.cur_scratch_regs++;
7071 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7075 if (GET_CODE (value) == CONST_INT)
7076 fprintf (rtl_dump_file, "Register %s will hold %ld\n",
7077 reg_names[ REGNO (reg)], (long)INTVAL (value));
7079 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7080 fprintf (rtl_dump_file, "Register %s will hold LR\n",
7081 reg_names[ REGNO (reg)]);
7084 fprintf (rtl_dump_file, "Register %s will hold a saved value\n",
7085 reg_names[ REGNO (reg)]);
7092 /* Update a MEM used in conditional code that might contain an offset to put
7093 the offset into a scratch register, so that the conditional load/store
7094 operations can be used. This function returns the original pointer if the
7095 MEM is valid to use in conditional code, NULL if we can't load up the offset
7096 into a temporary register, or the new MEM if we were successful. */
7099 frv_ifcvt_rewrite_mem (mem, mode, insn)
7101 enum machine_mode mode;
7104 rtx addr = XEXP (mem, 0);
7106 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE))
7108 if (GET_CODE (addr) == PLUS)
7110 rtx addr_op0 = XEXP (addr, 0);
7111 rtx addr_op1 = XEXP (addr, 1);
7113 if (plus_small_data_p (addr_op0, addr_op1))
7114 addr = frv_ifcvt_load_value (addr, insn);
7116 else if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7118 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7122 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7129 else if (CONSTANT_P (addr))
7130 addr = frv_ifcvt_load_value (addr, insn);
7135 if (addr == NULL_RTX)
7138 else if (XEXP (mem, 0) != addr)
7139 return change_address (mem, mode, addr);
7146 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7147 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7150 single_set_pattern (pattern)
7156 if (GET_CODE (pattern) == COND_EXEC)
7157 pattern = COND_EXEC_CODE (pattern);
7159 if (GET_CODE (pattern) == SET)
7162 else if (GET_CODE (pattern) == PARALLEL)
7164 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7166 rtx sub = XVECEXP (pattern, 0, i);
7168 switch (GET_CODE (sub))
7192 /* A C expression to modify the code described by the conditional if
7193 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7194 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7195 insn cannot be converted to be executed conditionally. */
7198 frv_ifcvt_modify_insn (ce_info, pattern, insn)
7199 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7203 rtx orig_ce_pattern = pattern;
7209 if (GET_CODE (pattern) != COND_EXEC)
7212 test = COND_EXEC_TEST (pattern);
7213 if (GET_CODE (test) == AND)
7215 rtx cr = frv_ifcvt.cr_reg;
7218 op0 = XEXP (test, 0);
7219 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7222 op1 = XEXP (test, 1);
7223 test_reg = XEXP (op1, 0);
7224 if (GET_CODE (test_reg) != REG)
7227 /* Is this the first nested if block in this sequence? If so, generate
7228 an andcr or andncr. */
7229 if (! frv_ifcvt.last_nested_if_cr)
7233 frv_ifcvt.last_nested_if_cr = test_reg;
7234 if (GET_CODE (op0) == NE)
7235 and_op = gen_andcr (test_reg, cr, test_reg);
7237 and_op = gen_andncr (test_reg, cr, test_reg);
7239 frv_ifcvt_add_insn (and_op, insn, TRUE);
7242 /* If this isn't the first statement in the nested if sequence, see if we
7243 are dealing with the same register. */
7244 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7247 COND_EXEC_TEST (pattern) = test = op1;
7250 /* If this isn't a nested if, reset state variables. */
7253 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7256 set = single_set_pattern (pattern);
7259 rtx dest = SET_DEST (set);
7260 rtx src = SET_SRC (set);
7261 enum machine_mode mode = GET_MODE (dest);
7263 /* Check for normal binary operators */
7265 && (GET_RTX_CLASS (GET_CODE (src)) == '2'
7266 || GET_RTX_CLASS (GET_CODE (src)) == 'c'))
7268 op0 = XEXP (src, 0);
7269 op1 = XEXP (src, 1);
7271 /* Special case load of small data address which looks like:
7273 if (GET_CODE (src) == PLUS && plus_small_data_p (op0, op1))
7275 src = frv_ifcvt_load_value (src, insn);
7277 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7282 else if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7284 op1 = frv_ifcvt_load_value (op1, insn);
7286 COND_EXEC_CODE (pattern)
7287 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7295 /* For multiply by a constant, we need to handle the sign extending
7296 correctly. Add a USE of the value after the multiply to prevent flow
7297 from cratering because only one register out of the two were used. */
7298 else if (mode == DImode && GET_CODE (src) == MULT)
7300 op0 = XEXP (src, 0);
7301 op1 = XEXP (src, 1);
7302 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7304 op1 = frv_ifcvt_load_value (op1, insn);
7307 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7308 COND_EXEC_CODE (pattern)
7309 = gen_rtx_SET (VOIDmode, dest,
7310 gen_rtx_MULT (DImode, op0, op1));
7316 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7319 /* If we are just loading a constant created for a nested conditional
7320 execution statement, just load the constant without any conditional
7321 execution, since we know that the constant will not interfere with any
7323 else if (frv_ifcvt.scratch_insns_bitmap
7324 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7328 else if (mode == QImode || mode == HImode || mode == SImode
7331 int changed_p = FALSE;
7333 /* Check for just loading up a constant */
7334 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7336 src = frv_ifcvt_load_value (src, insn);
7343 /* See if we need to fix up stores */
7344 if (GET_CODE (dest) == MEM)
7346 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7351 else if (new_mem != dest)
7358 /* See if we need to fix up loads */
7359 if (GET_CODE (src) == MEM)
7361 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7366 else if (new_mem != src)
7373 /* If either src or destination changed, redo SET. */
7375 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7378 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7379 rewriting the CC register to be the same as the paired CC/CR register
7381 else if (mode == CC_CCRmode && GET_RTX_CLASS (GET_CODE (src)) == '<')
7383 int regno = REGNO (XEXP (src, 0));
7386 if (ce_info->pass > 1
7387 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7388 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7390 src = gen_rtx_fmt_ee (GET_CODE (src),
7392 frv_ifcvt.nested_cc_reg,
7396 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7397 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7400 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7401 else if (ce_info->pass > 1
7402 && GET_CODE (dest) == REG
7403 && CC_P (REGNO (dest))
7404 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7405 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7407 && GET_CODE (src) == COMPARE)
7409 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7410 COND_EXEC_CODE (pattern)
7411 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7415 if (TARGET_DEBUG_COND_EXEC)
7417 rtx orig_pattern = PATTERN (insn);
7419 PATTERN (insn) = pattern;
7421 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7425 PATTERN (insn) = orig_pattern;
7431 if (TARGET_DEBUG_COND_EXEC)
7433 rtx orig_pattern = PATTERN (insn);
7435 PATTERN (insn) = orig_ce_pattern;
7437 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7441 PATTERN (insn) = orig_pattern;
7448 /* A C expression to perform any final machine dependent modifications in
7449 converting code to conditional execution in the code described by the
7450 conditional if information CE_INFO. */
7453 frv_ifcvt_modify_final (ce_info)
7454 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7458 rtx p = frv_ifcvt.added_insns_list;
7461 /* Loop inserting the check insns. The last check insn is the first test,
7462 and is the appropriate place to insert constants. */
7468 rtx check_and_insert_insns = XEXP (p, 0);
7471 check_insn = XEXP (check_and_insert_insns, 0);
7472 existing_insn = XEXP (check_and_insert_insns, 1);
7475 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7476 the existing insn, otherwise it is to be inserted AFTER. */
7477 if (check_and_insert_insns->jump)
7479 emit_insn_before (check_insn, existing_insn);
7480 check_and_insert_insns->jump = 0;
7483 emit_insn_after (check_insn, existing_insn);
7485 free_EXPR_LIST_node (check_and_insert_insns);
7486 free_EXPR_LIST_node (old_p);
7488 while (p != NULL_RTX);
7490 /* Load up any constants needed into temp gprs */
7491 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7493 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7494 if (! frv_ifcvt.scratch_insns_bitmap)
7495 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7496 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7497 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7500 frv_ifcvt.added_insns_list = NULL_RTX;
7501 frv_ifcvt.cur_scratch_regs = 0;
7505 /* A C expression to cancel any machine dependent modifications in converting
7506 code to conditional execution in the code described by the conditional if
7507 information CE_INFO. */
7510 frv_ifcvt_modify_cancel (ce_info)
7511 ce_if_block_t *ce_info ATTRIBUTE_UNUSED;
7514 rtx p = frv_ifcvt.added_insns_list;
7516 /* Loop freeing up the EXPR_LIST's allocated. */
7517 while (p != NULL_RTX)
7519 rtx check_and_jump = XEXP (p, 0);
7523 free_EXPR_LIST_node (check_and_jump);
7524 free_EXPR_LIST_node (old_p);
7527 /* Release any temporary gprs allocated. */
7528 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7529 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7531 frv_ifcvt.added_insns_list = NULL_RTX;
7532 frv_ifcvt.cur_scratch_regs = 0;
7536 /* A C expression for the size in bytes of the trampoline, as an integer.
7540 setlo #0, <static_chain>
7542 sethi #0, <static_chain>
7543 jmpl @(gr0,<jmp_reg>) */
7546 frv_trampoline_size ()
7548 return 5 /* instructions */ * 4 /* instruction size */;
7552 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7553 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7554 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7555 should be passed to the function when it is called.
7560 setlo #0, <static_chain>
7562 sethi #0, <static_chain>
7563 jmpl @(gr0,<jmp_reg>) */
7566 frv_initialize_trampoline (addr, fnaddr, static_chain)
7571 rtx sc_reg = force_reg (Pmode, static_chain);
7573 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7576 GEN_INT (frv_trampoline_size ()), SImode,
7582 /* Many machines have some registers that cannot be copied directly to or from
7583 memory or even from other types of registers. An example is the `MQ'
7584 register, which on most machines, can only be copied to or from general
7585 registers, but not memory. Some machines allow copying all registers to and
7586 from memory, but require a scratch register for stores to some memory
7587 locations (e.g., those with symbolic address on the RT, and those with
7588 certain symbolic address on the SPARC when compiling PIC). In some cases,
7589 both an intermediate and a scratch register are required.
7591 You should define these macros to indicate to the reload phase that it may
7592 need to allocate at least one register for a reload in addition to the
7593 register to contain the data. Specifically, if copying X to a register
7594 CLASS in MODE requires an intermediate register, you should define
7595 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7596 whose registers can be used as intermediate registers or scratch registers.
7598 If copying a register CLASS in MODE to X requires an intermediate or scratch
7599 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7600 largest register class required. If the requirements for input and output
7601 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7602 instead of defining both macros identically.
7604 The values returned by these macros are often `GENERAL_REGS'. Return
7605 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7606 to or from a register of CLASS in MODE without requiring a scratch register.
7607 Do not define this macro if it would always return `NO_REGS'.
7609 If a scratch register is required (either with or without an intermediate
7610 register), you should define patterns for `reload_inM' or `reload_outM', as
7611 required.. These patterns, which will normally be implemented with a
7612 `define_expand', should be similar to the `movM' patterns, except that
7613 operand 2 is the scratch register.
7615 Define constraints for the reload register and scratch register that contain
7616 a single register class. If the original reload register (whose class is
7617 CLASS) can meet the constraint given in the pattern, the value returned by
7618 these macros is used for the class of the scratch register. Otherwise, two
7619 additional reload registers are required. Their classes are obtained from
7620 the constraints in the insn pattern.
7622 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7623 either be in a hard register or in memory. Use `true_regnum' to find out;
7624 it will return -1 if the pseudo is in memory and the hard register number if
7625 it is in a register.
7627 These macros should not be used in the case where a particular class of
7628 registers can only be copied to memory and not to another class of
7629 registers. In that case, secondary reload registers are not needed and
7630 would not be helpful. Instead, a stack location must be used to perform the
7631 copy and the `movM' pattern should use memory as an intermediate storage.
7632 This case often occurs between floating-point and general registers. */
7635 frv_secondary_reload_class (class, mode, x, in_p)
7636 enum reg_class class;
7637 enum machine_mode mode ATTRIBUTE_UNUSED;
7639 int in_p ATTRIBUTE_UNUSED;
7649 /* Accumulators/Accumulator guard registers need to go through floating
7655 if (x && GET_CODE (x) == REG)
7657 int regno = REGNO (x);
7659 if (ACC_P (regno) || ACCG_P (regno))
7664 /* Nonzero constants should be loaded into an FPR through a GPR. */
7668 if (x && CONSTANT_P (x) && !ZERO_P (x))
7674 /* All of these types need gpr registers. */
7686 /* The accumulators need fpr registers */
7699 /* A C expression whose value is nonzero if pseudos that have been assigned to
7700 registers of class CLASS would likely be spilled because registers of CLASS
7701 are needed for spill registers.
7703 The default value of this macro returns 1 if CLASS has exactly one register
7704 and zero otherwise. On most machines, this default should be used. Only
7705 define this macro to some other expression if pseudo allocated by
7706 `local-alloc.c' end up in memory because their hard registers were needed
7707 for spill registers. If this macro returns nonzero for those classes, those
7708 pseudos will only be allocated by `global.c', which knows how to reallocate
7709 the pseudo to another register. If there would not be another register
7710 available for reallocation, you should not change the definition of this
7711 macro since the only effect of such a definition would be to slow down
7712 register allocation. */
7715 frv_class_likely_spilled_p (class)
7716 enum reg_class class;
7743 /* An expression for the alignment of a structure field FIELD if the
7744 alignment computed in the usual way is COMPUTED. GCC uses this
7745 value instead of the value in `BIGGEST_ALIGNMENT' or
7746 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7748 /* The definition type of the bit field data is either char, short, long or
7749 long long. The maximum bit size is the number of bits of its own type.
7751 The bit field data is assigned to a storage unit that has an adequate size
7752 for bit field data retention and is located at the smallest address.
7754 Consecutive bit field data are packed at consecutive bits having the same
7755 storage unit, with regard to the type, beginning with the MSB and continuing
7758 If a field to be assigned lies over a bit field type boundary, its
7759 assignment is completed by aligning it with a boundary suitable for the
7762 When a bit field having a bit length of 0 is declared, it is forcibly
7763 assigned to the next storage unit.
7776 &x 00000000 00000000 00000000 00000000
7779 &x+4 00000000 00000000 00000000 00000000
7782 &x+8 00000000 00000000 00000000 00000000
7785 &x+12 00000000 00000000 00000000 00000000
7791 frv_adjust_field_align (field, computed)
7795 /* C++ provides a null DECL_CONTEXT if the bit field is wider than its
7797 if (DECL_BIT_FIELD (field) && DECL_CONTEXT (field))
7799 tree parent = DECL_CONTEXT (field);
7800 tree prev = NULL_TREE;
7803 /* Loop finding the previous field to the current one */
7804 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7806 if (TREE_CODE (cur) != FIELD_DECL)
7815 /* If this isn't a :0 field and if the previous element is a bitfield
7816 also, see if the type is different, if so, we will need to align the
7817 bit-field to the next boundary */
7819 && ! DECL_PACKED (field)
7820 && ! integer_zerop (DECL_SIZE (field))
7821 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7823 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7824 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7825 computed = (prev_align > cur_align) ? prev_align : cur_align;
7833 /* A C expression that is nonzero if it is permissible to store a value of mode
7834 MODE in hard register number REGNO (or in several registers starting with
7835 that one). For a machine where all registers are equivalent, a suitable
7838 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7840 It is not necessary for this macro to check for the numbers of fixed
7841 registers, because the allocation mechanism considers them to be always
7844 On some machines, double-precision values must be kept in even/odd register
7845 pairs. The way to implement that is to define this macro to reject odd
7846 register numbers for such modes.
7848 The minimum requirement for a mode to be OK in a register is that the
7849 `movMODE' instruction pattern support moves between the register and any
7850 other hard register for which the mode is OK; and that moving a value into
7851 the register and back out not alter it.
7853 Since the same instruction used to move `SImode' will work for all narrower
7854 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7855 to distinguish between these modes, provided you define patterns `movhi',
7856 etc., to take advantage of this. This is useful because of the interaction
7857 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7858 all integer modes to be tieable.
7860 Many machines have special registers for floating point arithmetic. Often
7861 people assume that floating point machine modes are allowed only in floating
7862 point registers. This is not true. Any registers that can hold integers
7863 can safely *hold* a floating point machine mode, whether or not floating
7864 arithmetic can be done on it in those registers. Integer move instructions
7865 can be used to move the values.
7867 On some machines, though, the converse is true: fixed-point machine modes
7868 may not go in floating registers. This is true if the floating registers
7869 normalize any value stored in them, because storing a non-floating value
7870 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7871 fixed-point machine modes in floating registers. But if the floating
7872 registers do not automatically normalize, if you can store any bit pattern
7873 in one and retrieve it unchanged without a trap, then any machine mode may
7874 go in a floating register, so you can define this macro to say so.
7876 The primary significance of special floating registers is rather that they
7877 are the registers acceptable in floating point arithmetic instructions.
7878 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7879 writing the proper constraints for those instructions.
7881 On some machines, the floating registers are especially slow to access, so
7882 that it is better to store a value in a stack frame than in such a register
7883 if floating point arithmetic is not being done. As long as the floating
7884 registers are not in class `GENERAL_REGS', they will not be used unless some
7885 pattern's constraint asks for one. */
7888 frv_hard_regno_mode_ok (regno, mode)
7890 enum machine_mode mode;
7899 return ICC_P (regno) || GPR_P (regno);
7902 return CR_P (regno) || GPR_P (regno);
7905 return FCC_P (regno) || GPR_P (regno);
7911 /* Set BASE to the first register in REGNO's class. Set MASK to the
7912 bits that must be clear in (REGNO - BASE) for the register to be
7914 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7918 /* ACCGs store one byte. Two-byte quantities must start in
7919 even-numbered registers, four-byte ones in registers whose
7920 numbers are divisible by four, and so on. */
7922 mask = GET_MODE_SIZE (mode) - 1;
7926 /* The other registers store one word. */
7930 else if (FPR_P (regno))
7933 else if (ACC_P (regno))
7939 /* Anything smaller than an SI is OK in any word-sized register. */
7940 if (GET_MODE_SIZE (mode) < 4)
7943 mask = (GET_MODE_SIZE (mode) / 4) - 1;
7945 return (((regno - base) & mask) == 0);
7952 /* A C expression for the number of consecutive hard registers, starting at
7953 register number REGNO, required to hold a value of mode MODE.
7955 On a machine where all registers are exactly one word, a suitable definition
7958 #define HARD_REGNO_NREGS(REGNO, MODE) \
7959 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
7960 / UNITS_PER_WORD)) */
7962 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
7963 that we can build the appropriate instructions to properly reload the
7964 values. Also, make the byte-sized accumulator guards use one guard
7968 frv_hard_regno_nregs (regno, mode)
7970 enum machine_mode mode;
7973 return GET_MODE_SIZE (mode);
7975 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7979 /* A C expression for the maximum number of consecutive registers of
7980 class CLASS needed to hold a value of mode MODE.
7982 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
7983 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
7984 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
7986 This macro helps control the handling of multiple-word values in
7989 This declaration is required. */
7992 frv_class_max_nregs (class, mode)
7993 enum reg_class class;
7994 enum machine_mode mode;
7996 if (class == ACCG_REGS)
7997 /* An N-byte value requires N accumulator guards. */
7998 return GET_MODE_SIZE (mode);
8000 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8004 /* A C expression that is nonzero if X is a legitimate constant for an
8005 immediate operand on the target machine. You can assume that X satisfies
8006 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8007 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8010 frv_legitimate_constant_p (x)
8013 enum machine_mode mode = GET_MODE (x);
8015 /* All of the integer constants are ok */
8016 if (GET_CODE (x) != CONST_DOUBLE)
8019 /* double integer constants are ok */
8020 if (mode == VOIDmode || mode == DImode)
8023 /* 0 is always ok */
8024 if (x == CONST0_RTX (mode))
8027 /* If floating point is just emulated, allow any constant, since it will be
8028 constructed in the GPRs */
8029 if (!TARGET_HAS_FPRS)
8032 if (mode == DFmode && !TARGET_DOUBLE)
8035 /* Otherwise store the constant away and do a load. */
8039 /* A C expression for the cost of moving data from a register in class FROM to
8040 one in class TO. The classes are expressed using the enumeration values
8041 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8042 interpreted relative to that.
8044 It is not required that the cost always equal 2 when FROM is the same as TO;
8045 on some machines it is expensive to move between registers if they are not
8048 If reload sees an insn consisting of a single `set' between two hard
8049 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8050 value of 2, reload does not check to ensure that the constraints of the insn
8051 are met. Setting a cost of other than 2 will allow reload to verify that
8052 the constraints are met. You should do this if the `movM' pattern's
8053 constraints do not allow such copying. */
8055 #define HIGH_COST 40
8056 #define MEDIUM_COST 3
8060 frv_register_move_cost (from, to)
8061 enum reg_class from;
8146 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8147 use ".picptr" to generate safe relocations for PIC code. We also
8148 need a fixup entry for aligned (non-debugging) code. */
8151 frv_assemble_integer (value, size, aligned_p)
8156 if (flag_pic && size == UNITS_PER_WORD)
8158 if (GET_CODE (value) == CONST
8159 || GET_CODE (value) == SYMBOL_REF
8160 || GET_CODE (value) == LABEL_REF)
8164 static int label_num = 0;
8168 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8169 p = (* targetm.strip_name_encoding) (buf);
8171 fprintf (asm_out_file, "%s:\n", p);
8172 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8173 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8174 fprintf (asm_out_file, "\t.previous\n");
8176 assemble_integer_with_op ("\t.picptr\t", value);
8181 /* We've set the unaligned SI op to NULL, so we always have to
8182 handle the unaligned case here. */
8183 assemble_integer_with_op ("\t.4byte\t", value);
8187 return default_assemble_integer (value, size, aligned_p);
8190 /* Function to set up the backend function structure. */
8192 static struct machine_function *
8193 frv_init_machine_status ()
8195 return ggc_alloc_cleared (sizeof (struct machine_function));
8198 /* Implement TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. */
8201 frv_use_dfa_pipeline_interface (void)
8206 /* Update the register state information, to know about which registers are set
8210 frv_registers_update (x, reg_state, modified, p_num_mod, flag)
8212 unsigned char reg_state[];
8224 switch (GET_CODE (x))
8229 /* Clobber just modifies a register, it doesn't make it live. */
8231 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8232 flag | REGSTATE_MODIFIED);
8235 /* Pre modify updates the first argument, just references the second. */
8238 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8239 flag | REGSTATE_MODIFIED | REGSTATE_LIVE);
8240 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, flag);
8243 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8244 statement, but just to be sure, make sure it is the type of cond_exec
8248 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8249 && GET_CODE (XEXP (cond, 0)) == REG
8250 && CR_P (REGNO (XEXP (cond, 0)))
8251 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8252 && INTVAL (XEXP (cond, 1)) == 0
8253 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8255 frv_registers_update (cond, reg_state, modified, p_num_mod, flag);
8256 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8257 | ((GET_CODE (cond) == NE)
8259 : REGSTATE_IF_FALSE));
8261 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod,
8266 fatal_insn ("frv_registers_update", x);
8268 /* MEM resets the modification bits. */
8270 flag &= ~REGSTATE_MODIFIED;
8273 /* See if we need to set the modified flag. */
8275 reg = SUBREG_REG (x);
8276 if (GET_CODE (reg) == REG)
8278 regno = subreg_regno (x);
8279 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8286 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8290 if (flag & REGSTATE_MODIFIED)
8292 flag &= REGSTATE_MASK;
8293 while (regno < reg_max)
8295 int rs = reg_state[regno];
8299 if ((rs & REGSTATE_MODIFIED) == 0)
8301 modified[ *p_num_mod ] = regno;
8305 /* If the previous register state had the register as
8306 modified, possibly in some conditional execution context,
8307 and the current insn modifies in some other context, or
8308 outside of conditional execution, just mark the variable
8311 flag &= ~(REGSTATE_IF_EITHER | REGSTATE_CC_MASK);
8313 reg_state[regno] = (rs | flag);
8322 length = GET_RTX_LENGTH (GET_CODE (x));
8323 format = GET_RTX_FORMAT (GET_CODE (x));
8325 for (j = 0; j < length; ++j)
8330 frv_registers_update (XEXP (x, j), reg_state, modified, p_num_mod,
8336 if (XVEC (x, j) != 0)
8339 for (k = 0; k < XVECLEN (x, j); ++k)
8340 frv_registers_update (XVECEXP (x, j, k), reg_state, modified,
8346 /* Nothing to do. */
8355 /* Return if any registers in a hard register set were used an insn. */
8358 frv_registers_used_p (x, reg_state, flag)
8360 unsigned char reg_state[];
8372 switch (GET_CODE (x))
8377 /* Skip clobber, that doesn't use the previous value */
8381 /* For SET, if a conditional jump has occurred in the same insn, only
8382 allow a set of a CR register if that register is not currently live.
8383 This is because on the FR-V, B0/B1 instructions are always last.
8384 Otherwise, don't look at the result, except within a MEM, but do look
8387 dest = SET_DEST (x);
8388 if (flag & REGSTATE_CONDJUMP
8389 && GET_CODE (dest) == REG && CR_P (REGNO (dest))
8390 && (reg_state[ REGNO (dest) ] & REGSTATE_LIVE) != 0)
8393 if (GET_CODE (dest) == MEM)
8395 result = frv_registers_used_p (XEXP (dest, 0), reg_state, flag);
8400 return frv_registers_used_p (SET_SRC (x), reg_state, flag);
8402 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8403 statement, but just to be sure, make sure it is the type of cond_exec
8407 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8408 && GET_CODE (XEXP (cond, 0)) == REG
8409 && CR_P (REGNO (XEXP (cond, 0)))
8410 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8411 && INTVAL (XEXP (cond, 1)) == 0
8412 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8414 result = frv_registers_used_p (cond, reg_state, flag);
8418 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8419 | ((GET_CODE (cond) == NE)
8421 : REGSTATE_IF_FALSE));
8423 return frv_registers_used_p (XEXP (x, 1), reg_state, flag);
8426 fatal_insn ("frv_registers_used_p", x);
8428 /* See if a register or subreg was modified in the same VLIW insn. */
8430 reg = SUBREG_REG (x);
8431 if (GET_CODE (reg) == REG)
8433 regno = subreg_regno (x);
8434 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8441 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8445 while (regno < reg_max)
8447 int rs = reg_state[regno];
8449 if (rs & REGSTATE_MODIFIED)
8451 int rs_if = rs & REGSTATE_IF_EITHER;
8452 int flag_if = flag & REGSTATE_IF_EITHER;
8454 /* Simple modification, no conditional execution */
8455 if ((rs & REGSTATE_IF_EITHER) == 0)
8458 /* See if the variable is only modified in a conditional
8459 execution expression opposite to the conditional execution
8460 expression that governs this expression (ie, true vs. false
8461 for the same CC register). If this isn't two halves of the
8462 same conditional expression, consider the register
8464 if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE)
8465 || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE))
8466 && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK)))
8478 length = GET_RTX_LENGTH (GET_CODE (x));
8479 format = GET_RTX_FORMAT (GET_CODE (x));
8481 for (j = 0; j < length; ++j)
8486 result = frv_registers_used_p (XEXP (x, j), reg_state, flag);
8493 if (XVEC (x, j) != 0)
8496 for (k = 0; k < XVECLEN (x, j); ++k)
8498 result = frv_registers_used_p (XVECEXP (x, j, k), reg_state,
8507 /* Nothing to do. */
8515 /* Return if any registers in a hard register set were set in an insn. */
8518 frv_registers_set_p (x, reg_state, modify_p)
8520 unsigned char reg_state[];
8530 switch (GET_CODE (x))
8536 return frv_registers_set_p (XEXP (x, 0), reg_state, TRUE);
8540 return (frv_registers_set_p (XEXP (x, 0), reg_state, TRUE)
8541 || frv_registers_set_p (XEXP (x, 1), reg_state, FALSE));
8545 /* just to be sure, make sure it is the type of cond_exec we
8547 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8548 && GET_CODE (XEXP (cond, 0)) == REG
8549 && CR_P (REGNO (XEXP (cond, 0)))
8550 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8551 && INTVAL (XEXP (cond, 1)) == 0
8553 return frv_registers_set_p (XEXP (x, 1), reg_state, modify_p);
8555 fatal_insn ("frv_registers_set_p", x);
8557 /* MEM resets the modification bits. */
8562 /* See if we need to set the modified modify_p. */
8564 reg = SUBREG_REG (x);
8565 if (GET_CODE (reg) == REG)
8567 regno = subreg_regno (x);
8568 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8575 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8580 while (regno < reg_max)
8582 int rs = reg_state[regno];
8584 if (rs & REGSTATE_MODIFIED)
8592 length = GET_RTX_LENGTH (GET_CODE (x));
8593 format = GET_RTX_FORMAT (GET_CODE (x));
8595 for (j = 0; j < length; ++j)
8600 if (frv_registers_set_p (XEXP (x, j), reg_state, modify_p))
8606 if (XVEC (x, j) != 0)
8609 for (k = 0; k < XVECLEN (x, j); ++k)
8610 if (frv_registers_set_p (XVECEXP (x, j, k), reg_state,
8617 /* Nothing to do. */
8626 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8627 conditional branches/calls/jumps, etc. with previous insns where it can. It
8628 does not reorder the instructions. We assume the scheduler left the flow
8629 information in a reasonable state. */
8634 state_t frv_state; /* frv state machine */
8635 int cur_start_vliw_p; /* current insn starts a VLIW insn */
8636 int next_start_vliw_p; /* next insn starts a VLIW insn */
8637 int cur_condjump_p; /* flag if current insn is a cond jump*/
8638 int next_condjump_p; /* flag if next insn is a cond jump */
8642 int num_mod = 0; /* # of modified registers */
8643 int modified[FIRST_PSEUDO_REGISTER]; /* registers modified in current VLIW */
8644 /* register state information */
8645 unsigned char reg_state[FIRST_PSEUDO_REGISTER];
8647 /* If we weren't going to pack the insns, don't bother with this pass. */
8648 if (!optimize || !flag_schedule_insns_after_reload || TARGET_NO_VLIW_BRANCH)
8651 switch (frv_cpu_type)
8654 case FRV_CPU_FR300: /* FR300/simple are single issue */
8655 case FRV_CPU_SIMPLE:
8658 case FRV_CPU_GENERIC: /* FR-V and FR500 are multi-issue */
8661 case FRV_CPU_TOMCAT:
8665 /* Set up the instruction and register states. */
8667 frv_state = (state_t) xmalloc (state_size ());
8668 memset (reg_state, REGSTATE_DEAD, sizeof (reg_state));
8670 /* Go through the insns, and repack the insns. */
8671 state_reset (frv_state);
8672 cur_start_vliw_p = FALSE;
8673 next_start_vliw_p = TRUE;
8675 next_condjump_p = 0;
8677 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
8679 enum rtx_code code = GET_CODE (insn);
8680 enum rtx_code pattern_code;
8682 /* For basic block begin notes redo the live information, and skip other
8686 if (NOTE_LINE_NUMBER (insn) == (int)NOTE_INSN_BASIC_BLOCK)
8690 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
8691 reg_state[j] &= ~ REGSTATE_LIVE;
8693 live = NOTE_BASIC_BLOCK (insn)->global_live_at_start;
8694 EXECUTE_IF_SET_IN_REG_SET(live, 0, j,
8696 reg_state[j] |= REGSTATE_LIVE;
8703 /* things like labels reset everything. */
8704 if (GET_RTX_CLASS (code) != 'i')
8706 next_start_vliw_p = TRUE;
8710 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8711 set on the USE insn that preceeds the return, and potentially on
8712 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8713 holding the case table labels. */
8714 pattern_code = GET_CODE (PATTERN (insn));
8715 if (pattern_code == USE || pattern_code == CLOBBER
8716 || pattern_code == ADDR_VEC || pattern_code == ADDR_DIFF_VEC)
8718 CLEAR_VLIW_START (insn);
8722 cur_start_vliw_p = next_start_vliw_p;
8723 next_start_vliw_p = FALSE;
8725 cur_condjump_p |= next_condjump_p;
8726 next_condjump_p = 0;
8728 /* Unconditional branches and calls end the current VLIW insn. */
8729 if (code == CALL_INSN)
8731 next_start_vliw_p = TRUE;
8733 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8734 if (frv_cpu_type == FRV_CPU_TOMCAT)
8735 cur_start_vliw_p = TRUE;
8737 else if (code == JUMP_INSN)
8739 if (any_condjump_p (insn))
8740 next_condjump_p = REGSTATE_CONDJUMP;
8742 next_start_vliw_p = TRUE;
8745 /* Only allow setting a CCR register after a conditional branch. */
8746 else if (((cur_condjump_p & REGSTATE_CONDJUMP) != 0)
8747 && get_attr_type (insn) != TYPE_CCR)
8748 cur_start_vliw_p = TRUE;
8750 /* Determine if we need to start a new VLIW instruction. */
8751 if (cur_start_vliw_p
8752 /* Do not check for register conflicts in a setlo instruction
8753 because any output or true dependencies will be with the
8754 partnering sethi instruction, with which it can be packed.
8756 Although output dependencies are rare they are still
8757 possible. So check output dependencies in VLIW insn. */
8758 || (get_attr_type (insn) != TYPE_SETLO
8759 && (frv_registers_used_p (PATTERN (insn),
8762 || frv_registers_set_p (PATTERN (insn), reg_state, FALSE)))
8763 || state_transition (frv_state, insn) >= 0)
8765 SET_VLIW_START (insn);
8766 state_reset (frv_state);
8767 state_transition (frv_state, insn);
8770 /* Update the modified registers. */
8771 for (j = 0; j < num_mod; j++)
8772 reg_state[ modified[j] ] &= ~(REGSTATE_CC_MASK
8773 | REGSTATE_IF_EITHER
8774 | REGSTATE_MODIFIED);
8779 CLEAR_VLIW_START (insn);
8781 /* Record which registers are modified. */
8782 frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0);
8784 /* Process the death notices */
8785 for (link = REG_NOTES (insn);
8787 link = XEXP (link, 1))
8789 rtx reg = XEXP (link, 0);
8791 if (REG_NOTE_KIND (link) == REG_DEAD && GET_CODE (reg) == REG)
8793 int regno = REGNO (reg);
8794 int n = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8795 for (; regno < n; regno++)
8796 reg_state[regno] &= ~REGSTATE_LIVE;
8807 #define def_builtin(name, type, code) \
8808 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8810 struct builtin_description
8812 enum insn_code icode;
8814 enum frv_builtins code;
8815 enum rtx_code comparison;
8819 /* Media intrinsics that take a single, constant argument. */
8821 static struct builtin_description bdesc_set[] =
8823 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8826 /* Media intrinsics that take just one argument. */
8828 static struct builtin_description bdesc_1arg[] =
8830 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8831 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8832 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8833 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8834 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }
8837 /* Media intrinsics that take two arguments. */
8839 static struct builtin_description bdesc_2arg[] =
8841 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8842 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8843 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8844 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8845 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8846 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8847 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8848 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8849 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8850 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8851 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8852 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8853 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8854 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8855 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8856 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
8857 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8858 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8859 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8860 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }
8863 /* Media intrinsics that take two arguments, the first being an ACC number. */
8865 static struct builtin_description bdesc_cut[] =
8867 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8868 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8869 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8872 /* Two-argument media intrinsics with an immediate second argument. */
8874 static struct builtin_description bdesc_2argimm[] =
8876 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8877 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8878 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8879 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8880 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8881 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8882 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8883 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8884 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8885 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8886 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8887 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8888 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8889 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8890 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }
8893 /* Media intrinsics that take two arguments and return void, the first argument
8894 being a pointer to 4 words in memory. */
8896 static struct builtin_description bdesc_void2arg[] =
8898 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8899 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8902 /* Media intrinsics that take three arguments, the first being a const_int that
8903 denotes an accumulator, and that return void. */
8905 static struct builtin_description bdesc_void3arg[] =
8907 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8908 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8909 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8910 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8911 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8912 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8913 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8914 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8915 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8916 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8917 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8918 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8919 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8920 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8921 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8922 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8923 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8924 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8925 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8926 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8927 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8928 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8929 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8930 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8931 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8934 /* Media intrinsics that take two accumulator numbers as argument and
8937 static struct builtin_description bdesc_voidacc[] =
8939 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8940 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8941 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8942 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8943 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8944 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8947 /* Initialize media builtins. */
8950 frv_init_builtins ()
8952 tree endlink = void_list_node;
8953 tree accumulator = integer_type_node;
8954 tree integer = integer_type_node;
8955 tree voidt = void_type_node;
8956 tree uhalf = short_unsigned_type_node;
8957 tree sword1 = long_integer_type_node;
8958 tree uword1 = long_unsigned_type_node;
8959 tree sword2 = long_long_integer_type_node;
8960 tree uword2 = long_long_unsigned_type_node;
8961 tree uword4 = build_pointer_type (uword1);
8963 #define UNARY(RET, T1) \
8964 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8966 #define BINARY(RET, T1, T2) \
8967 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8968 tree_cons (NULL_TREE, T2, endlink)))
8970 #define TRINARY(RET, T1, T2, T3) \
8971 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8972 tree_cons (NULL_TREE, T2, \
8973 tree_cons (NULL_TREE, T3, endlink))))
8975 tree void_ftype_void = build_function_type (voidt, endlink);
8977 tree void_ftype_acc = UNARY (voidt, accumulator);
8978 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8979 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8980 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8981 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8982 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8983 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8984 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8985 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8987 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8988 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8989 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8990 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8991 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8992 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8993 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8994 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8995 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8996 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8997 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8999 tree sw1_ftype_int = UNARY (sword1, integer);
9000 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9001 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9003 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9004 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9005 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9006 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9007 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9009 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9011 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9012 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9013 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9014 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9015 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9016 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9017 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9018 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9019 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9020 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9021 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9022 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9023 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9024 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9025 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9026 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9027 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9028 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9029 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9030 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9031 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9032 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9033 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9034 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9035 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9036 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9037 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9038 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9039 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9040 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9041 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9042 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9043 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9044 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9045 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9046 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9047 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9048 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9049 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9050 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9051 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9052 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9053 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9054 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9055 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9056 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9057 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9058 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9059 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9060 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9061 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9062 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9063 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9064 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9065 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9066 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9067 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9068 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9069 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9070 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9071 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9072 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9073 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9074 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9075 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9076 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9077 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9078 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9079 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9080 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9081 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9082 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9083 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9084 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9085 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9086 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9087 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9088 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9089 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9090 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9091 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9092 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9093 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9094 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9101 /* Set the names for various arithmetic operations according to the
9104 frv_init_libfuncs (void)
9106 set_optab_libfunc (smod_optab, SImode, "__modi");
9107 set_optab_libfunc (umod_optab, SImode, "__umodi");
9109 set_optab_libfunc (add_optab, DImode, "__addll");
9110 set_optab_libfunc (sub_optab, DImode, "__subll");
9111 set_optab_libfunc (smul_optab, DImode, "__mulll");
9112 set_optab_libfunc (sdiv_optab, DImode, "__divll");
9113 set_optab_libfunc (smod_optab, DImode, "__modll");
9114 set_optab_libfunc (umod_optab, DImode, "__umodll");
9115 set_optab_libfunc (and_optab, DImode, "__andll");
9116 set_optab_libfunc (ior_optab, DImode, "__orll");
9117 set_optab_libfunc (xor_optab, DImode, "__xorll");
9118 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
9120 set_optab_libfunc (add_optab, SFmode, "__addf");
9121 set_optab_libfunc (sub_optab, SFmode, "__subf");
9122 set_optab_libfunc (smul_optab, SFmode, "__mulf");
9123 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
9125 set_optab_libfunc (add_optab, DFmode, "__addd");
9126 set_optab_libfunc (sub_optab, DFmode, "__subd");
9127 set_optab_libfunc (smul_optab, DFmode, "__muld");
9128 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
9130 fixsfsi_libfunc = init_one_libfunc ("__ftoi");
9131 fixunssfsi_libfunc = init_one_libfunc ("__ftoui");
9132 fixsfdi_libfunc = init_one_libfunc ("__ftoll");
9133 fixunssfdi_libfunc = init_one_libfunc ("__ftoull");
9134 fixdfsi_libfunc = init_one_libfunc ("__dtoi");
9135 fixunsdfsi_libfunc = init_one_libfunc ("__dtoui");
9136 fixdfdi_libfunc = init_one_libfunc ("__dtoll");
9137 fixunsdfdi_libfunc = init_one_libfunc ("__dtoull");
9138 floatsisf_libfunc = init_one_libfunc ("__itof");
9139 floatdisf_libfunc = init_one_libfunc ("__lltof");
9140 floatsidf_libfunc = init_one_libfunc ("__itod");
9141 floatdidf_libfunc = init_one_libfunc ("__lltod");
9142 extendsfdf2_libfunc = init_one_libfunc ("__ftod");
9143 truncdfsf2_libfunc = init_one_libfunc ("__dtof");
9146 /* Convert an integer constant to an accumulator register. ICODE is the
9147 code of the target instruction, OPNUM is the number of the
9148 accumulator operand and OPVAL is the constant integer. Try both
9149 ACC and ACCG registers; only report an error if neither fit the
9153 frv_int_to_acc (icode, opnum, opval)
9154 enum insn_code icode;
9160 if (GET_CODE (opval) != CONST_INT)
9162 error ("accumulator is not a constant integer");
9165 if (! IN_RANGE_P (INTVAL (opval), 0, NUM_ACCS - 1))
9167 error ("accumulator number is out of bounds");
9171 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9172 ACC_FIRST + INTVAL (opval));
9173 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9174 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9176 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9178 error ("inappropriate accumulator for `%s'", insn_data[icode].name);
9184 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9187 static enum machine_mode
9188 frv_matching_accg_mode (mode)
9189 enum machine_mode mode;
9207 /* Return the accumulator guard that should be paired with accumulator
9208 register ACC. The mode of the returned register is in the same
9209 class as ACC, but is four times smaller. */
9212 frv_matching_accg_for_acc (acc)
9215 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9216 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9219 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9220 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9224 frv_read_argument (arglistptr)
9227 tree next = TREE_VALUE (*arglistptr);
9228 *arglistptr = TREE_CHAIN (*arglistptr);
9229 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9232 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9233 The instruction should require a constant operand of some sort. The
9234 function prints an error if OPVAL is not valid. */
9237 frv_check_constant_argument (icode, opnum, opval)
9238 enum insn_code icode;
9242 if (GET_CODE (opval) != CONST_INT)
9244 error ("`%s' expects a constant argument", insn_data[icode].name);
9247 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9249 error ("constant argument out of range for `%s'", insn_data[icode].name);
9255 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9256 if it's not null, has the right mode, and satisfies operand 0's
9260 frv_legitimize_target (icode, target)
9261 enum insn_code icode;
9264 enum machine_mode mode = insn_data[icode].operand[0].mode;
9267 || GET_MODE (target) != mode
9268 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9269 return gen_reg_rtx (mode);
9274 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9275 check whether ARG satisfies the operand's contraints. If it doesn't,
9276 copy ARG to a temporary register and return that. Otherwise return ARG
9280 frv_legitimize_argument (icode, opnum, arg)
9281 enum insn_code icode;
9285 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9287 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9290 return copy_to_mode_reg (mode, arg);
9293 /* Expand builtins that take a single, constant argument. At the moment,
9294 only MHDSETS falls into this category. */
9297 frv_expand_set_builtin (icode, arglist, target)
9298 enum insn_code icode;
9303 rtx op0 = frv_read_argument (&arglist);
9305 if (! frv_check_constant_argument (icode, 1, op0))
9308 target = frv_legitimize_target (icode, target);
9309 pat = GEN_FCN (icode) (target, op0);
9317 /* Expand builtins that take one operand. */
9320 frv_expand_unop_builtin (icode, arglist, target)
9321 enum insn_code icode;
9326 rtx op0 = frv_read_argument (&arglist);
9328 target = frv_legitimize_target (icode, target);
9329 op0 = frv_legitimize_argument (icode, 1, op0);
9330 pat = GEN_FCN (icode) (target, op0);
9338 /* Expand builtins that take two operands. */
9341 frv_expand_binop_builtin (icode, arglist, target)
9342 enum insn_code icode;
9347 rtx op0 = frv_read_argument (&arglist);
9348 rtx op1 = frv_read_argument (&arglist);
9350 target = frv_legitimize_target (icode, target);
9351 op0 = frv_legitimize_argument (icode, 1, op0);
9352 op1 = frv_legitimize_argument (icode, 2, op1);
9353 pat = GEN_FCN (icode) (target, op0, op1);
9361 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9365 frv_expand_cut_builtin (icode, arglist, target)
9366 enum insn_code icode;
9371 rtx op0 = frv_read_argument (&arglist);
9372 rtx op1 = frv_read_argument (&arglist);
9375 target = frv_legitimize_target (icode, target);
9376 op0 = frv_int_to_acc (icode, 1, op0);
9380 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9382 if (! frv_check_constant_argument (icode, 2, op1))
9386 op1 = frv_legitimize_argument (icode, 2, op1);
9388 op2 = frv_matching_accg_for_acc (op0);
9389 pat = GEN_FCN (icode) (target, op0, op1, op2);
9397 /* Expand builtins that take two operands and the second is immediate. */
9400 frv_expand_binopimm_builtin (icode, arglist, target)
9401 enum insn_code icode;
9406 rtx op0 = frv_read_argument (&arglist);
9407 rtx op1 = frv_read_argument (&arglist);
9409 if (! frv_check_constant_argument (icode, 2, op1))
9412 target = frv_legitimize_target (icode, target);
9413 op0 = frv_legitimize_argument (icode, 1, op0);
9414 pat = GEN_FCN (icode) (target, op0, op1);
9422 /* Expand builtins that take two operands, the first operand being a pointer to
9423 ints and return void. */
9426 frv_expand_voidbinop_builtin (icode, arglist)
9427 enum insn_code icode;
9431 rtx op0 = frv_read_argument (&arglist);
9432 rtx op1 = frv_read_argument (&arglist);
9433 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9436 if (GET_CODE (op0) != MEM)
9440 if (! offsettable_address_p (0, mode0, op0))
9442 reg = gen_reg_rtx (Pmode);
9443 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9446 op0 = gen_rtx_MEM (SImode, reg);
9449 addr = XEXP (op0, 0);
9450 if (! offsettable_address_p (0, mode0, addr))
9451 addr = copy_to_mode_reg (Pmode, op0);
9453 op0 = change_address (op0, V4SImode, addr);
9454 op1 = frv_legitimize_argument (icode, 1, op1);
9455 pat = GEN_FCN (icode) (op0, op1);
9463 /* Expand builtins that take three operands and return void. The first
9464 argument must be a constant that describes a pair or quad accumulators. A
9465 fourth argument is created that is the accumulator guard register that
9466 corresponds to the accumulator. */
9469 frv_expand_voidtriop_builtin (icode, arglist)
9470 enum insn_code icode;
9474 rtx op0 = frv_read_argument (&arglist);
9475 rtx op1 = frv_read_argument (&arglist);
9476 rtx op2 = frv_read_argument (&arglist);
9479 op0 = frv_int_to_acc (icode, 0, op0);
9483 op1 = frv_legitimize_argument (icode, 1, op1);
9484 op2 = frv_legitimize_argument (icode, 2, op2);
9485 op3 = frv_matching_accg_for_acc (op0);
9486 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9494 /* Expand builtins that perform accumulator-to-accumulator operations.
9495 These builtins take two accumulator numbers as argument and return
9499 frv_expand_voidaccop_builtin (icode, arglist)
9500 enum insn_code icode;
9504 rtx op0 = frv_read_argument (&arglist);
9505 rtx op1 = frv_read_argument (&arglist);
9509 op0 = frv_int_to_acc (icode, 0, op0);
9513 op1 = frv_int_to_acc (icode, 1, op1);
9517 op2 = frv_matching_accg_for_acc (op0);
9518 op3 = frv_matching_accg_for_acc (op1);
9519 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9527 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9528 number as argument. */
9531 frv_expand_mclracc_builtin (arglist)
9534 enum insn_code icode = CODE_FOR_mclracc;
9536 rtx op0 = frv_read_argument (&arglist);
9538 op0 = frv_int_to_acc (icode, 0, op0);
9542 pat = GEN_FCN (icode) (op0);
9549 /* Expand builtins that take no arguments. */
9552 frv_expand_noargs_builtin (icode)
9553 enum insn_code icode;
9555 rtx pat = GEN_FCN (icode) (GEN_INT (0));
9562 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9563 number or accumulator guard number as argument and return an SI integer. */
9566 frv_expand_mrdacc_builtin (icode, arglist)
9567 enum insn_code icode;
9571 rtx target = gen_reg_rtx (SImode);
9572 rtx op0 = frv_read_argument (&arglist);
9574 op0 = frv_int_to_acc (icode, 1, op0);
9578 pat = GEN_FCN (icode) (target, op0);
9586 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9587 accumulator guard as their first argument and an SImode value as their
9591 frv_expand_mwtacc_builtin (icode, arglist)
9592 enum insn_code icode;
9596 rtx op0 = frv_read_argument (&arglist);
9597 rtx op1 = frv_read_argument (&arglist);
9599 op0 = frv_int_to_acc (icode, 0, op0);
9603 op1 = frv_legitimize_argument (icode, 1, op1);
9604 pat = GEN_FCN (icode) (op0, op1);
9611 /* Expand builtins. */
9614 frv_expand_builtin (exp, target, subtarget, mode, ignore)
9617 rtx subtarget ATTRIBUTE_UNUSED;
9618 enum machine_mode mode ATTRIBUTE_UNUSED;
9619 int ignore ATTRIBUTE_UNUSED;
9621 tree arglist = TREE_OPERAND (exp, 1);
9622 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9623 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9625 struct builtin_description *d;
9629 error ("media functions are not available unless -mmedia is used");
9635 case FRV_BUILTIN_MCOP1:
9636 case FRV_BUILTIN_MCOP2:
9637 case FRV_BUILTIN_MDUNPACKH:
9638 case FRV_BUILTIN_MBTOHE:
9639 if (! TARGET_MEDIA_REV1)
9641 error ("this media function is only available on the fr500");
9646 case FRV_BUILTIN_MQXMACHS:
9647 case FRV_BUILTIN_MQXMACXHS:
9648 case FRV_BUILTIN_MQMACXHS:
9649 case FRV_BUILTIN_MADDACCS:
9650 case FRV_BUILTIN_MSUBACCS:
9651 case FRV_BUILTIN_MASACCS:
9652 case FRV_BUILTIN_MDADDACCS:
9653 case FRV_BUILTIN_MDSUBACCS:
9654 case FRV_BUILTIN_MDASACCS:
9655 case FRV_BUILTIN_MABSHS:
9656 case FRV_BUILTIN_MDROTLI:
9657 case FRV_BUILTIN_MCPLHI:
9658 case FRV_BUILTIN_MCPLI:
9659 case FRV_BUILTIN_MDCUTSSI:
9660 case FRV_BUILTIN_MQSATHS:
9661 case FRV_BUILTIN_MHSETLOS:
9662 case FRV_BUILTIN_MHSETLOH:
9663 case FRV_BUILTIN_MHSETHIS:
9664 case FRV_BUILTIN_MHSETHIH:
9665 case FRV_BUILTIN_MHDSETS:
9666 case FRV_BUILTIN_MHDSETH:
9667 if (! TARGET_MEDIA_REV2)
9669 error ("this media function is only available on the fr400");
9678 /* Expand unique builtins. */
9682 case FRV_BUILTIN_MTRAP:
9683 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9685 case FRV_BUILTIN_MCLRACC:
9686 return frv_expand_mclracc_builtin (arglist);
9688 case FRV_BUILTIN_MCLRACCA:
9690 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9692 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9694 case FRV_BUILTIN_MRDACC:
9695 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
9697 case FRV_BUILTIN_MRDACCG:
9698 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
9700 case FRV_BUILTIN_MWTACC:
9701 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
9703 case FRV_BUILTIN_MWTACCG:
9704 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
9710 /* Expand groups of builtins. */
9712 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9713 if (d->code == fcode)
9714 return frv_expand_set_builtin (d->icode, arglist, target);
9716 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9717 if (d->code == fcode)
9718 return frv_expand_unop_builtin (d->icode, arglist, target);
9720 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9721 if (d->code == fcode)
9722 return frv_expand_binop_builtin (d->icode, arglist, target);
9724 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9725 if (d->code == fcode)
9726 return frv_expand_cut_builtin (d->icode, arglist, target);
9728 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9729 if (d->code == fcode)
9730 return frv_expand_binopimm_builtin (d->icode, arglist, target);
9732 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9733 if (d->code == fcode)
9734 return frv_expand_voidbinop_builtin (d->icode, arglist);
9736 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9737 if (d->code == fcode)
9738 return frv_expand_voidtriop_builtin (d->icode, arglist);
9740 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9741 if (d->code == fcode)
9742 return frv_expand_voidaccop_builtin (d->icode, arglist);
9748 frv_in_small_data_p (decl)
9754 /* Don't apply the -G flag to internal compiler structures. We
9755 should leave such structures in the main data section, partly
9756 for efficiency and partly because the size of some of them
9757 (such as C++ typeinfos) is not known until later. */
9758 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9761 size = int_size_in_bytes (TREE_TYPE (decl));
9762 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9765 /* If we already know which section the decl should be in, see if
9766 it's a small data section. */
9767 section_name = DECL_SECTION_NAME (decl);
9770 if (TREE_CODE (section_name) != STRING_CST)
9772 if (frv_string_begins_with (section_name, ".sdata"))
9774 if (frv_string_begins_with (section_name, ".sbss"))
9782 frv_rtx_costs (x, code, outer_code, total)
9784 int code, outer_code ATTRIBUTE_UNUSED;
9790 /* Make 12 bit integers really cheap. */
9791 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9802 *total = COSTS_N_INSNS (2);
9816 if (GET_MODE (x) == SImode)
9817 *total = COSTS_N_INSNS (1);
9818 else if (GET_MODE (x) == DImode)
9819 *total = COSTS_N_INSNS (2);
9821 *total = COSTS_N_INSNS (3);
9825 if (GET_MODE (x) == SImode)
9826 *total = COSTS_N_INSNS (2);
9828 *total = COSTS_N_INSNS (6); /* guess */
9835 *total = COSTS_N_INSNS (18);
9844 frv_asm_out_constructor (symbol, priority)
9846 int priority ATTRIBUTE_UNUSED;
9849 assemble_align (POINTER_SIZE);
9850 assemble_integer_with_op ("\t.picptr\t", symbol);
9854 frv_asm_out_destructor (symbol, priority)
9856 int priority ATTRIBUTE_UNUSED;
9859 assemble_align (POINTER_SIZE);
9860 assemble_integer_with_op ("\t.picptr\t", symbol);