1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
268 static int frv_default_flags_for_cpu (void);
269 static int frv_string_begins_with (const_tree, const char *);
270 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
271 static void frv_print_operand (FILE *, rtx, int);
272 static void frv_print_operand_address (FILE *, rtx);
273 static bool frv_print_operand_punct_valid_p (unsigned char code);
274 static void frv_print_operand_memory_reference_reg
276 static void frv_print_operand_memory_reference (FILE *, rtx, int);
277 static int frv_print_operand_jump_hint (rtx);
278 static const char *comparison_string (enum rtx_code, rtx);
279 static rtx frv_function_value (const_tree, const_tree,
281 static rtx frv_libcall_value (enum machine_mode,
283 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
284 static rtx single_set_pattern (rtx);
285 static int frv_function_contains_far_jump (void);
286 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
290 static rtx frv_frame_offset_rtx (int);
291 static rtx frv_frame_mem (enum machine_mode, rtx, int);
292 static rtx frv_dwarf_store (rtx, int);
293 static void frv_frame_insn (rtx, rtx);
294 static void frv_frame_access (frv_frame_accessor_t*,
296 static void frv_frame_access_multi (frv_frame_accessor_t*,
298 static void frv_frame_access_standard_regs (enum frv_stack_op,
300 static struct machine_function *frv_init_machine_status (void);
301 static rtx frv_int_to_acc (enum insn_code, int, rtx);
302 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
303 static rtx frv_read_argument (tree, unsigned int);
304 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
305 static int frv_check_constant_argument (enum insn_code, int, rtx);
306 static rtx frv_legitimize_target (enum insn_code, rtx);
307 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
308 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
309 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
310 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
312 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
313 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
314 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
315 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
316 static rtx frv_expand_int_void2arg (enum insn_code, tree);
317 static rtx frv_expand_prefetches (enum insn_code, tree);
318 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
319 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
320 static rtx frv_expand_mclracc_builtin (tree);
321 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
322 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
323 static rtx frv_expand_noargs_builtin (enum insn_code);
324 static void frv_split_iacc_move (rtx, rtx);
325 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
326 static int frv_clear_registers_used (rtx *, void *);
327 static void frv_ifcvt_add_insn (rtx, rtx, int);
328 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
329 static rtx frv_ifcvt_load_value (rtx, rtx);
330 static int frv_acc_group_1 (rtx *, void *);
331 static unsigned int frv_insn_unit (rtx);
332 static bool frv_issues_to_branch_unit_p (rtx);
333 static int frv_cond_flags (rtx);
334 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
335 static int frv_registers_conflict_p_1 (rtx *, void *);
336 static bool frv_registers_conflict_p (rtx);
337 static void frv_registers_update_1 (rtx, const_rtx, void *);
338 static void frv_registers_update (rtx);
339 static void frv_start_packet (void);
340 static void frv_start_packet_block (void);
341 static void frv_finish_packet (void (*) (void));
342 static bool frv_pack_insn_p (rtx);
343 static void frv_add_insn_to_packet (rtx);
344 static void frv_insert_nop_in_packet (rtx);
345 static bool frv_for_each_packet (void (*) (void));
346 static bool frv_sort_insn_group_1 (enum frv_insn_group,
347 unsigned int, unsigned int,
348 unsigned int, unsigned int,
350 static int frv_compare_insns (const void *, const void *);
351 static void frv_sort_insn_group (enum frv_insn_group);
352 static void frv_reorder_packet (void);
353 static void frv_fill_unused_units (enum frv_insn_group);
354 static void frv_align_label (void);
355 static void frv_reorg_packet (void);
356 static void frv_register_nop (rtx);
357 static void frv_reorg (void);
358 static void frv_pack_insns (void);
359 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
360 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
361 static bool frv_assemble_integer (rtx, unsigned, int);
362 static void frv_init_builtins (void);
363 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
364 static void frv_init_libfuncs (void);
365 static bool frv_in_small_data_p (const_tree);
366 static void frv_asm_output_mi_thunk
367 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
368 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
371 static rtx frv_expand_builtin_saveregs (void);
372 static void frv_expand_builtin_va_start (tree, rtx);
373 static bool frv_rtx_costs (rtx, int, int, int*, bool);
374 static void frv_asm_out_constructor (rtx, int);
375 static void frv_asm_out_destructor (rtx, int);
376 static bool frv_function_symbol_referenced_p (rtx);
377 static bool frv_cannot_force_const_mem (rtx);
378 static const char *unspec_got_name (int);
379 static void frv_output_const_unspec (FILE *,
380 const struct frv_unspec *);
381 static bool frv_function_ok_for_sibcall (tree, tree);
382 static rtx frv_struct_value_rtx (tree, int);
383 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
384 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
386 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
388 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
390 secondary_reload_info *);
391 static bool frv_frame_pointer_required (void);
392 static bool frv_can_eliminate (const int, const int);
393 static void frv_trampoline_init (rtx, tree, rtx);
395 /* Allow us to easily change the default for -malloc-cc. */
396 #ifndef DEFAULT_NO_ALLOC_CC
397 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
399 #define MASK_DEFAULT_ALLOC_CC 0
402 /* Initialize the GCC target structure. */
403 #undef TARGET_PRINT_OPERAND
404 #define TARGET_PRINT_OPERAND frv_print_operand
405 #undef TARGET_PRINT_OPERAND_ADDRESS
406 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
407 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
408 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
409 #undef TARGET_ASM_FUNCTION_PROLOGUE
410 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
411 #undef TARGET_ASM_FUNCTION_EPILOGUE
412 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
413 #undef TARGET_ASM_INTEGER
414 #define TARGET_ASM_INTEGER frv_assemble_integer
415 #undef TARGET_DEFAULT_TARGET_FLAGS
416 #define TARGET_DEFAULT_TARGET_FLAGS \
417 (MASK_DEFAULT_ALLOC_CC \
424 #undef TARGET_HANDLE_OPTION
425 #define TARGET_HANDLE_OPTION frv_handle_option
426 #undef TARGET_INIT_BUILTINS
427 #define TARGET_INIT_BUILTINS frv_init_builtins
428 #undef TARGET_EXPAND_BUILTIN
429 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
430 #undef TARGET_INIT_LIBFUNCS
431 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
432 #undef TARGET_IN_SMALL_DATA_P
433 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
434 #undef TARGET_RTX_COSTS
435 #define TARGET_RTX_COSTS frv_rtx_costs
436 #undef TARGET_ASM_CONSTRUCTOR
437 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
438 #undef TARGET_ASM_DESTRUCTOR
439 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
441 #undef TARGET_ASM_OUTPUT_MI_THUNK
442 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
443 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
444 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
446 #undef TARGET_SCHED_ISSUE_RATE
447 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
449 #undef TARGET_LEGITIMIZE_ADDRESS
450 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
452 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
453 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
454 #undef TARGET_CANNOT_FORCE_CONST_MEM
455 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
457 #undef TARGET_HAVE_TLS
458 #define TARGET_HAVE_TLS HAVE_AS_TLS
460 #undef TARGET_STRUCT_VALUE_RTX
461 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
462 #undef TARGET_MUST_PASS_IN_STACK
463 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
464 #undef TARGET_PASS_BY_REFERENCE
465 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
466 #undef TARGET_ARG_PARTIAL_BYTES
467 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
469 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
470 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
471 #undef TARGET_SETUP_INCOMING_VARARGS
472 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
473 #undef TARGET_MACHINE_DEPENDENT_REORG
474 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
476 #undef TARGET_EXPAND_BUILTIN_VA_START
477 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
480 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
481 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
484 #undef TARGET_SECONDARY_RELOAD
485 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
487 #undef TARGET_LEGITIMATE_ADDRESS_P
488 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
490 #undef TARGET_FRAME_POINTER_REQUIRED
491 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
493 #undef TARGET_CAN_ELIMINATE
494 #define TARGET_CAN_ELIMINATE frv_can_eliminate
496 #undef TARGET_TRAMPOLINE_INIT
497 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
499 #undef TARGET_FUNCTION_VALUE
500 #define TARGET_FUNCTION_VALUE frv_function_value
501 #undef TARGET_LIBCALL_VALUE
502 #define TARGET_LIBCALL_VALUE frv_libcall_value
504 struct gcc_target targetm = TARGET_INITIALIZER;
506 #define FRV_SYMBOL_REF_TLS_P(RTX) \
507 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
510 /* Any function call that satisfies the machine-independent
511 requirements is eligible on FR-V. */
514 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
515 tree exp ATTRIBUTE_UNUSED)
520 /* Return true if SYMBOL is a small data symbol and relocation RELOC
521 can be used to access it directly in a load or store. */
523 static FRV_INLINE bool
524 frv_small_data_reloc_p (rtx symbol, int reloc)
526 return (GET_CODE (symbol) == SYMBOL_REF
527 && SYMBOL_REF_SMALL_P (symbol)
528 && (!TARGET_FDPIC || flag_pic == 1)
529 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
532 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
536 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
538 if (GET_CODE (x) == CONST)
542 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
544 unspec->offset += INTVAL (XEXP (x, 1));
547 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
549 unspec->symbol = XVECEXP (x, 0, 0);
550 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
552 if (unspec->offset == 0)
555 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
556 && unspec->offset > 0
557 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
564 /* Decide whether we can force certain constants to memory. If we
565 decide we can't, the caller should be able to cope with it in
568 We never allow constants to be forced into memory for TARGET_FDPIC.
569 This is necessary for several reasons:
571 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
572 target-independent code will try to force them into the constant
573 pool, thus leading to infinite recursion.
575 2. We can never introduce new constant pool references during reload.
576 Any such reference would require use of the pseudo FDPIC register.
578 3. We can't represent a constant added to a function pointer (which is
579 not the same as a pointer to a function+constant).
581 4. In many cases, it's more efficient to calculate the constant in-line. */
584 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
589 /* Implement TARGET_HANDLE_OPTION. */
592 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
597 if (strcmp (arg, "simple") == 0)
598 frv_cpu_type = FRV_CPU_SIMPLE;
599 else if (strcmp (arg, "tomcat") == 0)
600 frv_cpu_type = FRV_CPU_TOMCAT;
601 else if (strcmp (arg, "fr550") == 0)
602 frv_cpu_type = FRV_CPU_FR550;
603 else if (strcmp (arg, "fr500") == 0)
604 frv_cpu_type = FRV_CPU_FR500;
605 else if (strcmp (arg, "fr450") == 0)
606 frv_cpu_type = FRV_CPU_FR450;
607 else if (strcmp (arg, "fr405") == 0)
608 frv_cpu_type = FRV_CPU_FR405;
609 else if (strcmp (arg, "fr400") == 0)
610 frv_cpu_type = FRV_CPU_FR400;
611 else if (strcmp (arg, "fr300") == 0)
612 frv_cpu_type = FRV_CPU_FR300;
613 else if (strcmp (arg, "frv") == 0)
614 frv_cpu_type = FRV_CPU_GENERIC;
625 frv_default_flags_for_cpu (void)
627 switch (frv_cpu_type)
629 case FRV_CPU_GENERIC:
630 return MASK_DEFAULT_FRV;
633 return MASK_DEFAULT_FR550;
637 return MASK_DEFAULT_FR500;
640 return MASK_DEFAULT_FR450;
644 return MASK_DEFAULT_FR400;
648 return MASK_DEFAULT_SIMPLE;
655 /* Sometimes certain combinations of command options do not make
656 sense on a particular target machine. You can define a macro
657 `OVERRIDE_OPTIONS' to take account of this. This macro, if
658 defined, is executed once just after all the command options have
661 Don't use this macro to turn on various extra optimizations for
662 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
665 frv_override_options (void)
670 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
672 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
673 linker about linking pic and non-pic code. */
676 if (!flag_pic) /* -fPIC */
679 if (! g_switch_set) /* -G0 */
686 /* A C expression whose value is a register class containing hard
687 register REGNO. In general there is more than one such class;
688 choose a class which is "minimal", meaning that no smaller class
689 also contains the register. */
691 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
693 enum reg_class rclass;
697 int gpr_reg = regno - GPR_FIRST;
699 if (gpr_reg == GR8_REG)
702 else if (gpr_reg == GR9_REG)
705 else if (gpr_reg == GR14_REG)
706 rclass = FDPIC_FPTR_REGS;
708 else if (gpr_reg == FDPIC_REGNO)
711 else if ((gpr_reg & 3) == 0)
714 else if ((gpr_reg & 1) == 0)
721 else if (FPR_P (regno))
723 int fpr_reg = regno - GPR_FIRST;
724 if ((fpr_reg & 3) == 0)
725 rclass = QUAD_FPR_REGS;
727 else if ((fpr_reg & 1) == 0)
734 else if (regno == LR_REGNO)
737 else if (regno == LCR_REGNO)
740 else if (ICC_P (regno))
743 else if (FCC_P (regno))
746 else if (ICR_P (regno))
749 else if (FCR_P (regno))
752 else if (ACC_P (regno))
754 int r = regno - ACC_FIRST;
756 rclass = QUAD_ACC_REGS;
757 else if ((r & 1) == 0)
758 rclass = EVEN_ACC_REGS;
763 else if (ACCG_P (regno))
769 regno_reg_class[regno] = rclass;
772 /* Check for small data option */
774 g_switch_value = SDATA_DEFAULT_SIZE;
776 /* A C expression which defines the machine-dependent operand
777 constraint letters for register classes. If CHAR is such a
778 letter, the value should be the register class corresponding to
779 it. Otherwise, the value should be `NO_REGS'. The register
780 letter `r', corresponding to class `GENERAL_REGS', will not be
781 passed to this macro; you do not need to handle it.
783 The following letters are unavailable, due to being used as
788 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
789 'Q', 'R', 'S', 'T', 'U'
791 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
793 for (i = 0; i < 256; i++)
794 reg_class_from_letter[i] = NO_REGS;
796 reg_class_from_letter['a'] = ACC_REGS;
797 reg_class_from_letter['b'] = EVEN_ACC_REGS;
798 reg_class_from_letter['c'] = CC_REGS;
799 reg_class_from_letter['d'] = GPR_REGS;
800 reg_class_from_letter['e'] = EVEN_REGS;
801 reg_class_from_letter['f'] = FPR_REGS;
802 reg_class_from_letter['h'] = FEVEN_REGS;
803 reg_class_from_letter['l'] = LR_REG;
804 reg_class_from_letter['q'] = QUAD_REGS;
805 reg_class_from_letter['t'] = ICC_REGS;
806 reg_class_from_letter['u'] = FCC_REGS;
807 reg_class_from_letter['v'] = ICR_REGS;
808 reg_class_from_letter['w'] = FCR_REGS;
809 reg_class_from_letter['x'] = QUAD_FPR_REGS;
810 reg_class_from_letter['y'] = LCR_REG;
811 reg_class_from_letter['z'] = SPR_REGS;
812 reg_class_from_letter['A'] = QUAD_ACC_REGS;
813 reg_class_from_letter['B'] = ACCG_REGS;
814 reg_class_from_letter['C'] = CR_REGS;
815 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
816 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
818 /* There is no single unaligned SI op for PIC code. Sometimes we
819 need to use ".4byte" and sometimes we need to use ".picptr".
820 See frv_assemble_integer for details. */
821 if (flag_pic || TARGET_FDPIC)
822 targetm.asm_out.unaligned_op.si = 0;
824 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
825 target_flags |= MASK_LINKED_FP;
827 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
828 target_flags |= MASK_OPTIMIZE_MEMBAR;
830 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
831 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
833 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
834 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
836 init_machine_status = frv_init_machine_status;
840 /* Some machines may desire to change what optimizations are performed for
841 various optimization levels. This macro, if defined, is executed once just
842 after the optimization level is determined and before the remainder of the
843 command options have been parsed. Values set in this macro are used as the
844 default values for the other command line options.
846 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
847 `-O' is specified, and 0 if neither is specified.
849 SIZE is nonzero if `-Os' is specified, 0 otherwise.
851 You should not use this macro to change options that are not
852 machine-specific. These should uniformly selected by the same optimization
853 level on all supported machines. Use this macro to enable machine-specific
856 *Do not examine `write_symbols' in this macro!* The debugging options are
857 *not supposed to alter the generated code. */
859 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
860 scheduling pass at the current time. */
862 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
866 #ifdef DISABLE_SCHED2
867 flag_schedule_insns_after_reload = 0;
876 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
879 frv_string_begins_with (const_tree name, const char *prefix)
881 const int prefix_len = strlen (prefix);
883 /* Remember: NAME's length includes the null terminator. */
884 return (TREE_STRING_LENGTH (name) > prefix_len
885 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
888 /* Zero or more C statements that may conditionally modify two variables
889 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
890 been initialized from the two preceding macros.
892 This is necessary in case the fixed or call-clobbered registers depend on
895 You need not define this macro if it has no work to do.
897 If the usage of an entire class of registers depends on the target flags,
898 you may indicate this to GCC by using this macro to modify `fixed_regs' and
899 `call_used_regs' to 1 for each of the registers in the classes which should
900 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
901 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
903 (However, if this class is not included in `GENERAL_REGS' and all of the
904 insn patterns whose constraints permit this class are controlled by target
905 switches, then GCC will automatically avoid using these registers when the
906 target switches are opposed to them.) */
909 frv_conditional_register_usage (void)
913 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
914 fixed_regs[i] = call_used_regs[i] = 1;
916 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
917 fixed_regs[i] = call_used_regs[i] = 1;
919 /* Reserve the registers used for conditional execution. At present, we need
920 1 ICC and 1 ICR register. */
921 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
922 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
926 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
927 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
928 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
929 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
933 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
934 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
937 /* If -fpic, SDA_BASE_REG is the PIC register. */
938 if (g_switch_value == 0 && !flag_pic)
939 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
942 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
948 * Compute the stack frame layout
951 * +---------------+-----------------------+-----------------------+
952 * |Register |type |caller-save/callee-save|
953 * +---------------+-----------------------+-----------------------+
954 * |GR0 |Zero register | - |
955 * |GR1 |Stack pointer(SP) | - |
956 * |GR2 |Frame pointer(FP) | - |
957 * |GR3 |Hidden parameter | caller save |
958 * |GR4-GR7 | - | caller save |
959 * |GR8-GR13 |Argument register | caller save |
960 * |GR14-GR15 | - | caller save |
961 * |GR16-GR31 | - | callee save |
962 * |GR32-GR47 | - | caller save |
963 * |GR48-GR63 | - | callee save |
964 * |FR0-FR15 | - | caller save |
965 * |FR16-FR31 | - | callee save |
966 * |FR32-FR47 | - | caller save |
967 * |FR48-FR63 | - | callee save |
968 * +---------------+-----------------------+-----------------------+
972 * SP-> |-----------------------------------|
974 * |-----------------------------------|
975 * | Register save area |
976 * |-----------------------------------|
977 * | Local variable save area |
978 * FP-> |-----------------------------------|
980 * |-----------------------------------|
981 * | Hidden parameter save area |
982 * |-----------------------------------|
983 * | Return address(LR) storage area |
984 * |-----------------------------------|
985 * | Padding for alignment |
986 * |-----------------------------------|
987 * | Register argument area |
988 * OLD SP-> |-----------------------------------|
990 * |-----------------------------------|
993 * Argument area/Parameter area:
995 * When a function is called, this area is used for argument transfer. When
996 * the argument is set up by the caller function, this area is referred to as
997 * the argument area. When the argument is referenced by the callee function,
998 * this area is referred to as the parameter area. The area is allocated when
999 * all arguments cannot be placed on the argument register at the time of
1000 * argument transfer.
1002 * Register save area:
1004 * This is a register save area that must be guaranteed for the caller
1005 * function. This area is not secured when the register save operation is not
1008 * Local variable save area:
1010 * This is the area for local variables and temporary variables.
1014 * This area stores the FP value of the caller function.
1016 * Hidden parameter save area:
1018 * This area stores the start address of the return value storage
1019 * area for a struct/union return function.
1020 * When a struct/union is used as the return value, the caller
1021 * function stores the return value storage area start address in
1022 * register GR3 and passes it to the caller function.
1023 * The callee function interprets the address stored in the GR3
1024 * as the return value storage area start address.
1025 * When register GR3 needs to be saved into memory, the callee
1026 * function saves it in the hidden parameter save area. This
1027 * area is not secured when the save operation is not needed.
1029 * Return address(LR) storage area:
1031 * This area saves the LR. The LR stores the address of a return to the caller
1032 * function for the purpose of function calling.
1034 * Argument register area:
1036 * This area saves the argument register. This area is not secured when the
1037 * save operation is not needed.
1041 * Arguments, the count of which equals the count of argument registers (6
1042 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1043 * function. When a struct/union return function is called, the return value
1044 * area address is stored in register GR3. Arguments not placed in the
1045 * argument registers will be stored in the stack argument area for transfer
1046 * purposes. When an 8-byte type argument is to be delivered using registers,
1047 * it is divided into two and placed in two registers for transfer. When
1048 * argument registers must be saved to memory, the callee function secures an
1049 * argument register save area in the stack. In this case, a continuous
1050 * argument register save area must be established in the parameter area. The
1051 * argument register save area must be allocated as needed to cover the size of
1052 * the argument register to be saved. If the function has a variable count of
1053 * arguments, it saves all argument registers in the argument register save
1056 * Argument Extension Format:
1058 * When an argument is to be stored in the stack, its type is converted to an
1059 * extended type in accordance with the individual argument type. The argument
1060 * is freed by the caller function after the return from the callee function is
1063 * +-----------------------+---------------+------------------------+
1064 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1065 * +-----------------------+---------------+------------------------+
1067 * |signed char |int | 4 |
1068 * |unsigned char |int | 4 |
1069 * |[signed] short int |int | 4 |
1070 * |unsigned short int |int | 4 |
1071 * |[signed] int |No extension | 4 |
1072 * |unsigned int |No extension | 4 |
1073 * |[signed] long int |No extension | 4 |
1074 * |unsigned long int |No extension | 4 |
1075 * |[signed] long long int |No extension | 8 |
1076 * |unsigned long long int |No extension | 8 |
1077 * |float |double | 8 |
1078 * |double |No extension | 8 |
1079 * |long double |No extension | 8 |
1080 * |pointer |No extension | 4 |
1081 * |struct/union |- | 4 (*1) |
1082 * +-----------------------+---------------+------------------------+
1084 * When a struct/union is to be delivered as an argument, the caller copies it
1085 * to the local variable area and delivers the address of that area.
1089 * +-------------------------------+----------------------+
1090 * |Return Value Type |Return Value Interface|
1091 * +-------------------------------+----------------------+
1093 * |[signed|unsigned] char |GR8 |
1094 * |[signed|unsigned] short int |GR8 |
1095 * |[signed|unsigned] int |GR8 |
1096 * |[signed|unsigned] long int |GR8 |
1098 * |[signed|unsigned] long long int|GR8 & GR9 |
1100 * |double |GR8 & GR9 |
1101 * |long double |GR8 & GR9 |
1102 * |struct/union |(*1) |
1103 * +-------------------------------+----------------------+
1105 * When a struct/union is used as the return value, the caller function stores
1106 * the start address of the return value storage area into GR3 and then passes
1107 * it to the callee function. The callee function interprets GR3 as the start
1108 * address of the return value storage area. When this address needs to be
1109 * saved in memory, the callee function secures the hidden parameter save area
1110 * and saves the address in that area.
1114 frv_stack_info (void)
1116 static frv_stack_t info, zero_info;
1117 frv_stack_t *info_ptr = &info;
1118 tree fndecl = current_function_decl;
1126 /* If we've already calculated the values and reload is complete,
1128 if (frv_stack_cache)
1129 return frv_stack_cache;
1131 /* Zero all fields. */
1134 /* Set up the register range information. */
1135 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1136 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1137 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1138 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1140 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1141 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1142 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1143 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1145 info_ptr->regs[STACK_REGS_LR].name = "lr";
1146 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1147 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1148 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1150 info_ptr->regs[STACK_REGS_CC].name = "cc";
1151 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1152 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1153 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1155 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1156 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1157 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1159 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1160 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1161 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1162 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1163 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1165 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1166 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1167 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1168 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1170 info_ptr->regs[STACK_REGS_FP].name = "fp";
1171 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1172 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1173 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1175 /* Determine if this is a stdarg function. If so, allocate space to store
1182 /* Find the last argument, and see if it is __builtin_va_alist. */
1183 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1185 next_arg = DECL_CHAIN (cur_arg);
1186 if (next_arg == (tree)0)
1188 if (DECL_NAME (cur_arg)
1189 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1197 /* Iterate over all of the register ranges. */
1198 for (range = 0; range < STACK_REGS_MAX; range++)
1200 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1201 int first = reg_ptr->first;
1202 int last = reg_ptr->last;
1204 int size_2words = 0;
1207 /* Calculate which registers need to be saved & save area size. */
1211 for (regno = first; regno <= last; regno++)
1213 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1214 || (crtl->calls_eh_return
1215 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1216 || (!TARGET_FDPIC && flag_pic
1217 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1219 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1220 size_1word += UNITS_PER_WORD;
1225 /* Calculate whether we need to create a frame after everything else
1226 has been processed. */
1231 if (df_regs_ever_live_p (LR_REGNO)
1233 /* This is set for __builtin_return_address, etc. */
1234 || cfun->machine->frame_needed
1235 || (TARGET_LINKED_FP && frame_pointer_needed)
1236 || (!TARGET_FDPIC && flag_pic
1237 && crtl->uses_pic_offset_table))
1239 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1240 size_1word += UNITS_PER_WORD;
1244 case STACK_REGS_STDARG:
1247 /* If this is a stdarg function with a non varardic
1248 argument split between registers and the stack,
1249 adjust the saved registers downward. */
1250 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1253 for (regno = first; regno <= last; regno++)
1255 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1256 size_1word += UNITS_PER_WORD;
1259 info_ptr->stdarg_size = size_1word;
1263 case STACK_REGS_STRUCT:
1264 if (cfun->returns_struct)
1266 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1267 size_1word += UNITS_PER_WORD;
1275 /* If this is a field, it only takes one word. */
1276 if (reg_ptr->field_p)
1277 size_1word = UNITS_PER_WORD;
1279 /* Determine which register pairs can be saved together. */
1280 else if (reg_ptr->dword_p && TARGET_DWORD)
1282 for (regno = first; regno < last; regno += 2)
1284 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1286 size_2words += 2 * UNITS_PER_WORD;
1287 size_1word -= 2 * UNITS_PER_WORD;
1288 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1289 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1294 reg_ptr->size_1word = size_1word;
1295 reg_ptr->size_2words = size_2words;
1297 if (! reg_ptr->special_p)
1299 info_ptr->regs_size_1word += size_1word;
1300 info_ptr->regs_size_2words += size_2words;
1305 /* Set up the sizes of each each field in the frame body, making the sizes
1306 of each be divisible by the size of a dword if dword operations might
1307 be used, or the size of a word otherwise. */
1308 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1310 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1311 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1312 + info_ptr->regs_size_1word,
1314 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1316 info_ptr->pretend_size = crtl->args.pretend_args_size;
1318 /* Work out the size of the frame, excluding the header. Both the frame
1319 body and register parameter area will be dword-aligned. */
1320 info_ptr->total_size
1321 = (ADDR_ALIGN (info_ptr->parameter_size
1322 + info_ptr->regs_size
1323 + info_ptr->vars_size,
1325 + ADDR_ALIGN (info_ptr->pretend_size
1326 + info_ptr->stdarg_size,
1327 2 * UNITS_PER_WORD));
1329 /* See if we need to create a frame at all, if so add header area. */
1330 if (info_ptr->total_size > 0
1331 || frame_pointer_needed
1332 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1333 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1335 offset = info_ptr->parameter_size;
1336 info_ptr->header_size = 4 * UNITS_PER_WORD;
1337 info_ptr->total_size += 4 * UNITS_PER_WORD;
1339 /* Calculate the offsets to save normal register pairs. */
1340 for (range = 0; range < STACK_REGS_MAX; range++)
1342 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1343 if (! reg_ptr->special_p)
1345 int first = reg_ptr->first;
1346 int last = reg_ptr->last;
1349 for (regno = first; regno <= last; regno++)
1350 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1351 && regno != FRAME_POINTER_REGNUM
1352 && (regno < FIRST_ARG_REGNUM
1353 || regno > LAST_ARG_REGNUM))
1355 info_ptr->reg_offset[regno] = offset;
1356 offset += 2 * UNITS_PER_WORD;
1361 /* Calculate the offsets to save normal single registers. */
1362 for (range = 0; range < STACK_REGS_MAX; range++)
1364 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1365 if (! reg_ptr->special_p)
1367 int first = reg_ptr->first;
1368 int last = reg_ptr->last;
1371 for (regno = first; regno <= last; regno++)
1372 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1373 && regno != FRAME_POINTER_REGNUM
1374 && (regno < FIRST_ARG_REGNUM
1375 || regno > LAST_ARG_REGNUM))
1377 info_ptr->reg_offset[regno] = offset;
1378 offset += UNITS_PER_WORD;
1383 /* Calculate the offset to save the local variables at. */
1384 offset = ADDR_ALIGN (offset, alignment);
1385 if (info_ptr->vars_size)
1387 info_ptr->vars_offset = offset;
1388 offset += info_ptr->vars_size;
1391 /* Align header to a dword-boundary. */
1392 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1394 /* Calculate the offsets in the fixed frame. */
1395 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1396 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1397 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1399 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1400 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1401 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1403 if (cfun->returns_struct)
1405 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1406 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1407 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1410 /* Calculate the offsets to store the arguments passed in registers
1411 for stdarg functions. The register pairs are first and the single
1412 register if any is last. The register save area starts on a
1414 if (info_ptr->stdarg_size)
1416 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1417 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1420 /* Skip the header. */
1421 offset += 4 * UNITS_PER_WORD;
1422 for (regno = first; regno <= last; regno++)
1424 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1426 info_ptr->reg_offset[regno] = offset;
1427 offset += 2 * UNITS_PER_WORD;
1429 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1431 info_ptr->reg_offset[regno] = offset;
1432 offset += UNITS_PER_WORD;
1438 if (reload_completed)
1439 frv_stack_cache = info_ptr;
1445 /* Print the information about the frv stack offsets, etc. when debugging. */
1448 frv_debug_stack (frv_stack_t *info)
1453 info = frv_stack_info ();
1455 fprintf (stderr, "\nStack information for function %s:\n",
1456 ((current_function_decl && DECL_NAME (current_function_decl))
1457 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1460 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1461 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1462 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1463 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1464 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1466 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1467 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1468 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1469 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1471 for (range = 0; range < STACK_REGS_MAX; range++)
1473 frv_stack_regs_t *regs = &(info->regs[range]);
1474 if ((regs->size_1word + regs->size_2words) > 0)
1476 int first = regs->first;
1477 int last = regs->last;
1480 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1481 regs->name, regs->size_1word + regs->size_2words,
1482 regs->size_1word, regs->size_2words);
1484 for (regno = first; regno <= last; regno++)
1486 if (info->save_p[regno] == REG_SAVE_1WORD)
1487 fprintf (stderr, " %s (%d)", reg_names[regno],
1488 info->reg_offset[regno]);
1490 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1491 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1492 reg_names[regno+1], info->reg_offset[regno]);
1495 fputc ('\n', stderr);
1505 /* Used during final to control the packing of insns. The value is
1506 1 if the current instruction should be packed with the next one,
1507 0 if it shouldn't or -1 if packing is disabled altogether. */
1509 static int frv_insn_packing_flag;
1511 /* True if the current function contains a far jump. */
1514 frv_function_contains_far_jump (void)
1516 rtx insn = get_insns ();
1518 && !(GET_CODE (insn) == JUMP_INSN
1519 /* Ignore tablejump patterns. */
1520 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1521 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1522 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1523 insn = NEXT_INSN (insn);
1524 return (insn != NULL);
1527 /* For the FRV, this function makes sure that a function with far jumps
1528 will return correctly. It also does the VLIW packing. */
1531 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1533 /* If no frame was created, check whether the function uses a call
1534 instruction to implement a far jump. If so, save the link in gr3 and
1535 replace all returns to LR with returns to GR3. GR3 is used because it
1536 is call-clobbered, because is not available to the register allocator,
1537 and because all functions that take a hidden argument pointer will have
1539 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1543 /* Just to check that the above comment is true. */
1544 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1546 /* Generate the instruction that saves the link register. */
1547 fprintf (file, "\tmovsg lr,gr3\n");
1549 /* Replace the LR with GR3 in *return_internal patterns. The insn
1550 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1551 simply emit a different assembly directive because bralr and jmpl
1552 execute in different units. */
1553 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1554 if (GET_CODE (insn) == JUMP_INSN)
1556 rtx pattern = PATTERN (insn);
1557 if (GET_CODE (pattern) == PARALLEL
1558 && XVECLEN (pattern, 0) >= 2
1559 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1560 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1562 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1563 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1564 SET_REGNO (address, GPR_FIRST + 3);
1571 /* Allow the garbage collector to free the nops created by frv_reorg. */
1572 memset (frv_nops, 0, sizeof (frv_nops));
1576 /* Return the next available temporary register in a given class. */
1579 frv_alloc_temp_reg (
1580 frv_tmp_reg_t *info, /* which registers are available */
1581 enum reg_class rclass, /* register class desired */
1582 enum machine_mode mode, /* mode to allocate register with */
1583 int mark_as_used, /* register not available after allocation */
1584 int no_abort) /* return NULL instead of aborting */
1586 int regno = info->next_reg[ (int)rclass ];
1587 int orig_regno = regno;
1588 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1593 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1594 && TEST_HARD_REG_BIT (info->regs, regno))
1597 if (++regno >= FIRST_PSEUDO_REGISTER)
1599 if (regno == orig_regno)
1601 gcc_assert (no_abort);
1606 nr = HARD_REGNO_NREGS (regno, mode);
1607 info->next_reg[ (int)rclass ] = regno + nr;
1610 for (i = 0; i < nr; i++)
1611 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1613 return gen_rtx_REG (mode, regno);
1617 /* Return an rtx with the value OFFSET, which will either be a register or a
1618 signed 12-bit integer. It can be used as the second operand in an "add"
1619 instruction, or as the index in a load or store.
1621 The function returns a constant rtx if OFFSET is small enough, otherwise
1622 it loads the constant into register OFFSET_REGNO and returns that. */
1624 frv_frame_offset_rtx (int offset)
1626 rtx offset_rtx = GEN_INT (offset);
1627 if (IN_RANGE_P (offset, -2048, 2047))
1631 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1632 if (IN_RANGE_P (offset, -32768, 32767))
1633 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1636 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1637 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1643 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1644 prologue and epilogue uses such expressions to access the stack. */
1646 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1648 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1650 frv_frame_offset_rtx (offset)));
1653 /* Generate a frame-related expression:
1655 (set REG (mem (plus (sp) (const_int OFFSET)))).
1657 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1658 instructions. Marking the expressions as frame-related is superfluous if
1659 the note contains just a single set. But if the note contains a PARALLEL
1660 or SEQUENCE that has several sets, each set must be individually marked
1661 as frame-related. */
1663 frv_dwarf_store (rtx reg, int offset)
1665 rtx set = gen_rtx_SET (VOIDmode,
1666 gen_rtx_MEM (GET_MODE (reg),
1667 plus_constant (stack_pointer_rtx,
1670 RTX_FRAME_RELATED_P (set) = 1;
1674 /* Emit a frame-related instruction whose pattern is PATTERN. The
1675 instruction is the last in a sequence that cumulatively performs the
1676 operation described by DWARF_PATTERN. The instruction is marked as
1677 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1680 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1682 rtx insn = emit_insn (pattern);
1683 RTX_FRAME_RELATED_P (insn) = 1;
1684 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1689 /* Emit instructions that transfer REG to or from the memory location (sp +
1690 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1691 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1692 function to store registers and only the epilogue uses it to load them.
1694 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1695 The generated instruction will use BASE as its base register. BASE may
1696 simply be the stack pointer, but if several accesses are being made to a
1697 region far away from the stack pointer, it may be more efficient to set
1698 up a temporary instead.
1700 Store instructions will be frame-related and will be annotated with the
1701 overall effect of the store. Load instructions will be followed by a
1702 (use) to prevent later optimizations from zapping them.
1704 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1705 as a temporary in such cases. */
1707 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1709 enum machine_mode mode = GET_MODE (reg);
1710 rtx mem = frv_frame_mem (mode,
1712 stack_offset - accessor->base_offset);
1714 if (accessor->op == FRV_LOAD)
1716 if (SPR_P (REGNO (reg)))
1718 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1719 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1720 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1724 /* We cannot use reg+reg addressing for DImode access. */
1726 && GET_CODE (XEXP (mem, 0)) == PLUS
1727 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1728 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1730 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1731 rtx insn = emit_move_insn (temp,
1732 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1733 XEXP (XEXP (mem, 0), 1)));
1734 mem = gen_rtx_MEM (DImode, temp);
1736 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1742 if (SPR_P (REGNO (reg)))
1744 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1745 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1746 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1747 frv_dwarf_store (reg, stack_offset));
1749 else if (mode == DImode)
1751 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1752 with a separate save for each register. */
1753 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1754 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1755 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1756 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1758 /* Also we cannot use reg+reg addressing. */
1759 if (GET_CODE (XEXP (mem, 0)) == PLUS
1760 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1761 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1763 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1764 rtx insn = emit_move_insn (temp,
1765 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1766 XEXP (XEXP (mem, 0), 1)));
1767 mem = gen_rtx_MEM (DImode, temp);
1770 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1771 gen_rtx_PARALLEL (VOIDmode,
1772 gen_rtvec (2, set1, set2)));
1775 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1776 frv_dwarf_store (reg, stack_offset));
1780 /* A function that uses frv_frame_access to transfer a group of registers to
1781 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1782 is the stack information generated by frv_stack_info, and REG_SET is the
1783 number of the register set to transfer. */
1785 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1789 frv_stack_regs_t *regs_info;
1792 regs_info = &info->regs[reg_set];
1793 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1794 if (info->save_p[regno])
1795 frv_frame_access (accessor,
1796 info->save_p[regno] == REG_SAVE_2WORDS
1797 ? gen_rtx_REG (DImode, regno)
1798 : gen_rtx_REG (SImode, regno),
1799 info->reg_offset[regno]);
1802 /* Save or restore callee-saved registers that are kept outside the frame
1803 header. The function saves the registers if OP is FRV_STORE and restores
1804 them if OP is FRV_LOAD. INFO is the stack information generated by
1807 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1809 frv_frame_accessor_t accessor;
1812 accessor.base = stack_pointer_rtx;
1813 accessor.base_offset = 0;
1814 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1815 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1816 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1820 /* Called after register allocation to add any instructions needed for the
1821 prologue. Using a prologue insn is favored compared to putting all of the
1822 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1823 it allows the scheduler to intermix instructions with the saves of
1824 the caller saved registers. In some cases, it might be necessary
1825 to emit a barrier instruction as the last insn to prevent such
1828 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1829 so that the debug info generation code can handle them properly. */
1831 frv_expand_prologue (void)
1833 frv_stack_t *info = frv_stack_info ();
1834 rtx sp = stack_pointer_rtx;
1835 rtx fp = frame_pointer_rtx;
1836 frv_frame_accessor_t accessor;
1838 if (TARGET_DEBUG_STACK)
1839 frv_debug_stack (info);
1841 if (info->total_size == 0)
1844 /* We're interested in three areas of the frame here:
1846 A: the register save area
1848 C: the header after B
1850 If the frame pointer isn't used, we'll have to set up A, B and C
1851 using the stack pointer. If the frame pointer is used, we'll access
1855 B: set up using sp or a temporary (see below)
1858 We set up B using the stack pointer if the frame is small enough.
1859 Otherwise, it's more efficient to copy the old stack pointer into a
1860 temporary and use that.
1862 Note that it's important to make sure the prologue and epilogue use the
1863 same registers to access A and C, since doing otherwise will confuse
1864 the aliasing code. */
1866 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1867 isn't used, the same method will serve for C. */
1868 accessor.op = FRV_STORE;
1869 if (frame_pointer_needed && info->total_size > 2048)
1873 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1874 accessor.base_offset = info->total_size;
1875 insn = emit_insn (gen_movsi (accessor.base, sp));
1879 accessor.base = stack_pointer_rtx;
1880 accessor.base_offset = 0;
1883 /* Allocate the stack space. */
1885 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1886 rtx dwarf_offset = GEN_INT (-info->total_size);
1888 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1891 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1894 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1895 and point the new one to that location. */
1896 if (frame_pointer_needed)
1898 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1900 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1901 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1903 rtx asm_src = plus_constant (accessor.base,
1904 fp_offset - accessor.base_offset);
1905 rtx dwarf_src = plus_constant (sp, fp_offset);
1907 /* Store the old frame pointer at (sp + FP_OFFSET). */
1908 frv_frame_access (&accessor, fp, fp_offset);
1910 /* Set up the new frame pointer. */
1911 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1912 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1914 /* Access region C from the frame pointer. */
1916 accessor.base_offset = fp_offset;
1919 /* Set up region C. */
1920 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1921 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1922 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1924 /* Set up region A. */
1925 frv_frame_access_standard_regs (FRV_STORE, info);
1927 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1928 scheduler from moving loads before the stores saving the registers. */
1929 if (info->stdarg_size > 0)
1930 emit_insn (gen_blockage ());
1932 /* Set up pic register/small data register for this function. */
1933 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1934 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1935 gen_rtx_REG (Pmode, LR_REGNO),
1936 gen_rtx_REG (SImode, OFFSET_REGNO)));
1940 /* Under frv, all of the work is done via frv_expand_epilogue, but
1941 this function provides a convenient place to do cleanup. */
1944 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1945 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1947 frv_stack_cache = (frv_stack_t *)0;
1949 /* Zap last used registers for conditional execution. */
1950 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1952 /* Release the bitmap of created insns. */
1953 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1957 /* Called after register allocation to add any instructions needed for the
1958 epilogue. Using an epilogue insn is favored compared to putting all of the
1959 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1960 it allows the scheduler to intermix instructions with the saves of
1961 the caller saved registers. In some cases, it might be necessary
1962 to emit a barrier instruction as the last insn to prevent such
1966 frv_expand_epilogue (bool emit_return)
1968 frv_stack_t *info = frv_stack_info ();
1969 rtx fp = frame_pointer_rtx;
1970 rtx sp = stack_pointer_rtx;
1974 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1976 /* Restore the stack pointer to its original value if alloca or the like
1978 if (! current_function_sp_is_unchanging)
1979 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1981 /* Restore the callee-saved registers that were used in this function. */
1982 frv_frame_access_standard_regs (FRV_LOAD, info);
1984 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1985 no return instruction should be emitted. */
1986 if (info->save_p[LR_REGNO])
1991 /* Use the same method to access the link register's slot as we did in
1992 the prologue. In other words, use the frame pointer if available,
1993 otherwise use the stack pointer.
1995 LR_OFFSET is the offset of the link register's slot from the start
1996 of the frame and MEM is a memory rtx for it. */
1997 lr_offset = info->reg_offset[LR_REGNO];
1998 if (frame_pointer_needed)
1999 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
2001 mem = frv_frame_mem (Pmode, sp, lr_offset);
2003 /* Load the old link register into a GPR. */
2004 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
2005 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
2008 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
2010 /* Restore the old frame pointer. Emit a USE afterwards to make sure
2011 the load is preserved. */
2012 if (frame_pointer_needed)
2014 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
2018 /* Deallocate the stack frame. */
2019 if (info->total_size != 0)
2021 rtx offset = frv_frame_offset_rtx (info->total_size);
2022 emit_insn (gen_stack_adjust (sp, sp, offset));
2025 /* If this function uses eh_return, add the final stack adjustment now. */
2026 if (crtl->calls_eh_return)
2027 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2030 emit_jump_insn (gen_epilogue_return (return_addr));
2033 rtx lr = return_addr;
2035 if (REGNO (return_addr) != LR_REGNO)
2037 lr = gen_rtx_REG (Pmode, LR_REGNO);
2038 emit_move_insn (lr, return_addr);
2046 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2049 frv_asm_output_mi_thunk (FILE *file,
2050 tree thunk_fndecl ATTRIBUTE_UNUSED,
2051 HOST_WIDE_INT delta,
2052 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2055 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2056 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2057 const char *name_jmp = reg_names[JUMP_REGNO];
2058 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2060 /* Do the add using an addi if possible. */
2061 if (IN_RANGE_P (delta, -2048, 2047))
2062 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2065 const char *const name_add = reg_names[TEMP_REGNO];
2066 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2067 parallel, delta, name_add);
2068 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2070 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2075 const char *name_pic = reg_names[FDPIC_REGNO];
2076 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2080 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2081 assemble_name (file, name_func);
2082 fprintf (file, "),%s\n", name_jmp);
2084 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2085 assemble_name (file, name_func);
2086 fprintf (file, "),%s\n", name_jmp);
2088 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2092 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2093 assemble_name (file, name_func);
2094 fprintf (file, "\t)), %s\n", name_jmp);
2099 fprintf (file, "\tsethi%s #hi(", parallel);
2100 assemble_name (file, name_func);
2101 fprintf (file, "),%s\n", name_jmp);
2103 fprintf (file, "\tsetlo #lo(");
2104 assemble_name (file, name_func);
2105 fprintf (file, "),%s\n", name_jmp);
2109 /* Use JUMP_REGNO as a temporary PIC register. */
2110 const char *name_lr = reg_names[LR_REGNO];
2111 const char *name_gppic = name_jmp;
2112 const char *name_tmp = reg_names[TEMP_REGNO];
2114 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2115 fprintf (file, "\tcall 1f\n");
2116 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2117 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2118 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2119 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2120 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2122 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2123 assemble_name (file, name_func);
2124 fprintf (file, "),%s\n", name_tmp);
2126 fprintf (file, "\tsetlo #gprello(");
2127 assemble_name (file, name_func);
2128 fprintf (file, "),%s\n", name_tmp);
2130 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2133 /* Jump to the function address. */
2134 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2139 /* On frv, create a frame whenever we need to create stack. */
2142 frv_frame_pointer_required (void)
2144 /* If we forgoing the usual linkage requirements, we only need
2145 a frame pointer if the stack pointer might change. */
2146 if (!TARGET_LINKED_FP)
2147 return !current_function_sp_is_unchanging;
2149 if (! current_function_is_leaf)
2152 if (get_frame_size () != 0)
2158 if (!current_function_sp_is_unchanging)
2161 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2167 if (cfun->machine->frame_needed)
2174 /* Worker function for TARGET_CAN_ELIMINATE. */
2177 frv_can_eliminate (const int from, const int to)
2179 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2180 ? ! frame_pointer_needed
2184 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2185 initial difference between the specified pair of registers. This macro must
2186 be defined if `ELIMINABLE_REGS' is defined. */
2188 /* See frv_stack_info for more details on the frv stack frame. */
2191 frv_initial_elimination_offset (int from, int to)
2193 frv_stack_t *info = frv_stack_info ();
2196 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2197 ret = info->total_size - info->pretend_size;
2199 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2200 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2202 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2203 ret = (info->total_size
2204 - info->reg_offset[FRAME_POINTER_REGNUM]
2205 - info->pretend_size);
2210 if (TARGET_DEBUG_STACK)
2211 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2212 reg_names [from], reg_names[to], ret);
2218 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2221 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2222 enum machine_mode mode,
2223 tree type ATTRIBUTE_UNUSED,
2227 if (TARGET_DEBUG_ARG)
2229 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2230 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2234 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2237 frv_expand_builtin_saveregs (void)
2239 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2241 if (TARGET_DEBUG_ARG)
2242 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2245 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2249 /* Expand __builtin_va_start to do the va_start macro. */
2252 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2255 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2257 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2258 GEN_INT (UNITS_PER_WORD * num));
2260 if (TARGET_DEBUG_ARG)
2262 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2263 crtl->args.info, num);
2265 debug_rtx (nextarg);
2268 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2269 fold_convert (TREE_TYPE (valist),
2270 make_tree (sizetype, nextarg)));
2271 TREE_SIDE_EFFECTS (t) = 1;
2273 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2277 /* Expand a block move operation, and return 1 if successful. Return 0
2278 if we should let the compiler generate normal code.
2280 operands[0] is the destination
2281 operands[1] is the source
2282 operands[2] is the length
2283 operands[3] is the alignment */
2285 /* Maximum number of loads to do before doing the stores */
2286 #ifndef MAX_MOVE_REG
2287 #define MAX_MOVE_REG 4
2290 /* Maximum number of total loads to do. */
2291 #ifndef TOTAL_MOVE_REG
2292 #define TOTAL_MOVE_REG 8
2296 frv_expand_block_move (rtx operands[])
2298 rtx orig_dest = operands[0];
2299 rtx orig_src = operands[1];
2300 rtx bytes_rtx = operands[2];
2301 rtx align_rtx = operands[3];
2302 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2315 rtx stores[MAX_MOVE_REG];
2317 enum machine_mode mode;
2319 /* If this is not a fixed size move, just call memcpy. */
2323 /* This should be a fixed size alignment. */
2324 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2326 align = INTVAL (align_rtx);
2328 /* Anything to move? */
2329 bytes = INTVAL (bytes_rtx);
2333 /* Don't support real large moves. */
2334 if (bytes > TOTAL_MOVE_REG*align)
2337 /* Move the address into scratch registers. */
2338 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2339 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2341 num_reg = offset = 0;
2342 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2344 /* Calculate the correct offset for src/dest. */
2348 dest_addr = dest_reg;
2352 src_addr = plus_constant (src_reg, offset);
2353 dest_addr = plus_constant (dest_reg, offset);
2356 /* Generate the appropriate load and store, saving the stores
2358 if (bytes >= 4 && align >= 4)
2360 else if (bytes >= 2 && align >= 2)
2365 move_bytes = GET_MODE_SIZE (mode);
2366 tmp_reg = gen_reg_rtx (mode);
2367 src_mem = change_address (orig_src, mode, src_addr);
2368 dest_mem = change_address (orig_dest, mode, dest_addr);
2369 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2370 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2372 if (num_reg >= MAX_MOVE_REG)
2374 for (i = 0; i < num_reg; i++)
2375 emit_insn (stores[i]);
2380 for (i = 0; i < num_reg; i++)
2381 emit_insn (stores[i]);
2387 /* Expand a block clear operation, and return 1 if successful. Return 0
2388 if we should let the compiler generate normal code.
2390 operands[0] is the destination
2391 operands[1] is the length
2392 operands[3] is the alignment */
2395 frv_expand_block_clear (rtx operands[])
2397 rtx orig_dest = operands[0];
2398 rtx bytes_rtx = operands[1];
2399 rtx align_rtx = operands[3];
2400 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2409 enum machine_mode mode;
2411 /* If this is not a fixed size move, just call memcpy. */
2415 /* This should be a fixed size alignment. */
2416 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2418 align = INTVAL (align_rtx);
2420 /* Anything to move? */
2421 bytes = INTVAL (bytes_rtx);
2425 /* Don't support real large clears. */
2426 if (bytes > TOTAL_MOVE_REG*align)
2429 /* Move the address into a scratch register. */
2430 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2432 num_reg = offset = 0;
2433 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2435 /* Calculate the correct offset for src/dest. */
2436 dest_addr = ((offset == 0)
2438 : plus_constant (dest_reg, offset));
2440 /* Generate the appropriate store of gr0. */
2441 if (bytes >= 4 && align >= 4)
2443 else if (bytes >= 2 && align >= 2)
2448 clear_bytes = GET_MODE_SIZE (mode);
2449 dest_mem = change_address (orig_dest, mode, dest_addr);
2450 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2457 /* The following variable is used to output modifiers of assembler
2458 code of the current output insn. */
2460 static rtx *frv_insn_operands;
2462 /* The following function is used to add assembler insn code suffix .p
2463 if it is necessary. */
2466 frv_asm_output_opcode (FILE *f, const char *ptr)
2470 if (frv_insn_packing_flag <= 0)
2473 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2476 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2477 || (*ptr >= 'A' && *ptr <= 'Z')))
2479 int letter = *ptr++;
2482 frv_print_operand (f, frv_insn_operands [c], letter);
2483 while ((c = *ptr) >= '0' && c <= '9')
2495 /* Set up the packing bit for the current output insn. Note that this
2496 function is not called for asm insns. */
2499 frv_final_prescan_insn (rtx insn, rtx *opvec,
2500 int noperands ATTRIBUTE_UNUSED)
2504 if (frv_insn_packing_flag >= 0)
2506 frv_insn_operands = opvec;
2507 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2509 else if (recog_memoized (insn) >= 0
2510 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2511 /* Packing optimizations have been disabled, but INSN can only
2512 be issued in M1. Insert an mnop in M0. */
2513 fprintf (asm_out_file, "\tmnop.p\n");
2519 /* A C expression whose value is RTL representing the address in a stack frame
2520 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2521 an RTL expression for the address of the stack frame itself.
2523 If you don't define this macro, the default is to return the value of
2524 FRAMEADDR--that is, the stack frame address is also the address of the stack
2525 word that points to the previous frame. */
2527 /* The default is correct, but we need to make sure the frame gets created. */
2529 frv_dynamic_chain_address (rtx frame)
2531 cfun->machine->frame_needed = 1;
2536 /* A C expression whose value is RTL representing the value of the return
2537 address for the frame COUNT steps up from the current frame, after the
2538 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2539 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2542 The value of the expression must always be the correct address when COUNT is
2543 zero, but may be `NULL_RTX' if there is not way to determine the return
2544 address of other frames. */
2547 frv_return_addr_rtx (int count, rtx frame)
2551 cfun->machine->frame_needed = 1;
2552 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2555 /* Given a memory reference MEMREF, interpret the referenced memory as
2556 an array of MODE values, and return a reference to the element
2557 specified by INDEX. Assume that any pre-modification implicit in
2558 MEMREF has already happened.
2560 MEMREF must be a legitimate operand for modes larger than SImode.
2561 frv_legitimate_address_p forbids register+register addresses, which
2562 this function cannot handle. */
2564 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2566 rtx base = XEXP (memref, 0);
2567 if (GET_CODE (base) == PRE_MODIFY)
2568 base = XEXP (base, 0);
2569 return change_address (memref, mode,
2570 plus_constant (base, index * GET_MODE_SIZE (mode)));
2574 /* Print a memory address as an operand to reference that memory location. */
2576 frv_print_operand_address (FILE * stream, rtx x)
2578 if (GET_CODE (x) == MEM)
2581 switch (GET_CODE (x))
2584 fputs (reg_names [ REGNO (x)], stream);
2588 fprintf (stream, "%ld", (long) INTVAL (x));
2592 assemble_name (stream, XSTR (x, 0));
2597 output_addr_const (stream, x);
2601 /* Poorly constructed asm statements can trigger this alternative.
2602 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2603 frv_print_operand_memory_reference (stream, x, 0);
2610 fatal_insn ("bad insn to frv_print_operand_address:", x);
2615 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2617 int regno = true_regnum (x);
2619 fputs (reg_names[regno], stream);
2621 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2624 /* Print a memory reference suitable for the ld/st instructions. */
2627 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2629 struct frv_unspec unspec;
2633 switch (GET_CODE (x))
2640 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2642 x1 = XEXP (XEXP (x, 1), 1);
2652 if (GET_CODE (x0) == CONST_INT)
2660 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2669 else if (GET_CODE (x1) != CONST_INT)
2670 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2673 fputs ("@(", stream);
2675 fputs (reg_names[GPR_R0], stream);
2676 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2677 frv_print_operand_memory_reference_reg (stream, x0);
2679 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2681 fputs (",", stream);
2683 fputs (reg_names [GPR_R0], stream);
2687 switch (GET_CODE (x1))
2691 frv_print_operand_memory_reference_reg (stream, x1);
2695 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2699 if (!frv_const_unspec_p (x1, &unspec))
2700 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2701 frv_output_const_unspec (stream, &unspec);
2705 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2709 fputs (")", stream);
2713 /* Return 2 for likely branches and 0 for non-likely branches */
2715 #define FRV_JUMP_LIKELY 2
2716 #define FRV_JUMP_NOT_LIKELY 0
2719 frv_print_operand_jump_hint (rtx insn)
2724 HOST_WIDE_INT prob = -1;
2725 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2727 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2729 /* Assume any non-conditional jump is likely. */
2730 if (! any_condjump_p (insn))
2731 ret = FRV_JUMP_LIKELY;
2735 labelref = condjump_label (insn);
2738 rtx label = XEXP (labelref, 0);
2739 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2744 note = find_reg_note (insn, REG_BR_PROB, 0);
2746 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2750 prob = INTVAL (XEXP (note, 0));
2751 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2753 : FRV_JUMP_NOT_LIKELY);
2765 case UNKNOWN: direction = "unknown jump direction"; break;
2766 case BACKWARD: direction = "jump backward"; break;
2767 case FORWARD: direction = "jump forward"; break;
2771 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2772 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2773 (long)INSN_UID (insn), direction, (long)prob,
2774 (long)REG_BR_PROB_BASE, ret);
2782 /* Return the comparison operator to use for CODE given that the ICC
2786 comparison_string (enum rtx_code code, rtx op0)
2788 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2791 default: output_operand_lossage ("bad condition code");
2792 case EQ: return "eq";
2793 case NE: return "ne";
2794 case LT: return is_nz_p ? "n" : "lt";
2795 case LE: return "le";
2796 case GT: return "gt";
2797 case GE: return is_nz_p ? "p" : "ge";
2798 case LTU: return is_nz_p ? "no" : "c";
2799 case LEU: return is_nz_p ? "eq" : "ls";
2800 case GTU: return is_nz_p ? "ne" : "hi";
2801 case GEU: return is_nz_p ? "ra" : "nc";
2805 /* Print an operand to an assembler instruction.
2807 `%' followed by a letter and a digit says to output an operand in an
2808 alternate fashion. Four letters have standard, built-in meanings
2809 described below. The hook `TARGET_PRINT_OPERAND' can define
2810 additional letters with nonstandard meanings.
2812 `%cDIGIT' can be used to substitute an operand that is a constant value
2813 without the syntax that normally indicates an immediate operand.
2815 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2818 `%aDIGIT' can be used to substitute an operand as if it were a memory
2819 reference, with the actual operand treated as the address. This may be
2820 useful when outputting a "load address" instruction, because often the
2821 assembler syntax for such an instruction requires you to write the operand
2822 as if it were a memory reference.
2824 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2826 `%=' outputs a number which is unique to each instruction in the entire
2827 compilation. This is useful for making local labels to be referred to more
2828 than once in a single template that generates multiple assembler
2831 `%' followed by a punctuation character specifies a substitution that
2832 does not use an operand. Only one case is standard: `%%' outputs a
2833 `%' into the assembler code. Other nonstandard cases can be defined
2834 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2835 punctuation characters are valid with the
2836 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2839 frv_print_operand (FILE * file, rtx x, int code)
2841 struct frv_unspec unspec;
2842 HOST_WIDE_INT value;
2845 if (code != 0 && !ISALPHA (code))
2848 else if (GET_CODE (x) == CONST_INT)
2851 else if (GET_CODE (x) == CONST_DOUBLE)
2853 if (GET_MODE (x) == SFmode)
2858 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2859 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2863 else if (GET_MODE (x) == VOIDmode)
2864 value = CONST_DOUBLE_LOW (x);
2867 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2878 fputs (reg_names[GPR_R0], file);
2882 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2886 /* Output small data area base register (gr16). */
2887 fputs (reg_names[SDA_BASE_REG], file);
2891 /* Output pic register (gr17). */
2892 fputs (reg_names[PIC_REGNO], file);
2896 /* Output the temporary integer CCR register. */
2897 fputs (reg_names[ICR_TEMP], file);
2901 /* Output the temporary integer CC register. */
2902 fputs (reg_names[ICC_TEMP], file);
2905 /* case 'a': print an address. */
2908 /* Print appropriate test for integer branch false operation. */
2909 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2910 XEXP (x, 0)), file);
2914 /* Print appropriate test for integer branch true operation. */
2915 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2919 /* Print 1 for a NE and 0 for an EQ to give the final argument
2920 for a conditional instruction. */
2921 if (GET_CODE (x) == NE)
2924 else if (GET_CODE (x) == EQ)
2928 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2932 /* Print appropriate test for floating point branch false operation. */
2933 switch (GET_CODE (x))
2936 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2938 case EQ: fputs ("ne", file); break;
2939 case NE: fputs ("eq", file); break;
2940 case LT: fputs ("uge", file); break;
2941 case LE: fputs ("ug", file); break;
2942 case GT: fputs ("ule", file); break;
2943 case GE: fputs ("ul", file); break;
2948 /* Print appropriate test for floating point branch true operation. */
2949 switch (GET_CODE (x))
2952 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2954 case EQ: fputs ("eq", file); break;
2955 case NE: fputs ("ne", file); break;
2956 case LT: fputs ("lt", file); break;
2957 case LE: fputs ("le", file); break;
2958 case GT: fputs ("gt", file); break;
2959 case GE: fputs ("ge", file); break;
2964 /* Print appropriate GOT function. */
2965 if (GET_CODE (x) != CONST_INT)
2966 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2967 fputs (unspec_got_name (INTVAL (x)), file);
2971 /* Print 'i' if the operand is a constant, or is a memory reference that
2973 if (GET_CODE (x) == MEM)
2974 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2975 ? XEXP (XEXP (x, 0), 1)
2977 else if (GET_CODE (x) == PLUS)
2980 switch (GET_CODE (x))
2994 /* For jump instructions, print 'i' if the operand is a constant or
2995 is an expression that adds a constant. */
2996 if (GET_CODE (x) == CONST_INT)
3001 if (GET_CODE (x) == CONST_INT
3002 || (GET_CODE (x) == PLUS
3003 && (GET_CODE (XEXP (x, 1)) == CONST_INT
3004 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
3010 /* Print the lower register of a double word register pair */
3011 if (GET_CODE (x) == REG)
3012 fputs (reg_names[ REGNO (x)+1 ], file);
3014 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
3017 /* case 'l': print a LABEL_REF. */
3021 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
3022 for the second word of double memory operations. */
3023 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3024 switch (GET_CODE (x))
3027 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3030 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3038 frv_print_operand_memory_reference (file, x, offset);
3044 /* Print the opcode of a command. */
3045 switch (GET_CODE (x))
3048 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3050 case PLUS: fputs ("add", file); break;
3051 case MINUS: fputs ("sub", file); break;
3052 case AND: fputs ("and", file); break;
3053 case IOR: fputs ("or", file); break;
3054 case XOR: fputs ("xor", file); break;
3055 case ASHIFT: fputs ("sll", file); break;
3056 case ASHIFTRT: fputs ("sra", file); break;
3057 case LSHIFTRT: fputs ("srl", file); break;
3061 /* case 'n': negate and print a constant int. */
3064 /* Print PIC label using operand as the number. */
3065 if (GET_CODE (x) != CONST_INT)
3066 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3068 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3072 /* Print 'u' if the operand is a update load/store. */
3073 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3078 /* If value is 0, print gr0, otherwise it must be a register. */
3079 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3080 fputs (reg_names[GPR_R0], file);
3082 else if (GET_CODE (x) == REG)
3083 fputs (reg_names [REGNO (x)], file);
3086 fatal_insn ("bad insn in frv_print_operand, z case", x);
3090 /* Print constant in hex. */
3091 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3093 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3100 if (GET_CODE (x) == REG)
3101 fputs (reg_names [REGNO (x)], file);
3103 else if (GET_CODE (x) == CONST_INT
3104 || GET_CODE (x) == CONST_DOUBLE)
3105 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3107 else if (frv_const_unspec_p (x, &unspec))
3108 frv_output_const_unspec (file, &unspec);
3110 else if (GET_CODE (x) == MEM)
3111 frv_print_operand_address (file, XEXP (x, 0));
3113 else if (CONSTANT_ADDRESS_P (x))
3114 frv_print_operand_address (file, x);
3117 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3122 fatal_insn ("frv_print_operand: unknown code", x);
3130 frv_print_operand_punct_valid_p (unsigned char code)
3132 return (code == '.' || code == '#' || code == '@' || code == '~'
3133 || code == '*' || code == '&');
3137 /* A C statement (sans semicolon) for initializing the variable CUM for the
3138 state at the beginning of the argument list. The variable has type
3139 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3140 of the function which will receive the args, or 0 if the args are to a
3141 compiler support library function. The value of INDIRECT is nonzero when
3142 processing an indirect call, for example a call through a function pointer.
3143 The value of INDIRECT is zero for a call to an explicitly named function, a
3144 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3145 arguments for the function being compiled.
3147 When processing a call to a compiler support library function, LIBNAME
3148 identifies which one. It is a `symbol_ref' rtx which contains the name of
3149 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3150 being processed. Thus, each time this macro is called, either LIBNAME or
3151 FNTYPE is nonzero, but never both of them at once. */
3154 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3160 *cum = FIRST_ARG_REGNUM;
3162 if (TARGET_DEBUG_ARG)
3164 fprintf (stderr, "\ninit_cumulative_args:");
3165 if (!fndecl && fntype)
3166 fputs (" indirect", stderr);
3169 fputs (" incoming", stderr);
3173 tree ret_type = TREE_TYPE (fntype);
3174 fprintf (stderr, " return=%s,",
3175 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3178 if (libname && GET_CODE (libname) == SYMBOL_REF)
3179 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3181 if (cfun->returns_struct)
3182 fprintf (stderr, " return-struct");
3184 putc ('\n', stderr);
3189 /* Return true if we should pass an argument on the stack rather than
3193 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3195 if (mode == BLKmode)
3199 return AGGREGATE_TYPE_P (type);
3202 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3203 argument with the specified mode and type. If it is not defined,
3204 `PARM_BOUNDARY' is used for all arguments. */
3207 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3208 tree type ATTRIBUTE_UNUSED)
3210 return BITS_PER_WORD;
3214 frv_function_arg (CUMULATIVE_ARGS *cum,
3215 enum machine_mode mode,
3216 tree type ATTRIBUTE_UNUSED,
3218 int incoming ATTRIBUTE_UNUSED)
3220 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3225 /* Return a marker for use in the call instruction. */
3226 if (xmode == VOIDmode)
3232 else if (arg_num <= LAST_ARG_REGNUM)
3234 ret = gen_rtx_REG (xmode, arg_num);
3235 debstr = reg_names[arg_num];
3244 if (TARGET_DEBUG_ARG)
3246 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3247 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3253 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3254 advance past an argument in the argument list. The values MODE, TYPE and
3255 NAMED describe that argument. Once this is done, the variable CUM is
3256 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3258 This macro need not do anything if the argument in question was passed on
3259 the stack. The compiler knows how to track the amount of stack space used
3260 for arguments without any special help. */
3263 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3264 enum machine_mode mode,
3265 tree type ATTRIBUTE_UNUSED,
3268 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3269 int bytes = GET_MODE_SIZE (xmode);
3270 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3273 *cum = arg_num + words;
3275 if (TARGET_DEBUG_ARG)
3277 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3278 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3282 /* A C expression for the number of words, at the beginning of an argument,
3283 must be put in registers. The value must be zero for arguments that are
3284 passed entirely in registers or that are entirely pushed on the stack.
3286 On some machines, certain arguments must be passed partially in registers
3287 and partially in memory. On these machines, typically the first N words of
3288 arguments are passed in registers, and the rest on the stack. If a
3289 multi-word argument (a `double' or a structure) crosses that boundary, its
3290 first few words must be passed in registers and the rest must be pushed.
3291 This macro tells the compiler when this occurs, and how many of the words
3292 should go in registers.
3294 `FUNCTION_ARG' for these arguments should return the first register to be
3295 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3296 the called function. */
3299 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3300 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3302 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3303 int bytes = GET_MODE_SIZE (xmode);
3304 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3308 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3309 ? LAST_ARG_REGNUM - arg_num + 1
3311 ret *= UNITS_PER_WORD;
3313 if (TARGET_DEBUG_ARG && ret)
3314 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3320 /* Implements TARGET_FUNCTION_VALUE. */
3323 frv_function_value (const_tree valtype,
3324 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3325 bool outgoing ATTRIBUTE_UNUSED)
3327 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3331 /* Implements TARGET_LIBCALL_VALUE. */
3334 frv_libcall_value (enum machine_mode mode,
3335 const_rtx fun ATTRIBUTE_UNUSED)
3337 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3341 /* Implements FUNCTION_VALUE_REGNO_P. */
3344 frv_function_value_regno_p (const unsigned int regno)
3346 return (regno == RETURN_VALUE_REGNUM);
3349 /* Return true if a register is ok to use as a base or index register. */
3351 static FRV_INLINE int
3352 frv_regno_ok_for_base_p (int regno, int strict_p)
3358 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3360 if (regno == ARG_POINTER_REGNUM)
3363 return (regno >= FIRST_PSEUDO_REGISTER);
3367 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3368 RTX) is a legitimate memory address on the target machine for a memory
3369 operand of mode MODE.
3371 It usually pays to define several simpler macros to serve as subroutines for
3372 this one. Otherwise it may be too complicated to understand.
3374 This macro must exist in two variants: a strict variant and a non-strict
3375 one. The strict variant is used in the reload pass. It must be defined so
3376 that any pseudo-register that has not been allocated a hard register is
3377 considered a memory reference. In contexts where some kind of register is
3378 required, a pseudo-register with no hard register must be rejected.
3380 The non-strict variant is used in other passes. It must be defined to
3381 accept all pseudo-registers in every context where some kind of register is
3384 Compiler source files that want to use the strict variant of this macro
3385 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3386 conditional to define the strict variant in that case and the non-strict
3389 Normally, constant addresses which are the sum of a `symbol_ref' and an
3390 integer are stored inside a `const' RTX to mark them as constant.
3391 Therefore, there is no need to recognize such sums specifically as
3392 legitimate addresses. Normally you would simply recognize any `const' as
3395 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3396 constant sums that are not marked with `const'. It assumes that a
3397 naked `plus' indicates indexing. If so, then you *must* reject such
3398 naked constant sums as illegitimate addresses, so that none of them
3399 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3402 frv_legitimate_address_p_1 (enum machine_mode mode,
3406 int allow_double_reg_p)
3410 HOST_WIDE_INT value;
3413 if (FRV_SYMBOL_REF_TLS_P (x))
3416 switch (GET_CODE (x))
3423 if (GET_CODE (x) != REG)
3429 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3435 if (GET_CODE (x0) != REG
3436 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3437 || GET_CODE (x1) != PLUS
3438 || ! rtx_equal_p (x0, XEXP (x1, 0))
3439 || GET_CODE (XEXP (x1, 1)) != REG
3440 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3447 /* 12-bit immediate */
3452 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3454 /* If we can't use load/store double operations, make sure we can
3455 address the second word. */
3456 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3457 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3466 if (GET_CODE (x0) == SUBREG)
3467 x0 = SUBREG_REG (x0);
3469 if (GET_CODE (x0) != REG)
3472 regno0 = REGNO (x0);
3473 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3476 switch (GET_CODE (x1))
3482 x1 = SUBREG_REG (x1);
3483 if (GET_CODE (x1) != REG)
3489 /* Do not allow reg+reg addressing for modes > 1 word if we
3490 can't depend on having move double instructions. */
3491 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3494 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3498 /* 12-bit immediate */
3503 value = INTVAL (x1);
3504 ret = IN_RANGE_P (value, -2048, 2047);
3506 /* If we can't use load/store double operations, make sure we can
3507 address the second word. */
3508 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3509 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3514 if (!condexec_p && got12_operand (x1, VOIDmode))
3522 if (TARGET_DEBUG_ADDR)
3524 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3525 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3526 (condexec_p) ? ", inside conditional code" : "");
3534 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3536 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3539 /* Given an ADDR, generate code to inline the PLT. */
3541 gen_inlined_tls_plt (rtx addr)
3544 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3547 dest = gen_reg_rtx (DImode);
3554 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3555 calll #gettlsoff(ADDR)@(gr8, gr0)
3557 emit_insn (gen_tls_lddi (dest, addr, picreg));
3564 sethi.p #gottlsdeschi(ADDR), gr8
3565 setlo #gottlsdesclo(ADDR), gr8
3566 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3567 calll #gettlsoff(ADDR)@(gr8, gr0)
3569 rtx reguse = gen_reg_rtx (Pmode);
3570 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3571 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3574 retval = gen_reg_rtx (Pmode);
3575 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3579 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3580 the destination address. */
3582 gen_tlsmoff (rtx addr, rtx reg)
3584 rtx dest = gen_reg_rtx (Pmode);
3588 /* sethi.p #tlsmoffhi(x), grA
3589 setlo #tlsmofflo(x), grA
3591 dest = gen_reg_rtx (Pmode);
3592 emit_insn (gen_tlsoff_hilo (dest, addr,
3593 GEN_INT (R_FRV_TLSMOFFHI)));
3594 dest = gen_rtx_PLUS (Pmode, dest, reg);
3598 /* addi grB, #tlsmoff12(x), grC
3600 ld/st @(grB, #tlsmoff12(x)), grC
3602 dest = gen_reg_rtx (Pmode);
3603 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3604 GEN_INT (R_FRV_TLSMOFF12)));
3609 /* Generate code for a TLS address. */
3611 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3613 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3614 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3618 case TLS_MODEL_INITIAL_EXEC:
3622 ldi @(gr15, #gottlsoff12(x)), gr5
3624 dest = gen_reg_rtx (Pmode);
3625 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3626 dest = gen_rtx_PLUS (Pmode, tp, dest);
3630 /* -fPIC or anything else.
3632 sethi.p #gottlsoffhi(x), gr14
3633 setlo #gottlsofflo(x), gr14
3634 ld #tlsoff(x)@(gr15, gr14), gr9
3636 rtx tmp = gen_reg_rtx (Pmode);
3637 dest = gen_reg_rtx (Pmode);
3638 emit_insn (gen_tlsoff_hilo (tmp, addr,
3639 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3641 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3642 dest = gen_rtx_PLUS (Pmode, tp, dest);
3645 case TLS_MODEL_LOCAL_DYNAMIC:
3649 if (TARGET_INLINE_PLT)
3650 retval = gen_inlined_tls_plt (GEN_INT (0));
3653 /* call #gettlsoff(0) */
3654 retval = gen_reg_rtx (Pmode);
3655 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3658 reg = gen_reg_rtx (Pmode);
3659 emit_insn (gen_rtx_SET (VOIDmode, reg,
3660 gen_rtx_PLUS (Pmode,
3663 dest = gen_tlsmoff (addr, reg);
3666 dest = gen_reg_rtx (Pmode);
3667 emit_insn (gen_tlsoff_hilo (dest, addr,
3668 GEN_INT (R_FRV_TLSMOFFHI)));
3669 dest = gen_rtx_PLUS (Pmode, dest, reg);
3673 case TLS_MODEL_LOCAL_EXEC:
3674 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3676 case TLS_MODEL_GLOBAL_DYNAMIC:
3680 if (TARGET_INLINE_PLT)
3681 retval = gen_inlined_tls_plt (addr);
3684 /* call #gettlsoff(x) */
3685 retval = gen_reg_rtx (Pmode);
3686 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3688 dest = gen_rtx_PLUS (Pmode, retval, tp);
3699 frv_legitimize_address (rtx x,
3700 rtx oldx ATTRIBUTE_UNUSED,
3701 enum machine_mode mode ATTRIBUTE_UNUSED)
3703 if (GET_CODE (x) == SYMBOL_REF)
3705 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3707 return frv_legitimize_tls_address (x, model);
3713 /* Test whether a local function descriptor is canonical, i.e.,
3714 whether we can use FUNCDESC_GOTOFF to compute the address of the
3718 frv_local_funcdesc_p (rtx fnx)
3721 enum symbol_visibility vis;
3724 if (! SYMBOL_REF_LOCAL_P (fnx))
3727 fn = SYMBOL_REF_DECL (fnx);
3732 vis = DECL_VISIBILITY (fn);
3734 if (vis == VISIBILITY_PROTECTED)
3735 /* Private function descriptors for protected functions are not
3736 canonical. Temporarily change the visibility to global. */
3737 vis = VISIBILITY_DEFAULT;
3738 else if (flag_shlib)
3739 /* If we're already compiling for a shared library (that, unlike
3740 executables, can't assume that the existence of a definition
3741 implies local binding), we can skip the re-testing. */
3744 ret = default_binds_local_p_1 (fn, flag_pic);
3746 DECL_VISIBILITY (fn) = vis;
3751 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3755 frv_gen_GPsym2reg (rtx dest, rtx src)
3757 tree gp = get_identifier ("_gp");
3758 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3760 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3764 unspec_got_name (int i)
3768 case R_FRV_GOT12: return "got12";
3769 case R_FRV_GOTHI: return "gothi";
3770 case R_FRV_GOTLO: return "gotlo";
3771 case R_FRV_FUNCDESC: return "funcdesc";
3772 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3773 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3774 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3775 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3776 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3777 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3778 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3779 case R_FRV_GOTOFF12: return "gotoff12";
3780 case R_FRV_GOTOFFHI: return "gotoffhi";
3781 case R_FRV_GOTOFFLO: return "gotofflo";
3782 case R_FRV_GPREL12: return "gprel12";
3783 case R_FRV_GPRELHI: return "gprelhi";
3784 case R_FRV_GPRELLO: return "gprello";
3785 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3786 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3787 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3788 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3789 case R_FRV_TLSMOFF12: return "tlsmoff12";
3790 case R_FRV_TLSDESCHI: return "tlsdeschi";
3791 case R_FRV_TLSDESCLO: return "tlsdesclo";
3792 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3793 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3794 default: gcc_unreachable ();
3798 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3799 is added inside the relocation operator. */
3802 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3804 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3805 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3806 fputs (")", stream);
3809 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3810 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3811 otherwise return ORIG_X. */
3814 frv_find_base_term (rtx x)
3816 struct frv_unspec unspec;
3818 if (frv_const_unspec_p (x, &unspec)
3819 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3820 return plus_constant (unspec.symbol, unspec.offset);
3825 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3826 the operand is used by a predicated instruction. */
3829 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3831 return ((GET_MODE (op) == mode || mode == VOIDmode)
3832 && GET_CODE (op) == MEM
3833 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3834 reload_completed, condexec_p, FALSE));
3838 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3840 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3841 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3847 rvrtx = operands[0];
3851 addr = XEXP (operands[0], 0);
3853 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3854 any calls that would involve a PLT, but can't tell, since we
3855 don't know whether an extern function is going to be provided by
3856 a separate translation unit or imported from a separate module.
3857 When compiling for shared libraries, if the function has default
3858 visibility, we assume it's overridable, so we inline the PLT, but
3859 for executables, we don't really have a way to make a good
3860 decision: a function is as likely to be imported from a shared
3861 library as it is to be defined in the executable itself. We
3862 assume executables will get global functions defined locally,
3863 whereas shared libraries will have them potentially overridden,
3864 so we only inline PLTs when compiling for shared libraries.
3866 In order to mark a function as local to a shared library, any
3867 non-default visibility attribute suffices. Unfortunately,
3868 there's no simple way to tag a function declaration as ``in a
3869 different module'', which we could then use to trigger PLT
3870 inlining on executables. There's -minline-plt, but it affects
3871 all external functions, so one would have to also mark function
3872 declarations available in the same module with non-default
3873 visibility, which is advantageous in itself. */
3874 if (GET_CODE (addr) == SYMBOL_REF
3875 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3879 dest = gen_reg_rtx (SImode);
3881 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3882 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3884 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3885 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3887 crtl->uses_pic_offset_table = TRUE;
3890 else if (GET_CODE (addr) == SYMBOL_REF)
3892 /* These are always either local, or handled through a local
3895 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3896 operands[2], picreg, lr);
3898 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3902 else if (! ldd_address_operand (addr, Pmode))
3903 addr = force_reg (Pmode, addr);
3905 picreg = gen_reg_rtx (DImode);
3906 emit_insn (gen_movdi_ldd (picreg, addr));
3908 if (sibcall && ret_value)
3909 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3911 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3913 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3915 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3919 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3920 process these separately from any offsets, such that we add any
3921 offsets to the function descriptor (the actual pointer), not to the
3922 function address. */
3925 frv_function_symbol_referenced_p (rtx x)
3931 if (GET_CODE (x) == SYMBOL_REF)
3932 return SYMBOL_REF_FUNCTION_P (x);
3934 length = GET_RTX_LENGTH (GET_CODE (x));
3935 format = GET_RTX_FORMAT (GET_CODE (x));
3937 for (j = 0; j < length; ++j)
3942 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3948 if (XVEC (x, j) != 0)
3951 for (k = 0; k < XVECLEN (x, j); ++k)
3952 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3958 /* Nothing to do. */
3966 /* Return true if the memory operand is one that can be conditionally
3970 condexec_memory_operand (rtx op, enum machine_mode mode)
3972 enum machine_mode op_mode = GET_MODE (op);
3975 if (mode != VOIDmode && op_mode != mode)
3990 if (GET_CODE (op) != MEM)
3993 addr = XEXP (op, 0);
3994 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3997 /* Return true if the bare return instruction can be used outside of the
3998 epilog code. For frv, we only do it if there was no stack allocation. */
4001 direct_return_p (void)
4005 if (!reload_completed)
4008 info = frv_stack_info ();
4009 return (info->total_size == 0);
4014 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
4016 if (GET_CODE (src) == SYMBOL_REF)
4018 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
4020 src = frv_legitimize_tls_address (src, model);
4026 if (frv_emit_movsi (dest, src))
4035 if (!reload_in_progress
4036 && !reload_completed
4037 && !register_operand (dest, mode)
4038 && !reg_or_0_operand (src, mode))
4039 src = copy_to_mode_reg (mode, src);
4046 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4049 /* Emit code to handle a MOVSI, adding in the small data register or pic
4050 register if needed to load up addresses. Return TRUE if the appropriate
4051 instructions are emitted. */
4054 frv_emit_movsi (rtx dest, rtx src)
4056 int base_regno = -1;
4059 struct frv_unspec old_unspec;
4061 if (!reload_in_progress
4062 && !reload_completed
4063 && !register_operand (dest, SImode)
4064 && (!reg_or_0_operand (src, SImode)
4065 /* Virtual registers will almost always be replaced by an
4066 add instruction, so expose this to CSE by copying to
4067 an intermediate register. */
4068 || (GET_CODE (src) == REG
4069 && IN_RANGE_P (REGNO (src),
4070 FIRST_VIRTUAL_REGISTER,
4071 LAST_VIRTUAL_REGISTER))))
4073 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4077 /* Explicitly add in the PIC or small data register if needed. */
4078 switch (GET_CODE (src))
4087 /* Using GPREL12, we use a single GOT entry for all symbols
4088 in read-only sections, but trade sequences such as:
4090 sethi #gothi(label), gr#
4091 setlo #gotlo(label), gr#
4096 ld @(gr15,#got12(_gp)), gr#
4097 sethi #gprelhi(label), gr##
4098 setlo #gprello(label), gr##
4101 We may often be able to share gr# for multiple
4102 computations of GPREL addresses, and we may often fold
4103 the final add into the pair of registers of a load or
4104 store instruction, so it's often profitable. Even when
4105 optimizing for size, we're trading a GOT entry for an
4106 additional instruction, which trades GOT space
4107 (read-write) for code size (read-only, shareable), as
4108 long as the symbol is not used in more than two different
4111 With -fpie/-fpic, we'd be trading a single load for a
4112 sequence of 4 instructions, because the offset of the
4113 label can't be assumed to be addressable with 12 bits, so
4114 we don't do this. */
4115 if (TARGET_GPREL_RO)
4116 unspec = R_FRV_GPREL12;
4118 unspec = R_FRV_GOT12;
4121 base_regno = PIC_REGNO;
4126 if (frv_const_unspec_p (src, &old_unspec))
4129 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4132 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4133 emit_move_insn (dest, src);
4138 sym = XEXP (sym, 0);
4139 if (GET_CODE (sym) == PLUS
4140 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4141 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4142 sym = XEXP (sym, 0);
4143 if (GET_CODE (sym) == SYMBOL_REF)
4145 else if (GET_CODE (sym) == LABEL_REF)
4148 goto handle_whatever;
4156 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4160 src = frv_legitimize_tls_address (src, model);
4161 emit_move_insn (dest, src);
4165 if (SYMBOL_REF_FUNCTION_P (sym))
4167 if (frv_local_funcdesc_p (sym))
4168 unspec = R_FRV_FUNCDESC_GOTOFF12;
4170 unspec = R_FRV_FUNCDESC_GOT12;
4174 if (CONSTANT_POOL_ADDRESS_P (sym))
4175 switch (GET_CODE (get_pool_constant (sym)))
4182 unspec = R_FRV_GOTOFF12;
4187 if (TARGET_GPREL_RO)
4188 unspec = R_FRV_GPREL12;
4190 unspec = R_FRV_GOT12;
4193 else if (SYMBOL_REF_LOCAL_P (sym)
4194 && !SYMBOL_REF_EXTERNAL_P (sym)
4195 && SYMBOL_REF_DECL (sym)
4196 && (!DECL_P (SYMBOL_REF_DECL (sym))
4197 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4199 tree decl = SYMBOL_REF_DECL (sym);
4200 tree init = TREE_CODE (decl) == VAR_DECL
4201 ? DECL_INITIAL (decl)
4202 : TREE_CODE (decl) == CONSTRUCTOR
4205 bool named_section, readonly;
4207 if (init && init != error_mark_node)
4208 reloc = compute_reloc_for_constant (init);
4210 named_section = TREE_CODE (decl) == VAR_DECL
4211 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4212 readonly = decl_readonly_section (decl, reloc);
4215 unspec = R_FRV_GOT12;
4217 unspec = R_FRV_GOTOFF12;
4218 else if (readonly && TARGET_GPREL_RO)
4219 unspec = R_FRV_GPREL12;
4221 unspec = R_FRV_GOT12;
4224 unspec = R_FRV_GOT12;
4228 else if (SYMBOL_REF_SMALL_P (sym))
4229 base_regno = SDA_BASE_REG;
4232 base_regno = PIC_REGNO;
4237 if (base_regno >= 0)
4239 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4240 emit_insn (gen_symGOTOFF2reg (dest, src,
4241 gen_rtx_REG (Pmode, base_regno),
4242 GEN_INT (R_FRV_GPREL12)));
4244 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4245 gen_rtx_REG (Pmode, base_regno),
4246 GEN_INT (R_FRV_GPREL12)));
4247 if (base_regno == PIC_REGNO)
4248 crtl->uses_pic_offset_table = TRUE;
4256 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4257 new uses of it once reload has begun. */
4258 gcc_assert (!reload_in_progress && !reload_completed);
4262 case R_FRV_GOTOFF12:
4263 if (!frv_small_data_reloc_p (sym, unspec))
4264 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4267 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4270 if (!frv_small_data_reloc_p (sym, unspec))
4271 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4274 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4276 case R_FRV_FUNCDESC_GOTOFF12:
4278 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4281 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4285 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4288 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4292 crtl->uses_pic_offset_table = TRUE;
4301 /* Return a string to output a single word move. */
4304 output_move_single (rtx operands[], rtx insn)
4306 rtx dest = operands[0];
4307 rtx src = operands[1];
4309 if (GET_CODE (dest) == REG)
4311 int dest_regno = REGNO (dest);
4312 enum machine_mode mode = GET_MODE (dest);
4314 if (GPR_P (dest_regno))
4316 if (GET_CODE (src) == REG)
4318 /* gpr <- some sort of register */
4319 int src_regno = REGNO (src);
4321 if (GPR_P (src_regno))
4322 return "mov %1, %0";
4324 else if (FPR_P (src_regno))
4325 return "movfg %1, %0";
4327 else if (SPR_P (src_regno))
4328 return "movsg %1, %0";
4331 else if (GET_CODE (src) == MEM)
4340 return "ldsb%I1%U1 %M1,%0";
4343 return "ldsh%I1%U1 %M1,%0";
4347 return "ld%I1%U1 %M1, %0";
4351 else if (GET_CODE (src) == CONST_INT
4352 || GET_CODE (src) == CONST_DOUBLE)
4354 /* gpr <- integer/floating constant */
4355 HOST_WIDE_INT value;
4357 if (GET_CODE (src) == CONST_INT)
4358 value = INTVAL (src);
4360 else if (mode == SFmode)
4365 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4366 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4371 value = CONST_DOUBLE_LOW (src);
4373 if (IN_RANGE_P (value, -32768, 32767))
4374 return "setlos %1, %0";
4379 else if (GET_CODE (src) == SYMBOL_REF
4380 || GET_CODE (src) == LABEL_REF
4381 || GET_CODE (src) == CONST)
4387 else if (FPR_P (dest_regno))
4389 if (GET_CODE (src) == REG)
4391 /* fpr <- some sort of register */
4392 int src_regno = REGNO (src);
4394 if (GPR_P (src_regno))
4395 return "movgf %1, %0";
4397 else if (FPR_P (src_regno))
4399 if (TARGET_HARD_FLOAT)
4400 return "fmovs %1, %0";
4402 return "mor %1, %1, %0";
4406 else if (GET_CODE (src) == MEM)
4415 return "ldbf%I1%U1 %M1,%0";
4418 return "ldhf%I1%U1 %M1,%0";
4422 return "ldf%I1%U1 %M1, %0";
4426 else if (ZERO_P (src))
4427 return "movgf %., %0";
4430 else if (SPR_P (dest_regno))
4432 if (GET_CODE (src) == REG)
4434 /* spr <- some sort of register */
4435 int src_regno = REGNO (src);
4437 if (GPR_P (src_regno))
4438 return "movgs %1, %0";
4440 else if (ZERO_P (src))
4441 return "movgs %., %0";
4445 else if (GET_CODE (dest) == MEM)
4447 if (GET_CODE (src) == REG)
4449 int src_regno = REGNO (src);
4450 enum machine_mode mode = GET_MODE (dest);
4452 if (GPR_P (src_regno))
4460 return "stb%I0%U0 %1, %M0";
4463 return "sth%I0%U0 %1, %M0";
4467 return "st%I0%U0 %1, %M0";
4471 else if (FPR_P (src_regno))
4479 return "stbf%I0%U0 %1, %M0";
4482 return "sthf%I0%U0 %1, %M0";
4486 return "stf%I0%U0 %1, %M0";
4491 else if (ZERO_P (src))
4493 switch (GET_MODE (dest))
4499 return "stb%I0%U0 %., %M0";
4502 return "sth%I0%U0 %., %M0";
4506 return "st%I0%U0 %., %M0";
4511 fatal_insn ("bad output_move_single operand", insn);
4516 /* Return a string to output a double word move. */
4519 output_move_double (rtx operands[], rtx insn)
4521 rtx dest = operands[0];
4522 rtx src = operands[1];
4523 enum machine_mode mode = GET_MODE (dest);
4525 if (GET_CODE (dest) == REG)
4527 int dest_regno = REGNO (dest);
4529 if (GPR_P (dest_regno))
4531 if (GET_CODE (src) == REG)
4533 /* gpr <- some sort of register */
4534 int src_regno = REGNO (src);
4536 if (GPR_P (src_regno))
4539 else if (FPR_P (src_regno))
4541 if (((dest_regno - GPR_FIRST) & 1) == 0
4542 && ((src_regno - FPR_FIRST) & 1) == 0)
4543 return "movfgd %1, %0";
4549 else if (GET_CODE (src) == MEM)
4552 if (dbl_memory_one_insn_operand (src, mode))
4553 return "ldd%I1%U1 %M1, %0";
4558 else if (GET_CODE (src) == CONST_INT
4559 || GET_CODE (src) == CONST_DOUBLE)
4563 else if (FPR_P (dest_regno))
4565 if (GET_CODE (src) == REG)
4567 /* fpr <- some sort of register */
4568 int src_regno = REGNO (src);
4570 if (GPR_P (src_regno))
4572 if (((dest_regno - FPR_FIRST) & 1) == 0
4573 && ((src_regno - GPR_FIRST) & 1) == 0)
4574 return "movgfd %1, %0";
4579 else if (FPR_P (src_regno))
4582 && ((dest_regno - FPR_FIRST) & 1) == 0
4583 && ((src_regno - FPR_FIRST) & 1) == 0)
4584 return "fmovd %1, %0";
4590 else if (GET_CODE (src) == MEM)
4593 if (dbl_memory_one_insn_operand (src, mode))
4594 return "lddf%I1%U1 %M1, %0";
4599 else if (ZERO_P (src))
4604 else if (GET_CODE (dest) == MEM)
4606 if (GET_CODE (src) == REG)
4608 int src_regno = REGNO (src);
4610 if (GPR_P (src_regno))
4612 if (((src_regno - GPR_FIRST) & 1) == 0
4613 && dbl_memory_one_insn_operand (dest, mode))
4614 return "std%I0%U0 %1, %M0";
4619 if (FPR_P (src_regno))
4621 if (((src_regno - FPR_FIRST) & 1) == 0
4622 && dbl_memory_one_insn_operand (dest, mode))
4623 return "stdf%I0%U0 %1, %M0";
4629 else if (ZERO_P (src))
4631 if (dbl_memory_one_insn_operand (dest, mode))
4632 return "std%I0%U0 %., %M0";
4638 fatal_insn ("bad output_move_double operand", insn);
4643 /* Return a string to output a single word conditional move.
4644 Operand0 -- EQ/NE of ccr register and 0
4645 Operand1 -- CCR register
4646 Operand2 -- destination
4647 Operand3 -- source */
4650 output_condmove_single (rtx operands[], rtx insn)
4652 rtx dest = operands[2];
4653 rtx src = operands[3];
4655 if (GET_CODE (dest) == REG)
4657 int dest_regno = REGNO (dest);
4658 enum machine_mode mode = GET_MODE (dest);
4660 if (GPR_P (dest_regno))
4662 if (GET_CODE (src) == REG)
4664 /* gpr <- some sort of register */
4665 int src_regno = REGNO (src);
4667 if (GPR_P (src_regno))
4668 return "cmov %z3, %2, %1, %e0";
4670 else if (FPR_P (src_regno))
4671 return "cmovfg %3, %2, %1, %e0";
4674 else if (GET_CODE (src) == MEM)
4683 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4686 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4690 return "cld%I3%U3 %M3, %2, %1, %e0";
4694 else if (ZERO_P (src))
4695 return "cmov %., %2, %1, %e0";
4698 else if (FPR_P (dest_regno))
4700 if (GET_CODE (src) == REG)
4702 /* fpr <- some sort of register */
4703 int src_regno = REGNO (src);
4705 if (GPR_P (src_regno))
4706 return "cmovgf %3, %2, %1, %e0";
4708 else if (FPR_P (src_regno))
4710 if (TARGET_HARD_FLOAT)
4711 return "cfmovs %3,%2,%1,%e0";
4713 return "cmor %3, %3, %2, %1, %e0";
4717 else if (GET_CODE (src) == MEM)
4720 if (mode == SImode || mode == SFmode)
4721 return "cldf%I3%U3 %M3, %2, %1, %e0";
4724 else if (ZERO_P (src))
4725 return "cmovgf %., %2, %1, %e0";
4729 else if (GET_CODE (dest) == MEM)
4731 if (GET_CODE (src) == REG)
4733 int src_regno = REGNO (src);
4734 enum machine_mode mode = GET_MODE (dest);
4736 if (GPR_P (src_regno))
4744 return "cstb%I2%U2 %3, %M2, %1, %e0";
4747 return "csth%I2%U2 %3, %M2, %1, %e0";
4751 return "cst%I2%U2 %3, %M2, %1, %e0";
4755 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4756 return "cstf%I2%U2 %3, %M2, %1, %e0";
4759 else if (ZERO_P (src))
4761 enum machine_mode mode = GET_MODE (dest);
4768 return "cstb%I2%U2 %., %M2, %1, %e0";
4771 return "csth%I2%U2 %., %M2, %1, %e0";
4775 return "cst%I2%U2 %., %M2, %1, %e0";
4780 fatal_insn ("bad output_condmove_single operand", insn);
4785 /* Emit the appropriate code to do a comparison, returning the register the
4786 comparison was done it. */
4789 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4791 enum machine_mode cc_mode;
4794 /* Floating point doesn't have comparison against a constant. */
4795 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4796 op1 = force_reg (GET_MODE (op0), op1);
4798 /* Possibly disable using anything but a fixed register in order to work
4799 around cse moving comparisons past function calls. */
4800 cc_mode = SELECT_CC_MODE (test, op0, op1);
4801 cc_reg = ((TARGET_ALLOC_CC)
4802 ? gen_reg_rtx (cc_mode)
4803 : gen_rtx_REG (cc_mode,
4804 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4806 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4807 gen_rtx_COMPARE (cc_mode, op0, op1)));
4813 /* Emit code for a conditional branch.
4814 XXX: I originally wanted to add a clobber of a CCR register to use in
4815 conditional execution, but that confuses the rest of the compiler. */
4818 frv_emit_cond_branch (rtx operands[])
4823 enum rtx_code test = GET_CODE (operands[0]);
4824 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4825 enum machine_mode cc_mode = GET_MODE (cc_reg);
4827 /* Branches generate:
4829 (if_then_else (<test>, <cc_reg>, (const_int 0))
4830 (label_ref <branch_label>)
4832 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4833 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4834 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4835 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4840 /* Emit code to set a gpr to 1/0 based on a comparison. */
4843 frv_emit_scc (rtx operands[])
4849 enum rtx_code test = GET_CODE (operands[1]);
4850 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4852 /* SCC instructions generate:
4853 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4854 (clobber (<ccr_reg>))]) */
4855 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4856 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4858 cr_reg = ((TARGET_ALLOC_CC)
4859 ? gen_reg_rtx (CC_CCRmode)
4860 : gen_rtx_REG (CC_CCRmode,
4861 ((GET_MODE (cc_reg) == CC_FPmode)
4865 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4866 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4871 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4872 the separate insns. */
4875 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4881 /* Set the appropriate CCR bit. */
4882 emit_insn (gen_rtx_SET (VOIDmode,
4884 gen_rtx_fmt_ee (GET_CODE (test),
4889 /* Move the value into the destination. */
4890 emit_move_insn (dest, GEN_INT (value));
4892 /* Move 0 into the destination if the test failed */
4893 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4894 gen_rtx_EQ (GET_MODE (cr_reg),
4897 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4899 /* Finish up, return sequence. */
4906 /* Emit the code for a conditional move, return TRUE if we could do the
4910 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4917 enum rtx_code test = GET_CODE (test_rtx);
4918 rtx cc_reg = frv_emit_comparison (test,
4919 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4920 enum machine_mode cc_mode = GET_MODE (cc_reg);
4922 /* Conditional move instructions generate:
4923 (parallel [(set <target>
4924 (if_then_else (<test> <cc_reg> (const_int 0))
4927 (clobber (<ccr_reg>))]) */
4929 /* Handle various cases of conditional move involving two constants. */
4930 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4932 HOST_WIDE_INT value1 = INTVAL (src1);
4933 HOST_WIDE_INT value2 = INTVAL (src2);
4935 /* Having 0 as one of the constants can be done by loading the other
4936 constant, and optionally moving in gr0. */
4937 if (value1 == 0 || value2 == 0)
4940 /* If the first value is within an addi range and also the difference
4941 between the two fits in an addi's range, load up the difference, then
4942 conditionally move in 0, and then unconditionally add the first
4944 else if (IN_RANGE_P (value1, -2048, 2047)
4945 && IN_RANGE_P (value2 - value1, -2048, 2047))
4948 /* If neither condition holds, just force the constant into a
4952 src1 = force_reg (GET_MODE (dest), src1);
4953 src2 = force_reg (GET_MODE (dest), src2);
4957 /* If one value is a register, insure the other value is either 0 or a
4961 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4962 src1 = force_reg (GET_MODE (dest), src1);
4964 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4965 src2 = force_reg (GET_MODE (dest), src2);
4968 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4969 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4971 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4973 cr_reg = ((TARGET_ALLOC_CC)
4974 ? gen_reg_rtx (CC_CCRmode)
4975 : gen_rtx_REG (CC_CCRmode,
4976 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4978 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4979 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4984 /* Split a conditional move into constituent parts, returning a SEQUENCE
4985 containing all of the insns. */
4988 frv_split_cond_move (rtx operands[])
4990 rtx dest = operands[0];
4991 rtx test = operands[1];
4992 rtx cc_reg = operands[2];
4993 rtx src1 = operands[3];
4994 rtx src2 = operands[4];
4995 rtx cr_reg = operands[5];
4997 enum machine_mode cr_mode = GET_MODE (cr_reg);
5001 /* Set the appropriate CCR bit. */
5002 emit_insn (gen_rtx_SET (VOIDmode,
5004 gen_rtx_fmt_ee (GET_CODE (test),
5009 /* Handle various cases of conditional move involving two constants. */
5010 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
5012 HOST_WIDE_INT value1 = INTVAL (src1);
5013 HOST_WIDE_INT value2 = INTVAL (src2);
5015 /* Having 0 as one of the constants can be done by loading the other
5016 constant, and optionally moving in gr0. */
5019 emit_move_insn (dest, src2);
5020 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5021 gen_rtx_NE (cr_mode, cr_reg,
5023 gen_rtx_SET (VOIDmode, dest, src1)));
5026 else if (value2 == 0)
5028 emit_move_insn (dest, src1);
5029 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5030 gen_rtx_EQ (cr_mode, cr_reg,
5032 gen_rtx_SET (VOIDmode, dest, src2)));
5035 /* If the first value is within an addi range and also the difference
5036 between the two fits in an addi's range, load up the difference, then
5037 conditionally move in 0, and then unconditionally add the first
5039 else if (IN_RANGE_P (value1, -2048, 2047)
5040 && IN_RANGE_P (value2 - value1, -2048, 2047))
5042 rtx dest_si = ((GET_MODE (dest) == SImode)
5044 : gen_rtx_SUBREG (SImode, dest, 0));
5046 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5047 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5048 gen_rtx_NE (cr_mode, cr_reg,
5050 gen_rtx_SET (VOIDmode, dest_si,
5052 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5060 /* Emit the conditional move for the test being true if needed. */
5061 if (! rtx_equal_p (dest, src1))
5062 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5063 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5064 gen_rtx_SET (VOIDmode, dest, src1)));
5066 /* Emit the conditional move for the test being false if needed. */
5067 if (! rtx_equal_p (dest, src2))
5068 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5069 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5070 gen_rtx_SET (VOIDmode, dest, src2)));
5073 /* Finish up, return sequence. */
5080 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5081 memory location that is not known to be dword-aligned. */
5083 frv_split_double_load (rtx dest, rtx source)
5085 int regno = REGNO (dest);
5086 rtx dest1 = gen_highpart (SImode, dest);
5087 rtx dest2 = gen_lowpart (SImode, dest);
5088 rtx address = XEXP (source, 0);
5090 /* If the address is pre-modified, load the lower-numbered register
5091 first, then load the other register using an integer offset from
5092 the modified base register. This order should always be safe,
5093 since the pre-modification cannot affect the same registers as the
5096 The situation for other loads is more complicated. Loading one
5097 of the registers could affect the value of ADDRESS, so we must
5098 be careful which order we do them in. */
5099 if (GET_CODE (address) == PRE_MODIFY
5100 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5102 /* It is safe to load the lower-numbered register first. */
5103 emit_move_insn (dest1, change_address (source, SImode, NULL));
5104 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5108 /* ADDRESS is not pre-modified and the address depends on the
5109 lower-numbered register. Load the higher-numbered register
5111 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5112 emit_move_insn (dest1, change_address (source, SImode, NULL));
5116 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5117 and SOURCE is either a double register or the constant zero. */
5119 frv_split_double_store (rtx dest, rtx source)
5121 rtx dest1 = change_address (dest, SImode, NULL);
5122 rtx dest2 = frv_index_memory (dest, SImode, 1);
5123 if (ZERO_P (source))
5125 emit_move_insn (dest1, CONST0_RTX (SImode));
5126 emit_move_insn (dest2, CONST0_RTX (SImode));
5130 emit_move_insn (dest1, gen_highpart (SImode, source));
5131 emit_move_insn (dest2, gen_lowpart (SImode, source));
5136 /* Split a min/max operation returning a SEQUENCE containing all of the
5140 frv_split_minmax (rtx operands[])
5142 rtx dest = operands[0];
5143 rtx minmax = operands[1];
5144 rtx src1 = operands[2];
5145 rtx src2 = operands[3];
5146 rtx cc_reg = operands[4];
5147 rtx cr_reg = operands[5];
5149 enum rtx_code test_code;
5150 enum machine_mode cr_mode = GET_MODE (cr_reg);
5154 /* Figure out which test to use. */
5155 switch (GET_CODE (minmax))
5160 case SMIN: test_code = LT; break;
5161 case SMAX: test_code = GT; break;
5162 case UMIN: test_code = LTU; break;
5163 case UMAX: test_code = GTU; break;
5166 /* Issue the compare instruction. */
5167 emit_insn (gen_rtx_SET (VOIDmode,
5169 gen_rtx_COMPARE (GET_MODE (cc_reg),
5172 /* Set the appropriate CCR bit. */
5173 emit_insn (gen_rtx_SET (VOIDmode,
5175 gen_rtx_fmt_ee (test_code,
5180 /* If are taking the min/max of a nonzero constant, load that first, and
5181 then do a conditional move of the other value. */
5182 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5184 gcc_assert (!rtx_equal_p (dest, src1));
5186 emit_move_insn (dest, src2);
5187 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5188 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5189 gen_rtx_SET (VOIDmode, dest, src1)));
5192 /* Otherwise, do each half of the move. */
5195 /* Emit the conditional move for the test being true if needed. */
5196 if (! rtx_equal_p (dest, src1))
5197 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5198 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5199 gen_rtx_SET (VOIDmode, dest, src1)));
5201 /* Emit the conditional move for the test being false if needed. */
5202 if (! rtx_equal_p (dest, src2))
5203 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5204 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5205 gen_rtx_SET (VOIDmode, dest, src2)));
5208 /* Finish up, return sequence. */
5215 /* Split an integer abs operation returning a SEQUENCE containing all of the
5219 frv_split_abs (rtx operands[])
5221 rtx dest = operands[0];
5222 rtx src = operands[1];
5223 rtx cc_reg = operands[2];
5224 rtx cr_reg = operands[3];
5229 /* Issue the compare < 0 instruction. */
5230 emit_insn (gen_rtx_SET (VOIDmode,
5232 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5234 /* Set the appropriate CCR bit. */
5235 emit_insn (gen_rtx_SET (VOIDmode,
5237 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5239 /* Emit the conditional negate if the value is negative. */
5240 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5241 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5242 gen_negsi2 (dest, src)));
5244 /* Emit the conditional move for the test being false if needed. */
5245 if (! rtx_equal_p (dest, src))
5246 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5247 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5248 gen_rtx_SET (VOIDmode, dest, src)));
5250 /* Finish up, return sequence. */
5257 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5258 register used in an insn. */
5261 frv_clear_registers_used (rtx *ptr, void *data)
5263 if (GET_CODE (*ptr) == REG)
5265 int regno = REGNO (*ptr);
5266 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5268 if (regno < FIRST_PSEUDO_REGISTER)
5270 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5272 while (regno < reg_max)
5274 CLEAR_HARD_REG_BIT (*p_regs, regno);
5284 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5286 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5287 initialize the static storage. */
5289 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5291 frv_ifcvt.added_insns_list = NULL_RTX;
5292 frv_ifcvt.cur_scratch_regs = 0;
5293 frv_ifcvt.num_nested_cond_exec = 0;
5294 frv_ifcvt.cr_reg = NULL_RTX;
5295 frv_ifcvt.nested_cc_reg = NULL_RTX;
5296 frv_ifcvt.extra_int_cr = NULL_RTX;
5297 frv_ifcvt.extra_fp_cr = NULL_RTX;
5298 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5302 /* Internal function to add a potential insn to the list of insns to be inserted
5303 if the conditional execution conversion is successful. */
5306 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5308 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5310 link->jump = before_p; /* Mark to add this before or after insn. */
5311 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5312 frv_ifcvt.added_insns_list);
5314 if (TARGET_DEBUG_COND_EXEC)
5317 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5318 (before_p) ? "before" : "after",
5319 (int)INSN_UID (insn));
5321 debug_rtx (pattern);
5326 /* A C expression to modify the code described by the conditional if
5327 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5328 FALSE_EXPR for converting if-then and if-then-else code to conditional
5329 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5330 tests cannot be converted. */
5333 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5335 basic_block test_bb = ce_info->test_bb; /* test basic block */
5336 basic_block then_bb = ce_info->then_bb; /* THEN */
5337 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5338 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5339 rtx true_expr = *p_true;
5343 enum machine_mode mode = GET_MODE (true_expr);
5347 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5349 rtx sub_cond_exec_reg;
5351 enum rtx_code code_true;
5352 enum rtx_code code_false;
5353 enum reg_class cc_class;
5354 enum reg_class cr_class;
5357 reg_set_iterator rsi;
5359 /* Make sure we are only dealing with hard registers. Also honor the
5360 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5362 if (!reload_completed || !TARGET_COND_EXEC
5363 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5366 /* Figure out which registers we can allocate for our own purposes. Only
5367 consider registers that are not preserved across function calls and are
5368 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5369 if we did not need to use them in reloading other registers. */
5370 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5371 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5372 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5373 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5374 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5376 /* If this is a nested IF, we need to discover whether the CC registers that
5377 are set/used inside of the block are used anywhere else. If not, we can
5378 change them to be the CC register that is paired with the CR register that
5379 controls the outermost IF block. */
5380 if (ce_info->pass > 1)
5382 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5383 for (j = CC_FIRST; j <= CC_LAST; j++)
5384 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5386 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5390 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5394 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5397 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5401 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5402 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5404 frv_ifcvt.added_insns_list = NULL_RTX;
5405 frv_ifcvt.cur_scratch_regs = 0;
5407 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5408 * sizeof (basic_block));
5414 /* Remove anything live at the beginning of the join block from being
5415 available for allocation. */
5416 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5418 if (regno < FIRST_PSEUDO_REGISTER)
5419 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5423 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5425 if (ce_info->num_multiple_test_blocks)
5427 basic_block multiple_test_bb = ce_info->last_test_bb;
5429 while (multiple_test_bb != test_bb)
5431 bb[num_bb++] = multiple_test_bb;
5432 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5436 /* Add in the THEN and ELSE blocks to be scanned. */
5437 bb[num_bb++] = then_bb;
5439 bb[num_bb++] = else_bb;
5441 sub_cond_exec_reg = NULL_RTX;
5442 frv_ifcvt.num_nested_cond_exec = 0;
5444 /* Scan all of the blocks for registers that must not be allocated. */
5445 for (j = 0; j < num_bb; j++)
5447 rtx last_insn = BB_END (bb[j]);
5448 rtx insn = BB_HEAD (bb[j]);
5452 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5453 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5455 (int) INSN_UID (BB_HEAD (bb[j])),
5456 (int) INSN_UID (BB_END (bb[j])));
5458 /* Anything live at the beginning of the block is obviously unavailable
5460 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5462 if (regno < FIRST_PSEUDO_REGISTER)
5463 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5466 /* Loop through the insns in the block. */
5469 /* Mark any new registers that are created as being unavailable for
5470 allocation. Also see if the CC register used in nested IFs can be
5476 int skip_nested_if = FALSE;
5478 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5479 (void *)&tmp_reg->regs);
5481 pattern = PATTERN (insn);
5482 if (GET_CODE (pattern) == COND_EXEC)
5484 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5486 if (reg != sub_cond_exec_reg)
5488 sub_cond_exec_reg = reg;
5489 frv_ifcvt.num_nested_cond_exec++;
5493 set = single_set_pattern (pattern);
5496 rtx dest = SET_DEST (set);
5497 rtx src = SET_SRC (set);
5499 if (GET_CODE (dest) == REG)
5501 int regno = REGNO (dest);
5502 enum rtx_code src_code = GET_CODE (src);
5504 if (CC_P (regno) && src_code == COMPARE)
5505 skip_nested_if = TRUE;
5507 else if (CR_P (regno)
5508 && (src_code == IF_THEN_ELSE
5509 || COMPARISON_P (src)))
5510 skip_nested_if = TRUE;
5514 if (! skip_nested_if)
5515 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5516 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5519 if (insn == last_insn)
5522 insn = NEXT_INSN (insn);
5526 /* If this is a nested if, rewrite the CC registers that are available to
5527 include the ones that can be rewritten, to increase the chance of being
5528 able to allocate a paired CC/CR register combination. */
5529 if (ce_info->pass > 1)
5531 for (j = CC_FIRST; j <= CC_LAST; j++)
5532 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5533 SET_HARD_REG_BIT (tmp_reg->regs, j);
5535 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5541 fprintf (dump_file, "Available GPRs: ");
5543 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5544 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5546 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5547 if (++num_gprs > GPR_TEMP_NUM+2)
5551 fprintf (dump_file, "%s\nAvailable CRs: ",
5552 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5554 for (j = CR_FIRST; j <= CR_LAST; j++)
5555 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5556 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5558 fputs ("\n", dump_file);
5560 if (ce_info->pass > 1)
5562 fprintf (dump_file, "Modifiable CCs: ");
5563 for (j = CC_FIRST; j <= CC_LAST; j++)
5564 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5565 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5567 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5568 frv_ifcvt.num_nested_cond_exec);
5572 /* Allocate the appropriate temporary condition code register. Try to
5573 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5574 that conditional cmp's can be done. */
5575 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5577 cr_class = ICR_REGS;
5578 cc_class = ICC_REGS;
5579 cc_first = ICC_FIRST;
5582 else if (mode == CC_FPmode)
5584 cr_class = FCR_REGS;
5585 cc_class = FCC_REGS;
5586 cc_first = FCC_FIRST;
5591 cc_first = cc_last = 0;
5592 cr_class = cc_class = NO_REGS;
5595 cc = XEXP (true_expr, 0);
5596 nested_cc = cr = NULL_RTX;
5597 if (cc_class != NO_REGS)
5599 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5600 so we can execute a csubcc/caddcc/cfcmps instruction. */
5603 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5605 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5607 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5608 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5610 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5611 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5614 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5615 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5625 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5632 "Will use %s for conditional execution, %s for nested comparisons\n",
5633 reg_names[ REGNO (cr)],
5634 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5636 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5637 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5638 bit being true. We don't do this for floating point, because of NaNs. */
5639 code = GET_CODE (true_expr);
5640 if (GET_MODE (cc) != CC_FPmode)
5642 code = reverse_condition (code);
5652 check_insn = gen_rtx_SET (VOIDmode, cr,
5653 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5655 /* Record the check insn to be inserted later. */
5656 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5658 /* Update the tests. */
5659 frv_ifcvt.cr_reg = cr;
5660 frv_ifcvt.nested_cc_reg = nested_cc;
5661 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5662 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5665 /* Fail, don't do this conditional execution. */
5668 *p_false = NULL_RTX;
5670 fprintf (dump_file, "Disabling this conditional execution.\n");
5676 /* A C expression to modify the code described by the conditional if
5677 information CE_INFO, for the basic block BB, possibly updating the tests in
5678 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5679 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5680 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5682 /* p_true and p_false are given expressions of the form:
5684 (and (eq:CC_CCR (reg:CC_CCR)
5690 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5695 rtx old_true = XEXP (*p_true, 0);
5696 rtx old_false = XEXP (*p_false, 0);
5697 rtx true_expr = XEXP (*p_true, 1);
5698 rtx false_expr = XEXP (*p_false, 1);
5701 rtx cr = XEXP (old_true, 0);
5703 rtx new_cr = NULL_RTX;
5704 rtx *p_new_cr = (rtx *)0;
5708 enum reg_class cr_class;
5709 enum machine_mode mode = GET_MODE (true_expr);
5710 rtx (*logical_func)(rtx, rtx, rtx);
5712 if (TARGET_DEBUG_COND_EXEC)
5715 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5716 ce_info->and_and_p ? "&&" : "||");
5718 debug_rtx (*p_true);
5720 fputs ("\nfalse insn:\n", stderr);
5721 debug_rtx (*p_false);
5724 if (!TARGET_MULTI_CE)
5727 if (GET_CODE (cr) != REG)
5730 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5732 cr_class = ICR_REGS;
5733 p_new_cr = &frv_ifcvt.extra_int_cr;
5735 else if (mode == CC_FPmode)
5737 cr_class = FCR_REGS;
5738 p_new_cr = &frv_ifcvt.extra_fp_cr;
5743 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5744 more &&/|| tests. */
5748 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5749 CC_CCRmode, TRUE, TRUE);
5754 if (ce_info->and_and_p)
5756 old_test = old_false;
5757 test_expr = true_expr;
5758 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5759 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5760 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5764 old_test = old_false;
5765 test_expr = false_expr;
5766 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5767 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5768 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5771 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5772 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5774 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5776 /* Now add the conditional check insn. */
5777 cc = XEXP (test_expr, 0);
5778 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5779 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5781 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5783 /* Add the new check insn to the list of check insns that need to be
5785 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5787 if (TARGET_DEBUG_COND_EXEC)
5789 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5792 debug_rtx (*p_true);
5794 fputs ("\nfalse insn:\n", stderr);
5795 debug_rtx (*p_false);
5801 *p_true = *p_false = NULL_RTX;
5803 /* If we allocated a CR register, release it. */
5806 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5807 *p_new_cr = NULL_RTX;
5810 if (TARGET_DEBUG_COND_EXEC)
5811 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5817 /* Return a register which will be loaded with a value if an IF block is
5818 converted to conditional execution. This is used to rewrite instructions
5819 that use constants to ones that just use registers. */
5822 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5824 int num_alloc = frv_ifcvt.cur_scratch_regs;
5828 /* We know gr0 == 0, so replace any errant uses. */
5829 if (value == const0_rtx)
5830 return gen_rtx_REG (SImode, GPR_FIRST);
5832 /* First search all registers currently loaded to see if we have an
5833 applicable constant. */
5834 if (CONSTANT_P (value)
5835 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5837 for (i = 0; i < num_alloc; i++)
5839 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5840 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5844 /* Have we exhausted the number of registers available? */
5845 if (num_alloc >= GPR_TEMP_NUM)
5848 fprintf (dump_file, "Too many temporary registers allocated\n");
5853 /* Allocate the new register. */
5854 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5858 fputs ("Could not find a scratch register\n", dump_file);
5863 frv_ifcvt.cur_scratch_regs++;
5864 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5868 if (GET_CODE (value) == CONST_INT)
5869 fprintf (dump_file, "Register %s will hold %ld\n",
5870 reg_names[ REGNO (reg)], (long)INTVAL (value));
5872 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5873 fprintf (dump_file, "Register %s will hold LR\n",
5874 reg_names[ REGNO (reg)]);
5877 fprintf (dump_file, "Register %s will hold a saved value\n",
5878 reg_names[ REGNO (reg)]);
5885 /* Update a MEM used in conditional code that might contain an offset to put
5886 the offset into a scratch register, so that the conditional load/store
5887 operations can be used. This function returns the original pointer if the
5888 MEM is valid to use in conditional code, NULL if we can't load up the offset
5889 into a temporary register, or the new MEM if we were successful. */
5892 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5894 rtx addr = XEXP (mem, 0);
5896 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5898 if (GET_CODE (addr) == PLUS)
5900 rtx addr_op0 = XEXP (addr, 0);
5901 rtx addr_op1 = XEXP (addr, 1);
5903 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5905 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5909 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5916 else if (CONSTANT_P (addr))
5917 addr = frv_ifcvt_load_value (addr, insn);
5922 if (addr == NULL_RTX)
5925 else if (XEXP (mem, 0) != addr)
5926 return change_address (mem, mode, addr);
5933 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5934 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5937 single_set_pattern (rtx pattern)
5942 if (GET_CODE (pattern) == COND_EXEC)
5943 pattern = COND_EXEC_CODE (pattern);
5945 if (GET_CODE (pattern) == SET)
5948 else if (GET_CODE (pattern) == PARALLEL)
5950 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5952 rtx sub = XVECEXP (pattern, 0, i);
5954 switch (GET_CODE (sub))
5978 /* A C expression to modify the code described by the conditional if
5979 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5980 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5981 insn cannot be converted to be executed conditionally. */
5984 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5988 rtx orig_ce_pattern = pattern;
5994 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5996 test = COND_EXEC_TEST (pattern);
5997 if (GET_CODE (test) == AND)
5999 rtx cr = frv_ifcvt.cr_reg;
6002 op0 = XEXP (test, 0);
6003 if (! rtx_equal_p (cr, XEXP (op0, 0)))
6006 op1 = XEXP (test, 1);
6007 test_reg = XEXP (op1, 0);
6008 if (GET_CODE (test_reg) != REG)
6011 /* Is this the first nested if block in this sequence? If so, generate
6012 an andcr or andncr. */
6013 if (! frv_ifcvt.last_nested_if_cr)
6017 frv_ifcvt.last_nested_if_cr = test_reg;
6018 if (GET_CODE (op0) == NE)
6019 and_op = gen_andcr (test_reg, cr, test_reg);
6021 and_op = gen_andncr (test_reg, cr, test_reg);
6023 frv_ifcvt_add_insn (and_op, insn, TRUE);
6026 /* If this isn't the first statement in the nested if sequence, see if we
6027 are dealing with the same register. */
6028 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6031 COND_EXEC_TEST (pattern) = test = op1;
6034 /* If this isn't a nested if, reset state variables. */
6037 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6040 set = single_set_pattern (pattern);
6043 rtx dest = SET_DEST (set);
6044 rtx src = SET_SRC (set);
6045 enum machine_mode mode = GET_MODE (dest);
6047 /* Check for normal binary operators. */
6048 if (mode == SImode && ARITHMETIC_P (src))
6050 op0 = XEXP (src, 0);
6051 op1 = XEXP (src, 1);
6053 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6055 op1 = frv_ifcvt_load_value (op1, insn);
6057 COND_EXEC_CODE (pattern)
6058 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6066 /* For multiply by a constant, we need to handle the sign extending
6067 correctly. Add a USE of the value after the multiply to prevent flow
6068 from cratering because only one register out of the two were used. */
6069 else if (mode == DImode && GET_CODE (src) == MULT)
6071 op0 = XEXP (src, 0);
6072 op1 = XEXP (src, 1);
6073 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6075 op1 = frv_ifcvt_load_value (op1, insn);
6078 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6079 COND_EXEC_CODE (pattern)
6080 = gen_rtx_SET (VOIDmode, dest,
6081 gen_rtx_MULT (DImode, op0, op1));
6087 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6090 /* If we are just loading a constant created for a nested conditional
6091 execution statement, just load the constant without any conditional
6092 execution, since we know that the constant will not interfere with any
6094 else if (frv_ifcvt.scratch_insns_bitmap
6095 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6097 && REG_P (SET_DEST (set))
6098 /* We must not unconditionally set a scratch reg chosen
6099 for a nested if-converted block if its incoming
6100 value from the TEST block (or the result of the THEN
6101 branch) could/should propagate to the JOIN block.
6102 It suffices to test whether the register is live at
6103 the JOIN point: if it's live there, we can infer
6104 that we set it in the former JOIN block of the
6105 nested if-converted block (otherwise it wouldn't
6106 have been available as a scratch register), and it
6107 is either propagated through or set in the other
6108 conditional block. It's probably not worth trying
6109 to catch the latter case, and it could actually
6110 limit scheduling of the combined block quite
6113 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6114 REGNO (SET_DEST (set))))
6115 /* Similarly, we must not unconditionally set a reg
6116 used as scratch in the THEN branch if the same reg
6117 is live in the ELSE branch. */
6118 && (! ce_info->else_bb
6119 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6120 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6121 REGNO (SET_DEST (set))))))
6124 else if (mode == QImode || mode == HImode || mode == SImode
6127 int changed_p = FALSE;
6129 /* Check for just loading up a constant */
6130 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6132 src = frv_ifcvt_load_value (src, insn);
6139 /* See if we need to fix up stores */
6140 if (GET_CODE (dest) == MEM)
6142 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6147 else if (new_mem != dest)
6154 /* See if we need to fix up loads */
6155 if (GET_CODE (src) == MEM)
6157 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6162 else if (new_mem != src)
6169 /* If either src or destination changed, redo SET. */
6171 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6174 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6175 rewriting the CC register to be the same as the paired CC/CR register
6177 else if (mode == CC_CCRmode && COMPARISON_P (src))
6179 int regno = REGNO (XEXP (src, 0));
6182 if (ce_info->pass > 1
6183 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6184 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6186 src = gen_rtx_fmt_ee (GET_CODE (src),
6188 frv_ifcvt.nested_cc_reg,
6192 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6193 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6196 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6197 else if (ce_info->pass > 1
6198 && GET_CODE (dest) == REG
6199 && CC_P (REGNO (dest))
6200 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6201 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6203 && GET_CODE (src) == COMPARE)
6205 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6206 COND_EXEC_CODE (pattern)
6207 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6211 if (TARGET_DEBUG_COND_EXEC)
6213 rtx orig_pattern = PATTERN (insn);
6215 PATTERN (insn) = pattern;
6217 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6221 PATTERN (insn) = orig_pattern;
6227 if (TARGET_DEBUG_COND_EXEC)
6229 rtx orig_pattern = PATTERN (insn);
6231 PATTERN (insn) = orig_ce_pattern;
6233 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6237 PATTERN (insn) = orig_pattern;
6244 /* A C expression to perform any final machine dependent modifications in
6245 converting code to conditional execution in the code described by the
6246 conditional if information CE_INFO. */
6249 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6253 rtx p = frv_ifcvt.added_insns_list;
6256 /* Loop inserting the check insns. The last check insn is the first test,
6257 and is the appropriate place to insert constants. */
6262 rtx check_and_insert_insns = XEXP (p, 0);
6265 check_insn = XEXP (check_and_insert_insns, 0);
6266 existing_insn = XEXP (check_and_insert_insns, 1);
6269 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6270 the existing insn, otherwise it is to be inserted AFTER. */
6271 if (check_and_insert_insns->jump)
6273 emit_insn_before (check_insn, existing_insn);
6274 check_and_insert_insns->jump = 0;
6277 emit_insn_after (check_insn, existing_insn);
6279 free_EXPR_LIST_node (check_and_insert_insns);
6280 free_EXPR_LIST_node (old_p);
6282 while (p != NULL_RTX);
6284 /* Load up any constants needed into temp gprs */
6285 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6287 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6288 if (! frv_ifcvt.scratch_insns_bitmap)
6289 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6290 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6291 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6294 frv_ifcvt.added_insns_list = NULL_RTX;
6295 frv_ifcvt.cur_scratch_regs = 0;
6299 /* A C expression to cancel any machine dependent modifications in converting
6300 code to conditional execution in the code described by the conditional if
6301 information CE_INFO. */
6304 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6307 rtx p = frv_ifcvt.added_insns_list;
6309 /* Loop freeing up the EXPR_LIST's allocated. */
6310 while (p != NULL_RTX)
6312 rtx check_and_jump = XEXP (p, 0);
6316 free_EXPR_LIST_node (check_and_jump);
6317 free_EXPR_LIST_node (old_p);
6320 /* Release any temporary gprs allocated. */
6321 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6322 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6324 frv_ifcvt.added_insns_list = NULL_RTX;
6325 frv_ifcvt.cur_scratch_regs = 0;
6329 /* A C expression for the size in bytes of the trampoline, as an integer.
6333 setlo #0, <static_chain>
6335 sethi #0, <static_chain>
6336 jmpl @(gr0,<jmp_reg>) */
6339 frv_trampoline_size (void)
6342 /* Allocate room for the function descriptor and the lddi
6345 return 5 /* instructions */ * 4 /* instruction size. */;
6349 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6350 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6351 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6352 should be passed to the function when it is called.
6357 setlo #0, <static_chain>
6359 sethi #0, <static_chain>
6360 jmpl @(gr0,<jmp_reg>) */
6363 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6365 rtx addr = XEXP (m_tramp, 0);
6366 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6367 rtx sc_reg = force_reg (Pmode, static_chain);
6369 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6372 GEN_INT (frv_trampoline_size ()), SImode,
6378 /* Many machines have some registers that cannot be copied directly to or from
6379 memory or even from other types of registers. An example is the `MQ'
6380 register, which on most machines, can only be copied to or from general
6381 registers, but not memory. Some machines allow copying all registers to and
6382 from memory, but require a scratch register for stores to some memory
6383 locations (e.g., those with symbolic address on the RT, and those with
6384 certain symbolic address on the SPARC when compiling PIC). In some cases,
6385 both an intermediate and a scratch register are required.
6387 You should define these macros to indicate to the reload phase that it may
6388 need to allocate at least one register for a reload in addition to the
6389 register to contain the data. Specifically, if copying X to a register
6390 RCLASS in MODE requires an intermediate register, you should define
6391 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6392 whose registers can be used as intermediate registers or scratch registers.
6394 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6395 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6396 largest register class required. If the requirements for input and output
6397 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6398 instead of defining both macros identically.
6400 The values returned by these macros are often `GENERAL_REGS'. Return
6401 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6402 to or from a register of RCLASS in MODE without requiring a scratch register.
6403 Do not define this macro if it would always return `NO_REGS'.
6405 If a scratch register is required (either with or without an intermediate
6406 register), you should define patterns for `reload_inM' or `reload_outM', as
6407 required.. These patterns, which will normally be implemented with a
6408 `define_expand', should be similar to the `movM' patterns, except that
6409 operand 2 is the scratch register.
6411 Define constraints for the reload register and scratch register that contain
6412 a single register class. If the original reload register (whose class is
6413 RCLASS) can meet the constraint given in the pattern, the value returned by
6414 these macros is used for the class of the scratch register. Otherwise, two
6415 additional reload registers are required. Their classes are obtained from
6416 the constraints in the insn pattern.
6418 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6419 either be in a hard register or in memory. Use `true_regnum' to find out;
6420 it will return -1 if the pseudo is in memory and the hard register number if
6421 it is in a register.
6423 These macros should not be used in the case where a particular class of
6424 registers can only be copied to memory and not to another class of
6425 registers. In that case, secondary reload registers are not needed and
6426 would not be helpful. Instead, a stack location must be used to perform the
6427 copy and the `movM' pattern should use memory as an intermediate storage.
6428 This case often occurs between floating-point and general registers. */
6431 frv_secondary_reload_class (enum reg_class rclass,
6432 enum machine_mode mode ATTRIBUTE_UNUSED,
6443 /* Accumulators/Accumulator guard registers need to go through floating
6449 if (x && GET_CODE (x) == REG)
6451 int regno = REGNO (x);
6453 if (ACC_P (regno) || ACCG_P (regno))
6458 /* Nonzero constants should be loaded into an FPR through a GPR. */
6462 if (x && CONSTANT_P (x) && !ZERO_P (x))
6468 /* All of these types need gpr registers. */
6480 /* The accumulators need fpr registers. */
6492 /* This hook exists to catch the case where secondary_reload_class() is
6493 called from init_reg_autoinc() in regclass.c - before the reload optabs
6494 have been initialised. */
6497 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6498 enum machine_mode reload_mode,
6499 secondary_reload_info * sri)
6501 enum reg_class rclass = NO_REGS;
6502 enum reg_class reload_class = (enum reg_class) reload_class_i;
6504 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6506 sri->icode = sri->prev_sri->t_icode;
6510 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6512 if (rclass != NO_REGS)
6514 enum insn_code icode
6515 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6519 /* This happens when then the reload_[in|out]_optabs have
6520 not been initialised. */
6521 sri->t_icode = CODE_FOR_nothing;
6526 /* Fall back to the default secondary reload handler. */
6527 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6531 /* A C expression whose value is nonzero if pseudos that have been assigned to
6532 registers of class RCLASS would likely be spilled because registers of RCLASS
6533 are needed for spill registers.
6535 The default value of this macro returns 1 if RCLASS has exactly one register
6536 and zero otherwise. On most machines, this default should be used. Only
6537 define this macro to some other expression if pseudo allocated by
6538 `local-alloc.c' end up in memory because their hard registers were needed
6539 for spill registers. If this macro returns nonzero for those classes, those
6540 pseudos will only be allocated by `global.c', which knows how to reallocate
6541 the pseudo to another register. If there would not be another register
6542 available for reallocation, you should not change the definition of this
6543 macro since the only effect of such a definition would be to slow down
6544 register allocation. */
6547 frv_class_likely_spilled_p (enum reg_class rclass)
6557 case FDPIC_FPTR_REGS:
6579 /* An expression for the alignment of a structure field FIELD if the
6580 alignment computed in the usual way is COMPUTED. GCC uses this
6581 value instead of the value in `BIGGEST_ALIGNMENT' or
6582 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6584 /* The definition type of the bit field data is either char, short, long or
6585 long long. The maximum bit size is the number of bits of its own type.
6587 The bit field data is assigned to a storage unit that has an adequate size
6588 for bit field data retention and is located at the smallest address.
6590 Consecutive bit field data are packed at consecutive bits having the same
6591 storage unit, with regard to the type, beginning with the MSB and continuing
6594 If a field to be assigned lies over a bit field type boundary, its
6595 assignment is completed by aligning it with a boundary suitable for the
6598 When a bit field having a bit length of 0 is declared, it is forcibly
6599 assigned to the next storage unit.
6612 &x 00000000 00000000 00000000 00000000
6615 &x+4 00000000 00000000 00000000 00000000
6618 &x+8 00000000 00000000 00000000 00000000
6621 &x+12 00000000 00000000 00000000 00000000
6627 frv_adjust_field_align (tree field, int computed)
6629 /* Make sure that the bitfield is not wider than the type. */
6630 if (DECL_BIT_FIELD (field)
6631 && !DECL_ARTIFICIAL (field))
6633 tree parent = DECL_CONTEXT (field);
6634 tree prev = NULL_TREE;
6637 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6639 if (TREE_CODE (cur) != FIELD_DECL)
6647 /* If this isn't a :0 field and if the previous element is a bitfield
6648 also, see if the type is different, if so, we will need to align the
6649 bit-field to the next boundary. */
6651 && ! DECL_PACKED (field)
6652 && ! integer_zerop (DECL_SIZE (field))
6653 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6655 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6656 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6657 computed = (prev_align > cur_align) ? prev_align : cur_align;
6665 /* A C expression that is nonzero if it is permissible to store a value of mode
6666 MODE in hard register number REGNO (or in several registers starting with
6667 that one). For a machine where all registers are equivalent, a suitable
6670 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6672 It is not necessary for this macro to check for the numbers of fixed
6673 registers, because the allocation mechanism considers them to be always
6676 On some machines, double-precision values must be kept in even/odd register
6677 pairs. The way to implement that is to define this macro to reject odd
6678 register numbers for such modes.
6680 The minimum requirement for a mode to be OK in a register is that the
6681 `movMODE' instruction pattern support moves between the register and any
6682 other hard register for which the mode is OK; and that moving a value into
6683 the register and back out not alter it.
6685 Since the same instruction used to move `SImode' will work for all narrower
6686 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6687 to distinguish between these modes, provided you define patterns `movhi',
6688 etc., to take advantage of this. This is useful because of the interaction
6689 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6690 all integer modes to be tieable.
6692 Many machines have special registers for floating point arithmetic. Often
6693 people assume that floating point machine modes are allowed only in floating
6694 point registers. This is not true. Any registers that can hold integers
6695 can safely *hold* a floating point machine mode, whether or not floating
6696 arithmetic can be done on it in those registers. Integer move instructions
6697 can be used to move the values.
6699 On some machines, though, the converse is true: fixed-point machine modes
6700 may not go in floating registers. This is true if the floating registers
6701 normalize any value stored in them, because storing a non-floating value
6702 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6703 fixed-point machine modes in floating registers. But if the floating
6704 registers do not automatically normalize, if you can store any bit pattern
6705 in one and retrieve it unchanged without a trap, then any machine mode may
6706 go in a floating register, so you can define this macro to say so.
6708 The primary significance of special floating registers is rather that they
6709 are the registers acceptable in floating point arithmetic instructions.
6710 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6711 writing the proper constraints for those instructions.
6713 On some machines, the floating registers are especially slow to access, so
6714 that it is better to store a value in a stack frame than in such a register
6715 if floating point arithmetic is not being done. As long as the floating
6716 registers are not in class `GENERAL_REGS', they will not be used unless some
6717 pattern's constraint asks for one. */
6720 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6730 return ICC_P (regno) || GPR_P (regno);
6733 return CR_P (regno) || GPR_P (regno);
6736 return FCC_P (regno) || GPR_P (regno);
6742 /* Set BASE to the first register in REGNO's class. Set MASK to the
6743 bits that must be clear in (REGNO - BASE) for the register to be
6745 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6749 /* ACCGs store one byte. Two-byte quantities must start in
6750 even-numbered registers, four-byte ones in registers whose
6751 numbers are divisible by four, and so on. */
6753 mask = GET_MODE_SIZE (mode) - 1;
6757 /* The other registers store one word. */
6758 if (GPR_P (regno) || regno == AP_FIRST)
6761 else if (FPR_P (regno))
6764 else if (ACC_P (regno))
6767 else if (SPR_P (regno))
6768 return mode == SImode;
6770 /* Fill in the table. */
6774 /* Anything smaller than an SI is OK in any word-sized register. */
6775 if (GET_MODE_SIZE (mode) < 4)
6778 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6780 return (((regno - base) & mask) == 0);
6787 /* A C expression for the number of consecutive hard registers, starting at
6788 register number REGNO, required to hold a value of mode MODE.
6790 On a machine where all registers are exactly one word, a suitable definition
6793 #define HARD_REGNO_NREGS(REGNO, MODE) \
6794 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6795 / UNITS_PER_WORD)) */
6797 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6798 that we can build the appropriate instructions to properly reload the
6799 values. Also, make the byte-sized accumulator guards use one guard
6803 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6806 return GET_MODE_SIZE (mode);
6808 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6812 /* A C expression for the maximum number of consecutive registers of
6813 class RCLASS needed to hold a value of mode MODE.
6815 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6816 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6817 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6819 This macro helps control the handling of multiple-word values in
6822 This declaration is required. */
6825 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6827 if (rclass == ACCG_REGS)
6828 /* An N-byte value requires N accumulator guards. */
6829 return GET_MODE_SIZE (mode);
6831 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6835 /* A C expression that is nonzero if X is a legitimate constant for an
6836 immediate operand on the target machine. You can assume that X satisfies
6837 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6838 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6841 frv_legitimate_constant_p (rtx x)
6843 enum machine_mode mode = GET_MODE (x);
6845 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6846 means that the move expanders will be expected to deal with most
6847 kinds of constant, regardless of what we return here.
6849 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6850 a constant can be entered into reg_equiv_constant[]. If we return true,
6851 reload can create new instances of the constant whenever it likes.
6853 The idea is therefore to accept as many constants as possible (to give
6854 reload more freedom) while rejecting constants that can only be created
6855 at certain times. In particular, anything with a symbolic component will
6856 require use of the pseudo FDPIC register, which is only available before
6859 return LEGITIMATE_PIC_OPERAND_P (x);
6861 /* All of the integer constants are ok. */
6862 if (GET_CODE (x) != CONST_DOUBLE)
6865 /* double integer constants are ok. */
6866 if (mode == VOIDmode || mode == DImode)
6869 /* 0 is always ok. */
6870 if (x == CONST0_RTX (mode))
6873 /* If floating point is just emulated, allow any constant, since it will be
6874 constructed in the GPRs. */
6875 if (!TARGET_HAS_FPRS)
6878 if (mode == DFmode && !TARGET_DOUBLE)
6881 /* Otherwise store the constant away and do a load. */
6885 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6886 CC_NZ for comparisons against zero in which a single Z or N flag test
6887 is enough, CC_UNS for other unsigned comparisons, and CC for other
6888 signed comparisons. */
6891 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6893 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6902 return y == const0_rtx ? CC_NZmode : CCmode;
6908 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6915 /* A C expression for the cost of moving data from a register in class FROM to
6916 one in class TO. The classes are expressed using the enumeration values
6917 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6918 interpreted relative to that.
6920 It is not required that the cost always equal 2 when FROM is the same as TO;
6921 on some machines it is expensive to move between registers if they are not
6924 If reload sees an insn consisting of a single `set' between two hard
6925 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6926 value of 2, reload does not check to ensure that the constraints of the insn
6927 are met. Setting a cost of other than 2 will allow reload to verify that
6928 the constraints are met. You should do this if the `movM' pattern's
6929 constraints do not allow such copying. */
6931 #define HIGH_COST 40
6932 #define MEDIUM_COST 3
6936 frv_register_move_cost (enum reg_class from, enum reg_class to)
7020 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7021 use ".picptr" to generate safe relocations for PIC code. We also
7022 need a fixup entry for aligned (non-debugging) code. */
7025 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
7027 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
7029 if (GET_CODE (value) == CONST
7030 || GET_CODE (value) == SYMBOL_REF
7031 || GET_CODE (value) == LABEL_REF)
7033 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
7034 && SYMBOL_REF_FUNCTION_P (value))
7036 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
7037 output_addr_const (asm_out_file, value);
7038 fputs (")\n", asm_out_file);
7041 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7042 && frv_function_symbol_referenced_p (value))
7044 if (aligned_p && !TARGET_FDPIC)
7046 static int label_num = 0;
7050 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7051 p = (* targetm.strip_name_encoding) (buf);
7053 fprintf (asm_out_file, "%s:\n", p);
7054 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7055 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7056 fprintf (asm_out_file, "\t.previous\n");
7058 assemble_integer_with_op ("\t.picptr\t", value);
7063 /* We've set the unaligned SI op to NULL, so we always have to
7064 handle the unaligned case here. */
7065 assemble_integer_with_op ("\t.4byte\t", value);
7069 return default_assemble_integer (value, size, aligned_p);
7072 /* Function to set up the backend function structure. */
7074 static struct machine_function *
7075 frv_init_machine_status (void)
7077 return ggc_alloc_cleared_machine_function ();
7080 /* Implement TARGET_SCHED_ISSUE_RATE. */
7083 frv_issue_rate (void)
7088 switch (frv_cpu_type)
7092 case FRV_CPU_SIMPLE:
7100 case FRV_CPU_GENERIC:
7102 case FRV_CPU_TOMCAT:
7110 /* A for_each_rtx callback. If X refers to an accumulator, return
7111 ACC_GROUP_ODD if the bit 2 of the register number is set and
7112 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7116 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7120 if (ACC_P (REGNO (*x)))
7121 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7122 if (ACCG_P (REGNO (*x)))
7123 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7128 /* Return the value of INSN's acc_group attribute. */
7131 frv_acc_group (rtx insn)
7133 /* This distinction only applies to the FR550 packing constraints. */
7134 if (frv_cpu_type != FRV_CPU_FR550)
7135 return ACC_GROUP_NONE;
7136 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7139 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7140 INSN will try to claim first. Since this value depends only on the
7141 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7144 frv_insn_unit (rtx insn)
7146 enum attr_type type;
7148 type = get_attr_type (insn);
7149 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7151 /* We haven't seen this type of instruction before. */
7155 /* Issue the instruction on its own to see which unit it prefers. */
7156 state = alloca (state_size ());
7157 state_reset (state);
7158 state_transition (state, insn);
7160 /* Find out which unit was taken. */
7161 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7162 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7165 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7167 frv_type_to_unit[type] = unit;
7169 return frv_type_to_unit[type];
7172 /* Return true if INSN issues to a branch unit. */
7175 frv_issues_to_branch_unit_p (rtx insn)
7177 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7180 /* The current state of the packing pass, implemented by frv_pack_insns. */
7182 /* The state of the pipeline DFA. */
7185 /* Which hardware registers are set within the current packet,
7186 and the conditions under which they are set. */
7187 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7189 /* The memory locations that have been modified so far in this
7190 packet. MEM is the memref and COND is the regstate_t condition
7191 under which it is set. */
7197 /* The number of valid entries in MEMS. The value is larger than
7198 ARRAY_SIZE (mems) if there were too many mems to record. */
7199 unsigned int num_mems;
7201 /* The maximum number of instructions that can be packed together. */
7202 unsigned int issue_rate;
7204 /* The instructions in the packet, partitioned into groups. */
7205 struct frv_packet_group {
7206 /* How many instructions in the packet belong to this group. */
7207 unsigned int num_insns;
7209 /* A list of the instructions that belong to this group, in the order
7210 they appear in the rtl stream. */
7211 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7213 /* The contents of INSNS after they have been sorted into the correct
7214 assembly-language order. Element X issues to unit X. The list may
7215 contain extra nops. */
7216 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7218 /* The member of frv_nops[] to use in sorted[]. */
7220 } groups[NUM_GROUPS];
7222 /* The instructions that make up the current packet. */
7223 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7224 unsigned int num_insns;
7227 /* Return the regstate_t flags for the given COND_EXEC condition.
7228 Abort if the condition isn't in the right form. */
7231 frv_cond_flags (rtx cond)
7233 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7234 && GET_CODE (XEXP (cond, 0)) == REG
7235 && CR_P (REGNO (XEXP (cond, 0)))
7236 && XEXP (cond, 1) == const0_rtx);
7237 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7238 | (GET_CODE (cond) == NE
7240 : REGSTATE_IF_FALSE));
7244 /* Return true if something accessed under condition COND2 can
7245 conflict with something written under condition COND1. */
7248 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7250 /* If either reference was unconditional, we have a conflict. */
7251 if ((cond1 & REGSTATE_IF_EITHER) == 0
7252 || (cond2 & REGSTATE_IF_EITHER) == 0)
7255 /* The references might conflict if they were controlled by
7257 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7260 /* They definitely conflict if they are controlled by the
7262 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7269 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7270 the current packet. DATA points to a regstate_t that describes the
7271 condition under which *X might be set or used. */
7274 frv_registers_conflict_p_1 (rtx *x, void *data)
7276 unsigned int regno, i;
7279 cond = *(regstate_t *) data;
7281 if (GET_CODE (*x) == REG)
7282 FOR_EACH_REGNO (regno, *x)
7283 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7284 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7287 if (GET_CODE (*x) == MEM)
7289 /* If we ran out of memory slots, assume a conflict. */
7290 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7293 /* Check for output or true dependencies with earlier MEMs. */
7294 for (i = 0; i < frv_packet.num_mems; i++)
7295 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7297 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7301 if (output_dependence (frv_packet.mems[i].mem, *x))
7306 /* The return values of calls aren't significant: they describe
7307 the effect of the call as a whole, not of the insn itself. */
7308 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7310 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7315 /* Check subexpressions. */
7320 /* Return true if something in X might depend on an instruction
7321 in the current packet. */
7324 frv_registers_conflict_p (rtx x)
7329 if (GET_CODE (x) == COND_EXEC)
7331 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7334 flags |= frv_cond_flags (XEXP (x, 0));
7337 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7341 /* A note_stores callback. DATA points to the regstate_t condition
7342 under which X is modified. Update FRV_PACKET accordingly. */
7345 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7349 if (GET_CODE (x) == REG)
7350 FOR_EACH_REGNO (regno, x)
7351 frv_packet.regstate[regno] |= *(regstate_t *) data;
7353 if (GET_CODE (x) == MEM)
7355 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7357 frv_packet.mems[frv_packet.num_mems].mem = x;
7358 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7360 frv_packet.num_mems++;
7365 /* Update the register state information for an instruction whose
7369 frv_registers_update (rtx x)
7373 flags = REGSTATE_MODIFIED;
7374 if (GET_CODE (x) == COND_EXEC)
7376 flags |= frv_cond_flags (XEXP (x, 0));
7379 note_stores (x, frv_registers_update_1, &flags);
7383 /* Initialize frv_packet for the start of a new packet. */
7386 frv_start_packet (void)
7388 enum frv_insn_group group;
7390 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7391 frv_packet.num_mems = 0;
7392 frv_packet.num_insns = 0;
7393 for (group = 0; group < NUM_GROUPS; group++)
7394 frv_packet.groups[group].num_insns = 0;
7398 /* Likewise for the start of a new basic block. */
7401 frv_start_packet_block (void)
7403 state_reset (frv_packet.dfa_state);
7404 frv_start_packet ();
7408 /* Finish the current packet, if any, and start a new one. Call
7409 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7412 frv_finish_packet (void (*handle_packet) (void))
7414 if (frv_packet.num_insns > 0)
7417 state_transition (frv_packet.dfa_state, 0);
7418 frv_start_packet ();
7423 /* Return true if INSN can be added to the current packet. Update
7424 the DFA state on success. */
7427 frv_pack_insn_p (rtx insn)
7429 /* See if the packet is already as long as it can be. */
7430 if (frv_packet.num_insns == frv_packet.issue_rate)
7433 /* If the scheduler thought that an instruction should start a packet,
7434 it's usually a good idea to believe it. It knows much more about
7435 the latencies than we do.
7437 There are some exceptions though:
7439 - Conditional instructions are scheduled on the assumption that
7440 they will be executed. This is usually a good thing, since it
7441 tends to avoid unnecessary stalls in the conditional code.
7442 But we want to pack conditional instructions as tightly as
7443 possible, in order to optimize the case where they aren't
7446 - The scheduler will always put branches on their own, even
7447 if there's no real dependency.
7449 - There's no point putting a call in its own packet unless
7451 if (frv_packet.num_insns > 0
7452 && GET_CODE (insn) == INSN
7453 && GET_MODE (insn) == TImode
7454 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7457 /* Check for register conflicts. Don't do this for setlo since any
7458 conflict will be with the partnering sethi, with which it can
7460 if (get_attr_type (insn) != TYPE_SETLO)
7461 if (frv_registers_conflict_p (PATTERN (insn)))
7464 return state_transition (frv_packet.dfa_state, insn) < 0;
7468 /* Add instruction INSN to the current packet. */
7471 frv_add_insn_to_packet (rtx insn)
7473 struct frv_packet_group *packet_group;
7475 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7476 packet_group->insns[packet_group->num_insns++] = insn;
7477 frv_packet.insns[frv_packet.num_insns++] = insn;
7479 frv_registers_update (PATTERN (insn));
7483 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7484 packet ends in a branch or call, insert the nop before it, otherwise
7488 frv_insert_nop_in_packet (rtx insn)
7490 struct frv_packet_group *packet_group;
7493 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7494 last = frv_packet.insns[frv_packet.num_insns - 1];
7495 if (GET_CODE (last) != INSN)
7497 insn = emit_insn_before (PATTERN (insn), last);
7498 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7499 frv_packet.insns[frv_packet.num_insns++] = last;
7503 insn = emit_insn_after (PATTERN (insn), last);
7504 frv_packet.insns[frv_packet.num_insns++] = insn;
7506 packet_group->insns[packet_group->num_insns++] = insn;
7510 /* If packing is enabled, divide the instructions into packets and
7511 return true. Call HANDLE_PACKET for each complete packet. */
7514 frv_for_each_packet (void (*handle_packet) (void))
7516 rtx insn, next_insn;
7518 frv_packet.issue_rate = frv_issue_rate ();
7520 /* Early exit if we don't want to pack insns. */
7522 || !flag_schedule_insns_after_reload
7523 || !TARGET_VLIW_BRANCH
7524 || frv_packet.issue_rate == 1)
7527 /* Set up the initial packing state. */
7529 frv_packet.dfa_state = alloca (state_size ());
7531 frv_start_packet_block ();
7532 for (insn = get_insns (); insn != 0; insn = next_insn)
7537 code = GET_CODE (insn);
7538 next_insn = NEXT_INSN (insn);
7540 if (code == CODE_LABEL)
7542 frv_finish_packet (handle_packet);
7543 frv_start_packet_block ();
7547 switch (GET_CODE (PATTERN (insn)))
7556 /* Calls mustn't be packed on a TOMCAT. */
7557 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7558 frv_finish_packet (handle_packet);
7560 /* Since the last instruction in a packet determines the EH
7561 region, any exception-throwing instruction must come at
7562 the end of reordered packet. Insns that issue to a
7563 branch unit are bound to come last; for others it's
7564 too hard to predict. */
7565 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7566 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7567 frv_finish_packet (handle_packet);
7569 /* Finish the current packet if we can't add INSN to it.
7570 Simulate cycles until INSN is ready to issue. */
7571 if (!frv_pack_insn_p (insn))
7573 frv_finish_packet (handle_packet);
7574 while (!frv_pack_insn_p (insn))
7575 state_transition (frv_packet.dfa_state, 0);
7578 /* Add the instruction to the packet. */
7579 frv_add_insn_to_packet (insn);
7581 /* Calls and jumps end a packet, as do insns that throw
7583 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7584 frv_finish_packet (handle_packet);
7588 frv_finish_packet (handle_packet);
7593 /* Subroutine of frv_sort_insn_group. We are trying to sort
7594 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7595 language order. We have already picked a new position for
7596 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7597 These instructions will occupy elements [0, LOWER_SLOT) and
7598 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7599 the DFA state after issuing these instructions.
7601 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7602 of the unused instructions. Return true if one such permutation gives
7603 a valid ordering, leaving the successful permutation in sorted[].
7604 Do not modify sorted[] until a valid permutation is found. */
7607 frv_sort_insn_group_1 (enum frv_insn_group group,
7608 unsigned int lower_slot, unsigned int upper_slot,
7609 unsigned int issued, unsigned int num_insns,
7612 struct frv_packet_group *packet_group;
7618 /* Early success if we've filled all the slots. */
7619 if (lower_slot == upper_slot)
7622 packet_group = &frv_packet.groups[group];
7623 dfa_size = state_size ();
7624 test_state = alloca (dfa_size);
7626 /* Try issuing each unused instruction. */
7627 for (i = num_insns - 1; i + 1 != 0; i--)
7628 if (~issued & (1 << i))
7630 insn = packet_group->sorted[i];
7631 memcpy (test_state, state, dfa_size);
7632 if (state_transition (test_state, insn) < 0
7633 && cpu_unit_reservation_p (test_state,
7634 NTH_UNIT (group, upper_slot - 1))
7635 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7636 issued | (1 << i), num_insns,
7639 packet_group->sorted[upper_slot - 1] = insn;
7647 /* Compare two instructions by their frv_insn_unit. */
7650 frv_compare_insns (const void *first, const void *second)
7652 const rtx *const insn1 = (rtx const *) first,
7653 *const insn2 = (rtx const *) second;
7654 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7657 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7658 and sort it into assembly language order. See frv.md for a description of
7662 frv_sort_insn_group (enum frv_insn_group group)
7664 struct frv_packet_group *packet_group;
7665 unsigned int first, i, nop, max_unit, num_slots;
7666 state_t state, test_state;
7669 packet_group = &frv_packet.groups[group];
7671 /* Assume no nop is needed. */
7672 packet_group->nop = 0;
7674 if (packet_group->num_insns == 0)
7677 /* Copy insns[] to sorted[]. */
7678 memcpy (packet_group->sorted, packet_group->insns,
7679 sizeof (rtx) * packet_group->num_insns);
7681 /* Sort sorted[] by the unit that each insn tries to take first. */
7682 if (packet_group->num_insns > 1)
7683 qsort (packet_group->sorted, packet_group->num_insns,
7684 sizeof (rtx), frv_compare_insns);
7686 /* That's always enough for branch and control insns. */
7687 if (group == GROUP_B || group == GROUP_C)
7690 dfa_size = state_size ();
7691 state = alloca (dfa_size);
7692 test_state = alloca (dfa_size);
7694 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7695 consecutively and such that the DFA takes unit X when sorted[X]
7696 is added. Set STATE to the new DFA state. */
7697 state_reset (test_state);
7698 for (first = 0; first < packet_group->num_insns; first++)
7700 memcpy (state, test_state, dfa_size);
7701 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7702 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7706 /* If all the instructions issued in ascending order, we're done. */
7707 if (first == packet_group->num_insns)
7710 /* Add nops to the end of sorted[] and try each permutation until
7711 we find one that works. */
7712 for (nop = 0; nop < frv_num_nops; nop++)
7714 max_unit = frv_insn_unit (frv_nops[nop]);
7715 if (frv_unit_groups[max_unit] == group)
7717 packet_group->nop = frv_nops[nop];
7718 num_slots = UNIT_NUMBER (max_unit) + 1;
7719 for (i = packet_group->num_insns; i < num_slots; i++)
7720 packet_group->sorted[i] = frv_nops[nop];
7721 if (frv_sort_insn_group_1 (group, first, num_slots,
7722 (1 << first) - 1, num_slots, state))
7729 /* Sort the current packet into assembly-language order. Set packing
7730 flags as appropriate. */
7733 frv_reorder_packet (void)
7735 unsigned int cursor[NUM_GROUPS];
7736 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7737 unsigned int unit, to, from;
7738 enum frv_insn_group group;
7739 struct frv_packet_group *packet_group;
7741 /* First sort each group individually. */
7742 for (group = 0; group < NUM_GROUPS; group++)
7745 frv_sort_insn_group (group);
7748 /* Go through the unit template and try add an instruction from
7749 that unit's group. */
7751 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7753 group = frv_unit_groups[unit];
7754 packet_group = &frv_packet.groups[group];
7755 if (cursor[group] < packet_group->num_insns)
7757 /* frv_reorg should have added nops for us. */
7758 gcc_assert (packet_group->sorted[cursor[group]]
7759 != packet_group->nop);
7760 insns[to++] = packet_group->sorted[cursor[group]++];
7764 gcc_assert (to == frv_packet.num_insns);
7766 /* Clear the last instruction's packing flag, thus marking the end of
7767 a packet. Reorder the other instructions relative to it. */
7768 CLEAR_PACKING_FLAG (insns[to - 1]);
7769 for (from = 0; from < to - 1; from++)
7771 remove_insn (insns[from]);
7772 add_insn_before (insns[from], insns[to - 1], NULL);
7773 SET_PACKING_FLAG (insns[from]);
7778 /* Divide instructions into packets. Reorder the contents of each
7779 packet so that they are in the correct assembly-language order.
7781 Since this pass can change the raw meaning of the rtl stream, it must
7782 only be called at the last minute, just before the instructions are
7786 frv_pack_insns (void)
7788 if (frv_for_each_packet (frv_reorder_packet))
7789 frv_insn_packing_flag = 0;
7791 frv_insn_packing_flag = -1;
7794 /* See whether we need to add nops to group GROUP in order to
7795 make a valid packet. */
7798 frv_fill_unused_units (enum frv_insn_group group)
7800 unsigned int non_nops, nops, i;
7801 struct frv_packet_group *packet_group;
7803 packet_group = &frv_packet.groups[group];
7805 /* Sort the instructions into assembly-language order.
7806 Use nops to fill slots that are otherwise unused. */
7807 frv_sort_insn_group (group);
7809 /* See how many nops are needed before the final useful instruction. */
7811 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7812 while (packet_group->sorted[i++] == packet_group->nop)
7815 /* Insert that many nops into the instruction stream. */
7817 frv_insert_nop_in_packet (packet_group->nop);
7820 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7823 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7825 if (io1->const_address != 0 && io2->const_address != 0)
7826 return io1->const_address == io2->const_address;
7828 if (io1->var_address != 0 && io2->var_address != 0)
7829 return rtx_equal_p (io1->var_address, io2->var_address);
7834 /* Return true if operations IO1 and IO2 are guaranteed to complete
7838 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7840 /* The order of writes is always preserved. */
7841 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7844 /* The order of reads isn't preserved. */
7845 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7848 /* One operation is a write and the other is (or could be) a read.
7849 The order is only guaranteed if the accesses are to the same
7851 return frv_same_doubleword_p (io1, io2);
7854 /* Generalize I/O operation X so that it covers both X and Y. */
7857 frv_io_union (struct frv_io *x, const struct frv_io *y)
7859 if (x->type != y->type)
7860 x->type = FRV_IO_UNKNOWN;
7861 if (!frv_same_doubleword_p (x, y))
7863 x->const_address = 0;
7868 /* Fill IO with information about the load or store associated with
7869 membar instruction INSN. */
7872 frv_extract_membar (struct frv_io *io, rtx insn)
7874 extract_insn (insn);
7875 io->type = INTVAL (recog_data.operand[2]);
7876 io->const_address = INTVAL (recog_data.operand[1]);
7877 io->var_address = XEXP (recog_data.operand[0], 0);
7880 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7881 if X is a register and *DATA depends on X. */
7884 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7886 rtx *other = (rtx *) data;
7888 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7892 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7893 Remove every modified register from the set. */
7896 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7898 HARD_REG_SET *set = (HARD_REG_SET *) data;
7902 FOR_EACH_REGNO (regno, x)
7903 CLEAR_HARD_REG_BIT (*set, regno);
7906 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7907 Add every register in *X to the set. */
7910 frv_io_handle_use_1 (rtx *x, void *data)
7912 HARD_REG_SET *set = (HARD_REG_SET *) data;
7916 FOR_EACH_REGNO (regno, *x)
7917 SET_HARD_REG_BIT (*set, regno);
7922 /* A note_stores callback that applies frv_io_handle_use_1 to an
7923 entire rhs value. */
7926 frv_io_handle_use (rtx *x, void *data)
7928 for_each_rtx (x, frv_io_handle_use_1, data);
7931 /* Go through block BB looking for membars to remove. There are two
7932 cases where intra-block analysis is enough:
7934 - a membar is redundant if it occurs between two consecutive I/O
7935 operations and if those operations are guaranteed to complete
7938 - a membar for a __builtin_read is redundant if the result is
7939 used before the next I/O operation is issued.
7941 If the last membar in the block could not be removed, and there
7942 are guaranteed to be no I/O operations between that membar and
7943 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7946 Describe the block's first I/O operation in *NEXT_IO. Describe
7947 an unknown operation if the block doesn't do any I/O. */
7950 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7953 HARD_REG_SET used_regs;
7954 rtx next_membar, set, insn;
7957 /* NEXT_IO is the next I/O operation to be performed after the current
7958 instruction. It starts off as being an unknown operation. */
7959 memset (next_io, 0, sizeof (*next_io));
7961 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7962 next_is_end_p = true;
7964 /* If the current instruction is a __builtin_read or __builtin_write,
7965 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7966 is null if the membar has already been deleted.
7968 Note that the initialization here should only be needed to
7969 suppress warnings. */
7972 /* USED_REGS is the set of registers that are used before the
7973 next I/O instruction. */
7974 CLEAR_HARD_REG_SET (used_regs);
7976 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7977 if (GET_CODE (insn) == CALL_INSN)
7979 /* We can't predict what a call will do to volatile memory. */
7980 memset (next_io, 0, sizeof (struct frv_io));
7981 next_is_end_p = false;
7982 CLEAR_HARD_REG_SET (used_regs);
7984 else if (INSN_P (insn))
7985 switch (recog_memoized (insn))
7987 case CODE_FOR_optional_membar_qi:
7988 case CODE_FOR_optional_membar_hi:
7989 case CODE_FOR_optional_membar_si:
7990 case CODE_FOR_optional_membar_di:
7994 /* Local information isn't enough to decide whether this
7995 membar is needed. Stash it away for later. */
7996 *last_membar = insn;
7997 frv_extract_membar (next_io, insn);
7998 next_is_end_p = false;
8002 /* Check whether the I/O operation before INSN could be
8003 reordered with one described by NEXT_IO. If it can't,
8004 INSN will not be needed. */
8005 struct frv_io prev_io;
8007 frv_extract_membar (&prev_io, insn);
8008 if (frv_io_fixed_order_p (&prev_io, next_io))
8012 ";; [Local] Removing membar %d since order"
8013 " of accesses is guaranteed\n",
8014 INSN_UID (next_membar));
8016 insn = NEXT_INSN (insn);
8017 delete_insn (next_membar);
8025 /* Invalidate NEXT_IO's address if it depends on something that
8026 is clobbered by INSN. */
8027 if (next_io->var_address)
8028 note_stores (PATTERN (insn), frv_io_check_address,
8029 &next_io->var_address);
8031 /* If the next membar is associated with a __builtin_read,
8032 see if INSN reads from that address. If it does, and if
8033 the destination register is used before the next I/O access,
8034 there is no need for the membar. */
8035 set = PATTERN (insn);
8036 if (next_io->type == FRV_IO_READ
8037 && next_io->var_address != 0
8039 && GET_CODE (set) == SET
8040 && GET_CODE (SET_DEST (set)) == REG
8041 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8045 src = SET_SRC (set);
8046 if (GET_CODE (src) == ZERO_EXTEND)
8047 src = XEXP (src, 0);
8049 if (GET_CODE (src) == MEM
8050 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8054 ";; [Local] Removing membar %d since the target"
8055 " of %d is used before the I/O operation\n",
8056 INSN_UID (next_membar), INSN_UID (insn));
8058 if (next_membar == *last_membar)
8061 delete_insn (next_membar);
8066 /* If INSN has volatile references, forget about any registers
8067 that are used after it. Otherwise forget about uses that
8068 are (or might be) defined by INSN. */
8069 if (volatile_refs_p (PATTERN (insn)))
8070 CLEAR_HARD_REG_SET (used_regs);
8072 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8074 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8079 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8080 FIRST_IO[X] describes the first operation performed by basic block X. */
8083 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8086 struct frv_io this_io, next_io;
8090 /* We need to keep the membar if there is an edge to the exit block. */
8091 FOR_EACH_EDGE (succ, ei, bb->succs)
8092 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8093 if (succ->dest == EXIT_BLOCK_PTR)
8096 /* Work out the union of all successor blocks. */
8097 ei = ei_start (bb->succs);
8098 ei_cond (ei, &succ);
8099 /* next_io = first_io[bb->succ->dest->index]; */
8100 next_io = first_io[succ->dest->index];
8101 ei = ei_start (bb->succs);
8102 if (ei_cond (ei, &succ))
8104 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8105 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8106 frv_io_union (&next_io, &first_io[succ->dest->index]);
8111 frv_extract_membar (&this_io, membar);
8112 if (frv_io_fixed_order_p (&this_io, &next_io))
8116 ";; [Global] Removing membar %d since order of accesses"
8117 " is guaranteed\n", INSN_UID (membar));
8119 delete_insn (membar);
8123 /* Remove redundant membars from the current function. */
8126 frv_optimize_membar (void)
8129 struct frv_io *first_io;
8132 compute_bb_for_insn ();
8133 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8134 last_membar = XCNEWVEC (rtx, last_basic_block);
8137 frv_optimize_membar_local (bb, &first_io[bb->index],
8138 &last_membar[bb->index]);
8141 if (last_membar[bb->index] != 0)
8142 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8148 /* Used by frv_reorg to keep track of the current packet's address. */
8149 static unsigned int frv_packet_address;
8151 /* If the current packet falls through to a label, try to pad the packet
8152 with nops in order to fit the label's alignment requirements. */
8155 frv_align_label (void)
8157 unsigned int alignment, target, nop;
8158 rtx x, last, barrier, label;
8160 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8161 maximum alignment of that packet, LABEL to the last label between
8162 the packets, and BARRIER to the last barrier. */
8163 last = frv_packet.insns[frv_packet.num_insns - 1];
8164 label = barrier = 0;
8166 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8170 unsigned int subalign = 1 << label_to_alignment (x);
8171 alignment = MAX (alignment, subalign);
8178 /* If -malign-labels, and the packet falls through to an unaligned
8179 label, try introducing a nop to align that label to 8 bytes. */
8180 if (TARGET_ALIGN_LABELS
8183 && frv_packet.num_insns < frv_packet.issue_rate)
8184 alignment = MAX (alignment, 8);
8186 /* Advance the address to the end of the current packet. */
8187 frv_packet_address += frv_packet.num_insns * 4;
8189 /* Work out the target address, after alignment. */
8190 target = (frv_packet_address + alignment - 1) & -alignment;
8192 /* If the packet falls through to the label, try to find an efficient
8193 padding sequence. */
8196 /* First try adding nops to the current packet. */
8197 for (nop = 0; nop < frv_num_nops; nop++)
8198 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8200 frv_insert_nop_in_packet (frv_nops[nop]);
8201 frv_packet_address += 4;
8204 /* If we still haven't reached the target, add some new packets that
8205 contain only nops. If there are two types of nop, insert an
8206 alternating sequence of frv_nops[0] and frv_nops[1], which will
8207 lead to packets like:
8214 etc. Just emit frv_nops[0] if that's the only nop we have. */
8215 last = frv_packet.insns[frv_packet.num_insns - 1];
8217 while (frv_packet_address < target)
8219 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8220 frv_packet_address += 4;
8221 if (frv_num_nops > 1)
8226 frv_packet_address = target;
8229 /* Subroutine of frv_reorg, called after each packet has been constructed
8233 frv_reorg_packet (void)
8235 frv_fill_unused_units (GROUP_I);
8236 frv_fill_unused_units (GROUP_FM);
8240 /* Add an instruction with pattern NOP to frv_nops[]. */
8243 frv_register_nop (rtx nop)
8245 nop = make_insn_raw (nop);
8246 NEXT_INSN (nop) = 0;
8247 PREV_INSN (nop) = 0;
8248 frv_nops[frv_num_nops++] = nop;
8251 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8252 into packets and check whether we need to insert nops in order to
8253 fulfill the processor's issue requirements. Also, if the user has
8254 requested a certain alignment for a label, try to meet that alignment
8255 by inserting nops in the previous packet. */
8260 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8261 frv_optimize_membar ();
8264 frv_register_nop (gen_nop ());
8266 frv_register_nop (gen_mnop ());
8267 if (TARGET_HARD_FLOAT)
8268 frv_register_nop (gen_fnop ());
8270 /* Estimate the length of each branch. Although this may change after
8271 we've inserted nops, it will only do so in big functions. */
8272 shorten_branches (get_insns ());
8274 frv_packet_address = 0;
8275 frv_for_each_packet (frv_reorg_packet);
8278 #define def_builtin(name, type, code) \
8279 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8281 struct builtin_description
8283 enum insn_code icode;
8285 enum frv_builtins code;
8286 enum rtx_code comparison;
8290 /* Media intrinsics that take a single, constant argument. */
8292 static struct builtin_description bdesc_set[] =
8294 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8297 /* Media intrinsics that take just one argument. */
8299 static struct builtin_description bdesc_1arg[] =
8301 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8302 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8303 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8304 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8305 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8306 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8309 /* Media intrinsics that take two arguments. */
8311 static struct builtin_description bdesc_2arg[] =
8313 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8314 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8315 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8316 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8317 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8318 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8319 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8320 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8321 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8322 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8323 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8324 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8325 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8326 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8327 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8328 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8329 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8330 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8331 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8332 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8333 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8334 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8335 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8336 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8337 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8338 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8339 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8342 /* Integer intrinsics that take two arguments and have no return value. */
8344 static struct builtin_description bdesc_int_void2arg[] =
8346 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8347 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8348 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8351 static struct builtin_description bdesc_prefetches[] =
8353 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8354 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8357 /* Media intrinsics that take two arguments, the first being an ACC number. */
8359 static struct builtin_description bdesc_cut[] =
8361 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8362 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8363 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8366 /* Two-argument media intrinsics with an immediate second argument. */
8368 static struct builtin_description bdesc_2argimm[] =
8370 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8371 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8372 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8373 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8374 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8375 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8376 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8377 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8378 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8379 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8380 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8381 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8382 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8383 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8384 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8385 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8386 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8389 /* Media intrinsics that take two arguments and return void, the first argument
8390 being a pointer to 4 words in memory. */
8392 static struct builtin_description bdesc_void2arg[] =
8394 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8395 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8398 /* Media intrinsics that take three arguments, the first being a const_int that
8399 denotes an accumulator, and that return void. */
8401 static struct builtin_description bdesc_void3arg[] =
8403 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8404 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8405 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8406 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8407 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8408 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8409 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8410 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8411 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8412 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8413 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8414 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8415 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8416 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8417 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8418 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8419 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8420 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8421 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8422 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8423 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8424 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8425 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8426 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8427 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8430 /* Media intrinsics that take two accumulator numbers as argument and
8433 static struct builtin_description bdesc_voidacc[] =
8435 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8436 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8437 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8438 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8439 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8440 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8443 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8444 a normal move and the ICODE is for the membar. */
8446 static struct builtin_description bdesc_loads[] =
8448 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8449 FRV_BUILTIN_READ8, 0, 0 },
8450 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8451 FRV_BUILTIN_READ16, 0, 0 },
8452 { CODE_FOR_optional_membar_si, "__builtin_read32",
8453 FRV_BUILTIN_READ32, 0, 0 },
8454 { CODE_FOR_optional_membar_di, "__builtin_read64",
8455 FRV_BUILTIN_READ64, 0, 0 }
8458 /* Likewise stores. */
8460 static struct builtin_description bdesc_stores[] =
8462 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8463 FRV_BUILTIN_WRITE8, 0, 0 },
8464 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8465 FRV_BUILTIN_WRITE16, 0, 0 },
8466 { CODE_FOR_optional_membar_si, "__builtin_write32",
8467 FRV_BUILTIN_WRITE32, 0, 0 },
8468 { CODE_FOR_optional_membar_di, "__builtin_write64",
8469 FRV_BUILTIN_WRITE64, 0, 0 },
8472 /* Initialize media builtins. */
8475 frv_init_builtins (void)
8477 tree endlink = void_list_node;
8478 tree accumulator = integer_type_node;
8479 tree integer = integer_type_node;
8480 tree voidt = void_type_node;
8481 tree uhalf = short_unsigned_type_node;
8482 tree sword1 = long_integer_type_node;
8483 tree uword1 = long_unsigned_type_node;
8484 tree sword2 = long_long_integer_type_node;
8485 tree uword2 = long_long_unsigned_type_node;
8486 tree uword4 = build_pointer_type (uword1);
8487 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8488 tree ubyte = unsigned_char_type_node;
8489 tree iacc = integer_type_node;
8491 #define UNARY(RET, T1) \
8492 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8494 #define BINARY(RET, T1, T2) \
8495 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8496 tree_cons (NULL_TREE, T2, endlink)))
8498 #define TRINARY(RET, T1, T2, T3) \
8499 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8500 tree_cons (NULL_TREE, T2, \
8501 tree_cons (NULL_TREE, T3, endlink))))
8503 #define QUAD(RET, T1, T2, T3, T4) \
8504 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8505 tree_cons (NULL_TREE, T2, \
8506 tree_cons (NULL_TREE, T3, \
8507 tree_cons (NULL_TREE, T4, endlink)))))
8509 tree void_ftype_void = build_function_type (voidt, endlink);
8511 tree void_ftype_acc = UNARY (voidt, accumulator);
8512 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8513 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8514 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8515 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8516 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8517 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8518 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8519 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8521 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8522 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8523 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8524 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8525 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8526 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8527 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8528 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8529 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8530 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8531 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8533 tree sw1_ftype_int = UNARY (sword1, integer);
8534 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8535 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8537 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8538 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8539 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8540 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8541 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8542 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8544 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8545 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8546 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8547 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8548 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8549 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8550 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8551 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8552 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8553 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8554 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8555 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8556 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8557 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8558 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8559 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8560 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8562 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8563 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8564 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8565 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8566 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8567 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8568 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8569 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8570 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8571 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8572 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8573 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8574 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8575 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8576 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8577 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8578 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8579 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8580 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8581 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8582 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8583 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8584 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8585 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8586 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8587 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8588 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8589 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8590 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8591 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8592 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8593 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8594 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8595 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8596 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8597 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8598 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8599 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8600 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8601 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8602 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8603 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8604 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8605 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8606 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8607 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8608 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8609 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8610 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8611 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8612 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8613 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8614 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8615 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8616 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8617 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8618 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8619 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8620 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8621 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8622 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8623 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8624 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8625 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8626 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8627 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8628 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8629 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8630 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8631 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8632 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8633 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8634 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8635 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8636 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8637 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8638 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8639 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8640 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8641 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8642 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8643 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8644 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8645 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8646 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8647 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8648 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8649 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8650 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8651 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8652 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8653 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8654 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8655 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8656 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8657 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8658 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8659 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8660 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8661 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8662 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8663 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8664 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8665 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8666 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8667 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8668 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8669 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8671 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8672 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8673 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8674 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8682 /* Set the names for various arithmetic operations according to the
8685 frv_init_libfuncs (void)
8687 set_optab_libfunc (smod_optab, SImode, "__modi");
8688 set_optab_libfunc (umod_optab, SImode, "__umodi");
8690 set_optab_libfunc (add_optab, DImode, "__addll");
8691 set_optab_libfunc (sub_optab, DImode, "__subll");
8692 set_optab_libfunc (smul_optab, DImode, "__mulll");
8693 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8694 set_optab_libfunc (smod_optab, DImode, "__modll");
8695 set_optab_libfunc (umod_optab, DImode, "__umodll");
8696 set_optab_libfunc (and_optab, DImode, "__andll");
8697 set_optab_libfunc (ior_optab, DImode, "__orll");
8698 set_optab_libfunc (xor_optab, DImode, "__xorll");
8699 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8701 set_optab_libfunc (add_optab, SFmode, "__addf");
8702 set_optab_libfunc (sub_optab, SFmode, "__subf");
8703 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8704 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8706 set_optab_libfunc (add_optab, DFmode, "__addd");
8707 set_optab_libfunc (sub_optab, DFmode, "__subd");
8708 set_optab_libfunc (smul_optab, DFmode, "__muld");
8709 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8711 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8712 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8714 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8715 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8716 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8717 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8719 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8720 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8721 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8722 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8724 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8725 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8726 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8727 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8730 /* Convert an integer constant to an accumulator register. ICODE is the
8731 code of the target instruction, OPNUM is the number of the
8732 accumulator operand and OPVAL is the constant integer. Try both
8733 ACC and ACCG registers; only report an error if neither fit the
8737 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8742 /* ACCs and ACCGs are implicit global registers if media intrinsics
8743 are being used. We set up this lazily to avoid creating lots of
8744 unnecessary call_insn rtl in non-media code. */
8745 for (i = 0; i <= ACC_MASK; i++)
8746 if ((i & ACC_MASK) == i)
8747 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8749 if (GET_CODE (opval) != CONST_INT)
8751 error ("accumulator is not a constant integer");
8754 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8756 error ("accumulator number is out of bounds");
8760 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8761 ACC_FIRST + INTVAL (opval));
8762 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8763 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8765 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8767 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8773 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8776 static enum machine_mode
8777 frv_matching_accg_mode (enum machine_mode mode)
8795 /* Given that a __builtin_read or __builtin_write function is accessing
8796 address ADDRESS, return the value that should be used as operand 1
8800 frv_io_address_cookie (rtx address)
8802 return (GET_CODE (address) == CONST_INT
8803 ? GEN_INT (INTVAL (address) / 8 * 8)
8807 /* Return the accumulator guard that should be paired with accumulator
8808 register ACC. The mode of the returned register is in the same
8809 class as ACC, but is four times smaller. */
8812 frv_matching_accg_for_acc (rtx acc)
8814 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8815 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8818 /* Read the requested argument from the call EXP given by INDEX.
8819 Return the value as an rtx. */
8822 frv_read_argument (tree exp, unsigned int index)
8824 return expand_expr (CALL_EXPR_ARG (exp, index),
8825 NULL_RTX, VOIDmode, 0);
8828 /* Like frv_read_argument, but interpret the argument as the number
8829 of an IACC register and return a (reg:MODE ...) rtx for it. */
8832 frv_read_iacc_argument (enum machine_mode mode, tree call,
8838 op = frv_read_argument (call, index);
8839 if (GET_CODE (op) != CONST_INT
8841 || INTVAL (op) > IACC_LAST - IACC_FIRST
8842 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8844 error ("invalid IACC argument");
8848 /* IACCs are implicit global registers. We set up this lazily to
8849 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8851 regno = INTVAL (op) + IACC_FIRST;
8852 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8853 global_regs[regno + i] = 1;
8855 return gen_rtx_REG (mode, regno);
8858 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8859 The instruction should require a constant operand of some sort. The
8860 function prints an error if OPVAL is not valid. */
8863 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8865 if (GET_CODE (opval) != CONST_INT)
8867 error ("%qs expects a constant argument", insn_data[icode].name);
8870 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8872 error ("constant argument out of range for %qs", insn_data[icode].name);
8878 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8879 if it's not null, has the right mode, and satisfies operand 0's
8883 frv_legitimize_target (enum insn_code icode, rtx target)
8885 enum machine_mode mode = insn_data[icode].operand[0].mode;
8888 || GET_MODE (target) != mode
8889 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8890 return gen_reg_rtx (mode);
8895 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8896 check whether ARG satisfies the operand's constraints. If it doesn't,
8897 copy ARG to a temporary register and return that. Otherwise return ARG
8901 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8903 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8905 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8908 return copy_to_mode_reg (mode, arg);
8911 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8914 frv_volatile_memref (enum machine_mode mode, rtx arg)
8918 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8919 MEM_VOLATILE_P (mem) = 1;
8923 /* Expand builtins that take a single, constant argument. At the moment,
8924 only MHDSETS falls into this category. */
8927 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8930 rtx op0 = frv_read_argument (call, 0);
8932 if (! frv_check_constant_argument (icode, 1, op0))
8935 target = frv_legitimize_target (icode, target);
8936 pat = GEN_FCN (icode) (target, op0);
8944 /* Expand builtins that take one operand. */
8947 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8950 rtx op0 = frv_read_argument (call, 0);
8952 target = frv_legitimize_target (icode, target);
8953 op0 = frv_legitimize_argument (icode, 1, op0);
8954 pat = GEN_FCN (icode) (target, op0);
8962 /* Expand builtins that take two operands. */
8965 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8968 rtx op0 = frv_read_argument (call, 0);
8969 rtx op1 = frv_read_argument (call, 1);
8971 target = frv_legitimize_target (icode, target);
8972 op0 = frv_legitimize_argument (icode, 1, op0);
8973 op1 = frv_legitimize_argument (icode, 2, op1);
8974 pat = GEN_FCN (icode) (target, op0, op1);
8982 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8986 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8989 rtx op0 = frv_read_argument (call, 0);
8990 rtx op1 = frv_read_argument (call, 1);
8993 target = frv_legitimize_target (icode, target);
8994 op0 = frv_int_to_acc (icode, 1, op0);
8998 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9000 if (! frv_check_constant_argument (icode, 2, op1))
9004 op1 = frv_legitimize_argument (icode, 2, op1);
9006 op2 = frv_matching_accg_for_acc (op0);
9007 pat = GEN_FCN (icode) (target, op0, op1, op2);
9015 /* Expand builtins that take two operands and the second is immediate. */
9018 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
9021 rtx op0 = frv_read_argument (call, 0);
9022 rtx op1 = frv_read_argument (call, 1);
9024 if (! frv_check_constant_argument (icode, 2, op1))
9027 target = frv_legitimize_target (icode, target);
9028 op0 = frv_legitimize_argument (icode, 1, op0);
9029 pat = GEN_FCN (icode) (target, op0, op1);
9037 /* Expand builtins that take two operands, the first operand being a pointer to
9038 ints and return void. */
9041 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9044 rtx op0 = frv_read_argument (call, 0);
9045 rtx op1 = frv_read_argument (call, 1);
9046 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9049 if (GET_CODE (op0) != MEM)
9053 if (! offsettable_address_p (0, mode0, op0))
9055 reg = gen_reg_rtx (Pmode);
9056 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9059 op0 = gen_rtx_MEM (SImode, reg);
9062 addr = XEXP (op0, 0);
9063 if (! offsettable_address_p (0, mode0, addr))
9064 addr = copy_to_mode_reg (Pmode, op0);
9066 op0 = change_address (op0, V4SImode, addr);
9067 op1 = frv_legitimize_argument (icode, 1, op1);
9068 pat = GEN_FCN (icode) (op0, op1);
9076 /* Expand builtins that take two long operands and return void. */
9079 frv_expand_int_void2arg (enum insn_code icode, tree call)
9082 rtx op0 = frv_read_argument (call, 0);
9083 rtx op1 = frv_read_argument (call, 1);
9085 op0 = frv_legitimize_argument (icode, 1, op0);
9086 op1 = frv_legitimize_argument (icode, 1, op1);
9087 pat = GEN_FCN (icode) (op0, op1);
9095 /* Expand prefetch builtins. These take a single address as argument. */
9098 frv_expand_prefetches (enum insn_code icode, tree call)
9101 rtx op0 = frv_read_argument (call, 0);
9103 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9111 /* Expand builtins that take three operands and return void. The first
9112 argument must be a constant that describes a pair or quad accumulators. A
9113 fourth argument is created that is the accumulator guard register that
9114 corresponds to the accumulator. */
9117 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9120 rtx op0 = frv_read_argument (call, 0);
9121 rtx op1 = frv_read_argument (call, 1);
9122 rtx op2 = frv_read_argument (call, 2);
9125 op0 = frv_int_to_acc (icode, 0, op0);
9129 op1 = frv_legitimize_argument (icode, 1, op1);
9130 op2 = frv_legitimize_argument (icode, 2, op2);
9131 op3 = frv_matching_accg_for_acc (op0);
9132 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9140 /* Expand builtins that perform accumulator-to-accumulator operations.
9141 These builtins take two accumulator numbers as argument and return
9145 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9148 rtx op0 = frv_read_argument (call, 0);
9149 rtx op1 = frv_read_argument (call, 1);
9153 op0 = frv_int_to_acc (icode, 0, op0);
9157 op1 = frv_int_to_acc (icode, 1, op1);
9161 op2 = frv_matching_accg_for_acc (op0);
9162 op3 = frv_matching_accg_for_acc (op1);
9163 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9171 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9172 membar and TARGET_MODE is the mode that the loaded value should have. */
9175 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9176 tree call, rtx target)
9178 rtx op0 = frv_read_argument (call, 0);
9179 rtx cookie = frv_io_address_cookie (op0);
9181 if (target == 0 || !REG_P (target))
9182 target = gen_reg_rtx (target_mode);
9183 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9184 convert_move (target, op0, 1);
9185 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9186 cfun->machine->has_membar_p = 1;
9190 /* Likewise __builtin_write* functions. */
9193 frv_expand_store_builtin (enum insn_code icode, tree call)
9195 rtx op0 = frv_read_argument (call, 0);
9196 rtx op1 = frv_read_argument (call, 1);
9197 rtx cookie = frv_io_address_cookie (op0);
9199 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9200 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9201 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9202 cfun->machine->has_membar_p = 1;
9206 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9207 each argument forms one word of the two double-word input registers.
9208 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9209 to put the return value. */
9212 frv_expand_mdpackh_builtin (tree call, rtx target)
9214 enum insn_code icode = CODE_FOR_mdpackh;
9216 rtx arg1 = frv_read_argument (call, 0);
9217 rtx arg2 = frv_read_argument (call, 1);
9218 rtx arg3 = frv_read_argument (call, 2);
9219 rtx arg4 = frv_read_argument (call, 3);
9221 target = frv_legitimize_target (icode, target);
9222 op0 = gen_reg_rtx (DImode);
9223 op1 = gen_reg_rtx (DImode);
9225 /* The high half of each word is not explicitly initialized, so indicate
9226 that the input operands are not live before this point. */
9230 /* Move each argument into the low half of its associated input word. */
9231 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9232 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9233 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9234 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9236 pat = GEN_FCN (icode) (target, op0, op1);
9244 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9245 number as argument. */
9248 frv_expand_mclracc_builtin (tree call)
9250 enum insn_code icode = CODE_FOR_mclracc;
9252 rtx op0 = frv_read_argument (call, 0);
9254 op0 = frv_int_to_acc (icode, 0, op0);
9258 pat = GEN_FCN (icode) (op0);
9265 /* Expand builtins that take no arguments. */
9268 frv_expand_noargs_builtin (enum insn_code icode)
9270 rtx pat = GEN_FCN (icode) (const0_rtx);
9277 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9278 number or accumulator guard number as argument and return an SI integer. */
9281 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9284 rtx target = gen_reg_rtx (SImode);
9285 rtx op0 = frv_read_argument (call, 0);
9287 op0 = frv_int_to_acc (icode, 1, op0);
9291 pat = GEN_FCN (icode) (target, op0);
9299 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9300 accumulator guard as their first argument and an SImode value as their
9304 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9307 rtx op0 = frv_read_argument (call, 0);
9308 rtx op1 = frv_read_argument (call, 1);
9310 op0 = frv_int_to_acc (icode, 0, op0);
9314 op1 = frv_legitimize_argument (icode, 1, op1);
9315 pat = GEN_FCN (icode) (op0, op1);
9322 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9323 to move DImode values into and out of IACC0. */
9326 frv_split_iacc_move (rtx dest, rtx src)
9328 enum machine_mode inner;
9331 inner = GET_MODE (dest);
9332 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9333 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9334 simplify_gen_subreg (SImode, src, inner, i));
9337 /* Expand builtins. */
9340 frv_expand_builtin (tree exp,
9342 rtx subtarget ATTRIBUTE_UNUSED,
9343 enum machine_mode mode ATTRIBUTE_UNUSED,
9344 int ignore ATTRIBUTE_UNUSED)
9346 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9347 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9349 struct builtin_description *d;
9351 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9353 error ("media functions are not available unless -mmedia is used");
9359 case FRV_BUILTIN_MCOP1:
9360 case FRV_BUILTIN_MCOP2:
9361 case FRV_BUILTIN_MDUNPACKH:
9362 case FRV_BUILTIN_MBTOHE:
9363 if (! TARGET_MEDIA_REV1)
9365 error ("this media function is only available on the fr500");
9370 case FRV_BUILTIN_MQXMACHS:
9371 case FRV_BUILTIN_MQXMACXHS:
9372 case FRV_BUILTIN_MQMACXHS:
9373 case FRV_BUILTIN_MADDACCS:
9374 case FRV_BUILTIN_MSUBACCS:
9375 case FRV_BUILTIN_MASACCS:
9376 case FRV_BUILTIN_MDADDACCS:
9377 case FRV_BUILTIN_MDSUBACCS:
9378 case FRV_BUILTIN_MDASACCS:
9379 case FRV_BUILTIN_MABSHS:
9380 case FRV_BUILTIN_MDROTLI:
9381 case FRV_BUILTIN_MCPLHI:
9382 case FRV_BUILTIN_MCPLI:
9383 case FRV_BUILTIN_MDCUTSSI:
9384 case FRV_BUILTIN_MQSATHS:
9385 case FRV_BUILTIN_MHSETLOS:
9386 case FRV_BUILTIN_MHSETLOH:
9387 case FRV_BUILTIN_MHSETHIS:
9388 case FRV_BUILTIN_MHSETHIH:
9389 case FRV_BUILTIN_MHDSETS:
9390 case FRV_BUILTIN_MHDSETH:
9391 if (! TARGET_MEDIA_REV2)
9393 error ("this media function is only available on the fr400"
9399 case FRV_BUILTIN_SMASS:
9400 case FRV_BUILTIN_SMSSS:
9401 case FRV_BUILTIN_SMU:
9402 case FRV_BUILTIN_ADDSS:
9403 case FRV_BUILTIN_SUBSS:
9404 case FRV_BUILTIN_SLASS:
9405 case FRV_BUILTIN_SCUTSS:
9406 case FRV_BUILTIN_IACCreadll:
9407 case FRV_BUILTIN_IACCreadl:
9408 case FRV_BUILTIN_IACCsetll:
9409 case FRV_BUILTIN_IACCsetl:
9410 if (!TARGET_FR405_BUILTINS)
9412 error ("this builtin function is only available"
9413 " on the fr405 and fr450");
9418 case FRV_BUILTIN_PREFETCH:
9419 if (!TARGET_FR500_FR550_BUILTINS)
9421 error ("this builtin function is only available on the fr500"
9427 case FRV_BUILTIN_MQLCLRHS:
9428 case FRV_BUILTIN_MQLMTHS:
9429 case FRV_BUILTIN_MQSLLHI:
9430 case FRV_BUILTIN_MQSRAHI:
9431 if (!TARGET_MEDIA_FR450)
9433 error ("this builtin function is only available on the fr450");
9442 /* Expand unique builtins. */
9446 case FRV_BUILTIN_MTRAP:
9447 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9449 case FRV_BUILTIN_MCLRACC:
9450 return frv_expand_mclracc_builtin (exp);
9452 case FRV_BUILTIN_MCLRACCA:
9454 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9456 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9458 case FRV_BUILTIN_MRDACC:
9459 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9461 case FRV_BUILTIN_MRDACCG:
9462 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9464 case FRV_BUILTIN_MWTACC:
9465 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9467 case FRV_BUILTIN_MWTACCG:
9468 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9470 case FRV_BUILTIN_MDPACKH:
9471 return frv_expand_mdpackh_builtin (exp, target);
9473 case FRV_BUILTIN_IACCreadll:
9475 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9476 if (target == 0 || !REG_P (target))
9477 target = gen_reg_rtx (DImode);
9478 frv_split_iacc_move (target, src);
9482 case FRV_BUILTIN_IACCreadl:
9483 return frv_read_iacc_argument (SImode, exp, 0);
9485 case FRV_BUILTIN_IACCsetll:
9487 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9488 rtx src = frv_read_argument (exp, 1);
9489 frv_split_iacc_move (dest, force_reg (DImode, src));
9493 case FRV_BUILTIN_IACCsetl:
9495 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9496 rtx src = frv_read_argument (exp, 1);
9497 emit_move_insn (dest, force_reg (SImode, src));
9505 /* Expand groups of builtins. */
9507 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9508 if (d->code == fcode)
9509 return frv_expand_set_builtin (d->icode, exp, target);
9511 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9512 if (d->code == fcode)
9513 return frv_expand_unop_builtin (d->icode, exp, target);
9515 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9516 if (d->code == fcode)
9517 return frv_expand_binop_builtin (d->icode, exp, target);
9519 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9520 if (d->code == fcode)
9521 return frv_expand_cut_builtin (d->icode, exp, target);
9523 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9524 if (d->code == fcode)
9525 return frv_expand_binopimm_builtin (d->icode, exp, target);
9527 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9528 if (d->code == fcode)
9529 return frv_expand_voidbinop_builtin (d->icode, exp);
9531 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9532 if (d->code == fcode)
9533 return frv_expand_voidtriop_builtin (d->icode, exp);
9535 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9536 if (d->code == fcode)
9537 return frv_expand_voidaccop_builtin (d->icode, exp);
9539 for (i = 0, d = bdesc_int_void2arg;
9540 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9541 if (d->code == fcode)
9542 return frv_expand_int_void2arg (d->icode, exp);
9544 for (i = 0, d = bdesc_prefetches;
9545 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9546 if (d->code == fcode)
9547 return frv_expand_prefetches (d->icode, exp);
9549 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9550 if (d->code == fcode)
9551 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9554 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9555 if (d->code == fcode)
9556 return frv_expand_store_builtin (d->icode, exp);
9562 frv_in_small_data_p (const_tree decl)
9565 const_tree section_name;
9567 /* Don't apply the -G flag to internal compiler structures. We
9568 should leave such structures in the main data section, partly
9569 for efficiency and partly because the size of some of them
9570 (such as C++ typeinfos) is not known until later. */
9571 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9574 /* If we already know which section the decl should be in, see if
9575 it's a small data section. */
9576 section_name = DECL_SECTION_NAME (decl);
9579 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9580 if (frv_string_begins_with (section_name, ".sdata"))
9582 if (frv_string_begins_with (section_name, ".sbss"))
9587 size = int_size_in_bytes (TREE_TYPE (decl));
9588 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9595 frv_rtx_costs (rtx x,
9596 int code ATTRIBUTE_UNUSED,
9597 int outer_code ATTRIBUTE_UNUSED,
9599 bool speed ATTRIBUTE_UNUSED)
9601 if (outer_code == MEM)
9603 /* Don't differentiate between memory addresses. All the ones
9604 we accept have equal cost. */
9605 *total = COSTS_N_INSNS (0);
9612 /* Make 12-bit integers really cheap. */
9613 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9624 *total = COSTS_N_INSNS (2);
9638 if (GET_MODE (x) == SImode)
9639 *total = COSTS_N_INSNS (1);
9640 else if (GET_MODE (x) == DImode)
9641 *total = COSTS_N_INSNS (2);
9643 *total = COSTS_N_INSNS (3);
9647 if (GET_MODE (x) == SImode)
9648 *total = COSTS_N_INSNS (2);
9650 *total = COSTS_N_INSNS (6); /* guess */
9657 *total = COSTS_N_INSNS (18);
9661 *total = COSTS_N_INSNS (3);
9670 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9672 switch_to_section (ctors_section);
9673 assemble_align (POINTER_SIZE);
9676 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9681 assemble_integer_with_op ("\t.picptr\t", symbol);
9685 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9687 switch_to_section (dtors_section);
9688 assemble_align (POINTER_SIZE);
9691 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9696 assemble_integer_with_op ("\t.picptr\t", symbol);
9699 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9702 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9703 int incoming ATTRIBUTE_UNUSED)
9705 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9708 #define TLS_BIAS (2048 - 16)
9710 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9711 We need to emit DTP-relative relocations. */
9714 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9716 gcc_assert (size == 4);
9717 fputs ("\t.picptr\ttlsmoff(", file);
9718 /* We want the unbiased TLS offset, so add the bias to the
9719 expression, such that the implicit biasing cancels out. */
9720 output_addr_const (file, plus_constant (x, TLS_BIAS));