1 /* Definitions of target machine for Mitsubishi D30V.
2 Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
41 #include "integrate.h"
44 #include "target-def.h"
45 #include "langhooks.h"
47 static void d30v_print_operand_memory_reference PARAMS ((FILE *, rtx));
48 static void d30v_build_long_insn PARAMS ((HOST_WIDE_INT, HOST_WIDE_INT,
50 static void d30v_add_gc_roots PARAMS ((void));
51 static void d30v_init_machine_status PARAMS ((struct function *));
52 static void d30v_mark_machine_status PARAMS ((struct function *));
53 static void d30v_free_machine_status PARAMS ((struct function *));
54 static void d30v_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
55 static void d30v_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
56 static int d30v_adjust_cost PARAMS ((rtx, rtx, rtx, int));
57 static int d30v_issue_rate PARAMS ((void));
59 /* Define the information needed to generate branch and scc insns. This is
60 stored from the compare operation. */
62 struct rtx_def *d30v_compare_op0;
63 struct rtx_def *d30v_compare_op1;
65 /* Cached value of d30v_stack_info */
66 static d30v_stack_t *d30v_stack_cache = (d30v_stack_t *)0;
68 /* Values of the -mbranch-cost=n string. */
69 int d30v_branch_cost = D30V_DEFAULT_BRANCH_COST;
70 const char *d30v_branch_cost_string = (const char *)0;
72 /* Values of the -mcond-exec=n string. */
73 int d30v_cond_exec = D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE;
74 const char *d30v_cond_exec_string = (const char *)0;
76 /* Whether or not a hard register can accept a register */
77 unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER];
79 /* Whether to try and avoid moves between two different modes */
80 unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ];
82 /* Map register number to smallest register class. */
83 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
85 /* Map class letter into register class */
86 enum reg_class reg_class_from_letter[256];
88 /* Initialize the GCC target structure. */
89 #undef TARGET_ASM_ALIGNED_HI_OP
90 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
91 #undef TARGET_ASM_ALIGNED_SI_OP
92 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
94 #undef TARGET_ASM_FUNCTION_PROLOGUE
95 #define TARGET_ASM_FUNCTION_PROLOGUE d30v_output_function_prologue
96 #undef TARGET_ASM_FUNCTION_EPILOGUE
97 #define TARGET_ASM_FUNCTION_EPILOGUE d30v_output_function_epilogue
98 #undef TARGET_SCHED_ADJUST_COST
99 #define TARGET_SCHED_ADJUST_COST d30v_adjust_cost
100 #undef TARGET_SCHED_ISSUE_RATE
101 #define TARGET_SCHED_ISSUE_RATE d30v_issue_rate
103 struct gcc_target targetm = TARGET_INITIALIZER;
105 /* Sometimes certain combinations of command options do not make
106 sense on a particular target machine. You can define a macro
107 `OVERRIDE_OPTIONS' to take account of this. This macro, if
108 defined, is executed once just after all the command options have
111 Don't use this macro to turn on various extra optimizations for
112 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
118 enum machine_mode mode1, mode2;
120 /* Set up the branch cost information */
121 if (d30v_branch_cost_string)
122 d30v_branch_cost = atoi (d30v_branch_cost_string);
124 /* Set up max # instructions to use with conditional execution */
125 if (d30v_cond_exec_string)
126 d30v_cond_exec = atoi (d30v_cond_exec_string);
128 /* Setup hard_regno_mode_ok/modes_tieable_p */
129 for (mode1 = VOIDmode;
130 (int)mode1 < NUM_MACHINE_MODES;
131 mode1 = (enum machine_mode)((int)mode1 + 1))
133 int size = GET_MODE_SIZE (mode1);
134 int large_p = size > UNITS_PER_WORD;
135 int int_p = GET_MODE_CLASS (mode1) == MODE_INT;
137 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
139 if (mode1 == VOIDmode)
142 else if (GPR_P (regno))
147 ok_p = (((regno - GPR_FIRST) & 1) == 0);
150 else if (FLAG_P (regno))
151 ok_p = (mode1 == CCmode);
153 else if (CR_P (regno))
154 ok_p = int_p && !large_p;
156 else if (ACCUM_P (regno))
157 ok_p = (mode1 == DImode);
159 else if (SPECIAL_REG_P (regno))
160 ok_p = (mode1 == SImode);
165 hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p;
168 /* A C expression that is nonzero if it is desirable to choose
169 register allocation so as to avoid move instructions between a
170 value of mode MODE1 and a value of mode MODE2.
172 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
173 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
174 MODE2)' must be zero. */
175 for (mode2 = VOIDmode;
176 (int)mode2 <= NUM_MACHINE_MODES;
177 mode2 = (enum machine_mode)((int)mode2 + 1))
183 else if (GET_MODE_CLASS (mode1) == MODE_INT
184 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
185 && GET_MODE_CLASS (mode2) == MODE_INT
186 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
193 modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p;
198 for (mode1 = VOIDmode;
199 (int)mode1 < NUM_MACHINE_MODES;
200 mode1 = (enum machine_mode)((int)mode1 + 1))
202 for (mode2 = VOIDmode;
203 (int)mode2 <= NUM_MACHINE_MODES;
204 mode2 = (enum machine_mode)((int)mode2 + 1))
206 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
208 && (hard_regno_mode_ok[(int)mode1][regno]
209 != hard_regno_mode_ok[(int)mode2][regno]))
210 error ("bad modes_tieable_p for register %s, mode1 %s, mode2 %s",
211 reg_names[regno], GET_MODE_NAME (mode1),
212 GET_MODE_NAME (mode2));
217 /* A C expression whose value is a register class containing hard
218 register REGNO. In general there is more than one such class;
219 choose a class which is "minimal", meaning that no smaller class
220 also contains the register. */
221 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
223 enum reg_class class;
226 class = (IN_RANGE_P (regno, GPR_FIRST+2, GPR_FIRST+62)
227 && ((regno - GPR_FIRST) & 1) == 0) ? EVEN_REGS : GPR_REGS;
229 else if (regno == FLAG_F0)
232 else if (regno == FLAG_F1)
235 else if (FLAG_P (regno))
236 class = OTHER_FLAG_REGS;
238 else if (ACCUM_P (regno))
241 else if (regno == CR_RPT_C)
244 else if (CR_P (regno))
247 else if (SPECIAL_REG_P (regno))
253 regno_reg_class[regno] = class;
257 static const char *const names[] = REG_CLASS_NAMES;
258 fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]);
259 for (mode1 = VOIDmode;
260 (int)mode1 < NUM_MACHINE_MODES;
261 mode1 = (enum machine_mode)((int)mode1 + 1))
263 if (hard_regno_mode_ok[ (int)mode1 ][ regno ])
264 fprintf (stderr, " %s", GET_MODE_NAME (mode1));
266 fprintf (stderr, "\n");
271 /* A C expression which defines the machine-dependent operand
272 constraint letters for register classes. If CHAR is such a
273 letter, the value should be the register class corresponding to
274 it. Otherwise, the value should be `NO_REGS'. The register
275 letter `r', corresponding to class `GENERAL_REGS', will not be
276 passed to this macro; you do not need to handle it.
278 The following letters are unavailable, due to being used as
283 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
284 'Q', 'R', 'S', 'T', 'U'
286 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
288 for (i = 0; i < 256; i++)
289 reg_class_from_letter[i] = NO_REGS;
291 reg_class_from_letter['a'] = ACCUM_REGS;
292 reg_class_from_letter['b'] = BR_FLAG_REGS;
293 reg_class_from_letter['c'] = CR_REGS;
294 reg_class_from_letter['d'] = GPR_REGS;
295 reg_class_from_letter['e'] = EVEN_REGS;
296 reg_class_from_letter['f'] = FLAG_REGS;
297 reg_class_from_letter['l'] = REPEAT_REGS;
298 reg_class_from_letter['x'] = F0_REGS;
299 reg_class_from_letter['y'] = F1_REGS;
300 reg_class_from_letter['z'] = OTHER_FLAG_REGS;
302 d30v_add_gc_roots ();
306 /* Return true if a memory operand is a short memory operand. */
309 short_memory_operand (op, mode)
311 enum machine_mode mode;
313 if (GET_CODE (op) != MEM)
316 if (GET_MODE (op) != mode && mode != VOIDmode)
319 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
323 /* Return true if a memory operand is a long operand. */
326 long_memory_operand (op, mode)
328 enum machine_mode mode;
330 if (GET_CODE (op) != MEM)
333 if (GET_MODE (op) != mode && mode != VOIDmode)
336 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
340 /* Return true if a memory operand is valid for the D30V. */
343 d30v_memory_operand (op, mode)
345 enum machine_mode mode;
347 if (GET_CODE (op) != MEM)
350 if (GET_MODE (op) != mode && mode != VOIDmode)
353 return (d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed)
357 /* Return true if a memory operand uses a single register for the
361 single_reg_memory_operand (op, mode)
363 enum machine_mode mode;
367 if (GET_CODE (op) != MEM)
370 if (GET_MODE (op) != mode && mode != VOIDmode)
374 if (! d30v_legitimate_address_p (mode, addr, reload_completed))
377 if (GET_CODE (addr) == SUBREG)
378 addr = SUBREG_REG (addr);
380 return (GET_CODE (addr) == REG);
383 /* Return true if a memory operand uses a constant address. */
386 const_addr_memory_operand (op, mode)
388 enum machine_mode mode;
390 if (GET_CODE (op) != MEM)
393 if (GET_MODE (op) != mode && mode != VOIDmode)
396 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
399 switch (GET_CODE (XEXP (op, 0)))
414 /* Return true if operand is a memory reference suitable for a call. */
417 call_operand (op, mode)
419 enum machine_mode mode;
421 if (GET_CODE (op) != MEM)
424 if (GET_MODE (op) != mode && mode != VOIDmode)
427 if (! d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed))
430 switch (GET_CODE (XEXP (op, 0)))
436 op = SUBREG_REG (op);
437 if (GET_CODE (op) != REG)
443 return (GPR_OR_PSEUDO_P (REGNO (XEXP (op, 0))));
455 /* Return true if operand is a GPR register. */
458 gpr_operand (op, mode)
460 enum machine_mode mode;
462 if (GET_MODE (op) != mode && mode != VOIDmode)
465 if (GET_CODE (op) == SUBREG)
467 if (GET_CODE (SUBREG_REG (op)) != REG)
468 return register_operand (op, mode);
470 op = SUBREG_REG (op);
473 if (GET_CODE (op) != REG)
476 return GPR_OR_PSEUDO_P (REGNO (op));
479 /* Return true if operand is an accumulator register. */
482 accum_operand (op, mode)
484 enum machine_mode mode;
486 if (GET_MODE (op) != mode && mode != VOIDmode)
489 if (GET_CODE (op) == SUBREG)
491 if (GET_CODE (SUBREG_REG (op)) != REG)
492 return register_operand (op, mode);
494 op = SUBREG_REG (op);
497 if (GET_CODE (op) != REG)
500 return ACCUM_OR_PSEUDO_P (REGNO (op));
503 /* Return true if operand is a GPR or an accumulator register. */
506 gpr_or_accum_operand (op, mode)
508 enum machine_mode mode;
510 if (GET_MODE (op) != mode && mode != VOIDmode)
513 if (GET_CODE (op) == SUBREG)
515 if (GET_CODE (SUBREG_REG (op)) != REG)
516 return register_operand (op, mode);
518 op = SUBREG_REG (op);
521 if (GET_CODE (op) != REG)
524 if (ACCUM_P (REGNO (op)))
527 return GPR_OR_PSEUDO_P (REGNO (op));
530 /* Return true if operand is a CR register. */
533 cr_operand (op, mode)
535 enum machine_mode mode;
537 if (GET_MODE (op) != mode && mode != VOIDmode)
540 if (GET_CODE (op) == SUBREG)
542 if (GET_CODE (SUBREG_REG (op)) != REG)
543 return register_operand (op, mode);
545 op = SUBREG_REG (op);
548 if (GET_CODE (op) != REG)
551 return CR_OR_PSEUDO_P (REGNO (op));
554 /* Return true if operand is the repeat count register. */
557 repeat_operand (op, mode)
559 enum machine_mode mode;
561 if (GET_MODE (op) != mode && mode != VOIDmode)
564 if (GET_CODE (op) == SUBREG)
566 if (GET_CODE (SUBREG_REG (op)) != REG)
567 return register_operand (op, mode);
569 op = SUBREG_REG (op);
572 if (GET_CODE (op) != REG)
575 return (REGNO (op) == CR_RPT_C || REGNO (op) >= FIRST_PSEUDO_REGISTER);
578 /* Return true if operand is a FLAG register. */
581 flag_operand (op, mode)
583 enum machine_mode mode;
585 if (GET_MODE (op) != mode && mode != VOIDmode)
588 if (GET_CODE (op) == SUBREG)
590 if (GET_CODE (SUBREG_REG (op)) != REG)
591 return register_operand (op, mode);
593 op = SUBREG_REG (op);
596 if (GET_CODE (op) != REG)
599 return FLAG_OR_PSEUDO_P (REGNO (op));
602 /* Return true if operand is either F0 or F1. */
605 br_flag_operand (op, mode)
607 enum machine_mode mode;
609 if (GET_MODE (op) != mode && mode != VOIDmode)
612 if (GET_CODE (op) == SUBREG)
614 if (GET_CODE (SUBREG_REG (op)) != REG)
615 return register_operand (op, mode);
617 op = SUBREG_REG (op);
620 if (GET_CODE (op) != REG)
623 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
626 /* Return true if operand is either F0/F1 or the constants 0/1. */
629 br_flag_or_constant_operand (op, mode)
631 enum machine_mode mode;
633 if (GET_MODE (op) != mode && mode != VOIDmode)
636 if (GET_CODE (op) == SUBREG)
638 if (GET_CODE (SUBREG_REG (op)) != REG)
639 return register_operand (op, mode);
641 op = SUBREG_REG (op);
644 if (GET_CODE (op) == CONST_INT)
645 return (INTVAL (op) == 0 || INTVAL (op) == 1);
647 if (GET_CODE (op) != REG)
650 return BR_FLAG_OR_PSEUDO_P (REGNO (op));
653 /* Return true if operand is either F0 or F1, or a GPR register. */
656 gpr_or_br_flag_operand (op, mode)
658 enum machine_mode mode;
660 if (GET_MODE (op) != mode && mode != VOIDmode)
663 if (GET_CODE (op) == SUBREG)
665 if (GET_CODE (SUBREG_REG (op)) != REG)
666 return register_operand (op, mode);
668 op = SUBREG_REG (op);
671 if (GET_CODE (op) != REG)
674 return GPR_OR_PSEUDO_P (REGNO (op)) || BR_FLAG_P (REGNO (op));
677 /* Return true if operand is the F0 register. */
680 f0_operand (op, mode)
682 enum machine_mode mode;
684 if (GET_MODE (op) != mode && mode != VOIDmode)
687 if (GET_CODE (op) == SUBREG)
689 if (GET_CODE (SUBREG_REG (op)) != REG)
690 return register_operand (op, mode);
692 op = SUBREG_REG (op);
695 if (GET_CODE (op) != REG)
698 return (REGNO (op) == FLAG_F0 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
701 /* Return true if operand is the F1 register. */
704 f1_operand (op, mode)
706 enum machine_mode mode;
708 if (GET_MODE (op) != mode && mode != VOIDmode)
711 if (GET_CODE (op) == SUBREG)
713 if (GET_CODE (SUBREG_REG (op)) != REG)
714 return register_operand (op, mode);
716 op = SUBREG_REG (op);
719 if (GET_CODE (op) != REG)
722 return (REGNO (op) == FLAG_F1 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
725 /* Return true if operand is the F1 register. */
728 carry_operand (op, mode)
730 enum machine_mode mode;
732 if (GET_MODE (op) != mode && mode != VOIDmode)
735 if (GET_CODE (op) == SUBREG)
737 if (GET_CODE (SUBREG_REG (op)) != REG)
738 return register_operand (op, mode);
740 op = SUBREG_REG (op);
743 if (GET_CODE (op) != REG)
746 return (REGNO (op) == FLAG_CARRY || REGNO (op) >= FIRST_PSEUDO_REGISTER);
749 /* Return true if operand is a register of any flavor or a 0 of the
753 reg_or_0_operand (op, mode)
755 enum machine_mode mode;
757 switch (GET_CODE (op))
764 if (GET_MODE (op) != mode && mode != VOIDmode)
767 return register_operand (op, mode);
770 return INTVAL (op) == 0;
773 return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0;
779 /* Return true if operand is a GPR register or a signed 6 bit immediate. */
782 gpr_or_signed6_operand (op, mode)
784 enum machine_mode mode;
786 if (GET_CODE (op) == SUBREG)
788 if (GET_CODE (SUBREG_REG (op)) != REG)
789 return register_operand (op, mode);
791 op = SUBREG_REG (op);
794 if (GET_CODE (op) == CONST_INT)
795 return IN_RANGE_P (INTVAL (op), -32, 31);
797 if (GET_CODE (op) != REG)
800 if (GET_MODE (op) != mode && mode != VOIDmode)
803 return GPR_OR_PSEUDO_P (REGNO (op));
806 /* Return true if operand is a GPR register or an unsigned 5 bit immediate. */
809 gpr_or_unsigned5_operand (op, mode)
811 enum machine_mode mode;
813 if (GET_CODE (op) == SUBREG)
815 if (GET_CODE (SUBREG_REG (op)) != REG)
816 return register_operand (op, mode);
818 op = SUBREG_REG (op);
821 if (GET_CODE (op) == CONST_INT)
822 return IN_RANGE_P (INTVAL (op), 0, 31);
824 if (GET_CODE (op) != REG)
827 if (GET_MODE (op) != mode && mode != VOIDmode)
830 return GPR_OR_PSEUDO_P (REGNO (op));
833 /* Return true if operand is a GPR register or an unsigned 6 bit immediate. */
836 gpr_or_unsigned6_operand (op, mode)
838 enum machine_mode mode;
840 if (GET_CODE (op) == SUBREG)
842 if (GET_CODE (SUBREG_REG (op)) != REG)
843 return register_operand (op, mode);
845 op = SUBREG_REG (op);
848 if (GET_CODE (op) == CONST_INT)
849 return IN_RANGE_P (INTVAL (op), 0, 63);
851 if (GET_CODE (op) != REG)
854 if (GET_MODE (op) != mode && mode != VOIDmode)
857 return GPR_OR_PSEUDO_P (REGNO (op));
860 /* Return true if operand is a GPR register or a constant of some form. */
863 gpr_or_constant_operand (op, mode)
865 enum machine_mode mode;
867 switch (GET_CODE (op))
879 if (GET_CODE (SUBREG_REG (op)) != REG)
880 return register_operand (op, mode);
882 op = SUBREG_REG (op);
886 if (GET_MODE (op) != mode && mode != VOIDmode)
889 return GPR_OR_PSEUDO_P (REGNO (op));
895 /* Return true if operand is a GPR register or a constant of some form,
896 including a CONST_DOUBLE, which gpr_or_constant_operand doesn't recognize. */
899 gpr_or_dbl_const_operand (op, mode)
901 enum machine_mode mode;
903 switch (GET_CODE (op))
916 if (GET_CODE (SUBREG_REG (op)) != REG)
917 return register_operand (op, mode);
919 op = SUBREG_REG (op);
923 if (GET_MODE (op) != mode && mode != VOIDmode)
926 return GPR_OR_PSEUDO_P (REGNO (op));
932 /* Return true if operand is a gpr register or a valid memory operation. */
935 gpr_or_memory_operand (op, mode)
937 enum machine_mode mode;
939 switch (GET_CODE (op))
945 if (GET_CODE (SUBREG_REG (op)) != REG)
946 return register_operand (op, mode);
948 op = SUBREG_REG (op);
952 if (GET_MODE (op) != mode && mode != VOIDmode)
955 return GPR_OR_PSEUDO_P (REGNO (op));
958 return d30v_legitimate_address_p (mode, XEXP (op, 0), reload_completed);
964 /* Return true if operand is something that can be an input for a move
968 move_input_operand (op, mode)
970 enum machine_mode mode;
975 switch (GET_CODE (op))
988 if (GET_MODE (op) != mode && mode != VOIDmode)
991 subreg = SUBREG_REG (op);
992 code = GET_CODE (subreg);
994 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
997 return (code == REG);
1000 if (GET_MODE (op) != mode && mode != VOIDmode)
1006 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1008 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1015 /* Return true if operand is something that can be an output for a move
1019 move_output_operand (op, mode)
1021 enum machine_mode mode;
1026 switch (GET_CODE (op))
1032 if (GET_MODE (op) != mode && mode != VOIDmode)
1035 subreg = SUBREG_REG (op);
1036 code = GET_CODE (subreg);
1038 return d30v_legitimate_address_p ((int)mode, XEXP (subreg, 0),
1041 return (code == REG);
1044 if (GET_MODE (op) != mode && mode != VOIDmode)
1050 if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1052 return d30v_legitimate_address_p (mode, XEXP (op, 0),
1059 /* Return true if operand is a signed 6 bit immediate. */
1062 signed6_operand (op, mode)
1064 enum machine_mode mode ATTRIBUTE_UNUSED;
1066 if (GET_CODE (op) == CONST_INT)
1067 return IN_RANGE_P (INTVAL (op), -32, 31);
1072 /* Return true if operand is an unsigned 5 bit immediate. */
1075 unsigned5_operand (op, mode)
1077 enum machine_mode mode ATTRIBUTE_UNUSED;
1079 if (GET_CODE (op) == CONST_INT)
1080 return IN_RANGE_P (INTVAL (op), 0, 31);
1085 /* Return true if operand is an unsigned 6 bit immediate. */
1088 unsigned6_operand (op, mode)
1090 enum machine_mode mode ATTRIBUTE_UNUSED;
1092 if (GET_CODE (op) == CONST_INT)
1093 return IN_RANGE_P (INTVAL (op), 0, 63);
1098 /* Return true if operand is a constant with a single bit set. */
1101 bitset_operand (op, mode)
1103 enum machine_mode mode ATTRIBUTE_UNUSED;
1105 if (GET_CODE (op) == CONST_INT)
1106 return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31);
1111 /* Return true if the operator is a ==/!= test against f0 or f1 that can be
1112 used in conditional execution. */
1115 condexec_test_operator (op, mode)
1117 enum machine_mode mode;
1121 if (GET_MODE (op) != mode && mode != VOIDmode)
1124 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1128 if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0)))
1132 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1138 /* Return true if the operator is a ==/!= test against f0, f1, or a general
1139 register that can be used in a branch instruction. */
1142 condexec_branch_operator (op, mode)
1144 enum machine_mode mode;
1148 if (GET_MODE (op) != mode && mode != VOIDmode)
1151 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1155 if (GET_CODE (x0) == REG)
1157 int regno = REGNO (x0);
1158 if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno))
1161 /* Allow the optimizer to generate things like:
1162 (if_then_else (ne (const_int 1) (const_int 0))) */
1163 else if (GET_CODE (x0) != CONST_INT)
1167 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1173 /* Return true if the unary operator can be executed with conditional
1177 condexec_unary_operator (op, mode)
1179 enum machine_mode mode ATTRIBUTE_UNUSED;
1183 /* Only do this after register allocation, so that we can look at the register # */
1184 if (!reload_completed)
1187 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1191 if (GET_CODE (op0) == SUBREG)
1192 op0 = SUBREG_REG (op0);
1194 switch (GET_CODE (op))
1201 if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
1210 /* Return true if the add or subtraction can be executed with conditional
1214 condexec_addsub_operator (op, mode)
1216 enum machine_mode mode ATTRIBUTE_UNUSED;
1220 /* Only do this after register allocation, so that we can look at the register # */
1221 if (!reload_completed)
1224 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1230 if (GET_CODE (op0) == SUBREG)
1231 op0 = SUBREG_REG (op0);
1233 if (GET_CODE (op1) == SUBREG)
1234 op1 = SUBREG_REG (op1);
1236 if (GET_CODE (op0) != REG)
1239 switch (GET_CODE (op))
1246 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1247 && gpr_or_constant_operand (op1, SImode));
1253 /* Return true if the binary operator can be executed with conditional
1254 execution. We don't include add/sub here, since they have extra
1255 clobbers for the flags registers. */
1258 condexec_binary_operator (op, mode)
1260 enum machine_mode mode ATTRIBUTE_UNUSED;
1264 /* Only do this after register allocation, so that we can look at the register # */
1265 if (!reload_completed)
1268 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1274 if (GET_CODE (op0) == SUBREG)
1275 op0 = SUBREG_REG (op0);
1277 if (GET_CODE (op1) == SUBREG)
1278 op1 = SUBREG_REG (op1);
1280 if (GET_CODE (op0) != REG)
1283 /* MULT is not included here, because it is an IU only instruction. */
1284 switch (GET_CODE (op))
1295 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1296 && gpr_or_constant_operand (op1, SImode));
1300 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1301 && GET_CODE (op1) == CONST_INT);
1307 /* Return true if the shift/rotate left operator can be executed with
1308 conditional execution. */
1311 condexec_shiftl_operator (op, mode)
1313 enum machine_mode mode ATTRIBUTE_UNUSED;
1317 /* Only do this after register allocation, so that we can look at the register # */
1318 if (!reload_completed)
1321 if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
1327 if (GET_CODE (op0) == SUBREG)
1328 op0 = SUBREG_REG (op0);
1330 if (GET_CODE (op1) == SUBREG)
1331 op1 = SUBREG_REG (op1);
1333 if (GET_CODE (op0) != REG)
1336 switch (GET_CODE (op))
1343 return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
1344 && GET_CODE (op1) == NEG
1345 && GET_CODE (XEXP (op1, 0)) == REG
1346 && GPR_P (REGNO (XEXP (op1, 0))));
1352 /* Return true if the {sign,zero} extend operator from memory can be
1353 conditionally executed. */
1356 condexec_extend_operator (op, mode)
1358 enum machine_mode mode ATTRIBUTE_UNUSED;
1360 /* Only do this after register allocation, so that we can look at the register # */
1361 if (!reload_completed)
1364 if (GET_RTX_CLASS (GET_CODE (op)) != '1')
1367 switch (GET_CODE (op))
1374 if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode)
1375 || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode)
1376 || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode))
1385 /* Return true for comparisons against 0 that can be turned into a
1386 bratnz/bratzr instruction. */
1389 branch_zero_operator (op, mode)
1391 enum machine_mode mode;
1395 if (GET_MODE (op) != mode && mode != VOIDmode)
1398 if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
1402 if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0)))
1406 if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
1412 /* Return true if an operand is simple, suitable for use as the destination of
1413 a conditional move */
1416 cond_move_dest_operand (op, mode)
1418 enum machine_mode mode ATTRIBUTE_UNUSED;
1422 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1425 switch (GET_CODE (op))
1432 return gpr_operand (op, mode);
1434 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1436 addr = XEXP (op, 0);
1437 return (GET_CODE (addr) != POST_DEC
1438 && GET_CODE (addr) != POST_INC
1439 && d30v_legitimate_address_p (mode, addr, reload_completed));
1445 /* Return true if an operand is simple, suitable for use in a conditional move */
1448 cond_move_operand (op, mode)
1450 enum machine_mode mode ATTRIBUTE_UNUSED;
1454 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1457 switch (GET_CODE (op))
1464 return gpr_operand (op, mode);
1467 return GET_MODE (op) == SFmode;
1475 /* Don't allow post dec/inc, since we might not get the side effects correct. */
1477 addr = XEXP (op, 0);
1478 return (GET_CODE (addr) != POST_DEC
1479 && GET_CODE (addr) != POST_INC
1480 && d30v_legitimate_address_p (mode, addr, reload_completed));
1486 /* Return true if an operand is simple, suitable for use in conditional execution.
1487 Unlike cond_move, we can allow auto inc/dec. */
1490 cond_exec_operand (op, mode)
1492 enum machine_mode mode;
1494 if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
1497 switch (GET_CODE (op))
1504 return gpr_operand (op, mode);
1507 return GET_MODE (op) == SFmode;
1516 return memory_operand (op, mode);
1522 /* Return true if operand is a SI mode signed relational test. */
1525 srelational_si_operator (op, mode)
1527 enum machine_mode mode;
1531 if (GET_MODE (op) != mode && mode != VOIDmode)
1534 switch (GET_CODE (op))
1549 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1552 if (GET_MODE (x0) != SImode)
1556 switch (GET_CODE (x1))
1573 /* Return true if operand is a SI mode unsigned relational test. */
1576 urelational_si_operator (op, mode)
1578 enum machine_mode mode;
1582 if (GET_MODE (op) != mode && mode != VOIDmode)
1585 switch (GET_CODE (op))
1598 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1601 if (GET_MODE (x0) != SImode)
1605 switch (GET_CODE (x1))
1622 /* Return true if operand is a DI mode relational test. */
1625 relational_di_operator (op, mode)
1627 enum machine_mode mode;
1631 if (GET_MODE (op) != mode && mode != VOIDmode)
1634 if (GET_RTX_CLASS (GET_CODE (op)) != '<')
1638 if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
1641 if (GET_MODE (x0) != DImode)
1645 if (GET_CODE (x1) != REG && GET_CODE (x1) != SUBREG
1646 && GET_CODE (x1) != CONST_INT && GET_CODE (x1) != CONST_DOUBLE)
1653 /* Calculate the stack information for the current function.
1655 D30V stack frames look like:
1658 +-------------------------------+
1659 | Argument word #19 |
1660 +-------------------------------+
1661 | Argument word #18 |
1662 +-------------------------------+
1663 | Argument word #17 |
1664 +-------------------------------+
1665 | Argument word #16 |
1666 Prev sp +-------------------------------+
1668 | Save for arguments 1..16 if |
1669 | the func. uses stdarg/varargs |
1671 +-------------------------------+
1673 | Save area for GPR registers |
1675 +-------------------------------+
1677 | Save area for accumulators |
1679 +-------------------------------+
1683 +-------------------------------+
1685 | alloca space if used |
1687 +-------------------------------+
1689 | Space for outgoing arguments |
1691 low SP----> +-------------------------------+
1697 static d30v_stack_t info, zero_info;
1698 d30v_stack_t *info_ptr = &info;
1699 tree fndecl = current_function_decl;
1700 tree fntype = TREE_TYPE (fndecl);
1708 unsigned char save_gpr_p[GPR_LAST];
1711 /* If we've already calculated the values and reload is complete, just return now */
1712 if (d30v_stack_cache)
1713 return d30v_stack_cache;
1715 /* Zero all fields */
1718 if (current_function_profile)
1719 regs_ever_live[GPR_LINK] = 1;
1721 /* Determine if this is a stdarg function */
1722 if (TYPE_ARG_TYPES (fntype) != 0
1723 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
1727 /* Find the last argument, and see if it is __builtin_va_alist. */
1728 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1730 next_arg = TREE_CHAIN (cur_arg);
1731 if (next_arg == (tree)0)
1733 if (DECL_NAME (cur_arg)
1734 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1742 /* Calculate which registers need to be saved & save area size */
1746 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
1748 if (regs_ever_live[i] && !call_used_regs[i])
1750 info_ptr->save_p[i] = 2;
1757 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1759 if (regs_ever_live[i] && (!call_used_regs[i] || i == GPR_LINK))
1768 /* Determine which register pairs can be saved together with ld2w/st2w */
1769 for (i = GPR_FIRST; i <= GPR_LAST; i++)
1771 if (((i - GPR_FIRST) & 1) == 0 && save_gpr_p[i] && save_gpr_p[i+1])
1774 info_ptr->save_p[i++] = 2;
1776 else if (save_gpr_p[i])
1779 info_ptr->save_p[i] = 1;
1783 /* Determine various sizes */
1784 info_ptr->varargs_p = varargs_p;
1785 info_ptr->varargs_size = ((varargs_p)
1786 ? (GPR_ARG_LAST + 1 - GPR_ARG_FIRST) * UNITS_PER_WORD
1789 info_ptr->accum_size = 2 * UNITS_PER_WORD * saved_accs;
1790 info_ptr->gpr_size = D30V_ALIGN (UNITS_PER_WORD * saved_gprs,
1791 2 * UNITS_PER_WORD);
1792 info_ptr->vars_size = D30V_ALIGN (get_frame_size (), 2 * UNITS_PER_WORD);
1793 info_ptr->parm_size = D30V_ALIGN (current_function_outgoing_args_size,
1794 2 * UNITS_PER_WORD);
1796 info_ptr->total_size = D30V_ALIGN ((info_ptr->gpr_size
1797 + info_ptr->accum_size
1798 + info_ptr->vars_size
1799 + info_ptr->parm_size
1800 + info_ptr->varargs_size
1801 + current_function_pretend_args_size),
1802 (STACK_BOUNDARY / BITS_PER_UNIT));
1804 info_ptr->save_offset = (info_ptr->total_size
1805 - (current_function_pretend_args_size
1806 + info_ptr->varargs_size
1807 + info_ptr->gpr_size
1808 + info_ptr->accum_size));
1810 /* The link register is the last GPR saved, but there might be some padding
1811 bytes after it, so account for that. */
1812 info_ptr->link_offset = (info_ptr->total_size
1813 - (current_function_pretend_args_size
1814 + info_ptr->varargs_size
1815 + (info_ptr->gpr_size
1816 - UNITS_PER_WORD * saved_gprs)
1819 info_ptr->memrefs_varargs = info_ptr->varargs_size / (2 * UNITS_PER_WORD);
1820 info_ptr->memrefs_2words = memrefs_2words;
1821 info_ptr->memrefs_1word = memrefs_1word;
1823 if (reload_completed)
1824 d30v_stack_cache = info_ptr;
1830 /* Internal function to print all of the information about the stack */
1833 debug_stack_info (info)
1839 info = d30v_stack_info ();
1841 fprintf (stderr, "\nStack information for function %s:\n",
1842 ((current_function_decl && DECL_NAME (current_function_decl))
1843 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1846 fprintf (stderr, "\tsave_offset = %d\n", info->save_offset);
1847 fprintf (stderr, "\tmemrefs_varargs = %d\n", info->memrefs_varargs);
1848 fprintf (stderr, "\tmemrefs_2words = %d\n", info->memrefs_2words);
1849 fprintf (stderr, "\tmemrefs_1word = %d\n", info->memrefs_1word);
1850 fprintf (stderr, "\tvarargs_p = %d\n", info->varargs_p);
1851 fprintf (stderr, "\tvarargs_size = %d\n", info->varargs_size);
1852 fprintf (stderr, "\tvars_size = %d\n", info->vars_size);
1853 fprintf (stderr, "\tparm_size = %d\n", info->parm_size);
1854 fprintf (stderr, "\tgpr_size = %d\n", info->gpr_size);
1855 fprintf (stderr, "\taccum_size = %d\n", info->accum_size);
1856 fprintf (stderr, "\ttotal_size = %d\n", info->total_size);
1857 fprintf (stderr, "\tsaved registers =");
1859 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1861 if (info->save_p[i] == 2)
1863 fprintf (stderr, " %s-%s", reg_names[i], reg_names[i+1]);
1866 else if (info->save_p[i])
1867 fprintf (stderr, " %s", reg_names[i]);
1870 putc ('\n', stderr);
1875 /* Return non-zero if this function is known to have a null or 1 instruction epilogue. */
1880 if (reload_completed)
1882 d30v_stack_t *info = d30v_stack_info ();
1884 /* If no epilogue code is needed, can use just a simple jump */
1885 if (info->total_size == 0)
1889 /* If just a small amount of local stack was allocated and no registers
1890 saved, skip forward branch */
1891 if (info->total_size == info->vars_size
1892 && IN_RANGE_P (info->total_size, 1, 31))
1901 /* A C statement (sans semicolon) for initializing the variable CUM for the
1902 state at the beginning of the argument list. The variable has type
1903 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1904 of the function which will receive the args, or 0 if the args are to a
1905 compiler support library function. The value of INDIRECT is nonzero when
1906 processing an indirect call, for example a call through a function pointer.
1907 The value of INDIRECT is zero for a call to an explicitly named function, a
1908 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1909 arguments for the function being compiled.
1911 When processing a call to a compiler support library function, LIBNAME
1912 identifies which one. It is a `symbol_ref' rtx which contains the name of
1913 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1914 being processed. Thus, each time this macro is called, either LIBNAME or
1915 FNTYPE is nonzero, but never both of them at once. */
1918 d30v_init_cumulative_args (cum, fntype, libname, indirect, incoming)
1919 CUMULATIVE_ARGS *cum;
1925 *cum = GPR_ARG_FIRST;
1927 if (TARGET_DEBUG_ARG)
1929 fprintf (stderr, "\ninit_cumulative_args:");
1931 fputs (" indirect", stderr);
1934 fputs (" incoming", stderr);
1938 tree ret_type = TREE_TYPE (fntype);
1939 fprintf (stderr, " return=%s,",
1940 tree_code_name[ (int)TREE_CODE (ret_type) ]);
1943 if (libname && GET_CODE (libname) == SYMBOL_REF)
1944 fprintf (stderr, " libname=%s", XSTR (libname, 0));
1946 putc ('\n', stderr);
1951 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1952 argument with the specified mode and type. If it is not defined,
1953 `PARM_BOUNDARY' is used for all arguments. */
1956 d30v_function_arg_boundary (mode, type)
1957 enum machine_mode mode;
1960 int size = ((mode == BLKmode && type)
1961 ? int_size_in_bytes (type)
1962 : (int) GET_MODE_SIZE (mode));
1964 return (size > UNITS_PER_WORD) ? 2*UNITS_PER_WORD : UNITS_PER_WORD;
1968 /* A C expression that controls whether a function argument is passed in a
1969 register, and which register.
1971 The arguments are CUM, which summarizes all the previous arguments; MODE,
1972 the machine mode of the argument; TYPE, the data type of the argument as a
1973 tree node or 0 if that is not known (which happens for C support library
1974 functions); and NAMED, which is 1 for an ordinary argument and 0 for
1975 nameless arguments that correspond to `...' in the called function's
1978 The value of the expression should either be a `reg' RTX for the hard
1979 register in which to pass the argument, or zero to pass the argument on the
1982 For machines like the VAX and 68000, where normally all arguments are
1983 pushed, zero suffices as a definition.
1985 The usual way to make the ANSI library `stdarg.h' work on a machine where
1986 some arguments are usually passed in registers, is to cause nameless
1987 arguments to be passed on the stack instead. This is done by making
1988 `FUNCTION_ARG' return 0 whenever NAMED is 0.
1990 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
1991 this macro to determine if this argument is of a type that must be passed in
1992 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
1993 returns non-zero for such an argument, the compiler will abort. If
1994 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
1995 stack and then loaded into a register. */
1998 d30v_function_arg (cum, mode, type, named, incoming)
1999 CUMULATIVE_ARGS *cum;
2000 enum machine_mode mode;
2003 int incoming ATTRIBUTE_UNUSED;
2005 int size = ((mode == BLKmode && type)
2006 ? int_size_in_bytes (type)
2007 : (int) GET_MODE_SIZE (mode));
2008 int adjust = (size > UNITS_PER_WORD && (*cum & 1) != 0);
2011 /* Return a marker for use in the call instruction. */
2012 if (mode == VOIDmode)
2015 else if (*cum + adjust <= GPR_ARG_LAST)
2016 ret = gen_rtx (REG, mode, *cum + adjust);
2021 if (TARGET_DEBUG_ARG)
2023 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d, arg = %s\n",
2024 *cum, GET_MODE_NAME (mode), named, size, adjust,
2025 (ret) ? ((ret == const0_rtx) ? "<0>" : reg_names[ REGNO (ret) ]) : "memory");
2031 /* A C expression for the number of words, at the beginning of an argument,
2032 must be put in registers. The value must be zero for arguments that are
2033 passed entirely in registers or that are entirely pushed on the stack.
2035 On some machines, certain arguments must be passed partially in registers
2036 and partially in memory. On these machines, typically the first N words of
2037 arguments are passed in registers, and the rest on the stack. If a
2038 multi-word argument (a `double' or a structure) crosses that boundary, its
2039 first few words must be passed in registers and the rest must be pushed.
2040 This macro tells the compiler when this occurs, and how many of the words
2041 should go in registers.
2043 `FUNCTION_ARG' for these arguments should return the first register to be
2044 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
2045 the called function. */
2048 d30v_function_arg_partial_nregs (cum, mode, type, named)
2049 CUMULATIVE_ARGS *cum;
2050 enum machine_mode mode;
2052 int named ATTRIBUTE_UNUSED;
2054 int bytes = ((mode == BLKmode)
2055 ? int_size_in_bytes (type)
2056 : (int) GET_MODE_SIZE (mode));
2057 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2058 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2059 int arg_num = *cum + adjust;
2062 ret = ((arg_num <= GPR_ARG_LAST && arg_num + words > GPR_ARG_LAST+1)
2063 ? GPR_ARG_LAST - arg_num + 1
2066 if (TARGET_DEBUG_ARG && ret)
2067 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
2073 /* A C expression that indicates when an argument must be passed by reference.
2074 If nonzero for an argument, a copy of that argument is made in memory and a
2075 pointer to the argument is passed instead of the argument itself. The
2076 pointer is passed in whatever way is appropriate for passing a pointer to
2079 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
2080 definition of this macro might be
2081 #define FUNCTION_ARG_PASS_BY_REFERENCE\
2082 (CUM, MODE, TYPE, NAMED) \
2083 MUST_PASS_IN_STACK (MODE, TYPE) */
2086 d30v_function_arg_pass_by_reference (cum, mode, type, named)
2087 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2088 enum machine_mode mode;
2090 int named ATTRIBUTE_UNUSED;
2092 int ret = MUST_PASS_IN_STACK (mode, type);
2094 if (TARGET_DEBUG_ARG && ret)
2095 fprintf (stderr, "function_arg_pass_by_reference: %d\n", ret);
2101 /* A C statement (sans semicolon) to update the summarizer variable CUM to
2102 advance past an argument in the argument list. The values MODE, TYPE and
2103 NAMED describe that argument. Once this is done, the variable CUM is
2104 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
2106 This macro need not do anything if the argument in question was passed on
2107 the stack. The compiler knows how to track the amount of stack space used
2108 for arguments without any special help. */
2111 d30v_function_arg_advance (cum, mode, type, named)
2112 CUMULATIVE_ARGS *cum;
2113 enum machine_mode mode;
2117 int bytes = ((mode == BLKmode)
2118 ? int_size_in_bytes (type)
2119 : (int) GET_MODE_SIZE (mode));
2120 int words = D30V_ALIGN (bytes, UNITS_PER_WORD) / UNITS_PER_WORD;
2121 int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
2123 *cum += words + adjust;
2125 if (TARGET_DEBUG_ARG)
2127 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d\n",
2128 *cum, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD, adjust);
2132 /* If defined, is a C expression that produces the machine-specific code for a
2133 call to `__builtin_saveregs'. This code will be moved to the very beginning
2134 of the function, before any parameter access are made. The return value of
2135 this function should be an RTX that contains the value to use as the return
2136 of `__builtin_saveregs'.
2138 If this macro is not defined, the compiler will output an ordinary call to
2139 the library function `__builtin_saveregs'. */
2142 d30v_expand_builtin_saveregs ()
2144 int offset = UNITS_PER_WORD * (GPR_ARG_LAST + 1 - GPR_ARG_FIRST);
2146 if (TARGET_DEBUG_ARG)
2147 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2150 return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2154 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2155 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2156 arguments into the stack so that all the arguments appear to have been
2157 passed consecutively on the stack. Once this is done, you can use the
2158 standard implementation of varargs that works for machines that pass all
2159 their arguments on the stack.
2161 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2162 the values that obtain after processing of the named arguments. The
2163 arguments MODE and TYPE describe the last named argument--its machine mode
2164 and its data type as a tree node.
2166 The macro implementation should do two things: first, push onto the stack
2167 all the argument registers *not* used for the named arguments, and second,
2168 store the size of the data thus pushed into the `int'-valued variable whose
2169 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2170 store here will serve as additional offset for setting up the stack frame.
2172 Because you must generate code to push the anonymous arguments at compile
2173 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2174 useful on machines that have just a single category of argument register and
2175 use it uniformly for all data types.
2177 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2178 function are being analyzed for the second time. This happens for an inline
2179 function, which is not actually compiled until the end of the source file.
2180 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2184 d30v_setup_incoming_varargs (cum, mode, type, pretend_size, second_time)
2185 CUMULATIVE_ARGS *cum;
2186 enum machine_mode mode;
2187 tree type ATTRIBUTE_UNUSED;
2188 int *pretend_size ATTRIBUTE_UNUSED;
2191 if (TARGET_DEBUG_ARG)
2193 "setup_vararg: words = %2d, mode = %4s, second_time = %d\n",
2194 *cum, GET_MODE_NAME (mode), second_time);
2198 /* Create the va_list data type. */
2201 d30v_build_va_list ()
2203 tree f_arg_ptr, f_arg_num, record, type_decl;
2206 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2207 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2208 int_type_node = make_signed_type (INT_TYPE_SIZE);
2210 f_arg_ptr = build_decl (FIELD_DECL, get_identifier ("__va_arg_ptr"),
2212 f_arg_num = build_decl (FIELD_DECL, get_identifier ("__va_arg_num"),
2215 DECL_FIELD_CONTEXT (f_arg_ptr) = record;
2216 DECL_FIELD_CONTEXT (f_arg_num) = record;
2218 TREE_CHAIN (record) = type_decl;
2219 TYPE_NAME (record) = type_decl;
2220 TYPE_FIELDS (record) = f_arg_ptr;
2221 TREE_CHAIN (f_arg_ptr) = f_arg_num;
2223 layout_type (record);
2225 /* The correct type is an array type of one element. */
2226 return build_array_type (record, build_index_type (size_zero_node));
2230 /* Expand __builtin_va_start to do the va_start macro. */
2233 d30v_expand_builtin_va_start (stdarg_p, valist, nextarg)
2234 int stdarg_p ATTRIBUTE_UNUSED;
2236 rtx nextarg ATTRIBUTE_UNUSED;
2238 HOST_WIDE_INT words;
2239 tree f_arg_ptr, f_arg_num;
2240 tree arg_ptr, arg_num, saveregs, t;
2242 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2243 f_arg_num = TREE_CHAIN (f_arg_ptr);
2245 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2246 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2247 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2249 words = current_function_args_info; /* __builtin_args_info (0) */
2251 /* (AP)->__va_arg_ptr = (int *) __builtin_saveregs (); */
2252 saveregs = make_tree (TREE_TYPE (arg_ptr), d30v_expand_builtin_saveregs ());
2253 t = build (MODIFY_EXPR, TREE_TYPE (arg_ptr), arg_ptr, saveregs);
2254 TREE_SIDE_EFFECTS (t) = 1;
2255 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2257 /* (AP)->__va_arg_num = __builtin_args_info (0) - 2; */
2258 t = build (PLUS_EXPR, TREE_TYPE (arg_num), build_int_2 (words, 0),
2259 build_int_2 (-GPR_ARG_FIRST, 0));
2260 t = build (MODIFY_EXPR, TREE_TYPE (arg_num), arg_num, t);
2261 TREE_SIDE_EFFECTS (t) = 1;
2262 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2266 /* Expand __builtin_va_arg to do the va_arg macro. */
2269 d30v_expand_builtin_va_arg(valist, type)
2273 tree f_arg_ptr, f_arg_num;
2274 tree arg_ptr, arg_num, t, ptr;
2276 rtx lab_false, ptr_rtx, r;
2278 f_arg_ptr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
2279 f_arg_num = TREE_CHAIN (f_arg_ptr);
2281 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
2282 arg_ptr = build (COMPONENT_REF, TREE_TYPE (f_arg_ptr), valist, f_arg_ptr);
2283 arg_num = build (COMPONENT_REF, TREE_TYPE (f_arg_num), valist, f_arg_num);
2285 size = int_size_in_bytes (type);
2287 lab_false = gen_label_rtx ();
2288 ptr_rtx = gen_reg_rtx (Pmode);
2290 /* if (sizeof (TYPE) > 4 && ((AP)->__va_arg_num & 1) != 0)
2291 (AP)->__va_arg_num++; */
2293 if (size > UNITS_PER_WORD)
2295 t = build (BIT_AND_EXPR, TREE_TYPE (arg_num), arg_num,
2296 build_int_2 (1, 0));
2298 emit_cmp_and_jump_insns (expand_expr (t, NULL_RTX, QImode, EXPAND_NORMAL),
2299 GEN_INT (0), EQ, const1_rtx, QImode, 1,
2302 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2303 build_int_2 (1, 0));
2304 TREE_SIDE_EFFECTS (t) = 1;
2305 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2307 emit_label (lab_false);
2311 /* __ptr = (TYPE *)(((char *)(void *)((AP)->__va_arg_ptr
2312 + (AP)->__va_arg_num))); */
2314 t = build (MULT_EXPR, TREE_TYPE (arg_num), arg_num, build_int_2 (4, 0));
2315 t = build (PLUS_EXPR, ptr_type_node, arg_ptr, t);
2317 /* if (sizeof (TYPE) < 4)
2318 __ptr = (void *)__ptr + 4 - sizeof (TYPE); */
2320 if (size < UNITS_PER_WORD)
2321 t = build (PLUS_EXPR, ptr_type_node, t,
2322 build_int_2 (UNITS_PER_WORD - size, 0));
2324 TREE_SIDE_EFFECTS (t) = 1;
2326 ptr = build1 (NOP_EXPR, build_pointer_type (type), t);
2327 t = build (MODIFY_EXPR, type, ptr, t);
2329 r = expand_expr (t, ptr_rtx, Pmode, EXPAND_NORMAL);
2331 emit_move_insn (ptr_rtx, r);
2334 /* (AP)->__va_arg_num += (sizeof (TYPE) + 3) / 4; */
2335 num = (size + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
2336 t = build (POSTINCREMENT_EXPR, TREE_TYPE (arg_num), arg_num,
2337 build_int_2 (num, 0));
2338 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2343 /* Generate the assembly code for function entry. FILE is a stdio
2344 stream to output the code to. SIZE is an int: how many units of
2345 temporary storage to allocate.
2347 Refer to the array `regs_ever_live' to determine which registers to
2348 save; `regs_ever_live[I]' is nonzero if register number I is ever
2349 used in the function. This function is responsible for knowing
2350 which registers should not be saved even if used. */
2353 d30v_output_function_prologue (stream, size)
2354 FILE *stream ATTRIBUTE_UNUSED;
2355 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2357 /* For the d30v, move all of the prologue processing into separate
2362 /* Called after register allocation to add any instructions needed for
2363 the prologue. Using a prologue insn is favored compared to putting
2364 all of the instructions in output_function_prologue (), since it
2365 allows the scheduler to intermix instructions with the saves of the
2366 caller saved registers. In some cases, it might be necessary to
2367 emit a barrier instruction as the last insn to prevent such
2371 d30v_expand_prologue ()
2373 rtx sp = stack_pointer_rtx;
2374 d30v_stack_t *info = d30v_stack_info ();
2376 rtx mem_di = NULL_RTX;
2377 rtx mem_si = NULL_RTX;
2378 int num_memrefs = (info->memrefs_2words
2379 + info->memrefs_1word
2380 + info->memrefs_varargs);
2382 if (TARGET_DEBUG_STACK)
2383 debug_stack_info (info);
2385 /* Grow the stack. */
2386 if (info->total_size)
2387 emit_insn (gen_addsi3 (sp, sp, GEN_INT (- info->total_size)));
2389 /* If there is more than one save, use post-increment addressing which will
2390 result in smaller code, than would the normal references. If there is
2391 only one save, just do the store as normal. */
2393 if (num_memrefs > 1)
2395 rtx save_tmp = gen_rtx (REG, Pmode, GPR_STACK_TMP);
2396 rtx post_inc = gen_rtx (POST_INC, Pmode, save_tmp);
2397 mem_di = gen_rtx (MEM, DImode, post_inc);
2398 mem_si = gen_rtx (MEM, SImode, post_inc);
2399 emit_insn (gen_addsi3 (save_tmp, sp, GEN_INT (info->save_offset)));
2401 else if (num_memrefs == 1)
2403 rtx addr = plus_constant (sp, info->save_offset);
2404 mem_di = gen_rtx (MEM, DImode, addr);
2405 mem_si = gen_rtx (MEM, SImode, addr);
2408 /* Save the accumulators. */
2409 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2410 if (info->save_p[i])
2412 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2413 emit_insn (gen_movdi (acc_tmp, gen_rtx (REG, DImode, i)));
2414 emit_insn (gen_movdi (mem_di, acc_tmp));
2417 /* Save the GPR registers that are adjacent to each other with st2w. */
2418 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2419 if (info->save_p[i] == 2)
2420 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2422 /* Save the GPR registers that need to be saved with a single word store. */
2423 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2424 if (info->save_p[i] == 1)
2425 emit_insn (gen_movsi (mem_si, gen_rtx (REG, SImode, i)));
2427 /* Save the argument registers if this function accepts variable args. */
2428 if (info->varargs_p)
2430 /* Realign r22 if an odd # of GPRs were saved. */
2431 if ((info->memrefs_1word & 1) != 0)
2433 rtx save_tmp = XEXP (XEXP (mem_si, 0), 0);
2434 emit_insn (gen_addsi3 (save_tmp, save_tmp, GEN_INT (UNITS_PER_WORD)));
2437 for (i = GPR_ARG_FIRST; i <= GPR_ARG_LAST; i += 2)
2438 emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
2441 /* Update the frame pointer. */
2442 if (frame_pointer_needed)
2443 emit_move_insn (frame_pointer_rtx, sp);
2445 /* Hack for now, to prevent scheduler from being too cleaver */
2446 emit_insn (gen_blockage ());
2450 /* This function generates the assembly code for function exit.
2451 Args are as for output_function_prologue ().
2453 The function epilogue should not depend on the current stack
2454 pointer! It should use the frame pointer only. This is mandatory
2455 because of alloca; we also take advantage of it to omit stack
2456 adjustments before returning. */
2459 d30v_output_function_epilogue (stream, size)
2460 FILE *stream ATTRIBUTE_UNUSED;
2461 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2463 /* For the d30v, move all processing to be as insns, but do any
2464 cleanup here, since it is done after handling all of the insns. */
2465 d30v_stack_cache = (d30v_stack_t *)0; /* reset stack cache */
2470 /* Called after register allocation to add any instructions needed for
2471 the epilogue. Using an epilogue insn is favored compared to putting
2472 all of the instructions in output_function_prologue(), since it
2473 allows the scheduler to intermix instructions with the saves of the
2474 caller saved registers. In some cases, it might be necessary to
2475 emit a barrier instruction as the last insn to prevent such
2479 d30v_expand_epilogue ()
2481 rtx sp = stack_pointer_rtx;
2482 d30v_stack_t *info = d30v_stack_info ();
2484 rtx mem_di = NULL_RTX;
2485 rtx mem_si = NULL_RTX;
2489 /* Hack for now, to prevent scheduler from being too cleaver */
2490 emit_insn (gen_blockage ());
2492 /* Restore sp from fp. */
2493 if (frame_pointer_needed)
2494 emit_move_insn (sp, frame_pointer_rtx);
2496 /* For the epilogue, use post-increment addressing all of the time. First
2497 adjust the sp, to eliminate all of the stack, except for the save area. */
2499 if (info->save_offset)
2500 emit_insn (gen_addsi3 (sp, sp, GEN_INT (info->save_offset)));
2502 post_inc = gen_rtx (POST_INC, Pmode, sp);
2503 mem_di = gen_rtx (MEM, DImode, post_inc);
2504 mem_si = gen_rtx (MEM, SImode, post_inc);
2506 /* Restore the accumulators. */
2507 for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
2508 if (info->save_p[i])
2510 rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
2511 emit_insn (gen_movdi (acc_tmp, mem_di));
2512 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), acc_tmp));
2515 /* Restore the GPR registers that are adjacent to each other with ld2w. */
2516 for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
2517 if (info->save_p[i] == 2)
2518 emit_insn (gen_movdi (gen_rtx (REG, DImode, i), mem_di));
2520 /* Save the GPR registers that need to be saved with a single word store. */
2522 for (i = GPR_FIRST; i <= GPR_LAST; i++)
2523 if (info->save_p[i] == 1)
2525 if (cfun->machine->eh_epilogue_sp_ofs && i == GPR_LINK)
2531 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2534 emit_insn (gen_movsi (gen_rtx (REG, SImode, i), mem_si));
2538 /* Release any remaining stack that was allocated for saving the
2539 varargs registers or because an odd # of registers were stored. */
2540 if ((info->memrefs_1word & 1) != 0)
2541 extra_stack += UNITS_PER_WORD;
2542 extra_stack += current_function_pretend_args_size + info->varargs_size;
2546 if (cfun->machine->eh_epilogue_sp_ofs)
2547 emit_insn (gen_addsi3 (cfun->machine->eh_epilogue_sp_ofs,
2548 cfun->machine->eh_epilogue_sp_ofs,
2549 GEN_INT (extra_stack)));
2551 emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
2553 if (cfun->machine->eh_epilogue_sp_ofs)
2554 emit_insn (gen_addsi3 (sp, sp, cfun->machine->eh_epilogue_sp_ofs));
2556 /* Now emit the return instruction. */
2557 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
2561 /* A C statement or compound statement to output to FILE some assembler code to
2562 call the profiling subroutine `mcount'. Before calling, the assembler code
2563 must load the address of a counter variable into a register where `mcount'
2564 expects to find the address. The name of this variable is `LP' followed by
2565 the number LABELNO, so you would generate the name using `LP%d' in a
2568 The details of how the address should be passed to `mcount' are determined
2569 by your operating system environment, not by GNU CC. To figure them out,
2570 compile a small program for profiling using the system's installed C
2571 compiler and look at the assembler code that results. */
2574 d30v_function_profiler (stream, labelno)
2576 int labelno ATTRIBUTE_UNUSED;
2578 fprintf (stream, "# profile\n");
2582 /* Split a 64 bit item into an upper and a lower part. We specifically do not
2583 want to call gen_highpart/gen_lowpart on CONST_DOUBLEs since it will give us
2584 the wrong part for floating point in cross compilers, and split_double does
2585 not handle registers. Also abort if the register is not a general purpose
2589 d30v_split_double (value, p_high, p_low)
2597 if (!reload_completed)
2600 switch (GET_CODE (value))
2603 if (GET_CODE (SUBREG_REG (value)) != REG)
2605 offset = subreg_regno_offset (REGNO (SUBREG_REG (value)),
2606 GET_MODE (SUBREG_REG (value)),
2607 SUBREG_BYTE (value),
2609 value = SUBREG_REG (value);
2614 regno = REGNO (value) + offset;
2618 *p_high = gen_rtx (REG, SImode, regno);
2619 *p_low = gen_rtx (REG, SImode, regno+1);
2624 split_double (value, p_high, p_low);
2633 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2634 for an instruction operand that is a memory reference whose address is X. X
2635 is an RTL expression. */
2638 d30v_print_operand_address (stream, x)
2642 if (GET_CODE (x) == MEM)
2645 switch (GET_CODE (x))
2651 fputs (reg_names[ REGNO (x) ], stream);
2655 fprintf (stream, "%ld", (long) INTVAL (x));
2658 /* We wrap simple symbol refs inside a parenthesis, so that a name
2659 like `r2' is not taken for a register name. */
2661 fputs ("(", stream);
2662 assemble_name (stream, XSTR (x, 0));
2663 fputs (")", stream);
2668 output_addr_const (stream, x);
2672 fatal_insn ("bad insn to d30v_print_operand_address:", x);
2676 /* Print a memory reference suitable for the ld/st instructions. */
2679 d30v_print_operand_memory_reference (stream, x)
2686 switch (GET_CODE (x))
2689 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2709 if (GET_CODE (x0) == CONST_INT || GET_CODE (x0) == SYMBOL_REF
2710 || GET_CODE (x0) == CONST || GET_CODE (x0) == LABEL_REF)
2718 fputs ("@(", stream);
2720 fputs (reg_names[GPR_R0], stream);
2724 const char *suffix = "";
2727 if (GET_CODE (x0) == SUBREG)
2729 offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)),
2730 GET_MODE (SUBREG_REG (x0)),
2733 x0 = SUBREG_REG (x0);
2736 if (GET_CODE (x0) == POST_INC)
2741 else if (GET_CODE (x0) == POST_DEC)
2747 if (GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
2748 fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix);
2750 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2753 fputs (",", stream);
2756 fputs (reg_names[GPR_R0], stream);
2762 switch (GET_CODE (x1))
2765 offset1 = subreg_regno_offset (REGNO (SUBREG_REG (x1)),
2766 GET_MODE (SUBREG_REG (x1)),
2769 x1 = SUBREG_REG (x1);
2770 if (GET_CODE (x1) != REG)
2771 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2775 fputs (reg_names[REGNO (x1) + offset1], stream);
2779 fprintf (stream, "%ld", (long) INTVAL (x1));
2785 d30v_print_operand_address (stream, x1);
2789 fatal_insn ("bad insn to d30v_print_operand_memory_reference:", x);
2793 fputs (")", stream);
2797 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2798 for an instruction operand X. X is an RTL expression.
2800 LETTER is a value that can be used to specify one of several ways of
2801 printing the operand. It is used when identical operands must be printed
2802 differently depending on the context. LETTER comes from the `%'
2803 specification that was used to request printing of the operand. If the
2804 specification was just `%DIGIT' then LETTER is 0; if the specification was
2805 `%LTR DIGIT' then LETTER is the ASCII code for LTR.
2807 If X is a register, this macro should print the register's name. The names
2808 can be found in an array `reg_names' whose type is `char *[]'. `reg_names'
2809 is initialized from `REGISTER_NAMES'.
2811 When the machine description has a specification `%PUNCT' (a `%' followed by
2812 a punctuation character), this macro is called with a null pointer for X and
2813 the punctuation character for LETTER.
2815 Standard operand flags that are handled elsewhere:
2816 `=' Output a number unique to each instruction in the compilation.
2817 `a' Substitute an operand as if it were a memory reference.
2818 `c' Omit the syntax that indicates an immediate operand.
2819 `l' Substitute a LABEL_REF into a jump instruction.
2820 `n' Like %cDIGIT, except negate the value before printing.
2822 The d30v specific operand flags are:
2824 `f' Print a SF constant as an int.
2825 `s' Subtract 32 and negate.
2826 `A' Print accumulator number without an `a' in front of it.
2827 `B' Print bit offset for BSET, etc. instructions.
2828 `E' Print u if this is zero extend, nothing if this is sign extend.
2829 `F' Emit /{f,t,x}{f,t,x} for executing a false condition.
2830 `L' Print the lower half of a 64 bit item.
2831 `M' Print a memory reference for ld/st instructions.
2832 `R' Return appropriate cmp instruction for relational test.
2834 `T' Emit /{f,t,x}{f,t,x} for executing a true condition.
2835 `U' Print the upper half of a 64 bit item. */
2838 d30v_print_operand (stream, x, letter)
2843 enum rtx_code code = (x) ? GET_CODE (x) : NIL;
2844 rtx split_values[2];
2851 case '.': /* Output r0 */
2852 fputs (reg_names[GPR_R0], stream);
2855 case 'f': /* Print a SF floating constant as an int */
2856 if (GET_CODE (x) != CONST_DOUBLE)
2857 fatal_insn ("bad insn to d30v_print_operand, 'f' modifier:", x);
2859 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2860 REAL_VALUE_TO_TARGET_SINGLE (rv, num);
2861 fprintf (stream, "%ld", num);
2864 case 'A': /* Print accumulator number without an `a' in front of it. */
2865 if (GET_CODE (x) != REG || !ACCUM_P (REGNO (x)))
2866 fatal_insn ("bad insn to d30v_print_operand, 'A' modifier:", x);
2868 putc ('0' + REGNO (x) - ACCUM_FIRST, stream);
2871 case 'M': /* Print a memory reference for ld/st */
2872 if (GET_CODE (x) != MEM)
2873 fatal_insn ("bad insn to d30v_print_operand, 'M' modifier:", x);
2875 d30v_print_operand_memory_reference (stream, XEXP (x, 0));
2878 case 'L': /* print lower part of 64 bit item. */
2879 case 'U': /* print upper part of 64 bit item. */
2880 d30v_split_double (x, &split_values[0], &split_values[1]);
2881 d30v_print_operand (stream, split_values[ letter == 'L' ], '\0');
2884 case ':': /* Output the condition for the current insn. */
2885 x = current_insn_predicate;
2891 case 'F': /* Print an appropriate suffix for a false comparision. */
2892 case 'T': /* Print an appropriate suffix for a true comparision. */
2893 /* Note that the sense of appropriate suffix is for conditional execution
2894 and opposite of what branches want. Branches just use the inverse
2896 if ((GET_CODE (x) == NE || GET_CODE (x) == EQ)
2897 && GET_MODE (x) == CCmode
2898 && GET_CODE (XEXP (x, 0)) == REG
2899 && (GPR_P (REGNO (XEXP (x, 0))) || BR_FLAG_P (REGNO (XEXP (x, 0))))
2900 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
2902 int true_false = (letter == 'T');
2904 if (GET_CODE (x) == EQ)
2905 true_false = !true_false;
2907 if (REGNO (XEXP (x, 0)) == FLAG_F0)
2908 fprintf (stream, "/%cx", (true_false) ? 'f' : 't');
2910 else if (REGNO (XEXP (x, 0)) == FLAG_F1)
2911 fprintf (stream, "/x%c", (true_false) ? 'f' : 't');
2914 fputs ((true_false) ? "tnz" : "tzr", stream);
2917 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F0)
2918 fprintf (stream, "/%cx", (letter == 'T') ? 't' : 'f');
2920 else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F1)
2921 fprintf (stream, "/x%c", (letter == 'T') ? 't' : 'f');
2923 else if (GET_CODE (x) == REG && GPR_P (REGNO (x)))
2924 fputs ((letter == 'T') ? "tnz" : "tzr", stream);
2927 fatal_insn ("bad insn to print_operand, 'F' or 'T' modifier:", x);
2930 case 'B': /* emit offset single bit to change */
2931 if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0)
2932 fprintf (stream, "%d", 31 - log);
2934 else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0)
2935 fprintf (stream, "%d", 31 - log);
2938 fatal_insn ("bad insn to print_operand, 'B' modifier:", x);
2941 case 'E': /* Print u if this is zero extend, nothing if sign extend. */
2942 if (GET_CODE (x) == ZERO_EXTEND)
2944 else if (GET_CODE (x) != SIGN_EXTEND)
2945 fatal_insn ("bad insn to print_operand, 'E' modifier:", x);
2948 case 'R': /* Return appropriate cmp instruction for relational test. */
2949 switch (GET_CODE (x))
2951 case EQ: fputs ("cmpeq", stream); break;
2952 case NE: fputs ("cmpne", stream); break;
2953 case LT: fputs ("cmplt", stream); break;
2954 case LE: fputs ("cmple", stream); break;
2955 case GT: fputs ("cmpgt", stream); break;
2956 case GE: fputs ("cmpge", stream); break;
2957 case LTU: fputs ("cmpult", stream); break;
2958 case LEU: fputs ("cmpule", stream); break;
2959 case GTU: fputs ("cmpugt", stream); break;
2960 case GEU: fputs ("cmpuge", stream); break;
2963 fatal_insn ("bad insn to print_operand, 'R' modifier:", x);
2967 case 's': /* Subtract 32 and negate (for 64 bit shifts). */
2968 if (GET_CODE (x) == CONST_INT)
2969 fprintf (stream, "%d", (int) (32 - INTVAL (x)));
2972 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2975 case 'S': /* Subtract 32. */
2976 if (GET_CODE (x) == CONST_INT)
2977 fprintf (stream, "%d", (int)(INTVAL (x) - 32));
2980 fatal_insn ("bad insn to print_operand, 's' modifier:", x);
2984 case 'z': /* If arg is 0 or 0.0, print r0, otherwise print as normal */
2985 if ((GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2986 || (GET_CODE (x) == CONST_DOUBLE && CONST_DOUBLE_LOW (x) == 0
2987 && CONST_DOUBLE_HIGH (x) == 0))
2989 fputs (reg_names[GPR_FIRST], stream);
2997 fputs (reg_names[ REGNO (x) ], stream);
2999 else if (code == CONST_INT)
3000 fprintf (stream, "%d", (int)INTVAL (x));
3002 else if (code == MEM)
3003 d30v_print_operand_address (stream, XEXP (x, 0));
3005 else if (CONSTANT_ADDRESS_P (x))
3006 d30v_print_operand_address (stream, x);
3009 fatal_insn ("bad insn in d30v_print_operand, 0 case", x);
3017 sprintf (buf, "invalid asm template character '%%%c'", letter);
3018 fatal_insn (buf, x);
3024 /* A C expression for the size in bytes of the trampoline, as an integer. */
3027 d30v_trampoline_size ()
3033 /* Create a long instruction for building up a trampoline. */
3036 d30v_build_long_insn (high_bits, low_bits, imm, mem)
3037 HOST_WIDE_INT high_bits;
3038 HOST_WIDE_INT low_bits;
3042 rtx reg = gen_reg_rtx (DImode);
3043 rtx high_word = gen_highpart (SImode, reg);
3044 rtx low_word = gen_lowpart (SImode, reg);
3045 rtx tmp1 = gen_reg_rtx (SImode);
3046 rtx tmp2 = gen_reg_rtx (SImode);
3047 rtx tmp3 = gen_reg_rtx (SImode);
3048 rtx tmp4 = gen_reg_rtx (SImode);
3049 rtx tmp5 = gen_reg_rtx (SImode);
3050 rtx tmp6 = gen_reg_rtx (SImode);
3052 imm = force_reg (SImode, imm);
3054 /* Stuff top 6 bits of immediate value into high word */
3055 emit_insn (gen_lshrsi3 (tmp1, imm, GEN_INT (26)));
3056 emit_insn (gen_andsi3 (tmp2, tmp1, GEN_INT (0x3F)));
3057 emit_insn (gen_iorsi3 (high_word, tmp2, GEN_INT (high_bits)));
3059 /* Now get the next 8 bits for building the low word */
3060 emit_insn (gen_andsi3 (tmp3, imm, GEN_INT (0x03FC0000)));
3061 emit_insn (gen_ashlsi3 (tmp4, tmp3, GEN_INT (2)));
3063 /* And the bottom 18 bits */
3064 emit_insn (gen_andsi3 (tmp5, imm, GEN_INT (0x0003FFFF)));
3065 emit_insn (gen_iorsi3 (tmp6, tmp4, tmp5));
3066 emit_insn (gen_iorsi3 (low_word, tmp6, GEN_INT (low_bits)));
3068 /* Store the instruction */
3069 emit_insn (gen_movdi (mem, reg));
3073 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
3074 RTX for the address of the trampoline; FNADDR is an RTX for the address of
3075 the nested function; STATIC_CHAIN is an RTX for the static chain value that
3076 should be passed to the function when it is called. */
3079 d30v_initialize_trampoline (addr, fnaddr, static_chain)
3084 /* The instruction space can only be accessed by ld2w/st2w.
3085 Generate on the fly:
3086 or r18,r0,<static-chain>
3088 d30v_build_long_insn (0x83A80000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 12),
3089 0x80000000, static_chain,
3090 gen_rtx (MEM, DImode, addr));
3092 d30v_build_long_insn (0x80180000, 0x80000000, fnaddr,
3093 gen_rtx (MEM, DImode, plus_constant (addr, 8)));
3097 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3098 RTX) is a legitimate memory address on the target machine for a memory
3099 operand of mode MODE. */
3101 #define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P) \
3103 ? REGNO_OK_FOR_BASE_P (REGNO) \
3104 : GPR_OR_PSEUDO_P (REGNO))
3107 d30v_legitimate_address_p (mode, x, strict_p)
3108 enum machine_mode mode;
3115 switch (GET_CODE (x))
3122 if (GET_CODE (x) != REG)
3128 ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p);
3135 if (GET_CODE (x0) == SUBREG)
3136 x0 = SUBREG_REG (x0);
3138 if (GET_CODE (x0) == POST_INC || GET_CODE (x0) == POST_DEC)
3141 if (GET_CODE (x0) != REG || !XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3144 switch (GET_CODE (x1))
3150 x1 = SUBREG_REG (x1);
3151 if (GET_CODE (x1) != REG)
3157 ret = XREGNO_OK_FOR_BASE_P (REGNO (x1), strict_p);
3161 ret = (IN_RANGE_P (INTVAL (x1), -32, 31)) ? 1 : 2;
3173 ret = (IN_RANGE_P (INTVAL (x), -32, 31)) ? 1 : 2;
3185 if (GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
3190 if (TARGET_DEBUG_ADDR)
3192 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n",
3193 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ");
3201 /* A C compound statement that attempts to replace X with a valid memory
3202 address for an operand of mode MODE. WIN will be a C statement label
3203 elsewhere in the code; the macro definition may use
3205 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3207 to avoid further processing if the address has become legitimate.
3209 X will always be the result of a call to `break_out_memory_refs', and OLDX
3210 will be the operand that was given to that function to produce X.
3212 The code generated by this macro should not alter the substructure of X. If
3213 it transforms X into a more legitimate form, it should assign X (which will
3214 always be a C variable) a new value.
3216 It is not necessary for this macro to come up with a legitimate address.
3217 The compiler has standard ways of doing so in all cases. In fact, it is
3218 safe for this macro to do nothing. But often a machine-dependent strategy
3219 can generate better code. */
3222 d30v_legitimize_address (x, oldx, mode, strict_p)
3224 rtx oldx ATTRIBUTE_UNUSED;
3225 enum machine_mode mode ATTRIBUTE_UNUSED;
3226 int strict_p ATTRIBUTE_UNUSED;
3230 if (TARGET_DEBUG_ADDR)
3234 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n");
3236 fprintf (stderr, "\ninto:\n");
3241 fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n");
3250 /* A C statement or compound statement with a conditional `goto LABEL;'
3251 executed if memory address X (an RTX) can have different meanings depending
3252 on the machine mode of the memory reference it is used for or if the address
3253 is valid for some modes but not others.
3255 Autoincrement and autodecrement addresses typically have mode-dependent
3256 effects because the amount of the increment or decrement is the size of the
3257 operand being addressed. Some machines have other mode-dependent addresses.
3258 Many RISC machines have no mode-dependent addresses.
3260 You may assume that ADDR is a valid address for the machine. */
3263 d30v_mode_dependent_address_p (addr)
3266 switch (GET_CODE (addr))
3280 /* Generate the appropriate comparison code for a test. */
3283 d30v_emit_comparison (test_int, result, arg1, arg2)
3289 enum rtx_code test = (enum rtx_code) test_int;
3290 enum machine_mode mode = GET_MODE (arg1);
3291 rtx rtx_test = gen_rtx (SET, VOIDmode, result, gen_rtx (test, CCmode, arg1, arg2));
3294 || (mode == DImode && (test == EQ || test == NE))
3295 || (mode == DImode && (test == LT || test == GE)
3296 && GET_CODE (arg2) == CONST_INT && INTVAL (arg2) == 0))
3299 else if (mode == DImode)
3300 return gen_rtx (PARALLEL, VOIDmode,
3303 gen_rtx (CLOBBER, VOIDmode,
3304 gen_reg_rtx (CCmode))));
3307 fatal_insn ("d30v_emit_comparison", rtx_test);
3311 /* Return appropriate code to move 2 words. Since DImode registers must start
3312 on even register numbers, there is no possibility of overlap. */
3315 d30v_move_2words (operands, insn)
3319 if (GET_CODE (operands[0]) == REG && GPR_P (REGNO (operands[0])))
3321 if (GET_CODE (operands[1]) == REG && GPR_P (REGNO (operands[1])))
3322 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3324 else if (GET_CODE (operands[1]) == REG && ACCUM_P (REGNO (operands[1])))
3325 return "mvfacc %L0,%1,%.\n\tmvfacc %U0,%1,32";
3327 else if (GET_CODE (operands[1]) == MEM)
3328 return "ld2w %0,%M1";
3330 else if (GET_CODE (operands[1]) == CONST_INT
3331 || GET_CODE (operands[1]) == CONST_DOUBLE)
3332 return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
3335 else if (GET_CODE (operands[0]) == REG && ACCUM_P (REGNO (operands[0])))
3337 if (GET_CODE (operands[1]) == REG
3338 && GPR_P (REGNO (operands[1])))
3339 return "mvtacc %0,%U1,%L1";
3341 if (GET_CODE (operands[1]) == CONST_INT
3342 && INTVAL (operands[1]) == 0)
3343 return "mvtacc %0,%.,%.";
3346 else if (GET_CODE (operands[0]) == MEM
3347 && GET_CODE (operands[1]) == REG
3348 && GPR_P (REGNO (operands[1])))
3349 return "st2w %1,%M0";
3351 fatal_insn ("bad call to d30v_move_2words", insn);
3355 /* Emit the code to do a conditional move instruction. Return FALSE
3356 if the conditional move could not be executed. */
3359 d30v_emit_cond_move (dest, test, true_value, false_value)
3366 enum machine_mode mode = GET_MODE (dest);
3367 int two_mem_moves_p = FALSE;
3369 if (GET_CODE (dest) == MEM)
3371 if (!reg_or_0_operand (true_value, mode))
3374 if (rtx_equal_p (dest, false_value))
3375 two_mem_moves_p = TRUE;
3377 else if (!reg_or_0_operand (false_value, mode))
3381 /* We used to try to optimize setting 0/1 by using mvfsys, but that turns out
3382 to be slower than just doing the conditional execution. */
3384 br_reg = gen_reg_rtx (CCmode);
3385 emit_insn (d30v_emit_comparison (GET_CODE (test), br_reg,
3386 d30v_compare_op0, d30v_compare_op1));
3388 if (!two_mem_moves_p)
3389 emit_insn (gen_rtx_SET (VOIDmode,
3391 gen_rtx_IF_THEN_ELSE (mode,
3392 gen_rtx_NE (CCmode, br_reg,
3398 /* Emit conditional stores as two separate stores. This avoids a problem
3399 where you have a conditional store, and one of the arms of the
3400 conditional store is spilled to memory. */
3401 emit_insn (gen_rtx_SET (VOIDmode,
3403 gen_rtx_IF_THEN_ELSE (mode,
3404 gen_rtx_NE (CCmode, br_reg,
3409 emit_insn (gen_rtx_SET (VOIDmode,
3411 gen_rtx_IF_THEN_ELSE (mode,
3412 gen_rtx_EQ (CCmode, br_reg,
3423 /* In rare cases, correct code generation requires extra machine dependent
3424 processing between the second jump optimization pass and delayed branch
3425 scheduling. On those machines, define this macro as a C statement to act on
3426 the code starting at INSN. */
3429 d30v_machine_dependent_reorg (insn)
3430 rtx insn ATTRIBUTE_UNUSED;
3435 /* A C statement (sans semicolon) to update the integer variable COST based on
3436 the relationship between INSN that is dependent on DEP_INSN through the
3437 dependence LINK. The default is to make no adjustment to COST. This can be
3438 used for example to specify to the scheduler that an output- or
3439 anti-dependence does not incur the same cost as a data-dependence. */
3441 /* For the d30v, try to insure that the source operands for a load/store are
3442 set 2 cycles before the memory reference. */
3445 d30v_adjust_cost (insn, link, dep_insn, cost)
3447 rtx link ATTRIBUTE_UNUSED;
3451 rtx set_dep = single_set (dep_insn);
3452 rtx set_insn = single_set (insn);
3454 if (set_dep != NULL_RTX && set_insn != NULL_RTX
3455 && GET_CODE (SET_DEST (set_dep)) == REG)
3457 rtx reg = SET_DEST (set_dep);
3460 if ((GET_CODE (mem = SET_SRC (set_insn)) == MEM
3461 && reg_mentioned_p (reg, XEXP (mem, 0)))
3462 || (GET_CODE (mem = SET_DEST (set_insn)) == MEM
3463 && reg_mentioned_p (reg, XEXP (mem, 0))))
3472 /* Function which returns the number of insns that can be
3473 scheduled in the same machine cycle. This must be constant
3474 over an entire compilation. The default is 1. */
3482 /* Routine to allocate, mark and free a per-function,
3483 machine specific structure. */
3486 d30v_init_machine_status (p)
3490 (machine_function *) xcalloc (1, sizeof (machine_function));
3494 d30v_mark_machine_status (p)
3495 struct function * p;
3497 if (p->machine == NULL)
3500 ggc_mark_rtx (p->machine->eh_epilogue_sp_ofs);
3504 d30v_free_machine_status (p)
3507 struct machine_function *machine = p->machine;
3509 if (machine == NULL)
3516 /* Do anything needed before RTL is emitted for each function. */
3519 d30v_init_expanders ()
3521 /* Arrange to save and restore machine status around nested functions. */
3522 init_machine_status = d30v_init_machine_status;
3523 mark_machine_status = d30v_mark_machine_status;
3524 free_machine_status = d30v_free_machine_status;
3527 /* Find the current function's return address.
3529 ??? It would be better to arrange things such that if we would ordinarily
3530 have been a leaf function and we didn't spill the hard reg that we
3531 wouldn't have to save the register in the prolog. But it's not clear
3532 how to get the right information at the right time. */
3537 return get_hard_reg_initial_val (Pmode, GPR_LINK);
3540 /* Called to register all of our global variables with the garbage
3544 d30v_add_gc_roots ()
3546 ggc_add_rtx_root (&d30v_compare_op0, 1);
3547 ggc_add_rtx_root (&d30v_compare_op1, 1);