1 ;;- Machine description for GNU compiler, Convex Version
2 ;; Copyright (C) 1988, 1994, 1995, 1998, 1999 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;; Attribute specifications
24 (define_attr "cpu" "c1,c32,c34,c38"
25 (const (symbol_ref "(enum attr_cpu) target_cpu")))
27 ;; Instruction classification
30 "alu,xalu,mldw,mldl,mldb,mst,adds,addd,mulw,mull,muls,muld,divw,divl,divs,divd,shfw,shfl,cvts,cvtd"
35 (define_function_unit "mem" 1 0
36 (and (eq_attr "cpu" "c1") (eq_attr "type" "mldw")) 2 0)
37 (define_function_unit "mem" 1 0
38 (and (eq_attr "cpu" "c1") (eq_attr "type" "mldl")) 4 0)
39 (define_function_unit "mem" 1 0
40 (and (eq_attr "cpu" "c32") (eq_attr "type" "mldw,mldl")) 2 0)
41 (define_function_unit "mem" 1 0
42 (and (eq_attr "cpu" "c34") (eq_attr "type" "mldw,mldl")) 4 0)
43 (define_function_unit "mem" 1 0
44 (and (eq_attr "cpu" "c38") (eq_attr "type" "mldw,mldl")) 2 0)
46 (define_function_unit "mem" 1 0
47 (and (eq_attr "cpu" "c32") (eq_attr "type" "mldb")) 9 0)
48 (define_function_unit "mem" 1 0
49 (and (eq_attr "cpu" "c34") (eq_attr "type" "mldb")) 36 0)
50 (define_function_unit "mem" 1 0
51 (and (eq_attr "cpu" "c38") (eq_attr "type" "mldb")) 21 0)
53 (define_function_unit "mem" 1 0
54 (and (eq_attr "cpu" "c1") (eq_attr "type" "xalu")) 1 0)
55 (define_function_unit "mem" 1 0
56 (and (eq_attr "cpu" "c32") (eq_attr "type" "xalu")) 1 0)
57 (define_function_unit "mem" 1 0
58 (and (eq_attr "cpu" "c34") (eq_attr "type" "xalu")) 5 0)
59 (define_function_unit "mem" 1 0
60 (and (eq_attr "cpu" "c38") (eq_attr "type" "xalu")) 2 0)
62 (define_function_unit "add" 1 0
63 (and (eq_attr "cpu" "c1") (eq_attr "type" "adds,addd")) 3 2)
64 (define_function_unit "add" 1 0
65 (and (eq_attr "cpu" "c32") (eq_attr "type" "adds,addd")) 2 1)
66 (define_function_unit "add" 1 0
67 (and (eq_attr "cpu" "c34") (eq_attr "type" "adds,addd")) 5 2)
68 (define_function_unit "add" 1 0
69 (and (eq_attr "cpu" "c38") (eq_attr "type" "adds,addd")) 2 1)
71 (define_function_unit "mul" 1 0
72 (and (eq_attr "cpu" "c1") (eq_attr "type" "mulw,muls")) 3 2)
73 (define_function_unit "mul" 1 0
74 (and (eq_attr "cpu" "c32") (eq_attr "type" "mulw,muls")) 4 2)
75 (define_function_unit "mul" 1 0
76 (and (eq_attr "cpu" "c34") (eq_attr "type" "mulw,muls")) 6 2)
77 (define_function_unit "mul" 1 0
78 (and (eq_attr "cpu" "c38") (eq_attr "type" "mulw,muls")) 3 2)
80 (define_function_unit "mul" 1 0
81 (and (eq_attr "cpu" "c1") (eq_attr "type" "mull,muld")) 4 3)
82 (define_function_unit "mul" 1 0
83 (and (eq_attr "cpu" "c32") (eq_attr "type" "mull")) 10 7)
84 (define_function_unit "mul" 1 0
85 (and (eq_attr "cpu" "c32") (eq_attr "type" "muld")) 5 2)
86 (define_function_unit "mul" 1 0
87 (and (eq_attr "cpu" "c34") (eq_attr "type" "mull,muld")) 7 3)
88 (define_function_unit "mul" 1 0
89 (and (eq_attr "cpu" "c38") (eq_attr "type" "mull,muld")) 4 3)
91 (define_function_unit "div" 1 0
92 (and (eq_attr "cpu" "c1") (eq_attr "type" "divw")) 24 24)
93 (define_function_unit "div" 1 0
94 (and (eq_attr "cpu" "c32") (eq_attr "type" "divw")) 44 6)
95 (define_function_unit "div" 1 0
96 (and (eq_attr "cpu" "c34") (eq_attr "type" "divw")) 14 10)
97 (define_function_unit "div" 1 0
98 (and (eq_attr "cpu" "c38") (eq_attr "type" "divw")) 11 10)
100 (define_function_unit "div" 1 0
101 (and (eq_attr "cpu" "c1") (eq_attr "type" "divl")) 41 42)
102 (define_function_unit "div" 1 0
103 (and (eq_attr "cpu" "c32") (eq_attr "type" "divl")) 76 5)
104 (define_function_unit "div" 1 0
105 (and (eq_attr "cpu" "c34") (eq_attr "type" "divl")) 22 18)
106 (define_function_unit "div" 1 0
107 (and (eq_attr "cpu" "c38") (eq_attr "type" "divl")) 19 18)
109 (define_function_unit "div" 1 0
110 (and (eq_attr "cpu" "c1") (eq_attr "type" "divs")) 22 22)
111 (define_function_unit "div" 1 0
112 (and (eq_attr "cpu" "c32") (eq_attr "type" "divs")) 8 6)
113 (define_function_unit "div" 1 0
114 (and (eq_attr "cpu" "c34") (eq_attr "type" "divs")) 13 9)
115 (define_function_unit "div" 1 0
116 (and (eq_attr "cpu" "c38") (eq_attr "type" "divs")) 10 9)
118 (define_function_unit "div" 1 0
119 (and (eq_attr "cpu" "c1") (eq_attr "type" "divd")) 37 38)
120 (define_function_unit "div" 1 0
121 (and (eq_attr "cpu" "c32") (eq_attr "type" "divd")) 12 8)
122 (define_function_unit "div" 1 0
123 (and (eq_attr "cpu" "c34") (eq_attr "type" "divd")) 20 16)
124 (define_function_unit "div" 1 0
125 (and (eq_attr "cpu" "c38") (eq_attr "type" "divd")) 17 16)
127 (define_function_unit "misc" 1 0
128 (and (eq_attr "cpu" "c1") (eq_attr "type" "cvts,cvtd")) 4 3)
129 (define_function_unit "misc" 1 0
130 (and (eq_attr "cpu" "c32") (eq_attr "type" "cvts")) 9 7)
131 (define_function_unit "misc" 1 0
132 (and (eq_attr "cpu" "c32") (eq_attr "type" "cvtd")) 9 6)
133 (define_function_unit "misc" 1 0
134 (and (eq_attr "cpu" "c34") (eq_attr "type" "cvts")) 6 2)
135 (define_function_unit "misc" 1 0
136 (and (eq_attr "cpu" "c34") (eq_attr "type" "cvtd")) 6 1)
137 (define_function_unit "misc" 1 0
138 (and (eq_attr "cpu" "c38") (eq_attr "type" "cvts,cvtd")) 3 1)
140 (define_function_unit "misc" 1 0
141 (and (eq_attr "cpu" "c1") (eq_attr "type" "shfw,shfl")) 3 2)
142 (define_function_unit "misc" 1 0
143 (and (eq_attr "cpu" "c32") (eq_attr "type" "shfw")) 7 5)
144 (define_function_unit "misc" 1 0
145 (and (eq_attr "cpu" "c32") (eq_attr "type" "shfl")) 7 4)
146 (define_function_unit "misc" 1 0
147 (and (eq_attr "cpu" "c38") (eq_attr "type" "shfw,shfl")) 3 1)
149 (define_function_unit "mystery_latch" 1 1
150 (and (eq_attr "type" "!alu,mldw,mldl,adds,addd") (eq_attr "cpu" "c32")) 2 2)
152 ;(define_function_unit "ip" 1 1
153 ; (and (eq_attr "cpu" "c1")
154 ; (eq_attr "type" "divw,divl,divs,divd,xalu")) 2 2)
155 ;(define_function_unit "ip" 1 1
156 ; (and (eq_attr "cpu" "c1")
157 ; (eq_attr "type" "!divw,divl,divs,divd,xalu")) 1 1)
158 ;(define_function_unit "ip" 1 1
159 ; (and (eq_attr "cpu" "c32")
160 ; (eq_attr "type" "mull,muld,divl,divd,shfl,cvtd,xalu")) 2 2)
161 ;(define_function_unit "ip" 1 1
162 ; (and (eq_attr "cpu" "c32")
163 ; (eq_attr "type" "!mull,muld,divl,divd,shfl,cvtd,xalu")) 1 1)
164 ;(define_function_unit "ip" 1 1
165 ; (and (eq_attr "cpu" "c34")
166 ; (eq_attr "type" "addd,mull,muld,divl,divd,cvtd,xalu")) 2 2)
167 ;(define_function_unit "ip" 1 1
168 ; (and (eq_attr "cpu" "c34")
169 ; (eq_attr "type" "!addd,mull,muld,divl,divd,cvtd,xalu")) 1 1)
171 ;; Make the first thing a real insn in case of genattrtab bug
180 (define_expand "movdf"
181 [(set (match_operand:DF 0 "general_operand" "")
182 (match_operand:DF 1 "general_operand" ""))]
184 "if (GET_CODE (operands[0]) != REG)
185 operands[1] = force_reg (DFmode, operands[1]);")
188 [(set (match_operand:DF 0 "general_operand" "=d,d,d,d,d,<,m")
189 (match_operand:DF 1 "general_operand" "d,Q,m,G,H,d,d"))]
190 "register_operand (operands[0], DFmode)
191 || register_operand (operands[1], DFmode)"
200 [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")])
202 ;; This is here so we can load any result of RTL constant folding
203 ;; but do not use it on constants that can be loaded from memory.
204 ;; It is never better and can be worse.
207 [(set (match_operand:DF 0 "register_operand" "=d")
208 (match_operand:DF 1 "const_double_operand" "F"))]
209 "CONST_DOUBLE_MEM (operands[1]) == const0_rtx"
210 "ld.u %u1,%0\;ld.w %v1,%0"
211 [(set_attr "type" "xalu")])
213 (define_expand "movsf"
214 [(set (match_operand:SF 0 "general_operand" "")
215 (match_operand:SF 1 "general_operand" ""))]
217 "if (GET_CODE (operands[0]) != REG)
218 operands[1] = force_reg (SFmode, operands[1]);")
221 [(set (match_operand:SF 0 "general_operand" "=d,d,d,d,<,m")
222 (match_operand:SF 1 "general_operand" "d,Q,m,F,d,d"))]
223 "register_operand (operands[0], SFmode)
224 || register_operand (operands[1], SFmode)"
232 [(set_attr "type" "alu,mldb,mldw,alu,alu,mst")])
234 (define_expand "movdi"
235 [(set (match_operand:DI 0 "general_operand" "")
236 (match_operand:DI 1 "general_operand" ""))]
238 "if (GET_CODE (operands[0]) != REG)
239 operands[1] = force_reg (DImode, operands[1]);")
242 [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,d,<,m")
243 (match_operand:DI 1 "general_operand" "d,Q,m,G,HI,d,d"))]
244 "register_operand (operands[0], DImode)
245 || register_operand (operands[1], DImode)"
254 [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")])
256 ;; This is here so we can load any result of RTL constant folding
257 ;; but do not use it on constants that can be loaded from memory.
258 ;; It is never better and can be worse.
261 [(set (match_operand:DI 0 "register_operand" "=d")
262 (match_operand:DI 1 "const_double_operand" "F"))]
263 "CONST_DOUBLE_MEM (operands[1]) == const0_rtx"
264 "ld.u %u1,%0\;ld.w %v1,%0"
265 [(set_attr "type" "xalu")])
267 (define_expand "movsi"
268 [(set (match_operand:SI 0 "general_operand" "")
269 (match_operand:SI 1 "general_operand" ""))]
271 "if (GET_CODE (operands[0]) != REG)
272 operands[1] = force_reg (SImode, operands[1]);")
275 [(set (match_operand:SI 0 "push_operand" "=<,<")
276 (match_operand:SI 1 "nonmemory_operand" "Ad,i"))]
283 [(set (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m")
284 (match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))]
285 "register_operand (operands[0], SImode)
286 || register_operand (operands[1], SImode)"
294 [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")])
296 (define_expand "movstrictsi"
297 [(set (strict_low_part (match_operand:SI 0 "general_operand" ""))
298 (match_operand:SI 1 "general_operand" ""))]
300 "if (GET_CODE (operands[0]) != REG)
301 operands[1] = force_reg (SImode, operands[1]);")
304 [(set (strict_low_part (match_operand:SI 0 "general_operand" "+d,r,d,r,r,m"))
305 (match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))]
306 "register_operand (operands[0], SImode)
307 || register_operand (operands[1], SImode)"
315 [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")])
317 (define_expand "movhi"
318 [(set (match_operand:HI 0 "general_operand" "")
319 (match_operand:HI 1 "general_operand" ""))]
321 "if (GET_CODE (operands[0]) != REG)
322 operands[1] = force_reg (HImode, operands[1]);")
325 [(set (match_operand:HI 0 "general_operand" "=d,r,d,r,r,<,m")
326 (match_operand:HI 1 "general_operand" "d,r,Q,m,i,Ad,r"))]
327 "register_operand (operands[0], HImode)
328 || register_operand (operands[1], HImode)"
337 [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")])
339 (define_expand "movqi"
340 [(set (match_operand:QI 0 "general_operand" "")
341 (match_operand:QI 1 "general_operand" ""))]
343 "if (GET_CODE (operands[0]) != REG)
344 operands[1] = force_reg (QImode, operands[1]);")
347 [(set (match_operand:QI 0 "general_operand" "=d,r,d,r,r,<,m")
348 (match_operand:QI 1 "general_operand" "d,r,Q,m,i,Ad,r"))]
349 "register_operand (operands[0], QImode)
350 || register_operand (operands[1], QImode)"
359 [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")])
361 ;; Expand block moves manually to get code that pipelines the loads.
363 (define_expand "movstrsi"
364 [(set (match_operand:BLK 0 "memory_operand" "=m")
365 (match_operand:BLK 1 "memory_operand" "m"))
366 (use (match_operand:SI 2 "const_int_operand" "i"))
367 (use (match_operand:SI 3 "const_int_operand" "i"))]
369 " expand_movstr (operands); DONE; ")
371 ;; Extension and truncation insns.
372 ;; Those for integer source operand
373 ;; are ordered widest source type first.
375 (define_insn "truncsiqi2"
376 [(set (match_operand:QI 0 "register_operand" "=d,a")
377 (truncate:QI (match_operand:SI 1 "register_operand" "d,a")))]
381 (define_insn "truncsihi2"
382 [(set (match_operand:HI 0 "register_operand" "=d,a")
383 (truncate:HI (match_operand:SI 1 "register_operand" "d,a")))]
387 (define_insn "trunchiqi2"
388 [(set (match_operand:QI 0 "register_operand" "=r")
389 (truncate:QI (match_operand:HI 1 "register_operand" "0")))]
393 (define_insn "truncdisi2"
394 [(set (match_operand:SI 0 "register_operand" "=d")
395 (truncate:SI (match_operand:DI 1 "register_operand" "d")))]
399 (define_insn "extendsidi2"
400 [(set (match_operand:DI 0 "register_operand" "=d")
401 (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
405 (define_insn "extendhisi2"
406 [(set (match_operand:SI 0 "register_operand" "=d,a")
407 (sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))]
411 (define_insn "extendqihi2"
412 [(set (match_operand:HI 0 "register_operand" "=d,a")
413 (sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))]
417 (define_insn "extendqisi2"
418 [(set (match_operand:SI 0 "register_operand" "=d,a")
419 (sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))]
423 (define_insn "extendsfdf2"
424 [(set (match_operand:DF 0 "register_operand" "=d")
425 (float_extend:DF (match_operand:SF 1 "register_operand" "d")))]
428 [(set_attr "type" "cvts")])
430 (define_insn "truncdfsf2"
431 [(set (match_operand:SF 0 "register_operand" "=d")
432 (float_truncate:SF (match_operand:DF 1 "register_operand" "d")))]
435 [(set_attr "type" "cvtd")])
437 (define_insn "zero_extendhisi2"
438 [(set (match_operand:SI 0 "register_operand" "=r")
439 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
443 (define_insn "zero_extendqihi2"
444 [(set (match_operand:HI 0 "register_operand" "=r")
445 (zero_extend:HI (match_operand:QI 1 "register_operand" "0")))]
449 (define_insn "zero_extendqisi2"
450 [(set (match_operand:SI 0 "register_operand" "=r")
451 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
455 (define_insn "zero_extendsidi2"
456 [(set (match_operand:DI 0 "register_operand" "=d")
457 (zero_extend:DI (match_operand:SI 1 "register_operand" "0")))]
461 ;; Fix-to-float conversion insns.
462 ;; Note that the ones that start with SImode come first.
463 ;; That is so that an operand that is a CONST_INT
464 ;; (and therefore lacks a specific machine mode).
465 ;; will be recognized as SImode (which is always valid)
466 ;; rather than as QImode or HImode.
468 (define_insn "floatsisf2"
469 [(set (match_operand:SF 0 "register_operand" "=d")
470 (float:SF (match_operand:SI 1 "register_operand" "d")))]
473 [(set_attr "type" "cvts")])
475 (define_insn "floatdisf2"
476 [(set (match_operand:SF 0 "register_operand" "=d")
477 (float:SF (match_operand:DI 1 "register_operand" "d")))]
480 [(set_attr "type" "cvtd")])
482 (define_insn "floatsidf2"
483 [(set (match_operand:DF 0 "register_operand" "=d")
484 (float:DF (match_operand:SI 1 "register_operand" "d")))]
487 [(set_attr "type" "cvts")])
489 (define_insn "floatdidf2"
490 [(set (match_operand:DF 0 "register_operand" "=d")
491 (float:DF (match_operand:DI 1 "register_operand" "d")))]
494 [(set_attr "type" "cvtd")])
496 ;; These are a little slower than gcc's normal way of doing unsigned
497 ;; DI floats (if the DI number is "negative") but they avoid double
498 ;; rounding and they avoid explicit constants.
500 (define_expand "floatunsdidf2"
501 [(set (match_operand:DF 0 "register_operand" "=d")
502 (float:DF (match_operand:DI 1 "register_operand" "d")))
503 (set (cc0) (compare:DI (match_dup 3) (match_dup 1)))
505 (if_then_else (le (cc0) (const_int 0))
506 (label_ref (match_dup 4))
508 (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1)))
509 (set (match_dup 0) (float:DF (match_dup 2)))
510 (set (match_dup 0) (plus:DF (match_dup 0) (match_dup 0)))
512 (set (match_dup 0) (match_dup 0))]
516 operands[2] = gen_reg_rtx (DImode);
517 operands[3] = force_reg (DImode, const0_rtx);
518 operands[4] = gen_label_rtx ();
521 (define_expand "floatunsdisf2"
522 [(set (match_operand:SF 0 "register_operand" "=d")
523 (float:SF (match_operand:DI 1 "register_operand" "d")))
524 (set (cc0) (compare:DI (match_dup 3) (match_dup 1)))
526 (if_then_else (le (cc0) (const_int 0))
527 (label_ref (match_dup 4))
529 (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1)))
530 (set (match_dup 0) (float:SF (match_dup 2)))
531 (set (match_dup 0) (plus:SF (match_dup 0) (match_dup 0)))
533 (set (match_dup 0) (match_dup 0))]
537 operands[2] = gen_reg_rtx (DImode);
538 operands[3] = force_reg (DImode, const0_rtx);
539 operands[4] = gen_label_rtx ();
542 ;; These patterns are identical to gcc's default action
543 ;; if DI->DF and DI->SF are not present. There are here
544 ;; only to prevent SI->*F from promoting to DI->*F.
546 (define_expand "floatunssidf2"
548 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
549 (set (match_operand:DF 0 "register_operand" "")
550 (float:DF (match_dup 2)))]
552 "operands[2] = gen_reg_rtx (DImode);")
554 (define_expand "floatunssisf2"
556 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
557 (set (match_operand:SF 0 "register_operand" "")
558 (float:SF (match_dup 2)))]
560 "operands[2] = gen_reg_rtx (DImode);")
562 ;; Float-to-fix conversion insns.
564 (define_insn "fix_truncsfsi2"
565 [(set (match_operand:SI 0 "register_operand" "=d")
566 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
569 [(set_attr "type" "cvts")])
571 (define_insn "fix_truncsfdi2"
572 [(set (match_operand:DI 0 "register_operand" "=d")
573 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
576 [(set_attr "type" "cvts")])
578 (define_insn "fix_truncdfsi2"
579 [(set (match_operand:SI 0 "register_operand" "=d")
580 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
583 [(set_attr "type" "cvtd")])
585 (define_insn "fix_truncdfdi2"
586 [(set (match_operand:DI 0 "register_operand" "=d")
587 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
590 [(set_attr "type" "cvtd")])
592 ;;- All kinds of add instructions.
594 (define_insn "adddf3"
595 [(set (match_operand:DF 0 "register_operand" "=d")
596 (plus:DF (match_operand:DF 1 "register_operand" "%0")
597 (match_operand:DF 2 "register_operand" "d")))]
600 [(set_attr "type" "addd")])
602 (define_insn "addsf3"
603 [(set (match_operand:SF 0 "register_operand" "=d")
604 (plus:SF (match_operand:SF 1 "register_operand" "%0")
605 (match_operand:SF 2 "nonmemory_operand" "dF")))]
608 [(set_attr "type" "adds")])
610 (define_insn "adddi3"
611 [(set (match_operand:DI 0 "register_operand" "=d")
612 (plus:DI (match_operand:DI 1 "register_operand" "%0")
613 (match_operand:DI 2 "register_operand" "d")))]
617 (define_expand "addsi3"
618 [(set (match_operand:SI 0 "register_operand" "")
619 (plus:SI (match_operand:SI 1 "register_operand" "")
620 (match_operand:SI 2 "nonmemory_operand" "")))]
625 [(set (match_operand:SI 0 "register_operand" "=a")
626 (plus:SI (match_operand:SI 1 "register_operand" "%A")
627 (match_operand:SI 2 "immediate_operand" "i")))]
628 "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx"
632 [(set (match_operand:SI 0 "register_operand" "=a")
633 (plus:SI (match_operand:SI 1 "register_operand" "%a")
634 (match_operand:SI 2 "nonmemory_operand" "ri")))]
635 "operands[1] == stack_pointer_rtx && operands[0] != stack_pointer_rtx"
636 "mov %1,%0\;add.w %2,%0")
639 [(set (match_operand:SI 0 "push_operand" "=<")
640 (plus:SI (match_operand:SI 1 "register_operand" "A")
641 (match_operand:SI 2 "immediate_operand" "i")))]
642 "operands[1] != stack_pointer_rtx"
644 [(set_attr "type" "mst")])
647 [(set (match_operand:SI 0 "register_operand" "=d,a,a")
648 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,A")
649 (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]
657 [(set (match_operand:SI 0 "register_operand" "=d,a,r")
658 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,A")
659 (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]
666 (define_insn "addhi3"
667 [(set (match_operand:HI 0 "register_operand" "=d,a")
668 (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
669 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
673 (define_insn "addqi3"
674 [(set (match_operand:QI 0 "register_operand" "=d,d")
675 (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
676 (match_operand:QI 2 "nonmemory_operand" "d,i")))]
682 ;;- All kinds of subtract instructions.
684 (define_insn "subdf3"
685 [(set (match_operand:DF 0 "register_operand" "=d")
686 (minus:DF (match_operand:DF 1 "register_operand" "0")
687 (match_operand:DF 2 "register_operand" "d")))]
690 [(set_attr "type" "addd")])
692 (define_insn "subsf3"
693 [(set (match_operand:SF 0 "register_operand" "=d")
694 (minus:SF (match_operand:SF 1 "register_operand" "0")
695 (match_operand:SF 2 "nonmemory_operand" "dF")))]
698 [(set_attr "type" "adds")])
700 (define_insn "subdi3"
701 [(set (match_operand:DI 0 "register_operand" "=d")
702 (minus:DI (match_operand:DI 1 "register_operand" "0")
703 (match_operand:DI 2 "register_operand" "d")))]
707 (define_insn "subsi3"
708 [(set (match_operand:SI 0 "register_operand" "=d,a,?d,?a")
709 (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,0,di,ai")
710 (match_operand:SI 2 "nonmemory_operand" "di,ai,0,0")))]
715 sub.w %1,%0\;neg.w %0,%0
716 sub.w %1,%0\;neg.w %0,%0")
718 (define_insn "subhi3"
719 [(set (match_operand:HI 0 "register_operand" "=d,a")
720 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
721 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
725 (define_insn "subqi3"
726 [(set (match_operand:QI 0 "register_operand" "=d,d")
727 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
728 (match_operand:QI 2 "nonmemory_operand" "d,i")))]
734 ;;- Multiply instructions.
736 (define_insn "muldf3"
737 [(set (match_operand:DF 0 "register_operand" "=d")
738 (mult:DF (match_operand:DF 1 "register_operand" "%0")
739 (match_operand:DF 2 "register_operand" "d")))]
742 [(set_attr "type" "muld")])
744 (define_insn "mulsf3"
745 [(set (match_operand:SF 0 "register_operand" "=d")
746 (mult:SF (match_operand:SF 1 "register_operand" "%0")
747 (match_operand:SF 2 "nonmemory_operand" "dF")))]
750 [(set_attr "type" "muls")])
752 (define_insn "muldi3"
753 [(set (match_operand:DI 0 "register_operand" "=d")
754 (mult:DI (match_operand:DI 1 "register_operand" "%0")
755 (match_operand:DI 2 "register_operand" "d")))]
758 [(set_attr "type" "mull")])
760 (define_insn "mulsi3"
761 [(set (match_operand:SI 0 "register_operand" "=d,a")
762 (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
763 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
766 [(set_attr "type" "mulw")])
768 (define_insn "mulhi3"
769 [(set (match_operand:HI 0 "register_operand" "=d,a")
770 (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
771 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
774 [(set_attr "type" "mulw")])
776 (define_insn "mulqi3"
777 [(set (match_operand:QI 0 "register_operand" "=d,d")
778 (mult:QI (match_operand:QI 1 "register_operand" "%0,0")
779 (match_operand:QI 2 "nonmemory_operand" "d,i")))]
784 [(set_attr "type" "mulw,mulw")])
786 ;;- Divide instructions.
788 (define_insn "divdf3"
789 [(set (match_operand:DF 0 "register_operand" "=d")
790 (div:DF (match_operand:DF 1 "register_operand" "0")
791 (match_operand:DF 2 "register_operand" "d")))]
794 [(set_attr "type" "divd")])
796 (define_insn "divsf3"
797 [(set (match_operand:SF 0 "register_operand" "=d")
798 (div:SF (match_operand:SF 1 "register_operand" "0")
799 (match_operand:SF 2 "nonmemory_operand" "dF")))]
802 [(set_attr "type" "divs")])
804 (define_insn "divdi3"
805 [(set (match_operand:DI 0 "register_operand" "=d")
806 (div:DI (match_operand:DI 1 "register_operand" "0")
807 (match_operand:DI 2 "register_operand" "d")))]
810 [(set_attr "type" "divl")])
812 (define_expand "udivsi3"
814 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
816 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
818 (div:DI (match_dup 3) (match_dup 4)))
819 (set (match_operand:SI 0 "register_operand" "")
820 (subreg:SI (match_dup 3) 0))]
822 "operands[3] = gen_reg_rtx (DImode);
823 operands[4] = gen_reg_rtx (DImode); ")
825 (define_insn "udivdi3"
826 [(set (match_operand:DI 0 "register_operand" "=d")
827 (udiv:DI (match_operand:DI 1 "register_operand" "d")
828 (match_operand:DI 2 "register_operand" "d")))]
830 "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp")
832 (define_insn "divsi3"
833 [(set (match_operand:SI 0 "register_operand" "=d,a")
834 (div:SI (match_operand:SI 1 "register_operand" "0,0")
835 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
838 [(set_attr "type" "divw")])
840 (define_insn "divhi3"
841 [(set (match_operand:HI 0 "register_operand" "=d,a")
842 (div:HI (match_operand:HI 1 "register_operand" "0,0")
843 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
846 [(set_attr "type" "divw")])
848 (define_insn "divqi3"
849 [(set (match_operand:QI 0 "register_operand" "=d")
850 (div:QI (match_operand:QI 1 "register_operand" "0")
851 (match_operand:QI 2 "register_operand" "d")))]
854 [(set_attr "type" "divw")])
856 ;;- Bit clear instructions.
859 [(set (match_operand:DI 0 "register_operand" "=d")
860 (and:DI (match_operand:DI 1 "register_operand" "%0")
861 (match_operand:DI 2 "" "")))]
862 "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
863 || (GET_CODE (operands[2]) == CONST_DOUBLE
864 && CONST_DOUBLE_HIGH (operands[2]) == -1)"
867 (define_insn "anddi3"
868 [(set (match_operand:DI 0 "register_operand" "=d")
869 (and:DI (match_operand:DI 1 "register_operand" "%0")
870 (match_operand:DI 2 "register_operand" "d")))]
874 (define_insn "andsi3"
875 [(set (match_operand:SI 0 "register_operand" "=d,a")
876 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
877 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
881 (define_insn "andhi3"
882 [(set (match_operand:HI 0 "register_operand" "=d,a")
883 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
884 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
888 (define_insn "andqi3"
889 [(set (match_operand:QI 0 "register_operand" "=d,a")
890 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
891 (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
895 ;;- Bit set instructions.
898 [(set (match_operand:DI 0 "register_operand" "=d")
899 (ior:DI (match_operand:DI 1 "register_operand" "%0")
900 (match_operand:DI 2 "" "")))]
901 "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
902 || (GET_CODE (operands[2]) == CONST_DOUBLE
903 && CONST_DOUBLE_HIGH (operands[2]) == 0)"
906 (define_insn "iordi3"
907 [(set (match_operand:DI 0 "register_operand" "=d")
908 (ior:DI (match_operand:DI 1 "register_operand" "%0")
909 (match_operand:DI 2 "register_operand" "d")))]
913 (define_insn "iorsi3"
914 [(set (match_operand:SI 0 "register_operand" "=d,a")
915 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
916 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
920 (define_insn "iorhi3"
921 [(set (match_operand:HI 0 "register_operand" "=d,a")
922 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
923 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
927 (define_insn "iorqi3"
928 [(set (match_operand:QI 0 "register_operand" "=d,a")
929 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
930 (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
934 ;;- xor instructions.
937 [(set (match_operand:DI 0 "register_operand" "=d")
938 (xor:DI (match_operand:DI 1 "register_operand" "%0")
939 (match_operand:DI 2 "" "")))]
940 "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
941 || (GET_CODE (operands[2]) == CONST_DOUBLE
942 && CONST_DOUBLE_HIGH (operands[2]) == 0)"
945 (define_insn "xordi3"
946 [(set (match_operand:DI 0 "register_operand" "=d")
947 (xor:DI (match_operand:DI 1 "register_operand" "%0")
948 (match_operand:DI 2 "register_operand" "d")))]
952 (define_insn "xorsi3"
953 [(set (match_operand:SI 0 "register_operand" "=d,a")
954 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
955 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
959 (define_insn "xorhi3"
960 [(set (match_operand:HI 0 "register_operand" "=d,a")
961 (xor:HI (match_operand:HI 1 "register_operand" "%0,0")
962 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
966 (define_insn "xorqi3"
967 [(set (match_operand:QI 0 "register_operand" "=d,a")
968 (xor:QI (match_operand:QI 1 "register_operand" "%0,0")
969 (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
973 (define_insn "negdf2"
974 [(set (match_operand:DF 0 "register_operand" "=d")
975 (neg:DF (match_operand:DF 1 "register_operand" "d")))]
978 [(set_attr "type" "addd")])
980 (define_insn "negsf2"
981 [(set (match_operand:SF 0 "register_operand" "=d")
982 (neg:SF (match_operand:SF 1 "register_operand" "d")))]
985 [(set_attr "type" "adds")])
987 (define_insn "negdi2"
988 [(set (match_operand:DI 0 "register_operand" "=d")
989 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
993 (define_insn "negsi2"
994 [(set (match_operand:SI 0 "register_operand" "=d,a")
995 (neg:SI (match_operand:SI 1 "register_operand" "d,a")))]
999 (define_insn "neghi2"
1000 [(set (match_operand:HI 0 "register_operand" "=d,a")
1001 (neg:HI (match_operand:HI 1 "register_operand" "d,a")))]
1005 (define_insn "negqi2"
1006 [(set (match_operand:QI 0 "register_operand" "=d")
1007 (neg:QI (match_operand:QI 1 "register_operand" "d")))]
1011 (define_insn "one_cmpldi2"
1012 [(set (match_operand:DI 0 "register_operand" "=d")
1013 (not:DI (match_operand:DI 1 "register_operand" "d")))]
1017 (define_insn "one_cmplsi2"
1018 [(set (match_operand:SI 0 "register_operand" "=d,a")
1019 (not:SI (match_operand:SI 1 "register_operand" "d,a")))]
1023 (define_insn "one_cmplhi2"
1024 [(set (match_operand:HI 0 "register_operand" "=d,a")
1025 (not:HI (match_operand:HI 1 "register_operand" "d,a")))]
1029 (define_insn "one_cmplqi2"
1030 [(set (match_operand:QI 0 "register_operand" "=d,a")
1031 (not:QI (match_operand:QI 1 "register_operand" "d,a")))]
1037 ;; The extreme profusion of patterns here is due to the different-speed
1038 ;; shifts on different machines, and the C1's lack of word shift S-register
1043 ;; Arithmetic left 1, 1 cycle on all machines via add
1046 [(set (match_operand:SI 0 "register_operand" "=r")
1047 (ashift:SI (match_operand:SI 1 "register_operand" "0")
1052 ;; C34 general shift is 1 cycle
1055 [(set (match_operand:SI 0 "register_operand" "=d,a")
1056 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
1057 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
1062 [(set_attr "type" "shfw,shfw")])
1064 ;; else shift left 0..7 is 1 cycle if we use an A register
1067 [(set (match_operand:SI 0 "register_operand" "=a,?d")
1068 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
1069 (match_operand:SI 2 "immediate_operand" "ai,di")))]
1070 "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8"
1074 [(set_attr "type" "alu,shfl")])
1077 [(set (match_operand:SI 0 "register_operand" "=a,?d")
1078 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
1079 (match_operand:SI 2 "immediate_operand" "ai,di")))]
1080 "INTVAL (operands[2]) < (unsigned) 8"
1084 [(set_attr "type" "alu,shfw")])
1086 ;; else general left shift
1089 [(set (match_operand:SI 0 "register_operand" "=d,a")
1090 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
1091 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
1096 [(set_attr "type" "shfl,shfw")])
1098 ;; but C2 left shift by a constant is faster via multiply
1101 [(set (match_operand:SI 0 "register_operand" "=r")
1102 (ashift:SI (match_operand:SI 1 "register_operand" "0")
1103 (match_operand:SI 2 "const_int_operand" "i")))]
1104 "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32"
1106 [(set_attr "type" "mulw")])
1108 (define_insn "ashlsi3"
1109 [(set (match_operand:SI 0 "register_operand" "=d,a")
1110 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
1111 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
1116 [(set_attr "type" "shfw,shfw")])
1118 ;; Logical right, general
1119 ;; The hardware wants the negative of the shift count
1121 (define_expand "lshrsi3"
1122 [(set (match_operand:SI 0 "register_operand" "")
1123 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1124 (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
1126 "operands[2] = negate_rtx (SImode, operands[2]);")
1128 ;; C1 lacks word shift S reg
1132 (match_operand:SI 0 "register_operand" "=a,?d")
1133 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
1134 (neg:SI (match_operand:SI 2 "nonmemory_operand" "ai,di"))))]
1138 ld.u #0,%0\;shf %2,%0"
1139 [(set_attr "type" "shfw,shfl")])
1145 (match_operand:SI 0 "register_operand" "=d,a")
1146 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
1147 (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))]
1152 [(set_attr "type" "shfw,shfw")])
1154 ;; Patterns without neg produced by constant folding
1158 (match_operand:SI 0 "register_operand" "=a,?d")
1159 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
1160 (match_operand:SI 2 "immediate_operand" "i,i")))]
1164 ld.u #0,%0\;shf #%n2,%0"
1165 [(set_attr "type" "shfw,shfl")])
1169 (match_operand:SI 0 "register_operand" "=d,a")
1170 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
1171 (match_operand:SI 2 "immediate_operand" "i,i")))]
1176 [(set_attr "type" "shfw,shfw")])
1178 ;; Arithmetic right, general
1179 ;; Sign-extend to 64 bits, then shift that. Works for 0..32.
1181 (define_expand "ashrsi3"
1182 [(set (match_operand:SI 0 "register_operand" "")
1183 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1184 (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
1186 "operands[2] = negate_rtx (SImode, operands[2]);")
1189 [(set (match_operand:SI 0 "register_operand" "=d,&d")
1190 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
1192 (match_operand:SI 2 "nonmemory_operand" "di,di"))))]
1194 "cvtw.l %1,%0\;shf %2,%0"
1195 [(set_attr "type" "shfl,shfl")])
1198 [(set (match_operand:SI 0 "register_operand" "=d")
1199 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
1200 (match_operand:SI 2 "immediate_operand" "i")))]
1202 "cvtw.l %1,%0\;shf #%n2,%0"
1203 [(set_attr "type" "shfl")])
1206 ;; Arithmetic left, 1-cycle
1209 [(set (match_operand:DI 0 "register_operand" "=d")
1210 (ashift:DI (match_operand:DI 1 "register_operand" "0")
1215 ;; Arithmetic left, general
1217 (define_insn "ashldi3"
1218 [(set (match_operand:DI 0 "register_operand" "=d")
1219 (ashift:DI (match_operand:DI 1 "register_operand" "0")
1220 (match_operand:SI 2 "nonmemory_operand" "di")))]
1223 [(set_attr "type" "shfl")])
1225 ;; Can omit zero- or sign-extend if shift is 32 or more.
1228 [(set (match_operand:DI 0 "register_operand" "=d")
1229 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
1230 (match_operand:SI 2 "const_int_operand" "i")))]
1231 "INTVAL (operands[2]) >= 32"
1233 [(set_attr "type" "shfl")])
1236 [(set (match_operand:DI 0 "register_operand" "=d")
1237 (ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
1238 (match_operand:SI 2 "const_int_operand" "i")))]
1239 "INTVAL (operands[2]) >= 32"
1241 [(set_attr "type" "shfl")])
1243 ;; Logical right, general
1245 (define_expand "lshrdi3"
1246 [(set (match_operand:DI 0 "register_operand" "")
1247 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1248 (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
1250 "operands[2] = negate_rtx (SImode, operands[2]);")
1253 [(set (match_operand:DI 0 "register_operand" "=d")
1254 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
1255 (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
1258 [(set_attr "type" "shfl")])
1261 [(set (match_operand:DI 0 "register_operand" "=d")
1262 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
1263 (match_operand:SI 2 "immediate_operand" "i")))]
1266 [(set_attr "type" "shfl")])
1268 ;; Arithmetic right, general
1270 ;; ((a >> b) ^ signbit) - signbit
1271 ;; where signbit is (1 << 63) >> b
1272 ;; Works for 0..63. Does not work for 64; unfortunate but valid.
1274 (define_expand "ashrdi3"
1275 [(set (match_operand:DI 0 "register_operand" "")
1276 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1277 (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))
1278 (set (match_dup 3) (lshiftrt:DI (match_dup 3) (neg:SI (match_dup 2))))
1279 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 3)))
1280 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
1284 if (GET_CODE (operands[2]) == CONST_INT)
1285 switch (INTVAL (operands[2]))
1288 emit_insn (gen_ashrdi3_32 (operands[0], operands[1]));
1292 operands[2] = negate_rtx (SImode, operands[2]);
1293 operands[3] = force_reg (DImode, immed_double_const (0, 1 << 31, DImode));
1296 ;; Arithmetic right 32, a common case that can save a couple of insns.
1298 (define_expand "ashrdi3_32"
1299 [(set (match_operand:DI 0 "register_operand" "")
1300 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1303 (sign_extend:DI (subreg:SI (match_dup 0) 0)))]
1307 ;; __builtin instructions
1309 (define_insn "sqrtdf2"
1310 [(set (match_operand:DF 0 "register_operand" "=d")
1311 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
1312 "! TARGET_C1 && flag_unsafe_math_optimizations"
1314 [(set_attr "type" "divd")])
1316 (define_insn "sqrtsf2"
1317 [(set (match_operand:SF 0 "register_operand" "=d")
1318 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
1319 "! TARGET_C1 && flag_unsafe_math_optimizations"
1321 [(set_attr "type" "divs")])
1323 (define_insn "sindf2"
1324 [(set (match_operand:DF 0 "register_operand" "=d")
1325 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
1326 "! TARGET_C1 && flag_unsafe_math_optimizations"
1329 (define_insn "sinsf2"
1330 [(set (match_operand:SF 0 "register_operand" "=d")
1331 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
1332 "! TARGET_C1 && flag_unsafe_math_optimizations"
1335 (define_insn "cosdf2"
1336 [(set (match_operand:DF 0 "register_operand" "=d")
1337 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
1338 "! TARGET_C1 && flag_unsafe_math_optimizations"
1341 (define_insn "cossf2"
1342 [(set (match_operand:SF 0 "register_operand" "=d")
1343 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
1344 "! TARGET_C1 && flag_unsafe_math_optimizations"
1347 (define_insn "ftruncdf2"
1348 [(set (match_operand:DF 0 "register_operand" "=d")
1349 (fix:DF (match_operand:DF 1 "register_operand" "d")))]
1352 [(set_attr "type" "cvtd")])
1354 (define_insn "ftruncsf2"
1355 [(set (match_operand:SF 0 "register_operand" "=d")
1356 (fix:SF (match_operand:SF 1 "register_operand" "d")))]
1359 [(set_attr "type" "cvts")])
1362 [(set (match_operand:SI 0 "register_operand" "=d")
1363 (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
1366 "tzc %1,%0\;le.w #32,%0\;jbrs.f L0%=\;ld.w #-1,%0\\nL0%=:")
1368 (define_expand "ffssi2"
1369 [(set (match_operand:SI 0 "register_operand" "=d")
1370 (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
1373 (plus:SI (match_dup 0)
1378 (define_insn "abssf2"
1379 [(set (match_operand:SF 0 "register_operand" "=d")
1380 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1382 "and #0x7fffffff,%0")
1384 (define_expand "absdf2"
1385 [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0)
1386 (and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0)
1389 "operands[2] = force_reg (DImode,
1390 immed_double_const (-1, 0x7fffffff, DImode));")
1394 (define_insn "cmpdi"
1396 (compare (match_operand:DI 0 "register_operand" "d")
1397 (match_operand:DI 1 "register_operand" "d")))]
1399 "* return output_cmp (operands[0], operands[1], 'l');")
1402 [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
1403 (clobber (match_scratch:DI 1 "=d"))]
1404 "next_insn_tests_no_inequality (insn)"
1405 "* return output_cmp (operands[0], operands[1], 'L');")
1407 (define_insn "cmpsi"
1409 (compare (match_operand:SI 0 "register_operand" "d,a")
1410 (match_operand:SI 1 "nonmemory_operand" "di,ai")))]
1412 "* return output_cmp (operands[0], operands[1], 'w');")
1414 (define_insn "cmphi"
1416 (compare (match_operand:HI 0 "register_operand" "d,a")
1417 (match_operand:HI 1 "nonmemory_operand" "di,ai")))]
1419 "* return output_cmp (operands[0], operands[1], 'h');")
1421 ; cmpqi is intentionally omitted.
1423 ; gcc will sign-extend or zero-extend the operands to the next
1424 ; wider mode, HImode.
1426 ; For reg .cmp. constant, we just go with the halfword immediate
1427 ; instruction. Perhaps the widening insn can be cse'd or combined away.
1428 ; If not, we're still as good as loading a byte constant into a register
1429 ; to do a reg-reg byte compare.
1431 ; The following patterns pick up cases that can use reg .cmp. reg after all.
1436 (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
1437 (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))))]
1439 "* return output_cmp (operands[0], operands[1], 'b');")
1444 (ashift:HI (subreg:HI (match_operand:QI 0 "register_operand" "d") 0)
1446 (ashift:HI (subreg:HI (match_operand:QI 1 "register_operand" "d") 0)
1449 "* return output_cmp (operands[0], operands[1], 'b');")
1453 (compare (match_operand:QI 0 "register_operand" "d")
1454 (match_operand:QI 1 "register_operand" "d")))]
1456 "* return output_cmp (operands[0], operands[1], 'b');")
1459 [(set (cc0) (match_operand:QI 0 "register_operand" "d"))
1460 (clobber (match_scratch:QI 1 "=d"))]
1461 "next_insn_tests_no_inequality (insn)"
1462 "* return output_cmp (operands[0], operands[1], 'B');")
1465 [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d") 0))
1466 (clobber (match_scratch:QI 1 "=d"))]
1467 "next_insn_tests_no_inequality (insn)"
1468 "* return output_cmp (operands[0], operands[1], 'B');")
1472 (zero_extend (subreg (match_operand:QI 0 "register_operand" "d") 0)))
1473 (clobber (match_scratch:QI 1 "=d"))]
1474 "next_insn_tests_no_inequality (insn)"
1475 "* return output_cmp (operands[0], operands[1], 'B');")
1477 (define_insn "cmpdf"
1479 (compare (match_operand:DF 0 "register_operand" "d")
1480 (match_operand:DF 1 "register_operand" "d")))]
1482 "* return output_cmp (operands[0], operands[1], 'd');")
1484 (define_insn "cmpsf"
1486 (compare (match_operand:SF 0 "register_operand" "d")
1487 (match_operand:SF 1 "nonmemory_cmpsf_operand" "dF")))]
1489 "* return output_cmp (operands[0], operands[1], 's');")
1491 ;; decrement-and-set-cc0 insns.
1493 ;; The most important case where we can use the carry bit from an
1494 ;; arithmetic insn to eliminate a redundant compare is the decrement in
1495 ;; constructs like while (n--) and while (--n >= 0).
1497 ;; We do it with combine patterns instead of NOTICE_UPDATE_CC because
1498 ;; the decrement needs to be kept at the end of the block during scheduling.
1500 ;; These patterns must have memory alternatives because reload refuses
1501 ;; to do output reloads for an insn that sets cc0 (since it does not
1502 ;; want to clobber cc0 with its moves). Convex moves do not clobber
1503 ;; cc0, but there is no evident way to get reload to know that.
1507 (match_operand:SI 0 "register_operand" "+r,*m"))
1509 (plus:SI (match_dup 0)
1511 "next_insn_tests_no_inequality (insn)"
1514 if (which_alternative == 0)
1516 output_cmp (operands[0], constm1_rtx, 'W');
1517 return \"add.w #-1,%0\";
1521 output_cmp (gen_rtx_REG (SImode, 7), constm1_rtx, 'W');
1522 return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\";
1528 (plus:SI (match_operand:SI 0 "register_operand" "+r,*m")
1531 (plus:SI (match_dup 0)
1533 "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)"
1536 if (which_alternative == 0)
1538 output_cmp (operands[0], const0_rtx, 'W');
1539 return \"add.w #-1,%0\";
1543 output_cmp (gen_rtx_REG (SImode, 7), const0_rtx, 'W');
1544 return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\";
1550 (match_operand:HI 0 "register_operand" "+r,*m"))
1552 (plus:HI (match_dup 0)
1554 "next_insn_tests_no_inequality (insn)"
1557 if (which_alternative == 0)
1559 output_cmp (operands[0], constm1_rtx, 'H');
1560 return \"add.h #-1,%0\";
1564 output_cmp (gen_rtx_REG (HImode, 7), constm1_rtx, 'H');
1565 return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
1571 (plus:HI (match_operand:HI 0 "register_operand" "+r,*m")
1574 (plus:HI (match_dup 0)
1576 "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)"
1579 if (which_alternative == 0)
1581 output_cmp (operands[0], const0_rtx, 'H');
1582 return \"add.h #-1,%0\";
1586 output_cmp (gen_rtx_REG (HImode, 7), const0_rtx, 'H');
1587 return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
1595 (label_ref (match_operand 0 "" "")))]
1601 (if_then_else (eq (cc0)
1603 (label_ref (match_operand 0 "" ""))
1606 "* return output_condjump (operands[0], \"eq\", 't'); ")
1610 (if_then_else (ne (cc0)
1612 (label_ref (match_operand 0 "" ""))
1615 "* return output_condjump (operands[0], \"eq\", 'f'); ")
1619 (if_then_else (gt (cc0)
1621 (label_ref (match_operand 0 "" ""))
1624 "* return output_condjump (operands[0], \"le\", 'f'); ")
1628 (if_then_else (gtu (cc0)
1630 (label_ref (match_operand 0 "" ""))
1633 "* return output_condjump (operands[0], \"leu\", 'f'); ")
1637 (if_then_else (lt (cc0)
1639 (label_ref (match_operand 0 "" ""))
1642 "* return output_condjump (operands[0], \"lt\", 't'); ")
1646 (if_then_else (ltu (cc0)
1648 (label_ref (match_operand 0 "" ""))
1651 "* return output_condjump (operands[0], \"ltu\", 't'); ")
1655 (if_then_else (ge (cc0)
1657 (label_ref (match_operand 0 "" ""))
1660 "* return output_condjump (operands[0], \"lt\", 'f'); ")
1664 (if_then_else (geu (cc0)
1666 (label_ref (match_operand 0 "" ""))
1669 "* return output_condjump (operands[0], \"ltu\", 'f'); ")
1673 (if_then_else (le (cc0)
1675 (label_ref (match_operand 0 "" ""))
1678 "* return output_condjump (operands[0], \"le\", 't'); ")
1682 (if_then_else (leu (cc0)
1684 (label_ref (match_operand 0 "" ""))
1687 "* return output_condjump (operands[0], \"leu\", 't'); ")
1691 (if_then_else (eq (cc0)
1694 (label_ref (match_operand 0 "" ""))))]
1696 "* return output_condjump (operands[0], \"eq\", 'f'); ")
1700 (if_then_else (ne (cc0)
1703 (label_ref (match_operand 0 "" ""))))]
1705 "* return output_condjump (operands[0], \"eq\", 't'); ")
1709 (if_then_else (gt (cc0)
1712 (label_ref (match_operand 0 "" ""))))]
1714 "* return output_condjump (operands[0], \"le\", 't'); ")
1718 (if_then_else (gtu (cc0)
1721 (label_ref (match_operand 0 "" ""))))]
1723 "* return output_condjump (operands[0], \"leu\", 't'); ")
1727 (if_then_else (lt (cc0)
1730 (label_ref (match_operand 0 "" ""))))]
1732 "* return output_condjump (operands[0], \"lt\", 'f'); ")
1736 (if_then_else (ltu (cc0)
1739 (label_ref (match_operand 0 "" ""))))]
1741 "* return output_condjump (operands[0], \"ltu\", 'f'); ")
1745 (if_then_else (ge (cc0)
1748 (label_ref (match_operand 0 "" ""))))]
1750 "* return output_condjump (operands[0], \"lt\", 't'); ")
1754 (if_then_else (geu (cc0)
1757 (label_ref (match_operand 0 "" ""))))]
1759 "* return output_condjump (operands[0], \"ltu\", 't'); ")
1763 (if_then_else (le (cc0)
1766 (label_ref (match_operand 0 "" ""))))]
1768 "* return output_condjump (operands[0], \"le\", 'f'); ")
1772 (if_then_else (leu (cc0)
1775 (label_ref (match_operand 0 "" ""))))]
1777 "* return output_condjump (operands[0], \"leu\", 'f'); ")
1781 (define_expand "call_pop"
1782 [(parallel [(call (match_operand:QI 0 "memory_operand" "m")
1783 (match_operand:SI 1 "const_int_operand" "i"))
1784 (match_operand:SI 2 "const_int_operand" "i")
1785 (match_operand:SI 3 "const_int_operand" "i")
1791 [(call (match_operand:QI 0 "memory_operand" "m")
1792 (match_operand:SI 1 "const_int_operand" "i"))
1793 (match_operand:SI 2 "const_int_operand" "i")
1794 (match_operand:SI 3 "const_int_operand" "i")
1795 (match_operand:SI 4 "" "")]
1797 "* return output_call (insn, &operands[0]);")
1799 (define_expand "call_value_pop"
1800 [(parallel [(set (match_operand 0 "" "=g")
1801 (call (match_operand:QI 1 "memory_operand" "m")
1802 (match_operand:SI 2 "const_int_operand" "i")))
1803 (match_operand:SI 3 "const_int_operand" "i")
1804 (match_operand:SI 4 "const_int_operand" "i")
1810 [(set (match_operand 0 "" "=g")
1811 (call (match_operand:QI 1 "memory_operand" "m")
1812 (match_operand:SI 2 "const_int_operand" "i")))
1813 (match_operand:SI 3 "const_int_operand" "i")
1814 (match_operand:SI 4 "const_int_operand" "i")
1815 (match_operand:SI 5 "" "")]
1817 "* return output_call (insn, &operands[1]); ")
1819 ;; Call subroutine returning any type.
1821 (define_expand "untyped_call"
1822 [(parallel [(call (match_operand 0 "" "")
1824 (match_operand 1 "" "")
1825 (match_operand 2 "" "")])]
1831 emit_call_insn (gen_call_pop (operands[0], const0_rtx,
1832 const0_rtx, const0_rtx));
1834 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1836 rtx set = XVECEXP (operands[2], 0, i);
1837 emit_move_insn (SET_DEST (set), SET_SRC (set));
1840 /* The optimizer does not know that the call sets the function value
1841 registers we stored in the result block. We avoid problems by
1842 claiming that all hard registers are used and clobbered at this
1844 emit_insn (gen_blockage ());
1849 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1850 ;; all of memory. This blocks insns from being moved across this point.
1852 (define_insn "blockage"
1853 [(unspec_volatile [(const_int 0)] 0)]
1857 (define_expand "return"
1860 " replace_arg_pushes (); ")
1867 (define_expand "prologue"
1872 emit_ap_optimizations ();
1876 (define_insn "tablejump"
1877 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
1878 (use (label_ref (match_operand 1 "" "")))]
1882 (define_insn "indirect_jump"
1883 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]