1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 /* RUN-TIME TARGET SPECIFICATION. */
31 #define TARGET_CPU_CPP_BUILTINS() \
35 builtin_define ("_BIGMODEL"); \
36 if (!TARGET_MEMPARM) \
37 builtin_define ("_REGPARM"); \
38 if (flag_inline_functions \
39 || flag_inline_trees) \
40 builtin_define ("_INLINE"); \
43 builtin_define ("_TMS320C3x"); \
44 builtin_define ("_C3x"); \
47 builtin_define ("_TMS320C30"); \
48 builtin_define ("_C30"); \
50 else if (TARGET_C31) \
52 builtin_define ("_TMS320C31"); \
53 builtin_define ("_C31"); \
55 else if (TARGET_C32) \
57 builtin_define ("_TMS320C32"); \
58 builtin_define ("_C32"); \
60 else if (TARGET_C33) \
62 builtin_define ("_TMS320C33"); \
63 builtin_define ("_C33"); \
68 builtin_define ("_TMS320C4x"); \
69 builtin_define ("_C4x"); \
72 builtin_define ("_TMS320C40"); \
73 builtin_define ("_C40"); \
75 else if (TARGET_C44) \
77 builtin_define ("_TMS320C44"); \
78 builtin_define ("_C44"); \
84 /* Name of the c4x assembler. */
86 #define ASM_PROG "c4x-as"
88 /* Name of the c4x linker. */
90 #define LD_PROG "c4x-ld"
92 /* Define assembler options. */
95 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
96 %{!m30:%{!m40:-m40}}}}}}}} \
109 %{mmemparm:-p} %{mregparm:-r} \
110 %{!mmemparm:%{!mregparm:-r}} \
111 %{mbig:-b} %{msmall:-s} \
112 %{!msmall:%{!mbig:-b}}"
114 /* Define linker options. */
117 %{m30:--architecture c3x} \
118 %{m31:--architecture c3x} \
119 %{m32:--architecture c3x} \
120 %{m33:--architecture c3x} \
121 %{mcpu=30:--architecture c3x} \
122 %{mcpu=31:--architecture c3x} \
123 %{mcpu=32:--architecture c3x} \
124 %{mcpu=33:--architecture c3x}"
126 /* Specify the end file to link with. */
128 #define ENDFILE_SPEC ""
130 /* Target compilation option flags. */
132 #define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
133 #define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
134 #define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
135 #define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
136 #define C3X_FLAG 0x0000010 /* Emit C3x code. */
137 #define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
138 #define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
139 #define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
140 #define DEVEL_FLAG 0x0000100 /* Enable features under development. */
141 #define RPTB_FLAG 0x0000200 /* Enable repeat block. */
142 #define BK_FLAG 0x0000400 /* Use BK as general register. */
143 #define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
144 #define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
145 #define HOIST_FLAG 0x0002000 /* Force constants into registers. */
146 #define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
147 #define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
148 #define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
149 #define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
150 #define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
151 #define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
153 #define C30_FLAG 0x0100000 /* Emit C30 code. */
154 #define C31_FLAG 0x0200000 /* Emit C31 code. */
155 #define C32_FLAG 0x0400000 /* Emit C32 code. */
156 #define C33_FLAG 0x0400000 /* Emit C33 code. */
157 #define C40_FLAG 0x1000000 /* Emit C40 code. */
158 #define C44_FLAG 0x2000000 /* Emit C44 code. */
160 /* Run-time compilation parameters selecting different hardware subsets.
162 Macro to define tables used to set the flags.
163 This is a list in braces of triplets in braces,
164 each pair being { "NAME", VALUE, "DESCRIPTION" }
165 where VALUE is the bits to set or minus the bits to clear.
166 An empty string NAME is used to identify the default VALUE. */
168 #define TARGET_SWITCHES \
169 { { "small", SMALL_MEMORY_FLAG, \
170 N_("Small memory model") }, \
171 { "big", -SMALL_MEMORY_FLAG, \
172 N_("Big memory model") }, \
173 { "mpyi", MPYI_FLAG, \
174 N_("Use MPYI instruction for C3x") }, \
175 { "no-mpyi", -MPYI_FLAG, \
176 N_("Do not use MPYI instruction for C3x") }, \
177 { "fast-fix", FAST_FIX_FLAG, \
178 N_("Use fast but approximate float to integer conversion") }, \
179 { "no-fast-fix", -FAST_FIX_FLAG, \
180 N_("Use slow but accurate float to integer conversion") }, \
181 { "rpts", RPTS_FLAG, \
182 N_("Enable use of RTPS instruction") }, \
183 { "no-rpts", -RPTS_FLAG, \
184 N_("Disable use of RTPS instruction") }, \
185 { "rptb", RPTB_FLAG, \
186 N_("Enable use of RTPB instruction") }, \
187 { "no-rptb", -RPTB_FLAG, \
188 N_("Disable use of RTPB instruction") }, \
190 N_("Generate code for C30 CPU")}, \
192 N_("Generate code for C31 CPU")}, \
194 N_("Generate code for C32 CPU")}, \
196 N_("Generate code for C33 CPU")}, \
198 N_("Generate code for C40 CPU")}, \
200 N_("Generate code for C44 CPU")}, \
202 N_("Emit code compatible with TI tools")}, \
203 { "no-ti", -TI_FLAG, \
204 N_("Emit code to use GAS extensions")}, \
205 { "paranoid", PARANOID_FLAG, \
206 N_("Save DP across ISR in small memory model") }, \
207 { "no-paranoid", -PARANOID_FLAG, \
208 N_("Don't save DP across ISR in small memory model") }, \
209 { "isr-dp-reload", PARANOID_FLAG, \
210 N_("Save DP across ISR in small memory model") }, \
211 { "no-isr-dp-reload", -PARANOID_FLAG, \
212 N_("Don't save DP across ISR in small memory model") }, \
213 { "memparm", MEMPARM_FLAG, \
214 N_("Pass arguments on the stack") }, \
215 { "regparm", -MEMPARM_FLAG, \
216 N_("Pass arguments in registers") }, \
217 { "devel", DEVEL_FLAG, \
218 N_("Enable new features under development") }, \
219 { "no-devel", -DEVEL_FLAG, \
220 N_("Disable new features under development") }, \
222 N_("Use the BK register as a general purpose register") }, \
223 { "no-bk", -BK_FLAG, \
224 N_("Do not allocate BK register") }, \
226 N_("Enable use of DB instruction") }, \
227 { "no-db", -DB_FLAG, \
228 N_("Disable use of DB instruction") }, \
229 { "debug", DEBUG_FLAG, \
230 N_("Enable debugging") }, \
231 { "no-debug", -DEBUG_FLAG, \
232 N_("Disable debugging") }, \
233 { "hoist", HOIST_FLAG, \
234 N_("Force constants into registers to improve hoisting") }, \
235 { "no-hoist", -HOIST_FLAG, \
236 N_("Don't force constants into registers") }, \
237 { "force", FORCE_FLAG, \
238 N_("Force RTL generation to emit valid 3 operand insns") }, \
239 { "no-force", -FORCE_FLAG, \
240 N_("Allow RTL generation to emit invalid 3 operand insns") }, \
241 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
242 N_("Allow unsigned interation counts for RPTB/DB") }, \
243 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
244 N_("Disallow unsigned iteration counts for RPTB/DB") }, \
245 { "preserve-float", PRESERVE_FLOAT_FLAG, \
246 N_("Preserve all 40 bits of FP reg across call") }, \
247 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
248 N_("Only preserve 32 bits of FP reg across call") }, \
249 { "parallel-insns", PARALLEL_INSN_FLAG, \
250 N_("Enable parallel instructions") }, \
251 { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
252 N_("Disable parallel instructions") }, \
253 { "parallel-mpy", PARALLEL_MPY_FLAG, \
254 N_("Enable MPY||ADD and MPY||SUB instructions") }, \
255 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
256 N_("Disable MPY||ADD and MPY||SUB instructions") }, \
257 { "aliases", ALIASES_FLAG, \
258 N_("Assume that pointers may be aliased") }, \
259 { "no-aliases", -ALIASES_FLAG, \
260 N_("Assume that pointers not aliased") }, \
261 { "", TARGET_DEFAULT, ""} }
263 /* Default target switches. */
265 /* Play safe, not the fastest code. */
266 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
267 | PARALLEL_MPY_FLAG | RPTB_FLAG
270 Max iteration count for RPTB/RPTS is 2^31 + 1.
271 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
272 RPTS blocks interrupts. */
275 extern int target_flags;
277 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
278 #define TARGET_SMALL_REG_CLASS 0
280 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
281 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
282 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
283 #define TARGET_RPTS (target_flags & RPTS_FLAG)
284 #define TARGET_TI (target_flags & TI_FLAG)
285 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
286 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
287 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
288 #define TARGET_RPTB (target_flags & RPTB_FLAG \
290 #define TARGET_BK (target_flags & BK_FLAG)
291 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
292 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
293 #define TARGET_HOIST (target_flags & HOIST_FLAG)
294 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
295 #define TARGET_FORCE (target_flags & FORCE_FLAG)
296 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
297 #define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
299 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
300 && (target_flags & PARALLEL_MPY_FLAG))
301 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
303 #define TARGET_C3X (target_flags & C3X_FLAG)
304 #define TARGET_C30 (target_flags & C30_FLAG)
305 #define TARGET_C31 (target_flags & C31_FLAG)
306 #define TARGET_C32 (target_flags & C32_FLAG)
307 #define TARGET_C33 (target_flags & C33_FLAG)
308 #define TARGET_C40 (target_flags & C40_FLAG)
309 #define TARGET_C44 (target_flags & C44_FLAG)
311 /* Define some options to control code generation. */
312 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
313 /* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
314 during RTL generation. */
315 #define TARGET_EXPOSE_LDP 0
316 /* Nonzero to force loading of direct memory references into a register. */
317 #define TARGET_LOAD_DIRECT_MEMS 0
319 /* -mrpts allows the use of the RPTS instruction irregardless.
320 -mrpts=max-cycles will use RPTS if the number of cycles is constant
321 and less than max-cycles. */
323 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
325 #define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED)
327 /* -mcpu=XX with XX = target DSP version number. */
329 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
331 #define TARGET_OPTIONS \
332 { {"rpts=", &c4x_rpts_cycles_string, \
333 N_("Specify maximum number of iterations for RPTS") }, \
334 {"cpu=", &c4x_cpu_version_string, \
335 N_("Select CPU to generate code for") } }
337 /* Sometimes certain combinations of command options do not make sense
338 on a particular target machine. You can define a macro
339 `OVERRIDE_OPTIONS' to take account of this. This macro, if
340 defined, is executed once just after all the command options have
343 #define OVERRIDE_OPTIONS c4x_override_options ()
345 /* Define this to change the optimizations performed by default. */
347 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
349 /* Run Time Target Specification. */
351 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
353 /* Storage Layout. */
355 #define BITS_BIG_ENDIAN 0
356 #define BYTES_BIG_ENDIAN 0
357 #define WORDS_BIG_ENDIAN 0
359 /* Technically, we are little endian, but we put the floats out as
360 whole longs and this makes GCC put them out in the right order. */
362 #define FLOAT_WORDS_BIG_ENDIAN 1
364 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
365 all integral and floating point data types are stored in memory as
366 32-bits (floating point types can be stored as 40-bits in the
367 extended precision registers), so sizeof(char) = sizeof(short) =
368 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
370 #define BITS_PER_UNIT 32
371 #define UNITS_PER_WORD 1
372 #define PARM_BOUNDARY 32
373 #define STACK_BOUNDARY 32
374 #define FUNCTION_BOUNDARY 32
375 #define BIGGEST_ALIGNMENT 32
376 #define EMPTY_FIELD_BOUNDARY 32
377 #define STRICT_ALIGNMENT 0
378 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
379 #define MAX_FIXED_MODE_SIZE 64 /* HImode. */
381 /* If a structure has a floating point field then force structure
382 to have BLKMODE, unless it is the only field. */
383 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
384 (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
386 /* Number of bits in the high and low parts of a two stage
387 load of an immediate constant. */
388 #define BITS_PER_HIGH 16
389 #define BITS_PER_LO_SUM 16
391 /* Define register numbers. */
393 /* Extended-precision registers. */
404 /* Auxiliary (address) registers. */
415 /* Data page register. */
419 /* Index registers. */
424 /* Block size register. */
432 /* Status register. */
436 /* Misc. interrupt registers. */
438 #define DIE_REGNO 22 /* C4x only. */
439 #define IE_REGNO 22 /* C3x only. */
440 #define IIE_REGNO 23 /* C4x only. */
441 #define IF_REGNO 23 /* C3x only. */
442 #define IIF_REGNO 24 /* C4x only. */
443 #define IOF_REGNO 24 /* C3x only. */
445 /* Repeat block registers. */
451 /* Additional extended-precision registers. */
453 #define R8_REGNO 28 /* C4x only. */
454 #define R9_REGNO 29 /* C4x only. */
455 #define R10_REGNO 30 /* C4x only. */
456 #define R11_REGNO 31 /* C4x only. */
458 #define FIRST_PSEUDO_REGISTER 32
460 /* Extended precision registers (low set). */
462 #define IS_R0R1_REGNO(r) \
463 ((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
464 #define IS_R2R3_REGNO(r) \
465 ((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
466 #define IS_EXT_LOW_REGNO(r) \
467 ((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
469 /* Extended precision registers (high set). */
471 #define IS_EXT_HIGH_REGNO(r) \
473 && ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
475 /* Address registers. */
477 #define IS_AUX_REGNO(r) \
478 ((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
479 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
480 #define IS_DP_REGNO(r) ((r) == DP_REGNO)
481 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
482 #define IS_SP_REGNO(r) ((r) == SP_REGNO)
483 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
485 /* Misc registers. */
487 #define IS_ST_REGNO(r) ((r) == ST_REGNO)
488 #define IS_RC_REGNO(r) ((r) == RC_REGNO)
489 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
491 /* Composite register sets. */
493 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
494 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
495 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
496 || IS_REPEAT_REGNO(r) \
499 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
500 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
501 #define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
502 || ((r) == R8_REGNO))
503 #define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
505 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
506 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
507 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
508 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
509 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
510 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
511 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
512 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
513 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
514 || IS_PSEUDO_REGNO(r))
515 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
516 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
517 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
518 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
520 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
521 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
522 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
523 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
524 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
525 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
526 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
528 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
529 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
530 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
531 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
532 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
533 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
535 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
536 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
537 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
538 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
539 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
540 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
542 /* 1 for registers that have pervasive standard uses
543 and are not available for the register allocator. */
545 #define FIXED_REGISTERS \
547 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
549 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
550 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
553 /* 1 for registers not available across function calls.
554 These must include the FIXED_REGISTERS and also any
555 registers that can be used without being saved.
556 The latter must include the registers where values are returned
557 and the register where structure-value addresses are passed.
558 Aside from that, you can include as many other registers as you like.
560 Note that the extended precision registers are only saved in some
561 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
562 get clobbered for a given regno. */
564 #define CALL_USED_REGISTERS \
566 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
567 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
568 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
572 /* Macro to conditionally modify fixed_regs/call_used_regs. */
574 #define CONDITIONAL_REGISTER_USAGE \
578 fixed_regs[BK_REGNO] = 1; \
579 call_used_regs[BK_REGNO] = 1; \
580 c4x_regclass_map[BK_REGNO] = NO_REGS; \
586 reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
587 reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
588 reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
590 for (i = R8_REGNO; i <= R11_REGNO; i++) \
592 fixed_regs[i] = call_used_regs[i] = 1; \
593 c4x_regclass_map[i] = NO_REGS; \
596 if (TARGET_PRESERVE_FLOAT) \
598 c4x_caller_save_map[R6_REGNO] = HFmode; \
599 c4x_caller_save_map[R7_REGNO] = HFmode; \
603 /* Order of Allocation of Registers. */
605 /* List the order in which to allocate registers. Each register must be
606 listed once, even those in FIXED_REGISTERS.
608 First allocate registers that don't need preservation across calls,
609 except index and address registers. Then allocate data registers
610 that require preservation across calls (even though this invokes an
611 extra overhead of having to save/restore these registers). Next
612 allocate the address and index registers, since using these
613 registers for arithmetic can cause pipeline stalls. Finally
614 allocated the fixed registers which won't be allocated anyhow. */
616 #define REG_ALLOC_ORDER \
617 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
618 R9_REGNO, R10_REGNO, R11_REGNO, \
619 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
620 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
621 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
622 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
623 IR0_REGNO, IR1_REGNO, \
624 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
626 /* A C expression that is nonzero if hard register number REGNO2 can be
627 considered for use as a rename register for REGNO1 */
629 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
630 c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
632 /* Determine which register classes are very likely used by spill registers.
633 local-alloc.c won't allocate pseudos that have these classes as their
634 preferred class unless they are "preferred or nothing". */
636 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
638 /* CCmode is wrongly defined in machmode.def. It should have a size
639 of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single
640 extended precision register. Similarly, HCmode fits within two
641 extended precision registers. */
643 #define HARD_REGNO_NREGS(REGNO, MODE) \
644 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
645 ((MODE) == HFmode) ? 1 : \
646 ((MODE) == HCmode) ? 2 : \
647 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
650 /* A C expression that is nonzero if the hard register REGNO is preserved
651 across a call in mode MODE. This does not have to include the call used
654 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
655 ((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
656 || (IS_INT_CALL_SAVED_REGNO (REGNO) \
657 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
659 /* Specify the modes required to caller save a given hard regno. */
661 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
663 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
665 /* A C expression that is nonzero if it is desirable to choose
666 register allocation so as to avoid move instructions between a
667 value of mode MODE1 and a value of mode MODE2.
669 Value is 1 if it is a good idea to tie two pseudo registers
670 when one has mode MODE1 and one has mode MODE2.
671 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
672 for any hard reg, then this must be 0 for correct output. */
674 #define MODES_TIEABLE_P(MODE1, MODE2) 0
677 /* Define the classes of registers for register constraints in the
678 machine description. Also define ranges of constants.
680 One of the classes must always be named ALL_REGS and include all hard regs.
681 If there is more than one class, another class must be named NO_REGS
682 and contain no registers.
684 The name GENERAL_REGS must be the name of a class (or an alias for
685 another name such as ALL_REGS). This is the class of registers
686 that is allowed by "g" or "r" in a register constraint.
687 Also, registers outside this class are allocated only when
688 instructions express preferences for them.
690 The classes must be numbered in nondecreasing order; that is,
691 a larger-numbered class must never be contained completely
692 in a smaller-numbered class.
694 For any two classes, it is very desirable that there be another
695 class that represents their union. */
700 R0R1_REGS, /* 't'. */
701 R2R3_REGS, /* 'u'. */
702 EXT_LOW_REGS, /* 'q'. */
704 ADDR_REGS, /* 'a'. */
705 INDEX_REGS, /* 'x'. */
711 GENERAL_REGS, /* 'r'. */
718 #define N_REG_CLASSES (int) LIM_REG_CLASSES
720 #define REG_CLASS_NAMES \
740 /* Define which registers fit in which classes.
741 This is an initializer for a vector of HARD_REG_SET
742 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
743 since the register allocator will often choose a general register
744 in preference to RC for the decrement_and_branch_on_count pattern. */
746 #define REG_CLASS_CONTENTS \
748 {0x00000000}, /* No registers. */ \
749 {0x00000003}, /* 't' R0-R1 . */ \
750 {0x0000000c}, /* 'u' R2-R3 . */ \
751 {0x000000ff}, /* 'q' R0-R7 . */ \
752 {0xf00000ff}, /* 'f' R0-R11 */ \
753 {0x0000ff00}, /* 'a' AR0-AR7. */ \
754 {0x00060000}, /* 'x' IR0-IR1. */ \
755 {0x00080000}, /* 'k' BK. */ \
756 {0x00100000}, /* 'b' SP. */ \
757 {0x08000000}, /* 'v' RC. */ \
758 {0x0800ff00}, /* RC,AR0-AR7. */ \
759 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
760 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
761 {0x00010000}, /* 'z' DP. */ \
762 {0x00200000}, /* 'y' ST. */ \
763 {0xffffffff}, /* All registers. */ \
766 /* The same information, inverted:
767 Return the class number of the smallest class containing
768 reg number REGNO. This could be a conditional expression
769 or could index an array. */
771 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
773 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
774 explicitly used in the rtl is kept as short as possible.
776 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
777 is defined since the MPY|ADD insns require the classes R0R1_REGS and
778 R2R3_REGS which are used by the function return registers (R0,R1) and
779 the register arguments (R2,R3), respectively. I'm reluctant to define
780 this macro since it stomps on many potential optimisations. Ideally
781 it should have a register class argument so that not all the register
782 classes gets penalised for the sake of a naughty few... For long
783 double arithmetic we need two additional registers that we can use as
786 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
788 #define BASE_REG_CLASS ADDR_REGS
789 #define INDEX_REG_CLASS INDEX_REGS
792 Register constraints for the C4x
794 a - address reg (ar0-ar7)
796 c - other gp int-only reg
797 d - data/int reg (equiv. to f)
799 h - data/long double reg (equiv. to f)
804 v - repeat count (rc)
805 x - index register (ir0-ir1)
806 y - status register (st)
809 Memory/constant constraints for the C4x
811 G - short float 16-bit
812 I - signed 16-bit constant (sign extended)
813 J - signed 8-bit constant (sign extended) (C4x only)
814 K - signed 5-bit constant (sign extended) (C4x only for stik)
815 L - unsigned 16-bit constant
816 M - unsigned 8-bit constant (C4x only)
817 N - ones complement of unsigned 16-bit constant
818 Q - indirect arx + 9-bit signed displacement
819 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
820 R - indirect arx + 5-bit unsigned displacement (C4x only)
821 S - indirect arx + 0, 1, or irn displacement
822 T - direct symbol ref
823 > - indirect with autoincrement
824 < - indirect with autodecrement
825 } - indirect with post-modify
826 { - indirect with pre-modify
829 #define REG_CLASS_FROM_LETTER(CC) \
830 ( ((CC) == 'a') ? ADDR_REGS \
831 : ((CC) == 'b') ? SP_REG \
832 : ((CC) == 'c') ? INT_REGS \
833 : ((CC) == 'd') ? EXT_REGS \
834 : ((CC) == 'f') ? EXT_REGS \
835 : ((CC) == 'h') ? EXT_REGS \
836 : ((CC) == 'k') ? BK_REG \
837 : ((CC) == 'q') ? EXT_LOW_REGS \
838 : ((CC) == 't') ? R0R1_REGS \
839 : ((CC) == 'u') ? R2R3_REGS \
840 : ((CC) == 'v') ? RC_REG \
841 : ((CC) == 'x') ? INDEX_REGS \
842 : ((CC) == 'y') ? ST_REG \
843 : ((CC) == 'z') ? DP_REG \
846 /* These assume that REGNO is a hard or pseudo reg number.
847 They give nonzero only if REGNO is a hard reg of the suitable class
848 or a pseudo reg currently allocated to a suitable hard reg.
849 Since they use reg_renumber, they are safe only once reg_renumber
850 has been allocated, which happens in local-alloc.c. */
852 #define REGNO_OK_FOR_BASE_P(REGNO) \
853 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
855 #define REGNO_OK_FOR_INDEX_P(REGNO) \
856 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
858 /* If we have to generate framepointer + constant prefer an ADDR_REGS
859 register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
861 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
862 (GET_CODE (X) == PLUS \
863 && GET_MODE (X) == Pmode \
864 && GET_CODE (XEXP ((X), 0)) == REG \
865 && GET_MODE (XEXP ((X), 0)) == Pmode \
866 && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
867 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
868 ? ADDR_REGS : (CLASS))
870 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
872 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
874 #define CLASS_MAX_NREGS(CLASS, MODE) \
875 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
876 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
878 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
880 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
882 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
884 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
886 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
888 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
890 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
892 #define IS_HIGH_CONST(VAL) \
893 (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
896 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
898 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
900 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
901 && IS_DISP1_CONST (VAL + 1))
903 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
904 && IS_DISP8_CONST (VAL + 1))
906 #define CONST_OK_FOR_LETTER_P(VAL, C) \
907 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
908 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
909 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
910 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
911 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
912 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
913 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
916 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
917 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
918 : ((C) == 'H') ? (c4x_H_constant (OP)) \
921 #define EXTRA_CONSTRAINT(OP, C) \
922 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
923 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
924 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
925 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
926 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
929 #define SMALL_CONST(VAL, insn) \
930 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
931 ? IS_INT16_CONST (VAL) \
932 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
933 ? IS_NOT_UINT16_CONST (VAL) \
934 : ( (get_attr_data (insn) == DATA_HIGH_16) \
935 ? IS_HIGH_CONST (VAL) \
936 : IS_UINT16_CONST (VAL) \
942 I. Routine calling with arguments in registers
943 ----------------------------------------------
945 The TI C3x compiler has a rather unusual register passing algorithm.
946 Data is passed in the following registers (in order):
948 AR2, R2, R3, RC, RS, RE
950 However, the first and second floating point values are always in R2
951 and R3 (and all other floats are on the stack). Structs are always
952 passed on the stack. If the last argument is an ellipsis, the
953 previous argument is passed on the stack so that its address can be
954 taken for the stdargs macros.
956 Because of this, we have to pre-scan the list of arguments to figure
957 out what goes where in the list.
959 II. Routine calling with arguments on stack
960 -------------------------------------------
962 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
963 variables loc0, loc1, and loc2. After the function prologue has
964 been executed, the stack frame will look like:
966 [stack grows towards increasing addresses]
968 5 I saved reg1 I <= SP points here
978 0 I old FP I <= FP (AR3) points here
989 All local variables (locn) are accessible by means of +FP(n+1)
990 addressing, where n is the local variable number.
992 All stack arguments (argn) are accessible by means of -FP(n-2).
994 The stack pointer (SP) points to the last register saved in the
997 Note that a push instruction performs a preincrement of the stack
998 pointer. (STACK_PUSH_CODE == PRE_INC)
1000 III. Registers used in function calling convention
1001 --------------------------------------------------
1003 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
1004 R6...R7 (only by PUSHF, i.e. upper 32 bits)
1007 (Because of this model, we only assign FP values in R6, R7 and
1008 only assign integer values in R4, R5.)
1010 These registers are saved at each function entry and restored at
1011 the exit. Also it is expected any of these not affected by any
1012 call to user-defined (not service) functions.
1014 Not preserved across calls: R0...R3
1015 R4...R5 (upper 8 bits)
1016 R6...R7 (lower 8 bits)
1017 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
1019 These registers are used arbitrary in a function without being preserved.
1020 It is also expected that any of these can be clobbered by any call.
1022 Not used by GCC (except for in user "asm" statements):
1023 IE (DIE), IF (IIE), IOF (IIF)
1025 These registers are never used by GCC for any data, but can be used
1026 with "asm" statements. */
1031 /* Basic Stack Layout. */
1033 /* The stack grows upward, stack frame grows upward, and args grow
1036 #define STARTING_FRAME_OFFSET C4X_LOC0
1037 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
1038 #define ARGS_GROW_DOWNWARD
1039 #define STACK_POINTER_OFFSET 1
1041 /* Define this if pushing a word on the stack
1042 makes the stack pointer a smaller address. */
1044 /* #define STACK_GROWS_DOWNWARD. */
1045 /* Like the dsp16xx, i370, i960, and we32k ports. */
1047 /* Define this if the nominal address of the stack frame
1048 is at the high-address end of the local variables;
1049 that is, each additional local variable allocated
1050 goes at a more negative offset in the frame. */
1052 /* #define FRAME_GROWS_DOWNWARD. */
1055 /* Registers That Address the Stack Frame. */
1057 #define STACK_POINTER_REGNUM SP_REGNO /* SP. */
1058 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
1059 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
1060 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
1062 /* Eliminating Frame Pointer and Arg Pointer. */
1064 #define FRAME_POINTER_REQUIRED 0
1066 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1070 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1071 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1072 offset += TARGET_PRESERVE_FLOAT \
1073 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1074 (DEPTH) = -(offset + get_frame_size ()); \
1077 /* This is a hack... We need to specify a register. */
1078 #define ELIMINABLE_REGS \
1079 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1081 #define CAN_ELIMINATE(FROM, TO) \
1082 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1083 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1085 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1089 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1090 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1091 offset += TARGET_PRESERVE_FLOAT \
1092 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1093 (OFFSET) = -(offset + get_frame_size ()); \
1097 /* Passing Function Arguments on the Stack. */
1100 #define PUSH_ROUNDING(BYTES) (BYTES)
1101 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1103 /* The following structure is used by calls.c, function.c, c4x.c. */
1105 typedef struct c4x_args
1118 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1119 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1121 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1122 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1124 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1125 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1127 /* Define the profitability of saving registers around calls.
1128 We disable caller save to avoid a bug in flow.c (this also affects
1129 other targets such as m68k). Since we must use stf/sti,
1130 the profitability is marginal anyway. */
1132 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1134 /* Never pass data by reference. */
1136 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1138 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1140 /* 1 if N is a possible register number for function argument passing. */
1142 #define FUNCTION_ARG_REGNO_P(REGNO) \
1143 ( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
1144 || ((REGNO) == R2_REGNO) /* R2. */ \
1145 || ((REGNO) == R3_REGNO) /* R3. */ \
1146 || ((REGNO) == RC_REGNO) /* RC. */ \
1147 || ((REGNO) == RS_REGNO) /* RS. */ \
1148 || ((REGNO) == RE_REGNO)) /* RE. */ \
1152 /* How Scalar Function Values Are Returned. */
1154 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1155 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
1157 #define LIBCALL_VALUE(MODE) \
1158 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0. */
1160 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1162 /* How Large Values Are Returned. */
1164 #define DEFAULT_PCC_STRUCT_RETURN 0
1165 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0. */
1167 /* Varargs handling. */
1169 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1170 c4x_va_arg (valist, type)
1172 /* Generating Code for Profiling. */
1174 /* Note that the generated assembly uses the ^ operator to load the 16
1175 MSBs of the address. This is not supported by the TI assembler.
1176 The FUNCTION profiler needs a function mcount which gets passed
1177 a pointer to the LABELNO. */
1179 #define FUNCTION_PROFILER(FILE, LABELNO) \
1182 fprintf (FILE, "\tpush\tar2\n"); \
1183 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1184 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1185 fprintf (FILE, "\tcall\tmcount\n"); \
1186 fprintf (FILE, "\tpop\tar2\n"); \
1190 fprintf (FILE, "\tpush\tar2\n"); \
1191 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1192 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1193 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1194 fprintf (FILE, "\tcall\tmcount\n"); \
1195 fprintf (FILE, "\tpop\tar2\n"); \
1198 /* Implicit Calls to Library Routines. */
1200 #define MULQI3_LIBCALL "__mulqi3"
1201 #define DIVQI3_LIBCALL "__divqi3"
1202 #define UDIVQI3_LIBCALL "__udivqi3"
1203 #define MODQI3_LIBCALL "__modqi3"
1204 #define UMODQI3_LIBCALL "__umodqi3"
1206 #define DIVQF3_LIBCALL "__divqf3"
1208 #define MULHF3_LIBCALL "__mulhf3"
1209 #define DIVHF3_LIBCALL "__divhf3"
1211 #define MULHI3_LIBCALL "__mulhi3"
1212 #define SMULHI3_LIBCALL "__smulhi3_high"
1213 #define UMULHI3_LIBCALL "__umulhi3_high"
1214 #define DIVHI3_LIBCALL "__divhi3"
1215 #define UDIVHI3_LIBCALL "__udivhi3"
1216 #define MODHI3_LIBCALL "__modhi3"
1217 #define UMODHI3_LIBCALL "__umodhi3"
1219 #define FLOATHIQF2_LIBCALL "__floathiqf2"
1220 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
1221 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
1222 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
1224 #define FLOATHIHF2_LIBCALL "__floathihf2"
1225 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
1226 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
1227 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
1229 #define FFS_LIBCALL "__ffs"
1231 #define INIT_TARGET_OPTABS \
1233 smul_optab->handlers[(int) QImode].libfunc \
1234 = init_one_libfunc (MULQI3_LIBCALL); \
1235 sdiv_optab->handlers[(int) QImode].libfunc \
1236 = init_one_libfunc (DIVQI3_LIBCALL); \
1237 udiv_optab->handlers[(int) QImode].libfunc \
1238 = init_one_libfunc (UDIVQI3_LIBCALL); \
1239 smod_optab->handlers[(int) QImode].libfunc \
1240 = init_one_libfunc (MODQI3_LIBCALL); \
1241 umod_optab->handlers[(int) QImode].libfunc \
1242 = init_one_libfunc (UMODQI3_LIBCALL); \
1243 sdiv_optab->handlers[(int) QFmode].libfunc \
1244 = init_one_libfunc (DIVQF3_LIBCALL); \
1245 smul_optab->handlers[(int) HFmode].libfunc \
1246 = init_one_libfunc (MULHF3_LIBCALL); \
1247 sdiv_optab->handlers[(int) HFmode].libfunc \
1248 = init_one_libfunc (DIVHF3_LIBCALL); \
1249 smul_optab->handlers[(int) HImode].libfunc \
1250 = init_one_libfunc (MULHI3_LIBCALL); \
1251 sdiv_optab->handlers[(int) HImode].libfunc \
1252 = init_one_libfunc (DIVHI3_LIBCALL); \
1253 udiv_optab->handlers[(int) HImode].libfunc \
1254 = init_one_libfunc (UDIVHI3_LIBCALL); \
1255 smod_optab->handlers[(int) HImode].libfunc \
1256 = init_one_libfunc (MODHI3_LIBCALL); \
1257 umod_optab->handlers[(int) HImode].libfunc \
1258 = init_one_libfunc (UMODHI3_LIBCALL); \
1259 ffs_optab->handlers[(int) QImode].libfunc \
1260 = init_one_libfunc (FFS_LIBCALL); \
1262 = init_one_libfunc(SMULHI3_LIBCALL); \
1264 = init_one_libfunc(UMULHI3_LIBCALL); \
1265 fix_truncqfhi2_libfunc \
1266 = init_one_libfunc(FIX_TRUNCQFHI2_LIBCALL); \
1267 fixuns_truncqfhi2_libfunc \
1268 = init_one_libfunc(FIXUNS_TRUNCQFHI2_LIBCALL); \
1269 fix_trunchfhi2_libfunc \
1270 = init_one_libfunc(FIX_TRUNCHFHI2_LIBCALL); \
1271 fixuns_trunchfhi2_libfunc \
1272 = init_one_libfunc(FIXUNS_TRUNCHFHI2_LIBCALL); \
1273 floathiqf2_libfunc \
1274 = init_one_libfunc(FLOATHIQF2_LIBCALL); \
1275 floatunshiqf2_libfunc \
1276 = init_one_libfunc(FLOATUNSHIQF2_LIBCALL); \
1277 floathihf2_libfunc \
1278 = init_one_libfunc(FLOATHIHF2_LIBCALL); \
1279 floatunshihf2_libfunc \
1280 = init_one_libfunc(FLOATUNSHIHF2_LIBCALL); \
1283 #define TARGET_MEM_FUNCTIONS
1285 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1287 CCmode should be used when no special processing is needed. */
1288 #define SELECT_CC_MODE(OP,X,Y) \
1289 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1290 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1291 || GET_MODE (X) == ABS \
1292 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1293 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1294 || GET_MODE (Y) == ABS) \
1295 ? CC_NOOVmode : CCmode)
1297 /* Addressing Modes. */
1299 #define HAVE_POST_INCREMENT 1
1300 #define HAVE_PRE_INCREMENT 1
1301 #define HAVE_POST_DECREMENT 1
1302 #define HAVE_PRE_DECREMENT 1
1303 #define HAVE_PRE_MODIFY_REG 1
1304 #define HAVE_POST_MODIFY_REG 1
1305 #define HAVE_PRE_MODIFY_DISP 1
1306 #define HAVE_POST_MODIFY_DISP 1
1308 /* The number of insns that can be packed into a single opcode. */
1309 #define PACK_INSNS 2
1311 /* Recognize any constant value that is a valid address.
1312 We could allow arbitrary constant addresses in the large memory
1313 model but for the small memory model we can only accept addresses
1314 within the data page. I suppose we could also allow
1315 CONST PLUS SYMBOL_REF. */
1316 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1318 /* Maximum number of registers that can appear in a valid memory
1320 #define MAX_REGS_PER_ADDRESS 2
1322 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1323 and check its validity for a certain class.
1324 We have two alternate definitions for each of them.
1325 The usual definition accepts all pseudo regs; the other rejects
1326 them unless they have been allocated suitable hard regs.
1327 The symbol REG_OK_STRICT causes the latter definition to be used.
1329 Most source files want to accept pseudo regs in the hope that
1330 they will get allocated to the class that the insn wants them to be in.
1331 Source files for reload pass need to be strict.
1332 After reload, it makes no difference, since pseudo regs have
1333 been eliminated by then. */
1335 #ifndef REG_OK_STRICT
1337 /* Nonzero if X is a hard or pseudo reg that can be used as an base. */
1339 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
1341 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1343 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
1345 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1347 if (c4x_check_legit_addr (MODE, X, 0)) \
1353 /* Nonzero if X is a hard reg that can be used as an index. */
1355 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1357 /* Nonzero if X is a hard reg that can be used as a base reg. */
1359 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1361 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1363 if (c4x_check_legit_addr (MODE, X, 1)) \
1369 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1372 new = c4x_legitimize_address (X, MODE); \
1373 if (new != NULL_RTX) \
1380 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1382 if (MODE != HImode \
1384 && GET_MODE (X) != HImode \
1385 && GET_MODE (X) != HFmode \
1386 && (GET_CODE (X) == CONST \
1387 || GET_CODE (X) == SYMBOL_REF \
1388 || GET_CODE (X) == LABEL_REF)) \
1390 if (! TARGET_SMALL) \
1393 X = gen_rtx_LO_SUM (GET_MODE (X), \
1394 gen_rtx_HIGH (GET_MODE (X), X), X); \
1395 i = push_reload (XEXP (X, 0), NULL_RTX, \
1396 &XEXP (X, 0), NULL, \
1397 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1399 /* The only valid reg is DP. This is a fixed reg and will \
1400 normally not be used so force it. */ \
1401 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1402 rld[i].nocombine = 1; \
1406 else if (MODE != HImode \
1408 && GET_MODE (X) != HImode \
1409 && GET_MODE (X) != HFmode \
1410 && GET_CODE (X) == LO_SUM \
1411 && GET_CODE (XEXP (X,0)) == HIGH \
1412 && (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
1413 || GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
1414 || GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
1416 if (! TARGET_SMALL) \
1418 int i = push_reload (XEXP (X, 0), NULL_RTX, \
1419 &XEXP (X, 0), NULL, \
1420 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1422 /* The only valid reg is DP. This is a fixed reg and will \
1423 normally not be used so force it. */ \
1424 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1425 rld[i].nocombine = 1; \
1431 /* No mode-dependent addresses on the C4x are autoincrements. */
1433 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1434 if (GET_CODE (ADDR) == PRE_DEC \
1435 || GET_CODE (ADDR) == POST_DEC \
1436 || GET_CODE (ADDR) == PRE_INC \
1437 || GET_CODE (ADDR) == POST_INC \
1438 || GET_CODE (ADDR) == POST_MODIFY \
1439 || GET_CODE (ADDR) == PRE_MODIFY) \
1443 /* Nonzero if the constant value X is a legitimate general operand.
1444 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1446 The C4x can only load 16-bit immediate values, so we only allow a
1447 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1448 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1449 model) so that the symbols will be forced into the constant pool.
1450 On second thoughts, let's do this with the move expanders since
1451 the alias analysis has trouble if we force constant addresses
1455 #define LEGITIMATE_CONSTANT_P(X) \
1456 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1457 || (GET_CODE (X) == CONST_INT) \
1458 || (GET_CODE (X) == SYMBOL_REF) \
1459 || (GET_CODE (X) == LABEL_REF) \
1460 || (GET_CODE (X) == CONST) \
1461 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1462 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1464 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1466 /* Descripting Relative Cost of Operations. */
1468 /* Provide the costs of a rtl expression. This is in the body of a
1471 Note that we return, rather than break so that rtx_cost doesn't
1472 include CONST_COSTS otherwise expand_mult will think that it is
1473 cheaper to synthesise a multiply rather than to use a multiply
1474 instruction. I think this is because the algorithm synth_mult
1475 doesn't take into account the loading of the operands, whereas the
1476 calculation of mult_cost does.
1480 #define RTX_COSTS(RTX, CODE, OUTER_CODE) \
1489 return COSTS_N_INSNS (1); \
1491 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1492 || TARGET_MPYI ? 1 : 14); \
1497 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1500 /* Compute the cost of computing a constant rtl expression RTX
1501 whose rtx-code is CODE. The body of this macro is a portion
1502 of a switch statement. If the code is computed here,
1503 return it with a return statement. Otherwise, break from the switch.
1505 An insn is assumed to cost 4 units.
1506 COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
1508 Some small integers are effectively free for the C40. We should
1509 also consider if we are using the small memory model. With
1510 the big memory model we require an extra insn for a constant
1513 This is used by expand_binop to decide whether to force a constant
1514 into a register. If the cost is greater than 2 and the constant
1515 is used within a short loop, it gets forced into a register.
1516 Ideally, there should be some weighting as to how mnay times it is used
1519 #define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
1521 #define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
1522 || (C) == IOR || (C) == XOR)
1524 #define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
1526 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1528 if (c4x_J_constant (RTX)) \
1531 && OUTER_CODE == AND \
1532 && GET_CODE (RTX) == CONST_INT \
1533 && (INTVAL (RTX) == 255 || INTVAL (RTX) == 65535)) \
1536 && (OUTER_CODE == ASHIFTRT || OUTER_CODE == LSHIFTRT) \
1537 && GET_CODE (RTX) == CONST_INT \
1538 && (INTVAL (RTX) == 16 || INTVAL (RTX) == 24)) \
1540 if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \
1542 if (LOGICAL_CODE_P (OUTER_CODE) \
1543 ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \
1549 case CONST_DOUBLE: \
1550 if (c4x_H_constant (RTX)) \
1552 if (GET_MODE (RTX) == QFmode) \
1557 /* Compute the cost of an address. This is meant to approximate the size
1558 and/or execution delay of an insn using that address. If the cost is
1559 approximated by the RTL complexity, including CONST_COSTS above, as
1560 is usually the case for CISC machines, this macro should not be defined.
1561 For aggressively RISCy machines, only one insn format is allowed, so
1562 this macro should be a constant. The value of this macro only matters
1563 for valid addresses. We handle the most common address without
1564 a call to c4x_address_cost. */
1566 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
1568 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1569 if (REG_P (OP1) && ! REG_P (OP0)) \
1571 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1572 CODE = swap_condition (CODE); \
1575 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1576 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1577 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1578 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1579 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1581 /* Compute extra cost of moving data between one register class
1584 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
1586 /* Memory move cost is same as fast register move. Maybe this should
1589 #define MEMORY_MOVE_COST(M,C,I) 4
1591 /* Branches are kind of expensive (even with delayed branching) so
1592 make their cost higher. */
1594 #define BRANCH_COST 8
1596 #define WORD_REGISTER_OPERATIONS
1598 /* Dividing the Output into Sections. */
1600 #define TEXT_SECTION_ASM_OP "\t.text"
1602 #define DATA_SECTION_ASM_OP "\t.data"
1604 #define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
1606 /* Do not use .init section so __main will be called on startup. This will
1607 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1610 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1613 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1615 #undef EXTRA_SECTIONS
1616 #define EXTRA_SECTIONS in_init, in_fini
1618 #undef EXTRA_SECTION_FUNCTIONS
1619 #define EXTRA_SECTION_FUNCTIONS \
1620 INIT_SECTION_FUNCTION \
1621 FINI_SECTION_FUNCTION
1623 #define INIT_SECTION_FUNCTION \
1624 extern void init_section PARAMS ((void)); \
1628 if (in_section != in_init) \
1630 fprintf (asm_out_file, ";\t.init\n"); \
1631 in_section = in_init; \
1635 #define FINI_SECTION_FUNCTION \
1639 if (in_section != in_fini) \
1641 fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \
1642 in_section = in_fini; \
1646 #define ASM_STABS_OP "\t.stabs\t"
1648 /* Switch into a generic section. */
1649 #define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
1651 /* The TI assembler wants to have hex numbers this way. */
1653 #undef HOST_WIDE_INT_PRINT_HEX
1654 #ifndef HOST_WIDE_INT_PRINT_HEX
1655 # if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
1656 # define HOST_WIDE_INT_PRINT_HEX "0%xh"
1658 # if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
1659 # define HOST_WIDE_INT_PRINT_HEX "0%lxh"
1661 # define HOST_WIDE_INT_PRINT_HEX "0%llxh"
1664 #endif /* ! HOST_WIDE_INT_PRINT_HEX */
1666 /* Overall Framework of an Assembler File. */
1667 /* We need to have a data section we can identify so that we can set
1668 the DP register back to a data pointer in the small memory model.
1669 This is only required for ISRs if we are paranoid that someone
1670 may have quietly changed this register on the sly. */
1672 #define ASM_FILE_START(FILE) \
1674 int dspversion = 0; \
1675 if (TARGET_C30) dspversion = 30; \
1676 if (TARGET_C31) dspversion = 31; \
1677 if (TARGET_C32) dspversion = 32; \
1678 if (TARGET_C40) dspversion = 40; \
1679 if (TARGET_C44) dspversion = 44; \
1680 fprintf (FILE, "\t.version\t%d\n", dspversion); \
1681 fprintf (FILE, "\t.file\t"); \
1685 const char *after_dir = main_input_filename; \
1686 for (p = main_input_filename; *p; p++) \
1688 after_dir = p + 1; \
1689 output_quoted_string (FILE, after_dir); \
1692 output_quoted_string (FILE, main_input_filename); \
1693 fputs ("\n\t.data\ndata_sec:\n", FILE); \
1696 #define ASM_COMMENT_START ";"
1698 #define ASM_APP_ON ""
1699 #define ASM_APP_OFF ""
1701 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
1703 /* Output and Generation of Labels. */
1705 #define NO_DOT_IN_LABEL /* Only required for TI format. */
1707 /* Globalizing directive for a label. */
1708 #define GLOBAL_ASM_OP "\t.global\t"
1710 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1711 c4x_external_ref (NAME)
1713 /* A C statement to output on FILE an assembler pseudo-op to
1714 declare a library function named external.
1715 (Only needed to keep asm30 happy for ___divqf3 etc.) */
1717 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1718 c4x_external_ref (XSTR (FUN, 0))
1720 #define ASM_FILE_END(FILE) \
1723 /* The prefix to add to user-visible assembler symbols. */
1725 #define USER_LABEL_PREFIX "_"
1727 /* This is how to output an internal numbered label where
1728 PREFIX is the class of label and NUM is the number within the class. */
1730 #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
1731 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1733 /* This is how to store into the string LABEL
1734 the symbol_ref name of an internal numbered label where
1735 PREFIX is the class of label and NUM is the number within the class.
1736 This is suitable for output with `assemble_name'. */
1738 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
1739 sprintf (BUFFER, "*%s%d", PREFIX, NUM)
1741 /* Store in OUTPUT a string (made with alloca) containing
1742 an assembler-name for a local static variable named NAME.
1743 LABELNO is an integer which is different for each call. */
1745 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1746 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1747 sprintf ((OUTPUT), "%s$%d", (NAME), (LABELNO)))
1749 /* A C statement to output to the stdio stream STREAM assembler code which
1750 defines (equates) the symbol NAME to have the value VALUE. */
1752 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1754 assemble_name (STREAM, NAME); \
1755 fprintf (STREAM, "\t.set\t%s\n", VALUE); \
1758 /* Output of Dispatch Tables. */
1760 /* This is how to output an element of a case-vector that is absolute. */
1762 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1763 fprintf (FILE, "\t.long\tL%d\n", VALUE);
1765 /* This is how to output an element of a case-vector that is relative. */
1767 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1768 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
1771 #define SIZE_TYPE "unsigned int"
1774 #define PTRDIFF_TYPE "int"
1777 #define WCHAR_TYPE "long int"
1779 #undef WCHAR_TYPE_SIZE
1780 #define WCHAR_TYPE_SIZE 32
1782 #define INT_TYPE_SIZE 32
1783 #define LONG_LONG_TYPE_SIZE 64
1784 #define FLOAT_TYPE_SIZE 32
1785 #define DOUBLE_TYPE_SIZE 32
1786 #define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
1788 /* Output #ident as a .ident. */
1790 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1791 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
1793 /* Output of Uninitialized Variables. */
1795 /* This says how to output an assembler line to define a local
1796 uninitialized variable. */
1798 #undef ASM_OUTPUT_LOCAL
1799 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1800 ( fputs ("\t.bss\t", FILE), \
1801 assemble_name (FILE, (NAME)), \
1802 fprintf (FILE, ",%u\n", (ROUNDED)))
1804 /* This says how to output an assembler line to define a global
1805 uninitialized variable. */
1807 #undef ASM_OUTPUT_COMMON
1808 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1809 ( fputs ("\t.globl\t", FILE), \
1810 assemble_name (FILE, (NAME)), \
1811 fputs ("\n\t.bss\t", FILE), \
1812 assemble_name (FILE, (NAME)), \
1813 fprintf (FILE, ",%u\n", (ROUNDED)))
1815 #undef ASM_OUTPUT_BSS
1816 #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1817 ( fputs ("\t.globl\t", FILE), \
1818 assemble_name (FILE, (NAME)), \
1819 fputs ("\n\t.bss\t", FILE), \
1820 assemble_name (FILE, (NAME)), \
1821 fprintf (FILE, ",%u\n", (SIZE)))
1823 /* Macros Controlling Initialization Routines. */
1825 #define OBJECT_FORMAT_COFF
1826 #define REAL_NM_FILE_NAME "c4x-nm"
1828 /* Output of Assembler Instructions. */
1830 /* Register names when used for integer modes. */
1832 #define REGISTER_NAMES \
1834 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1835 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1836 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1837 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
1840 /* Alternate register names when used for floating point modes. */
1842 #define FLOAT_REGISTER_NAMES \
1844 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1845 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1846 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1847 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
1850 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
1852 /* Determine which codes are valid without a following integer. These must
1853 not be alphabetic. */
1855 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
1857 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
1859 /* C4x specific pragmas. */
1860 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
1861 cpp_register_pragma (PFILE, 0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
1862 cpp_register_pragma (PFILE, 0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
1863 cpp_register_pragma (PFILE, 0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
1864 cpp_register_pragma (PFILE, 0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
1865 cpp_register_pragma (PFILE, 0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
1866 cpp_register_pragma (PFILE, 0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
1867 cpp_register_pragma (PFILE, 0, "FUNC_NEVER_RETURNS", \
1868 c4x_pr_FUNC_NEVER_RETURNS); \
1869 cpp_register_pragma (PFILE, 0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
1870 cpp_register_pragma (PFILE, 0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
1871 cpp_register_pragma (PFILE, 0, "INTERRUPT", c4x_pr_INTERRUPT); \
1874 /* Assembler Commands for Alignment. */
1876 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
1878 for (; c > 0; --c) \
1879 fprintf (FILE,"\t.word\t0\n"); \
1882 #define ASM_NO_SKIP_IN_TEXT 1
1884 /* I'm not sure about this one. FIXME. */
1886 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
1888 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
1891 /* Macros for SDB and DWARF Output (use .sdef instead of .def
1892 to avoid conflict with TI's use of .def). */
1894 #define SDB_DELIM "\n"
1895 #define SDB_DEBUGGING_INFO 1
1897 /* Don't use octal since this can confuse gas for the c4x. */
1898 #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
1900 #define PUT_SDB_DEF(A) \
1901 do { fprintf (asm_out_file, "\t.sdef\t"); \
1902 ASM_OUTPUT_LABELREF (asm_out_file, A); \
1903 fprintf (asm_out_file, SDB_DELIM); } while (0)
1905 #define PUT_SDB_PLAIN_DEF(A) \
1906 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
1908 #define PUT_SDB_BLOCK_START(LINE) \
1909 fprintf (asm_out_file, \
1910 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1911 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1913 #define PUT_SDB_BLOCK_END(LINE) \
1914 fprintf (asm_out_file, \
1915 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1916 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1918 #define PUT_SDB_FUNCTION_START(LINE) \
1919 fprintf (asm_out_file, \
1920 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1921 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1923 /* Note we output relative line numbers for .ef which gas converts
1924 to absolute line numbers. The TI compiler outputs absolute line numbers
1925 in the .sym directive which gas does not support. */
1926 #define PUT_SDB_FUNCTION_END(LINE) \
1927 fprintf (asm_out_file, \
1928 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1929 SDB_DELIM, SDB_DELIM, SDB_DELIM, \
1932 #define PUT_SDB_EPILOGUE_END(NAME) \
1933 do { fprintf (asm_out_file, "\t.sdef\t"); \
1934 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
1935 fprintf (asm_out_file, \
1936 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
1937 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
1939 /* Define this as 1 if `char' should by default be signed; else as 0. */
1941 #define DEFAULT_SIGNED_CHAR 1
1943 /* A function address in a call instruction is a byte address (for
1944 indexing purposes) so give the MEM rtx a byte's mode. */
1946 #define FUNCTION_MODE QImode
1948 #define SLOW_BYTE_ACCESS 0
1950 /* Specify the machine mode that pointers have. After generation of
1951 RTL, the compiler makes no further distinction between pointers and
1952 any other objects of this machine mode. */
1954 #define Pmode QImode
1956 /* On the C4x we can write the following code. We have to clear the cache
1957 every time we execute it because the data in the stack could change.
1970 On the c3x this is a bit more difficult. We have to write self
1971 modifying code here. So we have to clear the cache every time
1972 we execute it because the data in the stack could change.
1974 ldiu TOP_OF_FUNCTION,ar1
1976 or BOTTOM_OF_FUNCTION,ar1
1977 ldiu TOP_OF_STATIC,ar0
1980 or BOTTOM_OF_STATIC,ar0
1985 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
1987 #define TRAMPOLINE_TEMPLATE(FILE) \
1991 fprintf (FILE, "\tldiu\t0,ar1\n"); \
1992 fprintf (FILE, "\tlsh\t16,ar1\n"); \
1993 fprintf (FILE, "\tor\t0,ar1\n"); \
1994 fprintf (FILE, "\tldiu\t0,ar0\n"); \
1995 fprintf (FILE, "\tbud\tar1\n"); \
1996 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1997 fprintf (FILE, "\tor\t0,ar0\n"); \
1998 fprintf (FILE, "\tor\t1000h,st\n"); \
2002 fprintf (FILE, "\tlaj\t$+4\n"); \
2003 fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
2004 fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
2005 fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
2006 fprintf (FILE, "\tbud\tar1\n"); \
2007 fprintf (FILE, "\tnop\n"); \
2008 fprintf (FILE, "\tnop\n"); \
2009 fprintf (FILE, "\tor\t1000h,st\n"); \
2010 fprintf (FILE, "\t.word\t0\n"); \
2011 fprintf (FILE, "\t.word\t0\n"); \
2015 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2020 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
2021 size_int (16), 0, 1); \
2022 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2023 GEN_INT (0x5069), size_int (16), 0, 1); \
2024 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2025 emit_move_insn (gen_rtx (MEM, QImode, \
2026 plus_constant (tramp, 0)), tmp1); \
2027 tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
2028 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2029 GEN_INT (0x1069), size_int (16), 0, 1); \
2030 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2031 emit_move_insn (gen_rtx (MEM, QImode, \
2032 plus_constant (tramp, 2)), tmp1); \
2033 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
2034 size_int (16), 0, 1); \
2035 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2036 GEN_INT (0x5068), size_int (16), 0, 1); \
2037 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2038 emit_move_insn (gen_rtx (MEM, QImode, \
2039 plus_constant (tramp, 3)), tmp1); \
2040 tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
2041 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2042 GEN_INT (0x1068), size_int (16), 0, 1); \
2043 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2044 emit_move_insn (gen_rtx (MEM, QImode, \
2045 plus_constant (tramp, 6)), tmp1); \
2049 emit_move_insn (gen_rtx (MEM, QImode, \
2050 plus_constant (TRAMP, 8)), FNADDR); \
2051 emit_move_insn (gen_rtx (MEM, QImode, \
2052 plus_constant (TRAMP, 9)), CXT); \
2056 /* Specify the machine mode that this machine uses for the index in
2057 the tablejump instruction. */
2059 #define CASE_VECTOR_MODE Pmode
2061 /* Max number of (32-bit) bytes we can move from memory to memory
2062 in one reasonably fast instruction. */
2066 /* MOVE_RATIO is the number of move instructions that is better than a
2069 #define MOVE_RATIO 3
2071 #define BSS_SECTION_ASM_OP "\t.bss"
2073 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2074 fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
2076 /* This is how to output an insn to pop a register from the stack.
2077 It need not be very fast code. */
2079 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2080 fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
2082 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2083 is done just by pretending it is already truncated. */
2085 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2087 /* We need to use direct addressing for large constants and addresses
2088 that cannot fit within an instruction. We must check for these
2089 after after the final jump optimisation pass, since this may
2090 introduce a local_move insn for a SYMBOL_REF. This pass
2091 must come before delayed branch slot filling since it can generate
2092 additional instructions. */
2094 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
2096 #define DBR_OUTPUT_SEQEND(FILE) \
2097 if (final_sequence != NULL_RTX) \
2100 rtx insn = XVECEXP (final_sequence, 0, 0); \
2101 int laj = GET_CODE (insn) == CALL_INSN \
2102 || (GET_CODE (insn) == INSN \
2103 && GET_CODE (PATTERN (insn)) == TRAP_IF);\
2105 count = dbr_sequence_length(); \
2106 while (count < (laj ? 2 : 3)) \
2108 fputs("\tnop\n", FILE); \
2112 fputs("\tpush\tr11\n", FILE); \
2115 #define NO_FUNCTION_CSE
2117 /* We don't want a leading tab. */
2119 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
2121 /* Define the codes that are matched by predicates in c4x.c. */
2123 #define PREDICATE_CODES \
2124 {"fp_zero_operand", {CONST_DOUBLE}}, \
2125 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
2126 {"stik_const_operand", {CONST_INT}}, \
2127 {"not_const_operand", {CONST_INT}}, \
2128 {"reg_operand", {REG, SUBREG}}, \
2129 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
2130 {"r0r1_reg_operand", {REG, SUBREG}}, \
2131 {"r2r3_reg_operand", {REG, SUBREG}}, \
2132 {"ext_low_reg_operand", {REG, SUBREG}}, \
2133 {"ext_reg_operand", {REG, SUBREG}}, \
2134 {"std_reg_operand", {REG, SUBREG}}, \
2135 {"std_or_reg_operand", {REG, SUBREG}}, \
2136 {"addr_reg_operand", {REG, SUBREG}}, \
2137 {"index_reg_operand", {REG, SUBREG}}, \
2138 {"dp_reg_operand", {REG}}, \
2139 {"sp_reg_operand", {REG}}, \
2140 {"st_reg_operand", {REG}}, \
2141 {"rc_reg_operand", {REG}}, \
2142 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
2143 {"dst_operand", {SUBREG, REG, MEM}}, \
2144 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2145 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
2146 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2147 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2148 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
2149 {"nonimmediate_lsrc_operand", {SUBREG, REG, MEM}}, \
2150 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2151 {"par_ind_operand", {MEM}}, \
2152 {"parallel_operand", {SUBREG, REG, MEM}}, \
2153 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2154 {"mem_operand", {MEM}},
2157 /* Define the intrinsic functions for the c3x/c4x. */
2161 /* intrinsic name */
2162 C4X_BUILTIN_FIX, /* fast_ftoi */
2163 C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */
2164 C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */
2165 C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */
2166 C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
2167 C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
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