1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 /* RUN-TIME TARGET SPECIFICATION. */
31 /* Name of the c4x assembler. */
33 #define ASM_PROG "c4x-as"
35 /* Name of the c4x linker. */
37 #define LD_PROG "c4x-ld"
39 /* Define assembler options. */
42 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
43 %{!m30:%{!m40:-m40}}}}}}}} \
56 %{mmemparm:-p} %{mregparm:-r} \
57 %{!mmemparm:%{!mregparm:-r}} \
58 %{mbig:-b} %{msmall:-s} \
59 %{!msmall:%{!mbig:-b}}"
61 /* Define linker options. */
64 %{m30:--architecture c3x} \
65 %{m31:--architecture c3x} \
66 %{m32:--architecture c3x} \
67 %{m33:--architecture c3x} \
68 %{mcpu=30:--architecture c3x} \
69 %{mcpu=31:--architecture c3x} \
70 %{mcpu=32:--architecture c3x} \
71 %{mcpu=33:--architecture c3x}"
73 /* Define C preprocessor options. */
76 %{!m30:%{!m31:%{!m32:%{!m33:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:\
77 %{!mcpu=40:%{!mcpu=44:%{\
78 !m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40}}}}}}}}}}}} \
79 %{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
80 %{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
81 %{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
82 %{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
83 %{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
84 %{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
85 %{mcpu=33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
86 %{m33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
87 %{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
88 %{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
89 %{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
90 %{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
91 %{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
92 %{!mmemparm:%{!mregparm:-D_REGPARM }} \
93 %{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
94 %{!msmall:%{!mbig:-D_BIGMODEL }} \
95 %{finline-functions:-D_INLINE }"
97 /* Specify the end file to link with. */
99 #define ENDFILE_SPEC ""
101 /* Target compilation option flags. */
103 #define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
104 #define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
105 #define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
106 #define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
107 #define C3X_FLAG 0x0000010 /* Emit C3x code. */
108 #define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
109 #define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
110 #define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
111 #define DEVEL_FLAG 0x0000100 /* Enable features under development. */
112 #define RPTB_FLAG 0x0000200 /* Enable repeat block. */
113 #define BK_FLAG 0x0000400 /* Use BK as general register. */
114 #define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
115 #define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
116 #define HOIST_FLAG 0x0002000 /* Force constants into registers. */
117 #define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
118 #define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
119 #define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
120 #define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
121 #define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
122 #define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
124 #define C30_FLAG 0x0100000 /* Emit C30 code. */
125 #define C31_FLAG 0x0200000 /* Emit C31 code. */
126 #define C32_FLAG 0x0400000 /* Emit C32 code. */
127 #define C33_FLAG 0x0400000 /* Emit C33 code. */
128 #define C40_FLAG 0x1000000 /* Emit C40 code. */
129 #define C44_FLAG 0x2000000 /* Emit C44 code. */
131 /* Run-time compilation parameters selecting different hardware subsets.
133 Macro to define tables used to set the flags.
134 This is a list in braces of triplets in braces,
135 each pair being { "NAME", VALUE, "DESCRIPTION" }
136 where VALUE is the bits to set or minus the bits to clear.
137 An empty string NAME is used to identify the default VALUE. */
139 #define TARGET_SWITCHES \
140 { { "small", SMALL_MEMORY_FLAG, \
141 N_("Small memory model") }, \
142 { "big", -SMALL_MEMORY_FLAG, \
143 N_("Big memory model") }, \
144 { "mpyi", MPYI_FLAG, \
145 N_("Use MPYI instruction for C3x") }, \
146 { "no-mpyi", -MPYI_FLAG, \
147 N_("Do not use MPYI instruction for C3x") }, \
148 { "fast-fix", FAST_FIX_FLAG, \
149 N_("Use fast but approximate float to integer conversion") }, \
150 { "no-fast-fix", -FAST_FIX_FLAG, \
151 N_("Use slow but accurate float to integer conversion") }, \
152 { "rpts", RPTS_FLAG, \
153 N_("Enable use of RTPS instruction") }, \
154 { "no-rpts", -RPTS_FLAG, \
155 N_("Disable use of RTPS instruction") }, \
156 { "rptb", RPTB_FLAG, \
157 N_("Enable use of RTPB instruction") }, \
158 { "no-rptb", -RPTB_FLAG, \
159 N_("Disable use of RTPB instruction") }, \
161 N_("Generate code for C30 CPU")}, \
163 N_("Generate code for C31 CPU")}, \
165 N_("Generate code for C32 CPU")}, \
167 N_("Generate code for C33 CPU")}, \
169 N_("Generate code for C40 CPU")}, \
171 N_("Generate code for C44 CPU")}, \
173 N_("Emit code compatible with TI tools")}, \
174 { "no-ti", -TI_FLAG, \
175 N_("Emit code to use GAS extensions")}, \
176 { "paranoid", PARANOID_FLAG, \
177 N_("Save DP across ISR in small memory model") }, \
178 { "no-paranoid", -PARANOID_FLAG, \
179 N_("Don't save DP across ISR in small memory model") }, \
180 { "isr-dp-reload", PARANOID_FLAG, \
181 N_("Save DP across ISR in small memory model") }, \
182 { "no-isr-dp-reload", -PARANOID_FLAG, \
183 N_("Don't save DP across ISR in small memory model") }, \
184 { "memparm", MEMPARM_FLAG, \
185 N_("Pass arguments on the stack") }, \
186 { "regparm", -MEMPARM_FLAG, \
187 N_("Pass arguments in registers") }, \
188 { "devel", DEVEL_FLAG, \
189 N_("Enable new features under development") }, \
190 { "no-devel", -DEVEL_FLAG, \
191 N_("Disable new features under development") }, \
193 N_("Use the BK register as a general purpose register") }, \
194 { "no-bk", -BK_FLAG, \
195 N_("Do not allocate BK register") }, \
197 N_("Enable use of DB instruction") }, \
198 { "no-db", -DB_FLAG, \
199 N_("Disable use of DB instruction") }, \
200 { "debug", DEBUG_FLAG, \
201 N_("Enable debugging") }, \
202 { "no-debug", -DEBUG_FLAG, \
203 N_("Disable debugging") }, \
204 { "hoist", HOIST_FLAG, \
205 N_("Force constants into registers to improve hoisting") }, \
206 { "no-hoist", -HOIST_FLAG, \
207 N_("Don't force constants into registers") }, \
208 { "force", FORCE_FLAG, \
209 N_("Force RTL generation to emit valid 3 operand insns") }, \
210 { "no-force", -FORCE_FLAG, \
211 N_("Allow RTL generation to emit invalid 3 operand insns") }, \
212 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
213 N_("Allow unsigned interation counts for RPTB/DB") }, \
214 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
215 N_("Disallow unsigned iteration counts for RPTB/DB") }, \
216 { "preserve-float", PRESERVE_FLOAT_FLAG, \
217 N_("Preserve all 40 bits of FP reg across call") }, \
218 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
219 N_("Only preserve 32 bits of FP reg across call") }, \
220 { "parallel-insns", PARALLEL_INSN_FLAG, \
221 N_("Enable parallel instructions") }, \
222 { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
223 N_("Disable parallel instructions") }, \
224 { "parallel-mpy", PARALLEL_MPY_FLAG, \
225 N_("Enable MPY||ADD and MPY||SUB instructions") }, \
226 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
227 N_("Disable MPY||ADD and MPY||SUB instructions") }, \
228 { "aliases", ALIASES_FLAG, \
229 N_("Assume that pointers may be aliased") }, \
230 { "no-aliases", -ALIASES_FLAG, \
231 N_("Assume that pointers not aliased") }, \
232 { "", TARGET_DEFAULT, ""} }
234 /* Default target switches. */
236 /* Play safe, not the fastest code. */
237 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
238 | PARALLEL_MPY_FLAG | RPTB_FLAG
241 Max iteration count for RPTB/RPTS is 2^31 + 1.
242 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
243 RPTS blocks interrupts. */
246 extern int target_flags;
248 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
249 #define TARGET_SMALL_REG_CLASS 0
251 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
252 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
253 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
254 #define TARGET_RPTS (target_flags & RPTS_FLAG)
255 #define TARGET_TI (target_flags & TI_FLAG)
256 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
257 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
258 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
259 #define TARGET_RPTB (target_flags & RPTB_FLAG \
261 #define TARGET_BK (target_flags & BK_FLAG)
262 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
263 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
264 #define TARGET_HOIST (target_flags & HOIST_FLAG)
265 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
266 #define TARGET_FORCE (target_flags & FORCE_FLAG)
267 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
268 #define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
270 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
271 && (target_flags & PARALLEL_MPY_FLAG))
272 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
274 #define TARGET_C3X (target_flags & C3X_FLAG)
275 #define TARGET_C30 (target_flags & C30_FLAG)
276 #define TARGET_C31 (target_flags & C31_FLAG)
277 #define TARGET_C32 (target_flags & C32_FLAG)
278 #define TARGET_C33 (target_flags & C33_FLAG)
279 #define TARGET_C40 (target_flags & C40_FLAG)
280 #define TARGET_C44 (target_flags & C44_FLAG)
282 /* Define some options to control code generation. */
283 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
284 #define TARGET_EXPOSE_LDP 0
286 /* -mrpts allows the use of the RPTS instruction irregardless.
287 -mrpts=max-cycles will use RPTS if the number of cycles is constant
288 and less than max-cycles. */
290 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
292 #define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED)
294 /* -mcpu=XX with XX = target DSP version number. */
296 /* This macro is similar to `TARGET_SWITCHES' but defines names of
297 command options that have values. Its definition is an
298 initializer with a subgrouping for each command option.
300 Each subgrouping contains a string constant, that defines the
301 fixed part of the option name, and the address of a variable.
302 The variable, type `char *', is set to the variable part of the
303 given option if the fixed part matches. The actual option name
304 is made by appending `-m' to the specified name.
306 Here is an example which defines `-mshort-data-NUMBER'. If the
307 given option is `-mshort-data-512', the variable `m88k_short_data'
308 will be set to the string `"512"'.
310 extern char *m88k_short_data;
311 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
313 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
315 #define TARGET_OPTIONS \
316 { {"rpts=", &c4x_rpts_cycles_string, \
317 N_("Specify maximum number of iterations for RPTS") }, \
318 {"cpu=", &c4x_cpu_version_string, \
319 N_("Select CPU to generate code for") } }
321 /* Sometimes certain combinations of command options do not make sense
322 on a particular target machine. You can define a macro
323 `OVERRIDE_OPTIONS' to take account of this. This macro, if
324 defined, is executed once just after all the command options have
327 #define OVERRIDE_OPTIONS c4x_override_options ()
329 /* Define this to change the optimizations performed by default. */
331 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
333 /* Run Time Target Specification. */
335 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
337 /* Storage Layout. */
339 #define BITS_BIG_ENDIAN 0
340 #define BYTES_BIG_ENDIAN 0
341 #define WORDS_BIG_ENDIAN 0
343 /* Technically, we are little endian, but we put the floats out as
344 whole longs and this makes GCC put them out in the right order. */
346 #define FLOAT_WORDS_BIG_ENDIAN 1
348 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
349 all integral and floating point data types are stored in memory as
350 32-bits (floating point types can be stored as 40-bits in the
351 extended precision registers), so sizeof(char) = sizeof(short) =
352 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
354 #define BITS_PER_UNIT 32
355 #define BITS_PER_WORD 32
356 #define UNITS_PER_WORD 1
357 #define POINTER_SIZE 32
358 #define PARM_BOUNDARY 32
359 #define STACK_BOUNDARY 32
360 #define FUNCTION_BOUNDARY 32
361 #define BIGGEST_ALIGNMENT 32
362 #define EMPTY_FIELD_BOUNDARY 32
363 #define STRICT_ALIGNMENT 0
364 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
365 #define MAX_FIXED_MODE_SIZE 64 /* HImode. */
367 /* If a structure has a floating point field then force structure
369 #define STRUCT_FORCE_BLK(FIELD) (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE)
371 /* Number of bits in the high and low parts of a two stage
372 load of an immediate constant. */
373 #define BITS_PER_HIGH 16
374 #define BITS_PER_LO_SUM 16
376 /* Use the internal floating point stuff in the compiler and not the
377 host floating point stuff. */
379 #define REAL_ARITHMETIC
381 /* Define register numbers. */
383 /* Extended-precision registers. */
394 /* Auxiliary (address) registers. */
405 /* Data page register. */
409 /* Index registers. */
414 /* Block size register. */
422 /* Status register. */
426 /* Misc. interrupt registers. */
428 #define DIE_REGNO 22 /* C4x only. */
429 #define IE_REGNO 22 /* C3x only. */
430 #define IIE_REGNO 23 /* C4x only. */
431 #define IF_REGNO 23 /* C3x only. */
432 #define IIF_REGNO 24 /* C4x only. */
433 #define IOF_REGNO 24 /* C3x only. */
435 /* Repeat block registers. */
441 /* Additional extended-precision registers. */
443 #define R8_REGNO 28 /* C4x only. */
444 #define R9_REGNO 29 /* C4x only. */
445 #define R10_REGNO 30 /* C4x only. */
446 #define R11_REGNO 31 /* C4x only. */
448 #define FIRST_PSEUDO_REGISTER 32
450 /* Extended precision registers (low set). */
452 #define IS_R0R1_REGNO(r) \
453 ((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
454 #define IS_R2R3_REGNO(r) \
455 ((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
456 #define IS_EXT_LOW_REGNO(r) \
457 ((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
459 /* Extended precision registers (high set). */
461 #define IS_EXT_HIGH_REGNO(r) \
463 && ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
465 /* Address registers. */
467 #define IS_AUX_REGNO(r) \
468 ((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
469 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
470 #define IS_DP_REGNO(r) ((r) == DP_REGNO)
471 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
472 #define IS_SP_REGNO(r) ((r) == SP_REGNO)
473 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
475 /* Misc registers. */
477 #define IS_ST_REGNO(r) ((r) == ST_REGNO)
478 #define IS_RC_REGNO(r) ((r) == RC_REGNO)
479 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
481 /* Composite register sets. */
483 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
484 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
485 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
486 || IS_REPEAT_REGNO(r) \
489 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
490 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
492 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
493 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
494 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
495 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
496 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
497 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
498 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
499 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
500 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
501 || IS_PSEUDO_REGNO(r))
502 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
503 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
504 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
505 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
507 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
508 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
509 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
510 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
511 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
512 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
513 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
515 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
516 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
517 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
518 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
519 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
520 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
522 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
523 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
524 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
525 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
526 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
527 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
529 /* 1 for registers that have pervasive standard uses
530 and are not available for the register allocator. */
532 #define FIXED_REGISTERS \
534 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
535 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
536 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
537 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
540 /* 1 for registers not available across function calls.
541 These must include the FIXED_REGISTERS and also any
542 registers that can be used without being saved.
543 The latter must include the registers where values are returned
544 and the register where structure-value addresses are passed.
545 Aside from that, you can include as many other registers as you like.
547 Note that the extended precision registers are only saved in some
548 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
549 get clobbered for a given regno. */
551 #define CALL_USED_REGISTERS \
553 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
554 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
555 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
559 /* Macro to conditionally modify fixed_regs/call_used_regs. */
561 #define CONDITIONAL_REGISTER_USAGE \
565 fixed_regs[BK_REGNO] = 1; \
566 call_used_regs[BK_REGNO] = 1; \
567 c4x_regclass_map[BK_REGNO] = NO_REGS; \
573 reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
574 reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
575 reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
577 for (i = R8_REGNO; i <= R11_REGNO; i++) \
579 fixed_regs[i] = call_used_regs[i] = 1; \
580 c4x_regclass_map[i] = NO_REGS; \
583 if (TARGET_PRESERVE_FLOAT) \
585 c4x_caller_save_map[R6_REGNO] = HFmode; \
586 c4x_caller_save_map[R7_REGNO] = HFmode; \
590 /* Order of Allocation of Registers. */
592 /* List the order in which to allocate registers. Each register must be
593 listed once, even those in FIXED_REGISTERS.
595 First allocate registers that don't need preservation across calls,
596 except index and address registers. Then allocate data registers
597 that require preservation across calls (even though this invokes an
598 extra overhead of having to save/restore these registers). Next
599 allocate the address and index registers, since using these
600 registers for arithmetic can cause pipeline stalls. Finally
601 allocated the fixed registers which won't be allocated anyhow. */
603 #define REG_ALLOC_ORDER \
604 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
605 R9_REGNO, R10_REGNO, R11_REGNO, \
606 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
607 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
608 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
609 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
610 IR0_REGNO, IR1_REGNO, \
611 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
614 /* Determine which register classes are very likely used by spill registers.
615 local-alloc.c won't allocate pseudos that have these classes as their
616 preferred class unless they are "preferred or nothing". */
618 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
620 /* CCmode is wrongly defined in machmode.def It should have a size
621 of UNITS_PER_WORD. */
623 #define HARD_REGNO_NREGS(REGNO, MODE) \
624 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
625 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
628 /* A C expression that is nonzero if the hard register REGNO is preserved
629 across a call in mode MODE. This does not have to include the call used
632 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
633 ((((REGNO) == R6_REGNO || (REGNO) == R7_REGNO) && ! ((MODE) == QFmode)) \
634 || (((REGNO) == R4_REGNO || (REGNO) == R5_REGNO || (REGNO == R8_REGNO)) \
635 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
637 /* Specify the modes required to caller save a given hard regno. */
639 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS) (c4x_caller_save_map[REGNO])
641 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
643 /* A C expression that is nonzero if it is desirable to choose
644 register allocation so as to avoid move instructions between a
645 value of mode MODE1 and a value of mode MODE2.
647 Value is 1 if it is a good idea to tie two pseudo registers
648 when one has mode MODE1 and one has mode MODE2.
649 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
650 for any hard reg, then this must be 0 for correct output. */
652 #define MODES_TIEABLE_P(MODE1, MODE2) 0
655 /* Define the classes of registers for register constraints in the
656 machine description. Also define ranges of constants.
658 One of the classes must always be named ALL_REGS and include all hard regs.
659 If there is more than one class, another class must be named NO_REGS
660 and contain no registers.
662 The name GENERAL_REGS must be the name of a class (or an alias for
663 another name such as ALL_REGS). This is the class of registers
664 that is allowed by "g" or "r" in a register constraint.
665 Also, registers outside this class are allocated only when
666 instructions express preferences for them.
668 The classes must be numbered in nondecreasing order; that is,
669 a larger-numbered class must never be contained completely
670 in a smaller-numbered class.
672 For any two classes, it is very desirable that there be another
673 class that represents their union. */
678 R0R1_REGS, /* 't'. */
679 R2R3_REGS, /* 'u'. */
680 EXT_LOW_REGS, /* 'q'. */
682 ADDR_REGS, /* 'a'. */
683 INDEX_REGS, /* 'x'. */
689 GENERAL_REGS, /* 'r'. */
696 #define N_REG_CLASSES (int) LIM_REG_CLASSES
698 #define REG_CLASS_NAMES \
718 /* Define which registers fit in which classes.
719 This is an initializer for a vector of HARD_REG_SET
720 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
721 since the register allocator will often choose a general register
722 in preference to RC for the decrement_and_branch_on_count pattern. */
724 #define REG_CLASS_CONTENTS \
726 {0x00000000}, /* No registers. */ \
727 {0x00000003}, /* 't' R0-R1 . */ \
728 {0x0000000c}, /* 'u' R2-R3 . */ \
729 {0x000000ff}, /* 'q' R0-R7 . */ \
730 {0xf00000ff}, /* 'f' R0-R11 */ \
731 {0x0000ff00}, /* 'a' AR0-AR7. */ \
732 {0x00060000}, /* 'x' IR0-IR1. */ \
733 {0x00080000}, /* 'k' BK. */ \
734 {0x00100000}, /* 'b' SP. */ \
735 {0x08000000}, /* 'v' RC. */ \
736 {0x0800ff00}, /* RC,AR0-AR7. */ \
737 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
738 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
739 {0x00010000}, /* 'z' DP. */ \
740 {0x00200000}, /* 'y' ST. */ \
741 {0xffffffff}, /* All registers. */ \
744 /* The same information, inverted:
745 Return the class number of the smallest class containing
746 reg number REGNO. This could be a conditional expression
747 or could index an array. */
749 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
751 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
752 explicitly used in the rtl is kept as short as possible.
754 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
755 is defined since the MPY|ADD insns require the classes R0R1_REGS and
756 R2R3_REGS which are used by the function return registers (R0,R1) and
757 the register arguments (R2,R3), respectively. I'm reluctant to define
758 this macro since it stomps on many potential optimisations. Ideally
759 it should have a register class argument so that not all the register
760 classes gets penalised for the sake of a naughty few... For long
761 double arithmetic we need two additional registers that we can use as
764 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
766 #define BASE_REG_CLASS ADDR_REGS
767 #define INDEX_REG_CLASS INDEX_REGS
770 Register constraints for the C4x
772 a - address reg (ar0-ar7)
774 c - other gp int-only reg
775 d - data/int reg (equiv. to f)
777 h - data/long double reg (equiv. to f)
782 v - repeat count (rc)
783 x - index register (ir0-ir1)
784 y - status register (st)
787 Memory/constant constraints for the C4x
789 G - short float 16-bit
790 I - signed 16-bit constant (sign extended)
791 J - signed 8-bit constant (sign extended) (C4x only)
792 K - signed 5-bit constant (sign extended) (C4x only for stik)
793 L - unsigned 16-bit constant
794 M - unsigned 8-bit constant (C4x only)
795 N - ones complement of unsigned 16-bit constant
796 Q - indirect arx + 9-bit signed displacement
797 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
798 R - indirect arx + 5-bit unsigned displacement (C4x only)
799 S - indirect arx + 0, 1, or irn displacement
800 T - direct symbol ref
801 > - indirect with autoincrement
802 < - indirect with autodecrement
803 } - indirect with post-modify
804 { - indirect with pre-modify
807 #define REG_CLASS_FROM_LETTER(CC) \
808 ( ((CC) == 'a') ? ADDR_REGS \
809 : ((CC) == 'b') ? SP_REG \
810 : ((CC) == 'c') ? INT_REGS \
811 : ((CC) == 'd') ? EXT_REGS \
812 : ((CC) == 'f') ? EXT_REGS \
813 : ((CC) == 'h') ? EXT_REGS \
814 : ((CC) == 'k') ? BK_REG \
815 : ((CC) == 'q') ? EXT_LOW_REGS \
816 : ((CC) == 't') ? R0R1_REGS \
817 : ((CC) == 'u') ? R2R3_REGS \
818 : ((CC) == 'v') ? RC_REG \
819 : ((CC) == 'x') ? INDEX_REGS \
820 : ((CC) == 'y') ? ST_REG \
821 : ((CC) == 'z') ? DP_REG \
824 /* These assume that REGNO is a hard or pseudo reg number.
825 They give nonzero only if REGNO is a hard reg of the suitable class
826 or a pseudo reg currently allocated to a suitable hard reg.
827 Since they use reg_renumber, they are safe only once reg_renumber
828 has been allocated, which happens in local-alloc.c. */
830 #define REGNO_OK_FOR_BASE_P(REGNO) \
831 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
833 #define REGNO_OK_FOR_INDEX_P(REGNO) \
834 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
836 /* If we have to generate framepointer + constant prefer an ADDR_REGS
837 register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
839 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
840 (GET_CODE (X) == PLUS \
841 && GET_MODE (X) == Pmode \
842 && GET_CODE (XEXP ((X), 0)) == REG \
843 && GET_MODE (XEXP ((X), 0)) == Pmode \
844 && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
845 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
846 ? ADDR_REGS : (CLASS))
848 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
850 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
852 #define CLASS_MAX_NREGS(CLASS, MODE) \
853 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
854 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
856 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
858 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
860 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
862 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
864 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
866 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
868 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
870 #define IS_HIGH_CONST(VAL) \
871 (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
874 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
876 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
878 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
879 && IS_DISP1_CONST (VAL + 1))
881 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
882 && IS_DISP8_CONST (VAL + 1))
884 #define CONST_OK_FOR_LETTER_P(VAL, C) \
885 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
886 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
887 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
888 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
889 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
890 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
891 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
894 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
895 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
896 : ((C) == 'H') ? (c4x_H_constant (OP)) \
899 #define EXTRA_CONSTRAINT(OP, C) \
900 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
901 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
902 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
903 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
904 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
907 #define SMALL_CONST(VAL, insn) \
908 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
909 ? IS_INT16_CONST (VAL) \
910 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
911 ? IS_NOT_UINT16_CONST (VAL) \
912 : ( (get_attr_data (insn) == DATA_HIGH_16) \
913 ? IS_HIGH_CONST (VAL) \
914 : IS_UINT16_CONST (VAL) \
920 I. Routine calling with arguments in registers
921 ----------------------------------------------
923 The TI C3x compiler has a rather unusual register passing algorithm.
924 Data is passed in the following registers (in order):
926 AR2, R2, R3, RC, RS, RE
928 However, the first and second floating point values are always in R2
929 and R3 (and all other floats are on the stack). Structs are always
930 passed on the stack. If the last argument is an ellipsis, the
931 previous argument is passed on the stack so that its address can be
932 taken for the stdargs macros.
934 Because of this, we have to pre-scan the list of arguments to figure
935 out what goes where in the list.
937 II. Routine calling with arguments on stack
938 -------------------------------------------
940 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
941 variables loc0, loc1, and loc2. After the function prologue has
942 been executed, the stack frame will look like:
944 [stack grows towards increasing addresses]
946 5 I saved reg1 I <= SP points here
956 0 I old FP I <= FP (AR3) points here
967 All local variables (locn) are accessible by means of +FP(n+1)
968 addressing, where n is the local variable number.
970 All stack arguments (argn) are accessible by means of -FP(n-2).
972 The stack pointer (SP) points to the last register saved in the
975 Note that a push instruction performs a preincrement of the stack
976 pointer. (STACK_PUSH_CODE == PRE_INC)
978 III. Registers used in function calling convention
979 --------------------------------------------------
981 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
982 R6...R7 (only by PUSHF, i.e. upper 32 bits)
985 (Because of this model, we only assign FP values in R6, R7 and
986 only assign integer values in R4, R5.)
988 These registers are saved at each function entry and restored at
989 the exit. Also it is expected any of these not affected by any
990 call to user-defined (not service) functions.
992 Not preserved across calls: R0...R3
993 R4...R5 (upper 8 bits)
994 R6...R7 (lower 8 bits)
995 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
997 These registers are used arbitrary in a function without being preserved.
998 It is also expected that any of these can be clobbered by any call.
1000 Not used by GCC (except for in user "asm" statements):
1001 IE (DIE), IF (IIE), IOF (IIF)
1003 These registers are never used by GCC for any data, but can be used
1004 with "asm" statements. */
1009 /* Basic Stack Layout. */
1011 /* The stack grows upward, stack frame grows upward, and args grow
1014 #define STARTING_FRAME_OFFSET C4X_LOC0
1015 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
1016 #define ARGS_GROW_DOWNWARD
1017 #define STACK_POINTER_OFFSET 1
1019 /* Define this if pushing a word on the stack
1020 makes the stack pointer a smaller address. */
1022 /* #define STACK_GROWS_DOWNWARD. */
1023 /* Like the dsp16xx, i370, i960, and we32k ports. */
1025 /* Define this if the nominal address of the stack frame
1026 is at the high-address end of the local variables;
1027 that is, each additional local variable allocated
1028 goes at a more negative offset in the frame. */
1030 /* #define FRAME_GROWS_DOWNWARD. */
1033 /* Registers That Address the Stack Frame. */
1035 #define STACK_POINTER_REGNUM SP_REGNO /* SP. */
1036 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
1037 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
1038 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
1040 /* Eliminating Frame Pointer and Arg Pointer. */
1042 #define FRAME_POINTER_REQUIRED 0
1044 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1048 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1049 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1050 offset += TARGET_PRESERVE_FLOAT \
1051 && ((regno == R6_REGNO) || (regno == R7_REGNO)) \
1053 (DEPTH) = -(offset + get_frame_size ()); \
1056 /* This is a hack... We need to specify a register. */
1057 #define ELIMINABLE_REGS \
1058 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1060 #define CAN_ELIMINATE(FROM, TO) \
1061 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1062 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1064 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1068 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1069 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1070 offset += TARGET_PRESERVE_FLOAT \
1071 && ((regno == R6_REGNO) || (regno == R7_REGNO)) \
1073 (OFFSET) = -(offset + get_frame_size ()); \
1077 /* Passing Function Arguments on the Stack. */
1080 #define PUSH_ROUNDING(BYTES) (BYTES)
1082 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1084 /* The following structure is used by calls.c, function.c, c4x.c. */
1086 typedef struct c4x_args
1099 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1100 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1102 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1103 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1105 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1106 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1108 /* Define the profitability of saving registers around calls.
1109 We disable caller save to avoid a bug in flow.c (this also affects
1110 other targets such as m68k). Since we must use stf/sti,
1111 the profitability is marginal anyway. */
1113 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1115 /* Never pass data by reference. */
1117 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1119 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1121 /* 1 if N is a possible register number for function argument passing. */
1123 #define FUNCTION_ARG_REGNO_P(REGNO) \
1124 ( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
1125 || ((REGNO) == R2_REGNO) /* R2. */ \
1126 || ((REGNO) == R3_REGNO) /* R3. */ \
1127 || ((REGNO) == RC_REGNO) /* RC. */ \
1128 || ((REGNO) == RS_REGNO) /* RS. */ \
1129 || ((REGNO) == RE_REGNO)) /* RE. */ \
1133 /* How Scalar Function Values Are Returned. */
1135 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1136 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
1138 #define LIBCALL_VALUE(MODE) \
1139 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0. */
1141 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1143 /* How Large Values Are Returned. */
1145 #define DEFAULT_PCC_STRUCT_RETURN 0
1146 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0. */
1148 /* Varargs handling. */
1150 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1151 c4x_va_start (stdarg, valist, nextarg)
1153 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1154 c4x_va_arg (valist, type)
1156 /* Generating Code for Profiling. */
1158 /* Note that the generated assembly uses the ^ operator to load the 16
1159 MSBs of the address. This is not supported by the TI assembler.
1160 The FUNCTION profiler needs a function mcount which gets passed
1161 a pointer to the LABELNO. */
1163 #define FUNCTION_PROFILER(FILE, LABELNO) \
1166 fprintf (FILE, "\tpush\tar2\n"); \
1167 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1168 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1169 fprintf (FILE, "\tcall\tmcount\n"); \
1170 fprintf (FILE, "\tpop\tar2\n"); \
1174 fprintf (FILE, "\tpush\tar2\n"); \
1175 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1176 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1177 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1178 fprintf (FILE, "\tcall\tmcount\n"); \
1179 fprintf (FILE, "\tpop\tar2\n"); \
1182 /* There are three profiling modes for basic blocks available.
1183 The modes are selected at compile time by using the options
1184 -a or -ax of the gnu compiler.
1185 The variable `profile_block_flag' will be set according to the
1188 profile_block_flag == 0, no option used:
1192 profile_block_flag == 1, -a option used.
1194 Count frequency of execution of every basic block.
1196 profile_block_flag == 2, -ax option used.
1198 Generate code to allow several different profiling modes at run time.
1199 Available modes are:
1200 Produce a trace of all basic blocks.
1201 Count frequency of jump instructions executed.
1202 In every mode it is possible to start profiling upon entering
1203 certain functions and to disable profiling of some other functions.
1205 The result of basic-block profiling will be written to a file `bb.out'.
1206 If the -ax option is used parameters for the profiling will be read
1211 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCKNO) \
1212 if (profile_block_flag == 2) \
1216 fprintf (FILE, "\tpush\tst\n"); \
1217 fprintf (FILE, "\tpush\tar2\n"); \
1218 fprintf (FILE, "\tpush\tr2\n"); \
1219 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1220 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1221 if (BLOCKNO > 32767) \
1223 fprintf (FILE, "\tldhi\t%d,r2\n", (BLOCKNO) >> 16); \
1224 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1228 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1230 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1231 fprintf (FILE, "\tpop\tr2\n"); \
1232 fprintf (FILE, "\tpop\tar2\n"); \
1233 fprintf (FILE, "\tpop\tst\n"); \
1237 fprintf (FILE, "\tpush\tst\n"); \
1238 fprintf (FILE, "\tpush\tar2\n"); \
1239 fprintf (FILE, "\tpush\tr2\n"); \
1240 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1241 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1242 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1243 if (BLOCKNO > 32767) \
1245 fprintf (FILE, "\tldi\t%d,r2\n", (BLOCKNO) >> 16); \
1246 fprintf (FILE, "\tlsh\t16,r2\n"); \
1247 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1251 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1253 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1254 fprintf (FILE, "\tpop\tr2\n"); \
1255 fprintf (FILE, "\tpop\tar2\n"); \
1256 fprintf (FILE, "\tpop\tst\n"); \
1263 fprintf (FILE, "\tpush\tst\n"); \
1264 fprintf (FILE, "\tpush\tar2\n"); \
1265 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1266 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1267 fprintf (FILE, "\tcmpi\t0,*ar2\n"); \
1268 fprintf (FILE, "\tbne\t$+2\n"); \
1269 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1270 fprintf (FILE, "\tpop\tar2\n"); \
1271 fprintf (FILE, "\tpop\tst\n"); \
1275 fprintf (FILE, "\tpush\tst\n"); \
1276 fprintf (FILE, "\tpush\tar2\n"); \
1277 fprintf (FILE, "\tpush\tr2\n"); \
1278 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1279 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1280 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1281 fprintf (FILE, "\tldi\t*ar2,r2\n"); \
1282 fprintf (FILE, "\tbne\t$+2\n"); \
1283 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1284 fprintf (FILE, "\tpop\tr2\n"); \
1285 fprintf (FILE, "\tpop\tar2\n"); \
1286 fprintf (FILE, "\tpop\tst\n"); \
1290 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1291 if (profile_block_flag == 2) \
1295 fprintf (FILE, "\tpush\tst\n"); \
1296 fprintf (FILE, "\tpush\tar2\n"); \
1297 fprintf (FILE, "\tpush\tar0\n"); \
1298 fprintf (FILE, "\tldhi\t^___bb,ar2\n"); \
1299 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1300 if (BLOCKNO > 32767) \
1302 fprintf (FILE, "\tldhi\t%d,ar0\n", (BLOCKNO) >> 16);\
1303 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1307 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1309 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1310 fprintf (FILE, "\tldhi\t^LPBX0,ar0\n"); \
1311 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1312 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1313 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1314 fprintf (FILE, "\tpop\tar0\n"); \
1315 fprintf (FILE, "\tpop\tar2\n"); \
1316 fprintf (FILE, "\tpop\tst\n"); \
1320 fprintf (FILE, "\tpush\tst\n"); \
1321 fprintf (FILE, "\tpush\tar2\n"); \
1322 fprintf (FILE, "\tpush\tar0\n"); \
1323 fprintf (FILE, "\tldiu\t^___bb,ar2\n"); \
1324 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1325 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1326 if (BLOCKNO > 32767) \
1328 fprintf (FILE, "\tldi\t%d,ar0\n", (BLOCKNO) >> 16); \
1329 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1330 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1334 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1336 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1337 fprintf (FILE, "\tldiu\t^LPBX0,ar0\n"); \
1338 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1339 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1340 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1341 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1342 fprintf (FILE, "\tpop\tar0\n"); \
1343 fprintf (FILE, "\tpop\tar2\n"); \
1344 fprintf (FILE, "\tpop\tst\n"); \
1351 fprintf (FILE, "\tpush\tar2\n"); \
1352 fprintf (FILE, "\tpush\tar0\n"); \
1353 fprintf (FILE, "\tldhi\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1354 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1355 fprintf (FILE, "\taddi3\t1,*ar2,ar0\n"); \
1356 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1357 fprintf (FILE, "\tpop\tar0\n"); \
1358 fprintf (FILE, "\tpop\tar2\n"); \
1362 fprintf (FILE, "\tpush\tar2\n"); \
1363 fprintf (FILE, "\tpush\tar0\n"); \
1364 fprintf (FILE, "\tldiu\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1365 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1366 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1367 fprintf (FILE, "\tldiu\t*ar2,ar0\n"); \
1368 fprintf (FILE, "\taddi\t1,ar0\n"); \
1369 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1370 fprintf (FILE, "\tpop\tar0\n"); \
1371 fprintf (FILE, "\tpop\tar2\n"); \
1375 #define FUNCTION_BLOCK_PROFILER_EXIT \
1377 emit_insn (gen_push_st ()); \
1378 emit_insn (gen_pushqi ( \
1379 gen_rtx_REG (QImode, AR2_REGNO))); \
1380 emit_call_insn (gen_nodb_call ( \
1381 gen_rtx_SYMBOL_REF (QImode, "__bb_trace_ret")));\
1382 emit_insn (gen_popqi_unspec ( \
1383 gen_rtx_REG (QImode, AR2_REGNO))); \
1384 emit_insn (gen_pop_st ()); \
1387 #define MACHINE_STATE_SAVE(ID) \
1398 asm(" .if .BIGMODEL"); \
1407 asm(" .if .tms320C40"); \
1411 asm(" pushf r10"); \
1413 asm(" pushf r11"); \
1416 #define MACHINE_STATE_RESTORE(ID) \
1417 asm(" .if .tms320C40"); \
1431 asm(" .if .BIGMODEL"); \
1445 /* Implicit Calls to Library Routines. */
1447 #define MULQI3_LIBCALL "__mulqi3"
1448 #define DIVQI3_LIBCALL "__divqi3"
1449 #define UDIVQI3_LIBCALL "__udivqi3"
1450 #define MODQI3_LIBCALL "__modqi3"
1451 #define UMODQI3_LIBCALL "__umodqi3"
1453 #define DIVQF3_LIBCALL "__divqf3"
1455 #define MULHF3_LIBCALL "__mulhf3"
1456 #define DIVHF3_LIBCALL "__divhf3"
1458 #define MULHI3_LIBCALL "__mulhi3"
1459 #define SMULHI3_LIBCALL "__smulhi3_high"
1460 #define UMULHI3_LIBCALL "__umulhi3_high"
1461 #define DIVHI3_LIBCALL "__divhi3"
1462 #define UDIVHI3_LIBCALL "__udivhi3"
1463 #define MODHI3_LIBCALL "__modhi3"
1464 #define UMODHI3_LIBCALL "__umodhi3"
1466 #define FLOATHIQF2_LIBCALL "__floathiqf2"
1467 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
1468 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
1469 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
1471 #define FLOATHIHF2_LIBCALL "__floathihf2"
1472 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
1473 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
1474 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
1476 #define FFS_LIBCALL "__ffs"
1478 #define INIT_TARGET_OPTABS \
1480 smul_optab->handlers[(int) QImode].libfunc \
1481 = init_one_libfunc (MULQI3_LIBCALL); \
1482 sdiv_optab->handlers[(int) QImode].libfunc \
1483 = init_one_libfunc (DIVQI3_LIBCALL); \
1484 udiv_optab->handlers[(int) QImode].libfunc \
1485 = init_one_libfunc (UDIVQI3_LIBCALL); \
1486 smod_optab->handlers[(int) QImode].libfunc \
1487 = init_one_libfunc (MODQI3_LIBCALL); \
1488 umod_optab->handlers[(int) QImode].libfunc \
1489 = init_one_libfunc (UMODQI3_LIBCALL); \
1490 flodiv_optab->handlers[(int) QFmode].libfunc \
1491 = init_one_libfunc (DIVQF3_LIBCALL); \
1492 smul_optab->handlers[(int) HFmode].libfunc \
1493 = init_one_libfunc (MULHF3_LIBCALL); \
1494 flodiv_optab->handlers[(int) HFmode].libfunc \
1495 = init_one_libfunc (DIVHF3_LIBCALL); \
1496 smul_optab->handlers[(int) HImode].libfunc \
1497 = init_one_libfunc (MULHI3_LIBCALL); \
1498 sdiv_optab->handlers[(int) HImode].libfunc \
1499 = init_one_libfunc (DIVHI3_LIBCALL); \
1500 udiv_optab->handlers[(int) HImode].libfunc \
1501 = init_one_libfunc (UDIVHI3_LIBCALL); \
1502 smod_optab->handlers[(int) HImode].libfunc \
1503 = init_one_libfunc (MODHI3_LIBCALL); \
1504 umod_optab->handlers[(int) HImode].libfunc \
1505 = init_one_libfunc (UMODHI3_LIBCALL); \
1506 ffs_optab->handlers[(int) QImode].libfunc \
1507 = init_one_libfunc (FFS_LIBCALL); \
1509 = init_one_libfunc(SMULHI3_LIBCALL); \
1511 = init_one_libfunc(UMULHI3_LIBCALL); \
1512 fix_truncqfhi2_libfunc \
1513 = init_one_libfunc(FIX_TRUNCQFHI2_LIBCALL); \
1514 fixuns_truncqfhi2_libfunc \
1515 = init_one_libfunc(FIXUNS_TRUNCQFHI2_LIBCALL); \
1516 fix_trunchfhi2_libfunc \
1517 = init_one_libfunc(FIX_TRUNCHFHI2_LIBCALL); \
1518 fixuns_trunchfhi2_libfunc \
1519 = init_one_libfunc(FIXUNS_TRUNCHFHI2_LIBCALL); \
1520 floathiqf2_libfunc \
1521 = init_one_libfunc(FLOATHIQF2_LIBCALL); \
1522 floatunshiqf2_libfunc \
1523 = init_one_libfunc(FLOATUNSHIQF2_LIBCALL); \
1524 floathihf2_libfunc \
1525 = init_one_libfunc(FLOATHIHF2_LIBCALL); \
1526 floatunshihf2_libfunc \
1527 = init_one_libfunc(FLOATUNSHIHF2_LIBCALL); \
1530 #define TARGET_MEM_FUNCTIONS
1532 /* Add any extra modes needed to represent the condition code.
1534 On the C4x, we have a "no-overflow" mode which is used when an ADD,
1535 SUB, NEG, or MPY insn is used to set the condition code. This is
1536 to prevent the combiner from optimising away a following CMP of the
1537 result with zero when a signed conditional branch or load insn
1540 The problem is a subtle one and deals with the manner in which the
1541 negative condition (N) flag is used on the C4x. This flag does not
1542 reflect the status of the actual result but of the ideal result had
1543 no overflow occured (when considering signed operands).
1545 For example, 0x7fffffff + 1 => 0x80000000 Z=0 V=1 N=0 C=0. Here
1546 the flags reflect the untruncated result, not the actual result.
1547 While the actual result is less than zero, the N flag is not set
1548 since the ideal result of the addition without truncation would
1551 Note that the while the N flag is handled differently to most other
1552 architectures, the use of it is self consistent and is not the
1553 cause of the problem.
1555 Logical operations set the N flag to the MSB of the result so if
1556 the result is negative, N is 1. However, integer and floating
1557 point operations set the N flag to be the MSB of the result
1558 exclusive ored with the overflow (V) flag. Thus if an overflow
1559 occurs and the result does not have the MSB set (i.e., the result
1560 looks like a positive number), the N flag is set. Conversely, if
1561 an overflow occurs and the MSB of the result is set, N is set to 0.
1562 Thus the N flag represents the sign of the result if it could have
1563 been stored without overflow but does not represent the apparent
1564 sign of the result. Note that most architectures set the N flag to
1565 be the MSB of the result.
1567 The C4x approach to setting the N flag simplifies signed
1568 conditional branches and loads which only have to test the state of
1569 the N flag, whereas most architectures have to look at both the N
1570 and V flags. The disadvantage is that there is no flag giving the
1571 status of the sign bit of the operation. However, there are no
1572 conditional load or branch instructions that make use of this
1573 feature (e.g., BMI---branch minus) instruction. Note that BN and
1574 BLT are identical in the C4x.
1576 To handle the problem where the N flag is set differently whenever
1577 there is an overflow we use a different CC mode, CC_NOOVmode which
1578 says that the CC reflects the comparison of the result against zero
1579 if no overflow occured.
1583 [(set (reg:CC_NOOV 21)
1584 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "")
1585 (match_operand:QI 2 "src_operand" ""))
1587 (set (match_operand:QI 0 "ext_reg_operand" "")
1588 (minus:QI (match_dup 1)
1591 Note that there is no problem for insns that don't return a result
1592 like CMP, since the CC reflects the effect of operation.
1594 An example of a potential problem is when GCC
1595 converts (LTU (MINUS (0x80000000) (0x7fffffff) (0x80000000)))
1596 to (LEU (MINUS (0x80000000) (0x7fffffff) (0x7fffffff)))
1597 to (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000)))
1599 Now (MINUS (0x80000000) (0x7fffffff)) returns 0x00000001 but the
1600 C4x sets the N flag since the result without overflow would have
1601 been 0xffffffff when treating the operands as signed integers.
1602 Thus (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000))) sets the N
1603 flag but (GE (0x00000001)) does not set the N flag.
1605 The upshot is that we can not use signed branch and conditional
1606 load instructions after an add, subtract, neg, abs or multiply.
1607 We must emit a compare insn to check the result against 0. */
1609 #define EXTRA_CC_MODES CC(CC_NOOVmode, "CC_NOOV")
1611 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1613 CCmode should be used when no special processing is needed. */
1614 #define SELECT_CC_MODE(OP,X,Y) \
1615 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1616 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1617 || GET_MODE (X) == ABS \
1618 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1619 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1620 || GET_MODE (Y) == ABS) \
1621 ? CC_NOOVmode : CCmode)
1623 /* Addressing Modes. */
1625 #define HAVE_POST_INCREMENT 1
1626 #define HAVE_PRE_INCREMENT 1
1627 #define HAVE_POST_DECREMENT 1
1628 #define HAVE_PRE_DECREMENT 1
1629 #define HAVE_PRE_MODIFY_REG 1
1630 #define HAVE_POST_MODIFY_REG 1
1631 #define HAVE_PRE_MODIFY_DISP 1
1632 #define HAVE_POST_MODIFY_DISP 1
1634 /* The number of insns that can be packed into a single opcode. */
1635 #define PACK_INSNS 2
1637 /* Recognize any constant value that is a valid address.
1638 We could allow arbitrary constant addresses in the large memory
1639 model but for the small memory model we can only accept addresses
1640 within the data page. I suppose we could also allow
1641 CONST PLUS SYMBOL_REF. */
1642 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1644 /* Maximum number of registers that can appear in a valid memory
1646 #define MAX_REGS_PER_ADDRESS 2
1648 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1649 and check its validity for a certain class.
1650 We have two alternate definitions for each of them.
1651 The usual definition accepts all pseudo regs; the other rejects
1652 them unless they have been allocated suitable hard regs.
1653 The symbol REG_OK_STRICT causes the latter definition to be used.
1655 Most source files want to accept pseudo regs in the hope that
1656 they will get allocated to the class that the insn wants them to be in.
1657 Source files for reload pass need to be strict.
1658 After reload, it makes no difference, since pseudo regs have
1659 been eliminated by then. */
1661 #ifndef REG_OK_STRICT
1663 /* Nonzero if X is a hard or pseudo reg that can be used as an base. */
1665 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
1667 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1669 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
1671 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1673 if (c4x_check_legit_addr (MODE, X, 0)) \
1679 /* Nonzero if X is a hard reg that can be used as an index. */
1681 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1683 /* Nonzero if X is a hard reg that can be used as a base reg. */
1685 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1687 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1689 if (c4x_check_legit_addr (MODE, X, 1)) \
1695 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1698 new = c4x_legitimize_address (X, MODE); \
1699 if (new != NULL_RTX) \
1706 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1709 new = c4x_legitimize_reload_address (X, MODE, insn); \
1710 if (new != NULL_RTX) \
1713 /* We do not have to call push_reload because we do not require \
1714 any more reloads. */ \
1720 /* No mode-dependent addresses on the C4x are autoincrements. */
1722 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1723 if (GET_CODE (ADDR) == PRE_DEC \
1724 || GET_CODE (ADDR) == POST_DEC \
1725 || GET_CODE (ADDR) == PRE_INC \
1726 || GET_CODE (ADDR) == POST_INC \
1727 || GET_CODE (ADDR) == POST_MODIFY \
1728 || GET_CODE (ADDR) == PRE_MODIFY) \
1732 /* Nonzero if the constant value X is a legitimate general operand.
1733 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1735 The C4x can only load 16-bit immediate values, so we only allow a
1736 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1737 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1738 model) so that the symbols will be forced into the constant pool.
1739 On second thoughts, let's do this with the move expanders since
1740 the alias analysis has trouble if we force constant addresses
1744 #define LEGITIMATE_CONSTANT_P(X) \
1745 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1746 || (GET_CODE (X) == CONST_INT) \
1747 || (GET_CODE (X) == SYMBOL_REF) \
1748 || (GET_CODE (X) == LABEL_REF) \
1749 || (GET_CODE (X) == CONST) \
1750 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1751 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1753 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1755 /* Define this macro if references to a symbol must be treated
1756 differently depending on something about the variable or
1757 function named by the symbol (such as what section it is in).
1759 The macro definition, if any, is executed immediately after the
1760 rtl for DECL or other node is created.
1761 The value of the rtl will be a `mem' whose address is a
1764 The usual thing for this macro to do is to a flag in the
1765 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1766 name string in the `symbol_ref' (if one bit is not enough
1769 On the C4x we use this to indicate if a symbol is in text or
1772 #define ENCODE_SECTION_INFO(DECL) c4x_encode_section_info (DECL);
1774 /* Descripting Relative Cost of Operations. */
1776 /* Provide the costs of a rtl expression. This is in the body of a
1779 Note that we return, rather than break so that rtx_cost doesn't
1780 include CONST_COSTS otherwise expand_mult will think that it is
1781 cheaper to synthesise a multiply rather than to use a multiply
1782 instruction. I think this is because the algorithm synth_mult
1783 doesn't take into account the loading of the operands, whereas the
1784 calculation of mult_cost does.
1788 #define RTX_COSTS(RTX, CODE, OUTER_CODE) \
1797 return COSTS_N_INSNS (1); \
1799 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1800 || TARGET_MPYI ? 1 : 14); \
1805 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1808 /* Compute the cost of computing a constant rtl expression RTX
1809 whose rtx-code is CODE. The body of this macro is a portion
1810 of a switch statement. If the code is computed here,
1811 return it with a return statement. Otherwise, break from the switch.
1813 An insn is assumed to cost 4 units.
1814 COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
1816 Some small integers are effectively free for the C40. We should
1817 also consider if we are using the small memory model. With
1818 the big memory model we require an extra insn for a constant
1821 This is used by expand_binop to decide whether to force a constant
1822 into a register. If the cost is greater than 2 and the constant
1823 is used within a short loop, it gets forced into a register.
1824 Ideally, there should be some weighting as to how mnay times it is used
1827 #define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
1829 #define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
1830 || (C) == IOR || (C) == XOR)
1832 #define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
1834 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1836 if (c4x_J_constant (RTX)) \
1839 && OUTER_CODE == AND \
1840 && GET_CODE (RTX) == CONST_INT \
1841 && (INTVAL (RTX) == 255 || INTVAL (RTX) == 65535)) \
1844 && (OUTER_CODE == ASHIFTRT || OUTER_CODE == LSHIFTRT) \
1845 && GET_CODE (RTX) == CONST_INT \
1846 && (INTVAL (RTX) == 16 || INTVAL (RTX) == 24)) \
1848 if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \
1850 if (LOGICAL_CODE_P (OUTER_CODE) \
1851 ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \
1857 case CONST_DOUBLE: \
1858 if (c4x_H_constant (RTX)) \
1860 if (GET_MODE (RTX) == QFmode) \
1865 /* Compute the cost of an address. This is meant to approximate the size
1866 and/or execution delay of an insn using that address. If the cost is
1867 approximated by the RTL complexity, including CONST_COSTS above, as
1868 is usually the case for CISC machines, this macro should not be defined.
1869 For aggressively RISCy machines, only one insn format is allowed, so
1870 this macro should be a constant. The value of this macro only matters
1871 for valid addresses. We handle the most common address without
1872 a call to c4x_address_cost. */
1874 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
1876 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1877 if (REG_P (OP1) && ! REG_P (OP0)) \
1879 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1880 CODE = swap_condition (CODE); \
1883 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1884 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1885 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1886 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1887 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1889 /* Compute extra cost of moving data between one register class
1892 #define REGISTER_MOVE_COST(FROM, TO) 2
1894 /* Memory move cost is same as fast register move. Maybe this should
1897 #define MEMORY_MOVE_COST(M,C,I) 4
1899 /* Branches are kind of expensive (even with delayed branching) so
1900 make their cost higher. */
1902 #define BRANCH_COST 8
1904 /* Adjust the cost of dependencies. */
1906 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1907 (COST) = c4x_adjust_cost (INSN, LINK, DEP, COST)
1909 #define WORD_REGISTER_OPERATIONS
1911 /* Dividing the Output into Sections. */
1913 #define TEXT_SECTION_ASM_OP "\t.text"
1915 #define DATA_SECTION_ASM_OP "\t.data"
1917 #define USE_CONST_SECTION 1
1919 #define CONST_SECTION_ASM_OP "\t.sect\t\".const\""
1921 /* Do not use .init section so __main will be called on startup. This will
1922 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1925 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1928 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1930 /* Support const sections and the ctors and dtors sections for g++.
1931 Note that there appears to be two different ways to support const
1932 sections at the moment. You can either #define the symbol
1933 READONLY_DATA_SECTION (giving it some code which switches to the
1934 readonly data section) or else you can #define the symbols
1935 EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
1936 SELECT_RTX_SECTION. We do both here just to be on the safe side. */
1938 /* Define a few machine-specific details of the implementation of
1941 The __CTORS_LIST__ goes in the .ctors section. Define CTOR_LIST_BEGIN
1942 and CTOR_LIST_END to contribute to the .ctors section an instruction to
1943 push a word containing 0 (or some equivalent of that).
1945 Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor. */
1947 #define CTORS_SECTION_ASM_OP "\t.sect\t\".ctors\""
1948 #define DTORS_SECTION_ASM_OP "\t.sect\t\".dtors\""
1950 /* Constructor list on stack is in reverse order. Go to the end of the
1951 list and go backwards to call constructors in the right order. */
1953 #define DO_GLOBAL_CTORS_BODY \
1955 extern func_ptr __CTOR_LIST__[]; \
1956 func_ptr *p, *beg = __CTOR_LIST__ + 1; \
1957 for (p = beg; *p ; p++) ; \
1962 #undef EXTRA_SECTIONS
1963 #define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors
1965 #undef EXTRA_SECTION_FUNCTIONS
1966 #define EXTRA_SECTION_FUNCTIONS \
1967 CONST_SECTION_FUNCTION \
1968 INIT_SECTION_FUNCTION \
1969 FINI_SECTION_FUNCTION \
1970 CTORS_SECTION_FUNCTION \
1971 DTORS_SECTION_FUNCTION
1973 #define INIT_SECTION_FUNCTION \
1977 if (in_section != in_init) \
1979 fprintf (asm_out_file, ";\t.init\n"); \
1980 in_section = in_init; \
1984 #define FINI_SECTION_FUNCTION \
1988 if (in_section != in_fini) \
1990 fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP); \
1991 in_section = in_fini; \
1995 #define READONLY_DATA_SECTION() const_section ()
1997 #define CONST_SECTION_FUNCTION \
2001 if (! USE_CONST_SECTION) \
2003 else if (in_section != in_const) \
2005 fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \
2006 in_section = in_const; \
2010 #define ASM_STABS_OP "\t.stabs"
2012 /* The ctors and dtors sections are not normally put into use
2013 by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h,
2014 but it can't hurt to define these macros for whatever systems use them. */
2016 #define CTORS_SECTION_FUNCTION \
2020 if (in_section != in_ctors) \
2022 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
2023 in_section = in_ctors; \
2027 #define DTORS_SECTION_FUNCTION \
2031 if (in_section != in_dtors) \
2033 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
2034 in_section = in_dtors; \
2038 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
2039 fprintf (FILE, "\t.sect\t\"%s\"\n", NAME);
2041 /* This is machine-dependent because it needs to push something
2044 /* A C statement (sans semicolon) to output an element in the table of
2045 global constructors. */
2046 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
2049 fprintf (FILE, "\t.word\t "); \
2050 assemble_name (FILE, NAME); \
2051 fprintf (FILE, "\n"); \
2054 /* A C statement (sans semicolon) to output an element in the table of
2055 global destructors. */
2056 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
2059 fprintf (FILE, "\t.word\t "); \
2060 assemble_name (FILE, NAME); \
2061 fprintf (FILE, "\n"); \
2064 /* A C statement or statements to switch to the appropriate
2065 section for output of DECL. DECL is either a `VAR_DECL' node
2066 or a constant of some sort. RELOC indicates whether forming
2067 the initial value of DECL requires link-time relocations. */
2069 #define SELECT_SECTION(DECL, RELOC) \
2071 if (TREE_CODE (DECL) == STRING_CST) \
2073 if (! flag_writable_strings) \
2078 else if (TREE_CODE (DECL) == VAR_DECL) \
2080 if ((0 && RELOC) /* Should be (flag_pic && RELOC). */ \
2081 || ! TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \
2082 || ! DECL_INITIAL (DECL) \
2083 || (DECL_INITIAL (DECL) != error_mark_node \
2084 && ! TREE_CONSTANT (DECL_INITIAL (DECL)))) \
2093 /* The TI assembler wants to have hex numbers this way. */
2095 #undef HOST_WIDE_INT_PRINT_HEX
2096 #ifndef HOST_WIDE_INT_PRINT_HEX
2097 # if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2098 # define HOST_WIDE_INT_PRINT_HEX "0%xh"
2100 # if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
2101 # define HOST_WIDE_INT_PRINT_HEX "0%lxh"
2103 # define HOST_WIDE_INT_PRINT_HEX "0%llxh"
2106 #endif /* ! HOST_WIDE_INT_PRINT_HEX */
2108 /* A C statement or statements to switch to the appropriate
2109 section for output of RTX in mode MODE. RTX is some kind
2110 of constant in RTL. The argument MODE is redundant except
2111 in the case of a `const_int' rtx. Currently, these always
2112 go into the const section. */
2114 #define SELECT_RTX_SECTION(MODE, RTX) const_section()
2117 /* Overall Framework of an Assembler File. */
2119 #define ASM_FILE_START(FILE) \
2121 int dspversion = 0; \
2122 if (TARGET_C30) dspversion = 30; \
2123 if (TARGET_C31) dspversion = 31; \
2124 if (TARGET_C32) dspversion = 32; \
2125 if (TARGET_C40) dspversion = 40; \
2126 if (TARGET_C44) dspversion = 44; \
2127 fprintf (FILE, "\t.version\t%d\n", dspversion); \
2128 fprintf (FILE, "\t.file\t"); \
2132 char *after_dir = main_input_filename; \
2133 for (p = main_input_filename; *p; p++) \
2135 after_dir = p + 1; \
2136 output_quoted_string (FILE, after_dir); \
2139 output_quoted_string (FILE, main_input_filename); \
2140 fprintf (FILE, "\n"); \
2143 /* We need to have a data section we can identify so that we can set
2144 the DP register back to a data pointer in the small memory model.
2145 This is only required for ISRs if we are paranoid that someone
2146 may have quietly changed this register on the sly. */
2148 #define ASM_IDENTIFY_GCC(FILE) \
2149 if (! TARGET_TI) fputs ("gcc2_compiled.:\n", FILE); \
2150 fputs ("\t.data\ndata_sec:\n", FILE);
2152 #define ASM_COMMENT_START ";"
2154 #define ASM_APP_ON ""
2155 #define ASM_APP_OFF ""
2157 /* Output float/double constants QFmode. */
2159 #define ASM_OUTPUT_BYTE_FLOAT(FILE, VALUE) \
2163 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2164 REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
2165 if (sizeof (int) == sizeof (long)) \
2166 fprintf (FILE, "\t.word\t0%08xh\t; %s\n", l, str);\
2168 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n", l, str);\
2171 /* Output long double constants HFmode.
2172 The first word contains the exponent and first part of the mantissa
2173 in the same manner as QFmode. The second word contains the full
2174 mantissa. We should ensure that the two words are allocated within
2175 the same page for the large memory model since we only output a single
2176 LDP instruction. FIXME. The simplest solution probably is to output
2177 a LDP for each load. */
2179 #define ASM_OUTPUT_SHORT_FLOAT(FILE, VALUE) \
2183 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2184 REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
2185 l[1] = (l[0] << 8) | ((l[1] >> 24) & 0xff); \
2186 if (sizeof (int) == sizeof (long)) \
2187 fprintf (FILE, "\t.word\t0%08xh\t; %s\n\t.word\t0%08xh\n", \
2190 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n\t.word\t0%08lxh\n", \
2194 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
2196 fprintf (FILE, "\t.word\t"); \
2197 output_addr_const (FILE, VALUE); \
2198 if (GET_CODE (VALUE) != SYMBOL_REF) \
2199 fprintf (FILE, " ; 0%08xh\n", INTVAL (VALUE)); \
2201 fputc ('\n', FILE); \
2204 #define ASM_OUTPUT_BYTE(FILE, VALUE) \
2205 fprintf (FILE, "\t.word\t0%xh\n", (VALUE))
2207 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
2209 #define ASM_OPEN_PAREN "("
2210 #define ASM_CLOSE_PAREN ")"
2213 /* Output and Generation of Labels. */
2215 #define NO_DOT_IN_LABEL /* Only required for TI format. */
2217 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2218 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0);
2220 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
2222 fprintf (FILE, "\t.global\t"); \
2223 assemble_name (FILE, NAME); \
2224 fputs ("\n", FILE); \
2225 c4x_global_label (NAME); \
2228 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
2229 c4x_external_ref (NAME)
2231 /* A C statement to output on FILE an assembler pseudo-op to
2232 declare a library function named external.
2233 (Only needed to keep asm30 happy for ___divqf3 etc.) */
2235 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
2236 c4x_external_ref (XSTR (FUN, 0))
2238 #define ASM_FILE_END(FILE) \
2241 /* The prefix to add to user-visible assembler symbols. */
2243 #define USER_LABEL_PREFIX "_"
2245 /* This is how to output an internal numbered label where
2246 PREFIX is the class of label and NUM is the number within the class. */
2248 #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
2249 asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2251 /* This is how to store into the string LABEL
2252 the symbol_ref name of an internal numbered label where
2253 PREFIX is the class of label and NUM is the number within the class.
2254 This is suitable for output with `assemble_name'. */
2256 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
2257 sprintf (BUFFER, "*%s%d", PREFIX, NUM)
2259 /* Store in OUTPUT a string (made with alloca) containing
2260 an assembler-name for a local static variable named NAME.
2261 LABELNO is an integer which is different for each call. */
2263 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2264 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2265 sprintf ((OUTPUT), "%s$%d", (NAME), (LABELNO)))
2268 /* Output of Dispatch Tables. */
2270 /* This is how to output an element of a case-vector that is absolute. */
2272 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2273 fprintf (FILE, "\t.long\tL%d\n", VALUE);
2275 /* This is how to output an element of a case-vector that is relative. */
2277 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2278 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
2281 #define SIZE_TYPE "unsigned int"
2284 #define PTRDIFF_TYPE "int"
2287 #define WCHAR_TYPE "long int"
2289 #undef WCHAR_TYPE_SIZE
2290 #define WCHAR_TYPE_SIZE 32
2292 #define INT_TYPE_SIZE 32
2293 #define LONG_LONG_TYPE_SIZE 64
2294 #define FLOAT_TYPE_SIZE 32
2295 #define DOUBLE_TYPE_SIZE 32
2296 #define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
2298 /* Allow #sccs in preprocessor. */
2300 #define SCCS_DIRECTIVE
2302 /* Output #ident as a .ident. */
2304 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2305 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
2307 #define CPP_PREDEFINES ""
2309 /* Output of Uninitialized Variables. */
2311 /* This says how to output an assembler line to define a local
2312 uninitialized variable. */
2314 #undef ASM_OUTPUT_LOCAL
2315 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2316 ( fputs ("\t.bss\t", FILE), \
2317 assemble_name (FILE, (NAME)), \
2318 fprintf (FILE, ",%u\n", (ROUNDED)))
2320 /* This says how to output an assembler line to define a global
2321 uninitialized variable. */
2323 #undef ASM_OUTPUT_COMMON
2324 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2325 ( fputs ("\t.globl\t", FILE), \
2326 assemble_name (FILE, (NAME)), \
2327 fputs ("\n\t.bss\t", FILE), \
2328 assemble_name (FILE, (NAME)), \
2329 fprintf (FILE, ",%u\n", (ROUNDED)))
2331 #undef ASM_OUTPUT_BSS
2332 #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2333 ( fputs ("\t.globl\t", FILE), \
2334 assemble_name (FILE, (NAME)), \
2335 fputs ("\n\t.bss\t", FILE), \
2336 assemble_name (FILE, (NAME)), \
2337 fprintf (FILE, ",%u\n", (SIZE)))
2339 /* Macros Controlling Initialization Routines. */
2341 #define OBJECT_FORMAT_COFF
2342 #define REAL_NM_FILE_NAME "c4x-nm"
2344 /* Output of Assembler Instructions. */
2346 /* Register names when used for integer modes. */
2348 #define REGISTER_NAMES \
2350 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2351 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2352 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2353 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
2356 /* Alternate register names when used for floating point modes. */
2358 #define FLOAT_REGISTER_NAMES \
2360 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2361 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2362 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2363 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
2366 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
2368 /* Determine which codes are valid without a following integer. These must
2369 not be alphabetic. */
2371 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
2373 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
2375 /* Define this macro if you want to implement any pragmas. If defined, it
2376 should be a C expression to be executed when #pragma is seen. The
2377 argument STREAM is the stdio input stream from which the source
2378 text can be read. CH is the first character after the #pragma. The
2379 result of the expression is the terminating character found
2380 (newline or EOF). */
2381 #define HANDLE_PRAGMA(GETC, UNGETC, NAME) \
2382 c4x_handle_pragma (GETC, UNGETC, NAME)
2384 #define SET_DEFAULT_DECL_ATTRIBUTES(DECL, ATTRIBUTES) \
2385 c4x_set_default_attributes (DECL, &ATTRIBUTES)
2387 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2388 (c4x_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2390 /* Assembler Commands for Alignment. */
2392 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
2394 for (; c > 0; --c) \
2395 fprintf (FILE,"\t.word\t0\n"); \
2398 #define ASM_NO_SKIP_IN_TEXT 1
2400 /* I'm not sure about this one. FIXME. */
2402 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
2404 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
2407 /* Macros for SDB and DWARF Output (use .sdef instead of .def
2408 to avoid conflict with TI's use of .def). */
2410 #define SDB_DELIM "\n"
2411 #define SDB_DEBUGGING_INFO
2413 /* Don't use octal since this can confuse gas for the c4x. */
2414 #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
2416 #define PUT_SDB_DEF(A) \
2417 do { fprintf (asm_out_file, "\t.sdef\t"); \
2418 ASM_OUTPUT_LABELREF (asm_out_file, A); \
2419 fprintf (asm_out_file, SDB_DELIM); } while (0)
2421 #define PUT_SDB_PLAIN_DEF(A) \
2422 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
2424 #define PUT_SDB_BLOCK_START(LINE) \
2425 fprintf (asm_out_file, \
2426 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2427 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2429 #define PUT_SDB_BLOCK_END(LINE) \
2430 fprintf (asm_out_file, \
2431 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2432 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2434 #define PUT_SDB_FUNCTION_START(LINE) \
2435 fprintf (asm_out_file, \
2436 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2437 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2439 /* Note we output relative line numbers for .ef which gas converts
2440 to absolute line numbers. The TI compiler outputs absolute line numbers
2441 in the .sym directive which gas does not support. */
2442 #define PUT_SDB_FUNCTION_END(LINE) \
2443 fprintf (asm_out_file, \
2444 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2445 SDB_DELIM, SDB_DELIM, SDB_DELIM, \
2448 #define PUT_SDB_EPILOGUE_END(NAME) \
2449 do { fprintf (asm_out_file, "\t.sdef\t"); \
2450 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
2451 fprintf (asm_out_file, \
2452 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
2453 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
2456 /* Define results of standard character escape sequences. */
2458 #define TARGET_BELL 007
2459 #define TARGET_BS 010
2460 #define TARGET_TAB 011
2461 #define TARGET_NEWLINE 012
2462 #define TARGET_VT 013
2463 #define TARGET_FF 014
2464 #define TARGET_CR 015
2466 /* This is the kind of divide that is easiest to do in the general case. */
2468 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2470 /* Define this as 1 if `char' should by default be signed; else as 0. */
2472 #define DEFAULT_SIGNED_CHAR 1
2474 /* A function address in a call instruction is a byte address (for
2475 indexing purposes) so give the MEM rtx a byte's mode. */
2477 #define FUNCTION_MODE QImode
2479 #define SLOW_BYTE_ACCESS 0
2481 /* Specify the machine mode that pointers have. After generation of
2482 RTL, the compiler makes no further distinction between pointers and
2483 any other objects of this machine mode. */
2485 #define Pmode QImode
2487 /* On the C4x we can write the following code. We have to clear the cache
2488 every time we execute it because the data in the stack could change.
2501 On the c3x this is a bit more difficult. We have to write self
2502 modifying code here. So we have to clear the cache every time
2503 we execute it because the data in the stack could change.
2505 ldiu TOP_OF_FUNCTION,ar1
2507 or BOTTOM_OF_FUNCTION,ar1
2508 ldiu TOP_OF_STATIC,ar0
2511 or BOTTOM_OF_STATIC,ar0
2516 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
2518 #define TRAMPOLINE_TEMPLATE(FILE) \
2522 asm_fprintf (FILE, "\tldiu\t0,ar1\n"); \
2523 asm_fprintf (FILE, "\tlsh\t16,ar1\n"); \
2524 asm_fprintf (FILE, "\tor\t0,ar1\n"); \
2525 asm_fprintf (FILE, "\tldiu\t0,ar0\n"); \
2526 asm_fprintf (FILE, "\tbud\tar1\n"); \
2527 asm_fprintf (FILE, "\tlsh\t16,ar0\n"); \
2528 asm_fprintf (FILE, "\tor\t0,ar0\n"); \
2529 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2533 asm_fprintf (FILE, "\tlaj\t$+4\n"); \
2534 asm_fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
2535 asm_fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
2536 asm_fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
2537 asm_fprintf (FILE, "\tbud\tar1\n"); \
2538 asm_fprintf (FILE, "\tnop\n"); \
2539 asm_fprintf (FILE, "\tnop\n"); \
2540 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2541 asm_fprintf (FILE, "\t.word\t0\n"); \
2542 asm_fprintf (FILE, "\t.word\t0\n"); \
2546 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2551 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
2552 size_int (16), 0, 1); \
2553 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2554 gen_rtx (CONST_INT, VOIDmode, 0x5069), \
2555 size_int (16), 0, 1); \
2556 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2557 emit_move_insn (gen_rtx (MEM, QImode, \
2558 plus_constant (tramp, 0)), tmp1); \
2559 tmp1 = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, \
2561 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2562 gen_rtx (CONST_INT, VOIDmode, 0x1069), \
2563 size_int (16), 0, 1); \
2564 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2565 emit_move_insn (gen_rtx (MEM, QImode, \
2566 plus_constant (tramp, 2)), tmp1); \
2567 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
2568 size_int (16), 0, 1); \
2569 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2570 gen_rtx (CONST_INT, VOIDmode, 0x5068), \
2571 size_int (16), 0, 1); \
2572 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2573 emit_move_insn (gen_rtx (MEM, QImode, \
2574 plus_constant (tramp, 3)), tmp1); \
2575 tmp1 = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, \
2577 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2578 gen_rtx (CONST_INT, VOIDmode, 0x1068), \
2579 size_int (16), 0, 1); \
2580 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2581 emit_move_insn (gen_rtx (MEM, QImode, \
2582 plus_constant (tramp, 6)), tmp1); \
2586 emit_move_insn (gen_rtx (MEM, QImode, \
2587 plus_constant (TRAMP, 8)), FNADDR); \
2588 emit_move_insn (gen_rtx (MEM, QImode, \
2589 plus_constant (TRAMP, 9)), CXT); \
2593 /* Specify the machine mode that this machine uses for the index in
2594 the tablejump instruction. */
2596 #define CASE_VECTOR_MODE Pmode
2598 /* Max number of (32-bit) bytes we can move from memory to memory
2599 in one reasonably fast instruction. */
2603 /* MOVE_RATIO is the number of move instructions that is better than a
2606 #define MOVE_RATIO 2 /* Default value. */
2608 #define BSS_SECTION_ASM_OP ".bss"
2610 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2611 asm_fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
2613 /* This is how to output an insn to pop a register from the stack.
2614 It need not be very fast code. */
2616 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2617 asm_fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
2619 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2620 is done just by pretending it is already truncated. */
2622 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2624 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2626 /* We need to use direct addressing for large constants and addresses
2627 that cannot fit within an instruction. We must check for these
2628 after after the final jump optimisation pass, since this may
2629 introduce a local_move insn for a SYMBOL_REF. This pass
2630 must come before delayed branch slot filling since it can generate
2631 additional instructions. */
2633 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
2635 #define DBR_OUTPUT_SEQEND(FILE) \
2636 if (final_sequence != NULL_RTX) \
2639 int laj = GET_CODE (XVECEXP (final_sequence, 0, 0)) == CALL_INSN; \
2641 count = dbr_sequence_length(); \
2642 while (count < (laj ? 2 : 3)) \
2644 fputs("\tnop\n", FILE); \
2648 fputs("\tpush\tr11\n", FILE); \
2651 #define NO_FUNCTION_CSE
2653 /* We don't want a leading tab. */
2655 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
2657 /* Define the codes that are matched by predicates in c4x.c. */
2659 #define PREDICATE_CODES \
2660 {"fp_zero_operand", {CONST_DOUBLE}}, \
2661 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
2662 {"stik_const_operand", {CONST_INT}}, \
2663 {"not_const_operand", {CONST_INT}}, \
2664 {"reg_operand", {REG, SUBREG}}, \
2665 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
2666 {"r0r1_reg_operand", {REG, SUBREG}}, \
2667 {"r2r3_reg_operand", {REG, SUBREG}}, \
2668 {"ext_low_reg_operand", {REG, SUBREG}}, \
2669 {"ext_reg_operand", {REG, SUBREG}}, \
2670 {"std_reg_operand", {REG, SUBREG}}, \
2671 {"std_or_reg_operand", {REG, SUBREG}}, \
2672 {"addr_reg_operand", {REG, SUBREG}}, \
2673 {"index_reg_operand", {REG, SUBREG}}, \
2674 {"dp_reg_operand", {REG}}, \
2675 {"sp_reg_operand", {REG}}, \
2676 {"st_reg_operand", {REG}}, \
2677 {"rc_reg_operand", {REG}}, \
2678 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
2679 {"dst_operand", {SUBREG, REG, MEM}}, \
2680 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2681 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
2682 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2683 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2684 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2685 {"par_ind_operand", {MEM}}, \
2686 {"parallel_operand", {SUBREG, REG, MEM}}, \
2687 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2688 {"mem_operand", {MEM}},
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