1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Analog Devices.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #define OBJECT_FORMAT_ELF
31 typedef enum bfin_cpu_type
66 extern bfin_cpu_t bfin_cpu_type;
68 /* Value of -msi-revision= */
69 extern int bfin_si_revision;
71 extern unsigned int bfin_workarounds;
73 /* Print subsidiary information on the compiler version in use. */
74 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
76 /* Predefinition in the preprocessor for this target machine */
77 #ifndef TARGET_CPU_CPP_BUILTINS
78 #define TARGET_CPU_CPP_BUILTINS() \
81 builtin_define_std ("bfin"); \
82 builtin_define_std ("BFIN"); \
83 builtin_define ("__ADSPBLACKFIN__"); \
84 builtin_define ("__ADSPLPBLACKFIN__"); \
86 switch (bfin_cpu_type) \
88 case BFIN_CPU_BF512: \
89 builtin_define ("__ADSPBF512__"); \
90 builtin_define ("__ADSPBF51x__"); \
92 case BFIN_CPU_BF514: \
93 builtin_define ("__ADSPBF514__"); \
94 builtin_define ("__ADSPBF51x__"); \
96 case BFIN_CPU_BF516: \
97 builtin_define ("__ADSPBF516__"); \
98 builtin_define ("__ADSPBF51x__"); \
100 case BFIN_CPU_BF518: \
101 builtin_define ("__ADSPBF518__"); \
102 builtin_define ("__ADSPBF51x__"); \
104 case BFIN_CPU_BF522: \
105 builtin_define ("__ADSPBF522__"); \
106 builtin_define ("__ADSPBF52x__"); \
108 case BFIN_CPU_BF523: \
109 builtin_define ("__ADSPBF523__"); \
110 builtin_define ("__ADSPBF52x__"); \
112 case BFIN_CPU_BF524: \
113 builtin_define ("__ADSPBF524__"); \
114 builtin_define ("__ADSPBF52x__"); \
116 case BFIN_CPU_BF525: \
117 builtin_define ("__ADSPBF525__"); \
118 builtin_define ("__ADSPBF52x__"); \
120 case BFIN_CPU_BF526: \
121 builtin_define ("__ADSPBF526__"); \
122 builtin_define ("__ADSPBF52x__"); \
124 case BFIN_CPU_BF527: \
125 builtin_define ("__ADSPBF527__"); \
126 builtin_define ("__ADSPBF52x__"); \
128 case BFIN_CPU_BF531: \
129 builtin_define ("__ADSPBF531__"); \
131 case BFIN_CPU_BF532: \
132 builtin_define ("__ADSPBF532__"); \
134 case BFIN_CPU_BF533: \
135 builtin_define ("__ADSPBF533__"); \
137 case BFIN_CPU_BF534: \
138 builtin_define ("__ADSPBF534__"); \
140 case BFIN_CPU_BF536: \
141 builtin_define ("__ADSPBF536__"); \
143 case BFIN_CPU_BF537: \
144 builtin_define ("__ADSPBF537__"); \
146 case BFIN_CPU_BF538: \
147 builtin_define ("__ADSPBF538__"); \
149 case BFIN_CPU_BF539: \
150 builtin_define ("__ADSPBF539__"); \
152 case BFIN_CPU_BF542M: \
153 builtin_define ("__ADSPBF542M__"); \
154 case BFIN_CPU_BF542: \
155 builtin_define ("__ADSPBF542__"); \
156 builtin_define ("__ADSPBF54x__"); \
158 case BFIN_CPU_BF544M: \
159 builtin_define ("__ADSPBF544M__"); \
160 case BFIN_CPU_BF544: \
161 builtin_define ("__ADSPBF544__"); \
162 builtin_define ("__ADSPBF54x__"); \
164 case BFIN_CPU_BF547M: \
165 builtin_define ("__ADSPBF547M__"); \
166 case BFIN_CPU_BF547: \
167 builtin_define ("__ADSPBF547__"); \
168 builtin_define ("__ADSPBF54x__"); \
170 case BFIN_CPU_BF548M: \
171 builtin_define ("__ADSPBF548M__"); \
172 case BFIN_CPU_BF548: \
173 builtin_define ("__ADSPBF548__"); \
174 builtin_define ("__ADSPBF54x__"); \
176 case BFIN_CPU_BF549M: \
177 builtin_define ("__ADSPBF549M__"); \
178 case BFIN_CPU_BF549: \
179 builtin_define ("__ADSPBF549__"); \
180 builtin_define ("__ADSPBF54x__"); \
182 case BFIN_CPU_BF561: \
183 builtin_define ("__ADSPBF561__"); \
187 if (bfin_si_revision != -1) \
189 /* space of 0xnnnn and a NUL */ \
190 char *buf = XALLOCAVEC (char, 7); \
192 sprintf (buf, "0x%04x", bfin_si_revision); \
193 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
196 if (bfin_workarounds) \
197 builtin_define ("__WORKAROUNDS_ENABLED"); \
198 if (ENABLE_WA_SPECULATIVE_LOADS) \
199 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
200 if (ENABLE_WA_SPECULATIVE_SYNCS) \
201 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
202 if (ENABLE_WA_INDIRECT_CALLS) \
203 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
204 if (ENABLE_WA_RETS) \
205 builtin_define ("__WORKAROUND_RETS"); \
209 builtin_define ("__BFIN_FDPIC__"); \
210 builtin_define ("__FDPIC__"); \
212 if (TARGET_ID_SHARED_LIBRARY \
213 && !TARGET_SEP_DATA) \
214 builtin_define ("__ID_SHARED_LIB__"); \
215 if (flag_no_builtin) \
216 builtin_define ("__NO_BUILTIN"); \
217 if (TARGET_MULTICORE) \
218 builtin_define ("__BFIN_MULTICORE"); \
220 builtin_define ("__BFIN_COREA"); \
222 builtin_define ("__BFIN_COREB"); \
224 builtin_define ("__BFIN_SDRAM"); \
229 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
230 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
231 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
232 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
234 #ifndef SUBTARGET_DRIVER_SELF_SPECS
235 # define SUBTARGET_DRIVER_SELF_SPECS
238 #define LINK_GCC_C_SEQUENCE_SPEC "\
239 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
244 %{mno-fdpic:-mnopic} %{mfdpic}"
248 %{mfdpic:-melf32bfinfd -z text} \
249 %{static:-dn -Bstatic} \
250 %{shared:-G -Bdynamic} \
251 %{symbolic:-Bsymbolic} \
252 -init __init -fini __fini "
254 /* Generate DSP instructions, like DSP halfword loads */
255 #define TARGET_DSP (1)
257 #define TARGET_DEFAULT 0
259 /* Maximum number of library ids we permit */
260 #define MAX_LIBRARY_ID 255
262 extern const char *bfin_library_id_string;
264 #define FUNCTION_MODE SImode
267 /* store-condition-codes instructions store 0 for false
268 This is the value stored for true. */
269 #define STORE_FLAG_VALUE 1
271 /* Define this if pushing a word on the stack
272 makes the stack pointer a smaller address. */
273 #define STACK_GROWS_DOWNWARD
275 #define STACK_PUSH_CODE PRE_DEC
277 /* Define this to nonzero if the nominal address of the stack frame
278 is at the high-address end of the local variables;
279 that is, each additional local variable allocated
280 goes at a more negative offset in the frame. */
281 #define FRAME_GROWS_DOWNWARD 1
283 /* We define a dummy ARGP register; the parameters start at offset 0 from
285 #define FIRST_PARM_OFFSET(DECL) 0
287 /* Offset within stack frame to start allocating local variables at.
288 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
289 first local allocated. Otherwise, it is the offset to the BEGINNING
290 of the first local allocated. */
291 #define STARTING_FRAME_OFFSET 0
293 /* Register to use for pushing function arguments. */
294 #define STACK_POINTER_REGNUM REG_P6
296 /* Base register for access to local variables of the function. */
297 #define FRAME_POINTER_REGNUM REG_P7
299 /* A dummy register that will be eliminated to either FP or SP. */
300 #define ARG_POINTER_REGNUM REG_ARGP
302 /* `PIC_OFFSET_TABLE_REGNUM'
303 The register number of the register used to address a table of
304 static data addresses in memory. In some cases this register is
305 defined by a processor's "application binary interface" (ABI).
306 When this macro is defined, RTL is generated for this register
307 once, as with the stack pointer and frame pointer registers. If
308 this macro is not defined, it is up to the machine-dependent files
309 to allocate such a register (if necessary). */
310 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
312 #define FDPIC_FPTR_REGNO REG_P1
313 #define FDPIC_REGNO REG_P3
314 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
316 /* A static chain register for nested functions. We need to use a
317 call-clobbered register for this. */
318 #define STATIC_CHAIN_REGNUM REG_P2
320 /* Define this if functions should assume that stack space has been
321 allocated for arguments even when their values are passed in
324 The value of this macro is the size, in bytes, of the area reserved for
325 arguments passed in registers.
327 This space can either be allocated by the caller or be a part of the
328 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
330 #define FIXED_STACK_AREA 12
331 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
333 /* Define this if the above stack space is to be considered part of the
334 * space allocated by the caller. */
335 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
337 /* Define this if the maximum size of all the outgoing args is to be
338 accumulated and pushed during the prologue. The amount can be
339 found in the variable crtl->outgoing_args_size. */
340 #define ACCUMULATE_OUTGOING_ARGS 1
342 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
344 /* If defined, a C expression to compute the alignment for a local
345 variable. TYPE is the data type, and ALIGN is the alignment that
346 the object would ordinarily have. The value of this macro is used
347 instead of that alignment to align the object.
349 If this macro is not defined, then ALIGN is used.
351 One use of this macro is to increase alignment of medium-size
352 data to make it all fit in fewer cache lines. */
354 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
356 /* Make strings word-aligned so strcpy from constants will be faster. */
357 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
358 (TREE_CODE (EXP) == STRING_CST \
359 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
361 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
363 /* Definitions for register eliminations.
365 This is an array of structures. Each structure initializes one pair
366 of eliminable registers. The "from" register number is given first,
367 followed by "to". Eliminations of the same "from" register are listed
368 in order of preference.
370 There are two registers that can always be eliminated on the i386.
371 The frame pointer and the arg pointer can be replaced by either the
372 hard frame pointer or to the stack pointer, depending upon the
373 circumstances. The hard frame pointer is not used before reload and
374 so it is not eligible for elimination. */
376 #define ELIMINABLE_REGS \
377 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
378 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
379 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
381 /* Define the offset between two registers, one to be eliminated, and the other
382 its replacement, at the start of a routine. */
384 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
385 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
387 /* This processor has
388 8 data register for doing arithmetic
389 8 pointer register for doing addressing, including
392 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
393 1 condition code flag register CC
394 5 return address registers RETS/I/X/N/E
395 1 arithmetic status register (ASTAT). */
397 #define FIRST_PSEUDO_REGISTER 50
399 #define D_REGNO_P(X) ((X) <= REG_R7)
400 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
401 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
402 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
403 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
404 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
405 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
406 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
407 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
409 #define REGISTER_NAMES { \
410 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
411 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
412 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
413 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
416 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
418 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
421 #define SHORT_REGISTER_NAMES { \
422 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
423 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
424 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
425 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
427 #define HIGH_REGISTER_NAMES { \
428 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
429 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
430 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
431 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
433 #define DREGS_PAIR_NAMES { \
434 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
436 #define BYTE_REGISTER_NAMES { \
437 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
440 /* 1 for registers that have pervasive standard uses
441 and are not available for the register allocator. */
443 #define FIXED_REGISTERS \
444 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
445 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
446 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
447 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
448 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
449 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
454 /* 1 for registers not available across function calls.
455 These must include the FIXED_REGISTERS and also any
456 registers that can be used without being saved.
457 The latter must include the registers where values are returned
458 and the register where structure-value addresses are passed.
459 Aside from that, you can include as many other registers as you like. */
461 #define CALL_USED_REGISTERS \
462 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
463 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
464 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
465 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
466 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
467 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
472 /* Order in which to allocate registers. Each register must be
473 listed once, even those in FIXED_REGISTERS. List frame pointer
474 late and fixed registers last. Note that, in general, we prefer
475 registers listed in CALL_USED_REGISTERS, keeping the others
476 available for storage of persistent values. */
478 #define REG_ALLOC_ORDER \
479 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
480 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
482 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
483 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
484 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
485 REG_ASTAT, REG_SEQSTAT, REG_USP, \
487 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
490 /* Define the classes of registers for register constraints in the
491 machine description. Also define ranges of constants.
493 One of the classes must always be named ALL_REGS and include all hard regs.
494 If there is more than one class, another class must be named NO_REGS
495 and contain no registers.
497 The name GENERAL_REGS must be the name of a class (or an alias for
498 another name such as ALL_REGS). This is the class of registers
499 that is allowed by "g" or "r" in a register constraint.
500 Also, registers outside this class are allocated only when
501 instructions express preferences for them.
503 The classes must be numbered in nondecreasing order; that is,
504 a larger-numbered class must never be contained completely
505 in a smaller-numbered class.
507 For any two classes, it is very desirable that there be another
508 class that represents their union. */
518 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
548 ALL_REGS, LIM_REG_CLASSES
551 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
553 #define GENERAL_REGS DPREGS
555 /* Give names of register classes as strings for dump file. */
557 #define REG_CLASS_NAMES \
595 /* An initializer containing the contents of the register classes, as integers
596 which are bit masks. The Nth integer specifies the contents of class N.
597 The way the integer MASK is interpreted is that register R is in the class
598 if `MASK & (1 << R)' is 1.
600 When the machine has more than 32 registers, an integer does not suffice.
601 Then the integers are replaced by sub-initializers, braced groupings
602 containing several integers. Each sub-initializer must be suitable as an
603 initializer for the type `HARD_REG_SET' which is defined in
606 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
607 MOST_REGS as the union of DPREGS and DAGREGS. */
609 #define REG_CLASS_CONTENTS \
611 { { 0x00000000, 0 }, /* NO_REGS */ \
612 { 0x000f0000, 0 }, /* IREGS */ \
613 { 0x00f00000, 0 }, /* BREGS */ \
614 { 0x0f000000, 0 }, /* LREGS */ \
615 { 0xf0000000, 0 }, /* MREGS */ \
616 { 0x0fff0000, 0 }, /* CIRCREGS */ \
617 { 0xffff0000, 0 }, /* DAGREGS */ \
618 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
619 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
620 { 0x00000000, 0x3 }, /* AREGS */ \
621 { 0x00000000, 0x4 }, /* CCREGS */ \
622 { 0x00000055, 0 }, /* EVEN_DREGS */ \
623 { 0x000000aa, 0 }, /* ODD_DREGS */ \
624 { 0x00000001, 0 }, /* D0REGS */ \
625 { 0x00000002, 0 }, /* D1REGS */ \
626 { 0x00000004, 0 }, /* D2REGS */ \
627 { 0x00000008, 0 }, /* D3REGS */ \
628 { 0x00000010, 0 }, /* D4REGS */ \
629 { 0x00000020, 0 }, /* D5REGS */ \
630 { 0x00000040, 0 }, /* D6REGS */ \
631 { 0x00000080, 0 }, /* D7REGS */ \
632 { 0x000000ff, 0 }, /* DREGS */ \
633 { 0x00000100, 0x000 }, /* P0REGS */ \
634 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
635 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
636 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
637 { 0x0000ff00, 0x800 }, /* PREGS */ \
638 { 0x000fff00, 0x800 }, /* IPREGS */ \
639 { 0x0000ffff, 0x800 }, /* DPREGS */ \
640 { 0xffffffff, 0x800 }, /* MOST_REGS */\
641 { 0x00000000, 0x3000 }, /* LT_REGS */\
642 { 0x00000000, 0xc000 }, /* LC_REGS */\
643 { 0x00000000, 0x30000 }, /* LB_REGS */\
644 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
645 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
646 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
648 #define IREG_POSSIBLE_P(OUTER) \
649 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
650 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
651 || (OUTER) == MEM || (OUTER) == ADDRESS)
653 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
654 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
656 #define INDEX_REG_CLASS PREGS
658 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
659 (P_REGNO_P (X) || (X) == REG_ARGP \
660 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
663 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
664 ((X) >= FIRST_PSEUDO_REGISTER \
665 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
668 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
669 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
671 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
672 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
675 #define REGNO_OK_FOR_INDEX_P(X) 0
677 /* The same information, inverted:
678 Return the class number of the smallest class containing
679 reg number REGNO. This could be a conditional expression
680 or could index an array. */
682 #define REGNO_REG_CLASS(REGNO) \
683 ((REGNO) == REG_R0 ? D0REGS \
684 : (REGNO) == REG_R1 ? D1REGS \
685 : (REGNO) == REG_R2 ? D2REGS \
686 : (REGNO) == REG_R3 ? D3REGS \
687 : (REGNO) == REG_R4 ? D4REGS \
688 : (REGNO) == REG_R5 ? D5REGS \
689 : (REGNO) == REG_R6 ? D6REGS \
690 : (REGNO) == REG_R7 ? D7REGS \
691 : (REGNO) == REG_P0 ? P0REGS \
692 : (REGNO) < REG_I0 ? PREGS \
693 : (REGNO) == REG_ARGP ? PREGS \
694 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
695 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
696 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
697 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
698 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
699 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
700 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
701 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
702 : (REGNO) == REG_CC ? CCREGS \
703 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
706 /* The following macro defines cover classes for Integrated Register
707 Allocator. Cover classes is a set of non-intersected register
708 classes covering all hard registers used for register allocation
709 purpose. Any move between two registers of a cover class should be
710 cheaper than load or store of the registers. The macro value is
711 array of register classes with LIM_REG_CLASSES used as the end
714 #define IRA_COVER_CLASSES \
716 MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \
719 /* When this hook returns true for MODE, the compiler allows
720 registers explicitly used in the rtl to be used as spill registers
721 but prevents the compiler from extending the lifetime of these
723 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
725 /* Do not allow to store a value in REG_CC for any mode */
726 /* Do not allow to store value in pregs if mode is not SI*/
727 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
729 /* Return the maximum number of consecutive registers
730 needed to represent mode MODE in a register of class CLASS. */
731 #define CLASS_MAX_NREGS(CLASS, MODE) \
732 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
733 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
735 #define HARD_REGNO_NREGS(REGNO, MODE) \
736 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
737 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
738 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
740 /* A C expression that is nonzero if hard register TO can be
741 considered for use as a rename register for FROM register */
742 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
744 /* A C expression that is nonzero if it is desirable to choose
745 register allocation so as to avoid move instructions between a
746 value of mode MODE1 and a value of mode MODE2.
748 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
749 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
750 MODE2)' must be zero. */
751 #define MODES_TIEABLE_P(MODE1, MODE2) \
752 ((MODE1) == (MODE2) \
753 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
754 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
755 && (GET_MODE_CLASS (MODE2) == MODE_INT \
756 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
757 && (MODE1) != BImode && (MODE2) != BImode \
758 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
759 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
761 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
762 A C expression that places additional restrictions on the register
763 class to use when it is necessary to copy value X into a register
764 in class CLASS. The value is a register class; perhaps CLASS, or
765 perhaps another, smaller class. */
766 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
767 (GET_CODE (X) == POST_INC \
768 || GET_CODE (X) == POST_DEC \
769 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
771 /* Function Calling Conventions. */
773 /* The type of the current function; normal functions are of type
776 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
778 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
780 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
782 /* Flags for the call/call_value rtl operations set up by function_arg */
783 #define CALL_NORMAL 0x00000000 /* no special processing */
784 #define CALL_LONG 0x00000001 /* always call indirect */
785 #define CALL_SHORT 0x00000002 /* always call by symbol */
788 int words; /* # words passed so far */
789 int nregs; /* # registers available for passing */
790 int *arg_regs; /* array of register -1 terminated */
791 int call_cookie; /* Do special things for this call */
794 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
797 /* Initialize a variable CUM of type CUMULATIVE_ARGS
798 for a call to a function whose data type is FNTYPE.
799 For a library call, FNTYPE is 0. */
800 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
801 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
803 /* Define how to find the value returned by a function.
804 VALTYPE is the data type of the value (as a tree).
805 If the precise function being called is known, FUNC is its FUNCTION_DECL;
806 otherwise, FUNC is 0.
809 #define VALUE_REGNO(MODE) (REG_R0)
811 #define FUNCTION_VALUE(VALTYPE, FUNC) \
812 gen_rtx_REG (TYPE_MODE (VALTYPE), \
813 VALUE_REGNO(TYPE_MODE(VALTYPE)))
815 /* Define how to find the value returned by a library function
816 assuming the value has mode MODE. */
818 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
820 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
822 #define DEFAULT_PCC_STRUCT_RETURN 0
824 /* Before the prologue, the return address is in the RETS register. */
825 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
827 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
829 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
831 /* Call instructions don't modify the stack pointer on the Blackfin. */
832 #define INCOMING_FRAME_SP_OFFSET 0
834 /* Describe how we implement __builtin_eh_return. */
835 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
836 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
837 #define EH_RETURN_HANDLER_RTX \
838 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
840 /* Addressing Modes */
842 /* Nonzero if the constant value X is a legitimate general operand.
843 symbol_ref are not legitimate and will be put into constant pool.
844 See force_const_mem().
845 If -mno-pool, all constants are legitimate.
847 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
849 /* A number, the maximum number of registers that can appear in a
850 valid memory address. Note that it is up to you to specify a
851 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
852 would ever accept. */
853 #define MAX_REGS_PER_ADDRESS 1
855 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
856 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
858 #define HAVE_POST_INCREMENT 1
859 #define HAVE_POST_DECREMENT 1
860 #define HAVE_PRE_DECREMENT 1
862 /* `LEGITIMATE_PIC_OPERAND_P (X)'
863 A C expression that is nonzero if X is a legitimate immediate
864 operand on the target machine when generating position independent
865 code. You can assume that X satisfies `CONSTANT_P', so you need
866 not check this. You can also assume FLAG_PIC is true, so you need
867 not check it either. You need not define this macro if all
868 constants (including `SYMBOL_REF') can be immediate operands when
869 generating position independent code. */
870 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
872 #define SYMBOLIC_CONST(X) \
873 (GET_CODE (X) == SYMBOL_REF \
874 || GET_CODE (X) == LABEL_REF \
875 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
877 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
879 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
880 is done just by pretending it is already truncated. */
881 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
883 /* Max number of bytes we can move from memory to memory
884 in one reasonably fast instruction. */
885 #define MOVE_MAX UNITS_PER_WORD
887 /* If a memory-to-memory move would take MOVE_RATIO or more simple
888 move-instruction pairs, we will do a movmem or libcall instead. */
890 #define MOVE_RATIO(speed) 5
892 /* STORAGE LAYOUT: target machine storage layout
893 Define this macro as a C expression which is nonzero if accessing
894 less than a word of memory (i.e. a `char' or a `short') is no
895 faster than accessing a word of memory, i.e., if such access
896 require more than one instruction or if there is no difference in
897 cost between byte and (aligned) word loads.
899 When this macro is not defined, the compiler will access a field by
900 finding the smallest containing object; when it is defined, a
901 fullword load will be used if alignment permits. Unless bytes
902 accesses are faster than word accesses, using word accesses is
903 preferable since it may eliminate subsequent memory access if
904 subsequent accesses occur to other fields in the same word of the
905 structure, but to different bytes. */
906 #define SLOW_BYTE_ACCESS 0
907 #define SLOW_SHORT_ACCESS 0
909 /* Define this if most significant bit is lowest numbered
910 in instructions that operate on numbered bit-fields. */
911 #define BITS_BIG_ENDIAN 0
913 /* Define this if most significant byte of a word is the lowest numbered.
914 We can't access bytes but if we could we would in the Big Endian order. */
915 #define BYTES_BIG_ENDIAN 0
917 /* Define this if most significant word of a multiword number is numbered. */
918 #define WORDS_BIG_ENDIAN 0
920 /* number of bits in an addressable storage unit */
921 #define BITS_PER_UNIT 8
923 /* Width in bits of a "word", which is the contents of a machine register.
924 Note that this is not necessarily the width of data type `int';
925 if using 16-bit ints on a 68000, this would still be 32.
926 But on a machine with 16-bit registers, this would be 16. */
927 #define BITS_PER_WORD 32
929 /* Width of a word, in units (bytes). */
930 #define UNITS_PER_WORD 4
932 /* Width in bits of a pointer.
933 See also the macro `Pmode1' defined below. */
934 #define POINTER_SIZE 32
936 /* Allocation boundary (in *bits*) for storing pointers in memory. */
937 #define POINTER_BOUNDARY 32
939 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
940 #define PARM_BOUNDARY 32
942 /* Boundary (in *bits*) on which stack pointer should be aligned. */
943 #define STACK_BOUNDARY 32
945 /* Allocation boundary (in *bits*) for the code of a function. */
946 #define FUNCTION_BOUNDARY 32
948 /* Alignment of field after `int : 0' in a structure. */
949 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
951 /* No data type wants to be aligned rounder than this. */
952 #define BIGGEST_ALIGNMENT 32
954 /* Define this if move instructions will actually fail to work
955 when given unaligned data. */
956 #define STRICT_ALIGNMENT 1
958 /* (shell-command "rm c-decl.o stor-layout.o")
959 * never define PCC_BITFIELD_TYPE_MATTERS
960 * really cause some alignment problem
963 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
966 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
970 /* what is the 'type' of size_t */
971 #define SIZE_TYPE "long unsigned int"
973 /* Define this as 1 if `char' should by default be signed; else as 0. */
974 #define DEFAULT_SIGNED_CHAR 1
975 #define FLOAT_TYPE_SIZE BITS_PER_WORD
976 #define SHORT_TYPE_SIZE 16
977 #define CHAR_TYPE_SIZE 8
978 #define INT_TYPE_SIZE 32
979 #define LONG_TYPE_SIZE 32
980 #define LONG_LONG_TYPE_SIZE 64
982 /* Note: Fix this to depend on target switch. -- lev */
984 /* Note: Try to implement double and force long double. -- tonyko
985 * #define __DOUBLES_ARE_FLOATS__
986 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
987 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
988 * #define DOUBLES_ARE_FLOATS 1
991 #define DOUBLE_TYPE_SIZE 64
992 #define LONG_DOUBLE_TYPE_SIZE 64
994 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
995 A macro to update M and UNSIGNEDP when an object whose type is
996 TYPE and which has the specified mode and signedness is to be
997 stored in a register. This macro is only called when TYPE is a
1000 On most RISC machines, which only have operations that operate on
1001 a full register, define this macro to set M to `word_mode' if M is
1002 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1003 only integer modes should be widened because wider-precision
1004 floating-point operations are usually more expensive than their
1005 narrower counterparts.
1007 For most machines, the macro definition does not change UNSIGNEDP.
1008 However, some machines, have instructions that preferentially
1009 handle either signed or unsigned quantities of certain modes. For
1010 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1011 instructions sign-extend the result to 64 bits. On such machines,
1012 set UNSIGNEDP according to which kind of extension is more
1015 Do not define this macro if it would never modify M.*/
1017 #define BFIN_PROMOTE_MODE_P(MODE) \
1018 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1019 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1021 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1022 if (BFIN_PROMOTE_MODE_P(MODE)) \
1024 if (MODE == QImode) \
1026 else if (MODE == HImode) \
1031 /* Describing Relative Costs of Operations */
1033 /* Do not put function addr into constant pool */
1034 #define NO_FUNCTION_CSE 1
1036 /* A C expression for the cost of moving data from a register in class FROM to
1037 one in class TO. The classes are expressed using the enumeration values
1038 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1039 interpreted relative to that.
1041 It is not required that the cost always equal 2 when FROM is the same as TO;
1042 on some machines it is expensive to move between registers if they are not
1043 general registers. */
1045 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1046 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1048 /* A C expression for the cost of moving data of mode M between a
1049 register and memory. A value of 2 is the default; this cost is
1050 relative to those in `REGISTER_MOVE_COST'.
1052 If moving between registers and memory is more expensive than
1053 between two registers, you should define this macro to express the
1056 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1057 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1059 /* Specify the machine mode that this machine uses
1060 for the index in the tablejump instruction. */
1061 #define CASE_VECTOR_MODE SImode
1063 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1065 /* Define if operations between registers always perform the operation
1066 on the full register even if a narrower mode is specified.
1067 #define WORD_REGISTER_OPERATIONS
1070 /* Evaluates to true if A and B are mac flags that can be used
1071 together in a single multiply insn. That is the case if they are
1072 both the same flag not involving M, or if one is a combination of
1073 the other with M. */
1074 #define MACFLAGS_MATCH_P(A, B) \
1076 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1077 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1078 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1079 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1081 /* Switch into a generic section. */
1082 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1084 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1085 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1087 typedef enum sections {
1093 typedef enum directives {
1102 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1104 || ((C) == '|' && (STR)[1] == '|'))
1106 #define TEXT_SECTION_ASM_OP ".text;"
1107 #define DATA_SECTION_ASM_OP ".data;"
1109 #define ASM_APP_ON ""
1110 #define ASM_APP_OFF ""
1112 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1113 do { fputs (".global ", FILE); \
1114 assemble_name (FILE, NAME); \
1116 fputc ('\n',FILE); \
1119 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1121 fputs (".type ", FILE); \
1122 assemble_name (FILE, NAME); \
1123 fputs (", STT_FUNC", FILE); \
1125 fputc ('\n',FILE); \
1126 ASM_OUTPUT_LABEL(FILE, NAME); \
1129 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1130 do { assemble_name (FILE, NAME); \
1131 fputs (":\n",FILE); \
1134 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1135 do { fprintf (FILE, "_%s", NAME); \
1138 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1139 do { char __buf[256]; \
1140 fprintf (FILE, "\t.dd\t"); \
1141 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1142 assemble_name (FILE, __buf); \
1143 fputc (';', FILE); \
1144 fputc ('\n', FILE); \
1147 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1148 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1150 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1153 fprintf (FILE, "\t.dd\t"); \
1154 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1155 assemble_name (FILE, __buf); \
1156 fputs (" - ", FILE); \
1157 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1158 assemble_name (FILE, __buf); \
1159 fputc (';', FILE); \
1160 fputc ('\n', FILE); \
1163 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1166 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1169 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1171 asm_output_skip (FILE, SIZE); \
1174 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1176 switch_to_section (data_section); \
1177 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1178 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1179 ASM_OUTPUT_LABEL (FILE, NAME); \
1180 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1181 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1184 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1186 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1187 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1189 #define ASM_COMMENT_START "//"
1191 #define FUNCTION_PROFILER(FILE, LABELNO) \
1193 fprintf (FILE, "\tCALL __mcount;\n"); \
1196 #undef NO_PROFILE_COUNTERS
1197 #define NO_PROFILE_COUNTERS 1
1199 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1200 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1202 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1204 /* This works for GAS and some other assemblers. */
1205 #define SET_ASM_OP ".set "
1207 /* DBX register number for a given compiler register number */
1208 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1210 #define SIZE_ASM_OP "\t.size\t"
1212 extern int splitting_for_sched, splitting_loops;
1214 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1216 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1217 #define TARGET_SUPPORTS_SYNC_CALLS 0
1220 #endif /* _BFIN_CONFIG */